1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
306 static const arm_feature_set fpu_vfp_fp16
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
308 static const arm_feature_set fpu_neon_ext_fma
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_fma
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
313 static const arm_feature_set fpu_vfp_ext_armv8
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
315 static const arm_feature_set fpu_vfp_ext_armv8xd
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
317 static const arm_feature_set fpu_neon_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
319 static const arm_feature_set fpu_crypto_ext_armv8
=
320 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
321 static const arm_feature_set crc_ext_armv8
=
322 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
323 static const arm_feature_set fpu_neon_ext_v8_1
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
325 static const arm_feature_set fpu_neon_ext_dotprod
=
326 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
328 static int mfloat_abi_opt
= -1;
329 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
331 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
332 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
334 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
335 /* Feature bits selected by the last -mcpu/-march or by the combination of the
336 last .cpu/.arch directive .arch_extension directives since that
338 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
339 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
340 static arm_feature_set selected_fpu
= FPU_NONE
;
341 /* Feature bits selected by the last .object_arch directive. */
342 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
343 /* Must be long enough to hold any of the names in arm_cpus. */
344 static char selected_cpu_name
[20];
346 extern FLONUM_TYPE generic_floating_point_number
;
348 /* Return if no cpu was selected on command-line. */
350 no_cpu_selected (void)
352 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
357 static int meabi_flags
= EABI_DEFAULT
;
359 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
362 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
367 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
372 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
373 symbolS
* GOT_symbol
;
376 /* 0: assemble for ARM,
377 1: assemble for Thumb,
378 2: assemble for Thumb even though target CPU does not support thumb
380 static int thumb_mode
= 0;
381 /* A value distinct from the possible values for thumb_mode that we
382 can use to record whether thumb_mode has been copied into the
383 tc_frag_data field of a frag. */
384 #define MODE_RECORDED (1 << 4)
386 /* Specifies the intrinsic IT insn behavior mode. */
387 enum implicit_it_mode
389 IMPLICIT_IT_MODE_NEVER
= 0x00,
390 IMPLICIT_IT_MODE_ARM
= 0x01,
391 IMPLICIT_IT_MODE_THUMB
= 0x02,
392 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
394 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
396 /* If unified_syntax is true, we are processing the new unified
397 ARM/Thumb syntax. Important differences from the old ARM mode:
399 - Immediate operands do not require a # prefix.
400 - Conditional affixes always appear at the end of the
401 instruction. (For backward compatibility, those instructions
402 that formerly had them in the middle, continue to accept them
404 - The IT instruction may appear, and if it does is validated
405 against subsequent conditional affixes. It does not generate
408 Important differences from the old Thumb mode:
410 - Immediate operands do not require a # prefix.
411 - Most of the V6T2 instructions are only available in unified mode.
412 - The .N and .W suffixes are recognized and honored (it is an error
413 if they cannot be honored).
414 - All instructions set the flags if and only if they have an 's' affix.
415 - Conditional affixes may be used. They are validated against
416 preceding IT instructions. Unlike ARM mode, you cannot use a
417 conditional affix except in the scope of an IT instruction. */
419 static bfd_boolean unified_syntax
= FALSE
;
421 /* An immediate operand can start with #, and ld*, st*, pld operands
422 can contain [ and ]. We need to tell APP not to elide whitespace
423 before a [, which can appear as the first operand for pld.
424 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
425 const char arm_symbol_chars
[] = "#[]{}";
440 enum neon_el_type type
;
444 #define NEON_MAX_TYPE_ELS 4
448 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
452 enum it_instruction_type
457 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
458 if inside, should be the last one. */
459 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
460 i.e. BKPT and NOP. */
461 IT_INSN
/* The IT insn has been parsed. */
464 /* The maximum number of operands we need. */
465 #define ARM_IT_MAX_OPERANDS 6
466 #define ARM_IT_MAX_RELOCS 3
471 unsigned long instruction
;
475 /* "uncond_value" is set to the value in place of the conditional field in
476 unconditional versions of the instruction, or -1 if nothing is
479 struct neon_type vectype
;
480 /* This does not indicate an actual NEON instruction, only that
481 the mnemonic accepts neon-style type suffixes. */
483 /* Set to the opcode if the instruction needs relaxation.
484 Zero if the instruction is not relaxed. */
488 bfd_reloc_code_real_type type
;
491 } relocs
[ARM_IT_MAX_RELOCS
];
493 enum it_instruction_type it_insn_type
;
499 struct neon_type_el vectype
;
500 unsigned present
: 1; /* Operand present. */
501 unsigned isreg
: 1; /* Operand was a register. */
502 unsigned immisreg
: 1; /* .imm field is a second register. */
503 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
504 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
505 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
506 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
507 instructions. This allows us to disambiguate ARM <-> vector insns. */
508 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
509 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
510 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
511 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
512 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
513 unsigned writeback
: 1; /* Operand has trailing ! */
514 unsigned preind
: 1; /* Preindexed address. */
515 unsigned postind
: 1; /* Postindexed address. */
516 unsigned negative
: 1; /* Index register was negated. */
517 unsigned shifted
: 1; /* Shift applied to operation. */
518 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
519 } operands
[ARM_IT_MAX_OPERANDS
];
522 static struct arm_it inst
;
524 #define NUM_FLOAT_VALS 8
526 const char * fp_const
[] =
528 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
531 /* Number of littlenums required to hold an extended precision number. */
532 #define MAX_LITTLENUMS 6
534 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
544 #define CP_T_X 0x00008000
545 #define CP_T_Y 0x00400000
547 #define CONDS_BIT 0x00100000
548 #define LOAD_BIT 0x00100000
550 #define DOUBLE_LOAD_FLAG 0x00000001
554 const char * template_name
;
558 #define COND_ALWAYS 0xE
562 const char * template_name
;
566 struct asm_barrier_opt
568 const char * template_name
;
570 const arm_feature_set arch
;
573 /* The bit that distinguishes CPSR and SPSR. */
574 #define SPSR_BIT (1 << 22)
576 /* The individual PSR flag bits. */
577 #define PSR_c (1 << 16)
578 #define PSR_x (1 << 17)
579 #define PSR_s (1 << 18)
580 #define PSR_f (1 << 19)
585 bfd_reloc_code_real_type reloc
;
590 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
591 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
596 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
599 /* Bits for DEFINED field in neon_typed_alias. */
600 #define NTA_HASTYPE 1
601 #define NTA_HASINDEX 2
603 struct neon_typed_alias
605 unsigned char defined
;
607 struct neon_type_el eltype
;
610 /* ARM register categories. This includes coprocessor numbers and various
611 architecture extensions' registers. Each entry should have an error message
612 in reg_expected_msgs below. */
640 /* Structure for a hash table entry for a register.
641 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
642 information which states whether a vector type or index is specified (for a
643 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
649 unsigned char builtin
;
650 struct neon_typed_alias
* neon
;
653 /* Diagnostics used when we don't get a register of the expected type. */
654 const char * const reg_expected_msgs
[] =
656 [REG_TYPE_RN
] = N_("ARM register expected"),
657 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
658 [REG_TYPE_CN
] = N_("co-processor register expected"),
659 [REG_TYPE_FN
] = N_("FPA register expected"),
660 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
661 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
662 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
663 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
664 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
665 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
666 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
668 [REG_TYPE_VFC
] = N_("VFP system register expected"),
669 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
670 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
671 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
672 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
673 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
674 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
675 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
676 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
677 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
678 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
679 [REG_TYPE_RNB
] = N_("")
682 /* Some well known registers that we refer to directly elsewhere. */
688 /* ARM instructions take 4bytes in the object file, Thumb instructions
694 /* Basic string to match. */
695 const char * template_name
;
697 /* Parameters to instruction. */
698 unsigned int operands
[8];
700 /* Conditional tag - see opcode_lookup. */
701 unsigned int tag
: 4;
703 /* Basic instruction code. */
704 unsigned int avalue
: 28;
706 /* Thumb-format instruction code. */
709 /* Which architecture variant provides this instruction. */
710 const arm_feature_set
* avariant
;
711 const arm_feature_set
* tvariant
;
713 /* Function to call to encode instruction in ARM format. */
714 void (* aencode
) (void);
716 /* Function to call to encode instruction in Thumb format. */
717 void (* tencode
) (void);
720 /* Defines for various bits that we will want to toggle. */
721 #define INST_IMMEDIATE 0x02000000
722 #define OFFSET_REG 0x02000000
723 #define HWOFFSET_IMM 0x00400000
724 #define SHIFT_BY_REG 0x00000010
725 #define PRE_INDEX 0x01000000
726 #define INDEX_UP 0x00800000
727 #define WRITE_BACK 0x00200000
728 #define LDM_TYPE_2_OR_3 0x00400000
729 #define CPSI_MMOD 0x00020000
731 #define LITERAL_MASK 0xf000f000
732 #define OPCODE_MASK 0xfe1fffff
733 #define V4_STR_BIT 0x00000020
734 #define VLDR_VMOV_SAME 0x0040f000
736 #define T2_SUBS_PC_LR 0xf3de8f00
738 #define DATA_OP_SHIFT 21
739 #define SBIT_SHIFT 20
741 #define T2_OPCODE_MASK 0xfe1fffff
742 #define T2_DATA_OP_SHIFT 21
743 #define T2_SBIT_SHIFT 20
745 #define A_COND_MASK 0xf0000000
746 #define A_PUSH_POP_OP_MASK 0x0fff0000
748 /* Opcodes for pushing/poping registers to/from the stack. */
749 #define A1_OPCODE_PUSH 0x092d0000
750 #define A2_OPCODE_PUSH 0x052d0004
751 #define A2_OPCODE_POP 0x049d0004
753 /* Codes to distinguish the arithmetic instructions. */
764 #define OPCODE_CMP 10
765 #define OPCODE_CMN 11
766 #define OPCODE_ORR 12
767 #define OPCODE_MOV 13
768 #define OPCODE_BIC 14
769 #define OPCODE_MVN 15
771 #define T2_OPCODE_AND 0
772 #define T2_OPCODE_BIC 1
773 #define T2_OPCODE_ORR 2
774 #define T2_OPCODE_ORN 3
775 #define T2_OPCODE_EOR 4
776 #define T2_OPCODE_ADD 8
777 #define T2_OPCODE_ADC 10
778 #define T2_OPCODE_SBC 11
779 #define T2_OPCODE_SUB 13
780 #define T2_OPCODE_RSB 14
782 #define T_OPCODE_MUL 0x4340
783 #define T_OPCODE_TST 0x4200
784 #define T_OPCODE_CMN 0x42c0
785 #define T_OPCODE_NEG 0x4240
786 #define T_OPCODE_MVN 0x43c0
788 #define T_OPCODE_ADD_R3 0x1800
789 #define T_OPCODE_SUB_R3 0x1a00
790 #define T_OPCODE_ADD_HI 0x4400
791 #define T_OPCODE_ADD_ST 0xb000
792 #define T_OPCODE_SUB_ST 0xb080
793 #define T_OPCODE_ADD_SP 0xa800
794 #define T_OPCODE_ADD_PC 0xa000
795 #define T_OPCODE_ADD_I8 0x3000
796 #define T_OPCODE_SUB_I8 0x3800
797 #define T_OPCODE_ADD_I3 0x1c00
798 #define T_OPCODE_SUB_I3 0x1e00
800 #define T_OPCODE_ASR_R 0x4100
801 #define T_OPCODE_LSL_R 0x4080
802 #define T_OPCODE_LSR_R 0x40c0
803 #define T_OPCODE_ROR_R 0x41c0
804 #define T_OPCODE_ASR_I 0x1000
805 #define T_OPCODE_LSL_I 0x0000
806 #define T_OPCODE_LSR_I 0x0800
808 #define T_OPCODE_MOV_I8 0x2000
809 #define T_OPCODE_CMP_I8 0x2800
810 #define T_OPCODE_CMP_LR 0x4280
811 #define T_OPCODE_MOV_HR 0x4600
812 #define T_OPCODE_CMP_HR 0x4500
814 #define T_OPCODE_LDR_PC 0x4800
815 #define T_OPCODE_LDR_SP 0x9800
816 #define T_OPCODE_STR_SP 0x9000
817 #define T_OPCODE_LDR_IW 0x6800
818 #define T_OPCODE_STR_IW 0x6000
819 #define T_OPCODE_LDR_IH 0x8800
820 #define T_OPCODE_STR_IH 0x8000
821 #define T_OPCODE_LDR_IB 0x7800
822 #define T_OPCODE_STR_IB 0x7000
823 #define T_OPCODE_LDR_RW 0x5800
824 #define T_OPCODE_STR_RW 0x5000
825 #define T_OPCODE_LDR_RH 0x5a00
826 #define T_OPCODE_STR_RH 0x5200
827 #define T_OPCODE_LDR_RB 0x5c00
828 #define T_OPCODE_STR_RB 0x5400
830 #define T_OPCODE_PUSH 0xb400
831 #define T_OPCODE_POP 0xbc00
833 #define T_OPCODE_BRANCH 0xe000
835 #define THUMB_SIZE 2 /* Size of thumb instruction. */
836 #define THUMB_PP_PC_LR 0x0100
837 #define THUMB_LOAD_BIT 0x0800
838 #define THUMB2_LOAD_BIT 0x00100000
840 #define BAD_ARGS _("bad arguments to instruction")
841 #define BAD_SP _("r13 not allowed here")
842 #define BAD_PC _("r15 not allowed here")
843 #define BAD_COND _("instruction cannot be conditional")
844 #define BAD_OVERLAP _("registers may not be the same")
845 #define BAD_HIREG _("lo register required")
846 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
847 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
848 #define BAD_BRANCH _("branch must be last instruction in IT block")
849 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
850 #define BAD_NOT_IT _("instruction not allowed in IT block")
851 #define BAD_FPU _("selected FPU does not support instruction")
852 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
853 #define BAD_IT_COND _("incorrect condition in IT block")
854 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
855 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
856 #define BAD_PC_ADDRESSING \
857 _("cannot use register index with PC-relative addressing")
858 #define BAD_PC_WRITEBACK \
859 _("cannot use writeback with PC-relative addressing")
860 #define BAD_RANGE _("branch out of range")
861 #define BAD_FP16 _("selected processor does not support fp16 instruction")
862 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
863 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
865 static struct hash_control
* arm_ops_hsh
;
866 static struct hash_control
* arm_cond_hsh
;
867 static struct hash_control
* arm_shift_hsh
;
868 static struct hash_control
* arm_psr_hsh
;
869 static struct hash_control
* arm_v7m_psr_hsh
;
870 static struct hash_control
* arm_reg_hsh
;
871 static struct hash_control
* arm_reloc_hsh
;
872 static struct hash_control
* arm_barrier_opt_hsh
;
874 /* Stuff needed to resolve the label ambiguity
883 symbolS
* last_label_seen
;
884 static int label_is_thumb_function_name
= FALSE
;
886 /* Literal pool structure. Held on a per-section
887 and per-sub-section basis. */
889 #define MAX_LITERAL_POOL_SIZE 1024
890 typedef struct literal_pool
892 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
893 unsigned int next_free_entry
;
899 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
901 struct literal_pool
* next
;
902 unsigned int alignment
;
905 /* Pointer to a linked list of literal pools. */
906 literal_pool
* list_of_pools
= NULL
;
908 typedef enum asmfunc_states
911 WAITING_ASMFUNC_NAME
,
915 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
918 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
920 static struct current_it now_it
;
924 now_it_compatible (int cond
)
926 return (cond
& ~1) == (now_it
.cc
& ~1);
930 conditional_insn (void)
932 return inst
.cond
!= COND_ALWAYS
;
935 static int in_it_block (void);
937 static int handle_it_state (void);
939 static void force_automatic_it_block_close (void);
941 static void it_fsm_post_encode (void);
943 #define set_it_insn_type(type) \
946 inst.it_insn_type = type; \
947 if (handle_it_state () == FAIL) \
952 #define set_it_insn_type_nonvoid(type, failret) \
955 inst.it_insn_type = type; \
956 if (handle_it_state () == FAIL) \
961 #define set_it_insn_type_last() \
964 if (inst.cond == COND_ALWAYS) \
965 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
967 set_it_insn_type (INSIDE_IT_LAST_INSN); \
973 /* This array holds the chars that always start a comment. If the
974 pre-processor is disabled, these aren't very useful. */
975 char arm_comment_chars
[] = "@";
977 /* This array holds the chars that only start a comment at the beginning of
978 a line. If the line seems to have the form '# 123 filename'
979 .line and .file directives will appear in the pre-processed output. */
980 /* Note that input_file.c hand checks for '#' at the beginning of the
981 first line of the input file. This is because the compiler outputs
982 #NO_APP at the beginning of its output. */
983 /* Also note that comments like this one will always work. */
984 const char line_comment_chars
[] = "#";
986 char arm_line_separator_chars
[] = ";";
988 /* Chars that can be used to separate mant
989 from exp in floating point numbers. */
990 const char EXP_CHARS
[] = "eE";
992 /* Chars that mean this number is a floating point constant. */
996 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
998 /* Prefix characters that indicate the start of an immediate
1000 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1002 /* Separator character handling. */
1004 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1007 skip_past_char (char ** str
, char c
)
1009 /* PR gas/14987: Allow for whitespace before the expected character. */
1010 skip_whitespace (*str
);
1021 #define skip_past_comma(str) skip_past_char (str, ',')
1023 /* Arithmetic expressions (possibly involving symbols). */
1025 /* Return TRUE if anything in the expression is a bignum. */
1028 walk_no_bignums (symbolS
* sp
)
1030 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1033 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1035 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1036 || (symbol_get_value_expression (sp
)->X_op_symbol
1037 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1043 static bfd_boolean in_my_get_expression
= FALSE
;
1045 /* Third argument to my_get_expression. */
1046 #define GE_NO_PREFIX 0
1047 #define GE_IMM_PREFIX 1
1048 #define GE_OPT_PREFIX 2
1049 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1050 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1051 #define GE_OPT_PREFIX_BIG 3
1054 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1058 /* In unified syntax, all prefixes are optional. */
1060 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1063 switch (prefix_mode
)
1065 case GE_NO_PREFIX
: break;
1067 if (!is_immediate_prefix (**str
))
1069 inst
.error
= _("immediate expression requires a # prefix");
1075 case GE_OPT_PREFIX_BIG
:
1076 if (is_immediate_prefix (**str
))
1083 memset (ep
, 0, sizeof (expressionS
));
1085 save_in
= input_line_pointer
;
1086 input_line_pointer
= *str
;
1087 in_my_get_expression
= TRUE
;
1089 in_my_get_expression
= FALSE
;
1091 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1093 /* We found a bad or missing expression in md_operand(). */
1094 *str
= input_line_pointer
;
1095 input_line_pointer
= save_in
;
1096 if (inst
.error
== NULL
)
1097 inst
.error
= (ep
->X_op
== O_absent
1098 ? _("missing expression") :_("bad expression"));
1102 /* Get rid of any bignums now, so that we don't generate an error for which
1103 we can't establish a line number later on. Big numbers are never valid
1104 in instructions, which is where this routine is always called. */
1105 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1106 && (ep
->X_op
== O_big
1107 || (ep
->X_add_symbol
1108 && (walk_no_bignums (ep
->X_add_symbol
)
1110 && walk_no_bignums (ep
->X_op_symbol
))))))
1112 inst
.error
= _("invalid constant");
1113 *str
= input_line_pointer
;
1114 input_line_pointer
= save_in
;
1118 *str
= input_line_pointer
;
1119 input_line_pointer
= save_in
;
1123 /* Turn a string in input_line_pointer into a floating point constant
1124 of type TYPE, and store the appropriate bytes in *LITP. The number
1125 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1126 returned, or NULL on OK.
1128 Note that fp constants aren't represent in the normal way on the ARM.
1129 In big endian mode, things are as expected. However, in little endian
1130 mode fp constants are big-endian word-wise, and little-endian byte-wise
1131 within the words. For example, (double) 1.1 in big endian mode is
1132 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1133 the byte sequence 99 99 f1 3f 9a 99 99 99.
1135 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1138 md_atof (int type
, char * litP
, int * sizeP
)
1141 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1173 return _("Unrecognized or unsupported floating point constant");
1176 t
= atof_ieee (input_line_pointer
, type
, words
);
1178 input_line_pointer
= t
;
1179 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1181 if (target_big_endian
)
1183 for (i
= 0; i
< prec
; i
++)
1185 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1186 litP
+= sizeof (LITTLENUM_TYPE
);
1191 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1192 for (i
= prec
- 1; i
>= 0; i
--)
1194 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= sizeof (LITTLENUM_TYPE
);
1198 /* For a 4 byte float the order of elements in `words' is 1 0.
1199 For an 8 byte float the order is 1 0 3 2. */
1200 for (i
= 0; i
< prec
; i
+= 2)
1202 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1203 sizeof (LITTLENUM_TYPE
));
1204 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1205 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1206 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1213 /* We handle all bad expressions here, so that we can report the faulty
1214 instruction in the error message. */
1217 md_operand (expressionS
* exp
)
1219 if (in_my_get_expression
)
1220 exp
->X_op
= O_illegal
;
1223 /* Immediate values. */
1226 /* Generic immediate-value read function for use in directives.
1227 Accepts anything that 'expression' can fold to a constant.
1228 *val receives the number. */
1231 immediate_for_directive (int *val
)
1234 exp
.X_op
= O_illegal
;
1236 if (is_immediate_prefix (*input_line_pointer
))
1238 input_line_pointer
++;
1242 if (exp
.X_op
!= O_constant
)
1244 as_bad (_("expected #constant"));
1245 ignore_rest_of_line ();
1248 *val
= exp
.X_add_number
;
1253 /* Register parsing. */
1255 /* Generic register parser. CCP points to what should be the
1256 beginning of a register name. If it is indeed a valid register
1257 name, advance CCP over it and return the reg_entry structure;
1258 otherwise return NULL. Does not issue diagnostics. */
1260 static struct reg_entry
*
1261 arm_reg_parse_multi (char **ccp
)
1265 struct reg_entry
*reg
;
1267 skip_whitespace (start
);
1269 #ifdef REGISTER_PREFIX
1270 if (*start
!= REGISTER_PREFIX
)
1274 #ifdef OPTIONAL_REGISTER_PREFIX
1275 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1280 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1285 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1287 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1297 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1298 enum arm_reg_type type
)
1300 /* Alternative syntaxes are accepted for a few register classes. */
1307 /* Generic coprocessor register names are allowed for these. */
1308 if (reg
&& reg
->type
== REG_TYPE_CN
)
1313 /* For backward compatibility, a bare number is valid here. */
1315 unsigned long processor
= strtoul (start
, ccp
, 10);
1316 if (*ccp
!= start
&& processor
<= 15)
1321 case REG_TYPE_MMXWC
:
1322 /* WC includes WCG. ??? I'm not sure this is true for all
1323 instructions that take WC registers. */
1324 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1335 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1336 return value is the register number or FAIL. */
1339 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1345 /* Do not allow a scalar (reg+index) to parse as a register. */
1346 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1349 if (reg
&& reg
->type
== type
)
1352 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1359 /* Parse a Neon type specifier. *STR should point at the leading '.'
1360 character. Does no verification at this stage that the type fits the opcode
1367 Can all be legally parsed by this function.
1369 Fills in neon_type struct pointer with parsed information, and updates STR
1370 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1371 type, FAIL if not. */
1374 parse_neon_type (struct neon_type
*type
, char **str
)
1381 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1383 enum neon_el_type thistype
= NT_untyped
;
1384 unsigned thissize
= -1u;
1391 /* Just a size without an explicit type. */
1395 switch (TOLOWER (*ptr
))
1397 case 'i': thistype
= NT_integer
; break;
1398 case 'f': thistype
= NT_float
; break;
1399 case 'p': thistype
= NT_poly
; break;
1400 case 's': thistype
= NT_signed
; break;
1401 case 'u': thistype
= NT_unsigned
; break;
1403 thistype
= NT_float
;
1408 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1414 /* .f is an abbreviation for .f32. */
1415 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1420 thissize
= strtoul (ptr
, &ptr
, 10);
1422 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1425 as_bad (_("bad size %d in type specifier"), thissize
);
1433 type
->el
[type
->elems
].type
= thistype
;
1434 type
->el
[type
->elems
].size
= thissize
;
1439 /* Empty/missing type is not a successful parse. */
1440 if (type
->elems
== 0)
1448 /* Errors may be set multiple times during parsing or bit encoding
1449 (particularly in the Neon bits), but usually the earliest error which is set
1450 will be the most meaningful. Avoid overwriting it with later (cascading)
1451 errors by calling this function. */
1454 first_error (const char *err
)
1460 /* Parse a single type, e.g. ".s32", leading period included. */
1462 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1465 struct neon_type optype
;
1469 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1471 if (optype
.elems
== 1)
1472 *vectype
= optype
.el
[0];
1475 first_error (_("only one type should be specified for operand"));
1481 first_error (_("vector type expected"));
1493 /* Special meanings for indices (which have a range of 0-7), which will fit into
1496 #define NEON_ALL_LANES 15
1497 #define NEON_INTERLEAVE_LANES 14
1499 /* Parse either a register or a scalar, with an optional type. Return the
1500 register number, and optionally fill in the actual type of the register
1501 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1502 type/index information in *TYPEINFO. */
1505 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1506 enum arm_reg_type
*rtype
,
1507 struct neon_typed_alias
*typeinfo
)
1510 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1511 struct neon_typed_alias atype
;
1512 struct neon_type_el parsetype
;
1516 atype
.eltype
.type
= NT_invtype
;
1517 atype
.eltype
.size
= -1;
1519 /* Try alternate syntax for some types of register. Note these are mutually
1520 exclusive with the Neon syntax extensions. */
1523 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1531 /* Undo polymorphism when a set of register types may be accepted. */
1532 if ((type
== REG_TYPE_NDQ
1533 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1534 || (type
== REG_TYPE_VFSD
1535 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1536 || (type
== REG_TYPE_NSDQ
1537 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1538 || reg
->type
== REG_TYPE_NQ
))
1539 || (type
== REG_TYPE_NSD
1540 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1541 || (type
== REG_TYPE_MMXWC
1542 && (reg
->type
== REG_TYPE_MMXWCG
)))
1543 type
= (enum arm_reg_type
) reg
->type
;
1545 if (type
!= reg
->type
)
1551 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1553 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1555 first_error (_("can't redefine type for operand"));
1558 atype
.defined
|= NTA_HASTYPE
;
1559 atype
.eltype
= parsetype
;
1562 if (skip_past_char (&str
, '[') == SUCCESS
)
1564 if (type
!= REG_TYPE_VFD
1565 && !(type
== REG_TYPE_VFS
1566 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1568 first_error (_("only D registers may be indexed"));
1572 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1574 first_error (_("can't change index for operand"));
1578 atype
.defined
|= NTA_HASINDEX
;
1580 if (skip_past_char (&str
, ']') == SUCCESS
)
1581 atype
.index
= NEON_ALL_LANES
;
1586 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1588 if (exp
.X_op
!= O_constant
)
1590 first_error (_("constant expression required"));
1594 if (skip_past_char (&str
, ']') == FAIL
)
1597 atype
.index
= exp
.X_add_number
;
1612 /* Like arm_reg_parse, but allow allow the following extra features:
1613 - If RTYPE is non-zero, return the (possibly restricted) type of the
1614 register (e.g. Neon double or quad reg when either has been requested).
1615 - If this is a Neon vector type with additional type information, fill
1616 in the struct pointed to by VECTYPE (if non-NULL).
1617 This function will fault on encountering a scalar. */
1620 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1621 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1623 struct neon_typed_alias atype
;
1625 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1630 /* Do not allow regname(... to parse as a register. */
1634 /* Do not allow a scalar (reg+index) to parse as a register. */
1635 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1637 first_error (_("register operand expected, but got scalar"));
1642 *vectype
= atype
.eltype
;
1649 #define NEON_SCALAR_REG(X) ((X) >> 4)
1650 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1652 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1653 have enough information to be able to do a good job bounds-checking. So, we
1654 just do easy checks here, and do further checks later. */
1657 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1661 struct neon_typed_alias atype
;
1662 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1665 reg_type
= REG_TYPE_VFS
;
1667 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1669 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1672 if (atype
.index
== NEON_ALL_LANES
)
1674 first_error (_("scalar must have an index"));
1677 else if (atype
.index
>= 64 / elsize
)
1679 first_error (_("scalar index out of range"));
1684 *type
= atype
.eltype
;
1688 return reg
* 16 + atype
.index
;
1691 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1694 parse_reg_list (char ** strp
)
1696 char * str
= * strp
;
1700 /* We come back here if we get ranges concatenated by '+' or '|'. */
1703 skip_whitespace (str
);
1717 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1719 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1729 first_error (_("bad range in register list"));
1733 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1735 if (range
& (1 << i
))
1737 (_("Warning: duplicated register (r%d) in register list"),
1745 if (range
& (1 << reg
))
1746 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1748 else if (reg
<= cur_reg
)
1749 as_tsktsk (_("Warning: register range not in ascending order"));
1754 while (skip_past_comma (&str
) != FAIL
1755 || (in_range
= 1, *str
++ == '-'));
1758 if (skip_past_char (&str
, '}') == FAIL
)
1760 first_error (_("missing `}'"));
1768 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1771 if (exp
.X_op
== O_constant
)
1773 if (exp
.X_add_number
1774 != (exp
.X_add_number
& 0x0000ffff))
1776 inst
.error
= _("invalid register mask");
1780 if ((range
& exp
.X_add_number
) != 0)
1782 int regno
= range
& exp
.X_add_number
;
1785 regno
= (1 << regno
) - 1;
1787 (_("Warning: duplicated register (r%d) in register list"),
1791 range
|= exp
.X_add_number
;
1795 if (inst
.relocs
[0].type
!= 0)
1797 inst
.error
= _("expression too complex");
1801 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1802 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1803 inst
.relocs
[0].pc_rel
= 0;
1807 if (*str
== '|' || *str
== '+')
1813 while (another_range
);
1819 /* Types of registers in a list. */
1828 /* Parse a VFP register list. If the string is invalid return FAIL.
1829 Otherwise return the number of registers, and set PBASE to the first
1830 register. Parses registers of type ETYPE.
1831 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1832 - Q registers can be used to specify pairs of D registers
1833 - { } can be omitted from around a singleton register list
1834 FIXME: This is not implemented, as it would require backtracking in
1837 This could be done (the meaning isn't really ambiguous), but doesn't
1838 fit in well with the current parsing framework.
1839 - 32 D registers may be used (also true for VFPv3).
1840 FIXME: Types are ignored in these register lists, which is probably a
1844 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1849 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1853 unsigned long mask
= 0;
1856 if (skip_past_char (&str
, '{') == FAIL
)
1858 inst
.error
= _("expecting {");
1865 regtype
= REG_TYPE_VFS
;
1870 regtype
= REG_TYPE_VFD
;
1873 case REGLIST_NEON_D
:
1874 regtype
= REG_TYPE_NDQ
;
1878 if (etype
!= REGLIST_VFP_S
)
1880 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1885 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1888 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1895 base_reg
= max_regs
;
1899 int setmask
= 1, addregs
= 1;
1901 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1903 if (new_base
== FAIL
)
1905 first_error (_(reg_expected_msgs
[regtype
]));
1909 if (new_base
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 /* Note: a value of 2 * n is returned for the register Q<n>. */
1916 if (regtype
== REG_TYPE_NQ
)
1922 if (new_base
< base_reg
)
1923 base_reg
= new_base
;
1925 if (mask
& (setmask
<< new_base
))
1927 first_error (_("invalid register list"));
1931 if ((mask
>> new_base
) != 0 && ! warned
)
1933 as_tsktsk (_("register list not in ascending order"));
1937 mask
|= setmask
<< new_base
;
1940 if (*str
== '-') /* We have the start of a range expression */
1946 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1949 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1953 if (high_range
>= max_regs
)
1955 first_error (_("register out of range in list"));
1959 if (regtype
== REG_TYPE_NQ
)
1960 high_range
= high_range
+ 1;
1962 if (high_range
<= new_base
)
1964 inst
.error
= _("register range not in ascending order");
1968 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1970 if (mask
& (setmask
<< new_base
))
1972 inst
.error
= _("invalid register list");
1976 mask
|= setmask
<< new_base
;
1981 while (skip_past_comma (&str
) != FAIL
);
1985 /* Sanity check -- should have raised a parse error above. */
1986 if (count
== 0 || count
> max_regs
)
1991 /* Final test -- the registers must be consecutive. */
1993 for (i
= 0; i
< count
; i
++)
1995 if ((mask
& (1u << i
)) == 0)
1997 inst
.error
= _("non-contiguous register range");
2007 /* True if two alias types are the same. */
2010 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2018 if (a
->defined
!= b
->defined
)
2021 if ((a
->defined
& NTA_HASTYPE
) != 0
2022 && (a
->eltype
.type
!= b
->eltype
.type
2023 || a
->eltype
.size
!= b
->eltype
.size
))
2026 if ((a
->defined
& NTA_HASINDEX
) != 0
2027 && (a
->index
!= b
->index
))
2033 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2034 The base register is put in *PBASE.
2035 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2037 The register stride (minus one) is put in bit 4 of the return value.
2038 Bits [6:5] encode the list length (minus one).
2039 The type of the list elements is put in *ELTYPE, if non-NULL. */
2041 #define NEON_LANE(X) ((X) & 0xf)
2042 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2043 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2046 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2047 struct neon_type_el
*eltype
)
2054 int leading_brace
= 0;
2055 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2056 const char *const incr_error
= _("register stride must be 1 or 2");
2057 const char *const type_error
= _("mismatched element/structure types in list");
2058 struct neon_typed_alias firsttype
;
2059 firsttype
.defined
= 0;
2060 firsttype
.eltype
.type
= NT_invtype
;
2061 firsttype
.eltype
.size
= -1;
2062 firsttype
.index
= -1;
2064 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2069 struct neon_typed_alias atype
;
2070 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2074 first_error (_(reg_expected_msgs
[rtype
]));
2081 if (rtype
== REG_TYPE_NQ
)
2087 else if (reg_incr
== -1)
2089 reg_incr
= getreg
- base_reg
;
2090 if (reg_incr
< 1 || reg_incr
> 2)
2092 first_error (_(incr_error
));
2096 else if (getreg
!= base_reg
+ reg_incr
* count
)
2098 first_error (_(incr_error
));
2102 if (! neon_alias_types_same (&atype
, &firsttype
))
2104 first_error (_(type_error
));
2108 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2112 struct neon_typed_alias htype
;
2113 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2115 lane
= NEON_INTERLEAVE_LANES
;
2116 else if (lane
!= NEON_INTERLEAVE_LANES
)
2118 first_error (_(type_error
));
2123 else if (reg_incr
!= 1)
2125 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2129 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2132 first_error (_(reg_expected_msgs
[rtype
]));
2135 if (! neon_alias_types_same (&htype
, &firsttype
))
2137 first_error (_(type_error
));
2140 count
+= hireg
+ dregs
- getreg
;
2144 /* If we're using Q registers, we can't use [] or [n] syntax. */
2145 if (rtype
== REG_TYPE_NQ
)
2151 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2155 else if (lane
!= atype
.index
)
2157 first_error (_(type_error
));
2161 else if (lane
== -1)
2162 lane
= NEON_INTERLEAVE_LANES
;
2163 else if (lane
!= NEON_INTERLEAVE_LANES
)
2165 first_error (_(type_error
));
2170 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2172 /* No lane set by [x]. We must be interleaving structures. */
2174 lane
= NEON_INTERLEAVE_LANES
;
2177 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2178 || (count
> 1 && reg_incr
== -1))
2180 first_error (_("error parsing element/structure list"));
2184 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2186 first_error (_("expected }"));
2194 *eltype
= firsttype
.eltype
;
2199 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2202 /* Parse an explicit relocation suffix on an expression. This is
2203 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2204 arm_reloc_hsh contains no entries, so this function can only
2205 succeed if there is no () after the word. Returns -1 on error,
2206 BFD_RELOC_UNUSED if there wasn't any suffix. */
2209 parse_reloc (char **str
)
2211 struct reloc_entry
*r
;
2215 return BFD_RELOC_UNUSED
;
2220 while (*q
&& *q
!= ')' && *q
!= ',')
2225 if ((r
= (struct reloc_entry
*)
2226 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2233 /* Directives: register aliases. */
2235 static struct reg_entry
*
2236 insert_reg_alias (char *str
, unsigned number
, int type
)
2238 struct reg_entry
*new_reg
;
2241 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2243 if (new_reg
->builtin
)
2244 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2246 /* Only warn about a redefinition if it's not defined as the
2248 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2249 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2254 name
= xstrdup (str
);
2255 new_reg
= XNEW (struct reg_entry
);
2257 new_reg
->name
= name
;
2258 new_reg
->number
= number
;
2259 new_reg
->type
= type
;
2260 new_reg
->builtin
= FALSE
;
2261 new_reg
->neon
= NULL
;
2263 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2270 insert_neon_reg_alias (char *str
, int number
, int type
,
2271 struct neon_typed_alias
*atype
)
2273 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2277 first_error (_("attempt to redefine typed alias"));
2283 reg
->neon
= XNEW (struct neon_typed_alias
);
2284 *reg
->neon
= *atype
;
2288 /* Look for the .req directive. This is of the form:
2290 new_register_name .req existing_register_name
2292 If we find one, or if it looks sufficiently like one that we want to
2293 handle any error here, return TRUE. Otherwise return FALSE. */
2296 create_register_alias (char * newname
, char *p
)
2298 struct reg_entry
*old
;
2299 char *oldname
, *nbuf
;
2302 /* The input scrubber ensures that whitespace after the mnemonic is
2303 collapsed to single spaces. */
2305 if (strncmp (oldname
, " .req ", 6) != 0)
2309 if (*oldname
== '\0')
2312 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2315 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2319 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2320 the desired alias name, and p points to its end. If not, then
2321 the desired alias name is in the global original_case_string. */
2322 #ifdef TC_CASE_SENSITIVE
2325 newname
= original_case_string
;
2326 nlen
= strlen (newname
);
2329 nbuf
= xmemdup0 (newname
, nlen
);
2331 /* Create aliases under the new name as stated; an all-lowercase
2332 version of the new name; and an all-uppercase version of the new
2334 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2336 for (p
= nbuf
; *p
; p
++)
2339 if (strncmp (nbuf
, newname
, nlen
))
2341 /* If this attempt to create an additional alias fails, do not bother
2342 trying to create the all-lower case alias. We will fail and issue
2343 a second, duplicate error message. This situation arises when the
2344 programmer does something like:
2347 The second .req creates the "Foo" alias but then fails to create
2348 the artificial FOO alias because it has already been created by the
2350 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2357 for (p
= nbuf
; *p
; p
++)
2360 if (strncmp (nbuf
, newname
, nlen
))
2361 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2368 /* Create a Neon typed/indexed register alias using directives, e.g.:
2373 These typed registers can be used instead of the types specified after the
2374 Neon mnemonic, so long as all operands given have types. Types can also be
2375 specified directly, e.g.:
2376 vadd d0.s32, d1.s32, d2.s32 */
2379 create_neon_reg_alias (char *newname
, char *p
)
2381 enum arm_reg_type basetype
;
2382 struct reg_entry
*basereg
;
2383 struct reg_entry mybasereg
;
2384 struct neon_type ntype
;
2385 struct neon_typed_alias typeinfo
;
2386 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2389 typeinfo
.defined
= 0;
2390 typeinfo
.eltype
.type
= NT_invtype
;
2391 typeinfo
.eltype
.size
= -1;
2392 typeinfo
.index
= -1;
2396 if (strncmp (p
, " .dn ", 5) == 0)
2397 basetype
= REG_TYPE_VFD
;
2398 else if (strncmp (p
, " .qn ", 5) == 0)
2399 basetype
= REG_TYPE_NQ
;
2408 basereg
= arm_reg_parse_multi (&p
);
2410 if (basereg
&& basereg
->type
!= basetype
)
2412 as_bad (_("bad type for register"));
2416 if (basereg
== NULL
)
2419 /* Try parsing as an integer. */
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2421 if (exp
.X_op
!= O_constant
)
2423 as_bad (_("expression must be constant"));
2426 basereg
= &mybasereg
;
2427 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2433 typeinfo
= *basereg
->neon
;
2435 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2437 /* We got a type. */
2438 if (typeinfo
.defined
& NTA_HASTYPE
)
2440 as_bad (_("can't redefine the type of a register alias"));
2444 typeinfo
.defined
|= NTA_HASTYPE
;
2445 if (ntype
.elems
!= 1)
2447 as_bad (_("you must specify a single type only"));
2450 typeinfo
.eltype
= ntype
.el
[0];
2453 if (skip_past_char (&p
, '[') == SUCCESS
)
2456 /* We got a scalar index. */
2458 if (typeinfo
.defined
& NTA_HASINDEX
)
2460 as_bad (_("can't redefine the index of a scalar alias"));
2464 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2466 if (exp
.X_op
!= O_constant
)
2468 as_bad (_("scalar index must be constant"));
2472 typeinfo
.defined
|= NTA_HASINDEX
;
2473 typeinfo
.index
= exp
.X_add_number
;
2475 if (skip_past_char (&p
, ']') == FAIL
)
2477 as_bad (_("expecting ]"));
2482 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2483 the desired alias name, and p points to its end. If not, then
2484 the desired alias name is in the global original_case_string. */
2485 #ifdef TC_CASE_SENSITIVE
2486 namelen
= nameend
- newname
;
2488 newname
= original_case_string
;
2489 namelen
= strlen (newname
);
2492 namebuf
= xmemdup0 (newname
, namelen
);
2494 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2495 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2497 /* Insert name in all uppercase. */
2498 for (p
= namebuf
; *p
; p
++)
2501 if (strncmp (namebuf
, newname
, namelen
))
2502 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2503 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2505 /* Insert name in all lowercase. */
2506 for (p
= namebuf
; *p
; p
++)
2509 if (strncmp (namebuf
, newname
, namelen
))
2510 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2511 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2517 /* Should never be called, as .req goes between the alias and the
2518 register name, not at the beginning of the line. */
2521 s_req (int a ATTRIBUTE_UNUSED
)
2523 as_bad (_("invalid syntax for .req directive"));
2527 s_dn (int a ATTRIBUTE_UNUSED
)
2529 as_bad (_("invalid syntax for .dn directive"));
2533 s_qn (int a ATTRIBUTE_UNUSED
)
2535 as_bad (_("invalid syntax for .qn directive"));
2538 /* The .unreq directive deletes an alias which was previously defined
2539 by .req. For example:
2545 s_unreq (int a ATTRIBUTE_UNUSED
)
2550 name
= input_line_pointer
;
2552 while (*input_line_pointer
!= 0
2553 && *input_line_pointer
!= ' '
2554 && *input_line_pointer
!= '\n')
2555 ++input_line_pointer
;
2557 saved_char
= *input_line_pointer
;
2558 *input_line_pointer
= 0;
2561 as_bad (_("invalid syntax for .unreq directive"));
2564 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2568 as_bad (_("unknown register alias '%s'"), name
);
2569 else if (reg
->builtin
)
2570 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2577 hash_delete (arm_reg_hsh
, name
, FALSE
);
2578 free ((char *) reg
->name
);
2583 /* Also locate the all upper case and all lower case versions.
2584 Do not complain if we cannot find one or the other as it
2585 was probably deleted above. */
2587 nbuf
= strdup (name
);
2588 for (p
= nbuf
; *p
; p
++)
2590 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2593 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2594 free ((char *) reg
->name
);
2600 for (p
= nbuf
; *p
; p
++)
2602 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2605 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2606 free ((char *) reg
->name
);
2616 *input_line_pointer
= saved_char
;
2617 demand_empty_rest_of_line ();
2620 /* Directives: Instruction set selection. */
2623 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2624 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2625 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2626 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2628 /* Create a new mapping symbol for the transition to STATE. */
2631 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2634 const char * symname
;
2641 type
= BSF_NO_FLAGS
;
2645 type
= BSF_NO_FLAGS
;
2649 type
= BSF_NO_FLAGS
;
2655 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2656 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2661 THUMB_SET_FUNC (symbolP
, 0);
2662 ARM_SET_THUMB (symbolP
, 0);
2663 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2667 THUMB_SET_FUNC (symbolP
, 1);
2668 ARM_SET_THUMB (symbolP
, 1);
2669 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2677 /* Save the mapping symbols for future reference. Also check that
2678 we do not place two mapping symbols at the same offset within a
2679 frag. We'll handle overlap between frags in
2680 check_mapping_symbols.
2682 If .fill or other data filling directive generates zero sized data,
2683 the mapping symbol for the following code will have the same value
2684 as the one generated for the data filling directive. In this case,
2685 we replace the old symbol with the new one at the same address. */
2688 if (frag
->tc_frag_data
.first_map
!= NULL
)
2690 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2691 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2693 frag
->tc_frag_data
.first_map
= symbolP
;
2695 if (frag
->tc_frag_data
.last_map
!= NULL
)
2697 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2698 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2699 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2701 frag
->tc_frag_data
.last_map
= symbolP
;
2704 /* We must sometimes convert a region marked as code to data during
2705 code alignment, if an odd number of bytes have to be padded. The
2706 code mapping symbol is pushed to an aligned address. */
2709 insert_data_mapping_symbol (enum mstate state
,
2710 valueT value
, fragS
*frag
, offsetT bytes
)
2712 /* If there was already a mapping symbol, remove it. */
2713 if (frag
->tc_frag_data
.last_map
!= NULL
2714 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2716 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2720 know (frag
->tc_frag_data
.first_map
== symp
);
2721 frag
->tc_frag_data
.first_map
= NULL
;
2723 frag
->tc_frag_data
.last_map
= NULL
;
2724 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2727 make_mapping_symbol (MAP_DATA
, value
, frag
);
2728 make_mapping_symbol (state
, value
+ bytes
, frag
);
2731 static void mapping_state_2 (enum mstate state
, int max_chars
);
2733 /* Set the mapping state to STATE. Only call this when about to
2734 emit some STATE bytes to the file. */
2736 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2738 mapping_state (enum mstate state
)
2740 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2742 if (mapstate
== state
)
2743 /* The mapping symbol has already been emitted.
2744 There is nothing else to do. */
2747 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2749 All ARM instructions require 4-byte alignment.
2750 (Almost) all Thumb instructions require 2-byte alignment.
2752 When emitting instructions into any section, mark the section
2755 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2756 but themselves require 2-byte alignment; this applies to some
2757 PC- relative forms. However, these cases will involve implicit
2758 literal pool generation or an explicit .align >=2, both of
2759 which will cause the section to me marked with sufficient
2760 alignment. Thus, we don't handle those cases here. */
2761 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2763 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2764 /* This case will be evaluated later. */
2767 mapping_state_2 (state
, 0);
2770 /* Same as mapping_state, but MAX_CHARS bytes have already been
2771 allocated. Put the mapping symbol that far back. */
2774 mapping_state_2 (enum mstate state
, int max_chars
)
2776 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2778 if (!SEG_NORMAL (now_seg
))
2781 if (mapstate
== state
)
2782 /* The mapping symbol has already been emitted.
2783 There is nothing else to do. */
2786 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2787 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2789 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2790 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2793 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2796 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2797 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2801 #define mapping_state(x) ((void)0)
2802 #define mapping_state_2(x, y) ((void)0)
2805 /* Find the real, Thumb encoded start of a Thumb function. */
2809 find_real_start (symbolS
* symbolP
)
2812 const char * name
= S_GET_NAME (symbolP
);
2813 symbolS
* new_target
;
2815 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2816 #define STUB_NAME ".real_start_of"
2821 /* The compiler may generate BL instructions to local labels because
2822 it needs to perform a branch to a far away location. These labels
2823 do not have a corresponding ".real_start_of" label. We check
2824 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2825 the ".real_start_of" convention for nonlocal branches. */
2826 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2829 real_start
= concat (STUB_NAME
, name
, NULL
);
2830 new_target
= symbol_find (real_start
);
2833 if (new_target
== NULL
)
2835 as_warn (_("Failed to find real start of function: %s\n"), name
);
2836 new_target
= symbolP
;
2844 opcode_select (int width
)
2851 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2852 as_bad (_("selected processor does not support THUMB opcodes"));
2855 /* No need to force the alignment, since we will have been
2856 coming from ARM mode, which is word-aligned. */
2857 record_alignment (now_seg
, 1);
2864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2865 as_bad (_("selected processor does not support ARM opcodes"));
2870 frag_align (2, 0, 0);
2872 record_alignment (now_seg
, 1);
2877 as_bad (_("invalid instruction size selected (%d)"), width
);
2882 s_arm (int ignore ATTRIBUTE_UNUSED
)
2885 demand_empty_rest_of_line ();
2889 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2892 demand_empty_rest_of_line ();
2896 s_code (int unused ATTRIBUTE_UNUSED
)
2900 temp
= get_absolute_expression ();
2905 opcode_select (temp
);
2909 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2914 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2916 /* If we are not already in thumb mode go into it, EVEN if
2917 the target processor does not support thumb instructions.
2918 This is used by gcc/config/arm/lib1funcs.asm for example
2919 to compile interworking support functions even if the
2920 target processor should not support interworking. */
2924 record_alignment (now_seg
, 1);
2927 demand_empty_rest_of_line ();
2931 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2935 /* The following label is the name/address of the start of a Thumb function.
2936 We need to know this for the interworking support. */
2937 label_is_thumb_function_name
= TRUE
;
2940 /* Perform a .set directive, but also mark the alias as
2941 being a thumb function. */
2944 s_thumb_set (int equiv
)
2946 /* XXX the following is a duplicate of the code for s_set() in read.c
2947 We cannot just call that code as we need to get at the symbol that
2954 /* Especial apologies for the random logic:
2955 This just grew, and could be parsed much more simply!
2957 delim
= get_symbol_name (& name
);
2958 end_name
= input_line_pointer
;
2959 (void) restore_line_pointer (delim
);
2961 if (*input_line_pointer
!= ',')
2964 as_bad (_("expected comma after name \"%s\""), name
);
2966 ignore_rest_of_line ();
2970 input_line_pointer
++;
2973 if (name
[0] == '.' && name
[1] == '\0')
2975 /* XXX - this should not happen to .thumb_set. */
2979 if ((symbolP
= symbol_find (name
)) == NULL
2980 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2983 /* When doing symbol listings, play games with dummy fragments living
2984 outside the normal fragment chain to record the file and line info
2986 if (listing
& LISTING_SYMBOLS
)
2988 extern struct list_info_struct
* listing_tail
;
2989 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2991 memset (dummy_frag
, 0, sizeof (fragS
));
2992 dummy_frag
->fr_type
= rs_fill
;
2993 dummy_frag
->line
= listing_tail
;
2994 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2995 dummy_frag
->fr_symbol
= symbolP
;
2999 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3002 /* "set" symbols are local unless otherwise specified. */
3003 SF_SET_LOCAL (symbolP
);
3004 #endif /* OBJ_COFF */
3005 } /* Make a new symbol. */
3007 symbol_table_insert (symbolP
);
3012 && S_IS_DEFINED (symbolP
)
3013 && S_GET_SEGMENT (symbolP
) != reg_section
)
3014 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3016 pseudo_set (symbolP
);
3018 demand_empty_rest_of_line ();
3020 /* XXX Now we come to the Thumb specific bit of code. */
3022 THUMB_SET_FUNC (symbolP
, 1);
3023 ARM_SET_THUMB (symbolP
, 1);
3024 #if defined OBJ_ELF || defined OBJ_COFF
3025 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3029 /* Directives: Mode selection. */
3031 /* .syntax [unified|divided] - choose the new unified syntax
3032 (same for Arm and Thumb encoding, modulo slight differences in what
3033 can be represented) or the old divergent syntax for each mode. */
3035 s_syntax (int unused ATTRIBUTE_UNUSED
)
3039 delim
= get_symbol_name (& name
);
3041 if (!strcasecmp (name
, "unified"))
3042 unified_syntax
= TRUE
;
3043 else if (!strcasecmp (name
, "divided"))
3044 unified_syntax
= FALSE
;
3047 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3050 (void) restore_line_pointer (delim
);
3051 demand_empty_rest_of_line ();
3054 /* Directives: sectioning and alignment. */
3057 s_bss (int ignore ATTRIBUTE_UNUSED
)
3059 /* We don't support putting frags in the BSS segment, we fake it by
3060 marking in_bss, then looking at s_skip for clues. */
3061 subseg_set (bss_section
, 0);
3062 demand_empty_rest_of_line ();
3064 #ifdef md_elf_section_change_hook
3065 md_elf_section_change_hook ();
3070 s_even (int ignore ATTRIBUTE_UNUSED
)
3072 /* Never make frag if expect extra pass. */
3074 frag_align (1, 0, 0);
3076 record_alignment (now_seg
, 1);
3078 demand_empty_rest_of_line ();
3081 /* Directives: CodeComposer Studio. */
3083 /* .ref (for CodeComposer Studio syntax only). */
3085 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3087 if (codecomposer_syntax
)
3088 ignore_rest_of_line ();
3090 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3093 /* If name is not NULL, then it is used for marking the beginning of a
3094 function, whereas if it is NULL then it means the function end. */
3096 asmfunc_debug (const char * name
)
3098 static const char * last_name
= NULL
;
3102 gas_assert (last_name
== NULL
);
3105 if (debug_type
== DEBUG_STABS
)
3106 stabs_generate_asm_func (name
, name
);
3110 gas_assert (last_name
!= NULL
);
3112 if (debug_type
== DEBUG_STABS
)
3113 stabs_generate_asm_endfunc (last_name
, last_name
);
3120 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3122 if (codecomposer_syntax
)
3124 switch (asmfunc_state
)
3126 case OUTSIDE_ASMFUNC
:
3127 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3130 case WAITING_ASMFUNC_NAME
:
3131 as_bad (_(".asmfunc repeated."));
3134 case WAITING_ENDASMFUNC
:
3135 as_bad (_(".asmfunc without function."));
3138 demand_empty_rest_of_line ();
3141 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3145 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3147 if (codecomposer_syntax
)
3149 switch (asmfunc_state
)
3151 case OUTSIDE_ASMFUNC
:
3152 as_bad (_(".endasmfunc without a .asmfunc."));
3155 case WAITING_ASMFUNC_NAME
:
3156 as_bad (_(".endasmfunc without function."));
3159 case WAITING_ENDASMFUNC
:
3160 asmfunc_state
= OUTSIDE_ASMFUNC
;
3161 asmfunc_debug (NULL
);
3164 demand_empty_rest_of_line ();
3167 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3171 s_ccs_def (int name
)
3173 if (codecomposer_syntax
)
3176 as_bad (_(".def pseudo-op only available with -mccs flag."));
3179 /* Directives: Literal pools. */
3181 static literal_pool
*
3182 find_literal_pool (void)
3184 literal_pool
* pool
;
3186 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3188 if (pool
->section
== now_seg
3189 && pool
->sub_section
== now_subseg
)
3196 static literal_pool
*
3197 find_or_make_literal_pool (void)
3199 /* Next literal pool ID number. */
3200 static unsigned int latest_pool_num
= 1;
3201 literal_pool
* pool
;
3203 pool
= find_literal_pool ();
3207 /* Create a new pool. */
3208 pool
= XNEW (literal_pool
);
3212 pool
->next_free_entry
= 0;
3213 pool
->section
= now_seg
;
3214 pool
->sub_section
= now_subseg
;
3215 pool
->next
= list_of_pools
;
3216 pool
->symbol
= NULL
;
3217 pool
->alignment
= 2;
3219 /* Add it to the list. */
3220 list_of_pools
= pool
;
3223 /* New pools, and emptied pools, will have a NULL symbol. */
3224 if (pool
->symbol
== NULL
)
3226 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3227 (valueT
) 0, &zero_address_frag
);
3228 pool
->id
= latest_pool_num
++;
3235 /* Add the literal in the global 'inst'
3236 structure to the relevant literal pool. */
3239 add_to_lit_pool (unsigned int nbytes
)
3241 #define PADDING_SLOT 0x1
3242 #define LIT_ENTRY_SIZE_MASK 0xFF
3243 literal_pool
* pool
;
3244 unsigned int entry
, pool_size
= 0;
3245 bfd_boolean padding_slot_p
= FALSE
;
3251 imm1
= inst
.operands
[1].imm
;
3252 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3253 : inst
.relocs
[0].exp
.X_unsigned
? 0
3254 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3255 if (target_big_endian
)
3258 imm2
= inst
.operands
[1].imm
;
3262 pool
= find_or_make_literal_pool ();
3264 /* Check if this literal value is already in the pool. */
3265 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3269 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3270 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3271 && (pool
->literals
[entry
].X_add_number
3272 == inst
.relocs
[0].exp
.X_add_number
)
3273 && (pool
->literals
[entry
].X_md
== nbytes
)
3274 && (pool
->literals
[entry
].X_unsigned
3275 == inst
.relocs
[0].exp
.X_unsigned
))
3278 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3279 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3280 && (pool
->literals
[entry
].X_add_number
3281 == inst
.relocs
[0].exp
.X_add_number
)
3282 && (pool
->literals
[entry
].X_add_symbol
3283 == inst
.relocs
[0].exp
.X_add_symbol
)
3284 && (pool
->literals
[entry
].X_op_symbol
3285 == inst
.relocs
[0].exp
.X_op_symbol
)
3286 && (pool
->literals
[entry
].X_md
== nbytes
))
3289 else if ((nbytes
== 8)
3290 && !(pool_size
& 0x7)
3291 && ((entry
+ 1) != pool
->next_free_entry
)
3292 && (pool
->literals
[entry
].X_op
== O_constant
)
3293 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3294 && (pool
->literals
[entry
].X_unsigned
3295 == inst
.relocs
[0].exp
.X_unsigned
)
3296 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3297 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3298 && (pool
->literals
[entry
+ 1].X_unsigned
3299 == inst
.relocs
[0].exp
.X_unsigned
))
3302 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3303 if (padding_slot_p
&& (nbytes
== 4))
3309 /* Do we need to create a new entry? */
3310 if (entry
== pool
->next_free_entry
)
3312 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3314 inst
.error
= _("literal pool overflow");
3320 /* For 8-byte entries, we align to an 8-byte boundary,
3321 and split it into two 4-byte entries, because on 32-bit
3322 host, 8-byte constants are treated as big num, thus
3323 saved in "generic_bignum" which will be overwritten
3324 by later assignments.
3326 We also need to make sure there is enough space for
3329 We also check to make sure the literal operand is a
3331 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3332 || inst
.relocs
[0].exp
.X_op
== O_big
))
3334 inst
.error
= _("invalid type for literal pool");
3337 else if (pool_size
& 0x7)
3339 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3341 inst
.error
= _("literal pool overflow");
3345 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3346 pool
->literals
[entry
].X_op
= O_constant
;
3347 pool
->literals
[entry
].X_add_number
= 0;
3348 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3349 pool
->next_free_entry
+= 1;
3352 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3354 inst
.error
= _("literal pool overflow");
3358 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3359 pool
->literals
[entry
].X_op
= O_constant
;
3360 pool
->literals
[entry
].X_add_number
= imm1
;
3361 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3362 pool
->literals
[entry
++].X_md
= 4;
3363 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3364 pool
->literals
[entry
].X_op
= O_constant
;
3365 pool
->literals
[entry
].X_add_number
= imm2
;
3366 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3367 pool
->literals
[entry
].X_md
= 4;
3368 pool
->alignment
= 3;
3369 pool
->next_free_entry
+= 1;
3373 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3374 pool
->literals
[entry
].X_md
= 4;
3378 /* PR ld/12974: Record the location of the first source line to reference
3379 this entry in the literal pool. If it turns out during linking that the
3380 symbol does not exist we will be able to give an accurate line number for
3381 the (first use of the) missing reference. */
3382 if (debug_type
== DEBUG_DWARF2
)
3383 dwarf2_where (pool
->locs
+ entry
);
3385 pool
->next_free_entry
+= 1;
3387 else if (padding_slot_p
)
3389 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3390 pool
->literals
[entry
].X_md
= nbytes
;
3393 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3394 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3395 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3401 tc_start_label_without_colon (void)
3403 bfd_boolean ret
= TRUE
;
3405 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3407 const char *label
= input_line_pointer
;
3409 while (!is_end_of_line
[(int) label
[-1]])
3414 as_bad (_("Invalid label '%s'"), label
);
3418 asmfunc_debug (label
);
3420 asmfunc_state
= WAITING_ENDASMFUNC
;
3426 /* Can't use symbol_new here, so have to create a symbol and then at
3427 a later date assign it a value. That's what these functions do. */
3430 symbol_locate (symbolS
* symbolP
,
3431 const char * name
, /* It is copied, the caller can modify. */
3432 segT segment
, /* Segment identifier (SEG_<something>). */
3433 valueT valu
, /* Symbol value. */
3434 fragS
* frag
) /* Associated fragment. */
3437 char * preserved_copy_of_name
;
3439 name_length
= strlen (name
) + 1; /* +1 for \0. */
3440 obstack_grow (¬es
, name
, name_length
);
3441 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3443 #ifdef tc_canonicalize_symbol_name
3444 preserved_copy_of_name
=
3445 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3448 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3450 S_SET_SEGMENT (symbolP
, segment
);
3451 S_SET_VALUE (symbolP
, valu
);
3452 symbol_clear_list_pointers (symbolP
);
3454 symbol_set_frag (symbolP
, frag
);
3456 /* Link to end of symbol chain. */
3458 extern int symbol_table_frozen
;
3460 if (symbol_table_frozen
)
3464 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3466 obj_symbol_new_hook (symbolP
);
3468 #ifdef tc_symbol_new_hook
3469 tc_symbol_new_hook (symbolP
);
3473 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3474 #endif /* DEBUG_SYMS */
3478 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3481 literal_pool
* pool
;
3484 pool
= find_literal_pool ();
3486 || pool
->symbol
== NULL
3487 || pool
->next_free_entry
== 0)
3490 /* Align pool as you have word accesses.
3491 Only make a frag if we have to. */
3493 frag_align (pool
->alignment
, 0, 0);
3495 record_alignment (now_seg
, 2);
3498 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3499 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3501 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3503 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3504 (valueT
) frag_now_fix (), frag_now
);
3505 symbol_table_insert (pool
->symbol
);
3507 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3509 #if defined OBJ_COFF || defined OBJ_ELF
3510 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3513 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3516 if (debug_type
== DEBUG_DWARF2
)
3517 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3519 /* First output the expression in the instruction to the pool. */
3520 emit_expr (&(pool
->literals
[entry
]),
3521 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3524 /* Mark the pool as empty. */
3525 pool
->next_free_entry
= 0;
3526 pool
->symbol
= NULL
;
3530 /* Forward declarations for functions below, in the MD interface
3532 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3533 static valueT
create_unwind_entry (int);
3534 static void start_unwind_section (const segT
, int);
3535 static void add_unwind_opcode (valueT
, int);
3536 static void flush_pending_unwind (void);
3538 /* Directives: Data. */
3541 s_arm_elf_cons (int nbytes
)
3545 #ifdef md_flush_pending_output
3546 md_flush_pending_output ();
3549 if (is_it_end_of_statement ())
3551 demand_empty_rest_of_line ();
3555 #ifdef md_cons_align
3556 md_cons_align (nbytes
);
3559 mapping_state (MAP_DATA
);
3563 char *base
= input_line_pointer
;
3567 if (exp
.X_op
!= O_symbol
)
3568 emit_expr (&exp
, (unsigned int) nbytes
);
3571 char *before_reloc
= input_line_pointer
;
3572 reloc
= parse_reloc (&input_line_pointer
);
3575 as_bad (_("unrecognized relocation suffix"));
3576 ignore_rest_of_line ();
3579 else if (reloc
== BFD_RELOC_UNUSED
)
3580 emit_expr (&exp
, (unsigned int) nbytes
);
3583 reloc_howto_type
*howto
= (reloc_howto_type
*)
3584 bfd_reloc_type_lookup (stdoutput
,
3585 (bfd_reloc_code_real_type
) reloc
);
3586 int size
= bfd_get_reloc_size (howto
);
3588 if (reloc
== BFD_RELOC_ARM_PLT32
)
3590 as_bad (_("(plt) is only valid on branch targets"));
3591 reloc
= BFD_RELOC_UNUSED
;
3596 as_bad (ngettext ("%s relocations do not fit in %d byte",
3597 "%s relocations do not fit in %d bytes",
3599 howto
->name
, nbytes
);
3602 /* We've parsed an expression stopping at O_symbol.
3603 But there may be more expression left now that we
3604 have parsed the relocation marker. Parse it again.
3605 XXX Surely there is a cleaner way to do this. */
3606 char *p
= input_line_pointer
;
3608 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3610 memcpy (save_buf
, base
, input_line_pointer
- base
);
3611 memmove (base
+ (input_line_pointer
- before_reloc
),
3612 base
, before_reloc
- base
);
3614 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3616 memcpy (base
, save_buf
, p
- base
);
3618 offset
= nbytes
- size
;
3619 p
= frag_more (nbytes
);
3620 memset (p
, 0, nbytes
);
3621 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3622 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3628 while (*input_line_pointer
++ == ',');
3630 /* Put terminator back into stream. */
3631 input_line_pointer
--;
3632 demand_empty_rest_of_line ();
3635 /* Emit an expression containing a 32-bit thumb instruction.
3636 Implementation based on put_thumb32_insn. */
3639 emit_thumb32_expr (expressionS
* exp
)
3641 expressionS exp_high
= *exp
;
3643 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3644 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3645 exp
->X_add_number
&= 0xffff;
3646 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3649 /* Guess the instruction size based on the opcode. */
3652 thumb_insn_size (int opcode
)
3654 if ((unsigned int) opcode
< 0xe800u
)
3656 else if ((unsigned int) opcode
>= 0xe8000000u
)
3663 emit_insn (expressionS
*exp
, int nbytes
)
3667 if (exp
->X_op
== O_constant
)
3672 size
= thumb_insn_size (exp
->X_add_number
);
3676 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3678 as_bad (_(".inst.n operand too big. "\
3679 "Use .inst.w instead"));
3684 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3685 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3687 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3689 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3690 emit_thumb32_expr (exp
);
3692 emit_expr (exp
, (unsigned int) size
);
3694 it_fsm_post_encode ();
3698 as_bad (_("cannot determine Thumb instruction size. " \
3699 "Use .inst.n/.inst.w instead"));
3702 as_bad (_("constant expression required"));
3707 /* Like s_arm_elf_cons but do not use md_cons_align and
3708 set the mapping state to MAP_ARM/MAP_THUMB. */
3711 s_arm_elf_inst (int nbytes
)
3713 if (is_it_end_of_statement ())
3715 demand_empty_rest_of_line ();
3719 /* Calling mapping_state () here will not change ARM/THUMB,
3720 but will ensure not to be in DATA state. */
3723 mapping_state (MAP_THUMB
);
3728 as_bad (_("width suffixes are invalid in ARM mode"));
3729 ignore_rest_of_line ();
3735 mapping_state (MAP_ARM
);
3744 if (! emit_insn (& exp
, nbytes
))
3746 ignore_rest_of_line ();
3750 while (*input_line_pointer
++ == ',');
3752 /* Put terminator back into stream. */
3753 input_line_pointer
--;
3754 demand_empty_rest_of_line ();
3757 /* Parse a .rel31 directive. */
3760 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3767 if (*input_line_pointer
== '1')
3768 highbit
= 0x80000000;
3769 else if (*input_line_pointer
!= '0')
3770 as_bad (_("expected 0 or 1"));
3772 input_line_pointer
++;
3773 if (*input_line_pointer
!= ',')
3774 as_bad (_("missing comma"));
3775 input_line_pointer
++;
3777 #ifdef md_flush_pending_output
3778 md_flush_pending_output ();
3781 #ifdef md_cons_align
3785 mapping_state (MAP_DATA
);
3790 md_number_to_chars (p
, highbit
, 4);
3791 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3792 BFD_RELOC_ARM_PREL31
);
3794 demand_empty_rest_of_line ();
3797 /* Directives: AEABI stack-unwind tables. */
3799 /* Parse an unwind_fnstart directive. Simply records the current location. */
3802 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3804 demand_empty_rest_of_line ();
3805 if (unwind
.proc_start
)
3807 as_bad (_("duplicate .fnstart directive"));
3811 /* Mark the start of the function. */
3812 unwind
.proc_start
= expr_build_dot ();
3814 /* Reset the rest of the unwind info. */
3815 unwind
.opcode_count
= 0;
3816 unwind
.table_entry
= NULL
;
3817 unwind
.personality_routine
= NULL
;
3818 unwind
.personality_index
= -1;
3819 unwind
.frame_size
= 0;
3820 unwind
.fp_offset
= 0;
3821 unwind
.fp_reg
= REG_SP
;
3823 unwind
.sp_restored
= 0;
3827 /* Parse a handlerdata directive. Creates the exception handling table entry
3828 for the function. */
3831 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3833 demand_empty_rest_of_line ();
3834 if (!unwind
.proc_start
)
3835 as_bad (MISSING_FNSTART
);
3837 if (unwind
.table_entry
)
3838 as_bad (_("duplicate .handlerdata directive"));
3840 create_unwind_entry (1);
3843 /* Parse an unwind_fnend directive. Generates the index table entry. */
3846 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3851 unsigned int marked_pr_dependency
;
3853 demand_empty_rest_of_line ();
3855 if (!unwind
.proc_start
)
3857 as_bad (_(".fnend directive without .fnstart"));
3861 /* Add eh table entry. */
3862 if (unwind
.table_entry
== NULL
)
3863 val
= create_unwind_entry (0);
3867 /* Add index table entry. This is two words. */
3868 start_unwind_section (unwind
.saved_seg
, 1);
3869 frag_align (2, 0, 0);
3870 record_alignment (now_seg
, 2);
3872 ptr
= frag_more (8);
3874 where
= frag_now_fix () - 8;
3876 /* Self relative offset of the function start. */
3877 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3878 BFD_RELOC_ARM_PREL31
);
3880 /* Indicate dependency on EHABI-defined personality routines to the
3881 linker, if it hasn't been done already. */
3882 marked_pr_dependency
3883 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3884 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3885 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3887 static const char *const name
[] =
3889 "__aeabi_unwind_cpp_pr0",
3890 "__aeabi_unwind_cpp_pr1",
3891 "__aeabi_unwind_cpp_pr2"
3893 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3894 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3895 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3896 |= 1 << unwind
.personality_index
;
3900 /* Inline exception table entry. */
3901 md_number_to_chars (ptr
+ 4, val
, 4);
3903 /* Self relative offset of the table entry. */
3904 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3905 BFD_RELOC_ARM_PREL31
);
3907 /* Restore the original section. */
3908 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3910 unwind
.proc_start
= NULL
;
3914 /* Parse an unwind_cantunwind directive. */
3917 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3919 demand_empty_rest_of_line ();
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("personality routine specified for cantunwind frame"));
3926 unwind
.personality_index
= -2;
3930 /* Parse a personalityindex directive. */
3933 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3937 if (!unwind
.proc_start
)
3938 as_bad (MISSING_FNSTART
);
3940 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3941 as_bad (_("duplicate .personalityindex directive"));
3945 if (exp
.X_op
!= O_constant
3946 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3948 as_bad (_("bad personality routine number"));
3949 ignore_rest_of_line ();
3953 unwind
.personality_index
= exp
.X_add_number
;
3955 demand_empty_rest_of_line ();
3959 /* Parse a personality directive. */
3962 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3966 if (!unwind
.proc_start
)
3967 as_bad (MISSING_FNSTART
);
3969 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3970 as_bad (_("duplicate .personality directive"));
3972 c
= get_symbol_name (& name
);
3973 p
= input_line_pointer
;
3975 ++ input_line_pointer
;
3976 unwind
.personality_routine
= symbol_find_or_make (name
);
3978 demand_empty_rest_of_line ();
3982 /* Parse a directive saving core registers. */
3985 s_arm_unwind_save_core (void)
3991 range
= parse_reg_list (&input_line_pointer
);
3994 as_bad (_("expected register list"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4001 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4002 into .unwind_save {..., sp...}. We aren't bothered about the value of
4003 ip because it is clobbered by calls. */
4004 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4005 && (range
& 0x3000) == 0x1000)
4007 unwind
.opcode_count
--;
4008 unwind
.sp_restored
= 0;
4009 range
= (range
| 0x2000) & ~0x1000;
4010 unwind
.pending_offset
= 0;
4016 /* See if we can use the short opcodes. These pop a block of up to 8
4017 registers starting with r4, plus maybe r14. */
4018 for (n
= 0; n
< 8; n
++)
4020 /* Break at the first non-saved register. */
4021 if ((range
& (1 << (n
+ 4))) == 0)
4024 /* See if there are any other bits set. */
4025 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4027 /* Use the long form. */
4028 op
= 0x8000 | ((range
>> 4) & 0xfff);
4029 add_unwind_opcode (op
, 2);
4033 /* Use the short form. */
4035 op
= 0xa8; /* Pop r14. */
4037 op
= 0xa0; /* Do not pop r14. */
4039 add_unwind_opcode (op
, 1);
4046 op
= 0xb100 | (range
& 0xf);
4047 add_unwind_opcode (op
, 2);
4050 /* Record the number of bytes pushed. */
4051 for (n
= 0; n
< 16; n
++)
4053 if (range
& (1 << n
))
4054 unwind
.frame_size
+= 4;
4059 /* Parse a directive saving FPA registers. */
4062 s_arm_unwind_save_fpa (int reg
)
4068 /* Get Number of registers to transfer. */
4069 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4072 exp
.X_op
= O_illegal
;
4074 if (exp
.X_op
!= O_constant
)
4076 as_bad (_("expected , <constant>"));
4077 ignore_rest_of_line ();
4081 num_regs
= exp
.X_add_number
;
4083 if (num_regs
< 1 || num_regs
> 4)
4085 as_bad (_("number of registers must be in the range [1:4]"));
4086 ignore_rest_of_line ();
4090 demand_empty_rest_of_line ();
4095 op
= 0xb4 | (num_regs
- 1);
4096 add_unwind_opcode (op
, 1);
4101 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4102 add_unwind_opcode (op
, 2);
4104 unwind
.frame_size
+= num_regs
* 12;
4108 /* Parse a directive saving VFP registers for ARMv6 and above. */
4111 s_arm_unwind_save_vfp_armv6 (void)
4116 int num_vfpv3_regs
= 0;
4117 int num_regs_below_16
;
4119 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4122 as_bad (_("expected register list"));
4123 ignore_rest_of_line ();
4127 demand_empty_rest_of_line ();
4129 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4130 than FSTMX/FLDMX-style ones). */
4132 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4134 num_vfpv3_regs
= count
;
4135 else if (start
+ count
> 16)
4136 num_vfpv3_regs
= start
+ count
- 16;
4138 if (num_vfpv3_regs
> 0)
4140 int start_offset
= start
> 16 ? start
- 16 : 0;
4141 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4142 add_unwind_opcode (op
, 2);
4145 /* Generate opcode for registers numbered in the range 0 .. 15. */
4146 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4147 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4148 if (num_regs_below_16
> 0)
4150 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4151 add_unwind_opcode (op
, 2);
4154 unwind
.frame_size
+= count
* 8;
4158 /* Parse a directive saving VFP registers for pre-ARMv6. */
4161 s_arm_unwind_save_vfp (void)
4167 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4170 as_bad (_("expected register list"));
4171 ignore_rest_of_line ();
4175 demand_empty_rest_of_line ();
4180 op
= 0xb8 | (count
- 1);
4181 add_unwind_opcode (op
, 1);
4186 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4187 add_unwind_opcode (op
, 2);
4189 unwind
.frame_size
+= count
* 8 + 4;
4193 /* Parse a directive saving iWMMXt data registers. */
4196 s_arm_unwind_save_mmxwr (void)
4204 if (*input_line_pointer
== '{')
4205 input_line_pointer
++;
4209 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4213 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4218 as_tsktsk (_("register list not in ascending order"));
4221 if (*input_line_pointer
== '-')
4223 input_line_pointer
++;
4224 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4227 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4230 else if (reg
>= hi_reg
)
4232 as_bad (_("bad register range"));
4235 for (; reg
< hi_reg
; reg
++)
4239 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4241 skip_past_char (&input_line_pointer
, '}');
4243 demand_empty_rest_of_line ();
4245 /* Generate any deferred opcodes because we're going to be looking at
4247 flush_pending_unwind ();
4249 for (i
= 0; i
< 16; i
++)
4251 if (mask
& (1 << i
))
4252 unwind
.frame_size
+= 8;
4255 /* Attempt to combine with a previous opcode. We do this because gcc
4256 likes to output separate unwind directives for a single block of
4258 if (unwind
.opcode_count
> 0)
4260 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4261 if ((i
& 0xf8) == 0xc0)
4264 /* Only merge if the blocks are contiguous. */
4267 if ((mask
& 0xfe00) == (1 << 9))
4269 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4270 unwind
.opcode_count
--;
4273 else if (i
== 6 && unwind
.opcode_count
>= 2)
4275 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4279 op
= 0xffff << (reg
- 1);
4281 && ((mask
& op
) == (1u << (reg
- 1))))
4283 op
= (1 << (reg
+ i
+ 1)) - 1;
4284 op
&= ~((1 << reg
) - 1);
4286 unwind
.opcode_count
-= 2;
4293 /* We want to generate opcodes in the order the registers have been
4294 saved, ie. descending order. */
4295 for (reg
= 15; reg
>= -1; reg
--)
4297 /* Save registers in blocks. */
4299 || !(mask
& (1 << reg
)))
4301 /* We found an unsaved reg. Generate opcodes to save the
4308 op
= 0xc0 | (hi_reg
- 10);
4309 add_unwind_opcode (op
, 1);
4314 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4315 add_unwind_opcode (op
, 2);
4324 ignore_rest_of_line ();
4328 s_arm_unwind_save_mmxwcg (void)
4335 if (*input_line_pointer
== '{')
4336 input_line_pointer
++;
4338 skip_whitespace (input_line_pointer
);
4342 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4346 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4352 as_tsktsk (_("register list not in ascending order"));
4355 if (*input_line_pointer
== '-')
4357 input_line_pointer
++;
4358 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4361 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4364 else if (reg
>= hi_reg
)
4366 as_bad (_("bad register range"));
4369 for (; reg
< hi_reg
; reg
++)
4373 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4375 skip_past_char (&input_line_pointer
, '}');
4377 demand_empty_rest_of_line ();
4379 /* Generate any deferred opcodes because we're going to be looking at
4381 flush_pending_unwind ();
4383 for (reg
= 0; reg
< 16; reg
++)
4385 if (mask
& (1 << reg
))
4386 unwind
.frame_size
+= 4;
4389 add_unwind_opcode (op
, 2);
4392 ignore_rest_of_line ();
4396 /* Parse an unwind_save directive.
4397 If the argument is non-zero, this is a .vsave directive. */
4400 s_arm_unwind_save (int arch_v6
)
4403 struct reg_entry
*reg
;
4404 bfd_boolean had_brace
= FALSE
;
4406 if (!unwind
.proc_start
)
4407 as_bad (MISSING_FNSTART
);
4409 /* Figure out what sort of save we have. */
4410 peek
= input_line_pointer
;
4418 reg
= arm_reg_parse_multi (&peek
);
4422 as_bad (_("register expected"));
4423 ignore_rest_of_line ();
4432 as_bad (_("FPA .unwind_save does not take a register list"));
4433 ignore_rest_of_line ();
4436 input_line_pointer
= peek
;
4437 s_arm_unwind_save_fpa (reg
->number
);
4441 s_arm_unwind_save_core ();
4446 s_arm_unwind_save_vfp_armv6 ();
4448 s_arm_unwind_save_vfp ();
4451 case REG_TYPE_MMXWR
:
4452 s_arm_unwind_save_mmxwr ();
4455 case REG_TYPE_MMXWCG
:
4456 s_arm_unwind_save_mmxwcg ();
4460 as_bad (_(".unwind_save does not support this kind of register"));
4461 ignore_rest_of_line ();
4466 /* Parse an unwind_movsp directive. */
4469 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4475 if (!unwind
.proc_start
)
4476 as_bad (MISSING_FNSTART
);
4478 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4481 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4482 ignore_rest_of_line ();
4486 /* Optional constant. */
4487 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4489 if (immediate_for_directive (&offset
) == FAIL
)
4495 demand_empty_rest_of_line ();
4497 if (reg
== REG_SP
|| reg
== REG_PC
)
4499 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4503 if (unwind
.fp_reg
!= REG_SP
)
4504 as_bad (_("unexpected .unwind_movsp directive"));
4506 /* Generate opcode to restore the value. */
4508 add_unwind_opcode (op
, 1);
4510 /* Record the information for later. */
4511 unwind
.fp_reg
= reg
;
4512 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4513 unwind
.sp_restored
= 1;
4516 /* Parse an unwind_pad directive. */
4519 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4523 if (!unwind
.proc_start
)
4524 as_bad (MISSING_FNSTART
);
4526 if (immediate_for_directive (&offset
) == FAIL
)
4531 as_bad (_("stack increment must be multiple of 4"));
4532 ignore_rest_of_line ();
4536 /* Don't generate any opcodes, just record the details for later. */
4537 unwind
.frame_size
+= offset
;
4538 unwind
.pending_offset
+= offset
;
4540 demand_empty_rest_of_line ();
4543 /* Parse an unwind_setfp directive. */
4546 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4552 if (!unwind
.proc_start
)
4553 as_bad (MISSING_FNSTART
);
4555 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4556 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4561 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4563 as_bad (_("expected <reg>, <reg>"));
4564 ignore_rest_of_line ();
4568 /* Optional constant. */
4569 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4571 if (immediate_for_directive (&offset
) == FAIL
)
4577 demand_empty_rest_of_line ();
4579 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4581 as_bad (_("register must be either sp or set by a previous"
4582 "unwind_movsp directive"));
4586 /* Don't generate any opcodes, just record the information for later. */
4587 unwind
.fp_reg
= fp_reg
;
4589 if (sp_reg
== REG_SP
)
4590 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4592 unwind
.fp_offset
-= offset
;
4595 /* Parse an unwind_raw directive. */
4598 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4601 /* This is an arbitrary limit. */
4602 unsigned char op
[16];
4605 if (!unwind
.proc_start
)
4606 as_bad (MISSING_FNSTART
);
4609 if (exp
.X_op
== O_constant
4610 && skip_past_comma (&input_line_pointer
) != FAIL
)
4612 unwind
.frame_size
+= exp
.X_add_number
;
4616 exp
.X_op
= O_illegal
;
4618 if (exp
.X_op
!= O_constant
)
4620 as_bad (_("expected <offset>, <opcode>"));
4621 ignore_rest_of_line ();
4627 /* Parse the opcode. */
4632 as_bad (_("unwind opcode too long"));
4633 ignore_rest_of_line ();
4635 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4637 as_bad (_("invalid unwind opcode"));
4638 ignore_rest_of_line ();
4641 op
[count
++] = exp
.X_add_number
;
4643 /* Parse the next byte. */
4644 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4650 /* Add the opcode bytes in reverse order. */
4652 add_unwind_opcode (op
[count
], 1);
4654 demand_empty_rest_of_line ();
4658 /* Parse a .eabi_attribute directive. */
4661 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4663 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4665 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4666 attributes_set_explicitly
[tag
] = 1;
4669 /* Emit a tls fix for the symbol. */
4672 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4676 #ifdef md_flush_pending_output
4677 md_flush_pending_output ();
4680 #ifdef md_cons_align
4684 /* Since we're just labelling the code, there's no need to define a
4687 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4688 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4689 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4690 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4692 #endif /* OBJ_ELF */
4694 static void s_arm_arch (int);
4695 static void s_arm_object_arch (int);
4696 static void s_arm_cpu (int);
4697 static void s_arm_fpu (int);
4698 static void s_arm_arch_extension (int);
4703 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4710 if (exp
.X_op
== O_symbol
)
4711 exp
.X_op
= O_secrel
;
4713 emit_expr (&exp
, 4);
4715 while (*input_line_pointer
++ == ',');
4717 input_line_pointer
--;
4718 demand_empty_rest_of_line ();
4722 /* This table describes all the machine specific pseudo-ops the assembler
4723 has to support. The fields are:
4724 pseudo-op name without dot
4725 function to call to execute this pseudo-op
4726 Integer arg to pass to the function. */
4728 const pseudo_typeS md_pseudo_table
[] =
4730 /* Never called because '.req' does not start a line. */
4731 { "req", s_req
, 0 },
4732 /* Following two are likewise never called. */
4735 { "unreq", s_unreq
, 0 },
4736 { "bss", s_bss
, 0 },
4737 { "align", s_align_ptwo
, 2 },
4738 { "arm", s_arm
, 0 },
4739 { "thumb", s_thumb
, 0 },
4740 { "code", s_code
, 0 },
4741 { "force_thumb", s_force_thumb
, 0 },
4742 { "thumb_func", s_thumb_func
, 0 },
4743 { "thumb_set", s_thumb_set
, 0 },
4744 { "even", s_even
, 0 },
4745 { "ltorg", s_ltorg
, 0 },
4746 { "pool", s_ltorg
, 0 },
4747 { "syntax", s_syntax
, 0 },
4748 { "cpu", s_arm_cpu
, 0 },
4749 { "arch", s_arm_arch
, 0 },
4750 { "object_arch", s_arm_object_arch
, 0 },
4751 { "fpu", s_arm_fpu
, 0 },
4752 { "arch_extension", s_arm_arch_extension
, 0 },
4754 { "word", s_arm_elf_cons
, 4 },
4755 { "long", s_arm_elf_cons
, 4 },
4756 { "inst.n", s_arm_elf_inst
, 2 },
4757 { "inst.w", s_arm_elf_inst
, 4 },
4758 { "inst", s_arm_elf_inst
, 0 },
4759 { "rel31", s_arm_rel31
, 0 },
4760 { "fnstart", s_arm_unwind_fnstart
, 0 },
4761 { "fnend", s_arm_unwind_fnend
, 0 },
4762 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4763 { "personality", s_arm_unwind_personality
, 0 },
4764 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4765 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4766 { "save", s_arm_unwind_save
, 0 },
4767 { "vsave", s_arm_unwind_save
, 1 },
4768 { "movsp", s_arm_unwind_movsp
, 0 },
4769 { "pad", s_arm_unwind_pad
, 0 },
4770 { "setfp", s_arm_unwind_setfp
, 0 },
4771 { "unwind_raw", s_arm_unwind_raw
, 0 },
4772 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4773 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4777 /* These are used for dwarf. */
4781 /* These are used for dwarf2. */
4782 { "file", dwarf2_directive_file
, 0 },
4783 { "loc", dwarf2_directive_loc
, 0 },
4784 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4786 { "extend", float_cons
, 'x' },
4787 { "ldouble", float_cons
, 'x' },
4788 { "packed", float_cons
, 'p' },
4790 {"secrel32", pe_directive_secrel
, 0},
4793 /* These are for compatibility with CodeComposer Studio. */
4794 {"ref", s_ccs_ref
, 0},
4795 {"def", s_ccs_def
, 0},
4796 {"asmfunc", s_ccs_asmfunc
, 0},
4797 {"endasmfunc", s_ccs_endasmfunc
, 0},
4802 /* Parser functions used exclusively in instruction operands. */
4804 /* Generic immediate-value read function for use in insn parsing.
4805 STR points to the beginning of the immediate (the leading #);
4806 VAL receives the value; if the value is outside [MIN, MAX]
4807 issue an error. PREFIX_OPT is true if the immediate prefix is
4811 parse_immediate (char **str
, int *val
, int min
, int max
,
4812 bfd_boolean prefix_opt
)
4816 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4817 if (exp
.X_op
!= O_constant
)
4819 inst
.error
= _("constant expression required");
4823 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4825 inst
.error
= _("immediate value out of range");
4829 *val
= exp
.X_add_number
;
4833 /* Less-generic immediate-value read function with the possibility of loading a
4834 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4835 instructions. Puts the result directly in inst.operands[i]. */
4838 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4839 bfd_boolean allow_symbol_p
)
4842 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4845 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4847 if (exp_p
->X_op
== O_constant
)
4849 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4850 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4851 O_constant. We have to be careful not to break compilation for
4852 32-bit X_add_number, though. */
4853 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4855 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4856 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4858 inst
.operands
[i
].regisimm
= 1;
4861 else if (exp_p
->X_op
== O_big
4862 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4864 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4866 /* Bignums have their least significant bits in
4867 generic_bignum[0]. Make sure we put 32 bits in imm and
4868 32 bits in reg, in a (hopefully) portable way. */
4869 gas_assert (parts
!= 0);
4871 /* Make sure that the number is not too big.
4872 PR 11972: Bignums can now be sign-extended to the
4873 size of a .octa so check that the out of range bits
4874 are all zero or all one. */
4875 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4877 LITTLENUM_TYPE m
= -1;
4879 if (generic_bignum
[parts
* 2] != 0
4880 && generic_bignum
[parts
* 2] != m
)
4883 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4884 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4888 inst
.operands
[i
].imm
= 0;
4889 for (j
= 0; j
< parts
; j
++, idx
++)
4890 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4891 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4892 inst
.operands
[i
].reg
= 0;
4893 for (j
= 0; j
< parts
; j
++, idx
++)
4894 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4895 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4896 inst
.operands
[i
].regisimm
= 1;
4898 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4906 /* Returns the pseudo-register number of an FPA immediate constant,
4907 or FAIL if there isn't a valid constant here. */
4910 parse_fpa_immediate (char ** str
)
4912 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4918 /* First try and match exact strings, this is to guarantee
4919 that some formats will work even for cross assembly. */
4921 for (i
= 0; fp_const
[i
]; i
++)
4923 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4927 *str
+= strlen (fp_const
[i
]);
4928 if (is_end_of_line
[(unsigned char) **str
])
4934 /* Just because we didn't get a match doesn't mean that the constant
4935 isn't valid, just that it is in a format that we don't
4936 automatically recognize. Try parsing it with the standard
4937 expression routines. */
4939 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4941 /* Look for a raw floating point number. */
4942 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4943 && is_end_of_line
[(unsigned char) *save_in
])
4945 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4947 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4949 if (words
[j
] != fp_values
[i
][j
])
4953 if (j
== MAX_LITTLENUMS
)
4961 /* Try and parse a more complex expression, this will probably fail
4962 unless the code uses a floating point prefix (eg "0f"). */
4963 save_in
= input_line_pointer
;
4964 input_line_pointer
= *str
;
4965 if (expression (&exp
) == absolute_section
4966 && exp
.X_op
== O_big
4967 && exp
.X_add_number
< 0)
4969 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4971 #define X_PRECISION 5
4972 #define E_PRECISION 15L
4973 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4975 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4977 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4979 if (words
[j
] != fp_values
[i
][j
])
4983 if (j
== MAX_LITTLENUMS
)
4985 *str
= input_line_pointer
;
4986 input_line_pointer
= save_in
;
4993 *str
= input_line_pointer
;
4994 input_line_pointer
= save_in
;
4995 inst
.error
= _("invalid FPA immediate expression");
4999 /* Returns 1 if a number has "quarter-precision" float format
5000 0baBbbbbbc defgh000 00000000 00000000. */
5003 is_quarter_float (unsigned imm
)
5005 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5006 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5010 /* Detect the presence of a floating point or integer zero constant,
5014 parse_ifimm_zero (char **in
)
5018 if (!is_immediate_prefix (**in
))
5020 /* In unified syntax, all prefixes are optional. */
5021 if (!unified_syntax
)
5027 /* Accept #0x0 as a synonym for #0. */
5028 if (strncmp (*in
, "0x", 2) == 0)
5031 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5036 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5037 &generic_floating_point_number
);
5040 && generic_floating_point_number
.sign
== '+'
5041 && (generic_floating_point_number
.low
5042 > generic_floating_point_number
.leader
))
5048 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5049 0baBbbbbbc defgh000 00000000 00000000.
5050 The zero and minus-zero cases need special handling, since they can't be
5051 encoded in the "quarter-precision" float format, but can nonetheless be
5052 loaded as integer constants. */
5055 parse_qfloat_immediate (char **ccp
, int *immed
)
5059 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5060 int found_fpchar
= 0;
5062 skip_past_char (&str
, '#');
5064 /* We must not accidentally parse an integer as a floating-point number. Make
5065 sure that the value we parse is not an integer by checking for special
5066 characters '.' or 'e'.
5067 FIXME: This is a horrible hack, but doing better is tricky because type
5068 information isn't in a very usable state at parse time. */
5070 skip_whitespace (fpnum
);
5072 if (strncmp (fpnum
, "0x", 2) == 0)
5076 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5077 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5087 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5089 unsigned fpword
= 0;
5092 /* Our FP word must be 32 bits (single-precision FP). */
5093 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5095 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5099 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5112 /* Shift operands. */
5115 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5118 struct asm_shift_name
5121 enum shift_kind kind
;
5124 /* Third argument to parse_shift. */
5125 enum parse_shift_mode
5127 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5128 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5129 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5130 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5131 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5134 /* Parse a <shift> specifier on an ARM data processing instruction.
5135 This has three forms:
5137 (LSL|LSR|ASL|ASR|ROR) Rs
5138 (LSL|LSR|ASL|ASR|ROR) #imm
5141 Note that ASL is assimilated to LSL in the instruction encoding, and
5142 RRX to ROR #0 (which cannot be written as such). */
5145 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5147 const struct asm_shift_name
*shift_name
;
5148 enum shift_kind shift
;
5153 for (p
= *str
; ISALPHA (*p
); p
++)
5158 inst
.error
= _("shift expression expected");
5162 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5165 if (shift_name
== NULL
)
5167 inst
.error
= _("shift expression expected");
5171 shift
= shift_name
->kind
;
5175 case NO_SHIFT_RESTRICT
:
5176 case SHIFT_IMMEDIATE
: break;
5178 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5179 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5181 inst
.error
= _("'LSL' or 'ASR' required");
5186 case SHIFT_LSL_IMMEDIATE
:
5187 if (shift
!= SHIFT_LSL
)
5189 inst
.error
= _("'LSL' required");
5194 case SHIFT_ASR_IMMEDIATE
:
5195 if (shift
!= SHIFT_ASR
)
5197 inst
.error
= _("'ASR' required");
5205 if (shift
!= SHIFT_RRX
)
5207 /* Whitespace can appear here if the next thing is a bare digit. */
5208 skip_whitespace (p
);
5210 if (mode
== NO_SHIFT_RESTRICT
5211 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5213 inst
.operands
[i
].imm
= reg
;
5214 inst
.operands
[i
].immisreg
= 1;
5216 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5219 inst
.operands
[i
].shift_kind
= shift
;
5220 inst
.operands
[i
].shifted
= 1;
5225 /* Parse a <shifter_operand> for an ARM data processing instruction:
5228 #<immediate>, <rotate>
5232 where <shift> is defined by parse_shift above, and <rotate> is a
5233 multiple of 2 between 0 and 30. Validation of immediate operands
5234 is deferred to md_apply_fix. */
5237 parse_shifter_operand (char **str
, int i
)
5242 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5244 inst
.operands
[i
].reg
= value
;
5245 inst
.operands
[i
].isreg
= 1;
5247 /* parse_shift will override this if appropriate */
5248 inst
.relocs
[0].exp
.X_op
= O_constant
;
5249 inst
.relocs
[0].exp
.X_add_number
= 0;
5251 if (skip_past_comma (str
) == FAIL
)
5254 /* Shift operation on register. */
5255 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5258 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5261 if (skip_past_comma (str
) == SUCCESS
)
5263 /* #x, y -- ie explicit rotation by Y. */
5264 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5267 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5269 inst
.error
= _("constant expression expected");
5273 value
= exp
.X_add_number
;
5274 if (value
< 0 || value
> 30 || value
% 2 != 0)
5276 inst
.error
= _("invalid rotation");
5279 if (inst
.relocs
[0].exp
.X_add_number
< 0
5280 || inst
.relocs
[0].exp
.X_add_number
> 255)
5282 inst
.error
= _("invalid constant");
5286 /* Encode as specified. */
5287 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5291 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5292 inst
.relocs
[0].pc_rel
= 0;
5296 /* Group relocation information. Each entry in the table contains the
5297 textual name of the relocation as may appear in assembler source
5298 and must end with a colon.
5299 Along with this textual name are the relocation codes to be used if
5300 the corresponding instruction is an ALU instruction (ADD or SUB only),
5301 an LDR, an LDRS, or an LDC. */
5303 struct group_reloc_table_entry
5314 /* Varieties of non-ALU group relocation. */
5321 static struct group_reloc_table_entry group_reloc_table
[] =
5322 { /* Program counter relative: */
5324 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5329 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5330 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5331 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5332 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5334 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5339 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5340 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5341 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5342 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5344 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5345 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5346 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5347 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5348 /* Section base relative */
5350 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5355 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5356 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5357 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5358 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5360 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5365 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5366 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5367 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5368 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5370 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5371 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5372 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5373 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5374 /* Absolute thumb alu relocations. */
5376 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5381 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5386 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5391 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5396 /* Given the address of a pointer pointing to the textual name of a group
5397 relocation as may appear in assembler source, attempt to find its details
5398 in group_reloc_table. The pointer will be updated to the character after
5399 the trailing colon. On failure, FAIL will be returned; SUCCESS
5400 otherwise. On success, *entry will be updated to point at the relevant
5401 group_reloc_table entry. */
5404 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5407 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5409 int length
= strlen (group_reloc_table
[i
].name
);
5411 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5412 && (*str
)[length
] == ':')
5414 *out
= &group_reloc_table
[i
];
5415 *str
+= (length
+ 1);
5423 /* Parse a <shifter_operand> for an ARM data processing instruction
5424 (as for parse_shifter_operand) where group relocations are allowed:
5427 #<immediate>, <rotate>
5428 #:<group_reloc>:<expression>
5432 where <group_reloc> is one of the strings defined in group_reloc_table.
5433 The hashes are optional.
5435 Everything else is as for parse_shifter_operand. */
5437 static parse_operand_result
5438 parse_shifter_operand_group_reloc (char **str
, int i
)
5440 /* Determine if we have the sequence of characters #: or just :
5441 coming next. If we do, then we check for a group relocation.
5442 If we don't, punt the whole lot to parse_shifter_operand. */
5444 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5445 || (*str
)[0] == ':')
5447 struct group_reloc_table_entry
*entry
;
5449 if ((*str
)[0] == '#')
5454 /* Try to parse a group relocation. Anything else is an error. */
5455 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5457 inst
.error
= _("unknown group relocation");
5458 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5461 /* We now have the group relocation table entry corresponding to
5462 the name in the assembler source. Next, we parse the expression. */
5463 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5464 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5466 /* Record the relocation type (always the ALU variant here). */
5467 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5468 gas_assert (inst
.relocs
[0].type
!= 0);
5470 return PARSE_OPERAND_SUCCESS
;
5473 return parse_shifter_operand (str
, i
) == SUCCESS
5474 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5476 /* Never reached. */
5479 /* Parse a Neon alignment expression. Information is written to
5480 inst.operands[i]. We assume the initial ':' has been skipped.
5482 align .imm = align << 8, .immisalign=1, .preind=0 */
5483 static parse_operand_result
5484 parse_neon_alignment (char **str
, int i
)
5489 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5491 if (exp
.X_op
!= O_constant
)
5493 inst
.error
= _("alignment must be constant");
5494 return PARSE_OPERAND_FAIL
;
5497 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5498 inst
.operands
[i
].immisalign
= 1;
5499 /* Alignments are not pre-indexes. */
5500 inst
.operands
[i
].preind
= 0;
5503 return PARSE_OPERAND_SUCCESS
;
5506 /* Parse all forms of an ARM address expression. Information is written
5507 to inst.operands[i] and/or inst.relocs[0].
5509 Preindexed addressing (.preind=1):
5511 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5512 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5513 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5514 .shift_kind=shift .relocs[0].exp=shift_imm
5516 These three may have a trailing ! which causes .writeback to be set also.
5518 Postindexed addressing (.postind=1, .writeback=1):
5520 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5521 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5522 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5523 .shift_kind=shift .relocs[0].exp=shift_imm
5525 Unindexed addressing (.preind=0, .postind=0):
5527 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5531 [Rn]{!} shorthand for [Rn,#0]{!}
5532 =immediate .isreg=0 .relocs[0].exp=immediate
5533 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5535 It is the caller's responsibility to check for addressing modes not
5536 supported by the instruction, and to set inst.relocs[0].type. */
5538 static parse_operand_result
5539 parse_address_main (char **str
, int i
, int group_relocations
,
5540 group_reloc_type group_type
)
5545 if (skip_past_char (&p
, '[') == FAIL
)
5547 if (skip_past_char (&p
, '=') == FAIL
)
5549 /* Bare address - translate to PC-relative offset. */
5550 inst
.relocs
[0].pc_rel
= 1;
5551 inst
.operands
[i
].reg
= REG_PC
;
5552 inst
.operands
[i
].isreg
= 1;
5553 inst
.operands
[i
].preind
= 1;
5555 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5556 return PARSE_OPERAND_FAIL
;
5558 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5559 /*allow_symbol_p=*/TRUE
))
5560 return PARSE_OPERAND_FAIL
;
5563 return PARSE_OPERAND_SUCCESS
;
5566 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5567 skip_whitespace (p
);
5569 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5571 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5572 return PARSE_OPERAND_FAIL
;
5574 inst
.operands
[i
].reg
= reg
;
5575 inst
.operands
[i
].isreg
= 1;
5577 if (skip_past_comma (&p
) == SUCCESS
)
5579 inst
.operands
[i
].preind
= 1;
5582 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5584 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5586 inst
.operands
[i
].imm
= reg
;
5587 inst
.operands
[i
].immisreg
= 1;
5589 if (skip_past_comma (&p
) == SUCCESS
)
5590 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5591 return PARSE_OPERAND_FAIL
;
5593 else if (skip_past_char (&p
, ':') == SUCCESS
)
5595 /* FIXME: '@' should be used here, but it's filtered out by generic
5596 code before we get to see it here. This may be subject to
5598 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5600 if (result
!= PARSE_OPERAND_SUCCESS
)
5605 if (inst
.operands
[i
].negative
)
5607 inst
.operands
[i
].negative
= 0;
5611 if (group_relocations
5612 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5614 struct group_reloc_table_entry
*entry
;
5616 /* Skip over the #: or : sequence. */
5622 /* Try to parse a group relocation. Anything else is an
5624 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5626 inst
.error
= _("unknown group relocation");
5627 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5630 /* We now have the group relocation table entry corresponding to
5631 the name in the assembler source. Next, we parse the
5633 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5634 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5636 /* Record the relocation type. */
5641 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5646 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5651 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5658 if (inst
.relocs
[0].type
== 0)
5660 inst
.error
= _("this group relocation is not allowed on this instruction");
5661 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5668 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5669 return PARSE_OPERAND_FAIL
;
5670 /* If the offset is 0, find out if it's a +0 or -0. */
5671 if (inst
.relocs
[0].exp
.X_op
== O_constant
5672 && inst
.relocs
[0].exp
.X_add_number
== 0)
5674 skip_whitespace (q
);
5678 skip_whitespace (q
);
5681 inst
.operands
[i
].negative
= 1;
5686 else if (skip_past_char (&p
, ':') == SUCCESS
)
5688 /* FIXME: '@' should be used here, but it's filtered out by generic code
5689 before we get to see it here. This may be subject to change. */
5690 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5692 if (result
!= PARSE_OPERAND_SUCCESS
)
5696 if (skip_past_char (&p
, ']') == FAIL
)
5698 inst
.error
= _("']' expected");
5699 return PARSE_OPERAND_FAIL
;
5702 if (skip_past_char (&p
, '!') == SUCCESS
)
5703 inst
.operands
[i
].writeback
= 1;
5705 else if (skip_past_comma (&p
) == SUCCESS
)
5707 if (skip_past_char (&p
, '{') == SUCCESS
)
5709 /* [Rn], {expr} - unindexed, with option */
5710 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5711 0, 255, TRUE
) == FAIL
)
5712 return PARSE_OPERAND_FAIL
;
5714 if (skip_past_char (&p
, '}') == FAIL
)
5716 inst
.error
= _("'}' expected at end of 'option' field");
5717 return PARSE_OPERAND_FAIL
;
5719 if (inst
.operands
[i
].preind
)
5721 inst
.error
= _("cannot combine index with option");
5722 return PARSE_OPERAND_FAIL
;
5725 return PARSE_OPERAND_SUCCESS
;
5729 inst
.operands
[i
].postind
= 1;
5730 inst
.operands
[i
].writeback
= 1;
5732 if (inst
.operands
[i
].preind
)
5734 inst
.error
= _("cannot combine pre- and post-indexing");
5735 return PARSE_OPERAND_FAIL
;
5739 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5741 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5743 /* We might be using the immediate for alignment already. If we
5744 are, OR the register number into the low-order bits. */
5745 if (inst
.operands
[i
].immisalign
)
5746 inst
.operands
[i
].imm
|= reg
;
5748 inst
.operands
[i
].imm
= reg
;
5749 inst
.operands
[i
].immisreg
= 1;
5751 if (skip_past_comma (&p
) == SUCCESS
)
5752 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5753 return PARSE_OPERAND_FAIL
;
5759 if (inst
.operands
[i
].negative
)
5761 inst
.operands
[i
].negative
= 0;
5764 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5765 return PARSE_OPERAND_FAIL
;
5766 /* If the offset is 0, find out if it's a +0 or -0. */
5767 if (inst
.relocs
[0].exp
.X_op
== O_constant
5768 && inst
.relocs
[0].exp
.X_add_number
== 0)
5770 skip_whitespace (q
);
5774 skip_whitespace (q
);
5777 inst
.operands
[i
].negative
= 1;
5783 /* If at this point neither .preind nor .postind is set, we have a
5784 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5785 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5787 inst
.operands
[i
].preind
= 1;
5788 inst
.relocs
[0].exp
.X_op
= O_constant
;
5789 inst
.relocs
[0].exp
.X_add_number
= 0;
5792 return PARSE_OPERAND_SUCCESS
;
5796 parse_address (char **str
, int i
)
5798 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5802 static parse_operand_result
5803 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5805 return parse_address_main (str
, i
, 1, type
);
5808 /* Parse an operand for a MOVW or MOVT instruction. */
5810 parse_half (char **str
)
5815 skip_past_char (&p
, '#');
5816 if (strncasecmp (p
, ":lower16:", 9) == 0)
5817 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
5818 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5819 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
5821 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
5824 skip_whitespace (p
);
5827 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5830 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
5832 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
5834 inst
.error
= _("constant expression expected");
5837 if (inst
.relocs
[0].exp
.X_add_number
< 0
5838 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
5840 inst
.error
= _("immediate value out of range");
5848 /* Miscellaneous. */
5850 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5851 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5853 parse_psr (char **str
, bfd_boolean lhs
)
5856 unsigned long psr_field
;
5857 const struct asm_psr
*psr
;
5859 bfd_boolean is_apsr
= FALSE
;
5860 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5862 /* PR gas/12698: If the user has specified -march=all then m_profile will
5863 be TRUE, but we want to ignore it in this case as we are building for any
5864 CPU type, including non-m variants. */
5865 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5868 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5869 feature for ease of use and backwards compatibility. */
5871 if (strncasecmp (p
, "SPSR", 4) == 0)
5874 goto unsupported_psr
;
5876 psr_field
= SPSR_BIT
;
5878 else if (strncasecmp (p
, "CPSR", 4) == 0)
5881 goto unsupported_psr
;
5885 else if (strncasecmp (p
, "APSR", 4) == 0)
5887 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5888 and ARMv7-R architecture CPUs. */
5897 while (ISALNUM (*p
) || *p
== '_');
5899 if (strncasecmp (start
, "iapsr", 5) == 0
5900 || strncasecmp (start
, "eapsr", 5) == 0
5901 || strncasecmp (start
, "xpsr", 4) == 0
5902 || strncasecmp (start
, "psr", 3) == 0)
5903 p
= start
+ strcspn (start
, "rR") + 1;
5905 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5911 /* If APSR is being written, a bitfield may be specified. Note that
5912 APSR itself is handled above. */
5913 if (psr
->field
<= 3)
5915 psr_field
= psr
->field
;
5921 /* M-profile MSR instructions have the mask field set to "10", except
5922 *PSR variants which modify APSR, which may use a different mask (and
5923 have been handled already). Do that by setting the PSR_f field
5925 return psr
->field
| (lhs
? PSR_f
: 0);
5928 goto unsupported_psr
;
5934 /* A suffix follows. */
5940 while (ISALNUM (*p
) || *p
== '_');
5944 /* APSR uses a notation for bits, rather than fields. */
5945 unsigned int nzcvq_bits
= 0;
5946 unsigned int g_bit
= 0;
5949 for (bit
= start
; bit
!= p
; bit
++)
5951 switch (TOLOWER (*bit
))
5954 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5958 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5962 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5966 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5970 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5974 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5978 inst
.error
= _("unexpected bit specified after APSR");
5983 if (nzcvq_bits
== 0x1f)
5988 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5990 inst
.error
= _("selected processor does not "
5991 "support DSP extension");
5998 if ((nzcvq_bits
& 0x20) != 0
5999 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6000 || (g_bit
& 0x2) != 0)
6002 inst
.error
= _("bad bitmask specified after APSR");
6008 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6013 psr_field
|= psr
->field
;
6019 goto error
; /* Garbage after "[CS]PSR". */
6021 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6022 is deprecated, but allow it anyway. */
6026 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6029 else if (!m_profile
)
6030 /* These bits are never right for M-profile devices: don't set them
6031 (only code paths which read/write APSR reach here). */
6032 psr_field
|= (PSR_c
| PSR_f
);
6038 inst
.error
= _("selected processor does not support requested special "
6039 "purpose register");
6043 inst
.error
= _("flag for {c}psr instruction expected");
6047 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6048 value suitable for splatting into the AIF field of the instruction. */
6051 parse_cps_flags (char **str
)
6060 case '\0': case ',':
6063 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6064 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6065 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6068 inst
.error
= _("unrecognized CPS flag");
6073 if (saw_a_flag
== 0)
6075 inst
.error
= _("missing CPS flags");
6083 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6084 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6087 parse_endian_specifier (char **str
)
6092 if (strncasecmp (s
, "BE", 2))
6094 else if (strncasecmp (s
, "LE", 2))
6098 inst
.error
= _("valid endian specifiers are be or le");
6102 if (ISALNUM (s
[2]) || s
[2] == '_')
6104 inst
.error
= _("valid endian specifiers are be or le");
6109 return little_endian
;
6112 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6113 value suitable for poking into the rotate field of an sxt or sxta
6114 instruction, or FAIL on error. */
6117 parse_ror (char **str
)
6122 if (strncasecmp (s
, "ROR", 3) == 0)
6126 inst
.error
= _("missing rotation field after comma");
6130 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6135 case 0: *str
= s
; return 0x0;
6136 case 8: *str
= s
; return 0x1;
6137 case 16: *str
= s
; return 0x2;
6138 case 24: *str
= s
; return 0x3;
6141 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6146 /* Parse a conditional code (from conds[] below). The value returned is in the
6147 range 0 .. 14, or FAIL. */
6149 parse_cond (char **str
)
6152 const struct asm_cond
*c
;
6154 /* Condition codes are always 2 characters, so matching up to
6155 3 characters is sufficient. */
6160 while (ISALPHA (*q
) && n
< 3)
6162 cond
[n
] = TOLOWER (*q
);
6167 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6170 inst
.error
= _("condition required");
6178 /* Record a use of the given feature. */
6180 record_feature_use (const arm_feature_set
*feature
)
6183 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6185 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6188 /* If the given feature is currently allowed, mark it as used and return TRUE.
6189 Return FALSE otherwise. */
6191 mark_feature_used (const arm_feature_set
*feature
)
6193 /* Ensure the option is currently allowed. */
6194 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6197 /* Add the appropriate architecture feature for the barrier option used. */
6198 record_feature_use (feature
);
6203 /* Parse an option for a barrier instruction. Returns the encoding for the
6206 parse_barrier (char **str
)
6209 const struct asm_barrier_opt
*o
;
6212 while (ISALPHA (*q
))
6215 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6220 if (!mark_feature_used (&o
->arch
))
6227 /* Parse the operands of a table branch instruction. Similar to a memory
6230 parse_tb (char **str
)
6235 if (skip_past_char (&p
, '[') == FAIL
)
6237 inst
.error
= _("'[' expected");
6241 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6243 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6246 inst
.operands
[0].reg
= reg
;
6248 if (skip_past_comma (&p
) == FAIL
)
6250 inst
.error
= _("',' expected");
6254 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6256 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6259 inst
.operands
[0].imm
= reg
;
6261 if (skip_past_comma (&p
) == SUCCESS
)
6263 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6265 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6267 inst
.error
= _("invalid shift");
6270 inst
.operands
[0].shifted
= 1;
6273 if (skip_past_char (&p
, ']') == FAIL
)
6275 inst
.error
= _("']' expected");
6282 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6283 information on the types the operands can take and how they are encoded.
6284 Up to four operands may be read; this function handles setting the
6285 ".present" field for each read operand itself.
6286 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6287 else returns FAIL. */
6290 parse_neon_mov (char **str
, int *which_operand
)
6292 int i
= *which_operand
, val
;
6293 enum arm_reg_type rtype
;
6295 struct neon_type_el optype
;
6297 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6299 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6300 inst
.operands
[i
].reg
= val
;
6301 inst
.operands
[i
].isscalar
= 1;
6302 inst
.operands
[i
].vectype
= optype
;
6303 inst
.operands
[i
++].present
= 1;
6305 if (skip_past_comma (&ptr
) == FAIL
)
6308 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].present
= 1;
6315 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6318 /* Cases 0, 1, 2, 3, 5 (D only). */
6319 if (skip_past_comma (&ptr
) == FAIL
)
6322 inst
.operands
[i
].reg
= val
;
6323 inst
.operands
[i
].isreg
= 1;
6324 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6325 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6326 inst
.operands
[i
].isvec
= 1;
6327 inst
.operands
[i
].vectype
= optype
;
6328 inst
.operands
[i
++].present
= 1;
6330 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6332 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6333 Case 13: VMOV <Sd>, <Rm> */
6334 inst
.operands
[i
].reg
= val
;
6335 inst
.operands
[i
].isreg
= 1;
6336 inst
.operands
[i
].present
= 1;
6338 if (rtype
== REG_TYPE_NQ
)
6340 first_error (_("can't use Neon quad register here"));
6343 else if (rtype
!= REG_TYPE_VFS
)
6346 if (skip_past_comma (&ptr
) == FAIL
)
6348 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6350 inst
.operands
[i
].reg
= val
;
6351 inst
.operands
[i
].isreg
= 1;
6352 inst
.operands
[i
].present
= 1;
6355 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6358 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6359 Case 1: VMOV<c><q> <Dd>, <Dm>
6360 Case 8: VMOV.F32 <Sd>, <Sm>
6361 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6363 inst
.operands
[i
].reg
= val
;
6364 inst
.operands
[i
].isreg
= 1;
6365 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6366 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].vectype
= optype
;
6369 inst
.operands
[i
].present
= 1;
6371 if (skip_past_comma (&ptr
) == SUCCESS
)
6376 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6379 inst
.operands
[i
].reg
= val
;
6380 inst
.operands
[i
].isreg
= 1;
6381 inst
.operands
[i
++].present
= 1;
6383 if (skip_past_comma (&ptr
) == FAIL
)
6386 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6389 inst
.operands
[i
].reg
= val
;
6390 inst
.operands
[i
].isreg
= 1;
6391 inst
.operands
[i
].present
= 1;
6394 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6395 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6396 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6397 Case 10: VMOV.F32 <Sd>, #<imm>
6398 Case 11: VMOV.F64 <Dd>, #<imm> */
6399 inst
.operands
[i
].immisfloat
= 1;
6400 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6402 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6403 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6407 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6411 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6414 inst
.operands
[i
].reg
= val
;
6415 inst
.operands
[i
].isreg
= 1;
6416 inst
.operands
[i
++].present
= 1;
6418 if (skip_past_comma (&ptr
) == FAIL
)
6421 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6423 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6424 inst
.operands
[i
].reg
= val
;
6425 inst
.operands
[i
].isscalar
= 1;
6426 inst
.operands
[i
].present
= 1;
6427 inst
.operands
[i
].vectype
= optype
;
6429 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6431 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6432 inst
.operands
[i
].reg
= val
;
6433 inst
.operands
[i
].isreg
= 1;
6434 inst
.operands
[i
++].present
= 1;
6436 if (skip_past_comma (&ptr
) == FAIL
)
6439 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6442 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6446 inst
.operands
[i
].reg
= val
;
6447 inst
.operands
[i
].isreg
= 1;
6448 inst
.operands
[i
].isvec
= 1;
6449 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6450 inst
.operands
[i
].vectype
= optype
;
6451 inst
.operands
[i
].present
= 1;
6453 if (rtype
== REG_TYPE_VFS
)
6457 if (skip_past_comma (&ptr
) == FAIL
)
6459 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6462 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6465 inst
.operands
[i
].reg
= val
;
6466 inst
.operands
[i
].isreg
= 1;
6467 inst
.operands
[i
].isvec
= 1;
6468 inst
.operands
[i
].issingle
= 1;
6469 inst
.operands
[i
].vectype
= optype
;
6470 inst
.operands
[i
].present
= 1;
6473 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6477 inst
.operands
[i
].reg
= val
;
6478 inst
.operands
[i
].isreg
= 1;
6479 inst
.operands
[i
].isvec
= 1;
6480 inst
.operands
[i
].issingle
= 1;
6481 inst
.operands
[i
].vectype
= optype
;
6482 inst
.operands
[i
].present
= 1;
6487 first_error (_("parse error"));
6491 /* Successfully parsed the operands. Update args. */
6497 first_error (_("expected comma"));
6501 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6505 /* Use this macro when the operand constraints are different
6506 for ARM and THUMB (e.g. ldrd). */
6507 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6508 ((arm_operand) | ((thumb_operand) << 16))
6510 /* Matcher codes for parse_operands. */
6511 enum operand_parse_code
6513 OP_stop
, /* end of line */
6515 OP_RR
, /* ARM register */
6516 OP_RRnpc
, /* ARM register, not r15 */
6517 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6518 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6519 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6520 optional trailing ! */
6521 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6522 OP_RCP
, /* Coprocessor number */
6523 OP_RCN
, /* Coprocessor register */
6524 OP_RF
, /* FPA register */
6525 OP_RVS
, /* VFP single precision register */
6526 OP_RVD
, /* VFP double precision register (0..15) */
6527 OP_RND
, /* Neon double precision register (0..31) */
6528 OP_RNQ
, /* Neon quad precision register */
6529 OP_RVSD
, /* VFP single or double precision register */
6530 OP_RNSD
, /* Neon single or double precision register */
6531 OP_RNDQ
, /* Neon double or quad precision register */
6532 OP_RNSDQ
, /* Neon single, double or quad precision register */
6533 OP_RNSC
, /* Neon scalar D[X] */
6534 OP_RVC
, /* VFP control register */
6535 OP_RMF
, /* Maverick F register */
6536 OP_RMD
, /* Maverick D register */
6537 OP_RMFX
, /* Maverick FX register */
6538 OP_RMDX
, /* Maverick DX register */
6539 OP_RMAX
, /* Maverick AX register */
6540 OP_RMDS
, /* Maverick DSPSC register */
6541 OP_RIWR
, /* iWMMXt wR register */
6542 OP_RIWC
, /* iWMMXt wC register */
6543 OP_RIWG
, /* iWMMXt wCG register */
6544 OP_RXA
, /* XScale accumulator register */
6546 OP_REGLST
, /* ARM register list */
6547 OP_VRSLST
, /* VFP single-precision register list */
6548 OP_VRDLST
, /* VFP double-precision register list */
6549 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6550 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6551 OP_NSTRLST
, /* Neon element/structure list */
6553 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6554 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6555 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6556 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6557 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6558 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6559 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6560 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6561 OP_VMOV
, /* Neon VMOV operands. */
6562 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6563 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6564 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6566 OP_I0
, /* immediate zero */
6567 OP_I7
, /* immediate value 0 .. 7 */
6568 OP_I15
, /* 0 .. 15 */
6569 OP_I16
, /* 1 .. 16 */
6570 OP_I16z
, /* 0 .. 16 */
6571 OP_I31
, /* 0 .. 31 */
6572 OP_I31w
, /* 0 .. 31, optional trailing ! */
6573 OP_I32
, /* 1 .. 32 */
6574 OP_I32z
, /* 0 .. 32 */
6575 OP_I63
, /* 0 .. 63 */
6576 OP_I63s
, /* -64 .. 63 */
6577 OP_I64
, /* 1 .. 64 */
6578 OP_I64z
, /* 0 .. 64 */
6579 OP_I255
, /* 0 .. 255 */
6581 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6582 OP_I7b
, /* 0 .. 7 */
6583 OP_I15b
, /* 0 .. 15 */
6584 OP_I31b
, /* 0 .. 31 */
6586 OP_SH
, /* shifter operand */
6587 OP_SHG
, /* shifter operand with possible group relocation */
6588 OP_ADDR
, /* Memory address expression (any mode) */
6589 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6590 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6591 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6592 OP_EXP
, /* arbitrary expression */
6593 OP_EXPi
, /* same, with optional immediate prefix */
6594 OP_EXPr
, /* same, with optional relocation suffix */
6595 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6596 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6597 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6598 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6600 OP_CPSF
, /* CPS flags */
6601 OP_ENDI
, /* Endianness specifier */
6602 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6603 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6604 OP_COND
, /* conditional code */
6605 OP_TB
, /* Table branch. */
6607 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6609 OP_RRnpc_I0
, /* ARM register or literal 0 */
6610 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6611 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6612 OP_RF_IF
, /* FPA register or immediate */
6613 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6614 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6616 /* Optional operands. */
6617 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6618 OP_oI31b
, /* 0 .. 31 */
6619 OP_oI32b
, /* 1 .. 32 */
6620 OP_oI32z
, /* 0 .. 32 */
6621 OP_oIffffb
, /* 0 .. 65535 */
6622 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6624 OP_oRR
, /* ARM register */
6625 OP_oRRnpc
, /* ARM register, not the PC */
6626 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6627 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6628 OP_oRND
, /* Optional Neon double precision register */
6629 OP_oRNQ
, /* Optional Neon quad precision register */
6630 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6631 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6632 OP_oSHll
, /* LSL immediate */
6633 OP_oSHar
, /* ASR immediate */
6634 OP_oSHllar
, /* LSL or ASR immediate */
6635 OP_oROR
, /* ROR 0/8/16/24 */
6636 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6638 /* Some pre-defined mixed (ARM/THUMB) operands. */
6639 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6640 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6641 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6643 OP_FIRST_OPTIONAL
= OP_oI7b
6646 /* Generic instruction operand parser. This does no encoding and no
6647 semantic validation; it merely squirrels values away in the inst
6648 structure. Returns SUCCESS or FAIL depending on whether the
6649 specified grammar matched. */
6651 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6653 unsigned const int *upat
= pattern
;
6654 char *backtrack_pos
= 0;
6655 const char *backtrack_error
= 0;
6656 int i
, val
= 0, backtrack_index
= 0;
6657 enum arm_reg_type rtype
;
6658 parse_operand_result result
;
6659 unsigned int op_parse_code
;
6661 #define po_char_or_fail(chr) \
6664 if (skip_past_char (&str, chr) == FAIL) \
6669 #define po_reg_or_fail(regtype) \
6672 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6673 & inst.operands[i].vectype); \
6676 first_error (_(reg_expected_msgs[regtype])); \
6679 inst.operands[i].reg = val; \
6680 inst.operands[i].isreg = 1; \
6681 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6682 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6683 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6684 || rtype == REG_TYPE_VFD \
6685 || rtype == REG_TYPE_NQ); \
6689 #define po_reg_or_goto(regtype, label) \
6692 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6693 & inst.operands[i].vectype); \
6697 inst.operands[i].reg = val; \
6698 inst.operands[i].isreg = 1; \
6699 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6700 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6701 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6702 || rtype == REG_TYPE_VFD \
6703 || rtype == REG_TYPE_NQ); \
6707 #define po_imm_or_fail(min, max, popt) \
6710 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6712 inst.operands[i].imm = val; \
6716 #define po_scalar_or_goto(elsz, label) \
6719 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6722 inst.operands[i].reg = val; \
6723 inst.operands[i].isscalar = 1; \
6727 #define po_misc_or_fail(expr) \
6735 #define po_misc_or_fail_no_backtrack(expr) \
6739 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6740 backtrack_pos = 0; \
6741 if (result != PARSE_OPERAND_SUCCESS) \
6746 #define po_barrier_or_imm(str) \
6749 val = parse_barrier (&str); \
6750 if (val == FAIL && ! ISALPHA (*str)) \
6753 /* ISB can only take SY as an option. */ \
6754 || ((inst.instruction & 0xf0) == 0x60 \
6757 inst.error = _("invalid barrier type"); \
6758 backtrack_pos = 0; \
6764 skip_whitespace (str
);
6766 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6768 op_parse_code
= upat
[i
];
6769 if (op_parse_code
>= 1<<16)
6770 op_parse_code
= thumb
? (op_parse_code
>> 16)
6771 : (op_parse_code
& ((1<<16)-1));
6773 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6775 /* Remember where we are in case we need to backtrack. */
6776 gas_assert (!backtrack_pos
);
6777 backtrack_pos
= str
;
6778 backtrack_error
= inst
.error
;
6779 backtrack_index
= i
;
6782 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6783 po_char_or_fail (',');
6785 switch (op_parse_code
)
6793 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6794 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6795 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6796 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6797 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6798 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6800 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6802 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6804 /* Also accept generic coprocessor regs for unknown registers. */
6806 po_reg_or_fail (REG_TYPE_CN
);
6808 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6809 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6810 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6811 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6812 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6813 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6814 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6815 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6816 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6817 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6819 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6820 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6822 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6823 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6825 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6827 /* Neon scalar. Using an element size of 8 means that some invalid
6828 scalars are accepted here, so deal with those in later code. */
6829 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6833 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6836 po_imm_or_fail (0, 0, TRUE
);
6841 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6846 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6849 if (parse_ifimm_zero (&str
))
6850 inst
.operands
[i
].imm
= 0;
6854 = _("only floating point zero is allowed as immediate value");
6862 po_scalar_or_goto (8, try_rr
);
6865 po_reg_or_fail (REG_TYPE_RN
);
6871 po_scalar_or_goto (8, try_nsdq
);
6874 po_reg_or_fail (REG_TYPE_NSDQ
);
6880 po_scalar_or_goto (8, try_s_scalar
);
6883 po_scalar_or_goto (4, try_nsd
);
6886 po_reg_or_fail (REG_TYPE_NSD
);
6892 po_scalar_or_goto (8, try_ndq
);
6895 po_reg_or_fail (REG_TYPE_NDQ
);
6901 po_scalar_or_goto (8, try_vfd
);
6904 po_reg_or_fail (REG_TYPE_VFD
);
6909 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6910 not careful then bad things might happen. */
6911 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6916 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6919 /* There's a possibility of getting a 64-bit immediate here, so
6920 we need special handling. */
6921 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6924 inst
.error
= _("immediate value is out of range");
6932 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6935 po_imm_or_fail (0, 63, TRUE
);
6940 po_char_or_fail ('[');
6941 po_reg_or_fail (REG_TYPE_RN
);
6942 po_char_or_fail (']');
6948 po_reg_or_fail (REG_TYPE_RN
);
6949 if (skip_past_char (&str
, '!') == SUCCESS
)
6950 inst
.operands
[i
].writeback
= 1;
6954 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6955 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6956 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6957 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6958 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6959 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6960 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6961 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6962 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6963 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6964 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6965 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6967 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6969 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6970 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6972 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6973 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6974 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6975 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6977 /* Immediate variants */
6979 po_char_or_fail ('{');
6980 po_imm_or_fail (0, 255, TRUE
);
6981 po_char_or_fail ('}');
6985 /* The expression parser chokes on a trailing !, so we have
6986 to find it first and zap it. */
6989 while (*s
&& *s
!= ',')
6994 inst
.operands
[i
].writeback
= 1;
6996 po_imm_or_fail (0, 31, TRUE
);
7004 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7009 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7014 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7016 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7018 val
= parse_reloc (&str
);
7021 inst
.error
= _("unrecognized relocation suffix");
7024 else if (val
!= BFD_RELOC_UNUSED
)
7026 inst
.operands
[i
].imm
= val
;
7027 inst
.operands
[i
].hasreloc
= 1;
7033 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7035 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7037 inst
.operands
[i
].hasreloc
= 1;
7039 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7041 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7042 inst
.operands
[i
].hasreloc
= 0;
7046 /* Operand for MOVW or MOVT. */
7048 po_misc_or_fail (parse_half (&str
));
7051 /* Register or expression. */
7052 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7053 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7055 /* Register or immediate. */
7056 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7057 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7059 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7061 if (!is_immediate_prefix (*str
))
7064 val
= parse_fpa_immediate (&str
);
7067 /* FPA immediates are encoded as registers 8-15.
7068 parse_fpa_immediate has already applied the offset. */
7069 inst
.operands
[i
].reg
= val
;
7070 inst
.operands
[i
].isreg
= 1;
7073 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7074 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7076 /* Two kinds of register. */
7079 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7081 || (rege
->type
!= REG_TYPE_MMXWR
7082 && rege
->type
!= REG_TYPE_MMXWC
7083 && rege
->type
!= REG_TYPE_MMXWCG
))
7085 inst
.error
= _("iWMMXt data or control register expected");
7088 inst
.operands
[i
].reg
= rege
->number
;
7089 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7095 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7097 || (rege
->type
!= REG_TYPE_MMXWC
7098 && rege
->type
!= REG_TYPE_MMXWCG
))
7100 inst
.error
= _("iWMMXt control register expected");
7103 inst
.operands
[i
].reg
= rege
->number
;
7104 inst
.operands
[i
].isreg
= 1;
7109 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7110 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7111 case OP_oROR
: val
= parse_ror (&str
); break;
7112 case OP_COND
: val
= parse_cond (&str
); break;
7113 case OP_oBARRIER_I15
:
7114 po_barrier_or_imm (str
); break;
7116 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7122 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7123 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7125 inst
.error
= _("Banked registers are not available with this "
7131 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7135 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7138 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7140 if (strncasecmp (str
, "APSR_", 5) == 0)
7147 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7148 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7149 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7150 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7151 default: found
= 16;
7155 inst
.operands
[i
].isvec
= 1;
7156 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7157 inst
.operands
[i
].reg
= REG_PC
;
7164 po_misc_or_fail (parse_tb (&str
));
7167 /* Register lists. */
7169 val
= parse_reg_list (&str
);
7172 inst
.operands
[i
].writeback
= 1;
7178 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7182 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7186 /* Allow Q registers too. */
7187 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7192 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7194 inst
.operands
[i
].issingle
= 1;
7199 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7204 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7205 &inst
.operands
[i
].vectype
);
7208 /* Addressing modes */
7210 po_misc_or_fail (parse_address (&str
, i
));
7214 po_misc_or_fail_no_backtrack (
7215 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7219 po_misc_or_fail_no_backtrack (
7220 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7224 po_misc_or_fail_no_backtrack (
7225 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7229 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7233 po_misc_or_fail_no_backtrack (
7234 parse_shifter_operand_group_reloc (&str
, i
));
7238 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7242 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7246 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7250 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7253 /* Various value-based sanity checks and shared operations. We
7254 do not signal immediate failures for the register constraints;
7255 this allows a syntax error to take precedence. */
7256 switch (op_parse_code
)
7264 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7265 inst
.error
= BAD_PC
;
7270 if (inst
.operands
[i
].isreg
)
7272 if (inst
.operands
[i
].reg
== REG_PC
)
7273 inst
.error
= BAD_PC
;
7274 else if (inst
.operands
[i
].reg
== REG_SP
7275 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7276 relaxed since ARMv8-A. */
7277 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7280 inst
.error
= BAD_SP
;
7286 if (inst
.operands
[i
].isreg
7287 && inst
.operands
[i
].reg
== REG_PC
7288 && (inst
.operands
[i
].writeback
|| thumb
))
7289 inst
.error
= BAD_PC
;
7298 case OP_oBARRIER_I15
:
7307 inst
.operands
[i
].imm
= val
;
7314 /* If we get here, this operand was successfully parsed. */
7315 inst
.operands
[i
].present
= 1;
7319 inst
.error
= BAD_ARGS
;
7324 /* The parse routine should already have set inst.error, but set a
7325 default here just in case. */
7327 inst
.error
= _("syntax error");
7331 /* Do not backtrack over a trailing optional argument that
7332 absorbed some text. We will only fail again, with the
7333 'garbage following instruction' error message, which is
7334 probably less helpful than the current one. */
7335 if (backtrack_index
== i
&& backtrack_pos
!= str
7336 && upat
[i
+1] == OP_stop
)
7339 inst
.error
= _("syntax error");
7343 /* Try again, skipping the optional argument at backtrack_pos. */
7344 str
= backtrack_pos
;
7345 inst
.error
= backtrack_error
;
7346 inst
.operands
[backtrack_index
].present
= 0;
7347 i
= backtrack_index
;
7351 /* Check that we have parsed all the arguments. */
7352 if (*str
!= '\0' && !inst
.error
)
7353 inst
.error
= _("garbage following instruction");
7355 return inst
.error
? FAIL
: SUCCESS
;
7358 #undef po_char_or_fail
7359 #undef po_reg_or_fail
7360 #undef po_reg_or_goto
7361 #undef po_imm_or_fail
7362 #undef po_scalar_or_fail
7363 #undef po_barrier_or_imm
7365 /* Shorthand macro for instruction encoding functions issuing errors. */
7366 #define constraint(expr, err) \
7377 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7378 instructions are unpredictable if these registers are used. This
7379 is the BadReg predicate in ARM's Thumb-2 documentation.
7381 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7382 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7383 #define reject_bad_reg(reg) \
7385 if (reg == REG_PC) \
7387 inst.error = BAD_PC; \
7390 else if (reg == REG_SP \
7391 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7393 inst.error = BAD_SP; \
7398 /* If REG is R13 (the stack pointer), warn that its use is
7400 #define warn_deprecated_sp(reg) \
7402 if (warn_on_deprecated && reg == REG_SP) \
7403 as_tsktsk (_("use of r13 is deprecated")); \
7406 /* Functions for operand encoding. ARM, then Thumb. */
7408 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7410 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7412 The only binary encoding difference is the Coprocessor number. Coprocessor
7413 9 is used for half-precision calculations or conversions. The format of the
7414 instruction is the same as the equivalent Coprocessor 10 instruction that
7415 exists for Single-Precision operation. */
7418 do_scalar_fp16_v82_encode (void)
7420 if (inst
.cond
!= COND_ALWAYS
)
7421 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7422 " the behaviour is UNPREDICTABLE"));
7423 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7426 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7427 mark_feature_used (&arm_ext_fp16
);
7430 /* If VAL can be encoded in the immediate field of an ARM instruction,
7431 return the encoded form. Otherwise, return FAIL. */
7434 encode_arm_immediate (unsigned int val
)
7441 for (i
= 2; i
< 32; i
+= 2)
7442 if ((a
= rotate_left (val
, i
)) <= 0xff)
7443 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7448 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7449 return the encoded form. Otherwise, return FAIL. */
7451 encode_thumb32_immediate (unsigned int val
)
7458 for (i
= 1; i
<= 24; i
++)
7461 if ((val
& ~(0xff << i
)) == 0)
7462 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7466 if (val
== ((a
<< 16) | a
))
7468 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7472 if (val
== ((a
<< 16) | a
))
7473 return 0x200 | (a
>> 8);
7477 /* Encode a VFP SP or DP register number into inst.instruction. */
7480 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7482 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7485 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7488 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7491 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7496 first_error (_("D register out of range for selected VFP version"));
7504 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7508 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7512 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7516 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7520 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7524 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7532 /* Encode a <shift> in an ARM-format instruction. The immediate,
7533 if any, is handled by md_apply_fix. */
7535 encode_arm_shift (int i
)
7537 /* register-shifted register. */
7538 if (inst
.operands
[i
].immisreg
)
7541 for (op_index
= 0; op_index
<= i
; ++op_index
)
7543 /* Check the operand only when it's presented. In pre-UAL syntax,
7544 if the destination register is the same as the first operand, two
7545 register form of the instruction can be used. */
7546 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7547 && inst
.operands
[op_index
].reg
== REG_PC
)
7548 as_warn (UNPRED_REG ("r15"));
7551 if (inst
.operands
[i
].imm
== REG_PC
)
7552 as_warn (UNPRED_REG ("r15"));
7555 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7556 inst
.instruction
|= SHIFT_ROR
<< 5;
7559 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7560 if (inst
.operands
[i
].immisreg
)
7562 inst
.instruction
|= SHIFT_BY_REG
;
7563 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7566 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7571 encode_arm_shifter_operand (int i
)
7573 if (inst
.operands
[i
].isreg
)
7575 inst
.instruction
|= inst
.operands
[i
].reg
;
7576 encode_arm_shift (i
);
7580 inst
.instruction
|= INST_IMMEDIATE
;
7581 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
7582 inst
.instruction
|= inst
.operands
[i
].imm
;
7586 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7588 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7591 Generate an error if the operand is not a register. */
7592 constraint (!inst
.operands
[i
].isreg
,
7593 _("Instruction does not support =N addresses"));
7595 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7597 if (inst
.operands
[i
].preind
)
7601 inst
.error
= _("instruction does not accept preindexed addressing");
7604 inst
.instruction
|= PRE_INDEX
;
7605 if (inst
.operands
[i
].writeback
)
7606 inst
.instruction
|= WRITE_BACK
;
7609 else if (inst
.operands
[i
].postind
)
7611 gas_assert (inst
.operands
[i
].writeback
);
7613 inst
.instruction
|= WRITE_BACK
;
7615 else /* unindexed - only for coprocessor */
7617 inst
.error
= _("instruction does not accept unindexed addressing");
7621 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7622 && (((inst
.instruction
& 0x000f0000) >> 16)
7623 == ((inst
.instruction
& 0x0000f000) >> 12)))
7624 as_warn ((inst
.instruction
& LOAD_BIT
)
7625 ? _("destination register same as write-back base")
7626 : _("source register same as write-back base"));
7629 /* inst.operands[i] was set up by parse_address. Encode it into an
7630 ARM-format mode 2 load or store instruction. If is_t is true,
7631 reject forms that cannot be used with a T instruction (i.e. not
7634 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7636 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7638 encode_arm_addr_mode_common (i
, is_t
);
7640 if (inst
.operands
[i
].immisreg
)
7642 constraint ((inst
.operands
[i
].imm
== REG_PC
7643 || (is_pc
&& inst
.operands
[i
].writeback
)),
7645 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7646 inst
.instruction
|= inst
.operands
[i
].imm
;
7647 if (!inst
.operands
[i
].negative
)
7648 inst
.instruction
|= INDEX_UP
;
7649 if (inst
.operands
[i
].shifted
)
7651 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7652 inst
.instruction
|= SHIFT_ROR
<< 5;
7655 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7656 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7660 else /* immediate offset in inst.relocs[0] */
7662 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
7664 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7666 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7667 cannot use PC in addressing.
7668 PC cannot be used in writeback addressing, either. */
7669 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7672 /* Use of PC in str is deprecated for ARMv7. */
7673 if (warn_on_deprecated
7675 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7676 as_tsktsk (_("use of PC in this instruction is deprecated"));
7679 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7681 /* Prefer + for zero encoded value. */
7682 if (!inst
.operands
[i
].negative
)
7683 inst
.instruction
|= INDEX_UP
;
7684 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
7689 /* inst.operands[i] was set up by parse_address. Encode it into an
7690 ARM-format mode 3 load or store instruction. Reject forms that
7691 cannot be used with such instructions. If is_t is true, reject
7692 forms that cannot be used with a T instruction (i.e. not
7695 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7697 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7699 inst
.error
= _("instruction does not accept scaled register index");
7703 encode_arm_addr_mode_common (i
, is_t
);
7705 if (inst
.operands
[i
].immisreg
)
7707 constraint ((inst
.operands
[i
].imm
== REG_PC
7708 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7710 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7712 inst
.instruction
|= inst
.operands
[i
].imm
;
7713 if (!inst
.operands
[i
].negative
)
7714 inst
.instruction
|= INDEX_UP
;
7716 else /* immediate offset in inst.relocs[0] */
7718 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
7719 && inst
.operands
[i
].writeback
),
7721 inst
.instruction
|= HWOFFSET_IMM
;
7722 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7724 /* Prefer + for zero encoded value. */
7725 if (!inst
.operands
[i
].negative
)
7726 inst
.instruction
|= INDEX_UP
;
7728 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7733 /* Write immediate bits [7:0] to the following locations:
7735 |28/24|23 19|18 16|15 4|3 0|
7736 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7738 This function is used by VMOV/VMVN/VORR/VBIC. */
7741 neon_write_immbits (unsigned immbits
)
7743 inst
.instruction
|= immbits
& 0xf;
7744 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7745 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7748 /* Invert low-order SIZE bits of XHI:XLO. */
7751 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7753 unsigned immlo
= xlo
? *xlo
: 0;
7754 unsigned immhi
= xhi
? *xhi
: 0;
7759 immlo
= (~immlo
) & 0xff;
7763 immlo
= (~immlo
) & 0xffff;
7767 immhi
= (~immhi
) & 0xffffffff;
7771 immlo
= (~immlo
) & 0xffffffff;
7785 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7789 neon_bits_same_in_bytes (unsigned imm
)
7791 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7792 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7793 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7794 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7797 /* For immediate of above form, return 0bABCD. */
7800 neon_squash_bits (unsigned imm
)
7802 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7803 | ((imm
& 0x01000000) >> 21);
7806 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7809 neon_qfloat_bits (unsigned imm
)
7811 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7814 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7815 the instruction. *OP is passed as the initial value of the op field, and
7816 may be set to a different value depending on the constant (i.e.
7817 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7818 MVN). If the immediate looks like a repeated pattern then also
7819 try smaller element sizes. */
7822 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7823 unsigned *immbits
, int *op
, int size
,
7824 enum neon_el_type type
)
7826 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7828 if (type
== NT_float
&& !float_p
)
7831 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7833 if (size
!= 32 || *op
== 1)
7835 *immbits
= neon_qfloat_bits (immlo
);
7841 if (neon_bits_same_in_bytes (immhi
)
7842 && neon_bits_same_in_bytes (immlo
))
7846 *immbits
= (neon_squash_bits (immhi
) << 4)
7847 | neon_squash_bits (immlo
);
7858 if (immlo
== (immlo
& 0x000000ff))
7863 else if (immlo
== (immlo
& 0x0000ff00))
7865 *immbits
= immlo
>> 8;
7868 else if (immlo
== (immlo
& 0x00ff0000))
7870 *immbits
= immlo
>> 16;
7873 else if (immlo
== (immlo
& 0xff000000))
7875 *immbits
= immlo
>> 24;
7878 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7880 *immbits
= (immlo
>> 8) & 0xff;
7883 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7885 *immbits
= (immlo
>> 16) & 0xff;
7889 if ((immlo
& 0xffff) != (immlo
>> 16))
7896 if (immlo
== (immlo
& 0x000000ff))
7901 else if (immlo
== (immlo
& 0x0000ff00))
7903 *immbits
= immlo
>> 8;
7907 if ((immlo
& 0xff) != (immlo
>> 8))
7912 if (immlo
== (immlo
& 0x000000ff))
7914 /* Don't allow MVN with 8-bit immediate. */
7924 #if defined BFD_HOST_64_BIT
7925 /* Returns TRUE if double precision value V may be cast
7926 to single precision without loss of accuracy. */
7929 is_double_a_single (bfd_int64_t v
)
7931 int exp
= (int)((v
>> 52) & 0x7FF);
7932 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7934 return (exp
== 0 || exp
== 0x7FF
7935 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7936 && (mantissa
& 0x1FFFFFFFl
) == 0;
7939 /* Returns a double precision value casted to single precision
7940 (ignoring the least significant bits in exponent and mantissa). */
7943 double_to_single (bfd_int64_t v
)
7945 int sign
= (int) ((v
>> 63) & 1l);
7946 int exp
= (int) ((v
>> 52) & 0x7FF);
7947 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7953 exp
= exp
- 1023 + 127;
7962 /* No denormalized numbers. */
7968 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7970 #endif /* BFD_HOST_64_BIT */
7979 static void do_vfp_nsyn_opcode (const char *);
7981 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
7982 Determine whether it can be performed with a move instruction; if
7983 it can, convert inst.instruction to that move instruction and
7984 return TRUE; if it can't, convert inst.instruction to a literal-pool
7985 load and return FALSE. If this is not a valid thing to do in the
7986 current context, set inst.error and return TRUE.
7988 inst.operands[i] describes the destination register. */
7991 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7994 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7995 bfd_boolean arm_p
= (t
== CONST_ARM
);
7998 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8002 if ((inst
.instruction
& tbit
) == 0)
8004 inst
.error
= _("invalid pseudo operation");
8008 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8009 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8010 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8012 inst
.error
= _("constant expression expected");
8016 if (inst
.relocs
[0].exp
.X_op
== O_constant
8017 || inst
.relocs
[0].exp
.X_op
== O_big
)
8019 #if defined BFD_HOST_64_BIT
8024 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8026 LITTLENUM_TYPE w
[X_PRECISION
];
8029 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8031 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8033 /* FIXME: Should we check words w[2..5] ? */
8038 #if defined BFD_HOST_64_BIT
8040 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8041 << LITTLENUM_NUMBER_OF_BITS
)
8042 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8043 << LITTLENUM_NUMBER_OF_BITS
)
8044 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8045 << LITTLENUM_NUMBER_OF_BITS
)
8046 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8048 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8049 | (l
[0] & LITTLENUM_MASK
);
8053 v
= inst
.relocs
[0].exp
.X_add_number
;
8055 if (!inst
.operands
[i
].issingle
)
8059 /* LDR should not use lead in a flag-setting instruction being
8060 chosen so we do not check whether movs can be used. */
8062 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8063 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8064 && inst
.operands
[i
].reg
!= 13
8065 && inst
.operands
[i
].reg
!= 15)
8067 /* Check if on thumb2 it can be done with a mov.w, mvn or
8068 movw instruction. */
8069 unsigned int newimm
;
8070 bfd_boolean isNegated
;
8072 newimm
= encode_thumb32_immediate (v
);
8073 if (newimm
!= (unsigned int) FAIL
)
8077 newimm
= encode_thumb32_immediate (~v
);
8078 if (newimm
!= (unsigned int) FAIL
)
8082 /* The number can be loaded with a mov.w or mvn
8084 if (newimm
!= (unsigned int) FAIL
8085 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8087 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8088 | (inst
.operands
[i
].reg
<< 8));
8089 /* Change to MOVN. */
8090 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8091 inst
.instruction
|= (newimm
& 0x800) << 15;
8092 inst
.instruction
|= (newimm
& 0x700) << 4;
8093 inst
.instruction
|= (newimm
& 0x0ff);
8096 /* The number can be loaded with a movw instruction. */
8097 else if ((v
& ~0xFFFF) == 0
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8100 int imm
= v
& 0xFFFF;
8102 inst
.instruction
= 0xf2400000; /* MOVW. */
8103 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8104 inst
.instruction
|= (imm
& 0xf000) << 4;
8105 inst
.instruction
|= (imm
& 0x0800) << 15;
8106 inst
.instruction
|= (imm
& 0x0700) << 4;
8107 inst
.instruction
|= (imm
& 0x00ff);
8114 int value
= encode_arm_immediate (v
);
8118 /* This can be done with a mov instruction. */
8119 inst
.instruction
&= LITERAL_MASK
;
8120 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8121 inst
.instruction
|= value
& 0xfff;
8125 value
= encode_arm_immediate (~ v
);
8128 /* This can be done with a mvn instruction. */
8129 inst
.instruction
&= LITERAL_MASK
;
8130 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8131 inst
.instruction
|= value
& 0xfff;
8135 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8138 unsigned immbits
= 0;
8139 unsigned immlo
= inst
.operands
[1].imm
;
8140 unsigned immhi
= inst
.operands
[1].regisimm
8141 ? inst
.operands
[1].reg
8142 : inst
.relocs
[0].exp
.X_unsigned
8144 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8145 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8146 &op
, 64, NT_invtype
);
8150 neon_invert_size (&immlo
, &immhi
, 64);
8152 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8153 &op
, 64, NT_invtype
);
8158 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8164 /* Fill other bits in vmov encoding for both thumb and arm. */
8166 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8168 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8169 neon_write_immbits (immbits
);
8177 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8178 if (inst
.operands
[i
].issingle
8179 && is_quarter_float (inst
.operands
[1].imm
)
8180 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8182 inst
.operands
[1].imm
=
8183 neon_qfloat_bits (v
);
8184 do_vfp_nsyn_opcode ("fconsts");
8188 /* If our host does not support a 64-bit type then we cannot perform
8189 the following optimization. This mean that there will be a
8190 discrepancy between the output produced by an assembler built for
8191 a 32-bit-only host and the output produced from a 64-bit host, but
8192 this cannot be helped. */
8193 #if defined BFD_HOST_64_BIT
8194 else if (!inst
.operands
[1].issingle
8195 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8197 if (is_double_a_single (v
)
8198 && is_quarter_float (double_to_single (v
)))
8200 inst
.operands
[1].imm
=
8201 neon_qfloat_bits (double_to_single (v
));
8202 do_vfp_nsyn_opcode ("fconstd");
8210 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8211 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8214 inst
.operands
[1].reg
= REG_PC
;
8215 inst
.operands
[1].isreg
= 1;
8216 inst
.operands
[1].preind
= 1;
8217 inst
.relocs
[0].pc_rel
= 1;
8218 inst
.relocs
[0].type
= (thumb_p
8219 ? BFD_RELOC_ARM_THUMB_OFFSET
8221 ? BFD_RELOC_ARM_HWLITERAL
8222 : BFD_RELOC_ARM_LITERAL
));
8226 /* inst.operands[i] was set up by parse_address. Encode it into an
8227 ARM-format instruction. Reject all forms which cannot be encoded
8228 into a coprocessor load/store instruction. If wb_ok is false,
8229 reject use of writeback; if unind_ok is false, reject use of
8230 unindexed addressing. If reloc_override is not 0, use it instead
8231 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8232 (in which case it is preserved). */
8235 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8237 if (!inst
.operands
[i
].isreg
)
8240 if (! inst
.operands
[0].isvec
)
8242 inst
.error
= _("invalid co-processor operand");
8245 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8249 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8251 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8253 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8255 gas_assert (!inst
.operands
[i
].writeback
);
8258 inst
.error
= _("instruction does not support unindexed addressing");
8261 inst
.instruction
|= inst
.operands
[i
].imm
;
8262 inst
.instruction
|= INDEX_UP
;
8266 if (inst
.operands
[i
].preind
)
8267 inst
.instruction
|= PRE_INDEX
;
8269 if (inst
.operands
[i
].writeback
)
8271 if (inst
.operands
[i
].reg
== REG_PC
)
8273 inst
.error
= _("pc may not be used with write-back");
8278 inst
.error
= _("instruction does not support writeback");
8281 inst
.instruction
|= WRITE_BACK
;
8285 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8286 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8287 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8288 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8291 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8293 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8296 /* Prefer + for zero encoded value. */
8297 if (!inst
.operands
[i
].negative
)
8298 inst
.instruction
|= INDEX_UP
;
8303 /* Functions for instruction encoding, sorted by sub-architecture.
8304 First some generics; their names are taken from the conventional
8305 bit positions for register arguments in ARM format instructions. */
8315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8328 inst
.instruction
|= inst
.operands
[1].reg
;
8334 inst
.instruction
|= inst
.operands
[0].reg
;
8335 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8342 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8348 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8349 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8355 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8356 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8360 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8362 if (ARM_CPU_IS_ANY (cpu_variant
))
8364 as_tsktsk ("%s", msg
);
8367 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8379 unsigned Rn
= inst
.operands
[2].reg
;
8380 /* Enforce restrictions on SWP instruction. */
8381 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8383 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8384 _("Rn must not overlap other operands"));
8386 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8388 if (!check_obsolete (&arm_ext_v8
,
8389 _("swp{b} use is obsoleted for ARMv8 and later"))
8390 && warn_on_deprecated
8391 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8392 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8396 inst
.instruction
|= inst
.operands
[1].reg
;
8397 inst
.instruction
|= Rn
<< 16;
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8404 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8405 inst
.instruction
|= inst
.operands
[2].reg
;
8411 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8412 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8413 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8414 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8416 inst
.instruction
|= inst
.operands
[0].reg
;
8417 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8418 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8424 inst
.instruction
|= inst
.operands
[0].imm
;
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8434 /* ARM instructions, in alphabetical order by function name (except
8435 that wrapper functions appear immediately after the function they
8438 /* This is a pseudo-op of the form "adr rd, label" to be converted
8439 into a relative address of the form "add rd, pc, #label-.-8". */
8444 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8446 /* Frag hacking will turn this into a sub instruction if the offset turns
8447 out to be negative. */
8448 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8449 inst
.relocs
[0].pc_rel
= 1;
8450 inst
.relocs
[0].exp
.X_add_number
-= 8;
8452 if (support_interwork
8453 && inst
.relocs
[0].exp
.X_op
== O_symbol
8454 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8455 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8456 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8457 inst
.relocs
[0].exp
.X_add_number
|= 1;
8460 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8461 into a relative address of the form:
8462 add rd, pc, #low(label-.-8)"
8463 add rd, rd, #high(label-.-8)" */
8468 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8470 /* Frag hacking will turn this into a sub instruction if the offset turns
8471 out to be negative. */
8472 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8473 inst
.relocs
[0].pc_rel
= 1;
8474 inst
.size
= INSN_SIZE
* 2;
8475 inst
.relocs
[0].exp
.X_add_number
-= 8;
8477 if (support_interwork
8478 && inst
.relocs
[0].exp
.X_op
== O_symbol
8479 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8480 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8481 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8482 inst
.relocs
[0].exp
.X_add_number
|= 1;
8488 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8489 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8491 if (!inst
.operands
[1].present
)
8492 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8495 encode_arm_shifter_operand (2);
8501 if (inst
.operands
[0].present
)
8502 inst
.instruction
|= inst
.operands
[0].imm
;
8504 inst
.instruction
|= 0xf;
8510 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8511 constraint (msb
> 32, _("bit-field extends past end of register"));
8512 /* The instruction encoding stores the LSB and MSB,
8513 not the LSB and width. */
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8516 inst
.instruction
|= (msb
- 1) << 16;
8524 /* #0 in second position is alternative syntax for bfc, which is
8525 the same instruction but with REG_PC in the Rm field. */
8526 if (!inst
.operands
[1].isreg
)
8527 inst
.operands
[1].reg
= REG_PC
;
8529 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8530 constraint (msb
> 32, _("bit-field extends past end of register"));
8531 /* The instruction encoding stores the LSB and MSB,
8532 not the LSB and width. */
8533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8534 inst
.instruction
|= inst
.operands
[1].reg
;
8535 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8536 inst
.instruction
|= (msb
- 1) << 16;
8542 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8543 _("bit-field extends past end of register"));
8544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8545 inst
.instruction
|= inst
.operands
[1].reg
;
8546 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8547 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8550 /* ARM V5 breakpoint instruction (argument parse)
8551 BKPT <16 bit unsigned immediate>
8552 Instruction is not conditional.
8553 The bit pattern given in insns[] has the COND_ALWAYS condition,
8554 and it is an error if the caller tried to override that. */
8559 /* Top 12 of 16 bits to bits 19:8. */
8560 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8562 /* Bottom 4 of 16 bits to bits 3:0. */
8563 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8567 encode_branch (int default_reloc
)
8569 if (inst
.operands
[0].hasreloc
)
8571 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8572 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8573 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8574 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8575 ? BFD_RELOC_ARM_PLT32
8576 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8579 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
8580 inst
.relocs
[0].pc_rel
= 1;
8587 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8588 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8591 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8598 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8600 if (inst
.cond
== COND_ALWAYS
)
8601 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8603 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8607 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8610 /* ARM V5 branch-link-exchange instruction (argument parse)
8611 BLX <target_addr> ie BLX(1)
8612 BLX{<condition>} <Rm> ie BLX(2)
8613 Unfortunately, there are two different opcodes for this mnemonic.
8614 So, the insns[].value is not used, and the code here zaps values
8615 into inst.instruction.
8616 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8621 if (inst
.operands
[0].isreg
)
8623 /* Arg is a register; the opcode provided by insns[] is correct.
8624 It is not illegal to do "blx pc", just useless. */
8625 if (inst
.operands
[0].reg
== REG_PC
)
8626 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8628 inst
.instruction
|= inst
.operands
[0].reg
;
8632 /* Arg is an address; this instruction cannot be executed
8633 conditionally, and the opcode must be adjusted.
8634 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8635 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8636 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8637 inst
.instruction
= 0xfa000000;
8638 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8645 bfd_boolean want_reloc
;
8647 if (inst
.operands
[0].reg
== REG_PC
)
8648 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8650 inst
.instruction
|= inst
.operands
[0].reg
;
8651 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8652 it is for ARMv4t or earlier. */
8653 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8654 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8655 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8659 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8664 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
8668 /* ARM v5TEJ. Jump to Jazelle code. */
8673 if (inst
.operands
[0].reg
== REG_PC
)
8674 as_tsktsk (_("use of r15 in bxj is not really useful"));
8676 inst
.instruction
|= inst
.operands
[0].reg
;
8679 /* Co-processor data operation:
8680 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8681 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8686 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8687 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8688 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8689 inst
.instruction
|= inst
.operands
[4].reg
;
8690 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8696 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8697 encode_arm_shifter_operand (1);
8700 /* Transfer between coprocessor and ARM registers.
8701 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8706 No special properties. */
8708 struct deprecated_coproc_regs_s
8715 arm_feature_set deprecated
;
8716 arm_feature_set obsoleted
;
8717 const char *dep_msg
;
8718 const char *obs_msg
;
8721 #define DEPR_ACCESS_V8 \
8722 N_("This coprocessor register access is deprecated in ARMv8")
8724 /* Table of all deprecated coprocessor registers. */
8725 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8727 {15, 0, 7, 10, 5, /* CP15DMB. */
8728 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8729 DEPR_ACCESS_V8
, NULL
},
8730 {15, 0, 7, 10, 4, /* CP15DSB. */
8731 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8732 DEPR_ACCESS_V8
, NULL
},
8733 {15, 0, 7, 5, 4, /* CP15ISB. */
8734 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8735 DEPR_ACCESS_V8
, NULL
},
8736 {14, 6, 1, 0, 0, /* TEEHBR. */
8737 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8738 DEPR_ACCESS_V8
, NULL
},
8739 {14, 6, 0, 0, 0, /* TEECR. */
8740 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8741 DEPR_ACCESS_V8
, NULL
},
8744 #undef DEPR_ACCESS_V8
8746 static const size_t deprecated_coproc_reg_count
=
8747 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8755 Rd
= inst
.operands
[2].reg
;
8758 if (inst
.instruction
== 0xee000010
8759 || inst
.instruction
== 0xfe000010)
8761 reject_bad_reg (Rd
);
8762 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8764 constraint (Rd
== REG_SP
, BAD_SP
);
8769 if (inst
.instruction
== 0xe000010)
8770 constraint (Rd
== REG_PC
, BAD_PC
);
8773 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8775 const struct deprecated_coproc_regs_s
*r
=
8776 deprecated_coproc_regs
+ i
;
8778 if (inst
.operands
[0].reg
== r
->cp
8779 && inst
.operands
[1].imm
== r
->opc1
8780 && inst
.operands
[3].reg
== r
->crn
8781 && inst
.operands
[4].reg
== r
->crm
8782 && inst
.operands
[5].imm
== r
->opc2
)
8784 if (! ARM_CPU_IS_ANY (cpu_variant
)
8785 && warn_on_deprecated
8786 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8787 as_tsktsk ("%s", r
->dep_msg
);
8791 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8792 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8793 inst
.instruction
|= Rd
<< 12;
8794 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8795 inst
.instruction
|= inst
.operands
[4].reg
;
8796 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8799 /* Transfer between coprocessor register and pair of ARM registers.
8800 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8805 Two XScale instructions are special cases of these:
8807 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8808 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8810 Result unpredictable if Rd or Rn is R15. */
8817 Rd
= inst
.operands
[2].reg
;
8818 Rn
= inst
.operands
[3].reg
;
8822 reject_bad_reg (Rd
);
8823 reject_bad_reg (Rn
);
8827 constraint (Rd
== REG_PC
, BAD_PC
);
8828 constraint (Rn
== REG_PC
, BAD_PC
);
8831 /* Only check the MRRC{2} variants. */
8832 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8834 /* If Rd == Rn, error that the operation is
8835 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8836 constraint (Rd
== Rn
, BAD_OVERLAP
);
8839 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8840 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8841 inst
.instruction
|= Rd
<< 12;
8842 inst
.instruction
|= Rn
<< 16;
8843 inst
.instruction
|= inst
.operands
[4].reg
;
8849 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8850 if (inst
.operands
[1].present
)
8852 inst
.instruction
|= CPSI_MMOD
;
8853 inst
.instruction
|= inst
.operands
[1].imm
;
8860 inst
.instruction
|= inst
.operands
[0].imm
;
8866 unsigned Rd
, Rn
, Rm
;
8868 Rd
= inst
.operands
[0].reg
;
8869 Rn
= (inst
.operands
[1].present
8870 ? inst
.operands
[1].reg
: Rd
);
8871 Rm
= inst
.operands
[2].reg
;
8873 constraint ((Rd
== REG_PC
), BAD_PC
);
8874 constraint ((Rn
== REG_PC
), BAD_PC
);
8875 constraint ((Rm
== REG_PC
), BAD_PC
);
8877 inst
.instruction
|= Rd
<< 16;
8878 inst
.instruction
|= Rn
<< 0;
8879 inst
.instruction
|= Rm
<< 8;
8885 /* There is no IT instruction in ARM mode. We
8886 process it to do the validation as if in
8887 thumb mode, just in case the code gets
8888 assembled for thumb using the unified syntax. */
8893 set_it_insn_type (IT_INSN
);
8894 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8895 now_it
.cc
= inst
.operands
[0].imm
;
8899 /* If there is only one register in the register list,
8900 then return its register number. Otherwise return -1. */
8902 only_one_reg_in_list (int range
)
8904 int i
= ffs (range
) - 1;
8905 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8909 encode_ldmstm(int from_push_pop_mnem
)
8911 int base_reg
= inst
.operands
[0].reg
;
8912 int range
= inst
.operands
[1].imm
;
8915 inst
.instruction
|= base_reg
<< 16;
8916 inst
.instruction
|= range
;
8918 if (inst
.operands
[1].writeback
)
8919 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8921 if (inst
.operands
[0].writeback
)
8923 inst
.instruction
|= WRITE_BACK
;
8924 /* Check for unpredictable uses of writeback. */
8925 if (inst
.instruction
& LOAD_BIT
)
8927 /* Not allowed in LDM type 2. */
8928 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8929 && ((range
& (1 << REG_PC
)) == 0))
8930 as_warn (_("writeback of base register is UNPREDICTABLE"));
8931 /* Only allowed if base reg not in list for other types. */
8932 else if (range
& (1 << base_reg
))
8933 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8937 /* Not allowed for type 2. */
8938 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8939 as_warn (_("writeback of base register is UNPREDICTABLE"));
8940 /* Only allowed if base reg not in list, or first in list. */
8941 else if ((range
& (1 << base_reg
))
8942 && (range
& ((1 << base_reg
) - 1)))
8943 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8947 /* If PUSH/POP has only one register, then use the A2 encoding. */
8948 one_reg
= only_one_reg_in_list (range
);
8949 if (from_push_pop_mnem
&& one_reg
>= 0)
8951 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8953 if (is_push
&& one_reg
== 13 /* SP */)
8954 /* PR 22483: The A2 encoding cannot be used when
8955 pushing the stack pointer as this is UNPREDICTABLE. */
8958 inst
.instruction
&= A_COND_MASK
;
8959 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8960 inst
.instruction
|= one_reg
<< 12;
8967 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8970 /* ARMv5TE load-consecutive (argument parse)
8979 constraint (inst
.operands
[0].reg
% 2 != 0,
8980 _("first transfer register must be even"));
8981 constraint (inst
.operands
[1].present
8982 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8983 _("can only transfer two consecutive registers"));
8984 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8985 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8987 if (!inst
.operands
[1].present
)
8988 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8990 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8991 register and the first register written; we have to diagnose
8992 overlap between the base and the second register written here. */
8994 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8995 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8996 as_warn (_("base register written back, and overlaps "
8997 "second transfer register"));
8999 if (!(inst
.instruction
& V4_STR_BIT
))
9001 /* For an index-register load, the index register must not overlap the
9002 destination (even if not write-back). */
9003 if (inst
.operands
[2].immisreg
9004 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9005 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9006 as_warn (_("index register overlaps transfer register"));
9008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9009 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9015 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9016 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9017 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9018 || inst
.operands
[1].negative
9019 /* This can arise if the programmer has written
9021 or if they have mistakenly used a register name as the last
9024 It is very difficult to distinguish between these two cases
9025 because "rX" might actually be a label. ie the register
9026 name has been occluded by a symbol of the same name. So we
9027 just generate a general 'bad addressing mode' type error
9028 message and leave it up to the programmer to discover the
9029 true cause and fix their mistake. */
9030 || (inst
.operands
[1].reg
== REG_PC
),
9033 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9034 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9035 _("offset must be zero in ARM encoding"));
9037 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9041 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9047 constraint (inst
.operands
[0].reg
% 2 != 0,
9048 _("even register required"));
9049 constraint (inst
.operands
[1].present
9050 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9051 _("can only load two consecutive registers"));
9052 /* If op 1 were present and equal to PC, this function wouldn't
9053 have been called in the first place. */
9054 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9057 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9060 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9061 which is not a multiple of four is UNPREDICTABLE. */
9063 check_ldr_r15_aligned (void)
9065 constraint (!(inst
.operands
[1].immisreg
)
9066 && (inst
.operands
[0].reg
== REG_PC
9067 && inst
.operands
[1].reg
== REG_PC
9068 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9069 _("ldr to register 15 must be 4-byte aligned"));
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 if (!inst
.operands
[1].isreg
)
9077 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9079 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9080 check_ldr_r15_aligned ();
9086 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9088 if (inst
.operands
[1].preind
)
9090 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9091 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9092 _("this instruction requires a post-indexed address"));
9094 inst
.operands
[1].preind
= 0;
9095 inst
.operands
[1].postind
= 1;
9096 inst
.operands
[1].writeback
= 1;
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9102 /* Halfword and signed-byte load/store operations. */
9107 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9109 if (!inst
.operands
[1].isreg
)
9110 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9112 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9118 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9120 if (inst
.operands
[1].preind
)
9122 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9123 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9124 _("this instruction requires a post-indexed address"));
9126 inst
.operands
[1].preind
= 0;
9127 inst
.operands
[1].postind
= 1;
9128 inst
.operands
[1].writeback
= 1;
9130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9131 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9134 /* Co-processor register load/store.
9135 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9139 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9141 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9147 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9148 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9149 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9150 && !(inst
.instruction
& 0x00400000))
9151 as_tsktsk (_("Rd and Rm should be different in mla"));
9153 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9154 inst
.instruction
|= inst
.operands
[1].reg
;
9155 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9156 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9162 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9163 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9166 encode_arm_shifter_operand (1);
9169 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9176 top
= (inst
.instruction
& 0x00400000) != 0;
9177 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9178 _(":lower16: not allowed in this instruction"));
9179 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9180 _(":upper16: not allowed in this instruction"));
9181 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9182 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9184 imm
= inst
.relocs
[0].exp
.X_add_number
;
9185 /* The value is in two pieces: 0:11, 16:19. */
9186 inst
.instruction
|= (imm
& 0x00000fff);
9187 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9192 do_vfp_nsyn_mrs (void)
9194 if (inst
.operands
[0].isvec
)
9196 if (inst
.operands
[1].reg
!= 1)
9197 first_error (_("operand 1 must be FPSCR"));
9198 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9199 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9200 do_vfp_nsyn_opcode ("fmstat");
9202 else if (inst
.operands
[1].isvec
)
9203 do_vfp_nsyn_opcode ("fmrx");
9211 do_vfp_nsyn_msr (void)
9213 if (inst
.operands
[0].isvec
)
9214 do_vfp_nsyn_opcode ("fmxr");
9224 unsigned Rt
= inst
.operands
[0].reg
;
9226 if (thumb_mode
&& Rt
== REG_SP
)
9228 inst
.error
= BAD_SP
;
9232 /* MVFR2 is only valid at ARMv8-A. */
9233 if (inst
.operands
[1].reg
== 5)
9234 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9237 /* APSR_ sets isvec. All other refs to PC are illegal. */
9238 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9240 inst
.error
= BAD_PC
;
9244 /* If we get through parsing the register name, we just insert the number
9245 generated into the instruction without further validation. */
9246 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9247 inst
.instruction
|= (Rt
<< 12);
9253 unsigned Rt
= inst
.operands
[1].reg
;
9256 reject_bad_reg (Rt
);
9257 else if (Rt
== REG_PC
)
9259 inst
.error
= BAD_PC
;
9263 /* MVFR2 is only valid for ARMv8-A. */
9264 if (inst
.operands
[0].reg
== 5)
9265 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9268 /* If we get through parsing the register name, we just insert the number
9269 generated into the instruction without further validation. */
9270 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9271 inst
.instruction
|= (Rt
<< 12);
9279 if (do_vfp_nsyn_mrs () == SUCCESS
)
9282 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9285 if (inst
.operands
[1].isreg
)
9287 br
= inst
.operands
[1].reg
;
9288 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9289 as_bad (_("bad register for mrs"));
9293 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9294 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9296 _("'APSR', 'CPSR' or 'SPSR' expected"));
9297 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9300 inst
.instruction
|= br
;
9303 /* Two possible forms:
9304 "{C|S}PSR_<field>, Rm",
9305 "{C|S}PSR_f, #expression". */
9310 if (do_vfp_nsyn_msr () == SUCCESS
)
9313 inst
.instruction
|= inst
.operands
[0].imm
;
9314 if (inst
.operands
[1].isreg
)
9315 inst
.instruction
|= inst
.operands
[1].reg
;
9318 inst
.instruction
|= INST_IMMEDIATE
;
9319 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9320 inst
.relocs
[0].pc_rel
= 0;
9327 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9329 if (!inst
.operands
[2].present
)
9330 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9332 inst
.instruction
|= inst
.operands
[1].reg
;
9333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9335 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9336 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9337 as_tsktsk (_("Rd and Rm should be different in mul"));
9340 /* Long Multiply Parser
9341 UMULL RdLo, RdHi, Rm, Rs
9342 SMULL RdLo, RdHi, Rm, Rs
9343 UMLAL RdLo, RdHi, Rm, Rs
9344 SMLAL RdLo, RdHi, Rm, Rs. */
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9351 inst
.instruction
|= inst
.operands
[2].reg
;
9352 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9354 /* rdhi and rdlo must be different. */
9355 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9356 as_tsktsk (_("rdhi and rdlo must be different"));
9358 /* rdhi, rdlo and rm must all be different before armv6. */
9359 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9360 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9361 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9362 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9368 if (inst
.operands
[0].present
9369 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9371 /* Architectural NOP hints are CPSR sets with no bits selected. */
9372 inst
.instruction
&= 0xf0000000;
9373 inst
.instruction
|= 0x0320f000;
9374 if (inst
.operands
[0].present
)
9375 inst
.instruction
|= inst
.operands
[0].imm
;
9379 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9380 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9381 Condition defaults to COND_ALWAYS.
9382 Error if Rd, Rn or Rm are R15. */
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9389 inst
.instruction
|= inst
.operands
[2].reg
;
9390 if (inst
.operands
[3].present
)
9391 encode_arm_shift (3);
9394 /* ARM V6 PKHTB (Argument Parse). */
9399 if (!inst
.operands
[3].present
)
9401 /* If the shift specifier is omitted, turn the instruction
9402 into pkhbt rd, rm, rn. */
9403 inst
.instruction
&= 0xfff00010;
9404 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9405 inst
.instruction
|= inst
.operands
[1].reg
;
9406 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9411 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9412 inst
.instruction
|= inst
.operands
[2].reg
;
9413 encode_arm_shift (3);
9417 /* ARMv5TE: Preload-Cache
9418 MP Extensions: Preload for write
9422 Syntactically, like LDR with B=1, W=0, L=1. */
9427 constraint (!inst
.operands
[0].isreg
,
9428 _("'[' expected after PLD mnemonic"));
9429 constraint (inst
.operands
[0].postind
,
9430 _("post-indexed expression used in preload instruction"));
9431 constraint (inst
.operands
[0].writeback
,
9432 _("writeback used in preload instruction"));
9433 constraint (!inst
.operands
[0].preind
,
9434 _("unindexed addressing used in preload instruction"));
9435 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9438 /* ARMv7: PLI <addr_mode> */
9442 constraint (!inst
.operands
[0].isreg
,
9443 _("'[' expected after PLI mnemonic"));
9444 constraint (inst
.operands
[0].postind
,
9445 _("post-indexed expression used in preload instruction"));
9446 constraint (inst
.operands
[0].writeback
,
9447 _("writeback used in preload instruction"));
9448 constraint (!inst
.operands
[0].preind
,
9449 _("unindexed addressing used in preload instruction"));
9450 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9451 inst
.instruction
&= ~PRE_INDEX
;
9457 constraint (inst
.operands
[0].writeback
,
9458 _("push/pop do not support {reglist}^"));
9459 inst
.operands
[1] = inst
.operands
[0];
9460 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9461 inst
.operands
[0].isreg
= 1;
9462 inst
.operands
[0].writeback
= 1;
9463 inst
.operands
[0].reg
= REG_SP
;
9464 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9467 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9468 word at the specified address and the following word
9470 Unconditionally executed.
9471 Error if Rn is R15. */
9476 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9477 if (inst
.operands
[0].writeback
)
9478 inst
.instruction
|= WRITE_BACK
;
9481 /* ARM V6 ssat (argument parse). */
9486 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9487 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9488 inst
.instruction
|= inst
.operands
[2].reg
;
9490 if (inst
.operands
[3].present
)
9491 encode_arm_shift (3);
9494 /* ARM V6 usat (argument parse). */
9499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9500 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9501 inst
.instruction
|= inst
.operands
[2].reg
;
9503 if (inst
.operands
[3].present
)
9504 encode_arm_shift (3);
9507 /* ARM V6 ssat16 (argument parse). */
9512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9513 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9514 inst
.instruction
|= inst
.operands
[2].reg
;
9520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9521 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9522 inst
.instruction
|= inst
.operands
[2].reg
;
9525 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9526 preserving the other bits.
9528 setend <endian_specifier>, where <endian_specifier> is either
9534 if (warn_on_deprecated
9535 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9536 as_tsktsk (_("setend use is deprecated for ARMv8"));
9538 if (inst
.operands
[0].imm
)
9539 inst
.instruction
|= 0x200;
9545 unsigned int Rm
= (inst
.operands
[1].present
9546 ? inst
.operands
[1].reg
9547 : inst
.operands
[0].reg
);
9549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9550 inst
.instruction
|= Rm
;
9551 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9553 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9554 inst
.instruction
|= SHIFT_BY_REG
;
9555 /* PR 12854: Error on extraneous shifts. */
9556 constraint (inst
.operands
[2].shifted
,
9557 _("extraneous shift as part of operand to shift insn"));
9560 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
9566 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
9567 inst
.relocs
[0].pc_rel
= 0;
9573 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
9574 inst
.relocs
[0].pc_rel
= 0;
9580 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
9581 inst
.relocs
[0].pc_rel
= 0;
9587 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9588 _("selected processor does not support SETPAN instruction"));
9590 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9596 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9597 _("selected processor does not support SETPAN instruction"));
9599 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9602 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9603 SMLAxy{cond} Rd,Rm,Rs,Rn
9604 SMLAWy{cond} Rd,Rm,Rs,Rn
9605 Error if any register is R15. */
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[1].reg
;
9612 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9613 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9616 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9617 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9618 Error if any register is R15.
9619 Warning if Rdlo == Rdhi. */
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9625 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9626 inst
.instruction
|= inst
.operands
[2].reg
;
9627 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9629 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9630 as_tsktsk (_("rdhi and rdlo must be different"));
9633 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9634 SMULxy{cond} Rd,Rm,Rs
9635 Error if any register is R15. */
9640 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9641 inst
.instruction
|= inst
.operands
[1].reg
;
9642 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9645 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9646 the same for both ARM and Thumb-2. */
9653 if (inst
.operands
[0].present
)
9655 reg
= inst
.operands
[0].reg
;
9656 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9661 inst
.instruction
|= reg
<< 16;
9662 inst
.instruction
|= inst
.operands
[1].imm
;
9663 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9664 inst
.instruction
|= WRITE_BACK
;
9667 /* ARM V6 strex (argument parse). */
9672 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9673 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9674 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9675 || inst
.operands
[2].negative
9676 /* See comment in do_ldrex(). */
9677 || (inst
.operands
[2].reg
== REG_PC
),
9680 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9681 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9684 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9685 _("offset must be zero in ARM encoding"));
9687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9688 inst
.instruction
|= inst
.operands
[1].reg
;
9689 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9690 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9696 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9697 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9698 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9699 || inst
.operands
[2].negative
,
9702 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9703 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9711 constraint (inst
.operands
[1].reg
% 2 != 0,
9712 _("even register required"));
9713 constraint (inst
.operands
[2].present
9714 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9715 _("can only store two consecutive registers"));
9716 /* If op 2 were present and equal to PC, this function wouldn't
9717 have been called in the first place. */
9718 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9720 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9721 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9722 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9726 inst
.instruction
|= inst
.operands
[1].reg
;
9727 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9734 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9735 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9743 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9744 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9749 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9750 extends it to 32-bits, and adds the result to a value in another
9751 register. You can specify a rotation by 0, 8, 16, or 24 bits
9752 before extracting the 16-bit value.
9753 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9754 Condition defaults to COND_ALWAYS.
9755 Error if any register uses R15. */
9760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9761 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9762 inst
.instruction
|= inst
.operands
[2].reg
;
9763 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9768 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9769 Condition defaults to COND_ALWAYS.
9770 Error if any register uses R15. */
9775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9776 inst
.instruction
|= inst
.operands
[1].reg
;
9777 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9780 /* VFP instructions. In a logical order: SP variant first, monad
9781 before dyad, arithmetic then move then load/store. */
9784 do_vfp_sp_monadic (void)
9786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9791 do_vfp_sp_dyadic (void)
9793 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9794 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9795 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9799 do_vfp_sp_compare_z (void)
9801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9805 do_vfp_dp_sp_cvt (void)
9807 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9808 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9812 do_vfp_sp_dp_cvt (void)
9814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9815 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9819 do_vfp_reg_from_sp (void)
9821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9822 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9826 do_vfp_reg2_from_sp2 (void)
9828 constraint (inst
.operands
[2].imm
!= 2,
9829 _("only two consecutive VFP SP registers allowed here"));
9830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9832 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9836 do_vfp_sp_from_reg (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9839 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9843 do_vfp_sp2_from_reg2 (void)
9845 constraint (inst
.operands
[0].imm
!= 2,
9846 _("only two consecutive VFP SP registers allowed here"));
9847 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9848 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9849 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9853 do_vfp_sp_ldst (void)
9855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9856 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9860 do_vfp_dp_ldst (void)
9862 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9863 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9868 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9870 if (inst
.operands
[0].writeback
)
9871 inst
.instruction
|= WRITE_BACK
;
9873 constraint (ldstm_type
!= VFP_LDSTMIA
,
9874 _("this addressing mode requires base-register writeback"));
9875 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9876 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9877 inst
.instruction
|= inst
.operands
[1].imm
;
9881 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9885 if (inst
.operands
[0].writeback
)
9886 inst
.instruction
|= WRITE_BACK
;
9888 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9889 _("this addressing mode requires base-register writeback"));
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9892 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9894 count
= inst
.operands
[1].imm
<< 1;
9895 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9898 inst
.instruction
|= count
;
9902 do_vfp_sp_ldstmia (void)
9904 vfp_sp_ldstm (VFP_LDSTMIA
);
9908 do_vfp_sp_ldstmdb (void)
9910 vfp_sp_ldstm (VFP_LDSTMDB
);
9914 do_vfp_dp_ldstmia (void)
9916 vfp_dp_ldstm (VFP_LDSTMIA
);
9920 do_vfp_dp_ldstmdb (void)
9922 vfp_dp_ldstm (VFP_LDSTMDB
);
9926 do_vfp_xp_ldstmia (void)
9928 vfp_dp_ldstm (VFP_LDSTMIAX
);
9932 do_vfp_xp_ldstmdb (void)
9934 vfp_dp_ldstm (VFP_LDSTMDBX
);
9938 do_vfp_dp_rd_rm (void)
9940 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9941 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9945 do_vfp_dp_rn_rd (void)
9947 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9948 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9952 do_vfp_dp_rd_rn (void)
9954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9955 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9959 do_vfp_dp_rd_rn_rm (void)
9961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9962 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9963 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9969 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9973 do_vfp_dp_rm_rd_rn (void)
9975 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9976 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9977 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9980 /* VFPv3 instructions. */
9982 do_vfp_sp_const (void)
9984 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9985 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9986 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9990 do_vfp_dp_const (void)
9992 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9993 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9994 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9998 vfp_conv (int srcsize
)
10000 int immbits
= srcsize
- inst
.operands
[1].imm
;
10002 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10004 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10005 i.e. immbits must be in range 0 - 16. */
10006 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10009 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10011 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10012 i.e. immbits must be in range 0 - 31. */
10013 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10017 inst
.instruction
|= (immbits
& 1) << 5;
10018 inst
.instruction
|= (immbits
>> 1);
10022 do_vfp_sp_conv_16 (void)
10024 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10029 do_vfp_dp_conv_16 (void)
10031 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10036 do_vfp_sp_conv_32 (void)
10038 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10043 do_vfp_dp_conv_32 (void)
10045 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10049 /* FPA instructions. Also in a logical order. */
10054 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10055 inst
.instruction
|= inst
.operands
[1].reg
;
10059 do_fpa_ldmstm (void)
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10062 switch (inst
.operands
[1].imm
)
10064 case 1: inst
.instruction
|= CP_T_X
; break;
10065 case 2: inst
.instruction
|= CP_T_Y
; break;
10066 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10071 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10073 /* The instruction specified "ea" or "fd", so we can only accept
10074 [Rn]{!}. The instruction does not really support stacking or
10075 unstacking, so we have to emulate these by setting appropriate
10076 bits and offsets. */
10077 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10078 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10079 _("this instruction does not support indexing"));
10081 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10082 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10084 if (!(inst
.instruction
& INDEX_UP
))
10085 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10087 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10089 inst
.operands
[2].preind
= 0;
10090 inst
.operands
[2].postind
= 1;
10094 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10097 /* iWMMXt instructions: strictly in alphabetical order. */
10100 do_iwmmxt_tandorc (void)
10102 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10106 do_iwmmxt_textrc (void)
10108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10109 inst
.instruction
|= inst
.operands
[1].imm
;
10113 do_iwmmxt_textrm (void)
10115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10117 inst
.instruction
|= inst
.operands
[2].imm
;
10121 do_iwmmxt_tinsr (void)
10123 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10124 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10125 inst
.instruction
|= inst
.operands
[2].imm
;
10129 do_iwmmxt_tmia (void)
10131 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10132 inst
.instruction
|= inst
.operands
[1].reg
;
10133 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10137 do_iwmmxt_waligni (void)
10139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10140 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10141 inst
.instruction
|= inst
.operands
[2].reg
;
10142 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10146 do_iwmmxt_wmerge (void)
10148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10150 inst
.instruction
|= inst
.operands
[2].reg
;
10151 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10155 do_iwmmxt_wmov (void)
10157 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10159 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10160 inst
.instruction
|= inst
.operands
[1].reg
;
10164 do_iwmmxt_wldstbh (void)
10167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10169 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10171 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10172 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10176 do_iwmmxt_wldstw (void)
10178 /* RIWR_RIWC clears .isreg for a control register. */
10179 if (!inst
.operands
[0].isreg
)
10181 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10182 inst
.instruction
|= 0xf0000000;
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10186 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10190 do_iwmmxt_wldstd (void)
10192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10193 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10194 && inst
.operands
[1].immisreg
)
10196 inst
.instruction
&= ~0x1a000ff;
10197 inst
.instruction
|= (0xfU
<< 28);
10198 if (inst
.operands
[1].preind
)
10199 inst
.instruction
|= PRE_INDEX
;
10200 if (!inst
.operands
[1].negative
)
10201 inst
.instruction
|= INDEX_UP
;
10202 if (inst
.operands
[1].writeback
)
10203 inst
.instruction
|= WRITE_BACK
;
10204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10205 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10206 inst
.instruction
|= inst
.operands
[1].imm
;
10209 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10213 do_iwmmxt_wshufh (void)
10215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10216 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10217 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10218 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10222 do_iwmmxt_wzero (void)
10224 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10225 inst
.instruction
|= inst
.operands
[0].reg
;
10226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10227 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10231 do_iwmmxt_wrwrwr_or_imm5 (void)
10233 if (inst
.operands
[2].isreg
)
10236 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10237 _("immediate operand requires iWMMXt2"));
10239 if (inst
.operands
[2].imm
== 0)
10241 switch ((inst
.instruction
>> 20) & 0xf)
10247 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10248 inst
.operands
[2].imm
= 16;
10249 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10255 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10256 inst
.operands
[2].imm
= 32;
10257 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10264 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10266 wrn
= (inst
.instruction
>> 16) & 0xf;
10267 inst
.instruction
&= 0xff0fff0f;
10268 inst
.instruction
|= wrn
;
10269 /* Bail out here; the instruction is now assembled. */
10274 /* Map 32 -> 0, etc. */
10275 inst
.operands
[2].imm
&= 0x1f;
10276 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10280 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10281 operations first, then control, shift, and load/store. */
10283 /* Insns like "foo X,Y,Z". */
10286 do_mav_triple (void)
10288 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10289 inst
.instruction
|= inst
.operands
[1].reg
;
10290 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10293 /* Insns like "foo W,X,Y,Z".
10294 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10299 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10300 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10301 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10302 inst
.instruction
|= inst
.operands
[3].reg
;
10305 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10307 do_mav_dspsc (void)
10309 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10312 /* Maverick shift immediate instructions.
10313 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10314 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10317 do_mav_shift (void)
10319 int imm
= inst
.operands
[2].imm
;
10321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10322 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10324 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10325 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10326 Bit 4 should be 0. */
10327 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10329 inst
.instruction
|= imm
;
10332 /* XScale instructions. Also sorted arithmetic before move. */
10334 /* Xscale multiply-accumulate (argument parse)
10337 MIAxycc acc0,Rm,Rs. */
10342 inst
.instruction
|= inst
.operands
[1].reg
;
10343 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10346 /* Xscale move-accumulator-register (argument parse)
10348 MARcc acc0,RdLo,RdHi. */
10353 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10354 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10357 /* Xscale move-register-accumulator (argument parse)
10359 MRAcc RdLo,RdHi,acc0. */
10364 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10366 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10369 /* Encoding functions relevant only to Thumb. */
10371 /* inst.operands[i] is a shifted-register operand; encode
10372 it into inst.instruction in the format used by Thumb32. */
10375 encode_thumb32_shifted_operand (int i
)
10377 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10378 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10380 constraint (inst
.operands
[i
].immisreg
,
10381 _("shift by register not allowed in thumb mode"));
10382 inst
.instruction
|= inst
.operands
[i
].reg
;
10383 if (shift
== SHIFT_RRX
)
10384 inst
.instruction
|= SHIFT_ROR
<< 4;
10387 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10388 _("expression too complex"));
10390 constraint (value
> 32
10391 || (value
== 32 && (shift
== SHIFT_LSL
10392 || shift
== SHIFT_ROR
)),
10393 _("shift expression is too large"));
10397 else if (value
== 32)
10400 inst
.instruction
|= shift
<< 4;
10401 inst
.instruction
|= (value
& 0x1c) << 10;
10402 inst
.instruction
|= (value
& 0x03) << 6;
10407 /* inst.operands[i] was set up by parse_address. Encode it into a
10408 Thumb32 format load or store instruction. Reject forms that cannot
10409 be used with such instructions. If is_t is true, reject forms that
10410 cannot be used with a T instruction; if is_d is true, reject forms
10411 that cannot be used with a D instruction. If it is a store insn,
10412 reject PC in Rn. */
10415 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10417 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10419 constraint (!inst
.operands
[i
].isreg
,
10420 _("Instruction does not support =N addresses"));
10422 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10423 if (inst
.operands
[i
].immisreg
)
10425 constraint (is_pc
, BAD_PC_ADDRESSING
);
10426 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10427 constraint (inst
.operands
[i
].negative
,
10428 _("Thumb does not support negative register indexing"));
10429 constraint (inst
.operands
[i
].postind
,
10430 _("Thumb does not support register post-indexing"));
10431 constraint (inst
.operands
[i
].writeback
,
10432 _("Thumb does not support register indexing with writeback"));
10433 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10434 _("Thumb supports only LSL in shifted register indexing"));
10436 inst
.instruction
|= inst
.operands
[i
].imm
;
10437 if (inst
.operands
[i
].shifted
)
10439 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10440 _("expression too complex"));
10441 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10442 || inst
.relocs
[0].exp
.X_add_number
> 3,
10443 _("shift out of range"));
10444 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10446 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10448 else if (inst
.operands
[i
].preind
)
10450 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10451 constraint (is_t
&& inst
.operands
[i
].writeback
,
10452 _("cannot use writeback with this instruction"));
10453 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10454 BAD_PC_ADDRESSING
);
10458 inst
.instruction
|= 0x01000000;
10459 if (inst
.operands
[i
].writeback
)
10460 inst
.instruction
|= 0x00200000;
10464 inst
.instruction
|= 0x00000c00;
10465 if (inst
.operands
[i
].writeback
)
10466 inst
.instruction
|= 0x00000100;
10468 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10470 else if (inst
.operands
[i
].postind
)
10472 gas_assert (inst
.operands
[i
].writeback
);
10473 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10474 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10477 inst
.instruction
|= 0x00200000;
10479 inst
.instruction
|= 0x00000900;
10480 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10482 else /* unindexed - only for coprocessor */
10483 inst
.error
= _("instruction does not accept unindexed addressing");
10486 /* Table of Thumb instructions which exist in both 16- and 32-bit
10487 encodings (the latter only in post-V6T2 cores). The index is the
10488 value used in the insns table below. When there is more than one
10489 possible 16-bit encoding for the instruction, this table always
10491 Also contains several pseudo-instructions used during relaxation. */
10492 #define T16_32_TAB \
10493 X(_adc, 4140, eb400000), \
10494 X(_adcs, 4140, eb500000), \
10495 X(_add, 1c00, eb000000), \
10496 X(_adds, 1c00, eb100000), \
10497 X(_addi, 0000, f1000000), \
10498 X(_addis, 0000, f1100000), \
10499 X(_add_pc,000f, f20f0000), \
10500 X(_add_sp,000d, f10d0000), \
10501 X(_adr, 000f, f20f0000), \
10502 X(_and, 4000, ea000000), \
10503 X(_ands, 4000, ea100000), \
10504 X(_asr, 1000, fa40f000), \
10505 X(_asrs, 1000, fa50f000), \
10506 X(_b, e000, f000b000), \
10507 X(_bcond, d000, f0008000), \
10508 X(_bf, 0000, f040e001), \
10509 X(_bfcsel,0000, f000e001), \
10510 X(_bfx, 0000, f060e001), \
10511 X(_bfl, 0000, f000c001), \
10512 X(_bflx, 0000, f070e001), \
10513 X(_bic, 4380, ea200000), \
10514 X(_bics, 4380, ea300000), \
10515 X(_cmn, 42c0, eb100f00), \
10516 X(_cmp, 2800, ebb00f00), \
10517 X(_cpsie, b660, f3af8400), \
10518 X(_cpsid, b670, f3af8600), \
10519 X(_cpy, 4600, ea4f0000), \
10520 X(_dec_sp,80dd, f1ad0d00), \
10521 X(_eor, 4040, ea800000), \
10522 X(_eors, 4040, ea900000), \
10523 X(_inc_sp,00dd, f10d0d00), \
10524 X(_ldmia, c800, e8900000), \
10525 X(_ldr, 6800, f8500000), \
10526 X(_ldrb, 7800, f8100000), \
10527 X(_ldrh, 8800, f8300000), \
10528 X(_ldrsb, 5600, f9100000), \
10529 X(_ldrsh, 5e00, f9300000), \
10530 X(_ldr_pc,4800, f85f0000), \
10531 X(_ldr_pc2,4800, f85f0000), \
10532 X(_ldr_sp,9800, f85d0000), \
10533 X(_lsl, 0000, fa00f000), \
10534 X(_lsls, 0000, fa10f000), \
10535 X(_lsr, 0800, fa20f000), \
10536 X(_lsrs, 0800, fa30f000), \
10537 X(_mov, 2000, ea4f0000), \
10538 X(_movs, 2000, ea5f0000), \
10539 X(_mul, 4340, fb00f000), \
10540 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10541 X(_mvn, 43c0, ea6f0000), \
10542 X(_mvns, 43c0, ea7f0000), \
10543 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10544 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10545 X(_orr, 4300, ea400000), \
10546 X(_orrs, 4300, ea500000), \
10547 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10548 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10549 X(_rev, ba00, fa90f080), \
10550 X(_rev16, ba40, fa90f090), \
10551 X(_revsh, bac0, fa90f0b0), \
10552 X(_ror, 41c0, fa60f000), \
10553 X(_rors, 41c0, fa70f000), \
10554 X(_sbc, 4180, eb600000), \
10555 X(_sbcs, 4180, eb700000), \
10556 X(_stmia, c000, e8800000), \
10557 X(_str, 6000, f8400000), \
10558 X(_strb, 7000, f8000000), \
10559 X(_strh, 8000, f8200000), \
10560 X(_str_sp,9000, f84d0000), \
10561 X(_sub, 1e00, eba00000), \
10562 X(_subs, 1e00, ebb00000), \
10563 X(_subi, 8000, f1a00000), \
10564 X(_subis, 8000, f1b00000), \
10565 X(_sxtb, b240, fa4ff080), \
10566 X(_sxth, b200, fa0ff080), \
10567 X(_tst, 4200, ea100f00), \
10568 X(_uxtb, b2c0, fa5ff080), \
10569 X(_uxth, b280, fa1ff080), \
10570 X(_nop, bf00, f3af8000), \
10571 X(_yield, bf10, f3af8001), \
10572 X(_wfe, bf20, f3af8002), \
10573 X(_wfi, bf30, f3af8003), \
10574 X(_sev, bf40, f3af8004), \
10575 X(_sevl, bf50, f3af8005), \
10576 X(_udf, de00, f7f0a000)
10578 /* To catch errors in encoding functions, the codes are all offset by
10579 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10580 as 16-bit instructions. */
10581 #define X(a,b,c) T_MNEM##a
10582 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10585 #define X(a,b,c) 0x##b
10586 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10587 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10590 #define X(a,b,c) 0x##c
10591 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10592 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10593 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10597 /* Thumb instruction encoders, in alphabetical order. */
10599 /* ADDW or SUBW. */
10602 do_t_add_sub_w (void)
10606 Rd
= inst
.operands
[0].reg
;
10607 Rn
= inst
.operands
[1].reg
;
10609 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10610 is the SP-{plus,minus}-immediate form of the instruction. */
10612 constraint (Rd
== REG_PC
, BAD_PC
);
10614 reject_bad_reg (Rd
);
10616 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10617 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10620 /* Parse an add or subtract instruction. We get here with inst.instruction
10621 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10624 do_t_add_sub (void)
10628 Rd
= inst
.operands
[0].reg
;
10629 Rs
= (inst
.operands
[1].present
10630 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10631 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10634 set_it_insn_type_last ();
10636 if (unified_syntax
)
10639 bfd_boolean narrow
;
10642 flags
= (inst
.instruction
== T_MNEM_adds
10643 || inst
.instruction
== T_MNEM_subs
);
10645 narrow
= !in_it_block ();
10647 narrow
= in_it_block ();
10648 if (!inst
.operands
[2].isreg
)
10652 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10653 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10655 add
= (inst
.instruction
== T_MNEM_add
10656 || inst
.instruction
== T_MNEM_adds
);
10658 if (inst
.size_req
!= 4)
10660 /* Attempt to use a narrow opcode, with relaxation if
10662 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10663 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10664 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10665 opcode
= T_MNEM_add_sp
;
10666 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10667 opcode
= T_MNEM_add_pc
;
10668 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10671 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10673 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10677 inst
.instruction
= THUMB_OP16(opcode
);
10678 inst
.instruction
|= (Rd
<< 4) | Rs
;
10679 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10680 || (inst
.relocs
[0].type
10681 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
10683 if (inst
.size_req
== 2)
10684 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10686 inst
.relax
= opcode
;
10690 constraint (inst
.size_req
== 2, BAD_HIREG
);
10692 if (inst
.size_req
== 4
10693 || (inst
.size_req
!= 2 && !opcode
))
10695 constraint ((inst
.relocs
[0].type
10696 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
10697 && (inst
.relocs
[0].type
10698 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
10699 THUMB1_RELOC_ONLY
);
10702 constraint (add
, BAD_PC
);
10703 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10704 _("only SUBS PC, LR, #const allowed"));
10705 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10706 _("expression too complex"));
10707 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10708 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
10709 _("immediate value out of range"));
10710 inst
.instruction
= T2_SUBS_PC_LR
10711 | inst
.relocs
[0].exp
.X_add_number
;
10712 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10715 else if (Rs
== REG_PC
)
10717 /* Always use addw/subw. */
10718 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10719 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10723 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10724 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10727 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10729 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10731 inst
.instruction
|= Rd
<< 8;
10732 inst
.instruction
|= Rs
<< 16;
10737 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10738 unsigned int shift
= inst
.operands
[2].shift_kind
;
10740 Rn
= inst
.operands
[2].reg
;
10741 /* See if we can do this with a 16-bit instruction. */
10742 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10744 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10749 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10750 || inst
.instruction
== T_MNEM_add
)
10752 : T_OPCODE_SUB_R3
);
10753 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10757 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10759 /* Thumb-1 cores (except v6-M) require at least one high
10760 register in a narrow non flag setting add. */
10761 if (Rd
> 7 || Rn
> 7
10762 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10763 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10770 inst
.instruction
= T_OPCODE_ADD_HI
;
10771 inst
.instruction
|= (Rd
& 8) << 4;
10772 inst
.instruction
|= (Rd
& 7);
10773 inst
.instruction
|= Rn
<< 3;
10779 constraint (Rd
== REG_PC
, BAD_PC
);
10780 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10781 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10782 constraint (Rs
== REG_PC
, BAD_PC
);
10783 reject_bad_reg (Rn
);
10785 /* If we get here, it can't be done in 16 bits. */
10786 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10787 _("shift must be constant"));
10788 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10789 inst
.instruction
|= Rd
<< 8;
10790 inst
.instruction
|= Rs
<< 16;
10791 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10792 _("shift value over 3 not allowed in thumb mode"));
10793 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10794 _("only LSL shift allowed in thumb mode"));
10795 encode_thumb32_shifted_operand (2);
10800 constraint (inst
.instruction
== T_MNEM_adds
10801 || inst
.instruction
== T_MNEM_subs
,
10804 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10806 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10807 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10810 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10811 ? 0x0000 : 0x8000);
10812 inst
.instruction
|= (Rd
<< 4) | Rs
;
10813 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10817 Rn
= inst
.operands
[2].reg
;
10818 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10820 /* We now have Rd, Rs, and Rn set to registers. */
10821 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10823 /* Can't do this for SUB. */
10824 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10825 inst
.instruction
= T_OPCODE_ADD_HI
;
10826 inst
.instruction
|= (Rd
& 8) << 4;
10827 inst
.instruction
|= (Rd
& 7);
10829 inst
.instruction
|= Rn
<< 3;
10831 inst
.instruction
|= Rs
<< 3;
10833 constraint (1, _("dest must overlap one source register"));
10837 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10838 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10839 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10849 Rd
= inst
.operands
[0].reg
;
10850 reject_bad_reg (Rd
);
10852 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10854 /* Defer to section relaxation. */
10855 inst
.relax
= inst
.instruction
;
10856 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10857 inst
.instruction
|= Rd
<< 4;
10859 else if (unified_syntax
&& inst
.size_req
!= 2)
10861 /* Generate a 32-bit opcode. */
10862 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10863 inst
.instruction
|= Rd
<< 8;
10864 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10865 inst
.relocs
[0].pc_rel
= 1;
10869 /* Generate a 16-bit opcode. */
10870 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10871 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10872 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
10873 inst
.relocs
[0].pc_rel
= 1;
10874 inst
.instruction
|= Rd
<< 4;
10877 if (inst
.relocs
[0].exp
.X_op
== O_symbol
10878 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
10879 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
10880 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
10881 inst
.relocs
[0].exp
.X_add_number
+= 1;
10884 /* Arithmetic instructions for which there is just one 16-bit
10885 instruction encoding, and it allows only two low registers.
10886 For maximal compatibility with ARM syntax, we allow three register
10887 operands even when Thumb-32 instructions are not available, as long
10888 as the first two are identical. For instance, both "sbc r0,r1" and
10889 "sbc r0,r0,r1" are allowed. */
10895 Rd
= inst
.operands
[0].reg
;
10896 Rs
= (inst
.operands
[1].present
10897 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10898 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10899 Rn
= inst
.operands
[2].reg
;
10901 reject_bad_reg (Rd
);
10902 reject_bad_reg (Rs
);
10903 if (inst
.operands
[2].isreg
)
10904 reject_bad_reg (Rn
);
10906 if (unified_syntax
)
10908 if (!inst
.operands
[2].isreg
)
10910 /* For an immediate, we always generate a 32-bit opcode;
10911 section relaxation will shrink it later if possible. */
10912 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10913 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10914 inst
.instruction
|= Rd
<< 8;
10915 inst
.instruction
|= Rs
<< 16;
10916 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10920 bfd_boolean narrow
;
10922 /* See if we can do this with a 16-bit instruction. */
10923 if (THUMB_SETS_FLAGS (inst
.instruction
))
10924 narrow
= !in_it_block ();
10926 narrow
= in_it_block ();
10928 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10930 if (inst
.operands
[2].shifted
)
10932 if (inst
.size_req
== 4)
10938 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10939 inst
.instruction
|= Rd
;
10940 inst
.instruction
|= Rn
<< 3;
10944 /* If we get here, it can't be done in 16 bits. */
10945 constraint (inst
.operands
[2].shifted
10946 && inst
.operands
[2].immisreg
,
10947 _("shift must be constant"));
10948 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10949 inst
.instruction
|= Rd
<< 8;
10950 inst
.instruction
|= Rs
<< 16;
10951 encode_thumb32_shifted_operand (2);
10956 /* On its face this is a lie - the instruction does set the
10957 flags. However, the only supported mnemonic in this mode
10958 says it doesn't. */
10959 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10961 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10962 _("unshifted register required"));
10963 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10964 constraint (Rd
!= Rs
,
10965 _("dest and source1 must be the same register"));
10967 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10968 inst
.instruction
|= Rd
;
10969 inst
.instruction
|= Rn
<< 3;
10973 /* Similarly, but for instructions where the arithmetic operation is
10974 commutative, so we can allow either of them to be different from
10975 the destination operand in a 16-bit instruction. For instance, all
10976 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10983 Rd
= inst
.operands
[0].reg
;
10984 Rs
= (inst
.operands
[1].present
10985 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10986 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10987 Rn
= inst
.operands
[2].reg
;
10989 reject_bad_reg (Rd
);
10990 reject_bad_reg (Rs
);
10991 if (inst
.operands
[2].isreg
)
10992 reject_bad_reg (Rn
);
10994 if (unified_syntax
)
10996 if (!inst
.operands
[2].isreg
)
10998 /* For an immediate, we always generate a 32-bit opcode;
10999 section relaxation will shrink it later if possible. */
11000 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11001 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11002 inst
.instruction
|= Rd
<< 8;
11003 inst
.instruction
|= Rs
<< 16;
11004 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11008 bfd_boolean narrow
;
11010 /* See if we can do this with a 16-bit instruction. */
11011 if (THUMB_SETS_FLAGS (inst
.instruction
))
11012 narrow
= !in_it_block ();
11014 narrow
= in_it_block ();
11016 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11018 if (inst
.operands
[2].shifted
)
11020 if (inst
.size_req
== 4)
11027 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11028 inst
.instruction
|= Rd
;
11029 inst
.instruction
|= Rn
<< 3;
11034 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11035 inst
.instruction
|= Rd
;
11036 inst
.instruction
|= Rs
<< 3;
11041 /* If we get here, it can't be done in 16 bits. */
11042 constraint (inst
.operands
[2].shifted
11043 && inst
.operands
[2].immisreg
,
11044 _("shift must be constant"));
11045 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11046 inst
.instruction
|= Rd
<< 8;
11047 inst
.instruction
|= Rs
<< 16;
11048 encode_thumb32_shifted_operand (2);
11053 /* On its face this is a lie - the instruction does set the
11054 flags. However, the only supported mnemonic in this mode
11055 says it doesn't. */
11056 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11058 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11059 _("unshifted register required"));
11060 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11062 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11063 inst
.instruction
|= Rd
;
11066 inst
.instruction
|= Rn
<< 3;
11068 inst
.instruction
|= Rs
<< 3;
11070 constraint (1, _("dest must overlap one source register"));
11078 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11079 constraint (msb
> 32, _("bit-field extends past end of register"));
11080 /* The instruction encoding stores the LSB and MSB,
11081 not the LSB and width. */
11082 Rd
= inst
.operands
[0].reg
;
11083 reject_bad_reg (Rd
);
11084 inst
.instruction
|= Rd
<< 8;
11085 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11086 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11087 inst
.instruction
|= msb
- 1;
11096 Rd
= inst
.operands
[0].reg
;
11097 reject_bad_reg (Rd
);
11099 /* #0 in second position is alternative syntax for bfc, which is
11100 the same instruction but with REG_PC in the Rm field. */
11101 if (!inst
.operands
[1].isreg
)
11105 Rn
= inst
.operands
[1].reg
;
11106 reject_bad_reg (Rn
);
11109 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11110 constraint (msb
> 32, _("bit-field extends past end of register"));
11111 /* The instruction encoding stores the LSB and MSB,
11112 not the LSB and width. */
11113 inst
.instruction
|= Rd
<< 8;
11114 inst
.instruction
|= Rn
<< 16;
11115 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11116 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11117 inst
.instruction
|= msb
- 1;
11125 Rd
= inst
.operands
[0].reg
;
11126 Rn
= inst
.operands
[1].reg
;
11128 reject_bad_reg (Rd
);
11129 reject_bad_reg (Rn
);
11131 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11132 _("bit-field extends past end of register"));
11133 inst
.instruction
|= Rd
<< 8;
11134 inst
.instruction
|= Rn
<< 16;
11135 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11136 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11137 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11140 /* ARM V5 Thumb BLX (argument parse)
11141 BLX <target_addr> which is BLX(1)
11142 BLX <Rm> which is BLX(2)
11143 Unfortunately, there are two different opcodes for this mnemonic.
11144 So, the insns[].value is not used, and the code here zaps values
11145 into inst.instruction.
11147 ??? How to take advantage of the additional two bits of displacement
11148 available in Thumb32 mode? Need new relocation? */
11153 set_it_insn_type_last ();
11155 if (inst
.operands
[0].isreg
)
11157 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11158 /* We have a register, so this is BLX(2). */
11159 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11163 /* No register. This must be BLX(1). */
11164 inst
.instruction
= 0xf000e800;
11165 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11174 bfd_reloc_code_real_type reloc
;
11177 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11179 if (in_it_block ())
11181 /* Conditional branches inside IT blocks are encoded as unconditional
11183 cond
= COND_ALWAYS
;
11188 if (cond
!= COND_ALWAYS
)
11189 opcode
= T_MNEM_bcond
;
11191 opcode
= inst
.instruction
;
11194 && (inst
.size_req
== 4
11195 || (inst
.size_req
!= 2
11196 && (inst
.operands
[0].hasreloc
11197 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11199 inst
.instruction
= THUMB_OP32(opcode
);
11200 if (cond
== COND_ALWAYS
)
11201 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11205 _("selected architecture does not support "
11206 "wide conditional branch instruction"));
11208 gas_assert (cond
!= 0xF);
11209 inst
.instruction
|= cond
<< 22;
11210 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11215 inst
.instruction
= THUMB_OP16(opcode
);
11216 if (cond
== COND_ALWAYS
)
11217 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11220 inst
.instruction
|= cond
<< 8;
11221 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11223 /* Allow section relaxation. */
11224 if (unified_syntax
&& inst
.size_req
!= 2)
11225 inst
.relax
= opcode
;
11227 inst
.relocs
[0].type
= reloc
;
11228 inst
.relocs
[0].pc_rel
= 1;
11231 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11232 between the two is the maximum immediate allowed - which is passed in
11235 do_t_bkpt_hlt1 (int range
)
11237 constraint (inst
.cond
!= COND_ALWAYS
,
11238 _("instruction is always unconditional"));
11239 if (inst
.operands
[0].present
)
11241 constraint (inst
.operands
[0].imm
> range
,
11242 _("immediate value out of range"));
11243 inst
.instruction
|= inst
.operands
[0].imm
;
11246 set_it_insn_type (NEUTRAL_IT_INSN
);
11252 do_t_bkpt_hlt1 (63);
11258 do_t_bkpt_hlt1 (255);
11262 do_t_branch23 (void)
11264 set_it_insn_type_last ();
11265 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11267 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11268 this file. We used to simply ignore the PLT reloc type here --
11269 the branch encoding is now needed to deal with TLSCALL relocs.
11270 So if we see a PLT reloc now, put it back to how it used to be to
11271 keep the preexisting behaviour. */
11272 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11273 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11275 #if defined(OBJ_COFF)
11276 /* If the destination of the branch is a defined symbol which does not have
11277 the THUMB_FUNC attribute, then we must be calling a function which has
11278 the (interfacearm) attribute. We look for the Thumb entry point to that
11279 function and change the branch to refer to that function instead. */
11280 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11281 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11282 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11283 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11284 inst
.relocs
[0].exp
.X_add_symbol
11285 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11292 set_it_insn_type_last ();
11293 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11294 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11295 should cause the alignment to be checked once it is known. This is
11296 because BX PC only works if the instruction is word aligned. */
11304 set_it_insn_type_last ();
11305 Rm
= inst
.operands
[0].reg
;
11306 reject_bad_reg (Rm
);
11307 inst
.instruction
|= Rm
<< 16;
11316 Rd
= inst
.operands
[0].reg
;
11317 Rm
= inst
.operands
[1].reg
;
11319 reject_bad_reg (Rd
);
11320 reject_bad_reg (Rm
);
11322 inst
.instruction
|= Rd
<< 8;
11323 inst
.instruction
|= Rm
<< 16;
11324 inst
.instruction
|= Rm
;
11330 set_it_insn_type (OUTSIDE_IT_INSN
);
11336 set_it_insn_type (OUTSIDE_IT_INSN
);
11337 inst
.instruction
|= inst
.operands
[0].imm
;
11343 set_it_insn_type (OUTSIDE_IT_INSN
);
11345 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11346 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11348 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11349 inst
.instruction
= 0xf3af8000;
11350 inst
.instruction
|= imod
<< 9;
11351 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11352 if (inst
.operands
[1].present
)
11353 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11357 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11358 && (inst
.operands
[0].imm
& 4),
11359 _("selected processor does not support 'A' form "
11360 "of this instruction"));
11361 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11362 _("Thumb does not support the 2-argument "
11363 "form of this instruction"));
11364 inst
.instruction
|= inst
.operands
[0].imm
;
11368 /* THUMB CPY instruction (argument parse). */
11373 if (inst
.size_req
== 4)
11375 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11376 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11377 inst
.instruction
|= inst
.operands
[1].reg
;
11381 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11382 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11383 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11390 set_it_insn_type (OUTSIDE_IT_INSN
);
11391 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11392 inst
.instruction
|= inst
.operands
[0].reg
;
11393 inst
.relocs
[0].pc_rel
= 1;
11394 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11400 inst
.instruction
|= inst
.operands
[0].imm
;
11406 unsigned Rd
, Rn
, Rm
;
11408 Rd
= inst
.operands
[0].reg
;
11409 Rn
= (inst
.operands
[1].present
11410 ? inst
.operands
[1].reg
: Rd
);
11411 Rm
= inst
.operands
[2].reg
;
11413 reject_bad_reg (Rd
);
11414 reject_bad_reg (Rn
);
11415 reject_bad_reg (Rm
);
11417 inst
.instruction
|= Rd
<< 8;
11418 inst
.instruction
|= Rn
<< 16;
11419 inst
.instruction
|= Rm
;
11425 if (unified_syntax
&& inst
.size_req
== 4)
11426 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11434 unsigned int cond
= inst
.operands
[0].imm
;
11436 set_it_insn_type (IT_INSN
);
11437 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11439 now_it
.warn_deprecated
= FALSE
;
11441 /* If the condition is a negative condition, invert the mask. */
11442 if ((cond
& 0x1) == 0x0)
11444 unsigned int mask
= inst
.instruction
& 0x000f;
11446 if ((mask
& 0x7) == 0)
11448 /* No conversion needed. */
11449 now_it
.block_length
= 1;
11451 else if ((mask
& 0x3) == 0)
11454 now_it
.block_length
= 2;
11456 else if ((mask
& 0x1) == 0)
11459 now_it
.block_length
= 3;
11464 now_it
.block_length
= 4;
11467 inst
.instruction
&= 0xfff0;
11468 inst
.instruction
|= mask
;
11471 inst
.instruction
|= cond
<< 4;
11474 /* Helper function used for both push/pop and ldm/stm. */
11476 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11480 load
= (inst
.instruction
& (1 << 20)) != 0;
11482 if (mask
& (1 << 13))
11483 inst
.error
= _("SP not allowed in register list");
11485 if ((mask
& (1 << base
)) != 0
11487 inst
.error
= _("having the base register in the register list when "
11488 "using write back is UNPREDICTABLE");
11492 if (mask
& (1 << 15))
11494 if (mask
& (1 << 14))
11495 inst
.error
= _("LR and PC should not both be in register list");
11497 set_it_insn_type_last ();
11502 if (mask
& (1 << 15))
11503 inst
.error
= _("PC not allowed in register list");
11506 if ((mask
& (mask
- 1)) == 0)
11508 /* Single register transfers implemented as str/ldr. */
11511 if (inst
.instruction
& (1 << 23))
11512 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11514 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11518 if (inst
.instruction
& (1 << 23))
11519 inst
.instruction
= 0x00800000; /* ia -> [base] */
11521 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11524 inst
.instruction
|= 0xf8400000;
11526 inst
.instruction
|= 0x00100000;
11528 mask
= ffs (mask
) - 1;
11531 else if (writeback
)
11532 inst
.instruction
|= WRITE_BACK
;
11534 inst
.instruction
|= mask
;
11535 inst
.instruction
|= base
<< 16;
11541 /* This really doesn't seem worth it. */
11542 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
11543 _("expression too complex"));
11544 constraint (inst
.operands
[1].writeback
,
11545 _("Thumb load/store multiple does not support {reglist}^"));
11547 if (unified_syntax
)
11549 bfd_boolean narrow
;
11553 /* See if we can use a 16-bit instruction. */
11554 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11555 && inst
.size_req
!= 4
11556 && !(inst
.operands
[1].imm
& ~0xff))
11558 mask
= 1 << inst
.operands
[0].reg
;
11560 if (inst
.operands
[0].reg
<= 7)
11562 if (inst
.instruction
== T_MNEM_stmia
11563 ? inst
.operands
[0].writeback
11564 : (inst
.operands
[0].writeback
11565 == !(inst
.operands
[1].imm
& mask
)))
11567 if (inst
.instruction
== T_MNEM_stmia
11568 && (inst
.operands
[1].imm
& mask
)
11569 && (inst
.operands
[1].imm
& (mask
- 1)))
11570 as_warn (_("value stored for r%d is UNKNOWN"),
11571 inst
.operands
[0].reg
);
11573 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11574 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11575 inst
.instruction
|= inst
.operands
[1].imm
;
11578 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11580 /* This means 1 register in reg list one of 3 situations:
11581 1. Instruction is stmia, but without writeback.
11582 2. lmdia without writeback, but with Rn not in
11584 3. ldmia with writeback, but with Rn in reglist.
11585 Case 3 is UNPREDICTABLE behaviour, so we handle
11586 case 1 and 2 which can be converted into a 16-bit
11587 str or ldr. The SP cases are handled below. */
11588 unsigned long opcode
;
11589 /* First, record an error for Case 3. */
11590 if (inst
.operands
[1].imm
& mask
11591 && inst
.operands
[0].writeback
)
11593 _("having the base register in the register list when "
11594 "using write back is UNPREDICTABLE");
11596 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11598 inst
.instruction
= THUMB_OP16 (opcode
);
11599 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11600 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11604 else if (inst
.operands
[0] .reg
== REG_SP
)
11606 if (inst
.operands
[0].writeback
)
11609 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11610 ? T_MNEM_push
: T_MNEM_pop
);
11611 inst
.instruction
|= inst
.operands
[1].imm
;
11614 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11617 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11618 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11619 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11627 if (inst
.instruction
< 0xffff)
11628 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11630 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11631 inst
.operands
[0].writeback
);
11636 constraint (inst
.operands
[0].reg
> 7
11637 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11638 constraint (inst
.instruction
!= T_MNEM_ldmia
11639 && inst
.instruction
!= T_MNEM_stmia
,
11640 _("Thumb-2 instruction only valid in unified syntax"));
11641 if (inst
.instruction
== T_MNEM_stmia
)
11643 if (!inst
.operands
[0].writeback
)
11644 as_warn (_("this instruction will write back the base register"));
11645 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11646 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11647 as_warn (_("value stored for r%d is UNKNOWN"),
11648 inst
.operands
[0].reg
);
11652 if (!inst
.operands
[0].writeback
11653 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11654 as_warn (_("this instruction will write back the base register"));
11655 else if (inst
.operands
[0].writeback
11656 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11657 as_warn (_("this instruction will not write back the base register"));
11660 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11661 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11662 inst
.instruction
|= inst
.operands
[1].imm
;
11669 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11670 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11671 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11672 || inst
.operands
[1].negative
,
11675 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11678 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11679 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11685 if (!inst
.operands
[1].present
)
11687 constraint (inst
.operands
[0].reg
== REG_LR
,
11688 _("r14 not allowed as first register "
11689 "when second register is omitted"));
11690 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11692 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11696 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11697 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11703 unsigned long opcode
;
11706 if (inst
.operands
[0].isreg
11707 && !inst
.operands
[0].preind
11708 && inst
.operands
[0].reg
== REG_PC
)
11709 set_it_insn_type_last ();
11711 opcode
= inst
.instruction
;
11712 if (unified_syntax
)
11714 if (!inst
.operands
[1].isreg
)
11716 if (opcode
<= 0xffff)
11717 inst
.instruction
= THUMB_OP32 (opcode
);
11718 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11721 if (inst
.operands
[1].isreg
11722 && !inst
.operands
[1].writeback
11723 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11724 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11725 && opcode
<= 0xffff
11726 && inst
.size_req
!= 4)
11728 /* Insn may have a 16-bit form. */
11729 Rn
= inst
.operands
[1].reg
;
11730 if (inst
.operands
[1].immisreg
)
11732 inst
.instruction
= THUMB_OP16 (opcode
);
11734 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11736 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11737 reject_bad_reg (inst
.operands
[1].imm
);
11739 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11740 && opcode
!= T_MNEM_ldrsb
)
11741 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11742 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11749 if (inst
.relocs
[0].pc_rel
)
11750 opcode
= T_MNEM_ldr_pc2
;
11752 opcode
= T_MNEM_ldr_pc
;
11756 if (opcode
== T_MNEM_ldr
)
11757 opcode
= T_MNEM_ldr_sp
;
11759 opcode
= T_MNEM_str_sp
;
11761 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11765 inst
.instruction
= inst
.operands
[0].reg
;
11766 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11768 inst
.instruction
|= THUMB_OP16 (opcode
);
11769 if (inst
.size_req
== 2)
11770 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11772 inst
.relax
= opcode
;
11776 /* Definitely a 32-bit variant. */
11778 /* Warning for Erratum 752419. */
11779 if (opcode
== T_MNEM_ldr
11780 && inst
.operands
[0].reg
== REG_SP
11781 && inst
.operands
[1].writeback
== 1
11782 && !inst
.operands
[1].immisreg
)
11784 if (no_cpu_selected ()
11785 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11786 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11787 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11788 as_warn (_("This instruction may be unpredictable "
11789 "if executed on M-profile cores "
11790 "with interrupts enabled."));
11793 /* Do some validations regarding addressing modes. */
11794 if (inst
.operands
[1].immisreg
)
11795 reject_bad_reg (inst
.operands
[1].imm
);
11797 constraint (inst
.operands
[1].writeback
== 1
11798 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11801 inst
.instruction
= THUMB_OP32 (opcode
);
11802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11803 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11804 check_ldr_r15_aligned ();
11808 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11810 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11812 /* Only [Rn,Rm] is acceptable. */
11813 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11814 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11815 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11816 || inst
.operands
[1].negative
,
11817 _("Thumb does not support this addressing mode"));
11818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11822 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11823 if (!inst
.operands
[1].isreg
)
11824 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11827 constraint (!inst
.operands
[1].preind
11828 || inst
.operands
[1].shifted
11829 || inst
.operands
[1].writeback
,
11830 _("Thumb does not support this addressing mode"));
11831 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11833 constraint (inst
.instruction
& 0x0600,
11834 _("byte or halfword not valid for base register"));
11835 constraint (inst
.operands
[1].reg
== REG_PC
11836 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11837 _("r15 based store not allowed"));
11838 constraint (inst
.operands
[1].immisreg
,
11839 _("invalid base register for register offset"));
11841 if (inst
.operands
[1].reg
== REG_PC
)
11842 inst
.instruction
= T_OPCODE_LDR_PC
;
11843 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11844 inst
.instruction
= T_OPCODE_LDR_SP
;
11846 inst
.instruction
= T_OPCODE_STR_SP
;
11848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11849 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11853 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11854 if (!inst
.operands
[1].immisreg
)
11856 /* Immediate offset. */
11857 inst
.instruction
|= inst
.operands
[0].reg
;
11858 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11859 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11863 /* Register offset. */
11864 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11865 constraint (inst
.operands
[1].negative
,
11866 _("Thumb does not support this addressing mode"));
11869 switch (inst
.instruction
)
11871 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11872 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11873 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11874 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11875 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11876 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11877 case 0x5600 /* ldrsb */:
11878 case 0x5e00 /* ldrsh */: break;
11882 inst
.instruction
|= inst
.operands
[0].reg
;
11883 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11884 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11890 if (!inst
.operands
[1].present
)
11892 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11893 constraint (inst
.operands
[0].reg
== REG_LR
,
11894 _("r14 not allowed here"));
11895 constraint (inst
.operands
[0].reg
== REG_R12
,
11896 _("r12 not allowed here"));
11899 if (inst
.operands
[2].writeback
11900 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11901 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11902 as_warn (_("base register written back, and overlaps "
11903 "one of transfer registers"));
11905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11906 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11907 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11914 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11920 unsigned Rd
, Rn
, Rm
, Ra
;
11922 Rd
= inst
.operands
[0].reg
;
11923 Rn
= inst
.operands
[1].reg
;
11924 Rm
= inst
.operands
[2].reg
;
11925 Ra
= inst
.operands
[3].reg
;
11927 reject_bad_reg (Rd
);
11928 reject_bad_reg (Rn
);
11929 reject_bad_reg (Rm
);
11930 reject_bad_reg (Ra
);
11932 inst
.instruction
|= Rd
<< 8;
11933 inst
.instruction
|= Rn
<< 16;
11934 inst
.instruction
|= Rm
;
11935 inst
.instruction
|= Ra
<< 12;
11941 unsigned RdLo
, RdHi
, Rn
, Rm
;
11943 RdLo
= inst
.operands
[0].reg
;
11944 RdHi
= inst
.operands
[1].reg
;
11945 Rn
= inst
.operands
[2].reg
;
11946 Rm
= inst
.operands
[3].reg
;
11948 reject_bad_reg (RdLo
);
11949 reject_bad_reg (RdHi
);
11950 reject_bad_reg (Rn
);
11951 reject_bad_reg (Rm
);
11953 inst
.instruction
|= RdLo
<< 12;
11954 inst
.instruction
|= RdHi
<< 8;
11955 inst
.instruction
|= Rn
<< 16;
11956 inst
.instruction
|= Rm
;
11960 do_t_mov_cmp (void)
11964 Rn
= inst
.operands
[0].reg
;
11965 Rm
= inst
.operands
[1].reg
;
11968 set_it_insn_type_last ();
11970 if (unified_syntax
)
11972 int r0off
= (inst
.instruction
== T_MNEM_mov
11973 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11974 unsigned long opcode
;
11975 bfd_boolean narrow
;
11976 bfd_boolean low_regs
;
11978 low_regs
= (Rn
<= 7 && Rm
<= 7);
11979 opcode
= inst
.instruction
;
11980 if (in_it_block ())
11981 narrow
= opcode
!= T_MNEM_movs
;
11983 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11984 if (inst
.size_req
== 4
11985 || inst
.operands
[1].shifted
)
11988 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11989 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11990 && !inst
.operands
[1].shifted
11994 inst
.instruction
= T2_SUBS_PC_LR
;
11998 if (opcode
== T_MNEM_cmp
)
12000 constraint (Rn
== REG_PC
, BAD_PC
);
12003 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12005 warn_deprecated_sp (Rm
);
12006 /* R15 was documented as a valid choice for Rm in ARMv6,
12007 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12008 tools reject R15, so we do too. */
12009 constraint (Rm
== REG_PC
, BAD_PC
);
12012 reject_bad_reg (Rm
);
12014 else if (opcode
== T_MNEM_mov
12015 || opcode
== T_MNEM_movs
)
12017 if (inst
.operands
[1].isreg
)
12019 if (opcode
== T_MNEM_movs
)
12021 reject_bad_reg (Rn
);
12022 reject_bad_reg (Rm
);
12026 /* This is mov.n. */
12027 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12028 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12030 as_tsktsk (_("Use of r%u as a source register is "
12031 "deprecated when r%u is the destination "
12032 "register."), Rm
, Rn
);
12037 /* This is mov.w. */
12038 constraint (Rn
== REG_PC
, BAD_PC
);
12039 constraint (Rm
== REG_PC
, BAD_PC
);
12040 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12041 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12045 reject_bad_reg (Rn
);
12048 if (!inst
.operands
[1].isreg
)
12050 /* Immediate operand. */
12051 if (!in_it_block () && opcode
== T_MNEM_mov
)
12053 if (low_regs
&& narrow
)
12055 inst
.instruction
= THUMB_OP16 (opcode
);
12056 inst
.instruction
|= Rn
<< 8;
12057 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12058 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12060 if (inst
.size_req
== 2)
12061 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12063 inst
.relax
= opcode
;
12068 constraint ((inst
.relocs
[0].type
12069 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12070 && (inst
.relocs
[0].type
12071 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12072 THUMB1_RELOC_ONLY
);
12074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12075 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12076 inst
.instruction
|= Rn
<< r0off
;
12077 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12080 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12081 && (inst
.instruction
== T_MNEM_mov
12082 || inst
.instruction
== T_MNEM_movs
))
12084 /* Register shifts are encoded as separate shift instructions. */
12085 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12087 if (in_it_block ())
12092 if (inst
.size_req
== 4)
12095 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12101 switch (inst
.operands
[1].shift_kind
)
12104 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12107 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12110 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12113 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12119 inst
.instruction
= opcode
;
12122 inst
.instruction
|= Rn
;
12123 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12128 inst
.instruction
|= CONDS_BIT
;
12130 inst
.instruction
|= Rn
<< 8;
12131 inst
.instruction
|= Rm
<< 16;
12132 inst
.instruction
|= inst
.operands
[1].imm
;
12137 /* Some mov with immediate shift have narrow variants.
12138 Register shifts are handled above. */
12139 if (low_regs
&& inst
.operands
[1].shifted
12140 && (inst
.instruction
== T_MNEM_mov
12141 || inst
.instruction
== T_MNEM_movs
))
12143 if (in_it_block ())
12144 narrow
= (inst
.instruction
== T_MNEM_mov
);
12146 narrow
= (inst
.instruction
== T_MNEM_movs
);
12151 switch (inst
.operands
[1].shift_kind
)
12153 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12154 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12155 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12156 default: narrow
= FALSE
; break;
12162 inst
.instruction
|= Rn
;
12163 inst
.instruction
|= Rm
<< 3;
12164 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12168 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12169 inst
.instruction
|= Rn
<< r0off
;
12170 encode_thumb32_shifted_operand (1);
12174 switch (inst
.instruction
)
12177 /* In v4t or v5t a move of two lowregs produces unpredictable
12178 results. Don't allow this. */
12181 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12182 "MOV Rd, Rs with two low registers is not "
12183 "permitted on this architecture");
12184 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12188 inst
.instruction
= T_OPCODE_MOV_HR
;
12189 inst
.instruction
|= (Rn
& 0x8) << 4;
12190 inst
.instruction
|= (Rn
& 0x7);
12191 inst
.instruction
|= Rm
<< 3;
12195 /* We know we have low registers at this point.
12196 Generate LSLS Rd, Rs, #0. */
12197 inst
.instruction
= T_OPCODE_LSL_I
;
12198 inst
.instruction
|= Rn
;
12199 inst
.instruction
|= Rm
<< 3;
12205 inst
.instruction
= T_OPCODE_CMP_LR
;
12206 inst
.instruction
|= Rn
;
12207 inst
.instruction
|= Rm
<< 3;
12211 inst
.instruction
= T_OPCODE_CMP_HR
;
12212 inst
.instruction
|= (Rn
& 0x8) << 4;
12213 inst
.instruction
|= (Rn
& 0x7);
12214 inst
.instruction
|= Rm
<< 3;
12221 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12223 /* PR 10443: Do not silently ignore shifted operands. */
12224 constraint (inst
.operands
[1].shifted
,
12225 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12227 if (inst
.operands
[1].isreg
)
12229 if (Rn
< 8 && Rm
< 8)
12231 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12232 since a MOV instruction produces unpredictable results. */
12233 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12234 inst
.instruction
= T_OPCODE_ADD_I3
;
12236 inst
.instruction
= T_OPCODE_CMP_LR
;
12238 inst
.instruction
|= Rn
;
12239 inst
.instruction
|= Rm
<< 3;
12243 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12244 inst
.instruction
= T_OPCODE_MOV_HR
;
12246 inst
.instruction
= T_OPCODE_CMP_HR
;
12252 constraint (Rn
> 7,
12253 _("only lo regs allowed with immediate"));
12254 inst
.instruction
|= Rn
<< 8;
12255 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12266 top
= (inst
.instruction
& 0x00800000) != 0;
12267 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12269 constraint (top
, _(":lower16: not allowed in this instruction"));
12270 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12272 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12274 constraint (!top
, _(":upper16: not allowed in this instruction"));
12275 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12278 Rd
= inst
.operands
[0].reg
;
12279 reject_bad_reg (Rd
);
12281 inst
.instruction
|= Rd
<< 8;
12282 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12284 imm
= inst
.relocs
[0].exp
.X_add_number
;
12285 inst
.instruction
|= (imm
& 0xf000) << 4;
12286 inst
.instruction
|= (imm
& 0x0800) << 15;
12287 inst
.instruction
|= (imm
& 0x0700) << 4;
12288 inst
.instruction
|= (imm
& 0x00ff);
12293 do_t_mvn_tst (void)
12297 Rn
= inst
.operands
[0].reg
;
12298 Rm
= inst
.operands
[1].reg
;
12300 if (inst
.instruction
== T_MNEM_cmp
12301 || inst
.instruction
== T_MNEM_cmn
)
12302 constraint (Rn
== REG_PC
, BAD_PC
);
12304 reject_bad_reg (Rn
);
12305 reject_bad_reg (Rm
);
12307 if (unified_syntax
)
12309 int r0off
= (inst
.instruction
== T_MNEM_mvn
12310 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12311 bfd_boolean narrow
;
12313 if (inst
.size_req
== 4
12314 || inst
.instruction
> 0xffff
12315 || inst
.operands
[1].shifted
12316 || Rn
> 7 || Rm
> 7)
12318 else if (inst
.instruction
== T_MNEM_cmn
12319 || inst
.instruction
== T_MNEM_tst
)
12321 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12322 narrow
= !in_it_block ();
12324 narrow
= in_it_block ();
12326 if (!inst
.operands
[1].isreg
)
12328 /* For an immediate, we always generate a 32-bit opcode;
12329 section relaxation will shrink it later if possible. */
12330 if (inst
.instruction
< 0xffff)
12331 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12332 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12333 inst
.instruction
|= Rn
<< r0off
;
12334 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12338 /* See if we can do this with a 16-bit instruction. */
12341 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12342 inst
.instruction
|= Rn
;
12343 inst
.instruction
|= Rm
<< 3;
12347 constraint (inst
.operands
[1].shifted
12348 && inst
.operands
[1].immisreg
,
12349 _("shift must be constant"));
12350 if (inst
.instruction
< 0xffff)
12351 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12352 inst
.instruction
|= Rn
<< r0off
;
12353 encode_thumb32_shifted_operand (1);
12359 constraint (inst
.instruction
> 0xffff
12360 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12361 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12362 _("unshifted register required"));
12363 constraint (Rn
> 7 || Rm
> 7,
12366 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12367 inst
.instruction
|= Rn
;
12368 inst
.instruction
|= Rm
<< 3;
12377 if (do_vfp_nsyn_mrs () == SUCCESS
)
12380 Rd
= inst
.operands
[0].reg
;
12381 reject_bad_reg (Rd
);
12382 inst
.instruction
|= Rd
<< 8;
12384 if (inst
.operands
[1].isreg
)
12386 unsigned br
= inst
.operands
[1].reg
;
12387 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12388 as_bad (_("bad register for mrs"));
12390 inst
.instruction
|= br
& (0xf << 16);
12391 inst
.instruction
|= (br
& 0x300) >> 4;
12392 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12396 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12398 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12400 /* PR gas/12698: The constraint is only applied for m_profile.
12401 If the user has specified -march=all, we want to ignore it as
12402 we are building for any CPU type, including non-m variants. */
12403 bfd_boolean m_profile
=
12404 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12405 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12406 "not support requested special purpose register"));
12409 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12411 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12412 _("'APSR', 'CPSR' or 'SPSR' expected"));
12414 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12415 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12416 inst
.instruction
|= 0xf0000;
12426 if (do_vfp_nsyn_msr () == SUCCESS
)
12429 constraint (!inst
.operands
[1].isreg
,
12430 _("Thumb encoding does not support an immediate here"));
12432 if (inst
.operands
[0].isreg
)
12433 flags
= (int)(inst
.operands
[0].reg
);
12435 flags
= inst
.operands
[0].imm
;
12437 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12439 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12441 /* PR gas/12698: The constraint is only applied for m_profile.
12442 If the user has specified -march=all, we want to ignore it as
12443 we are building for any CPU type, including non-m variants. */
12444 bfd_boolean m_profile
=
12445 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12446 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12447 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12448 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12449 && bits
!= PSR_f
)) && m_profile
,
12450 _("selected processor does not support requested special "
12451 "purpose register"));
12454 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12455 "requested special purpose register"));
12457 Rn
= inst
.operands
[1].reg
;
12458 reject_bad_reg (Rn
);
12460 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12461 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12462 inst
.instruction
|= (flags
& 0x300) >> 4;
12463 inst
.instruction
|= (flags
& 0xff);
12464 inst
.instruction
|= Rn
<< 16;
12470 bfd_boolean narrow
;
12471 unsigned Rd
, Rn
, Rm
;
12473 if (!inst
.operands
[2].present
)
12474 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12476 Rd
= inst
.operands
[0].reg
;
12477 Rn
= inst
.operands
[1].reg
;
12478 Rm
= inst
.operands
[2].reg
;
12480 if (unified_syntax
)
12482 if (inst
.size_req
== 4
12488 else if (inst
.instruction
== T_MNEM_muls
)
12489 narrow
= !in_it_block ();
12491 narrow
= in_it_block ();
12495 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12496 constraint (Rn
> 7 || Rm
> 7,
12503 /* 16-bit MULS/Conditional MUL. */
12504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12505 inst
.instruction
|= Rd
;
12508 inst
.instruction
|= Rm
<< 3;
12510 inst
.instruction
|= Rn
<< 3;
12512 constraint (1, _("dest must overlap one source register"));
12516 constraint (inst
.instruction
!= T_MNEM_mul
,
12517 _("Thumb-2 MUL must not set flags"));
12519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12520 inst
.instruction
|= Rd
<< 8;
12521 inst
.instruction
|= Rn
<< 16;
12522 inst
.instruction
|= Rm
<< 0;
12524 reject_bad_reg (Rd
);
12525 reject_bad_reg (Rn
);
12526 reject_bad_reg (Rm
);
12533 unsigned RdLo
, RdHi
, Rn
, Rm
;
12535 RdLo
= inst
.operands
[0].reg
;
12536 RdHi
= inst
.operands
[1].reg
;
12537 Rn
= inst
.operands
[2].reg
;
12538 Rm
= inst
.operands
[3].reg
;
12540 reject_bad_reg (RdLo
);
12541 reject_bad_reg (RdHi
);
12542 reject_bad_reg (Rn
);
12543 reject_bad_reg (Rm
);
12545 inst
.instruction
|= RdLo
<< 12;
12546 inst
.instruction
|= RdHi
<< 8;
12547 inst
.instruction
|= Rn
<< 16;
12548 inst
.instruction
|= Rm
;
12551 as_tsktsk (_("rdhi and rdlo must be different"));
12557 set_it_insn_type (NEUTRAL_IT_INSN
);
12559 if (unified_syntax
)
12561 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12564 inst
.instruction
|= inst
.operands
[0].imm
;
12568 /* PR9722: Check for Thumb2 availability before
12569 generating a thumb2 nop instruction. */
12570 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12572 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12573 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12576 inst
.instruction
= 0x46c0;
12581 constraint (inst
.operands
[0].present
,
12582 _("Thumb does not support NOP with hints"));
12583 inst
.instruction
= 0x46c0;
12590 if (unified_syntax
)
12592 bfd_boolean narrow
;
12594 if (THUMB_SETS_FLAGS (inst
.instruction
))
12595 narrow
= !in_it_block ();
12597 narrow
= in_it_block ();
12598 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12600 if (inst
.size_req
== 4)
12605 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12606 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12611 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12612 inst
.instruction
|= inst
.operands
[0].reg
;
12613 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12618 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12620 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12623 inst
.instruction
|= inst
.operands
[0].reg
;
12624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12633 Rd
= inst
.operands
[0].reg
;
12634 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12636 reject_bad_reg (Rd
);
12637 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12638 reject_bad_reg (Rn
);
12640 inst
.instruction
|= Rd
<< 8;
12641 inst
.instruction
|= Rn
<< 16;
12643 if (!inst
.operands
[2].isreg
)
12645 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12646 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12652 Rm
= inst
.operands
[2].reg
;
12653 reject_bad_reg (Rm
);
12655 constraint (inst
.operands
[2].shifted
12656 && inst
.operands
[2].immisreg
,
12657 _("shift must be constant"));
12658 encode_thumb32_shifted_operand (2);
12665 unsigned Rd
, Rn
, Rm
;
12667 Rd
= inst
.operands
[0].reg
;
12668 Rn
= inst
.operands
[1].reg
;
12669 Rm
= inst
.operands
[2].reg
;
12671 reject_bad_reg (Rd
);
12672 reject_bad_reg (Rn
);
12673 reject_bad_reg (Rm
);
12675 inst
.instruction
|= Rd
<< 8;
12676 inst
.instruction
|= Rn
<< 16;
12677 inst
.instruction
|= Rm
;
12678 if (inst
.operands
[3].present
)
12680 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
12681 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
12682 _("expression too complex"));
12683 inst
.instruction
|= (val
& 0x1c) << 10;
12684 inst
.instruction
|= (val
& 0x03) << 6;
12691 if (!inst
.operands
[3].present
)
12695 inst
.instruction
&= ~0x00000020;
12697 /* PR 10168. Swap the Rm and Rn registers. */
12698 Rtmp
= inst
.operands
[1].reg
;
12699 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12700 inst
.operands
[2].reg
= Rtmp
;
12708 if (inst
.operands
[0].immisreg
)
12709 reject_bad_reg (inst
.operands
[0].imm
);
12711 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12715 do_t_push_pop (void)
12719 constraint (inst
.operands
[0].writeback
,
12720 _("push/pop do not support {reglist}^"));
12721 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12722 _("expression too complex"));
12724 mask
= inst
.operands
[0].imm
;
12725 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12726 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12727 else if (inst
.size_req
!= 4
12728 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12729 ? REG_LR
: REG_PC
)))
12731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12732 inst
.instruction
|= THUMB_PP_PC_LR
;
12733 inst
.instruction
|= mask
& 0xff;
12735 else if (unified_syntax
)
12737 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12738 encode_thumb2_ldmstm (13, mask
, TRUE
);
12742 inst
.error
= _("invalid register list to push/pop instruction");
12752 Rd
= inst
.operands
[0].reg
;
12753 Rm
= inst
.operands
[1].reg
;
12755 reject_bad_reg (Rd
);
12756 reject_bad_reg (Rm
);
12758 inst
.instruction
|= Rd
<< 8;
12759 inst
.instruction
|= Rm
<< 16;
12760 inst
.instruction
|= Rm
;
12768 Rd
= inst
.operands
[0].reg
;
12769 Rm
= inst
.operands
[1].reg
;
12771 reject_bad_reg (Rd
);
12772 reject_bad_reg (Rm
);
12774 if (Rd
<= 7 && Rm
<= 7
12775 && inst
.size_req
!= 4)
12777 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12778 inst
.instruction
|= Rd
;
12779 inst
.instruction
|= Rm
<< 3;
12781 else if (unified_syntax
)
12783 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12784 inst
.instruction
|= Rd
<< 8;
12785 inst
.instruction
|= Rm
<< 16;
12786 inst
.instruction
|= Rm
;
12789 inst
.error
= BAD_HIREG
;
12797 Rd
= inst
.operands
[0].reg
;
12798 Rm
= inst
.operands
[1].reg
;
12800 reject_bad_reg (Rd
);
12801 reject_bad_reg (Rm
);
12803 inst
.instruction
|= Rd
<< 8;
12804 inst
.instruction
|= Rm
;
12812 Rd
= inst
.operands
[0].reg
;
12813 Rs
= (inst
.operands
[1].present
12814 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12815 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12817 reject_bad_reg (Rd
);
12818 reject_bad_reg (Rs
);
12819 if (inst
.operands
[2].isreg
)
12820 reject_bad_reg (inst
.operands
[2].reg
);
12822 inst
.instruction
|= Rd
<< 8;
12823 inst
.instruction
|= Rs
<< 16;
12824 if (!inst
.operands
[2].isreg
)
12826 bfd_boolean narrow
;
12828 if ((inst
.instruction
& 0x00100000) != 0)
12829 narrow
= !in_it_block ();
12831 narrow
= in_it_block ();
12833 if (Rd
> 7 || Rs
> 7)
12836 if (inst
.size_req
== 4 || !unified_syntax
)
12839 if (inst
.relocs
[0].exp
.X_op
!= O_constant
12840 || inst
.relocs
[0].exp
.X_add_number
!= 0)
12843 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12844 relaxation, but it doesn't seem worth the hassle. */
12847 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12848 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12849 inst
.instruction
|= Rs
<< 3;
12850 inst
.instruction
|= Rd
;
12854 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12855 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12859 encode_thumb32_shifted_operand (2);
12865 if (warn_on_deprecated
12866 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12867 as_tsktsk (_("setend use is deprecated for ARMv8"));
12869 set_it_insn_type (OUTSIDE_IT_INSN
);
12870 if (inst
.operands
[0].imm
)
12871 inst
.instruction
|= 0x8;
12877 if (!inst
.operands
[1].present
)
12878 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12880 if (unified_syntax
)
12882 bfd_boolean narrow
;
12885 switch (inst
.instruction
)
12888 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12890 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12892 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12894 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12898 if (THUMB_SETS_FLAGS (inst
.instruction
))
12899 narrow
= !in_it_block ();
12901 narrow
= in_it_block ();
12902 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12904 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12906 if (inst
.operands
[2].isreg
12907 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12908 || inst
.operands
[2].reg
> 7))
12910 if (inst
.size_req
== 4)
12913 reject_bad_reg (inst
.operands
[0].reg
);
12914 reject_bad_reg (inst
.operands
[1].reg
);
12918 if (inst
.operands
[2].isreg
)
12920 reject_bad_reg (inst
.operands
[2].reg
);
12921 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12922 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12924 inst
.instruction
|= inst
.operands
[2].reg
;
12926 /* PR 12854: Error on extraneous shifts. */
12927 constraint (inst
.operands
[2].shifted
,
12928 _("extraneous shift as part of operand to shift insn"));
12932 inst
.operands
[1].shifted
= 1;
12933 inst
.operands
[1].shift_kind
= shift_kind
;
12934 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12935 ? T_MNEM_movs
: T_MNEM_mov
);
12936 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12937 encode_thumb32_shifted_operand (1);
12938 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12939 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12944 if (inst
.operands
[2].isreg
)
12946 switch (shift_kind
)
12948 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12949 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12950 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12951 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12955 inst
.instruction
|= inst
.operands
[0].reg
;
12956 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12958 /* PR 12854: Error on extraneous shifts. */
12959 constraint (inst
.operands
[2].shifted
,
12960 _("extraneous shift as part of operand to shift insn"));
12964 switch (shift_kind
)
12966 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12967 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12968 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12971 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12972 inst
.instruction
|= inst
.operands
[0].reg
;
12973 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12979 constraint (inst
.operands
[0].reg
> 7
12980 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12981 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12983 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12985 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12986 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12987 _("source1 and dest must be same register"));
12989 switch (inst
.instruction
)
12991 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12992 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12993 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12994 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12998 inst
.instruction
|= inst
.operands
[0].reg
;
12999 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13001 /* PR 12854: Error on extraneous shifts. */
13002 constraint (inst
.operands
[2].shifted
,
13003 _("extraneous shift as part of operand to shift insn"));
13007 switch (inst
.instruction
)
13009 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13010 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13011 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13012 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13015 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13016 inst
.instruction
|= inst
.operands
[0].reg
;
13017 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13025 unsigned Rd
, Rn
, Rm
;
13027 Rd
= inst
.operands
[0].reg
;
13028 Rn
= inst
.operands
[1].reg
;
13029 Rm
= inst
.operands
[2].reg
;
13031 reject_bad_reg (Rd
);
13032 reject_bad_reg (Rn
);
13033 reject_bad_reg (Rm
);
13035 inst
.instruction
|= Rd
<< 8;
13036 inst
.instruction
|= Rn
<< 16;
13037 inst
.instruction
|= Rm
;
13043 unsigned Rd
, Rn
, Rm
;
13045 Rd
= inst
.operands
[0].reg
;
13046 Rm
= inst
.operands
[1].reg
;
13047 Rn
= inst
.operands
[2].reg
;
13049 reject_bad_reg (Rd
);
13050 reject_bad_reg (Rn
);
13051 reject_bad_reg (Rm
);
13053 inst
.instruction
|= Rd
<< 8;
13054 inst
.instruction
|= Rn
<< 16;
13055 inst
.instruction
|= Rm
;
13061 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13063 _("SMC is not permitted on this architecture"));
13064 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13065 _("expression too complex"));
13066 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13067 inst
.instruction
|= (value
& 0xf000) >> 12;
13068 inst
.instruction
|= (value
& 0x0ff0);
13069 inst
.instruction
|= (value
& 0x000f) << 16;
13070 /* PR gas/15623: SMC instructions must be last in an IT block. */
13071 set_it_insn_type_last ();
13077 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13079 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13080 inst
.instruction
|= (value
& 0x0fff);
13081 inst
.instruction
|= (value
& 0xf000) << 4;
13085 do_t_ssat_usat (int bias
)
13089 Rd
= inst
.operands
[0].reg
;
13090 Rn
= inst
.operands
[2].reg
;
13092 reject_bad_reg (Rd
);
13093 reject_bad_reg (Rn
);
13095 inst
.instruction
|= Rd
<< 8;
13096 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13097 inst
.instruction
|= Rn
<< 16;
13099 if (inst
.operands
[3].present
)
13101 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13103 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13105 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13106 _("expression too complex"));
13108 if (shift_amount
!= 0)
13110 constraint (shift_amount
> 31,
13111 _("shift expression is too large"));
13113 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13114 inst
.instruction
|= 0x00200000; /* sh bit. */
13116 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13117 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13125 do_t_ssat_usat (1);
13133 Rd
= inst
.operands
[0].reg
;
13134 Rn
= inst
.operands
[2].reg
;
13136 reject_bad_reg (Rd
);
13137 reject_bad_reg (Rn
);
13139 inst
.instruction
|= Rd
<< 8;
13140 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13141 inst
.instruction
|= Rn
<< 16;
13147 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13148 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13149 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13150 || inst
.operands
[2].negative
,
13153 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13155 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13156 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13157 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13158 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13164 if (!inst
.operands
[2].present
)
13165 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13167 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13168 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13169 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13172 inst
.instruction
|= inst
.operands
[0].reg
;
13173 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13174 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13175 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13181 unsigned Rd
, Rn
, Rm
;
13183 Rd
= inst
.operands
[0].reg
;
13184 Rn
= inst
.operands
[1].reg
;
13185 Rm
= inst
.operands
[2].reg
;
13187 reject_bad_reg (Rd
);
13188 reject_bad_reg (Rn
);
13189 reject_bad_reg (Rm
);
13191 inst
.instruction
|= Rd
<< 8;
13192 inst
.instruction
|= Rn
<< 16;
13193 inst
.instruction
|= Rm
;
13194 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13202 Rd
= inst
.operands
[0].reg
;
13203 Rm
= inst
.operands
[1].reg
;
13205 reject_bad_reg (Rd
);
13206 reject_bad_reg (Rm
);
13208 if (inst
.instruction
<= 0xffff
13209 && inst
.size_req
!= 4
13210 && Rd
<= 7 && Rm
<= 7
13211 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13213 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13214 inst
.instruction
|= Rd
;
13215 inst
.instruction
|= Rm
<< 3;
13217 else if (unified_syntax
)
13219 if (inst
.instruction
<= 0xffff)
13220 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13221 inst
.instruction
|= Rd
<< 8;
13222 inst
.instruction
|= Rm
;
13223 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13227 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13228 _("Thumb encoding does not support rotation"));
13229 constraint (1, BAD_HIREG
);
13236 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13245 half
= (inst
.instruction
& 0x10) != 0;
13246 set_it_insn_type_last ();
13247 constraint (inst
.operands
[0].immisreg
,
13248 _("instruction requires register index"));
13250 Rn
= inst
.operands
[0].reg
;
13251 Rm
= inst
.operands
[0].imm
;
13253 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13254 constraint (Rn
== REG_SP
, BAD_SP
);
13255 reject_bad_reg (Rm
);
13257 constraint (!half
&& inst
.operands
[0].shifted
,
13258 _("instruction does not allow shifted index"));
13259 inst
.instruction
|= (Rn
<< 16) | Rm
;
13265 if (!inst
.operands
[0].present
)
13266 inst
.operands
[0].imm
= 0;
13268 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13270 constraint (inst
.size_req
== 2,
13271 _("immediate value out of range"));
13272 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13273 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13274 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13279 inst
.instruction
|= inst
.operands
[0].imm
;
13282 set_it_insn_type (NEUTRAL_IT_INSN
);
13289 do_t_ssat_usat (0);
13297 Rd
= inst
.operands
[0].reg
;
13298 Rn
= inst
.operands
[2].reg
;
13300 reject_bad_reg (Rd
);
13301 reject_bad_reg (Rn
);
13303 inst
.instruction
|= Rd
<< 8;
13304 inst
.instruction
|= inst
.operands
[1].imm
;
13305 inst
.instruction
|= Rn
<< 16;
13308 /* Checking the range of the branch offset (VAL) with NBITS bits
13309 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13311 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13313 gas_assert (nbits
> 0 && nbits
<= 32);
13316 int cmp
= (1 << (nbits
- 1));
13317 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13322 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13328 /* For branches in Armv8.1-M Mainline. */
13330 do_t_branch_future (void)
13332 unsigned long insn
= inst
.instruction
;
13334 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13335 if (inst
.operands
[0].hasreloc
== 0)
13337 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13338 as_bad (BAD_BRANCH_OFF
);
13340 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13344 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13345 inst
.relocs
[0].pc_rel
= 1;
13351 if (inst
.operands
[1].hasreloc
== 0)
13353 int val
= inst
.operands
[1].imm
;
13354 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13355 as_bad (BAD_BRANCH_OFF
);
13357 int immA
= (val
& 0x0001f000) >> 12;
13358 int immB
= (val
& 0x00000ffc) >> 2;
13359 int immC
= (val
& 0x00000002) >> 1;
13360 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13364 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13365 inst
.relocs
[1].pc_rel
= 1;
13370 if (inst
.operands
[1].hasreloc
== 0)
13372 int val
= inst
.operands
[1].imm
;
13373 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13374 as_bad (BAD_BRANCH_OFF
);
13376 int immA
= (val
& 0x0007f000) >> 12;
13377 int immB
= (val
& 0x00000ffc) >> 2;
13378 int immC
= (val
& 0x00000002) >> 1;
13379 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13383 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13384 inst
.relocs
[1].pc_rel
= 1;
13388 case T_MNEM_bfcsel
:
13390 if (inst
.operands
[1].hasreloc
== 0)
13392 int val
= inst
.operands
[1].imm
;
13393 int immA
= (val
& 0x00001000) >> 12;
13394 int immB
= (val
& 0x00000ffc) >> 2;
13395 int immC
= (val
& 0x00000002) >> 1;
13396 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13400 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
13401 inst
.relocs
[1].pc_rel
= 1;
13405 if (inst
.operands
[2].hasreloc
== 0)
13407 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
13408 int val2
= inst
.operands
[2].imm
;
13409 int val0
= inst
.operands
[0].imm
& 0x1f;
13410 int diff
= val2
- val0
;
13412 inst
.instruction
|= 1 << 17; /* T bit. */
13413 else if (diff
!= 2)
13414 as_bad (_("out of range label-relative fixup value"));
13418 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
13419 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
13420 inst
.relocs
[2].pc_rel
= 1;
13424 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
13425 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
13430 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13437 /* Neon instruction encoder helpers. */
13439 /* Encodings for the different types for various Neon opcodes. */
13441 /* An "invalid" code for the following tables. */
13444 struct neon_tab_entry
13447 unsigned float_or_poly
;
13448 unsigned scalar_or_imm
;
13451 /* Map overloaded Neon opcodes to their respective encodings. */
13452 #define NEON_ENC_TAB \
13453 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13454 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13455 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13456 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13457 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13458 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13459 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13460 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13461 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13462 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13463 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13464 /* Register variants of the following two instructions are encoded as
13465 vcge / vcgt with the operands reversed. */ \
13466 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13467 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13468 X(vfma, N_INV, 0x0000c10, N_INV), \
13469 X(vfms, N_INV, 0x0200c10, N_INV), \
13470 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13471 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13472 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13473 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13474 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13475 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13476 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13477 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13478 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13479 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13480 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13481 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13482 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13483 X(vshl, 0x0000400, N_INV, 0x0800510), \
13484 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13485 X(vand, 0x0000110, N_INV, 0x0800030), \
13486 X(vbic, 0x0100110, N_INV, 0x0800030), \
13487 X(veor, 0x1000110, N_INV, N_INV), \
13488 X(vorn, 0x0300110, N_INV, 0x0800010), \
13489 X(vorr, 0x0200110, N_INV, 0x0800010), \
13490 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13491 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13492 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13493 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13494 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13495 X(vst1, 0x0000000, 0x0800000, N_INV), \
13496 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13497 X(vst2, 0x0000100, 0x0800100, N_INV), \
13498 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13499 X(vst3, 0x0000200, 0x0800200, N_INV), \
13500 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13501 X(vst4, 0x0000300, 0x0800300, N_INV), \
13502 X(vmovn, 0x1b20200, N_INV, N_INV), \
13503 X(vtrn, 0x1b20080, N_INV, N_INV), \
13504 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13505 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13506 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13507 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13508 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13509 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13510 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13511 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13512 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13513 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13514 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13515 X(vseleq, 0xe000a00, N_INV, N_INV), \
13516 X(vselvs, 0xe100a00, N_INV, N_INV), \
13517 X(vselge, 0xe200a00, N_INV, N_INV), \
13518 X(vselgt, 0xe300a00, N_INV, N_INV), \
13519 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13520 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13521 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13522 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13523 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13524 X(aes, 0x3b00300, N_INV, N_INV), \
13525 X(sha3op, 0x2000c00, N_INV, N_INV), \
13526 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13527 X(sha2op, 0x3ba0380, N_INV, N_INV)
13531 #define X(OPC,I,F,S) N_MNEM_##OPC
13536 static const struct neon_tab_entry neon_enc_tab
[] =
13538 #define X(OPC,I,F,S) { (I), (F), (S) }
13543 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13544 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13545 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13546 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13547 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13548 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13549 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13550 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13551 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13552 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13553 #define NEON_ENC_SINGLE_(X) \
13554 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13555 #define NEON_ENC_DOUBLE_(X) \
13556 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13557 #define NEON_ENC_FPV8_(X) \
13558 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13560 #define NEON_ENCODE(type, inst) \
13563 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13564 inst.is_neon = 1; \
13568 #define check_neon_suffixes \
13571 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13573 as_bad (_("invalid neon suffix for non neon instruction")); \
13579 /* Define shapes for instruction operands. The following mnemonic characters
13580 are used in this table:
13582 F - VFP S<n> register
13583 D - Neon D<n> register
13584 Q - Neon Q<n> register
13588 L - D<n> register list
13590 This table is used to generate various data:
13591 - enumerations of the form NS_DDR to be used as arguments to
13593 - a table classifying shapes into single, double, quad, mixed.
13594 - a table used to drive neon_select_shape. */
13596 #define NEON_SHAPE_DEF \
13597 X(3, (D, D, D), DOUBLE), \
13598 X(3, (Q, Q, Q), QUAD), \
13599 X(3, (D, D, I), DOUBLE), \
13600 X(3, (Q, Q, I), QUAD), \
13601 X(3, (D, D, S), DOUBLE), \
13602 X(3, (Q, Q, S), QUAD), \
13603 X(2, (D, D), DOUBLE), \
13604 X(2, (Q, Q), QUAD), \
13605 X(2, (D, S), DOUBLE), \
13606 X(2, (Q, S), QUAD), \
13607 X(2, (D, R), DOUBLE), \
13608 X(2, (Q, R), QUAD), \
13609 X(2, (D, I), DOUBLE), \
13610 X(2, (Q, I), QUAD), \
13611 X(3, (D, L, D), DOUBLE), \
13612 X(2, (D, Q), MIXED), \
13613 X(2, (Q, D), MIXED), \
13614 X(3, (D, Q, I), MIXED), \
13615 X(3, (Q, D, I), MIXED), \
13616 X(3, (Q, D, D), MIXED), \
13617 X(3, (D, Q, Q), MIXED), \
13618 X(3, (Q, Q, D), MIXED), \
13619 X(3, (Q, D, S), MIXED), \
13620 X(3, (D, Q, S), MIXED), \
13621 X(4, (D, D, D, I), DOUBLE), \
13622 X(4, (Q, Q, Q, I), QUAD), \
13623 X(4, (D, D, S, I), DOUBLE), \
13624 X(4, (Q, Q, S, I), QUAD), \
13625 X(2, (F, F), SINGLE), \
13626 X(3, (F, F, F), SINGLE), \
13627 X(2, (F, I), SINGLE), \
13628 X(2, (F, D), MIXED), \
13629 X(2, (D, F), MIXED), \
13630 X(3, (F, F, I), MIXED), \
13631 X(4, (R, R, F, F), SINGLE), \
13632 X(4, (F, F, R, R), SINGLE), \
13633 X(3, (D, R, R), DOUBLE), \
13634 X(3, (R, R, D), DOUBLE), \
13635 X(2, (S, R), SINGLE), \
13636 X(2, (R, S), SINGLE), \
13637 X(2, (F, R), SINGLE), \
13638 X(2, (R, F), SINGLE), \
13639 /* Half float shape supported so far. */\
13640 X (2, (H, D), MIXED), \
13641 X (2, (D, H), MIXED), \
13642 X (2, (H, F), MIXED), \
13643 X (2, (F, H), MIXED), \
13644 X (2, (H, H), HALF), \
13645 X (2, (H, R), HALF), \
13646 X (2, (R, H), HALF), \
13647 X (2, (H, I), HALF), \
13648 X (3, (H, H, H), HALF), \
13649 X (3, (H, F, I), MIXED), \
13650 X (3, (F, H, I), MIXED), \
13651 X (3, (D, H, H), MIXED), \
13652 X (3, (D, H, S), MIXED)
13654 #define S2(A,B) NS_##A##B
13655 #define S3(A,B,C) NS_##A##B##C
13656 #define S4(A,B,C,D) NS_##A##B##C##D
13658 #define X(N, L, C) S##N L
13671 enum neon_shape_class
13680 #define X(N, L, C) SC_##C
13682 static enum neon_shape_class neon_shape_class
[] =
13701 /* Register widths of above. */
13702 static unsigned neon_shape_el_size
[] =
13714 struct neon_shape_info
13717 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13720 #define S2(A,B) { SE_##A, SE_##B }
13721 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13722 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13724 #define X(N, L, C) { N, S##N L }
13726 static struct neon_shape_info neon_shape_tab
[] =
13736 /* Bit masks used in type checking given instructions.
13737 'N_EQK' means the type must be the same as (or based on in some way) the key
13738 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13739 set, various other bits can be set as well in order to modify the meaning of
13740 the type constraint. */
13742 enum neon_type_mask
13766 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13767 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13768 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13769 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13770 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13771 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13772 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13773 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13774 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13775 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13776 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13778 N_MAX_NONSPECIAL
= N_P64
13781 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13783 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13784 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13785 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13786 #define N_S_32 (N_S8 | N_S16 | N_S32)
13787 #define N_F_16_32 (N_F16 | N_F32)
13788 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13789 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13790 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13791 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13793 /* Pass this as the first type argument to neon_check_type to ignore types
13795 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13797 /* Select a "shape" for the current instruction (describing register types or
13798 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13799 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13800 function of operand parsing, so this function doesn't need to be called.
13801 Shapes should be listed in order of decreasing length. */
13803 static enum neon_shape
13804 neon_select_shape (enum neon_shape shape
, ...)
13807 enum neon_shape first_shape
= shape
;
13809 /* Fix missing optional operands. FIXME: we don't know at this point how
13810 many arguments we should have, so this makes the assumption that we have
13811 > 1. This is true of all current Neon opcodes, I think, but may not be
13812 true in the future. */
13813 if (!inst
.operands
[1].present
)
13814 inst
.operands
[1] = inst
.operands
[0];
13816 va_start (ap
, shape
);
13818 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13823 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13825 if (!inst
.operands
[j
].present
)
13831 switch (neon_shape_tab
[shape
].el
[j
])
13833 /* If a .f16, .16, .u16, .s16 type specifier is given over
13834 a VFP single precision register operand, it's essentially
13835 means only half of the register is used.
13837 If the type specifier is given after the mnemonics, the
13838 information is stored in inst.vectype. If the type specifier
13839 is given after register operand, the information is stored
13840 in inst.operands[].vectype.
13842 When there is only one type specifier, and all the register
13843 operands are the same type of hardware register, the type
13844 specifier applies to all register operands.
13846 If no type specifier is given, the shape is inferred from
13847 operand information.
13850 vadd.f16 s0, s1, s2: NS_HHH
13851 vabs.f16 s0, s1: NS_HH
13852 vmov.f16 s0, r1: NS_HR
13853 vmov.f16 r0, s1: NS_RH
13854 vcvt.f16 r0, s1: NS_RH
13855 vcvt.f16.s32 s2, s2, #29: NS_HFI
13856 vcvt.f16.s32 s2, s2: NS_HF
13859 if (!(inst
.operands
[j
].isreg
13860 && inst
.operands
[j
].isvec
13861 && inst
.operands
[j
].issingle
13862 && !inst
.operands
[j
].isquad
13863 && ((inst
.vectype
.elems
== 1
13864 && inst
.vectype
.el
[0].size
== 16)
13865 || (inst
.vectype
.elems
> 1
13866 && inst
.vectype
.el
[j
].size
== 16)
13867 || (inst
.vectype
.elems
== 0
13868 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13869 && inst
.operands
[j
].vectype
.size
== 16))))
13874 if (!(inst
.operands
[j
].isreg
13875 && inst
.operands
[j
].isvec
13876 && inst
.operands
[j
].issingle
13877 && !inst
.operands
[j
].isquad
13878 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13879 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13880 || (inst
.vectype
.elems
== 0
13881 && (inst
.operands
[j
].vectype
.size
== 32
13882 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13887 if (!(inst
.operands
[j
].isreg
13888 && inst
.operands
[j
].isvec
13889 && !inst
.operands
[j
].isquad
13890 && !inst
.operands
[j
].issingle
))
13895 if (!(inst
.operands
[j
].isreg
13896 && !inst
.operands
[j
].isvec
))
13901 if (!(inst
.operands
[j
].isreg
13902 && inst
.operands
[j
].isvec
13903 && inst
.operands
[j
].isquad
13904 && !inst
.operands
[j
].issingle
))
13909 if (!(!inst
.operands
[j
].isreg
13910 && !inst
.operands
[j
].isscalar
))
13915 if (!(!inst
.operands
[j
].isreg
13916 && inst
.operands
[j
].isscalar
))
13926 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13927 /* We've matched all the entries in the shape table, and we don't
13928 have any left over operands which have not been matched. */
13934 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13935 first_error (_("invalid instruction shape"));
13940 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13941 means the Q bit should be set). */
13944 neon_quad (enum neon_shape shape
)
13946 return neon_shape_class
[shape
] == SC_QUAD
;
13950 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13953 /* Allow modification to be made to types which are constrained to be
13954 based on the key element, based on bits set alongside N_EQK. */
13955 if ((typebits
& N_EQK
) != 0)
13957 if ((typebits
& N_HLF
) != 0)
13959 else if ((typebits
& N_DBL
) != 0)
13961 if ((typebits
& N_SGN
) != 0)
13962 *g_type
= NT_signed
;
13963 else if ((typebits
& N_UNS
) != 0)
13964 *g_type
= NT_unsigned
;
13965 else if ((typebits
& N_INT
) != 0)
13966 *g_type
= NT_integer
;
13967 else if ((typebits
& N_FLT
) != 0)
13968 *g_type
= NT_float
;
13969 else if ((typebits
& N_SIZ
) != 0)
13970 *g_type
= NT_untyped
;
13974 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13975 operand type, i.e. the single type specified in a Neon instruction when it
13976 is the only one given. */
13978 static struct neon_type_el
13979 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13981 struct neon_type_el dest
= *key
;
13983 gas_assert ((thisarg
& N_EQK
) != 0);
13985 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13990 /* Convert Neon type and size into compact bitmask representation. */
13992 static enum neon_type_mask
13993 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14000 case 8: return N_8
;
14001 case 16: return N_16
;
14002 case 32: return N_32
;
14003 case 64: return N_64
;
14011 case 8: return N_I8
;
14012 case 16: return N_I16
;
14013 case 32: return N_I32
;
14014 case 64: return N_I64
;
14022 case 16: return N_F16
;
14023 case 32: return N_F32
;
14024 case 64: return N_F64
;
14032 case 8: return N_P8
;
14033 case 16: return N_P16
;
14034 case 64: return N_P64
;
14042 case 8: return N_S8
;
14043 case 16: return N_S16
;
14044 case 32: return N_S32
;
14045 case 64: return N_S64
;
14053 case 8: return N_U8
;
14054 case 16: return N_U16
;
14055 case 32: return N_U32
;
14056 case 64: return N_U64
;
14067 /* Convert compact Neon bitmask type representation to a type and size. Only
14068 handles the case where a single bit is set in the mask. */
14071 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14072 enum neon_type_mask mask
)
14074 if ((mask
& N_EQK
) != 0)
14077 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14079 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14081 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14083 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14088 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14090 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14091 *type
= NT_unsigned
;
14092 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14093 *type
= NT_integer
;
14094 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14095 *type
= NT_untyped
;
14096 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14098 else if ((mask
& (N_F_ALL
)) != 0)
14106 /* Modify a bitmask of allowed types. This is only needed for type
14110 modify_types_allowed (unsigned allowed
, unsigned mods
)
14113 enum neon_el_type type
;
14119 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14121 if (el_type_of_type_chk (&type
, &size
,
14122 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14124 neon_modify_type_size (mods
, &type
, &size
);
14125 destmask
|= type_chk_of_el_type (type
, size
);
14132 /* Check type and return type classification.
14133 The manual states (paraphrase): If one datatype is given, it indicates the
14135 - the second operand, if there is one
14136 - the operand, if there is no second operand
14137 - the result, if there are no operands.
14138 This isn't quite good enough though, so we use a concept of a "key" datatype
14139 which is set on a per-instruction basis, which is the one which matters when
14140 only one data type is written.
14141 Note: this function has side-effects (e.g. filling in missing operands). All
14142 Neon instructions should call it before performing bit encoding. */
14144 static struct neon_type_el
14145 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14148 unsigned i
, pass
, key_el
= 0;
14149 unsigned types
[NEON_MAX_TYPE_ELS
];
14150 enum neon_el_type k_type
= NT_invtype
;
14151 unsigned k_size
= -1u;
14152 struct neon_type_el badtype
= {NT_invtype
, -1};
14153 unsigned key_allowed
= 0;
14155 /* Optional registers in Neon instructions are always (not) in operand 1.
14156 Fill in the missing operand here, if it was omitted. */
14157 if (els
> 1 && !inst
.operands
[1].present
)
14158 inst
.operands
[1] = inst
.operands
[0];
14160 /* Suck up all the varargs. */
14162 for (i
= 0; i
< els
; i
++)
14164 unsigned thisarg
= va_arg (ap
, unsigned);
14165 if (thisarg
== N_IGNORE_TYPE
)
14170 types
[i
] = thisarg
;
14171 if ((thisarg
& N_KEY
) != 0)
14176 if (inst
.vectype
.elems
> 0)
14177 for (i
= 0; i
< els
; i
++)
14178 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14180 first_error (_("types specified in both the mnemonic and operands"));
14184 /* Duplicate inst.vectype elements here as necessary.
14185 FIXME: No idea if this is exactly the same as the ARM assembler,
14186 particularly when an insn takes one register and one non-register
14188 if (inst
.vectype
.elems
== 1 && els
> 1)
14191 inst
.vectype
.elems
= els
;
14192 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14193 for (j
= 0; j
< els
; j
++)
14195 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14198 else if (inst
.vectype
.elems
== 0 && els
> 0)
14201 /* No types were given after the mnemonic, so look for types specified
14202 after each operand. We allow some flexibility here; as long as the
14203 "key" operand has a type, we can infer the others. */
14204 for (j
= 0; j
< els
; j
++)
14205 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14206 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14208 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14210 for (j
= 0; j
< els
; j
++)
14211 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14212 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14217 first_error (_("operand types can't be inferred"));
14221 else if (inst
.vectype
.elems
!= els
)
14223 first_error (_("type specifier has the wrong number of parts"));
14227 for (pass
= 0; pass
< 2; pass
++)
14229 for (i
= 0; i
< els
; i
++)
14231 unsigned thisarg
= types
[i
];
14232 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14233 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14234 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14235 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14237 /* Decay more-specific signed & unsigned types to sign-insensitive
14238 integer types if sign-specific variants are unavailable. */
14239 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14240 && (types_allowed
& N_SU_ALL
) == 0)
14241 g_type
= NT_integer
;
14243 /* If only untyped args are allowed, decay any more specific types to
14244 them. Some instructions only care about signs for some element
14245 sizes, so handle that properly. */
14246 if (((types_allowed
& N_UNT
) == 0)
14247 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14248 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14249 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14250 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14251 g_type
= NT_untyped
;
14255 if ((thisarg
& N_KEY
) != 0)
14259 key_allowed
= thisarg
& ~N_KEY
;
14261 /* Check architecture constraint on FP16 extension. */
14263 && k_type
== NT_float
14264 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14266 inst
.error
= _(BAD_FP16
);
14273 if ((thisarg
& N_VFP
) != 0)
14275 enum neon_shape_el regshape
;
14276 unsigned regwidth
, match
;
14278 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14281 first_error (_("invalid instruction shape"));
14284 regshape
= neon_shape_tab
[ns
].el
[i
];
14285 regwidth
= neon_shape_el_size
[regshape
];
14287 /* In VFP mode, operands must match register widths. If we
14288 have a key operand, use its width, else use the width of
14289 the current operand. */
14295 /* FP16 will use a single precision register. */
14296 if (regwidth
== 32 && match
== 16)
14298 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14302 inst
.error
= _(BAD_FP16
);
14307 if (regwidth
!= match
)
14309 first_error (_("operand size must match register width"));
14314 if ((thisarg
& N_EQK
) == 0)
14316 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14318 if ((given_type
& types_allowed
) == 0)
14320 first_error (_("bad type in Neon instruction"));
14326 enum neon_el_type mod_k_type
= k_type
;
14327 unsigned mod_k_size
= k_size
;
14328 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14329 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14331 first_error (_("inconsistent types in Neon instruction"));
14339 return inst
.vectype
.el
[key_el
];
14342 /* Neon-style VFP instruction forwarding. */
14344 /* Thumb VFP instructions have 0xE in the condition field. */
14347 do_vfp_cond_or_thumb (void)
14352 inst
.instruction
|= 0xe0000000;
14354 inst
.instruction
|= inst
.cond
<< 28;
14357 /* Look up and encode a simple mnemonic, for use as a helper function for the
14358 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14359 etc. It is assumed that operand parsing has already been done, and that the
14360 operands are in the form expected by the given opcode (this isn't necessarily
14361 the same as the form in which they were parsed, hence some massaging must
14362 take place before this function is called).
14363 Checks current arch version against that in the looked-up opcode. */
14366 do_vfp_nsyn_opcode (const char *opname
)
14368 const struct asm_opcode
*opcode
;
14370 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14375 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14376 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14383 inst
.instruction
= opcode
->tvalue
;
14384 opcode
->tencode ();
14388 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14389 opcode
->aencode ();
14394 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14396 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14398 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14401 do_vfp_nsyn_opcode ("fadds");
14403 do_vfp_nsyn_opcode ("fsubs");
14405 /* ARMv8.2 fp16 instruction. */
14407 do_scalar_fp16_v82_encode ();
14412 do_vfp_nsyn_opcode ("faddd");
14414 do_vfp_nsyn_opcode ("fsubd");
14418 /* Check operand types to see if this is a VFP instruction, and if so call
14422 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14424 enum neon_shape rs
;
14425 struct neon_type_el et
;
14430 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14431 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14435 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14436 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14437 N_F_ALL
| N_KEY
| N_VFP
);
14444 if (et
.type
!= NT_invtype
)
14455 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14457 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14459 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14462 do_vfp_nsyn_opcode ("fmacs");
14464 do_vfp_nsyn_opcode ("fnmacs");
14466 /* ARMv8.2 fp16 instruction. */
14468 do_scalar_fp16_v82_encode ();
14473 do_vfp_nsyn_opcode ("fmacd");
14475 do_vfp_nsyn_opcode ("fnmacd");
14480 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14482 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14484 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14487 do_vfp_nsyn_opcode ("ffmas");
14489 do_vfp_nsyn_opcode ("ffnmas");
14491 /* ARMv8.2 fp16 instruction. */
14493 do_scalar_fp16_v82_encode ();
14498 do_vfp_nsyn_opcode ("ffmad");
14500 do_vfp_nsyn_opcode ("ffnmad");
14505 do_vfp_nsyn_mul (enum neon_shape rs
)
14507 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14509 do_vfp_nsyn_opcode ("fmuls");
14511 /* ARMv8.2 fp16 instruction. */
14513 do_scalar_fp16_v82_encode ();
14516 do_vfp_nsyn_opcode ("fmuld");
14520 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14522 int is_neg
= (inst
.instruction
& 0x80) != 0;
14523 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14525 if (rs
== NS_FF
|| rs
== NS_HH
)
14528 do_vfp_nsyn_opcode ("fnegs");
14530 do_vfp_nsyn_opcode ("fabss");
14532 /* ARMv8.2 fp16 instruction. */
14534 do_scalar_fp16_v82_encode ();
14539 do_vfp_nsyn_opcode ("fnegd");
14541 do_vfp_nsyn_opcode ("fabsd");
14545 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14546 insns belong to Neon, and are handled elsewhere. */
14549 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14551 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14555 do_vfp_nsyn_opcode ("fldmdbs");
14557 do_vfp_nsyn_opcode ("fldmias");
14562 do_vfp_nsyn_opcode ("fstmdbs");
14564 do_vfp_nsyn_opcode ("fstmias");
14569 do_vfp_nsyn_sqrt (void)
14571 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14572 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14574 if (rs
== NS_FF
|| rs
== NS_HH
)
14576 do_vfp_nsyn_opcode ("fsqrts");
14578 /* ARMv8.2 fp16 instruction. */
14580 do_scalar_fp16_v82_encode ();
14583 do_vfp_nsyn_opcode ("fsqrtd");
14587 do_vfp_nsyn_div (void)
14589 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14590 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14591 N_F_ALL
| N_KEY
| N_VFP
);
14593 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14595 do_vfp_nsyn_opcode ("fdivs");
14597 /* ARMv8.2 fp16 instruction. */
14599 do_scalar_fp16_v82_encode ();
14602 do_vfp_nsyn_opcode ("fdivd");
14606 do_vfp_nsyn_nmul (void)
14608 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14609 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14610 N_F_ALL
| N_KEY
| N_VFP
);
14612 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14614 NEON_ENCODE (SINGLE
, inst
);
14615 do_vfp_sp_dyadic ();
14617 /* ARMv8.2 fp16 instruction. */
14619 do_scalar_fp16_v82_encode ();
14623 NEON_ENCODE (DOUBLE
, inst
);
14624 do_vfp_dp_rd_rn_rm ();
14626 do_vfp_cond_or_thumb ();
14631 do_vfp_nsyn_cmp (void)
14633 enum neon_shape rs
;
14634 if (inst
.operands
[1].isreg
)
14636 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14637 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14639 if (rs
== NS_FF
|| rs
== NS_HH
)
14641 NEON_ENCODE (SINGLE
, inst
);
14642 do_vfp_sp_monadic ();
14646 NEON_ENCODE (DOUBLE
, inst
);
14647 do_vfp_dp_rd_rm ();
14652 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14653 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14655 switch (inst
.instruction
& 0x0fffffff)
14658 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14661 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14667 if (rs
== NS_FI
|| rs
== NS_HI
)
14669 NEON_ENCODE (SINGLE
, inst
);
14670 do_vfp_sp_compare_z ();
14674 NEON_ENCODE (DOUBLE
, inst
);
14678 do_vfp_cond_or_thumb ();
14680 /* ARMv8.2 fp16 instruction. */
14681 if (rs
== NS_HI
|| rs
== NS_HH
)
14682 do_scalar_fp16_v82_encode ();
14686 nsyn_insert_sp (void)
14688 inst
.operands
[1] = inst
.operands
[0];
14689 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14690 inst
.operands
[0].reg
= REG_SP
;
14691 inst
.operands
[0].isreg
= 1;
14692 inst
.operands
[0].writeback
= 1;
14693 inst
.operands
[0].present
= 1;
14697 do_vfp_nsyn_push (void)
14701 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14702 _("register list must contain at least 1 and at most 16 "
14705 if (inst
.operands
[1].issingle
)
14706 do_vfp_nsyn_opcode ("fstmdbs");
14708 do_vfp_nsyn_opcode ("fstmdbd");
14712 do_vfp_nsyn_pop (void)
14716 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14717 _("register list must contain at least 1 and at most 16 "
14720 if (inst
.operands
[1].issingle
)
14721 do_vfp_nsyn_opcode ("fldmias");
14723 do_vfp_nsyn_opcode ("fldmiad");
14726 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14727 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14730 neon_dp_fixup (struct arm_it
* insn
)
14732 unsigned int i
= insn
->instruction
;
14737 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14748 insn
->instruction
= i
;
14751 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14755 neon_logbits (unsigned x
)
14757 return ffs (x
) - 4;
14760 #define LOW4(R) ((R) & 0xf)
14761 #define HI1(R) (((R) >> 4) & 1)
14763 /* Encode insns with bit pattern:
14765 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14766 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14768 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14769 different meaning for some instruction. */
14772 neon_three_same (int isquad
, int ubit
, int size
)
14774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14778 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14779 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14780 inst
.instruction
|= (isquad
!= 0) << 6;
14781 inst
.instruction
|= (ubit
!= 0) << 24;
14783 inst
.instruction
|= neon_logbits (size
) << 20;
14785 neon_dp_fixup (&inst
);
14788 /* Encode instructions of the form:
14790 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14791 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14793 Don't write size if SIZE == -1. */
14796 neon_two_same (int qbit
, int ubit
, int size
)
14798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14800 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14801 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14802 inst
.instruction
|= (qbit
!= 0) << 6;
14803 inst
.instruction
|= (ubit
!= 0) << 24;
14806 inst
.instruction
|= neon_logbits (size
) << 18;
14808 neon_dp_fixup (&inst
);
14811 /* Neon instruction encoders, in approximate order of appearance. */
14814 do_neon_dyadic_i_su (void)
14816 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14817 struct neon_type_el et
= neon_check_type (3, rs
,
14818 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14819 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14823 do_neon_dyadic_i64_su (void)
14825 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14826 struct neon_type_el et
= neon_check_type (3, rs
,
14827 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14828 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14832 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14835 unsigned size
= et
.size
>> 3;
14836 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14837 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14838 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14839 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14840 inst
.instruction
|= (isquad
!= 0) << 6;
14841 inst
.instruction
|= immbits
<< 16;
14842 inst
.instruction
|= (size
>> 3) << 7;
14843 inst
.instruction
|= (size
& 0x7) << 19;
14845 inst
.instruction
|= (uval
!= 0) << 24;
14847 neon_dp_fixup (&inst
);
14851 do_neon_shl_imm (void)
14853 if (!inst
.operands
[2].isreg
)
14855 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14856 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14857 int imm
= inst
.operands
[2].imm
;
14859 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14860 _("immediate out of range for shift"));
14861 NEON_ENCODE (IMMED
, inst
);
14862 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14866 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14867 struct neon_type_el et
= neon_check_type (3, rs
,
14868 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14871 /* VSHL/VQSHL 3-register variants have syntax such as:
14873 whereas other 3-register operations encoded by neon_three_same have
14876 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14878 tmp
= inst
.operands
[2].reg
;
14879 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14880 inst
.operands
[1].reg
= tmp
;
14881 NEON_ENCODE (INTEGER
, inst
);
14882 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14887 do_neon_qshl_imm (void)
14889 if (!inst
.operands
[2].isreg
)
14891 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14892 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14893 int imm
= inst
.operands
[2].imm
;
14895 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14896 _("immediate out of range for shift"));
14897 NEON_ENCODE (IMMED
, inst
);
14898 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14902 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14903 struct neon_type_el et
= neon_check_type (3, rs
,
14904 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14907 /* See note in do_neon_shl_imm. */
14908 tmp
= inst
.operands
[2].reg
;
14909 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14910 inst
.operands
[1].reg
= tmp
;
14911 NEON_ENCODE (INTEGER
, inst
);
14912 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14917 do_neon_rshl (void)
14919 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14920 struct neon_type_el et
= neon_check_type (3, rs
,
14921 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14924 tmp
= inst
.operands
[2].reg
;
14925 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14926 inst
.operands
[1].reg
= tmp
;
14927 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14931 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14933 /* Handle .I8 pseudo-instructions. */
14936 /* Unfortunately, this will make everything apart from zero out-of-range.
14937 FIXME is this the intended semantics? There doesn't seem much point in
14938 accepting .I8 if so. */
14939 immediate
|= immediate
<< 8;
14945 if (immediate
== (immediate
& 0x000000ff))
14947 *immbits
= immediate
;
14950 else if (immediate
== (immediate
& 0x0000ff00))
14952 *immbits
= immediate
>> 8;
14955 else if (immediate
== (immediate
& 0x00ff0000))
14957 *immbits
= immediate
>> 16;
14960 else if (immediate
== (immediate
& 0xff000000))
14962 *immbits
= immediate
>> 24;
14965 if ((immediate
& 0xffff) != (immediate
>> 16))
14966 goto bad_immediate
;
14967 immediate
&= 0xffff;
14970 if (immediate
== (immediate
& 0x000000ff))
14972 *immbits
= immediate
;
14975 else if (immediate
== (immediate
& 0x0000ff00))
14977 *immbits
= immediate
>> 8;
14982 first_error (_("immediate value out of range"));
14987 do_neon_logic (void)
14989 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14991 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14992 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14993 /* U bit and size field were set as part of the bitmask. */
14994 NEON_ENCODE (INTEGER
, inst
);
14995 neon_three_same (neon_quad (rs
), 0, -1);
14999 const int three_ops_form
= (inst
.operands
[2].present
15000 && !inst
.operands
[2].isreg
);
15001 const int immoperand
= (three_ops_form
? 2 : 1);
15002 enum neon_shape rs
= (three_ops_form
15003 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
15004 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
15005 struct neon_type_el et
= neon_check_type (2, rs
,
15006 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15007 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
15011 if (et
.type
== NT_invtype
)
15014 if (three_ops_form
)
15015 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15016 _("first and second operands shall be the same register"));
15018 NEON_ENCODE (IMMED
, inst
);
15020 immbits
= inst
.operands
[immoperand
].imm
;
15023 /* .i64 is a pseudo-op, so the immediate must be a repeating
15025 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
15026 inst
.operands
[immoperand
].reg
: 0))
15028 /* Set immbits to an invalid constant. */
15029 immbits
= 0xdeadbeef;
15036 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15040 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15044 /* Pseudo-instruction for VBIC. */
15045 neon_invert_size (&immbits
, 0, et
.size
);
15046 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15050 /* Pseudo-instruction for VORR. */
15051 neon_invert_size (&immbits
, 0, et
.size
);
15052 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15062 inst
.instruction
|= neon_quad (rs
) << 6;
15063 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15064 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15065 inst
.instruction
|= cmode
<< 8;
15066 neon_write_immbits (immbits
);
15068 neon_dp_fixup (&inst
);
15073 do_neon_bitfield (void)
15075 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15076 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15077 neon_three_same (neon_quad (rs
), 0, -1);
15081 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15084 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15085 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15087 if (et
.type
== NT_float
)
15089 NEON_ENCODE (FLOAT
, inst
);
15090 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15094 NEON_ENCODE (INTEGER
, inst
);
15095 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15100 do_neon_dyadic_if_su (void)
15102 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15106 do_neon_dyadic_if_su_d (void)
15108 /* This version only allow D registers, but that constraint is enforced during
15109 operand parsing so we don't need to do anything extra here. */
15110 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15114 do_neon_dyadic_if_i_d (void)
15116 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15117 affected if we specify unsigned args. */
15118 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15121 enum vfp_or_neon_is_neon_bits
15124 NEON_CHECK_ARCH
= 2,
15125 NEON_CHECK_ARCH8
= 4
15128 /* Call this function if an instruction which may have belonged to the VFP or
15129 Neon instruction sets, but turned out to be a Neon instruction (due to the
15130 operand types involved, etc.). We have to check and/or fix-up a couple of
15133 - Make sure the user hasn't attempted to make a Neon instruction
15135 - Alter the value in the condition code field if necessary.
15136 - Make sure that the arch supports Neon instructions.
15138 Which of these operations take place depends on bits from enum
15139 vfp_or_neon_is_neon_bits.
15141 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15142 current instruction's condition is COND_ALWAYS, the condition field is
15143 changed to inst.uncond_value. This is necessary because instructions shared
15144 between VFP and Neon may be conditional for the VFP variants only, and the
15145 unconditional Neon version must have, e.g., 0xF in the condition field. */
15148 vfp_or_neon_is_neon (unsigned check
)
15150 /* Conditions are always legal in Thumb mode (IT blocks). */
15151 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15153 if (inst
.cond
!= COND_ALWAYS
)
15155 first_error (_(BAD_COND
));
15158 if (inst
.uncond_value
!= -1)
15159 inst
.instruction
|= inst
.uncond_value
<< 28;
15162 if ((check
& NEON_CHECK_ARCH
)
15163 && !mark_feature_used (&fpu_neon_ext_v1
))
15165 first_error (_(BAD_FPU
));
15169 if ((check
& NEON_CHECK_ARCH8
)
15170 && !mark_feature_used (&fpu_neon_ext_armv8
))
15172 first_error (_(BAD_FPU
));
15180 do_neon_addsub_if_i (void)
15182 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15185 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15188 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15189 affected if we specify unsigned args. */
15190 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15193 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15195 V<op> A,B (A is operand 0, B is operand 2)
15200 so handle that case specially. */
15203 neon_exchange_operands (void)
15205 if (inst
.operands
[1].present
)
15207 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15209 /* Swap operands[1] and operands[2]. */
15210 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15211 inst
.operands
[1] = inst
.operands
[2];
15212 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15217 inst
.operands
[1] = inst
.operands
[2];
15218 inst
.operands
[2] = inst
.operands
[0];
15223 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15225 if (inst
.operands
[2].isreg
)
15228 neon_exchange_operands ();
15229 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15233 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15234 struct neon_type_el et
= neon_check_type (2, rs
,
15235 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15237 NEON_ENCODE (IMMED
, inst
);
15238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15240 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15241 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15242 inst
.instruction
|= neon_quad (rs
) << 6;
15243 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15244 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15246 neon_dp_fixup (&inst
);
15253 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15257 do_neon_cmp_inv (void)
15259 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15265 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15268 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15269 scalars, which are encoded in 5 bits, M : Rm.
15270 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15271 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15274 Dot Product instructions are similar to multiply instructions except elsize
15275 should always be 32.
15277 This function translates SCALAR, which is GAS's internal encoding of indexed
15278 scalar register, to raw encoding. There is also register and index range
15279 check based on ELSIZE. */
15282 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15284 unsigned regno
= NEON_SCALAR_REG (scalar
);
15285 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15290 if (regno
> 7 || elno
> 3)
15292 return regno
| (elno
<< 3);
15295 if (regno
> 15 || elno
> 1)
15297 return regno
| (elno
<< 4);
15301 first_error (_("scalar out of range for multiply instruction"));
15307 /* Encode multiply / multiply-accumulate scalar instructions. */
15310 neon_mul_mac (struct neon_type_el et
, int ubit
)
15314 /* Give a more helpful error message if we have an invalid type. */
15315 if (et
.type
== NT_invtype
)
15318 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15321 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15322 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15323 inst
.instruction
|= LOW4 (scalar
);
15324 inst
.instruction
|= HI1 (scalar
) << 5;
15325 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15326 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15327 inst
.instruction
|= (ubit
!= 0) << 24;
15329 neon_dp_fixup (&inst
);
15333 do_neon_mac_maybe_scalar (void)
15335 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15338 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15341 if (inst
.operands
[2].isscalar
)
15343 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15344 struct neon_type_el et
= neon_check_type (3, rs
,
15345 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15346 NEON_ENCODE (SCALAR
, inst
);
15347 neon_mul_mac (et
, neon_quad (rs
));
15351 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15352 affected if we specify unsigned args. */
15353 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15358 do_neon_fmac (void)
15360 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15363 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15366 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15372 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15373 struct neon_type_el et
= neon_check_type (3, rs
,
15374 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15375 neon_three_same (neon_quad (rs
), 0, et
.size
);
15378 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15379 same types as the MAC equivalents. The polynomial type for this instruction
15380 is encoded the same as the integer type. */
15385 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15388 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15391 if (inst
.operands
[2].isscalar
)
15392 do_neon_mac_maybe_scalar ();
15394 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15398 do_neon_qdmulh (void)
15400 if (inst
.operands
[2].isscalar
)
15402 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15403 struct neon_type_el et
= neon_check_type (3, rs
,
15404 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15405 NEON_ENCODE (SCALAR
, inst
);
15406 neon_mul_mac (et
, neon_quad (rs
));
15410 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15411 struct neon_type_el et
= neon_check_type (3, rs
,
15412 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15413 NEON_ENCODE (INTEGER
, inst
);
15414 /* The U bit (rounding) comes from bit mask. */
15415 neon_three_same (neon_quad (rs
), 0, et
.size
);
15420 do_neon_qrdmlah (void)
15422 /* Check we're on the correct architecture. */
15423 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15425 _("instruction form not available on this architecture.");
15426 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15428 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15429 record_feature_use (&fpu_neon_ext_v8_1
);
15432 if (inst
.operands
[2].isscalar
)
15434 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15435 struct neon_type_el et
= neon_check_type (3, rs
,
15436 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15437 NEON_ENCODE (SCALAR
, inst
);
15438 neon_mul_mac (et
, neon_quad (rs
));
15442 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15443 struct neon_type_el et
= neon_check_type (3, rs
,
15444 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15445 NEON_ENCODE (INTEGER
, inst
);
15446 /* The U bit (rounding) comes from bit mask. */
15447 neon_three_same (neon_quad (rs
), 0, et
.size
);
15452 do_neon_fcmp_absolute (void)
15454 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15455 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15456 N_F_16_32
| N_KEY
);
15457 /* Size field comes from bit mask. */
15458 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15462 do_neon_fcmp_absolute_inv (void)
15464 neon_exchange_operands ();
15465 do_neon_fcmp_absolute ();
15469 do_neon_step (void)
15471 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15472 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15473 N_F_16_32
| N_KEY
);
15474 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15478 do_neon_abs_neg (void)
15480 enum neon_shape rs
;
15481 struct neon_type_el et
;
15483 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15486 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15489 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15490 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15492 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15493 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15494 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15495 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15496 inst
.instruction
|= neon_quad (rs
) << 6;
15497 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15498 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15500 neon_dp_fixup (&inst
);
15506 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15507 struct neon_type_el et
= neon_check_type (2, rs
,
15508 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15509 int imm
= inst
.operands
[2].imm
;
15510 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15511 _("immediate out of range for insert"));
15512 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15518 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15519 struct neon_type_el et
= neon_check_type (2, rs
,
15520 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15521 int imm
= inst
.operands
[2].imm
;
15522 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15523 _("immediate out of range for insert"));
15524 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15528 do_neon_qshlu_imm (void)
15530 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15531 struct neon_type_el et
= neon_check_type (2, rs
,
15532 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15533 int imm
= inst
.operands
[2].imm
;
15534 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15535 _("immediate out of range for shift"));
15536 /* Only encodes the 'U present' variant of the instruction.
15537 In this case, signed types have OP (bit 8) set to 0.
15538 Unsigned types have OP set to 1. */
15539 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15540 /* The rest of the bits are the same as other immediate shifts. */
15541 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15545 do_neon_qmovn (void)
15547 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15548 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15549 /* Saturating move where operands can be signed or unsigned, and the
15550 destination has the same signedness. */
15551 NEON_ENCODE (INTEGER
, inst
);
15552 if (et
.type
== NT_unsigned
)
15553 inst
.instruction
|= 0xc0;
15555 inst
.instruction
|= 0x80;
15556 neon_two_same (0, 1, et
.size
/ 2);
15560 do_neon_qmovun (void)
15562 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15563 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15564 /* Saturating move with unsigned results. Operands must be signed. */
15565 NEON_ENCODE (INTEGER
, inst
);
15566 neon_two_same (0, 1, et
.size
/ 2);
15570 do_neon_rshift_sat_narrow (void)
15572 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15573 or unsigned. If operands are unsigned, results must also be unsigned. */
15574 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15575 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15576 int imm
= inst
.operands
[2].imm
;
15577 /* This gets the bounds check, size encoding and immediate bits calculation
15581 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15582 VQMOVN.I<size> <Dd>, <Qm>. */
15585 inst
.operands
[2].present
= 0;
15586 inst
.instruction
= N_MNEM_vqmovn
;
15591 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15592 _("immediate out of range"));
15593 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15597 do_neon_rshift_sat_narrow_u (void)
15599 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15600 or unsigned. If operands are unsigned, results must also be unsigned. */
15601 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15602 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15603 int imm
= inst
.operands
[2].imm
;
15604 /* This gets the bounds check, size encoding and immediate bits calculation
15608 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15609 VQMOVUN.I<size> <Dd>, <Qm>. */
15612 inst
.operands
[2].present
= 0;
15613 inst
.instruction
= N_MNEM_vqmovun
;
15618 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15619 _("immediate out of range"));
15620 /* FIXME: The manual is kind of unclear about what value U should have in
15621 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15623 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15627 do_neon_movn (void)
15629 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15630 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15631 NEON_ENCODE (INTEGER
, inst
);
15632 neon_two_same (0, 1, et
.size
/ 2);
15636 do_neon_rshift_narrow (void)
15638 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15639 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15640 int imm
= inst
.operands
[2].imm
;
15641 /* This gets the bounds check, size encoding and immediate bits calculation
15645 /* If immediate is zero then we are a pseudo-instruction for
15646 VMOVN.I<size> <Dd>, <Qm> */
15649 inst
.operands
[2].present
= 0;
15650 inst
.instruction
= N_MNEM_vmovn
;
15655 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15656 _("immediate out of range for narrowing operation"));
15657 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15661 do_neon_shll (void)
15663 /* FIXME: Type checking when lengthening. */
15664 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15665 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15666 unsigned imm
= inst
.operands
[2].imm
;
15668 if (imm
== et
.size
)
15670 /* Maximum shift variant. */
15671 NEON_ENCODE (INTEGER
, inst
);
15672 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15673 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15674 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15675 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15676 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15678 neon_dp_fixup (&inst
);
15682 /* A more-specific type check for non-max versions. */
15683 et
= neon_check_type (2, NS_QDI
,
15684 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15685 NEON_ENCODE (IMMED
, inst
);
15686 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15690 /* Check the various types for the VCVT instruction, and return which version
15691 the current instruction is. */
15693 #define CVT_FLAVOUR_VAR \
15694 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15695 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15696 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15697 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15698 /* Half-precision conversions. */ \
15699 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15700 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15701 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15702 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15703 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15704 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15705 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15706 Compared with single/double precision variants, only the co-processor \
15707 field is different, so the encoding flow is reused here. */ \
15708 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15709 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15710 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15711 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15712 /* VFP instructions. */ \
15713 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15714 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15715 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15716 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15717 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15718 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15719 /* VFP instructions with bitshift. */ \
15720 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15721 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15722 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15723 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15724 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15725 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15726 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15727 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15729 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15730 neon_cvt_flavour_##C,
15732 /* The different types of conversions we can do. */
15733 enum neon_cvt_flavour
15736 neon_cvt_flavour_invalid
,
15737 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15742 static enum neon_cvt_flavour
15743 get_neon_cvt_flavour (enum neon_shape rs
)
15745 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15746 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15747 if (et.type != NT_invtype) \
15749 inst.error = NULL; \
15750 return (neon_cvt_flavour_##C); \
15753 struct neon_type_el et
;
15754 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15755 || rs
== NS_FF
) ? N_VFP
: 0;
15756 /* The instruction versions which take an immediate take one register
15757 argument, which is extended to the width of the full register. Thus the
15758 "source" and "destination" registers must have the same width. Hack that
15759 here by making the size equal to the key (wider, in this case) operand. */
15760 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15764 return neon_cvt_flavour_invalid
;
15779 /* Neon-syntax VFP conversions. */
15782 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15784 const char *opname
= 0;
15786 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15787 || rs
== NS_FHI
|| rs
== NS_HFI
)
15789 /* Conversions with immediate bitshift. */
15790 const char *enc
[] =
15792 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15798 if (flavour
< (int) ARRAY_SIZE (enc
))
15800 opname
= enc
[flavour
];
15801 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15802 _("operands 0 and 1 must be the same register"));
15803 inst
.operands
[1] = inst
.operands
[2];
15804 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15809 /* Conversions without bitshift. */
15810 const char *enc
[] =
15812 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15818 if (flavour
< (int) ARRAY_SIZE (enc
))
15819 opname
= enc
[flavour
];
15823 do_vfp_nsyn_opcode (opname
);
15825 /* ARMv8.2 fp16 VCVT instruction. */
15826 if (flavour
== neon_cvt_flavour_s32_f16
15827 || flavour
== neon_cvt_flavour_u32_f16
15828 || flavour
== neon_cvt_flavour_f16_u32
15829 || flavour
== neon_cvt_flavour_f16_s32
)
15830 do_scalar_fp16_v82_encode ();
15834 do_vfp_nsyn_cvtz (void)
15836 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15837 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15838 const char *enc
[] =
15840 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15846 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15847 do_vfp_nsyn_opcode (enc
[flavour
]);
15851 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15852 enum neon_cvt_mode mode
)
15857 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15858 D register operands. */
15859 if (flavour
== neon_cvt_flavour_s32_f64
15860 || flavour
== neon_cvt_flavour_u32_f64
)
15861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15864 if (flavour
== neon_cvt_flavour_s32_f16
15865 || flavour
== neon_cvt_flavour_u32_f16
)
15866 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15869 set_it_insn_type (OUTSIDE_IT_INSN
);
15873 case neon_cvt_flavour_s32_f64
:
15877 case neon_cvt_flavour_s32_f32
:
15881 case neon_cvt_flavour_s32_f16
:
15885 case neon_cvt_flavour_u32_f64
:
15889 case neon_cvt_flavour_u32_f32
:
15893 case neon_cvt_flavour_u32_f16
:
15898 first_error (_("invalid instruction shape"));
15904 case neon_cvt_mode_a
: rm
= 0; break;
15905 case neon_cvt_mode_n
: rm
= 1; break;
15906 case neon_cvt_mode_p
: rm
= 2; break;
15907 case neon_cvt_mode_m
: rm
= 3; break;
15908 default: first_error (_("invalid rounding mode")); return;
15911 NEON_ENCODE (FPV8
, inst
);
15912 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15913 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15914 inst
.instruction
|= sz
<< 8;
15916 /* ARMv8.2 fp16 VCVT instruction. */
15917 if (flavour
== neon_cvt_flavour_s32_f16
15918 ||flavour
== neon_cvt_flavour_u32_f16
)
15919 do_scalar_fp16_v82_encode ();
15920 inst
.instruction
|= op
<< 7;
15921 inst
.instruction
|= rm
<< 16;
15922 inst
.instruction
|= 0xf0000000;
15923 inst
.is_neon
= TRUE
;
15927 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15929 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15930 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15931 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15933 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15935 if (flavour
== neon_cvt_flavour_invalid
)
15938 /* PR11109: Handle round-to-zero for VCVT conversions. */
15939 if (mode
== neon_cvt_mode_z
15940 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15941 && (flavour
== neon_cvt_flavour_s16_f16
15942 || flavour
== neon_cvt_flavour_u16_f16
15943 || flavour
== neon_cvt_flavour_s32_f32
15944 || flavour
== neon_cvt_flavour_u32_f32
15945 || flavour
== neon_cvt_flavour_s32_f64
15946 || flavour
== neon_cvt_flavour_u32_f64
)
15947 && (rs
== NS_FD
|| rs
== NS_FF
))
15949 do_vfp_nsyn_cvtz ();
15953 /* ARMv8.2 fp16 VCVT conversions. */
15954 if (mode
== neon_cvt_mode_z
15955 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15956 && (flavour
== neon_cvt_flavour_s32_f16
15957 || flavour
== neon_cvt_flavour_u32_f16
)
15960 do_vfp_nsyn_cvtz ();
15961 do_scalar_fp16_v82_encode ();
15965 /* VFP rather than Neon conversions. */
15966 if (flavour
>= neon_cvt_flavour_first_fp
)
15968 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15969 do_vfp_nsyn_cvt (rs
, flavour
);
15971 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15982 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15983 0x0000100, 0x1000100, 0x0, 0x1000000};
15985 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15988 /* Fixed-point conversion with #0 immediate is encoded as an
15989 integer conversion. */
15990 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15992 NEON_ENCODE (IMMED
, inst
);
15993 if (flavour
!= neon_cvt_flavour_invalid
)
15994 inst
.instruction
|= enctab
[flavour
];
15995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15999 inst
.instruction
|= neon_quad (rs
) << 6;
16000 inst
.instruction
|= 1 << 21;
16001 if (flavour
< neon_cvt_flavour_s16_f16
)
16003 inst
.instruction
|= 1 << 21;
16004 immbits
= 32 - inst
.operands
[2].imm
;
16005 inst
.instruction
|= immbits
<< 16;
16009 inst
.instruction
|= 3 << 20;
16010 immbits
= 16 - inst
.operands
[2].imm
;
16011 inst
.instruction
|= immbits
<< 16;
16012 inst
.instruction
&= ~(1 << 9);
16015 neon_dp_fixup (&inst
);
16021 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
16023 NEON_ENCODE (FLOAT
, inst
);
16024 set_it_insn_type (OUTSIDE_IT_INSN
);
16026 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16030 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16033 inst
.instruction
|= neon_quad (rs
) << 6;
16034 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
16035 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
16036 inst
.instruction
|= mode
<< 8;
16037 if (flavour
== neon_cvt_flavour_u16_f16
16038 || flavour
== neon_cvt_flavour_s16_f16
)
16039 /* Mask off the original size bits and reencode them. */
16040 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
16043 inst
.instruction
|= 0xfc000000;
16045 inst
.instruction
|= 0xf0000000;
16051 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
16052 0x100, 0x180, 0x0, 0x080};
16054 NEON_ENCODE (INTEGER
, inst
);
16056 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16059 if (flavour
!= neon_cvt_flavour_invalid
)
16060 inst
.instruction
|= enctab
[flavour
];
16062 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16063 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16064 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16065 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16066 inst
.instruction
|= neon_quad (rs
) << 6;
16067 if (flavour
>= neon_cvt_flavour_s16_f16
16068 && flavour
<= neon_cvt_flavour_f16_u16
)
16069 /* Half precision. */
16070 inst
.instruction
|= 1 << 18;
16072 inst
.instruction
|= 2 << 18;
16074 neon_dp_fixup (&inst
);
16079 /* Half-precision conversions for Advanced SIMD -- neon. */
16082 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16086 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
16088 as_bad (_("operand size must match register width"));
16093 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
16095 as_bad (_("operand size must match register width"));
16100 inst
.instruction
= 0x3b60600;
16102 inst
.instruction
= 0x3b60700;
16104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16105 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16106 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16107 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16108 neon_dp_fixup (&inst
);
16112 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
16113 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16114 do_vfp_nsyn_cvt (rs
, flavour
);
16116 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16121 do_neon_cvtr (void)
16123 do_neon_cvt_1 (neon_cvt_mode_x
);
16129 do_neon_cvt_1 (neon_cvt_mode_z
);
16133 do_neon_cvta (void)
16135 do_neon_cvt_1 (neon_cvt_mode_a
);
16139 do_neon_cvtn (void)
16141 do_neon_cvt_1 (neon_cvt_mode_n
);
16145 do_neon_cvtp (void)
16147 do_neon_cvt_1 (neon_cvt_mode_p
);
16151 do_neon_cvtm (void)
16153 do_neon_cvt_1 (neon_cvt_mode_m
);
16157 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16160 mark_feature_used (&fpu_vfp_ext_armv8
);
16162 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16163 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16164 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16165 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16166 inst
.instruction
|= to
? 0x10000 : 0;
16167 inst
.instruction
|= t
? 0x80 : 0;
16168 inst
.instruction
|= is_double
? 0x100 : 0;
16169 do_vfp_cond_or_thumb ();
16173 do_neon_cvttb_1 (bfd_boolean t
)
16175 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16176 NS_DF
, NS_DH
, NS_NULL
);
16180 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16183 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16185 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16188 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16190 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16192 /* The VCVTB and VCVTT instructions with D-register operands
16193 don't work for SP only targets. */
16194 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16198 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16200 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16202 /* The VCVTB and VCVTT instructions with D-register operands
16203 don't work for SP only targets. */
16204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16208 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16215 do_neon_cvtb (void)
16217 do_neon_cvttb_1 (FALSE
);
16222 do_neon_cvtt (void)
16224 do_neon_cvttb_1 (TRUE
);
16228 neon_move_immediate (void)
16230 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16231 struct neon_type_el et
= neon_check_type (2, rs
,
16232 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16233 unsigned immlo
, immhi
= 0, immbits
;
16234 int op
, cmode
, float_p
;
16236 constraint (et
.type
== NT_invtype
,
16237 _("operand size must be specified for immediate VMOV"));
16239 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16240 op
= (inst
.instruction
& (1 << 5)) != 0;
16242 immlo
= inst
.operands
[1].imm
;
16243 if (inst
.operands
[1].regisimm
)
16244 immhi
= inst
.operands
[1].reg
;
16246 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16247 _("immediate has bits set outside the operand size"));
16249 float_p
= inst
.operands
[1].immisfloat
;
16251 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16252 et
.size
, et
.type
)) == FAIL
)
16254 /* Invert relevant bits only. */
16255 neon_invert_size (&immlo
, &immhi
, et
.size
);
16256 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16257 with one or the other; those cases are caught by
16258 neon_cmode_for_move_imm. */
16260 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16261 &op
, et
.size
, et
.type
)) == FAIL
)
16263 first_error (_("immediate out of range"));
16268 inst
.instruction
&= ~(1 << 5);
16269 inst
.instruction
|= op
<< 5;
16271 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16273 inst
.instruction
|= neon_quad (rs
) << 6;
16274 inst
.instruction
|= cmode
<< 8;
16276 neon_write_immbits (immbits
);
16282 if (inst
.operands
[1].isreg
)
16284 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16286 NEON_ENCODE (INTEGER
, inst
);
16287 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16288 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16289 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16290 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16291 inst
.instruction
|= neon_quad (rs
) << 6;
16295 NEON_ENCODE (IMMED
, inst
);
16296 neon_move_immediate ();
16299 neon_dp_fixup (&inst
);
16302 /* Encode instructions of form:
16304 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16305 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16308 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16310 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16311 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16312 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16313 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16314 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16315 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16316 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16317 inst
.instruction
|= neon_logbits (size
) << 20;
16319 neon_dp_fixup (&inst
);
16323 do_neon_dyadic_long (void)
16325 /* FIXME: Type checking for lengthening op. */
16326 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16327 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16328 neon_mixed_length (et
, et
.size
);
16332 do_neon_abal (void)
16334 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16335 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16336 neon_mixed_length (et
, et
.size
);
16340 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16342 if (inst
.operands
[2].isscalar
)
16344 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16345 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16346 NEON_ENCODE (SCALAR
, inst
);
16347 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16351 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16352 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16353 NEON_ENCODE (INTEGER
, inst
);
16354 neon_mixed_length (et
, et
.size
);
16359 do_neon_mac_maybe_scalar_long (void)
16361 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16364 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16365 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16368 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16370 unsigned regno
= NEON_SCALAR_REG (scalar
);
16371 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16375 if (regno
> 7 || elno
> 3)
16378 return ((regno
& 0x7)
16379 | ((elno
& 0x1) << 3)
16380 | (((elno
>> 1) & 0x1) << 5));
16384 if (regno
> 15 || elno
> 1)
16387 return (((regno
& 0x1) << 5)
16388 | ((regno
>> 1) & 0x7)
16389 | ((elno
& 0x1) << 3));
16393 first_error (_("scalar out of range for multiply instruction"));
16398 do_neon_fmac_maybe_scalar_long (int subtype
)
16400 enum neon_shape rs
;
16402 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16403 field (bits[21:20]) has different meaning. For scalar index variant, it's
16404 used to differentiate add and subtract, otherwise it's with fixed value
16408 if (inst
.cond
!= COND_ALWAYS
)
16409 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16410 "behaviour is UNPREDICTABLE"));
16412 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16415 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16418 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16419 be a scalar index register. */
16420 if (inst
.operands
[2].isscalar
)
16422 high8
= 0xfe000000;
16425 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16429 high8
= 0xfc000000;
16432 inst
.instruction
|= (0x1 << 23);
16433 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16436 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16438 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16439 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16440 so we simply pass -1 as size. */
16441 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16442 neon_three_same (quad_p
, 0, size
);
16444 /* Undo neon_dp_fixup. Redo the high eight bits. */
16445 inst
.instruction
&= 0x00ffffff;
16446 inst
.instruction
|= high8
;
16448 #define LOW1(R) ((R) & 0x1)
16449 #define HI4(R) (((R) >> 1) & 0xf)
16450 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16451 whether the instruction is in Q form and whether Vm is a scalar indexed
16453 if (inst
.operands
[2].isscalar
)
16456 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16457 inst
.instruction
&= 0xffffffd0;
16458 inst
.instruction
|= rm
;
16462 /* Redo Rn as well. */
16463 inst
.instruction
&= 0xfff0ff7f;
16464 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16465 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16470 /* Redo Rn and Rm. */
16471 inst
.instruction
&= 0xfff0ff50;
16472 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16473 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16474 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16475 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16480 do_neon_vfmal (void)
16482 return do_neon_fmac_maybe_scalar_long (0);
16486 do_neon_vfmsl (void)
16488 return do_neon_fmac_maybe_scalar_long (1);
16492 do_neon_dyadic_wide (void)
16494 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16495 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16496 neon_mixed_length (et
, et
.size
);
16500 do_neon_dyadic_narrow (void)
16502 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16503 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16504 /* Operand sign is unimportant, and the U bit is part of the opcode,
16505 so force the operand type to integer. */
16506 et
.type
= NT_integer
;
16507 neon_mixed_length (et
, et
.size
/ 2);
16511 do_neon_mul_sat_scalar_long (void)
16513 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16517 do_neon_vmull (void)
16519 if (inst
.operands
[2].isscalar
)
16520 do_neon_mac_maybe_scalar_long ();
16523 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16524 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16526 if (et
.type
== NT_poly
)
16527 NEON_ENCODE (POLY
, inst
);
16529 NEON_ENCODE (INTEGER
, inst
);
16531 /* For polynomial encoding the U bit must be zero, and the size must
16532 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16533 obviously, as 0b10). */
16536 /* Check we're on the correct architecture. */
16537 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16539 _("Instruction form not available on this architecture.");
16544 neon_mixed_length (et
, et
.size
);
16551 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16552 struct neon_type_el et
= neon_check_type (3, rs
,
16553 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16554 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16556 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16557 _("shift out of range"));
16558 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16559 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16560 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16561 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16562 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16563 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16564 inst
.instruction
|= neon_quad (rs
) << 6;
16565 inst
.instruction
|= imm
<< 8;
16567 neon_dp_fixup (&inst
);
16573 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16574 struct neon_type_el et
= neon_check_type (2, rs
,
16575 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16576 unsigned op
= (inst
.instruction
>> 7) & 3;
16577 /* N (width of reversed regions) is encoded as part of the bitmask. We
16578 extract it here to check the elements to be reversed are smaller.
16579 Otherwise we'd get a reserved instruction. */
16580 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16581 gas_assert (elsize
!= 0);
16582 constraint (et
.size
>= elsize
,
16583 _("elements must be smaller than reversal region"));
16584 neon_two_same (neon_quad (rs
), 1, et
.size
);
16590 if (inst
.operands
[1].isscalar
)
16592 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16593 struct neon_type_el et
= neon_check_type (2, rs
,
16594 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16595 unsigned sizebits
= et
.size
>> 3;
16596 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16597 int logsize
= neon_logbits (et
.size
);
16598 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16600 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16603 NEON_ENCODE (SCALAR
, inst
);
16604 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16605 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16606 inst
.instruction
|= LOW4 (dm
);
16607 inst
.instruction
|= HI1 (dm
) << 5;
16608 inst
.instruction
|= neon_quad (rs
) << 6;
16609 inst
.instruction
|= x
<< 17;
16610 inst
.instruction
|= sizebits
<< 16;
16612 neon_dp_fixup (&inst
);
16616 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16617 struct neon_type_el et
= neon_check_type (2, rs
,
16618 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16619 /* Duplicate ARM register to lanes of vector. */
16620 NEON_ENCODE (ARMREG
, inst
);
16623 case 8: inst
.instruction
|= 0x400000; break;
16624 case 16: inst
.instruction
|= 0x000020; break;
16625 case 32: inst
.instruction
|= 0x000000; break;
16628 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16629 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16631 inst
.instruction
|= neon_quad (rs
) << 21;
16632 /* The encoding for this instruction is identical for the ARM and Thumb
16633 variants, except for the condition field. */
16634 do_vfp_cond_or_thumb ();
16638 /* VMOV has particularly many variations. It can be one of:
16639 0. VMOV<c><q> <Qd>, <Qm>
16640 1. VMOV<c><q> <Dd>, <Dm>
16641 (Register operations, which are VORR with Rm = Rn.)
16642 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16643 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16645 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16646 (ARM register to scalar.)
16647 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16648 (Two ARM registers to vector.)
16649 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16650 (Scalar to ARM register.)
16651 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16652 (Vector to two ARM registers.)
16653 8. VMOV.F32 <Sd>, <Sm>
16654 9. VMOV.F64 <Dd>, <Dm>
16655 (VFP register moves.)
16656 10. VMOV.F32 <Sd>, #imm
16657 11. VMOV.F64 <Dd>, #imm
16658 (VFP float immediate load.)
16659 12. VMOV <Rd>, <Sm>
16660 (VFP single to ARM reg.)
16661 13. VMOV <Sd>, <Rm>
16662 (ARM reg to VFP single.)
16663 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16664 (Two ARM regs to two VFP singles.)
16665 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16666 (Two VFP singles to two ARM regs.)
16668 These cases can be disambiguated using neon_select_shape, except cases 1/9
16669 and 3/11 which depend on the operand type too.
16671 All the encoded bits are hardcoded by this function.
16673 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16674 Cases 5, 7 may be used with VFPv2 and above.
16676 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16677 can specify a type where it doesn't make sense to, and is ignored). */
16682 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16683 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16684 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16685 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16686 struct neon_type_el et
;
16687 const char *ldconst
= 0;
16691 case NS_DD
: /* case 1/9. */
16692 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16693 /* It is not an error here if no type is given. */
16695 if (et
.type
== NT_float
&& et
.size
== 64)
16697 do_vfp_nsyn_opcode ("fcpyd");
16700 /* fall through. */
16702 case NS_QQ
: /* case 0/1. */
16704 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16706 /* The architecture manual I have doesn't explicitly state which
16707 value the U bit should have for register->register moves, but
16708 the equivalent VORR instruction has U = 0, so do that. */
16709 inst
.instruction
= 0x0200110;
16710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16716 inst
.instruction
|= neon_quad (rs
) << 6;
16718 neon_dp_fixup (&inst
);
16722 case NS_DI
: /* case 3/11. */
16723 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16725 if (et
.type
== NT_float
&& et
.size
== 64)
16727 /* case 11 (fconstd). */
16728 ldconst
= "fconstd";
16729 goto encode_fconstd
;
16731 /* fall through. */
16733 case NS_QI
: /* case 2/3. */
16734 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16736 inst
.instruction
= 0x0800010;
16737 neon_move_immediate ();
16738 neon_dp_fixup (&inst
);
16741 case NS_SR
: /* case 4. */
16743 unsigned bcdebits
= 0;
16745 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16746 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16748 /* .<size> is optional here, defaulting to .32. */
16749 if (inst
.vectype
.elems
== 0
16750 && inst
.operands
[0].vectype
.type
== NT_invtype
16751 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16753 inst
.vectype
.el
[0].type
= NT_untyped
;
16754 inst
.vectype
.el
[0].size
= 32;
16755 inst
.vectype
.elems
= 1;
16758 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16759 logsize
= neon_logbits (et
.size
);
16761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16763 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16764 && et
.size
!= 32, _(BAD_FPU
));
16765 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16766 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16770 case 8: bcdebits
= 0x8; break;
16771 case 16: bcdebits
= 0x1; break;
16772 case 32: bcdebits
= 0x0; break;
16776 bcdebits
|= x
<< logsize
;
16778 inst
.instruction
= 0xe000b10;
16779 do_vfp_cond_or_thumb ();
16780 inst
.instruction
|= LOW4 (dn
) << 16;
16781 inst
.instruction
|= HI1 (dn
) << 7;
16782 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16783 inst
.instruction
|= (bcdebits
& 3) << 5;
16784 inst
.instruction
|= (bcdebits
>> 2) << 21;
16788 case NS_DRR
: /* case 5 (fmdrr). */
16789 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16792 inst
.instruction
= 0xc400b10;
16793 do_vfp_cond_or_thumb ();
16794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16796 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16797 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16800 case NS_RS
: /* case 6. */
16803 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16804 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16805 unsigned abcdebits
= 0;
16807 /* .<dt> is optional here, defaulting to .32. */
16808 if (inst
.vectype
.elems
== 0
16809 && inst
.operands
[0].vectype
.type
== NT_invtype
16810 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16812 inst
.vectype
.el
[0].type
= NT_untyped
;
16813 inst
.vectype
.el
[0].size
= 32;
16814 inst
.vectype
.elems
= 1;
16817 et
= neon_check_type (2, NS_NULL
,
16818 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16819 logsize
= neon_logbits (et
.size
);
16821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16823 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16824 && et
.size
!= 32, _(BAD_FPU
));
16825 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16826 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16830 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16831 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16832 case 32: abcdebits
= 0x00; break;
16836 abcdebits
|= x
<< logsize
;
16837 inst
.instruction
= 0xe100b10;
16838 do_vfp_cond_or_thumb ();
16839 inst
.instruction
|= LOW4 (dn
) << 16;
16840 inst
.instruction
|= HI1 (dn
) << 7;
16841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16842 inst
.instruction
|= (abcdebits
& 3) << 5;
16843 inst
.instruction
|= (abcdebits
>> 2) << 21;
16847 case NS_RRD
: /* case 7 (fmrrd). */
16848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16851 inst
.instruction
= 0xc500b10;
16852 do_vfp_cond_or_thumb ();
16853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16854 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16855 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16856 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16859 case NS_FF
: /* case 8 (fcpys). */
16860 do_vfp_nsyn_opcode ("fcpys");
16864 case NS_FI
: /* case 10 (fconsts). */
16865 ldconst
= "fconsts";
16867 if (!inst
.operands
[1].immisfloat
)
16870 /* Immediate has to fit in 8 bits so float is enough. */
16871 float imm
= (float) inst
.operands
[1].imm
;
16872 memcpy (&new_imm
, &imm
, sizeof (float));
16873 /* But the assembly may have been written to provide an integer
16874 bit pattern that equates to a float, so check that the
16875 conversion has worked. */
16876 if (is_quarter_float (new_imm
))
16878 if (is_quarter_float (inst
.operands
[1].imm
))
16879 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16881 inst
.operands
[1].imm
= new_imm
;
16882 inst
.operands
[1].immisfloat
= 1;
16886 if (is_quarter_float (inst
.operands
[1].imm
))
16888 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16889 do_vfp_nsyn_opcode (ldconst
);
16891 /* ARMv8.2 fp16 vmov.f16 instruction. */
16893 do_scalar_fp16_v82_encode ();
16896 first_error (_("immediate out of range"));
16900 case NS_RF
: /* case 12 (fmrs). */
16901 do_vfp_nsyn_opcode ("fmrs");
16902 /* ARMv8.2 fp16 vmov.f16 instruction. */
16904 do_scalar_fp16_v82_encode ();
16908 case NS_FR
: /* case 13 (fmsr). */
16909 do_vfp_nsyn_opcode ("fmsr");
16910 /* ARMv8.2 fp16 vmov.f16 instruction. */
16912 do_scalar_fp16_v82_encode ();
16915 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16916 (one of which is a list), but we have parsed four. Do some fiddling to
16917 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16919 case NS_RRFF
: /* case 14 (fmrrs). */
16920 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16921 _("VFP registers must be adjacent"));
16922 inst
.operands
[2].imm
= 2;
16923 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16924 do_vfp_nsyn_opcode ("fmrrs");
16927 case NS_FFRR
: /* case 15 (fmsrr). */
16928 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16929 _("VFP registers must be adjacent"));
16930 inst
.operands
[1] = inst
.operands
[2];
16931 inst
.operands
[2] = inst
.operands
[3];
16932 inst
.operands
[0].imm
= 2;
16933 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16934 do_vfp_nsyn_opcode ("fmsrr");
16938 /* neon_select_shape has determined that the instruction
16939 shape is wrong and has already set the error message. */
16948 do_neon_rshift_round_imm (void)
16950 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16951 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16952 int imm
= inst
.operands
[2].imm
;
16954 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16957 inst
.operands
[2].present
= 0;
16962 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16963 _("immediate out of range for shift"));
16964 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16969 do_neon_movhf (void)
16971 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16972 constraint (rs
!= NS_HH
, _("invalid suffix"));
16974 if (inst
.cond
!= COND_ALWAYS
)
16978 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16979 " the behaviour is UNPREDICTABLE"));
16983 inst
.error
= BAD_COND
;
16988 do_vfp_sp_monadic ();
16991 inst
.instruction
|= 0xf0000000;
16995 do_neon_movl (void)
16997 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16998 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16999 unsigned sizebits
= et
.size
>> 3;
17000 inst
.instruction
|= sizebits
<< 19;
17001 neon_two_same (0, et
.type
== NT_unsigned
, -1);
17007 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17008 struct neon_type_el et
= neon_check_type (2, rs
,
17009 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17010 NEON_ENCODE (INTEGER
, inst
);
17011 neon_two_same (neon_quad (rs
), 1, et
.size
);
17015 do_neon_zip_uzp (void)
17017 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17018 struct neon_type_el et
= neon_check_type (2, rs
,
17019 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17020 if (rs
== NS_DD
&& et
.size
== 32)
17022 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
17023 inst
.instruction
= N_MNEM_vtrn
;
17027 neon_two_same (neon_quad (rs
), 1, et
.size
);
17031 do_neon_sat_abs_neg (void)
17033 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17034 struct neon_type_el et
= neon_check_type (2, rs
,
17035 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17036 neon_two_same (neon_quad (rs
), 1, et
.size
);
17040 do_neon_pair_long (void)
17042 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17043 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17044 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
17045 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
17046 neon_two_same (neon_quad (rs
), 1, et
.size
);
17050 do_neon_recip_est (void)
17052 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17053 struct neon_type_el et
= neon_check_type (2, rs
,
17054 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
17055 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17056 neon_two_same (neon_quad (rs
), 1, et
.size
);
17062 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17063 struct neon_type_el et
= neon_check_type (2, rs
,
17064 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17065 neon_two_same (neon_quad (rs
), 1, et
.size
);
17071 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17072 struct neon_type_el et
= neon_check_type (2, rs
,
17073 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
17074 neon_two_same (neon_quad (rs
), 1, et
.size
);
17080 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17081 struct neon_type_el et
= neon_check_type (2, rs
,
17082 N_EQK
| N_INT
, N_8
| N_KEY
);
17083 neon_two_same (neon_quad (rs
), 1, et
.size
);
17089 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17090 neon_two_same (neon_quad (rs
), 1, -1);
17094 do_neon_tbl_tbx (void)
17096 unsigned listlenbits
;
17097 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
17099 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
17101 first_error (_("bad list length for table lookup"));
17105 listlenbits
= inst
.operands
[1].imm
- 1;
17106 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17107 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17108 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17109 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17110 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17111 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17112 inst
.instruction
|= listlenbits
<< 8;
17114 neon_dp_fixup (&inst
);
17118 do_neon_ldm_stm (void)
17120 /* P, U and L bits are part of bitmask. */
17121 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
17122 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
17124 if (inst
.operands
[1].issingle
)
17126 do_vfp_nsyn_ldm_stm (is_dbmode
);
17130 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
17131 _("writeback (!) must be used for VLDMDB and VSTMDB"));
17133 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
17134 _("register list must contain at least 1 and at most 16 "
17137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
17138 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17139 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17140 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17142 inst
.instruction
|= offsetbits
;
17144 do_vfp_cond_or_thumb ();
17148 do_neon_ldr_str (void)
17150 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17152 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17153 And is UNPREDICTABLE in thumb mode. */
17155 && inst
.operands
[1].reg
== REG_PC
17156 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17159 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17160 else if (warn_on_deprecated
)
17161 as_tsktsk (_("Use of PC here is deprecated"));
17164 if (inst
.operands
[0].issingle
)
17167 do_vfp_nsyn_opcode ("flds");
17169 do_vfp_nsyn_opcode ("fsts");
17171 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17172 if (inst
.vectype
.el
[0].size
== 16)
17173 do_scalar_fp16_v82_encode ();
17178 do_vfp_nsyn_opcode ("fldd");
17180 do_vfp_nsyn_opcode ("fstd");
17184 /* "interleave" version also handles non-interleaving register VLD1/VST1
17188 do_neon_ld_st_interleave (void)
17190 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17191 N_8
| N_16
| N_32
| N_64
);
17192 unsigned alignbits
= 0;
17194 /* The bits in this table go:
17195 0: register stride of one (0) or two (1)
17196 1,2: register list length, minus one (1, 2, 3, 4).
17197 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17198 We use -1 for invalid entries. */
17199 const int typetable
[] =
17201 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17202 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17203 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17204 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17208 if (et
.type
== NT_invtype
)
17211 if (inst
.operands
[1].immisalign
)
17212 switch (inst
.operands
[1].imm
>> 8)
17214 case 64: alignbits
= 1; break;
17216 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17217 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17218 goto bad_alignment
;
17222 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17223 goto bad_alignment
;
17228 first_error (_("bad alignment"));
17232 inst
.instruction
|= alignbits
<< 4;
17233 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17235 /* Bits [4:6] of the immediate in a list specifier encode register stride
17236 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17237 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17238 up the right value for "type" in a table based on this value and the given
17239 list style, then stick it back. */
17240 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17241 | (((inst
.instruction
>> 8) & 3) << 3);
17243 typebits
= typetable
[idx
];
17245 constraint (typebits
== -1, _("bad list type for instruction"));
17246 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17247 _("bad element type for instruction"));
17249 inst
.instruction
&= ~0xf00;
17250 inst
.instruction
|= typebits
<< 8;
17253 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17254 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17255 otherwise. The variable arguments are a list of pairs of legal (size, align)
17256 values, terminated with -1. */
17259 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17262 int result
= FAIL
, thissize
, thisalign
;
17264 if (!inst
.operands
[1].immisalign
)
17270 va_start (ap
, do_alignment
);
17274 thissize
= va_arg (ap
, int);
17275 if (thissize
== -1)
17277 thisalign
= va_arg (ap
, int);
17279 if (size
== thissize
&& align
== thisalign
)
17282 while (result
!= SUCCESS
);
17286 if (result
== SUCCESS
)
17289 first_error (_("unsupported alignment for instruction"));
17295 do_neon_ld_st_lane (void)
17297 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17298 int align_good
, do_alignment
= 0;
17299 int logsize
= neon_logbits (et
.size
);
17300 int align
= inst
.operands
[1].imm
>> 8;
17301 int n
= (inst
.instruction
>> 8) & 3;
17302 int max_el
= 64 / et
.size
;
17304 if (et
.type
== NT_invtype
)
17307 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17308 _("bad list length"));
17309 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17310 _("scalar index out of range"));
17311 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17313 _("stride of 2 unavailable when element size is 8"));
17317 case 0: /* VLD1 / VST1. */
17318 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17320 if (align_good
== FAIL
)
17324 unsigned alignbits
= 0;
17327 case 16: alignbits
= 0x1; break;
17328 case 32: alignbits
= 0x3; break;
17331 inst
.instruction
|= alignbits
<< 4;
17335 case 1: /* VLD2 / VST2. */
17336 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17337 16, 32, 32, 64, -1);
17338 if (align_good
== FAIL
)
17341 inst
.instruction
|= 1 << 4;
17344 case 2: /* VLD3 / VST3. */
17345 constraint (inst
.operands
[1].immisalign
,
17346 _("can't use alignment with this instruction"));
17349 case 3: /* VLD4 / VST4. */
17350 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17351 16, 64, 32, 64, 32, 128, -1);
17352 if (align_good
== FAIL
)
17356 unsigned alignbits
= 0;
17359 case 8: alignbits
= 0x1; break;
17360 case 16: alignbits
= 0x1; break;
17361 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17364 inst
.instruction
|= alignbits
<< 4;
17371 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17372 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17373 inst
.instruction
|= 1 << (4 + logsize
);
17375 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17376 inst
.instruction
|= logsize
<< 10;
17379 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17382 do_neon_ld_dup (void)
17384 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17385 int align_good
, do_alignment
= 0;
17387 if (et
.type
== NT_invtype
)
17390 switch ((inst
.instruction
>> 8) & 3)
17392 case 0: /* VLD1. */
17393 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17394 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17395 &do_alignment
, 16, 16, 32, 32, -1);
17396 if (align_good
== FAIL
)
17398 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17401 case 2: inst
.instruction
|= 1 << 5; break;
17402 default: first_error (_("bad list length")); return;
17404 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17407 case 1: /* VLD2. */
17408 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17409 &do_alignment
, 8, 16, 16, 32, 32, 64,
17411 if (align_good
== FAIL
)
17413 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17414 _("bad list length"));
17415 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17416 inst
.instruction
|= 1 << 5;
17417 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17420 case 2: /* VLD3. */
17421 constraint (inst
.operands
[1].immisalign
,
17422 _("can't use alignment with this instruction"));
17423 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17424 _("bad list length"));
17425 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17426 inst
.instruction
|= 1 << 5;
17427 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17430 case 3: /* VLD4. */
17432 int align
= inst
.operands
[1].imm
>> 8;
17433 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17434 16, 64, 32, 64, 32, 128, -1);
17435 if (align_good
== FAIL
)
17437 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17438 _("bad list length"));
17439 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17440 inst
.instruction
|= 1 << 5;
17441 if (et
.size
== 32 && align
== 128)
17442 inst
.instruction
|= 0x3 << 6;
17444 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17451 inst
.instruction
|= do_alignment
<< 4;
17454 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17455 apart from bits [11:4]. */
17458 do_neon_ldx_stx (void)
17460 if (inst
.operands
[1].isreg
)
17461 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17463 switch (NEON_LANE (inst
.operands
[0].imm
))
17465 case NEON_INTERLEAVE_LANES
:
17466 NEON_ENCODE (INTERLV
, inst
);
17467 do_neon_ld_st_interleave ();
17470 case NEON_ALL_LANES
:
17471 NEON_ENCODE (DUP
, inst
);
17472 if (inst
.instruction
== N_INV
)
17474 first_error ("only loads support such operands");
17481 NEON_ENCODE (LANE
, inst
);
17482 do_neon_ld_st_lane ();
17485 /* L bit comes from bit mask. */
17486 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17487 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17488 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17490 if (inst
.operands
[1].postind
)
17492 int postreg
= inst
.operands
[1].imm
& 0xf;
17493 constraint (!inst
.operands
[1].immisreg
,
17494 _("post-index must be a register"));
17495 constraint (postreg
== 0xd || postreg
== 0xf,
17496 _("bad register for post-index"));
17497 inst
.instruction
|= postreg
;
17501 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17502 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
17503 || inst
.relocs
[0].exp
.X_add_number
!= 0,
17506 if (inst
.operands
[1].writeback
)
17508 inst
.instruction
|= 0xd;
17511 inst
.instruction
|= 0xf;
17515 inst
.instruction
|= 0xf9000000;
17517 inst
.instruction
|= 0xf4000000;
17522 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17524 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17525 D register operands. */
17526 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17527 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17530 NEON_ENCODE (FPV8
, inst
);
17532 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17534 do_vfp_sp_dyadic ();
17536 /* ARMv8.2 fp16 instruction. */
17538 do_scalar_fp16_v82_encode ();
17541 do_vfp_dp_rd_rn_rm ();
17544 inst
.instruction
|= 0x100;
17546 inst
.instruction
|= 0xf0000000;
17552 set_it_insn_type (OUTSIDE_IT_INSN
);
17554 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17555 first_error (_("invalid instruction shape"));
17561 set_it_insn_type (OUTSIDE_IT_INSN
);
17563 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17566 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17569 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17573 do_vrint_1 (enum neon_cvt_mode mode
)
17575 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17576 struct neon_type_el et
;
17581 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17582 D register operands. */
17583 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17587 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17589 if (et
.type
!= NT_invtype
)
17591 /* VFP encodings. */
17592 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17593 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17594 set_it_insn_type (OUTSIDE_IT_INSN
);
17596 NEON_ENCODE (FPV8
, inst
);
17597 if (rs
== NS_FF
|| rs
== NS_HH
)
17598 do_vfp_sp_monadic ();
17600 do_vfp_dp_rd_rm ();
17604 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17605 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17606 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17607 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17608 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17609 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17610 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17614 inst
.instruction
|= (rs
== NS_DD
) << 8;
17615 do_vfp_cond_or_thumb ();
17617 /* ARMv8.2 fp16 vrint instruction. */
17619 do_scalar_fp16_v82_encode ();
17623 /* Neon encodings (or something broken...). */
17625 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17627 if (et
.type
== NT_invtype
)
17630 set_it_insn_type (OUTSIDE_IT_INSN
);
17631 NEON_ENCODE (FLOAT
, inst
);
17633 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17636 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17637 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17639 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17640 inst
.instruction
|= neon_quad (rs
) << 6;
17641 /* Mask off the original size bits and reencode them. */
17642 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17643 | neon_logbits (et
.size
) << 18);
17647 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17648 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17649 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17650 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17651 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17652 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17653 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17658 inst
.instruction
|= 0xfc000000;
17660 inst
.instruction
|= 0xf0000000;
17667 do_vrint_1 (neon_cvt_mode_x
);
17673 do_vrint_1 (neon_cvt_mode_z
);
17679 do_vrint_1 (neon_cvt_mode_r
);
17685 do_vrint_1 (neon_cvt_mode_a
);
17691 do_vrint_1 (neon_cvt_mode_n
);
17697 do_vrint_1 (neon_cvt_mode_p
);
17703 do_vrint_1 (neon_cvt_mode_m
);
17707 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17709 unsigned regno
= NEON_SCALAR_REG (opnd
);
17710 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17712 if (elsize
== 16 && elno
< 2 && regno
< 16)
17713 return regno
| (elno
<< 4);
17714 else if (elsize
== 32 && elno
== 0)
17717 first_error (_("scalar out of range"));
17724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17726 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17727 _("expression too complex"));
17728 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17729 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17730 _("immediate out of range"));
17732 if (inst
.operands
[2].isscalar
)
17734 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17735 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17736 N_KEY
| N_F16
| N_F32
).size
;
17737 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17739 inst
.instruction
= 0xfe000800;
17740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17742 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17743 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17744 inst
.instruction
|= LOW4 (m
);
17745 inst
.instruction
|= HI1 (m
) << 5;
17746 inst
.instruction
|= neon_quad (rs
) << 6;
17747 inst
.instruction
|= rot
<< 20;
17748 inst
.instruction
|= (size
== 32) << 23;
17752 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17753 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17754 N_KEY
| N_F16
| N_F32
).size
;
17755 neon_three_same (neon_quad (rs
), 0, -1);
17756 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17757 inst
.instruction
|= 0xfc200800;
17758 inst
.instruction
|= rot
<< 23;
17759 inst
.instruction
|= (size
== 32) << 20;
17766 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17768 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17769 _("expression too complex"));
17770 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17771 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17772 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17773 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17774 N_KEY
| N_F16
| N_F32
).size
;
17775 neon_three_same (neon_quad (rs
), 0, -1);
17776 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17777 inst
.instruction
|= 0xfc800800;
17778 inst
.instruction
|= (rot
== 270) << 24;
17779 inst
.instruction
|= (size
== 32) << 20;
17782 /* Dot Product instructions encoding support. */
17785 do_neon_dotproduct (int unsigned_p
)
17787 enum neon_shape rs
;
17788 unsigned scalar_oprd2
= 0;
17791 if (inst
.cond
!= COND_ALWAYS
)
17792 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17793 "is UNPREDICTABLE"));
17795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17798 /* Dot Product instructions are in three-same D/Q register format or the third
17799 operand can be a scalar index register. */
17800 if (inst
.operands
[2].isscalar
)
17802 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17803 high8
= 0xfe000000;
17804 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17808 high8
= 0xfc000000;
17809 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17813 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17815 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17817 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17818 Product instruction, so we pass 0 as the "ubit" parameter. And the
17819 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17820 neon_three_same (neon_quad (rs
), 0, 32);
17822 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17823 different NEON three-same encoding. */
17824 inst
.instruction
&= 0x00ffffff;
17825 inst
.instruction
|= high8
;
17826 /* Encode 'U' bit which indicates signedness. */
17827 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17828 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17829 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17830 the instruction encoding. */
17831 if (inst
.operands
[2].isscalar
)
17833 inst
.instruction
&= 0xffffffd0;
17834 inst
.instruction
|= LOW4 (scalar_oprd2
);
17835 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17839 /* Dot Product instructions for signed integer. */
17842 do_neon_dotproduct_s (void)
17844 return do_neon_dotproduct (0);
17847 /* Dot Product instructions for unsigned integer. */
17850 do_neon_dotproduct_u (void)
17852 return do_neon_dotproduct (1);
17855 /* Crypto v1 instructions. */
17857 do_crypto_2op_1 (unsigned elttype
, int op
)
17859 set_it_insn_type (OUTSIDE_IT_INSN
);
17861 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17867 NEON_ENCODE (INTEGER
, inst
);
17868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17870 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17871 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17873 inst
.instruction
|= op
<< 6;
17876 inst
.instruction
|= 0xfc000000;
17878 inst
.instruction
|= 0xf0000000;
17882 do_crypto_3op_1 (int u
, int op
)
17884 set_it_insn_type (OUTSIDE_IT_INSN
);
17886 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17887 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17892 NEON_ENCODE (INTEGER
, inst
);
17893 neon_three_same (1, u
, 8 << op
);
17899 do_crypto_2op_1 (N_8
, 0);
17905 do_crypto_2op_1 (N_8
, 1);
17911 do_crypto_2op_1 (N_8
, 2);
17917 do_crypto_2op_1 (N_8
, 3);
17923 do_crypto_3op_1 (0, 0);
17929 do_crypto_3op_1 (0, 1);
17935 do_crypto_3op_1 (0, 2);
17941 do_crypto_3op_1 (0, 3);
17947 do_crypto_3op_1 (1, 0);
17953 do_crypto_3op_1 (1, 1);
17957 do_sha256su1 (void)
17959 do_crypto_3op_1 (1, 2);
17965 do_crypto_2op_1 (N_32
, -1);
17971 do_crypto_2op_1 (N_32
, 0);
17975 do_sha256su0 (void)
17977 do_crypto_2op_1 (N_32
, 1);
17981 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17983 unsigned int Rd
= inst
.operands
[0].reg
;
17984 unsigned int Rn
= inst
.operands
[1].reg
;
17985 unsigned int Rm
= inst
.operands
[2].reg
;
17987 set_it_insn_type (OUTSIDE_IT_INSN
);
17988 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17989 inst
.instruction
|= LOW4 (Rn
) << 16;
17990 inst
.instruction
|= LOW4 (Rm
);
17991 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17992 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17994 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17995 as_warn (UNPRED_REG ("r15"));
18037 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18039 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
18040 do_vfp_sp_dp_cvt ();
18041 do_vfp_cond_or_thumb ();
18045 /* Overall per-instruction processing. */
18047 /* We need to be able to fix up arbitrary expressions in some statements.
18048 This is so that we can handle symbols that are an arbitrary distance from
18049 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
18050 which returns part of an address in a form which will be valid for
18051 a data instruction. We do this by pushing the expression into a symbol
18052 in the expr_section, and creating a fix for that. */
18055 fix_new_arm (fragS
* frag
,
18069 /* Create an absolute valued symbol, so we have something to
18070 refer to in the object file. Unfortunately for us, gas's
18071 generic expression parsing will already have folded out
18072 any use of .set foo/.type foo %function that may have
18073 been used to set type information of the target location,
18074 that's being specified symbolically. We have to presume
18075 the user knows what they are doing. */
18079 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
18081 symbol
= symbol_find_or_make (name
);
18082 S_SET_SEGMENT (symbol
, absolute_section
);
18083 symbol_set_frag (symbol
, &zero_address_frag
);
18084 S_SET_VALUE (symbol
, exp
->X_add_number
);
18085 exp
->X_op
= O_symbol
;
18086 exp
->X_add_symbol
= symbol
;
18087 exp
->X_add_number
= 0;
18093 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
18094 (enum bfd_reloc_code_real
) reloc
);
18098 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
18099 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
18103 /* Mark whether the fix is to a THUMB instruction, or an ARM
18105 new_fix
->tc_fix_data
= thumb_mode
;
18108 /* Create a frg for an instruction requiring relaxation. */
18110 output_relax_insn (void)
18116 /* The size of the instruction is unknown, so tie the debug info to the
18117 start of the instruction. */
18118 dwarf2_emit_insn (0);
18120 switch (inst
.relocs
[0].exp
.X_op
)
18123 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
18124 offset
= inst
.relocs
[0].exp
.X_add_number
;
18128 offset
= inst
.relocs
[0].exp
.X_add_number
;
18131 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
18135 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
18136 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
18137 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
18140 /* Write a 32-bit thumb instruction to buf. */
18142 put_thumb32_insn (char * buf
, unsigned long insn
)
18144 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18145 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18149 output_inst (const char * str
)
18155 as_bad ("%s -- `%s'", inst
.error
, str
);
18160 output_relax_insn ();
18163 if (inst
.size
== 0)
18166 to
= frag_more (inst
.size
);
18167 /* PR 9814: Record the thumb mode into the current frag so that we know
18168 what type of NOP padding to use, if necessary. We override any previous
18169 setting so that if the mode has changed then the NOPS that we use will
18170 match the encoding of the last instruction in the frag. */
18171 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18173 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18175 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18176 put_thumb32_insn (to
, inst
.instruction
);
18178 else if (inst
.size
> INSN_SIZE
)
18180 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18181 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18182 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18185 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18188 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18190 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
18191 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18192 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
18193 inst
.relocs
[r
].type
);
18196 dwarf2_emit_insn (inst
.size
);
18200 output_it_inst (int cond
, int mask
, char * to
)
18202 unsigned long instruction
= 0xbf00;
18205 instruction
|= mask
;
18206 instruction
|= cond
<< 4;
18210 to
= frag_more (2);
18212 dwarf2_emit_insn (2);
18216 md_number_to_chars (to
, instruction
, 2);
18221 /* Tag values used in struct asm_opcode's tag field. */
18224 OT_unconditional
, /* Instruction cannot be conditionalized.
18225 The ARM condition field is still 0xE. */
18226 OT_unconditionalF
, /* Instruction cannot be conditionalized
18227 and carries 0xF in its ARM condition field. */
18228 OT_csuffix
, /* Instruction takes a conditional suffix. */
18229 OT_csuffixF
, /* Some forms of the instruction take a conditional
18230 suffix, others place 0xF where the condition field
18232 OT_cinfix3
, /* Instruction takes a conditional infix,
18233 beginning at character index 3. (In
18234 unified mode, it becomes a suffix.) */
18235 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18236 tsts, cmps, cmns, and teqs. */
18237 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18238 character index 3, even in unified mode. Used for
18239 legacy instructions where suffix and infix forms
18240 may be ambiguous. */
18241 OT_csuf_or_in3
, /* Instruction takes either a conditional
18242 suffix or an infix at character index 3. */
18243 OT_odd_infix_unc
, /* This is the unconditional variant of an
18244 instruction that takes a conditional infix
18245 at an unusual position. In unified mode,
18246 this variant will accept a suffix. */
18247 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18248 are the conditional variants of instructions that
18249 take conditional infixes in unusual positions.
18250 The infix appears at character index
18251 (tag - OT_odd_infix_0). These are not accepted
18252 in unified mode. */
18255 /* Subroutine of md_assemble, responsible for looking up the primary
18256 opcode from the mnemonic the user wrote. STR points to the
18257 beginning of the mnemonic.
18259 This is not simply a hash table lookup, because of conditional
18260 variants. Most instructions have conditional variants, which are
18261 expressed with a _conditional affix_ to the mnemonic. If we were
18262 to encode each conditional variant as a literal string in the opcode
18263 table, it would have approximately 20,000 entries.
18265 Most mnemonics take this affix as a suffix, and in unified syntax,
18266 'most' is upgraded to 'all'. However, in the divided syntax, some
18267 instructions take the affix as an infix, notably the s-variants of
18268 the arithmetic instructions. Of those instructions, all but six
18269 have the infix appear after the third character of the mnemonic.
18271 Accordingly, the algorithm for looking up primary opcodes given
18274 1. Look up the identifier in the opcode table.
18275 If we find a match, go to step U.
18277 2. Look up the last two characters of the identifier in the
18278 conditions table. If we find a match, look up the first N-2
18279 characters of the identifier in the opcode table. If we
18280 find a match, go to step CE.
18282 3. Look up the fourth and fifth characters of the identifier in
18283 the conditions table. If we find a match, extract those
18284 characters from the identifier, and look up the remaining
18285 characters in the opcode table. If we find a match, go
18290 U. Examine the tag field of the opcode structure, in case this is
18291 one of the six instructions with its conditional infix in an
18292 unusual place. If it is, the tag tells us where to find the
18293 infix; look it up in the conditions table and set inst.cond
18294 accordingly. Otherwise, this is an unconditional instruction.
18295 Again set inst.cond accordingly. Return the opcode structure.
18297 CE. Examine the tag field to make sure this is an instruction that
18298 should receive a conditional suffix. If it is not, fail.
18299 Otherwise, set inst.cond from the suffix we already looked up,
18300 and return the opcode structure.
18302 CM. Examine the tag field to make sure this is an instruction that
18303 should receive a conditional infix after the third character.
18304 If it is not, fail. Otherwise, undo the edits to the current
18305 line of input and proceed as for case CE. */
18307 static const struct asm_opcode
*
18308 opcode_lookup (char **str
)
18312 const struct asm_opcode
*opcode
;
18313 const struct asm_cond
*cond
;
18316 /* Scan up to the end of the mnemonic, which must end in white space,
18317 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18318 for (base
= end
= *str
; *end
!= '\0'; end
++)
18319 if (*end
== ' ' || *end
== '.')
18325 /* Handle a possible width suffix and/or Neon type suffix. */
18330 /* The .w and .n suffixes are only valid if the unified syntax is in
18332 if (unified_syntax
&& end
[1] == 'w')
18334 else if (unified_syntax
&& end
[1] == 'n')
18339 inst
.vectype
.elems
= 0;
18341 *str
= end
+ offset
;
18343 if (end
[offset
] == '.')
18345 /* See if we have a Neon type suffix (possible in either unified or
18346 non-unified ARM syntax mode). */
18347 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18350 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18356 /* Look for unaffixed or special-case affixed mnemonic. */
18357 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18362 if (opcode
->tag
< OT_odd_infix_0
)
18364 inst
.cond
= COND_ALWAYS
;
18368 if (warn_on_deprecated
&& unified_syntax
)
18369 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18370 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18371 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18374 inst
.cond
= cond
->value
;
18378 /* Cannot have a conditional suffix on a mnemonic of less than two
18380 if (end
- base
< 3)
18383 /* Look for suffixed mnemonic. */
18385 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18386 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18388 if (opcode
&& cond
)
18391 switch (opcode
->tag
)
18393 case OT_cinfix3_legacy
:
18394 /* Ignore conditional suffixes matched on infix only mnemonics. */
18398 case OT_cinfix3_deprecated
:
18399 case OT_odd_infix_unc
:
18400 if (!unified_syntax
)
18402 /* Fall through. */
18406 case OT_csuf_or_in3
:
18407 inst
.cond
= cond
->value
;
18410 case OT_unconditional
:
18411 case OT_unconditionalF
:
18413 inst
.cond
= cond
->value
;
18416 /* Delayed diagnostic. */
18417 inst
.error
= BAD_COND
;
18418 inst
.cond
= COND_ALWAYS
;
18427 /* Cannot have a usual-position infix on a mnemonic of less than
18428 six characters (five would be a suffix). */
18429 if (end
- base
< 6)
18432 /* Look for infixed mnemonic in the usual position. */
18434 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18438 memcpy (save
, affix
, 2);
18439 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18440 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18442 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18443 memcpy (affix
, save
, 2);
18446 && (opcode
->tag
== OT_cinfix3
18447 || opcode
->tag
== OT_cinfix3_deprecated
18448 || opcode
->tag
== OT_csuf_or_in3
18449 || opcode
->tag
== OT_cinfix3_legacy
))
18452 if (warn_on_deprecated
&& unified_syntax
18453 && (opcode
->tag
== OT_cinfix3
18454 || opcode
->tag
== OT_cinfix3_deprecated
))
18455 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18457 inst
.cond
= cond
->value
;
18464 /* This function generates an initial IT instruction, leaving its block
18465 virtually open for the new instructions. Eventually,
18466 the mask will be updated by now_it_add_mask () each time
18467 a new instruction needs to be included in the IT block.
18468 Finally, the block is closed with close_automatic_it_block ().
18469 The block closure can be requested either from md_assemble (),
18470 a tencode (), or due to a label hook. */
18473 new_automatic_it_block (int cond
)
18475 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18476 now_it
.mask
= 0x18;
18478 now_it
.block_length
= 1;
18479 mapping_state (MAP_THUMB
);
18480 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18481 now_it
.warn_deprecated
= FALSE
;
18482 now_it
.insn_cond
= TRUE
;
18485 /* Close an automatic IT block.
18486 See comments in new_automatic_it_block (). */
18489 close_automatic_it_block (void)
18491 now_it
.mask
= 0x10;
18492 now_it
.block_length
= 0;
18495 /* Update the mask of the current automatically-generated IT
18496 instruction. See comments in new_automatic_it_block (). */
18499 now_it_add_mask (int cond
)
18501 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18502 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18503 | ((bitvalue) << (nbit)))
18504 const int resulting_bit
= (cond
& 1);
18506 now_it
.mask
&= 0xf;
18507 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18509 (5 - now_it
.block_length
));
18510 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18512 ((5 - now_it
.block_length
) - 1) );
18513 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18516 #undef SET_BIT_VALUE
18519 /* The IT blocks handling machinery is accessed through the these functions:
18520 it_fsm_pre_encode () from md_assemble ()
18521 set_it_insn_type () optional, from the tencode functions
18522 set_it_insn_type_last () ditto
18523 in_it_block () ditto
18524 it_fsm_post_encode () from md_assemble ()
18525 force_automatic_it_block_close () from label handling functions
18528 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18529 initializing the IT insn type with a generic initial value depending
18530 on the inst.condition.
18531 2) During the tencode function, two things may happen:
18532 a) The tencode function overrides the IT insn type by
18533 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18534 b) The tencode function queries the IT block state by
18535 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18537 Both set_it_insn_type and in_it_block run the internal FSM state
18538 handling function (handle_it_state), because: a) setting the IT insn
18539 type may incur in an invalid state (exiting the function),
18540 and b) querying the state requires the FSM to be updated.
18541 Specifically we want to avoid creating an IT block for conditional
18542 branches, so it_fsm_pre_encode is actually a guess and we can't
18543 determine whether an IT block is required until the tencode () routine
18544 has decided what type of instruction this actually it.
18545 Because of this, if set_it_insn_type and in_it_block have to be used,
18546 set_it_insn_type has to be called first.
18548 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18549 determines the insn IT type depending on the inst.cond code.
18550 When a tencode () routine encodes an instruction that can be
18551 either outside an IT block, or, in the case of being inside, has to be
18552 the last one, set_it_insn_type_last () will determine the proper
18553 IT instruction type based on the inst.cond code. Otherwise,
18554 set_it_insn_type can be called for overriding that logic or
18555 for covering other cases.
18557 Calling handle_it_state () may not transition the IT block state to
18558 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18559 still queried. Instead, if the FSM determines that the state should
18560 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18561 after the tencode () function: that's what it_fsm_post_encode () does.
18563 Since in_it_block () calls the state handling function to get an
18564 updated state, an error may occur (due to invalid insns combination).
18565 In that case, inst.error is set.
18566 Therefore, inst.error has to be checked after the execution of
18567 the tencode () routine.
18569 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18570 any pending state change (if any) that didn't take place in
18571 handle_it_state () as explained above. */
18574 it_fsm_pre_encode (void)
18576 if (inst
.cond
!= COND_ALWAYS
)
18577 inst
.it_insn_type
= INSIDE_IT_INSN
;
18579 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18581 now_it
.state_handled
= 0;
18584 /* IT state FSM handling function. */
18587 handle_it_state (void)
18589 now_it
.state_handled
= 1;
18590 now_it
.insn_cond
= FALSE
;
18592 switch (now_it
.state
)
18594 case OUTSIDE_IT_BLOCK
:
18595 switch (inst
.it_insn_type
)
18597 case OUTSIDE_IT_INSN
:
18600 case INSIDE_IT_INSN
:
18601 case INSIDE_IT_LAST_INSN
:
18602 if (thumb_mode
== 0)
18605 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18606 as_tsktsk (_("Warning: conditional outside an IT block"\
18611 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18612 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18614 /* Automatically generate the IT instruction. */
18615 new_automatic_it_block (inst
.cond
);
18616 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18617 close_automatic_it_block ();
18621 inst
.error
= BAD_OUT_IT
;
18627 case IF_INSIDE_IT_LAST_INSN
:
18628 case NEUTRAL_IT_INSN
:
18632 now_it
.state
= MANUAL_IT_BLOCK
;
18633 now_it
.block_length
= 0;
18638 case AUTOMATIC_IT_BLOCK
:
18639 /* Three things may happen now:
18640 a) We should increment current it block size;
18641 b) We should close current it block (closing insn or 4 insns);
18642 c) We should close current it block and start a new one (due
18643 to incompatible conditions or
18644 4 insns-length block reached). */
18646 switch (inst
.it_insn_type
)
18648 case OUTSIDE_IT_INSN
:
18649 /* The closure of the block shall happen immediately,
18650 so any in_it_block () call reports the block as closed. */
18651 force_automatic_it_block_close ();
18654 case INSIDE_IT_INSN
:
18655 case INSIDE_IT_LAST_INSN
:
18656 case IF_INSIDE_IT_LAST_INSN
:
18657 now_it
.block_length
++;
18659 if (now_it
.block_length
> 4
18660 || !now_it_compatible (inst
.cond
))
18662 force_automatic_it_block_close ();
18663 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18664 new_automatic_it_block (inst
.cond
);
18668 now_it
.insn_cond
= TRUE
;
18669 now_it_add_mask (inst
.cond
);
18672 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18673 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18674 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18675 close_automatic_it_block ();
18678 case NEUTRAL_IT_INSN
:
18679 now_it
.block_length
++;
18680 now_it
.insn_cond
= TRUE
;
18682 if (now_it
.block_length
> 4)
18683 force_automatic_it_block_close ();
18685 now_it_add_mask (now_it
.cc
& 1);
18689 close_automatic_it_block ();
18690 now_it
.state
= MANUAL_IT_BLOCK
;
18695 case MANUAL_IT_BLOCK
:
18697 /* Check conditional suffixes. */
18698 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18701 now_it
.mask
&= 0x1f;
18702 is_last
= (now_it
.mask
== 0x10);
18703 now_it
.insn_cond
= TRUE
;
18705 switch (inst
.it_insn_type
)
18707 case OUTSIDE_IT_INSN
:
18708 inst
.error
= BAD_NOT_IT
;
18711 case INSIDE_IT_INSN
:
18712 if (cond
!= inst
.cond
)
18714 inst
.error
= BAD_IT_COND
;
18719 case INSIDE_IT_LAST_INSN
:
18720 case IF_INSIDE_IT_LAST_INSN
:
18721 if (cond
!= inst
.cond
)
18723 inst
.error
= BAD_IT_COND
;
18728 inst
.error
= BAD_BRANCH
;
18733 case NEUTRAL_IT_INSN
:
18734 /* The BKPT instruction is unconditional even in an IT block. */
18738 inst
.error
= BAD_IT_IT
;
18748 struct depr_insn_mask
18750 unsigned long pattern
;
18751 unsigned long mask
;
18752 const char* description
;
18755 /* List of 16-bit instruction patterns deprecated in an IT block in
18757 static const struct depr_insn_mask depr_it_insns
[] = {
18758 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18759 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18760 { 0xa000, 0xb800, N_("ADR") },
18761 { 0x4800, 0xf800, N_("Literal loads") },
18762 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18763 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18764 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18765 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18766 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18771 it_fsm_post_encode (void)
18775 if (!now_it
.state_handled
)
18776 handle_it_state ();
18778 if (now_it
.insn_cond
18779 && !now_it
.warn_deprecated
18780 && warn_on_deprecated
18781 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18782 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18784 if (inst
.instruction
>= 0x10000)
18786 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18787 "performance deprecated in ARMv8-A and ARMv8-R"));
18788 now_it
.warn_deprecated
= TRUE
;
18792 const struct depr_insn_mask
*p
= depr_it_insns
;
18794 while (p
->mask
!= 0)
18796 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18798 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18799 "instructions of the following class are "
18800 "performance deprecated in ARMv8-A and "
18801 "ARMv8-R: %s"), p
->description
);
18802 now_it
.warn_deprecated
= TRUE
;
18810 if (now_it
.block_length
> 1)
18812 as_tsktsk (_("IT blocks containing more than one conditional "
18813 "instruction are performance deprecated in ARMv8-A and "
18815 now_it
.warn_deprecated
= TRUE
;
18819 is_last
= (now_it
.mask
== 0x10);
18822 now_it
.state
= OUTSIDE_IT_BLOCK
;
18828 force_automatic_it_block_close (void)
18830 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18832 close_automatic_it_block ();
18833 now_it
.state
= OUTSIDE_IT_BLOCK
;
18841 if (!now_it
.state_handled
)
18842 handle_it_state ();
18844 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18847 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18848 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18849 here, hence the "known" in the function name. */
18852 known_t32_only_insn (const struct asm_opcode
*opcode
)
18854 /* Original Thumb-1 wide instruction. */
18855 if (opcode
->tencode
== do_t_blx
18856 || opcode
->tencode
== do_t_branch23
18857 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18858 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18861 /* Wide-only instruction added to ARMv8-M Baseline. */
18862 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18863 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18864 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18865 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18871 /* Whether wide instruction variant can be used if available for a valid OPCODE
18875 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18877 if (known_t32_only_insn (opcode
))
18880 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18881 of variant T3 of B.W is checked in do_t_branch. */
18882 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18883 && opcode
->tencode
== do_t_branch
)
18886 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18887 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18888 && opcode
->tencode
== do_t_mov_cmp
18889 /* Make sure CMP instruction is not affected. */
18890 && opcode
->aencode
== do_mov
)
18893 /* Wide instruction variants of all instructions with narrow *and* wide
18894 variants become available with ARMv6t2. Other opcodes are either
18895 narrow-only or wide-only and are thus available if OPCODE is valid. */
18896 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18899 /* OPCODE with narrow only instruction variant or wide variant not
18905 md_assemble (char *str
)
18908 const struct asm_opcode
* opcode
;
18910 /* Align the previous label if needed. */
18911 if (last_label_seen
!= NULL
)
18913 symbol_set_frag (last_label_seen
, frag_now
);
18914 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18915 S_SET_SEGMENT (last_label_seen
, now_seg
);
18918 memset (&inst
, '\0', sizeof (inst
));
18920 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18921 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
18923 opcode
= opcode_lookup (&p
);
18926 /* It wasn't an instruction, but it might be a register alias of
18927 the form alias .req reg, or a Neon .dn/.qn directive. */
18928 if (! create_register_alias (str
, p
)
18929 && ! create_neon_reg_alias (str
, p
))
18930 as_bad (_("bad instruction `%s'"), str
);
18935 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18936 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18938 /* The value which unconditional instructions should have in place of the
18939 condition field. */
18940 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18944 arm_feature_set variant
;
18946 variant
= cpu_variant
;
18947 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18948 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18949 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18950 /* Check that this instruction is supported for this CPU. */
18951 if (!opcode
->tvariant
18952 || (thumb_mode
== 1
18953 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18955 if (opcode
->tencode
== do_t_swi
)
18956 as_bad (_("SVC is not permitted on this architecture"));
18958 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18961 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18962 && opcode
->tencode
!= do_t_branch
)
18964 as_bad (_("Thumb does not support conditional execution"));
18968 /* Two things are addressed here:
18969 1) Implicit require narrow instructions on Thumb-1.
18970 This avoids relaxation accidentally introducing Thumb-2
18972 2) Reject wide instructions in non Thumb-2 cores.
18974 Only instructions with narrow and wide variants need to be handled
18975 but selecting all non wide-only instructions is easier. */
18976 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18977 && !t32_insn_ok (variant
, opcode
))
18979 if (inst
.size_req
== 0)
18981 else if (inst
.size_req
== 4)
18983 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18984 as_bad (_("selected processor does not support 32bit wide "
18985 "variant of instruction `%s'"), str
);
18987 as_bad (_("selected processor does not support `%s' in "
18988 "Thumb-2 mode"), str
);
18993 inst
.instruction
= opcode
->tvalue
;
18995 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18997 /* Prepare the it_insn_type for those encodings that don't set
18999 it_fsm_pre_encode ();
19001 opcode
->tencode ();
19003 it_fsm_post_encode ();
19006 if (!(inst
.error
|| inst
.relax
))
19008 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
19009 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
19010 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
19012 as_bad (_("cannot honor width suffix -- `%s'"), str
);
19017 /* Something has gone badly wrong if we try to relax a fixed size
19019 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
19021 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19022 *opcode
->tvariant
);
19023 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
19024 set those bits when Thumb-2 32-bit instructions are seen. The impact
19025 of relaxable instructions will be considered later after we finish all
19027 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
19028 variant
= arm_arch_none
;
19030 variant
= cpu_variant
;
19031 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
19032 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19035 check_neon_suffixes
;
19039 mapping_state (MAP_THUMB
);
19042 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19046 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
19047 is_bx
= (opcode
->aencode
== do_bx
);
19049 /* Check that this instruction is supported for this CPU. */
19050 if (!(is_bx
&& fix_v4bx
)
19051 && !(opcode
->avariant
&&
19052 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
19054 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
19059 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
19063 inst
.instruction
= opcode
->avalue
;
19064 if (opcode
->tag
== OT_unconditionalF
)
19065 inst
.instruction
|= 0xFU
<< 28;
19067 inst
.instruction
|= inst
.cond
<< 28;
19068 inst
.size
= INSN_SIZE
;
19069 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
19071 it_fsm_pre_encode ();
19072 opcode
->aencode ();
19073 it_fsm_post_encode ();
19075 /* Arm mode bx is marked as both v4T and v5 because it's still required
19076 on a hypothetical non-thumb v5 core. */
19078 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
19080 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
19081 *opcode
->avariant
);
19083 check_neon_suffixes
;
19087 mapping_state (MAP_ARM
);
19092 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
19100 check_it_blocks_finished (void)
19105 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
19106 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
19107 == MANUAL_IT_BLOCK
)
19109 as_warn (_("section '%s' finished with an open IT block."),
19113 if (now_it
.state
== MANUAL_IT_BLOCK
)
19114 as_warn (_("file finished with an open IT block."));
19118 /* Various frobbings of labels and their addresses. */
19121 arm_start_line_hook (void)
19123 last_label_seen
= NULL
;
19127 arm_frob_label (symbolS
* sym
)
19129 last_label_seen
= sym
;
19131 ARM_SET_THUMB (sym
, thumb_mode
);
19133 #if defined OBJ_COFF || defined OBJ_ELF
19134 ARM_SET_INTERWORK (sym
, support_interwork
);
19137 force_automatic_it_block_close ();
19139 /* Note - do not allow local symbols (.Lxxx) to be labelled
19140 as Thumb functions. This is because these labels, whilst
19141 they exist inside Thumb code, are not the entry points for
19142 possible ARM->Thumb calls. Also, these labels can be used
19143 as part of a computed goto or switch statement. eg gcc
19144 can generate code that looks like this:
19146 ldr r2, [pc, .Laaa]
19156 The first instruction loads the address of the jump table.
19157 The second instruction converts a table index into a byte offset.
19158 The third instruction gets the jump address out of the table.
19159 The fourth instruction performs the jump.
19161 If the address stored at .Laaa is that of a symbol which has the
19162 Thumb_Func bit set, then the linker will arrange for this address
19163 to have the bottom bit set, which in turn would mean that the
19164 address computation performed by the third instruction would end
19165 up with the bottom bit set. Since the ARM is capable of unaligned
19166 word loads, the instruction would then load the incorrect address
19167 out of the jump table, and chaos would ensue. */
19168 if (label_is_thumb_function_name
19169 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19170 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19172 /* When the address of a Thumb function is taken the bottom
19173 bit of that address should be set. This will allow
19174 interworking between Arm and Thumb functions to work
19177 THUMB_SET_FUNC (sym
, 1);
19179 label_is_thumb_function_name
= FALSE
;
19182 dwarf2_emit_label (sym
);
19186 arm_data_in_code (void)
19188 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19190 *input_line_pointer
= '/';
19191 input_line_pointer
+= 5;
19192 *input_line_pointer
= 0;
19200 arm_canonicalize_symbol_name (char * name
)
19204 if (thumb_mode
&& (len
= strlen (name
)) > 5
19205 && streq (name
+ len
- 5, "/data"))
19206 *(name
+ len
- 5) = 0;
19211 /* Table of all register names defined by default. The user can
19212 define additional names with .req. Note that all register names
19213 should appear in both upper and lowercase variants. Some registers
19214 also have mixed-case names. */
19216 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19217 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19218 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19219 #define REGSET(p,t) \
19220 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19221 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19222 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19223 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19224 #define REGSETH(p,t) \
19225 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19226 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19227 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19228 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19229 #define REGSET2(p,t) \
19230 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19231 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19232 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19233 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19234 #define SPLRBANK(base,bank,t) \
19235 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19236 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19237 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19238 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19239 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19240 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19242 static const struct reg_entry reg_names
[] =
19244 /* ARM integer registers. */
19245 REGSET(r
, RN
), REGSET(R
, RN
),
19247 /* ATPCS synonyms. */
19248 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19249 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19250 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19252 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19253 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19254 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19256 /* Well-known aliases. */
19257 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19258 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19260 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19261 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19263 /* Coprocessor numbers. */
19264 REGSET(p
, CP
), REGSET(P
, CP
),
19266 /* Coprocessor register numbers. The "cr" variants are for backward
19268 REGSET(c
, CN
), REGSET(C
, CN
),
19269 REGSET(cr
, CN
), REGSET(CR
, CN
),
19271 /* ARM banked registers. */
19272 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19273 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19274 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19275 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19276 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19277 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19278 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19280 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19281 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19282 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19283 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19284 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19285 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19286 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19287 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19289 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19290 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19291 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19292 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19293 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19294 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19295 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19296 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19297 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19299 /* FPA registers. */
19300 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19301 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19303 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19304 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19306 /* VFP SP registers. */
19307 REGSET(s
,VFS
), REGSET(S
,VFS
),
19308 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19310 /* VFP DP Registers. */
19311 REGSET(d
,VFD
), REGSET(D
,VFD
),
19312 /* Extra Neon DP registers. */
19313 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19315 /* Neon QP registers. */
19316 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19318 /* VFP control registers. */
19319 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19320 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19321 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19322 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19323 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19324 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19325 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19327 /* Maverick DSP coprocessor registers. */
19328 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19329 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19331 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19332 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19333 REGDEF(dspsc
,0,DSPSC
),
19335 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19336 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19337 REGDEF(DSPSC
,0,DSPSC
),
19339 /* iWMMXt data registers - p0, c0-15. */
19340 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19342 /* iWMMXt control registers - p1, c0-3. */
19343 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19344 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19345 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19346 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19348 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19349 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19350 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19351 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19352 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19354 /* XScale accumulator registers. */
19355 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19361 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19362 within psr_required_here. */
19363 static const struct asm_psr psrs
[] =
19365 /* Backward compatibility notation. Note that "all" is no longer
19366 truly all possible PSR bits. */
19367 {"all", PSR_c
| PSR_f
},
19371 /* Individual flags. */
19377 /* Combinations of flags. */
19378 {"fs", PSR_f
| PSR_s
},
19379 {"fx", PSR_f
| PSR_x
},
19380 {"fc", PSR_f
| PSR_c
},
19381 {"sf", PSR_s
| PSR_f
},
19382 {"sx", PSR_s
| PSR_x
},
19383 {"sc", PSR_s
| PSR_c
},
19384 {"xf", PSR_x
| PSR_f
},
19385 {"xs", PSR_x
| PSR_s
},
19386 {"xc", PSR_x
| PSR_c
},
19387 {"cf", PSR_c
| PSR_f
},
19388 {"cs", PSR_c
| PSR_s
},
19389 {"cx", PSR_c
| PSR_x
},
19390 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19391 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19392 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19393 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19394 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19395 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19396 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19397 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19398 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19399 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19400 {"scf", PSR_s
| PSR_c
| PSR_f
},
19401 {"scx", PSR_s
| PSR_c
| PSR_x
},
19402 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19403 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19404 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19405 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19406 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19407 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19408 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19409 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19410 {"csf", PSR_c
| PSR_s
| PSR_f
},
19411 {"csx", PSR_c
| PSR_s
| PSR_x
},
19412 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19413 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19414 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19415 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19416 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19417 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19418 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19419 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19420 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19421 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19422 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19423 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19424 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19425 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19426 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19427 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19428 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19429 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19430 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19431 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19432 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19433 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19434 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19435 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19436 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19437 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19440 /* Table of V7M psr names. */
19441 static const struct asm_psr v7m_psrs
[] =
19443 {"apsr", 0x0 }, {"APSR", 0x0 },
19444 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19445 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19446 {"psr", 0x3 }, {"PSR", 0x3 },
19447 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19448 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19449 {"epsr", 0x6 }, {"EPSR", 0x6 },
19450 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19451 {"msp", 0x8 }, {"MSP", 0x8 },
19452 {"psp", 0x9 }, {"PSP", 0x9 },
19453 {"msplim", 0xa }, {"MSPLIM", 0xa },
19454 {"psplim", 0xb }, {"PSPLIM", 0xb },
19455 {"primask", 0x10}, {"PRIMASK", 0x10},
19456 {"basepri", 0x11}, {"BASEPRI", 0x11},
19457 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19458 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19459 {"control", 0x14}, {"CONTROL", 0x14},
19460 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19461 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19462 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19463 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19464 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19465 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19466 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19467 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19468 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19471 /* Table of all shift-in-operand names. */
19472 static const struct asm_shift_name shift_names
[] =
19474 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19475 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19476 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19477 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19478 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19479 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19482 /* Table of all explicit relocation names. */
19484 static struct reloc_entry reloc_names
[] =
19486 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19487 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19488 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19489 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19490 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19491 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19492 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19493 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19494 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19495 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19496 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19497 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19498 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19499 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19500 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19501 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19502 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19503 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19504 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19505 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19506 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19507 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19508 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19509 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19510 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19511 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19512 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19516 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19517 static const struct asm_cond conds
[] =
19521 {"cs", 0x2}, {"hs", 0x2},
19522 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19536 #define UL_BARRIER(L,U,CODE,FEAT) \
19537 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19538 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19540 static struct asm_barrier_opt barrier_opt_names
[] =
19542 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19543 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19544 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19545 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19546 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19547 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19548 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19549 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19550 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19551 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19552 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19553 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19554 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19555 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19556 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19557 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19562 /* Table of ARM-format instructions. */
19564 /* Macros for gluing together operand strings. N.B. In all cases
19565 other than OPS0, the trailing OP_stop comes from default
19566 zero-initialization of the unspecified elements of the array. */
19567 #define OPS0() { OP_stop, }
19568 #define OPS1(a) { OP_##a, }
19569 #define OPS2(a,b) { OP_##a,OP_##b, }
19570 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19571 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19572 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19573 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19575 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19576 This is useful when mixing operands for ARM and THUMB, i.e. using the
19577 MIX_ARM_THUMB_OPERANDS macro.
19578 In order to use these macros, prefix the number of operands with _
19580 #define OPS_1(a) { a, }
19581 #define OPS_2(a,b) { a,b, }
19582 #define OPS_3(a,b,c) { a,b,c, }
19583 #define OPS_4(a,b,c,d) { a,b,c,d, }
19584 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19585 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19587 /* These macros abstract out the exact format of the mnemonic table and
19588 save some repeated characters. */
19590 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19591 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19592 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19593 THUMB_VARIANT, do_##ae, do_##te }
19595 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19596 a T_MNEM_xyz enumerator. */
19597 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19598 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19599 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19600 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19602 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19603 infix after the third character. */
19604 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19605 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19606 THUMB_VARIANT, do_##ae, do_##te }
19607 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19608 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19609 THUMB_VARIANT, do_##ae, do_##te }
19610 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19611 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19612 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19613 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19614 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19615 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19616 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19617 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19619 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19620 field is still 0xE. Many of the Thumb variants can be executed
19621 conditionally, so this is checked separately. */
19622 #define TUE(mnem, op, top, nops, ops, ae, te) \
19623 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19624 THUMB_VARIANT, do_##ae, do_##te }
19626 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19627 Used by mnemonics that have very minimal differences in the encoding for
19628 ARM and Thumb variants and can be handled in a common function. */
19629 #define TUEc(mnem, op, top, nops, ops, en) \
19630 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19631 THUMB_VARIANT, do_##en, do_##en }
19633 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19634 condition code field. */
19635 #define TUF(mnem, op, top, nops, ops, ae, te) \
19636 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19637 THUMB_VARIANT, do_##ae, do_##te }
19639 /* ARM-only variants of all the above. */
19640 #define CE(mnem, op, nops, ops, ae) \
19641 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19643 #define C3(mnem, op, nops, ops, ae) \
19644 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19646 /* Thumb-only variants of TCE and TUE. */
19647 #define ToC(mnem, top, nops, ops, te) \
19648 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19651 #define ToU(mnem, top, nops, ops, te) \
19652 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19655 /* T_MNEM_xyz enumerator variants of ToC. */
19656 #define toC(mnem, top, nops, ops, te) \
19657 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
19660 /* T_MNEM_xyz enumerator variants of ToU. */
19661 #define toU(mnem, top, nops, ops, te) \
19662 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
19665 /* Legacy mnemonics that always have conditional infix after the third
19667 #define CL(mnem, op, nops, ops, ae) \
19668 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19669 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19671 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19672 #define cCE(mnem, op, nops, ops, ae) \
19673 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19675 /* Legacy coprocessor instructions where conditional infix and conditional
19676 suffix are ambiguous. For consistency this includes all FPA instructions,
19677 not just the potentially ambiguous ones. */
19678 #define cCL(mnem, op, nops, ops, ae) \
19679 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19680 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19682 /* Coprocessor, takes either a suffix or a position-3 infix
19683 (for an FPA corner case). */
19684 #define C3E(mnem, op, nops, ops, ae) \
19685 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19686 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19688 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19689 { m1 #m2 m3, OPS##nops ops, \
19690 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19691 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19693 #define CM(m1, m2, op, nops, ops, ae) \
19694 xCM_ (m1, , m2, op, nops, ops, ae), \
19695 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19696 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19697 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19698 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19699 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19700 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19701 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19702 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19703 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19704 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19705 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19706 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19707 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19708 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19709 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19710 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19711 xCM_ (m1, le, m2, op, nops, ops, ae), \
19712 xCM_ (m1, al, m2, op, nops, ops, ae)
19714 #define UE(mnem, op, nops, ops, ae) \
19715 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19717 #define UF(mnem, op, nops, ops, ae) \
19718 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19720 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19721 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19722 use the same encoding function for each. */
19723 #define NUF(mnem, op, nops, ops, enc) \
19724 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19725 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19727 /* Neon data processing, version which indirects through neon_enc_tab for
19728 the various overloaded versions of opcodes. */
19729 #define nUF(mnem, op, nops, ops, enc) \
19730 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19731 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19733 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19735 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19736 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19737 THUMB_VARIANT, do_##enc, do_##enc }
19739 #define NCE(mnem, op, nops, ops, enc) \
19740 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19742 #define NCEF(mnem, op, nops, ops, enc) \
19743 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19745 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19746 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19747 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19748 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19750 #define nCE(mnem, op, nops, ops, enc) \
19751 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19753 #define nCEF(mnem, op, nops, ops, enc) \
19754 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19758 static const struct asm_opcode insns
[] =
19760 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19761 #define THUMB_VARIANT & arm_ext_v4t
19762 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19763 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19764 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19765 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19766 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19767 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19768 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19769 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19770 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19771 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19772 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19773 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19774 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19775 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19776 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19777 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19779 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19780 for setting PSR flag bits. They are obsolete in V6 and do not
19781 have Thumb equivalents. */
19782 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19783 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19784 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19785 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19786 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19787 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19788 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19789 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19790 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19792 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19793 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19794 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19795 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19797 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19798 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19799 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19801 OP_ADDRGLDR
),ldst
, t_ldst
),
19802 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19804 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19805 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19806 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19807 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19808 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19809 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19811 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19812 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19815 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19816 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19817 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19818 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19820 /* Thumb-compatibility pseudo ops. */
19821 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19822 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19823 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19824 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19825 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19826 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19827 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19828 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19829 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19830 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19831 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19832 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19834 /* These may simplify to neg. */
19835 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19836 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19838 #undef THUMB_VARIANT
19839 #define THUMB_VARIANT & arm_ext_os
19841 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19842 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19844 #undef THUMB_VARIANT
19845 #define THUMB_VARIANT & arm_ext_v6
19847 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19849 /* V1 instructions with no Thumb analogue prior to V6T2. */
19850 #undef THUMB_VARIANT
19851 #define THUMB_VARIANT & arm_ext_v6t2
19853 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19854 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19855 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19857 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19858 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19859 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19860 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19862 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19863 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19865 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19866 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19868 /* V1 instructions with no Thumb analogue at all. */
19869 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19870 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19872 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19873 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19874 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19875 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19876 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19877 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19878 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19879 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19882 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19883 #undef THUMB_VARIANT
19884 #define THUMB_VARIANT & arm_ext_v4t
19886 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19887 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19889 #undef THUMB_VARIANT
19890 #define THUMB_VARIANT & arm_ext_v6t2
19892 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19893 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19895 /* Generic coprocessor instructions. */
19896 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19897 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19898 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19899 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19900 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19901 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19902 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19905 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19907 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19908 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19911 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19912 #undef THUMB_VARIANT
19913 #define THUMB_VARIANT & arm_ext_msr
19915 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19916 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19919 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19920 #undef THUMB_VARIANT
19921 #define THUMB_VARIANT & arm_ext_v6t2
19923 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19924 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19925 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19926 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19927 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19928 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19929 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19930 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19933 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19934 #undef THUMB_VARIANT
19935 #define THUMB_VARIANT & arm_ext_v4t
19937 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19938 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19939 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19940 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19941 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19942 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19945 #define ARM_VARIANT & arm_ext_v4t_5
19947 /* ARM Architecture 4T. */
19948 /* Note: bx (and blx) are required on V5, even if the processor does
19949 not support Thumb. */
19950 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19953 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19954 #undef THUMB_VARIANT
19955 #define THUMB_VARIANT & arm_ext_v5t
19957 /* Note: blx has 2 variants; the .value coded here is for
19958 BLX(2). Only this variant has conditional execution. */
19959 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19960 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19962 #undef THUMB_VARIANT
19963 #define THUMB_VARIANT & arm_ext_v6t2
19965 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19966 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19967 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19968 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19969 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19970 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19971 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19972 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19975 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19976 #undef THUMB_VARIANT
19977 #define THUMB_VARIANT & arm_ext_v5exp
19979 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19980 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19981 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19982 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19984 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19985 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19987 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19988 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19989 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19990 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19992 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19993 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19994 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19995 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19997 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19998 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20000 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20001 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20002 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20003 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20006 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
20007 #undef THUMB_VARIANT
20008 #define THUMB_VARIANT & arm_ext_v6t2
20010 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
20011 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
20013 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
20014 ADDRGLDRS
), ldrd
, t_ldstd
),
20016 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20017 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20020 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
20022 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
20025 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
20026 #undef THUMB_VARIANT
20027 #define THUMB_VARIANT & arm_ext_v6
20029 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20030 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20031 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20032 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20033 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20034 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20035 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20036 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20037 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20038 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
20040 #undef THUMB_VARIANT
20041 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20043 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
20044 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20046 #undef THUMB_VARIANT
20047 #define THUMB_VARIANT & arm_ext_v6t2
20049 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20050 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20052 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
20053 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
20055 /* ARM V6 not included in V7M. */
20056 #undef THUMB_VARIANT
20057 #define THUMB_VARIANT & arm_ext_v6_notm
20058 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20059 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20060 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
20061 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
20062 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20063 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20064 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
20065 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20066 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
20067 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20068 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20069 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20070 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20071 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20072 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
20073 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
20074 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20075 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20076 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
20078 /* ARM V6 not included in V7M (eg. integer SIMD). */
20079 #undef THUMB_VARIANT
20080 #define THUMB_VARIANT & arm_ext_v6_dsp
20081 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
20082 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
20083 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20084 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20085 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20086 /* Old name for QASX. */
20087 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20088 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20089 /* Old name for QSAX. */
20090 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20091 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20092 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20093 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20094 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20095 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20096 /* Old name for SASX. */
20097 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20098 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20099 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20100 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20101 /* Old name for SHASX. */
20102 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20103 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20104 /* Old name for SHSAX. */
20105 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20106 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20107 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20108 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20109 /* Old name for SSAX. */
20110 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20111 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20112 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20113 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20114 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20115 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20116 /* Old name for UASX. */
20117 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20118 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20119 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20120 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20121 /* Old name for UHASX. */
20122 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20123 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20124 /* Old name for UHSAX. */
20125 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20126 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20127 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20128 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20129 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20130 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20131 /* Old name for UQASX. */
20132 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20133 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20134 /* Old name for UQSAX. */
20135 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20136 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20137 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20138 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20139 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20140 /* Old name for USAX. */
20141 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20142 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20143 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20144 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20145 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20146 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20147 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20148 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20149 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20150 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20151 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20152 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20153 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20154 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20155 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20156 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20157 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20158 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20159 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20160 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20161 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20162 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20163 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20164 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20165 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20166 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20167 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20168 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20169 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20170 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
20171 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
20172 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20173 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20174 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20177 #define ARM_VARIANT & arm_ext_v6k_v6t2
20178 #undef THUMB_VARIANT
20179 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20181 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20182 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20183 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20184 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20186 #undef THUMB_VARIANT
20187 #define THUMB_VARIANT & arm_ext_v6_notm
20188 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20190 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20191 RRnpcb
), strexd
, t_strexd
),
20193 #undef THUMB_VARIANT
20194 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20195 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20197 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20199 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20201 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20203 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20206 #define ARM_VARIANT & arm_ext_sec
20207 #undef THUMB_VARIANT
20208 #define THUMB_VARIANT & arm_ext_sec
20210 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20213 #define ARM_VARIANT & arm_ext_virt
20214 #undef THUMB_VARIANT
20215 #define THUMB_VARIANT & arm_ext_virt
20217 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20218 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20221 #define ARM_VARIANT & arm_ext_pan
20222 #undef THUMB_VARIANT
20223 #define THUMB_VARIANT & arm_ext_pan
20225 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20228 #define ARM_VARIANT & arm_ext_v6t2
20229 #undef THUMB_VARIANT
20230 #define THUMB_VARIANT & arm_ext_v6t2
20232 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20233 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20234 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20235 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20237 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20238 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20240 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20241 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20242 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20243 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20246 #define ARM_VARIANT & arm_ext_v3
20247 #undef THUMB_VARIANT
20248 #define THUMB_VARIANT & arm_ext_v6t2
20250 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20251 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20252 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20255 #define ARM_VARIANT & arm_ext_v6t2
20256 #undef THUMB_VARIANT
20257 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20258 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20259 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20261 /* Thumb-only instructions. */
20263 #define ARM_VARIANT NULL
20264 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20265 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20267 /* ARM does not really have an IT instruction, so always allow it.
20268 The opcode is copied from Thumb in order to allow warnings in
20269 -mimplicit-it=[never | arm] modes. */
20271 #define ARM_VARIANT & arm_ext_v1
20272 #undef THUMB_VARIANT
20273 #define THUMB_VARIANT & arm_ext_v6t2
20275 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20276 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20277 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20278 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20279 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20280 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20281 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20282 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20283 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20284 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20285 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20286 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20287 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20288 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20289 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20290 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20291 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20292 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20294 /* Thumb2 only instructions. */
20296 #define ARM_VARIANT NULL
20298 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20299 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20300 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20301 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20302 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20303 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20305 /* Hardware division instructions. */
20307 #define ARM_VARIANT & arm_ext_adiv
20308 #undef THUMB_VARIANT
20309 #define THUMB_VARIANT & arm_ext_div
20311 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20312 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20314 /* ARM V6M/V7 instructions. */
20316 #define ARM_VARIANT & arm_ext_barrier
20317 #undef THUMB_VARIANT
20318 #define THUMB_VARIANT & arm_ext_barrier
20320 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20321 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20322 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20324 /* ARM V7 instructions. */
20326 #define ARM_VARIANT & arm_ext_v7
20327 #undef THUMB_VARIANT
20328 #define THUMB_VARIANT & arm_ext_v7
20330 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20331 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20334 #define ARM_VARIANT & arm_ext_mp
20335 #undef THUMB_VARIANT
20336 #define THUMB_VARIANT & arm_ext_mp
20338 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20340 /* AArchv8 instructions. */
20342 #define ARM_VARIANT & arm_ext_v8
20344 /* Instructions shared between armv8-a and armv8-m. */
20345 #undef THUMB_VARIANT
20346 #define THUMB_VARIANT & arm_ext_atomics
20348 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20349 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20350 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20351 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20352 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20353 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20354 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20355 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20356 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20357 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20359 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20361 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20363 #undef THUMB_VARIANT
20364 #define THUMB_VARIANT & arm_ext_v8
20366 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20367 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20369 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20372 /* Defined in V8 but is in undefined encoding space for earlier
20373 architectures. However earlier architectures are required to treat
20374 this instuction as a semihosting trap as well. Hence while not explicitly
20375 defined as such, it is in fact correct to define the instruction for all
20377 #undef THUMB_VARIANT
20378 #define THUMB_VARIANT & arm_ext_v1
20380 #define ARM_VARIANT & arm_ext_v1
20381 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20383 /* ARMv8 T32 only. */
20385 #define ARM_VARIANT NULL
20386 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20387 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20388 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20390 /* FP for ARMv8. */
20392 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20393 #undef THUMB_VARIANT
20394 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20396 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20397 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20398 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20399 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20400 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20401 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20402 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20403 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20404 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20405 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20406 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20407 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20408 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20409 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20410 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20411 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20412 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20414 /* Crypto v1 extensions. */
20416 #define ARM_VARIANT & fpu_crypto_ext_armv8
20417 #undef THUMB_VARIANT
20418 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20420 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20421 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20422 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20423 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20424 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20425 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20426 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20427 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20428 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20429 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20430 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20431 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20432 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20433 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20436 #define ARM_VARIANT & crc_ext_armv8
20437 #undef THUMB_VARIANT
20438 #define THUMB_VARIANT & crc_ext_armv8
20439 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20440 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20441 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20442 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20443 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20444 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20446 /* ARMv8.2 RAS extension. */
20448 #define ARM_VARIANT & arm_ext_ras
20449 #undef THUMB_VARIANT
20450 #define THUMB_VARIANT & arm_ext_ras
20451 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20454 #define ARM_VARIANT & arm_ext_v8_3
20455 #undef THUMB_VARIANT
20456 #define THUMB_VARIANT & arm_ext_v8_3
20457 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20458 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20459 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20462 #define ARM_VARIANT & fpu_neon_ext_dotprod
20463 #undef THUMB_VARIANT
20464 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20465 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20466 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20469 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20470 #undef THUMB_VARIANT
20471 #define THUMB_VARIANT NULL
20473 cCE("wfs", e200110
, 1, (RR
), rd
),
20474 cCE("rfs", e300110
, 1, (RR
), rd
),
20475 cCE("wfc", e400110
, 1, (RR
), rd
),
20476 cCE("rfc", e500110
, 1, (RR
), rd
),
20478 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20479 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20480 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20481 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20483 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20484 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20485 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20486 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20488 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20489 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20490 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20491 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20492 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20493 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20494 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20495 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20496 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20497 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20498 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20499 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20501 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20502 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20503 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20504 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20505 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20506 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20507 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20508 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20509 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20510 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20511 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20512 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20514 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20515 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20516 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20517 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20518 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20519 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20520 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20521 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20522 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20523 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20524 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20525 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20527 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20528 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20529 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20530 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20531 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20532 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20533 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20534 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20535 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20536 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20537 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20538 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20540 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20541 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20542 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20543 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20544 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20545 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20546 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20547 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20548 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20549 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20550 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20551 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20553 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20554 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20555 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20556 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20557 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20558 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20559 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20560 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20561 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20562 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20563 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20564 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20566 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20567 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20568 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20569 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20570 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20571 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20572 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20573 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20574 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20575 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20576 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20577 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20579 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20580 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20581 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20582 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20583 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20584 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20585 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20586 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20587 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20588 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20589 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20590 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20592 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20593 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20594 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20595 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20596 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20597 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20598 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20599 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20600 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20601 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20602 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20603 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20605 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20606 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20607 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20608 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20609 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20610 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20611 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20612 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20613 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20614 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20615 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20616 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20618 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20619 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20620 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20621 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20622 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20623 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20624 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20625 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20626 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20627 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20628 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20629 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20631 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20632 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20633 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20634 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20635 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20636 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20637 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20638 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20639 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20640 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20641 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20642 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20644 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20645 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20646 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20647 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20648 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20649 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20650 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20651 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20652 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20653 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20654 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20655 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20657 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20658 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20659 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20660 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20661 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20662 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20663 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20664 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20665 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20666 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20667 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20668 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20670 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20671 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20672 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20673 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20674 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20675 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20676 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20677 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20678 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20679 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20680 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20681 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20683 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20684 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20685 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20686 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20687 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20688 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20689 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20690 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20691 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20692 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20693 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20694 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20696 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20697 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20698 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20699 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20700 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20701 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20702 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20703 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20704 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20705 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20706 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20707 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20709 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20710 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20711 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20712 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20713 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20714 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20715 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20716 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20717 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20718 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20719 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20720 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20722 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20723 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20724 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20725 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20726 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20727 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20728 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20729 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20730 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20731 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20732 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20733 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20735 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20736 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20737 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20738 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20739 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20740 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20741 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20742 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20743 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20744 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20745 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20746 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20748 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20749 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20750 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20751 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20752 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20753 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20754 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20755 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20756 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20757 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20758 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20759 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20761 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20762 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20763 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20764 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20765 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20766 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20767 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20768 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20769 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20770 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20771 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20772 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20774 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20775 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20776 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20777 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20778 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20779 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20780 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20781 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20782 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20783 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20784 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20785 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20787 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20788 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20789 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20790 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20791 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20792 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20793 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20794 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20795 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20796 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20797 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20798 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20800 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20801 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20802 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20803 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20804 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20805 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20806 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20807 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20808 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20809 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20810 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20811 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20813 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20814 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20815 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20816 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20817 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20818 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20819 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20820 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20821 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20822 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20823 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20824 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20826 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20827 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20828 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20829 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20830 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20831 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20832 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20833 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20834 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20835 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20836 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20837 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20839 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20840 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20841 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20842 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20843 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20844 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20845 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20846 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20847 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20848 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20849 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20850 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20852 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20853 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20854 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20855 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20856 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20857 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20858 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20859 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20860 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20861 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20862 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20863 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20865 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20866 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20867 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20868 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20870 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20871 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20872 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20873 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20874 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20875 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20876 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20877 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20878 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20879 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20880 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20881 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20883 /* The implementation of the FIX instruction is broken on some
20884 assemblers, in that it accepts a precision specifier as well as a
20885 rounding specifier, despite the fact that this is meaningless.
20886 To be more compatible, we accept it as well, though of course it
20887 does not set any bits. */
20888 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20889 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20890 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20891 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20892 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20893 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20894 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20895 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20896 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20897 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20898 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20899 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20900 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20902 /* Instructions that were new with the real FPA, call them V2. */
20904 #define ARM_VARIANT & fpu_fpa_ext_v2
20906 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20907 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20908 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20909 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20910 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20911 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20914 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20916 /* Moves and type conversions. */
20917 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20918 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20919 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20920 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20921 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20922 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20923 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20924 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20925 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20926 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20927 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20928 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20929 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20930 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20932 /* Memory operations. */
20933 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20934 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20935 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20936 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20937 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20938 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20939 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20940 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20941 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20942 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20943 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20944 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20945 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20946 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20947 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20948 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20949 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20950 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20952 /* Monadic operations. */
20953 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20954 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20955 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20957 /* Dyadic operations. */
20958 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20959 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20960 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20961 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20962 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20963 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20964 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20965 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20966 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20969 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20970 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20971 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20972 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20974 /* Double precision load/store are still present on single precision
20975 implementations. */
20976 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20977 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20978 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20979 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20980 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20981 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20982 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20983 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20984 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20985 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20988 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20990 /* Moves and type conversions. */
20991 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20992 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20993 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20994 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20995 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20996 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20997 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20998 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20999 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21000 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21001 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21002 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21003 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21005 /* Monadic operations. */
21006 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21007 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21008 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21010 /* Dyadic operations. */
21011 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21012 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21013 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21014 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21015 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21016 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21017 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21018 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21019 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21022 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21023 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
21024 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21025 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
21028 #define ARM_VARIANT & fpu_vfp_ext_v2
21030 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
21031 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
21032 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
21033 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
21035 /* Instructions which may belong to either the Neon or VFP instruction sets.
21036 Individual encoder functions perform additional architecture checks. */
21038 #define ARM_VARIANT & fpu_vfp_ext_v1xd
21039 #undef THUMB_VARIANT
21040 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
21042 /* These mnemonics are unique to VFP. */
21043 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
21044 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
21045 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21046 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21047 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21048 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21049 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21050 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
21051 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
21052 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
21054 /* Mnemonics shared by Neon and VFP. */
21055 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
21056 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21057 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21059 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21060 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21062 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21063 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21065 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21066 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21067 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21068 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21069 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21070 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21071 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21072 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21074 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
21075 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
21076 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
21077 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
21080 /* NOTE: All VMOV encoding is special-cased! */
21081 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
21082 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
21085 #define ARM_VARIANT & arm_ext_fp16
21086 #undef THUMB_VARIANT
21087 #define THUMB_VARIANT & arm_ext_fp16
21088 /* New instructions added from v8.2, allowing the extraction and insertion of
21089 the upper 16 bits of a 32-bit vector register. */
21090 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
21091 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
21093 /* New backported fma/fms instructions optional in v8.2. */
21094 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
21095 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
21097 #undef THUMB_VARIANT
21098 #define THUMB_VARIANT & fpu_neon_ext_v1
21100 #define ARM_VARIANT & fpu_neon_ext_v1
21102 /* Data processing with three registers of the same length. */
21103 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
21104 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
21105 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
21106 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21107 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21108 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21109 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21110 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21111 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21112 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
21113 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21114 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21115 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21116 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21117 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21118 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21119 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21120 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21121 /* If not immediate, fall back to neon_dyadic_i64_su.
21122 shl_imm should accept I8 I16 I32 I64,
21123 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21124 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
21125 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
21126 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
21127 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
21128 /* Logic ops, types optional & ignored. */
21129 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21130 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21131 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21132 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21133 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21134 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21135 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21136 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21137 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
21138 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
21139 /* Bitfield ops, untyped. */
21140 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21141 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21142 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21143 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21144 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21145 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21146 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21147 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21148 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21149 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21150 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21151 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21152 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21153 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
21154 back to neon_dyadic_if_su. */
21155 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21156 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21157 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21158 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21159 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21160 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21161 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21162 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21163 /* Comparison. Type I8 I16 I32 F32. */
21164 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
21165 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
21166 /* As above, D registers only. */
21167 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21168 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21169 /* Int and float variants, signedness unimportant. */
21170 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21171 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21172 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
21173 /* Add/sub take types I8 I16 I32 I64 F32. */
21174 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21175 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21176 /* vtst takes sizes 8, 16, 32. */
21177 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21178 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21179 /* VMUL takes I8 I16 I32 F32 P8. */
21180 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21181 /* VQD{R}MULH takes S16 S32. */
21182 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21183 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21184 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21185 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21186 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21187 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21188 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21189 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21190 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21191 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21192 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21193 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21194 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21195 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21196 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21197 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21198 /* ARM v8.1 extension. */
21199 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21200 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21201 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21202 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21204 /* Two address, int/float. Types S8 S16 S32 F32. */
21205 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21206 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21208 /* Data processing with two registers and a shift amount. */
21209 /* Right shifts, and variants with rounding.
21210 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21211 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21212 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21213 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21214 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21215 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21216 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21217 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21218 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21219 /* Shift and insert. Sizes accepted 8 16 32 64. */
21220 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21221 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21222 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21223 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21224 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21225 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21226 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21227 /* Right shift immediate, saturating & narrowing, with rounding variants.
21228 Types accepted S16 S32 S64 U16 U32 U64. */
21229 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21230 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21231 /* As above, unsigned. Types accepted S16 S32 S64. */
21232 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21233 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21234 /* Right shift narrowing. Types accepted I16 I32 I64. */
21235 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21236 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21237 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21238 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21239 /* CVT with optional immediate for fixed-point variant. */
21240 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21242 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21243 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21245 /* Data processing, three registers of different lengths. */
21246 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21247 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21248 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21249 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21250 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21251 /* If not scalar, fall back to neon_dyadic_long.
21252 Vector types as above, scalar types S16 S32 U16 U32. */
21253 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21254 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21255 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21256 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21257 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21258 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21259 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21260 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21261 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21262 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21263 /* Saturating doubling multiplies. Types S16 S32. */
21264 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21265 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21266 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21267 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21268 S16 S32 U16 U32. */
21269 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21271 /* Extract. Size 8. */
21272 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21273 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21275 /* Two registers, miscellaneous. */
21276 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21277 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21278 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21279 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21280 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21281 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21282 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21283 /* Vector replicate. Sizes 8 16 32. */
21284 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21285 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21286 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21287 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21288 /* VMOVN. Types I16 I32 I64. */
21289 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21290 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21291 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21292 /* VQMOVUN. Types S16 S32 S64. */
21293 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21294 /* VZIP / VUZP. Sizes 8 16 32. */
21295 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21296 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21297 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21298 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21299 /* VQABS / VQNEG. Types S8 S16 S32. */
21300 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21301 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21302 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21303 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21304 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21305 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21306 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21307 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21308 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21309 /* Reciprocal estimates. Types U32 F16 F32. */
21310 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21311 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21312 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21313 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21314 /* VCLS. Types S8 S16 S32. */
21315 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21316 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21317 /* VCLZ. Types I8 I16 I32. */
21318 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21319 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21320 /* VCNT. Size 8. */
21321 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21322 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21323 /* Two address, untyped. */
21324 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21325 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21326 /* VTRN. Sizes 8 16 32. */
21327 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21328 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21330 /* Table lookup. Size 8. */
21331 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21332 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21334 #undef THUMB_VARIANT
21335 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21337 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21339 /* Neon element/structure load/store. */
21340 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21341 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21342 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21343 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21344 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21345 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21346 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21347 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21349 #undef THUMB_VARIANT
21350 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21352 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21353 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21354 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21355 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21356 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21357 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21358 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21359 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21360 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21361 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21363 #undef THUMB_VARIANT
21364 #define THUMB_VARIANT & fpu_vfp_ext_v3
21366 #define ARM_VARIANT & fpu_vfp_ext_v3
21368 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21369 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21370 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21371 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21372 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21373 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21374 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21375 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21376 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21379 #define ARM_VARIANT & fpu_vfp_ext_fma
21380 #undef THUMB_VARIANT
21381 #define THUMB_VARIANT & fpu_vfp_ext_fma
21382 /* Mnemonics shared by Neon and VFP. These are included in the
21383 VFP FMA variant; NEON and VFP FMA always includes the NEON
21384 FMA instructions. */
21385 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21386 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21387 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21388 the v form should always be used. */
21389 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21390 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21391 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21392 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21393 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21394 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21396 #undef THUMB_VARIANT
21398 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21400 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21401 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21402 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21403 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21404 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21405 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21406 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21407 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21410 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21412 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21413 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21414 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21415 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21416 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21417 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21418 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21419 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21420 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21421 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21422 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21423 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21424 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21425 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21426 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21427 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21428 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21429 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21430 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21431 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21432 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21433 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21434 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21435 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21436 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21437 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21438 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21439 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21440 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21441 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21442 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21443 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21444 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21445 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21446 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21447 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21448 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21449 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21450 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21451 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21452 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21453 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21454 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21455 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21456 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21457 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21458 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21459 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21460 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21461 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21462 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21463 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21464 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21465 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21466 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21467 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21468 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21469 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21470 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21471 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21472 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21473 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21474 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21475 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21476 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21477 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21478 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21479 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21480 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21481 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21482 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21483 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21484 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21485 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21486 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21487 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21488 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21489 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21490 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21491 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21492 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21493 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21494 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21495 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21496 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21497 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21498 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21499 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21500 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21501 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21502 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21503 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21504 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21505 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21506 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21507 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21508 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21509 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21510 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21511 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21512 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21513 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21514 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21515 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21516 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21517 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21518 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21519 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21520 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21521 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21522 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21523 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21524 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21525 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21526 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21527 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21528 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21529 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21530 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21531 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21532 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21533 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21534 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21535 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21536 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21537 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21538 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21539 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21540 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21541 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21542 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21543 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21544 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21545 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21546 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21547 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21548 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21549 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21550 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21551 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21552 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21553 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21554 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21555 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21556 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21557 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21558 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21559 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21560 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21561 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21562 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21563 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21564 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21565 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21566 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21567 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21568 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21569 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21570 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21571 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21572 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21573 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21576 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21578 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21579 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21580 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21581 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21582 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21583 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21584 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21585 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21586 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21587 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21588 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21589 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21590 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21591 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21592 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21593 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21594 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21595 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21596 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21597 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21598 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21599 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21600 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21601 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21602 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21603 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21604 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21605 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21606 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21607 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21608 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21609 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21610 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21611 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21612 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21613 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21614 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21615 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21616 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21617 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21618 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21619 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21620 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21621 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21622 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21623 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21624 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21625 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21626 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21627 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21628 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21629 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21630 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21631 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21632 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21633 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21634 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21637 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21639 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21640 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21641 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21642 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21643 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21644 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21645 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21646 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21647 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21648 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21649 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21650 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21651 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21652 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21653 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21654 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21655 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21656 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21657 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21658 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21659 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21660 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21661 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21662 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21663 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21664 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21665 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21666 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21667 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21668 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21669 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21670 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21671 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21672 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21673 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21674 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21675 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21676 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21677 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21678 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21679 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21680 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21681 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21682 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21683 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21684 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21685 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21686 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21687 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21688 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21689 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21690 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21691 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21692 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21693 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21694 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21695 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21696 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21697 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21698 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21699 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21700 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21701 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21702 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21703 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21704 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21705 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21706 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21707 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21708 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21709 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21710 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21711 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21712 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21713 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21714 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21716 /* ARMv8.5-A instructions. */
21718 #define ARM_VARIANT & arm_ext_sb
21719 #undef THUMB_VARIANT
21720 #define THUMB_VARIANT & arm_ext_sb
21721 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21724 #define ARM_VARIANT & arm_ext_predres
21725 #undef THUMB_VARIANT
21726 #define THUMB_VARIANT & arm_ext_predres
21727 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21728 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21729 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21731 /* ARMv8-M instructions. */
21733 #define ARM_VARIANT NULL
21734 #undef THUMB_VARIANT
21735 #define THUMB_VARIANT & arm_ext_v8m
21736 ToU("sg", e97fe97f
, 0, (), noargs
),
21737 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21738 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21739 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21740 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21741 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21742 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21744 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21745 instructions behave as nop if no VFP is present. */
21746 #undef THUMB_VARIANT
21747 #define THUMB_VARIANT & arm_ext_v8m_main
21748 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21749 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21751 /* Armv8.1-M Mainline instructions. */
21752 #undef THUMB_VARIANT
21753 #define THUMB_VARIANT & arm_ext_v8_1m_main
21754 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
21755 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
21756 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21757 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
21758 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21761 #undef THUMB_VARIANT
21793 /* MD interface: bits in the object file. */
21795 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21796 for use in the a.out file, and stores them in the array pointed to by buf.
21797 This knows about the endian-ness of the target machine and does
21798 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21799 2 (short) and 4 (long) Floating numbers are put out as a series of
21800 LITTLENUMS (shorts, here at least). */
21803 md_number_to_chars (char * buf
, valueT val
, int n
)
21805 if (target_big_endian
)
21806 number_to_chars_bigendian (buf
, val
, n
);
21808 number_to_chars_littleendian (buf
, val
, n
);
21812 md_chars_to_number (char * buf
, int n
)
21815 unsigned char * where
= (unsigned char *) buf
;
21817 if (target_big_endian
)
21822 result
|= (*where
++ & 255);
21830 result
|= (where
[n
] & 255);
21837 /* MD interface: Sections. */
21839 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21840 that an rs_machine_dependent frag may reach. */
21843 arm_frag_max_var (fragS
*fragp
)
21845 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21846 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21848 Note that we generate relaxable instructions even for cases that don't
21849 really need it, like an immediate that's a trivial constant. So we're
21850 overestimating the instruction size for some of those cases. Rather
21851 than putting more intelligence here, it would probably be better to
21852 avoid generating a relaxation frag in the first place when it can be
21853 determined up front that a short instruction will suffice. */
21855 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21859 /* Estimate the size of a frag before relaxing. Assume everything fits in
21863 md_estimate_size_before_relax (fragS
* fragp
,
21864 segT segtype ATTRIBUTE_UNUSED
)
21870 /* Convert a machine dependent frag. */
21873 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21875 unsigned long insn
;
21876 unsigned long old_op
;
21884 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21886 old_op
= bfd_get_16(abfd
, buf
);
21887 if (fragp
->fr_symbol
)
21889 exp
.X_op
= O_symbol
;
21890 exp
.X_add_symbol
= fragp
->fr_symbol
;
21894 exp
.X_op
= O_constant
;
21896 exp
.X_add_number
= fragp
->fr_offset
;
21897 opcode
= fragp
->fr_subtype
;
21900 case T_MNEM_ldr_pc
:
21901 case T_MNEM_ldr_pc2
:
21902 case T_MNEM_ldr_sp
:
21903 case T_MNEM_str_sp
:
21910 if (fragp
->fr_var
== 4)
21912 insn
= THUMB_OP32 (opcode
);
21913 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21915 insn
|= (old_op
& 0x700) << 4;
21919 insn
|= (old_op
& 7) << 12;
21920 insn
|= (old_op
& 0x38) << 13;
21922 insn
|= 0x00000c00;
21923 put_thumb32_insn (buf
, insn
);
21924 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21928 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21930 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21933 if (fragp
->fr_var
== 4)
21935 insn
= THUMB_OP32 (opcode
);
21936 insn
|= (old_op
& 0xf0) << 4;
21937 put_thumb32_insn (buf
, insn
);
21938 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21942 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21943 exp
.X_add_number
-= 4;
21951 if (fragp
->fr_var
== 4)
21953 int r0off
= (opcode
== T_MNEM_mov
21954 || opcode
== T_MNEM_movs
) ? 0 : 8;
21955 insn
= THUMB_OP32 (opcode
);
21956 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21957 insn
|= (old_op
& 0x700) << r0off
;
21958 put_thumb32_insn (buf
, insn
);
21959 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21963 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21968 if (fragp
->fr_var
== 4)
21970 insn
= THUMB_OP32(opcode
);
21971 put_thumb32_insn (buf
, insn
);
21972 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21975 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21979 if (fragp
->fr_var
== 4)
21981 insn
= THUMB_OP32(opcode
);
21982 insn
|= (old_op
& 0xf00) << 14;
21983 put_thumb32_insn (buf
, insn
);
21984 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21987 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21990 case T_MNEM_add_sp
:
21991 case T_MNEM_add_pc
:
21992 case T_MNEM_inc_sp
:
21993 case T_MNEM_dec_sp
:
21994 if (fragp
->fr_var
== 4)
21996 /* ??? Choose between add and addw. */
21997 insn
= THUMB_OP32 (opcode
);
21998 insn
|= (old_op
& 0xf0) << 4;
21999 put_thumb32_insn (buf
, insn
);
22000 if (opcode
== T_MNEM_add_pc
)
22001 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
22003 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22006 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22014 if (fragp
->fr_var
== 4)
22016 insn
= THUMB_OP32 (opcode
);
22017 insn
|= (old_op
& 0xf0) << 4;
22018 insn
|= (old_op
& 0xf) << 16;
22019 put_thumb32_insn (buf
, insn
);
22020 if (insn
& (1 << 20))
22021 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22023 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22026 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22032 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
22033 (enum bfd_reloc_code_real
) reloc_type
);
22034 fixp
->fx_file
= fragp
->fr_file
;
22035 fixp
->fx_line
= fragp
->fr_line
;
22036 fragp
->fr_fix
+= fragp
->fr_var
;
22038 /* Set whether we use thumb-2 ISA based on final relaxation results. */
22039 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
22040 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
22041 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
22044 /* Return the size of a relaxable immediate operand instruction.
22045 SHIFT and SIZE specify the form of the allowable immediate. */
22047 relax_immediate (fragS
*fragp
, int size
, int shift
)
22053 /* ??? Should be able to do better than this. */
22054 if (fragp
->fr_symbol
)
22057 low
= (1 << shift
) - 1;
22058 mask
= (1 << (shift
+ size
)) - (1 << shift
);
22059 offset
= fragp
->fr_offset
;
22060 /* Force misaligned offsets to 32-bit variant. */
22063 if (offset
& ~mask
)
22068 /* Get the address of a symbol during relaxation. */
22070 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
22076 sym
= fragp
->fr_symbol
;
22077 sym_frag
= symbol_get_frag (sym
);
22078 know (S_GET_SEGMENT (sym
) != absolute_section
22079 || sym_frag
== &zero_address_frag
);
22080 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
22082 /* If frag has yet to be reached on this pass, assume it will
22083 move by STRETCH just as we did. If this is not so, it will
22084 be because some frag between grows, and that will force
22088 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
22092 /* Adjust stretch for any alignment frag. Note that if have
22093 been expanding the earlier code, the symbol may be
22094 defined in what appears to be an earlier frag. FIXME:
22095 This doesn't handle the fr_subtype field, which specifies
22096 a maximum number of bytes to skip when doing an
22098 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
22100 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
22103 stretch
= - ((- stretch
)
22104 & ~ ((1 << (int) f
->fr_offset
) - 1));
22106 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
22118 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
22121 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
22126 /* Assume worst case for symbols not known to be in the same section. */
22127 if (fragp
->fr_symbol
== NULL
22128 || !S_IS_DEFINED (fragp
->fr_symbol
)
22129 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22130 || S_IS_WEAK (fragp
->fr_symbol
))
22133 val
= relaxed_symbol_addr (fragp
, stretch
);
22134 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
22135 addr
= (addr
+ 4) & ~3;
22136 /* Force misaligned targets to 32-bit variant. */
22140 if (val
< 0 || val
> 1020)
22145 /* Return the size of a relaxable add/sub immediate instruction. */
22147 relax_addsub (fragS
*fragp
, asection
*sec
)
22152 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22153 op
= bfd_get_16(sec
->owner
, buf
);
22154 if ((op
& 0xf) == ((op
>> 4) & 0xf))
22155 return relax_immediate (fragp
, 8, 0);
22157 return relax_immediate (fragp
, 3, 0);
22160 /* Return TRUE iff the definition of symbol S could be pre-empted
22161 (overridden) at link or load time. */
22163 symbol_preemptible (symbolS
*s
)
22165 /* Weak symbols can always be pre-empted. */
22169 /* Non-global symbols cannot be pre-empted. */
22170 if (! S_IS_EXTERNAL (s
))
22174 /* In ELF, a global symbol can be marked protected, or private. In that
22175 case it can't be pre-empted (other definitions in the same link unit
22176 would violate the ODR). */
22177 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
22181 /* Other global symbols might be pre-empted. */
22185 /* Return the size of a relaxable branch instruction. BITS is the
22186 size of the offset field in the narrow instruction. */
22189 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22195 /* Assume worst case for symbols not known to be in the same section. */
22196 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22197 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22198 || S_IS_WEAK (fragp
->fr_symbol
))
22202 /* A branch to a function in ARM state will require interworking. */
22203 if (S_IS_DEFINED (fragp
->fr_symbol
)
22204 && ARM_IS_FUNC (fragp
->fr_symbol
))
22208 if (symbol_preemptible (fragp
->fr_symbol
))
22211 val
= relaxed_symbol_addr (fragp
, stretch
);
22212 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22215 /* Offset is a signed value *2 */
22217 if (val
>= limit
|| val
< -limit
)
22223 /* Relax a machine dependent frag. This returns the amount by which
22224 the current size of the frag should change. */
22227 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22232 oldsize
= fragp
->fr_var
;
22233 switch (fragp
->fr_subtype
)
22235 case T_MNEM_ldr_pc2
:
22236 newsize
= relax_adr (fragp
, sec
, stretch
);
22238 case T_MNEM_ldr_pc
:
22239 case T_MNEM_ldr_sp
:
22240 case T_MNEM_str_sp
:
22241 newsize
= relax_immediate (fragp
, 8, 2);
22245 newsize
= relax_immediate (fragp
, 5, 2);
22249 newsize
= relax_immediate (fragp
, 5, 1);
22253 newsize
= relax_immediate (fragp
, 5, 0);
22256 newsize
= relax_adr (fragp
, sec
, stretch
);
22262 newsize
= relax_immediate (fragp
, 8, 0);
22265 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22268 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22270 case T_MNEM_add_sp
:
22271 case T_MNEM_add_pc
:
22272 newsize
= relax_immediate (fragp
, 8, 2);
22274 case T_MNEM_inc_sp
:
22275 case T_MNEM_dec_sp
:
22276 newsize
= relax_immediate (fragp
, 7, 2);
22282 newsize
= relax_addsub (fragp
, sec
);
22288 fragp
->fr_var
= newsize
;
22289 /* Freeze wide instructions that are at or before the same location as
22290 in the previous pass. This avoids infinite loops.
22291 Don't freeze them unconditionally because targets may be artificially
22292 misaligned by the expansion of preceding frags. */
22293 if (stretch
<= 0 && newsize
> 2)
22295 md_convert_frag (sec
->owner
, sec
, fragp
);
22299 return newsize
- oldsize
;
22302 /* Round up a section size to the appropriate boundary. */
22305 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22311 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22312 of an rs_align_code fragment. */
22315 arm_handle_align (fragS
* fragP
)
22317 static unsigned char const arm_noop
[2][2][4] =
22320 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22321 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22324 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22325 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22328 static unsigned char const thumb_noop
[2][2][2] =
22331 {0xc0, 0x46}, /* LE */
22332 {0x46, 0xc0}, /* BE */
22335 {0x00, 0xbf}, /* LE */
22336 {0xbf, 0x00} /* BE */
22339 static unsigned char const wide_thumb_noop
[2][4] =
22340 { /* Wide Thumb-2 */
22341 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22342 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22345 unsigned bytes
, fix
, noop_size
;
22347 const unsigned char * noop
;
22348 const unsigned char *narrow_noop
= NULL
;
22353 if (fragP
->fr_type
!= rs_align_code
)
22356 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22357 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22360 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22361 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22363 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22365 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22367 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22368 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22370 narrow_noop
= thumb_noop
[1][target_big_endian
];
22371 noop
= wide_thumb_noop
[target_big_endian
];
22374 noop
= thumb_noop
[0][target_big_endian
];
22382 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22383 ? selected_cpu
: arm_arch_none
,
22385 [target_big_endian
];
22392 fragP
->fr_var
= noop_size
;
22394 if (bytes
& (noop_size
- 1))
22396 fix
= bytes
& (noop_size
- 1);
22398 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22400 memset (p
, 0, fix
);
22407 if (bytes
& noop_size
)
22409 /* Insert a narrow noop. */
22410 memcpy (p
, narrow_noop
, noop_size
);
22412 bytes
-= noop_size
;
22416 /* Use wide noops for the remainder */
22420 while (bytes
>= noop_size
)
22422 memcpy (p
, noop
, noop_size
);
22424 bytes
-= noop_size
;
22428 fragP
->fr_fix
+= fix
;
22431 /* Called from md_do_align. Used to create an alignment
22432 frag in a code section. */
22435 arm_frag_align_code (int n
, int max
)
22439 /* We assume that there will never be a requirement
22440 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22441 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22446 _("alignments greater than %d bytes not supported in .text sections."),
22447 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22448 as_fatal ("%s", err_msg
);
22451 p
= frag_var (rs_align_code
,
22452 MAX_MEM_FOR_RS_ALIGN_CODE
,
22454 (relax_substateT
) max
,
22461 /* Perform target specific initialisation of a frag.
22462 Note - despite the name this initialisation is not done when the frag
22463 is created, but only when its type is assigned. A frag can be created
22464 and used a long time before its type is set, so beware of assuming that
22465 this initialisation is performed first. */
22469 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22471 /* Record whether this frag is in an ARM or a THUMB area. */
22472 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22475 #else /* OBJ_ELF is defined. */
22477 arm_init_frag (fragS
* fragP
, int max_chars
)
22479 bfd_boolean frag_thumb_mode
;
22481 /* If the current ARM vs THUMB mode has not already
22482 been recorded into this frag then do so now. */
22483 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22484 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22486 /* PR 21809: Do not set a mapping state for debug sections
22487 - it just confuses other tools. */
22488 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22491 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22493 /* Record a mapping symbol for alignment frags. We will delete this
22494 later if the alignment ends up empty. */
22495 switch (fragP
->fr_type
)
22498 case rs_align_test
:
22500 mapping_state_2 (MAP_DATA
, max_chars
);
22502 case rs_align_code
:
22503 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22510 /* When we change sections we need to issue a new mapping symbol. */
22513 arm_elf_change_section (void)
22515 /* Link an unlinked unwind index table section to the .text section. */
22516 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22517 && elf_linked_to_section (now_seg
) == NULL
)
22518 elf_linked_to_section (now_seg
) = text_section
;
22522 arm_elf_section_type (const char * str
, size_t len
)
22524 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22525 return SHT_ARM_EXIDX
;
22530 /* Code to deal with unwinding tables. */
22532 static void add_unwind_adjustsp (offsetT
);
22534 /* Generate any deferred unwind frame offset. */
22537 flush_pending_unwind (void)
22541 offset
= unwind
.pending_offset
;
22542 unwind
.pending_offset
= 0;
22544 add_unwind_adjustsp (offset
);
22547 /* Add an opcode to this list for this function. Two-byte opcodes should
22548 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22552 add_unwind_opcode (valueT op
, int length
)
22554 /* Add any deferred stack adjustment. */
22555 if (unwind
.pending_offset
)
22556 flush_pending_unwind ();
22558 unwind
.sp_restored
= 0;
22560 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22562 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22563 if (unwind
.opcodes
)
22564 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22565 unwind
.opcode_alloc
);
22567 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22572 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22574 unwind
.opcode_count
++;
22578 /* Add unwind opcodes to adjust the stack pointer. */
22581 add_unwind_adjustsp (offsetT offset
)
22585 if (offset
> 0x200)
22587 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22592 /* Long form: 0xb2, uleb128. */
22593 /* This might not fit in a word so add the individual bytes,
22594 remembering the list is built in reverse order. */
22595 o
= (valueT
) ((offset
- 0x204) >> 2);
22597 add_unwind_opcode (0, 1);
22599 /* Calculate the uleb128 encoding of the offset. */
22603 bytes
[n
] = o
& 0x7f;
22609 /* Add the insn. */
22611 add_unwind_opcode (bytes
[n
- 1], 1);
22612 add_unwind_opcode (0xb2, 1);
22614 else if (offset
> 0x100)
22616 /* Two short opcodes. */
22617 add_unwind_opcode (0x3f, 1);
22618 op
= (offset
- 0x104) >> 2;
22619 add_unwind_opcode (op
, 1);
22621 else if (offset
> 0)
22623 /* Short opcode. */
22624 op
= (offset
- 4) >> 2;
22625 add_unwind_opcode (op
, 1);
22627 else if (offset
< 0)
22630 while (offset
> 0x100)
22632 add_unwind_opcode (0x7f, 1);
22635 op
= ((offset
- 4) >> 2) | 0x40;
22636 add_unwind_opcode (op
, 1);
22640 /* Finish the list of unwind opcodes for this function. */
22643 finish_unwind_opcodes (void)
22647 if (unwind
.fp_used
)
22649 /* Adjust sp as necessary. */
22650 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22651 flush_pending_unwind ();
22653 /* After restoring sp from the frame pointer. */
22654 op
= 0x90 | unwind
.fp_reg
;
22655 add_unwind_opcode (op
, 1);
22658 flush_pending_unwind ();
22662 /* Start an exception table entry. If idx is nonzero this is an index table
22666 start_unwind_section (const segT text_seg
, int idx
)
22668 const char * text_name
;
22669 const char * prefix
;
22670 const char * prefix_once
;
22671 const char * group_name
;
22679 prefix
= ELF_STRING_ARM_unwind
;
22680 prefix_once
= ELF_STRING_ARM_unwind_once
;
22681 type
= SHT_ARM_EXIDX
;
22685 prefix
= ELF_STRING_ARM_unwind_info
;
22686 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22687 type
= SHT_PROGBITS
;
22690 text_name
= segment_name (text_seg
);
22691 if (streq (text_name
, ".text"))
22694 if (strncmp (text_name
, ".gnu.linkonce.t.",
22695 strlen (".gnu.linkonce.t.")) == 0)
22697 prefix
= prefix_once
;
22698 text_name
+= strlen (".gnu.linkonce.t.");
22701 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22707 /* Handle COMDAT group. */
22708 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22710 group_name
= elf_group_name (text_seg
);
22711 if (group_name
== NULL
)
22713 as_bad (_("Group section `%s' has no group signature"),
22714 segment_name (text_seg
));
22715 ignore_rest_of_line ();
22718 flags
|= SHF_GROUP
;
22722 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22725 /* Set the section link for index tables. */
22727 elf_linked_to_section (now_seg
) = text_seg
;
22731 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22732 personality routine data. Returns zero, or the index table value for
22733 an inline entry. */
22736 create_unwind_entry (int have_data
)
22741 /* The current word of data. */
22743 /* The number of bytes left in this word. */
22746 finish_unwind_opcodes ();
22748 /* Remember the current text section. */
22749 unwind
.saved_seg
= now_seg
;
22750 unwind
.saved_subseg
= now_subseg
;
22752 start_unwind_section (now_seg
, 0);
22754 if (unwind
.personality_routine
== NULL
)
22756 if (unwind
.personality_index
== -2)
22759 as_bad (_("handlerdata in cantunwind frame"));
22760 return 1; /* EXIDX_CANTUNWIND. */
22763 /* Use a default personality routine if none is specified. */
22764 if (unwind
.personality_index
== -1)
22766 if (unwind
.opcode_count
> 3)
22767 unwind
.personality_index
= 1;
22769 unwind
.personality_index
= 0;
22772 /* Space for the personality routine entry. */
22773 if (unwind
.personality_index
== 0)
22775 if (unwind
.opcode_count
> 3)
22776 as_bad (_("too many unwind opcodes for personality routine 0"));
22780 /* All the data is inline in the index table. */
22783 while (unwind
.opcode_count
> 0)
22785 unwind
.opcode_count
--;
22786 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22790 /* Pad with "finish" opcodes. */
22792 data
= (data
<< 8) | 0xb0;
22799 /* We get two opcodes "free" in the first word. */
22800 size
= unwind
.opcode_count
- 2;
22804 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22805 if (unwind
.personality_index
!= -1)
22807 as_bad (_("attempt to recreate an unwind entry"));
22811 /* An extra byte is required for the opcode count. */
22812 size
= unwind
.opcode_count
+ 1;
22815 size
= (size
+ 3) >> 2;
22817 as_bad (_("too many unwind opcodes"));
22819 frag_align (2, 0, 0);
22820 record_alignment (now_seg
, 2);
22821 unwind
.table_entry
= expr_build_dot ();
22823 /* Allocate the table entry. */
22824 ptr
= frag_more ((size
<< 2) + 4);
22825 /* PR 13449: Zero the table entries in case some of them are not used. */
22826 memset (ptr
, 0, (size
<< 2) + 4);
22827 where
= frag_now_fix () - ((size
<< 2) + 4);
22829 switch (unwind
.personality_index
)
22832 /* ??? Should this be a PLT generating relocation? */
22833 /* Custom personality routine. */
22834 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22835 BFD_RELOC_ARM_PREL31
);
22840 /* Set the first byte to the number of additional words. */
22841 data
= size
> 0 ? size
- 1 : 0;
22845 /* ABI defined personality routines. */
22847 /* Three opcodes bytes are packed into the first word. */
22854 /* The size and first two opcode bytes go in the first word. */
22855 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22860 /* Should never happen. */
22864 /* Pack the opcodes into words (MSB first), reversing the list at the same
22866 while (unwind
.opcode_count
> 0)
22870 md_number_to_chars (ptr
, data
, 4);
22875 unwind
.opcode_count
--;
22877 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22880 /* Finish off the last word. */
22883 /* Pad with "finish" opcodes. */
22885 data
= (data
<< 8) | 0xb0;
22887 md_number_to_chars (ptr
, data
, 4);
22892 /* Add an empty descriptor if there is no user-specified data. */
22893 ptr
= frag_more (4);
22894 md_number_to_chars (ptr
, 0, 4);
22901 /* Initialize the DWARF-2 unwind information for this procedure. */
22904 tc_arm_frame_initial_instructions (void)
22906 cfi_add_CFA_def_cfa (REG_SP
, 0);
22908 #endif /* OBJ_ELF */
22910 /* Convert REGNAME to a DWARF-2 register number. */
22913 tc_arm_regname_to_dw2regnum (char *regname
)
22915 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22919 /* PR 16694: Allow VFP registers as well. */
22920 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22924 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22933 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22937 exp
.X_op
= O_secrel
;
22938 exp
.X_add_symbol
= symbol
;
22939 exp
.X_add_number
= 0;
22940 emit_expr (&exp
, size
);
22944 /* MD interface: Symbol and relocation handling. */
22946 /* Return the address within the segment that a PC-relative fixup is
22947 relative to. For ARM, PC-relative fixups applied to instructions
22948 are generally relative to the location of the fixup plus 8 bytes.
22949 Thumb branches are offset by 4, and Thumb loads relative to PC
22950 require special handling. */
22953 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22955 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22957 /* If this is pc-relative and we are going to emit a relocation
22958 then we just want to put out any pipeline compensation that the linker
22959 will need. Otherwise we want to use the calculated base.
22960 For WinCE we skip the bias for externals as well, since this
22961 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22963 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22964 || (arm_force_relocation (fixP
)
22966 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22972 switch (fixP
->fx_r_type
)
22974 /* PC relative addressing on the Thumb is slightly odd as the
22975 bottom two bits of the PC are forced to zero for the
22976 calculation. This happens *after* application of the
22977 pipeline offset. However, Thumb adrl already adjusts for
22978 this, so we need not do it again. */
22979 case BFD_RELOC_ARM_THUMB_ADD
:
22982 case BFD_RELOC_ARM_THUMB_OFFSET
:
22983 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22984 case BFD_RELOC_ARM_T32_ADD_PC12
:
22985 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22986 return (base
+ 4) & ~3;
22988 /* Thumb branches are simply offset by +4. */
22989 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
22990 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22991 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22992 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22993 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22994 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22995 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
22996 case BFD_RELOC_ARM_THUMB_BF17
:
22997 case BFD_RELOC_ARM_THUMB_BF19
:
22998 case BFD_RELOC_ARM_THUMB_BF13
:
23001 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23003 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23004 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23005 && ARM_IS_FUNC (fixP
->fx_addsy
)
23006 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23007 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23010 /* BLX is like branches above, but forces the low two bits of PC to
23012 case BFD_RELOC_THUMB_PCREL_BLX
:
23014 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23015 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23016 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23017 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23018 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23019 return (base
+ 4) & ~3;
23021 /* ARM mode branches are offset by +8. However, the Windows CE
23022 loader expects the relocation not to take this into account. */
23023 case BFD_RELOC_ARM_PCREL_BLX
:
23025 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23026 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23027 && ARM_IS_FUNC (fixP
->fx_addsy
)
23028 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23029 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23032 case BFD_RELOC_ARM_PCREL_CALL
:
23034 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23035 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23036 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23037 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23038 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23041 case BFD_RELOC_ARM_PCREL_BRANCH
:
23042 case BFD_RELOC_ARM_PCREL_JUMP
:
23043 case BFD_RELOC_ARM_PLT32
:
23045 /* When handling fixups immediately, because we have already
23046 discovered the value of a symbol, or the address of the frag involved
23047 we must account for the offset by +8, as the OS loader will never see the reloc.
23048 see fixup_segment() in write.c
23049 The S_IS_EXTERNAL test handles the case of global symbols.
23050 Those need the calculated base, not just the pipe compensation the linker will need. */
23052 && fixP
->fx_addsy
!= NULL
23053 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23054 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
23062 /* ARM mode loads relative to PC are also offset by +8. Unlike
23063 branches, the Windows CE loader *does* expect the relocation
23064 to take this into account. */
23065 case BFD_RELOC_ARM_OFFSET_IMM
:
23066 case BFD_RELOC_ARM_OFFSET_IMM8
:
23067 case BFD_RELOC_ARM_HWLITERAL
:
23068 case BFD_RELOC_ARM_LITERAL
:
23069 case BFD_RELOC_ARM_CP_OFF_IMM
:
23073 /* Other PC-relative relocations are un-offset. */
23079 static bfd_boolean flag_warn_syms
= TRUE
;
23082 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
23084 /* PR 18347 - Warn if the user attempts to create a symbol with the same
23085 name as an ARM instruction. Whilst strictly speaking it is allowed, it
23086 does mean that the resulting code might be very confusing to the reader.
23087 Also this warning can be triggered if the user omits an operand before
23088 an immediate address, eg:
23092 GAS treats this as an assignment of the value of the symbol foo to a
23093 symbol LDR, and so (without this code) it will not issue any kind of
23094 warning or error message.
23096 Note - ARM instructions are case-insensitive but the strings in the hash
23097 table are all stored in lower case, so we must first ensure that name is
23099 if (flag_warn_syms
&& arm_ops_hsh
)
23101 char * nbuf
= strdup (name
);
23104 for (p
= nbuf
; *p
; p
++)
23106 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
23108 static struct hash_control
* already_warned
= NULL
;
23110 if (already_warned
== NULL
)
23111 already_warned
= hash_new ();
23112 /* Only warn about the symbol once. To keep the code
23113 simple we let hash_insert do the lookup for us. */
23114 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
23115 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
23124 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
23125 Otherwise we have no need to default values of symbols. */
23128 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
23131 if (name
[0] == '_' && name
[1] == 'G'
23132 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
23136 if (symbol_find (name
))
23137 as_bad (_("GOT already in the symbol table"));
23139 GOT_symbol
= symbol_new (name
, undefined_section
,
23140 (valueT
) 0, & zero_address_frag
);
23150 /* Subroutine of md_apply_fix. Check to see if an immediate can be
23151 computed as two separate immediate values, added together. We
23152 already know that this value cannot be computed by just one ARM
23155 static unsigned int
23156 validate_immediate_twopart (unsigned int val
,
23157 unsigned int * highpart
)
23162 for (i
= 0; i
< 32; i
+= 2)
23163 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
23169 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
23171 else if (a
& 0xff0000)
23173 if (a
& 0xff000000)
23175 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
23179 gas_assert (a
& 0xff000000);
23180 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
23183 return (a
& 0xff) | (i
<< 7);
23190 validate_offset_imm (unsigned int val
, int hwse
)
23192 if ((hwse
&& val
> 255) || val
> 4095)
23197 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23198 negative immediate constant by altering the instruction. A bit of
23203 by inverting the second operand, and
23206 by negating the second operand. */
23209 negate_data_op (unsigned long * instruction
,
23210 unsigned long value
)
23213 unsigned long negated
, inverted
;
23215 negated
= encode_arm_immediate (-value
);
23216 inverted
= encode_arm_immediate (~value
);
23218 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23221 /* First negates. */
23222 case OPCODE_SUB
: /* ADD <-> SUB */
23223 new_inst
= OPCODE_ADD
;
23228 new_inst
= OPCODE_SUB
;
23232 case OPCODE_CMP
: /* CMP <-> CMN */
23233 new_inst
= OPCODE_CMN
;
23238 new_inst
= OPCODE_CMP
;
23242 /* Now Inverted ops. */
23243 case OPCODE_MOV
: /* MOV <-> MVN */
23244 new_inst
= OPCODE_MVN
;
23249 new_inst
= OPCODE_MOV
;
23253 case OPCODE_AND
: /* AND <-> BIC */
23254 new_inst
= OPCODE_BIC
;
23259 new_inst
= OPCODE_AND
;
23263 case OPCODE_ADC
: /* ADC <-> SBC */
23264 new_inst
= OPCODE_SBC
;
23269 new_inst
= OPCODE_ADC
;
23273 /* We cannot do anything. */
23278 if (value
== (unsigned) FAIL
)
23281 *instruction
&= OPCODE_MASK
;
23282 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23286 /* Like negate_data_op, but for Thumb-2. */
23288 static unsigned int
23289 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23293 unsigned int negated
, inverted
;
23295 negated
= encode_thumb32_immediate (-value
);
23296 inverted
= encode_thumb32_immediate (~value
);
23298 rd
= (*instruction
>> 8) & 0xf;
23299 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23302 /* ADD <-> SUB. Includes CMP <-> CMN. */
23303 case T2_OPCODE_SUB
:
23304 new_inst
= T2_OPCODE_ADD
;
23308 case T2_OPCODE_ADD
:
23309 new_inst
= T2_OPCODE_SUB
;
23313 /* ORR <-> ORN. Includes MOV <-> MVN. */
23314 case T2_OPCODE_ORR
:
23315 new_inst
= T2_OPCODE_ORN
;
23319 case T2_OPCODE_ORN
:
23320 new_inst
= T2_OPCODE_ORR
;
23324 /* AND <-> BIC. TST has no inverted equivalent. */
23325 case T2_OPCODE_AND
:
23326 new_inst
= T2_OPCODE_BIC
;
23333 case T2_OPCODE_BIC
:
23334 new_inst
= T2_OPCODE_AND
;
23339 case T2_OPCODE_ADC
:
23340 new_inst
= T2_OPCODE_SBC
;
23344 case T2_OPCODE_SBC
:
23345 new_inst
= T2_OPCODE_ADC
;
23349 /* We cannot do anything. */
23354 if (value
== (unsigned int)FAIL
)
23357 *instruction
&= T2_OPCODE_MASK
;
23358 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23362 /* Read a 32-bit thumb instruction from buf. */
23364 static unsigned long
23365 get_thumb32_insn (char * buf
)
23367 unsigned long insn
;
23368 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23369 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23374 /* We usually want to set the low bit on the address of thumb function
23375 symbols. In particular .word foo - . should have the low bit set.
23376 Generic code tries to fold the difference of two symbols to
23377 a constant. Prevent this and force a relocation when the first symbols
23378 is a thumb function. */
23381 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23383 if (op
== O_subtract
23384 && l
->X_op
== O_symbol
23385 && r
->X_op
== O_symbol
23386 && THUMB_IS_FUNC (l
->X_add_symbol
))
23388 l
->X_op
= O_subtract
;
23389 l
->X_op_symbol
= r
->X_add_symbol
;
23390 l
->X_add_number
-= r
->X_add_number
;
23394 /* Process as normal. */
23398 /* Encode Thumb2 unconditional branches and calls. The encoding
23399 for the 2 are identical for the immediate values. */
23402 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23404 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23407 addressT S
, I1
, I2
, lo
, hi
;
23409 S
= (value
>> 24) & 0x01;
23410 I1
= (value
>> 23) & 0x01;
23411 I2
= (value
>> 22) & 0x01;
23412 hi
= (value
>> 12) & 0x3ff;
23413 lo
= (value
>> 1) & 0x7ff;
23414 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23415 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23416 newval
|= (S
<< 10) | hi
;
23417 newval2
&= ~T2I1I2MASK
;
23418 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23419 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23420 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23424 md_apply_fix (fixS
* fixP
,
23428 offsetT value
= * valP
;
23430 unsigned int newimm
;
23431 unsigned long temp
;
23433 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23435 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23437 /* Note whether this will delete the relocation. */
23439 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23442 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23443 consistency with the behaviour on 32-bit hosts. Remember value
23445 value
&= 0xffffffff;
23446 value
^= 0x80000000;
23447 value
-= 0x80000000;
23450 fixP
->fx_addnumber
= value
;
23452 /* Same treatment for fixP->fx_offset. */
23453 fixP
->fx_offset
&= 0xffffffff;
23454 fixP
->fx_offset
^= 0x80000000;
23455 fixP
->fx_offset
-= 0x80000000;
23457 switch (fixP
->fx_r_type
)
23459 case BFD_RELOC_NONE
:
23460 /* This will need to go in the object file. */
23464 case BFD_RELOC_ARM_IMMEDIATE
:
23465 /* We claim that this fixup has been processed here,
23466 even if in fact we generate an error because we do
23467 not have a reloc for it, so tc_gen_reloc will reject it. */
23470 if (fixP
->fx_addsy
)
23472 const char *msg
= 0;
23474 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23475 msg
= _("undefined symbol %s used as an immediate value");
23476 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23477 msg
= _("symbol %s is in a different section");
23478 else if (S_IS_WEAK (fixP
->fx_addsy
))
23479 msg
= _("symbol %s is weak and may be overridden later");
23483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23484 msg
, S_GET_NAME (fixP
->fx_addsy
));
23489 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23491 /* If the offset is negative, we should use encoding A2 for ADR. */
23492 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23493 newimm
= negate_data_op (&temp
, value
);
23496 newimm
= encode_arm_immediate (value
);
23498 /* If the instruction will fail, see if we can fix things up by
23499 changing the opcode. */
23500 if (newimm
== (unsigned int) FAIL
)
23501 newimm
= negate_data_op (&temp
, value
);
23502 /* MOV accepts both ARM modified immediate (A1 encoding) and
23503 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23504 When disassembling, MOV is preferred when there is no encoding
23506 if (newimm
== (unsigned int) FAIL
23507 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23508 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23509 && !((temp
>> SBIT_SHIFT
) & 0x1)
23510 && value
>= 0 && value
<= 0xffff)
23512 /* Clear bits[23:20] to change encoding from A1 to A2. */
23513 temp
&= 0xff0fffff;
23514 /* Encoding high 4bits imm. Code below will encode the remaining
23516 temp
|= (value
& 0x0000f000) << 4;
23517 newimm
= value
& 0x00000fff;
23521 if (newimm
== (unsigned int) FAIL
)
23523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23524 _("invalid constant (%lx) after fixup"),
23525 (unsigned long) value
);
23529 newimm
|= (temp
& 0xfffff000);
23530 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23533 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23535 unsigned int highpart
= 0;
23536 unsigned int newinsn
= 0xe1a00000; /* nop. */
23538 if (fixP
->fx_addsy
)
23540 const char *msg
= 0;
23542 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23543 msg
= _("undefined symbol %s used as an immediate value");
23544 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23545 msg
= _("symbol %s is in a different section");
23546 else if (S_IS_WEAK (fixP
->fx_addsy
))
23547 msg
= _("symbol %s is weak and may be overridden later");
23551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23552 msg
, S_GET_NAME (fixP
->fx_addsy
));
23557 newimm
= encode_arm_immediate (value
);
23558 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23560 /* If the instruction will fail, see if we can fix things up by
23561 changing the opcode. */
23562 if (newimm
== (unsigned int) FAIL
23563 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23565 /* No ? OK - try using two ADD instructions to generate
23567 newimm
= validate_immediate_twopart (value
, & highpart
);
23569 /* Yes - then make sure that the second instruction is
23571 if (newimm
!= (unsigned int) FAIL
)
23573 /* Still No ? Try using a negated value. */
23574 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23575 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23576 /* Otherwise - give up. */
23579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23580 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23585 /* Replace the first operand in the 2nd instruction (which
23586 is the PC) with the destination register. We have
23587 already added in the PC in the first instruction and we
23588 do not want to do it again. */
23589 newinsn
&= ~ 0xf0000;
23590 newinsn
|= ((newinsn
& 0x0f000) << 4);
23593 newimm
|= (temp
& 0xfffff000);
23594 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23596 highpart
|= (newinsn
& 0xfffff000);
23597 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23601 case BFD_RELOC_ARM_OFFSET_IMM
:
23602 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23604 /* Fall through. */
23606 case BFD_RELOC_ARM_LITERAL
:
23612 if (validate_offset_imm (value
, 0) == FAIL
)
23614 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23616 _("invalid literal constant: pool needs to be closer"));
23618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23619 _("bad immediate value for offset (%ld)"),
23624 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23626 newval
&= 0xfffff000;
23629 newval
&= 0xff7ff000;
23630 newval
|= value
| (sign
? INDEX_UP
: 0);
23632 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23635 case BFD_RELOC_ARM_OFFSET_IMM8
:
23636 case BFD_RELOC_ARM_HWLITERAL
:
23642 if (validate_offset_imm (value
, 1) == FAIL
)
23644 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23646 _("invalid literal constant: pool needs to be closer"));
23648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23649 _("bad immediate value for 8-bit offset (%ld)"),
23654 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23656 newval
&= 0xfffff0f0;
23659 newval
&= 0xff7ff0f0;
23660 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23662 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23665 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23666 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23668 _("bad immediate value for offset (%ld)"), (long) value
);
23671 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23673 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23676 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23677 /* This is a complicated relocation used for all varieties of Thumb32
23678 load/store instruction with immediate offset:
23680 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23681 *4, optional writeback(W)
23682 (doubleword load/store)
23684 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23685 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23686 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23687 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23688 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23690 Uppercase letters indicate bits that are already encoded at
23691 this point. Lowercase letters are our problem. For the
23692 second block of instructions, the secondary opcode nybble
23693 (bits 8..11) is present, and bit 23 is zero, even if this is
23694 a PC-relative operation. */
23695 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23697 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23699 if ((newval
& 0xf0000000) == 0xe0000000)
23701 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23703 newval
|= (1 << 23);
23706 if (value
% 4 != 0)
23708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23709 _("offset not a multiple of 4"));
23715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23716 _("offset out of range"));
23721 else if ((newval
& 0x000f0000) == 0x000f0000)
23723 /* PC-relative, 12-bit offset. */
23725 newval
|= (1 << 23);
23730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23731 _("offset out of range"));
23736 else if ((newval
& 0x00000100) == 0x00000100)
23738 /* Writeback: 8-bit, +/- offset. */
23740 newval
|= (1 << 9);
23745 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23746 _("offset out of range"));
23751 else if ((newval
& 0x00000f00) == 0x00000e00)
23753 /* T-instruction: positive 8-bit offset. */
23754 if (value
< 0 || value
> 0xff)
23756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23757 _("offset out of range"));
23765 /* Positive 12-bit or negative 8-bit offset. */
23769 newval
|= (1 << 23);
23779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23780 _("offset out of range"));
23787 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23788 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23791 case BFD_RELOC_ARM_SHIFT_IMM
:
23792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23793 if (((unsigned long) value
) > 32
23795 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23798 _("shift expression is too large"));
23803 /* Shifts of zero must be done as lsl. */
23805 else if (value
== 32)
23807 newval
&= 0xfffff07f;
23808 newval
|= (value
& 0x1f) << 7;
23809 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23812 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23813 case BFD_RELOC_ARM_T32_ADD_IMM
:
23814 case BFD_RELOC_ARM_T32_IMM12
:
23815 case BFD_RELOC_ARM_T32_ADD_PC12
:
23816 /* We claim that this fixup has been processed here,
23817 even if in fact we generate an error because we do
23818 not have a reloc for it, so tc_gen_reloc will reject it. */
23822 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23825 _("undefined symbol %s used as an immediate value"),
23826 S_GET_NAME (fixP
->fx_addsy
));
23830 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23832 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23835 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23836 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23837 Thumb2 modified immediate encoding (T2). */
23838 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23839 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23841 newimm
= encode_thumb32_immediate (value
);
23842 if (newimm
== (unsigned int) FAIL
)
23843 newimm
= thumb32_negate_data_op (&newval
, value
);
23845 if (newimm
== (unsigned int) FAIL
)
23847 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23849 /* Turn add/sum into addw/subw. */
23850 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23851 newval
= (newval
& 0xfeffffff) | 0x02000000;
23852 /* No flat 12-bit imm encoding for addsw/subsw. */
23853 if ((newval
& 0x00100000) == 0)
23855 /* 12 bit immediate for addw/subw. */
23859 newval
^= 0x00a00000;
23862 newimm
= (unsigned int) FAIL
;
23869 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23870 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23871 disassembling, MOV is preferred when there is no encoding
23873 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23874 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23875 but with the Rn field [19:16] set to 1111. */
23876 && (((newval
>> 16) & 0xf) == 0xf)
23877 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23878 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23879 && value
>= 0 && value
<= 0xffff)
23881 /* Toggle bit[25] to change encoding from T2 to T3. */
23883 /* Clear bits[19:16]. */
23884 newval
&= 0xfff0ffff;
23885 /* Encoding high 4bits imm. Code below will encode the
23886 remaining low 12bits. */
23887 newval
|= (value
& 0x0000f000) << 4;
23888 newimm
= value
& 0x00000fff;
23893 if (newimm
== (unsigned int)FAIL
)
23895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23896 _("invalid constant (%lx) after fixup"),
23897 (unsigned long) value
);
23901 newval
|= (newimm
& 0x800) << 15;
23902 newval
|= (newimm
& 0x700) << 4;
23903 newval
|= (newimm
& 0x0ff);
23905 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23906 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23909 case BFD_RELOC_ARM_SMC
:
23910 if (((unsigned long) value
) > 0xffff)
23911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23912 _("invalid smc expression"));
23913 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23914 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23915 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23918 case BFD_RELOC_ARM_HVC
:
23919 if (((unsigned long) value
) > 0xffff)
23920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23921 _("invalid hvc expression"));
23922 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23923 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23924 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23927 case BFD_RELOC_ARM_SWI
:
23928 if (fixP
->tc_fix_data
!= 0)
23930 if (((unsigned long) value
) > 0xff)
23931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23932 _("invalid swi expression"));
23933 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23935 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23939 if (((unsigned long) value
) > 0x00ffffff)
23940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23941 _("invalid swi expression"));
23942 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23944 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23948 case BFD_RELOC_ARM_MULTI
:
23949 if (((unsigned long) value
) > 0xffff)
23950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23951 _("invalid expression in load/store multiple"));
23952 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23953 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23957 case BFD_RELOC_ARM_PCREL_CALL
:
23959 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23961 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23962 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23963 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23964 /* Flip the bl to blx. This is a simple flip
23965 bit here because we generate PCREL_CALL for
23966 unconditional bls. */
23968 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23969 newval
= newval
| 0x10000000;
23970 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23976 goto arm_branch_common
;
23978 case BFD_RELOC_ARM_PCREL_JUMP
:
23979 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23981 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23982 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23983 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23985 /* This would map to a bl<cond>, b<cond>,
23986 b<always> to a Thumb function. We
23987 need to force a relocation for this particular
23989 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23992 /* Fall through. */
23994 case BFD_RELOC_ARM_PLT32
:
23996 case BFD_RELOC_ARM_PCREL_BRANCH
:
23998 goto arm_branch_common
;
24000 case BFD_RELOC_ARM_PCREL_BLX
:
24003 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24005 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24006 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24007 && ARM_IS_FUNC (fixP
->fx_addsy
))
24009 /* Flip the blx to a bl and warn. */
24010 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24011 newval
= 0xeb000000;
24012 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24013 _("blx to '%s' an ARM ISA state function changed to bl"),
24015 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24021 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24022 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
24026 /* We are going to store value (shifted right by two) in the
24027 instruction, in a 24 bit, signed field. Bits 26 through 32 either
24028 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
24031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24032 _("misaligned branch destination"));
24033 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
24034 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
24035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24037 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24039 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24040 newval
|= (value
>> 2) & 0x00ffffff;
24041 /* Set the H bit on BLX instructions. */
24045 newval
|= 0x01000000;
24047 newval
&= ~0x01000000;
24049 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24053 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
24054 /* CBZ can only branch forward. */
24056 /* Attempts to use CBZ to branch to the next instruction
24057 (which, strictly speaking, are prohibited) will be turned into
24060 FIXME: It may be better to remove the instruction completely and
24061 perform relaxation. */
24064 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24065 newval
= 0xbf00; /* NOP encoding T1 */
24066 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24073 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24075 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24076 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
24077 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24082 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
24083 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
24084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24086 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24088 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24089 newval
|= (value
& 0x1ff) >> 1;
24090 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24094 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
24095 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
24096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24098 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24100 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24101 newval
|= (value
& 0xfff) >> 1;
24102 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24106 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24108 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24109 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24110 && ARM_IS_FUNC (fixP
->fx_addsy
)
24111 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24113 /* Force a relocation for a branch 20 bits wide. */
24116 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
24117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24118 _("conditional branch out of range"));
24120 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24123 addressT S
, J1
, J2
, lo
, hi
;
24125 S
= (value
& 0x00100000) >> 20;
24126 J2
= (value
& 0x00080000) >> 19;
24127 J1
= (value
& 0x00040000) >> 18;
24128 hi
= (value
& 0x0003f000) >> 12;
24129 lo
= (value
& 0x00000ffe) >> 1;
24131 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24132 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24133 newval
|= (S
<< 10) | hi
;
24134 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
24135 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24136 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24140 case BFD_RELOC_THUMB_PCREL_BLX
:
24141 /* If there is a blx from a thumb state function to
24142 another thumb function flip this to a bl and warn
24146 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24147 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24148 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24150 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24151 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24152 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
24154 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24155 newval
= newval
| 0x1000;
24156 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24157 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24162 goto thumb_bl_common
;
24164 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24165 /* A bl from Thumb state ISA to an internal ARM state function
24166 is converted to a blx. */
24168 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24169 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24170 && ARM_IS_FUNC (fixP
->fx_addsy
)
24171 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24173 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24174 newval
= newval
& ~0x1000;
24175 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24176 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
24182 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24183 /* For a BLX instruction, make sure that the relocation is rounded up
24184 to a word boundary. This follows the semantics of the instruction
24185 which specifies that bit 1 of the target address will come from bit
24186 1 of the base address. */
24187 value
= (value
+ 3) & ~ 3;
24190 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
24191 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24192 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24195 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24197 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24199 else if ((value
& ~0x1ffffff)
24200 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24202 _("Thumb2 branch out of range"));
24205 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24206 encode_thumb2_b_bl_offset (buf
, value
);
24210 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24211 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24214 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24215 encode_thumb2_b_bl_offset (buf
, value
);
24220 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24225 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24226 md_number_to_chars (buf
, value
, 2);
24230 case BFD_RELOC_ARM_TLS_CALL
:
24231 case BFD_RELOC_ARM_THM_TLS_CALL
:
24232 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24233 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24234 case BFD_RELOC_ARM_TLS_GOTDESC
:
24235 case BFD_RELOC_ARM_TLS_GD32
:
24236 case BFD_RELOC_ARM_TLS_LE32
:
24237 case BFD_RELOC_ARM_TLS_IE32
:
24238 case BFD_RELOC_ARM_TLS_LDM32
:
24239 case BFD_RELOC_ARM_TLS_LDO32
:
24240 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24243 /* Same handling as above, but with the arm_fdpic guard. */
24244 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24245 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24246 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24249 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24254 _("Relocation supported only in FDPIC mode"));
24258 case BFD_RELOC_ARM_GOT32
:
24259 case BFD_RELOC_ARM_GOTOFF
:
24262 case BFD_RELOC_ARM_GOT_PREL
:
24263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24264 md_number_to_chars (buf
, value
, 4);
24267 case BFD_RELOC_ARM_TARGET2
:
24268 /* TARGET2 is not partial-inplace, so we need to write the
24269 addend here for REL targets, because it won't be written out
24270 during reloc processing later. */
24271 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24272 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24275 /* Relocations for FDPIC. */
24276 case BFD_RELOC_ARM_GOTFUNCDESC
:
24277 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24278 case BFD_RELOC_ARM_FUNCDESC
:
24281 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24282 md_number_to_chars (buf
, 0, 4);
24286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24287 _("Relocation supported only in FDPIC mode"));
24292 case BFD_RELOC_RVA
:
24294 case BFD_RELOC_ARM_TARGET1
:
24295 case BFD_RELOC_ARM_ROSEGREL32
:
24296 case BFD_RELOC_ARM_SBREL32
:
24297 case BFD_RELOC_32_PCREL
:
24299 case BFD_RELOC_32_SECREL
:
24301 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24303 /* For WinCE we only do this for pcrel fixups. */
24304 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24306 md_number_to_chars (buf
, value
, 4);
24310 case BFD_RELOC_ARM_PREL31
:
24311 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24313 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24314 if ((value
^ (value
>> 1)) & 0x40000000)
24316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24317 _("rel31 relocation overflow"));
24319 newval
|= value
& 0x7fffffff;
24320 md_number_to_chars (buf
, newval
, 4);
24325 case BFD_RELOC_ARM_CP_OFF_IMM
:
24326 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24327 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24328 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24330 newval
= get_thumb32_insn (buf
);
24331 if ((newval
& 0x0f200f00) == 0x0d000900)
24333 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24334 has permitted values that are multiples of 2, in the range 0
24336 if (value
< -510 || value
> 510 || (value
& 1))
24337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24338 _("co-processor offset out of range"));
24340 else if (value
< -1023 || value
> 1023 || (value
& 3))
24341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24342 _("co-processor offset out of range"));
24347 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24348 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24349 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24351 newval
= get_thumb32_insn (buf
);
24353 newval
&= 0xffffff00;
24356 newval
&= 0xff7fff00;
24357 if ((newval
& 0x0f200f00) == 0x0d000900)
24359 /* This is a fp16 vstr/vldr.
24361 It requires the immediate offset in the instruction is shifted
24362 left by 1 to be a half-word offset.
24364 Here, left shift by 1 first, and later right shift by 2
24365 should get the right offset. */
24368 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24370 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24371 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24372 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24374 put_thumb32_insn (buf
, newval
);
24377 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24378 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24379 if (value
< -255 || value
> 255)
24380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24381 _("co-processor offset out of range"));
24383 goto cp_off_common
;
24385 case BFD_RELOC_ARM_THUMB_OFFSET
:
24386 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24387 /* Exactly what ranges, and where the offset is inserted depends
24388 on the type of instruction, we can establish this from the
24390 switch (newval
>> 12)
24392 case 4: /* PC load. */
24393 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24394 forced to zero for these loads; md_pcrel_from has already
24395 compensated for this. */
24397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24398 _("invalid offset, target not word aligned (0x%08lX)"),
24399 (((unsigned long) fixP
->fx_frag
->fr_address
24400 + (unsigned long) fixP
->fx_where
) & ~3)
24401 + (unsigned long) value
);
24403 if (value
& ~0x3fc)
24404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24405 _("invalid offset, value too big (0x%08lX)"),
24408 newval
|= value
>> 2;
24411 case 9: /* SP load/store. */
24412 if (value
& ~0x3fc)
24413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24414 _("invalid offset, value too big (0x%08lX)"),
24416 newval
|= value
>> 2;
24419 case 6: /* Word load/store. */
24421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24422 _("invalid offset, value too big (0x%08lX)"),
24424 newval
|= value
<< 4; /* 6 - 2. */
24427 case 7: /* Byte load/store. */
24429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24430 _("invalid offset, value too big (0x%08lX)"),
24432 newval
|= value
<< 6;
24435 case 8: /* Halfword load/store. */
24437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24438 _("invalid offset, value too big (0x%08lX)"),
24440 newval
|= value
<< 5; /* 6 - 1. */
24444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24445 "Unable to process relocation for thumb opcode: %lx",
24446 (unsigned long) newval
);
24449 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24452 case BFD_RELOC_ARM_THUMB_ADD
:
24453 /* This is a complicated relocation, since we use it for all of
24454 the following immediate relocations:
24458 9bit ADD/SUB SP word-aligned
24459 10bit ADD PC/SP word-aligned
24461 The type of instruction being processed is encoded in the
24468 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24470 int rd
= (newval
>> 4) & 0xf;
24471 int rs
= newval
& 0xf;
24472 int subtract
= !!(newval
& 0x8000);
24474 /* Check for HI regs, only very restricted cases allowed:
24475 Adjusting SP, and using PC or SP to get an address. */
24476 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24477 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24479 _("invalid Hi register with immediate"));
24481 /* If value is negative, choose the opposite instruction. */
24485 subtract
= !subtract
;
24487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24488 _("immediate value out of range"));
24493 if (value
& ~0x1fc)
24494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24495 _("invalid immediate for stack address calculation"));
24496 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24497 newval
|= value
>> 2;
24499 else if (rs
== REG_PC
|| rs
== REG_SP
)
24501 /* PR gas/18541. If the addition is for a defined symbol
24502 within range of an ADR instruction then accept it. */
24505 && fixP
->fx_addsy
!= NULL
)
24509 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24510 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24511 || S_IS_WEAK (fixP
->fx_addsy
))
24513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24514 _("address calculation needs a strongly defined nearby symbol"));
24518 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24520 /* Round up to the next 4-byte boundary. */
24525 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24530 _("symbol too far away"));
24540 if (subtract
|| value
& ~0x3fc)
24541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24542 _("invalid immediate for address calculation (value = 0x%08lX)"),
24543 (unsigned long) (subtract
? - value
: value
));
24544 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24546 newval
|= value
>> 2;
24551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24552 _("immediate value out of range"));
24553 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24554 newval
|= (rd
<< 8) | value
;
24559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24560 _("immediate value out of range"));
24561 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24562 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24565 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24568 case BFD_RELOC_ARM_THUMB_IMM
:
24569 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24570 if (value
< 0 || value
> 255)
24571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24572 _("invalid immediate: %ld is out of range"),
24575 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24578 case BFD_RELOC_ARM_THUMB_SHIFT
:
24579 /* 5bit shift value (0..32). LSL cannot take 32. */
24580 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24581 temp
= newval
& 0xf800;
24582 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24583 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24584 _("invalid shift value: %ld"), (long) value
);
24585 /* Shifts of zero must be encoded as LSL. */
24587 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24588 /* Shifts of 32 are encoded as zero. */
24589 else if (value
== 32)
24591 newval
|= value
<< 6;
24592 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24595 case BFD_RELOC_VTABLE_INHERIT
:
24596 case BFD_RELOC_VTABLE_ENTRY
:
24600 case BFD_RELOC_ARM_MOVW
:
24601 case BFD_RELOC_ARM_MOVT
:
24602 case BFD_RELOC_ARM_THUMB_MOVW
:
24603 case BFD_RELOC_ARM_THUMB_MOVT
:
24604 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24606 /* REL format relocations are limited to a 16-bit addend. */
24607 if (!fixP
->fx_done
)
24609 if (value
< -0x8000 || value
> 0x7fff)
24610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24611 _("offset out of range"));
24613 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24614 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24619 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24620 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24622 newval
= get_thumb32_insn (buf
);
24623 newval
&= 0xfbf08f00;
24624 newval
|= (value
& 0xf000) << 4;
24625 newval
|= (value
& 0x0800) << 15;
24626 newval
|= (value
& 0x0700) << 4;
24627 newval
|= (value
& 0x00ff);
24628 put_thumb32_insn (buf
, newval
);
24632 newval
= md_chars_to_number (buf
, 4);
24633 newval
&= 0xfff0f000;
24634 newval
|= value
& 0x0fff;
24635 newval
|= (value
& 0xf000) << 4;
24636 md_number_to_chars (buf
, newval
, 4);
24641 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24642 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24643 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24644 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24645 gas_assert (!fixP
->fx_done
);
24648 bfd_boolean is_mov
;
24649 bfd_vma encoded_addend
= value
;
24651 /* Check that addend can be encoded in instruction. */
24652 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24654 _("the offset 0x%08lX is not representable"),
24655 (unsigned long) encoded_addend
);
24657 /* Extract the instruction. */
24658 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24659 is_mov
= (insn
& 0xf800) == 0x2000;
24664 if (!seg
->use_rela_p
)
24665 insn
|= encoded_addend
;
24671 /* Extract the instruction. */
24672 /* Encoding is the following
24677 /* The following conditions must be true :
24682 rd
= (insn
>> 4) & 0xf;
24684 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24686 _("Unable to process relocation for thumb opcode: %lx"),
24687 (unsigned long) insn
);
24689 /* Encode as ADD immediate8 thumb 1 code. */
24690 insn
= 0x3000 | (rd
<< 8);
24692 /* Place the encoded addend into the first 8 bits of the
24694 if (!seg
->use_rela_p
)
24695 insn
|= encoded_addend
;
24698 /* Update the instruction. */
24699 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24703 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24704 case BFD_RELOC_ARM_ALU_PC_G0
:
24705 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24706 case BFD_RELOC_ARM_ALU_PC_G1
:
24707 case BFD_RELOC_ARM_ALU_PC_G2
:
24708 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24709 case BFD_RELOC_ARM_ALU_SB_G0
:
24710 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24711 case BFD_RELOC_ARM_ALU_SB_G1
:
24712 case BFD_RELOC_ARM_ALU_SB_G2
:
24713 gas_assert (!fixP
->fx_done
);
24714 if (!seg
->use_rela_p
)
24717 bfd_vma encoded_addend
;
24718 bfd_vma addend_abs
= llabs (value
);
24720 /* Check that the absolute value of the addend can be
24721 expressed as an 8-bit constant plus a rotation. */
24722 encoded_addend
= encode_arm_immediate (addend_abs
);
24723 if (encoded_addend
== (unsigned int) FAIL
)
24724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24725 _("the offset 0x%08lX is not representable"),
24726 (unsigned long) addend_abs
);
24728 /* Extract the instruction. */
24729 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24731 /* If the addend is positive, use an ADD instruction.
24732 Otherwise use a SUB. Take care not to destroy the S bit. */
24733 insn
&= 0xff1fffff;
24739 /* Place the encoded addend into the first 12 bits of the
24741 insn
&= 0xfffff000;
24742 insn
|= encoded_addend
;
24744 /* Update the instruction. */
24745 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24749 case BFD_RELOC_ARM_LDR_PC_G0
:
24750 case BFD_RELOC_ARM_LDR_PC_G1
:
24751 case BFD_RELOC_ARM_LDR_PC_G2
:
24752 case BFD_RELOC_ARM_LDR_SB_G0
:
24753 case BFD_RELOC_ARM_LDR_SB_G1
:
24754 case BFD_RELOC_ARM_LDR_SB_G2
:
24755 gas_assert (!fixP
->fx_done
);
24756 if (!seg
->use_rela_p
)
24759 bfd_vma addend_abs
= llabs (value
);
24761 /* Check that the absolute value of the addend can be
24762 encoded in 12 bits. */
24763 if (addend_abs
>= 0x1000)
24764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24765 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24766 (unsigned long) addend_abs
);
24768 /* Extract the instruction. */
24769 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24771 /* If the addend is negative, clear bit 23 of the instruction.
24772 Otherwise set it. */
24774 insn
&= ~(1 << 23);
24778 /* Place the absolute value of the addend into the first 12 bits
24779 of the instruction. */
24780 insn
&= 0xfffff000;
24781 insn
|= addend_abs
;
24783 /* Update the instruction. */
24784 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24788 case BFD_RELOC_ARM_LDRS_PC_G0
:
24789 case BFD_RELOC_ARM_LDRS_PC_G1
:
24790 case BFD_RELOC_ARM_LDRS_PC_G2
:
24791 case BFD_RELOC_ARM_LDRS_SB_G0
:
24792 case BFD_RELOC_ARM_LDRS_SB_G1
:
24793 case BFD_RELOC_ARM_LDRS_SB_G2
:
24794 gas_assert (!fixP
->fx_done
);
24795 if (!seg
->use_rela_p
)
24798 bfd_vma addend_abs
= llabs (value
);
24800 /* Check that the absolute value of the addend can be
24801 encoded in 8 bits. */
24802 if (addend_abs
>= 0x100)
24803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24804 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24805 (unsigned long) addend_abs
);
24807 /* Extract the instruction. */
24808 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24810 /* If the addend is negative, clear bit 23 of the instruction.
24811 Otherwise set it. */
24813 insn
&= ~(1 << 23);
24817 /* Place the first four bits of the absolute value of the addend
24818 into the first 4 bits of the instruction, and the remaining
24819 four into bits 8 .. 11. */
24820 insn
&= 0xfffff0f0;
24821 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24823 /* Update the instruction. */
24824 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24828 case BFD_RELOC_ARM_LDC_PC_G0
:
24829 case BFD_RELOC_ARM_LDC_PC_G1
:
24830 case BFD_RELOC_ARM_LDC_PC_G2
:
24831 case BFD_RELOC_ARM_LDC_SB_G0
:
24832 case BFD_RELOC_ARM_LDC_SB_G1
:
24833 case BFD_RELOC_ARM_LDC_SB_G2
:
24834 gas_assert (!fixP
->fx_done
);
24835 if (!seg
->use_rela_p
)
24838 bfd_vma addend_abs
= llabs (value
);
24840 /* Check that the absolute value of the addend is a multiple of
24841 four and, when divided by four, fits in 8 bits. */
24842 if (addend_abs
& 0x3)
24843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24844 _("bad offset 0x%08lX (must be word-aligned)"),
24845 (unsigned long) addend_abs
);
24847 if ((addend_abs
>> 2) > 0xff)
24848 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24849 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24850 (unsigned long) addend_abs
);
24852 /* Extract the instruction. */
24853 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24855 /* If the addend is negative, clear bit 23 of the instruction.
24856 Otherwise set it. */
24858 insn
&= ~(1 << 23);
24862 /* Place the addend (divided by four) into the first eight
24863 bits of the instruction. */
24864 insn
&= 0xfffffff0;
24865 insn
|= addend_abs
>> 2;
24867 /* Update the instruction. */
24868 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24872 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24874 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24875 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24876 && ARM_IS_FUNC (fixP
->fx_addsy
)
24877 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24879 /* Force a relocation for a branch 5 bits wide. */
24882 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
24883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24886 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24888 addressT boff
= value
>> 1;
24890 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24891 newval
|= (boff
<< 7);
24892 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24896 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
24898 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24900 && ARM_IS_FUNC (fixP
->fx_addsy
)
24901 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24905 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
24906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24907 _("branch out of range"));
24909 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24911 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24913 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
24914 addressT diff
= value
- boff
;
24918 newval
|= 1 << 1; /* T bit. */
24920 else if (diff
!= 2)
24922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24923 _("out of range label-relative fixup value"));
24925 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24929 case BFD_RELOC_ARM_THUMB_BF17
:
24931 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24932 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24933 && ARM_IS_FUNC (fixP
->fx_addsy
)
24934 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24936 /* Force a relocation for a branch 17 bits wide. */
24940 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
24941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24944 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24947 addressT immA
, immB
, immC
;
24949 immA
= (value
& 0x0001f000) >> 12;
24950 immB
= (value
& 0x00000ffc) >> 2;
24951 immC
= (value
& 0x00000002) >> 1;
24953 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24954 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24956 newval2
|= (immC
<< 11) | (immB
<< 1);
24957 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24958 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24962 case BFD_RELOC_ARM_THUMB_BF19
:
24964 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24965 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24966 && ARM_IS_FUNC (fixP
->fx_addsy
)
24967 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24969 /* Force a relocation for a branch 19 bits wide. */
24973 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
24974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24977 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24980 addressT immA
, immB
, immC
;
24982 immA
= (value
& 0x0007f000) >> 12;
24983 immB
= (value
& 0x00000ffc) >> 2;
24984 immC
= (value
& 0x00000002) >> 1;
24986 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24987 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24989 newval2
|= (immC
<< 11) | (immB
<< 1);
24990 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24991 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24995 case BFD_RELOC_ARM_THUMB_BF13
:
24997 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24998 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24999 && ARM_IS_FUNC (fixP
->fx_addsy
)
25000 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25002 /* Force a relocation for a branch 13 bits wide. */
25006 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
25007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25013 addressT immA
, immB
, immC
;
25015 immA
= (value
& 0x00001000) >> 12;
25016 immB
= (value
& 0x00000ffc) >> 2;
25017 immC
= (value
& 0x00000002) >> 1;
25019 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25020 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25022 newval2
|= (immC
<< 11) | (immB
<< 1);
25023 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25024 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25028 case BFD_RELOC_ARM_V4BX
:
25029 /* This will need to go in the object file. */
25033 case BFD_RELOC_UNUSED
:
25035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25036 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
25040 /* Translate internal representation of relocation info to BFD target
25044 tc_gen_reloc (asection
*section
, fixS
*fixp
)
25047 bfd_reloc_code_real_type code
;
25049 reloc
= XNEW (arelent
);
25051 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
25052 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
25053 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
25055 if (fixp
->fx_pcrel
)
25057 if (section
->use_rela_p
)
25058 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
25060 fixp
->fx_offset
= reloc
->address
;
25062 reloc
->addend
= fixp
->fx_offset
;
25064 switch (fixp
->fx_r_type
)
25067 if (fixp
->fx_pcrel
)
25069 code
= BFD_RELOC_8_PCREL
;
25072 /* Fall through. */
25075 if (fixp
->fx_pcrel
)
25077 code
= BFD_RELOC_16_PCREL
;
25080 /* Fall through. */
25083 if (fixp
->fx_pcrel
)
25085 code
= BFD_RELOC_32_PCREL
;
25088 /* Fall through. */
25090 case BFD_RELOC_ARM_MOVW
:
25091 if (fixp
->fx_pcrel
)
25093 code
= BFD_RELOC_ARM_MOVW_PCREL
;
25096 /* Fall through. */
25098 case BFD_RELOC_ARM_MOVT
:
25099 if (fixp
->fx_pcrel
)
25101 code
= BFD_RELOC_ARM_MOVT_PCREL
;
25104 /* Fall through. */
25106 case BFD_RELOC_ARM_THUMB_MOVW
:
25107 if (fixp
->fx_pcrel
)
25109 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
25112 /* Fall through. */
25114 case BFD_RELOC_ARM_THUMB_MOVT
:
25115 if (fixp
->fx_pcrel
)
25117 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
25120 /* Fall through. */
25122 case BFD_RELOC_NONE
:
25123 case BFD_RELOC_ARM_PCREL_BRANCH
:
25124 case BFD_RELOC_ARM_PCREL_BLX
:
25125 case BFD_RELOC_RVA
:
25126 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25127 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25128 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25129 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25130 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25131 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25132 case BFD_RELOC_VTABLE_ENTRY
:
25133 case BFD_RELOC_VTABLE_INHERIT
:
25135 case BFD_RELOC_32_SECREL
:
25137 code
= fixp
->fx_r_type
;
25140 case BFD_RELOC_THUMB_PCREL_BLX
:
25142 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
25143 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25146 code
= BFD_RELOC_THUMB_PCREL_BLX
;
25149 case BFD_RELOC_ARM_LITERAL
:
25150 case BFD_RELOC_ARM_HWLITERAL
:
25151 /* If this is called then the a literal has
25152 been referenced across a section boundary. */
25153 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25154 _("literal referenced across section boundary"));
25158 case BFD_RELOC_ARM_TLS_CALL
:
25159 case BFD_RELOC_ARM_THM_TLS_CALL
:
25160 case BFD_RELOC_ARM_TLS_DESCSEQ
:
25161 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
25162 case BFD_RELOC_ARM_GOT32
:
25163 case BFD_RELOC_ARM_GOTOFF
:
25164 case BFD_RELOC_ARM_GOT_PREL
:
25165 case BFD_RELOC_ARM_PLT32
:
25166 case BFD_RELOC_ARM_TARGET1
:
25167 case BFD_RELOC_ARM_ROSEGREL32
:
25168 case BFD_RELOC_ARM_SBREL32
:
25169 case BFD_RELOC_ARM_PREL31
:
25170 case BFD_RELOC_ARM_TARGET2
:
25171 case BFD_RELOC_ARM_TLS_LDO32
:
25172 case BFD_RELOC_ARM_PCREL_CALL
:
25173 case BFD_RELOC_ARM_PCREL_JUMP
:
25174 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
25175 case BFD_RELOC_ARM_ALU_PC_G0
:
25176 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
25177 case BFD_RELOC_ARM_ALU_PC_G1
:
25178 case BFD_RELOC_ARM_ALU_PC_G2
:
25179 case BFD_RELOC_ARM_LDR_PC_G0
:
25180 case BFD_RELOC_ARM_LDR_PC_G1
:
25181 case BFD_RELOC_ARM_LDR_PC_G2
:
25182 case BFD_RELOC_ARM_LDRS_PC_G0
:
25183 case BFD_RELOC_ARM_LDRS_PC_G1
:
25184 case BFD_RELOC_ARM_LDRS_PC_G2
:
25185 case BFD_RELOC_ARM_LDC_PC_G0
:
25186 case BFD_RELOC_ARM_LDC_PC_G1
:
25187 case BFD_RELOC_ARM_LDC_PC_G2
:
25188 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
25189 case BFD_RELOC_ARM_ALU_SB_G0
:
25190 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
25191 case BFD_RELOC_ARM_ALU_SB_G1
:
25192 case BFD_RELOC_ARM_ALU_SB_G2
:
25193 case BFD_RELOC_ARM_LDR_SB_G0
:
25194 case BFD_RELOC_ARM_LDR_SB_G1
:
25195 case BFD_RELOC_ARM_LDR_SB_G2
:
25196 case BFD_RELOC_ARM_LDRS_SB_G0
:
25197 case BFD_RELOC_ARM_LDRS_SB_G1
:
25198 case BFD_RELOC_ARM_LDRS_SB_G2
:
25199 case BFD_RELOC_ARM_LDC_SB_G0
:
25200 case BFD_RELOC_ARM_LDC_SB_G1
:
25201 case BFD_RELOC_ARM_LDC_SB_G2
:
25202 case BFD_RELOC_ARM_V4BX
:
25203 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
25204 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
25205 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
25206 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
25207 case BFD_RELOC_ARM_GOTFUNCDESC
:
25208 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
25209 case BFD_RELOC_ARM_FUNCDESC
:
25210 case BFD_RELOC_ARM_THUMB_BF17
:
25211 case BFD_RELOC_ARM_THUMB_BF19
:
25212 case BFD_RELOC_ARM_THUMB_BF13
:
25213 code
= fixp
->fx_r_type
;
25216 case BFD_RELOC_ARM_TLS_GOTDESC
:
25217 case BFD_RELOC_ARM_TLS_GD32
:
25218 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
25219 case BFD_RELOC_ARM_TLS_LE32
:
25220 case BFD_RELOC_ARM_TLS_IE32
:
25221 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
25222 case BFD_RELOC_ARM_TLS_LDM32
:
25223 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
25224 /* BFD will include the symbol's address in the addend.
25225 But we don't want that, so subtract it out again here. */
25226 if (!S_IS_COMMON (fixp
->fx_addsy
))
25227 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
25228 code
= fixp
->fx_r_type
;
25232 case BFD_RELOC_ARM_IMMEDIATE
:
25233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25234 _("internal relocation (type: IMMEDIATE) not fixed up"));
25237 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25238 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25239 _("ADRL used for a symbol not defined in the same file"));
25242 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25243 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25244 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25245 _("%s used for a symbol not defined in the same file"),
25246 bfd_get_reloc_code_name (fixp
->fx_r_type
));
25249 case BFD_RELOC_ARM_OFFSET_IMM
:
25250 if (section
->use_rela_p
)
25252 code
= fixp
->fx_r_type
;
25256 if (fixp
->fx_addsy
!= NULL
25257 && !S_IS_DEFINED (fixp
->fx_addsy
)
25258 && S_IS_LOCAL (fixp
->fx_addsy
))
25260 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25261 _("undefined local label `%s'"),
25262 S_GET_NAME (fixp
->fx_addsy
));
25266 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25267 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
25274 switch (fixp
->fx_r_type
)
25276 case BFD_RELOC_NONE
: type
= "NONE"; break;
25277 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
25278 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
25279 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
25280 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
25281 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
25282 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
25283 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
25284 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
25285 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
25286 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
25287 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
25288 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
25289 default: type
= _("<unknown>"); break;
25291 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25292 _("cannot represent %s relocation in this object file format"),
25299 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
25301 && fixp
->fx_addsy
== GOT_symbol
)
25303 code
= BFD_RELOC_ARM_GOTPC
;
25304 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
25308 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
25310 if (reloc
->howto
== NULL
)
25312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25313 _("cannot represent %s relocation in this object file format"),
25314 bfd_get_reloc_code_name (code
));
25318 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
25319 vtable entry to be used in the relocation's section offset. */
25320 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25321 reloc
->address
= fixp
->fx_offset
;
25326 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
25329 cons_fix_new_arm (fragS
* frag
,
25333 bfd_reloc_code_real_type reloc
)
25338 FIXME: @@ Should look at CPU word size. */
25342 reloc
= BFD_RELOC_8
;
25345 reloc
= BFD_RELOC_16
;
25349 reloc
= BFD_RELOC_32
;
25352 reloc
= BFD_RELOC_64
;
25357 if (exp
->X_op
== O_secrel
)
25359 exp
->X_op
= O_symbol
;
25360 reloc
= BFD_RELOC_32_SECREL
;
25364 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25367 #if defined (OBJ_COFF)
25369 arm_validate_fix (fixS
* fixP
)
25371 /* If the destination of the branch is a defined symbol which does not have
25372 the THUMB_FUNC attribute, then we must be calling a function which has
25373 the (interfacearm) attribute. We look for the Thumb entry point to that
25374 function and change the branch to refer to that function instead. */
25375 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25376 && fixP
->fx_addsy
!= NULL
25377 && S_IS_DEFINED (fixP
->fx_addsy
)
25378 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25380 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25387 arm_force_relocation (struct fix
* fixp
)
25389 #if defined (OBJ_COFF) && defined (TE_PE)
25390 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25394 /* In case we have a call or a branch to a function in ARM ISA mode from
25395 a thumb function or vice-versa force the relocation. These relocations
25396 are cleared off for some cores that might have blx and simple transformations
25400 switch (fixp
->fx_r_type
)
25402 case BFD_RELOC_ARM_PCREL_JUMP
:
25403 case BFD_RELOC_ARM_PCREL_CALL
:
25404 case BFD_RELOC_THUMB_PCREL_BLX
:
25405 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25409 case BFD_RELOC_ARM_PCREL_BLX
:
25410 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25411 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25412 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25413 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25422 /* Resolve these relocations even if the symbol is extern or weak.
25423 Technically this is probably wrong due to symbol preemption.
25424 In practice these relocations do not have enough range to be useful
25425 at dynamic link time, and some code (e.g. in the Linux kernel)
25426 expects these references to be resolved. */
25427 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25428 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25429 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25430 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25431 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25432 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25433 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25434 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25435 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25436 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25437 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25438 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25439 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25440 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25443 /* Always leave these relocations for the linker. */
25444 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25445 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25446 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25449 /* Always generate relocations against function symbols. */
25450 if (fixp
->fx_r_type
== BFD_RELOC_32
25452 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25455 return generic_force_reloc (fixp
);
25458 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25459 /* Relocations against function names must be left unadjusted,
25460 so that the linker can use this information to generate interworking
25461 stubs. The MIPS version of this function
25462 also prevents relocations that are mips-16 specific, but I do not
25463 know why it does this.
25466 There is one other problem that ought to be addressed here, but
25467 which currently is not: Taking the address of a label (rather
25468 than a function) and then later jumping to that address. Such
25469 addresses also ought to have their bottom bit set (assuming that
25470 they reside in Thumb code), but at the moment they will not. */
25473 arm_fix_adjustable (fixS
* fixP
)
25475 if (fixP
->fx_addsy
== NULL
)
25478 /* Preserve relocations against symbols with function type. */
25479 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25482 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25483 && fixP
->fx_subsy
== NULL
)
25486 /* We need the symbol name for the VTABLE entries. */
25487 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25488 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25491 /* Don't allow symbols to be discarded on GOT related relocs. */
25492 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25493 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25494 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25495 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25496 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25497 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25498 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25499 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25500 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25501 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25502 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25503 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25504 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25505 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25506 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25507 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25508 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25511 /* Similarly for group relocations. */
25512 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25513 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25514 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25517 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25518 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25519 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25520 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25521 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25522 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25523 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25524 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25525 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25528 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25529 offsets, so keep these symbols. */
25530 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25531 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25536 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25540 elf32_arm_target_format (void)
25543 return (target_big_endian
25544 ? "elf32-bigarm-symbian"
25545 : "elf32-littlearm-symbian");
25546 #elif defined (TE_VXWORKS)
25547 return (target_big_endian
25548 ? "elf32-bigarm-vxworks"
25549 : "elf32-littlearm-vxworks");
25550 #elif defined (TE_NACL)
25551 return (target_big_endian
25552 ? "elf32-bigarm-nacl"
25553 : "elf32-littlearm-nacl");
25557 if (target_big_endian
)
25558 return "elf32-bigarm-fdpic";
25560 return "elf32-littlearm-fdpic";
25564 if (target_big_endian
)
25565 return "elf32-bigarm";
25567 return "elf32-littlearm";
25573 armelf_frob_symbol (symbolS
* symp
,
25576 elf_frob_symbol (symp
, puntp
);
25580 /* MD interface: Finalization. */
25585 literal_pool
* pool
;
25587 /* Ensure that all the IT blocks are properly closed. */
25588 check_it_blocks_finished ();
25590 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25592 /* Put it at the end of the relevant section. */
25593 subseg_set (pool
->section
, pool
->sub_section
);
25595 arm_elf_change_section ();
25602 /* Remove any excess mapping symbols generated for alignment frags in
25603 SEC. We may have created a mapping symbol before a zero byte
25604 alignment; remove it if there's a mapping symbol after the
25607 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25608 void *dummy ATTRIBUTE_UNUSED
)
25610 segment_info_type
*seginfo
= seg_info (sec
);
25613 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25616 for (fragp
= seginfo
->frchainP
->frch_root
;
25618 fragp
= fragp
->fr_next
)
25620 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25621 fragS
*next
= fragp
->fr_next
;
25623 /* Variable-sized frags have been converted to fixed size by
25624 this point. But if this was variable-sized to start with,
25625 there will be a fixed-size frag after it. So don't handle
25627 if (sym
== NULL
|| next
== NULL
)
25630 if (S_GET_VALUE (sym
) < next
->fr_address
)
25631 /* Not at the end of this frag. */
25633 know (S_GET_VALUE (sym
) == next
->fr_address
);
25637 if (next
->tc_frag_data
.first_map
!= NULL
)
25639 /* Next frag starts with a mapping symbol. Discard this
25641 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25645 if (next
->fr_next
== NULL
)
25647 /* This mapping symbol is at the end of the section. Discard
25649 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25650 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25654 /* As long as we have empty frags without any mapping symbols,
25656 /* If the next frag is non-empty and does not start with a
25657 mapping symbol, then this mapping symbol is required. */
25658 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25661 next
= next
->fr_next
;
25663 while (next
!= NULL
);
25668 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25672 arm_adjust_symtab (void)
25677 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25679 if (ARM_IS_THUMB (sym
))
25681 if (THUMB_IS_FUNC (sym
))
25683 /* Mark the symbol as a Thumb function. */
25684 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25685 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25686 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25688 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25689 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25691 as_bad (_("%s: unexpected function type: %d"),
25692 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25694 else switch (S_GET_STORAGE_CLASS (sym
))
25697 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25700 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25703 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25711 if (ARM_IS_INTERWORK (sym
))
25712 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25719 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25721 if (ARM_IS_THUMB (sym
))
25723 elf_symbol_type
* elf_sym
;
25725 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25726 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25728 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25729 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25731 /* If it's a .thumb_func, declare it as so,
25732 otherwise tag label as .code 16. */
25733 if (THUMB_IS_FUNC (sym
))
25734 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25735 ST_BRANCH_TO_THUMB
);
25736 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25737 elf_sym
->internal_elf_sym
.st_info
=
25738 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25743 /* Remove any overlapping mapping symbols generated by alignment frags. */
25744 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25745 /* Now do generic ELF adjustments. */
25746 elf_adjust_symtab ();
25750 /* MD interface: Initialization. */
25753 set_constant_flonums (void)
25757 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25758 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25762 /* Auto-select Thumb mode if it's the only available instruction set for the
25763 given architecture. */
25766 autoselect_thumb_from_cpu_variant (void)
25768 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25769 opcode_select (16);
25778 if ( (arm_ops_hsh
= hash_new ()) == NULL
25779 || (arm_cond_hsh
= hash_new ()) == NULL
25780 || (arm_shift_hsh
= hash_new ()) == NULL
25781 || (arm_psr_hsh
= hash_new ()) == NULL
25782 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25783 || (arm_reg_hsh
= hash_new ()) == NULL
25784 || (arm_reloc_hsh
= hash_new ()) == NULL
25785 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25786 as_fatal (_("virtual memory exhausted"));
25788 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25789 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25790 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25791 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25792 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25793 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25794 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25795 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25796 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25797 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25798 (void *) (v7m_psrs
+ i
));
25799 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25800 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25802 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25804 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25805 (void *) (barrier_opt_names
+ i
));
25807 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25809 struct reloc_entry
* entry
= reloc_names
+ i
;
25811 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25812 /* This makes encode_branch() use the EABI versions of this relocation. */
25813 entry
->reloc
= BFD_RELOC_UNUSED
;
25815 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25819 set_constant_flonums ();
25821 /* Set the cpu variant based on the command-line options. We prefer
25822 -mcpu= over -march= if both are set (as for GCC); and we prefer
25823 -mfpu= over any other way of setting the floating point unit.
25824 Use of legacy options with new options are faulted. */
25827 if (mcpu_cpu_opt
|| march_cpu_opt
)
25828 as_bad (_("use of old and new-style options to set CPU type"));
25830 selected_arch
= *legacy_cpu
;
25832 else if (mcpu_cpu_opt
)
25834 selected_arch
= *mcpu_cpu_opt
;
25835 selected_ext
= *mcpu_ext_opt
;
25837 else if (march_cpu_opt
)
25839 selected_arch
= *march_cpu_opt
;
25840 selected_ext
= *march_ext_opt
;
25842 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25847 as_bad (_("use of old and new-style options to set FPU type"));
25849 selected_fpu
= *legacy_fpu
;
25852 selected_fpu
= *mfpu_opt
;
25855 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25856 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25857 /* Some environments specify a default FPU. If they don't, infer it
25858 from the processor. */
25860 selected_fpu
= *mcpu_fpu_opt
;
25861 else if (march_fpu_opt
)
25862 selected_fpu
= *march_fpu_opt
;
25864 selected_fpu
= fpu_default
;
25868 if (ARM_FEATURE_ZERO (selected_fpu
))
25870 if (!no_cpu_selected ())
25871 selected_fpu
= fpu_default
;
25873 selected_fpu
= fpu_arch_fpa
;
25877 if (ARM_FEATURE_ZERO (selected_arch
))
25879 selected_arch
= cpu_default
;
25880 selected_cpu
= selected_arch
;
25882 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25884 /* Autodection of feature mode: allow all features in cpu_variant but leave
25885 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25886 after all instruction have been processed and we can decide what CPU
25887 should be selected. */
25888 if (ARM_FEATURE_ZERO (selected_arch
))
25889 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25891 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25894 autoselect_thumb_from_cpu_variant ();
25896 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25898 #if defined OBJ_COFF || defined OBJ_ELF
25900 unsigned int flags
= 0;
25902 #if defined OBJ_ELF
25903 flags
= meabi_flags
;
25905 switch (meabi_flags
)
25907 case EF_ARM_EABI_UNKNOWN
:
25909 /* Set the flags in the private structure. */
25910 if (uses_apcs_26
) flags
|= F_APCS26
;
25911 if (support_interwork
) flags
|= F_INTERWORK
;
25912 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25913 if (pic_code
) flags
|= F_PIC
;
25914 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25915 flags
|= F_SOFT_FLOAT
;
25917 switch (mfloat_abi_opt
)
25919 case ARM_FLOAT_ABI_SOFT
:
25920 case ARM_FLOAT_ABI_SOFTFP
:
25921 flags
|= F_SOFT_FLOAT
;
25924 case ARM_FLOAT_ABI_HARD
:
25925 if (flags
& F_SOFT_FLOAT
)
25926 as_bad (_("hard-float conflicts with specified fpu"));
25930 /* Using pure-endian doubles (even if soft-float). */
25931 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25932 flags
|= F_VFP_FLOAT
;
25934 #if defined OBJ_ELF
25935 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25936 flags
|= EF_ARM_MAVERICK_FLOAT
;
25939 case EF_ARM_EABI_VER4
:
25940 case EF_ARM_EABI_VER5
:
25941 /* No additional flags to set. */
25948 bfd_set_private_flags (stdoutput
, flags
);
25950 /* We have run out flags in the COFF header to encode the
25951 status of ATPCS support, so instead we create a dummy,
25952 empty, debug section called .arm.atpcs. */
25957 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25961 bfd_set_section_flags
25962 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25963 bfd_set_section_size (stdoutput
, sec
, 0);
25964 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25970 /* Record the CPU type as well. */
25971 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25972 mach
= bfd_mach_arm_iWMMXt2
;
25973 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25974 mach
= bfd_mach_arm_iWMMXt
;
25975 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25976 mach
= bfd_mach_arm_XScale
;
25977 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25978 mach
= bfd_mach_arm_ep9312
;
25979 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25980 mach
= bfd_mach_arm_5TE
;
25981 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25983 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25984 mach
= bfd_mach_arm_5T
;
25986 mach
= bfd_mach_arm_5
;
25988 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25990 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25991 mach
= bfd_mach_arm_4T
;
25993 mach
= bfd_mach_arm_4
;
25995 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25996 mach
= bfd_mach_arm_3M
;
25997 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25998 mach
= bfd_mach_arm_3
;
25999 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
26000 mach
= bfd_mach_arm_2a
;
26001 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
26002 mach
= bfd_mach_arm_2
;
26004 mach
= bfd_mach_arm_unknown
;
26006 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
26009 /* Command line processing. */
26012 Invocation line includes a switch not recognized by the base assembler.
26013 See if it's a processor-specific option.
26015 This routine is somewhat complicated by the need for backwards
26016 compatibility (since older releases of gcc can't be changed).
26017 The new options try to make the interface as compatible as
26020 New options (supported) are:
26022 -mcpu=<cpu name> Assemble for selected processor
26023 -march=<architecture name> Assemble for selected architecture
26024 -mfpu=<fpu architecture> Assemble for selected FPU.
26025 -EB/-mbig-endian Big-endian
26026 -EL/-mlittle-endian Little-endian
26027 -k Generate PIC code
26028 -mthumb Start in Thumb mode
26029 -mthumb-interwork Code supports ARM/Thumb interworking
26031 -m[no-]warn-deprecated Warn about deprecated features
26032 -m[no-]warn-syms Warn when symbols match instructions
26034 For now we will also provide support for:
26036 -mapcs-32 32-bit Program counter
26037 -mapcs-26 26-bit Program counter
26038 -macps-float Floats passed in FP registers
26039 -mapcs-reentrant Reentrant code
26041 (sometime these will probably be replaced with -mapcs=<list of options>
26042 and -matpcs=<list of options>)
26044 The remaining options are only supported for back-wards compatibility.
26045 Cpu variants, the arm part is optional:
26046 -m[arm]1 Currently not supported.
26047 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
26048 -m[arm]3 Arm 3 processor
26049 -m[arm]6[xx], Arm 6 processors
26050 -m[arm]7[xx][t][[d]m] Arm 7 processors
26051 -m[arm]8[10] Arm 8 processors
26052 -m[arm]9[20][tdmi] Arm 9 processors
26053 -mstrongarm[110[0]] StrongARM processors
26054 -mxscale XScale processors
26055 -m[arm]v[2345[t[e]]] Arm architectures
26056 -mall All (except the ARM1)
26058 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
26059 -mfpe-old (No float load/store multiples)
26060 -mvfpxd VFP Single precision
26062 -mno-fpu Disable all floating point instructions
26064 The following CPU names are recognized:
26065 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
26066 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
26067 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
26068 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
26069 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
26070 arm10t arm10e, arm1020t, arm1020e, arm10200e,
26071 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
26075 const char * md_shortopts
= "m:k";
26077 #ifdef ARM_BI_ENDIAN
26078 #define OPTION_EB (OPTION_MD_BASE + 0)
26079 #define OPTION_EL (OPTION_MD_BASE + 1)
26081 #if TARGET_BYTES_BIG_ENDIAN
26082 #define OPTION_EB (OPTION_MD_BASE + 0)
26084 #define OPTION_EL (OPTION_MD_BASE + 1)
26087 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
26088 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
26090 struct option md_longopts
[] =
26093 {"EB", no_argument
, NULL
, OPTION_EB
},
26096 {"EL", no_argument
, NULL
, OPTION_EL
},
26098 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
26100 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
26102 {NULL
, no_argument
, NULL
, 0}
26105 size_t md_longopts_size
= sizeof (md_longopts
);
26107 struct arm_option_table
26109 const char * option
; /* Option name to match. */
26110 const char * help
; /* Help information. */
26111 int * var
; /* Variable to change. */
26112 int value
; /* What to change it to. */
26113 const char * deprecated
; /* If non-null, print this message. */
26116 struct arm_option_table arm_opts
[] =
26118 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
26119 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
26120 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
26121 &support_interwork
, 1, NULL
},
26122 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
26123 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
26124 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
26126 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
26127 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
26128 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
26129 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
26132 /* These are recognized by the assembler, but have no affect on code. */
26133 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
26134 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
26136 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
26137 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
26138 &warn_on_deprecated
, 0, NULL
},
26139 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
26140 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
26141 {NULL
, NULL
, NULL
, 0, NULL
}
26144 struct arm_legacy_option_table
26146 const char * option
; /* Option name to match. */
26147 const arm_feature_set
** var
; /* Variable to change. */
26148 const arm_feature_set value
; /* What to change it to. */
26149 const char * deprecated
; /* If non-null, print this message. */
26152 const struct arm_legacy_option_table arm_legacy_opts
[] =
26154 /* DON'T add any new processors to this list -- we want the whole list
26155 to go away... Add them to the processors table instead. */
26156 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26157 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26158 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26159 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26160 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26161 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26162 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26163 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26164 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26165 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26166 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26167 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26168 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26169 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26170 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26171 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26172 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26173 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26174 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26175 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26176 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26177 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26178 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26179 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26180 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26181 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26182 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26183 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26184 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26185 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26186 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26187 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26188 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26189 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26190 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26191 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26192 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26193 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26194 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26195 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26196 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26197 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26198 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26199 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26200 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26201 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26202 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26203 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26204 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26205 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26206 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26207 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26208 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26209 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26210 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26211 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26212 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26213 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26214 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26215 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26216 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26217 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26218 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26219 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26220 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26221 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26222 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26223 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26224 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
26225 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
26226 N_("use -mcpu=strongarm110")},
26227 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
26228 N_("use -mcpu=strongarm1100")},
26229 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
26230 N_("use -mcpu=strongarm1110")},
26231 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
26232 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
26233 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
26235 /* Architecture variants -- don't add any more to this list either. */
26236 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26237 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26238 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26239 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26240 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26241 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26242 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26243 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26244 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26245 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26246 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26247 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26248 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26249 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26250 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26251 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26252 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26253 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26255 /* Floating point variants -- don't add any more to this list either. */
26256 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
26257 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
26258 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
26259 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
26260 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
26262 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
26265 struct arm_cpu_option_table
26269 const arm_feature_set value
;
26270 const arm_feature_set ext
;
26271 /* For some CPUs we assume an FPU unless the user explicitly sets
26273 const arm_feature_set default_fpu
;
26274 /* The canonical name of the CPU, or NULL to use NAME converted to upper
26276 const char * canonical_name
;
26279 /* This list should, at a minimum, contain all the cpu names
26280 recognized by GCC. */
26281 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
26283 static const struct arm_cpu_option_table arm_cpus
[] =
26285 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
26288 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
26291 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
26294 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
26297 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
26300 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
26303 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
26306 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
26309 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
26312 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
26315 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
26318 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
26321 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
26324 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
26327 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
26330 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
26333 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
26336 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
26339 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
26342 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
26345 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
26348 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
26351 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
26354 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
26357 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
26360 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26363 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26366 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26369 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26372 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26375 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26378 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26381 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26384 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26387 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26390 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26393 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26396 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26399 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26402 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26405 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26408 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26411 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26414 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26417 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26420 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26424 /* For V5 or later processors we default to using VFP; but the user
26425 should really set the FPU type explicitly. */
26426 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26429 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26432 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26435 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26438 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26441 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26444 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26447 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26450 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26453 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26456 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26459 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26462 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26465 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26468 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26471 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26474 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26477 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26480 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26483 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26486 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26489 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26492 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26495 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26498 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26501 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26504 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26507 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26510 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26513 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26516 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26519 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26522 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26525 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26528 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26531 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26534 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26535 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26537 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26539 FPU_ARCH_NEON_VFP_V4
),
26540 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26541 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26542 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26543 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26544 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26545 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26546 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26548 FPU_ARCH_NEON_VFP_V4
),
26549 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26551 FPU_ARCH_NEON_VFP_V4
),
26552 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26554 FPU_ARCH_NEON_VFP_V4
),
26555 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26556 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26557 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26558 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26559 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26560 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26561 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26562 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26563 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26564 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26565 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26566 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26567 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26568 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26569 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26570 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26571 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26572 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26573 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26574 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26575 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26576 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26577 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26578 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26579 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26580 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26581 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26582 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26583 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26584 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26585 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26588 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26590 FPU_ARCH_VFP_V3D16
),
26591 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26592 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26594 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26595 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26596 FPU_ARCH_VFP_V3D16
),
26597 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26598 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26599 FPU_ARCH_VFP_V3D16
),
26600 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26601 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26602 FPU_ARCH_NEON_VFP_ARMV8
),
26603 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26604 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26606 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26609 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26612 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26615 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26618 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26621 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26624 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26627 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26628 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26629 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26630 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26631 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26632 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26633 /* ??? XSCALE is really an architecture. */
26634 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26638 /* ??? iwmmxt is not a processor. */
26639 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26642 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26645 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26650 ARM_CPU_OPT ("ep9312", "ARM920T",
26651 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26652 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26654 /* Marvell processors. */
26655 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26656 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26657 FPU_ARCH_VFP_V3D16
),
26658 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26659 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26660 FPU_ARCH_NEON_VFP_V4
),
26662 /* APM X-Gene family. */
26663 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26665 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26666 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26667 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26668 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26670 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26674 struct arm_ext_table
26678 const arm_feature_set merge
;
26679 const arm_feature_set clear
;
26682 struct arm_arch_option_table
26686 const arm_feature_set value
;
26687 const arm_feature_set default_fpu
;
26688 const struct arm_ext_table
* ext_table
;
26691 /* Used to add support for +E and +noE extension. */
26692 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26693 /* Used to add support for a +E extension. */
26694 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26695 /* Used to add support for a +noE extension. */
26696 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26698 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26699 ~0 & ~FPU_ENDIAN_PURE)
26701 static const struct arm_ext_table armv5te_ext_table
[] =
26703 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26704 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26707 static const struct arm_ext_table armv7_ext_table
[] =
26709 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26710 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26713 static const struct arm_ext_table armv7ve_ext_table
[] =
26715 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26716 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26717 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26718 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26719 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26720 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26721 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26723 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26724 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26726 /* Aliases for +simd. */
26727 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26729 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26730 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26731 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26733 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26736 static const struct arm_ext_table armv7a_ext_table
[] =
26738 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26739 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26740 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26741 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26742 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26743 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
26744 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26746 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
26747 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26749 /* Aliases for +simd. */
26750 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26751 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26753 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26754 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26756 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
26757 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
26758 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26761 static const struct arm_ext_table armv7r_ext_table
[] =
26763 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
26764 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
26765 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26766 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26767 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
26768 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26769 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26770 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
26771 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26774 static const struct arm_ext_table armv7em_ext_table
[] =
26776 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
26777 /* Alias for +fp, used to be known as fpv4-sp-d16. */
26778 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
26779 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
26780 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26781 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
26782 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26785 static const struct arm_ext_table armv8a_ext_table
[] =
26787 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26788 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26789 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26790 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26792 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26793 should use the +simd option to turn on FP. */
26794 ARM_REMOVE ("fp", ALL_FP
),
26795 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26796 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26797 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26801 static const struct arm_ext_table armv81a_ext_table
[] =
26803 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26804 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26805 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26807 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26808 should use the +simd option to turn on FP. */
26809 ARM_REMOVE ("fp", ALL_FP
),
26810 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26811 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26812 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26815 static const struct arm_ext_table armv82a_ext_table
[] =
26817 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26818 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
26819 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
26820 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26821 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26822 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26824 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26825 should use the +simd option to turn on FP. */
26826 ARM_REMOVE ("fp", ALL_FP
),
26827 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26828 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26829 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26832 static const struct arm_ext_table armv84a_ext_table
[] =
26834 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26835 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26836 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26837 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26839 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26840 should use the +simd option to turn on FP. */
26841 ARM_REMOVE ("fp", ALL_FP
),
26842 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26843 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26844 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26847 static const struct arm_ext_table armv85a_ext_table
[] =
26849 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26850 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26851 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26852 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26854 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26855 should use the +simd option to turn on FP. */
26856 ARM_REMOVE ("fp", ALL_FP
),
26857 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26860 static const struct arm_ext_table armv8m_main_ext_table
[] =
26862 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26863 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26864 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
26865 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26866 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26869 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
26871 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26872 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26874 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26875 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
26878 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26879 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
26880 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26883 static const struct arm_ext_table armv8r_ext_table
[] =
26885 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26886 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26887 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26888 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26889 ARM_REMOVE ("fp", ALL_FP
),
26890 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
26891 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26894 /* This list should, at a minimum, contain all the architecture names
26895 recognized by GCC. */
26896 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
26897 #define ARM_ARCH_OPT2(N, V, DF, ext) \
26898 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
26900 static const struct arm_arch_option_table arm_archs
[] =
26902 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26903 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26904 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26905 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26906 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26907 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26908 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26909 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26910 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26911 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26912 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26913 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26914 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26915 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26916 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
26917 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
26918 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
26919 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26920 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26921 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
26922 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
26923 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26924 kept to preserve existing behaviour. */
26925 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26926 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26927 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
26928 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
26929 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
26930 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26931 kept to preserve existing behaviour. */
26932 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26933 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26934 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26935 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26936 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
26937 /* The official spelling of the ARMv7 profile variants is the dashed form.
26938 Accept the non-dashed form for compatibility with old toolchains. */
26939 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26940 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
26941 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26942 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26943 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26944 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26945 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26946 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
26947 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26948 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
26950 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
26952 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
26953 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
26954 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
26955 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
26956 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
26957 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
26958 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
26959 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26960 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26961 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
26962 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26964 #undef ARM_ARCH_OPT
26966 /* ISA extensions in the co-processor and main instruction set space. */
26968 struct arm_option_extension_value_table
26972 const arm_feature_set merge_value
;
26973 const arm_feature_set clear_value
;
26974 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26975 indicates that an extension is available for all architectures while
26976 ARM_ANY marks an empty entry. */
26977 const arm_feature_set allowed_archs
[2];
26980 /* The following table must be in alphabetical order with a NULL last entry. */
26982 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26983 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26985 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
26986 use the context sensitive approach using arm_ext_table's. */
26987 static const struct arm_option_extension_value_table arm_extensions
[] =
26989 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26990 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26991 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26992 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26993 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26994 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26995 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26997 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26998 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26999 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
27000 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
27001 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27002 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27003 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27005 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27006 | ARM_EXT2_FP16_FML
),
27007 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27008 | ARM_EXT2_FP16_FML
),
27010 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27011 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27012 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27013 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27014 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
27015 Thumb divide instruction. Due to this having the same name as the
27016 previous entry, this will be ignored when doing command-line parsing and
27017 only considered by build attribute selection code. */
27018 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27019 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27020 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
27021 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
27022 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
27023 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
27024 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
27025 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
27026 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
27027 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27028 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27029 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27030 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27031 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27032 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27033 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
27034 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
27035 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
27036 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27037 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27038 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27040 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
27041 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
27042 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27043 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
27044 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
27045 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27046 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27047 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27049 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27050 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27051 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
27052 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27053 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
27054 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
27055 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27056 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
27058 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
27059 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27060 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
27061 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
27062 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
27066 /* ISA floating-point and Advanced SIMD extensions. */
27067 struct arm_option_fpu_value_table
27070 const arm_feature_set value
;
27073 /* This list should, at a minimum, contain all the fpu names
27074 recognized by GCC. */
27075 static const struct arm_option_fpu_value_table arm_fpus
[] =
27077 {"softfpa", FPU_NONE
},
27078 {"fpe", FPU_ARCH_FPE
},
27079 {"fpe2", FPU_ARCH_FPE
},
27080 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
27081 {"fpa", FPU_ARCH_FPA
},
27082 {"fpa10", FPU_ARCH_FPA
},
27083 {"fpa11", FPU_ARCH_FPA
},
27084 {"arm7500fe", FPU_ARCH_FPA
},
27085 {"softvfp", FPU_ARCH_VFP
},
27086 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
27087 {"vfp", FPU_ARCH_VFP_V2
},
27088 {"vfp9", FPU_ARCH_VFP_V2
},
27089 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
27090 {"vfp10", FPU_ARCH_VFP_V2
},
27091 {"vfp10-r0", FPU_ARCH_VFP_V1
},
27092 {"vfpxd", FPU_ARCH_VFP_V1xD
},
27093 {"vfpv2", FPU_ARCH_VFP_V2
},
27094 {"vfpv3", FPU_ARCH_VFP_V3
},
27095 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
27096 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
27097 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
27098 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
27099 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
27100 {"arm1020t", FPU_ARCH_VFP_V1
},
27101 {"arm1020e", FPU_ARCH_VFP_V2
},
27102 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
27103 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
27104 {"maverick", FPU_ARCH_MAVERICK
},
27105 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27106 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27107 {"neon-fp16", FPU_ARCH_NEON_FP16
},
27108 {"vfpv4", FPU_ARCH_VFP_V4
},
27109 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
27110 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
27111 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
27112 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
27113 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
27114 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
27115 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
27116 {"crypto-neon-fp-armv8",
27117 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
27118 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
27119 {"crypto-neon-fp-armv8.1",
27120 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
27121 {NULL
, ARM_ARCH_NONE
}
27124 struct arm_option_value_table
27130 static const struct arm_option_value_table arm_float_abis
[] =
27132 {"hard", ARM_FLOAT_ABI_HARD
},
27133 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
27134 {"soft", ARM_FLOAT_ABI_SOFT
},
27139 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
27140 static const struct arm_option_value_table arm_eabis
[] =
27142 {"gnu", EF_ARM_EABI_UNKNOWN
},
27143 {"4", EF_ARM_EABI_VER4
},
27144 {"5", EF_ARM_EABI_VER5
},
27149 struct arm_long_option_table
27151 const char * option
; /* Substring to match. */
27152 const char * help
; /* Help information. */
27153 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
27154 const char * deprecated
; /* If non-null, print this message. */
27158 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
27159 arm_feature_set
*ext_set
,
27160 const struct arm_ext_table
*ext_table
)
27162 /* We insist on extensions being specified in alphabetical order, and with
27163 extensions being added before being removed. We achieve this by having
27164 the global ARM_EXTENSIONS table in alphabetical order, and using the
27165 ADDING_VALUE variable to indicate whether we are adding an extension (1)
27166 or removing it (0) and only allowing it to change in the order
27168 const struct arm_option_extension_value_table
* opt
= NULL
;
27169 const arm_feature_set arm_any
= ARM_ANY
;
27170 int adding_value
= -1;
27172 while (str
!= NULL
&& *str
!= 0)
27179 as_bad (_("invalid architectural extension"));
27184 ext
= strchr (str
, '+');
27189 len
= strlen (str
);
27191 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
27193 if (adding_value
!= 0)
27196 opt
= arm_extensions
;
27204 if (adding_value
== -1)
27207 opt
= arm_extensions
;
27209 else if (adding_value
!= 1)
27211 as_bad (_("must specify extensions to add before specifying "
27212 "those to remove"));
27219 as_bad (_("missing architectural extension"));
27223 gas_assert (adding_value
!= -1);
27224 gas_assert (opt
!= NULL
);
27226 if (ext_table
!= NULL
)
27228 const struct arm_ext_table
* ext_opt
= ext_table
;
27229 bfd_boolean found
= FALSE
;
27230 for (; ext_opt
->name
!= NULL
; ext_opt
++)
27231 if (ext_opt
->name_len
== len
27232 && strncmp (ext_opt
->name
, str
, len
) == 0)
27236 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
27237 /* TODO: Option not supported. When we remove the
27238 legacy table this case should error out. */
27241 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
27245 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
27246 /* TODO: Option not supported. When we remove the
27247 legacy table this case should error out. */
27249 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
27261 /* Scan over the options table trying to find an exact match. */
27262 for (; opt
->name
!= NULL
; opt
++)
27263 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27265 int i
, nb_allowed_archs
=
27266 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27267 /* Check we can apply the extension to this architecture. */
27268 for (i
= 0; i
< nb_allowed_archs
; i
++)
27271 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27273 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
27276 if (i
== nb_allowed_archs
)
27278 as_bad (_("extension does not apply to the base architecture"));
27282 /* Add or remove the extension. */
27284 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
27286 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
27288 /* Allowing Thumb division instructions for ARMv7 in autodetection
27289 rely on this break so that duplicate extensions (extensions
27290 with the same name as a previous extension in the list) are not
27291 considered for command-line parsing. */
27295 if (opt
->name
== NULL
)
27297 /* Did we fail to find an extension because it wasn't specified in
27298 alphabetical order, or because it does not exist? */
27300 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27301 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27304 if (opt
->name
== NULL
)
27305 as_bad (_("unknown architectural extension `%s'"), str
);
27307 as_bad (_("architectural extensions must be specified in "
27308 "alphabetical order"));
27314 /* We should skip the extension we've just matched the next time
27326 arm_parse_cpu (const char *str
)
27328 const struct arm_cpu_option_table
*opt
;
27329 const char *ext
= strchr (str
, '+');
27335 len
= strlen (str
);
27339 as_bad (_("missing cpu name `%s'"), str
);
27343 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
27344 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27346 mcpu_cpu_opt
= &opt
->value
;
27347 if (mcpu_ext_opt
== NULL
)
27348 mcpu_ext_opt
= XNEW (arm_feature_set
);
27349 *mcpu_ext_opt
= opt
->ext
;
27350 mcpu_fpu_opt
= &opt
->default_fpu
;
27351 if (opt
->canonical_name
)
27353 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
27354 strcpy (selected_cpu_name
, opt
->canonical_name
);
27360 if (len
>= sizeof selected_cpu_name
)
27361 len
= (sizeof selected_cpu_name
) - 1;
27363 for (i
= 0; i
< len
; i
++)
27364 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27365 selected_cpu_name
[i
] = 0;
27369 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
27374 as_bad (_("unknown cpu `%s'"), str
);
27379 arm_parse_arch (const char *str
)
27381 const struct arm_arch_option_table
*opt
;
27382 const char *ext
= strchr (str
, '+');
27388 len
= strlen (str
);
27392 as_bad (_("missing architecture name `%s'"), str
);
27396 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27397 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27399 march_cpu_opt
= &opt
->value
;
27400 if (march_ext_opt
== NULL
)
27401 march_ext_opt
= XNEW (arm_feature_set
);
27402 *march_ext_opt
= arm_arch_none
;
27403 march_fpu_opt
= &opt
->default_fpu
;
27404 strcpy (selected_cpu_name
, opt
->name
);
27407 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27413 as_bad (_("unknown architecture `%s'\n"), str
);
27418 arm_parse_fpu (const char * str
)
27420 const struct arm_option_fpu_value_table
* opt
;
27422 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27423 if (streq (opt
->name
, str
))
27425 mfpu_opt
= &opt
->value
;
27429 as_bad (_("unknown floating point format `%s'\n"), str
);
27434 arm_parse_float_abi (const char * str
)
27436 const struct arm_option_value_table
* opt
;
27438 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27439 if (streq (opt
->name
, str
))
27441 mfloat_abi_opt
= opt
->value
;
27445 as_bad (_("unknown floating point abi `%s'\n"), str
);
27451 arm_parse_eabi (const char * str
)
27453 const struct arm_option_value_table
*opt
;
27455 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27456 if (streq (opt
->name
, str
))
27458 meabi_flags
= opt
->value
;
27461 as_bad (_("unknown EABI `%s'\n"), str
);
27467 arm_parse_it_mode (const char * str
)
27469 bfd_boolean ret
= TRUE
;
27471 if (streq ("arm", str
))
27472 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27473 else if (streq ("thumb", str
))
27474 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27475 else if (streq ("always", str
))
27476 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27477 else if (streq ("never", str
))
27478 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27481 as_bad (_("unknown implicit IT mode `%s', should be "\
27482 "arm, thumb, always, or never."), str
);
27490 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27492 codecomposer_syntax
= TRUE
;
27493 arm_comment_chars
[0] = ';';
27494 arm_line_separator_chars
[0] = 0;
27498 struct arm_long_option_table arm_long_opts
[] =
27500 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27501 arm_parse_cpu
, NULL
},
27502 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27503 arm_parse_arch
, NULL
},
27504 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27505 arm_parse_fpu
, NULL
},
27506 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27507 arm_parse_float_abi
, NULL
},
27509 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27510 arm_parse_eabi
, NULL
},
27512 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27513 arm_parse_it_mode
, NULL
},
27514 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27515 arm_ccs_mode
, NULL
},
27516 {NULL
, NULL
, 0, NULL
}
27520 md_parse_option (int c
, const char * arg
)
27522 struct arm_option_table
*opt
;
27523 const struct arm_legacy_option_table
*fopt
;
27524 struct arm_long_option_table
*lopt
;
27530 target_big_endian
= 1;
27536 target_big_endian
= 0;
27540 case OPTION_FIX_V4BX
:
27548 #endif /* OBJ_ELF */
27551 /* Listing option. Just ignore these, we don't support additional
27556 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27558 if (c
== opt
->option
[0]
27559 && ((arg
== NULL
&& opt
->option
[1] == 0)
27560 || streq (arg
, opt
->option
+ 1)))
27562 /* If the option is deprecated, tell the user. */
27563 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27564 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27565 arg
? arg
: "", _(opt
->deprecated
));
27567 if (opt
->var
!= NULL
)
27568 *opt
->var
= opt
->value
;
27574 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27576 if (c
== fopt
->option
[0]
27577 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27578 || streq (arg
, fopt
->option
+ 1)))
27580 /* If the option is deprecated, tell the user. */
27581 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27582 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27583 arg
? arg
: "", _(fopt
->deprecated
));
27585 if (fopt
->var
!= NULL
)
27586 *fopt
->var
= &fopt
->value
;
27592 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27594 /* These options are expected to have an argument. */
27595 if (c
== lopt
->option
[0]
27597 && strncmp (arg
, lopt
->option
+ 1,
27598 strlen (lopt
->option
+ 1)) == 0)
27600 /* If the option is deprecated, tell the user. */
27601 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27602 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27603 _(lopt
->deprecated
));
27605 /* Call the sup-option parser. */
27606 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27617 md_show_usage (FILE * fp
)
27619 struct arm_option_table
*opt
;
27620 struct arm_long_option_table
*lopt
;
27622 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27624 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27625 if (opt
->help
!= NULL
)
27626 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27628 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27629 if (lopt
->help
!= NULL
)
27630 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27634 -EB assemble code for a big-endian cpu\n"));
27639 -EL assemble code for a little-endian cpu\n"));
27643 --fix-v4bx Allow BX in ARMv4 code\n"));
27647 --fdpic generate an FDPIC object file\n"));
27648 #endif /* OBJ_ELF */
27656 arm_feature_set flags
;
27657 } cpu_arch_ver_table
;
27659 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27660 chronologically for architectures, with an exception for ARMv6-M and
27661 ARMv6S-M due to legacy reasons. No new architecture should have a
27662 special case. This allows for build attribute selection results to be
27663 stable when new architectures are added. */
27664 static const cpu_arch_ver_table cpu_arch_ver
[] =
27666 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27667 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27668 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27669 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27670 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27671 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27672 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27673 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27674 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27675 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27676 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27677 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27678 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27679 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27680 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27681 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27682 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27683 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27684 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27685 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27686 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27687 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27688 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27689 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27691 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27692 always selected build attributes to match those of ARMv6-M
27693 (resp. ARMv6S-M). However, due to these architectures being a strict
27694 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27695 would be selected when fully respecting chronology of architectures.
27696 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27697 move them before ARMv7 architectures. */
27698 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27699 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27701 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27702 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27703 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27704 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27705 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27706 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27707 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27708 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27709 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27710 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27711 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27712 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27713 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27714 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27715 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27716 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27717 {-1, ARM_ARCH_NONE
}
27720 /* Set an attribute if it has not already been set by the user. */
27723 aeabi_set_attribute_int (int tag
, int value
)
27726 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27727 || !attributes_set_explicitly
[tag
])
27728 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27732 aeabi_set_attribute_string (int tag
, const char *value
)
27735 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27736 || !attributes_set_explicitly
[tag
])
27737 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27740 /* Return whether features in the *NEEDED feature set are available via
27741 extensions for the architecture whose feature set is *ARCH_FSET. */
27744 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27745 const arm_feature_set
*needed
)
27747 int i
, nb_allowed_archs
;
27748 arm_feature_set ext_fset
;
27749 const struct arm_option_extension_value_table
*opt
;
27751 ext_fset
= arm_arch_none
;
27752 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27754 /* Extension does not provide any feature we need. */
27755 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27759 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27760 for (i
= 0; i
< nb_allowed_archs
; i
++)
27763 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27766 /* Extension is available, add it. */
27767 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27768 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27772 /* Can we enable all features in *needed? */
27773 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27776 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27777 a given architecture feature set *ARCH_EXT_FSET including extension feature
27778 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27779 - if true, check for an exact match of the architecture modulo extensions;
27780 - otherwise, select build attribute value of the first superset
27781 architecture released so that results remains stable when new architectures
27783 For -march/-mcpu=all the build attribute value of the most featureful
27784 architecture is returned. Tag_CPU_arch_profile result is returned in
27788 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27789 const arm_feature_set
*ext_fset
,
27790 char *profile
, int exact_match
)
27792 arm_feature_set arch_fset
;
27793 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27795 /* Select most featureful architecture with all its extensions if building
27796 for -march=all as the feature sets used to set build attributes. */
27797 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27799 /* Force revisiting of decision for each new architecture. */
27800 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27802 return TAG_CPU_ARCH_V8
;
27805 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27807 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27809 arm_feature_set known_arch_fset
;
27811 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27814 /* Base architecture match user-specified architecture and
27815 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27816 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27821 /* Base architecture match user-specified architecture only
27822 (eg. ARMv6-M in the same case as above). Record it in case we
27823 find a match with above condition. */
27824 else if (p_ver_ret
== NULL
27825 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27831 /* Architecture has all features wanted. */
27832 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27834 arm_feature_set added_fset
;
27836 /* Compute features added by this architecture over the one
27837 recorded in p_ver_ret. */
27838 if (p_ver_ret
!= NULL
)
27839 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27841 /* First architecture that match incl. with extensions, or the
27842 only difference in features over the recorded match is
27843 features that were optional and are now mandatory. */
27844 if (p_ver_ret
== NULL
27845 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27851 else if (p_ver_ret
== NULL
)
27853 arm_feature_set needed_ext_fset
;
27855 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27857 /* Architecture has all features needed when using some
27858 extensions. Record it and continue searching in case there
27859 exist an architecture providing all needed features without
27860 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27862 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27869 if (p_ver_ret
== NULL
)
27873 /* Tag_CPU_arch_profile. */
27874 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27875 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27876 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27877 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27879 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27881 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27885 return p_ver_ret
->val
;
27888 /* Set the public EABI object attributes. */
27891 aeabi_set_public_attributes (void)
27893 char profile
= '\0';
27896 int fp16_optional
= 0;
27897 int skip_exact_match
= 0;
27898 arm_feature_set flags
, flags_arch
, flags_ext
;
27900 /* Autodetection mode, choose the architecture based the instructions
27902 if (no_cpu_selected ())
27904 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27906 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27907 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27909 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27910 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27912 /* Code run during relaxation relies on selected_cpu being set. */
27913 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27914 flags_ext
= arm_arch_none
;
27915 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27916 selected_ext
= flags_ext
;
27917 selected_cpu
= flags
;
27919 /* Otherwise, choose the architecture based on the capabilities of the
27923 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27924 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27925 flags_ext
= selected_ext
;
27926 flags
= selected_cpu
;
27928 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27930 /* Allow the user to override the reported architecture. */
27931 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27933 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27934 flags_ext
= arm_arch_none
;
27937 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27939 /* When this function is run again after relaxation has happened there is no
27940 way to determine whether an architecture or CPU was specified by the user:
27941 - selected_cpu is set above for relaxation to work;
27942 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27943 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27944 Therefore, if not in -march=all case we first try an exact match and fall
27945 back to autodetection. */
27946 if (!skip_exact_match
)
27947 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27949 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27951 as_bad (_("no architecture contains all the instructions used\n"));
27953 /* Tag_CPU_name. */
27954 if (selected_cpu_name
[0])
27958 q
= selected_cpu_name
;
27959 if (strncmp (q
, "armv", 4) == 0)
27964 for (i
= 0; q
[i
]; i
++)
27965 q
[i
] = TOUPPER (q
[i
]);
27967 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27970 /* Tag_CPU_arch. */
27971 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27973 /* Tag_CPU_arch_profile. */
27974 if (profile
!= '\0')
27975 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27977 /* Tag_DSP_extension. */
27978 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27979 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27981 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27982 /* Tag_ARM_ISA_use. */
27983 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27984 || ARM_FEATURE_ZERO (flags_arch
))
27985 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27987 /* Tag_THUMB_ISA_use. */
27988 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27989 || ARM_FEATURE_ZERO (flags_arch
))
27993 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27994 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27996 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
28000 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
28003 /* Tag_VFP_arch. */
28004 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
28005 aeabi_set_attribute_int (Tag_VFP_arch
,
28006 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28008 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
28009 aeabi_set_attribute_int (Tag_VFP_arch
,
28010 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28012 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
28015 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
28017 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
28019 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
28022 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
28023 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
28024 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
28025 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
28026 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
28028 /* Tag_ABI_HardFP_use. */
28029 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
28030 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
28031 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
28033 /* Tag_WMMX_arch. */
28034 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
28035 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
28036 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
28037 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
28039 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
28040 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
28041 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
28042 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
28043 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
28044 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
28046 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
28048 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
28052 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
28057 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
28058 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
28059 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
28063 We set Tag_DIV_use to two when integer divide instructions have been used
28064 in ARM state, or when Thumb integer divide instructions have been used,
28065 but we have no architecture profile set, nor have we any ARM instructions.
28067 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
28068 by the base architecture.
28070 For new architectures we will have to check these tests. */
28071 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
28072 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28073 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
28074 aeabi_set_attribute_int (Tag_DIV_use
, 0);
28075 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
28076 || (profile
== '\0'
28077 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
28078 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
28079 aeabi_set_attribute_int (Tag_DIV_use
, 2);
28081 /* Tag_MP_extension_use. */
28082 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
28083 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
28085 /* Tag Virtualization_use. */
28086 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
28088 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
28091 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
28094 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
28095 finished and free extension feature bits which will not be used anymore. */
28098 arm_md_post_relax (void)
28100 aeabi_set_public_attributes ();
28101 XDELETE (mcpu_ext_opt
);
28102 mcpu_ext_opt
= NULL
;
28103 XDELETE (march_ext_opt
);
28104 march_ext_opt
= NULL
;
28107 /* Add the default contents for the .ARM.attributes section. */
28112 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28115 aeabi_set_public_attributes ();
28117 #endif /* OBJ_ELF */
28119 /* Parse a .cpu directive. */
28122 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
28124 const struct arm_cpu_option_table
*opt
;
28128 name
= input_line_pointer
;
28129 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28130 input_line_pointer
++;
28131 saved_char
= *input_line_pointer
;
28132 *input_line_pointer
= 0;
28134 /* Skip the first "all" entry. */
28135 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
28136 if (streq (opt
->name
, name
))
28138 selected_arch
= opt
->value
;
28139 selected_ext
= opt
->ext
;
28140 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28141 if (opt
->canonical_name
)
28142 strcpy (selected_cpu_name
, opt
->canonical_name
);
28146 for (i
= 0; opt
->name
[i
]; i
++)
28147 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
28149 selected_cpu_name
[i
] = 0;
28151 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28153 *input_line_pointer
= saved_char
;
28154 demand_empty_rest_of_line ();
28157 as_bad (_("unknown cpu `%s'"), name
);
28158 *input_line_pointer
= saved_char
;
28159 ignore_rest_of_line ();
28162 /* Parse a .arch directive. */
28165 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
28167 const struct arm_arch_option_table
*opt
;
28171 name
= input_line_pointer
;
28172 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28173 input_line_pointer
++;
28174 saved_char
= *input_line_pointer
;
28175 *input_line_pointer
= 0;
28177 /* Skip the first "all" entry. */
28178 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28179 if (streq (opt
->name
, name
))
28181 selected_arch
= opt
->value
;
28182 selected_ext
= arm_arch_none
;
28183 selected_cpu
= selected_arch
;
28184 strcpy (selected_cpu_name
, opt
->name
);
28185 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28186 *input_line_pointer
= saved_char
;
28187 demand_empty_rest_of_line ();
28191 as_bad (_("unknown architecture `%s'\n"), name
);
28192 *input_line_pointer
= saved_char
;
28193 ignore_rest_of_line ();
28196 /* Parse a .object_arch directive. */
28199 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
28201 const struct arm_arch_option_table
*opt
;
28205 name
= input_line_pointer
;
28206 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28207 input_line_pointer
++;
28208 saved_char
= *input_line_pointer
;
28209 *input_line_pointer
= 0;
28211 /* Skip the first "all" entry. */
28212 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28213 if (streq (opt
->name
, name
))
28215 selected_object_arch
= opt
->value
;
28216 *input_line_pointer
= saved_char
;
28217 demand_empty_rest_of_line ();
28221 as_bad (_("unknown architecture `%s'\n"), name
);
28222 *input_line_pointer
= saved_char
;
28223 ignore_rest_of_line ();
28226 /* Parse a .arch_extension directive. */
28229 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
28231 const struct arm_option_extension_value_table
*opt
;
28234 int adding_value
= 1;
28236 name
= input_line_pointer
;
28237 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28238 input_line_pointer
++;
28239 saved_char
= *input_line_pointer
;
28240 *input_line_pointer
= 0;
28242 if (strlen (name
) >= 2
28243 && strncmp (name
, "no", 2) == 0)
28249 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28250 if (streq (opt
->name
, name
))
28252 int i
, nb_allowed_archs
=
28253 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
28254 for (i
= 0; i
< nb_allowed_archs
; i
++)
28257 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
28259 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
28263 if (i
== nb_allowed_archs
)
28265 as_bad (_("architectural extension `%s' is not allowed for the "
28266 "current base architecture"), name
);
28271 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
28274 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
28276 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28277 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28278 *input_line_pointer
= saved_char
;
28279 demand_empty_rest_of_line ();
28280 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
28281 on this return so that duplicate extensions (extensions with the
28282 same name as a previous extension in the list) are not considered
28283 for command-line parsing. */
28287 if (opt
->name
== NULL
)
28288 as_bad (_("unknown architecture extension `%s'\n"), name
);
28290 *input_line_pointer
= saved_char
;
28291 ignore_rest_of_line ();
28294 /* Parse a .fpu directive. */
28297 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
28299 const struct arm_option_fpu_value_table
*opt
;
28303 name
= input_line_pointer
;
28304 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28305 input_line_pointer
++;
28306 saved_char
= *input_line_pointer
;
28307 *input_line_pointer
= 0;
28309 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
28310 if (streq (opt
->name
, name
))
28312 selected_fpu
= opt
->value
;
28313 #ifndef CPU_DEFAULT
28314 if (no_cpu_selected ())
28315 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28318 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28319 *input_line_pointer
= saved_char
;
28320 demand_empty_rest_of_line ();
28324 as_bad (_("unknown floating point format `%s'\n"), name
);
28325 *input_line_pointer
= saved_char
;
28326 ignore_rest_of_line ();
28329 /* Copy symbol information. */
28332 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
28334 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
28338 /* Given a symbolic attribute NAME, return the proper integer value.
28339 Returns -1 if the attribute is not known. */
28342 arm_convert_symbolic_attribute (const char *name
)
28344 static const struct
28349 attribute_table
[] =
28351 /* When you modify this table you should
28352 also modify the list in doc/c-arm.texi. */
28353 #define T(tag) {#tag, tag}
28354 T (Tag_CPU_raw_name
),
28357 T (Tag_CPU_arch_profile
),
28358 T (Tag_ARM_ISA_use
),
28359 T (Tag_THUMB_ISA_use
),
28363 T (Tag_Advanced_SIMD_arch
),
28364 T (Tag_PCS_config
),
28365 T (Tag_ABI_PCS_R9_use
),
28366 T (Tag_ABI_PCS_RW_data
),
28367 T (Tag_ABI_PCS_RO_data
),
28368 T (Tag_ABI_PCS_GOT_use
),
28369 T (Tag_ABI_PCS_wchar_t
),
28370 T (Tag_ABI_FP_rounding
),
28371 T (Tag_ABI_FP_denormal
),
28372 T (Tag_ABI_FP_exceptions
),
28373 T (Tag_ABI_FP_user_exceptions
),
28374 T (Tag_ABI_FP_number_model
),
28375 T (Tag_ABI_align_needed
),
28376 T (Tag_ABI_align8_needed
),
28377 T (Tag_ABI_align_preserved
),
28378 T (Tag_ABI_align8_preserved
),
28379 T (Tag_ABI_enum_size
),
28380 T (Tag_ABI_HardFP_use
),
28381 T (Tag_ABI_VFP_args
),
28382 T (Tag_ABI_WMMX_args
),
28383 T (Tag_ABI_optimization_goals
),
28384 T (Tag_ABI_FP_optimization_goals
),
28385 T (Tag_compatibility
),
28386 T (Tag_CPU_unaligned_access
),
28387 T (Tag_FP_HP_extension
),
28388 T (Tag_VFP_HP_extension
),
28389 T (Tag_ABI_FP_16bit_format
),
28390 T (Tag_MPextension_use
),
28392 T (Tag_nodefaults
),
28393 T (Tag_also_compatible_with
),
28394 T (Tag_conformance
),
28396 T (Tag_Virtualization_use
),
28397 T (Tag_DSP_extension
),
28398 /* We deliberately do not include Tag_MPextension_use_legacy. */
28406 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28407 if (streq (name
, attribute_table
[i
].name
))
28408 return attribute_table
[i
].tag
;
28413 /* Apply sym value for relocations only in the case that they are for
28414 local symbols in the same segment as the fixup and you have the
28415 respective architectural feature for blx and simple switches. */
28418 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28421 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28422 /* PR 17444: If the local symbol is in a different section then a reloc
28423 will always be generated for it, so applying the symbol value now
28424 will result in a double offset being stored in the relocation. */
28425 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28426 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28428 switch (fixP
->fx_r_type
)
28430 case BFD_RELOC_ARM_PCREL_BLX
:
28431 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28432 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28436 case BFD_RELOC_ARM_PCREL_CALL
:
28437 case BFD_RELOC_THUMB_PCREL_BLX
:
28438 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28449 #endif /* OBJ_ELF */