1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2014 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
35 int insn_size
; /* In words. */
37 unsigned int bin_opcode
;
40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
43 struct avr_opcodes_s avr_opcodes
[] =
45 #include "opcode/avr.h"
46 {NULL
, NULL
, NULL
, 0, 0, 0}
49 const char comment_chars
[] = ";";
50 const char line_comment_chars
[] = "#";
51 const char line_separator_chars
[] = "$";
53 const char *md_shortopts
= "m:";
61 /* XXX - devices that don't seem to exist (renamed, replaced with larger
62 ones, or planned but never produced), left here for compatibility. */
64 static struct mcu_type_s mcu_types
[] =
66 {"avr1", AVR_ISA_AVR1
, bfd_mach_avr1
},
67 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
68 but set to AVR_ISA_AVR25 for some following version
69 of GCC (from 4.3) for backward compatibility. */
70 {"avr2", AVR_ISA_AVR25
, bfd_mach_avr2
},
71 {"avr25", AVR_ISA_AVR25
, bfd_mach_avr25
},
72 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
73 but set to AVR_ISA_AVR3_ALL for some following version
74 of GCC (from 4.3) for backward compatibility. */
75 {"avr3", AVR_ISA_AVR3_ALL
, bfd_mach_avr3
},
76 {"avr31", AVR_ISA_AVR31
, bfd_mach_avr31
},
77 {"avr35", AVR_ISA_AVR35
, bfd_mach_avr35
},
78 {"avr4", AVR_ISA_AVR4
, bfd_mach_avr4
},
79 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
80 but set to AVR_ISA_AVR51 for some following version
81 of GCC (from 4.3) for backward compatibility. */
82 {"avr5", AVR_ISA_AVR51
, bfd_mach_avr5
},
83 {"avr51", AVR_ISA_AVR51
, bfd_mach_avr51
},
84 {"avr6", AVR_ISA_AVR6
, bfd_mach_avr6
},
85 {"avrxmega1", AVR_ISA_XMEGA
, bfd_mach_avrxmega1
},
86 {"avrxmega2", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
87 {"avrxmega3", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
88 {"avrxmega4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
89 {"avrxmega5", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
90 {"avrxmega6", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
91 {"avrxmega7", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
92 {"avrtiny", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
93 {"at90s1200", AVR_ISA_1200
, bfd_mach_avr1
},
94 {"attiny11", AVR_ISA_AVR1
, bfd_mach_avr1
},
95 {"attiny12", AVR_ISA_AVR1
, bfd_mach_avr1
},
96 {"attiny15", AVR_ISA_AVR1
, bfd_mach_avr1
},
97 {"attiny28", AVR_ISA_AVR1
, bfd_mach_avr1
},
98 {"at90s2313", AVR_ISA_AVR2
, bfd_mach_avr2
},
99 {"at90s2323", AVR_ISA_AVR2
, bfd_mach_avr2
},
100 {"at90s2333", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 4433 */
101 {"at90s2343", AVR_ISA_AVR2
, bfd_mach_avr2
},
102 {"attiny22", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 2343 */
103 {"attiny26", AVR_ISA_2xxe
, bfd_mach_avr2
},
104 {"at90s4414", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8515 */
105 {"at90s4433", AVR_ISA_AVR2
, bfd_mach_avr2
},
106 {"at90s4434", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8535 */
107 {"at90s8515", AVR_ISA_AVR2
, bfd_mach_avr2
},
108 {"at90c8534", AVR_ISA_AVR2
, bfd_mach_avr2
},
109 {"at90s8535", AVR_ISA_AVR2
, bfd_mach_avr2
},
110 {"ata5272", AVR_ISA_AVR25
, bfd_mach_avr25
},
111 {"attiny13", AVR_ISA_AVR25
, bfd_mach_avr25
},
112 {"attiny13a", AVR_ISA_AVR25
, bfd_mach_avr25
},
113 {"attiny2313", AVR_ISA_AVR25
, bfd_mach_avr25
},
114 {"attiny2313a",AVR_ISA_AVR25
, bfd_mach_avr25
},
115 {"attiny24", AVR_ISA_AVR25
, bfd_mach_avr25
},
116 {"attiny24a", AVR_ISA_AVR25
, bfd_mach_avr25
},
117 {"attiny4313", AVR_ISA_AVR25
, bfd_mach_avr25
},
118 {"attiny44", AVR_ISA_AVR25
, bfd_mach_avr25
},
119 {"attiny44a", AVR_ISA_AVR25
, bfd_mach_avr25
},
120 {"attiny84", AVR_ISA_AVR25
, bfd_mach_avr25
},
121 {"attiny84a", AVR_ISA_AVR25
, bfd_mach_avr25
},
122 {"attiny25", AVR_ISA_AVR25
, bfd_mach_avr25
},
123 {"attiny45", AVR_ISA_AVR25
, bfd_mach_avr25
},
124 {"attiny85", AVR_ISA_AVR25
, bfd_mach_avr25
},
125 {"attiny261", AVR_ISA_AVR25
, bfd_mach_avr25
},
126 {"attiny261a", AVR_ISA_AVR25
, bfd_mach_avr25
},
127 {"attiny461", AVR_ISA_AVR25
, bfd_mach_avr25
},
128 {"attiny461a", AVR_ISA_AVR25
, bfd_mach_avr25
},
129 {"attiny861", AVR_ISA_AVR25
, bfd_mach_avr25
},
130 {"attiny861a", AVR_ISA_AVR25
, bfd_mach_avr25
},
131 {"attiny87", AVR_ISA_AVR25
, bfd_mach_avr25
},
132 {"attiny43u", AVR_ISA_AVR25
, bfd_mach_avr25
},
133 {"attiny48", AVR_ISA_AVR25
, bfd_mach_avr25
},
134 {"attiny88", AVR_ISA_AVR25
, bfd_mach_avr25
},
135 {"attiny828", AVR_ISA_AVR25
, bfd_mach_avr25
},
136 {"at86rf401", AVR_ISA_RF401
, bfd_mach_avr25
},
137 {"at43usb355", AVR_ISA_AVR3
, bfd_mach_avr3
},
138 {"at76c711", AVR_ISA_AVR3
, bfd_mach_avr3
},
139 {"atmega103", AVR_ISA_AVR31
, bfd_mach_avr31
},
140 {"at43usb320", AVR_ISA_AVR31
, bfd_mach_avr31
},
141 {"attiny167", AVR_ISA_AVR35
, bfd_mach_avr35
},
142 {"at90usb82", AVR_ISA_AVR35
, bfd_mach_avr35
},
143 {"at90usb162", AVR_ISA_AVR35
, bfd_mach_avr35
},
144 {"ata5505", AVR_ISA_AVR35
, bfd_mach_avr35
},
145 {"atmega8u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
146 {"atmega16u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
147 {"atmega32u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
148 {"attiny1634", AVR_ISA_AVR35
, bfd_mach_avr35
},
149 {"atmega8", AVR_ISA_M8
, bfd_mach_avr4
},
150 {"ata6289", AVR_ISA_AVR4
, bfd_mach_avr4
},
151 {"atmega8a", AVR_ISA_M8
, bfd_mach_avr4
},
152 {"ata6285", AVR_ISA_AVR4
, bfd_mach_avr4
},
153 {"ata6286", AVR_ISA_AVR4
, bfd_mach_avr4
},
154 {"atmega48", AVR_ISA_AVR4
, bfd_mach_avr4
},
155 {"atmega48a", AVR_ISA_AVR4
, bfd_mach_avr4
},
156 {"atmega48pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
157 {"atmega48p", AVR_ISA_AVR4
, bfd_mach_avr4
},
158 {"atmega88", AVR_ISA_AVR4
, bfd_mach_avr4
},
159 {"atmega88a", AVR_ISA_AVR4
, bfd_mach_avr4
},
160 {"atmega88p", AVR_ISA_AVR4
, bfd_mach_avr4
},
161 {"atmega88pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
162 {"atmega8515", AVR_ISA_M8
, bfd_mach_avr4
},
163 {"atmega8535", AVR_ISA_M8
, bfd_mach_avr4
},
164 {"atmega8hva", AVR_ISA_AVR4
, bfd_mach_avr4
},
165 {"at90pwm1", AVR_ISA_AVR4
, bfd_mach_avr4
},
166 {"at90pwm2", AVR_ISA_AVR4
, bfd_mach_avr4
},
167 {"at90pwm2b", AVR_ISA_AVR4
, bfd_mach_avr4
},
168 {"at90pwm3", AVR_ISA_AVR4
, bfd_mach_avr4
},
169 {"at90pwm3b", AVR_ISA_AVR4
, bfd_mach_avr4
},
170 {"at90pwm81", AVR_ISA_AVR4
, bfd_mach_avr4
},
171 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
172 {"ata5790", AVR_ISA_AVR5
, bfd_mach_avr5
},
173 {"ata5795", AVR_ISA_AVR5
, bfd_mach_avr5
},
174 {"atmega16", AVR_ISA_AVR5
, bfd_mach_avr5
},
175 {"atmega16a", AVR_ISA_AVR5
, bfd_mach_avr5
},
176 {"atmega161", AVR_ISA_M161
, bfd_mach_avr5
},
177 {"atmega162", AVR_ISA_AVR5
, bfd_mach_avr5
},
178 {"atmega163", AVR_ISA_M161
, bfd_mach_avr5
},
179 {"atmega164a", AVR_ISA_AVR5
, bfd_mach_avr5
},
180 {"atmega164p", AVR_ISA_AVR5
, bfd_mach_avr5
},
181 {"atmega164pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
182 {"atmega165", AVR_ISA_AVR5
, bfd_mach_avr5
},
183 {"atmega165a", AVR_ISA_AVR5
, bfd_mach_avr5
},
184 {"atmega165p", AVR_ISA_AVR5
, bfd_mach_avr5
},
185 {"atmega165pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
186 {"atmega168", AVR_ISA_AVR5
, bfd_mach_avr5
},
187 {"atmega168a", AVR_ISA_AVR5
, bfd_mach_avr5
},
188 {"atmega168p", AVR_ISA_AVR5
, bfd_mach_avr5
},
189 {"atmega168pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
190 {"atmega169", AVR_ISA_AVR5
, bfd_mach_avr5
},
191 {"atmega169a", AVR_ISA_AVR5
, bfd_mach_avr5
},
192 {"atmega169p", AVR_ISA_AVR5
, bfd_mach_avr5
},
193 {"atmega169pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
194 {"atmega32", AVR_ISA_AVR5
, bfd_mach_avr5
},
195 {"atmega32a", AVR_ISA_AVR5
, bfd_mach_avr5
},
196 {"atmega323", AVR_ISA_AVR5
, bfd_mach_avr5
},
197 {"atmega324a", AVR_ISA_AVR5
, bfd_mach_avr5
},
198 {"atmega324p", AVR_ISA_AVR5
, bfd_mach_avr5
},
199 {"atmega324pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
200 {"atmega325", AVR_ISA_AVR5
, bfd_mach_avr5
},
201 {"atmega325a", AVR_ISA_AVR5
, bfd_mach_avr5
},
202 {"atmega325p", AVR_ISA_AVR5
, bfd_mach_avr5
},
203 {"atmega325pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
204 {"atmega3250", AVR_ISA_AVR5
, bfd_mach_avr5
},
205 {"atmega3250a",AVR_ISA_AVR5
, bfd_mach_avr5
},
206 {"atmega3250p",AVR_ISA_AVR5
, bfd_mach_avr5
},
207 {"atmega3250pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
208 {"atmega328", AVR_ISA_AVR5
, bfd_mach_avr5
},
209 {"atmega328p", AVR_ISA_AVR5
, bfd_mach_avr5
},
210 {"atmega329", AVR_ISA_AVR5
, bfd_mach_avr5
},
211 {"atmega329a", AVR_ISA_AVR5
, bfd_mach_avr5
},
212 {"atmega329p", AVR_ISA_AVR5
, bfd_mach_avr5
},
213 {"atmega329pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
214 {"atmega3290", AVR_ISA_AVR5
, bfd_mach_avr5
},
215 {"atmega3290a",AVR_ISA_AVR5
, bfd_mach_avr5
},
216 {"atmega3290p",AVR_ISA_AVR5
, bfd_mach_avr5
},
217 {"atmega3290pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
218 {"atmega406", AVR_ISA_AVR5
, bfd_mach_avr5
},
219 {"atmega64rfr2", AVR_ISA_AVR5
, bfd_mach_avr5
},
220 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
221 {"atmega64", AVR_ISA_AVR5
, bfd_mach_avr5
},
222 {"atmega64a", AVR_ISA_AVR5
, bfd_mach_avr5
},
223 {"atmega640", AVR_ISA_AVR5
, bfd_mach_avr5
},
224 {"atmega644", AVR_ISA_AVR5
, bfd_mach_avr5
},
225 {"atmega644a", AVR_ISA_AVR5
, bfd_mach_avr5
},
226 {"atmega644p", AVR_ISA_AVR5
, bfd_mach_avr5
},
227 {"atmega644pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
228 {"atmega645", AVR_ISA_AVR5
, bfd_mach_avr5
},
229 {"atmega645a", AVR_ISA_AVR5
, bfd_mach_avr5
},
230 {"atmega645p", AVR_ISA_AVR5
, bfd_mach_avr5
},
231 {"atmega649", AVR_ISA_AVR5
, bfd_mach_avr5
},
232 {"atmega649a", AVR_ISA_AVR5
, bfd_mach_avr5
},
233 {"atmega649p", AVR_ISA_AVR5
, bfd_mach_avr5
},
234 {"atmega6450", AVR_ISA_AVR5
, bfd_mach_avr5
},
235 {"atmega6450a",AVR_ISA_AVR5
, bfd_mach_avr5
},
236 {"atmega6450p",AVR_ISA_AVR5
, bfd_mach_avr5
},
237 {"atmega6490", AVR_ISA_AVR5
, bfd_mach_avr5
},
238 {"atmega6490a",AVR_ISA_AVR5
, bfd_mach_avr5
},
239 {"atmega6490p",AVR_ISA_AVR5
, bfd_mach_avr5
},
240 {"atmega64rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
241 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
242 {"atmega16hva",AVR_ISA_AVR5
, bfd_mach_avr5
},
243 {"atmega16hva2",AVR_ISA_AVR5
, bfd_mach_avr5
},
244 {"atmega16hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
245 {"atmega16hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
246 {"atmega32hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
247 {"atmega32hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
248 {"atmega64hve",AVR_ISA_AVR5
, bfd_mach_avr5
},
249 {"at90can32" , AVR_ISA_AVR5
, bfd_mach_avr5
},
250 {"at90can64" , AVR_ISA_AVR5
, bfd_mach_avr5
},
251 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
252 {"at90pwm216", AVR_ISA_AVR5
, bfd_mach_avr5
},
253 {"at90pwm316", AVR_ISA_AVR5
, bfd_mach_avr5
},
254 {"atmega32c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
255 {"atmega64c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
256 {"atmega16m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
257 {"atmega32m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
258 {"atmega64m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
259 {"atmega16u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
260 {"atmega32u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
261 {"atmega32u6", AVR_ISA_AVR5
, bfd_mach_avr5
},
262 {"at90usb646", AVR_ISA_AVR5
, bfd_mach_avr5
},
263 {"at90usb647", AVR_ISA_AVR5
, bfd_mach_avr5
},
264 {"at90scr100", AVR_ISA_AVR5
, bfd_mach_avr5
},
265 {"at94k", AVR_ISA_94K
, bfd_mach_avr5
},
266 {"m3000", AVR_ISA_AVR5
, bfd_mach_avr5
},
267 {"atmega128", AVR_ISA_AVR51
, bfd_mach_avr51
},
268 {"atmega128a", AVR_ISA_AVR51
, bfd_mach_avr51
},
269 {"atmega1280", AVR_ISA_AVR51
, bfd_mach_avr51
},
270 {"atmega1281", AVR_ISA_AVR51
, bfd_mach_avr51
},
271 {"atmega1284", AVR_ISA_AVR51
, bfd_mach_avr51
},
272 {"atmega1284p",AVR_ISA_AVR51
, bfd_mach_avr51
},
273 {"atmega128rfa1",AVR_ISA_AVR51
, bfd_mach_avr51
},
274 {"atmega128rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
275 {"atmega1284rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
276 {"at90can128", AVR_ISA_AVR51
, bfd_mach_avr51
},
277 {"at90usb1286",AVR_ISA_AVR51
, bfd_mach_avr51
},
278 {"at90usb1287",AVR_ISA_AVR51
, bfd_mach_avr51
},
279 {"atmega2560", AVR_ISA_AVR6
, bfd_mach_avr6
},
280 {"atmega2561", AVR_ISA_AVR6
, bfd_mach_avr6
},
281 {"atmega256rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
282 {"atmega2564rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
283 {"atxmega16a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
284 {"atxmega16a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
285 {"atxmega16c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
286 {"atxmega16d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
287 {"atxmega32a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
288 {"atxmega32a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
289 {"atxmega32c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
290 {"atxmega32d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
291 {"atxmega32e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
292 {"atxmega16e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
293 {"atxmega8e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
294 {"atxmega32x1", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
295 {"atxmega64a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
296 {"atxmega64a3u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
297 {"atxmega64a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
298 {"atxmega64b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
299 {"atxmega64b3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
300 {"atxmega64c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
301 {"atxmega64d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
302 {"atxmega64d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
303 {"atxmega64a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
304 {"atxmega64a1u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega5
},
305 {"atxmega128a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
306 {"atxmega128a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
307 {"atxmega128b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
308 {"atxmega128b3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
309 {"atxmega128c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
310 {"atxmega128d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
311 {"atxmega128d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
312 {"atxmega192a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
313 {"atxmega192a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
314 {"atxmega192c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
315 {"atxmega192d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
316 {"atxmega256a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
317 {"atxmega256a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
318 {"atxmega256a3b",AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
319 {"atxmega256a3bu",AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
320 {"atxmega256c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
321 {"atxmega256d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
322 {"atxmega384c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
323 {"atxmega384d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
324 {"atxmega128a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
325 {"atxmega128a1u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
326 {"atxmega128a4u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
327 {"attiny4", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
328 {"attiny5", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
329 {"attiny9", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
330 {"attiny10", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
331 {"attiny20", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
332 {"attiny40", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
337 /* Current MCU type. */
338 static struct mcu_type_s default_mcu
= {"avr2", AVR_ISA_AVR2
, bfd_mach_avr2
};
339 static struct mcu_type_s specified_mcu
;
340 static struct mcu_type_s
* avr_mcu
= & default_mcu
;
342 /* AVR target-specific switches. */
345 int all_opcodes
; /* -mall-opcodes: accept all known AVR opcodes. */
346 int no_skip_bug
; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
347 int no_wrap
; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
348 int link_relax
; /* -mlink-relax: generate relocations for linker
352 static struct avr_opt_s avr_opt
= { 0, 0, 0, 0 };
354 const char EXP_CHARS
[] = "eE";
355 const char FLT_CHARS
[] = "dD";
357 static void avr_set_arch (int);
359 /* The target specific pseudo-ops which we support. */
360 const pseudo_typeS md_pseudo_table
[] =
362 {"arch", avr_set_arch
, 0},
366 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
368 #define EXP_MOD_NAME(i) exp_mod[i].name
369 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
370 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
371 #define HAVE_PM_P(i) exp_mod[i].have_pm
376 bfd_reloc_code_real_type reloc
;
377 bfd_reloc_code_real_type neg_reloc
;
381 static struct exp_mod_s exp_mod
[] =
383 {"hh8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 1},
384 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM
, BFD_RELOC_AVR_HH8_LDI_PM_NEG
, 0},
385 {"hi8", BFD_RELOC_AVR_HI8_LDI
, BFD_RELOC_AVR_HI8_LDI_NEG
, 1},
386 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM
, BFD_RELOC_AVR_HI8_LDI_PM_NEG
, 0},
387 {"lo8", BFD_RELOC_AVR_LO8_LDI
, BFD_RELOC_AVR_LO8_LDI_NEG
, 1},
388 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM
, BFD_RELOC_AVR_LO8_LDI_PM_NEG
, 0},
389 {"hlo8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 0},
390 {"hhi8", BFD_RELOC_AVR_MS8_LDI
, BFD_RELOC_AVR_MS8_LDI_NEG
, 0},
393 /* A union used to store indicies into the exp_mod[] array
394 in a hash table which expects void * data types. */
401 /* Opcode hash table. */
402 static struct hash_control
*avr_hash
;
404 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
405 static struct hash_control
*avr_mod_hash
;
407 #define OPTION_MMCU 'm'
410 OPTION_ALL_OPCODES
= OPTION_MD_BASE
+ 1,
417 struct option md_longopts
[] =
419 { "mmcu", required_argument
, NULL
, OPTION_MMCU
},
420 { "mall-opcodes", no_argument
, NULL
, OPTION_ALL_OPCODES
},
421 { "mno-skip-bug", no_argument
, NULL
, OPTION_NO_SKIP_BUG
},
422 { "mno-wrap", no_argument
, NULL
, OPTION_NO_WRAP
},
423 { "mrmw", no_argument
, NULL
, OPTION_ISA_RMW
},
424 { "mlink-relax", no_argument
, NULL
, OPTION_LINK_RELAX
},
425 { NULL
, no_argument
, NULL
, 0 }
428 size_t md_longopts_size
= sizeof (md_longopts
);
430 /* Display nicely formatted list of known MCU names. */
433 show_mcu_list (FILE *stream
)
437 fprintf (stream
, _("Known MCU names:"));
440 for (i
= 0; mcu_types
[i
].name
; i
++)
442 int len
= strlen (mcu_types
[i
].name
);
447 fprintf (stream
, " %s", mcu_types
[i
].name
);
450 fprintf (stream
, "\n %s", mcu_types
[i
].name
);
455 fprintf (stream
, "\n");
461 while (*s
== ' ' || *s
== '\t')
466 /* Extract one word from FROM and copy it to TO. */
469 extract_word (char *from
, char *to
, int limit
)
474 /* Drop leading whitespace. */
475 from
= skip_space (from
);
478 /* Find the op code end. */
479 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
481 to
[size
++] = *op_end
++;
482 if (size
+ 1 >= limit
)
491 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
492 asection
*seg ATTRIBUTE_UNUSED
)
499 md_show_usage (FILE *stream
)
502 _("AVR Assembler options:\n"
503 " -mmcu=[avr-name] select microcontroller variant\n"
504 " [avr-name] can be:\n"
505 " avr1 - classic AVR core without data RAM\n"
506 " avr2 - classic AVR core with up to 8K program memory\n"
507 " avr25 - classic AVR core with up to 8K program memory\n"
508 " plus the MOVW instruction\n"
509 " avr3 - classic AVR core with up to 64K program memory\n"
510 " avr31 - classic AVR core with up to 128K program memory\n"
511 " avr35 - classic AVR core with up to 64K program memory\n"
512 " plus the MOVW instruction\n"
513 " avr4 - enhanced AVR core with up to 8K program memory\n"
514 " avr5 - enhanced AVR core with up to 64K program memory\n"
515 " avr51 - enhanced AVR core with up to 128K program memory\n"
516 " avr6 - enhanced AVR core with up to 256K program memory\n"
517 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
518 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
519 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
520 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
521 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
522 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
523 " avrtiny - AVR Tiny core with 16 gp registers\n"));
525 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
526 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
527 " (default for avr4, avr5)\n"
528 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
529 " (default for avr3, avr5)\n"
530 " -mrmw accept Read-Modify-Write instructions\n"
531 " -mlink-relax generate relocations for linker relaxation\n"
533 show_mcu_list (stream
);
537 avr_set_arch (int dummy ATTRIBUTE_UNUSED
)
541 input_line_pointer
= extract_word (input_line_pointer
, str
, 20);
542 md_parse_option (OPTION_MMCU
, str
);
543 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
547 md_parse_option (int c
, char *arg
)
554 char *s
= alloca (strlen (arg
) + 1);
561 *t
= TOLOWER (*arg1
++);
565 for (i
= 0; mcu_types
[i
].name
; ++i
)
566 if (strcmp (mcu_types
[i
].name
, s
) == 0)
569 if (!mcu_types
[i
].name
)
571 show_mcu_list (stderr
);
572 as_fatal (_("unknown MCU: %s\n"), arg
);
575 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
576 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
577 as .arch ... in the asm output at the same time. */
578 if (avr_mcu
== &default_mcu
|| avr_mcu
->mach
== mcu_types
[i
].mach
)
580 specified_mcu
.name
= mcu_types
[i
].name
;
581 specified_mcu
.isa
|= mcu_types
[i
].isa
;
582 specified_mcu
.mach
= mcu_types
[i
].mach
;
583 avr_mcu
= &specified_mcu
;
586 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
587 avr_mcu
->name
, mcu_types
[i
].name
);
590 case OPTION_ALL_OPCODES
:
591 avr_opt
.all_opcodes
= 1;
593 case OPTION_NO_SKIP_BUG
:
594 avr_opt
.no_skip_bug
= 1;
600 specified_mcu
.isa
|= AVR_ISA_RMW
;
602 case OPTION_LINK_RELAX
:
603 avr_opt
.link_relax
= 1;
611 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
617 md_atof (int type
, char *litP
, int *sizeP
)
619 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
623 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
624 asection
*sec ATTRIBUTE_UNUSED
,
625 fragS
*fragP ATTRIBUTE_UNUSED
)
634 struct avr_opcodes_s
*opcode
;
636 avr_hash
= hash_new ();
638 /* Insert unique names into hash table. This hash table then provides a
639 quick index to the first opcode with a particular name in the opcode
641 for (opcode
= avr_opcodes
; opcode
->name
; opcode
++)
642 hash_insert (avr_hash
, opcode
->name
, (char *) opcode
);
644 avr_mod_hash
= hash_new ();
646 for (i
= 0; i
< ARRAY_SIZE (exp_mod
); ++i
)
651 hash_insert (avr_mod_hash
, EXP_MOD_NAME (i
), m
.ptr
);
654 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
655 linkrelax
= avr_opt
.link_relax
;
658 /* Resolve STR as a constant expression and return the result.
659 If result greater than MAX then error. */
662 avr_get_constant (char *str
, int max
)
666 str
= skip_space (str
);
667 input_line_pointer
= str
;
670 if (ex
.X_op
!= O_constant
)
671 as_bad (_("constant value required"));
673 if (ex
.X_add_number
> max
|| ex
.X_add_number
< 0)
674 as_bad (_("number must be positive and less than %d"), max
+ 1);
676 return ex
.X_add_number
;
679 /* Parse for ldd/std offset. */
682 avr_offset_expression (expressionS
*exp
)
684 char *str
= input_line_pointer
;
689 str
= extract_word (str
, op
, sizeof (op
));
691 input_line_pointer
= tmp
;
694 /* Warn about expressions that fail to use lo8 (). */
695 if (exp
->X_op
== O_constant
)
697 int x
= exp
->X_add_number
;
699 if (x
< -255 || x
> 255)
700 as_warn (_("constant out of 8-bit range: %d"), x
);
704 /* Parse ordinary expression. */
707 parse_exp (char *s
, expressionS
*op
)
709 input_line_pointer
= s
;
711 if (op
->X_op
== O_absent
)
712 as_bad (_("missing operand"));
713 return input_line_pointer
;
716 /* Parse special expressions (needed for LDI command):
721 where xx is: hh, hi, lo. */
723 static bfd_reloc_code_real_type
724 avr_ldi_expression (expressionS
*exp
)
726 char *str
= input_line_pointer
;
730 int linker_stubs_should_be_generated
= 0;
734 str
= extract_word (str
, op
, sizeof (op
));
740 m
.ptr
= hash_find (avr_mod_hash
, op
);
748 str
= skip_space (str
);
752 bfd_reloc_code_real_type reloc_to_return
;
757 if (strncmp ("pm(", str
, 3) == 0
758 || strncmp ("gs(",str
,3) == 0
759 || strncmp ("-(gs(",str
,5) == 0
760 || strncmp ("-(pm(", str
, 5) == 0)
768 as_bad (_("illegal expression"));
770 if (str
[0] == 'g' || str
[2] == 'g')
771 linker_stubs_should_be_generated
= 1;
783 if (*str
== '-' && *(str
+ 1) == '(')
790 input_line_pointer
= str
;
795 if (*input_line_pointer
!= ')')
797 as_bad (_("`)' required"));
800 input_line_pointer
++;
805 neg_p
? EXP_MOD_NEG_RELOC (mod
) : EXP_MOD_RELOC (mod
);
806 if (linker_stubs_should_be_generated
)
808 switch (reloc_to_return
)
810 case BFD_RELOC_AVR_LO8_LDI_PM
:
811 reloc_to_return
= BFD_RELOC_AVR_LO8_LDI_GS
;
813 case BFD_RELOC_AVR_HI8_LDI_PM
:
814 reloc_to_return
= BFD_RELOC_AVR_HI8_LDI_GS
;
818 /* PR 5523: Do not generate a warning here,
819 legitimate code can trigger this case. */
823 return reloc_to_return
;
828 input_line_pointer
= tmp
;
831 /* Warn about expressions that fail to use lo8 (). */
832 if (exp
->X_op
== O_constant
)
834 int x
= exp
->X_add_number
;
836 if (x
< -255 || x
> 255)
837 as_warn (_("constant out of 8-bit range: %d"), x
);
840 return BFD_RELOC_AVR_LDI
;
843 /* Parse one instruction operand.
844 Return operand bitmask. Also fixups can be generated. */
847 avr_operand (struct avr_opcodes_s
*opcode
,
853 unsigned int op_mask
= 0;
854 char *str
= skip_space (*line
);
858 /* Any register operand. */
865 char * old_str
= str
;
869 str
= extract_word (str
, r_name
, sizeof (r_name
));
870 for (lower
= r_name
; *lower
; ++lower
)
872 if (*lower
>= 'A' && *lower
<= 'Z')
876 if (r_name
[0] == 'r' && ISDIGIT (r_name
[1]) && r_name
[2] == 0)
877 /* Single-digit register number, ie r0-r9. */
878 op_mask
= r_name
[1] - '0';
879 else if (r_name
[0] == 'r' && ISDIGIT (r_name
[1])
880 && ISDIGIT (r_name
[2]) && r_name
[3] == 0)
881 /* Double-digit register number, ie r10 - r32. */
882 op_mask
= (r_name
[1] - '0') * 10 + r_name
[2] - '0';
883 else if (r_name
[0] >= 'x' && r_name
[0] <= 'z'
884 && (r_name
[1] == 'l' || r_name
[1] == 'h') && r_name
[2] == 0)
885 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
886 op_mask
= (r_name
[0] - 'x') * 2 + (r_name
[1] == 'h') + 26;
887 else if ((*op
== 'v' || *op
== 'w')
888 && r_name
[0] >= 'x' && r_name
[0] <= 'z' && r_name
[1] == 0)
889 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
890 op_mask
= (r_name
[0] - 'x') * 2 + 26;
893 /* Numeric or symbolic constant register number. */
894 op_mask
= avr_get_constant (old_str
, 31);
895 str
= input_line_pointer
;
899 if (avr_mcu
->mach
== bfd_mach_avrtiny
)
901 if (op_mask
< 16 || op_mask
> 31)
903 as_bad (_("register name or number from 16 to 31 required"));
907 else if (op_mask
> 31)
909 as_bad (_("register name or number from 0 to 31 required"));
916 if (op_mask
< 16 || op_mask
> 23)
917 as_bad (_("register r16-r23 required"));
923 as_bad (_("register number above 15 required"));
929 as_bad (_("even register number required"));
934 if ((op_mask
& 1) || op_mask
< 24)
935 as_bad (_("register r24, r26, r28 or r30 required"));
936 op_mask
= (op_mask
- 24) >> 1;
947 str
= skip_space (str
+ 1);
956 as_bad (_("pointer register (X, Y or Z) required"));
958 str
= skip_space (str
+ 1);
963 as_bad (_("cannot both predecrement and postincrement"));
967 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
968 registers, no predecrement, no postincrement. */
969 if (!avr_opt
.all_opcodes
&& (op_mask
& 0x100F)
970 && !(avr_mcu
->isa
& AVR_ISA_SRAM
))
971 as_bad (_("addressing mode not supported"));
977 as_bad (_("can't predecrement"));
979 if (! (*str
== 'z' || *str
== 'Z'))
980 as_bad (_("pointer register Z required"));
982 str
= skip_space (str
+ 1);
988 for (s
= opcode
->opcode
; *s
; ++s
)
991 op_mask
|= (1 << (15 - (s
- opcode
->opcode
)));
995 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
996 if (!avr_opt
.all_opcodes
997 && (op_mask
& 0x0001)
998 && !(avr_mcu
->isa
& AVR_ISA_MOVW
))
999 as_bad (_("postincrement not supported"));
1004 char c
= TOLOWER (*str
++);
1009 as_bad (_("pointer register (Y or Z) required"));
1010 str
= skip_space (str
);
1013 input_line_pointer
= str
;
1014 avr_offset_expression (& op_expr
);
1015 str
= input_line_pointer
;
1016 fix_new_exp (frag_now
, where
, 3,
1017 &op_expr
, FALSE
, BFD_RELOC_AVR_6
);
1023 str
= parse_exp (str
, &op_expr
);
1024 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1025 &op_expr
, FALSE
, BFD_RELOC_AVR_CALL
);
1029 str
= parse_exp (str
, &op_expr
);
1030 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1031 &op_expr
, TRUE
, BFD_RELOC_AVR_13_PCREL
);
1035 str
= parse_exp (str
, &op_expr
);
1036 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1037 &op_expr
, TRUE
, BFD_RELOC_AVR_7_PCREL
);
1041 str
= parse_exp (str
, &op_expr
);
1042 fix_new_exp (frag_now
, where
+ 2, opcode
->insn_size
* 2,
1043 &op_expr
, FALSE
, BFD_RELOC_16
);
1047 str
= parse_exp (str
, &op_expr
);
1048 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1049 &op_expr
, FALSE
, BFD_RELOC_AVR_LDS_STS_16
);
1054 bfd_reloc_code_real_type r_type
;
1056 input_line_pointer
= str
;
1057 r_type
= avr_ldi_expression (&op_expr
);
1058 str
= input_line_pointer
;
1059 fix_new_exp (frag_now
, where
, 3,
1060 &op_expr
, FALSE
, r_type
);
1068 x
= ~avr_get_constant (str
, 255);
1069 str
= input_line_pointer
;
1070 op_mask
|= (x
& 0xf) | ((x
<< 4) & 0xf00);
1075 input_line_pointer
= str
;
1076 avr_offset_expression (& op_expr
);
1077 str
= input_line_pointer
;
1078 fix_new_exp (frag_now
, where
, 3,
1079 & op_expr
, FALSE
, BFD_RELOC_AVR_6_ADIW
);
1087 x
= avr_get_constant (str
, 7);
1088 str
= input_line_pointer
;
1096 str
= parse_exp (str
, &op_expr
);
1097 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1098 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT6
);
1102 str
= parse_exp (str
, &op_expr
);
1103 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1104 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT5
);
1111 x
= avr_get_constant (str
, 15);
1112 str
= input_line_pointer
;
1113 op_mask
|= (x
<< 4);
1121 as_bad (_("unknown constraint `%c'"), *op
);
1128 /* Parse instruction operands.
1129 Return binary opcode. */
1132 avr_operands (struct avr_opcodes_s
*opcode
, char **line
)
1134 char *op
= opcode
->constraints
;
1135 unsigned int bin
= opcode
->bin_opcode
;
1136 char *frag
= frag_more (opcode
->insn_size
* 2);
1138 int where
= frag
- frag_now
->fr_literal
;
1139 static unsigned int prev
= 0; /* Previous opcode. */
1141 /* Opcode have operands. */
1144 unsigned int reg1
= 0;
1145 unsigned int reg2
= 0;
1146 int reg1_present
= 0;
1147 int reg2_present
= 0;
1149 /* Parse first operand. */
1150 if (REGISTER_P (*op
))
1152 reg1
= avr_operand (opcode
, where
, op
, &str
);
1155 /* Parse second operand. */
1168 if (REGISTER_P (*op
))
1171 str
= skip_space (str
);
1173 as_bad (_("`,' required"));
1174 str
= skip_space (str
);
1176 reg2
= avr_operand (opcode
, where
, op
, &str
);
1179 if (reg1_present
&& reg2_present
)
1180 reg2
= (reg2
& 0xf) | ((reg2
<< 5) & 0x200);
1181 else if (reg2_present
)
1189 /* Detect undefined combinations (like ld r31,Z+). */
1190 if (!avr_opt
.all_opcodes
&& AVR_UNDEF_P (bin
))
1191 as_warn (_("undefined combination of operands"));
1193 if (opcode
->insn_size
== 2)
1195 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1196 (AVR core bug, fixed in the newer devices). */
1197 if (!(avr_opt
.no_skip_bug
||
1198 (avr_mcu
->isa
& (AVR_ISA_MUL
| AVR_ISA_MOVW
)))
1199 && AVR_SKIP_P (prev
))
1200 as_warn (_("skipping two-word instruction"));
1202 bfd_putl32 ((bfd_vma
) bin
, frag
);
1205 bfd_putl16 ((bfd_vma
) bin
, frag
);
1212 /* GAS will call this function for each section at the end of the assembly,
1213 to permit the CPU backend to adjust the alignment of a section. */
1216 md_section_align (asection
*seg
, valueT addr
)
1218 int align
= bfd_get_section_alignment (stdoutput
, seg
);
1219 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
1222 /* If you define this macro, it should return the offset between the
1223 address of a PC relative fixup and the position from which the PC
1224 relative adjustment should be made. On many processors, the base
1225 of a PC relative instruction is the next instruction, so this
1226 macro would return the length of an instruction. */
1229 md_pcrel_from_section (fixS
*fixp
, segT sec
)
1231 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1232 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1233 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1236 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1240 relaxable_section (asection
*sec
)
1242 return (sec
->flags
& SEC_DEBUGGING
) == 0;
1245 /* Does whatever the xtensa port does. */
1247 avr_validate_fix_sub (fixS
*fix
)
1249 segT add_symbol_segment
, sub_symbol_segment
;
1251 /* The difference of two symbols should be resolved by the assembler when
1252 linkrelax is not set. If the linker may relax the section containing
1253 the symbols, then an Xtensa DIFF relocation must be generated so that
1254 the linker knows to adjust the difference value. */
1255 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
1258 /* Make sure both symbols are in the same segment, and that segment is
1259 "normal" and relaxable. If the segment is not "normal", then the
1260 fix is not valid. If the segment is not "relaxable", then the fix
1261 should have been handled earlier. */
1262 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
1263 if (! SEG_NORMAL (add_symbol_segment
) ||
1264 ! relaxable_section (add_symbol_segment
))
1267 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
1268 return (sub_symbol_segment
== add_symbol_segment
);
1271 /* TC_FORCE_RELOCATION hook */
1273 /* If linkrelax is turned on, and the symbol to relocate
1274 against is in a relaxable segment, don't compute the value -
1275 generate a relocation instead. */
1277 avr_force_relocation (fixS
*fix
)
1279 if (linkrelax
&& fix
->fx_addsy
1280 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
1283 return generic_force_reloc (fix
);
1286 /* GAS will call this for each fixup. It should store the correct
1287 value in the object file. */
1290 md_apply_fix (fixS
*fixP
, valueT
* valP
, segT seg
)
1292 unsigned char *where
;
1296 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1299 else if (fixP
->fx_pcrel
)
1301 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
1303 if (s
== seg
|| s
== absolute_section
)
1305 value
+= S_GET_VALUE (fixP
->fx_addsy
);
1309 else if (linkrelax
&& fixP
->fx_subsy
)
1311 /* For a subtraction relocation expression, generate one
1312 of the DIFF relocs, with the value being the difference.
1313 Note that a sym1 - sym2 expression is adjusted into a
1314 section_start_sym + sym4_offset_from_section_start - sym1
1315 expression. fixP->fx_addsy holds the section start symbol,
1316 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1317 holds sym1. Calculate the current difference and write value,
1318 but leave fx_offset as is - during relaxation,
1319 fx_offset - value gives sym1's value. */
1321 switch (fixP
->fx_r_type
)
1324 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF8
;
1327 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF16
;
1330 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF32
;
1333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1337 value
= S_GET_VALUE (fixP
->fx_addsy
) +
1338 fixP
->fx_offset
- S_GET_VALUE (fixP
->fx_subsy
);
1340 fixP
->fx_subsy
= NULL
;
1342 /* We don't actually support subtracting a symbol. */
1343 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1346 /* For the DIFF relocs, write the value into the object file while still
1347 keeping fx_done FALSE, as both the difference (recorded in the object file)
1348 and the sym offset (part of fixP) are needed at link relax time. */
1349 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1350 switch (fixP
->fx_r_type
)
1353 fixP
->fx_no_overflow
= 1;
1355 case BFD_RELOC_AVR_7_PCREL
:
1356 case BFD_RELOC_AVR_13_PCREL
:
1360 case BFD_RELOC_AVR_DIFF8
:
1363 case BFD_RELOC_AVR_DIFF16
:
1364 bfd_putl16 ((bfd_vma
) value
, where
);
1366 case BFD_RELOC_AVR_DIFF32
:
1367 bfd_putl32 ((bfd_vma
) value
, where
);
1369 case BFD_RELOC_AVR_CALL
:
1375 /* Fetch the instruction, insert the fully resolved operand
1376 value, and stuff the instruction back again. */
1377 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1378 insn
= bfd_getl16 (where
);
1380 switch (fixP
->fx_r_type
)
1382 case BFD_RELOC_AVR_7_PCREL
:
1384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1385 _("odd address operand: %ld"), value
);
1387 /* Instruction addresses are always right-shifted by 1. */
1389 --value
; /* Correct PC. */
1391 if (value
< -64 || value
> 63)
1392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1393 _("operand out of range: %ld"), value
);
1394 value
= (value
<< 3) & 0x3f8;
1395 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1398 case BFD_RELOC_AVR_13_PCREL
:
1400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1401 _("odd address operand: %ld"), value
);
1403 /* Instruction addresses are always right-shifted by 1. */
1405 --value
; /* Correct PC. */
1407 if (value
< -2048 || value
> 2047)
1409 /* No wrap for devices with >8K of program memory. */
1410 if ((avr_mcu
->isa
& AVR_ISA_MEGA
) || avr_opt
.no_wrap
)
1411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1412 _("operand out of range: %ld"), value
);
1416 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1420 bfd_putl32 ((bfd_vma
) value
, where
);
1424 bfd_putl16 ((bfd_vma
) value
, where
);
1428 if (value
> 255 || value
< -128)
1429 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1430 _("operand out of range: %ld"), value
);
1434 case BFD_RELOC_AVR_16_PM
:
1435 bfd_putl16 ((bfd_vma
) (value
>> 1), where
);
1438 case BFD_RELOC_AVR_LDI
:
1440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1441 _("operand out of range: %ld"), value
);
1442 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1445 case BFD_RELOC_AVR_LDS_STS_16
:
1446 if ((value
< 0x40) || (value
> 0xBF))
1447 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1448 _("operand out of range: 0x%lx"),
1449 (unsigned long)value
);
1450 insn
|= ((value
& 0xF) | ((value
& 0x30) << 5) | ((value
& 0x40) << 2));
1451 bfd_putl16 ((bfd_vma
) insn
, where
);
1454 case BFD_RELOC_AVR_6
:
1455 if ((value
> 63) || (value
< 0))
1456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1457 _("operand out of range: %ld"), value
);
1458 bfd_putl16 ((bfd_vma
) insn
| ((value
& 7) | ((value
& (3 << 3)) << 7)
1459 | ((value
& (1 << 5)) << 8)), where
);
1462 case BFD_RELOC_AVR_6_ADIW
:
1463 if ((value
> 63) || (value
< 0))
1464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1465 _("operand out of range: %ld"), value
);
1466 bfd_putl16 ((bfd_vma
) insn
| (value
& 0xf) | ((value
& 0x30) << 2), where
);
1469 case BFD_RELOC_AVR_LO8_LDI
:
1470 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1473 case BFD_RELOC_AVR_HI8_LDI
:
1474 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 8), where
);
1477 case BFD_RELOC_AVR_MS8_LDI
:
1478 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 24), where
);
1481 case BFD_RELOC_AVR_HH8_LDI
:
1482 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 16), where
);
1485 case BFD_RELOC_AVR_LO8_LDI_NEG
:
1486 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
), where
);
1489 case BFD_RELOC_AVR_HI8_LDI_NEG
:
1490 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 8), where
);
1493 case BFD_RELOC_AVR_MS8_LDI_NEG
:
1494 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 24), where
);
1497 case BFD_RELOC_AVR_HH8_LDI_NEG
:
1498 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 16), where
);
1501 case BFD_RELOC_AVR_LO8_LDI_PM
:
1502 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 1), where
);
1505 case BFD_RELOC_AVR_HI8_LDI_PM
:
1506 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 9), where
);
1509 case BFD_RELOC_AVR_HH8_LDI_PM
:
1510 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 17), where
);
1513 case BFD_RELOC_AVR_LO8_LDI_PM_NEG
:
1514 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 1), where
);
1517 case BFD_RELOC_AVR_HI8_LDI_PM_NEG
:
1518 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 9), where
);
1521 case BFD_RELOC_AVR_HH8_LDI_PM_NEG
:
1522 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 17), where
);
1525 case BFD_RELOC_AVR_CALL
:
1529 x
= bfd_getl16 (where
);
1531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1532 _("odd address operand: %ld"), value
);
1534 x
|= ((value
& 0x10000) | ((value
<< 3) & 0x1f00000)) >> 16;
1535 bfd_putl16 ((bfd_vma
) x
, where
);
1536 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
1540 case BFD_RELOC_AVR_8_LO
:
1541 *where
= 0xff & value
;
1544 case BFD_RELOC_AVR_8_HI
:
1545 *where
= 0xff & (value
>> 8);
1548 case BFD_RELOC_AVR_8_HLO
:
1549 *where
= 0xff & (value
>> 16);
1553 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1554 fixP
->fx_line
, fixP
->fx_r_type
);
1557 case BFD_RELOC_AVR_PORT6
:
1559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1560 _("operand out of range: %ld"), value
);
1561 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x30) << 5) | (value
& 0x0f), where
);
1564 case BFD_RELOC_AVR_PORT5
:
1566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1567 _("operand out of range: %ld"), value
);
1568 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x1f) << 3), where
);
1574 switch ((int) fixP
->fx_r_type
)
1576 case -BFD_RELOC_AVR_HI8_LDI_NEG
:
1577 case -BFD_RELOC_AVR_HI8_LDI
:
1578 case -BFD_RELOC_AVR_LO8_LDI_NEG
:
1579 case -BFD_RELOC_AVR_LO8_LDI
:
1580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1581 _("only constant expression allowed"));
1590 /* GAS will call this to generate a reloc, passing the resulting reloc
1591 to `bfd_install_relocation'. This currently works poorly, as
1592 `bfd_install_relocation' often does the wrong thing, and instances of
1593 `tc_gen_reloc' have been written to work around the problems, which
1594 in turns makes it difficult to fix `bfd_install_relocation'. */
1596 /* If while processing a fixup, a reloc really needs to be created
1597 then it is done here. */
1600 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
,
1605 if (fixp
->fx_subsy
!= NULL
)
1607 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
1611 reloc
= xmalloc (sizeof (arelent
));
1613 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
1614 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1616 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1617 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1618 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1620 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1621 _("reloc %d not supported by object file format"),
1622 (int) fixp
->fx_r_type
);
1626 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1627 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1628 reloc
->address
= fixp
->fx_offset
;
1630 reloc
->addend
= fixp
->fx_offset
;
1636 md_assemble (char *str
)
1638 struct avr_opcodes_s
*opcode
;
1641 str
= skip_space (extract_word (str
, op
, sizeof (op
)));
1644 as_bad (_("can't find opcode "));
1646 opcode
= (struct avr_opcodes_s
*) hash_find (avr_hash
, op
);
1648 if (opcode
&& !avr_opt
.all_opcodes
)
1650 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1651 specified by the user. If not look for other instructions
1652 specifications with same mnemonic who's ISA bits matches.
1654 This requires include/opcode/avr.h to have the instructions with
1655 same mnenomic to be specified in sequence. */
1657 while ((opcode
->isa
& avr_mcu
->isa
) != opcode
->isa
)
1661 if (opcode
->name
&& strcmp(op
, opcode
->name
))
1663 as_bad (_("illegal opcode %s for mcu %s"),
1664 opcode
->name
, avr_mcu
->name
);
1672 as_bad (_("unknown opcode `%s'"), op
);
1676 /* Special case for opcodes with optional operands (lpm, elpm) -
1677 version with operands exists in avr_opcodes[] in the next entry. */
1679 if (*str
&& *opcode
->constraints
== '?')
1682 dwarf2_emit_insn (0);
1684 /* We used to set input_line_pointer to the result of get_operands,
1685 but that is wrong. Our caller assumes we don't change it. */
1687 char *t
= input_line_pointer
;
1689 avr_operands (opcode
, &str
);
1690 if (*skip_space (str
))
1691 as_bad (_("garbage at end of line"));
1692 input_line_pointer
= t
;
1696 const exp_mod_data_t exp_mod_data
[] =
1698 /* Default, must be first. */
1699 { "", 0, BFD_RELOC_16
, "" },
1700 /* Divides by 2 to get word address. Generate Stub. */
1701 { "gs", 2, BFD_RELOC_AVR_16_PM
, "`gs' " },
1702 { "pm", 2, BFD_RELOC_AVR_16_PM
, "`pm' " },
1703 /* The following are used together with avr-gcc's __memx address space
1704 in order to initialize a 24-bit pointer variable with a 24-bit address.
1705 For address in flash, hlo8 will contain the flash segment if the
1706 symbol is located in flash. If the symbol is located in RAM; hlo8
1707 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1708 addresses linearize address space. */
1709 { "lo8", 1, BFD_RELOC_AVR_8_LO
, "`lo8' " },
1710 { "hi8", 1, BFD_RELOC_AVR_8_HI
, "`hi8' " },
1711 { "hlo8", 1, BFD_RELOC_AVR_8_HLO
, "`hlo8' " },
1712 { "hh8", 1, BFD_RELOC_AVR_8_HLO
, "`hh8' " },
1714 { NULL
, 0, 0, NULL
}
1717 /* Parse special CONS expression: pm (expression) or alternatively
1718 gs (expression). These are used for addressing program memory. Moreover,
1719 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1721 const exp_mod_data_t
*
1722 avr_parse_cons_expression (expressionS
*exp
, int nbytes
)
1724 const exp_mod_data_t
*pexp
= &exp_mod_data
[0];
1727 tmp
= input_line_pointer
= skip_space (input_line_pointer
);
1729 /* The first entry of exp_mod_data[] contains an entry if no
1730 expression modifier is present. Skip it. */
1732 for (pexp
++; pexp
->name
; pexp
++)
1734 int len
= strlen (pexp
->name
);
1736 if (nbytes
== pexp
->nbytes
1737 && strncasecmp (input_line_pointer
, pexp
->name
, len
) == 0)
1739 input_line_pointer
= skip_space (input_line_pointer
+ len
);
1741 if (*input_line_pointer
== '(')
1743 input_line_pointer
= skip_space (input_line_pointer
+ 1);
1746 if (*input_line_pointer
== ')')
1748 ++input_line_pointer
;
1753 as_bad (_("`)' required"));
1754 return &exp_mod_data
[0];
1758 input_line_pointer
= tmp
;
1765 return &exp_mod_data
[0];
1769 avr_cons_fix_new (fragS
*frag
,
1773 const exp_mod_data_t
*pexp_mod_data
)
1777 switch (pexp_mod_data
->reloc
)
1781 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_8
);
1782 else if (nbytes
== 2)
1783 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_16
);
1784 else if (nbytes
== 4)
1785 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_32
);
1790 case BFD_RELOC_AVR_16_PM
:
1791 case BFD_RELOC_AVR_8_LO
:
1792 case BFD_RELOC_AVR_8_HI
:
1793 case BFD_RELOC_AVR_8_HLO
:
1794 if (nbytes
== pexp_mod_data
->nbytes
)
1795 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, pexp_mod_data
->reloc
);
1802 as_bad (_("illegal %srelocation size: %d"), pexp_mod_data
->error
, nbytes
);
1806 mcu_has_3_byte_pc (void)
1808 int mach
= avr_mcu
->mach
;
1810 return mach
== bfd_mach_avr6
1811 || mach
== bfd_mach_avrxmega6
1812 || mach
== bfd_mach_avrxmega7
;
1816 tc_cfi_frame_initial_instructions (void)
1818 /* AVR6 pushes 3 bytes for calls. */
1819 int return_size
= (mcu_has_3_byte_pc () ? 3 : 2);
1821 /* The CFA is the caller's stack location before the call insn. */
1822 /* Note that the stack pointer is dwarf register number 32. */
1823 cfi_add_CFA_def_cfa (32, return_size
);
1825 /* Note that AVR consistently uses post-decrement, which means that things
1826 do not line up the same way as for targers that use pre-decrement. */
1827 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, 1-return_size
);
1831 avr_allow_local_subtract (expressionS
* left
,
1832 expressionS
* right
,
1835 /* If we are not in relaxation mode, subtraction is OK. */
1839 /* If the symbols are not in a code section then they are OK. */
1840 if ((section
->flags
& SEC_CODE
) == 0)
1843 if (left
->X_add_symbol
== right
->X_add_symbol
)
1846 /* We have to assume that there may be instructions between the
1847 two symbols and that relaxation may increase the distance between
1853 avr_elf_final_processing (void)
1856 elf_elfheader (stdoutput
)->e_flags
|= EF_AVR_LINKRELAX_PREPARED
;