gas/config/tc-bfin.c

   1 /* tc-bfin.c -- Assembler for the ADI Blackfin.
   2    Copyright 2005, 2006, 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "as.h"
  23 #include "struc-symbol.h"
  24 #include "bfin-defs.h"
  25 #include "obstack.h"
  26 #include "safe-ctype.h"
  27 #ifdef OBJ_ELF
  28 #include "dwarf2dbg.h"
  29 #endif
  30 #include "libbfd.h"
  31 #include "elf/common.h"
  32 #include "elf/bfin.h"
  33
  34 extern int yyparse (void);
  35 struct yy_buffer_state;
  36 typedef struct yy_buffer_state *YY_BUFFER_STATE;
  37 extern YY_BUFFER_STATE yy_scan_string (const char *yy_str);
  38 extern void yy_delete_buffer (YY_BUFFER_STATE b);
  39 static parse_state parse (char *line);
  40
  41 /* Global variables. */
  42 struct bfin_insn *insn;
  43 int last_insn_size;
  44
  45 extern struct obstack mempool;
  46 FILE *errorf;
  47
  48 /* Flags to set in the elf header */
  49 #define DEFAULT_FLAGS 0
  50
  51 #ifdef OBJ_FDPIC_ELF
  52 # define DEFAULT_FDPIC EF_BFIN_FDPIC
  53 #else
  54 # define DEFAULT_FDPIC 0
  55 #endif
  56
  57 static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
  58 static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
  59
  60 /* Registers list.  */
  61 struct bfin_reg_entry
  62 {
  63   const char *name;
  64   int number;
  65 };
  66
  67 static const struct bfin_reg_entry bfin_reg_info[] = {
  68   {"R0.L", REG_RL0},
  69   {"R1.L", REG_RL1},
  70   {"R2.L", REG_RL2},
  71   {"R3.L", REG_RL3},
  72   {"R4.L", REG_RL4},
  73   {"R5.L", REG_RL5},
  74   {"R6.L", REG_RL6},
  75   {"R7.L", REG_RL7},
  76   {"R0.H", REG_RH0},
  77   {"R1.H", REG_RH1},
  78   {"R2.H", REG_RH2},
  79   {"R3.H", REG_RH3},
  80   {"R4.H", REG_RH4},
  81   {"R5.H", REG_RH5},
  82   {"R6.H", REG_RH6},
  83   {"R7.H", REG_RH7},
  84   {"R0", REG_R0},
  85   {"R1", REG_R1},
  86   {"R2", REG_R2},
  87   {"R3", REG_R3},
  88   {"R4", REG_R4},
  89   {"R5", REG_R5},
  90   {"R6", REG_R6},
  91   {"R7", REG_R7},
  92   {"P0", REG_P0},
  93   {"P0.H", REG_P0},
  94   {"P0.L", REG_P0},
  95   {"P1", REG_P1},
  96   {"P1.H", REG_P1},
  97   {"P1.L", REG_P1},
  98   {"P2", REG_P2},
  99   {"P2.H", REG_P2},
 100   {"P2.L", REG_P2},
 101   {"P3", REG_P3},
 102   {"P3.H", REG_P3},
 103   {"P3.L", REG_P3},
 104   {"P4", REG_P4},
 105   {"P4.H", REG_P4},
 106   {"P4.L", REG_P4},
 107   {"P5", REG_P5},
 108   {"P5.H", REG_P5},
 109   {"P5.L", REG_P5},
 110   {"SP", REG_SP},
 111   {"SP.L", REG_SP},
 112   {"SP.H", REG_SP},
 113   {"FP", REG_FP},
 114   {"FP.L", REG_FP},
 115   {"FP.H", REG_FP},
 116   {"A0x", REG_A0x},
 117   {"A1x", REG_A1x},
 118   {"A0w", REG_A0w},
 119   {"A1w", REG_A1w},
 120   {"A0.x", REG_A0x},
 121   {"A1.x", REG_A1x},
 122   {"A0.w", REG_A0w},
 123   {"A1.w", REG_A1w},
 124   {"A0", REG_A0},
 125   {"A0.L", REG_A0},
 126   {"A0.H", REG_A0},
 127   {"A1", REG_A1},
 128   {"A1.L", REG_A1},
 129   {"A1.H", REG_A1},
 130   {"I0", REG_I0},
 131   {"I0.L", REG_I0},
 132   {"I0.H", REG_I0},
 133   {"I1", REG_I1},
 134   {"I1.L", REG_I1},
 135   {"I1.H", REG_I1},
 136   {"I2", REG_I2},
 137   {"I2.L", REG_I2},
 138   {"I2.H", REG_I2},
 139   {"I3", REG_I3},
 140   {"I3.L", REG_I3},
 141   {"I3.H", REG_I3},
 142   {"M0", REG_M0},
 143   {"M0.H", REG_M0},
 144   {"M0.L", REG_M0},
 145   {"M1", REG_M1},
 146   {"M1.H", REG_M1},
 147   {"M1.L", REG_M1},
 148   {"M2", REG_M2},
 149   {"M2.H", REG_M2},
 150   {"M2.L", REG_M2},
 151   {"M3", REG_M3},
 152   {"M3.H", REG_M3},
 153   {"M3.L", REG_M3},
 154   {"B0", REG_B0},
 155   {"B0.H", REG_B0},
 156   {"B0.L", REG_B0},
 157   {"B1", REG_B1},
 158   {"B1.H", REG_B1},
 159   {"B1.L", REG_B1},
 160   {"B2", REG_B2},
 161   {"B2.H", REG_B2},
 162   {"B2.L", REG_B2},
 163   {"B3", REG_B3},
 164   {"B3.H", REG_B3},
 165   {"B3.L", REG_B3},
 166   {"L0", REG_L0},
 167   {"L0.H", REG_L0},
 168   {"L0.L", REG_L0},
 169   {"L1", REG_L1},
 170   {"L1.H", REG_L1},
 171   {"L1.L", REG_L1},
 172   {"L2", REG_L2},
 173   {"L2.H", REG_L2},
 174   {"L2.L", REG_L2},
 175   {"L3", REG_L3},
 176   {"L3.H", REG_L3},
 177   {"L3.L", REG_L3},
 178   {"AZ", S_AZ},
 179   {"AN", S_AN},
 180   {"AC0", S_AC0},
 181   {"AC1", S_AC1},
 182   {"AV0", S_AV0},
 183   {"AV0S", S_AV0S},
 184   {"AV1", S_AV1},
 185   {"AV1S", S_AV1S},
 186   {"AQ", S_AQ},
 187   {"V", S_V},
 188   {"VS", S_VS},
 189   {"sftreset", REG_sftreset},
 190   {"omode", REG_omode},
 191   {"excause", REG_excause},
 192   {"emucause", REG_emucause},
 193   {"idle_req", REG_idle_req},
 194   {"hwerrcause", REG_hwerrcause},
 195   {"CC", REG_CC},
 196   {"LC0", REG_LC0},
 197   {"LC1", REG_LC1},
 198   {"ASTAT", REG_ASTAT},
 199   {"RETS", REG_RETS},
 200   {"LT0", REG_LT0},
 201   {"LB0", REG_LB0},
 202   {"LT1", REG_LT1},
 203   {"LB1", REG_LB1},
 204   {"CYCLES", REG_CYCLES},
 205   {"CYCLES2", REG_CYCLES2},
 206   {"USP", REG_USP},
 207   {"SEQSTAT", REG_SEQSTAT},
 208   {"SYSCFG", REG_SYSCFG},
 209   {"RETI", REG_RETI},
 210   {"RETX", REG_RETX},
 211   {"RETN", REG_RETN},
 212   {"RETE", REG_RETE},
 213   {"EMUDAT", REG_EMUDAT},
 214   {0, 0}
 215 };
 216
 217 /* Blackfin specific function to handle FD-PIC pointer initializations.  */
 218
 219 static void
 220 bfin_pic_ptr (int nbytes)
 221 {
 222   expressionS exp;
 223   char *p;
 224
 225   if (nbytes != 4)
 226     abort ();
 227
 228 #ifdef md_flush_pending_output
 229   md_flush_pending_output ();
 230 #endif
 231
 232   if (is_it_end_of_statement ())
 233     {
 234       demand_empty_rest_of_line ();
 235       return;
 236     }
 237
 238 #ifdef md_cons_align
 239   md_cons_align (nbytes);
 240 #endif
 241
 242   do
 243     {
 244       bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC;
 245
 246       if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
 247         {
 248           input_line_pointer += 9;
 249           expression (&exp);
 250           if (*input_line_pointer == ')')
 251             input_line_pointer++;
 252           else
 253             as_bad (_("missing ')'"));
 254         }
 255       else
 256         error ("missing funcdesc in picptr");
 257
 258       p = frag_more (4);
 259       memset (p, 0, 4);
 260       fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
 261                    reloc_type);
 262     }
 263   while (*input_line_pointer++ == ',');
 264
 265   input_line_pointer--;                 /* Put terminator back into stream. */
 266   demand_empty_rest_of_line ();
 267 }
 268
 269 static void
 270 bfin_s_bss (int ignore ATTRIBUTE_UNUSED)
 271 {
 272   register int temp;
 273
 274   temp = get_absolute_expression ();
 275   subseg_set (bss_section, (subsegT) temp);
 276   demand_empty_rest_of_line ();
 277 }
 278
 279 const pseudo_typeS md_pseudo_table[] = {
 280   {"align", s_align_bytes, 0},
 281   {"byte2", cons, 2},
 282   {"byte4", cons, 4},
 283   {"picptr", bfin_pic_ptr, 4},
 284   {"code", obj_elf_section, 0},
 285   {"db", cons, 1},
 286   {"dd", cons, 4},
 287   {"dw", cons, 2},
 288   {"p", s_ignore, 0},
 289   {"pdata", s_ignore, 0},
 290   {"var", s_ignore, 0},
 291   {"bss", bfin_s_bss, 0},
 292   {0, 0, 0}
 293 };
 294
 295 /* Characters that are used to denote comments and line separators. */
 296 const char comment_chars[] = "";
 297 const char line_comment_chars[] = "#";
 298 const char line_separator_chars[] = ";";
 299
 300 /* Characters that can be used to separate the mantissa from the
 301    exponent in floating point numbers. */
 302 const char EXP_CHARS[] = "eE";
 303
 304 /* Characters that mean this number is a floating point constant.
 305    As in 0f12.456 or  0d1.2345e12.  */
 306 const char FLT_CHARS[] = "fFdDxX";
 307
 308 typedef enum bfin_cpu_type
 309 {
 310   BFIN_CPU_UNKNOWN,
 311   BFIN_CPU_BF512,
 312   BFIN_CPU_BF514,
 313   BFIN_CPU_BF516,
 314   BFIN_CPU_BF518,
 315   BFIN_CPU_BF522,
 316   BFIN_CPU_BF523,
 317   BFIN_CPU_BF524,
 318   BFIN_CPU_BF525,
 319   BFIN_CPU_BF526,
 320   BFIN_CPU_BF527,
 321   BFIN_CPU_BF531,
 322   BFIN_CPU_BF532,
 323   BFIN_CPU_BF533,
 324   BFIN_CPU_BF534,
 325   BFIN_CPU_BF536,
 326   BFIN_CPU_BF537,
 327   BFIN_CPU_BF538,
 328   BFIN_CPU_BF539,
 329   BFIN_CPU_BF542,
 330   BFIN_CPU_BF542M,
 331   BFIN_CPU_BF544,
 332   BFIN_CPU_BF544M,
 333   BFIN_CPU_BF547,
 334   BFIN_CPU_BF547M,
 335   BFIN_CPU_BF548,
 336   BFIN_CPU_BF548M,
 337   BFIN_CPU_BF549,
 338   BFIN_CPU_BF549M,
 339   BFIN_CPU_BF561
 340 } bfin_cpu_t;
 341
 342 bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
 343 /* -msi-revision support. There are three special values:
 344    -1      -msi-revision=none.
 345    0xffff  -msi-revision=any.  */
 346 int bfin_si_revision;
 347
 348 unsigned int bfin_anomaly_checks = 0;
 349
 350 struct bfin_cpu
 351 {
 352   const char *name;
 353   bfin_cpu_t type;
 354   int si_revision;
 355   unsigned int anomaly_checks;
 356 };
 357
 358 struct bfin_cpu bfin_cpus[] =
 359 {
 360   {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
 361   {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
 362
 363   {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
 364   {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
 365
 366   {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
 367   {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
 368
 369   {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
 370   {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
 371
 372   {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074},
 373   {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074},
 374   {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074},
 375
 376   {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074},
 377   {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074},
 378   {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074},
 379
 380   {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074},
 381   {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074},
 382   {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074},
 383
 384   {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074},
 385   {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074},
 386   {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074},
 387
 388   {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074},
 389   {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074},
 390   {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074},
 391
 392   {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074},
 393   {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074},
 394   {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074},
 395
 396   {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074},
 397   {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074},
 398   {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074},
 399   {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074},
 400
 401   {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074},
 402   {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074},
 403   {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074},
 404   {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074},
 405
 406   {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074},
 407   {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074},
 408   {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074},
 409   {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074},
 410
 411   {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074},
 412   {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074},
 413   {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074},
 414
 415   {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074},
 416   {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074},
 417   {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074},
 418
 419   {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074},
 420   {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074},
 421   {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074},
 422
 423   {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074},
 424   {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074},
 425   {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074},
 426   {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074},
 427
 428   {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074},
 429   {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074},
 430   {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074},
 431   {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074},
 432
 433   {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
 434
 435   {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
 436   {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
 437   {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
 438
 439   {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
 440
 441   {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
 442   {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
 443   {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
 444
 445   {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
 446
 447   {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
 448   {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
 449   {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
 450
 451   {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
 452
 453   {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
 454   {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
 455   {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
 456
 457   {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
 458
 459   {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
 460   {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
 461   {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
 462
 463   {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074},
 464   {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
 465   {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
 466
 467   {NULL, 0, 0, 0}
 468 };
 469
 470 /* Define bfin-specific command-line options (there are none). */
 471 const char *md_shortopts = "";
 472
 473 #define OPTION_FDPIC            (OPTION_MD_BASE)
 474 #define OPTION_NOPIC            (OPTION_MD_BASE + 1)
 475 #define OPTION_MCPU             (OPTION_MD_BASE + 2)
 476
 477 struct option md_longopts[] =
 478 {
 479   { "mcpu",             required_argument,      NULL, OPTION_MCPU       },
 480   { "mfdpic",           no_argument,            NULL, OPTION_FDPIC      },
 481   { "mnopic",           no_argument,            NULL, OPTION_NOPIC      },
 482   { "mno-fdpic",        no_argument,            NULL, OPTION_NOPIC      },
 483   { NULL,               no_argument,            NULL, 0                 },
 484 };
 485
 486 size_t md_longopts_size = sizeof (md_longopts);
 487
 488
 489 int
 490 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
 491 {
 492   switch (c)
 493     {
 494     default:
 495       return 0;
 496
 497     case OPTION_MCPU:
 498       {
 499         const char *p, *q;
 500         int i;
 501
 502         i = 0;
 503         while ((p = bfin_cpus[i].name) != NULL)
 504           {
 505             if (strncmp (arg, p, strlen (p)) == 0)
 506               break;
 507             i++;
 508           }
 509
 510         if (p == NULL)
 511           {
 512             error ("-mcpu=%s is not valid", arg);
 513             return 0;
 514           }
 515
 516         bfin_cpu_type = bfin_cpus[i].type;
 517
 518         q = arg + strlen (p);
 519
 520         if (*q == '\0')
 521           {
 522             bfin_si_revision = bfin_cpus[i].si_revision;
 523             bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
 524           }
 525         else if (strcmp (q, "-none") == 0)
 526           bfin_si_revision = -1;
 527         else if (strcmp (q, "-any") == 0)
 528           {
 529             bfin_si_revision = 0xffff;
 530             while (bfin_cpus[i].type == bfin_cpu_type)
 531               {
 532                 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
 533                 i++;
 534               }
 535           }
 536         else
 537           {
 538             unsigned int si_major, si_minor;
 539             int rev_len, n;
 540
 541             rev_len = strlen (q);
 542
 543             if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
 544                 || n != rev_len
 545                 || si_major > 0xff || si_minor > 0xff)
 546               {
 547               invalid_silicon_revision:
 548                 error ("-mcpu=%s has invalid silicon revision", arg);
 549                 return 0;
 550               }
 551
 552             bfin_si_revision = (si_major << 8) | si_minor;
 553
 554             while (bfin_cpus[i].type == bfin_cpu_type
 555                    && bfin_cpus[i].si_revision != bfin_si_revision)
 556               i++;
 557
 558             if (bfin_cpus[i].type != bfin_cpu_type)
 559               goto invalid_silicon_revision;
 560
 561             bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
 562           }
 563
 564         break;
 565       }
 566
 567     case OPTION_FDPIC:
 568       bfin_flags |= EF_BFIN_FDPIC;
 569       bfin_pic_flag = "-mfdpic";
 570       break;
 571
 572     case OPTION_NOPIC:
 573       bfin_flags &= ~(EF_BFIN_FDPIC);
 574       bfin_pic_flag = 0;
 575       break;
 576     }
 577
 578   return 1;
 579 }
 580
 581 void
 582 md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
 583 {
 584   fprintf (stream, _(" BFIN specific command line options:\n"));
 585 }
 586
 587 /* Perform machine-specific initializations.  */
 588 void
 589 md_begin ()
 590 {
 591   /* Set the ELF flags if desired. */
 592   if (bfin_flags)
 593     bfd_set_private_flags (stdoutput, bfin_flags);
 594
 595   /* Set the default machine type. */
 596   if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0))
 597     as_warn (_("Could not set architecture and machine."));
 598
 599   /* Ensure that lines can begin with '(', for multiple
 600      register stack pops. */
 601   lex_type ['('] = LEX_BEGIN_NAME;
 602
 603 #ifdef OBJ_ELF
 604   record_alignment (text_section, 2);
 605   record_alignment (data_section, 2);
 606   record_alignment (bss_section, 2);
 607 #endif
 608
 609   errorf = stderr;
 610   obstack_init (&mempool);
 611
 612 #ifdef DEBUG
 613   extern int debug_codeselection;
 614   debug_codeselection = 1;
 615 #endif
 616
 617   last_insn_size = 0;
 618 }
 619
 620 /* Perform the main parsing, and assembly of the input here.  Also,
 621    call the required routines for alignment and fixups here.
 622    This is called for every line that contains real assembly code.  */
 623
 624 void
 625 md_assemble (char *line)
 626 {
 627   char *toP = 0;
 628   extern char *current_inputline;
 629   int size, insn_size;
 630   struct bfin_insn *tmp_insn;
 631   size_t len;
 632   static size_t buffer_len = 0;
 633   parse_state state;
 634
 635   len = strlen (line);
 636   if (len + 2 > buffer_len)
 637     {
 638       if (buffer_len > 0)
 639         free (current_inputline);
 640       buffer_len = len + 40;
 641       current_inputline = xmalloc (buffer_len);
 642     }
 643   memcpy (current_inputline, line, len);
 644   current_inputline[len] = ';';
 645   current_inputline[len + 1] = '\0';
 646
 647   state = parse (current_inputline);
 648   if (state == NO_INSN_GENERATED)
 649     return;
 650
 651   for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next)
 652     if (!tmp_insn->reloc || !tmp_insn->exp->symbol)
 653       insn_size += 2;
 654
 655   if (insn_size)
 656     toP = frag_more (insn_size);
 657
 658   last_insn_size = insn_size;
 659
 660 #ifdef DEBUG
 661   printf ("INS:");
 662 #endif
 663   while (insn)
 664     {
 665       if (insn->reloc && insn->exp->symbol)
 666         {
 667           char *prev_toP = toP - 2;
 668           switch (insn->reloc)
 669             {
 670             case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
 671             case BFD_RELOC_24_PCREL:
 672             case BFD_RELOC_BFIN_16_LOW:
 673             case BFD_RELOC_BFIN_16_HIGH:
 674               size = 4;
 675               break;
 676             default:
 677               size = 2;
 678             }
 679
 680           /* Following if condition checks for the arithmetic relocations.
 681              If the case then it doesn't required to generate the code.
 682              It has been assumed that, their ID will be contiguous.  */
 683           if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc
 684                && BFD_ARELOC_BFIN_COMP >= insn->reloc)
 685               || insn->reloc == BFD_RELOC_BFIN_16_IMM)
 686             {
 687               size = 2;
 688             }
 689           if (insn->reloc == BFD_ARELOC_BFIN_CONST
 690               || insn->reloc == BFD_ARELOC_BFIN_PUSH)
 691             size = 4;
 692
 693           fix_new (frag_now,
 694                    (prev_toP - frag_now->fr_literal),
 695                    size, insn->exp->symbol, insn->exp->value,
 696                    insn->pcrel, insn->reloc);
 697         }
 698       else
 699         {
 700           md_number_to_chars (toP, insn->value, 2);
 701           toP += 2;
 702         }
 703
 704 #ifdef DEBUG
 705       printf (" reloc :");
 706       printf (" %02x%02x", ((unsigned char *) &insn->value)[0],
 707               ((unsigned char *) &insn->value)[1]);
 708       printf ("\n");
 709 #endif
 710       insn = insn->next;
 711     }
 712 #ifdef OBJ_ELF
 713   dwarf2_emit_insn (insn_size);
 714 #endif
 715
 716   while (*line++ != '\0')
 717     if (*line == '\n')
 718       bump_line_counters ();
 719 }
 720
 721 /* Parse one line of instructions, and generate opcode for it.
 722    To parse the line, YACC and LEX are used, because the instruction set
 723    syntax doesn't confirm to the AT&T assembly syntax.
 724    To call a YACC & LEX generated parser, we must provide the input via
 725    a FILE stream, otherwise stdin is used by default.  Below the input
 726    to the function will be put into a temporary file, then the generated
 727    parser uses the temporary file for parsing.  */
 728
 729 static parse_state
 730 parse (char *line)
 731 {
 732   parse_state state;
 733   YY_BUFFER_STATE buffstate;
 734
 735   buffstate = yy_scan_string (line);
 736
 737   /* our lex requires setting the start state to keyword
 738      every line as the first word may be a keyword.
 739      Fixes a bug where we could not have keywords as labels.  */
 740   set_start_state ();
 741
 742   /* Call yyparse here.  */
 743   state = yyparse ();
 744   if (state == SEMANTIC_ERROR)
 745     {
 746       as_bad (_("Parse failed."));
 747       insn = 0;
 748     }
 749
 750   yy_delete_buffer (buffstate);
 751   return state;
 752 }
 753
 754 /* We need to handle various expressions properly.
 755    Such as, [SP--] = 34, concerned by md_assemble().  */
 756
 757 void
 758 md_operand (expressionS * expressionP)
 759 {
 760   if (*input_line_pointer == '[')
 761     {
 762       as_tsktsk ("We found a '['!");
 763       input_line_pointer++;
 764       expression (expressionP);
 765     }
 766 }
 767
 768 /* Handle undefined symbols. */
 769 symbolS *
 770 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 771 {
 772   return (symbolS *) 0;
 773 }
 774
 775 int
 776 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
 777                                segT segment ATTRIBUTE_UNUSED)
 778 {
 779   return 0;
 780 }
 781
 782 /* Convert from target byte order to host byte order.  */
 783
 784 static int
 785 md_chars_to_number (char *val, int n)
 786 {
 787   int retval;
 788
 789   for (retval = 0; n--;)
 790     {
 791       retval <<= 8;
 792       retval |= val[n];
 793     }
 794   return retval;
 795 }
 796
 797 void
 798 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
 799 {
 800   char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
 801
 802   long value = *valueP;
 803   long newval;
 804
 805   switch (fixP->fx_r_type)
 806     {
 807     case BFD_RELOC_BFIN_GOT:
 808     case BFD_RELOC_BFIN_GOT17M4:
 809     case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
 810       fixP->fx_no_overflow = 1;
 811       newval = md_chars_to_number (where, 2);
 812       newval |= 0x0 & 0x7f;
 813       md_number_to_chars (where, newval, 2);
 814       break;
 815
 816     case BFD_RELOC_BFIN_10_PCREL:
 817       if (!value)
 818         break;
 819       if (value < -1024 || value > 1022)
 820         as_bad_where (fixP->fx_file, fixP->fx_line,
 821                       _("pcrel too far BFD_RELOC_BFIN_10"));
 822
 823       /* 11 bit offset even numbered, so we remove right bit.  */
 824       value = value >> 1;
 825       newval = md_chars_to_number (where, 2);
 826       newval |= value & 0x03ff;
 827       md_number_to_chars (where, newval, 2);
 828       break;
 829
 830     case BFD_RELOC_BFIN_12_PCREL_JUMP:
 831     case BFD_RELOC_BFIN_12_PCREL_JUMP_S:
 832     case BFD_RELOC_12_PCREL:
 833       if (!value)
 834         break;
 835
 836       if (value < -4096 || value > 4094)
 837         as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_12"));
 838       /* 13 bit offset even numbered, so we remove right bit.  */
 839       value = value >> 1;
 840       newval = md_chars_to_number (where, 2);
 841       newval |= value & 0xfff;
 842       md_number_to_chars (where, newval, 2);
 843       break;
 844
 845     case BFD_RELOC_BFIN_16_LOW:
 846     case BFD_RELOC_BFIN_16_HIGH:
 847       fixP->fx_done = FALSE;
 848       break;
 849
 850     case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
 851     case BFD_RELOC_BFIN_24_PCREL_CALL_X:
 852     case BFD_RELOC_24_PCREL:
 853       if (!value)
 854         break;
 855
 856       if (value < -16777216 || value > 16777214)
 857         as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_24"));
 858
 859       /* 25 bit offset even numbered, so we remove right bit.  */
 860       value = value >> 1;
 861       value++;
 862
 863       md_number_to_chars (where - 2, value >> 16, 1);
 864       md_number_to_chars (where, value, 1);
 865       md_number_to_chars (where + 1, value >> 8, 1);
 866       break;
 867
 868     case BFD_RELOC_BFIN_5_PCREL:        /* LSETUP (a, b) : "a" */
 869       if (!value)
 870         break;
 871       if (value < 4 || value > 30)
 872         as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_5"));
 873       value = value >> 1;
 874       newval = md_chars_to_number (where, 1);
 875       newval = (newval & 0xf0) | (value & 0xf);
 876       md_number_to_chars (where, newval, 1);
 877       break;
 878
 879     case BFD_RELOC_BFIN_11_PCREL:       /* LSETUP (a, b) : "b" */
 880       if (!value)
 881         break;
 882       value += 2;
 883       if (value < 4 || value > 2046)
 884         as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_11_PCREL"));
 885       /* 11 bit unsigned even, so we remove right bit.  */
 886       value = value >> 1;
 887       newval = md_chars_to_number (where, 2);
 888       newval |= value & 0x03ff;
 889       md_number_to_chars (where, newval, 2);
 890       break;
 891
 892     case BFD_RELOC_8:
 893       if (value < -0x80 || value >= 0x7f)
 894         as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_8"));
 895       md_number_to_chars (where, value, 1);
 896       break;
 897
 898     case BFD_RELOC_BFIN_16_IMM:
 899     case BFD_RELOC_16:
 900       if (value < -0x8000 || value >= 0x7fff)
 901         as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16"));
 902       md_number_to_chars (where, value, 2);
 903       break;
 904
 905     case BFD_RELOC_32:
 906       md_number_to_chars (where, value, 4);
 907       break;
 908
 909     case BFD_RELOC_BFIN_PLTPC:
 910       md_number_to_chars (where, value, 2);
 911       break;
 912
 913     case BFD_RELOC_BFIN_FUNCDESC:
 914     case BFD_RELOC_VTABLE_INHERIT:
 915     case BFD_RELOC_VTABLE_ENTRY:
 916       fixP->fx_done = FALSE;
 917       break;
 918
 919     default:
 920       if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type))
 921         {
 922           fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type);
 923           return;
 924         }
 925     }
 926
 927   if (!fixP->fx_addsy)
 928     fixP->fx_done = TRUE;
 929
 930 }
 931
 932 /* Round up a section size to the appropriate boundary.  */
 933 valueT
 934 md_section_align (segment, size)
 935      segT segment;
 936      valueT size;
 937 {
 938   int boundary = bfd_get_section_alignment (stdoutput, segment);
 939   return ((size + (1 << boundary) - 1) & (-1 << boundary));
 940 }
 941
 942
 943 char *
 944 md_atof (int type, char * litP, int * sizeP)
 945 {
 946   return ieee_md_atof (type, litP, sizeP, FALSE);
 947 }
 948
 949
 950 /* If while processing a fixup, a reloc really needs to be created
 951    then it is done here.  */
 952
 953 arelent *
 954 tc_gen_reloc (seg, fixp)
 955      asection *seg ATTRIBUTE_UNUSED;
 956      fixS *fixp;
 957 {
 958   arelent *reloc;
 959
 960   reloc               = (arelent *) xmalloc (sizeof (arelent));
 961   reloc->sym_ptr_ptr  = (asymbol **) xmalloc (sizeof (asymbol *));
 962   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 963   reloc->address      = fixp->fx_frag->fr_address + fixp->fx_where;
 964
 965   reloc->addend = fixp->fx_offset;
 966   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
 967
 968   if (reloc->howto == (reloc_howto_type *) NULL)
 969     {
 970       as_bad_where (fixp->fx_file, fixp->fx_line,
 971                     /* xgettext:c-format.  */
 972                     _("reloc %d not supported by object file format"),
 973                     (int) fixp->fx_r_type);
 974
 975       xfree (reloc);
 976
 977       return NULL;
 978     }
 979
 980   return reloc;
 981 }
 982
 983 /*  The location from which a PC relative jump should be calculated,
 984     given a PC relative reloc.  */
 985
 986 long
 987 md_pcrel_from_section (fixP, sec)
 988      fixS *fixP;
 989      segT sec;
 990 {
 991   if (fixP->fx_addsy != (symbolS *) NULL
 992       && (!S_IS_DEFINED (fixP->fx_addsy)
 993       || S_GET_SEGMENT (fixP->fx_addsy) != sec))
 994     {
 995       /* The symbol is undefined (or is defined but not in this section).
 996          Let the linker figure it out.  */
 997       return 0;
 998     }
 999   return fixP->fx_frag->fr_address + fixP->fx_where;
1000 }
1001
1002 /* Return true if the fix can be handled by GAS, false if it must
1003    be passed through to the linker.  */
1004
1005 bfd_boolean
1006 bfin_fix_adjustable (fixS *fixP)
1007 {
1008   switch (fixP->fx_r_type)
1009     {
1010   /* Adjust_reloc_syms doesn't know about the GOT.  */
1011     case BFD_RELOC_BFIN_GOT:
1012     case BFD_RELOC_BFIN_PLTPC:
1013   /* We need the symbol name for the VTABLE entries.  */
1014     case BFD_RELOC_VTABLE_INHERIT:
1015     case BFD_RELOC_VTABLE_ENTRY:
1016       return 0;
1017
1018     default:
1019       return 1;
1020     }
1021 }
1022
1023 /* Special extra functions that help bfin-parse.y perform its job.  */
1024
1025 struct obstack mempool;
1026
1027 INSTR_T
1028 conscode (INSTR_T head, INSTR_T tail)
1029 {
1030   if (!head)
1031     return tail;
1032   head->next = tail;
1033   return head;
1034 }
1035
1036 INSTR_T
1037 conctcode (INSTR_T head, INSTR_T tail)
1038 {
1039   INSTR_T temp = (head);
1040   if (!head)
1041     return tail;
1042   while (temp->next)
1043     temp = temp->next;
1044   temp->next = tail;
1045
1046   return head;
1047 }
1048
1049 INSTR_T
1050 note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel)
1051 {
1052   /* Assert that the symbol is not an operator.  */
1053   gas_assert (symbol->type == Expr_Node_Reloc);
1054
1055   return note_reloc1 (code, symbol->value.s_value, reloc, pcrel);
1056
1057 }
1058
1059 INSTR_T
1060 note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel)
1061 {
1062   code->reloc = reloc;
1063   code->exp = mkexpr (0, symbol_find_or_make (symbol));
1064   code->pcrel = pcrel;
1065   return code;
1066 }
1067
1068 INSTR_T
1069 note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel)
1070 {
1071   code->reloc = reloc;
1072   code->exp = mkexpr (value, symbol_find_or_make (symbol));
1073   code->pcrel = pcrel;
1074   return code;
1075 }
1076
1077 INSTR_T
1078 gencode (unsigned long x)
1079 {
1080   INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn));
1081   memset (cell, 0, sizeof (struct bfin_insn));
1082   cell->value = (x);
1083   return cell;
1084 }
1085
1086 int reloc;
1087 int ninsns;
1088 int count_insns;
1089
1090 static void *
1091 allocate (int n)
1092 {
1093   return obstack_alloc (&mempool, n);
1094 }
1095
1096 Expr_Node *
1097 Expr_Node_Create (Expr_Node_Type type,
1098                   Expr_Node_Value value,
1099                   Expr_Node *Left_Child,
1100                   Expr_Node *Right_Child)
1101 {
1102
1103
1104   Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node));
1105   node->type = type;
1106   node->value = value;
1107   node->Left_Child = Left_Child;
1108   node->Right_Child = Right_Child;
1109   return node;
1110 }
1111
1112 static const char *con = ".__constant";
1113 static const char *op = ".__operator";
1114 static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head);
1115 INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
1116
1117 INSTR_T
1118 Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
1119 {
1120   /* Top level reloction expression generator VDSP style.
1121    If the relocation is just by itself, generate one item
1122    else generate this convoluted expression.  */
1123
1124   INSTR_T note = NULL_CODE;
1125   INSTR_T note1 = NULL_CODE;
1126   int pcrel = 1;  /* Is the parent reloc pcrelative?
1127                   This calculation here and HOWTO should match.  */
1128
1129   if (parent_reloc)
1130     {
1131       /*  If it's 32 bit quantity then 16bit code needs to be added.  */
1132       int value = 0;
1133
1134       if (head->type == Expr_Node_Constant)
1135         {
1136           /* If note1 is not null code, we have to generate a right
1137              aligned value for the constant. Otherwise the reloc is
1138              a part of the basic command and the yacc file
1139              generates this.  */
1140           value = head->value.i_value;
1141         }
1142       switch (parent_reloc)
1143         {
1144           /*  Some relocations will need to allocate extra words.  */
1145         case BFD_RELOC_BFIN_16_IMM:
1146         case BFD_RELOC_BFIN_16_LOW:
1147         case BFD_RELOC_BFIN_16_HIGH:
1148           note1 = conscode (gencode (value), NULL_CODE);
1149           pcrel = 0;
1150           break;
1151         case BFD_RELOC_BFIN_PLTPC:
1152           note1 = conscode (gencode (value), NULL_CODE);
1153           pcrel = 0;
1154           break;
1155         case BFD_RELOC_16:
1156         case BFD_RELOC_BFIN_GOT:
1157         case BFD_RELOC_BFIN_GOT17M4:
1158         case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
1159           note1 = conscode (gencode (value), NULL_CODE);
1160           pcrel = 0;
1161           break;
1162         case BFD_RELOC_24_PCREL:
1163         case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
1164         case BFD_RELOC_BFIN_24_PCREL_CALL_X:
1165           /* These offsets are even numbered pcrel.  */
1166           note1 = conscode (gencode (value >> 1), NULL_CODE);
1167           break;
1168         default:
1169           note1 = NULL_CODE;
1170         }
1171     }
1172   if (head->type == Expr_Node_Constant)
1173     note = note1;
1174   else if (head->type == Expr_Node_Reloc)
1175     {
1176       note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel);
1177       if (note1 != NULL_CODE)
1178         note = conscode (note1, note);
1179     }
1180   else if (head->type == Expr_Node_Binop
1181            && (head->value.op_value == Expr_Op_Type_Add
1182                || head->value.op_value == Expr_Op_Type_Sub)
1183            && head->Left_Child->type == Expr_Node_Reloc
1184            && head->Right_Child->type == Expr_Node_Constant)
1185     {
1186       int val = head->Right_Child->value.i_value;
1187       if (head->value.op_value == Expr_Op_Type_Sub)
1188         val = -val;
1189       note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value,
1190                                     parent_reloc, val, 0),
1191                        NULL_CODE);
1192       if (note1 != NULL_CODE)
1193         note = conscode (note1, note);
1194     }
1195   else
1196     {
1197       /* Call the recursive function.  */
1198       note = note_reloc1 (gencode (0), op, parent_reloc, pcrel);
1199       if (note1 != NULL_CODE)
1200         note = conscode (note1, note);
1201       note = conctcode (Expr_Node_Gen_Reloc_R (head), note);
1202     }
1203   return note;
1204 }
1205
1206 static INSTR_T
1207 Expr_Node_Gen_Reloc_R (Expr_Node * head)
1208 {
1209
1210   INSTR_T note = 0;
1211   INSTR_T note1 = 0;
1212
1213   switch (head->type)
1214     {
1215     case Expr_Node_Constant:
1216       note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE);
1217       break;
1218     case Expr_Node_Reloc:
1219       note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE);
1220       break;
1221     case Expr_Node_Binop:
1222       note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child));
1223       switch (head->value.op_value)
1224         {
1225         case Expr_Op_Type_Add:
1226           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE));
1227           break;
1228         case Expr_Op_Type_Sub:
1229           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE));
1230           break;
1231         case Expr_Op_Type_Mult:
1232           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE));
1233           break;
1234         case Expr_Op_Type_Div:
1235           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE));
1236           break;
1237         case Expr_Op_Type_Mod:
1238           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE));
1239           break;
1240         case Expr_Op_Type_Lshift:
1241           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE));
1242           break;
1243         case Expr_Op_Type_Rshift:
1244           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE));
1245           break;
1246         case Expr_Op_Type_BAND:
1247           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE));
1248           break;
1249         case Expr_Op_Type_BOR:
1250           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE));
1251           break;
1252         case Expr_Op_Type_BXOR:
1253           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE));
1254           break;
1255         case Expr_Op_Type_LAND:
1256           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE));
1257           break;
1258         case Expr_Op_Type_LOR:
1259           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE));
1260           break;
1261         default:
1262           fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1263
1264
1265         }
1266       break;
1267     case Expr_Node_Unop:
1268       note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE);
1269       switch (head->value.op_value)
1270         {
1271         case Expr_Op_Type_NEG:
1272           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE));
1273           break;
1274         case Expr_Op_Type_COMP:
1275           note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE));
1276           break;
1277         default:
1278           fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1279         }
1280       break;
1281     default:
1282       fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__);
1283     }
1284   return note;
1285 }
1286 \f
1287 /* Blackfin opcode generation.  */
1288
1289 /* These functions are called by the generated parser
1290    (from bfin-parse.y), the register type classification
1291    happens in bfin-lex.l.  */
1292
1293 #include "bfin-aux.h"
1294 #include "opcode/bfin.h"
1295
1296 #define INIT(t)  t c_code = init_##t
1297 #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
1298 #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
1299
1300 #define HI(x) ((x >> 16) & 0xffff)
1301 #define LO(x) ((x      ) & 0xffff)
1302
1303 #define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
1304
1305 #define GEN_OPCODE32()  \
1306         conscode (gencode (HI (c_code.opcode)), \
1307         conscode (gencode (LO (c_code.opcode)), NULL_CODE))
1308
1309 #define GEN_OPCODE16()  \
1310         conscode (gencode (c_code.opcode), NULL_CODE)
1311
1312
1313 /*  32 BIT INSTRUCTIONS.  */
1314
1315
1316 /* DSP32 instruction generation.  */
1317
1318 INSTR_T
1319 bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P,
1320                    int h01, int h11, int h00, int h10, int op0,
1321                    REG_T dst, REG_T src0, REG_T src1, int w0)
1322 {
1323   INIT (DSP32Mac);
1324
1325   ASSIGN (op0);
1326   ASSIGN (op1);
1327   ASSIGN (MM);
1328   ASSIGN (mmod);
1329   ASSIGN (w0);
1330   ASSIGN (w1);
1331   ASSIGN (h01);
1332   ASSIGN (h11);
1333   ASSIGN (h00);
1334   ASSIGN (h10);
1335   ASSIGN (P);
1336
1337   /* If we have full reg assignments, mask out LSB to encode
1338   single or simultaneous even/odd register moves.  */
1339   if (P)
1340     {
1341       dst->regno &= 0x06;
1342     }
1343
1344   ASSIGN_R (dst);
1345   ASSIGN_R (src0);
1346   ASSIGN_R (src1);
1347
1348   return GEN_OPCODE32 ();
1349 }
1350
1351 INSTR_T
1352 bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P,
1353                     int h01, int h11, int h00, int h10, int op0,
1354                     REG_T dst, REG_T src0, REG_T src1, int w0)
1355 {
1356   INIT (DSP32Mult);
1357
1358   ASSIGN (op0);
1359   ASSIGN (op1);
1360   ASSIGN (MM);
1361   ASSIGN (mmod);
1362   ASSIGN (w0);
1363   ASSIGN (w1);
1364   ASSIGN (h01);
1365   ASSIGN (h11);
1366   ASSIGN (h00);
1367   ASSIGN (h10);
1368   ASSIGN (P);
1369
1370   if (P)
1371     {
1372       dst->regno &= 0x06;
1373     }
1374
1375   ASSIGN_R (dst);
1376   ASSIGN_R (src0);
1377   ASSIGN_R (src1);
1378
1379   return GEN_OPCODE32 ();
1380 }
1381
1382 INSTR_T
1383 bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,
1384               REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1385 {
1386   INIT (DSP32Alu);
1387
1388   ASSIGN (HL);
1389   ASSIGN (aopcde);
1390   ASSIGN (aop);
1391   ASSIGN (s);
1392   ASSIGN (x);
1393   ASSIGN_R (dst0);
1394   ASSIGN_R (dst1);
1395   ASSIGN_R (src0);
1396   ASSIGN_R (src1);
1397
1398   return GEN_OPCODE32 ();
1399 }
1400
1401 INSTR_T
1402 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1403                 REG_T src1, int sop, int HLs)
1404 {
1405   INIT (DSP32Shift);
1406
1407   ASSIGN (sopcde);
1408   ASSIGN (sop);
1409   ASSIGN (HLs);
1410
1411   ASSIGN_R (dst0);
1412   ASSIGN_R (src0);
1413   ASSIGN_R (src1);
1414
1415   return GEN_OPCODE32 ();
1416 }
1417
1418 INSTR_T
1419 bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag,
1420                    REG_T src1, int sop, int HLs)
1421 {
1422   INIT (DSP32ShiftImm);
1423
1424   ASSIGN (sopcde);
1425   ASSIGN (sop);
1426   ASSIGN (HLs);
1427
1428   ASSIGN_R (dst0);
1429   ASSIGN (immag);
1430   ASSIGN_R (src1);
1431
1432   return GEN_OPCODE32 ();
1433 }
1434
1435 /* LOOP SETUP.  */
1436
1437 INSTR_T
1438 bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop,
1439                Expr_Node * peoffset, REG_T reg)
1440 {
1441   int soffset, eoffset;
1442   INIT (LoopSetup);
1443
1444   soffset = (EXPR_VALUE (psoffset) >> 1);
1445   ASSIGN (soffset);
1446   eoffset = (EXPR_VALUE (peoffset) >> 1);
1447   ASSIGN (eoffset);
1448   ASSIGN (rop);
1449   ASSIGN_R (c);
1450   ASSIGN_R (reg);
1451
1452   return
1453       conscode (gencode (HI (c_code.opcode)),
1454                 conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL),
1455                            conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL))));
1456
1457 }
1458
1459 /*  Call, Link.  */
1460
1461 INSTR_T
1462 bfin_gen_calla (Expr_Node * addr, int S)
1463 {
1464   int val;
1465   int high_val;
1466   int reloc = 0;
1467   INIT (CALLa);
1468
1469   switch(S){
1470    case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
1471    case 1 : reloc = BFD_RELOC_24_PCREL; break;
1472    case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
1473    default : break;
1474   }
1475
1476   ASSIGN (S);
1477
1478   val = EXPR_VALUE (addr) >> 1;
1479   high_val = val >> 16;
1480
1481   return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
1482                      Expr_Node_Gen_Reloc (addr, reloc));
1483   }
1484
1485 INSTR_T
1486 bfin_gen_linkage (int R, int framesize)
1487 {
1488   INIT (Linkage);
1489
1490   ASSIGN (R);
1491   ASSIGN (framesize);
1492
1493   return GEN_OPCODE32 ();
1494 }
1495
1496
1497 /* Load and Store.  */
1498
1499 INSTR_T
1500 bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc)
1501 {
1502   int grp, hword;
1503   unsigned val = EXPR_VALUE (phword);
1504   INIT (LDIMMhalf);
1505
1506   ASSIGN (H);
1507   ASSIGN (S);
1508   ASSIGN (Z);
1509
1510   ASSIGN_R (reg);
1511   grp = (GROUP (reg));
1512   ASSIGN (grp);
1513   if (reloc == 2)
1514     {
1515       return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
1516     }
1517   else if (reloc == 1)
1518     {
1519       return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
1520     }
1521   else
1522     {
1523       hword = val;
1524       ASSIGN (hword);
1525     }
1526   return GEN_OPCODE32 ();
1527 }
1528
1529 INSTR_T
1530 bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset)
1531 {
1532   INIT (LDSTidxI);
1533
1534   if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1535     {
1536       fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1537       return 0;
1538     }
1539
1540   ASSIGN_R (ptr);
1541   ASSIGN_R (reg);
1542   ASSIGN (W);
1543   ASSIGN (sz);
1544
1545   ASSIGN (Z);
1546
1547   if (poffset->type != Expr_Node_Constant)
1548     {
1549       /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
1550       /* distinguish between R0 = [P5 + symbol@GOT] and
1551          P5 = [P5 + _current_shared_library_p5_offset_]
1552       */
1553       if (poffset->type == Expr_Node_Reloc
1554           && !strcmp (poffset->value.s_value,
1555                       "_current_shared_library_p5_offset_"))
1556         {
1557           return  conscode (gencode (HI (c_code.opcode)),
1558                             Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16));
1559         }
1560       else if (poffset->type != Expr_Node_GOT_Reloc)
1561         abort ();
1562
1563       return conscode (gencode (HI (c_code.opcode)),
1564                        Expr_Node_Gen_Reloc(poffset->Left_Child,
1565                                            poffset->value.i_value));
1566     }
1567   else
1568     {
1569       int value, offset;
1570       switch (sz)
1571         {                               /* load/store access size */
1572         case 0:                 /* 32 bit */
1573           value = EXPR_VALUE (poffset) >> 2;
1574           break;
1575         case 1:                 /* 16 bit */
1576           value = EXPR_VALUE (poffset) >> 1;
1577           break;
1578         case 2:                 /* 8 bit */
1579           value = EXPR_VALUE (poffset);
1580           break;
1581         default:
1582           abort ();
1583         }
1584
1585       offset = (value & 0xffff);
1586       ASSIGN (offset);
1587       return GEN_OPCODE32 ();
1588     }
1589 }
1590
1591
1592 INSTR_T
1593 bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W)
1594 {
1595   INIT (LDST);
1596
1597   if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1598     {
1599       fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1600       return 0;
1601     }
1602
1603   ASSIGN_R (ptr);
1604   ASSIGN_R (reg);
1605   ASSIGN (aop);
1606   ASSIGN (sz);
1607   ASSIGN (Z);
1608   ASSIGN (W);
1609
1610   return GEN_OPCODE16 ();
1611 }
1612
1613 INSTR_T
1614 bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op)
1615 {
1616   int offset;
1617   int value = 0;
1618   INIT (LDSTii);
1619
1620
1621   if (!IS_PREG (*ptr))
1622     {
1623       fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1624       return 0;
1625     }
1626
1627   switch (op)
1628     {
1629     case 1:
1630     case 2:
1631       value = EXPR_VALUE (poffset) >> 1;
1632       break;
1633     case 0:
1634     case 3:
1635       value = EXPR_VALUE (poffset) >> 2;
1636       break;
1637     }
1638
1639   ASSIGN_R (ptr);
1640   ASSIGN_R (reg);
1641
1642   offset = value;
1643   ASSIGN (offset);
1644   ASSIGN (W);
1645   ASSIGN (op);
1646
1647   return GEN_OPCODE16 ();
1648 }
1649
1650 INSTR_T
1651 bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W)
1652 {
1653   /* Set bit 4 if it's a Preg.  */
1654   int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0);
1655   int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1;
1656   INIT (LDSTiiFP);
1657   ASSIGN (reg);
1658   ASSIGN (offset);
1659   ASSIGN (W);
1660
1661   return GEN_OPCODE16 ();
1662 }
1663
1664 INSTR_T
1665 bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx)
1666 {
1667   INIT (LDSTpmod);
1668
1669   ASSIGN_R (ptr);
1670   ASSIGN_R (reg);
1671   ASSIGN (aop);
1672   ASSIGN (W);
1673   ASSIGN_R (idx);
1674
1675   return GEN_OPCODE16 ();
1676 }
1677
1678 INSTR_T
1679 bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m)
1680 {
1681   INIT (DspLDST);
1682
1683   ASSIGN_R (i);
1684   ASSIGN_R (reg);
1685   ASSIGN (aop);
1686   ASSIGN (W);
1687   ASSIGN (m);
1688
1689   return GEN_OPCODE16 ();
1690 }
1691
1692 INSTR_T
1693 bfin_gen_logi2op (int opc, int src, int dst)
1694 {
1695   INIT (LOGI2op);
1696
1697   ASSIGN (opc);
1698   ASSIGN (src);
1699   ASSIGN (dst);
1700
1701   return GEN_OPCODE16 ();
1702 }
1703
1704 INSTR_T
1705 bfin_gen_brcc (int T, int B, Expr_Node * poffset)
1706 {
1707   int offset;
1708   INIT (BRCC);
1709
1710   ASSIGN (T);
1711   ASSIGN (B);
1712   offset = ((EXPR_VALUE (poffset) >> 1));
1713   ASSIGN (offset);
1714   return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL));
1715 }
1716
1717 INSTR_T
1718 bfin_gen_ujump (Expr_Node * poffset)
1719 {
1720   int offset;
1721   INIT (UJump);
1722
1723   offset = ((EXPR_VALUE (poffset) >> 1));
1724   ASSIGN (offset);
1725
1726   return conscode (gencode (c_code.opcode),
1727                    Expr_Node_Gen_Reloc (
1728                        poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S));
1729 }
1730
1731 INSTR_T
1732 bfin_gen_alu2op (REG_T dst, REG_T src, int opc)
1733 {
1734   INIT (ALU2op);
1735
1736   ASSIGN_R (dst);
1737   ASSIGN_R (src);
1738   ASSIGN (opc);
1739
1740   return GEN_OPCODE16 ();
1741 }
1742
1743 INSTR_T
1744 bfin_gen_compi2opd (REG_T dst, int src, int op)
1745 {
1746   INIT (COMPI2opD);
1747
1748   ASSIGN_R (dst);
1749   ASSIGN (src);
1750   ASSIGN (op);
1751
1752   return GEN_OPCODE16 ();
1753 }
1754
1755 INSTR_T
1756 bfin_gen_compi2opp (REG_T dst, int src, int op)
1757 {
1758   INIT (COMPI2opP);
1759
1760   ASSIGN_R (dst);
1761   ASSIGN (src);
1762   ASSIGN (op);
1763
1764   return GEN_OPCODE16 ();
1765 }
1766
1767 INSTR_T
1768 bfin_gen_dagmodik (REG_T i, int op)
1769 {
1770   INIT (DagMODik);
1771
1772   ASSIGN_R (i);
1773   ASSIGN (op);
1774
1775   return GEN_OPCODE16 ();
1776 }
1777
1778 INSTR_T
1779 bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
1780 {
1781   INIT (DagMODim);
1782
1783   ASSIGN_R (i);
1784   ASSIGN_R (m);
1785   ASSIGN (op);
1786   ASSIGN (br);
1787
1788   return GEN_OPCODE16 ();
1789 }
1790
1791 INSTR_T
1792 bfin_gen_ptr2op (REG_T dst, REG_T src, int opc)
1793 {
1794   INIT (PTR2op);
1795
1796   ASSIGN_R (dst);
1797   ASSIGN_R (src);
1798   ASSIGN (opc);
1799
1800   return GEN_OPCODE16 ();
1801 }
1802
1803 INSTR_T
1804 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1805 {
1806   INIT (COMP3op);
1807
1808   ASSIGN_R (src0);
1809   ASSIGN_R (src1);
1810   ASSIGN_R (dst);
1811   ASSIGN (opc);
1812
1813   return GEN_OPCODE16 ();
1814 }
1815
1816 INSTR_T
1817 bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G)
1818 {
1819   INIT (CCflag);
1820
1821   ASSIGN_R (x);
1822   ASSIGN (y);
1823   ASSIGN (opc);
1824   ASSIGN (I);
1825   ASSIGN (G);
1826
1827   return GEN_OPCODE16 ();
1828 }
1829
1830 INSTR_T
1831 bfin_gen_ccmv (REG_T src, REG_T dst, int T)
1832 {
1833   int s, d;
1834   INIT (CCmv);
1835
1836   ASSIGN_R (src);
1837   ASSIGN_R (dst);
1838   s = (GROUP (src));
1839   ASSIGN (s);
1840   d = (GROUP (dst));
1841   ASSIGN (d);
1842   ASSIGN (T);
1843
1844   return GEN_OPCODE16 ();
1845 }
1846
1847 INSTR_T
1848 bfin_gen_cc2stat (int cbit, int op, int D)
1849 {
1850   INIT (CC2stat);
1851
1852   ASSIGN (cbit);
1853   ASSIGN (op);
1854   ASSIGN (D);
1855
1856   return GEN_OPCODE16 ();
1857 }
1858
1859 INSTR_T
1860 bfin_gen_regmv (REG_T src, REG_T dst)
1861 {
1862   int gs, gd;
1863   INIT (RegMv);
1864
1865   ASSIGN_R (src);
1866   ASSIGN_R (dst);
1867
1868   gs = (GROUP (src));
1869   ASSIGN (gs);
1870   gd = (GROUP (dst));
1871   ASSIGN (gd);
1872
1873   return GEN_OPCODE16 ();
1874 }
1875
1876 INSTR_T
1877 bfin_gen_cc2dreg (int op, REG_T reg)
1878 {
1879   INIT (CC2dreg);
1880
1881   ASSIGN (op);
1882   ASSIGN_R (reg);
1883
1884   return GEN_OPCODE16 ();
1885 }
1886
1887 INSTR_T
1888 bfin_gen_progctrl (int prgfunc, int poprnd)
1889 {
1890   INIT (ProgCtrl);
1891
1892   ASSIGN (prgfunc);
1893   ASSIGN (poprnd);
1894
1895   return GEN_OPCODE16 ();
1896 }
1897
1898 INSTR_T
1899 bfin_gen_cactrl (REG_T reg, int a, int op)
1900 {
1901   INIT (CaCTRL);
1902
1903   ASSIGN_R (reg);
1904   ASSIGN (a);
1905   ASSIGN (op);
1906
1907   return GEN_OPCODE16 ();
1908 }
1909
1910 INSTR_T
1911 bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W)
1912 {
1913   INIT (PushPopMultiple);
1914
1915   ASSIGN (dr);
1916   ASSIGN (pr);
1917   ASSIGN (d);
1918   ASSIGN (p);
1919   ASSIGN (W);
1920
1921   return GEN_OPCODE16 ();
1922 }
1923
1924 INSTR_T
1925 bfin_gen_pushpopreg (REG_T reg, int W)
1926 {
1927   int grp;
1928   INIT (PushPopReg);
1929
1930   ASSIGN_R (reg);
1931   grp = (GROUP (reg));
1932   ASSIGN (grp);
1933   ASSIGN (W);
1934
1935   return GEN_OPCODE16 ();
1936 }
1937
1938 /* Pseudo Debugging Support.  */
1939
1940 INSTR_T
1941 bfin_gen_pseudodbg (int fn, int reg, int grp)
1942 {
1943   INIT (PseudoDbg);
1944
1945   ASSIGN (fn);
1946   ASSIGN (reg);
1947   ASSIGN (grp);
1948
1949   return GEN_OPCODE16 ();
1950 }
1951
1952 INSTR_T
1953 bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
1954 {
1955   INIT (PseudoDbg_Assert);
1956
1957   ASSIGN (dbgop);
1958   ASSIGN_R (regtest);
1959   ASSIGN (expected);
1960
1961   return GEN_OPCODE32 ();
1962 }
1963
1964 /* Multiple instruction generation.  */
1965
1966 INSTR_T
1967 bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
1968 {
1969   INSTR_T walk;
1970
1971   /* If it's a 0, convert into MNOP. */
1972   if (dsp32)
1973     {
1974       walk = dsp32->next;
1975       SET_MULTI_INSTRUCTION_BIT (dsp32);
1976     }
1977   else
1978     {
1979       dsp32 = gencode (0xc803);
1980       walk = gencode (0x1800);
1981       dsp32->next = walk;
1982     }
1983
1984   if (!dsp16_grp1)
1985     {
1986       dsp16_grp1 = gencode (0x0000);
1987     }
1988
1989   if (!dsp16_grp2)
1990     {
1991       dsp16_grp2 = gencode (0x0000);
1992     }
1993
1994   walk->next = dsp16_grp1;
1995   dsp16_grp1->next = dsp16_grp2;
1996   dsp16_grp2->next = NULL_CODE;
1997
1998   return dsp32;
1999 }
2000
2001 INSTR_T
2002 bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
2003 {
2004   const char *loopsym;
2005   char *lbeginsym, *lendsym;
2006   Expr_Node_Value lbeginval, lendval;
2007   Expr_Node *lbegin, *lend;
2008
2009   loopsym = expr->value.s_value;
2010   lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5);
2011   lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5);
2012
2013   lbeginsym[0] = 0;
2014   lendsym[0] = 0;
2015
2016   strcat (lbeginsym, "L$L$");
2017   strcat (lbeginsym, loopsym);
2018   strcat (lbeginsym, "__BEGIN");
2019
2020   strcat (lendsym, "L$L$");
2021   strcat (lendsym, loopsym);
2022   strcat (lendsym, "__END");
2023
2024   lbeginval.s_value = lbeginsym;
2025   lendval.s_value = lendsym;
2026
2027   lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
2028   lend   = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
2029
2030   symbol_remove (symbol_find (loopsym), &symbol_rootP, &symbol_lastP);
2031
2032   return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
2033 }
2034
2035 void
2036 bfin_loop_beginend (Expr_Node *expr, int begin)
2037 {
2038   const char *loopsym;
2039   char *label_name;
2040   symbolS *line_label;
2041   const char *suffix = begin ? "__BEGIN" : "__END";
2042
2043   loopsym = expr->value.s_value;
2044   label_name = (char *) xmalloc (strlen (loopsym) + strlen (suffix) + 5);
2045
2046   label_name[0] = 0;
2047
2048   strcat (label_name, "L$L$");
2049   strcat (label_name, loopsym);
2050   strcat (label_name, suffix);
2051
2052   line_label = colon (label_name);
2053
2054   /* LOOP_END follows the last instruction in the loop.
2055      Adjust label address.  */
2056   if (!begin)
2057     ((struct local_symbol *) line_label)->lsy_value -= last_insn_size;
2058 }
2059
2060 bfd_boolean
2061 bfin_eol_in_insn (char *line)
2062 {
2063    /* Allow a new-line to appear in the middle of a multi-issue instruction.  */
2064
2065    char *temp = line;
2066
2067   if (*line != '\n')
2068     return FALSE;
2069
2070   /* A semi-colon followed by a newline is always the end of a line.  */
2071   if (line[-1] == ';')
2072     return FALSE;
2073
2074   if (line[-1] == '|')
2075     return TRUE;
2076
2077   /* If the || is on the next line, there might be leading whitespace.  */
2078   temp++;
2079   while (*temp == ' ' || *temp == '\t') temp++;
2080
2081   if (*temp == '|')
2082     return TRUE;
2083
2084   return FALSE;
2085 }
2086
2087 bfd_boolean
2088 bfin_start_label (char *s, char *ptr)
2089 {
2090   while (s != ptr)
2091     {
2092       if (*s == '(' || *s == '[')
2093         return FALSE;
2094       s++;
2095     }
2096
2097   return TRUE;
2098 }
2099
2100 int
2101 bfin_force_relocation (struct fix *fixp)
2102 {
2103   if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
2104       || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
2105     return TRUE;
2106
2107   return generic_force_reloc (fixp);
2108 }
2109 \f
2110 /* This is a stripped down version of the disassembler.  The only thing it
2111    does is return a mask of registers modified by an instruction.  Only
2112    instructions that can occur in a parallel-issue bundle are handled, and
2113    only the registers that can cause a conflict are recorded.  */
2114
2115 #define DREG_MASK(n) (0x101 << (n))
2116 #define DREGH_MASK(n) (0x100 << (n))
2117 #define DREGL_MASK(n) (0x001 << (n))
2118 #define IREG_MASK(n) (1 << ((n) + 16))
2119
2120 static int
2121 decode_ProgCtrl_0 (int iw0)
2122 {
2123   if (iw0 == 0)
2124     return 0;
2125   abort ();
2126 }
2127
2128 static int
2129 decode_LDSTpmod_0 (int iw0)
2130 {
2131   /* LDSTpmod
2132      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2133      | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
2134      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2135   int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
2136   int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
2137   int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
2138   int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
2139   int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
2140
2141   if (aop == 1 && W == 0 && idx == ptr)
2142     return DREGL_MASK (reg);
2143   else if (aop == 2 && W == 0 && idx == ptr)
2144     return DREGH_MASK (reg);
2145   else if (aop == 1 && W == 1 && idx == ptr)
2146     return 0;
2147   else if (aop == 2 && W == 1 && idx == ptr)
2148     return 0;
2149   else if (aop == 0 && W == 0)
2150     return DREG_MASK (reg);
2151   else if (aop == 1 && W == 0)
2152     return DREGL_MASK (reg);
2153   else if (aop == 2 && W == 0)
2154     return DREGH_MASK (reg);
2155   else if (aop == 3 && W == 0)
2156     return DREG_MASK (reg);
2157   else if (aop == 3 && W == 1)
2158     return DREG_MASK (reg);
2159   else if (aop == 0 && W == 1)
2160     return 0;
2161   else if (aop == 1 && W == 1)
2162     return 0;
2163   else if (aop == 2 && W == 1)
2164     return 0;
2165   else
2166     return 0;
2167
2168   return 2;
2169 }
2170
2171 static int
2172 decode_dagMODim_0 (int iw0)
2173 {
2174   /* dagMODim
2175      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2176      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2177      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2178   int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2179   int op  = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2180
2181   if (op == 0 || op == 1)
2182     return IREG_MASK (i);
2183   else
2184     return 0;
2185
2186   return 2;
2187 }
2188
2189 static int
2190 decode_dagMODik_0 (int iw0)
2191 {
2192   /* dagMODik
2193      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2194      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2195      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2196   int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2197   return IREG_MASK (i);
2198 }
2199
2200 /* GOOD */
2201 static int
2202 decode_dspLDST_0 (int iw0)
2203 {
2204   /* dspLDST
2205      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2206      | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2207      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2208   int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2209   int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2210   int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2211   int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2212   int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2213
2214   if (aop == 0 && W == 0 && m == 0)
2215     return DREG_MASK (reg) | IREG_MASK (i);
2216   else if (aop == 0 && W == 0 && m == 1)
2217     return DREGL_MASK (reg) | IREG_MASK (i);
2218   else if (aop == 0 && W == 0 && m == 2)
2219     return DREGH_MASK (reg) | IREG_MASK (i);
2220   else if (aop == 1 && W == 0 && m == 0)
2221     return DREG_MASK (reg) | IREG_MASK (i);
2222   else if (aop == 1 && W == 0 && m == 1)
2223     return DREGL_MASK (reg) | IREG_MASK (i);
2224   else if (aop == 1 && W == 0 && m == 2)
2225     return DREGH_MASK (reg) | IREG_MASK (i);
2226   else if (aop == 2 && W == 0 && m == 0)
2227     return DREG_MASK (reg);
2228   else if (aop == 2 && W == 0 && m == 1)
2229     return DREGL_MASK (reg);
2230   else if (aop == 2 && W == 0 && m == 2)
2231     return DREGH_MASK (reg);
2232   else if (aop == 0 && W == 1 && m == 0)
2233     return IREG_MASK (i);
2234   else if (aop == 0 && W == 1 && m == 1)
2235     return IREG_MASK (i);
2236   else if (aop == 0 && W == 1 && m == 2)
2237     return IREG_MASK (i);
2238   else if (aop == 1 && W == 1 && m == 0)
2239     return IREG_MASK (i);
2240   else if (aop == 1 && W == 1 && m == 1)
2241     return IREG_MASK (i);
2242   else if (aop == 1 && W == 1 && m == 2)
2243     return IREG_MASK (i);
2244   else if (aop == 2 && W == 1 && m == 0)
2245     return 0;
2246   else if (aop == 2 && W == 1 && m == 1)
2247     return 0;
2248   else if (aop == 2 && W == 1 && m == 2)
2249     return 0;
2250   else if (aop == 3 && W == 0)
2251     return DREG_MASK (reg) | IREG_MASK (i);
2252   else if (aop == 3 && W == 1)
2253     return IREG_MASK (i);
2254
2255   abort ();
2256 }
2257
2258 /* GOOD */
2259 static int
2260 decode_LDST_0 (int iw0)
2261 {
2262   /* LDST
2263      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2264      | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2265      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2266   int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2267   int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2268   int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2269   int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2270   int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2271
2272   if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2273     return DREG_MASK (reg);
2274   else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2275     return 0;
2276   else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2277     return DREG_MASK (reg);
2278   else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2279     return DREG_MASK (reg);
2280   else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2281     return DREG_MASK (reg);
2282   else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2283     return DREG_MASK (reg);
2284   else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2285     return DREG_MASK (reg);
2286   else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2287     return 0;
2288   else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2289     return DREG_MASK (reg);
2290   else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2291     return DREG_MASK (reg);
2292   else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2293     return DREG_MASK (reg);
2294   else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2295     return DREG_MASK (reg);
2296   else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2297     return DREG_MASK (reg);
2298   else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2299     return 0;
2300   else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2301     return DREG_MASK (reg);
2302   else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2303     return DREG_MASK (reg);
2304   else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2305     return DREG_MASK (reg);
2306   else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2307     return DREG_MASK (reg);
2308   else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2309     return 0;
2310   else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2311     return 0;
2312   else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2313     return 0;
2314   else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2315     return 0;
2316   else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2317     return 0;
2318   else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2319     return 0;
2320   else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2321     return 0;
2322   else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2323     return 0;
2324   else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2325     return 0;
2326   else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2327     return 0;
2328   else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2329     return 0;
2330   else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2331     return 0;
2332
2333   abort ();
2334 }
2335
2336 static int
2337 decode_LDSTiiFP_0 (int iw0)
2338 {
2339   /* LDSTiiFP
2340      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2341      | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2342      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2343   int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2344   int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2345
2346   if (W == 0)
2347     return reg < 8 ? DREG_MASK (reg) : 0;
2348   else
2349     return 0;
2350 }
2351
2352 static int
2353 decode_LDSTii_0 (int iw0)
2354 {
2355   /* LDSTii
2356      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2357      | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2358      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2359   int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2360   int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2361   int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2362
2363   if (W == 0 && op != 3)
2364     return DREG_MASK (reg);
2365   else if (W == 0 && op == 3)
2366    return 0;
2367   else if (W == 1 && op == 0)
2368     return 0;
2369   else if (W == 1 && op == 1)
2370     return 0;
2371   else if (W == 1 && op == 3)
2372     return 0;
2373
2374   abort ();
2375 }
2376
2377 static int
2378 decode_dsp32mac_0 (int iw0, int iw1)
2379 {
2380   int result = 0;
2381   /* dsp32mac
2382      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2383      | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2384      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2385      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2386   int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2387   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2388   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2389   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2390   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2391   int MM   = ((iw1 >> DSP32Mac_MM_bits) & DSP32Mac_MM_mask);
2392   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2393   int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2394
2395   if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2396     return 0;
2397
2398   if (op1 == 3 && MM)
2399     return 0;
2400
2401   if ((w1 || w0) && mmod == M_W32)
2402     return 0;
2403
2404   if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2405     return 0;
2406
2407   if (w1 == 1 || op1 != 3)
2408     {
2409       if (w1)
2410         {
2411           if (P)
2412             return DREG_MASK (dst + 1);
2413           else
2414             return DREGH_MASK (dst);
2415         }
2416     }
2417
2418   if (w0 == 1 || op0 != 3)
2419     {
2420       if (w0)
2421         {
2422           if (P)
2423             return DREG_MASK (dst);
2424           else
2425             return DREGL_MASK (dst);
2426         }
2427     }
2428
2429   return result;
2430 }
2431
2432 static int
2433 decode_dsp32mult_0 (int iw0, int iw1)
2434 {
2435   /* dsp32mult
2436      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2437      | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2438      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2439      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2440   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2441   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2442   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2443   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2444   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2445   int result = 0;
2446
2447   if (w1 == 0 && w0 == 0)
2448     return 0;
2449
2450   if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2451     return 0;
2452
2453   if (w1)
2454     {
2455       if (P)
2456         return DREG_MASK (dst | 1);
2457       else
2458         return DREGH_MASK (dst);
2459     }
2460
2461   if (w0)
2462     {
2463       if (P)
2464         return DREG_MASK (dst);
2465       else
2466         return DREGL_MASK (dst);
2467     }
2468
2469   return result;
2470 }
2471
2472 static int
2473 decode_dsp32alu_0 (int iw0, int iw1)
2474 {
2475   /* dsp32alu
2476      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2477      | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2478      |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2479      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2480   int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
2481   int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
2482   int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
2483   int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
2484   int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
2485   int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
2486   int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
2487
2488   if (aop == 0 && aopcde == 9 && s == 0)
2489     return 0;
2490   else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
2491     return 0;
2492   else if (aop >= x * 2 && aopcde == 5)
2493     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2494   else if (HL == 0 && aopcde == 2)
2495     return DREGL_MASK (dst0);
2496   else if (HL == 1 && aopcde == 2)
2497     return DREGH_MASK (dst0);
2498   else if (HL == 0 && aopcde == 3)
2499     return DREGL_MASK (dst0);
2500   else if (HL == 1 && aopcde == 3)
2501     return DREGH_MASK (dst0);
2502
2503   else if (aop == 0 && aopcde == 9 && s == 1)
2504     return 0;
2505   else if (aop == 1 && aopcde == 9 && s == 0)
2506     return 0;
2507   else if (aop == 2 && aopcde == 9 && s == 1)
2508     return 0;
2509   else if (aop == 3 && aopcde == 9 && s == 0)
2510     return 0;
2511   else if (aopcde == 8)
2512     return 0;
2513   else if (aop == 0 && aopcde == 11)
2514     return DREG_MASK (dst0);
2515   else if (aop == 1 && aopcde == 11)
2516     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2517   else if (aopcde == 11)
2518     return 0;
2519   else if (aopcde == 22)
2520     return DREG_MASK (dst0);
2521
2522   else if ((aop == 0 || aop == 1) && aopcde == 14)
2523     return 0;
2524   else if (aop == 3 && HL == 0 && aopcde == 14)
2525     return 0;
2526
2527   else if (aop == 3 && HL == 0 && aopcde == 15)
2528     return DREG_MASK (dst0);
2529
2530   else if (aop == 1 && aopcde == 16)
2531     return 0;
2532
2533   else if (aop == 0 && aopcde == 16)
2534     return 0;
2535
2536   else if (aop == 3 && HL == 0 && aopcde == 16)
2537     return 0;
2538
2539   else if (aop == 3 && HL == 0 && aopcde == 7)
2540     return DREG_MASK (dst0);
2541   else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 7)
2542     return DREG_MASK (dst0);
2543
2544   else if (aop == 0 && aopcde == 12)
2545     return DREG_MASK (dst0);
2546   else if (aop == 1 && aopcde == 12)
2547     return DREG_MASK (dst0) | DREG_MASK (dst1);
2548   else if (aop == 3 && aopcde == 12)
2549     return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2550
2551   else if (aopcde == 0)
2552     return DREG_MASK (dst0);
2553   else if (aopcde == 1)
2554     return DREG_MASK (dst0) | DREG_MASK (dst1);
2555
2556   else if (aop == 0 && aopcde == 10)
2557     return DREGL_MASK (dst0);
2558   else if (aop == 1 && aopcde == 10)
2559     return DREGL_MASK (dst0);
2560
2561   else if ((aop == 1 || aop == 0) && aopcde == 4)
2562     return DREG_MASK (dst0);
2563   else if (aop == 2 && aopcde == 4)
2564     return DREG_MASK (dst0) | DREG_MASK (dst1);
2565
2566   else if (aop == 0 && aopcde == 17)
2567     return DREG_MASK (dst0) | DREG_MASK (dst1);
2568   else if (aop == 1 && aopcde == 17)
2569     return DREG_MASK (dst0) | DREG_MASK (dst1);
2570   else if (aop == 0 && aopcde == 18)
2571     return 0;
2572   else if (aop == 3 && aopcde == 18)
2573     return 0;
2574
2575   else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 6)
2576     return DREG_MASK (dst0);
2577
2578   else if ((aop == 0 || aop == 1) && aopcde == 20)
2579     return DREG_MASK (dst0);
2580
2581   else if ((aop == 0 || aop == 1) && aopcde == 21)
2582     return DREG_MASK (dst0) | DREG_MASK (dst1);
2583
2584   else if (aop == 0 && aopcde == 23 && HL == 1)
2585     return DREG_MASK (dst0);
2586   else if (aop == 0 && aopcde == 23 && HL == 0)
2587     return DREG_MASK (dst0);
2588
2589   else if (aop == 0 && aopcde == 24)
2590     return DREG_MASK (dst0);
2591   else if (aop == 1 && aopcde == 24)
2592     return DREG_MASK (dst0) | DREG_MASK (dst1);
2593   else if (aopcde == 13)
2594     return DREG_MASK (dst0) | DREG_MASK (dst1);
2595   else
2596     return 0;
2597
2598   return 4;
2599 }
2600
2601 static int
2602 decode_dsp32shift_0 (int iw0, int iw1)
2603 {
2604   /* dsp32shift
2605      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2606      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
2607      |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2608      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2609   int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
2610   int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
2611   int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
2612   int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
2613   int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
2614   int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
2615
2616   if (sop == 0 && sopcde == 0)
2617     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2618   else if (sop == 1 && sopcde == 0)
2619     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2620   else if (sop == 2 && sopcde == 0)
2621     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2622   else if (sop == 0 && sopcde == 3)
2623     return 0;
2624   else if (sop == 1 && sopcde == 3)
2625     return 0;
2626   else if (sop == 2 && sopcde == 3)
2627     return 0;
2628   else if (sop == 3 && sopcde == 3)
2629     return DREG_MASK (dst0);
2630   else if (sop == 0 && sopcde == 1)
2631     return DREG_MASK (dst0);
2632   else if (sop == 1 && sopcde == 1)
2633     return DREG_MASK (dst0);
2634   else if (sop == 2 && sopcde == 1)
2635     return DREG_MASK (dst0);
2636   else if (sopcde == 2)
2637     return DREG_MASK (dst0);
2638   else if (sopcde == 4)
2639     return DREG_MASK (dst0);
2640   else if (sop == 0 && sopcde == 5)
2641     return DREGL_MASK (dst0);
2642   else if (sop == 1 && sopcde == 5)
2643     return DREGL_MASK (dst0);
2644   else if (sop == 2 && sopcde == 5)
2645     return DREGL_MASK (dst0);
2646   else if (sop == 0 && sopcde == 6)
2647     return DREGL_MASK (dst0);
2648   else if (sop == 1 && sopcde == 6)
2649     return DREGL_MASK (dst0);
2650   else if (sop == 3 && sopcde == 6)
2651     return DREGL_MASK (dst0);
2652   else if (sop == 0 && sopcde == 7)
2653     return DREGL_MASK (dst0);
2654   else if (sop == 1 && sopcde == 7)
2655     return DREGL_MASK (dst0);
2656   else if (sop == 2 && sopcde == 7)
2657     return DREGL_MASK (dst0);
2658   else if (sop == 3 && sopcde == 7)
2659     return DREGL_MASK (dst0);
2660   else if (sop == 0 && sopcde == 8)
2661     return DREG_MASK (src0) | DREG_MASK (src1);
2662 #if 0
2663     {
2664       OUTS (outf, "BITMUX (");
2665       OUTS (outf, dregs (src0));
2666       OUTS (outf, ", ");
2667       OUTS (outf, dregs (src1));
2668       OUTS (outf, ", A0) (ASR)");
2669     }
2670 #endif
2671   else if (sop == 1 && sopcde == 8)
2672     return DREG_MASK (src0) | DREG_MASK (src1);
2673 #if 0
2674     {
2675       OUTS (outf, "BITMUX (");
2676       OUTS (outf, dregs (src0));
2677       OUTS (outf, ", ");
2678       OUTS (outf, dregs (src1));
2679       OUTS (outf, ", A0) (ASL)");
2680     }
2681 #endif
2682   else if (sopcde == 9)
2683     return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0);
2684   else if (sopcde == 10)
2685     return DREG_MASK (dst0);
2686   else if (sop == 0 && sopcde == 11)
2687     return DREGL_MASK (dst0);
2688   else if (sop == 1 && sopcde == 11)
2689     return DREGL_MASK (dst0);
2690   else if (sop == 0 && sopcde == 12)
2691     return 0;
2692   else if (sop == 1 && sopcde == 12)
2693     return DREGL_MASK (dst0);
2694   else if (sop == 0 && sopcde == 13)
2695     return DREG_MASK (dst0);
2696   else if (sop == 1 && sopcde == 13)
2697     return DREG_MASK (dst0);
2698   else if (sop == 2 && sopcde == 13)
2699     return DREG_MASK (dst0);
2700
2701   abort ();
2702 }
2703
2704 static int
2705 decode_dsp32shiftimm_0 (int iw0, int iw1)
2706 {
2707   /* dsp32shiftimm
2708      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2709      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
2710      |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
2711      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2712   int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
2713   int bit8     = ((iw1 >> 8) & 0x1);
2714   int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
2715   int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
2716   int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
2717
2718
2719   if (sop == 0 && sopcde == 0)
2720     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2721   else if (sop == 1 && sopcde == 0 && bit8 == 0)
2722     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2723   else if (sop == 1 && sopcde == 0 && bit8 == 1)
2724     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2725   else if (sop == 2 && sopcde == 0 && bit8 == 0)
2726     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2727   else if (sop == 2 && sopcde == 0 && bit8 == 1)
2728     return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2729   else if (sop == 2 && sopcde == 3 && HLs == 1)
2730     return 0;
2731   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
2732     return 0;
2733   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
2734     return 0;
2735   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
2736     return 0;
2737   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
2738     return 0;
2739   else if (sop == 1 && sopcde == 3 && HLs == 0)
2740     return 0;
2741   else if (sop == 1 && sopcde == 3 && HLs == 1)
2742     return 0;
2743   else if (sop == 2 && sopcde == 3 && HLs == 0)
2744     return 0;
2745   else if (sop == 1 && sopcde == 1 && bit8 == 0)
2746     return DREG_MASK (dst0);
2747   else if (sop == 1 && sopcde == 1 && bit8 == 1)
2748     return DREG_MASK (dst0);
2749   else if (sop == 2 && sopcde == 1 && bit8 == 1)
2750     return DREG_MASK (dst0);
2751   else if (sop == 2 && sopcde == 1 && bit8 == 0)
2752     return DREG_MASK (dst0);
2753   else if (sop == 0 && sopcde == 1)
2754     return DREG_MASK (dst0);
2755   else if (sop == 1 && sopcde == 2)
2756     return DREG_MASK (dst0);
2757   else if (sop == 2 && sopcde == 2 && bit8 == 1)
2758     return DREG_MASK (dst0);
2759   else if (sop == 2 && sopcde == 2 && bit8 == 0)
2760     return DREG_MASK (dst0);
2761   else if (sop == 3 && sopcde == 2)
2762     return DREG_MASK (dst0);
2763   else if (sop == 0 && sopcde == 2)
2764     return DREG_MASK (dst0);
2765
2766   abort ();
2767 }
2768
2769 int
2770 insn_regmask (int iw0, int iw1)
2771 {
2772   if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
2773     return 0; /* MNOP */
2774   else if ((iw0 & 0xff00) == 0x0000)
2775     return decode_ProgCtrl_0 (iw0);
2776   else if ((iw0 & 0xffc0) == 0x0240)
2777     abort ();
2778   else if ((iw0 & 0xff80) == 0x0100)
2779     abort ();
2780   else if ((iw0 & 0xfe00) == 0x0400)
2781     abort ();
2782   else if ((iw0 & 0xfe00) == 0x0600)
2783     abort ();
2784   else if ((iw0 & 0xf800) == 0x0800)
2785     abort ();
2786   else if ((iw0 & 0xffe0) == 0x0200)
2787     abort ();
2788   else if ((iw0 & 0xff00) == 0x0300)
2789     abort ();
2790   else if ((iw0 & 0xf000) == 0x1000)
2791     abort ();
2792   else if ((iw0 & 0xf000) == 0x2000)
2793     abort ();
2794   else if ((iw0 & 0xf000) == 0x3000)
2795     abort ();
2796   else if ((iw0 & 0xfc00) == 0x4000)
2797     abort ();
2798   else if ((iw0 & 0xfe00) == 0x4400)
2799     abort ();
2800   else if ((iw0 & 0xf800) == 0x4800)
2801     abort ();
2802   else if ((iw0 & 0xf000) == 0x5000)
2803     abort ();
2804   else if ((iw0 & 0xf800) == 0x6000)
2805     abort ();
2806   else if ((iw0 & 0xf800) == 0x6800)
2807     abort ();
2808   else if ((iw0 & 0xf000) == 0x8000)
2809     return decode_LDSTpmod_0 (iw0);
2810   else if ((iw0 & 0xff60) == 0x9e60)
2811     return decode_dagMODim_0 (iw0);
2812   else if ((iw0 & 0xfff0) == 0x9f60)
2813     return decode_dagMODik_0 (iw0);
2814   else if ((iw0 & 0xfc00) == 0x9c00)
2815     return decode_dspLDST_0 (iw0);
2816   else if ((iw0 & 0xf000) == 0x9000)
2817     return decode_LDST_0 (iw0);
2818   else if ((iw0 & 0xfc00) == 0xb800)
2819     return decode_LDSTiiFP_0 (iw0);
2820   else if ((iw0 & 0xe000) == 0xA000)
2821     return decode_LDSTii_0 (iw0);
2822   else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
2823     abort ();
2824   else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
2825     abort ();
2826   else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
2827     abort ();
2828   else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
2829     abort ();
2830   else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
2831     abort ();
2832   else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
2833     return decode_dsp32mac_0 (iw0, iw1);
2834   else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
2835     return decode_dsp32mult_0 (iw0, iw1);
2836   else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
2837     return decode_dsp32alu_0 (iw0, iw1);
2838   else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
2839     return decode_dsp32shift_0 (iw0, iw1);
2840   else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
2841     return decode_dsp32shiftimm_0 (iw0, iw1);
2842   else if ((iw0 & 0xff00) == 0xf800)
2843     abort ();
2844   else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
2845     abort ();
2846
2847   abort ();
2848 }