1 /* tc-bpf.c -- Assembler for the Linux eBPF.
2 Copyright (C) 2019-2023 Free Software Foundation, Inc.
3 Contributed by Oracle, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
25 #include "opcode/bpf.h"
26 #include "elf/common.h"
28 #include "dwarf2dbg.h"
29 #include "libiberty.h"
32 /* Data structure representing a parsed BPF instruction. */
37 int size
; /* Instruction size in bytes. */
47 unsigned int has_dst
: 1;
48 unsigned int has_src
: 1;
49 unsigned int has_offset16
: 1;
50 unsigned int has_disp16
: 1;
51 unsigned int has_disp32
: 1;
52 unsigned int has_imm32
: 1;
53 unsigned int has_imm64
: 1;
55 unsigned int is_relaxable
: 1;
56 expressionS
*relaxed_exp
;
59 const char comment_chars
[] = ";#";
60 const char line_comment_chars
[] = "#";
61 const char line_separator_chars
[] = "`";
62 const char EXP_CHARS
[] = "eE";
63 const char FLT_CHARS
[] = "fFdD";
65 /* Like s_lcomm_internal in gas/read.c but the alignment string
66 is allowed to be optional. */
69 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
76 && *input_line_pointer
== ',')
78 align
= parse_align (needs_align
- 1);
80 if (align
== (addressT
) -1)
95 bss_alloc (symbolP
, size
, align
);
100 pe_lcomm (int needs_align
)
102 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
105 /* The target specific pseudo-ops which we support. */
106 const pseudo_typeS md_pseudo_table
[] =
110 { "dword", cons
, 8 },
111 { "lcomm", pe_lcomm
, 1 },
117 /* Command-line options processing. */
121 OPTION_LITTLE_ENDIAN
= OPTION_MD_BASE
,
129 struct option md_longopts
[] =
131 { "EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
132 { "EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
133 { "mxbpf", no_argument
, NULL
, OPTION_XBPF
},
134 { "mdialect", required_argument
, NULL
, OPTION_DIALECT
},
135 { "misa-spec", required_argument
, NULL
, OPTION_ISA_SPEC
},
136 { "mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
137 { NULL
, no_argument
, NULL
, 0 },
140 size_t md_longopts_size
= sizeof (md_longopts
);
142 const char * md_shortopts
= "";
144 /* BPF supports little-endian and big-endian variants. The following
145 global records what endianness to use. It can be configured using
146 command-line options. It defaults to the host endianness
147 initialized in md_begin. */
149 static int set_target_endian
= 0;
150 extern int target_big_endian
;
152 /* Whether to relax branch instructions. Default is yes. Can be
153 changed using the -mno-relax command line option. */
155 static int do_relax
= 1;
157 /* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4
158 or BPF_XPBF. The ISA spec to use can be configured using
159 command-line options. It defaults to the latest BPF spec. */
161 static int isa_spec
= BPF_V4
;
163 /* The assembler supports two different dialects: "normal" syntax and
164 "pseudoc" syntax. The dialect to use can be configured using
165 command-line options. */
167 enum target_asm_dialect
173 static int asm_dialect
= DIALECT_NORMAL
;
176 md_parse_option (int c
, const char * arg
)
180 case OPTION_BIG_ENDIAN
:
181 set_target_endian
= 1;
182 target_big_endian
= 1;
184 case OPTION_LITTLE_ENDIAN
:
185 set_target_endian
= 0;
186 target_big_endian
= 0;
189 if (strcmp (arg
, "normal") == 0)
190 asm_dialect
= DIALECT_NORMAL
;
191 else if (strcmp (arg
, "pseudoc") == 0)
192 asm_dialect
= DIALECT_PSEUDOC
;
194 as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"),
197 case OPTION_ISA_SPEC
:
198 if (strcmp (arg
, "v1") == 0)
200 else if (strcmp (arg
, "v2") == 0)
202 else if (strcmp (arg
, "v3") == 0)
204 else if (strcmp (arg
, "v4") == 0)
206 else if (strcmp (arg
, "xbpf") == 0)
209 as_fatal (_("-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf"),
213 /* This is an alias for -misa-spec=xbpf. */
216 case OPTION_NO_RELAX
:
227 md_show_usage (FILE * stream
)
229 fprintf (stream
, _("\nBPF options:\n"));
230 fprintf (stream
, _("\
232 -EL generate code for a little endian machine\n\
233 -EB generate code for a big endian machine\n\
234 -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\n\
235 -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\
236 -mxbpf alias for -misa-spec=xbpf\n"));
240 /* This function is called once, at assembler startup time. This
241 should set up all the tables, etc that the MD part of the assembler
247 /* If not specified in the command line, use the host
249 if (!set_target_endian
)
251 #ifdef WORDS_BIGENDIAN
252 target_big_endian
= 1;
254 target_big_endian
= 0;
258 /* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */
259 lex_type
['*'] |= LEX_BEGIN_NAME
;
261 /* Set the machine type. */
262 bfd_default_set_arch_mach (stdoutput
, bfd_arch_bpf
, bfd_mach_bpf
);
265 /* Round up a section size to the appropriate boundary. */
268 md_section_align (segT segment
, valueT size
)
270 int align
= bfd_section_alignment (segment
);
272 return ((size
+ (1 << align
) - 1) & -(1 << align
));
275 /* Return non-zero if the indicated VALUE has overflowed the maximum
276 range expressible by an signed number with the indicated number of
280 signed_overflow (offsetT value
, unsigned bits
)
283 if (bits
>= sizeof (offsetT
) * 8)
285 lim
= (offsetT
) 1 << (bits
- 1);
286 return (value
< -lim
|| value
>= lim
);
289 /* Return non-zero if the two's complement encoding of VALUE would
290 overflow an immediate field of width BITS bits. */
293 immediate_overflow (int64_t value
, unsigned bits
)
296 return signed_overflow (value
, bits
);
301 if (bits
>= sizeof (valueT
) * 8)
304 lim
= (valueT
) 1 << bits
;
305 return ((valueT
) value
>= lim
);
310 /* Functions concerning relocs. */
312 /* The location from which a PC relative jump should be calculated,
313 given a PC relative reloc. */
316 md_pcrel_from_section (fixS
*fixP
, segT sec
)
318 if (fixP
->fx_addsy
!= (symbolS
*) NULL
319 && (! S_IS_DEFINED (fixP
->fx_addsy
)
320 || (S_GET_SEGMENT (fixP
->fx_addsy
) != sec
)
321 || S_IS_EXTERNAL (fixP
->fx_addsy
)
322 || S_IS_WEAK (fixP
->fx_addsy
)))
324 /* The symbol is undefined (or is defined but not in this section).
325 Let the linker figure it out. */
329 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
332 /* Write a value out to the object file, using the appropriate endianness. */
335 md_number_to_chars (char * buf
, valueT val
, int n
)
337 if (target_big_endian
)
338 number_to_chars_bigendian (buf
, val
, n
);
340 number_to_chars_littleendian (buf
, val
, n
);
344 tc_gen_reloc (asection
*sec ATTRIBUTE_UNUSED
, fixS
*fixP
)
346 bfd_reloc_code_real_type r_type
= fixP
->fx_r_type
;
349 reloc
= XNEW (arelent
);
353 r_type
= (r_type
== BFD_RELOC_8
? BFD_RELOC_8_PCREL
354 : r_type
== BFD_RELOC_16
? BFD_RELOC_16_PCREL
355 : r_type
== BFD_RELOC_24
? BFD_RELOC_24_PCREL
356 : r_type
== BFD_RELOC_32
? BFD_RELOC_32_PCREL
357 : r_type
== BFD_RELOC_64
? BFD_RELOC_64_PCREL
361 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, r_type
);
363 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
366 _("relocation is not supported"));
370 //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
372 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
373 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
375 /* Use fx_offset for these cases. */
376 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
377 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
)
378 reloc
->addend
= fixP
->fx_offset
;
380 reloc
->addend
= fixP
->fx_addnumber
;
382 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
387 /* Relaxations supported by this assembler. */
389 #define RELAX_BRANCH_ENCODE(uncond, constant, length) \
392 | ((uncond) ? 1 : 0) \
393 | ((constant) ? 2 : 0) \
396 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
397 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xff)
398 #define RELAX_BRANCH_CONST(i) (((i) & 2) != 0)
399 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
402 /* Compute the length of a branch sequence, and adjust the stored
403 length accordingly. If FRAG is NULL, the worst-case length is
407 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
414 uncond
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
415 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
418 /* Length is the same for both JA and JAL. */
422 if (RELAX_BRANCH_CONST (fragp
->fr_subtype
))
424 int64_t val
= fragp
->fr_offset
;
426 if (val
< -32768 || val
> 32767)
431 else if (fragp
->fr_symbol
!= NULL
432 && S_IS_DEFINED (fragp
->fr_symbol
)
433 && !S_IS_WEAK (fragp
->fr_symbol
)
434 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
436 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
438 /* Convert to 64-bit words, minus one. */
441 /* See if it fits in the signed 16-bits field. */
442 if (val
< -32768 || val
> 32767)
448 /* Use short version, and let the linker relax instead, if
449 appropriate and if supported. */
454 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (uncond
,
455 RELAX_BRANCH_CONST (fragp
->fr_subtype
),
461 /* Estimate the size of a variant frag before relaxing. */
464 md_estimate_size_before_relax (fragS
*fragp
, asection
*sec
)
466 return (fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true));
469 /* Read a BPF instruction word from BUF. */
472 read_insn_word (bfd_byte
*buf
)
474 return bfd_getb64 (buf
);
477 /* Write the given signed 16-bit value in the given BUFFER using the
478 target endianness. */
481 encode_int16 (int16_t value
, char *buffer
)
483 uint16_t val
= value
;
485 if (target_big_endian
)
487 buffer
[0] = (val
>> 8) & 0xff;
488 buffer
[1] = val
& 0xff;
492 buffer
[1] = (val
>> 8) & 0xff;
493 buffer
[0] = val
& 0xff;
497 /* Write the given signed 32-bit value in the given BUFFER using the
498 target endianness. */
501 encode_int32 (int32_t value
, char *buffer
)
503 uint32_t val
= value
;
505 if (target_big_endian
)
507 buffer
[0] = (val
>> 24) & 0xff;
508 buffer
[1] = (val
>> 16) & 0xff;
509 buffer
[2] = (val
>> 8) & 0xff;
510 buffer
[3] = val
& 0xff;
514 buffer
[3] = (val
>> 24) & 0xff;
515 buffer
[2] = (val
>> 16) & 0xff;
516 buffer
[1] = (val
>> 8) & 0xff;
517 buffer
[0] = value
& 0xff;
521 /* Write a BPF instruction to BUF. */
524 write_insn_bytes (bfd_byte
*buf
, char *bytes
)
528 for (i
= 0; i
< 8; ++i
)
529 md_number_to_chars ((char *) buf
+ i
, (valueT
) bytes
[i
], 1);
532 /* *FRAGP has been relaxed to its final size, and now needs to have
533 the bytes inside it modified to conform to the new size.
535 Called after relaxation is finished.
536 fragP->fr_type == rs_machine_dependent.
537 fragP->fr_subtype is the subtype of what the address relaxed to. */
540 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
541 segT sec ATTRIBUTE_UNUSED
,
542 fragS
*fragp ATTRIBUTE_UNUSED
)
544 bfd_byte
*buf
= (bfd_byte
*) fragp
->fr_literal
+ fragp
->fr_fix
;
548 int disp_is_known
= 0;
549 int64_t disp_to_target
= 0;
553 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
555 /* Expression to be used in any resulting relocation in the relaxed
558 exp
.X_add_symbol
= fragp
->fr_symbol
;
559 exp
.X_add_number
= fragp
->fr_offset
;
561 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
563 /* Read an instruction word from the instruction to be relaxed, and
565 word
= read_insn_word (buf
);
566 code
= (word
>> 60) & 0xf;
568 /* Determine whether the 16-bit displacement to the target is known
570 if (RELAX_BRANCH_CONST (fragp
->fr_subtype
))
572 disp_to_target
= fragp
->fr_offset
;
575 else if (fragp
->fr_symbol
!= NULL
576 && S_IS_DEFINED (fragp
->fr_symbol
)
577 && !S_IS_WEAK (fragp
->fr_symbol
)
578 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
580 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
581 /* Convert to 64-bit blocks minus one. */
582 disp_to_target
= (val
- 8) / 8;
586 /* The displacement should fit in a signed 32-bit number. */
587 if (disp_is_known
&& signed_overflow (disp_to_target
, 32))
588 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
589 _("signed instruction operand out of range, shall fit in 32 bits"));
591 /* Now relax particular jump instructions. */
592 if (code
== BPF_CODE_JA
)
594 /* Unconditional jump.
597 gas_assert (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
601 if (disp_to_target
>= -32768 && disp_to_target
<= 32767)
603 /* 16-bit disp is known and in range. Install a fixup
604 for the disp16 if the branch value is not constant.
605 This will be resolved by the assembler and units
608 if (!RELAX_BRANCH_CONST (fragp
->fr_subtype
))
610 /* Install fixup for the JA. */
611 reloc_howto_type
*reloc_howto
612 = bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
616 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
617 bfd_get_reloc_size (reloc_howto
),
619 reloc_howto
->pc_relative
,
620 BFD_RELOC_BPF_DISP16
);
621 fixp
->fx_file
= fragp
->fr_file
;
622 fixp
->fx_line
= fragp
->fr_line
;
627 /* 16-bit disp is known and not in range. Turn the JA
628 into a JAL with a 32-bit displacement. */
631 bytes
[0] = ((BPF_CLASS_JMP32
|BPF_CODE_JA
|BPF_SRC_K
) >> 56) & 0xff;
632 bytes
[1] = (word
>> 48) & 0xff;
633 bytes
[2] = 0; /* disp16 high */
634 bytes
[3] = 0; /* disp16 lo */
635 encode_int32 ((int32_t) disp_to_target
, bytes
+ 4);
637 write_insn_bytes (buf
, bytes
);
642 /* The displacement to the target is not known. Do not
643 relax. The linker will maybe do it if it chooses to. */
645 reloc_howto_type
*reloc_howto
= NULL
;
647 gas_assert (!RELAX_BRANCH_CONST (fragp
->fr_subtype
));
649 /* Install fixup for the JA. */
650 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
654 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
655 bfd_get_reloc_size (reloc_howto
),
657 reloc_howto
->pc_relative
,
658 BFD_RELOC_BPF_DISP16
);
659 fixp
->fx_file
= fragp
->fr_file
;
660 fixp
->fx_line
= fragp
->fr_line
;
668 JXX d16 -> JXX +1; JA +1; JAL d32 */
670 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
674 if (disp_to_target
>= -32768 && disp_to_target
<= 32767)
676 /* 16-bit disp is known and in range. Install a fixup
677 for the disp16 if the branch value is not constant.
678 This will be resolved by the assembler and units
681 if (!RELAX_BRANCH_CONST (fragp
->fr_subtype
))
683 /* Install fixup for the branch. */
684 reloc_howto_type
*reloc_howto
685 = bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
689 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
690 bfd_get_reloc_size (reloc_howto
),
692 reloc_howto
->pc_relative
,
693 BFD_RELOC_BPF_DISP16
);
694 fixp
->fx_file
= fragp
->fr_file
;
695 fixp
->fx_line
= fragp
->fr_line
;
702 /* 16-bit disp is known and not in range. Turn the JXX
703 into a sequence JXX +1; JA +1; JAL d32. */
707 /* First, set the 16-bit offset in the current
710 if (target_big_endian
)
711 bfd_putb16 (1, buf
+ 2);
713 bfd_putl16 (1, buf
+ 2);
716 /* Then, write the JA + 1 */
718 bytes
[0] = 0x05; /* JA */
720 encode_int16 (1, bytes
+ 2);
725 write_insn_bytes (buf
, bytes
);
728 /* Finally, write the JAL to the target. */
730 bytes
[0] = ((BPF_CLASS_JMP32
|BPF_CODE_JA
|BPF_SRC_K
) >> 56) & 0xff;
734 encode_int32 ((int32_t) disp_to_target
, bytes
+ 4);
735 write_insn_bytes (buf
, bytes
);
741 /* The displacement to the target is not known. Do not
742 relax. The linker will maybe do it if it chooses to. */
744 reloc_howto_type
*reloc_howto
= NULL
;
746 gas_assert (!RELAX_BRANCH_CONST (fragp
->fr_subtype
));
748 /* Install fixup for the conditional jump. */
749 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
753 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
754 bfd_get_reloc_size (reloc_howto
),
756 reloc_howto
->pc_relative
,
757 BFD_RELOC_BPF_DISP16
);
758 fixp
->fx_file
= fragp
->fr_file
;
759 fixp
->fx_line
= fragp
->fr_line
;
764 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
765 + fragp
->fr_fix
+ fragp
->fr_var
);
767 fragp
->fr_fix
+= fragp
->fr_var
;
771 /* Apply a fixS (fixup of an instruction or data that we didn't have
772 enough info to complete immediately) to the data in a frag. */
775 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
777 char *where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
779 switch (fixP
->fx_r_type
)
781 case BFD_RELOC_BPF_DISP16
:
782 /* Convert from bytes to number of 64-bit words to the target,
784 *valP
= (((long) (*valP
)) - 8) / 8;
786 case BFD_RELOC_BPF_DISPCALL32
:
787 case BFD_RELOC_BPF_DISP32
:
788 /* Convert from bytes to number of 64-bit words to the target,
790 *valP
= (((long) (*valP
)) - 8) / 8;
792 if (fixP
->fx_r_type
== BFD_RELOC_BPF_DISPCALL32
)
794 /* eBPF supports two kind of CALL instructions: the so
795 called pseudo calls ("bpf to bpf") and external calls
798 Both kind of calls use the same instruction (CALL).
799 However, external calls are constructed by passing a
800 constant argument to the instruction, whereas pseudo
801 calls result from expressions involving symbols. In
802 practice, instructions requiring a fixup are interpreted
803 as pseudo-calls. If we are executing this code, this is
806 The kernel expects for pseudo-calls to be annotated by
807 having BPF_PSEUDO_CALL in the SRC field of the
808 instruction. But beware the infamous nibble-swapping of
809 eBPF and take endianness into account here.
811 Note that the CALL instruction has only one operand, so
812 this code is executed only once per instruction. */
813 md_number_to_chars (where
+ 1, target_big_endian
? 0x01 : 0x10, 1);
816 case BFD_RELOC_16_PCREL
:
817 /* Convert from bytes to number of 64-bit words to the target,
819 *valP
= (((long) (*valP
)) - 8) / 8;
825 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
830 /* We're finished with this fixup. Install it because
831 bfd_install_relocation won't be called to do it. */
832 switch (fixP
->fx_r_type
)
835 md_number_to_chars (where
, *valP
, 1);
838 md_number_to_chars (where
, *valP
, 2);
841 md_number_to_chars (where
, *valP
, 4);
844 md_number_to_chars (where
, *valP
, 8);
846 case BFD_RELOC_BPF_DISP16
:
847 md_number_to_chars (where
+ 2, (uint16_t) *valP
, 2);
849 case BFD_RELOC_BPF_DISP32
:
850 case BFD_RELOC_BPF_DISPCALL32
:
851 md_number_to_chars (where
+ 4, (uint32_t) *valP
, 4);
853 case BFD_RELOC_16_PCREL
:
854 md_number_to_chars (where
+ 2, (uint32_t) *valP
, 2);
857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
858 _("internal error: can't install fix for reloc type %d (`%s')"),
859 fixP
->fx_r_type
, bfd_get_reloc_code_name (fixP
->fx_r_type
));
864 /* Tuck `value' away for use by tc_gen_reloc.
865 See the comment describing fx_addnumber in write.h.
866 This field is misnamed (or misused :-). */
867 fixP
->fx_addnumber
= *valP
;
871 /* Instruction writing routines. */
873 /* Encode a BPF instruction in the given buffer BYTES. Non-constant
874 immediates are encoded as zeroes. */
877 encode_insn (struct bpf_insn
*insn
, char *bytes
,
878 int relaxed ATTRIBUTE_UNUSED
)
882 /* Zero all the bytes. */
883 memset (bytes
, 0, 16);
885 /* First encode the opcodes. Note that we have to handle the
886 endianness groups of the BPF instructions: 8 | 4 | 4 | 16 |
888 if (target_big_endian
)
891 bytes
[0] = (insn
->opcode
>> 56) & 0xff;
893 bytes
[1] = (insn
->opcode
>> 48) & 0xff;
895 bytes
[2] = (insn
->opcode
>> 40) & 0xff;
896 bytes
[3] = (insn
->opcode
>> 32) & 0xff;
898 bytes
[4] = (insn
->opcode
>> 24) & 0xff;
899 bytes
[5] = (insn
->opcode
>> 16) & 0xff;
900 bytes
[6] = (insn
->opcode
>> 8) & 0xff;
901 bytes
[7] = insn
->opcode
& 0xff;
906 bytes
[0] = (insn
->opcode
>> 56) & 0xff;
908 bytes
[1] = (((((insn
->opcode
>> 48) & 0xff) & 0xf) << 4)
909 | (((insn
->opcode
>> 48) & 0xff) & 0xf));
911 bytes
[3] = (insn
->opcode
>> 40) & 0xff;
912 bytes
[2] = (insn
->opcode
>> 32) & 0xff;
914 bytes
[7] = (insn
->opcode
>> 24) & 0xff;
915 bytes
[6] = (insn
->opcode
>> 16) & 0xff;
916 bytes
[5] = (insn
->opcode
>> 8) & 0xff;
917 bytes
[4] = insn
->opcode
& 0xff;
920 /* Now the registers. */
921 src
= insn
->has_src
? insn
->src
: 0;
922 dst
= insn
->has_dst
? insn
->dst
: 0;
924 if (target_big_endian
)
925 bytes
[1] = ((dst
& 0xf) << 4) | (src
& 0xf);
927 bytes
[1] = ((src
& 0xf) << 4) | (dst
& 0xf);
929 /* Now the immediates that are known to be constant. */
931 if (insn
->has_imm32
&& insn
->imm32
.X_op
== O_constant
)
933 int64_t imm
= insn
->imm32
.X_add_number
;
935 if (immediate_overflow (imm
, 32))
936 as_bad (_("immediate out of range, shall fit in 32 bits"));
938 encode_int32 (insn
->imm32
.X_add_number
, bytes
+ 4);
941 if (insn
->has_disp32
&& insn
->disp32
.X_op
== O_constant
)
943 int64_t disp
= insn
->disp32
.X_add_number
;
945 if (immediate_overflow (disp
, 32))
946 as_bad (_("pc-relative offset out of range, shall fit in 32 bits"));
948 encode_int32 (insn
->disp32
.X_add_number
, bytes
+ 4);
951 if (insn
->has_offset16
&& insn
->offset16
.X_op
== O_constant
)
953 int64_t offset
= insn
->offset16
.X_add_number
;
955 if (immediate_overflow (offset
, 16))
956 as_bad (_("pc-relative offset out of range, shall fit in 16 bits"));
958 encode_int16 (insn
->offset16
.X_add_number
, bytes
+ 2);
961 if (insn
->has_disp16
&& insn
->disp16
.X_op
== O_constant
)
963 int64_t disp
= insn
->disp16
.X_add_number
;
965 if (immediate_overflow (disp
, 16))
966 as_bad (_("pc-relative offset out of range, shall fit in 16 bits"));
968 encode_int16 (insn
->disp16
.X_add_number
, bytes
+ 2);
971 if (insn
->has_imm64
&& insn
->imm64
.X_op
== O_constant
)
973 uint64_t imm64
= insn
->imm64
.X_add_number
;
975 if (target_big_endian
)
977 bytes
[12] = (imm64
>> 56) & 0xff;
978 bytes
[13] = (imm64
>> 48) & 0xff;
979 bytes
[14] = (imm64
>> 40) & 0xff;
980 bytes
[15] = (imm64
>> 32) & 0xff;
981 bytes
[4] = (imm64
>> 24) & 0xff;
982 bytes
[5] = (imm64
>> 16) & 0xff;
983 bytes
[6] = (imm64
>> 8) & 0xff;
984 bytes
[7] = imm64
& 0xff;
988 bytes
[15] = (imm64
>> 56) & 0xff;
989 bytes
[14] = (imm64
>> 48) & 0xff;
990 bytes
[13] = (imm64
>> 40) & 0xff;
991 bytes
[12] = (imm64
>> 32) & 0xff;
992 bytes
[7] = (imm64
>> 24) & 0xff;
993 bytes
[6] = (imm64
>> 16) & 0xff;
994 bytes
[5] = (imm64
>> 8) & 0xff;
995 bytes
[4] = imm64
& 0xff;
1000 /* Install the fixups in INSN in their proper location in the
1001 specified FRAG at the location pointed by WHERE. */
1004 install_insn_fixups (struct bpf_insn
*insn
, fragS
*frag
, long where
)
1006 if (insn
->has_imm64
)
1008 switch (insn
->imm64
.X_op
)
1014 reloc_howto_type
*reloc_howto
;
1017 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_64
);
1021 size
= bfd_get_reloc_size (reloc_howto
);
1023 fix_new_exp (frag
, where
,
1024 size
, &insn
->imm64
, reloc_howto
->pc_relative
,
1029 /* Already handled in encode_insn. */
1036 if (insn
->has_imm32
)
1038 switch (insn
->imm32
.X_op
)
1045 reloc_howto_type
*reloc_howto
;
1048 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
1052 size
= bfd_get_reloc_size (reloc_howto
);
1054 fix_new_exp (frag
, where
+ 4,
1055 size
, &insn
->imm32
, reloc_howto
->pc_relative
,
1060 /* Already handled in encode_insn. */
1067 if (insn
->has_disp32
)
1069 switch (insn
->disp32
.X_op
)
1075 reloc_howto_type
*reloc_howto
;
1077 unsigned int bfd_reloc
1078 = (insn
->id
== BPF_INSN_CALL
1079 ? BFD_RELOC_BPF_DISPCALL32
1080 : BFD_RELOC_BPF_DISP32
);
1082 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, bfd_reloc
);
1086 size
= bfd_get_reloc_size (reloc_howto
);
1088 fix_new_exp (frag
, where
,
1089 size
, &insn
->disp32
, reloc_howto
->pc_relative
,
1094 /* Already handled in encode_insn. */
1101 if (insn
->has_offset16
)
1103 switch (insn
->offset16
.X_op
)
1109 reloc_howto_type
*reloc_howto
;
1112 /* XXX we really need a new pc-rel offset in bytes
1113 relocation for this. */
1114 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
1118 size
= bfd_get_reloc_size (reloc_howto
);
1120 fix_new_exp (frag
, where
,
1121 size
, &insn
->offset16
, reloc_howto
->pc_relative
,
1122 BFD_RELOC_BPF_DISP16
);
1126 /* Already handled in encode_insn. */
1133 if (insn
->has_disp16
)
1135 switch (insn
->disp16
.X_op
)
1141 reloc_howto_type
*reloc_howto
;
1144 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_BPF_DISP16
);
1148 size
= bfd_get_reloc_size (reloc_howto
);
1150 fix_new_exp (frag
, where
,
1151 size
, &insn
->disp16
, reloc_howto
->pc_relative
,
1152 BFD_RELOC_BPF_DISP16
);
1156 /* Already handled in encode_insn. */
1165 /* Add a new insn to the list of instructions. */
1168 add_fixed_insn (struct bpf_insn
*insn
)
1170 char *this_frag
= frag_more (insn
->size
);
1174 /* First encode the known parts of the instruction, including
1175 opcodes and constant immediates, and write them to the frag. */
1176 encode_insn (insn
, bytes
, 0 /* relax */);
1177 for (i
= 0; i
< insn
->size
; ++i
)
1178 md_number_to_chars (this_frag
+ i
, (valueT
) bytes
[i
], 1);
1180 /* Now install the instruction fixups. */
1181 install_insn_fixups (insn
, frag_now
,
1182 this_frag
- frag_now
->fr_literal
);
1185 /* Add a new relaxable to the list of instructions. */
1188 add_relaxed_insn (struct bpf_insn
*insn
, expressionS
*exp
)
1193 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1194 unsigned best_case
= insn
->size
;
1196 /* We only support relaxing branches, for the moment. */
1197 relax_substateT subtype
1198 = RELAX_BRANCH_ENCODE (insn
->id
== BPF_INSN_JAR
,
1199 exp
->X_op
== O_constant
,
1202 frag_grow (worst_case
);
1203 this_frag
= frag_more (0);
1205 /* First encode the known parts of the instruction, including
1206 opcodes and constant immediates, and write them to the frag. */
1207 encode_insn (insn
, bytes
, 1 /* relax */);
1208 for (i
= 0; i
< insn
->size
; ++i
)
1209 md_number_to_chars (this_frag
+ i
, (valueT
) bytes
[i
], 1);
1211 /* Note that instruction fixups will be applied once the frag is
1212 relaxed, in md_convert_frag. */
1213 frag_var (rs_machine_dependent
,
1214 worst_case
, best_case
,
1215 subtype
, exp
->X_add_symbol
, exp
->X_add_number
/* offset */,
1220 /* Parse an operand expression. Returns the first character that is
1221 not part of the expression, or NULL in case of parse error.
1223 See md_operand below to see how exp_parse_failed is used. */
1225 static int exp_parse_failed
= 0;
1228 parse_expression (char *s
, expressionS
*exp
)
1230 char *saved_input_line_pointer
= input_line_pointer
;
1233 exp_parse_failed
= 0;
1234 input_line_pointer
= s
;
1236 s
= input_line_pointer
;
1237 input_line_pointer
= saved_input_line_pointer
;
1239 switch (exp
->X_op
== O_absent
|| exp_parse_failed
)
1242 /* The expression parser may consume trailing whitespaces. We have
1243 to undo that since the instruction templates may be expecting
1244 these whitespaces. */
1247 for (p
= s
- 1; p
>= saved_s
&& *p
== ' '; --p
)
1254 /* Parse a BPF register name and return the corresponding register
1255 number. Return NULL in case of parse error, or a pointer to the
1256 first character in S that is not part of the register name. */
1259 parse_bpf_register (char *s
, char rw
, uint8_t *regno
)
1261 if (asm_dialect
== DIALECT_NORMAL
)
1268 if (*s
== 'f' && *(s
+ 1) == 'p')
1282 if (*(s
+ 1) == '0')
1293 else if (*s
>= '0' && *s
<= '9')
1302 /* Collect a parse error message. */
1304 static int partial_match_length
= 0;
1305 static char *errmsg
= NULL
;
1308 parse_error (int length
, const char *fmt
, ...)
1310 if (length
> partial_match_length
)
1315 va_start (args
, fmt
);
1316 errmsg
= xvasprintf (fmt
, args
);
1318 partial_match_length
= length
;
1322 /* Assemble a machine instruction in STR and emit the frags/bytes it
1326 md_assemble (char *str ATTRIBUTE_UNUSED
)
1328 /* There are two different syntaxes that can be used to write BPF
1329 instructions. One is very conventional and like any other
1330 assembly language where each instruction is conformed by an
1331 instruction mnemonic followed by its operands. This is what we
1332 call the "normal" syntax. The other syntax tries to look like C
1333 statements. We have to support both syntaxes in this assembler.
1335 One of the many nuisances introduced by this eccentricity is that
1336 in the pseudo-c syntax it is not possible to hash the opcodes
1337 table by instruction mnemonic, because there is none. So we have
1338 no other choice than to try to parse all instruction opcodes
1339 until one matches. This is slow.
1341 Another problem is that emitting detailed diagnostics becomes
1342 tricky, since the lack of mnemonic means it is not clear what
1343 instruction was intended by the user, and we cannot emit
1344 diagnostics for every attempted template. So if an instruction
1345 is not parsed, we report the diagnostic corresponding to the
1346 partially parsed instruction that was matched further. */
1348 unsigned int idx
= 0;
1349 struct bpf_insn insn
;
1350 const struct bpf_opcode
*opcode
;
1352 /* Initialize the global diagnostic variables. See the parse_error
1354 partial_match_length
= 0;
1357 #define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__)
1359 while ((opcode
= bpf_get_opcode (idx
++)) != NULL
)
1363 const char *template
1364 = (asm_dialect
== DIALECT_PSEUDOC
? opcode
->pseudoc
: opcode
->normal
);
1366 /* Do not try to match opcodes with a higher version than the
1367 selected ISA spec. */
1368 if (opcode
->version
> isa_spec
)
1371 memset (&insn
, 0, sizeof (struct bpf_insn
));
1373 for (s
= str
, p
= template; *p
!= '\0';)
1377 /* Expect zero or more spaces. */
1378 while (*s
!= '\0' && (*s
== ' ' || *s
== '\t'))
1384 if (*(p
+ 1) == '%')
1388 PARSE_ERROR ("expected '%%'");
1394 else if (*(p
+ 1) == 'w')
1396 /* Expect zero or more spaces. */
1397 while (*s
!= '\0' && (*s
== ' ' || *s
== '\t'))
1401 else if (*(p
+ 1) == 'W')
1403 /* Expect one or more spaces. */
1404 if (*s
!= ' ' && *s
!= '\t')
1406 PARSE_ERROR ("expected white space, got '%s'",
1410 while (*s
!= '\0' && (*s
== ' ' || *s
== '\t'))
1414 else if (strncmp (p
, "%dr", 3) == 0)
1417 char *news
= parse_bpf_register (s
, 'r', ®no
);
1419 if (news
== NULL
|| (insn
.has_dst
&& regno
!= insn
.dst
))
1422 PARSE_ERROR ("expected register r%d, got r%d",
1425 PARSE_ERROR ("expected register name, got '%s'", s
);
1433 else if (strncmp (p
, "%sr", 3) == 0)
1436 char *news
= parse_bpf_register (s
, 'r', ®no
);
1438 if (news
== NULL
|| (insn
.has_src
&& regno
!= insn
.src
))
1441 PARSE_ERROR ("expected register r%d, got r%d",
1444 PARSE_ERROR ("expected register name, got '%s'", s
);
1452 else if (strncmp (p
, "%dw", 3) == 0)
1455 char *news
= parse_bpf_register (s
, 'w', ®no
);
1457 if (news
== NULL
|| (insn
.has_dst
&& regno
!= insn
.dst
))
1460 PARSE_ERROR ("expected register r%d, got r%d",
1463 PARSE_ERROR ("expected register name, got '%s'", s
);
1471 else if (strncmp (p
, "%sw", 3) == 0)
1474 char *news
= parse_bpf_register (s
, 'w', ®no
);
1476 if (news
== NULL
|| (insn
.has_src
&& regno
!= insn
.src
))
1479 PARSE_ERROR ("expected register r%d, got r%d",
1482 PARSE_ERROR ("expected register name, got '%s'", s
);
1490 else if (strncmp (p
, "%i32", 4) == 0
1491 || strncmp (p
, "%I32", 4) == 0)
1495 while (*s
== ' ' || *s
== '\t')
1497 if (*s
!= '+' && *s
!= '-')
1499 PARSE_ERROR ("expected `+' or `-', got `%c'", *s
);
1504 s
= parse_expression (s
, &insn
.imm32
);
1507 PARSE_ERROR ("expected signed 32-bit immediate");
1513 else if (strncmp (p
, "%o16", 4) == 0)
1515 while (*s
== ' ' || *s
== '\t')
1517 if (*s
!= '+' && *s
!= '-')
1519 PARSE_ERROR ("expected `+' or `-', got `%c'", *s
);
1523 s
= parse_expression (s
, &insn
.offset16
);
1526 PARSE_ERROR ("expected signed 16-bit offset");
1529 insn
.has_offset16
= 1;
1532 else if (strncmp (p
, "%d16", 4) == 0)
1534 s
= parse_expression (s
, &insn
.disp16
);
1537 PARSE_ERROR ("expected signed 16-bit displacement");
1540 insn
.has_disp16
= 1;
1541 insn
.is_relaxable
= (insn
.disp16
.X_op
!= O_constant
);
1544 else if (strncmp (p
, "%d32", 4) == 0)
1546 s
= parse_expression (s
, &insn
.disp32
);
1549 PARSE_ERROR ("expected signed 32-bit displacement");
1552 insn
.has_disp32
= 1;
1555 else if (strncmp (p
, "%i64", 4) == 0)
1557 s
= parse_expression (s
, &insn
.imm64
);
1560 PARSE_ERROR ("expected signed 64-bit immediate");
1568 as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template);
1572 /* Match a literal character. */
1576 PARSE_ERROR ("expected '%c'", *p
);
1579 /* This is to workaround a bug in as_bad. */
1586 PARSE_ERROR ("expected '%c', got '%s'", *p
, tmp
);
1589 PARSE_ERROR ("expected '%c', got '%c'", *p
, *s
);
1599 /* Allow white spaces at the end of the line. */
1600 while (*s
!= '\0' && (*s
== ' ' || *s
== '\t'))
1603 /* We parsed an instruction successfully. */
1605 PARSE_ERROR ("extra junk at end of line");
1611 as_bad (_("unrecognized instruction `%s'"), str
);
1614 as_bad ("%s", errmsg
);
1620 insn
.id
= opcode
->id
;
1621 insn
.opcode
= opcode
->opcode
;
1625 /* Generate the frags and fixups for the parsed instruction. */
1626 if (do_relax
&& isa_spec
>= BPF_V4
&& insn
.is_relaxable
)
1628 expressionS
*relaxable_exp
= NULL
;
1630 if (insn
.has_disp16
)
1631 relaxable_exp
= &insn
.disp16
;
1635 add_relaxed_insn (&insn
, relaxable_exp
);
1638 add_fixed_insn (&insn
);
1640 /* Emit DWARF2 debugging information. */
1641 dwarf2_emit_insn (insn
.size
);
1644 /* Parse an operand that is machine-specific. */
1647 md_operand (expressionS
*expressionP
)
1649 /* If this hook is invoked it means GAS failed to parse a generic
1650 expression. We should inhibit the as_bad in expr.c, so we can fail
1651 while parsing instruction alternatives. To do that, we change the
1652 expression to not have an O_absent. But then we also need to set
1653 exp_parse_failed to parse_expression above does the right thing. */
1654 ++input_line_pointer
;
1655 expressionP
->X_op
= O_constant
;
1656 expressionP
->X_add_number
= 0;
1657 exp_parse_failed
= 1;
1661 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1667 /* Turn a string in input_line_pointer into a floating point constant
1668 of type TYPE, and store the appropriate bytes in *LITP. The number
1669 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1670 returned, or NULL on OK. */
1673 md_atof (int type
, char *litP
, int *sizeP
)
1675 return ieee_md_atof (type
, litP
, sizeP
, false);
1679 /* Determine whether the equal sign in the given string corresponds to
1680 a BPF instruction, i.e. when it is not to be considered a symbol
1684 bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char *str ATTRIBUTE_UNUSED
)
1688 /* Only pseudo-c instructions can have equal signs, and of these,
1689 all that could be confused with a symbol assignment all start
1690 with a register name. */
1691 if (asm_dialect
== DIALECT_PSEUDOC
)
1693 char *w
= parse_bpf_register (str
, 'w', ®no
);
1694 char *r
= parse_bpf_register (str
, 'r', ®no
);
1696 if ((w
!= NULL
&& *w
== '\0')
1697 || (r
!= NULL
&& *r
== '\0'))
1704 /* Some special processing for a BPF ELF file. */
1707 bpf_elf_final_processing (void)
1709 /* Annotate the BPF ISA version in the ELF flag bits. */
1710 elf_elfheader (stdoutput
)->e_flags
|= (isa_spec
& EF_BPF_CPUVER
);