1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && symbol_constant_p ((X)->X_op_symbol) \
41 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
45 #define MAX_INSN_FIXUPS (5)
52 bfd_reloc_code_real_type reloc
;
55 typedef struct _fixups
58 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
62 static Fixups FixUps
[2];
63 static Fixups
*fixups
;
65 static int do_not_ignore_hash
= 0;
67 typedef int packing_type
;
68 #define PACK_UNSPEC (0) /* Packing order not specified. */
69 #define PACK_PARALLEL (1) /* "||" */
70 #define PACK_LEFT_RIGHT (2) /* "->" */
71 #define PACK_RIGHT_LEFT (3) /* "<-" */
72 static packing_type etype
= PACK_UNSPEC
; /* Used by d10v_cleanup. */
74 /* True if instruction swapping warnings should be inhibited.
76 static boolean flag_warn_suppress_instructionswap
;
78 /* True if instruction packing should be performed when --gstabs is specified.
79 --gstabs-packing, --no-gstabs-packing. */
80 static boolean flag_allow_gstabs_packing
= 1;
82 /* Local functions. */
83 static int reg_name_search
PARAMS ((char *name
));
84 static int register_name
PARAMS ((expressionS
*expressionP
));
85 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
86 static int postfix
PARAMS ((char *p
));
87 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
88 static int get_operands
PARAMS ((expressionS exp
[]));
89 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
90 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
91 static void write_long
PARAMS ((unsigned long insn
, Fixups
*fx
));
92 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
93 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
94 struct d10v_opcode
*opcode2
, unsigned long insn2
, packing_type exec_type
, Fixups
*fx
));
95 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
96 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
97 offsetT value
, int left
, fixS
*fix
));
98 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
99 struct d10v_opcode
*opcode2
, unsigned long insn2
,
100 packing_type exec_type
));
101 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
103 struct option md_longopts
[] =
105 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
106 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
107 #define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1)
108 {"gstabspacking", no_argument
, NULL
, OPTION_GSTABSPACKING
},
109 {"gstabs-packing", no_argument
, NULL
, OPTION_GSTABSPACKING
},
110 #define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2)
111 {"nogstabspacking", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
112 {"no-gstabs-packing", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
113 {NULL
, no_argument
, NULL
, 0}
116 size_t md_longopts_size
= sizeof (md_longopts
);
118 static void d10v_dot_word
PARAMS ((int));
120 /* The target specific pseudo-ops which we support. */
121 const pseudo_typeS md_pseudo_table
[] =
123 { "word", d10v_dot_word
, 2 },
127 /* Opcode hash table. */
128 static struct hash_control
*d10v_hash
;
130 /* Do a binary search of the d10v_predefined_registers array to see if
131 NAME is a valid regiter name. Return the register number from the
132 array on success, or -1 on failure. */
135 reg_name_search (name
)
138 int middle
, low
, high
;
142 high
= d10v_reg_name_cnt () - 1;
146 middle
= (low
+ high
) / 2;
147 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
153 return d10v_predefined_registers
[middle
].value
;
159 /* Check the string at input_line_pointer
160 to see if it is a valid register name. */
163 register_name (expressionP
)
164 expressionS
*expressionP
;
167 char c
, *p
= input_line_pointer
;
170 && *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
177 /* Look to see if it's in the register table. */
178 reg_number
= reg_name_search (input_line_pointer
);
181 expressionP
->X_op
= O_register
;
182 /* Temporarily store a pointer to the string here. */
183 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
184 expressionP
->X_add_number
= reg_number
;
185 input_line_pointer
= p
;
194 check_range (num
, bits
, flags
)
202 /* Don't bother checking 16-bit values. */
206 if (flags
& OPERAND_SHIFT
)
208 /* All special shift operands are unsigned and <= 16.
209 We allow 0 for now. */
216 if (flags
& OPERAND_SIGNED
)
218 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
219 if (flags
& RESTRICTED_NUM3
)
221 if ((long) num
< -2 || (long) num
> 3)
226 max
= (1 << (bits
- 1)) - 1;
227 min
= - (1 << (bits
- 1));
228 if (((long) num
> max
) || ((long) num
< min
))
234 max
= (1 << bits
) - 1;
236 if (((long) num
> max
) || ((long) num
< min
))
243 md_show_usage (stream
)
246 fprintf (stream
, _("D10V options:\n\
247 -O Optimize. Will do some operations in parallel.\n\
248 --gstabs-packing Pack adjacent short instructions together even\n\
249 when --gstabs is specified. On by default.\n\
250 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
251 instructions together.\n"));
255 md_parse_option (c
, arg
)
257 char *arg ATTRIBUTE_UNUSED
;
262 /* Optimize. Will attempt to parallelize operations. */
265 case OPTION_NOWARNSWAP
:
266 flag_warn_suppress_instructionswap
= 1;
268 case OPTION_GSTABSPACKING
:
269 flag_allow_gstabs_packing
= 1;
271 case OPTION_NOGSTABSPACKING
:
272 flag_allow_gstabs_packing
= 0;
281 md_undefined_symbol (name
)
282 char *name ATTRIBUTE_UNUSED
;
287 /* Turn a string in input_line_pointer into a floating point constant
288 of type TYPE, and store the appropriate bytes in *LITP. The number
289 of LITTLENUMS emitted is stored in *SIZEP. An error message is
290 returned, or NULL on OK. */
293 md_atof (type
, litP
, sizeP
)
299 LITTLENUM_TYPE words
[4];
313 return _("bad call to md_atof");
316 t
= atof_ieee (input_line_pointer
, type
, words
);
318 input_line_pointer
= t
;
322 for (i
= 0; i
< prec
; i
++)
324 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
331 md_convert_frag (abfd
, sec
, fragP
)
332 bfd
*abfd ATTRIBUTE_UNUSED
;
333 asection
*sec ATTRIBUTE_UNUSED
;
334 fragS
*fragP ATTRIBUTE_UNUSED
;
340 md_section_align (seg
, addr
)
344 int align
= bfd_get_section_alignment (stdoutput
, seg
);
345 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
351 char *prev_name
= "";
352 struct d10v_opcode
*opcode
;
353 d10v_hash
= hash_new ();
355 /* Insert unique names into hash table. The D10v instruction set
356 has many identical opcode names that have different opcodes based
357 on the operands. This hash table then provides a quick index to
358 the first opcode with a particular name in the opcode table. */
360 for (opcode
= (struct d10v_opcode
*) d10v_opcodes
; opcode
->name
; opcode
++)
362 if (strcmp (prev_name
, opcode
->name
))
364 prev_name
= (char *) opcode
->name
;
365 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
370 FixUps
[0].next
= &FixUps
[1];
371 FixUps
[1].next
= &FixUps
[0];
374 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
375 from an expression. */
381 while (*p
!= '-' && *p
!= '+')
383 if (*p
== 0 || *p
== '\n' || *p
== '\r')
402 static bfd_reloc_code_real_type
404 struct d10v_operand
*op
;
411 if (op
->flags
& OPERAND_ADDR
)
414 return (BFD_RELOC_D10V_10_PCREL_R
);
416 return (BFD_RELOC_D10V_18_PCREL
);
419 return (BFD_RELOC_16
);
422 /* Parse a string of operands. Return an array of expressions. */
428 char *p
= input_line_pointer
;
435 while (*p
== ' ' || *p
== '\t' || *p
== ',')
437 if (*p
== 0 || *p
== '\n' || *p
== '\r')
445 exp
[numops
].X_op
= O_absent
;
449 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
454 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
458 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
467 /* Just skip the trailing paren. */
472 input_line_pointer
= p
;
474 /* Check to see if it might be a register name. */
475 if (!register_name (&exp
[numops
]))
477 /* Parse as an expression. */
480 /* Any expression that involves the indirect addressing
481 cannot also involve immediate addressing. Therefore
482 the use of the hash character is illegal. */
483 int save
= do_not_ignore_hash
;
484 do_not_ignore_hash
= 1;
486 expression (&exp
[numops
]);
488 do_not_ignore_hash
= save
;
491 expression (&exp
[numops
]);
494 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
496 input_line_pointer
+= 5;
497 if (exp
[numops
].X_op
== O_register
)
499 /* If it looked like a register name but was followed by
500 "@word" then it was really a symbol, so change it to
502 exp
[numops
].X_op
= O_symbol
;
503 exp
[numops
].X_add_symbol
=
504 symbol_find_or_make ((char *) exp
[numops
].X_op_symbol
);
507 /* Check for identifier@word+constant. */
508 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
511 expression (&new_exp
);
512 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
515 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
518 memset (&new_exp
, 0, sizeof new_exp
);
519 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
520 new_exp
.X_op
= O_constant
;
521 new_exp
.X_unsigned
= 1;
522 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
523 exp
[numops
].X_op
= O_right_shift
;
526 know (AT_WORD_P (&exp
[numops
]));
529 if (exp
[numops
].X_op
== O_illegal
)
530 as_bad (_("illegal operand"));
531 else if (exp
[numops
].X_op
== O_absent
)
532 as_bad (_("missing operand"));
535 p
= input_line_pointer
;
540 case -1: /* Postdecrement mode. */
541 exp
[numops
].X_op
= O_absent
;
542 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
544 case 1: /* Postincrement mode. */
545 exp
[numops
].X_op
= O_absent
;
546 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
550 exp
[numops
].X_op
= 0;
555 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
564 shift
= d10v_operands
[op_type
].shift
;
568 bits
= d10v_operands
[op_type
].bits
;
570 /* Truncate to the proper number of bits. */
571 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
572 as_bad_where (fix
->fx_file
, fix
->fx_line
,
573 _("operand out of range: %d"), value
);
575 value
&= 0x7FFFFFFF >> (31 - bits
);
576 insn
|= (value
<< shift
);
581 /* Take a pointer to the opcode entry in the opcode table and the
582 array of operand expressions. Return the instruction. */
585 build_insn (opcode
, opers
, insn
)
586 struct d10v_opcode
*opcode
;
590 int i
, bits
, shift
, flags
, format
;
591 unsigned long number
;
593 /* The insn argument is only used for the DIVS kludge. */
598 insn
= opcode
->opcode
;
599 format
= opcode
->format
;
602 for (i
= 0; opcode
->operands
[i
]; i
++)
604 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
605 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
606 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
607 number
= opers
[i
].X_add_number
;
609 if (flags
& OPERAND_REG
)
611 number
&= REGISTER_MASK
;
612 if (format
== LONG_L
)
616 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
618 /* Now create a fixup. */
620 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
621 as_fatal (_("too many fixups"));
623 if (AT_WORD_P (&opers
[i
]))
625 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
626 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
627 opers
[i
].X_op
= O_symbol
;
628 opers
[i
].X_op_symbol
= NULL
; /* Should free it. */
629 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
630 that, it is aligned with the symbol's value. Later,
631 BFD_RELOC_D10V_18 will right shift (symbol_value +
633 number
<<= AT_WORD_RIGHT_SHIFT
;
634 opers
[i
].X_add_number
= number
;
637 fixups
->fix
[fixups
->fc
].reloc
=
638 get_reloc ((struct d10v_operand
*) &d10v_operands
[opcode
->operands
[i
]]);
640 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
641 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
642 fixups
->fix
[fixups
->fc
].size
= 2;
644 fixups
->fix
[fixups
->fc
].size
= 4;
646 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
647 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
648 fixups
->fix
[fixups
->fc
].pcrel
=
649 (flags
& OPERAND_ADDR
) ? true : false;
653 /* Truncate to the proper number of bits. */
654 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
655 as_bad (_("operand out of range: %d"), number
);
656 number
&= 0x7FFFFFFF >> (31 - bits
);
657 insn
= insn
| (number
<< shift
);
660 /* kludge: for DIVS, we need to put the operands in twice */
661 /* on the second pass, format is changed to LONG_R to force
662 the second set of operands to not be shifted over 15. */
663 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
== LONG_L
))
664 insn
= build_insn (opcode
, opers
, insn
);
669 /* Write out a long form instruction. */
672 write_long (insn
, fx
)
677 char *f
= frag_more (4);
680 number_to_chars_bigendian (f
, insn
, 4);
682 for (i
= 0; i
< fx
->fc
; i
++)
684 if (fx
->fix
[i
].reloc
)
686 where
= f
- frag_now
->fr_literal
;
687 if (fx
->fix
[i
].size
== 2)
690 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
691 fx
->fix
[i
].operand
|= 4096;
693 fix_new_exp (frag_now
,
698 fx
->fix
[i
].operand
|2048);
704 /* Write out a short form instruction by itself. */
707 write_1_short (opcode
, insn
, fx
)
708 struct d10v_opcode
*opcode
;
712 char *f
= frag_more (4);
715 if (opcode
->exec_type
& PARONLY
)
716 as_fatal (_("Instruction must be executed in parallel with another instruction."));
718 /* The other container needs to be NOP. */
719 /* According to 4.3.1: for FM=00, sub-instructions performed only
720 by IU cannot be encoded in L-container. */
721 if (opcode
->unit
== IU
)
722 insn
|= FM00
| (NOP
<< 15); /* Right container. */
724 insn
= FM00
| (insn
<< 15) | NOP
; /* Left container. */
726 number_to_chars_bigendian (f
, insn
, 4);
727 for (i
= 0; i
< fx
->fc
; i
++)
729 if (fx
->fix
[i
].reloc
)
731 where
= f
- frag_now
->fr_literal
;
732 if (fx
->fix
[i
].size
== 2)
735 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
736 fx
->fix
[i
].operand
|= 4096;
738 /* If it's an R reloc, we may have to switch it to L. */
739 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
)
740 && (opcode
->unit
!= IU
))
741 fx
->fix
[i
].operand
|= 1024;
743 fix_new_exp (frag_now
,
748 fx
->fix
[i
].operand
|2048);
754 /* Expects two short instructions.
755 If possible, writes out both as a single packed instruction.
756 Otherwise, writes out the first one, packed with a NOP.
757 Returns number of instructions not written out. */
760 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
761 struct d10v_opcode
*opcode1
, *opcode2
;
762 unsigned long insn1
, insn2
;
763 packing_type exec_type
;
770 if ((exec_type
!= PACK_PARALLEL
)
771 && ((opcode1
->exec_type
& PARONLY
) || (opcode2
->exec_type
& PARONLY
)))
772 as_fatal (_("Instruction must be executed in parallel"));
774 if ((opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
775 as_fatal (_("Long instructions may not be combined."));
779 case PACK_UNSPEC
: /* Order not specified. */
780 if (opcode1
->exec_type
& ALONE
)
782 /* Case of a short branch on a separate GAS line.
784 write_1_short (opcode1
, insn1
, fx
->next
);
788 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
791 if (opcode1
->unit
== IU
)
792 insn
= FM00
| (insn2
<< 15) | insn1
;
793 else if (opcode2
->unit
== MU
)
794 insn
= FM00
| (insn2
<< 15) | insn1
;
797 insn
= FM00
| (insn1
<< 15) | insn2
;
798 /* Advance over dummy fixup since packed insn1 in L. */
802 else if (opcode1
->unit
== IU
)
803 /* Reverse sequential with IU opcode1 on right and done first. */
804 insn
= FM10
| (insn2
<< 15) | insn1
;
807 /* Sequential with non-IU opcode1 on left and done first. */
808 insn
= FM01
| (insn1
<< 15) | insn2
;
809 /* Advance over dummy fixup since packed insn1 in L. */
815 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
817 (_("One of these instructions may not be executed in parallel."));
818 if (opcode1
->unit
== IU
)
820 if (opcode2
->unit
== IU
)
821 as_fatal (_("Two IU instructions may not be executed in parallel"));
822 if (!flag_warn_suppress_instructionswap
)
823 as_warn (_("Swapping instruction order"));
824 insn
= FM00
| (insn2
<< 15) | insn1
;
826 else if (opcode2
->unit
== MU
)
828 if (opcode1
->unit
== MU
)
829 as_fatal (_("Two MU instructions may not be executed in parallel"));
830 if (!flag_warn_suppress_instructionswap
)
831 as_warn (_("Swapping instruction order"));
832 insn
= FM00
| (insn2
<< 15) | insn1
;
836 insn
= FM00
| (insn1
<< 15) | insn2
;
837 /* Advance over dummy fixup since packed insn1 in L. */
842 case PACK_LEFT_RIGHT
:
843 if (opcode1
->unit
!= IU
)
844 insn
= FM01
| (insn1
<< 15) | insn2
;
845 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
847 if (!flag_warn_suppress_instructionswap
)
848 as_warn (_("Swapping instruction order"));
849 insn
= FM10
| (insn2
<< 15) | insn1
;
852 as_fatal (_("IU instruction may not be in the left container"));
853 if (opcode1
->exec_type
& ALONE
)
854 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
855 /* Advance over dummy fixup. */
859 case PACK_RIGHT_LEFT
:
860 if (opcode2
->unit
!= MU
)
861 insn
= FM10
| (insn1
<< 15) | insn2
;
862 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
864 if (!flag_warn_suppress_instructionswap
)
865 as_warn (_("Swapping instruction order"));
866 insn
= FM01
| (insn2
<< 15) | insn1
;
869 as_fatal (_("MU instruction may not be in the right container"));
870 if (opcode2
->exec_type
& ALONE
)
871 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
872 /* Advance over dummy fixup. */
877 as_fatal (_("unknown execution type passed to write_2_short()"));
881 number_to_chars_bigendian (f
, insn
, 4);
883 /* Process fixup chains.
884 Note that the packing code above advanced fx conditionally.
885 dlindsay@cygnus.com: There's something subtle going on here involving
886 _dummy_first_bfd_reloc_code_real. This is related to the
887 difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
888 a fixup is done in the L or R container. A bug in this code
889 can pass Plum Hall fine, yet still affect hand-written assembler. */
891 for (j
= 0; j
< 2; j
++)
893 for (i
= 0; i
< fx
->fc
; i
++)
895 if (fx
->fix
[i
].reloc
)
897 where
= f
- frag_now
->fr_literal
;
898 if (fx
->fix
[i
].size
== 2)
901 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0))
902 fx
->fix
[i
].operand
|= 1024;
904 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
905 fx
->fix
[i
].operand
|= 4096;
907 fix_new_exp (frag_now
,
912 fx
->fix
[i
].operand
|2048);
921 /* Check 2 instructions and determine if they can be safely
922 executed in parallel. Return 1 if they can be. */
925 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
926 struct d10v_opcode
*op1
, *op2
;
927 unsigned long insn1
, insn2
;
928 packing_type exec_type
;
930 int i
, j
, flags
, mask
, shift
, regno
;
931 unsigned long ins
, mod
[2], used
[2];
932 struct d10v_opcode
*op
;
934 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
935 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
936 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
937 || (op1
->unit
== IU
&& op2
->unit
== IU
)
938 || (op1
->unit
== MU
&& op2
->unit
== MU
))
941 /* If this is auto parallization, and either instruction is a branch,
943 if (exec_type
== PACK_UNSPEC
944 && (op1
->exec_type
& ALONE
|| op2
->exec_type
& ALONE
))
947 /* The idea here is to create two sets of bitmasks (mod and used)
948 which indicate which registers are modified or used by each
949 instruction. The operation can only be done in parallel if
950 instruction 1 and instruction 2 modify different registers, and
951 the first instruction does not modify registers that the second
952 is using (The second instruction can modify registers that the
953 first is using as they are only written back after the first
954 instruction has completed). Accesses to control registers, PSW,
955 and memory are treated as accesses to a single register. So if
956 both instructions write memory or if the first instruction writes
957 memory and the second reads, then they cannot be done in
958 parallel. Likewise, if the first instruction mucks with the psw
959 and the second reads the PSW (which includes C, F0, and F1), then
960 they cannot operate safely in parallel. */
962 /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
965 /* cr (not psw) 18 */
969 for (j
= 0; j
< 2; j
++)
981 mod
[j
] = used
[j
] = 0;
982 if (op
->exec_type
& BRANCH_LINK
)
985 for (i
= 0; op
->operands
[i
]; i
++)
987 flags
= d10v_operands
[op
->operands
[i
]].flags
;
988 shift
= d10v_operands
[op
->operands
[i
]].shift
;
989 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
990 if (flags
& OPERAND_REG
)
992 regno
= (ins
>> shift
) & mask
;
993 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
995 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc. */
1002 else if (flags
& (OPERAND_FFLAG
| OPERAND_CFLAG
))
1005 if (flags
& OPERAND_DEST
)
1007 mod
[j
] |= 1 << regno
;
1008 if (flags
& OPERAND_EVEN
)
1009 mod
[j
] |= 1 << (regno
+ 1);
1013 used
[j
] |= 1 << regno
;
1014 if (flags
& OPERAND_EVEN
)
1015 used
[j
] |= 1 << (regno
+ 1);
1017 /* Auto inc/dec also modifies the register. */
1018 if (op
->operands
[i
+ 1] != 0
1019 && (d10v_operands
[op
->operands
[i
+ 1]].flags
1020 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
1021 mod
[j
] |= 1 << regno
;
1024 else if (flags
& OPERAND_ATMINUS
)
1026 /* SP implicitly used/modified. */
1031 if (op
->exec_type
& RMEM
)
1033 else if (op
->exec_type
& WMEM
)
1035 else if (op
->exec_type
& RF0
)
1037 else if (op
->exec_type
& WF0
)
1039 else if (op
->exec_type
& WCAR
)
1042 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
1047 /* This is the main entry point for the machine-dependent assembler.
1048 STR points to a machine-dependent instruction. This function is
1049 supposed to emit the frags/bytes it assembles to. For the D10V, it
1050 mostly handles the special VLIW parsing and packing and leaves the
1051 difficult stuff to do_assemble(). */
1053 static unsigned long prev_insn
;
1054 static struct d10v_opcode
*prev_opcode
= 0;
1055 static subsegT prev_subseg
;
1056 static segT prev_seg
= 0;;
1062 /* etype is saved extype. For multi-line instructions. */
1064 packing_type extype
= PACK_UNSPEC
; /* Parallel, etc. */
1066 struct d10v_opcode
*opcode
;
1070 if (etype
== PACK_UNSPEC
)
1072 /* Look for the special multiple instruction separators. */
1073 str2
= strstr (str
, "||");
1075 extype
= PACK_PARALLEL
;
1078 str2
= strstr (str
, "->");
1080 extype
= PACK_LEFT_RIGHT
;
1083 str2
= strstr (str
, "<-");
1085 extype
= PACK_RIGHT_LEFT
;
1088 /* STR2 points to the separator, if there is one. */
1093 /* If two instructions are present and we already have one saved,
1094 then first write out the saved one. */
1097 /* Assemble first instruction and save it. */
1098 prev_insn
= do_assemble (str
, &prev_opcode
);
1099 if (prev_insn
== (unsigned long) -1)
1100 as_fatal (_("can't find opcode "));
1101 fixups
= fixups
->next
;
1106 insn
= do_assemble (str
, &opcode
);
1107 if (insn
== (unsigned long) -1)
1109 if (extype
!= PACK_UNSPEC
)
1114 as_fatal (_("can't find opcode "));
1117 if (etype
!= PACK_UNSPEC
)
1120 etype
= PACK_UNSPEC
;
1123 /* If this is a long instruction, write it and any previous short
1125 if (opcode
->format
& LONG_OPCODE
)
1127 if (extype
!= PACK_UNSPEC
)
1128 as_fatal (_("Unable to mix instructions as specified"));
1130 write_long (insn
, fixups
);
1137 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1141 && (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1143 /* No instructions saved. */
1148 if (extype
!= PACK_UNSPEC
)
1149 as_fatal (_("Unable to mix instructions as specified"));
1150 /* Save last instruction so it may be packed on next pass. */
1151 prev_opcode
= opcode
;
1154 prev_subseg
= now_subseg
;
1155 fixups
= fixups
->next
;
1159 /* Assemble a single instruction.
1160 Return an opcode, or -1 (an invalid opcode) on error. */
1162 static unsigned long
1163 do_assemble (str
, opcode
)
1165 struct d10v_opcode
**opcode
;
1167 unsigned char *op_start
, *save
;
1168 unsigned char *op_end
;
1171 expressionS myops
[6];
1174 /* Drop leading whitespace. */
1178 /* Find the opcode end. */
1179 for (op_start
= op_end
= (unsigned char *) (str
);
1182 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1185 name
[nlen
] = tolower (op_start
[nlen
]);
1193 /* Find the first opcode with the proper name. */
1194 *opcode
= (struct d10v_opcode
*) hash_find (d10v_hash
, name
);
1195 if (*opcode
== NULL
)
1196 as_fatal (_("unknown opcode: %s"), name
);
1198 save
= input_line_pointer
;
1199 input_line_pointer
= op_end
;
1200 *opcode
= find_opcode (*opcode
, myops
);
1203 input_line_pointer
= save
;
1205 insn
= build_insn ((*opcode
), myops
, 0);
1209 /* Find the symbol which has the same name as the register in EXP. */
1212 find_symbol_matching_register (exp
)
1217 if (exp
->X_op
!= O_register
)
1220 /* Find the name of the register. */
1221 for (i
= d10v_reg_name_cnt (); i
--;)
1222 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1228 /* Now see if a symbol has been defined with the same name. */
1229 return symbol_find (d10v_predefined_registers
[i
].name
);
1232 /* Get a pointer to an entry in the opcode table.
1233 The function must look at all opcodes with the same name and use
1234 the operands to choose the correct opcode. */
1236 static struct d10v_opcode
*
1237 find_opcode (opcode
, myops
)
1238 struct d10v_opcode
*opcode
;
1239 expressionS myops
[];
1242 struct d10v_opcode
*next_opcode
;
1244 /* Get all the operands and save them as expressions. */
1245 get_operands (myops
);
1247 /* Now see if the operand is a fake. If so, find the correct size
1248 instruction, if possible. */
1249 if (opcode
->format
== OPCODE_FAKE
)
1251 int opnum
= opcode
->operands
[0];
1254 if (myops
[opnum
].X_op
== O_register
)
1256 myops
[opnum
].X_op
= O_symbol
;
1257 myops
[opnum
].X_add_symbol
=
1258 symbol_find_or_make ((char *) myops
[opnum
].X_op_symbol
);
1259 myops
[opnum
].X_add_number
= 0;
1260 myops
[opnum
].X_op_symbol
= NULL
;
1263 next_opcode
= opcode
+ 1;
1265 /* If the first operand is supposed to be a register, make sure
1266 we got a valid one. */
1267 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1268 if (flags
& OPERAND_REG
)
1270 int X_op
= myops
[0].X_op
;
1271 int num
= myops
[0].X_add_number
;
1273 if (X_op
!= O_register
1275 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1276 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1278 as_bad (_("bad opcode or operands"));
1283 if (myops
[opnum
].X_op
== O_constant
1284 || (myops
[opnum
].X_op
== O_symbol
1285 && S_IS_DEFINED (myops
[opnum
].X_add_symbol
)
1286 && (S_GET_SEGMENT (myops
[opnum
].X_add_symbol
) == now_seg
)))
1288 for (i
= 0; opcode
->operands
[i
+ 1]; i
++)
1290 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1291 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1292 if (flags
& OPERAND_ADDR
)
1295 if (myops
[opnum
].X_op
== O_constant
)
1297 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1304 unsigned long current_position
;
1305 unsigned long symbol_position
;
1306 unsigned long value
;
1307 boolean found_symbol
;
1309 /* Calculate the address of the current instruction
1310 and the address of the symbol. Do this by summing
1311 the offsets of previous frags until we reach the
1312 frag containing the symbol, and the current frag. */
1313 sym_frag
= symbol_get_frag (myops
[opnum
].X_add_symbol
);
1314 found_symbol
= false;
1317 obstack_next_free (&frchain_now
->frch_obstack
)
1318 - frag_now
->fr_literal
;
1319 symbol_position
= S_GET_VALUE (myops
[opnum
].X_add_symbol
);
1321 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1323 current_position
+= f
->fr_fix
+ f
->fr_offset
;
1326 found_symbol
= true;
1329 symbol_position
+= f
->fr_fix
+ f
->fr_offset
;
1332 value
= symbol_position
;
1334 if (flags
& OPERAND_ADDR
)
1335 value
-= current_position
;
1337 if (AT_WORD_P (&myops
[opnum
]))
1342 if (!check_range (value
, bits
, flags
))
1346 else if (!check_range (value
, bits
, flags
))
1351 as_fatal (_("value out of range"));
1355 /* Not a constant, so use a long instruction. */
1362 /* Now search the opcode table table for one with operands
1363 that matches what we've got. */
1367 for (i
= 0; opcode
->operands
[i
]; i
++)
1369 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1370 int X_op
= myops
[i
].X_op
;
1371 int num
= myops
[i
].X_add_number
;
1379 if (flags
& OPERAND_REG
)
1381 if ((X_op
!= O_register
)
1383 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1384 | OPERAND_FFLAG
| OPERAND_CFLAG
1385 | OPERAND_CONTROL
)))
1392 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1393 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1394 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1395 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1396 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1402 /* Unfortunatly, for the indirect operand in
1403 instructions such as ``ldb r1, @(c,r14)'' this
1404 function can be passed X_op == O_register (because
1405 'c' is a valid register name). However we cannot
1406 just ignore the case when X_op == O_register but
1407 flags & OPERAND_REG is null, so we check to see if a
1408 symbol of the same name as the register exists. If
1409 the symbol does exist, then the parser was unable to
1410 distinguish the two cases and we fix things here.
1413 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1415 symbolS
*sym
= find_symbol_matching_register (&myops
[i
]);
1419 myops
[i
].X_op
= X_op
= O_symbol
;
1420 myops
[i
].X_add_symbol
= sym
;
1424 (_("illegal operand - register name found where none expected"));
1428 /* We're only done if the operands matched so far AND there
1429 are no more to check. */
1430 if (match
&& myops
[i
].X_op
== 0)
1435 next_opcode
= opcode
+ 1;
1437 if (next_opcode
->opcode
== 0)
1440 if (strcmp (next_opcode
->name
, opcode
->name
))
1443 opcode
= next_opcode
;
1449 as_bad (_("bad opcode or operands"));
1453 /* Check that all registers that are required to be even are.
1454 Also, if any operands were marked as registers, but were really symbols,
1456 for (i
= 0; opcode
->operands
[i
]; i
++)
1458 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1459 (myops
[i
].X_add_number
& 1))
1460 as_fatal (_("Register number must be EVEN"));
1461 if (myops
[i
].X_op
== O_register
)
1463 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1465 myops
[i
].X_op
= O_symbol
;
1466 myops
[i
].X_add_symbol
=
1467 symbol_find_or_make ((char *) myops
[i
].X_op_symbol
);
1468 myops
[i
].X_add_number
= 0;
1469 myops
[i
].X_op_symbol
= NULL
;
1476 /* If while processing a fixup, a reloc really needs to be created.
1477 Then it is done here. */
1480 tc_gen_reloc (seg
, fixp
)
1481 asection
*seg ATTRIBUTE_UNUSED
;
1485 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1486 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1487 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1488 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1489 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1490 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1492 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1493 _("reloc %d not supported by object file format"),
1494 (int) fixp
->fx_r_type
);
1498 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1499 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1500 reloc
->address
= fixp
->fx_offset
;
1502 reloc
->addend
= fixp
->fx_addnumber
;
1508 md_estimate_size_before_relax (fragp
, seg
)
1509 fragS
*fragp ATTRIBUTE_UNUSED
;
1510 asection
*seg ATTRIBUTE_UNUSED
;
1517 md_pcrel_from_section (fixp
, sec
)
1521 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1522 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1523 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1525 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1529 md_apply_fix3 (fixp
, valuep
, seg
)
1532 segT seg ATTRIBUTE_UNUSED
;
1540 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1545 else if (fixp
->fx_pcrel
)
1549 value
= fixp
->fx_offset
;
1550 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1552 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1553 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1556 /* We don't actually support subtracting a symbol. */
1557 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1558 _("expression too complex"));
1563 op_type
= fixp
->fx_r_type
;
1570 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1573 else if (op_type
& 4096)
1576 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1580 get_reloc ((struct d10v_operand
*) &d10v_operands
[op_type
]);
1583 /* Fetch the instruction, insert the fully resolved operand
1584 value, and stuff the instruction back again. */
1585 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1586 insn
= bfd_getb32 ((unsigned char *) where
);
1588 switch (fixp
->fx_r_type
)
1590 case BFD_RELOC_D10V_10_PCREL_L
:
1591 case BFD_RELOC_D10V_10_PCREL_R
:
1592 case BFD_RELOC_D10V_18_PCREL
:
1593 case BFD_RELOC_D10V_18
:
1594 /* Instruction addresses are always right-shifted by 2. */
1595 value
>>= AT_WORD_RIGHT_SHIFT
;
1596 if (fixp
->fx_size
== 2)
1597 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1600 struct d10v_opcode
*rep
, *repi
;
1602 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1603 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1604 if ((insn
& FM11
) == FM11
1605 && ( (repi
!= NULL
&& (insn
& repi
->mask
) == (unsigned) repi
->opcode
)
1606 || (rep
!= NULL
&& (insn
& rep
->mask
) == (unsigned) rep
->opcode
))
1609 (_("line %d: rep or repi must include at least 4 instructions"),
1612 d10v_insert_operand (insn
, op_type
, (offsetT
) value
, left
, fixp
);
1613 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1617 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1620 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1623 case BFD_RELOC_VTABLE_INHERIT
:
1624 case BFD_RELOC_VTABLE_ENTRY
:
1629 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1630 fixp
->fx_line
, fixp
->fx_r_type
);
1635 /* d10v_cleanup() is called after the assembler has finished parsing
1636 the input file, when a label is read from the input file, or when a
1637 stab directive is output. Because the D10V assembler sometimes
1638 saves short instructions to see if it can package them with the
1639 next instruction, there may be a short instruction that still needs
1642 NOTE: accesses a global, etype.
1643 NOTE: invoked by various macros such as md_cleanup: see. */
1651 /* If cleanup was invoked because the assembler encountered, e.g., a
1652 user label, we write out the pending instruction, if any. If it
1653 was invoked because the assembler is outputting a piece of line
1654 debugging information, though, we write out the pending
1655 instruction only if the --no-gstabs-packing command line switch
1656 has been specified. */
1658 && etype
== PACK_UNSPEC
1659 && (! outputting_stabs_line_debug
|| ! flag_allow_gstabs_packing
))
1662 subseg
= now_subseg
;
1665 subseg_set (prev_seg
, prev_subseg
);
1667 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1669 subseg_set (seg
, subseg
);
1675 /* Like normal .word, except support @word. */
1676 /* Clobbers input_line_pointer, checks end-of-line. */
1679 d10v_dot_word (dummy
)
1680 int dummy ATTRIBUTE_UNUSED
;
1685 if (is_it_end_of_statement ())
1687 demand_empty_rest_of_line ();
1694 if (!strncasecmp (input_line_pointer
, "@word", 5))
1696 exp
.X_add_number
= 0;
1697 input_line_pointer
+= 5;
1700 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1701 &exp
, 0, BFD_RELOC_D10V_18
);
1704 emit_expr (&exp
, 2);
1706 while (*input_line_pointer
++ == ',');
1708 input_line_pointer
--; /* Put terminator back into stream. */
1709 demand_empty_rest_of_line ();
1712 /* Mitsubishi asked that we support some old syntax that apparently
1713 had immediate operands starting with '#'. This is in some of their
1714 sample code but is not documented (although it appears in some
1715 examples in their assembler manual). For now, we'll solve this
1716 compatibility problem by simply ignoring any '#' at the beginning
1719 /* Operands that begin with '#' should fall through to here. */
1723 md_operand (expressionP
)
1724 expressionS
*expressionP
;
1726 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1728 input_line_pointer
++;
1729 expression (expressionP
);
1734 d10v_fix_adjustable (fixP
)
1737 if (fixP
->fx_addsy
== NULL
)
1740 /* Prevent all adjustments to global symbols. */
1741 if (S_IS_EXTERN (fixP
->fx_addsy
))
1743 if (S_IS_WEAK (fixP
->fx_addsy
))
1746 /* We need the symbol name for the VTABLE entries. */
1747 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1748 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1755 d10v_force_relocation (fixp
)
1758 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1759 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)