1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* If we have selected a cpu we are generating instructions for. */
808 static int cpu_arch_tune_set
= 0;
810 /* Cpu we are generating instructions for. */
811 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
813 /* CPU instruction set architecture used. */
814 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
816 /* CPU feature flags of instruction set architecture used. */
817 i386_cpu_flags cpu_arch_isa_flags
;
819 /* If set, conditional jumps are not automatically promoted to handle
820 larger than a byte offset. */
821 static bool no_cond_jump_promotion
= false;
823 /* This will be set from an expression parser hook if there's any
824 applicable operator involved in an expression. */
827 expr_operator_present
,
831 /* Encode SSE instructions with VEX prefix. */
832 static unsigned int sse2avx
;
834 /* Encode aligned vector move as unaligned vector move. */
835 static unsigned int use_unaligned_vector_move
;
837 /* Maximum permitted vector size. */
838 #define VSZ_DEFAULT VSZ512
839 static unsigned int vector_size
= VSZ_DEFAULT
;
841 /* Encode scalar AVX instructions with specific vector length. */
848 /* Encode VEX WIG instructions with specific vex.w. */
855 /* Encode scalar EVEX LIG instructions with specific vector length. */
863 /* Encode EVEX WIG instructions with specific evex.w. */
870 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
871 static enum rc_type evexrcig
= rne
;
873 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
874 static symbolS
*GOT_symbol
;
876 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
877 unsigned int x86_dwarf2_return_column
;
879 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
880 int x86_cie_data_alignment
;
882 /* Interface to relax_segment.
883 There are 3 major relax states for 386 jump insns because the
884 different types of jumps add different sizes to frags when we're
885 figuring out what sort of jump to choose to reach a given label.
887 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
888 branches which are handled by md_estimate_size_before_relax() and
889 i386_generic_table_relax_frag(). */
892 #define UNCOND_JUMP 0
894 #define COND_JUMP86 2
895 #define BRANCH_PADDING 3
896 #define BRANCH_PREFIX 4
897 #define FUSED_JCC_PADDING 5
902 #define SMALL16 (SMALL | CODE16)
904 #define BIG16 (BIG | CODE16)
908 #define INLINE __inline__
914 #define ENCODE_RELAX_STATE(type, size) \
915 ((relax_substateT) (((type) << 2) | (size)))
916 #define TYPE_FROM_RELAX_STATE(s) \
918 #define DISP_SIZE_FROM_RELAX_STATE(s) \
919 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
921 /* This table is used by relax_frag to promote short jumps to long
922 ones where necessary. SMALL (short) jumps may be promoted to BIG
923 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
924 don't allow a short jump in a 32 bit code segment to be promoted to
925 a 16 bit offset jump because it's slower (requires data size
926 prefix), and doesn't work, unless the destination is in the bottom
927 64k of the code segment (The top 16 bits of eip are zeroed). */
929 const relax_typeS md_relax_table
[] =
932 1) most positive reach of this state,
933 2) most negative reach of this state,
934 3) how many bytes this mode will have in the variable part of the frag
935 4) which index into the table to try if we can't fit into this one. */
937 /* UNCOND_JUMP states. */
938 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
939 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
940 /* dword jmp adds 4 bytes to frag:
941 0 extra opcode bytes, 4 displacement bytes. */
943 /* word jmp adds 2 byte2 to frag:
944 0 extra opcode bytes, 2 displacement bytes. */
947 /* COND_JUMP states. */
948 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
949 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
950 /* dword conditionals adds 5 bytes to frag:
951 1 extra opcode byte, 4 displacement bytes. */
953 /* word conditionals add 3 bytes to frag:
954 1 extra opcode byte, 2 displacement bytes. */
957 /* COND_JUMP86 states. */
958 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
959 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
960 /* dword conditionals adds 5 bytes to frag:
961 1 extra opcode byte, 4 displacement bytes. */
963 /* word conditionals add 4 bytes to frag:
964 1 displacement byte and a 3 byte long branch insn. */
968 #define ARCH(n, t, f, s) \
969 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
971 #define SUBARCH(n, e, d, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
973 CPU_ ## d ## _FLAGS }
974 #define VECARCH(n, e, d, v) \
975 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
976 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
978 static const arch_entry cpu_arch
[] =
980 /* Do not replace the first two entries - i386_target_format() and
981 set_cpu_arch() rely on them being there in this order. */
982 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
983 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
984 ARCH (i8086
, UNKNOWN
, NONE
, false),
985 ARCH (i186
, UNKNOWN
, 186, false),
986 ARCH (i286
, UNKNOWN
, 286, false),
987 ARCH (i386
, I386
, 386, false),
988 ARCH (i486
, I486
, 486, false),
989 ARCH (i586
, PENTIUM
, 586, false),
990 ARCH (pentium
, PENTIUM
, 586, false),
991 ARCH (i686
, I686
, 686, false),
992 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
993 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
994 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
995 ARCH (pentium4
, PENTIUM4
, P4
, false),
996 ARCH (prescott
, NOCONA
, CORE
, false),
997 ARCH (nocona
, NOCONA
, NOCONA
, false),
998 ARCH (yonah
, CORE
, CORE
, true),
999 ARCH (core
, CORE
, CORE
, false),
1000 ARCH (merom
, CORE2
, CORE2
, true),
1001 ARCH (core2
, CORE2
, CORE2
, false),
1002 ARCH (corei7
, COREI7
, COREI7
, false),
1003 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1004 ARCH (k6
, K6
, K6
, false),
1005 ARCH (k6_2
, K6
, K6_2
, false),
1006 ARCH (athlon
, ATHLON
, ATHLON
, false),
1007 ARCH (sledgehammer
, K8
, K8
, true),
1008 ARCH (opteron
, K8
, K8
, false),
1009 ARCH (k8
, K8
, K8
, false),
1010 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1011 ARCH (bdver1
, BD
, BDVER1
, false),
1012 ARCH (bdver2
, BD
, BDVER2
, false),
1013 ARCH (bdver3
, BD
, BDVER3
, false),
1014 ARCH (bdver4
, BD
, BDVER4
, false),
1015 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1016 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1017 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1018 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1019 ARCH (btver1
, BT
, BTVER1
, false),
1020 ARCH (btver2
, BT
, BTVER2
, false),
1022 SUBARCH (8087, 8087, ANY_8087
, false),
1023 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1024 SUBARCH (287, 287, ANY_287
, false),
1025 SUBARCH (387, 387, ANY_387
, false),
1026 SUBARCH (687, 687, ANY_687
, false),
1027 SUBARCH (cmov
, CMOV
, CMOV
, false),
1028 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1029 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1030 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1031 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1032 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1033 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1034 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1035 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1036 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1037 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1038 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1039 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1040 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1041 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1042 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1043 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1044 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1045 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1046 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1047 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1048 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1049 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1050 SUBARCH (smx
, SMX
, SMX
, false),
1051 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1052 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1053 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1054 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1055 SUBARCH (aes
, AES
, ANY_AES
, false),
1056 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1057 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1058 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1059 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1060 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1061 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1062 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1063 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1064 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1065 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1066 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1067 SUBARCH (cx16
, CX16
, CX16
, false),
1068 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1069 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1070 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1071 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1072 SUBARCH (hle
, HLE
, HLE
, false),
1073 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1074 SUBARCH (tsx
, TSX
, TSX
, false),
1075 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1076 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1077 SUBARCH (nop
, NOP
, NOP
, false),
1078 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1079 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1080 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1081 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1082 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1083 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1084 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1085 SUBARCH (abm
, ABM
, ABM
, false),
1086 SUBARCH (bmi
, BMI
, BMI
, false),
1087 SUBARCH (tbm
, TBM
, TBM
, false),
1088 SUBARCH (adx
, ADX
, ADX
, false),
1089 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1090 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1091 SUBARCH (smap
, SMAP
, SMAP
, false),
1092 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1093 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1094 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1095 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1096 SUBARCH (se1
, SE1
, SE1
, false),
1097 SUBARCH (clwb
, CLWB
, CLWB
, false),
1098 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1099 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1100 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1101 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1102 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1103 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1104 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1105 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1106 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1107 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1108 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1109 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1110 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1111 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1112 SUBARCH (ibt
, IBT
, IBT
, false),
1113 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1114 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1115 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1116 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1117 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1118 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1119 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1120 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1121 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1122 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1123 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1124 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1125 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1126 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1127 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1128 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1129 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1130 ANY_AVX512_VP2INTERSECT
, reset
),
1131 SUBARCH (tdx
, TDX
, TDX
, false),
1132 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1133 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1134 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1135 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1136 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1137 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1138 SUBARCH (kl
, KL
, ANY_KL
, false),
1139 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1140 SUBARCH (uintr
, UINTR
, UINTR
, false),
1141 SUBARCH (hreset
, HRESET
, HRESET
, false),
1142 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1143 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1144 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1145 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1146 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1147 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1148 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1149 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1150 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1151 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1152 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1153 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1154 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1155 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1156 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1157 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1158 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1159 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1166 /* Like s_lcomm_internal in gas/read.c but the alignment string
1167 is allowed to be optional. */
1170 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1177 && *input_line_pointer
== ',')
1179 align
= parse_align (needs_align
- 1);
1181 if (align
== (addressT
) -1)
1196 bss_alloc (symbolP
, size
, align
);
1201 pe_lcomm (int needs_align
)
1203 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1207 const pseudo_typeS md_pseudo_table
[] =
1209 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1210 {"align", s_align_bytes
, 0},
1212 {"align", s_align_ptwo
, 0},
1214 {"arch", set_cpu_arch
, 0},
1218 {"lcomm", pe_lcomm
, 1},
1220 {"ffloat", float_cons
, 'f'},
1221 {"dfloat", float_cons
, 'd'},
1222 {"tfloat", float_cons
, 'x'},
1223 {"hfloat", float_cons
, 'h'},
1224 {"bfloat16", float_cons
, 'b'},
1226 {"slong", signed_cons
, 4},
1227 {"insn", s_insn
, 0},
1228 {"noopt", s_ignore
, 0},
1229 {"optim", s_ignore
, 0},
1230 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1231 {"code16", set_code_flag
, CODE_16BIT
},
1232 {"code32", set_code_flag
, CODE_32BIT
},
1234 {"code64", set_code_flag
, CODE_64BIT
},
1236 {"intel_syntax", set_intel_syntax
, 1},
1237 {"att_syntax", set_intel_syntax
, 0},
1238 {"intel_mnemonic", set_intel_mnemonic
, 1},
1239 {"att_mnemonic", set_intel_mnemonic
, 0},
1240 {"allow_index_reg", set_allow_index_reg
, 1},
1241 {"disallow_index_reg", set_allow_index_reg
, 0},
1242 {"sse_check", set_check
, 0},
1243 {"operand_check", set_check
, 1},
1244 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1245 {"largecomm", handle_large_common
, 0},
1247 {"file", dwarf2_directive_file
, 0},
1248 {"loc", dwarf2_directive_loc
, 0},
1249 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1252 {"secrel32", pe_directive_secrel
, 0},
1253 {"secidx", pe_directive_secidx
, 0},
1258 /* For interface with expression (). */
1259 extern char *input_line_pointer
;
1261 /* Hash table for instruction mnemonic lookup. */
1262 static htab_t op_hash
;
1264 /* Hash table for register lookup. */
1265 static htab_t reg_hash
;
1267 /* Various efficient no-op patterns for aligning code labels.
1268 Note: Don't try to assemble the instructions in the comments.
1269 0L and 0w are not legal. */
1270 static const unsigned char f32_1
[] =
1272 static const unsigned char f32_2
[] =
1273 {0x66,0x90}; /* xchg %ax,%ax */
1274 static const unsigned char f32_3
[] =
1275 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1276 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1277 static const unsigned char f32_5
[] =
1278 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1279 static const unsigned char f32_6
[] =
1280 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1281 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1282 static const unsigned char f32_8
[] =
1283 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1284 static const unsigned char f64_3
[] =
1285 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1286 static const unsigned char f64_4
[] =
1287 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1288 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1289 static const unsigned char f64_6
[] =
1290 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1291 static const unsigned char f64_7
[] =
1292 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1293 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1294 static const unsigned char f64_9
[] =
1295 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1296 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1297 static const unsigned char f16_3
[] =
1298 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1299 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1300 static const unsigned char f16_5
[] =
1301 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1302 static const unsigned char jump_disp8
[] =
1303 {0xeb}; /* jmp disp8 */
1304 static const unsigned char jump32_disp32
[] =
1305 {0xe9}; /* jmp disp32 */
1306 static const unsigned char jump16_disp32
[] =
1307 {0x66,0xe9}; /* jmp disp32 */
1308 /* 32-bit NOPs patterns. */
1309 static const unsigned char *const f32_patt
[] = {
1310 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1312 /* 64-bit NOPs patterns. */
1313 static const unsigned char *const f64_patt
[] = {
1314 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1316 /* 16-bit NOPs patterns. */
1317 static const unsigned char *const f16_patt
[] = {
1318 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1320 /* nopl (%[re]ax) */
1321 static const unsigned char alt_3
[] =
1323 /* nopl 0(%[re]ax) */
1324 static const unsigned char alt_4
[] =
1325 {0x0f,0x1f,0x40,0x00};
1326 /* nopl 0(%[re]ax,%[re]ax,1) */
1327 #define alt_5 (alt_6 + 1)
1328 /* nopw 0(%[re]ax,%[re]ax,1) */
1329 static const unsigned char alt_6
[] =
1330 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1331 /* nopl 0L(%[re]ax) */
1332 static const unsigned char alt_7
[] =
1333 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1334 /* nopl 0L(%[re]ax,%[re]ax,1) */
1335 #define alt_8 (alt_9 + 1)
1336 /* nopw 0L(%[re]ax,%[re]ax,1) */
1337 static const unsigned char alt_9
[] =
1338 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1339 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1340 #define alt_10 (alt_11 + 1)
1341 /* data16 nopw %cs:0L(%eax,%eax,1) */
1342 static const unsigned char alt_11
[] =
1343 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1344 /* 32-bit and 64-bit NOPs patterns. */
1345 static const unsigned char *const alt_patt
[] = {
1346 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1347 alt_9
, alt_10
, alt_11
1350 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1351 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1354 i386_output_nops (char *where
, const unsigned char *const *patt
,
1355 int count
, int max_single_nop_size
)
1358 /* Place the longer NOP first. */
1361 const unsigned char *nops
;
1363 if (max_single_nop_size
< 1)
1365 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1366 max_single_nop_size
);
1370 nops
= patt
[max_single_nop_size
- 1];
1371 last
= count
% max_single_nop_size
;
1374 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1375 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1379 nops
= patt
[last
- 1];
1380 memcpy (where
+ offset
, nops
, last
);
1385 fits_in_imm7 (offsetT num
)
1387 return (num
& 0x7f) == num
;
1391 fits_in_imm31 (offsetT num
)
1393 return (num
& 0x7fffffff) == num
;
1396 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1397 single NOP instruction LIMIT. */
1400 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1402 const unsigned char *const *patt
= NULL
;
1403 int max_single_nop_size
;
1404 /* Maximum number of NOPs before switching to jump over NOPs. */
1405 int max_number_of_nops
;
1407 switch (fragP
->fr_type
)
1412 case rs_machine_dependent
:
1413 /* Allow NOP padding for jumps and calls. */
1414 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1415 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1422 /* We need to decide which NOP sequence to use for 32bit and
1423 64bit. When -mtune= is used:
1425 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1426 PROCESSOR_GENERIC32, f32_patt will be used.
1427 2. For the rest, alt_patt will be used.
1429 When -mtune= isn't used, alt_patt will be used if
1430 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1433 When -march= or .arch is used, we can't use anything beyond
1434 cpu_arch_isa_flags. */
1436 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1439 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1440 /* Limit number of NOPs to 2 in 16-bit mode. */
1441 max_number_of_nops
= 2;
1445 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1446 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1448 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1449 explicitly disabled. */
1450 switch (fragP
->tc_frag_data
.tune
)
1452 case PROCESSOR_UNKNOWN
:
1453 /* We use cpu_arch_isa_flags to check if we SHOULD
1454 optimize with nops. */
1455 if (fragP
->tc_frag_data
.isanop
)
1459 case PROCESSOR_PENTIUMPRO
:
1460 case PROCESSOR_PENTIUM4
:
1461 case PROCESSOR_NOCONA
:
1462 case PROCESSOR_CORE
:
1463 case PROCESSOR_CORE2
:
1464 case PROCESSOR_COREI7
:
1465 case PROCESSOR_GENERIC64
:
1467 case PROCESSOR_ATHLON
:
1469 case PROCESSOR_AMDFAM10
:
1471 case PROCESSOR_ZNVER
:
1473 if (fragP
->tc_frag_data
.cpunop
)
1477 case PROCESSOR_I386
:
1478 case PROCESSOR_I486
:
1479 case PROCESSOR_PENTIUM
:
1480 case PROCESSOR_I686
:
1481 case PROCESSOR_IAMCU
:
1482 case PROCESSOR_GENERIC32
:
1484 case PROCESSOR_NONE
:
1490 switch (fragP
->tc_frag_data
.tune
)
1492 case PROCESSOR_UNKNOWN
:
1493 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1494 PROCESSOR_UNKNOWN. */
1499 /* We use cpu_arch_isa_flags to check if we CAN optimize
1501 if (fragP
->tc_frag_data
.isanop
)
1505 case PROCESSOR_NONE
:
1510 if (patt
!= alt_patt
)
1512 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1513 : ARRAY_SIZE (f64_patt
);
1514 /* Limit number of NOPs to 2 for older processors. */
1515 max_number_of_nops
= 2;
1519 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1520 /* Limit number of NOPs to 7 for newer processors. */
1521 max_number_of_nops
= 7;
1526 limit
= max_single_nop_size
;
1528 if (fragP
->fr_type
== rs_fill_nop
)
1530 /* Output NOPs for .nop directive. */
1531 if (limit
> max_single_nop_size
)
1533 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1534 _("invalid single nop size: %d "
1535 "(expect within [0, %d])"),
1536 limit
, max_single_nop_size
);
1540 else if (fragP
->fr_type
!= rs_machine_dependent
)
1541 fragP
->fr_var
= count
;
1543 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1545 /* Generate jump over NOPs. */
1546 offsetT disp
= count
- 2;
1547 if (fits_in_imm7 (disp
))
1549 /* Use "jmp disp8" if possible. */
1551 where
[0] = jump_disp8
[0];
1557 unsigned int size_of_jump
;
1559 if (flag_code
== CODE_16BIT
)
1561 where
[0] = jump16_disp32
[0];
1562 where
[1] = jump16_disp32
[1];
1567 where
[0] = jump32_disp32
[0];
1571 count
-= size_of_jump
+ 4;
1572 if (!fits_in_imm31 (count
))
1574 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1575 _("jump over nop padding out of range"));
1579 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1580 where
+= size_of_jump
+ 4;
1584 /* Generate multiple NOPs. */
1585 i386_output_nops (where
, patt
, count
, limit
);
1589 operand_type_all_zero (const union i386_operand_type
*x
)
1591 switch (ARRAY_SIZE(x
->array
))
1602 return !x
->array
[0];
1609 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1611 switch (ARRAY_SIZE(x
->array
))
1627 x
->bitfield
.class = ClassNone
;
1628 x
->bitfield
.instance
= InstanceNone
;
1632 operand_type_equal (const union i386_operand_type
*x
,
1633 const union i386_operand_type
*y
)
1635 switch (ARRAY_SIZE(x
->array
))
1638 if (x
->array
[2] != y
->array
[2])
1642 if (x
->array
[1] != y
->array
[1])
1646 return x
->array
[0] == y
->array
[0];
1654 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1658 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1659 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1660 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1661 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1662 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1663 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1664 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1665 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1666 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1667 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1669 gas_assert (cpu
< CpuAttrEnums
);
1671 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1674 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1676 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1677 i386_cpu_flags f
= { .array
[0] = 0 };
1679 switch (ARRAY_SIZE(a
.array
))
1682 f
.array
[CpuAttrEnums
/ bps
]
1683 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1684 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1685 f
.array
[CpuAttrEnums
/ bps
+ 1]
1686 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1693 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1699 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1701 switch (ARRAY_SIZE(x
->array
))
1720 return !x
->array
[0];
1727 cpu_flags_equal (const union i386_cpu_flags
*x
,
1728 const union i386_cpu_flags
*y
)
1730 switch (ARRAY_SIZE(x
->array
))
1733 if (x
->array
[4] != y
->array
[4])
1737 if (x
->array
[3] != y
->array
[3])
1741 if (x
->array
[2] != y
->array
[2])
1745 if (x
->array
[1] != y
->array
[1])
1749 return x
->array
[0] == y
->array
[0];
1757 cpu_flags_check_cpu64 (const insn_template
*t
)
1759 return flag_code
== CODE_64BIT
1760 ? !t
->cpu
.bitfield
.cpuno64
1761 : !t
->cpu
.bitfield
.cpu64
;
1764 static INLINE i386_cpu_flags
1765 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1767 switch (ARRAY_SIZE (x
.array
))
1770 x
.array
[4] &= y
.array
[4];
1773 x
.array
[3] &= y
.array
[3];
1776 x
.array
[2] &= y
.array
[2];
1779 x
.array
[1] &= y
.array
[1];
1782 x
.array
[0] &= y
.array
[0];
1790 static INLINE i386_cpu_flags
1791 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1793 switch (ARRAY_SIZE (x
.array
))
1796 x
.array
[4] |= y
.array
[4];
1799 x
.array
[3] |= y
.array
[3];
1802 x
.array
[2] |= y
.array
[2];
1805 x
.array
[1] |= y
.array
[1];
1808 x
.array
[0] |= y
.array
[0];
1816 static INLINE i386_cpu_flags
1817 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1819 switch (ARRAY_SIZE (x
.array
))
1822 x
.array
[4] &= ~y
.array
[4];
1825 x
.array
[3] &= ~y
.array
[3];
1828 x
.array
[2] &= ~y
.array
[2];
1831 x
.array
[1] &= ~y
.array
[1];
1834 x
.array
[0] &= ~y
.array
[0];
1842 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1844 static INLINE
bool need_evex_encoding (void)
1846 return i
.vec_encoding
== vex_encoding_evex
1847 || i
.vec_encoding
== vex_encoding_evex512
1851 #define CPU_FLAGS_ARCH_MATCH 0x1
1852 #define CPU_FLAGS_64BIT_MATCH 0x2
1854 #define CPU_FLAGS_PERFECT_MATCH \
1855 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1857 /* Return CPU flags match bits. */
1860 cpu_flags_match (const insn_template
*t
)
1862 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1863 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1865 x
.bitfield
.cpu64
= 0;
1866 x
.bitfield
.cpuno64
= 0;
1868 if (cpu_flags_all_zero (&x
))
1870 /* This instruction is available on all archs. */
1871 match
|= CPU_FLAGS_ARCH_MATCH
;
1875 /* This instruction is available only on some archs. */
1876 i386_cpu_flags cpu
= cpu_arch_flags
;
1878 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1879 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1881 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1882 know that EVEX encoding will be needed. */
1883 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1884 && x
.bitfield
.cpuavx512f
)
1886 if (need_evex_encoding ())
1888 x
.bitfield
.cpuavx
= 0;
1889 x
.bitfield
.cpuavx2
= 0;
1891 /* need_evex_encoding() isn't reliable before operands were
1893 else if (i
.operands
)
1895 x
.bitfield
.cpuavx512f
= 0;
1896 x
.bitfield
.cpuavx512vl
= 0;
1897 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1898 x
.bitfield
.cpuavx
= 0;
1903 /* AVX512VL is no standalone feature - match it and then strip it. */
1904 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1906 x
.bitfield
.cpuavx512vl
= 0;
1908 /* AVX and AVX2 present at the same time express an operand size
1909 dependency - strip AVX2 for the purposes here. The operand size
1910 dependent check occurs in check_vecOperands(). */
1911 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1912 x
.bitfield
.cpuavx2
= 0;
1914 cpu
= cpu_flags_and (x
, cpu
);
1915 if (!cpu_flags_all_zero (&cpu
))
1917 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1919 if ((need_evex_encoding ()
1920 ? cpu
.bitfield
.cpuavx512f
1921 : cpu
.bitfield
.cpuavx
)
1922 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1923 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1924 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1925 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1926 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1927 match
|= CPU_FLAGS_ARCH_MATCH
;
1929 else if (x
.bitfield
.cpuavx
)
1931 /* We need to check a few extra flags with AVX. */
1932 if (cpu
.bitfield
.cpuavx
1933 && (!t
->opcode_modifier
.sse2avx
1934 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1935 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1936 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1937 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1938 match
|= CPU_FLAGS_ARCH_MATCH
;
1940 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1941 match
|= CPU_FLAGS_ARCH_MATCH
;
1942 else if (x
.bitfield
.cpuavx512f
)
1944 /* We need to check a few extra flags with AVX512F. */
1945 if (cpu
.bitfield
.cpuavx512f
1946 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1947 match
|= CPU_FLAGS_ARCH_MATCH
;
1950 match
|= CPU_FLAGS_ARCH_MATCH
;
1956 static INLINE i386_operand_type
1957 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1959 if (x
.bitfield
.class != y
.bitfield
.class)
1960 x
.bitfield
.class = ClassNone
;
1961 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1962 x
.bitfield
.instance
= InstanceNone
;
1964 switch (ARRAY_SIZE (x
.array
))
1967 x
.array
[2] &= y
.array
[2];
1970 x
.array
[1] &= y
.array
[1];
1973 x
.array
[0] &= y
.array
[0];
1981 static INLINE i386_operand_type
1982 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1984 gas_assert (y
.bitfield
.class == ClassNone
);
1985 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1987 switch (ARRAY_SIZE (x
.array
))
1990 x
.array
[2] &= ~y
.array
[2];
1993 x
.array
[1] &= ~y
.array
[1];
1996 x
.array
[0] &= ~y
.array
[0];
2004 static INLINE i386_operand_type
2005 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2007 gas_assert (x
.bitfield
.class == ClassNone
||
2008 y
.bitfield
.class == ClassNone
||
2009 x
.bitfield
.class == y
.bitfield
.class);
2010 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2011 y
.bitfield
.instance
== InstanceNone
||
2012 x
.bitfield
.instance
== y
.bitfield
.instance
);
2014 switch (ARRAY_SIZE (x
.array
))
2017 x
.array
[2] |= y
.array
[2];
2020 x
.array
[1] |= y
.array
[1];
2023 x
.array
[0] |= y
.array
[0];
2031 static INLINE i386_operand_type
2032 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2034 gas_assert (y
.bitfield
.class == ClassNone
);
2035 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2037 switch (ARRAY_SIZE (x
.array
))
2040 x
.array
[2] ^= y
.array
[2];
2043 x
.array
[1] ^= y
.array
[1];
2046 x
.array
[0] ^= y
.array
[0];
2054 static const i386_operand_type anydisp
= {
2055 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2067 operand_type_check (i386_operand_type t
, enum operand_type c
)
2072 return t
.bitfield
.class == Reg
;
2075 return (t
.bitfield
.imm8
2079 || t
.bitfield
.imm32s
2080 || t
.bitfield
.imm64
);
2083 return (t
.bitfield
.disp8
2084 || t
.bitfield
.disp16
2085 || t
.bitfield
.disp32
2086 || t
.bitfield
.disp64
);
2089 return (t
.bitfield
.disp8
2090 || t
.bitfield
.disp16
2091 || t
.bitfield
.disp32
2092 || t
.bitfield
.disp64
2093 || t
.bitfield
.baseindex
);
2102 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2103 between operand GIVEN and opeand WANTED for instruction template T. */
2106 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2109 return !((i
.types
[given
].bitfield
.byte
2110 && !t
->operand_types
[wanted
].bitfield
.byte
)
2111 || (i
.types
[given
].bitfield
.word
2112 && !t
->operand_types
[wanted
].bitfield
.word
)
2113 || (i
.types
[given
].bitfield
.dword
2114 && !t
->operand_types
[wanted
].bitfield
.dword
)
2115 || (i
.types
[given
].bitfield
.qword
2116 && (!t
->operand_types
[wanted
].bitfield
.qword
2117 /* Don't allow 64-bit (memory) operands outside of 64-bit
2118 mode, when they're used where a 64-bit GPR could also
2119 be used. Checking is needed for Intel Syntax only. */
2121 && flag_code
!= CODE_64BIT
2122 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2123 || t
->operand_types
[wanted
].bitfield
.class == Accum
2124 || t
->opcode_modifier
.isstring
))))
2125 || (i
.types
[given
].bitfield
.tbyte
2126 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2129 /* Return 1 if there is no conflict in SIMD register between operand
2130 GIVEN and opeand WANTED for instruction template T. */
2133 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2136 return !((i
.types
[given
].bitfield
.xmmword
2137 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2138 || (i
.types
[given
].bitfield
.ymmword
2139 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2140 || (i
.types
[given
].bitfield
.zmmword
2141 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2142 || (i
.types
[given
].bitfield
.tmmword
2143 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2146 /* Return 1 if there is no conflict in any size between operand GIVEN
2147 and opeand WANTED for instruction template T. */
2150 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2153 return (match_operand_size (t
, wanted
, given
)
2154 && !((i
.types
[given
].bitfield
.unspecified
2155 && !i
.broadcast
.type
2156 && !i
.broadcast
.bytes
2157 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2158 || (i
.types
[given
].bitfield
.fword
2159 && !t
->operand_types
[wanted
].bitfield
.fword
)
2160 /* For scalar opcode templates to allow register and memory
2161 operands at the same time, some special casing is needed
2162 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2163 down-conversion vpmov*. */
2164 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2165 && t
->operand_types
[wanted
].bitfield
.byte
2166 + t
->operand_types
[wanted
].bitfield
.word
2167 + t
->operand_types
[wanted
].bitfield
.dword
2168 + t
->operand_types
[wanted
].bitfield
.qword
2169 > !!t
->opcode_modifier
.broadcast
)
2170 ? (i
.types
[given
].bitfield
.xmmword
2171 || i
.types
[given
].bitfield
.ymmword
2172 || i
.types
[given
].bitfield
.zmmword
)
2173 : !match_simd_size(t
, wanted
, given
))));
2176 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2177 operands for instruction template T, and it has MATCH_REVERSE set if there
2178 is no size conflict on any operands for the template with operands reversed
2179 (and the template allows for reversing in the first place). */
2181 #define MATCH_STRAIGHT 1
2182 #define MATCH_REVERSE 2
2184 static INLINE
unsigned int
2185 operand_size_match (const insn_template
*t
)
2187 unsigned int j
, match
= MATCH_STRAIGHT
;
2189 /* Don't check non-absolute jump instructions. */
2190 if (t
->opcode_modifier
.jump
2191 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2194 /* Check memory and accumulator operand size. */
2195 for (j
= 0; j
< i
.operands
; j
++)
2197 if (i
.types
[j
].bitfield
.class != Reg
2198 && i
.types
[j
].bitfield
.class != RegSIMD
2199 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2202 if (t
->operand_types
[j
].bitfield
.class == Reg
2203 && !match_operand_size (t
, j
, j
))
2209 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2210 && !match_simd_size (t
, j
, j
))
2216 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2217 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2223 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2230 if (!t
->opcode_modifier
.d
)
2233 /* Check reverse. */
2234 gas_assert (i
.operands
>= 2);
2236 for (j
= 0; j
< i
.operands
; j
++)
2238 unsigned int given
= i
.operands
- j
- 1;
2240 /* For FMA4 and XOP insns VEX.W controls just the first two
2241 register operands. */
2242 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2243 given
= j
< 2 ? 1 - j
: j
;
2245 if (t
->operand_types
[j
].bitfield
.class == Reg
2246 && !match_operand_size (t
, j
, given
))
2249 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2250 && !match_simd_size (t
, j
, given
))
2253 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2254 && (!match_operand_size (t
, j
, given
)
2255 || !match_simd_size (t
, j
, given
)))
2258 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2262 return match
| MATCH_REVERSE
;
2266 operand_type_match (i386_operand_type overlap
,
2267 i386_operand_type given
)
2269 i386_operand_type temp
= overlap
;
2271 temp
.bitfield
.unspecified
= 0;
2272 temp
.bitfield
.byte
= 0;
2273 temp
.bitfield
.word
= 0;
2274 temp
.bitfield
.dword
= 0;
2275 temp
.bitfield
.fword
= 0;
2276 temp
.bitfield
.qword
= 0;
2277 temp
.bitfield
.tbyte
= 0;
2278 temp
.bitfield
.xmmword
= 0;
2279 temp
.bitfield
.ymmword
= 0;
2280 temp
.bitfield
.zmmword
= 0;
2281 temp
.bitfield
.tmmword
= 0;
2282 if (operand_type_all_zero (&temp
))
2285 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2289 i
.error
= operand_type_mismatch
;
2293 /* If given types g0 and g1 are registers they must be of the same type
2294 unless the expected operand type register overlap is null.
2295 Intel syntax sized memory operands are also checked here. */
2298 operand_type_register_match (i386_operand_type g0
,
2299 i386_operand_type t0
,
2300 i386_operand_type g1
,
2301 i386_operand_type t1
)
2303 if (g0
.bitfield
.class != Reg
2304 && g0
.bitfield
.class != RegSIMD
2305 && (g0
.bitfield
.unspecified
2306 || !operand_type_check (g0
, anymem
)))
2309 if (g1
.bitfield
.class != Reg
2310 && g1
.bitfield
.class != RegSIMD
2311 && (g1
.bitfield
.unspecified
2312 || !operand_type_check (g1
, anymem
)))
2315 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2316 && g0
.bitfield
.word
== g1
.bitfield
.word
2317 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2318 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2319 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2320 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2321 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2324 /* If expectations overlap in no more than a single size, all is fine. */
2325 g0
= operand_type_and (t0
, t1
);
2326 if (g0
.bitfield
.byte
2330 + g0
.bitfield
.xmmword
2331 + g0
.bitfield
.ymmword
2332 + g0
.bitfield
.zmmword
<= 1)
2335 i
.error
= register_type_mismatch
;
2340 static INLINE
unsigned int
2341 register_number (const reg_entry
*r
)
2343 unsigned int nr
= r
->reg_num
;
2345 if (r
->reg_flags
& RegRex
)
2348 if (r
->reg_flags
& RegVRex
)
2354 static INLINE
unsigned int
2355 mode_from_disp_size (i386_operand_type t
)
2357 if (t
.bitfield
.disp8
)
2359 else if (t
.bitfield
.disp16
2360 || t
.bitfield
.disp32
)
2367 fits_in_signed_byte (addressT num
)
2369 return num
+ 0x80 <= 0xff;
2373 fits_in_unsigned_byte (addressT num
)
2379 fits_in_unsigned_word (addressT num
)
2381 return num
<= 0xffff;
2385 fits_in_signed_word (addressT num
)
2387 return num
+ 0x8000 <= 0xffff;
2391 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2396 return num
+ 0x80000000 <= 0xffffffff;
2398 } /* fits_in_signed_long() */
2401 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2406 return num
<= 0xffffffff;
2408 } /* fits_in_unsigned_long() */
2410 static INLINE valueT
extend_to_32bit_address (addressT num
)
2413 if (fits_in_unsigned_long(num
))
2414 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2416 if (!fits_in_signed_long (num
))
2417 return num
& 0xffffffff;
2424 fits_in_disp8 (offsetT num
)
2426 int shift
= i
.memshift
;
2432 mask
= (1 << shift
) - 1;
2434 /* Return 0 if NUM isn't properly aligned. */
2438 /* Check if NUM will fit in 8bit after shift. */
2439 return fits_in_signed_byte (num
>> shift
);
2443 fits_in_imm4 (offsetT num
)
2445 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2446 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2449 static i386_operand_type
2450 smallest_imm_type (offsetT num
)
2452 i386_operand_type t
;
2454 operand_type_set (&t
, 0);
2455 t
.bitfield
.imm64
= 1;
2457 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2459 /* This code is disabled on the 486 because all the Imm1 forms
2460 in the opcode table are slower on the i486. They're the
2461 versions with the implicitly specified single-position
2462 displacement, which has another syntax if you really want to
2464 t
.bitfield
.imm1
= 1;
2465 t
.bitfield
.imm8
= 1;
2466 t
.bitfield
.imm8s
= 1;
2467 t
.bitfield
.imm16
= 1;
2468 t
.bitfield
.imm32
= 1;
2469 t
.bitfield
.imm32s
= 1;
2471 else if (fits_in_signed_byte (num
))
2473 if (fits_in_unsigned_byte (num
))
2474 t
.bitfield
.imm8
= 1;
2475 t
.bitfield
.imm8s
= 1;
2476 t
.bitfield
.imm16
= 1;
2477 t
.bitfield
.imm32
= 1;
2478 t
.bitfield
.imm32s
= 1;
2480 else if (fits_in_unsigned_byte (num
))
2482 t
.bitfield
.imm8
= 1;
2483 t
.bitfield
.imm16
= 1;
2484 t
.bitfield
.imm32
= 1;
2485 t
.bitfield
.imm32s
= 1;
2487 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2489 t
.bitfield
.imm16
= 1;
2490 t
.bitfield
.imm32
= 1;
2491 t
.bitfield
.imm32s
= 1;
2493 else if (fits_in_signed_long (num
))
2495 t
.bitfield
.imm32
= 1;
2496 t
.bitfield
.imm32s
= 1;
2498 else if (fits_in_unsigned_long (num
))
2499 t
.bitfield
.imm32
= 1;
2505 offset_in_range (offsetT val
, int size
)
2511 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2512 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2514 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2516 case sizeof (val
): return val
;
2520 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2521 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2522 (uint64_t) val
, (uint64_t) (val
& mask
));
2527 static INLINE
const char *insn_name (const insn_template
*t
)
2529 return &i386_mnemonics
[t
->mnem_off
];
2542 a. PREFIX_EXIST if attempting to add a prefix where one from the
2543 same class already exists.
2544 b. PREFIX_LOCK if lock prefix is added.
2545 c. PREFIX_REP if rep/repne prefix is added.
2546 d. PREFIX_DS if ds prefix is added.
2547 e. PREFIX_OTHER if other prefix is added.
2550 static enum PREFIX_GROUP
2551 add_prefix (unsigned int prefix
)
2553 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2556 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2557 && flag_code
== CODE_64BIT
)
2559 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2560 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2561 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2562 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2573 case DS_PREFIX_OPCODE
:
2576 case CS_PREFIX_OPCODE
:
2577 case ES_PREFIX_OPCODE
:
2578 case FS_PREFIX_OPCODE
:
2579 case GS_PREFIX_OPCODE
:
2580 case SS_PREFIX_OPCODE
:
2584 case REPNE_PREFIX_OPCODE
:
2585 case REPE_PREFIX_OPCODE
:
2590 case LOCK_PREFIX_OPCODE
:
2599 case ADDR_PREFIX_OPCODE
:
2603 case DATA_PREFIX_OPCODE
:
2607 if (i
.prefix
[q
] != 0)
2615 i
.prefix
[q
] |= prefix
;
2618 as_bad (_("same type of prefix used twice"));
2624 update_code_flag (int value
, int check
)
2626 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2628 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2630 as_error (_("64bit mode not supported on `%s'."),
2631 cpu_arch_name
? cpu_arch_name
: default_arch
);
2635 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2637 as_error (_("32bit mode not supported on `%s'."),
2638 cpu_arch_name
? cpu_arch_name
: default_arch
);
2642 flag_code
= (enum flag_code
) value
;
2644 stackop_size
= '\0';
2648 set_code_flag (int value
)
2650 update_code_flag (value
, 0);
2654 set_16bit_gcc_code_flag (int new_code_flag
)
2656 flag_code
= (enum flag_code
) new_code_flag
;
2657 if (flag_code
!= CODE_16BIT
)
2659 stackop_size
= LONG_MNEM_SUFFIX
;
2663 set_intel_syntax (int syntax_flag
)
2665 /* Find out if register prefixing is specified. */
2666 int ask_naked_reg
= 0;
2669 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2672 int e
= get_symbol_name (&string
);
2674 if (strcmp (string
, "prefix") == 0)
2676 else if (strcmp (string
, "noprefix") == 0)
2679 as_bad (_("bad argument to syntax directive."));
2680 (void) restore_line_pointer (e
);
2682 demand_empty_rest_of_line ();
2684 intel_syntax
= syntax_flag
;
2686 if (ask_naked_reg
== 0)
2687 allow_naked_reg
= (intel_syntax
2688 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2690 allow_naked_reg
= (ask_naked_reg
< 0);
2692 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2694 register_prefix
= allow_naked_reg
? "" : "%";
2698 set_intel_mnemonic (int mnemonic_flag
)
2700 intel_mnemonic
= mnemonic_flag
;
2704 set_allow_index_reg (int flag
)
2706 allow_index_reg
= flag
;
2710 set_check (int what
)
2712 enum check_kind
*kind
;
2717 kind
= &operand_check
;
2728 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2731 int e
= get_symbol_name (&string
);
2733 if (strcmp (string
, "none") == 0)
2735 else if (strcmp (string
, "warning") == 0)
2736 *kind
= check_warning
;
2737 else if (strcmp (string
, "error") == 0)
2738 *kind
= check_error
;
2740 as_bad (_("bad argument to %s_check directive."), str
);
2741 (void) restore_line_pointer (e
);
2744 as_bad (_("missing argument for %s_check directive"), str
);
2746 demand_empty_rest_of_line ();
2750 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2751 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2754 static const char *arch
;
2756 /* Intel MCU is only supported on ELF. */
2762 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2763 use default_arch. */
2764 arch
= cpu_arch_name
;
2766 arch
= default_arch
;
2769 /* If we are targeting Intel MCU, we must enable it. */
2770 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2771 == new_flag
.bitfield
.cpuiamcu
)
2774 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2779 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2781 if (cpu_sub_arch_name
)
2782 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2783 pfx
, name
, (const char *) NULL
);
2785 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2788 static void isa_enable (unsigned int idx
)
2790 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2792 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2794 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2795 cpu_arch_flags
= flags
;
2798 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2801 static void isa_disable (unsigned int idx
)
2803 i386_cpu_flags flags
2804 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2806 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2808 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2809 cpu_arch_flags
= flags
;
2813 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2817 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2819 typedef struct arch_stack_entry
2821 const struct arch_stack_entry
*prev
;
2824 i386_cpu_flags flags
;
2825 i386_cpu_flags isa_flags
;
2826 enum processor_type isa
;
2827 enum flag_code flag_code
;
2828 unsigned int vector_size
;
2830 bool no_cond_jump_promotion
;
2832 static const arch_stack_entry
*arch_stack_top
;
2840 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2842 as_bad (_("missing cpu architecture"));
2843 input_line_pointer
++;
2847 e
= get_symbol_name (&s
);
2850 if (strcmp (string
, "push") == 0)
2852 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2854 top
->name
= cpu_arch_name
;
2855 if (cpu_sub_arch_name
)
2856 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2858 top
->sub_name
= NULL
;
2859 top
->flags
= cpu_arch_flags
;
2860 top
->isa
= cpu_arch_isa
;
2861 top
->isa_flags
= cpu_arch_isa_flags
;
2862 top
->flag_code
= flag_code
;
2863 top
->vector_size
= vector_size
;
2864 top
->stackop_size
= stackop_size
;
2865 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2867 top
->prev
= arch_stack_top
;
2868 arch_stack_top
= top
;
2870 (void) restore_line_pointer (e
);
2871 demand_empty_rest_of_line ();
2875 if (strcmp (string
, "pop") == 0)
2877 const arch_stack_entry
*top
= arch_stack_top
;
2880 as_bad (_(".arch stack is empty"));
2881 else if (top
->flag_code
!= flag_code
2882 || top
->stackop_size
!= stackop_size
)
2884 static const unsigned int bits
[] = {
2890 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2891 bits
[top
->flag_code
],
2892 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2896 arch_stack_top
= top
->prev
;
2898 cpu_arch_name
= top
->name
;
2899 free (cpu_sub_arch_name
);
2900 cpu_sub_arch_name
= top
->sub_name
;
2901 cpu_arch_flags
= top
->flags
;
2902 cpu_arch_isa
= top
->isa
;
2903 cpu_arch_isa_flags
= top
->isa_flags
;
2904 vector_size
= top
->vector_size
;
2905 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2910 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2915 if (strcmp (string
, "default") == 0)
2917 if (strcmp (default_arch
, "iamcu") == 0)
2918 string
= default_arch
;
2921 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2923 cpu_arch_name
= NULL
;
2924 free (cpu_sub_arch_name
);
2925 cpu_sub_arch_name
= NULL
;
2926 cpu_arch_flags
= cpu_unknown_flags
;
2927 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2928 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2929 if (!cpu_arch_tune_set
)
2930 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2932 vector_size
= VSZ_DEFAULT
;
2934 j
= ARRAY_SIZE (cpu_arch
) + 1;
2938 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2940 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2941 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2945 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2947 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2949 as_bad (_("64bit mode not supported on `%s'."),
2951 (void) restore_line_pointer (e
);
2952 ignore_rest_of_line ();
2956 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2958 as_bad (_("32bit mode not supported on `%s'."),
2960 (void) restore_line_pointer (e
);
2961 ignore_rest_of_line ();
2965 cpu_arch_name
= cpu_arch
[j
].name
;
2966 free (cpu_sub_arch_name
);
2967 cpu_sub_arch_name
= NULL
;
2968 cpu_arch_flags
= cpu_arch
[j
].enable
;
2969 cpu_arch_isa
= cpu_arch
[j
].type
;
2970 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2971 if (!cpu_arch_tune_set
)
2972 cpu_arch_tune
= cpu_arch_isa
;
2974 vector_size
= VSZ_DEFAULT
;
2976 pre_386_16bit_warned
= false;
2980 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2985 (void) restore_line_pointer (e
);
2987 switch (cpu_arch
[j
].vsz
)
2993 #ifdef SVR4_COMMENT_CHARS
2994 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2996 if (*input_line_pointer
== '/')
2999 ++input_line_pointer
;
3000 switch (get_absolute_expression ())
3002 case 512: vector_size
= VSZ512
; break;
3003 case 256: vector_size
= VSZ256
; break;
3004 case 128: vector_size
= VSZ128
; break;
3006 as_bad (_("Unrecognized vector size specifier"));
3007 ignore_rest_of_line ();
3014 vector_size
= VSZ_DEFAULT
;
3018 demand_empty_rest_of_line ();
3023 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3025 /* Disable an ISA extension. */
3026 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3027 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3028 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3032 if (cpu_arch
[j
].vsz
== vsz_set
)
3033 vector_size
= VSZ_DEFAULT
;
3035 (void) restore_line_pointer (e
);
3036 demand_empty_rest_of_line ();
3041 if (j
== ARRAY_SIZE (cpu_arch
))
3042 as_bad (_("no such architecture: `%s'"), string
);
3044 *input_line_pointer
= e
;
3046 no_cond_jump_promotion
= 0;
3047 if (*input_line_pointer
== ','
3048 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3050 ++input_line_pointer
;
3051 e
= get_symbol_name (&s
);
3054 if (strcmp (string
, "nojumps") == 0)
3055 no_cond_jump_promotion
= 1;
3056 else if (strcmp (string
, "jumps") == 0)
3059 as_bad (_("no such architecture modifier: `%s'"), string
);
3061 (void) restore_line_pointer (e
);
3064 demand_empty_rest_of_line ();
3067 enum bfd_architecture
3070 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3072 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3073 || flag_code
== CODE_64BIT
)
3074 as_fatal (_("Intel MCU is 32bit ELF only"));
3075 return bfd_arch_iamcu
;
3078 return bfd_arch_i386
;
3084 if (startswith (default_arch
, "x86_64"))
3086 if (default_arch
[6] == '\0')
3087 return bfd_mach_x86_64
;
3089 return bfd_mach_x64_32
;
3091 else if (!strcmp (default_arch
, "i386")
3092 || !strcmp (default_arch
, "iamcu"))
3094 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3096 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3097 as_fatal (_("Intel MCU is 32bit ELF only"));
3098 return bfd_mach_i386_iamcu
;
3101 return bfd_mach_i386_i386
;
3104 as_fatal (_("unknown architecture"));
3107 #include "opcodes/i386-tbl.h"
3112 /* Support pseudo prefixes like {disp32}. */
3113 lex_type
['{'] = LEX_BEGIN_NAME
;
3115 /* Initialize op_hash hash table. */
3116 op_hash
= str_htab_create ();
3119 const insn_template
*const *sets
= i386_op_sets
;
3120 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3122 /* Type checks to compensate for the conversion through void * which
3123 occurs during hash table insertion / lookup. */
3124 (void) sizeof (sets
== ¤t_templates
->start
);
3125 (void) sizeof (end
== ¤t_templates
->end
);
3126 for (; sets
< end
; ++sets
)
3127 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3128 as_fatal (_("duplicate %s"), insn_name (*sets
));
3131 /* Initialize reg_hash hash table. */
3132 reg_hash
= str_htab_create ();
3134 const reg_entry
*regtab
;
3135 unsigned int regtab_size
= i386_regtab_size
;
3137 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3139 switch (regtab
->reg_type
.bitfield
.class)
3142 if (regtab
->reg_type
.bitfield
.dword
)
3144 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3147 else if (regtab
->reg_type
.bitfield
.tbyte
)
3149 /* There's no point inserting st(<N>) in the hash table, as
3150 parentheses aren't included in register_chars[] anyway. */
3151 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3158 switch (regtab
->reg_num
)
3160 case 0: reg_es
= regtab
; break;
3161 case 2: reg_ss
= regtab
; break;
3162 case 3: reg_ds
= regtab
; break;
3167 if (!regtab
->reg_num
)
3172 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3173 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3177 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3182 for (c
= 0; c
< 256; c
++)
3184 if (ISDIGIT (c
) || ISLOWER (c
))
3186 mnemonic_chars
[c
] = c
;
3187 register_chars
[c
] = c
;
3188 operand_chars
[c
] = c
;
3190 else if (ISUPPER (c
))
3192 mnemonic_chars
[c
] = TOLOWER (c
);
3193 register_chars
[c
] = mnemonic_chars
[c
];
3194 operand_chars
[c
] = c
;
3196 #ifdef SVR4_COMMENT_CHARS
3197 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3198 operand_chars
[c
] = c
;
3202 operand_chars
[c
] = c
;
3205 mnemonic_chars
['_'] = '_';
3206 mnemonic_chars
['-'] = '-';
3207 mnemonic_chars
['.'] = '.';
3209 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3210 operand_chars
[(unsigned char) *p
] = *p
;
3211 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3212 operand_chars
[(unsigned char) *p
] = *p
;
3215 if (flag_code
== CODE_64BIT
)
3217 #if defined (OBJ_COFF) && defined (TE_PE)
3218 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3221 x86_dwarf2_return_column
= 16;
3223 x86_cie_data_alignment
= -8;
3224 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3225 x86_sframe_cfa_sp_reg
= 7;
3226 x86_sframe_cfa_fp_reg
= 6;
3231 x86_dwarf2_return_column
= 8;
3232 x86_cie_data_alignment
= -4;
3235 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3236 can be turned into BRANCH_PREFIX frag. */
3237 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3242 i386_print_statistics (FILE *file
)
3244 htab_print_statistics (file
, "i386 opcode", op_hash
);
3245 htab_print_statistics (file
, "i386 register", reg_hash
);
3251 htab_delete (op_hash
);
3252 htab_delete (reg_hash
);
3257 /* Debugging routines for md_assemble. */
3258 static void pte (insn_template
*);
3259 static void pt (i386_operand_type
);
3260 static void pe (expressionS
*);
3261 static void ps (symbolS
*);
3264 pi (const char *line
, i386_insn
*x
)
3268 fprintf (stdout
, "%s: template ", line
);
3270 fprintf (stdout
, " address: base %s index %s scale %x\n",
3271 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3272 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3273 x
->log2_scale_factor
);
3274 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3275 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3276 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3277 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3278 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3279 (x
->rex
& REX_W
) != 0,
3280 (x
->rex
& REX_R
) != 0,
3281 (x
->rex
& REX_X
) != 0,
3282 (x
->rex
& REX_B
) != 0);
3283 for (j
= 0; j
< x
->operands
; j
++)
3285 fprintf (stdout
, " #%d: ", j
+ 1);
3287 fprintf (stdout
, "\n");
3288 if (x
->types
[j
].bitfield
.class == Reg
3289 || x
->types
[j
].bitfield
.class == RegMMX
3290 || x
->types
[j
].bitfield
.class == RegSIMD
3291 || x
->types
[j
].bitfield
.class == RegMask
3292 || x
->types
[j
].bitfield
.class == SReg
3293 || x
->types
[j
].bitfield
.class == RegCR
3294 || x
->types
[j
].bitfield
.class == RegDR
3295 || x
->types
[j
].bitfield
.class == RegTR
3296 || x
->types
[j
].bitfield
.class == RegBND
)
3297 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3298 if (operand_type_check (x
->types
[j
], imm
))
3300 if (operand_type_check (x
->types
[j
], disp
))
3301 pe (x
->op
[j
].disps
);
3306 pte (insn_template
*t
)
3308 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3309 static const char *const opc_spc
[] = {
3310 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3311 "XOP08", "XOP09", "XOP0A",
3315 fprintf (stdout
, " %d operands ", t
->operands
);
3316 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3317 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3318 if (opc_spc
[t
->opcode_space
])
3319 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3320 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3321 if (t
->extension_opcode
!= None
)
3322 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3323 if (t
->opcode_modifier
.d
)
3324 fprintf (stdout
, "D");
3325 if (t
->opcode_modifier
.w
)
3326 fprintf (stdout
, "W");
3327 fprintf (stdout
, "\n");
3328 for (j
= 0; j
< t
->operands
; j
++)
3330 fprintf (stdout
, " #%d type ", j
+ 1);
3331 pt (t
->operand_types
[j
]);
3332 fprintf (stdout
, "\n");
3339 fprintf (stdout
, " operation %d\n", e
->X_op
);
3340 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3341 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3342 if (e
->X_add_symbol
)
3344 fprintf (stdout
, " add_symbol ");
3345 ps (e
->X_add_symbol
);
3346 fprintf (stdout
, "\n");
3350 fprintf (stdout
, " op_symbol ");
3351 ps (e
->X_op_symbol
);
3352 fprintf (stdout
, "\n");
3359 fprintf (stdout
, "%s type %s%s",
3361 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3362 segment_name (S_GET_SEGMENT (s
)));
3365 static struct type_name
3367 i386_operand_type mask
;
3370 const type_names
[] =
3372 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3373 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3374 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3375 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3376 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3377 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3378 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3379 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3380 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3381 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3382 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3383 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3384 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3385 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3386 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3387 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3388 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3389 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3390 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3391 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3392 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3393 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3394 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3395 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3396 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3397 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3398 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3399 { { .bitfield
= { .class = SReg
} }, "SReg" },
3400 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3401 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3402 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3403 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3404 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3405 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3409 pt (i386_operand_type t
)
3412 i386_operand_type a
;
3414 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3416 a
= operand_type_and (t
, type_names
[j
].mask
);
3417 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3418 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3423 #endif /* DEBUG386 */
3425 static bfd_reloc_code_real_type
3426 reloc (unsigned int size
,
3429 bfd_reloc_code_real_type other
)
3431 if (other
!= NO_RELOC
)
3433 reloc_howto_type
*rel
;
3438 case BFD_RELOC_X86_64_GOT32
:
3439 return BFD_RELOC_X86_64_GOT64
;
3441 case BFD_RELOC_X86_64_GOTPLT64
:
3442 return BFD_RELOC_X86_64_GOTPLT64
;
3444 case BFD_RELOC_X86_64_PLTOFF64
:
3445 return BFD_RELOC_X86_64_PLTOFF64
;
3447 case BFD_RELOC_X86_64_GOTPC32
:
3448 other
= BFD_RELOC_X86_64_GOTPC64
;
3450 case BFD_RELOC_X86_64_GOTPCREL
:
3451 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3453 case BFD_RELOC_X86_64_TPOFF32
:
3454 other
= BFD_RELOC_X86_64_TPOFF64
;
3456 case BFD_RELOC_X86_64_DTPOFF32
:
3457 other
= BFD_RELOC_X86_64_DTPOFF64
;
3463 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3464 if (other
== BFD_RELOC_SIZE32
)
3467 other
= BFD_RELOC_SIZE64
;
3470 as_bad (_("there are no pc-relative size relocations"));
3476 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3477 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3480 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3482 as_bad (_("unknown relocation (%u)"), other
);
3483 else if (size
!= bfd_get_reloc_size (rel
))
3484 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3485 bfd_get_reloc_size (rel
),
3487 else if (pcrel
&& !rel
->pc_relative
)
3488 as_bad (_("non-pc-relative relocation for pc-relative field"));
3489 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3491 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3493 as_bad (_("relocated field and relocation type differ in signedness"));
3502 as_bad (_("there are no unsigned pc-relative relocations"));
3505 case 1: return BFD_RELOC_8_PCREL
;
3506 case 2: return BFD_RELOC_16_PCREL
;
3507 case 4: return BFD_RELOC_32_PCREL
;
3508 case 8: return BFD_RELOC_64_PCREL
;
3510 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3517 case 4: return BFD_RELOC_X86_64_32S
;
3522 case 1: return BFD_RELOC_8
;
3523 case 2: return BFD_RELOC_16
;
3524 case 4: return BFD_RELOC_32
;
3525 case 8: return BFD_RELOC_64
;
3527 as_bad (_("cannot do %s %u byte relocation"),
3528 sign
> 0 ? "signed" : "unsigned", size
);
3534 /* Here we decide which fixups can be adjusted to make them relative to
3535 the beginning of the section instead of the symbol. Basically we need
3536 to make sure that the dynamic relocations are done correctly, so in
3537 some cases we force the original symbol to be used. */
3540 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3546 /* Don't adjust pc-relative references to merge sections in 64-bit
3548 if (use_rela_relocations
3549 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3553 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3554 and changed later by validate_fix. */
3555 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3556 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3559 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3560 for size relocations. */
3561 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3562 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3563 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3564 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3565 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3566 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3576 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3590 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3591 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3598 want_disp32 (const insn_template
*t
)
3600 return flag_code
!= CODE_64BIT
3601 || i
.prefix
[ADDR_PREFIX
]
3602 || (t
->mnem_off
== MN_lea
3603 && (!i
.types
[1].bitfield
.qword
3604 || t
->opcode_modifier
.size
== SIZE32
));
3608 intel_float_operand (const char *mnemonic
)
3610 /* Note that the value returned is meaningful only for opcodes with (memory)
3611 operands, hence the code here is free to improperly handle opcodes that
3612 have no operands (for better performance and smaller code). */
3614 if (mnemonic
[0] != 'f')
3615 return 0; /* non-math */
3617 switch (mnemonic
[1])
3619 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3620 the fs segment override prefix not currently handled because no
3621 call path can make opcodes without operands get here */
3623 return 2 /* integer op */;
3625 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3626 return 3; /* fldcw/fldenv */
3629 if (mnemonic
[2] != 'o' /* fnop */)
3630 return 3; /* non-waiting control op */
3633 if (mnemonic
[2] == 's')
3634 return 3; /* frstor/frstpm */
3637 if (mnemonic
[2] == 'a')
3638 return 3; /* fsave */
3639 if (mnemonic
[2] == 't')
3641 switch (mnemonic
[3])
3643 case 'c': /* fstcw */
3644 case 'd': /* fstdw */
3645 case 'e': /* fstenv */
3646 case 's': /* fsts[gw] */
3652 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3653 return 0; /* fxsave/fxrstor are not really math ops */
3661 install_template (const insn_template
*t
)
3667 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3668 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3670 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3671 && is_cpu (t
, CpuAVX512F
))
3673 if (need_evex_encoding ())
3675 i
.tm
.opcode_modifier
.vex
= 0;
3676 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3677 if (is_cpu (&i
.tm
, CpuAVX2
))
3678 i
.tm
.cpu
.bitfield
.isa
= 0;
3682 i
.tm
.opcode_modifier
.evex
= 0;
3683 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3688 /* Note that for pseudo prefixes this produces a length of 1. But for them
3689 the length isn't interesting at all. */
3690 for (l
= 1; l
< 4; ++l
)
3691 if (!(t
->base_opcode
>> (8 * l
)))
3694 i
.opcode_length
= l
;
3697 /* Build the VEX prefix. */
3700 build_vex_prefix (const insn_template
*t
)
3702 unsigned int register_specifier
;
3703 unsigned int vector_length
;
3706 /* Check register specifier. */
3707 if (i
.vex
.register_specifier
)
3709 register_specifier
=
3710 ~register_number (i
.vex
.register_specifier
) & 0xf;
3711 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3714 register_specifier
= 0xf;
3716 /* Use 2-byte VEX prefix by swapping destination and source operand
3717 if there are more than 1 register operand. */
3718 if (i
.reg_operands
> 1
3719 && i
.vec_encoding
!= vex_encoding_vex3
3720 && i
.dir_encoding
== dir_encoding_default
3721 && i
.operands
== i
.reg_operands
3722 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3723 && i
.tm
.opcode_space
== SPACE_0F
3724 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3729 swap_2_operands (0, i
.operands
- 1);
3731 gas_assert (i
.rm
.mode
== 3);
3735 i
.rm
.regmem
= i
.rm
.reg
;
3738 if (i
.tm
.opcode_modifier
.d
)
3739 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3740 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3741 else /* Use the next insn. */
3742 install_template (&t
[1]);
3745 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3746 are no memory operands and at least 3 register ones. */
3747 if (i
.reg_operands
>= 3
3748 && i
.vec_encoding
!= vex_encoding_vex3
3749 && i
.reg_operands
== i
.operands
- i
.imm_operands
3750 && i
.tm
.opcode_modifier
.vex
3751 && i
.tm
.opcode_modifier
.commutative
3752 && (i
.tm
.opcode_modifier
.sse2avx
3753 || (optimize
> 1 && !i
.no_optimize
))
3755 && i
.vex
.register_specifier
3756 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3758 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3760 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3761 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3762 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3763 &i
.types
[i
.operands
- 3]));
3764 gas_assert (i
.rm
.mode
== 3);
3766 swap_2_operands (xchg
, xchg
+ 1);
3769 xchg
= i
.rm
.regmem
| 8;
3770 i
.rm
.regmem
= ~register_specifier
& 0xf;
3771 gas_assert (!(i
.rm
.regmem
& 8));
3772 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3773 register_specifier
= ~xchg
& 0xf;
3776 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3777 vector_length
= avxscalar
;
3778 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3780 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3786 /* Determine vector length from the last multi-length vector
3789 for (op
= t
->operands
; op
--;)
3790 if (t
->operand_types
[op
].bitfield
.xmmword
3791 && t
->operand_types
[op
].bitfield
.ymmword
3792 && i
.types
[op
].bitfield
.ymmword
)
3799 /* Check the REX.W bit and VEXW. */
3800 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3801 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3802 else if (i
.tm
.opcode_modifier
.vexw
)
3803 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3805 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3807 /* Use 2-byte VEX prefix if possible. */
3809 && i
.vec_encoding
!= vex_encoding_vex3
3810 && i
.tm
.opcode_space
== SPACE_0F
3811 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3813 /* 2-byte VEX prefix. */
3817 i
.vex
.bytes
[0] = 0xc5;
3819 /* Check the REX.R bit. */
3820 r
= (i
.rex
& REX_R
) ? 0 : 1;
3821 i
.vex
.bytes
[1] = (r
<< 7
3822 | register_specifier
<< 3
3823 | vector_length
<< 2
3824 | i
.tm
.opcode_modifier
.opcodeprefix
);
3828 /* 3-byte VEX prefix. */
3831 switch (i
.tm
.opcode_space
)
3836 i
.vex
.bytes
[0] = 0xc4;
3841 i
.vex
.bytes
[0] = 0x8f;
3847 /* The high 3 bits of the second VEX byte are 1's compliment
3848 of RXB bits from REX. */
3849 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3850 | (!dot_insn () ? i
.tm
.opcode_space
3851 : i
.insn_opcode_space
);
3853 i
.vex
.bytes
[2] = (w
<< 7
3854 | register_specifier
<< 3
3855 | vector_length
<< 2
3856 | i
.tm
.opcode_modifier
.opcodeprefix
);
3861 is_evex_encoding (const insn_template
*t
)
3863 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3864 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3865 || t
->opcode_modifier
.sae
;
3869 is_any_vex_encoding (const insn_template
*t
)
3871 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3875 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3877 unsigned int op
, bytes
;
3878 const i386_operand_type
*types
;
3880 if (i
.broadcast
.type
)
3881 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3883 gas_assert (intel_syntax
);
3885 for (op
= 0; op
< t
->operands
; ++op
)
3886 if (t
->operand_types
[op
].bitfield
.baseindex
)
3889 gas_assert (op
< t
->operands
);
3891 if (t
->opcode_modifier
.evex
3892 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3893 switch (i
.broadcast
.bytes
)
3896 if (t
->operand_types
[op
].bitfield
.word
)
3900 if (t
->operand_types
[op
].bitfield
.dword
)
3904 if (t
->operand_types
[op
].bitfield
.qword
)
3908 if (t
->operand_types
[op
].bitfield
.xmmword
)
3910 if (t
->operand_types
[op
].bitfield
.ymmword
)
3912 if (t
->operand_types
[op
].bitfield
.zmmword
)
3919 gas_assert (op
+ 1 < t
->operands
);
3921 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3922 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3923 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3925 types
= &i
.types
[op
+ 1];
3928 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3929 types
= &t
->operand_types
[op
];
3931 if (types
->bitfield
.zmmword
)
3933 else if (types
->bitfield
.ymmword
)
3939 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3940 insn_name (t
), bytes
* 8);
3945 /* Build the EVEX prefix. */
3948 build_evex_prefix (void)
3950 unsigned int register_specifier
, w
;
3951 rex_byte vrex_used
= 0;
3953 /* Check register specifier. */
3954 if (i
.vex
.register_specifier
)
3956 gas_assert ((i
.vrex
& REX_X
) == 0);
3958 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3959 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3960 register_specifier
+= 8;
3961 /* The upper 16 registers are encoded in the fourth byte of the
3963 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3964 i
.vex
.bytes
[3] = 0x8;
3965 register_specifier
= ~register_specifier
& 0xf;
3969 register_specifier
= 0xf;
3971 /* Encode upper 16 vector index register in the fourth byte of
3973 if (!(i
.vrex
& REX_X
))
3974 i
.vex
.bytes
[3] = 0x8;
3979 /* 4 byte EVEX prefix. */
3981 i
.vex
.bytes
[0] = 0x62;
3983 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3985 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3986 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3987 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3988 | (!dot_insn () ? i
.tm
.opcode_space
3989 : i
.insn_opcode_space
);
3991 /* The fifth bit of the second EVEX byte is 1's compliment of the
3992 REX_R bit in VREX. */
3993 if (!(i
.vrex
& REX_R
))
3994 i
.vex
.bytes
[1] |= 0x10;
3998 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4000 /* When all operands are registers, the REX_X bit in REX is not
4001 used. We reuse it to encode the upper 16 registers, which is
4002 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4003 as 1's compliment. */
4004 if ((i
.vrex
& REX_B
))
4007 i
.vex
.bytes
[1] &= ~0x40;
4011 /* EVEX instructions shouldn't need the REX prefix. */
4012 i
.vrex
&= ~vrex_used
;
4013 gas_assert (i
.vrex
== 0);
4015 /* Check the REX.W bit and VEXW. */
4016 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4017 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4018 else if (i
.tm
.opcode_modifier
.vexw
)
4019 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4021 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4023 /* The third byte of the EVEX prefix. */
4024 i
.vex
.bytes
[2] = ((w
<< 7)
4025 | (register_specifier
<< 3)
4026 | 4 /* Encode the U bit. */
4027 | i
.tm
.opcode_modifier
.opcodeprefix
);
4029 /* The fourth byte of the EVEX prefix. */
4030 /* The zeroing-masking bit. */
4031 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4032 i
.vex
.bytes
[3] |= 0x80;
4034 /* Don't always set the broadcast bit if there is no RC. */
4035 if (i
.rounding
.type
== rc_none
)
4037 /* Encode the vector length. */
4038 unsigned int vec_length
;
4040 if (!i
.tm
.opcode_modifier
.evex
4041 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4045 /* Determine vector length from the last multi-length vector
4047 for (op
= i
.operands
; op
--;)
4048 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4049 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4050 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4052 if (i
.types
[op
].bitfield
.zmmword
)
4054 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4057 else if (i
.types
[op
].bitfield
.ymmword
)
4059 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4062 else if (i
.types
[op
].bitfield
.xmmword
)
4064 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4067 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4068 && op
== i
.broadcast
.operand
)
4070 switch (get_broadcast_bytes (&i
.tm
, true))
4073 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4076 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4079 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4088 if (op
>= MAX_OPERANDS
)
4092 switch (i
.tm
.opcode_modifier
.evex
)
4094 case EVEXLIG
: /* LL' is ignored */
4095 vec_length
= evexlig
<< 5;
4098 vec_length
= 0 << 5;
4101 vec_length
= 1 << 5;
4104 vec_length
= 2 << 5;
4109 vec_length
= 3 << 5;
4117 i
.vex
.bytes
[3] |= vec_length
;
4118 /* Encode the broadcast bit. */
4119 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4120 i
.vex
.bytes
[3] |= 0x10;
4122 else if (i
.rounding
.type
!= saeonly
)
4123 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4125 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4128 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4132 process_immext (void)
4136 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4137 which is coded in the same place as an 8-bit immediate field
4138 would be. Here we fake an 8-bit immediate operand from the
4139 opcode suffix stored in tm.extension_opcode.
4141 AVX instructions also use this encoding, for some of
4142 3 argument instructions. */
4144 gas_assert (i
.imm_operands
<= 1
4146 || (is_any_vex_encoding (&i
.tm
)
4147 && i
.operands
<= 4)));
4149 exp
= &im_expressions
[i
.imm_operands
++];
4150 i
.op
[i
.operands
].imms
= exp
;
4151 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4153 exp
->X_op
= O_constant
;
4154 exp
->X_add_number
= i
.tm
.extension_opcode
;
4155 i
.tm
.extension_opcode
= None
;
4162 switch (i
.tm
.opcode_modifier
.prefixok
)
4170 as_bad (_("invalid instruction `%s' after `%s'"),
4171 insn_name (&i
.tm
), i
.hle_prefix
);
4174 if (i
.prefix
[LOCK_PREFIX
])
4176 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4180 case PrefixHLERelease
:
4181 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4183 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4187 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4189 as_bad (_("memory destination needed for instruction `%s'"
4190 " after `xrelease'"), insn_name (&i
.tm
));
4197 /* Encode aligned vector move as unaligned vector move. */
4200 encode_with_unaligned_vector_move (void)
4202 switch (i
.tm
.base_opcode
)
4204 case 0x28: /* Load instructions. */
4205 case 0x29: /* Store instructions. */
4206 /* movaps/movapd/vmovaps/vmovapd. */
4207 if (i
.tm
.opcode_space
== SPACE_0F
4208 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4209 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4211 case 0x6f: /* Load instructions. */
4212 case 0x7f: /* Store instructions. */
4213 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4214 if (i
.tm
.opcode_space
== SPACE_0F
4215 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4216 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4223 /* Try the shortest encoding by shortening operand size. */
4226 optimize_encoding (void)
4230 if (i
.tm
.mnem_off
== MN_lea
)
4233 lea symbol, %rN -> mov $symbol, %rN
4234 lea (%rM), %rN -> mov %rM, %rN
4235 lea (,%rM,1), %rN -> mov %rM, %rN
4237 and in 32-bit mode for 16-bit addressing
4239 lea (%rM), %rN -> movzx %rM, %rN
4241 and in 64-bit mode zap 32-bit addressing in favor of using a
4242 32-bit (or less) destination.
4244 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4246 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4247 i
.tm
.opcode_modifier
.size
= SIZE32
;
4248 i
.prefix
[ADDR_PREFIX
] = 0;
4251 if (!i
.index_reg
&& !i
.base_reg
)
4254 lea symbol, %rN -> mov $symbol, %rN
4256 if (flag_code
== CODE_64BIT
)
4258 /* Don't transform a relocation to a 16-bit one. */
4260 && i
.op
[0].disps
->X_op
!= O_constant
4261 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4264 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4265 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4267 i
.tm
.base_opcode
= 0xb8;
4268 i
.tm
.opcode_modifier
.modrm
= 0;
4269 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4270 i
.types
[0].bitfield
.imm32
= 1;
4273 i
.tm
.opcode_modifier
.size
= SIZE16
;
4274 i
.types
[0].bitfield
.imm16
= 1;
4279 /* Subject to further optimization below. */
4280 i
.tm
.base_opcode
= 0xc7;
4281 i
.tm
.extension_opcode
= 0;
4282 i
.types
[0].bitfield
.imm32s
= 1;
4283 i
.types
[0].bitfield
.baseindex
= 0;
4286 /* Outside of 64-bit mode address and operand sizes have to match if
4287 a relocation is involved, as otherwise we wouldn't (currently) or
4288 even couldn't express the relocation correctly. */
4289 else if (i
.op
[0].disps
4290 && i
.op
[0].disps
->X_op
!= O_constant
4291 && ((!i
.prefix
[ADDR_PREFIX
])
4292 != (flag_code
== CODE_32BIT
4293 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4294 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4296 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4297 destination is going to grow encoding size. */
4298 else if (flag_code
== CODE_16BIT
4299 && (optimize
<= 1 || optimize_for_space
)
4300 && !i
.prefix
[ADDR_PREFIX
]
4301 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4305 i
.tm
.base_opcode
= 0xb8;
4306 i
.tm
.opcode_modifier
.modrm
= 0;
4307 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4308 i
.types
[0].bitfield
.imm32
= 1;
4310 i
.types
[0].bitfield
.imm16
= 1;
4313 && i
.op
[0].disps
->X_op
== O_constant
4314 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4315 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4317 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4318 i
.op
[0].disps
->X_add_number
&= 0xffff;
4321 i
.tm
.operand_types
[0] = i
.types
[0];
4325 i
.op
[0].imms
= &im_expressions
[0];
4326 i
.op
[0].imms
->X_op
= O_absent
;
4329 else if (i
.op
[0].disps
4330 && (i
.op
[0].disps
->X_op
!= O_constant
4331 || i
.op
[0].disps
->X_add_number
))
4336 lea (%rM), %rN -> mov %rM, %rN
4337 lea (,%rM,1), %rN -> mov %rM, %rN
4338 lea (%rM), %rN -> movzx %rM, %rN
4340 const reg_entry
*addr_reg
;
4342 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4343 addr_reg
= i
.base_reg
;
4344 else if (!i
.base_reg
4345 && i
.index_reg
->reg_num
!= RegIZ
4346 && !i
.log2_scale_factor
)
4347 addr_reg
= i
.index_reg
;
4351 if (addr_reg
->reg_type
.bitfield
.word
4352 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4354 if (flag_code
!= CODE_32BIT
)
4356 i
.tm
.opcode_space
= SPACE_0F
;
4357 i
.tm
.base_opcode
= 0xb7;
4360 i
.tm
.base_opcode
= 0x8b;
4362 if (addr_reg
->reg_type
.bitfield
.dword
4363 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4364 i
.tm
.opcode_modifier
.size
= SIZE32
;
4366 i
.op
[0].regs
= addr_reg
;
4371 i
.disp_operands
= 0;
4372 i
.prefix
[ADDR_PREFIX
] = 0;
4373 i
.prefix
[SEG_PREFIX
] = 0;
4377 if (optimize_for_space
4378 && i
.tm
.mnem_off
== MN_test
4379 && i
.reg_operands
== 1
4380 && i
.imm_operands
== 1
4381 && !i
.types
[1].bitfield
.byte
4382 && i
.op
[0].imms
->X_op
== O_constant
4383 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4386 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4388 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4389 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4391 i
.types
[1].bitfield
.byte
= 1;
4392 /* Ignore the suffix. */
4394 /* Convert to byte registers. */
4395 if (i
.types
[1].bitfield
.word
)
4397 else if (i
.types
[1].bitfield
.dword
)
4401 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4406 else if (flag_code
== CODE_64BIT
4407 && i
.tm
.opcode_space
== SPACE_BASE
4408 && ((i
.types
[1].bitfield
.qword
4409 && i
.reg_operands
== 1
4410 && i
.imm_operands
== 1
4411 && i
.op
[0].imms
->X_op
== O_constant
4412 && ((i
.tm
.base_opcode
== 0xb8
4413 && i
.tm
.extension_opcode
== None
4414 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4415 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4416 && (i
.tm
.base_opcode
== 0x24
4417 || (i
.tm
.base_opcode
== 0x80
4418 && i
.tm
.extension_opcode
== 0x4)
4419 || i
.tm
.mnem_off
== MN_test
4420 || ((i
.tm
.base_opcode
| 1) == 0xc7
4421 && i
.tm
.extension_opcode
== 0x0)))
4422 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4423 && i
.tm
.base_opcode
== 0x83
4424 && i
.tm
.extension_opcode
== 0x4)))
4425 || (i
.types
[0].bitfield
.qword
4426 && ((i
.reg_operands
== 2
4427 && i
.op
[0].regs
== i
.op
[1].regs
4428 && (i
.tm
.mnem_off
== MN_xor
4429 || i
.tm
.mnem_off
== MN_sub
))
4430 || i
.tm
.mnem_off
== MN_clr
))))
4433 andq $imm31, %r64 -> andl $imm31, %r32
4434 andq $imm7, %r64 -> andl $imm7, %r32
4435 testq $imm31, %r64 -> testl $imm31, %r32
4436 xorq %r64, %r64 -> xorl %r32, %r32
4437 subq %r64, %r64 -> subl %r32, %r32
4438 movq $imm31, %r64 -> movl $imm31, %r32
4439 movq $imm32, %r64 -> movl $imm32, %r32
4441 i
.tm
.opcode_modifier
.size
= SIZE32
;
4444 i
.types
[0].bitfield
.imm32
= 1;
4445 i
.types
[0].bitfield
.imm32s
= 0;
4446 i
.types
[0].bitfield
.imm64
= 0;
4450 i
.types
[0].bitfield
.dword
= 1;
4451 i
.types
[0].bitfield
.qword
= 0;
4453 i
.types
[1].bitfield
.dword
= 1;
4454 i
.types
[1].bitfield
.qword
= 0;
4455 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4458 movq $imm31, %r64 -> movl $imm31, %r32
4459 movq $imm32, %r64 -> movl $imm32, %r32
4461 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4462 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4463 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4464 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4467 movq $imm31, %r64 -> movl $imm31, %r32
4469 i
.tm
.base_opcode
= 0xb8;
4470 i
.tm
.extension_opcode
= None
;
4471 i
.tm
.opcode_modifier
.w
= 0;
4472 i
.tm
.opcode_modifier
.modrm
= 0;
4476 else if (optimize
> 1
4477 && !optimize_for_space
4478 && i
.reg_operands
== 2
4479 && i
.op
[0].regs
== i
.op
[1].regs
4480 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4481 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4484 andb %rN, %rN -> testb %rN, %rN
4485 andw %rN, %rN -> testw %rN, %rN
4486 andq %rN, %rN -> testq %rN, %rN
4487 orb %rN, %rN -> testb %rN, %rN
4488 orw %rN, %rN -> testw %rN, %rN
4489 orq %rN, %rN -> testq %rN, %rN
4491 and outside of 64-bit mode
4493 andl %rN, %rN -> testl %rN, %rN
4494 orl %rN, %rN -> testl %rN, %rN
4496 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4498 else if (i
.tm
.base_opcode
== 0xba
4499 && i
.tm
.opcode_space
== SPACE_0F
4500 && i
.reg_operands
== 1
4501 && i
.op
[0].imms
->X_op
== O_constant
4502 && i
.op
[0].imms
->X_add_number
>= 0)
4505 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4506 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4507 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4509 With <BT> one of bts, btr, and bts also:
4510 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4511 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4516 if (i
.tm
.extension_opcode
!= 4)
4518 if (i
.types
[1].bitfield
.qword
4519 && i
.op
[0].imms
->X_add_number
< 32
4520 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4521 i
.tm
.opcode_modifier
.size
= SIZE32
;
4524 if (i
.types
[1].bitfield
.word
4525 && i
.op
[0].imms
->X_add_number
< 16)
4526 i
.tm
.opcode_modifier
.size
= SIZE32
;
4529 if (i
.op
[0].imms
->X_add_number
< 16)
4530 i
.tm
.opcode_modifier
.size
= SIZE16
;
4534 else if (i
.reg_operands
== 3
4535 && i
.op
[0].regs
== i
.op
[1].regs
4536 && !i
.types
[2].bitfield
.xmmword
4537 && (i
.tm
.opcode_modifier
.vex
4538 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4539 && is_evex_encoding (&i
.tm
)
4540 && (i
.vec_encoding
!= vex_encoding_evex
4541 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4542 || is_cpu (&i
.tm
, CpuAVX512VL
)
4543 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4544 && i
.types
[2].bitfield
.ymmword
))))
4545 && i
.tm
.opcode_space
== SPACE_0F
4546 && ((i
.tm
.base_opcode
| 2) == 0x57
4547 || i
.tm
.base_opcode
== 0xdf
4548 || i
.tm
.base_opcode
== 0xef
4549 || (i
.tm
.base_opcode
| 3) == 0xfb
4550 || i
.tm
.base_opcode
== 0x42
4551 || i
.tm
.base_opcode
== 0x47))
4554 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4556 EVEX VOP %zmmM, %zmmM, %zmmN
4557 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4558 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4559 EVEX VOP %ymmM, %ymmM, %ymmN
4560 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4561 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4562 VEX VOP %ymmM, %ymmM, %ymmN
4563 -> VEX VOP %xmmM, %xmmM, %xmmN
4564 VOP, one of vpandn and vpxor:
4565 VEX VOP %ymmM, %ymmM, %ymmN
4566 -> VEX VOP %xmmM, %xmmM, %xmmN
4567 VOP, one of vpandnd and vpandnq:
4568 EVEX VOP %zmmM, %zmmM, %zmmN
4569 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4570 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4571 EVEX VOP %ymmM, %ymmM, %ymmN
4572 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4573 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4574 VOP, one of vpxord and vpxorq:
4575 EVEX VOP %zmmM, %zmmM, %zmmN
4576 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4577 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4578 EVEX VOP %ymmM, %ymmM, %ymmN
4579 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4580 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4581 VOP, one of kxord and kxorq:
4582 VEX VOP %kM, %kM, %kN
4583 -> VEX kxorw %kM, %kM, %kN
4584 VOP, one of kandnd and kandnq:
4585 VEX VOP %kM, %kM, %kN
4586 -> VEX kandnw %kM, %kM, %kN
4588 if (is_evex_encoding (&i
.tm
))
4590 if (i
.vec_encoding
!= vex_encoding_evex
)
4592 i
.tm
.opcode_modifier
.vex
= VEX128
;
4593 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4594 i
.tm
.opcode_modifier
.evex
= 0;
4595 i
.vec_encoding
= vex_encoding_vex
;
4598 else if (optimize
> 1)
4599 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4603 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4605 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4606 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4609 i
.tm
.opcode_modifier
.vex
= VEX128
;
4611 if (i
.tm
.opcode_modifier
.vex
)
4612 for (j
= 0; j
< 3; j
++)
4614 i
.types
[j
].bitfield
.xmmword
= 1;
4615 i
.types
[j
].bitfield
.ymmword
= 0;
4618 else if (i
.vec_encoding
!= vex_encoding_evex
4619 && !i
.types
[0].bitfield
.zmmword
4620 && !i
.types
[1].bitfield
.zmmword
4622 && !i
.broadcast
.type
4623 && !i
.broadcast
.bytes
4624 && is_evex_encoding (&i
.tm
)
4625 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4626 || (i
.tm
.base_opcode
& ~4) == 0xdb
4627 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4628 && i
.tm
.extension_opcode
== None
)
4631 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4632 vmovdqu32 and vmovdqu64:
4633 EVEX VOP %xmmM, %xmmN
4634 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4635 EVEX VOP %ymmM, %ymmN
4636 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4638 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4640 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4642 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4644 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4645 VOP, one of vpand, vpandn, vpor, vpxor:
4646 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4647 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4648 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4649 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4650 EVEX VOP{d,q} mem, %xmmM, %xmmN
4651 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4652 EVEX VOP{d,q} mem, %ymmM, %ymmN
4653 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4655 for (j
= 0; j
< i
.operands
; j
++)
4656 if (operand_type_check (i
.types
[j
], disp
)
4657 && i
.op
[j
].disps
->X_op
== O_constant
)
4659 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4660 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4661 bytes, we choose EVEX Disp8 over VEX Disp32. */
4662 int evex_disp8
, vex_disp8
;
4663 unsigned int memshift
= i
.memshift
;
4664 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4666 evex_disp8
= fits_in_disp8 (n
);
4668 vex_disp8
= fits_in_disp8 (n
);
4669 if (evex_disp8
!= vex_disp8
)
4671 i
.memshift
= memshift
;
4675 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4678 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4679 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4680 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4681 i
.tm
.opcode_modifier
.vex
4682 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4683 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4684 /* VPAND, VPOR, and VPXOR are commutative. */
4685 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4686 i
.tm
.opcode_modifier
.commutative
= 1;
4687 i
.tm
.opcode_modifier
.evex
= 0;
4688 i
.tm
.opcode_modifier
.masking
= 0;
4689 i
.tm
.opcode_modifier
.broadcast
= 0;
4690 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4693 i
.types
[j
].bitfield
.disp8
4694 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4696 else if (optimize_for_space
4697 && i
.tm
.base_opcode
== 0x29
4698 && i
.tm
.opcode_space
== SPACE_0F38
4699 && i
.operands
== i
.reg_operands
4700 && i
.op
[0].regs
== i
.op
[1].regs
4701 && (!i
.tm
.opcode_modifier
.vex
4702 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4703 && !is_evex_encoding (&i
.tm
))
4706 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4707 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4708 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4710 i
.tm
.opcode_space
= SPACE_0F
;
4711 i
.tm
.base_opcode
= 0x76;
4713 else if (((i
.tm
.base_opcode
>= 0x64
4714 && i
.tm
.base_opcode
<= 0x66
4715 && i
.tm
.opcode_space
== SPACE_0F
)
4716 || (i
.tm
.base_opcode
== 0x37
4717 && i
.tm
.opcode_space
== SPACE_0F38
))
4718 && i
.operands
== i
.reg_operands
4719 && i
.op
[0].regs
== i
.op
[1].regs
4720 && !is_evex_encoding (&i
.tm
))
4723 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4724 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4725 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4726 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4727 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4728 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4730 i
.tm
.opcode_space
= SPACE_0F
;
4731 i
.tm
.base_opcode
= 0xef;
4732 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4734 if (i
.operands
== 2)
4736 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4742 i
.op
[2].regs
= i
.op
[0].regs
;
4743 i
.types
[2] = i
.types
[0];
4744 i
.flags
[2] = i
.flags
[0];
4745 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4747 i
.tm
.opcode_modifier
.sse2avx
= 0;
4749 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4750 i
.op
[1].regs
= i
.op
[0].regs
;
4753 else if (optimize_for_space
4754 && i
.tm
.base_opcode
== 0x59
4755 && i
.tm
.opcode_space
== SPACE_0F38
4756 && i
.operands
== i
.reg_operands
4757 && i
.tm
.opcode_modifier
.vex
4758 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4759 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4760 && i
.vec_encoding
!= vex_encoding_vex3
)
4763 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4765 i
.tm
.opcode_space
= SPACE_0F
;
4766 i
.tm
.base_opcode
= 0x6c;
4767 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4773 i
.op
[2].regs
= i
.op
[0].regs
;
4774 i
.types
[2] = i
.types
[0];
4775 i
.flags
[2] = i
.flags
[0];
4776 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4778 swap_2_operands (1, 2);
4782 /* Return non-zero for load instruction. */
4788 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4789 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4793 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4794 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4795 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4799 if (i
.tm
.mnem_off
== MN_pop
)
4803 if (i
.tm
.opcode_space
== SPACE_BASE
)
4806 if (i
.tm
.base_opcode
== 0x9d
4807 || i
.tm
.base_opcode
== 0x61)
4810 /* movs, cmps, lods, scas. */
4811 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4815 if (base_opcode
== 0x6f
4816 || i
.tm
.base_opcode
== 0xd7)
4818 /* NB: For AMD-specific insns with implicit memory operands,
4819 they're intentionally not covered. */
4822 /* No memory operand. */
4823 if (!i
.mem_operands
)
4828 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4831 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4833 /* test, not, neg, mul, imul, div, idiv. */
4834 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4838 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4841 /* add, or, adc, sbb, and, sub, xor, cmp. */
4842 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4845 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4846 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4847 && i
.tm
.extension_opcode
!= 6)
4850 /* Check for x87 instructions. */
4851 if ((base_opcode
| 6) == 0xdf)
4853 /* Skip fst, fstp, fstenv, fstcw. */
4854 if (i
.tm
.base_opcode
== 0xd9
4855 && (i
.tm
.extension_opcode
== 2
4856 || i
.tm
.extension_opcode
== 3
4857 || i
.tm
.extension_opcode
== 6
4858 || i
.tm
.extension_opcode
== 7))
4861 /* Skip fisttp, fist, fistp, fstp. */
4862 if (i
.tm
.base_opcode
== 0xdb
4863 && (i
.tm
.extension_opcode
== 1
4864 || i
.tm
.extension_opcode
== 2
4865 || i
.tm
.extension_opcode
== 3
4866 || i
.tm
.extension_opcode
== 7))
4869 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4870 if (i
.tm
.base_opcode
== 0xdd
4871 && (i
.tm
.extension_opcode
== 1
4872 || i
.tm
.extension_opcode
== 2
4873 || i
.tm
.extension_opcode
== 3
4874 || i
.tm
.extension_opcode
== 6
4875 || i
.tm
.extension_opcode
== 7))
4878 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4879 if (i
.tm
.base_opcode
== 0xdf
4880 && (i
.tm
.extension_opcode
== 1
4881 || i
.tm
.extension_opcode
== 2
4882 || i
.tm
.extension_opcode
== 3
4883 || i
.tm
.extension_opcode
== 6
4884 || i
.tm
.extension_opcode
== 7))
4890 else if (i
.tm
.opcode_space
== SPACE_0F
)
4892 /* bt, bts, btr, btc. */
4893 if (i
.tm
.base_opcode
== 0xba
4894 && (i
.tm
.extension_opcode
| 3) == 7)
4897 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4898 if (i
.tm
.base_opcode
== 0xc7
4899 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4900 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4901 || i
.tm
.extension_opcode
== 6))
4904 /* fxrstor, ldmxcsr, xrstor. */
4905 if (i
.tm
.base_opcode
== 0xae
4906 && (i
.tm
.extension_opcode
== 1
4907 || i
.tm
.extension_opcode
== 2
4908 || i
.tm
.extension_opcode
== 5))
4911 /* lgdt, lidt, lmsw. */
4912 if (i
.tm
.base_opcode
== 0x01
4913 && (i
.tm
.extension_opcode
== 2
4914 || i
.tm
.extension_opcode
== 3
4915 || i
.tm
.extension_opcode
== 6))
4919 dest
= i
.operands
- 1;
4921 /* Check fake imm8 operand and 3 source operands. */
4922 if ((i
.tm
.opcode_modifier
.immext
4923 || i
.reg_operands
+ i
.mem_operands
== 4)
4924 && i
.types
[dest
].bitfield
.imm8
)
4927 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4928 if (i
.tm
.opcode_space
== SPACE_BASE
4929 && ((base_opcode
| 0x38) == 0x39
4930 || (base_opcode
| 2) == 0x87))
4933 if (i
.tm
.mnem_off
== MN_xadd
)
4936 /* Check for load instruction. */
4937 return (i
.types
[dest
].bitfield
.class != ClassNone
4938 || i
.types
[dest
].bitfield
.instance
== Accum
);
4941 /* Output lfence, 0xfaee8, after instruction. */
4944 insert_lfence_after (void)
4946 if (lfence_after_load
&& load_insn_p ())
4948 /* There are also two REP string instructions that require
4949 special treatment. Specifically, the compare string (CMPS)
4950 and scan string (SCAS) instructions set EFLAGS in a manner
4951 that depends on the data being compared/scanned. When used
4952 with a REP prefix, the number of iterations may therefore
4953 vary depending on this data. If the data is a program secret
4954 chosen by the adversary using an LVI method,
4955 then this data-dependent behavior may leak some aspect
4957 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4958 && i
.prefix
[REP_PREFIX
])
4960 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4963 char *p
= frag_more (3);
4970 /* Output lfence, 0xfaee8, before instruction. */
4973 insert_lfence_before (void)
4977 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4980 if (i
.tm
.base_opcode
== 0xff
4981 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4983 /* Insert lfence before indirect branch if needed. */
4985 if (lfence_before_indirect_branch
== lfence_branch_none
)
4988 if (i
.operands
!= 1)
4991 if (i
.reg_operands
== 1)
4993 /* Indirect branch via register. Don't insert lfence with
4994 -mlfence-after-load=yes. */
4995 if (lfence_after_load
4996 || lfence_before_indirect_branch
== lfence_branch_memory
)
4999 else if (i
.mem_operands
== 1
5000 && lfence_before_indirect_branch
!= lfence_branch_register
)
5002 as_warn (_("indirect `%s` with memory operand should be avoided"),
5009 if (last_insn
.kind
!= last_insn_other
5010 && last_insn
.seg
== now_seg
)
5012 as_warn_where (last_insn
.file
, last_insn
.line
,
5013 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5014 last_insn
.name
, insn_name (&i
.tm
));
5025 /* Output or/not/shl and lfence before near ret. */
5026 if (lfence_before_ret
!= lfence_before_ret_none
5027 && (i
.tm
.base_opcode
| 1) == 0xc3)
5029 if (last_insn
.kind
!= last_insn_other
5030 && last_insn
.seg
== now_seg
)
5032 as_warn_where (last_insn
.file
, last_insn
.line
,
5033 _("`%s` skips -mlfence-before-ret on `%s`"),
5034 last_insn
.name
, insn_name (&i
.tm
));
5038 /* Near ret ingore operand size override under CPU64. */
5039 char prefix
= flag_code
== CODE_64BIT
5041 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5043 if (lfence_before_ret
== lfence_before_ret_not
)
5045 /* not: 0xf71424, may add prefix
5046 for operand size override or 64-bit code. */
5047 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5061 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5064 if (lfence_before_ret
== lfence_before_ret_or
)
5066 /* or: 0x830c2400, may add prefix
5067 for operand size override or 64-bit code. */
5073 /* shl: 0xc1242400, may add prefix
5074 for operand size override or 64-bit code. */
5089 /* Shared helper for md_assemble() and s_insn(). */
5090 static void init_globals (void)
5094 memset (&i
, '\0', sizeof (i
));
5095 i
.rounding
.type
= rc_none
;
5096 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5097 i
.reloc
[j
] = NO_RELOC
;
5098 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5099 memset (im_expressions
, '\0', sizeof (im_expressions
));
5100 save_stack_p
= save_stack
;
5103 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5104 parsing pass. Instead of introducing a rarely use new insn attribute this
5105 utilizes a common pattern between affected templates. It is deemed
5106 acceptable that this will lead to unnecessary pass 2 preparations in a
5107 limited set of cases. */
5108 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5110 return t
->opcode_modifier
.sse2avx
5111 /* Note that all SSE2AVX templates have at least one operand. */
5112 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5113 : (t
->opcode_space
== SPACE_0F
5114 && (t
->base_opcode
| 1) == 0xbf)
5115 || (t
->opcode_space
== SPACE_BASE
5116 && t
->base_opcode
== 0x63);
5119 /* This is the guts of the machine-dependent assembler. LINE points to a
5120 machine dependent instruction. This function is supposed to emit
5121 the frags/bytes it assembles to. */
5124 md_assemble (char *line
)
5127 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5128 const char *end
, *pass1_mnem
= NULL
;
5129 enum i386_error pass1_err
= 0;
5130 const insn_template
*t
;
5132 /* Initialize globals. */
5133 current_templates
= NULL
;
5137 /* First parse an instruction mnemonic & call i386_operand for the operands.
5138 We assume that the scrubber has arranged it so that line[0] is the valid
5139 start of a (possibly prefixed) mnemonic. */
5141 end
= parse_insn (line
, mnemonic
, false);
5144 if (pass1_mnem
!= NULL
)
5146 if (i
.error
!= no_error
)
5148 gas_assert (current_templates
!= NULL
);
5149 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5151 /* No point in trying a 2nd pass - it'll only find the same suffix
5153 mnem_suffix
= i
.suffix
;
5158 t
= current_templates
->start
;
5159 if (may_need_pass2 (t
))
5161 /* Make a copy of the full line in case we need to retry. */
5162 copy
= xstrdup (line
);
5165 mnem_suffix
= i
.suffix
;
5167 line
= parse_operands (line
, mnemonic
);
5175 /* Now we've parsed the mnemonic into a set of templates, and have the
5176 operands at hand. */
5178 /* All Intel opcodes have reversed operands except for "bound", "enter",
5179 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5180 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5181 intersegment "jmp" and "call" instructions with 2 immediate operands so
5182 that the immediate segment precedes the offset consistently in Intel and
5186 && (t
->mnem_off
!= MN_bound
)
5187 && !startswith (mnemonic
, "invlpg")
5188 && !startswith (mnemonic
, "monitor")
5189 && !startswith (mnemonic
, "mwait")
5190 && (t
->mnem_off
!= MN_pvalidate
)
5191 && !startswith (mnemonic
, "rmp")
5192 && (t
->mnem_off
!= MN_tpause
)
5193 && (t
->mnem_off
!= MN_umwait
)
5194 && !(i
.operands
== 2
5195 && operand_type_check (i
.types
[0], imm
)
5196 && operand_type_check (i
.types
[1], imm
)))
5199 /* The order of the immediates should be reversed
5200 for 2 immediates extrq and insertq instructions */
5201 if (i
.imm_operands
== 2
5202 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5203 swap_2_operands (0, 1);
5208 if (i
.disp_operands
&& !optimize_disp (t
))
5211 /* Next, we find a template that matches the given insn,
5212 making sure the overlap of the given operands types is consistent
5213 with the template operand types. */
5215 if (!(t
= match_template (mnem_suffix
)))
5217 const char *err_msg
;
5219 if (copy
&& !mnem_suffix
)
5224 pass1_err
= i
.error
;
5225 pass1_mnem
= insn_name (current_templates
->start
);
5229 /* If a non-/only-64bit template (group) was found in pass 1, and if
5230 _some_ template (group) was found in pass 2, squash pass 1's
5232 if (pass1_err
== unsupported_64bit
)
5238 switch (pass1_mnem
? pass1_err
: i
.error
)
5242 case operand_size_mismatch
:
5243 err_msg
= _("operand size mismatch");
5245 case operand_type_mismatch
:
5246 err_msg
= _("operand type mismatch");
5248 case register_type_mismatch
:
5249 err_msg
= _("register type mismatch");
5251 case number_of_operands_mismatch
:
5252 err_msg
= _("number of operands mismatch");
5254 case invalid_instruction_suffix
:
5255 err_msg
= _("invalid instruction suffix");
5258 err_msg
= _("constant doesn't fit in 4 bits");
5260 case unsupported_with_intel_mnemonic
:
5261 err_msg
= _("unsupported with Intel mnemonic");
5263 case unsupported_syntax
:
5264 err_msg
= _("unsupported syntax");
5267 as_bad (_("unsupported instruction `%s'"),
5268 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5270 case unsupported_on_arch
:
5271 as_bad (_("`%s' is not supported on `%s%s'"),
5272 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5273 cpu_arch_name
? cpu_arch_name
: default_arch
,
5274 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5276 case unsupported_64bit
:
5277 if (ISLOWER (mnem_suffix
))
5279 if (flag_code
== CODE_64BIT
)
5280 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5281 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5284 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5285 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5290 if (flag_code
== CODE_64BIT
)
5291 as_bad (_("`%s' is not supported in 64-bit mode"),
5292 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5294 as_bad (_("`%s' is only supported in 64-bit mode"),
5295 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5298 case invalid_sib_address
:
5299 err_msg
= _("invalid SIB address");
5301 case invalid_vsib_address
:
5302 err_msg
= _("invalid VSIB address");
5304 case invalid_vector_register_set
:
5305 err_msg
= _("mask, index, and destination registers must be distinct");
5307 case invalid_tmm_register_set
:
5308 err_msg
= _("all tmm registers must be distinct");
5310 case invalid_dest_and_src_register_set
:
5311 err_msg
= _("destination and source registers must be distinct");
5313 case unsupported_vector_index_register
:
5314 err_msg
= _("unsupported vector index register");
5316 case unsupported_broadcast
:
5317 err_msg
= _("unsupported broadcast");
5319 case broadcast_needed
:
5320 err_msg
= _("broadcast is needed for operand of such type");
5322 case unsupported_masking
:
5323 err_msg
= _("unsupported masking");
5325 case mask_not_on_destination
:
5326 err_msg
= _("mask not on destination operand");
5328 case no_default_mask
:
5329 err_msg
= _("default mask isn't allowed");
5331 case unsupported_rc_sae
:
5332 err_msg
= _("unsupported static rounding/sae");
5334 case invalid_register_operand
:
5335 err_msg
= _("invalid register operand");
5337 case internal_error
:
5338 err_msg
= _("internal error");
5341 as_bad (_("%s for `%s'"), err_msg
,
5342 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5348 if (sse_check
!= check_none
5349 /* The opcode space check isn't strictly needed; it's there only to
5350 bypass the logic below when easily possible. */
5351 && t
->opcode_space
>= SPACE_0F
5352 && t
->opcode_space
<= SPACE_0F3A
5353 && !is_cpu (&i
.tm
, CpuSSE4a
)
5354 && !is_any_vex_encoding (t
))
5358 for (j
= 0; j
< t
->operands
; ++j
)
5360 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5362 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5366 if (j
>= t
->operands
&& simd
)
5367 (sse_check
== check_warning
5369 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5372 if (i
.tm
.opcode_modifier
.fwait
)
5373 if (!add_prefix (FWAIT_OPCODE
))
5376 /* Check if REP prefix is OK. */
5377 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5379 as_bad (_("invalid instruction `%s' after `%s'"),
5380 insn_name (&i
.tm
), i
.rep_prefix
);
5384 /* Check for lock without a lockable instruction. Destination operand
5385 must be memory unless it is xchg (0x86). */
5386 if (i
.prefix
[LOCK_PREFIX
])
5388 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5389 || i
.mem_operands
== 0
5390 || (i
.tm
.base_opcode
!= 0x86
5391 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5393 as_bad (_("expecting lockable instruction after `lock'"));
5397 /* Zap the redundant prefix from XCHG when optimizing. */
5398 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5399 i
.prefix
[LOCK_PREFIX
] = 0;
5402 if (is_any_vex_encoding (&i
.tm
)
5403 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5404 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5406 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5407 if (i
.prefix
[DATA_PREFIX
])
5409 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5413 /* Don't allow e.g. KMOV in TLS code sequences. */
5414 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5417 case BFD_RELOC_386_TLS_GOTIE
:
5418 case BFD_RELOC_386_TLS_LE_32
:
5419 case BFD_RELOC_X86_64_GOTTPOFF
:
5420 case BFD_RELOC_X86_64_TLSLD
:
5421 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5428 /* Check if HLE prefix is OK. */
5429 if (i
.hle_prefix
&& !check_hle ())
5432 /* Check BND prefix. */
5433 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5434 as_bad (_("expecting valid branch instruction after `bnd'"));
5436 /* Check NOTRACK prefix. */
5437 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5438 as_bad (_("expecting indirect branch instruction after `notrack'"));
5440 if (is_cpu (&i
.tm
, CpuMPX
))
5442 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5443 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5444 else if (flag_code
!= CODE_16BIT
5445 ? i
.prefix
[ADDR_PREFIX
]
5446 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5447 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5450 /* Insert BND prefix. */
5451 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5453 if (!i
.prefix
[BND_PREFIX
])
5454 add_prefix (BND_PREFIX_OPCODE
);
5455 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5457 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5458 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5462 /* Check string instruction segment overrides. */
5463 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5465 gas_assert (i
.mem_operands
);
5466 if (!check_string ())
5468 i
.disp_operands
= 0;
5471 /* The memory operand of (%dx) should be only used with input/output
5472 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5473 if (i
.input_output_operand
5474 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5475 || i
.tm
.opcode_space
!= SPACE_BASE
))
5477 as_bad (_("input/output port address isn't allowed with `%s'"),
5482 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5483 optimize_encoding ();
5485 /* Past optimization there's no need to distinguish vex_encoding_evex and
5486 vex_encoding_evex512 anymore. */
5487 if (i
.vec_encoding
== vex_encoding_evex512
)
5488 i
.vec_encoding
= vex_encoding_evex
;
5490 if (use_unaligned_vector_move
)
5491 encode_with_unaligned_vector_move ();
5493 if (!process_suffix ())
5496 /* Check if IP-relative addressing requirements can be satisfied. */
5497 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5498 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5499 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5501 /* Update operand types and check extended states. */
5502 for (j
= 0; j
< i
.operands
; j
++)
5504 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5505 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5510 i
.xstate
|= xstate_mmx
;
5513 i
.xstate
|= xstate_mask
;
5516 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5517 i
.xstate
|= xstate_tmm
;
5518 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5519 && !i
.tm
.opcode_modifier
.vex
5520 && vector_size
>= VSZ512
)
5521 i
.xstate
|= xstate_zmm
;
5522 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5523 && vector_size
>= VSZ256
)
5524 i
.xstate
|= xstate_ymm
;
5525 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5526 i
.xstate
|= xstate_xmm
;
5531 /* Make still unresolved immediate matches conform to size of immediate
5532 given in i.suffix. */
5533 if (!finalize_imm ())
5536 if (i
.types
[0].bitfield
.imm1
)
5537 i
.imm_operands
= 0; /* kludge for shift insns. */
5539 /* For insns with operands there are more diddles to do to the opcode. */
5542 if (!process_operands ())
5545 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5547 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5548 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5551 if (is_any_vex_encoding (&i
.tm
))
5553 if (!cpu_arch_flags
.bitfield
.cpui286
)
5555 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5560 /* Check for explicit REX prefix. */
5561 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5563 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5567 if (i
.tm
.opcode_modifier
.vex
)
5568 build_vex_prefix (t
);
5570 build_evex_prefix ();
5572 /* The individual REX.RXBW bits got consumed. */
5573 i
.rex
&= REX_OPCODE
;
5576 /* Handle conversion of 'int $3' --> special int3 insn. */
5577 if (i
.tm
.mnem_off
== MN_int
5578 && i
.op
[0].imms
->X_add_number
== 3)
5580 i
.tm
.base_opcode
= INT3_OPCODE
;
5584 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5585 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5586 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5587 && i
.op
[0].disps
->X_op
== O_constant
)
5589 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5590 the absolute address given by the constant. Since ix86 jumps and
5591 calls are pc relative, we need to generate a reloc. */
5592 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5593 i
.op
[0].disps
->X_op
= O_symbol
;
5596 /* For 8 bit registers we need an empty rex prefix. Also if the
5597 instruction already has a prefix, we need to convert old
5598 registers to new ones. */
5600 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5601 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5602 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5603 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5604 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5605 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5610 i
.rex
|= REX_OPCODE
;
5611 for (x
= 0; x
< 2; x
++)
5613 /* Look for 8 bit operand that uses old registers. */
5614 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5615 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5617 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5618 /* In case it is "hi" register, give up. */
5619 if (i
.op
[x
].regs
->reg_num
> 3)
5620 as_bad (_("can't encode register '%s%s' in an "
5621 "instruction requiring REX prefix."),
5622 register_prefix
, i
.op
[x
].regs
->reg_name
);
5624 /* Otherwise it is equivalent to the extended register.
5625 Since the encoding doesn't change this is merely
5626 cosmetic cleanup for debug output. */
5628 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5633 if (i
.rex
== 0 && i
.rex_encoding
)
5635 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5636 that uses legacy register. If it is "hi" register, don't add
5637 the REX_OPCODE byte. */
5639 for (x
= 0; x
< 2; x
++)
5640 if (i
.types
[x
].bitfield
.class == Reg
5641 && i
.types
[x
].bitfield
.byte
5642 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5643 && i
.op
[x
].regs
->reg_num
> 3)
5645 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5646 i
.rex_encoding
= false;
5655 add_prefix (REX_OPCODE
| i
.rex
);
5657 insert_lfence_before ();
5659 /* We are ready to output the insn. */
5662 insert_lfence_after ();
5664 last_insn
.seg
= now_seg
;
5666 if (i
.tm
.opcode_modifier
.isprefix
)
5668 last_insn
.kind
= last_insn_prefix
;
5669 last_insn
.name
= insn_name (&i
.tm
);
5670 last_insn
.file
= as_where (&last_insn
.line
);
5673 last_insn
.kind
= last_insn_other
;
5676 /* The Q suffix is generally valid only in 64-bit mode, with very few
5677 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5678 and fisttp only one of their two templates is matched below: That's
5679 sufficient since other relevant attributes are the same between both
5680 respective templates. */
5681 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5683 return flag_code
== CODE_64BIT
5684 || (t
->opcode_space
== SPACE_BASE
5685 && t
->base_opcode
== 0xdf
5686 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5687 || t
->mnem_off
== MN_cmpxchg8b
;
5691 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5693 const char *l
= line
, *token_start
= l
;
5695 bool pass1
= !current_templates
;
5697 const insn_template
*t
;
5703 /* Pseudo-prefixes start with an opening figure brace. */
5704 if ((*mnem_p
= *l
) == '{')
5709 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5714 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5717 as_bad (_("no such instruction: `%s'"), token_start
);
5722 /* Pseudo-prefixes end with a closing figure brace. */
5723 if (*mnemonic
== '{' && *l
== '}')
5726 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5730 /* Point l at the closing brace if there's no other separator. */
5731 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5732 && *l
!= PREFIX_SEPARATOR
)
5735 else if (!is_space_char (*l
)
5736 && *l
!= END_OF_INSN
5738 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5742 as_bad (_("invalid character %s in mnemonic"),
5743 output_invalid (*l
));
5746 if (token_start
== l
)
5748 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5749 as_bad (_("expecting prefix; got nothing"));
5751 as_bad (_("expecting mnemonic; got nothing"));
5755 /* Look up instruction (or prefix) via hash table. */
5756 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5758 if (*l
!= END_OF_INSN
5759 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5760 && current_templates
5761 && current_templates
->start
->opcode_modifier
.isprefix
)
5763 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5765 as_bad ((flag_code
!= CODE_64BIT
5766 ? _("`%s' is only supported in 64-bit mode")
5767 : _("`%s' is not supported in 64-bit mode")),
5768 insn_name (current_templates
->start
));
5771 /* If we are in 16-bit mode, do not allow addr16 or data16.
5772 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5773 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5774 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5775 && flag_code
!= CODE_64BIT
5776 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5777 ^ (flag_code
== CODE_16BIT
)))
5779 as_bad (_("redundant %s prefix"),
5780 insn_name (current_templates
->start
));
5784 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5786 /* Handle pseudo prefixes. */
5787 switch (current_templates
->start
->extension_opcode
)
5791 i
.disp_encoding
= disp_encoding_8bit
;
5795 i
.disp_encoding
= disp_encoding_16bit
;
5799 i
.disp_encoding
= disp_encoding_32bit
;
5803 i
.dir_encoding
= dir_encoding_load
;
5807 i
.dir_encoding
= dir_encoding_store
;
5811 i
.vec_encoding
= vex_encoding_vex
;
5815 i
.vec_encoding
= vex_encoding_vex3
;
5819 i
.vec_encoding
= vex_encoding_evex
;
5823 i
.rex_encoding
= true;
5825 case Prefix_NoOptimize
:
5827 i
.no_optimize
= true;
5835 /* Add prefix, checking for repeated prefixes. */
5836 switch (add_prefix (current_templates
->start
->base_opcode
))
5841 if (is_cpu (current_templates
->start
, CpuIBT
))
5842 i
.notrack_prefix
= insn_name (current_templates
->start
);
5845 if (is_cpu (current_templates
->start
, CpuHLE
))
5846 i
.hle_prefix
= insn_name (current_templates
->start
);
5847 else if (is_cpu (current_templates
->start
, CpuMPX
))
5848 i
.bnd_prefix
= insn_name (current_templates
->start
);
5850 i
.rep_prefix
= insn_name (current_templates
->start
);
5856 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5866 if (!current_templates
)
5868 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5869 Check if we should swap operand or force 32bit displacement in
5871 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5872 i
.dir_encoding
= dir_encoding_swap
;
5873 else if (mnem_p
- 3 == dot_p
5876 i
.disp_encoding
= disp_encoding_8bit
;
5877 else if (mnem_p
- 4 == dot_p
5881 i
.disp_encoding
= disp_encoding_32bit
;
5886 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5889 if (!current_templates
|| !pass1
)
5891 current_templates
= NULL
;
5894 if (mnem_p
> mnemonic
)
5896 /* See if we can get a match by trimming off a suffix. */
5899 case WORD_MNEM_SUFFIX
:
5900 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5901 i
.suffix
= SHORT_MNEM_SUFFIX
;
5904 case BYTE_MNEM_SUFFIX
:
5905 case QWORD_MNEM_SUFFIX
:
5906 i
.suffix
= mnem_p
[-1];
5909 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5911 case SHORT_MNEM_SUFFIX
:
5912 case LONG_MNEM_SUFFIX
:
5915 i
.suffix
= mnem_p
[-1];
5918 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5926 if (intel_float_operand (mnemonic
) == 1)
5927 i
.suffix
= SHORT_MNEM_SUFFIX
;
5929 i
.suffix
= LONG_MNEM_SUFFIX
;
5932 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5934 /* For compatibility reasons accept MOVSD and CMPSD without
5935 operands even in AT&T mode. */
5936 else if (*l
== END_OF_INSN
5937 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5941 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5942 if (current_templates
!= NULL
5944 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5945 && current_templates
->start
->opcode_space
5947 && mnem_p
[-2] == 's')
5949 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5950 mnemonic
, mnemonic
);
5951 i
.suffix
= LONG_MNEM_SUFFIX
;
5955 current_templates
= NULL
;
5963 if (!current_templates
)
5966 as_bad (_("no such instruction: `%s'"), token_start
);
5971 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5972 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5974 /* Check for a branch hint. We allow ",pt" and ",pn" for
5975 predict taken and predict not taken respectively.
5976 I'm not sure that branch hints actually do anything on loop
5977 and jcxz insns (JumpByte) for current Pentium4 chips. They
5978 may work in the future and it doesn't hurt to accept them
5980 if (l
[0] == ',' && l
[1] == 'p')
5984 if (!add_prefix (DS_PREFIX_OPCODE
))
5988 else if (l
[2] == 'n')
5990 if (!add_prefix (CS_PREFIX_OPCODE
))
5996 /* Any other comma loses. */
5999 as_bad (_("invalid character %s in mnemonic"),
6000 output_invalid (*l
));
6004 /* Check if instruction is supported on specified architecture. */
6006 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6008 supported
|= cpu_flags_match (t
);
6010 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6011 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6013 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6019 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6020 i
.error
= unsupported_on_arch
;
6022 i
.error
= unsupported_64bit
;
6029 parse_operands (char *l
, const char *mnemonic
)
6033 /* 1 if operand is pending after ','. */
6034 unsigned int expecting_operand
= 0;
6036 while (*l
!= END_OF_INSN
)
6038 /* Non-zero if operand parens not balanced. */
6039 unsigned int paren_not_balanced
= 0;
6040 /* True if inside double quotes. */
6041 bool in_quotes
= false;
6043 /* Skip optional white space before operand. */
6044 if (is_space_char (*l
))
6046 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6048 as_bad (_("invalid character %s before operand %d"),
6049 output_invalid (*l
),
6053 token_start
= l
; /* After white space. */
6054 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6056 if (*l
== END_OF_INSN
)
6060 as_bad (_("unbalanced double quotes in operand %d."),
6064 if (paren_not_balanced
)
6066 know (!intel_syntax
);
6067 as_bad (_("unbalanced parenthesis in operand %d."),
6072 break; /* we are done */
6074 else if (*l
== '\\' && l
[1] == '"')
6077 in_quotes
= !in_quotes
;
6078 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6080 as_bad (_("invalid character %s in operand %d"),
6081 output_invalid (*l
),
6085 if (!intel_syntax
&& !in_quotes
)
6088 ++paren_not_balanced
;
6090 --paren_not_balanced
;
6094 if (l
!= token_start
)
6095 { /* Yes, we've read in another operand. */
6096 unsigned int operand_ok
;
6097 this_operand
= i
.operands
++;
6098 if (i
.operands
> MAX_OPERANDS
)
6100 as_bad (_("spurious operands; (%d operands/instruction max)"),
6104 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6105 /* Now parse operand adding info to 'i' as we go along. */
6106 END_STRING_AND_SAVE (l
);
6108 if (i
.mem_operands
> 1)
6110 as_bad (_("too many memory references for `%s'"),
6117 i386_intel_operand (token_start
,
6118 intel_float_operand (mnemonic
));
6120 operand_ok
= i386_att_operand (token_start
);
6122 RESTORE_END_STRING (l
);
6128 if (expecting_operand
)
6130 expecting_operand_after_comma
:
6131 as_bad (_("expecting operand after ','; got nothing"));
6136 as_bad (_("expecting operand before ','; got nothing"));
6141 /* Now *l must be either ',' or END_OF_INSN. */
6144 if (*++l
== END_OF_INSN
)
6146 /* Just skip it, if it's \n complain. */
6147 goto expecting_operand_after_comma
;
6149 expecting_operand
= 1;
6156 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6158 union i386_op temp_op
;
6159 i386_operand_type temp_type
;
6160 unsigned int temp_flags
;
6161 enum bfd_reloc_code_real temp_reloc
;
6163 temp_type
= i
.types
[xchg2
];
6164 i
.types
[xchg2
] = i
.types
[xchg1
];
6165 i
.types
[xchg1
] = temp_type
;
6167 temp_flags
= i
.flags
[xchg2
];
6168 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6169 i
.flags
[xchg1
] = temp_flags
;
6171 temp_op
= i
.op
[xchg2
];
6172 i
.op
[xchg2
] = i
.op
[xchg1
];
6173 i
.op
[xchg1
] = temp_op
;
6175 temp_reloc
= i
.reloc
[xchg2
];
6176 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6177 i
.reloc
[xchg1
] = temp_reloc
;
6179 temp_flags
= i
.imm_bits
[xchg2
];
6180 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6181 i
.imm_bits
[xchg1
] = temp_flags
;
6185 if (i
.mask
.operand
== xchg1
)
6186 i
.mask
.operand
= xchg2
;
6187 else if (i
.mask
.operand
== xchg2
)
6188 i
.mask
.operand
= xchg1
;
6190 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6192 if (i
.broadcast
.operand
== xchg1
)
6193 i
.broadcast
.operand
= xchg2
;
6194 else if (i
.broadcast
.operand
== xchg2
)
6195 i
.broadcast
.operand
= xchg1
;
6200 swap_operands (void)
6206 swap_2_operands (1, i
.operands
- 2);
6210 swap_2_operands (0, i
.operands
- 1);
6216 if (i
.mem_operands
== 2)
6218 const reg_entry
*temp_seg
;
6219 temp_seg
= i
.seg
[0];
6220 i
.seg
[0] = i
.seg
[1];
6221 i
.seg
[1] = temp_seg
;
6225 /* Try to ensure constant immediates are represented in the smallest
6230 char guess_suffix
= 0;
6234 guess_suffix
= i
.suffix
;
6235 else if (i
.reg_operands
)
6237 /* Figure out a suffix from the last register operand specified.
6238 We can't do this properly yet, i.e. excluding special register
6239 instances, but the following works for instructions with
6240 immediates. In any case, we can't set i.suffix yet. */
6241 for (op
= i
.operands
; --op
>= 0;)
6242 if (i
.types
[op
].bitfield
.class != Reg
)
6244 else if (i
.types
[op
].bitfield
.byte
)
6246 guess_suffix
= BYTE_MNEM_SUFFIX
;
6249 else if (i
.types
[op
].bitfield
.word
)
6251 guess_suffix
= WORD_MNEM_SUFFIX
;
6254 else if (i
.types
[op
].bitfield
.dword
)
6256 guess_suffix
= LONG_MNEM_SUFFIX
;
6259 else if (i
.types
[op
].bitfield
.qword
)
6261 guess_suffix
= QWORD_MNEM_SUFFIX
;
6265 else if ((flag_code
== CODE_16BIT
)
6266 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6267 guess_suffix
= WORD_MNEM_SUFFIX
;
6268 else if (flag_code
!= CODE_64BIT
6269 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6270 /* A more generic (but also more involved) way of dealing
6271 with the special case(s) would be to go look for
6272 DefaultSize attributes on any of the templates. */
6273 && current_templates
->start
->mnem_off
!= MN_push
))
6274 guess_suffix
= LONG_MNEM_SUFFIX
;
6276 for (op
= i
.operands
; --op
>= 0;)
6277 if (operand_type_check (i
.types
[op
], imm
))
6279 switch (i
.op
[op
].imms
->X_op
)
6282 /* If a suffix is given, this operand may be shortened. */
6283 switch (guess_suffix
)
6285 case LONG_MNEM_SUFFIX
:
6286 i
.types
[op
].bitfield
.imm32
= 1;
6287 i
.types
[op
].bitfield
.imm64
= 1;
6289 case WORD_MNEM_SUFFIX
:
6290 i
.types
[op
].bitfield
.imm16
= 1;
6291 i
.types
[op
].bitfield
.imm32
= 1;
6292 i
.types
[op
].bitfield
.imm32s
= 1;
6293 i
.types
[op
].bitfield
.imm64
= 1;
6295 case BYTE_MNEM_SUFFIX
:
6296 i
.types
[op
].bitfield
.imm8
= 1;
6297 i
.types
[op
].bitfield
.imm8s
= 1;
6298 i
.types
[op
].bitfield
.imm16
= 1;
6299 i
.types
[op
].bitfield
.imm32
= 1;
6300 i
.types
[op
].bitfield
.imm32s
= 1;
6301 i
.types
[op
].bitfield
.imm64
= 1;
6305 /* If this operand is at most 16 bits, convert it
6306 to a signed 16 bit number before trying to see
6307 whether it will fit in an even smaller size.
6308 This allows a 16-bit operand such as $0xffe0 to
6309 be recognised as within Imm8S range. */
6310 if ((i
.types
[op
].bitfield
.imm16
)
6311 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6313 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6314 ^ 0x8000) - 0x8000);
6317 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6318 if ((i
.types
[op
].bitfield
.imm32
)
6319 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6321 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6322 ^ ((offsetT
) 1 << 31))
6323 - ((offsetT
) 1 << 31));
6327 = operand_type_or (i
.types
[op
],
6328 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6330 /* We must avoid matching of Imm32 templates when 64bit
6331 only immediate is available. */
6332 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6333 i
.types
[op
].bitfield
.imm32
= 0;
6340 /* Symbols and expressions. */
6342 /* Convert symbolic operand to proper sizes for matching, but don't
6343 prevent matching a set of insns that only supports sizes other
6344 than those matching the insn suffix. */
6346 i386_operand_type mask
, allowed
;
6347 const insn_template
*t
= current_templates
->start
;
6349 operand_type_set (&mask
, 0);
6350 switch (guess_suffix
)
6352 case QWORD_MNEM_SUFFIX
:
6353 mask
.bitfield
.imm64
= 1;
6354 mask
.bitfield
.imm32s
= 1;
6356 case LONG_MNEM_SUFFIX
:
6357 mask
.bitfield
.imm32
= 1;
6359 case WORD_MNEM_SUFFIX
:
6360 mask
.bitfield
.imm16
= 1;
6362 case BYTE_MNEM_SUFFIX
:
6363 mask
.bitfield
.imm8
= 1;
6369 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6370 while (++t
< current_templates
->end
)
6372 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6373 allowed
= operand_type_and (allowed
, mask
);
6376 if (!operand_type_all_zero (&allowed
))
6377 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6384 /* Try to use the smallest displacement type too. */
6386 optimize_disp (const insn_template
*t
)
6390 if (!want_disp32 (t
)
6391 && (!t
->opcode_modifier
.jump
6392 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6394 for (op
= 0; op
< i
.operands
; ++op
)
6396 const expressionS
*exp
= i
.op
[op
].disps
;
6398 if (!operand_type_check (i
.types
[op
], disp
))
6401 if (exp
->X_op
!= O_constant
)
6404 /* Since displacement is signed extended to 64bit, don't allow
6405 disp32 if it is out of range. */
6406 if (fits_in_signed_long (exp
->X_add_number
))
6409 i
.types
[op
].bitfield
.disp32
= 0;
6410 if (i
.types
[op
].bitfield
.baseindex
)
6412 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6413 (uint64_t) exp
->X_add_number
);
6419 /* Don't optimize displacement for movabs since it only takes 64bit
6421 if (i
.disp_encoding
> disp_encoding_8bit
6422 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6425 for (op
= i
.operands
; op
-- > 0;)
6426 if (operand_type_check (i
.types
[op
], disp
))
6428 if (i
.op
[op
].disps
->X_op
== O_constant
)
6430 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6432 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6434 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6435 i
.op
[op
].disps
= NULL
;
6440 if (i
.types
[op
].bitfield
.disp16
6441 && fits_in_unsigned_word (op_disp
))
6443 /* If this operand is at most 16 bits, convert
6444 to a signed 16 bit number and don't use 64bit
6446 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6447 i
.types
[op
].bitfield
.disp64
= 0;
6451 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6452 if ((flag_code
!= CODE_64BIT
6453 ? i
.types
[op
].bitfield
.disp32
6455 && (!t
->opcode_modifier
.jump
6456 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6457 && fits_in_unsigned_long (op_disp
))
6459 /* If this operand is at most 32 bits, convert
6460 to a signed 32 bit number and don't use 64bit
6462 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6463 i
.types
[op
].bitfield
.disp64
= 0;
6464 i
.types
[op
].bitfield
.disp32
= 1;
6467 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6469 i
.types
[op
].bitfield
.disp64
= 0;
6470 i
.types
[op
].bitfield
.disp32
= 1;
6473 if ((i
.types
[op
].bitfield
.disp32
6474 || i
.types
[op
].bitfield
.disp16
)
6475 && fits_in_disp8 (op_disp
))
6476 i
.types
[op
].bitfield
.disp8
= 1;
6478 i
.op
[op
].disps
->X_add_number
= op_disp
;
6480 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6481 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6483 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6484 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6485 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6488 /* We only support 64bit displacement on constants. */
6489 i
.types
[op
].bitfield
.disp64
= 0;
6495 /* Return 1 if there is a match in broadcast bytes between operand
6496 GIVEN and instruction template T. */
6499 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6501 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6502 && i
.types
[given
].bitfield
.byte
)
6503 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6504 && i
.types
[given
].bitfield
.word
)
6505 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6506 && i
.types
[given
].bitfield
.dword
)
6507 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6508 && i
.types
[given
].bitfield
.qword
));
6511 /* Check if operands are valid for the instruction. */
6514 check_VecOperands (const insn_template
*t
)
6519 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6520 any one operand are implicity requiring AVX512VL support if the actual
6521 operand size is YMMword or XMMword. Since this function runs after
6522 template matching, there's no need to check for YMMword/XMMword in
6524 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6525 if (!cpu_flags_all_zero (&cpu
)
6526 && !is_cpu (t
, CpuAVX512VL
)
6527 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6528 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6530 for (op
= 0; op
< t
->operands
; ++op
)
6532 if (t
->operand_types
[op
].bitfield
.zmmword
6533 && (i
.types
[op
].bitfield
.ymmword
6534 || i
.types
[op
].bitfield
.xmmword
))
6536 i
.error
= unsupported
;
6542 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6543 requiring AVX2 support if the actual operand size is YMMword. */
6544 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6545 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6547 for (op
= 0; op
< t
->operands
; ++op
)
6549 if (t
->operand_types
[op
].bitfield
.xmmword
6550 && i
.types
[op
].bitfield
.ymmword
)
6552 i
.error
= unsupported
;
6558 /* Without VSIB byte, we can't have a vector register for index. */
6559 if (!t
->opcode_modifier
.sib
6561 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6562 || i
.index_reg
->reg_type
.bitfield
.ymmword
6563 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6565 i
.error
= unsupported_vector_index_register
;
6569 /* Check if default mask is allowed. */
6570 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6571 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6573 i
.error
= no_default_mask
;
6577 /* For VSIB byte, we need a vector register for index, and all vector
6578 registers must be distinct. */
6579 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6582 || !((t
->opcode_modifier
.sib
== VECSIB128
6583 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6584 || (t
->opcode_modifier
.sib
== VECSIB256
6585 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6586 || (t
->opcode_modifier
.sib
== VECSIB512
6587 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6589 i
.error
= invalid_vsib_address
;
6593 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6594 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6596 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6597 gas_assert (i
.types
[0].bitfield
.xmmword
6598 || i
.types
[0].bitfield
.ymmword
);
6599 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6600 gas_assert (i
.types
[2].bitfield
.xmmword
6601 || i
.types
[2].bitfield
.ymmword
);
6602 if (operand_check
== check_none
)
6604 if (register_number (i
.op
[0].regs
)
6605 != register_number (i
.index_reg
)
6606 && register_number (i
.op
[2].regs
)
6607 != register_number (i
.index_reg
)
6608 && register_number (i
.op
[0].regs
)
6609 != register_number (i
.op
[2].regs
))
6611 if (operand_check
== check_error
)
6613 i
.error
= invalid_vector_register_set
;
6616 as_warn (_("mask, index, and destination registers should be distinct"));
6618 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6620 if (i
.types
[1].bitfield
.class == RegSIMD
6621 && (i
.types
[1].bitfield
.xmmword
6622 || i
.types
[1].bitfield
.ymmword
6623 || i
.types
[1].bitfield
.zmmword
)
6624 && (register_number (i
.op
[1].regs
)
6625 == register_number (i
.index_reg
)))
6627 if (operand_check
== check_error
)
6629 i
.error
= invalid_vector_register_set
;
6632 if (operand_check
!= check_none
)
6633 as_warn (_("index and destination registers should be distinct"));
6638 /* For AMX instructions with 3 TMM register operands, all operands
6639 must be distinct. */
6640 if (i
.reg_operands
== 3
6641 && t
->operand_types
[0].bitfield
.tmmword
6642 && (i
.op
[0].regs
== i
.op
[1].regs
6643 || i
.op
[0].regs
== i
.op
[2].regs
6644 || i
.op
[1].regs
== i
.op
[2].regs
))
6646 i
.error
= invalid_tmm_register_set
;
6650 /* For some special instructions require that destination must be distinct
6651 from source registers. */
6652 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6654 unsigned int dest_reg
= i
.operands
- 1;
6656 know (i
.operands
>= 3);
6658 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6659 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6660 || (i
.reg_operands
> 2
6661 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6663 i
.error
= invalid_dest_and_src_register_set
;
6668 /* Check if broadcast is supported by the instruction and is applied
6669 to the memory operand. */
6670 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6672 i386_operand_type type
, overlap
;
6674 /* Check if specified broadcast is supported in this instruction,
6675 and its broadcast bytes match the memory operand. */
6676 op
= i
.broadcast
.operand
;
6677 if (!t
->opcode_modifier
.broadcast
6678 || !(i
.flags
[op
] & Operand_Mem
)
6679 || (!i
.types
[op
].bitfield
.unspecified
6680 && !match_broadcast_size (t
, op
)))
6683 i
.error
= unsupported_broadcast
;
6687 operand_type_set (&type
, 0);
6688 switch (get_broadcast_bytes (t
, false))
6691 type
.bitfield
.word
= 1;
6694 type
.bitfield
.dword
= 1;
6697 type
.bitfield
.qword
= 1;
6700 type
.bitfield
.xmmword
= 1;
6703 if (vector_size
< VSZ256
)
6705 type
.bitfield
.ymmword
= 1;
6708 if (vector_size
< VSZ512
)
6710 type
.bitfield
.zmmword
= 1;
6716 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6717 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6718 && t
->operand_types
[op
].bitfield
.byte
6719 + t
->operand_types
[op
].bitfield
.word
6720 + t
->operand_types
[op
].bitfield
.dword
6721 + t
->operand_types
[op
].bitfield
.qword
> 1)
6723 overlap
.bitfield
.xmmword
= 0;
6724 overlap
.bitfield
.ymmword
= 0;
6725 overlap
.bitfield
.zmmword
= 0;
6727 if (operand_type_all_zero (&overlap
))
6730 if (t
->opcode_modifier
.checkoperandsize
)
6734 type
.bitfield
.baseindex
= 1;
6735 for (j
= 0; j
< i
.operands
; ++j
)
6738 && !operand_type_register_match(i
.types
[j
],
6739 t
->operand_types
[j
],
6741 t
->operand_types
[op
]))
6746 /* If broadcast is supported in this instruction, we need to check if
6747 operand of one-element size isn't specified without broadcast. */
6748 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6750 /* Find memory operand. */
6751 for (op
= 0; op
< i
.operands
; op
++)
6752 if (i
.flags
[op
] & Operand_Mem
)
6754 gas_assert (op
< i
.operands
);
6755 /* Check size of the memory operand. */
6756 if (match_broadcast_size (t
, op
))
6758 i
.error
= broadcast_needed
;
6763 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6765 /* Check if requested masking is supported. */
6768 if (!t
->opcode_modifier
.masking
)
6770 i
.error
= unsupported_masking
;
6774 /* Common rules for masking:
6775 - mask register destinations permit only zeroing-masking, without
6776 that actually being expressed by a {z} operand suffix or EVEX.z,
6777 - memory destinations allow only merging-masking,
6778 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6781 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6782 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6783 || t
->opcode_modifier
.sib
))
6785 i
.error
= unsupported_masking
;
6790 /* Check if masking is applied to dest operand. */
6791 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6793 i
.error
= mask_not_on_destination
;
6798 if (i
.rounding
.type
!= rc_none
)
6800 if (!t
->opcode_modifier
.sae
6801 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6804 i
.error
= unsupported_rc_sae
;
6808 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6810 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6812 for (op
= 0; op
< t
->operands
; ++op
)
6813 if (i
.types
[op
].bitfield
.zmmword
)
6815 if (op
>= t
->operands
)
6817 i
.error
= operand_size_mismatch
;
6823 /* Check the special Imm4 cases; must be the first operand. */
6824 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6826 if (i
.op
[0].imms
->X_op
!= O_constant
6827 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6833 /* Turn off Imm<N> so that update_imm won't complain. */
6834 operand_type_set (&i
.types
[0], 0);
6837 /* Check vector Disp8 operand. */
6838 if (t
->opcode_modifier
.disp8memshift
6839 && (!t
->opcode_modifier
.vex
6840 || need_evex_encoding ())
6841 && i
.disp_encoding
<= disp_encoding_8bit
)
6843 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6844 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6845 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6846 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6849 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6852 for (op
= 0; op
< i
.operands
; op
++)
6853 if (i
.flags
[op
] & Operand_Mem
)
6855 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6856 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6857 else if (t
->operand_types
[op
].bitfield
.xmmword
6858 + t
->operand_types
[op
].bitfield
.ymmword
6859 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6860 type
= &t
->operand_types
[op
];
6861 else if (!i
.types
[op
].bitfield
.unspecified
)
6862 type
= &i
.types
[op
];
6863 else /* Ambiguities get resolved elsewhere. */
6864 fallback
= &t
->operand_types
[op
];
6866 else if (i
.types
[op
].bitfield
.class == RegSIMD
6867 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6869 if (i
.types
[op
].bitfield
.zmmword
)
6871 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6873 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6877 if (!type
&& !i
.memshift
)
6881 if (type
->bitfield
.zmmword
)
6883 else if (type
->bitfield
.ymmword
)
6885 else if (type
->bitfield
.xmmword
)
6889 /* For the check in fits_in_disp8(). */
6890 if (i
.memshift
== 0)
6894 for (op
= 0; op
< i
.operands
; op
++)
6895 if (operand_type_check (i
.types
[op
], disp
)
6896 && i
.op
[op
].disps
->X_op
== O_constant
)
6898 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6900 i
.types
[op
].bitfield
.disp8
= 1;
6903 i
.types
[op
].bitfield
.disp8
= 0;
6912 /* Check if encoding requirements are met by the instruction. */
6915 VEX_check_encoding (const insn_template
*t
)
6917 if (i
.vec_encoding
== vex_encoding_error
)
6919 i
.error
= unsupported
;
6923 /* Vector size restrictions. */
6924 if ((vector_size
< VSZ512
6925 && (t
->opcode_modifier
.evex
== EVEX512
6926 || t
->opcode_modifier
.vsz
>= VSZ512
))
6927 || (vector_size
< VSZ256
6928 && (t
->opcode_modifier
.evex
== EVEX256
6929 || t
->opcode_modifier
.vex
== VEX256
6930 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6932 i
.error
= unsupported
;
6936 if (i
.vec_encoding
== vex_encoding_evex
6937 || i
.vec_encoding
== vex_encoding_evex512
)
6939 /* This instruction must be encoded with EVEX prefix. */
6940 if (!is_evex_encoding (t
))
6942 i
.error
= unsupported
;
6948 if (!t
->opcode_modifier
.vex
)
6950 /* This instruction template doesn't have VEX prefix. */
6951 if (i
.vec_encoding
!= vex_encoding_default
)
6953 i
.error
= unsupported
;
6962 /* Helper function for the progress() macro in match_template(). */
6963 static INLINE
enum i386_error
progress (enum i386_error
new,
6964 enum i386_error last
,
6965 unsigned int line
, unsigned int *line_p
)
6967 if (line
<= *line_p
)
6973 static const insn_template
*
6974 match_template (char mnem_suffix
)
6976 /* Points to template once we've found it. */
6977 const insn_template
*t
;
6978 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6979 i386_operand_type overlap4
;
6980 unsigned int found_reverse_match
;
6981 i386_operand_type operand_types
[MAX_OPERANDS
];
6982 int addr_prefix_disp
;
6983 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6984 enum i386_error specific_error
= number_of_operands_mismatch
;
6985 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6987 #if MAX_OPERANDS != 5
6988 # error "MAX_OPERANDS must be 5."
6991 found_reverse_match
= 0;
6992 addr_prefix_disp
= -1;
6994 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6996 addr_prefix_disp
= -1;
6997 found_reverse_match
= 0;
6999 /* Must have right number of operands. */
7000 if (i
.operands
!= t
->operands
)
7003 /* Check processor support. */
7004 specific_error
= progress (unsupported
);
7005 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7008 /* Check AT&T mnemonic. */
7009 specific_error
= progress (unsupported_with_intel_mnemonic
);
7010 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7013 /* Check AT&T/Intel syntax. */
7014 specific_error
= progress (unsupported_syntax
);
7015 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7016 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7019 /* Check Intel64/AMD64 ISA. */
7023 /* Default: Don't accept Intel64. */
7024 if (t
->opcode_modifier
.isa64
== INTEL64
)
7028 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7029 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7033 /* -mintel64: Don't accept AMD64. */
7034 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7039 /* Check the suffix. */
7040 specific_error
= progress (invalid_instruction_suffix
);
7041 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7042 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7043 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7044 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7045 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7048 specific_error
= progress (operand_size_mismatch
);
7049 size_match
= operand_size_match (t
);
7053 /* This is intentionally not
7055 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7057 as the case of a missing * on the operand is accepted (perhaps with
7058 a warning, issued further down). */
7059 specific_error
= progress (operand_type_mismatch
);
7060 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7063 /* In Intel syntax, normally we can check for memory operand size when
7064 there is no mnemonic suffix. But jmp and call have 2 different
7065 encodings with Dword memory operand size. Skip the "near" one
7066 (permitting a register operand) when "far" was requested. */
7068 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7069 && t
->operand_types
[0].bitfield
.class == Reg
)
7072 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7073 operand_types
[j
] = t
->operand_types
[j
];
7075 /* In general, don't allow 32-bit operands on pre-386. */
7076 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7077 : operand_size_mismatch
);
7078 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7079 if (i
.suffix
== LONG_MNEM_SUFFIX
7080 && !cpu_arch_flags
.bitfield
.cpui386
7082 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7083 && !intel_float_operand (insn_name (t
)))
7084 : intel_float_operand (insn_name (t
)) != 2)
7085 && (t
->operands
== i
.imm_operands
7086 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7087 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7088 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7089 || (operand_types
[j
].bitfield
.class != RegMMX
7090 && operand_types
[j
].bitfield
.class != RegSIMD
7091 && operand_types
[j
].bitfield
.class != RegMask
))
7092 && !t
->opcode_modifier
.sib
)
7095 /* Do not verify operands when there are none. */
7098 if (VEX_check_encoding (t
))
7100 specific_error
= progress (i
.error
);
7104 /* We've found a match; break out of loop. */
7108 if (!t
->opcode_modifier
.jump
7109 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7111 /* There should be only one Disp operand. */
7112 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7113 if (operand_type_check (operand_types
[j
], disp
))
7115 if (j
< MAX_OPERANDS
)
7117 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7119 addr_prefix_disp
= j
;
7121 /* Address size prefix will turn Disp64 operand into Disp32 and
7122 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7126 override
= !override
;
7129 if (operand_types
[j
].bitfield
.disp32
7130 && operand_types
[j
].bitfield
.disp16
)
7132 operand_types
[j
].bitfield
.disp16
= override
;
7133 operand_types
[j
].bitfield
.disp32
= !override
;
7135 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7139 if (operand_types
[j
].bitfield
.disp64
)
7141 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7142 operand_types
[j
].bitfield
.disp32
= override
;
7143 operand_types
[j
].bitfield
.disp64
= !override
;
7145 operand_types
[j
].bitfield
.disp16
= 0;
7151 /* We check register size if needed. */
7152 if (t
->opcode_modifier
.checkoperandsize
)
7154 check_register
= (1 << t
->operands
) - 1;
7155 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7156 check_register
&= ~(1 << i
.broadcast
.operand
);
7161 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7162 switch (t
->operands
)
7165 if (!operand_type_match (overlap0
, i
.types
[0]))
7168 /* Allow the ModR/M encoding to be requested by using the {load} or
7169 {store} pseudo prefix on an applicable insn. */
7170 if (!t
->opcode_modifier
.modrm
7171 && i
.reg_operands
== 1
7172 && ((i
.dir_encoding
== dir_encoding_load
7173 && t
->mnem_off
!= MN_pop
)
7174 || (i
.dir_encoding
== dir_encoding_store
7175 && t
->mnem_off
!= MN_push
))
7177 && t
->mnem_off
!= MN_bswap
)
7182 /* xchg %eax, %eax is a special case. It is an alias for nop
7183 only in 32bit mode and we can use opcode 0x90. In 64bit
7184 mode, we can't use 0x90 for xchg %eax, %eax since it should
7185 zero-extend %eax to %rax. */
7186 if (t
->base_opcode
== 0x90
7187 && t
->opcode_space
== SPACE_BASE
)
7189 if (flag_code
== CODE_64BIT
7190 && i
.types
[0].bitfield
.instance
== Accum
7191 && i
.types
[0].bitfield
.dword
7192 && i
.types
[1].bitfield
.instance
== Accum
)
7195 /* Allow the ModR/M encoding to be requested by using the
7196 {load} or {store} pseudo prefix. */
7197 if (i
.dir_encoding
== dir_encoding_load
7198 || i
.dir_encoding
== dir_encoding_store
)
7202 if (t
->base_opcode
== MOV_AX_DISP32
7203 && t
->opcode_space
== SPACE_BASE
7204 && t
->mnem_off
!= MN_movabs
)
7206 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7207 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7210 /* xrelease mov %eax, <disp> is another special case. It must not
7211 match the accumulator-only encoding of mov. */
7215 /* Allow the ModR/M encoding to be requested by using a suitable
7216 {load} or {store} pseudo prefix. */
7217 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7218 ? dir_encoding_store
7219 : dir_encoding_load
)
7220 && !i
.types
[0].bitfield
.disp64
7221 && !i
.types
[1].bitfield
.disp64
)
7225 /* Allow the ModR/M encoding to be requested by using the {load} or
7226 {store} pseudo prefix on an applicable insn. */
7227 if (!t
->opcode_modifier
.modrm
7228 && i
.reg_operands
== 1
7229 && i
.imm_operands
== 1
7230 && (i
.dir_encoding
== dir_encoding_load
7231 || i
.dir_encoding
== dir_encoding_store
)
7232 && t
->opcode_space
== SPACE_BASE
)
7234 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7235 && i
.dir_encoding
== dir_encoding_store
)
7238 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7239 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7240 || i
.dir_encoding
== dir_encoding_load
))
7243 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7244 && i
.dir_encoding
== dir_encoding_load
)
7250 if (!(size_match
& MATCH_STRAIGHT
))
7252 /* Reverse direction of operands if swapping is possible in the first
7253 place (operands need to be symmetric) and
7254 - the load form is requested, and the template is a store form,
7255 - the store form is requested, and the template is a load form,
7256 - the non-default (swapped) form is requested. */
7257 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7258 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7259 && !operand_type_all_zero (&overlap1
))
7260 switch (i
.dir_encoding
)
7262 case dir_encoding_load
:
7263 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7264 || t
->opcode_modifier
.regmem
)
7268 case dir_encoding_store
:
7269 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7270 && !t
->opcode_modifier
.regmem
)
7274 case dir_encoding_swap
:
7277 case dir_encoding_default
:
7280 /* If we want store form, we skip the current load. */
7281 if ((i
.dir_encoding
== dir_encoding_store
7282 || i
.dir_encoding
== dir_encoding_swap
)
7283 && i
.mem_operands
== 0
7284 && t
->opcode_modifier
.load
)
7289 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7290 if (!operand_type_match (overlap0
, i
.types
[0])
7291 || !operand_type_match (overlap1
, i
.types
[1])
7292 || ((check_register
& 3) == 3
7293 && !operand_type_register_match (i
.types
[0],
7298 specific_error
= progress (i
.error
);
7300 /* Check if other direction is valid ... */
7301 if (!t
->opcode_modifier
.d
)
7305 if (!(size_match
& MATCH_REVERSE
))
7307 /* Try reversing direction of operands. */
7308 j
= is_cpu (t
, CpuFMA4
)
7309 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7310 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7311 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7312 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7313 gas_assert (t
->operands
!= 3 || !check_register
);
7314 if (!operand_type_match (overlap0
, i
.types
[0])
7315 || !operand_type_match (overlap1
, i
.types
[j
])
7316 || (t
->operands
== 3
7317 && !operand_type_match (overlap2
, i
.types
[1]))
7319 && !operand_type_register_match (i
.types
[0],
7324 /* Does not match either direction. */
7325 specific_error
= progress (i
.error
);
7328 /* found_reverse_match holds which variant of D
7330 if (!t
->opcode_modifier
.d
)
7331 found_reverse_match
= 0;
7332 else if (operand_types
[0].bitfield
.tbyte
)
7334 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7335 found_reverse_match
= Opcode_FloatD
;
7337 found_reverse_match
= ~0;
7338 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7339 if ((t
->extension_opcode
& 4)
7340 && (intel_syntax
|| intel_mnemonic
))
7341 found_reverse_match
|= Opcode_FloatR
;
7343 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7345 found_reverse_match
= Opcode_VexW
;
7346 goto check_operands_345
;
7348 else if (t
->opcode_space
!= SPACE_BASE
7349 && (t
->opcode_space
!= SPACE_0F
7350 /* MOV to/from CR/DR/TR, as an exception, follow
7351 the base opcode space encoding model. */
7352 || (t
->base_opcode
| 7) != 0x27))
7353 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7354 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7355 else if (!t
->opcode_modifier
.commutative
)
7356 found_reverse_match
= Opcode_D
;
7358 found_reverse_match
= ~0;
7362 /* Found a forward 2 operand match here. */
7364 switch (t
->operands
)
7367 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7368 if (!operand_type_match (overlap4
, i
.types
[4])
7369 || !operand_type_register_match (i
.types
[3],
7374 specific_error
= progress (i
.error
);
7379 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7380 if (!operand_type_match (overlap3
, i
.types
[3])
7381 || ((check_register
& 0xa) == 0xa
7382 && !operand_type_register_match (i
.types
[1],
7386 || ((check_register
& 0xc) == 0xc
7387 && !operand_type_register_match (i
.types
[2],
7392 specific_error
= progress (i
.error
);
7397 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7398 if (!operand_type_match (overlap2
, i
.types
[2])
7399 || ((check_register
& 5) == 5
7400 && !operand_type_register_match (i
.types
[0],
7404 || ((check_register
& 6) == 6
7405 && !operand_type_register_match (i
.types
[1],
7410 specific_error
= progress (i
.error
);
7416 /* Found either forward/reverse 2, 3 or 4 operand match here:
7417 slip through to break. */
7420 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7421 if (VEX_check_encoding (t
))
7423 specific_error
= progress (i
.error
);
7427 /* Check if vector operands are valid. */
7428 if (check_VecOperands (t
))
7430 specific_error
= progress (i
.error
);
7434 /* Check whether to use the shorter VEX encoding for certain insns where
7435 the EVEX enconding comes first in the table. This requires the respective
7436 AVX-* feature to be explicitly enabled. */
7437 if (t
== current_templates
->start
7438 && t
->opcode_modifier
.disp8memshift
7439 && !t
->opcode_modifier
.vex
7440 && !need_evex_encoding ()
7441 && t
+ 1 < current_templates
->end
7442 && t
[1].opcode_modifier
.vex
)
7445 unsigned int memshift
= i
.memshift
;
7448 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7449 if (!cpu_flags_all_zero (&cpu
)
7450 && (!i
.types
[0].bitfield
.disp8
7451 || !operand_type_check (i
.types
[0], disp
)
7452 || i
.op
[0].disps
->X_op
!= O_constant
7453 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7455 specific_error
= progress (internal_error
);
7458 i
.memshift
= memshift
;
7461 /* We've found a match; break out of loop. */
7467 if (t
== current_templates
->end
)
7469 /* We found no match. */
7470 i
.error
= specific_error
;
7474 if (!quiet_warnings
)
7477 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7478 as_warn (_("indirect %s without `*'"), insn_name (t
));
7480 if (t
->opcode_modifier
.isprefix
7481 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7483 /* Warn them that a data or address size prefix doesn't
7484 affect assembly of the next line of code. */
7485 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7489 /* Copy the template we found. */
7490 install_template (t
);
7492 if (addr_prefix_disp
!= -1)
7493 i
.tm
.operand_types
[addr_prefix_disp
]
7494 = operand_types
[addr_prefix_disp
];
7496 switch (found_reverse_match
)
7502 case Opcode_FloatR
| Opcode_FloatD
:
7503 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7504 found_reverse_match
&= Opcode_FloatD
;
7508 /* If we found a reverse match we must alter the opcode direction
7509 bit and clear/flip the regmem modifier one. found_reverse_match
7510 holds bits to change (different for int & float insns). */
7512 i
.tm
.base_opcode
^= found_reverse_match
;
7514 /* Certain SIMD insns have their load forms specified in the opcode
7515 table, and hence we need to _set_ RegMem instead of clearing it.
7516 We need to avoid setting the bit though on insns like KMOVW. */
7517 i
.tm
.opcode_modifier
.regmem
7518 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7519 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7520 && !i
.tm
.opcode_modifier
.regmem
;
7524 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7525 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7529 /* Only the first two register operands need reversing, alongside
7531 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7533 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7534 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7535 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7545 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7546 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7548 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7550 as_bad (_("`%s' operand %u must use `%ses' segment"),
7552 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7557 /* There's only ever one segment override allowed per instruction.
7558 This instruction possibly has a legal segment override on the
7559 second operand, so copy the segment to where non-string
7560 instructions store it, allowing common code. */
7561 i
.seg
[op
] = i
.seg
[1];
7567 process_suffix (void)
7569 bool is_movx
= false;
7571 /* If matched instruction specifies an explicit instruction mnemonic
7573 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7574 i
.suffix
= WORD_MNEM_SUFFIX
;
7575 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7576 i
.suffix
= LONG_MNEM_SUFFIX
;
7577 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7578 i
.suffix
= QWORD_MNEM_SUFFIX
;
7579 else if (i
.reg_operands
7580 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7581 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7583 unsigned int numop
= i
.operands
;
7586 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7587 && (i
.tm
.base_opcode
| 8) == 0xbe)
7588 || (i
.tm
.opcode_space
== SPACE_BASE
7589 && i
.tm
.base_opcode
== 0x63
7590 && is_cpu (&i
.tm
, Cpu64
));
7592 /* movsx/movzx want only their source operand considered here, for the
7593 ambiguity checking below. The suffix will be replaced afterwards
7594 to represent the destination (register). */
7595 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7598 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7599 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7602 /* If there's no instruction mnemonic suffix we try to invent one
7603 based on GPR operands. */
7606 /* We take i.suffix from the last register operand specified,
7607 Destination register type is more significant than source
7608 register type. crc32 in SSE4.2 prefers source register
7610 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7613 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7614 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7616 if (i
.types
[op
].bitfield
.class != Reg
)
7618 if (i
.types
[op
].bitfield
.byte
)
7619 i
.suffix
= BYTE_MNEM_SUFFIX
;
7620 else if (i
.types
[op
].bitfield
.word
)
7621 i
.suffix
= WORD_MNEM_SUFFIX
;
7622 else if (i
.types
[op
].bitfield
.dword
)
7623 i
.suffix
= LONG_MNEM_SUFFIX
;
7624 else if (i
.types
[op
].bitfield
.qword
)
7625 i
.suffix
= QWORD_MNEM_SUFFIX
;
7631 /* As an exception, movsx/movzx silently default to a byte source
7633 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7634 i
.suffix
= BYTE_MNEM_SUFFIX
;
7636 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7638 if (!check_byte_reg ())
7641 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7643 if (!check_long_reg ())
7646 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7648 if (!check_qword_reg ())
7651 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7653 if (!check_word_reg ())
7656 else if (intel_syntax
7657 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7658 /* Do nothing if the instruction is going to ignore the prefix. */
7663 /* Undo the movsx/movzx change done above. */
7666 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7669 i
.suffix
= stackop_size
;
7670 if (stackop_size
== LONG_MNEM_SUFFIX
)
7672 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7673 .code16gcc directive to support 16-bit mode with
7674 32-bit address. For IRET without a suffix, generate
7675 16-bit IRET (opcode 0xcf) to return from an interrupt
7677 if (i
.tm
.base_opcode
== 0xcf)
7679 i
.suffix
= WORD_MNEM_SUFFIX
;
7680 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7682 /* Warn about changed behavior for segment register push/pop. */
7683 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7684 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7689 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7690 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7691 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7692 || (i
.tm
.opcode_space
== SPACE_0F
7693 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7694 && i
.tm
.extension_opcode
<= 3)))
7699 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7701 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7702 || i
.tm
.opcode_modifier
.no_lsuf
)
7703 i
.suffix
= QWORD_MNEM_SUFFIX
;
7708 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7709 i
.suffix
= LONG_MNEM_SUFFIX
;
7712 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7713 i
.suffix
= WORD_MNEM_SUFFIX
;
7719 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7720 /* Also cover lret/retf/iret in 64-bit mode. */
7721 || (flag_code
== CODE_64BIT
7722 && !i
.tm
.opcode_modifier
.no_lsuf
7723 && !i
.tm
.opcode_modifier
.no_qsuf
))
7724 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7725 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7726 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7727 /* Accept FLDENV et al without suffix. */
7728 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7730 unsigned int suffixes
, evex
= 0;
7732 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7733 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7735 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7737 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7739 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7742 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7743 also suitable for AT&T syntax mode, it was requested that this be
7744 restricted to just Intel syntax. */
7745 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7746 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7750 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7752 if (vector_size
< VSZ512
)
7754 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7755 if (vector_size
< VSZ256
)
7757 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7758 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7759 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7760 || (!i
.tm
.opcode_modifier
.evex
7761 && is_evex_encoding (&i
.tm
))))
7762 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7764 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7765 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7766 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7767 || (!i
.tm
.opcode_modifier
.evex
7768 && is_evex_encoding (&i
.tm
))))
7769 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7771 else if (is_evex_encoding (&i
.tm
)
7772 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7774 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7775 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7776 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7777 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7778 if (!i
.tm
.opcode_modifier
.evex
7779 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7780 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7783 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7784 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7785 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7788 /* Any properly sized operand disambiguates the insn. */
7789 if (i
.types
[op
].bitfield
.xmmword
7790 || i
.types
[op
].bitfield
.ymmword
7791 || i
.types
[op
].bitfield
.zmmword
)
7793 suffixes
&= ~(7 << 6);
7798 if ((i
.flags
[op
] & Operand_Mem
)
7799 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7801 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7803 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7805 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7807 if (is_evex_encoding (&i
.tm
))
7813 /* Are multiple suffixes / operand sizes allowed? */
7814 if (suffixes
& (suffixes
- 1))
7817 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7818 || operand_check
== check_error
))
7820 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7823 if (operand_check
== check_error
)
7825 as_bad (_("no instruction mnemonic suffix given and "
7826 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7829 if (operand_check
== check_warning
)
7830 as_warn (_("%s; using default for `%s'"),
7832 ? _("ambiguous operand size")
7833 : _("no instruction mnemonic suffix given and "
7834 "no register operands"),
7837 if (i
.tm
.opcode_modifier
.floatmf
)
7838 i
.suffix
= SHORT_MNEM_SUFFIX
;
7840 /* handled below */;
7842 i
.tm
.opcode_modifier
.evex
= evex
;
7843 else if (flag_code
== CODE_16BIT
)
7844 i
.suffix
= WORD_MNEM_SUFFIX
;
7845 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7846 i
.suffix
= LONG_MNEM_SUFFIX
;
7848 i
.suffix
= QWORD_MNEM_SUFFIX
;
7854 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7855 In AT&T syntax, if there is no suffix (warned about above), the default
7856 will be byte extension. */
7857 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7858 i
.tm
.base_opcode
|= 1;
7860 /* For further processing, the suffix should represent the destination
7861 (register). This is already the case when one was used with
7862 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7863 no suffix to begin with. */
7864 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7866 if (i
.types
[1].bitfield
.word
)
7867 i
.suffix
= WORD_MNEM_SUFFIX
;
7868 else if (i
.types
[1].bitfield
.qword
)
7869 i
.suffix
= QWORD_MNEM_SUFFIX
;
7871 i
.suffix
= LONG_MNEM_SUFFIX
;
7873 i
.tm
.opcode_modifier
.w
= 0;
7877 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7878 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7879 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7881 /* Change the opcode based on the operand size given by i.suffix. */
7884 /* Size floating point instruction. */
7885 case LONG_MNEM_SUFFIX
:
7886 if (i
.tm
.opcode_modifier
.floatmf
)
7888 i
.tm
.base_opcode
^= 4;
7892 case WORD_MNEM_SUFFIX
:
7893 case QWORD_MNEM_SUFFIX
:
7894 /* It's not a byte, select word/dword operation. */
7895 if (i
.tm
.opcode_modifier
.w
)
7898 i
.tm
.base_opcode
|= 8;
7900 i
.tm
.base_opcode
|= 1;
7903 case SHORT_MNEM_SUFFIX
:
7904 /* Now select between word & dword operations via the operand
7905 size prefix, except for instructions that will ignore this
7907 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7908 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7909 && !i
.tm
.opcode_modifier
.floatmf
7910 && !is_any_vex_encoding (&i
.tm
)
7911 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7912 || (flag_code
== CODE_64BIT
7913 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7915 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7917 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7918 prefix
= ADDR_PREFIX_OPCODE
;
7920 if (!add_prefix (prefix
))
7924 /* Set mode64 for an operand. */
7925 if (i
.suffix
== QWORD_MNEM_SUFFIX
7926 && flag_code
== CODE_64BIT
7927 && !i
.tm
.opcode_modifier
.norex64
7928 && !i
.tm
.opcode_modifier
.vexw
7929 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7931 && ! (i
.operands
== 2
7932 && i
.tm
.base_opcode
== 0x90
7933 && i
.tm
.opcode_space
== SPACE_BASE
7934 && i
.types
[0].bitfield
.instance
== Accum
7935 && i
.types
[0].bitfield
.qword
7936 && i
.types
[1].bitfield
.instance
== Accum
))
7942 /* Select word/dword/qword operation with explicit data sizing prefix
7943 when there are no suitable register operands. */
7944 if (i
.tm
.opcode_modifier
.w
7945 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7947 || (i
.reg_operands
== 1
7949 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7951 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7952 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7953 || i
.tm
.mnem_off
== MN_crc32
))))
7954 i
.tm
.base_opcode
|= 1;
7958 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7960 gas_assert (!i
.suffix
);
7961 gas_assert (i
.reg_operands
);
7963 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7966 /* The address size override prefix changes the size of the
7968 if (flag_code
== CODE_64BIT
7969 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7971 as_bad (_("16-bit addressing unavailable for `%s'"),
7976 if ((flag_code
== CODE_32BIT
7977 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7978 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7979 && !add_prefix (ADDR_PREFIX_OPCODE
))
7984 /* Check invalid register operand when the address size override
7985 prefix changes the size of register operands. */
7987 enum { need_word
, need_dword
, need_qword
} need
;
7989 /* Check the register operand for the address size prefix if
7990 the memory operand has no real registers, like symbol, DISP
7991 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7992 if (i
.mem_operands
== 1
7993 && i
.reg_operands
== 1
7995 && i
.types
[1].bitfield
.class == Reg
7996 && (flag_code
== CODE_32BIT
7997 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7998 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7999 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8000 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8001 || (x86_elf_abi
== X86_64_X32_ABI
8003 && i
.base_reg
->reg_num
== RegIP
8004 && i
.base_reg
->reg_type
.bitfield
.qword
))
8008 && !add_prefix (ADDR_PREFIX_OPCODE
))
8011 if (flag_code
== CODE_32BIT
)
8012 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8013 else if (i
.prefix
[ADDR_PREFIX
])
8016 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8018 for (op
= 0; op
< i
.operands
; op
++)
8020 if (i
.types
[op
].bitfield
.class != Reg
)
8026 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8030 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8034 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8039 as_bad (_("invalid register operand size for `%s'"),
8050 check_byte_reg (void)
8054 for (op
= i
.operands
; --op
>= 0;)
8056 /* Skip non-register operands. */
8057 if (i
.types
[op
].bitfield
.class != Reg
)
8060 /* If this is an eight bit register, it's OK. If it's the 16 or
8061 32 bit version of an eight bit register, we will just use the
8062 low portion, and that's OK too. */
8063 if (i
.types
[op
].bitfield
.byte
)
8066 /* I/O port address operands are OK too. */
8067 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8068 && i
.tm
.operand_types
[op
].bitfield
.word
)
8071 /* crc32 only wants its source operand checked here. */
8072 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8075 /* Any other register is bad. */
8076 as_bad (_("`%s%s' not allowed with `%s%c'"),
8077 register_prefix
, i
.op
[op
].regs
->reg_name
,
8078 insn_name (&i
.tm
), i
.suffix
);
8085 check_long_reg (void)
8089 for (op
= i
.operands
; --op
>= 0;)
8090 /* Skip non-register operands. */
8091 if (i
.types
[op
].bitfield
.class != Reg
)
8093 /* Reject eight bit registers, except where the template requires
8094 them. (eg. movzb) */
8095 else if (i
.types
[op
].bitfield
.byte
8096 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8097 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8098 && (i
.tm
.operand_types
[op
].bitfield
.word
8099 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8101 as_bad (_("`%s%s' not allowed with `%s%c'"),
8103 i
.op
[op
].regs
->reg_name
,
8108 /* Error if the e prefix on a general reg is missing. */
8109 else if (i
.types
[op
].bitfield
.word
8110 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8111 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8112 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8114 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8115 register_prefix
, i
.op
[op
].regs
->reg_name
,
8119 /* Warn if the r prefix on a general reg is present. */
8120 else if (i
.types
[op
].bitfield
.qword
8121 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8122 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8123 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8125 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8126 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8133 check_qword_reg (void)
8137 for (op
= i
.operands
; --op
>= 0; )
8138 /* Skip non-register operands. */
8139 if (i
.types
[op
].bitfield
.class != Reg
)
8141 /* Reject eight bit registers, except where the template requires
8142 them. (eg. movzb) */
8143 else if (i
.types
[op
].bitfield
.byte
8144 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8145 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8146 && (i
.tm
.operand_types
[op
].bitfield
.word
8147 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8149 as_bad (_("`%s%s' not allowed with `%s%c'"),
8151 i
.op
[op
].regs
->reg_name
,
8156 /* Warn if the r prefix on a general reg is missing. */
8157 else if ((i
.types
[op
].bitfield
.word
8158 || i
.types
[op
].bitfield
.dword
)
8159 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8160 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8161 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8163 /* Prohibit these changes in the 64bit mode, since the
8164 lowering is more complicated. */
8165 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8166 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8173 check_word_reg (void)
8176 for (op
= i
.operands
; --op
>= 0;)
8177 /* Skip non-register operands. */
8178 if (i
.types
[op
].bitfield
.class != Reg
)
8180 /* Reject eight bit registers, except where the template requires
8181 them. (eg. movzb) */
8182 else if (i
.types
[op
].bitfield
.byte
8183 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8184 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8185 && (i
.tm
.operand_types
[op
].bitfield
.word
8186 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8188 as_bad (_("`%s%s' not allowed with `%s%c'"),
8190 i
.op
[op
].regs
->reg_name
,
8195 /* Error if the e or r prefix on a general reg is present. */
8196 else if ((i
.types
[op
].bitfield
.dword
8197 || i
.types
[op
].bitfield
.qword
)
8198 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8199 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8200 && i
.tm
.operand_types
[op
].bitfield
.word
)
8202 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8203 register_prefix
, i
.op
[op
].regs
->reg_name
,
8211 update_imm (unsigned int j
)
8213 i386_operand_type overlap
= i
.types
[j
];
8215 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8216 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8217 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8219 /* This combination is used on 8-bit immediates where e.g. $~0 is
8220 desirable to permit. We're past operand type matching, so simply
8221 put things back in the shape they were before introducing the
8222 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8223 overlap
.bitfield
.imm8s
= 0;
8226 if (overlap
.bitfield
.imm8
8227 + overlap
.bitfield
.imm8s
8228 + overlap
.bitfield
.imm16
8229 + overlap
.bitfield
.imm32
8230 + overlap
.bitfield
.imm32s
8231 + overlap
.bitfield
.imm64
> 1)
8233 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8234 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8235 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8236 static const i386_operand_type imm16_32
= { .bitfield
=
8237 { .imm16
= 1, .imm32
= 1 }
8239 static const i386_operand_type imm16_32s
= { .bitfield
=
8240 { .imm16
= 1, .imm32s
= 1 }
8242 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8243 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8248 i386_operand_type temp
;
8250 operand_type_set (&temp
, 0);
8251 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8253 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8254 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8256 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8257 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8258 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8260 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8261 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8264 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8267 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8268 || operand_type_equal (&overlap
, &imm16_32
)
8269 || operand_type_equal (&overlap
, &imm16_32s
))
8271 if ((flag_code
== CODE_16BIT
)
8272 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8277 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8278 overlap
= operand_type_and (overlap
, imm32s
);
8279 else if (i
.prefix
[DATA_PREFIX
])
8280 overlap
= operand_type_and (overlap
,
8281 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8282 if (overlap
.bitfield
.imm8
8283 + overlap
.bitfield
.imm8s
8284 + overlap
.bitfield
.imm16
8285 + overlap
.bitfield
.imm32
8286 + overlap
.bitfield
.imm32s
8287 + overlap
.bitfield
.imm64
!= 1)
8289 as_bad (_("no instruction mnemonic suffix given; "
8290 "can't determine immediate size"));
8294 i
.types
[j
] = overlap
;
8304 /* Update the first 2 immediate operands. */
8305 n
= i
.operands
> 2 ? 2 : i
.operands
;
8308 for (j
= 0; j
< n
; j
++)
8309 if (update_imm (j
) == 0)
8312 /* The 3rd operand can't be immediate operand. */
8313 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8319 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8322 if (r
->reg_flags
& RegRex
)
8324 if (i
.rex
& rex_bit
)
8325 as_bad (_("same type of prefix used twice"));
8328 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8330 gas_assert (i
.vex
.register_specifier
== r
);
8331 i
.vex
.register_specifier
+= 8;
8334 if (r
->reg_flags
& RegVRex
)
8339 process_operands (void)
8341 /* Default segment register this instruction will use for memory
8342 accesses. 0 means unknown. This is only for optimizing out
8343 unnecessary segment overrides. */
8344 const reg_entry
*default_seg
= NULL
;
8346 /* We only need to check those implicit registers for instructions
8347 with 3 operands or less. */
8348 if (i
.operands
<= 3)
8349 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8350 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8353 if (i
.tm
.opcode_modifier
.sse2avx
)
8355 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8357 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8358 i
.prefix
[REX_PREFIX
] = 0;
8361 /* ImmExt should be processed after SSE2AVX. */
8362 else if (i
.tm
.opcode_modifier
.immext
)
8365 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8366 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8367 new destination operand here, while converting the source one to register
8369 if (i
.tm
.mnem_off
== MN_tilezero
)
8371 i
.op
[1].regs
= i
.op
[0].regs
;
8372 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8373 i
.types
[1] = i
.types
[0];
8374 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8375 i
.flags
[1] = i
.flags
[0];
8381 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8383 static const i386_operand_type regxmm
= {
8384 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8386 unsigned int dupl
= i
.operands
;
8387 unsigned int dest
= dupl
- 1;
8390 /* The destination must be an xmm register. */
8391 gas_assert (i
.reg_operands
8392 && MAX_OPERANDS
> dupl
8393 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8395 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8396 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8398 /* Keep xmm0 for instructions with VEX prefix and 3
8400 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8401 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8406 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8408 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8410 /* Add the implicit xmm0 for instructions with VEX prefix
8412 for (j
= i
.operands
; j
> 0; j
--)
8414 i
.op
[j
] = i
.op
[j
- 1];
8415 i
.types
[j
] = i
.types
[j
- 1];
8416 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8417 i
.flags
[j
] = i
.flags
[j
- 1];
8420 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8421 i
.types
[0] = regxmm
;
8422 i
.tm
.operand_types
[0] = regxmm
;
8425 i
.reg_operands
+= 2;
8430 i
.op
[dupl
] = i
.op
[dest
];
8431 i
.types
[dupl
] = i
.types
[dest
];
8432 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8433 i
.flags
[dupl
] = i
.flags
[dest
];
8442 i
.op
[dupl
] = i
.op
[dest
];
8443 i
.types
[dupl
] = i
.types
[dest
];
8444 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8445 i
.flags
[dupl
] = i
.flags
[dest
];
8448 if (i
.tm
.opcode_modifier
.immext
)
8451 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8452 && i
.tm
.opcode_modifier
.modrm
)
8456 for (j
= 1; j
< i
.operands
; j
++)
8458 i
.op
[j
- 1] = i
.op
[j
];
8459 i
.types
[j
- 1] = i
.types
[j
];
8461 /* We need to adjust fields in i.tm since they are used by
8462 build_modrm_byte. */
8463 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8465 i
.flags
[j
- 1] = i
.flags
[j
];
8468 /* No adjustment to i.reg_operands: This was already done at the top
8473 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8475 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8477 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8478 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8479 regnum
= register_number (i
.op
[1].regs
);
8480 first_reg_in_group
= regnum
& ~3;
8481 last_reg_in_group
= first_reg_in_group
+ 3;
8482 if (regnum
!= first_reg_in_group
)
8483 as_warn (_("source register `%s%s' implicitly denotes"
8484 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8485 register_prefix
, i
.op
[1].regs
->reg_name
,
8486 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8487 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8490 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8492 /* The imul $imm, %reg instruction is converted into
8493 imul $imm, %reg, %reg, and the clr %reg instruction
8494 is converted into xor %reg, %reg. */
8496 unsigned int first_reg_op
;
8498 if (operand_type_check (i
.types
[0], reg
))
8502 /* Pretend we saw the extra register operand. */
8503 gas_assert (i
.reg_operands
== 1
8504 && i
.op
[first_reg_op
+ 1].regs
== 0);
8505 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8506 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8511 if (i
.tm
.opcode_modifier
.modrm
)
8513 /* The opcode is completed (modulo i.tm.extension_opcode which
8514 must be put into the modrm byte). Now, we make the modrm and
8515 index base bytes based on all the info we've collected. */
8517 default_seg
= build_modrm_byte ();
8519 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8521 /* Warn about some common errors, but press on regardless. */
8522 if (i
.operands
== 2)
8524 /* Reversed arguments on faddp or fmulp. */
8525 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8526 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8527 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8529 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8531 /* Extraneous `l' suffix on fp insn. */
8532 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8533 register_prefix
, i
.op
[0].regs
->reg_name
);
8537 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8539 if (flag_code
!= CODE_64BIT
8540 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8541 && i
.op
[0].regs
->reg_num
== 1
8542 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8543 && i
.op
[0].regs
->reg_num
< 4)
8545 as_bad (_("you can't `%s %s%s'"),
8546 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8549 if (i
.op
[0].regs
->reg_num
> 3
8550 && i
.tm
.opcode_space
== SPACE_BASE
)
8552 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8553 i
.tm
.opcode_space
= SPACE_0F
;
8555 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8557 else if (i
.tm
.opcode_space
== SPACE_BASE
8558 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8560 default_seg
= reg_ds
;
8562 else if (i
.tm
.opcode_modifier
.isstring
)
8564 /* For the string instructions that allow a segment override
8565 on one of their operands, the default segment is ds. */
8566 default_seg
= reg_ds
;
8568 else if (i
.short_form
)
8570 /* The register operand is in the 1st or 2nd non-immediate operand. */
8571 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8574 && r
->reg_type
.bitfield
.instance
== Accum
8575 && i
.op
[i
.imm_operands
+ 1].regs
)
8576 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8577 /* Register goes in low 3 bits of opcode. */
8578 i
.tm
.base_opcode
|= r
->reg_num
;
8579 set_rex_vrex (r
, REX_B
, false);
8581 if (dot_insn () && i
.reg_operands
== 2)
8583 gas_assert (is_any_vex_encoding (&i
.tm
)
8584 || i
.vec_encoding
!= vex_encoding_default
);
8585 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8588 else if (i
.reg_operands
== 1
8589 && !i
.flags
[i
.operands
- 1]
8590 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8593 gas_assert (is_any_vex_encoding (&i
.tm
)
8594 || i
.vec_encoding
!= vex_encoding_default
);
8595 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8598 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8599 && i
.tm
.mnem_off
== MN_lea
)
8601 if (!quiet_warnings
)
8602 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8603 if (optimize
&& !i
.no_optimize
)
8606 i
.prefix
[SEG_PREFIX
] = 0;
8610 /* If a segment was explicitly specified, and the specified segment
8611 is neither the default nor the one already recorded from a prefix,
8612 use an opcode prefix to select it. If we never figured out what
8613 the default segment is, then default_seg will be zero at this
8614 point, and the specified segment prefix will always be used. */
8616 && i
.seg
[0] != default_seg
8617 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8619 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8625 static const reg_entry
*
8626 build_modrm_byte (void)
8628 const reg_entry
*default_seg
= NULL
;
8629 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8630 /* Compensate for kludge in md_assemble(). */
8631 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8632 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8633 unsigned int v
, op
, reg_slot
= ~0;
8635 /* Accumulator (in particular %st), shift count (%cl), and alike need
8636 to be skipped just like immediate operands do. */
8637 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8639 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8642 for (op
= source
; op
< i
.operands
; ++op
)
8643 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8646 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8650 /* There are 2 kinds of instructions:
8651 1. 5 operands: 4 register operands or 3 register operands
8652 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8653 VexW0 or VexW1. The destination must be either XMM, YMM or
8655 2. 4 operands: 4 register operands or 3 register operands
8656 plus 1 memory operand, with VexXDS.
8657 3. Other equivalent combinations when coming from s_insn(). */
8658 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8659 && i
.tm
.opcode_modifier
.vexw
);
8660 gas_assert (dot_insn ()
8661 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8663 /* Of the first two non-immediate operands the one with the template
8664 not allowing for a memory one is encoded in the immediate operand. */
8666 reg_slot
= source
+ 1;
8668 reg_slot
= source
++;
8672 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8673 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8676 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8678 if (i
.imm_operands
== 0)
8680 /* When there is no immediate operand, generate an 8bit
8681 immediate operand to encode the first operand. */
8682 exp
= &im_expressions
[i
.imm_operands
++];
8683 i
.op
[i
.operands
].imms
= exp
;
8684 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8687 exp
->X_op
= O_constant
;
8691 gas_assert (i
.imm_operands
== 1);
8692 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8693 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8695 /* Turn on Imm8 again so that output_imm will generate it. */
8696 i
.types
[0].bitfield
.imm8
= 1;
8700 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8701 << (3 + !(is_evex_encoding (&i
.tm
)
8702 || i
.vec_encoding
== vex_encoding_evex
));
8705 for (v
= source
+ 1; v
< dest
; ++v
)
8710 if (i
.tm
.extension_opcode
!= None
)
8716 gas_assert (source
< dest
);
8717 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8720 unsigned int tmp
= source
;
8726 if (v
< MAX_OPERANDS
)
8728 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8729 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8732 if (op
< i
.operands
)
8736 unsigned int fake_zero_displacement
= 0;
8738 gas_assert (i
.flags
[op
] & Operand_Mem
);
8740 if (i
.tm
.opcode_modifier
.sib
)
8742 /* The index register of VSIB shouldn't be RegIZ. */
8743 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8744 && i
.index_reg
->reg_num
== RegIZ
)
8747 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8750 i
.sib
.base
= NO_BASE_REGISTER
;
8751 i
.sib
.scale
= i
.log2_scale_factor
;
8752 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8753 i
.types
[op
].bitfield
.disp32
= 1;
8756 /* Since the mandatory SIB always has index register, so
8757 the code logic remains unchanged. The non-mandatory SIB
8758 without index register is allowed and will be handled
8762 if (i
.index_reg
->reg_num
== RegIZ
)
8763 i
.sib
.index
= NO_INDEX_REGISTER
;
8765 i
.sib
.index
= i
.index_reg
->reg_num
;
8766 set_rex_vrex (i
.index_reg
, REX_X
, false);
8770 default_seg
= reg_ds
;
8772 if (i
.base_reg
== 0)
8775 if (!i
.disp_operands
)
8776 fake_zero_displacement
= 1;
8777 if (i
.index_reg
== 0)
8779 /* Both check for VSIB and mandatory non-vector SIB. */
8780 gas_assert (!i
.tm
.opcode_modifier
.sib
8781 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8782 /* Operand is just <disp> */
8783 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8784 if (flag_code
== CODE_64BIT
)
8786 /* 64bit mode overwrites the 32bit absolute
8787 addressing by RIP relative addressing and
8788 absolute addressing is encoded by one of the
8789 redundant SIB forms. */
8790 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8791 i
.sib
.base
= NO_BASE_REGISTER
;
8792 i
.sib
.index
= NO_INDEX_REGISTER
;
8793 i
.types
[op
].bitfield
.disp32
= 1;
8795 else if ((flag_code
== CODE_16BIT
)
8796 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8798 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8799 i
.types
[op
].bitfield
.disp16
= 1;
8803 i
.rm
.regmem
= NO_BASE_REGISTER
;
8804 i
.types
[op
].bitfield
.disp32
= 1;
8807 else if (!i
.tm
.opcode_modifier
.sib
)
8809 /* !i.base_reg && i.index_reg */
8810 if (i
.index_reg
->reg_num
== RegIZ
)
8811 i
.sib
.index
= NO_INDEX_REGISTER
;
8813 i
.sib
.index
= i
.index_reg
->reg_num
;
8814 i
.sib
.base
= NO_BASE_REGISTER
;
8815 i
.sib
.scale
= i
.log2_scale_factor
;
8816 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8817 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8818 i
.types
[op
].bitfield
.disp32
= 1;
8819 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8823 /* RIP addressing for 64bit mode. */
8824 else if (i
.base_reg
->reg_num
== RegIP
)
8826 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8827 i
.rm
.regmem
= NO_BASE_REGISTER
;
8828 i
.types
[op
].bitfield
.disp8
= 0;
8829 i
.types
[op
].bitfield
.disp16
= 0;
8830 i
.types
[op
].bitfield
.disp32
= 1;
8831 i
.types
[op
].bitfield
.disp64
= 0;
8832 i
.flags
[op
] |= Operand_PCrel
;
8833 if (! i
.disp_operands
)
8834 fake_zero_displacement
= 1;
8836 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8838 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8839 switch (i
.base_reg
->reg_num
)
8842 if (i
.index_reg
== 0)
8844 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8845 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8848 default_seg
= reg_ss
;
8849 if (i
.index_reg
== 0)
8852 if (operand_type_check (i
.types
[op
], disp
) == 0)
8854 /* fake (%bp) into 0(%bp) */
8855 if (i
.disp_encoding
== disp_encoding_16bit
)
8856 i
.types
[op
].bitfield
.disp16
= 1;
8858 i
.types
[op
].bitfield
.disp8
= 1;
8859 fake_zero_displacement
= 1;
8862 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8863 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8865 default: /* (%si) -> 4 or (%di) -> 5 */
8866 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8868 if (!fake_zero_displacement
8872 fake_zero_displacement
= 1;
8873 if (i
.disp_encoding
== disp_encoding_8bit
)
8874 i
.types
[op
].bitfield
.disp8
= 1;
8876 i
.types
[op
].bitfield
.disp16
= 1;
8878 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8880 else /* i.base_reg and 32/64 bit mode */
8882 if (operand_type_check (i
.types
[op
], disp
))
8884 i
.types
[op
].bitfield
.disp16
= 0;
8885 i
.types
[op
].bitfield
.disp64
= 0;
8886 i
.types
[op
].bitfield
.disp32
= 1;
8889 if (!i
.tm
.opcode_modifier
.sib
)
8890 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8891 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8893 i
.sib
.base
= i
.base_reg
->reg_num
;
8894 /* x86-64 ignores REX prefix bit here to avoid decoder
8896 if (!(i
.base_reg
->reg_flags
& RegRex
)
8897 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8898 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8899 default_seg
= reg_ss
;
8900 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8902 fake_zero_displacement
= 1;
8903 if (i
.disp_encoding
== disp_encoding_32bit
)
8904 i
.types
[op
].bitfield
.disp32
= 1;
8906 i
.types
[op
].bitfield
.disp8
= 1;
8908 i
.sib
.scale
= i
.log2_scale_factor
;
8909 if (i
.index_reg
== 0)
8911 /* Only check for VSIB. */
8912 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8913 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8914 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8916 /* <disp>(%esp) becomes two byte modrm with no index
8917 register. We've already stored the code for esp
8918 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8919 Any base register besides %esp will not use the
8920 extra modrm byte. */
8921 i
.sib
.index
= NO_INDEX_REGISTER
;
8923 else if (!i
.tm
.opcode_modifier
.sib
)
8925 if (i
.index_reg
->reg_num
== RegIZ
)
8926 i
.sib
.index
= NO_INDEX_REGISTER
;
8928 i
.sib
.index
= i
.index_reg
->reg_num
;
8929 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8930 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8935 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8936 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8940 if (!fake_zero_displacement
8944 fake_zero_displacement
= 1;
8945 if (i
.disp_encoding
== disp_encoding_8bit
)
8946 i
.types
[op
].bitfield
.disp8
= 1;
8948 i
.types
[op
].bitfield
.disp32
= 1;
8950 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8954 if (fake_zero_displacement
)
8956 /* Fakes a zero displacement assuming that i.types[op]
8957 holds the correct displacement size. */
8960 gas_assert (i
.op
[op
].disps
== 0);
8961 exp
= &disp_expressions
[i
.disp_operands
++];
8962 i
.op
[op
].disps
= exp
;
8963 exp
->X_op
= O_constant
;
8964 exp
->X_add_number
= 0;
8965 exp
->X_add_symbol
= (symbolS
*) 0;
8966 exp
->X_op_symbol
= (symbolS
*) 0;
8972 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8973 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8984 if (!i
.tm
.opcode_modifier
.regmem
)
8986 gas_assert (source
< MAX_OPERANDS
);
8987 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8988 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8989 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8994 gas_assert (dest
< MAX_OPERANDS
);
8995 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8996 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9001 /* Fill in i.rm.reg field with extension opcode (if any) or the
9002 appropriate register. */
9003 if (i
.tm
.extension_opcode
!= None
)
9004 i
.rm
.reg
= i
.tm
.extension_opcode
;
9005 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9007 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9008 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9012 gas_assert (source
< MAX_OPERANDS
);
9013 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9014 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9017 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9019 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9021 add_prefix (LOCK_PREFIX_OPCODE
);
9028 frag_opcode_byte (unsigned char byte
)
9030 if (now_seg
!= absolute_section
)
9031 FRAG_APPEND_1_CHAR (byte
);
9033 ++abs_section_offset
;
9037 flip_code16 (unsigned int code16
)
9039 gas_assert (i
.tm
.operands
== 1);
9041 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9042 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9043 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9048 output_branch (void)
9054 relax_substateT subtype
;
9058 if (now_seg
== absolute_section
)
9060 as_bad (_("relaxable branches not supported in absolute section"));
9064 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9065 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9068 if (i
.prefix
[DATA_PREFIX
] != 0)
9072 code16
^= flip_code16(code16
);
9074 /* Pentium4 branch hints. */
9075 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9076 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9081 if (i
.prefix
[REX_PREFIX
] != 0)
9087 /* BND prefixed jump. */
9088 if (i
.prefix
[BND_PREFIX
] != 0)
9094 if (i
.prefixes
!= 0)
9095 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9097 /* It's always a symbol; End frag & setup for relax.
9098 Make sure there is enough room in this frag for the largest
9099 instruction we may generate in md_convert_frag. This is 2
9100 bytes for the opcode and room for the prefix and largest
9102 frag_grow (prefix
+ 2 + 4);
9103 /* Prefix and 1 opcode byte go in fr_fix. */
9104 p
= frag_more (prefix
+ 1);
9105 if (i
.prefix
[DATA_PREFIX
] != 0)
9106 *p
++ = DATA_PREFIX_OPCODE
;
9107 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9108 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9109 *p
++ = i
.prefix
[SEG_PREFIX
];
9110 if (i
.prefix
[BND_PREFIX
] != 0)
9111 *p
++ = BND_PREFIX_OPCODE
;
9112 if (i
.prefix
[REX_PREFIX
] != 0)
9113 *p
++ = i
.prefix
[REX_PREFIX
];
9114 *p
= i
.tm
.base_opcode
;
9116 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9117 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9118 else if (cpu_arch_flags
.bitfield
.cpui386
)
9119 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9121 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9124 sym
= i
.op
[0].disps
->X_add_symbol
;
9125 off
= i
.op
[0].disps
->X_add_number
;
9127 if (i
.op
[0].disps
->X_op
!= O_constant
9128 && i
.op
[0].disps
->X_op
!= O_symbol
)
9130 /* Handle complex expressions. */
9131 sym
= make_expr_symbol (i
.op
[0].disps
);
9135 /* 1 possible extra opcode + 4 byte displacement go in var part.
9136 Pass reloc in fr_var. */
9137 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9141 /* Return TRUE iff PLT32 relocation should be used for branching to
9145 need_plt32_p (symbolS
*s
)
9147 /* PLT32 relocation is ELF only. */
9152 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9153 krtld support it. */
9157 /* Since there is no need to prepare for PLT branch on x86-64, we
9158 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9159 be used as a marker for 32-bit PC-relative branches. */
9166 /* Weak or undefined symbol need PLT32 relocation. */
9167 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9170 /* Non-global symbol doesn't need PLT32 relocation. */
9171 if (! S_IS_EXTERNAL (s
))
9174 /* Other global symbols need PLT32 relocation. NB: Symbol with
9175 non-default visibilities are treated as normal global symbol
9176 so that PLT32 relocation can be used as a marker for 32-bit
9177 PC-relative branches. It is useful for linker relaxation. */
9188 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9190 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9192 /* This is a loop or jecxz type instruction. */
9194 if (i
.prefix
[ADDR_PREFIX
] != 0)
9196 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9199 /* Pentium4 branch hints. */
9200 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9201 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9203 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9212 if (flag_code
== CODE_16BIT
)
9215 if (i
.prefix
[DATA_PREFIX
] != 0)
9217 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9219 code16
^= flip_code16(code16
);
9227 /* BND prefixed jump. */
9228 if (i
.prefix
[BND_PREFIX
] != 0)
9230 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9234 if (i
.prefix
[REX_PREFIX
] != 0)
9236 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9240 if (i
.prefixes
!= 0)
9241 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9243 if (now_seg
== absolute_section
)
9245 abs_section_offset
+= i
.opcode_length
+ size
;
9249 p
= frag_more (i
.opcode_length
+ size
);
9250 switch (i
.opcode_length
)
9253 *p
++ = i
.tm
.base_opcode
>> 8;
9256 *p
++ = i
.tm
.base_opcode
;
9262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9263 if (flag_code
== CODE_64BIT
&& size
== 4
9264 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9265 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9266 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9269 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9271 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9272 i
.op
[0].disps
, 1, jump_reloc
);
9274 /* All jumps handled here are signed, but don't unconditionally use a
9275 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9276 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9281 fixP
->fx_signed
= 1;
9285 if (i
.tm
.mnem_off
== MN_xbegin
)
9286 fixP
->fx_signed
= 1;
9290 if (flag_code
== CODE_64BIT
)
9291 fixP
->fx_signed
= 1;
9297 output_interseg_jump (void)
9305 if (flag_code
== CODE_16BIT
)
9309 if (i
.prefix
[DATA_PREFIX
] != 0)
9316 gas_assert (!i
.prefix
[REX_PREFIX
]);
9322 if (i
.prefixes
!= 0)
9323 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9325 if (now_seg
== absolute_section
)
9327 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9331 /* 1 opcode; 2 segment; offset */
9332 p
= frag_more (prefix
+ 1 + 2 + size
);
9334 if (i
.prefix
[DATA_PREFIX
] != 0)
9335 *p
++ = DATA_PREFIX_OPCODE
;
9337 if (i
.prefix
[REX_PREFIX
] != 0)
9338 *p
++ = i
.prefix
[REX_PREFIX
];
9340 *p
++ = i
.tm
.base_opcode
;
9341 if (i
.op
[1].imms
->X_op
== O_constant
)
9343 offsetT n
= i
.op
[1].imms
->X_add_number
;
9346 && !fits_in_unsigned_word (n
)
9347 && !fits_in_signed_word (n
))
9349 as_bad (_("16-bit jump out of range"));
9352 md_number_to_chars (p
, n
, size
);
9355 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9356 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9359 if (i
.op
[0].imms
->X_op
== O_constant
)
9360 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9362 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9363 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9371 asection
*seg
= now_seg
;
9372 subsegT subseg
= now_subseg
;
9374 unsigned int alignment
, align_size_1
;
9375 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9376 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9377 unsigned int padding
;
9379 if (!IS_ELF
|| !x86_used_note
)
9382 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9384 /* The .note.gnu.property section layout:
9386 Field Length Contents
9389 n_descsz 4 The note descriptor size
9390 n_type 4 NT_GNU_PROPERTY_TYPE_0
9392 n_desc n_descsz The program property array
9396 /* Create the .note.gnu.property section. */
9397 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9398 bfd_set_section_flags (sec
,
9405 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9416 bfd_set_section_alignment (sec
, alignment
);
9417 elf_section_type (sec
) = SHT_NOTE
;
9419 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9421 isa_1_descsz_raw
= 4 + 4 + 4;
9422 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9423 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9425 feature_2_descsz_raw
= isa_1_descsz
;
9426 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9428 feature_2_descsz_raw
+= 4 + 4 + 4;
9429 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9430 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9433 descsz
= feature_2_descsz
;
9434 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9435 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9437 /* Write n_namsz. */
9438 md_number_to_chars (p
, (valueT
) 4, 4);
9440 /* Write n_descsz. */
9441 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9444 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9447 memcpy (p
+ 4 * 3, "GNU", 4);
9449 /* Write 4-byte type. */
9450 md_number_to_chars (p
+ 4 * 4,
9451 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9453 /* Write 4-byte data size. */
9454 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9456 /* Write 4-byte data. */
9457 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9459 /* Zero out paddings. */
9460 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9462 memset (p
+ 4 * 7, 0, padding
);
9464 /* Write 4-byte type. */
9465 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9466 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9468 /* Write 4-byte data size. */
9469 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9471 /* Write 4-byte data. */
9472 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9473 (valueT
) x86_feature_2_used
, 4);
9475 /* Zero out paddings. */
9476 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9478 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9480 /* We probably can't restore the current segment, for there likely
9483 subseg_set (seg
, subseg
);
9487 x86_support_sframe_p (void)
9489 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9490 return (x86_elf_abi
== X86_64_ABI
);
9494 x86_sframe_ra_tracking_p (void)
9496 /* In AMD64, return address is always stored on the stack at a fixed offset
9497 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9498 Do not track explicitly via an SFrame Frame Row Entry. */
9503 x86_sframe_cfa_ra_offset (void)
9505 gas_assert (x86_elf_abi
== X86_64_ABI
);
9506 return (offsetT
) -8;
9510 x86_sframe_get_abi_arch (void)
9512 unsigned char sframe_abi_arch
= 0;
9514 if (x86_support_sframe_p ())
9516 gas_assert (!target_big_endian
);
9517 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9520 return sframe_abi_arch
;
9526 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9527 const char *frag_now_ptr
)
9529 unsigned int len
= 0;
9531 if (start_frag
!= frag_now
)
9533 const fragS
*fr
= start_frag
;
9538 } while (fr
&& fr
!= frag_now
);
9541 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9544 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9545 be macro-fused with conditional jumps.
9546 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9547 or is one of the following format:
9560 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9562 /* No RIP address. */
9563 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9566 /* No opcodes outside of base encoding space. */
9567 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9570 /* add, sub without add/sub m, imm. */
9571 if (i
.tm
.base_opcode
<= 5
9572 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9573 || ((i
.tm
.base_opcode
| 3) == 0x83
9574 && (i
.tm
.extension_opcode
== 0x5
9575 || i
.tm
.extension_opcode
== 0x0)))
9577 *mf_cmp_p
= mf_cmp_alu_cmp
;
9578 return !(i
.mem_operands
&& i
.imm_operands
);
9581 /* and without and m, imm. */
9582 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9583 || ((i
.tm
.base_opcode
| 3) == 0x83
9584 && i
.tm
.extension_opcode
== 0x4))
9586 *mf_cmp_p
= mf_cmp_test_and
;
9587 return !(i
.mem_operands
&& i
.imm_operands
);
9590 /* test without test m imm. */
9591 if ((i
.tm
.base_opcode
| 1) == 0x85
9592 || (i
.tm
.base_opcode
| 1) == 0xa9
9593 || ((i
.tm
.base_opcode
| 1) == 0xf7
9594 && i
.tm
.extension_opcode
== 0))
9596 *mf_cmp_p
= mf_cmp_test_and
;
9597 return !(i
.mem_operands
&& i
.imm_operands
);
9600 /* cmp without cmp m, imm. */
9601 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9602 || ((i
.tm
.base_opcode
| 3) == 0x83
9603 && (i
.tm
.extension_opcode
== 0x7)))
9605 *mf_cmp_p
= mf_cmp_alu_cmp
;
9606 return !(i
.mem_operands
&& i
.imm_operands
);
9609 /* inc, dec without inc/dec m. */
9610 if ((is_cpu (&i
.tm
, CpuNo64
)
9611 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9612 || ((i
.tm
.base_opcode
| 1) == 0xff
9613 && i
.tm
.extension_opcode
<= 0x1))
9615 *mf_cmp_p
= mf_cmp_incdec
;
9616 return !i
.mem_operands
;
9622 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9625 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9627 /* NB: Don't work with COND_JUMP86 without i386. */
9628 if (!align_branch_power
9629 || now_seg
== absolute_section
9630 || !cpu_arch_flags
.bitfield
.cpui386
9631 || !(align_branch
& align_branch_fused_bit
))
9634 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9636 if (last_insn
.kind
== last_insn_other
9637 || last_insn
.seg
!= now_seg
)
9640 as_warn_where (last_insn
.file
, last_insn
.line
,
9641 _("`%s` skips -malign-branch-boundary on `%s`"),
9642 last_insn
.name
, insn_name (&i
.tm
));
9648 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9651 add_branch_prefix_frag_p (void)
9653 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9654 to PadLock instructions since they include prefixes in opcode. */
9655 if (!align_branch_power
9656 || !align_branch_prefix_size
9657 || now_seg
== absolute_section
9658 || is_cpu (&i
.tm
, CpuPadLock
)
9659 || !cpu_arch_flags
.bitfield
.cpui386
)
9662 /* Don't add prefix if it is a prefix or there is no operand in case
9663 that segment prefix is special. */
9664 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9667 if (last_insn
.kind
== last_insn_other
9668 || last_insn
.seg
!= now_seg
)
9672 as_warn_where (last_insn
.file
, last_insn
.line
,
9673 _("`%s` skips -malign-branch-boundary on `%s`"),
9674 last_insn
.name
, insn_name (&i
.tm
));
9679 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9682 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9683 enum mf_jcc_kind
*mf_jcc_p
)
9687 /* NB: Don't work with COND_JUMP86 without i386. */
9688 if (!align_branch_power
9689 || now_seg
== absolute_section
9690 || !cpu_arch_flags
.bitfield
.cpui386
9691 || i
.tm
.opcode_space
!= SPACE_BASE
)
9696 /* Check for jcc and direct jmp. */
9697 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9699 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9701 *branch_p
= align_branch_jmp
;
9702 add_padding
= align_branch
& align_branch_jmp_bit
;
9706 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9707 igore the lowest bit. */
9708 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9709 *branch_p
= align_branch_jcc
;
9710 if ((align_branch
& align_branch_jcc_bit
))
9714 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9717 *branch_p
= align_branch_ret
;
9718 if ((align_branch
& align_branch_ret_bit
))
9723 /* Check for indirect jmp, direct and indirect calls. */
9724 if (i
.tm
.base_opcode
== 0xe8)
9727 *branch_p
= align_branch_call
;
9728 if ((align_branch
& align_branch_call_bit
))
9731 else if (i
.tm
.base_opcode
== 0xff
9732 && (i
.tm
.extension_opcode
== 2
9733 || i
.tm
.extension_opcode
== 4))
9735 /* Indirect call and jmp. */
9736 *branch_p
= align_branch_indirect
;
9737 if ((align_branch
& align_branch_indirect_bit
))
9744 && (i
.op
[0].disps
->X_op
== O_symbol
9745 || (i
.op
[0].disps
->X_op
== O_subtract
9746 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9748 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9749 /* No padding to call to global or undefined tls_get_addr. */
9750 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9751 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9757 && last_insn
.kind
!= last_insn_other
9758 && last_insn
.seg
== now_seg
)
9761 as_warn_where (last_insn
.file
, last_insn
.line
,
9762 _("`%s` skips -malign-branch-boundary on `%s`"),
9763 last_insn
.name
, insn_name (&i
.tm
));
9773 fragS
*insn_start_frag
;
9774 offsetT insn_start_off
;
9775 fragS
*fragP
= NULL
;
9776 enum align_branch_kind branch
= align_branch_none
;
9777 /* The initializer is arbitrary just to avoid uninitialized error.
9778 it's actually either assigned in add_branch_padding_frag_p
9779 or never be used. */
9780 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9783 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9785 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9786 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9787 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9789 if (is_cpu (&i
.tm
, Cpu8087
)
9790 || is_cpu (&i
.tm
, Cpu287
)
9791 || is_cpu (&i
.tm
, Cpu387
)
9792 || is_cpu (&i
.tm
, Cpu687
)
9793 || is_cpu (&i
.tm
, CpuFISTTP
))
9794 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9796 if ((i
.xstate
& xstate_mmx
)
9797 || i
.tm
.mnem_off
== MN_emms
9798 || i
.tm
.mnem_off
== MN_femms
)
9799 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9803 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9804 i
.xstate
|= xstate_zmm
;
9805 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9806 i
.xstate
|= xstate_ymm
;
9807 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9808 i
.xstate
|= xstate_xmm
;
9811 /* vzeroall / vzeroupper */
9812 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9813 i
.xstate
|= xstate_ymm
;
9815 if ((i
.xstate
& xstate_xmm
)
9816 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9817 || (i
.tm
.base_opcode
== 0xae
9818 && (is_cpu (&i
.tm
, CpuSSE
)
9819 || is_cpu (&i
.tm
, CpuAVX
)))
9820 || is_cpu (&i
.tm
, CpuWideKL
)
9821 || is_cpu (&i
.tm
, CpuKL
))
9822 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9824 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9825 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9826 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9827 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9828 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9829 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9830 if (is_cpu (&i
.tm
, CpuFXSR
))
9831 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9832 if (is_cpu (&i
.tm
, CpuXsave
))
9833 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9834 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9835 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9836 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9837 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9839 if (x86_feature_2_used
9840 || is_cpu (&i
.tm
, CpuCMOV
)
9841 || is_cpu (&i
.tm
, CpuSYSCALL
)
9842 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9843 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9844 if (is_cpu (&i
.tm
, CpuSSE3
)
9845 || is_cpu (&i
.tm
, CpuSSSE3
)
9846 || is_cpu (&i
.tm
, CpuSSE4_1
)
9847 || is_cpu (&i
.tm
, CpuSSE4_2
)
9848 || is_cpu (&i
.tm
, CpuCX16
)
9849 || is_cpu (&i
.tm
, CpuPOPCNT
)
9850 /* LAHF-SAHF insns in 64-bit mode. */
9851 || (flag_code
== CODE_64BIT
9852 && (i
.tm
.base_opcode
| 1) == 0x9f
9853 && i
.tm
.opcode_space
== SPACE_BASE
))
9854 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9855 if (is_cpu (&i
.tm
, CpuAVX
)
9856 || is_cpu (&i
.tm
, CpuAVX2
)
9857 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9858 XOP, FMA4, LPW, TBM, and AMX. */
9859 || (i
.tm
.opcode_modifier
.vex
9860 && !is_cpu (&i
.tm
, CpuAVX512F
)
9861 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9862 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9863 && !is_cpu (&i
.tm
, CpuXOP
)
9864 && !is_cpu (&i
.tm
, CpuFMA4
)
9865 && !is_cpu (&i
.tm
, CpuLWP
)
9866 && !is_cpu (&i
.tm
, CpuTBM
)
9867 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9868 || is_cpu (&i
.tm
, CpuF16C
)
9869 || is_cpu (&i
.tm
, CpuFMA
)
9870 || is_cpu (&i
.tm
, CpuLZCNT
)
9871 || is_cpu (&i
.tm
, CpuMovbe
)
9872 || is_cpu (&i
.tm
, CpuXSAVES
)
9873 || (x86_feature_2_used
9874 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9875 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9876 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9877 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9878 if (is_cpu (&i
.tm
, CpuAVX512F
)
9879 || is_cpu (&i
.tm
, CpuAVX512BW
)
9880 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9881 || is_cpu (&i
.tm
, CpuAVX512VL
)
9882 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9883 AVX512-4FMAPS, and AVX512-4VNNIW. */
9884 || (i
.tm
.opcode_modifier
.evex
9885 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9886 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9887 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9888 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9889 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9893 /* Tie dwarf2 debug info to the address at the start of the insn.
9894 We can't do this after the insn has been output as the current
9895 frag may have been closed off. eg. by frag_var. */
9896 dwarf2_emit_insn (0);
9898 insn_start_frag
= frag_now
;
9899 insn_start_off
= frag_now_fix ();
9901 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9904 /* Branch can be 8 bytes. Leave some room for prefixes. */
9905 unsigned int max_branch_padding_size
= 14;
9907 /* Align section to boundary. */
9908 record_alignment (now_seg
, align_branch_power
);
9910 /* Make room for padding. */
9911 frag_grow (max_branch_padding_size
);
9913 /* Start of the padding. */
9918 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9919 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9922 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9923 fragP
->tc_frag_data
.branch_type
= branch
;
9924 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9927 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9928 && !pre_386_16bit_warned
)
9930 as_warn (_("use .code16 to ensure correct addressing mode"));
9931 pre_386_16bit_warned
= true;
9935 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9937 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9938 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9940 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9941 output_interseg_jump ();
9944 /* Output normal instructions here. */
9948 enum mf_cmp_kind mf_cmp
;
9951 && (i
.tm
.base_opcode
== 0xaee8
9952 || i
.tm
.base_opcode
== 0xaef0
9953 || i
.tm
.base_opcode
== 0xaef8))
9955 /* Encode lfence, mfence, and sfence as
9956 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9957 if (flag_code
== CODE_16BIT
)
9958 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9959 else if (omit_lock_prefix
)
9960 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9962 else if (now_seg
!= absolute_section
)
9964 offsetT val
= 0x240483f0ULL
;
9967 md_number_to_chars (p
, val
, 5);
9970 abs_section_offset
+= 5;
9974 /* Some processors fail on LOCK prefix. This options makes
9975 assembler ignore LOCK prefix and serves as a workaround. */
9976 if (omit_lock_prefix
)
9978 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9979 && i
.tm
.opcode_modifier
.isprefix
)
9981 i
.prefix
[LOCK_PREFIX
] = 0;
9985 /* Skip if this is a branch. */
9987 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9989 /* Make room for padding. */
9990 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9995 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9996 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9999 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10000 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10001 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10003 else if (add_branch_prefix_frag_p ())
10005 unsigned int max_prefix_size
= align_branch_prefix_size
;
10007 /* Make room for padding. */
10008 frag_grow (max_prefix_size
);
10013 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10014 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10017 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10020 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10021 don't need the explicit prefix. */
10022 if (!is_any_vex_encoding (&i
.tm
))
10024 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10033 if (!is_cpu (&i
.tm
, CpuPadLock
)
10034 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10038 switch (i
.opcode_length
)
10043 /* Check for pseudo prefixes. */
10044 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10046 as_bad_where (insn_start_frag
->fr_file
,
10047 insn_start_frag
->fr_line
,
10048 _("pseudo prefix without instruction"));
10058 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10059 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10060 R_X86_64_GOTTPOFF relocation so that linker can safely
10061 perform IE->LE optimization. A dummy REX_OPCODE prefix
10062 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10063 relocation for GDesc -> IE/LE optimization. */
10064 if (x86_elf_abi
== X86_64_X32_ABI
10066 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10067 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10068 && i
.prefix
[REX_PREFIX
] == 0)
10069 add_prefix (REX_OPCODE
);
10072 /* The prefix bytes. */
10073 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10075 frag_opcode_byte (*q
);
10079 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10085 frag_opcode_byte (*q
);
10088 /* There should be no other prefixes for instructions
10089 with VEX prefix. */
10093 /* For EVEX instructions i.vrex should become 0 after
10094 build_evex_prefix. For VEX instructions upper 16 registers
10095 aren't available, so VREX should be 0. */
10098 /* Now the VEX prefix. */
10099 if (now_seg
!= absolute_section
)
10101 p
= frag_more (i
.vex
.length
);
10102 for (j
= 0; j
< i
.vex
.length
; j
++)
10103 p
[j
] = i
.vex
.bytes
[j
];
10106 abs_section_offset
+= i
.vex
.length
;
10109 /* Now the opcode; be careful about word order here! */
10110 j
= i
.opcode_length
;
10112 switch (i
.tm
.opcode_space
)
10127 if (now_seg
== absolute_section
)
10128 abs_section_offset
+= j
;
10131 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10137 && i
.tm
.opcode_space
!= SPACE_BASE
)
10140 if (i
.tm
.opcode_space
!= SPACE_0F
)
10141 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10145 switch (i
.opcode_length
)
10148 /* Put out high byte first: can't use md_number_to_chars! */
10149 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10150 /* Fall through. */
10152 *p
= i
.tm
.base_opcode
& 0xff;
10161 /* Now the modrm byte and sib byte (if present). */
10162 if (i
.tm
.opcode_modifier
.modrm
)
10164 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10166 | (i
.rm
.mode
<< 6));
10167 /* If i.rm.regmem == ESP (4)
10168 && i.rm.mode != (Register mode)
10170 ==> need second modrm byte. */
10171 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10173 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10174 frag_opcode_byte ((i
.sib
.base
<< 0)
10175 | (i
.sib
.index
<< 3)
10176 | (i
.sib
.scale
<< 6));
10179 if (i
.disp_operands
)
10180 output_disp (insn_start_frag
, insn_start_off
);
10182 if (i
.imm_operands
)
10183 output_imm (insn_start_frag
, insn_start_off
);
10186 * frag_now_fix () returning plain abs_section_offset when we're in the
10187 * absolute section, and abs_section_offset not getting updated as data
10188 * gets added to the frag breaks the logic below.
10190 if (now_seg
!= absolute_section
)
10192 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10194 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10198 /* NB: Don't add prefix with GOTPC relocation since
10199 output_disp() above depends on the fixed encoding
10200 length. Can't add prefix with TLS relocation since
10201 it breaks TLS linker optimization. */
10202 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10203 /* Prefix count on the current instruction. */
10204 unsigned int count
= i
.vex
.length
;
10206 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10207 /* REX byte is encoded in VEX/EVEX prefix. */
10208 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10211 /* Count prefixes for extended opcode maps. */
10213 switch (i
.tm
.opcode_space
)
10228 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10231 /* Set the maximum prefix size in BRANCH_PREFIX
10233 if (fragP
->tc_frag_data
.max_bytes
> max
)
10234 fragP
->tc_frag_data
.max_bytes
= max
;
10235 if (fragP
->tc_frag_data
.max_bytes
> count
)
10236 fragP
->tc_frag_data
.max_bytes
-= count
;
10238 fragP
->tc_frag_data
.max_bytes
= 0;
10242 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10244 unsigned int max_prefix_size
;
10245 if (align_branch_prefix_size
> max
)
10246 max_prefix_size
= max
;
10248 max_prefix_size
= align_branch_prefix_size
;
10249 if (max_prefix_size
> count
)
10250 fragP
->tc_frag_data
.max_prefix_length
10251 = max_prefix_size
- count
;
10254 /* Use existing segment prefix if possible. Use CS
10255 segment prefix in 64-bit mode. In 32-bit mode, use SS
10256 segment prefix with ESP/EBP base register and use DS
10257 segment prefix without ESP/EBP base register. */
10258 if (i
.prefix
[SEG_PREFIX
])
10259 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10260 else if (flag_code
== CODE_64BIT
)
10261 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10262 else if (i
.base_reg
10263 && (i
.base_reg
->reg_num
== 4
10264 || i
.base_reg
->reg_num
== 5))
10265 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10267 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10272 /* NB: Don't work with COND_JUMP86 without i386. */
10273 if (align_branch_power
10274 && now_seg
!= absolute_section
10275 && cpu_arch_flags
.bitfield
.cpui386
)
10277 /* Terminate each frag so that we can add prefix and check for
10279 frag_wane (frag_now
);
10286 pi ("" /*line*/, &i
);
10288 #endif /* DEBUG386 */
10291 /* Return the size of the displacement operand N. */
10294 disp_size (unsigned int n
)
10298 if (i
.types
[n
].bitfield
.disp64
)
10300 else if (i
.types
[n
].bitfield
.disp8
)
10302 else if (i
.types
[n
].bitfield
.disp16
)
10307 /* Return the size of the immediate operand N. */
10310 imm_size (unsigned int n
)
10313 if (i
.types
[n
].bitfield
.imm64
)
10315 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10317 else if (i
.types
[n
].bitfield
.imm16
)
10323 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10328 for (n
= 0; n
< i
.operands
; n
++)
10330 if (operand_type_check (i
.types
[n
], disp
))
10332 int size
= disp_size (n
);
10334 if (now_seg
== absolute_section
)
10335 abs_section_offset
+= size
;
10336 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10338 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10340 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10342 p
= frag_more (size
);
10343 md_number_to_chars (p
, val
, size
);
10347 enum bfd_reloc_code_real reloc_type
;
10348 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10349 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10350 && (!want_disp32 (&i
.tm
)
10351 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10352 && !i
.types
[n
].bitfield
.baseindex
)))
10356 /* We can't have 8 bit displacement here. */
10357 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10359 /* The PC relative address is computed relative
10360 to the instruction boundary, so in case immediate
10361 fields follows, we need to adjust the value. */
10362 if (pcrel
&& i
.imm_operands
)
10367 for (n1
= 0; n1
< i
.operands
; n1
++)
10368 if (operand_type_check (i
.types
[n1
], imm
))
10370 /* Only one immediate is allowed for PC
10371 relative address, except with .insn. */
10372 gas_assert (sz
== 0 || dot_insn ());
10373 sz
+= imm_size (n1
);
10375 /* We should find at least one immediate. */
10376 gas_assert (sz
!= 0);
10377 i
.op
[n
].disps
->X_add_number
-= sz
;
10380 p
= frag_more (size
);
10381 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10383 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10384 && (((reloc_type
== BFD_RELOC_32
10385 || reloc_type
== BFD_RELOC_X86_64_32S
10386 || (reloc_type
== BFD_RELOC_64
10388 && (i
.op
[n
].disps
->X_op
== O_symbol
10389 || (i
.op
[n
].disps
->X_op
== O_add
10390 && ((symbol_get_value_expression
10391 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10393 || reloc_type
== BFD_RELOC_32_PCREL
))
10397 reloc_type
= BFD_RELOC_386_GOTPC
;
10398 i
.has_gotpc_tls_reloc
= true;
10399 i
.op
[n
].disps
->X_add_number
+=
10400 encoding_length (insn_start_frag
, insn_start_off
, p
);
10402 else if (reloc_type
== BFD_RELOC_64
)
10403 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10405 /* Don't do the adjustment for x86-64, as there
10406 the pcrel addressing is relative to the _next_
10407 insn, and that is taken care of in other code. */
10408 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10410 else if (align_branch_power
)
10412 switch (reloc_type
)
10414 case BFD_RELOC_386_TLS_GD
:
10415 case BFD_RELOC_386_TLS_LDM
:
10416 case BFD_RELOC_386_TLS_IE
:
10417 case BFD_RELOC_386_TLS_IE_32
:
10418 case BFD_RELOC_386_TLS_GOTIE
:
10419 case BFD_RELOC_386_TLS_GOTDESC
:
10420 case BFD_RELOC_386_TLS_DESC_CALL
:
10421 case BFD_RELOC_X86_64_TLSGD
:
10422 case BFD_RELOC_X86_64_TLSLD
:
10423 case BFD_RELOC_X86_64_GOTTPOFF
:
10424 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10425 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10426 i
.has_gotpc_tls_reloc
= true;
10431 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10432 size
, i
.op
[n
].disps
, pcrel
,
10435 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10436 && !i
.prefix
[ADDR_PREFIX
])
10437 fixP
->fx_signed
= 1;
10439 /* Check for "call/jmp *mem", "mov mem, %reg",
10440 "test %reg, mem" and "binop mem, %reg" where binop
10441 is one of adc, add, and, cmp, or, sbb, sub, xor
10442 instructions without data prefix. Always generate
10443 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10444 if (i
.prefix
[DATA_PREFIX
] == 0
10445 && (generate_relax_relocations
10448 && i
.rm
.regmem
== 5))
10450 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10451 && i
.tm
.opcode_space
== SPACE_BASE
10452 && ((i
.operands
== 1
10453 && i
.tm
.base_opcode
== 0xff
10454 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10455 || (i
.operands
== 2
10456 && (i
.tm
.base_opcode
== 0x8b
10457 || i
.tm
.base_opcode
== 0x85
10458 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10462 fixP
->fx_tcbit
= i
.rex
!= 0;
10464 && (i
.base_reg
->reg_num
== RegIP
))
10465 fixP
->fx_tcbit2
= 1;
10468 fixP
->fx_tcbit2
= 1;
10476 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10481 for (n
= 0; n
< i
.operands
; n
++)
10483 if (operand_type_check (i
.types
[n
], imm
))
10485 int size
= imm_size (n
);
10487 if (now_seg
== absolute_section
)
10488 abs_section_offset
+= size
;
10489 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10493 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10495 p
= frag_more (size
);
10496 md_number_to_chars (p
, val
, size
);
10500 /* Not absolute_section.
10501 Need a 32-bit fixup (don't support 8bit
10502 non-absolute imms). Try to support other
10504 enum bfd_reloc_code_real reloc_type
;
10507 if (i
.types
[n
].bitfield
.imm32s
10508 && (i
.suffix
== QWORD_MNEM_SUFFIX
10509 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10510 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10516 p
= frag_more (size
);
10517 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10519 /* This is tough to explain. We end up with this one if we
10520 * have operands that look like
10521 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10522 * obtain the absolute address of the GOT, and it is strongly
10523 * preferable from a performance point of view to avoid using
10524 * a runtime relocation for this. The actual sequence of
10525 * instructions often look something like:
10530 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10532 * The call and pop essentially return the absolute address
10533 * of the label .L66 and store it in %ebx. The linker itself
10534 * will ultimately change the first operand of the addl so
10535 * that %ebx points to the GOT, but to keep things simple, the
10536 * .o file must have this operand set so that it generates not
10537 * the absolute address of .L66, but the absolute address of
10538 * itself. This allows the linker itself simply treat a GOTPC
10539 * relocation as asking for a pcrel offset to the GOT to be
10540 * added in, and the addend of the relocation is stored in the
10541 * operand field for the instruction itself.
10543 * Our job here is to fix the operand so that it would add
10544 * the correct offset so that %ebx would point to itself. The
10545 * thing that is tricky is that .-.L66 will point to the
10546 * beginning of the instruction, so we need to further modify
10547 * the operand so that it will point to itself. There are
10548 * other cases where you have something like:
10550 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10552 * and here no correction would be required. Internally in
10553 * the assembler we treat operands of this form as not being
10554 * pcrel since the '.' is explicitly mentioned, and I wonder
10555 * whether it would simplify matters to do it this way. Who
10556 * knows. In earlier versions of the PIC patches, the
10557 * pcrel_adjust field was used to store the correction, but
10558 * since the expression is not pcrel, I felt it would be
10559 * confusing to do it this way. */
10561 if ((reloc_type
== BFD_RELOC_32
10562 || reloc_type
== BFD_RELOC_X86_64_32S
10563 || reloc_type
== BFD_RELOC_64
)
10565 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10566 && (i
.op
[n
].imms
->X_op
== O_symbol
10567 || (i
.op
[n
].imms
->X_op
== O_add
10568 && ((symbol_get_value_expression
10569 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10573 reloc_type
= BFD_RELOC_386_GOTPC
;
10574 else if (size
== 4)
10575 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10576 else if (size
== 8)
10577 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10578 i
.has_gotpc_tls_reloc
= true;
10579 i
.op
[n
].imms
->X_add_number
+=
10580 encoding_length (insn_start_frag
, insn_start_off
, p
);
10582 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10583 i
.op
[n
].imms
, 0, reloc_type
);
10589 /* x86_cons_fix_new is called via the expression parsing code when a
10590 reloc is needed. We use this hook to get the correct .got reloc. */
10591 static int cons_sign
= -1;
10594 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10595 expressionS
*exp
, bfd_reloc_code_real_type r
)
10597 r
= reloc (len
, 0, cons_sign
, r
);
10600 if (exp
->X_op
== O_secrel
)
10602 exp
->X_op
= O_symbol
;
10603 r
= BFD_RELOC_32_SECREL
;
10605 else if (exp
->X_op
== O_secidx
)
10606 r
= BFD_RELOC_16_SECIDX
;
10609 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10612 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10613 purpose of the `.dc.a' internal pseudo-op. */
10616 x86_address_bytes (void)
10618 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10620 return stdoutput
->arch_info
->bits_per_address
/ 8;
10623 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10624 || defined (LEX_AT)) && !defined (TE_PE)
10625 # define lex_got(reloc, adjust, types) NULL
10627 /* Parse operands of the form
10628 <symbol>@GOTOFF+<nnn>
10629 and similar .plt or .got references.
10631 If we find one, set up the correct relocation in RELOC and copy the
10632 input string, minus the `@GOTOFF' into a malloc'd buffer for
10633 parsing by the calling routine. Return this buffer, and if ADJUST
10634 is non-null set it to the length of the string we removed from the
10635 input line. Otherwise return NULL. */
10637 lex_got (enum bfd_reloc_code_real
*rel
,
10639 i386_operand_type
*types
)
10641 /* Some of the relocations depend on the size of what field is to
10642 be relocated. But in our callers i386_immediate and i386_displacement
10643 we don't yet know the operand size (this will be set by insn
10644 matching). Hence we record the word32 relocation here,
10645 and adjust the reloc according to the real size in reloc(). */
10646 static const struct
10650 const enum bfd_reloc_code_real rel
[2];
10651 const i386_operand_type types64
;
10652 bool need_GOT_symbol
;
10657 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10658 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10659 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10660 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10661 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10662 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10663 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10664 { .imm64 = 1, .disp64 = 1 } }
10667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10668 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10669 BFD_RELOC_SIZE32
},
10670 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10672 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10673 BFD_RELOC_X86_64_PLTOFF64
},
10674 { .bitfield
= { .imm64
= 1 } }, true },
10675 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10676 BFD_RELOC_X86_64_PLT32
},
10677 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10678 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10679 BFD_RELOC_X86_64_GOTPLT64
},
10680 OPERAND_TYPE_IMM64_DISP64
, true },
10681 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10682 BFD_RELOC_X86_64_GOTOFF64
},
10683 OPERAND_TYPE_IMM64_DISP64
, true },
10684 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10685 BFD_RELOC_X86_64_GOTPCREL
},
10686 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10687 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10688 BFD_RELOC_X86_64_TLSGD
},
10689 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10690 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10691 _dummy_first_bfd_reloc_code_real
},
10692 OPERAND_TYPE_NONE
, true },
10693 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10694 BFD_RELOC_X86_64_TLSLD
},
10695 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10696 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10697 BFD_RELOC_X86_64_GOTTPOFF
},
10698 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10699 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10700 BFD_RELOC_X86_64_TPOFF32
},
10701 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10702 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10703 _dummy_first_bfd_reloc_code_real
},
10704 OPERAND_TYPE_NONE
, true },
10705 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10706 BFD_RELOC_X86_64_DTPOFF32
},
10707 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10708 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10709 _dummy_first_bfd_reloc_code_real
},
10710 OPERAND_TYPE_NONE
, true },
10711 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10712 _dummy_first_bfd_reloc_code_real
},
10713 OPERAND_TYPE_NONE
, true },
10714 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10715 BFD_RELOC_X86_64_GOT32
},
10716 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10717 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10718 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10719 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10720 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10721 BFD_RELOC_X86_64_TLSDESC_CALL
},
10722 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10724 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10725 BFD_RELOC_32_SECREL
},
10726 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10729 #undef OPERAND_TYPE_IMM32_32S_DISP32
10730 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10731 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10732 #undef OPERAND_TYPE_IMM64_DISP64
10738 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10743 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10744 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10747 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10749 int len
= gotrel
[j
].len
;
10750 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10752 if (gotrel
[j
].rel
[object_64bit
] != 0)
10755 char *tmpbuf
, *past_reloc
;
10757 *rel
= gotrel
[j
].rel
[object_64bit
];
10761 if (flag_code
!= CODE_64BIT
)
10763 types
->bitfield
.imm32
= 1;
10764 types
->bitfield
.disp32
= 1;
10767 *types
= gotrel
[j
].types64
;
10770 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10771 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10773 /* The length of the first part of our input line. */
10774 first
= cp
- input_line_pointer
;
10776 /* The second part goes from after the reloc token until
10777 (and including) an end_of_line char or comma. */
10778 past_reloc
= cp
+ 1 + len
;
10780 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10782 second
= cp
+ 1 - past_reloc
;
10784 /* Allocate and copy string. The trailing NUL shouldn't
10785 be necessary, but be safe. */
10786 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10787 memcpy (tmpbuf
, input_line_pointer
, first
);
10788 if (second
!= 0 && *past_reloc
!= ' ')
10789 /* Replace the relocation token with ' ', so that
10790 errors like foo@GOTOFF1 will be detected. */
10791 tmpbuf
[first
++] = ' ';
10793 /* Increment length by 1 if the relocation token is
10798 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10799 tmpbuf
[first
+ second
] = '\0';
10803 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10804 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10809 /* Might be a symbol version string. Don't as_bad here. */
10814 bfd_reloc_code_real_type
10815 x86_cons (expressionS
*exp
, int size
)
10817 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10819 intel_syntax
= -intel_syntax
;
10821 expr_mode
= expr_operator_none
;
10823 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10824 && !defined (LEX_AT)) \
10826 if (size
== 4 || (object_64bit
&& size
== 8))
10828 /* Handle @GOTOFF and the like in an expression. */
10830 char *gotfree_input_line
;
10833 save
= input_line_pointer
;
10834 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10835 if (gotfree_input_line
)
10836 input_line_pointer
= gotfree_input_line
;
10840 if (gotfree_input_line
)
10842 /* expression () has merrily parsed up to the end of line,
10843 or a comma - in the wrong buffer. Transfer how far
10844 input_line_pointer has moved to the right buffer. */
10845 input_line_pointer
= (save
10846 + (input_line_pointer
- gotfree_input_line
)
10848 free (gotfree_input_line
);
10849 if (exp
->X_op
== O_constant
10850 || exp
->X_op
== O_absent
10851 || exp
->X_op
== O_illegal
10852 || exp
->X_op
== O_register
10853 || exp
->X_op
== O_big
)
10855 char c
= *input_line_pointer
;
10856 *input_line_pointer
= 0;
10857 as_bad (_("missing or invalid expression `%s'"), save
);
10858 *input_line_pointer
= c
;
10860 else if ((got_reloc
== BFD_RELOC_386_PLT32
10861 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10862 && exp
->X_op
!= O_symbol
)
10864 char c
= *input_line_pointer
;
10865 *input_line_pointer
= 0;
10866 as_bad (_("invalid PLT expression `%s'"), save
);
10867 *input_line_pointer
= c
;
10875 intel_syntax
= -intel_syntax
;
10878 i386_intel_simplify (exp
);
10880 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10881 if (size
<= 4 && expr_mode
== expr_operator_present
10882 && exp
->X_op
== O_constant
&& !object_64bit
)
10883 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10889 signed_cons (int size
)
10898 s_insn (int dummy ATTRIBUTE_UNUSED
)
10900 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10901 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10905 bool vex
= false, xop
= false, evex
= false;
10906 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10910 saved_char
= *saved_ilp
;
10913 end
= parse_insn (line
, mnemonic
, true);
10917 *saved_ilp
= saved_char
;
10918 ignore_rest_of_line ();
10922 line
+= end
- line
;
10924 current_templates
= &tt
;
10925 i
.tm
.mnem_off
= MN__insn
;
10926 i
.tm
.extension_opcode
= None
;
10928 if (startswith (line
, "VEX")
10929 && (line
[3] == '.' || is_space_char (line
[3])))
10934 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10937 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10939 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10940 && (*e
== '.' || is_space_char (*e
)))
10943 /* Arrange for build_vex_prefix() to emit 0x8f. */
10944 i
.tm
.opcode_space
= SPACE_XOP08
;
10945 i
.insn_opcode_space
= n
;
10949 else if (startswith (line
, "EVEX")
10950 && (line
[4] == '.' || is_space_char (line
[4])))
10957 ? i
.vec_encoding
== vex_encoding_evex
10959 ? i
.vec_encoding
== vex_encoding_vex
10960 || i
.vec_encoding
== vex_encoding_vex3
10961 : i
.vec_encoding
!= vex_encoding_default
)
10963 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10967 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10968 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10970 if (i
.vec_encoding
!= vex_encoding_default
)
10972 /* Only address size and segment override prefixes are permitted with
10973 VEX/XOP/EVEX encodings. */
10974 const unsigned char *p
= i
.prefix
;
10976 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10987 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
10993 if (line
> end
&& *line
== '.')
10995 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11003 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11005 i
.tm
.opcode_modifier
.vex
= VEX128
;
11010 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11012 i
.tm
.opcode_modifier
.vex
= VEX256
;
11017 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11022 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11026 if (line
[3] == 'G')
11029 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11031 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11037 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11042 if (line
[2] == '2' && line
[3] == '8')
11045 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11047 i
.tm
.opcode_modifier
.vex
= VEX128
;
11053 if (line
[2] == '5' && line
[3] == '6')
11056 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11058 i
.tm
.opcode_modifier
.vex
= VEX256
;
11064 if (evex
&& line
[2] == '1' && line
[3] == '2')
11066 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11073 if (line
> end
&& *line
== '.')
11075 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11079 if (line
[2] == 'P')
11084 if (line
[2] == '6')
11086 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11091 case 'F': case 'f':
11092 if (line
[2] == '3')
11094 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11097 else if (line
[2] == '2')
11099 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11106 if (line
> end
&& !xop
&& *line
== '.')
11108 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11112 if (TOUPPER (line
[2]) != 'F')
11114 if (line
[3] == '.' || is_space_char (line
[3]))
11116 i
.insn_opcode_space
= SPACE_0F
;
11119 else if (line
[3] == '3'
11120 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11121 && (line
[5] == '.' || is_space_char (line
[5])))
11123 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11129 if (ISDIGIT (line
[2]) && line
[2] != '0')
11132 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11134 if (n
<= (evex
? 15 : 31)
11135 && (*e
== '.' || is_space_char (*e
)))
11137 i
.insn_opcode_space
= n
;
11145 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11147 /* VEX.W, XOP.W, EVEX.W */
11151 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11155 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11159 if (line
[3] == 'G')
11161 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11167 if (i
.tm
.opcode_modifier
.vexw
)
11171 if (line
> end
&& *line
&& !is_space_char (*line
))
11173 /* Improve diagnostic a little. */
11174 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11179 /* Before processing the opcode expression, find trailing "+r" or
11180 "/<digit>" specifiers. */
11181 for (ptr
= line
; ; ++ptr
)
11186 ptr
= strpbrk (ptr
, "+/,");
11187 if (ptr
== NULL
|| *ptr
== ',')
11190 if (*ptr
== '+' && ptr
[1] == 'r'
11191 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11195 i
.short_form
= true;
11199 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11200 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11202 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11206 i
.tm
.extension_opcode
= n
;
11207 i
.tm
.opcode_modifier
.modrm
= 1;
11212 input_line_pointer
= line
;
11213 val
= get_absolute_expression ();
11214 line
= input_line_pointer
;
11216 if (i
.short_form
&& (val
& 7))
11217 as_warn ("`+r' assumes low three opcode bits to be clear");
11219 for (j
= 1; j
< sizeof(val
); ++j
)
11220 if (!(val
>> (j
* 8)))
11223 /* Trim off a prefix if present. */
11224 if (j
> 1 && !vex
&& !xop
&& !evex
)
11226 uint8_t byte
= val
>> ((j
- 1) * 8);
11230 case DATA_PREFIX_OPCODE
:
11231 case REPE_PREFIX_OPCODE
:
11232 case REPNE_PREFIX_OPCODE
:
11233 if (!add_prefix (byte
))
11235 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11240 /* Trim off encoding space. */
11241 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11243 uint8_t byte
= val
>> ((--j
- 1) * 8);
11245 i
.insn_opcode_space
= SPACE_0F
;
11246 switch (byte
& -(j
> 1))
11249 i
.insn_opcode_space
= SPACE_0F38
;
11253 i
.insn_opcode_space
= SPACE_0F3A
;
11257 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11258 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11260 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11261 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11262 Also avoid hitting abort() there or in build_evex_prefix(). */
11263 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11268 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11271 i
.opcode_length
= j
;
11273 /* Handle operands, if any. */
11276 i386_operand_type combined
;
11277 expressionS
*disp_exp
= NULL
;
11282 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11290 as_bad (_("expecting operand after ','; got nothing"));
11294 if (i
.mem_operands
> 1)
11296 as_bad (_("too many memory references for `%s'"),
11297 &i386_mnemonics
[MN__insn
]);
11301 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11302 if (i
.vec_encoding
== vex_encoding_evex512
)
11303 i
.vec_encoding
= vex_encoding_evex
;
11305 /* Are we to emit ModR/M encoding? */
11308 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11309 || i
.tm
.extension_opcode
!= None
))
11310 i
.tm
.opcode_modifier
.modrm
= 1;
11312 if (!i
.tm
.opcode_modifier
.modrm
11314 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11315 || i
.mem_operands
))
11317 as_bad (_("too many register/memory operands"));
11321 /* Enforce certain constraints on operands. */
11322 switch (i
.reg_operands
+ i
.mem_operands
11323 + (i
.tm
.extension_opcode
!= None
))
11328 as_bad (_("too few register/memory operands"));
11331 /* Fall through. */
11333 if (i
.tm
.opcode_modifier
.modrm
)
11335 as_bad (_("too few register/memory operands"));
11345 && (i
.op
[0].imms
->X_op
!= O_constant
11346 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11348 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11351 /* Fall through. */
11353 if (i
.vec_encoding
!= vex_encoding_default
)
11355 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11358 /* Fall through. */
11360 as_bad (_("too many register/memory operands"));
11364 /* Bring operands into canonical order (imm, mem, reg). */
11369 for (j
= 1; j
< i
.operands
; ++j
)
11371 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11372 && operand_type_check (i
.types
[j
], imm
))
11373 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11374 && i
.types
[j
].bitfield
.class == ClassNone
))
11376 swap_2_operands (j
- 1, j
);
11383 /* For Intel syntax swap the order of register operands. */
11385 switch (i
.reg_operands
)
11392 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11393 /* Fall through. */
11396 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11403 /* Enforce constraints when using VSIB. */
11405 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11406 || i
.index_reg
->reg_type
.bitfield
.ymmword
11407 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11409 if (i
.vec_encoding
== vex_encoding_default
)
11411 as_bad (_("VSIB unavailable with legacy encoding"));
11415 if (i
.vec_encoding
== vex_encoding_evex
11416 && i
.reg_operands
> 1)
11418 /* We could allow two register operands, encoding the 2nd one in
11419 an 8-bit immediate like for 4-register-operand insns, but that
11420 would require ugly fiddling with process_operands() and/or
11421 build_modrm_byte(). */
11422 as_bad (_("too many register operands with VSIB"));
11426 i
.tm
.opcode_modifier
.sib
= 1;
11429 /* Establish operand size encoding. */
11430 operand_type_set (&combined
, 0);
11432 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11434 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11436 if (operand_type_check (i
.types
[j
], disp
))
11438 i
.types
[j
].bitfield
.baseindex
= 1;
11439 disp_exp
= i
.op
[j
].disps
;
11442 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11444 unsigned int n
= i
.memshift
;
11446 if (i
.types
[j
].bitfield
.byte
)
11448 else if (i
.types
[j
].bitfield
.word
)
11450 else if (i
.types
[j
].bitfield
.dword
)
11452 else if (i
.types
[j
].bitfield
.qword
)
11454 else if (i
.types
[j
].bitfield
.xmmword
)
11456 else if (i
.types
[j
].bitfield
.ymmword
)
11458 else if (i
.types
[j
].bitfield
.zmmword
)
11461 if (i
.memshift
< 32 && n
!= i
.memshift
)
11462 as_warn ("conflicting memory operand size specifiers");
11466 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11467 && j
== i
.broadcast
.operand
)
11470 combined
= operand_type_or (combined
, i
.types
[j
]);
11471 combined
.bitfield
.class = ClassNone
;
11474 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11475 << (i
.memshift
< 32 ? i
.memshift
: 0))
11477 case 64: combined
.bitfield
.zmmword
= 1; break;
11478 case 32: combined
.bitfield
.ymmword
= 1; break;
11479 case 16: combined
.bitfield
.xmmword
= 1; break;
11480 case 8: combined
.bitfield
.qword
= 1; break;
11481 case 4: combined
.bitfield
.dword
= 1; break;
11484 if (i
.vec_encoding
== vex_encoding_default
)
11486 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11488 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11489 : combined
.bitfield
.word
)
11490 && !add_prefix (DATA_PREFIX_OPCODE
))
11493 else if (!i
.tm
.opcode_modifier
.vexw
)
11495 if (flag_code
== CODE_64BIT
)
11497 if (combined
.bitfield
.qword
)
11498 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11499 else if (combined
.bitfield
.dword
)
11500 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11503 if (!i
.tm
.opcode_modifier
.vexw
)
11504 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11509 if (!i
.tm
.opcode_modifier
.vex
)
11511 if (combined
.bitfield
.ymmword
)
11512 i
.tm
.opcode_modifier
.vex
= VEX256
;
11513 else if (combined
.bitfield
.xmmword
)
11514 i
.tm
.opcode_modifier
.vex
= VEX128
;
11519 if (!i
.tm
.opcode_modifier
.evex
)
11521 /* Do _not_ consider AVX512VL here. */
11522 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11523 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11524 else if (combined
.bitfield
.ymmword
)
11525 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11526 else if (combined
.bitfield
.xmmword
)
11527 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11530 if (i
.memshift
>= 32)
11532 unsigned int n
= 0;
11534 switch (i
.tm
.opcode_modifier
.evex
)
11536 case EVEX512
: n
= 64; break;
11537 case EVEX256
: n
= 32; break;
11538 case EVEX128
: n
= 16; break;
11541 if (i
.broadcast
.type
)
11542 n
/= i
.broadcast
.type
;
11545 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11547 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11548 && disp_exp
->X_add_number
!= 0
11549 && i
.disp_encoding
!= disp_encoding_32bit
)
11551 if (!quiet_warnings
)
11552 as_warn ("cannot determine memory operand size");
11553 i
.disp_encoding
= disp_encoding_32bit
;
11558 if (i
.memshift
>= 32)
11561 i
.vec_encoding
= vex_encoding_error
;
11563 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11566 /* Establish size for immediate operands. */
11567 for (j
= 0; j
< i
.imm_operands
; ++j
)
11569 expressionS
*expP
= i
.op
[j
].imms
;
11571 gas_assert (operand_type_check (i
.types
[j
], imm
));
11572 operand_type_set (&i
.types
[j
], 0);
11574 if (i
.imm_bits
[j
] > 32)
11575 i
.types
[j
].bitfield
.imm64
= 1;
11576 else if (i
.imm_bits
[j
] > 16)
11578 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11579 i
.types
[j
].bitfield
.imm32s
= 1;
11581 i
.types
[j
].bitfield
.imm32
= 1;
11583 else if (i
.imm_bits
[j
] > 8)
11584 i
.types
[j
].bitfield
.imm16
= 1;
11585 else if (i
.imm_bits
[j
] > 0)
11587 if (i
.flags
[j
] & Operand_Signed
)
11588 i
.types
[j
].bitfield
.imm8s
= 1;
11590 i
.types
[j
].bitfield
.imm8
= 1;
11592 else if (expP
->X_op
== O_constant
)
11594 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11595 i
.types
[j
].bitfield
.imm1
= 0;
11596 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11597 zapping since smallest_imm_type() sets it unconditionally. */
11598 if (flag_code
!= CODE_64BIT
)
11600 i
.types
[j
].bitfield
.imm64
= 0;
11601 i
.types
[j
].bitfield
.imm32s
= 0;
11602 i
.types
[j
].bitfield
.imm32
= 1;
11604 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11605 i
.types
[j
].bitfield
.imm64
= 0;
11608 /* Non-constant expressions are sized heuristically. */
11611 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11612 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11613 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11617 for (j
= 0; j
< i
.operands
; ++j
)
11618 i
.tm
.operand_types
[j
] = i
.types
[j
];
11620 process_operands ();
11623 /* Don't set opcode until after processing operands, to avoid any
11624 potential special casing there. */
11625 i
.tm
.base_opcode
|= val
;
11627 if (i
.vec_encoding
== vex_encoding_error
11628 || (i
.vec_encoding
!= vex_encoding_evex
11629 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11630 || i
.rounding
.type
!= rc_none
11632 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11633 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11634 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11636 as_bad (_("conflicting .insn operands"));
11642 if (!i
.tm
.opcode_modifier
.vex
)
11643 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11645 build_vex_prefix (NULL
);
11646 i
.rex
&= REX_OPCODE
;
11650 if (!i
.tm
.opcode_modifier
.evex
)
11651 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11653 build_evex_prefix ();
11654 i
.rex
&= REX_OPCODE
;
11656 else if (i
.rex
!= 0)
11657 add_prefix (REX_OPCODE
| i
.rex
);
11662 *saved_ilp
= saved_char
;
11663 input_line_pointer
= line
;
11665 demand_empty_rest_of_line ();
11667 /* Make sure dot_insn() won't yield "true" anymore. */
11673 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11680 if (exp
.X_op
== O_symbol
)
11681 exp
.X_op
= O_secrel
;
11683 emit_expr (&exp
, 4);
11685 while (*input_line_pointer
++ == ',');
11687 input_line_pointer
--;
11688 demand_empty_rest_of_line ();
11692 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11699 if (exp
.X_op
== O_symbol
)
11700 exp
.X_op
= O_secidx
;
11702 emit_expr (&exp
, 2);
11704 while (*input_line_pointer
++ == ',');
11706 input_line_pointer
--;
11707 demand_empty_rest_of_line ();
11711 /* Handle Rounding Control / SAE specifiers. */
11714 RC_SAE_specifier (const char *pstr
)
11718 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11720 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11722 if (i
.rounding
.type
!= rc_none
)
11724 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11728 if (i
.vec_encoding
== vex_encoding_default
)
11729 i
.vec_encoding
= vex_encoding_evex512
;
11730 else if (i
.vec_encoding
!= vex_encoding_evex
11731 && i
.vec_encoding
!= vex_encoding_evex512
)
11734 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11736 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11743 /* Handle Vector operations. */
11746 check_VecOperations (char *op_string
)
11748 const reg_entry
*mask
;
11755 if (*op_string
== '{')
11759 /* Check broadcasts. */
11760 if (startswith (op_string
, "1to"))
11762 unsigned int bcst_type
;
11764 if (i
.broadcast
.type
)
11765 goto duplicated_vec_op
;
11768 if (*op_string
== '8')
11770 else if (*op_string
== '4')
11772 else if (*op_string
== '2')
11774 else if (*op_string
== '1'
11775 && *(op_string
+1) == '6')
11780 else if (*op_string
== '3'
11781 && *(op_string
+1) == '2')
11788 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11793 if (i
.vec_encoding
== vex_encoding_default
)
11794 i
.vec_encoding
= vex_encoding_evex
;
11795 else if (i
.vec_encoding
!= vex_encoding_evex
11796 && i
.vec_encoding
!= vex_encoding_evex512
)
11797 goto unknown_vec_op
;
11799 i
.broadcast
.type
= bcst_type
;
11800 i
.broadcast
.operand
= this_operand
;
11802 /* For .insn a data size specifier may be appended. */
11803 if (dot_insn () && *op_string
== ':')
11804 goto dot_insn_modifier
;
11806 /* Check .insn special cases. */
11807 else if (dot_insn () && *op_string
== ':')
11810 switch (op_string
[1])
11815 if (i
.memshift
< 32)
11816 goto duplicated_vec_op
;
11818 n
= strtoul (op_string
+ 2, &end_op
, 0);
11820 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11822 if (i
.memshift
< 32 && n
== 1)
11823 op_string
= end_op
;
11826 case 's': case 'u':
11827 /* This isn't really a "vector" operation, but a sign/size
11828 specifier for immediate operands of .insn. Note that AT&T
11829 syntax handles the same in i386_immediate(). */
11833 if (i
.imm_bits
[this_operand
])
11834 goto duplicated_vec_op
;
11836 n
= strtoul (op_string
+ 2, &end_op
, 0);
11837 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11839 i
.imm_bits
[this_operand
] = n
;
11840 if (op_string
[1] == 's')
11841 i
.flags
[this_operand
] |= Operand_Signed
;
11842 op_string
= end_op
;
11847 /* Check masking operation. */
11848 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11850 if (mask
== &bad_reg
)
11853 /* k0 can't be used for write mask. */
11854 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11856 as_bad (_("`%s%s' can't be used for write mask"),
11857 register_prefix
, mask
->reg_name
);
11864 i
.mask
.operand
= this_operand
;
11866 else if (i
.mask
.reg
->reg_num
)
11867 goto duplicated_vec_op
;
11872 /* Only "{z}" is allowed here. No need to check
11873 zeroing mask explicitly. */
11874 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11876 as_bad (_("invalid write mask `%s'"), saved
);
11881 op_string
= end_op
;
11883 /* Check zeroing-flag for masking operation. */
11884 else if (*op_string
== 'z')
11888 i
.mask
.reg
= reg_k0
;
11889 i
.mask
.zeroing
= 1;
11890 i
.mask
.operand
= this_operand
;
11894 if (i
.mask
.zeroing
)
11897 as_bad (_("duplicated `%s'"), saved
);
11901 i
.mask
.zeroing
= 1;
11903 /* Only "{%k}" is allowed here. No need to check mask
11904 register explicitly. */
11905 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11907 as_bad (_("invalid zeroing-masking `%s'"),
11915 else if (intel_syntax
11916 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11917 i
.rounding
.modifier
= true;
11919 goto unknown_vec_op
;
11921 if (*op_string
!= '}')
11923 as_bad (_("missing `}' in `%s'"), saved
);
11928 /* Strip whitespace since the addition of pseudo prefixes
11929 changed how the scrubber treats '{'. */
11930 if (is_space_char (*op_string
))
11936 /* We don't know this one. */
11937 as_bad (_("unknown vector operation: `%s'"), saved
);
11941 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11943 as_bad (_("zeroing-masking only allowed with write mask"));
11951 i386_immediate (char *imm_start
)
11953 char *save_input_line_pointer
;
11954 char *gotfree_input_line
;
11957 i386_operand_type types
;
11959 operand_type_set (&types
, ~0);
11961 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11963 as_bad (_("at most %d immediate operands are allowed"),
11964 MAX_IMMEDIATE_OPERANDS
);
11968 exp
= &im_expressions
[i
.imm_operands
++];
11969 i
.op
[this_operand
].imms
= exp
;
11971 if (is_space_char (*imm_start
))
11974 save_input_line_pointer
= input_line_pointer
;
11975 input_line_pointer
= imm_start
;
11977 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11978 if (gotfree_input_line
)
11979 input_line_pointer
= gotfree_input_line
;
11981 expr_mode
= expr_operator_none
;
11982 exp_seg
= expression (exp
);
11984 /* For .insn immediates there may be a size specifier. */
11985 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11986 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11989 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11991 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11993 i
.imm_bits
[this_operand
] = n
;
11994 if (input_line_pointer
[2] == 's')
11995 i
.flags
[this_operand
] |= Operand_Signed
;
11996 input_line_pointer
= e
+ 1;
12000 SKIP_WHITESPACE ();
12001 if (*input_line_pointer
)
12002 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12004 input_line_pointer
= save_input_line_pointer
;
12005 if (gotfree_input_line
)
12007 free (gotfree_input_line
);
12009 if (exp
->X_op
== O_constant
)
12010 exp
->X_op
= O_illegal
;
12013 if (exp_seg
== reg_section
)
12015 as_bad (_("illegal immediate register operand %s"), imm_start
);
12019 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12023 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12024 i386_operand_type types
, const char *imm_start
)
12026 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12029 as_bad (_("missing or invalid immediate expression `%s'"),
12033 else if (exp
->X_op
== O_constant
)
12035 /* Size it properly later. */
12036 i
.types
[this_operand
].bitfield
.imm64
= 1;
12038 /* If not 64bit, sign/zero extend val, to account for wraparound
12040 if (expr_mode
== expr_operator_present
12041 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12042 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12044 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12045 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12046 && exp_seg
!= absolute_section
12047 && exp_seg
!= text_section
12048 && exp_seg
!= data_section
12049 && exp_seg
!= bss_section
12050 && exp_seg
!= undefined_section
12051 && !bfd_is_com_section (exp_seg
))
12053 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12059 /* This is an address. The size of the address will be
12060 determined later, depending on destination register,
12061 suffix, or the default for the section. */
12062 i
.types
[this_operand
].bitfield
.imm8
= 1;
12063 i
.types
[this_operand
].bitfield
.imm16
= 1;
12064 i
.types
[this_operand
].bitfield
.imm32
= 1;
12065 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12066 i
.types
[this_operand
].bitfield
.imm64
= 1;
12067 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12075 i386_scale (char *scale
)
12078 char *save
= input_line_pointer
;
12080 input_line_pointer
= scale
;
12081 val
= get_absolute_expression ();
12086 i
.log2_scale_factor
= 0;
12089 i
.log2_scale_factor
= 1;
12092 i
.log2_scale_factor
= 2;
12095 i
.log2_scale_factor
= 3;
12099 char sep
= *input_line_pointer
;
12101 *input_line_pointer
= '\0';
12102 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12104 *input_line_pointer
= sep
;
12105 input_line_pointer
= save
;
12109 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12111 as_warn (_("scale factor of %d without an index register"),
12112 1 << i
.log2_scale_factor
);
12113 i
.log2_scale_factor
= 0;
12115 scale
= input_line_pointer
;
12116 input_line_pointer
= save
;
12121 i386_displacement (char *disp_start
, char *disp_end
)
12125 char *save_input_line_pointer
;
12126 char *gotfree_input_line
;
12128 i386_operand_type bigdisp
, types
= anydisp
;
12131 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12133 as_bad (_("at most %d displacement operands are allowed"),
12134 MAX_MEMORY_OPERANDS
);
12138 operand_type_set (&bigdisp
, 0);
12140 || i
.types
[this_operand
].bitfield
.baseindex
12141 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12142 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12144 i386_addressing_mode ();
12145 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12146 if (flag_code
== CODE_64BIT
)
12148 bigdisp
.bitfield
.disp32
= 1;
12150 bigdisp
.bitfield
.disp64
= 1;
12152 else if ((flag_code
== CODE_16BIT
) ^ override
)
12153 bigdisp
.bitfield
.disp16
= 1;
12155 bigdisp
.bitfield
.disp32
= 1;
12159 /* For PC-relative branches, the width of the displacement may be
12160 dependent upon data size, but is never dependent upon address size.
12161 Also make sure to not unintentionally match against a non-PC-relative
12162 branch template. */
12163 static templates aux_templates
;
12164 const insn_template
*t
= current_templates
->start
;
12165 bool has_intel64
= false;
12167 aux_templates
.start
= t
;
12168 while (++t
< current_templates
->end
)
12170 if (t
->opcode_modifier
.jump
12171 != current_templates
->start
->opcode_modifier
.jump
)
12173 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12174 has_intel64
= true;
12176 if (t
< current_templates
->end
)
12178 aux_templates
.end
= t
;
12179 current_templates
= &aux_templates
;
12182 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12183 if (flag_code
== CODE_64BIT
)
12185 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12186 && (!intel64
|| !has_intel64
))
12187 bigdisp
.bitfield
.disp16
= 1;
12189 bigdisp
.bitfield
.disp32
= 1;
12194 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12196 : LONG_MNEM_SUFFIX
));
12197 bigdisp
.bitfield
.disp32
= 1;
12198 if ((flag_code
== CODE_16BIT
) ^ override
)
12200 bigdisp
.bitfield
.disp32
= 0;
12201 bigdisp
.bitfield
.disp16
= 1;
12205 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12208 exp
= &disp_expressions
[i
.disp_operands
];
12209 i
.op
[this_operand
].disps
= exp
;
12211 save_input_line_pointer
= input_line_pointer
;
12212 input_line_pointer
= disp_start
;
12213 END_STRING_AND_SAVE (disp_end
);
12215 #ifndef GCC_ASM_O_HACK
12216 #define GCC_ASM_O_HACK 0
12219 END_STRING_AND_SAVE (disp_end
+ 1);
12220 if (i
.types
[this_operand
].bitfield
.baseIndex
12221 && displacement_string_end
[-1] == '+')
12223 /* This hack is to avoid a warning when using the "o"
12224 constraint within gcc asm statements.
12227 #define _set_tssldt_desc(n,addr,limit,type) \
12228 __asm__ __volatile__ ( \
12229 "movw %w2,%0\n\t" \
12230 "movw %w1,2+%0\n\t" \
12231 "rorl $16,%1\n\t" \
12232 "movb %b1,4+%0\n\t" \
12233 "movb %4,5+%0\n\t" \
12234 "movb $0,6+%0\n\t" \
12235 "movb %h1,7+%0\n\t" \
12237 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12239 This works great except that the output assembler ends
12240 up looking a bit weird if it turns out that there is
12241 no offset. You end up producing code that looks like:
12254 So here we provide the missing zero. */
12256 *displacement_string_end
= '0';
12259 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12260 if (gotfree_input_line
)
12261 input_line_pointer
= gotfree_input_line
;
12263 expr_mode
= expr_operator_none
;
12264 exp_seg
= expression (exp
);
12266 SKIP_WHITESPACE ();
12267 if (*input_line_pointer
)
12268 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12270 RESTORE_END_STRING (disp_end
+ 1);
12272 input_line_pointer
= save_input_line_pointer
;
12273 if (gotfree_input_line
)
12275 free (gotfree_input_line
);
12277 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12278 exp
->X_op
= O_illegal
;
12281 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12283 RESTORE_END_STRING (disp_end
);
12289 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12290 i386_operand_type types
, const char *disp_start
)
12294 /* We do this to make sure that the section symbol is in
12295 the symbol table. We will ultimately change the relocation
12296 to be relative to the beginning of the section. */
12297 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12298 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12299 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12301 if (exp
->X_op
!= O_symbol
)
12304 if (S_IS_LOCAL (exp
->X_add_symbol
)
12305 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12306 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12307 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12308 exp
->X_op
= O_subtract
;
12309 exp
->X_op_symbol
= GOT_symbol
;
12310 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12311 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12312 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12313 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12315 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12318 else if (exp
->X_op
== O_absent
12319 || exp
->X_op
== O_illegal
12320 || exp
->X_op
== O_big
)
12323 as_bad (_("missing or invalid displacement expression `%s'"),
12328 else if (exp
->X_op
== O_constant
)
12330 /* Sizing gets taken care of by optimize_disp().
12332 If not 64bit, sign/zero extend val, to account for wraparound
12334 if (expr_mode
== expr_operator_present
12335 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12336 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12339 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12340 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12341 && exp_seg
!= absolute_section
12342 && exp_seg
!= text_section
12343 && exp_seg
!= data_section
12344 && exp_seg
!= bss_section
12345 && exp_seg
!= undefined_section
12346 && !bfd_is_com_section (exp_seg
))
12348 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12353 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12354 i
.types
[this_operand
].bitfield
.disp8
= 1;
12356 /* Check if this is a displacement only operand. */
12357 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12358 i
.types
[this_operand
] =
12359 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12360 operand_type_and (i
.types
[this_operand
], types
));
12365 /* Return the active addressing mode, taking address override and
12366 registers forming the address into consideration. Update the
12367 address override prefix if necessary. */
12369 static enum flag_code
12370 i386_addressing_mode (void)
12372 enum flag_code addr_mode
;
12374 if (i
.prefix
[ADDR_PREFIX
])
12375 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12376 else if (flag_code
== CODE_16BIT
12377 && is_cpu (current_templates
->start
, CpuMPX
)
12378 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12379 from md_assemble() by "is not a valid base/index expression"
12380 when there is a base and/or index. */
12381 && !i
.types
[this_operand
].bitfield
.baseindex
)
12383 /* MPX insn memory operands with neither base nor index must be forced
12384 to use 32-bit addressing in 16-bit mode. */
12385 addr_mode
= CODE_32BIT
;
12386 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12388 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12389 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12393 addr_mode
= flag_code
;
12395 #if INFER_ADDR_PREFIX
12396 if (i
.mem_operands
== 0)
12398 /* Infer address prefix from the first memory operand. */
12399 const reg_entry
*addr_reg
= i
.base_reg
;
12401 if (addr_reg
== NULL
)
12402 addr_reg
= i
.index_reg
;
12406 if (addr_reg
->reg_type
.bitfield
.dword
)
12407 addr_mode
= CODE_32BIT
;
12408 else if (flag_code
!= CODE_64BIT
12409 && addr_reg
->reg_type
.bitfield
.word
)
12410 addr_mode
= CODE_16BIT
;
12412 if (addr_mode
!= flag_code
)
12414 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12416 /* Change the size of any displacement too. At most one
12417 of Disp16 or Disp32 is set.
12418 FIXME. There doesn't seem to be any real need for
12419 separate Disp16 and Disp32 flags. The same goes for
12420 Imm16 and Imm32. Removing them would probably clean
12421 up the code quite a lot. */
12422 if (flag_code
!= CODE_64BIT
12423 && (i
.types
[this_operand
].bitfield
.disp16
12424 || i
.types
[this_operand
].bitfield
.disp32
))
12426 static const i386_operand_type disp16_32
= {
12427 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12430 i
.types
[this_operand
]
12431 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12442 /* Make sure the memory operand we've been dealt is valid.
12443 Return 1 on success, 0 on a failure. */
12446 i386_index_check (const char *operand_string
)
12448 const char *kind
= "base/index";
12449 enum flag_code addr_mode
= i386_addressing_mode ();
12450 const insn_template
*t
= current_templates
->end
- 1;
12452 if (t
->opcode_modifier
.isstring
)
12454 /* Memory operands of string insns are special in that they only allow
12455 a single register (rDI, rSI, or rBX) as their memory address. */
12456 const reg_entry
*expected_reg
;
12457 static const char di_si
[][2][4] =
12463 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12465 kind
= "string address";
12467 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12469 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12472 if (!t
->operand_types
[0].bitfield
.baseindex
12473 || ((!i
.mem_operands
!= !intel_syntax
)
12474 && t
->operand_types
[1].bitfield
.baseindex
))
12477 = (const reg_entry
*) str_hash_find (reg_hash
,
12478 di_si
[addr_mode
][op
== es_op
]);
12482 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12484 if (i
.base_reg
!= expected_reg
12486 || operand_type_check (i
.types
[this_operand
], disp
))
12488 /* The second memory operand must have the same size as
12492 && !((addr_mode
== CODE_64BIT
12493 && i
.base_reg
->reg_type
.bitfield
.qword
)
12494 || (addr_mode
== CODE_32BIT
12495 ? i
.base_reg
->reg_type
.bitfield
.dword
12496 : i
.base_reg
->reg_type
.bitfield
.word
)))
12499 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12501 intel_syntax
? '[' : '(',
12503 expected_reg
->reg_name
,
12504 intel_syntax
? ']' : ')');
12511 as_bad (_("`%s' is not a valid %s expression"),
12512 operand_string
, kind
);
12517 t
= current_templates
->start
;
12519 if (addr_mode
!= CODE_16BIT
)
12521 /* 32-bit/64-bit checks. */
12522 if (i
.disp_encoding
== disp_encoding_16bit
)
12525 as_bad (_("invalid `%s' prefix"),
12526 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12531 && ((addr_mode
== CODE_64BIT
12532 ? !i
.base_reg
->reg_type
.bitfield
.qword
12533 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12534 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12535 || i
.base_reg
->reg_num
== RegIZ
))
12537 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12538 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12539 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12540 && ((addr_mode
== CODE_64BIT
12541 ? !i
.index_reg
->reg_type
.bitfield
.qword
12542 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12543 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12546 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12547 if (t
->mnem_off
== MN_bndmk
12548 || t
->mnem_off
== MN_bndldx
12549 || t
->mnem_off
== MN_bndstx
12550 || t
->opcode_modifier
.sib
== SIBMEM
)
12552 /* They cannot use RIP-relative addressing. */
12553 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12555 as_bad (_("`%s' cannot be used here"), operand_string
);
12559 /* bndldx and bndstx ignore their scale factor. */
12560 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12561 && i
.log2_scale_factor
)
12562 as_warn (_("register scaling is being ignored here"));
12567 /* 16-bit checks. */
12568 if (i
.disp_encoding
== disp_encoding_32bit
)
12572 && (!i
.base_reg
->reg_type
.bitfield
.word
12573 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12575 && (!i
.index_reg
->reg_type
.bitfield
.word
12576 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12578 && i
.base_reg
->reg_num
< 6
12579 && i
.index_reg
->reg_num
>= 6
12580 && i
.log2_scale_factor
== 0))))
12587 /* Handle vector immediates. */
12590 RC_SAE_immediate (const char *imm_start
)
12592 const char *pstr
= imm_start
;
12597 pstr
= RC_SAE_specifier (pstr
+ 1);
12601 if (*pstr
++ != '}')
12603 as_bad (_("Missing '}': '%s'"), imm_start
);
12606 /* RC/SAE immediate string should contain nothing more. */;
12609 as_bad (_("Junk after '}': '%s'"), imm_start
);
12613 /* Internally this doesn't count as an operand. */
12619 static INLINE
bool starts_memory_operand (char c
)
12622 || is_name_beginner (c
)
12623 || strchr ("([\"+-!~", c
);
12626 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12630 i386_att_operand (char *operand_string
)
12632 const reg_entry
*r
;
12634 char *op_string
= operand_string
;
12636 if (is_space_char (*op_string
))
12639 /* We check for an absolute prefix (differentiating,
12640 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12641 if (*op_string
== ABSOLUTE_PREFIX
12642 && current_templates
->start
->opcode_modifier
.jump
)
12645 if (is_space_char (*op_string
))
12647 i
.jumpabsolute
= true;
12650 /* Check if operand is a register. */
12651 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12653 i386_operand_type temp
;
12658 /* Check for a segment override by searching for ':' after a
12659 segment register. */
12660 op_string
= end_op
;
12661 if (is_space_char (*op_string
))
12663 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12665 i
.seg
[i
.mem_operands
] = r
;
12667 /* Skip the ':' and whitespace. */
12669 if (is_space_char (*op_string
))
12672 /* Handle case of %es:*foo. */
12673 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12674 && current_templates
->start
->opcode_modifier
.jump
)
12677 if (is_space_char (*op_string
))
12679 i
.jumpabsolute
= true;
12682 if (!starts_memory_operand (*op_string
))
12684 as_bad (_("bad memory operand `%s'"), op_string
);
12687 goto do_memory_reference
;
12690 /* Handle vector operations. */
12691 if (*op_string
== '{')
12693 op_string
= check_VecOperations (op_string
);
12694 if (op_string
== NULL
)
12700 as_bad (_("junk `%s' after register"), op_string
);
12704 /* Reject pseudo registers for .insn. */
12705 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12707 as_bad (_("`%s%s' cannot be used here"),
12708 register_prefix
, r
->reg_name
);
12712 temp
= r
->reg_type
;
12713 temp
.bitfield
.baseindex
= 0;
12714 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12716 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12717 i
.op
[this_operand
].regs
= r
;
12720 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12721 operand was also present earlier on. */
12722 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12723 && i
.reg_operands
== 1)
12727 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12728 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12730 as_bad (_("`%s': misplaced `{%s}'"),
12731 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12735 else if (*op_string
== REGISTER_PREFIX
)
12737 as_bad (_("bad register name `%s'"), op_string
);
12740 else if (*op_string
== IMMEDIATE_PREFIX
)
12743 if (i
.jumpabsolute
)
12745 as_bad (_("immediate operand illegal with absolute jump"));
12748 if (!i386_immediate (op_string
))
12750 if (i
.rounding
.type
!= rc_none
)
12752 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12753 insn_name (current_templates
->start
));
12757 else if (RC_SAE_immediate (operand_string
))
12759 /* If it is a RC or SAE immediate, do the necessary placement check:
12760 Only another immediate or a GPR may precede it. */
12761 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12762 || (i
.reg_operands
== 1
12763 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12765 as_bad (_("`%s': misplaced `%s'"),
12766 insn_name (current_templates
->start
), operand_string
);
12770 else if (starts_memory_operand (*op_string
))
12772 /* This is a memory reference of some sort. */
12775 /* Start and end of displacement string expression (if found). */
12776 char *displacement_string_start
;
12777 char *displacement_string_end
;
12779 do_memory_reference
:
12780 /* Check for base index form. We detect the base index form by
12781 looking for an ')' at the end of the operand, searching
12782 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12784 base_string
= op_string
+ strlen (op_string
);
12786 /* Handle vector operations. */
12788 if (is_space_char (*base_string
))
12791 if (*base_string
== '}')
12793 char *vop_start
= NULL
;
12795 while (base_string
-- > op_string
)
12797 if (*base_string
== '"')
12799 if (*base_string
!= '{')
12802 vop_start
= base_string
;
12805 if (is_space_char (*base_string
))
12808 if (*base_string
!= '}')
12816 as_bad (_("unbalanced figure braces"));
12820 if (check_VecOperations (vop_start
) == NULL
)
12824 /* If we only have a displacement, set-up for it to be parsed later. */
12825 displacement_string_start
= op_string
;
12826 displacement_string_end
= base_string
+ 1;
12828 if (*base_string
== ')')
12831 unsigned int parens_not_balanced
= 0;
12832 bool in_quotes
= false;
12834 /* We've already checked that the number of left & right ()'s are
12835 equal, and that there's a matching set of double quotes. */
12836 end_op
= base_string
;
12837 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12839 if (*temp_string
== '\\' && temp_string
[1] == '"')
12841 else if (*temp_string
== '"')
12842 in_quotes
= !in_quotes
;
12843 else if (!in_quotes
)
12845 if (*temp_string
== '(' && !parens_not_balanced
++)
12846 base_string
= temp_string
;
12847 if (*temp_string
== ')')
12848 --parens_not_balanced
;
12852 temp_string
= base_string
;
12854 /* Skip past '(' and whitespace. */
12855 gas_assert (*base_string
== '(');
12857 if (is_space_char (*base_string
))
12860 if (*base_string
== ','
12861 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12864 displacement_string_end
= temp_string
;
12866 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12870 if (i
.base_reg
== &bad_reg
)
12872 base_string
= end_op
;
12873 if (is_space_char (*base_string
))
12877 /* There may be an index reg or scale factor here. */
12878 if (*base_string
== ',')
12881 if (is_space_char (*base_string
))
12884 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12887 if (i
.index_reg
== &bad_reg
)
12889 base_string
= end_op
;
12890 if (is_space_char (*base_string
))
12892 if (*base_string
== ',')
12895 if (is_space_char (*base_string
))
12898 else if (*base_string
!= ')')
12900 as_bad (_("expecting `,' or `)' "
12901 "after index register in `%s'"),
12906 else if (*base_string
== REGISTER_PREFIX
)
12908 end_op
= strchr (base_string
, ',');
12911 as_bad (_("bad register name `%s'"), base_string
);
12915 /* Check for scale factor. */
12916 if (*base_string
!= ')')
12918 char *end_scale
= i386_scale (base_string
);
12923 base_string
= end_scale
;
12924 if (is_space_char (*base_string
))
12926 if (*base_string
!= ')')
12928 as_bad (_("expecting `)' "
12929 "after scale factor in `%s'"),
12934 else if (!i
.index_reg
)
12936 as_bad (_("expecting index register or scale factor "
12937 "after `,'; got '%c'"),
12942 else if (*base_string
!= ')')
12944 as_bad (_("expecting `,' or `)' "
12945 "after base register in `%s'"),
12950 else if (*base_string
== REGISTER_PREFIX
)
12952 end_op
= strchr (base_string
, ',');
12955 as_bad (_("bad register name `%s'"), base_string
);
12960 /* If there's an expression beginning the operand, parse it,
12961 assuming displacement_string_start and
12962 displacement_string_end are meaningful. */
12963 if (displacement_string_start
!= displacement_string_end
)
12965 if (!i386_displacement (displacement_string_start
,
12966 displacement_string_end
))
12970 /* Special case for (%dx) while doing input/output op. */
12972 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12973 && i
.base_reg
->reg_type
.bitfield
.word
12974 && i
.index_reg
== 0
12975 && i
.log2_scale_factor
== 0
12976 && i
.seg
[i
.mem_operands
] == 0
12977 && !operand_type_check (i
.types
[this_operand
], disp
))
12979 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12980 i
.input_output_operand
= true;
12984 if (i386_index_check (operand_string
) == 0)
12986 i
.flags
[this_operand
] |= Operand_Mem
;
12991 /* It's not a memory operand; argh! */
12992 as_bad (_("invalid char %s beginning operand %d `%s'"),
12993 output_invalid (*op_string
),
12998 return 1; /* Normal return. */
13001 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13002 that an rs_machine_dependent frag may reach. */
13005 i386_frag_max_var (fragS
*frag
)
13007 /* The only relaxable frags are for jumps.
13008 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13009 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13010 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13015 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13017 /* STT_GNU_IFUNC symbol must go through PLT. */
13018 if ((symbol_get_bfdsym (fr_symbol
)->flags
13019 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13022 if (!S_IS_EXTERNAL (fr_symbol
))
13023 /* Symbol may be weak or local. */
13024 return !S_IS_WEAK (fr_symbol
);
13026 /* Global symbols with non-default visibility can't be preempted. */
13027 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13030 if (fr_var
!= NO_RELOC
)
13031 switch ((enum bfd_reloc_code_real
) fr_var
)
13033 case BFD_RELOC_386_PLT32
:
13034 case BFD_RELOC_X86_64_PLT32
:
13035 /* Symbol with PLT relocation may be preempted. */
13041 /* Global symbols with default visibility in a shared library may be
13042 preempted by another definition. */
13047 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13048 Note also work for Skylake and Cascadelake.
13049 ---------------------------------------------------------------------
13050 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13051 | ------ | ----------- | ------- | -------- |
13053 | Jno | N | N | Y |
13054 | Jc/Jb | Y | N | Y |
13055 | Jae/Jnb | Y | N | Y |
13056 | Je/Jz | Y | Y | Y |
13057 | Jne/Jnz | Y | Y | Y |
13058 | Jna/Jbe | Y | N | Y |
13059 | Ja/Jnbe | Y | N | Y |
13061 | Jns | N | N | Y |
13062 | Jp/Jpe | N | N | Y |
13063 | Jnp/Jpo | N | N | Y |
13064 | Jl/Jnge | Y | Y | Y |
13065 | Jge/Jnl | Y | Y | Y |
13066 | Jle/Jng | Y | Y | Y |
13067 | Jg/Jnle | Y | Y | Y |
13068 --------------------------------------------------------------------- */
13070 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13072 if (mf_cmp
== mf_cmp_alu_cmp
)
13073 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13074 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13075 if (mf_cmp
== mf_cmp_incdec
)
13076 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13077 || mf_jcc
== mf_jcc_jle
);
13078 if (mf_cmp
== mf_cmp_test_and
)
13083 /* Return the next non-empty frag. */
13086 i386_next_non_empty_frag (fragS
*fragP
)
13088 /* There may be a frag with a ".fill 0" when there is no room in
13089 the current frag for frag_grow in output_insn. */
13090 for (fragP
= fragP
->fr_next
;
13092 && fragP
->fr_type
== rs_fill
13093 && fragP
->fr_fix
== 0);
13094 fragP
= fragP
->fr_next
)
13099 /* Return the next jcc frag after BRANCH_PADDING. */
13102 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13104 fragS
*branch_fragP
;
13108 if (pad_fragP
->fr_type
== rs_machine_dependent
13109 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13110 == BRANCH_PADDING
))
13112 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13113 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13115 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13116 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13117 pad_fragP
->tc_frag_data
.mf_type
))
13118 return branch_fragP
;
13124 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13127 i386_classify_machine_dependent_frag (fragS
*fragP
)
13131 fragS
*branch_fragP
;
13133 unsigned int max_prefix_length
;
13135 if (fragP
->tc_frag_data
.classified
)
13138 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13139 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13140 for (next_fragP
= fragP
;
13141 next_fragP
!= NULL
;
13142 next_fragP
= next_fragP
->fr_next
)
13144 next_fragP
->tc_frag_data
.classified
= 1;
13145 if (next_fragP
->fr_type
== rs_machine_dependent
)
13146 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13148 case BRANCH_PADDING
:
13149 /* The BRANCH_PADDING frag must be followed by a branch
13151 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13152 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13154 case FUSED_JCC_PADDING
:
13155 /* Check if this is a fused jcc:
13157 CMP like instruction
13161 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13162 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13163 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13166 /* The BRANCH_PADDING frag is merged with the
13167 FUSED_JCC_PADDING frag. */
13168 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13169 /* CMP like instruction size. */
13170 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13171 frag_wane (pad_fragP
);
13172 /* Skip to branch_fragP. */
13173 next_fragP
= branch_fragP
;
13175 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13177 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13179 next_fragP
->fr_subtype
13180 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13181 next_fragP
->tc_frag_data
.max_bytes
13182 = next_fragP
->tc_frag_data
.max_prefix_length
;
13183 /* This will be updated in the BRANCH_PREFIX scan. */
13184 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13187 frag_wane (next_fragP
);
13192 /* Stop if there is no BRANCH_PREFIX. */
13193 if (!align_branch_prefix_size
)
13196 /* Scan for BRANCH_PREFIX. */
13197 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13199 if (fragP
->fr_type
!= rs_machine_dependent
13200 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13204 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13205 COND_JUMP_PREFIX. */
13206 max_prefix_length
= 0;
13207 for (next_fragP
= fragP
;
13208 next_fragP
!= NULL
;
13209 next_fragP
= next_fragP
->fr_next
)
13211 if (next_fragP
->fr_type
== rs_fill
)
13212 /* Skip rs_fill frags. */
13214 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13215 /* Stop for all other frags. */
13218 /* rs_machine_dependent frags. */
13219 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13222 /* Count BRANCH_PREFIX frags. */
13223 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13225 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13226 frag_wane (next_fragP
);
13230 += next_fragP
->tc_frag_data
.max_bytes
;
13232 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13234 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13235 == FUSED_JCC_PADDING
))
13237 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13238 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13242 /* Stop for other rs_machine_dependent frags. */
13246 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13248 /* Skip to the next frag. */
13249 fragP
= next_fragP
;
13253 /* Compute padding size for
13256 CMP like instruction
13258 COND_JUMP/UNCOND_JUMP
13263 COND_JUMP/UNCOND_JUMP
13267 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13269 unsigned int offset
, size
, padding_size
;
13270 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13272 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13274 address
= fragP
->fr_address
;
13275 address
+= fragP
->fr_fix
;
13277 /* CMP like instrunction size. */
13278 size
= fragP
->tc_frag_data
.cmp_size
;
13280 /* The base size of the branch frag. */
13281 size
+= branch_fragP
->fr_fix
;
13283 /* Add opcode and displacement bytes for the rs_machine_dependent
13285 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13286 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13288 /* Check if branch is within boundary and doesn't end at the last
13290 offset
= address
& ((1U << align_branch_power
) - 1);
13291 if ((offset
+ size
) >= (1U << align_branch_power
))
13292 /* Padding needed to avoid crossing boundary. */
13293 padding_size
= (1U << align_branch_power
) - offset
;
13295 /* No padding needed. */
13298 /* The return value may be saved in tc_frag_data.length which is
13300 if (!fits_in_unsigned_byte (padding_size
))
13303 return padding_size
;
13306 /* i386_generic_table_relax_frag()
13308 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13309 grow/shrink padding to align branch frags. Hand others to
13313 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13315 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13316 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13318 long padding_size
= i386_branch_padding_size (fragP
, 0);
13319 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13321 /* When the BRANCH_PREFIX frag is used, the computed address
13322 must match the actual address and there should be no padding. */
13323 if (fragP
->tc_frag_data
.padding_address
13324 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13328 /* Update the padding size. */
13330 fragP
->tc_frag_data
.length
= padding_size
;
13334 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13336 fragS
*padding_fragP
, *next_fragP
;
13337 long padding_size
, left_size
, last_size
;
13339 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13340 if (!padding_fragP
)
13341 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13342 return (fragP
->tc_frag_data
.length
13343 - fragP
->tc_frag_data
.last_length
);
13345 /* Compute the relative address of the padding frag in the very
13346 first time where the BRANCH_PREFIX frag sizes are zero. */
13347 if (!fragP
->tc_frag_data
.padding_address
)
13348 fragP
->tc_frag_data
.padding_address
13349 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13351 /* First update the last length from the previous interation. */
13352 left_size
= fragP
->tc_frag_data
.prefix_length
;
13353 for (next_fragP
= fragP
;
13354 next_fragP
!= padding_fragP
;
13355 next_fragP
= next_fragP
->fr_next
)
13356 if (next_fragP
->fr_type
== rs_machine_dependent
13357 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13362 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13366 if (max
> left_size
)
13371 next_fragP
->tc_frag_data
.last_length
= size
;
13375 next_fragP
->tc_frag_data
.last_length
= 0;
13378 /* Check the padding size for the padding frag. */
13379 padding_size
= i386_branch_padding_size
13380 (padding_fragP
, (fragP
->fr_address
13381 + fragP
->tc_frag_data
.padding_address
));
13383 last_size
= fragP
->tc_frag_data
.prefix_length
;
13384 /* Check if there is change from the last interation. */
13385 if (padding_size
== last_size
)
13387 /* Update the expected address of the padding frag. */
13388 padding_fragP
->tc_frag_data
.padding_address
13389 = (fragP
->fr_address
+ padding_size
13390 + fragP
->tc_frag_data
.padding_address
);
13394 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13396 /* No padding if there is no sufficient room. Clear the
13397 expected address of the padding frag. */
13398 padding_fragP
->tc_frag_data
.padding_address
= 0;
13402 /* Store the expected address of the padding frag. */
13403 padding_fragP
->tc_frag_data
.padding_address
13404 = (fragP
->fr_address
+ padding_size
13405 + fragP
->tc_frag_data
.padding_address
);
13407 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13409 /* Update the length for the current interation. */
13410 left_size
= padding_size
;
13411 for (next_fragP
= fragP
;
13412 next_fragP
!= padding_fragP
;
13413 next_fragP
= next_fragP
->fr_next
)
13414 if (next_fragP
->fr_type
== rs_machine_dependent
13415 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13420 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13424 if (max
> left_size
)
13429 next_fragP
->tc_frag_data
.length
= size
;
13433 next_fragP
->tc_frag_data
.length
= 0;
13436 return (fragP
->tc_frag_data
.length
13437 - fragP
->tc_frag_data
.last_length
);
13439 return relax_frag (segment
, fragP
, stretch
);
13442 /* md_estimate_size_before_relax()
13444 Called just before relax() for rs_machine_dependent frags. The x86
13445 assembler uses these frags to handle variable size jump
13448 Any symbol that is now undefined will not become defined.
13449 Return the correct fr_subtype in the frag.
13450 Return the initial "guess for variable size of frag" to caller.
13451 The guess is actually the growth beyond the fixed part. Whatever
13452 we do to grow the fixed or variable part contributes to our
13456 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13458 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13459 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13460 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13462 i386_classify_machine_dependent_frag (fragP
);
13463 return fragP
->tc_frag_data
.length
;
13466 /* We've already got fragP->fr_subtype right; all we have to do is
13467 check for un-relaxable symbols. On an ELF system, we can't relax
13468 an externally visible symbol, because it may be overridden by a
13470 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13473 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13476 #if defined (OBJ_COFF) && defined (TE_PE)
13477 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13478 && S_IS_WEAK (fragP
->fr_symbol
))
13482 /* Symbol is undefined in this segment, or we need to keep a
13483 reloc so that weak symbols can be overridden. */
13484 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13485 enum bfd_reloc_code_real reloc_type
;
13486 unsigned char *opcode
;
13490 if (fragP
->fr_var
!= NO_RELOC
)
13491 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13492 else if (size
== 2)
13493 reloc_type
= BFD_RELOC_16_PCREL
;
13494 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13495 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13496 && fragP
->fr_offset
== 0
13497 && need_plt32_p (fragP
->fr_symbol
))
13498 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13501 reloc_type
= BFD_RELOC_32_PCREL
;
13503 old_fr_fix
= fragP
->fr_fix
;
13504 opcode
= (unsigned char *) fragP
->fr_opcode
;
13506 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13509 /* Make jmp (0xeb) a (d)word displacement jump. */
13511 fragP
->fr_fix
+= size
;
13512 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13514 fragP
->fr_offset
, 1,
13520 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13522 /* Negate the condition, and branch past an
13523 unconditional jump. */
13526 /* Insert an unconditional jump. */
13528 /* We added two extra opcode bytes, and have a two byte
13530 fragP
->fr_fix
+= 2 + 2;
13531 fix_new (fragP
, old_fr_fix
+ 2, 2,
13533 fragP
->fr_offset
, 1,
13537 /* Fall through. */
13540 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13542 fragP
->fr_fix
+= 1;
13543 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13545 fragP
->fr_offset
, 1,
13546 BFD_RELOC_8_PCREL
);
13547 fixP
->fx_signed
= 1;
13551 /* This changes the byte-displacement jump 0x7N
13552 to the (d)word-displacement jump 0x0f,0x8N. */
13553 opcode
[1] = opcode
[0] + 0x10;
13554 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13555 /* We've added an opcode byte. */
13556 fragP
->fr_fix
+= 1 + size
;
13557 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13559 fragP
->fr_offset
, 1,
13564 BAD_CASE (fragP
->fr_subtype
);
13568 /* All jumps handled here are signed, but don't unconditionally use a
13569 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13570 around at 4G (outside of 64-bit mode) and 64k. */
13571 if (size
== 4 && flag_code
== CODE_64BIT
)
13572 fixP
->fx_signed
= 1;
13575 return fragP
->fr_fix
- old_fr_fix
;
13578 /* Guess size depending on current relax state. Initially the relax
13579 state will correspond to a short jump and we return 1, because
13580 the variable part of the frag (the branch offset) is one byte
13581 long. However, we can relax a section more than once and in that
13582 case we must either set fr_subtype back to the unrelaxed state,
13583 or return the value for the appropriate branch. */
13584 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13587 /* Called after relax() is finished.
13589 In: Address of frag.
13590 fr_type == rs_machine_dependent.
13591 fr_subtype is what the address relaxed to.
13593 Out: Any fixSs and constants are set up.
13594 Caller will turn frag into a ".space 0". */
13597 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13600 unsigned char *opcode
;
13601 unsigned char *where_to_put_displacement
= NULL
;
13602 offsetT target_address
;
13603 offsetT opcode_address
;
13604 unsigned int extension
= 0;
13605 offsetT displacement_from_opcode_start
;
13607 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13608 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13609 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13611 /* Generate nop padding. */
13612 unsigned int size
= fragP
->tc_frag_data
.length
;
13615 if (size
> fragP
->tc_frag_data
.max_bytes
)
13621 const char *branch
= "branch";
13622 const char *prefix
= "";
13623 fragS
*padding_fragP
;
13624 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13627 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13628 switch (fragP
->tc_frag_data
.default_prefix
)
13633 case CS_PREFIX_OPCODE
:
13636 case DS_PREFIX_OPCODE
:
13639 case ES_PREFIX_OPCODE
:
13642 case FS_PREFIX_OPCODE
:
13645 case GS_PREFIX_OPCODE
:
13648 case SS_PREFIX_OPCODE
:
13653 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13654 "%s within %d-byte boundary\n");
13656 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13657 "align %s within %d-byte boundary\n");
13661 padding_fragP
= fragP
;
13662 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13663 "%s within %d-byte boundary\n");
13667 switch (padding_fragP
->tc_frag_data
.branch_type
)
13669 case align_branch_jcc
:
13672 case align_branch_fused
:
13673 branch
= "fused jcc";
13675 case align_branch_jmp
:
13678 case align_branch_call
:
13681 case align_branch_indirect
:
13682 branch
= "indiret branch";
13684 case align_branch_ret
:
13691 fprintf (stdout
, msg
,
13692 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13693 (long long) fragP
->fr_address
, branch
,
13694 1 << align_branch_power
);
13696 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13697 memset (fragP
->fr_opcode
,
13698 fragP
->tc_frag_data
.default_prefix
, size
);
13700 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13702 fragP
->fr_fix
+= size
;
13707 opcode
= (unsigned char *) fragP
->fr_opcode
;
13709 /* Address we want to reach in file space. */
13710 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13712 /* Address opcode resides at in file space. */
13713 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13715 /* Displacement from opcode start to fill into instruction. */
13716 displacement_from_opcode_start
= target_address
- opcode_address
;
13718 if ((fragP
->fr_subtype
& BIG
) == 0)
13720 /* Don't have to change opcode. */
13721 extension
= 1; /* 1 opcode + 1 displacement */
13722 where_to_put_displacement
= &opcode
[1];
13726 if (no_cond_jump_promotion
13727 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13728 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13729 _("long jump required"));
13731 switch (fragP
->fr_subtype
)
13733 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13734 extension
= 4; /* 1 opcode + 4 displacement */
13736 where_to_put_displacement
= &opcode
[1];
13739 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13740 extension
= 2; /* 1 opcode + 2 displacement */
13742 where_to_put_displacement
= &opcode
[1];
13745 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13746 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13747 extension
= 5; /* 2 opcode + 4 displacement */
13748 opcode
[1] = opcode
[0] + 0x10;
13749 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13750 where_to_put_displacement
= &opcode
[2];
13753 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13754 extension
= 3; /* 2 opcode + 2 displacement */
13755 opcode
[1] = opcode
[0] + 0x10;
13756 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13757 where_to_put_displacement
= &opcode
[2];
13760 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13765 where_to_put_displacement
= &opcode
[3];
13769 BAD_CASE (fragP
->fr_subtype
);
13774 /* If size if less then four we are sure that the operand fits,
13775 but if it's 4, then it could be that the displacement is larger
13777 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13779 && ((addressT
) (displacement_from_opcode_start
- extension
13780 + ((addressT
) 1 << 31))
13781 > (((addressT
) 2 << 31) - 1)))
13783 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13784 _("jump target out of range"));
13785 /* Make us emit 0. */
13786 displacement_from_opcode_start
= extension
;
13788 /* Now put displacement after opcode. */
13789 md_number_to_chars ((char *) where_to_put_displacement
,
13790 (valueT
) (displacement_from_opcode_start
- extension
),
13791 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13792 fragP
->fr_fix
+= extension
;
13795 /* Apply a fixup (fixP) to segment data, once it has been determined
13796 by our caller that we have all the info we need to fix it up.
13798 Parameter valP is the pointer to the value of the bits.
13800 On the 386, immediates, displacements, and data pointers are all in
13801 the same (little-endian) format, so we don't need to care about which
13802 we are handling. */
13805 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13807 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13808 valueT value
= *valP
;
13810 #if !defined (TE_Mach)
13811 if (fixP
->fx_pcrel
)
13813 switch (fixP
->fx_r_type
)
13819 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13822 case BFD_RELOC_X86_64_32S
:
13823 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13826 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13829 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13834 if (fixP
->fx_addsy
!= NULL
13835 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13836 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13837 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13838 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13839 && !use_rela_relocations
)
13841 /* This is a hack. There should be a better way to handle this.
13842 This covers for the fact that bfd_install_relocation will
13843 subtract the current location (for partial_inplace, PC relative
13844 relocations); see more below. */
13848 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13851 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13856 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13858 if ((sym_seg
== seg
13859 || (symbol_section_p (fixP
->fx_addsy
)
13860 && sym_seg
!= absolute_section
))
13861 && !generic_force_reloc (fixP
))
13863 /* Yes, we add the values in twice. This is because
13864 bfd_install_relocation subtracts them out again. I think
13865 bfd_install_relocation is broken, but I don't dare change
13867 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13871 #if defined (OBJ_COFF) && defined (TE_PE)
13872 /* For some reason, the PE format does not store a
13873 section address offset for a PC relative symbol. */
13874 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13875 || S_IS_WEAK (fixP
->fx_addsy
))
13876 value
+= md_pcrel_from (fixP
);
13879 #if defined (OBJ_COFF) && defined (TE_PE)
13880 if (fixP
->fx_addsy
!= NULL
13881 && S_IS_WEAK (fixP
->fx_addsy
)
13882 /* PR 16858: Do not modify weak function references. */
13883 && ! fixP
->fx_pcrel
)
13885 #if !defined (TE_PEP)
13886 /* For x86 PE weak function symbols are neither PC-relative
13887 nor do they set S_IS_FUNCTION. So the only reliable way
13888 to detect them is to check the flags of their containing
13890 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13891 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13895 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13899 /* Fix a few things - the dynamic linker expects certain values here,
13900 and we must not disappoint it. */
13901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13902 if (IS_ELF
&& fixP
->fx_addsy
)
13903 switch (fixP
->fx_r_type
)
13905 case BFD_RELOC_386_PLT32
:
13906 case BFD_RELOC_X86_64_PLT32
:
13907 /* Make the jump instruction point to the address of the operand.
13908 At runtime we merely add the offset to the actual PLT entry.
13909 NB: Subtract the offset size only for jump instructions. */
13910 if (fixP
->fx_pcrel
)
13914 case BFD_RELOC_386_TLS_GD
:
13915 case BFD_RELOC_386_TLS_LDM
:
13916 case BFD_RELOC_386_TLS_IE_32
:
13917 case BFD_RELOC_386_TLS_IE
:
13918 case BFD_RELOC_386_TLS_GOTIE
:
13919 case BFD_RELOC_386_TLS_GOTDESC
:
13920 case BFD_RELOC_X86_64_TLSGD
:
13921 case BFD_RELOC_X86_64_TLSLD
:
13922 case BFD_RELOC_X86_64_GOTTPOFF
:
13923 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13924 value
= 0; /* Fully resolved at runtime. No addend. */
13926 case BFD_RELOC_386_TLS_LE
:
13927 case BFD_RELOC_386_TLS_LDO_32
:
13928 case BFD_RELOC_386_TLS_LE_32
:
13929 case BFD_RELOC_X86_64_DTPOFF32
:
13930 case BFD_RELOC_X86_64_DTPOFF64
:
13931 case BFD_RELOC_X86_64_TPOFF32
:
13932 case BFD_RELOC_X86_64_TPOFF64
:
13933 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13936 case BFD_RELOC_386_TLS_DESC_CALL
:
13937 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13938 value
= 0; /* Fully resolved at runtime. No addend. */
13939 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13943 case BFD_RELOC_VTABLE_INHERIT
:
13944 case BFD_RELOC_VTABLE_ENTRY
:
13951 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13953 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13955 value
= extend_to_32bit_address (value
);
13958 #endif /* !defined (TE_Mach) */
13960 /* Are we finished with this relocation now? */
13961 if (fixP
->fx_addsy
== NULL
)
13964 switch (fixP
->fx_r_type
)
13966 case BFD_RELOC_X86_64_32S
:
13967 fixP
->fx_signed
= 1;
13974 #if defined (OBJ_COFF) && defined (TE_PE)
13975 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13978 /* Remember value for tc_gen_reloc. */
13979 fixP
->fx_addnumber
= value
;
13980 /* Clear out the frag for now. */
13984 else if (use_rela_relocations
)
13986 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13987 fixP
->fx_no_overflow
= 1;
13988 /* Remember value for tc_gen_reloc. */
13989 fixP
->fx_addnumber
= value
;
13993 md_number_to_chars (p
, value
, fixP
->fx_size
);
13997 md_atof (int type
, char *litP
, int *sizeP
)
13999 /* This outputs the LITTLENUMs in REVERSE order;
14000 in accord with the bigendian 386. */
14001 return ieee_md_atof (type
, litP
, sizeP
, false);
14004 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14007 output_invalid (int c
)
14010 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14013 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14014 "(0x%x)", (unsigned char) c
);
14015 return output_invalid_buf
;
14018 /* Verify that @r can be used in the current context. */
14020 static bool check_register (const reg_entry
*r
)
14022 if (allow_pseudo_reg
)
14025 if (operand_type_all_zero (&r
->reg_type
))
14028 if ((r
->reg_type
.bitfield
.dword
14029 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14030 || r
->reg_type
.bitfield
.class == RegCR
14031 || r
->reg_type
.bitfield
.class == RegDR
)
14032 && !cpu_arch_flags
.bitfield
.cpui386
)
14035 if (r
->reg_type
.bitfield
.class == RegTR
14036 && (flag_code
== CODE_64BIT
14037 || !cpu_arch_flags
.bitfield
.cpui386
14038 || cpu_arch_isa_flags
.bitfield
.cpui586
14039 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14042 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14045 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14047 if (r
->reg_type
.bitfield
.zmmword
14048 || r
->reg_type
.bitfield
.class == RegMask
)
14051 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14053 if (r
->reg_type
.bitfield
.ymmword
)
14056 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14061 if (r
->reg_type
.bitfield
.zmmword
)
14063 if (vector_size
< VSZ512
)
14066 if (i
.vec_encoding
== vex_encoding_default
)
14067 i
.vec_encoding
= vex_encoding_evex512
;
14068 else if (i
.vec_encoding
!= vex_encoding_evex
14069 && i
.vec_encoding
!= vex_encoding_evex512
)
14070 i
.vec_encoding
= vex_encoding_error
;
14073 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14076 if (r
->reg_type
.bitfield
.tmmword
14077 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14078 || flag_code
!= CODE_64BIT
))
14081 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14084 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14085 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14088 /* Upper 16 vector registers are only available with VREX in 64bit
14089 mode, and require EVEX encoding. */
14090 if (r
->reg_flags
& RegVRex
)
14092 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14093 || flag_code
!= CODE_64BIT
)
14096 if (i
.vec_encoding
== vex_encoding_default
14097 || i
.vec_encoding
== vex_encoding_evex512
)
14098 i
.vec_encoding
= vex_encoding_evex
;
14099 else if (i
.vec_encoding
!= vex_encoding_evex
)
14100 i
.vec_encoding
= vex_encoding_error
;
14103 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14104 && (!cpu_arch_flags
.bitfield
.cpu64
14105 || r
->reg_type
.bitfield
.class != RegCR
14107 && flag_code
!= CODE_64BIT
)
14110 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14117 /* REG_STRING starts *before* REGISTER_PREFIX. */
14119 static const reg_entry
*
14120 parse_real_register (const char *reg_string
, char **end_op
)
14122 const char *s
= reg_string
;
14124 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14125 const reg_entry
*r
;
14127 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14128 if (*s
== REGISTER_PREFIX
)
14131 if (is_space_char (*s
))
14134 p
= reg_name_given
;
14135 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14137 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14138 return (const reg_entry
*) NULL
;
14142 if (is_part_of_name (*s
))
14143 return (const reg_entry
*) NULL
;
14145 *end_op
= (char *) s
;
14147 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14149 /* Handle floating point regs, allowing spaces in the (i) part. */
14152 if (!cpu_arch_flags
.bitfield
.cpu8087
14153 && !cpu_arch_flags
.bitfield
.cpu287
14154 && !cpu_arch_flags
.bitfield
.cpu387
14155 && !allow_pseudo_reg
)
14156 return (const reg_entry
*) NULL
;
14158 if (is_space_char (*s
))
14163 if (is_space_char (*s
))
14165 if (*s
>= '0' && *s
<= '7')
14167 int fpr
= *s
- '0';
14169 if (is_space_char (*s
))
14173 *end_op
= (char *) s
+ 1;
14174 know (r
[fpr
].reg_num
== fpr
);
14178 /* We have "%st(" then garbage. */
14179 return (const reg_entry
*) NULL
;
14183 return r
&& check_register (r
) ? r
: NULL
;
14186 /* REG_STRING starts *before* REGISTER_PREFIX. */
14188 static const reg_entry
*
14189 parse_register (const char *reg_string
, char **end_op
)
14191 const reg_entry
*r
;
14193 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14194 r
= parse_real_register (reg_string
, end_op
);
14199 char *save
= input_line_pointer
;
14200 char *buf
= xstrdup (reg_string
), *name
;
14203 input_line_pointer
= buf
;
14204 get_symbol_name (&name
);
14205 symbolP
= symbol_find (name
);
14206 while (symbolP
&& symbol_equated_p (symbolP
))
14208 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14210 if (e
->X_add_number
)
14212 symbolP
= e
->X_add_symbol
;
14214 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14216 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14218 if (e
->X_op
== O_register
)
14220 know (e
->X_add_number
>= 0
14221 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14222 r
= i386_regtab
+ e
->X_add_number
;
14223 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14225 if (r
&& !check_register (r
))
14227 as_bad (_("register '%s%s' cannot be used here"),
14228 register_prefix
, r
->reg_name
);
14232 input_line_pointer
= save
;
14239 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14241 const reg_entry
*r
= NULL
;
14242 char *end
= input_line_pointer
;
14244 /* We only know the terminating character here. It being double quote could
14245 be the closing one of a quoted symbol name, or an opening one from a
14246 following string (or another quoted symbol name). Since the latter can't
14247 be valid syntax for anything, bailing in either case is good enough. */
14248 if (*nextcharP
== '"')
14252 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14253 r
= parse_real_register (name
, &input_line_pointer
);
14254 if (r
&& end
<= input_line_pointer
)
14256 *nextcharP
= *input_line_pointer
;
14257 *input_line_pointer
= 0;
14258 e
->X_op
= O_register
;
14259 e
->X_add_number
= r
- i386_regtab
;
14262 input_line_pointer
= end
;
14264 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14268 md_operand (expressionS
*e
)
14271 const reg_entry
*r
;
14273 switch (*input_line_pointer
)
14275 case REGISTER_PREFIX
:
14276 r
= parse_real_register (input_line_pointer
, &end
);
14279 e
->X_op
= O_register
;
14280 e
->X_add_number
= r
- i386_regtab
;
14281 input_line_pointer
= end
;
14286 gas_assert (intel_syntax
);
14287 end
= input_line_pointer
++;
14289 if (*input_line_pointer
== ']')
14291 ++input_line_pointer
;
14292 e
->X_op_symbol
= make_expr_symbol (e
);
14293 e
->X_add_symbol
= NULL
;
14294 e
->X_add_number
= 0;
14299 e
->X_op
= O_absent
;
14300 input_line_pointer
= end
;
14307 /* To maintain consistency with !BFD64 builds of gas record, whether any
14308 (binary) operator was involved in an expression. As expressions are
14309 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14310 truncate results. */
14311 bool i386_record_operator (operatorT op
,
14312 const expressionS
*left
,
14313 const expressionS
*right
)
14315 if (op
== O_absent
)
14320 /* Since the expression parser applies unary operators fine to bignum
14321 operands, we don't need to be concerned of respective operands not
14322 fitting in 32 bits. */
14323 if (right
->X_op
== O_constant
&& right
->X_unsigned
14324 && !fits_in_unsigned_long (right
->X_add_number
))
14327 /* This isn't entirely right: The pattern can also result when constant
14328 expressions are folded (e.g. 0xffffffff + 1). */
14329 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14330 && !fits_in_unsigned_long (left
->X_add_number
))
14331 || (right
->X_op
== O_constant
&& right
->X_unsigned
14332 && !fits_in_unsigned_long (right
->X_add_number
)))
14333 expr_mode
= expr_large_value
;
14335 if (expr_mode
!= expr_large_value
)
14336 expr_mode
= expr_operator_present
;
14342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14343 const char *md_shortopts
= "kVQ:sqnO::";
14345 const char *md_shortopts
= "qnO::";
14348 #define OPTION_32 (OPTION_MD_BASE + 0)
14349 #define OPTION_64 (OPTION_MD_BASE + 1)
14350 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14351 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14352 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14353 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14354 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14355 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14356 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14357 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14358 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14359 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14360 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14361 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14362 #define OPTION_X32 (OPTION_MD_BASE + 14)
14363 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14364 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14365 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14366 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14367 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14368 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14369 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14370 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14371 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14372 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14373 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14374 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14375 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14376 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14377 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14378 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14379 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14380 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14381 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14382 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14384 struct option md_longopts
[] =
14386 {"32", no_argument
, NULL
, OPTION_32
},
14387 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14388 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14389 {"64", no_argument
, NULL
, OPTION_64
},
14391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14392 {"x32", no_argument
, NULL
, OPTION_X32
},
14393 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14394 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14396 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14397 {"march", required_argument
, NULL
, OPTION_MARCH
},
14398 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14399 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14400 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14401 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14402 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14403 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14404 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14405 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14406 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14407 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14408 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14409 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14410 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14411 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14412 # if defined (TE_PE) || defined (TE_PEP)
14413 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14415 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14416 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14417 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14418 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14419 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14420 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14421 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14422 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14423 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14424 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14425 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14426 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14427 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14428 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14429 {NULL
, no_argument
, NULL
, 0}
14431 size_t md_longopts_size
= sizeof (md_longopts
);
14434 md_parse_option (int c
, const char *arg
)
14437 char *arch
, *next
, *saved
, *type
;
14442 optimize_align_code
= 0;
14446 quiet_warnings
= 1;
14449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14450 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14451 should be emitted or not. FIXME: Not implemented. */
14453 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14457 /* -V: SVR4 argument to print version ID. */
14459 print_version_id ();
14462 /* -k: Ignore for FreeBSD compatibility. */
14467 /* -s: On i386 Solaris, this tells the native assembler to use
14468 .stab instead of .stab.excl. We always use .stab anyhow. */
14471 case OPTION_MSHARED
:
14475 case OPTION_X86_USED_NOTE
:
14476 if (strcasecmp (arg
, "yes") == 0)
14478 else if (strcasecmp (arg
, "no") == 0)
14481 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14486 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14487 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14490 const char **list
, **l
;
14492 list
= bfd_target_list ();
14493 for (l
= list
; *l
!= NULL
; l
++)
14494 if (startswith (*l
, "elf64-x86-64")
14495 || strcmp (*l
, "coff-x86-64") == 0
14496 || strcmp (*l
, "pe-x86-64") == 0
14497 || strcmp (*l
, "pei-x86-64") == 0
14498 || strcmp (*l
, "mach-o-x86-64") == 0)
14500 default_arch
= "x86_64";
14504 as_fatal (_("no compiled in support for x86_64"));
14510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14514 const char **list
, **l
;
14516 list
= bfd_target_list ();
14517 for (l
= list
; *l
!= NULL
; l
++)
14518 if (startswith (*l
, "elf32-x86-64"))
14520 default_arch
= "x86_64:32";
14524 as_fatal (_("no compiled in support for 32bit x86_64"));
14528 as_fatal (_("32bit x86_64 is only supported for ELF"));
14534 const char **list
, **l
;
14536 list
= bfd_target_list ();
14537 for (l
= list
; *l
!= NULL
; l
++)
14538 if (strstr (*l
, "-i386")
14539 || strstr (*l
, "-go32"))
14541 default_arch
= "i386";
14545 as_fatal (_("no compiled in support for ix86"));
14550 case OPTION_DIVIDE
:
14551 #ifdef SVR4_COMMENT_CHARS
14556 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14558 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14562 i386_comment_chars
= n
;
14568 saved
= xstrdup (arg
);
14570 /* Allow -march=+nosse. */
14578 as_fatal (_("invalid -march= option: `%s'"), arg
);
14579 next
= strchr (arch
, '+');
14582 vsz
= strchr (arch
, '/');
14585 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14587 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14590 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14591 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14594 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14597 cpu_arch_name
= cpu_arch
[j
].name
;
14598 free (cpu_sub_arch_name
);
14599 cpu_sub_arch_name
= NULL
;
14600 cpu_arch_flags
= cpu_arch
[j
].enable
;
14601 cpu_arch_isa
= cpu_arch
[j
].type
;
14602 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14603 if (!cpu_arch_tune_set
)
14604 cpu_arch_tune
= cpu_arch_isa
;
14605 vector_size
= VSZ_DEFAULT
;
14608 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14609 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14610 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14612 /* ISA extension. */
14615 switch (cpu_arch
[j
].vsz
)
14624 unsigned long val
= strtoul (vsz
, &end
, 0);
14630 case 512: vector_size
= VSZ512
; break;
14631 case 256: vector_size
= VSZ256
; break;
14632 case 128: vector_size
= VSZ128
; break;
14634 as_warn (_("Unrecognized vector size specifier ignored"));
14639 /* Fall through. */
14641 vector_size
= VSZ_DEFAULT
;
14649 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14651 /* Disable an ISA extension. */
14652 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14653 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14654 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14657 if (cpu_arch
[j
].vsz
== vsz_set
)
14658 vector_size
= VSZ_DEFAULT
;
14663 if (j
>= ARRAY_SIZE (cpu_arch
))
14664 as_fatal (_("invalid -march= option: `%s'"), arg
);
14668 while (next
!= NULL
);
14674 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14675 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14677 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14678 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14680 cpu_arch_tune_set
= 1;
14681 cpu_arch_tune
= cpu_arch
[j
].type
;
14685 if (j
>= ARRAY_SIZE (cpu_arch
))
14686 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14689 case OPTION_MMNEMONIC
:
14690 if (strcasecmp (arg
, "att") == 0)
14691 intel_mnemonic
= 0;
14692 else if (strcasecmp (arg
, "intel") == 0)
14693 intel_mnemonic
= 1;
14695 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14698 case OPTION_MSYNTAX
:
14699 if (strcasecmp (arg
, "att") == 0)
14701 else if (strcasecmp (arg
, "intel") == 0)
14704 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14707 case OPTION_MINDEX_REG
:
14708 allow_index_reg
= 1;
14711 case OPTION_MNAKED_REG
:
14712 allow_naked_reg
= 1;
14715 case OPTION_MSSE2AVX
:
14719 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14720 use_unaligned_vector_move
= 1;
14723 case OPTION_MSSE_CHECK
:
14724 if (strcasecmp (arg
, "error") == 0)
14725 sse_check
= check_error
;
14726 else if (strcasecmp (arg
, "warning") == 0)
14727 sse_check
= check_warning
;
14728 else if (strcasecmp (arg
, "none") == 0)
14729 sse_check
= check_none
;
14731 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14734 case OPTION_MOPERAND_CHECK
:
14735 if (strcasecmp (arg
, "error") == 0)
14736 operand_check
= check_error
;
14737 else if (strcasecmp (arg
, "warning") == 0)
14738 operand_check
= check_warning
;
14739 else if (strcasecmp (arg
, "none") == 0)
14740 operand_check
= check_none
;
14742 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14745 case OPTION_MAVXSCALAR
:
14746 if (strcasecmp (arg
, "128") == 0)
14747 avxscalar
= vex128
;
14748 else if (strcasecmp (arg
, "256") == 0)
14749 avxscalar
= vex256
;
14751 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14754 case OPTION_MVEXWIG
:
14755 if (strcmp (arg
, "0") == 0)
14757 else if (strcmp (arg
, "1") == 0)
14760 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14763 case OPTION_MADD_BND_PREFIX
:
14764 add_bnd_prefix
= 1;
14767 case OPTION_MEVEXLIG
:
14768 if (strcmp (arg
, "128") == 0)
14769 evexlig
= evexl128
;
14770 else if (strcmp (arg
, "256") == 0)
14771 evexlig
= evexl256
;
14772 else if (strcmp (arg
, "512") == 0)
14773 evexlig
= evexl512
;
14775 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14778 case OPTION_MEVEXRCIG
:
14779 if (strcmp (arg
, "rne") == 0)
14781 else if (strcmp (arg
, "rd") == 0)
14783 else if (strcmp (arg
, "ru") == 0)
14785 else if (strcmp (arg
, "rz") == 0)
14788 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14791 case OPTION_MEVEXWIG
:
14792 if (strcmp (arg
, "0") == 0)
14794 else if (strcmp (arg
, "1") == 0)
14797 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14800 # if defined (TE_PE) || defined (TE_PEP)
14801 case OPTION_MBIG_OBJ
:
14806 case OPTION_MOMIT_LOCK_PREFIX
:
14807 if (strcasecmp (arg
, "yes") == 0)
14808 omit_lock_prefix
= 1;
14809 else if (strcasecmp (arg
, "no") == 0)
14810 omit_lock_prefix
= 0;
14812 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14815 case OPTION_MFENCE_AS_LOCK_ADD
:
14816 if (strcasecmp (arg
, "yes") == 0)
14818 else if (strcasecmp (arg
, "no") == 0)
14821 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14824 case OPTION_MLFENCE_AFTER_LOAD
:
14825 if (strcasecmp (arg
, "yes") == 0)
14826 lfence_after_load
= 1;
14827 else if (strcasecmp (arg
, "no") == 0)
14828 lfence_after_load
= 0;
14830 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14833 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14834 if (strcasecmp (arg
, "all") == 0)
14836 lfence_before_indirect_branch
= lfence_branch_all
;
14837 if (lfence_before_ret
== lfence_before_ret_none
)
14838 lfence_before_ret
= lfence_before_ret_shl
;
14840 else if (strcasecmp (arg
, "memory") == 0)
14841 lfence_before_indirect_branch
= lfence_branch_memory
;
14842 else if (strcasecmp (arg
, "register") == 0)
14843 lfence_before_indirect_branch
= lfence_branch_register
;
14844 else if (strcasecmp (arg
, "none") == 0)
14845 lfence_before_indirect_branch
= lfence_branch_none
;
14847 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14851 case OPTION_MLFENCE_BEFORE_RET
:
14852 if (strcasecmp (arg
, "or") == 0)
14853 lfence_before_ret
= lfence_before_ret_or
;
14854 else if (strcasecmp (arg
, "not") == 0)
14855 lfence_before_ret
= lfence_before_ret_not
;
14856 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14857 lfence_before_ret
= lfence_before_ret_shl
;
14858 else if (strcasecmp (arg
, "none") == 0)
14859 lfence_before_ret
= lfence_before_ret_none
;
14861 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14865 case OPTION_MRELAX_RELOCATIONS
:
14866 if (strcasecmp (arg
, "yes") == 0)
14867 generate_relax_relocations
= 1;
14868 else if (strcasecmp (arg
, "no") == 0)
14869 generate_relax_relocations
= 0;
14871 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14874 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14877 long int align
= strtoul (arg
, &end
, 0);
14882 align_branch_power
= 0;
14885 else if (align
>= 16)
14888 for (align_power
= 0;
14890 align
>>= 1, align_power
++)
14892 /* Limit alignment power to 31. */
14893 if (align
== 1 && align_power
< 32)
14895 align_branch_power
= align_power
;
14900 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14904 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14907 int align
= strtoul (arg
, &end
, 0);
14908 /* Some processors only support 5 prefixes. */
14909 if (*end
== '\0' && align
>= 0 && align
< 6)
14911 align_branch_prefix_size
= align
;
14914 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14919 case OPTION_MALIGN_BRANCH
:
14921 saved
= xstrdup (arg
);
14925 next
= strchr (type
, '+');
14928 if (strcasecmp (type
, "jcc") == 0)
14929 align_branch
|= align_branch_jcc_bit
;
14930 else if (strcasecmp (type
, "fused") == 0)
14931 align_branch
|= align_branch_fused_bit
;
14932 else if (strcasecmp (type
, "jmp") == 0)
14933 align_branch
|= align_branch_jmp_bit
;
14934 else if (strcasecmp (type
, "call") == 0)
14935 align_branch
|= align_branch_call_bit
;
14936 else if (strcasecmp (type
, "ret") == 0)
14937 align_branch
|= align_branch_ret_bit
;
14938 else if (strcasecmp (type
, "indirect") == 0)
14939 align_branch
|= align_branch_indirect_bit
;
14941 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14944 while (next
!= NULL
);
14948 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14949 align_branch_power
= 5;
14950 align_branch_prefix_size
= 5;
14951 align_branch
= (align_branch_jcc_bit
14952 | align_branch_fused_bit
14953 | align_branch_jmp_bit
);
14956 case OPTION_MAMD64
:
14960 case OPTION_MINTEL64
:
14968 /* Turn off -Os. */
14969 optimize_for_space
= 0;
14971 else if (*arg
== 's')
14973 optimize_for_space
= 1;
14974 /* Turn on all encoding optimizations. */
14975 optimize
= INT_MAX
;
14979 optimize
= atoi (arg
);
14980 /* Turn off -Os. */
14981 optimize_for_space
= 0;
14991 #define MESSAGE_TEMPLATE \
14995 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14996 int *left_p
, const char *name
, int len
)
14998 int size
= sizeof (MESSAGE_TEMPLATE
);
14999 int left
= *left_p
;
15001 /* Reserve 2 spaces for ", " or ",\0" */
15004 /* Check if there is any room. */
15012 p
= mempcpy (p
, name
, len
);
15016 /* Output the current message now and start a new one. */
15019 fprintf (stream
, "%s\n", message
);
15021 left
= size
- (start
- message
) - len
- 2;
15023 gas_assert (left
>= 0);
15025 p
= mempcpy (p
, name
, len
);
15033 show_arch (FILE *stream
, int ext
, int check
)
15035 static char message
[] = MESSAGE_TEMPLATE
;
15036 char *start
= message
+ 27;
15038 int size
= sizeof (MESSAGE_TEMPLATE
);
15045 left
= size
- (start
- message
);
15049 p
= output_message (stream
, p
, message
, start
, &left
,
15050 STRING_COMMA_LEN ("default"));
15051 p
= output_message (stream
, p
, message
, start
, &left
,
15052 STRING_COMMA_LEN ("push"));
15053 p
= output_message (stream
, p
, message
, start
, &left
,
15054 STRING_COMMA_LEN ("pop"));
15057 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15059 /* Should it be skipped? */
15060 if (cpu_arch
[j
].skip
)
15063 name
= cpu_arch
[j
].name
;
15064 len
= cpu_arch
[j
].len
;
15065 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15067 /* It is an extension. Skip if we aren't asked to show it. */
15068 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15073 /* It is an processor. Skip if we show only extension. */
15076 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15078 /* It is an impossible processor - skip. */
15082 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15085 /* Display disabled extensions. */
15087 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15091 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15092 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15094 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15095 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15101 fprintf (stream
, "%s\n", message
);
15105 md_show_usage (FILE *stream
)
15107 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15108 fprintf (stream
, _("\
15109 -Qy, -Qn ignored\n\
15110 -V print assembler version number\n\
15113 fprintf (stream
, _("\
15114 -n do not optimize code alignment\n\
15115 -O{012s} attempt some code optimizations\n\
15116 -q quieten some warnings\n"));
15117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15118 fprintf (stream
, _("\
15122 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15123 fprintf (stream
, _("\
15124 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15125 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15126 fprintf (stream
, _("\
15127 --32/--64 generate 32bit/64bit object\n"));
15130 #ifdef SVR4_COMMENT_CHARS
15131 fprintf (stream
, _("\
15132 --divide do not treat `/' as a comment character\n"));
15134 fprintf (stream
, _("\
15135 --divide ignored\n"));
15137 fprintf (stream
, _("\
15138 -march=CPU[,+EXTENSION...]\n\
15139 generate code for CPU and EXTENSION, CPU is one of:\n"));
15140 show_arch (stream
, 0, 1);
15141 fprintf (stream
, _("\
15142 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15143 show_arch (stream
, 1, 0);
15144 fprintf (stream
, _("\
15145 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15146 show_arch (stream
, 0, 0);
15147 fprintf (stream
, _("\
15148 -msse2avx encode SSE instructions with VEX prefix\n"));
15149 fprintf (stream
, _("\
15150 -muse-unaligned-vector-move\n\
15151 encode aligned vector move as unaligned vector move\n"));
15152 fprintf (stream
, _("\
15153 -msse-check=[none|error|warning] (default: warning)\n\
15154 check SSE instructions\n"));
15155 fprintf (stream
, _("\
15156 -moperand-check=[none|error|warning] (default: warning)\n\
15157 check operand combinations for validity\n"));
15158 fprintf (stream
, _("\
15159 -mavxscalar=[128|256] (default: 128)\n\
15160 encode scalar AVX instructions with specific vector\n\
15162 fprintf (stream
, _("\
15163 -mvexwig=[0|1] (default: 0)\n\
15164 encode VEX instructions with specific VEX.W value\n\
15165 for VEX.W bit ignored instructions\n"));
15166 fprintf (stream
, _("\
15167 -mevexlig=[128|256|512] (default: 128)\n\
15168 encode scalar EVEX instructions with specific vector\n\
15170 fprintf (stream
, _("\
15171 -mevexwig=[0|1] (default: 0)\n\
15172 encode EVEX instructions with specific EVEX.W value\n\
15173 for EVEX.W bit ignored instructions\n"));
15174 fprintf (stream
, _("\
15175 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15176 encode EVEX instructions with specific EVEX.RC value\n\
15177 for SAE-only ignored instructions\n"));
15178 fprintf (stream
, _("\
15179 -mmnemonic=[att|intel] "));
15180 if (SYSV386_COMPAT
)
15181 fprintf (stream
, _("(default: att)\n"));
15183 fprintf (stream
, _("(default: intel)\n"));
15184 fprintf (stream
, _("\
15185 use AT&T/Intel mnemonic\n"));
15186 fprintf (stream
, _("\
15187 -msyntax=[att|intel] (default: att)\n\
15188 use AT&T/Intel syntax\n"));
15189 fprintf (stream
, _("\
15190 -mindex-reg support pseudo index registers\n"));
15191 fprintf (stream
, _("\
15192 -mnaked-reg don't require `%%' prefix for registers\n"));
15193 fprintf (stream
, _("\
15194 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15196 fprintf (stream
, _("\
15197 -mshared disable branch optimization for shared code\n"));
15198 fprintf (stream
, _("\
15199 -mx86-used-note=[no|yes] "));
15200 if (DEFAULT_X86_USED_NOTE
)
15201 fprintf (stream
, _("(default: yes)\n"));
15203 fprintf (stream
, _("(default: no)\n"));
15204 fprintf (stream
, _("\
15205 generate x86 used ISA and feature properties\n"));
15207 #if defined (TE_PE) || defined (TE_PEP)
15208 fprintf (stream
, _("\
15209 -mbig-obj generate big object files\n"));
15211 fprintf (stream
, _("\
15212 -momit-lock-prefix=[no|yes] (default: no)\n\
15213 strip all lock prefixes\n"));
15214 fprintf (stream
, _("\
15215 -mfence-as-lock-add=[no|yes] (default: no)\n\
15216 encode lfence, mfence and sfence as\n\
15217 lock addl $0x0, (%%{re}sp)\n"));
15218 fprintf (stream
, _("\
15219 -mrelax-relocations=[no|yes] "));
15220 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15221 fprintf (stream
, _("(default: yes)\n"));
15223 fprintf (stream
, _("(default: no)\n"));
15224 fprintf (stream
, _("\
15225 generate relax relocations\n"));
15226 fprintf (stream
, _("\
15227 -malign-branch-boundary=NUM (default: 0)\n\
15228 align branches within NUM byte boundary\n"));
15229 fprintf (stream
, _("\
15230 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15231 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15233 specify types of branches to align\n"));
15234 fprintf (stream
, _("\
15235 -malign-branch-prefix-size=NUM (default: 5)\n\
15236 align branches with NUM prefixes per instruction\n"));
15237 fprintf (stream
, _("\
15238 -mbranches-within-32B-boundaries\n\
15239 align branches within 32 byte boundary\n"));
15240 fprintf (stream
, _("\
15241 -mlfence-after-load=[no|yes] (default: no)\n\
15242 generate lfence after load\n"));
15243 fprintf (stream
, _("\
15244 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15245 generate lfence before indirect near branch\n"));
15246 fprintf (stream
, _("\
15247 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15248 generate lfence before ret\n"));
15249 fprintf (stream
, _("\
15250 -mamd64 accept only AMD64 ISA [default]\n"));
15251 fprintf (stream
, _("\
15252 -mintel64 accept only Intel64 ISA\n"));
15255 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15256 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15257 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15259 /* Pick the target format to use. */
15262 i386_target_format (void)
15264 if (startswith (default_arch
, "x86_64"))
15266 update_code_flag (CODE_64BIT
, 1);
15267 if (default_arch
[6] == '\0')
15268 x86_elf_abi
= X86_64_ABI
;
15270 x86_elf_abi
= X86_64_X32_ABI
;
15272 else if (!strcmp (default_arch
, "i386"))
15273 update_code_flag (CODE_32BIT
, 1);
15274 else if (!strcmp (default_arch
, "iamcu"))
15276 update_code_flag (CODE_32BIT
, 1);
15277 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15279 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15280 cpu_arch_name
= "iamcu";
15281 free (cpu_sub_arch_name
);
15282 cpu_sub_arch_name
= NULL
;
15283 cpu_arch_flags
= iamcu_flags
;
15284 cpu_arch_isa
= PROCESSOR_IAMCU
;
15285 cpu_arch_isa_flags
= iamcu_flags
;
15286 if (!cpu_arch_tune_set
)
15287 cpu_arch_tune
= PROCESSOR_IAMCU
;
15289 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15290 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15294 as_fatal (_("unknown architecture"));
15296 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15297 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15299 switch (OUTPUT_FLAVOR
)
15301 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15302 case bfd_target_aout_flavour
:
15303 return AOUT_TARGET_FORMAT
;
15305 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15306 # if defined (TE_PE) || defined (TE_PEP)
15307 case bfd_target_coff_flavour
:
15308 if (flag_code
== CODE_64BIT
)
15311 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15313 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15314 # elif defined (TE_GO32)
15315 case bfd_target_coff_flavour
:
15316 return "coff-go32";
15318 case bfd_target_coff_flavour
:
15319 return "coff-i386";
15322 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15323 case bfd_target_elf_flavour
:
15325 const char *format
;
15327 switch (x86_elf_abi
)
15330 format
= ELF_TARGET_FORMAT
;
15332 tls_get_addr
= "___tls_get_addr";
15336 use_rela_relocations
= 1;
15339 tls_get_addr
= "__tls_get_addr";
15341 format
= ELF_TARGET_FORMAT64
;
15343 case X86_64_X32_ABI
:
15344 use_rela_relocations
= 1;
15347 tls_get_addr
= "__tls_get_addr";
15349 disallow_64bit_reloc
= 1;
15350 format
= ELF_TARGET_FORMAT32
;
15353 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15355 if (x86_elf_abi
!= I386_ABI
)
15356 as_fatal (_("Intel MCU is 32bit only"));
15357 return ELF_TARGET_IAMCU_FORMAT
;
15363 #if defined (OBJ_MACH_O)
15364 case bfd_target_mach_o_flavour
:
15365 if (flag_code
== CODE_64BIT
)
15367 use_rela_relocations
= 1;
15369 return "mach-o-x86-64";
15372 return "mach-o-i386";
15380 #endif /* OBJ_MAYBE_ more than one */
15383 md_undefined_symbol (char *name
)
15385 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15386 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15387 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15388 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15392 if (symbol_find (name
))
15393 as_bad (_("GOT already in symbol table"));
15394 GOT_symbol
= symbol_new (name
, undefined_section
,
15395 &zero_address_frag
, 0);
15402 /* Round up a section size to the appropriate boundary. */
15405 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15407 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15408 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15410 /* For a.out, force the section size to be aligned. If we don't do
15411 this, BFD will align it for us, but it will not write out the
15412 final bytes of the section. This may be a bug in BFD, but it is
15413 easier to fix it here since that is how the other a.out targets
15417 align
= bfd_section_alignment (segment
);
15418 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15425 /* On the i386, PC-relative offsets are relative to the start of the
15426 next instruction. That is, the address of the offset, plus its
15427 size, since the offset is always the last part of the insn. */
15430 md_pcrel_from (fixS
*fixP
)
15432 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15438 s_bss (int ignore ATTRIBUTE_UNUSED
)
15442 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15444 obj_elf_section_change_hook ();
15446 temp
= get_absolute_expression ();
15447 subseg_set (bss_section
, (subsegT
) temp
);
15448 demand_empty_rest_of_line ();
15453 /* Remember constant directive. */
15456 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15458 if (last_insn
.kind
!= last_insn_directive
15459 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15461 last_insn
.seg
= now_seg
;
15462 last_insn
.kind
= last_insn_directive
;
15463 last_insn
.name
= "constant directive";
15464 last_insn
.file
= as_where (&last_insn
.line
);
15465 if (lfence_before_ret
!= lfence_before_ret_none
)
15467 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15468 as_warn (_("constant directive skips -mlfence-before-ret "
15469 "and -mlfence-before-indirect-branch"));
15471 as_warn (_("constant directive skips -mlfence-before-ret"));
15473 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15474 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15479 i386_validate_fix (fixS
*fixp
)
15481 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15483 reloc_howto_type
*howto
;
15485 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15486 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15487 _("invalid %s relocation against register"),
15488 howto
? howto
->name
: "<unknown>");
15492 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15493 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15494 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15495 return IS_ELF
&& fixp
->fx_addsy
15496 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15497 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15500 if (fixp
->fx_subsy
)
15502 if (fixp
->fx_subsy
== GOT_symbol
)
15504 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15509 if (fixp
->fx_tcbit2
)
15510 fixp
->fx_r_type
= (fixp
->fx_tcbit
15511 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15512 : BFD_RELOC_X86_64_GOTPCRELX
);
15515 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15520 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15522 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15524 fixp
->fx_subsy
= 0;
15527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15530 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15531 to section. Since PLT32 relocation must be against symbols,
15532 turn such PLT32 relocation into PC32 relocation. */
15534 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15535 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15536 && symbol_section_p (fixp
->fx_addsy
))
15537 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15540 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15541 && fixp
->fx_tcbit2
)
15542 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15551 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15554 bfd_reloc_code_real_type code
;
15556 switch (fixp
->fx_r_type
)
15558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15561 case BFD_RELOC_SIZE32
:
15562 case BFD_RELOC_SIZE64
:
15564 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15565 && (!fixp
->fx_subsy
15566 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15567 sym
= fixp
->fx_addsy
;
15568 else if (fixp
->fx_subsy
15569 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15570 && (!fixp
->fx_addsy
15571 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15572 sym
= fixp
->fx_subsy
;
15575 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15577 /* Resolve size relocation against local symbol to size of
15578 the symbol plus addend. */
15579 valueT value
= S_GET_SIZE (sym
);
15581 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15582 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15583 if (sym
== fixp
->fx_subsy
)
15586 if (fixp
->fx_addsy
)
15587 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15589 else if (fixp
->fx_subsy
)
15590 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15591 value
+= fixp
->fx_offset
;
15592 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15594 && !fits_in_unsigned_long (value
))
15595 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15596 _("symbol size computation overflow"));
15597 fixp
->fx_addsy
= NULL
;
15598 fixp
->fx_subsy
= NULL
;
15599 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15602 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15604 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15605 "unsupported expression involving @size");
15609 /* Fall through. */
15611 case BFD_RELOC_X86_64_PLT32
:
15612 case BFD_RELOC_X86_64_GOT32
:
15613 case BFD_RELOC_X86_64_GOTPCREL
:
15614 case BFD_RELOC_X86_64_GOTPCRELX
:
15615 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15616 case BFD_RELOC_386_PLT32
:
15617 case BFD_RELOC_386_GOT32
:
15618 case BFD_RELOC_386_GOT32X
:
15619 case BFD_RELOC_386_GOTOFF
:
15620 case BFD_RELOC_386_GOTPC
:
15621 case BFD_RELOC_386_TLS_GD
:
15622 case BFD_RELOC_386_TLS_LDM
:
15623 case BFD_RELOC_386_TLS_LDO_32
:
15624 case BFD_RELOC_386_TLS_IE_32
:
15625 case BFD_RELOC_386_TLS_IE
:
15626 case BFD_RELOC_386_TLS_GOTIE
:
15627 case BFD_RELOC_386_TLS_LE_32
:
15628 case BFD_RELOC_386_TLS_LE
:
15629 case BFD_RELOC_386_TLS_GOTDESC
:
15630 case BFD_RELOC_386_TLS_DESC_CALL
:
15631 case BFD_RELOC_X86_64_TLSGD
:
15632 case BFD_RELOC_X86_64_TLSLD
:
15633 case BFD_RELOC_X86_64_DTPOFF32
:
15634 case BFD_RELOC_X86_64_DTPOFF64
:
15635 case BFD_RELOC_X86_64_GOTTPOFF
:
15636 case BFD_RELOC_X86_64_TPOFF32
:
15637 case BFD_RELOC_X86_64_TPOFF64
:
15638 case BFD_RELOC_X86_64_GOTOFF64
:
15639 case BFD_RELOC_X86_64_GOTPC32
:
15640 case BFD_RELOC_X86_64_GOT64
:
15641 case BFD_RELOC_X86_64_GOTPCREL64
:
15642 case BFD_RELOC_X86_64_GOTPC64
:
15643 case BFD_RELOC_X86_64_GOTPLT64
:
15644 case BFD_RELOC_X86_64_PLTOFF64
:
15645 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15646 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15647 case BFD_RELOC_RVA
:
15648 case BFD_RELOC_VTABLE_ENTRY
:
15649 case BFD_RELOC_VTABLE_INHERIT
:
15651 case BFD_RELOC_32_SECREL
:
15652 case BFD_RELOC_16_SECIDX
:
15654 code
= fixp
->fx_r_type
;
15656 case BFD_RELOC_X86_64_32S
:
15657 if (!fixp
->fx_pcrel
)
15659 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15660 code
= fixp
->fx_r_type
;
15663 /* Fall through. */
15665 if (fixp
->fx_pcrel
)
15667 switch (fixp
->fx_size
)
15670 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15671 _("can not do %d byte pc-relative relocation"),
15673 code
= BFD_RELOC_32_PCREL
;
15675 case 1: code
= BFD_RELOC_8_PCREL
; break;
15676 case 2: code
= BFD_RELOC_16_PCREL
; break;
15677 case 4: code
= BFD_RELOC_32_PCREL
; break;
15679 case 8: code
= BFD_RELOC_64_PCREL
; break;
15685 switch (fixp
->fx_size
)
15688 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15689 _("can not do %d byte relocation"),
15691 code
= BFD_RELOC_32
;
15693 case 1: code
= BFD_RELOC_8
; break;
15694 case 2: code
= BFD_RELOC_16
; break;
15695 case 4: code
= BFD_RELOC_32
; break;
15697 case 8: code
= BFD_RELOC_64
; break;
15704 if ((code
== BFD_RELOC_32
15705 || code
== BFD_RELOC_32_PCREL
15706 || code
== BFD_RELOC_X86_64_32S
)
15708 && fixp
->fx_addsy
== GOT_symbol
)
15711 code
= BFD_RELOC_386_GOTPC
;
15713 code
= BFD_RELOC_X86_64_GOTPC32
;
15715 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15717 && fixp
->fx_addsy
== GOT_symbol
)
15719 code
= BFD_RELOC_X86_64_GOTPC64
;
15722 rel
= XNEW (arelent
);
15723 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15724 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15726 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15728 if (!use_rela_relocations
)
15730 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15731 vtable entry to be used in the relocation's section offset. */
15732 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15733 rel
->address
= fixp
->fx_offset
;
15734 #if defined (OBJ_COFF) && defined (TE_PE)
15735 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15736 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15741 /* Use the rela in 64bit mode. */
15744 if (disallow_64bit_reloc
)
15747 case BFD_RELOC_X86_64_DTPOFF64
:
15748 case BFD_RELOC_X86_64_TPOFF64
:
15749 case BFD_RELOC_64_PCREL
:
15750 case BFD_RELOC_X86_64_GOTOFF64
:
15751 case BFD_RELOC_X86_64_GOT64
:
15752 case BFD_RELOC_X86_64_GOTPCREL64
:
15753 case BFD_RELOC_X86_64_GOTPC64
:
15754 case BFD_RELOC_X86_64_GOTPLT64
:
15755 case BFD_RELOC_X86_64_PLTOFF64
:
15756 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15757 _("cannot represent relocation type %s in x32 mode"),
15758 bfd_get_reloc_code_name (code
));
15764 if (!fixp
->fx_pcrel
)
15765 rel
->addend
= fixp
->fx_offset
;
15769 case BFD_RELOC_X86_64_PLT32
:
15770 case BFD_RELOC_X86_64_GOT32
:
15771 case BFD_RELOC_X86_64_GOTPCREL
:
15772 case BFD_RELOC_X86_64_GOTPCRELX
:
15773 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15774 case BFD_RELOC_X86_64_TLSGD
:
15775 case BFD_RELOC_X86_64_TLSLD
:
15776 case BFD_RELOC_X86_64_GOTTPOFF
:
15777 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15778 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15779 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15782 rel
->addend
= (section
->vma
15784 + fixp
->fx_addnumber
15785 + md_pcrel_from (fixp
));
15790 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15791 if (rel
->howto
== NULL
)
15793 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15794 _("cannot represent relocation type %s"),
15795 bfd_get_reloc_code_name (code
));
15796 /* Set howto to a garbage value so that we can keep going. */
15797 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15798 gas_assert (rel
->howto
!= NULL
);
15804 #include "tc-i386-intel.c"
15807 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15809 int saved_naked_reg
;
15810 char saved_register_dot
;
15812 saved_naked_reg
= allow_naked_reg
;
15813 allow_naked_reg
= 1;
15814 saved_register_dot
= register_chars
['.'];
15815 register_chars
['.'] = '.';
15816 allow_pseudo_reg
= 1;
15817 expression_and_evaluate (exp
);
15818 allow_pseudo_reg
= 0;
15819 register_chars
['.'] = saved_register_dot
;
15820 allow_naked_reg
= saved_naked_reg
;
15822 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15824 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15826 exp
->X_op
= O_constant
;
15827 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15828 .dw2_regnum
[flag_code
>> 1];
15831 exp
->X_op
= O_illegal
;
15836 tc_x86_frame_initial_instructions (void)
15838 static unsigned int sp_regno
[2];
15840 if (!sp_regno
[flag_code
>> 1])
15842 char *saved_input
= input_line_pointer
;
15843 char sp
[][4] = {"esp", "rsp"};
15846 input_line_pointer
= sp
[flag_code
>> 1];
15847 tc_x86_parse_to_dw2regnum (&exp
);
15848 gas_assert (exp
.X_op
== O_constant
);
15849 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15850 input_line_pointer
= saved_input
;
15853 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15854 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15858 x86_dwarf2_addr_size (void)
15860 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15861 if (x86_elf_abi
== X86_64_X32_ABI
)
15864 return bfd_arch_bits_per_address (stdoutput
) / 8;
15868 i386_elf_section_type (const char *str
, size_t len
)
15870 if (flag_code
== CODE_64BIT
15871 && len
== sizeof ("unwind") - 1
15872 && startswith (str
, "unwind"))
15873 return SHT_X86_64_UNWIND
;
15880 i386_solaris_fix_up_eh_frame (segT sec
)
15882 if (flag_code
== CODE_64BIT
)
15883 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15889 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15893 exp
.X_op
= O_secrel
;
15894 exp
.X_add_symbol
= symbol
;
15895 exp
.X_add_number
= 0;
15896 emit_expr (&exp
, size
);
15900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15901 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15904 x86_64_section_letter (int letter
, const char **ptr_msg
)
15906 if (flag_code
== CODE_64BIT
)
15909 return SHF_X86_64_LARGE
;
15911 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15914 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15919 handle_large_common (int small ATTRIBUTE_UNUSED
)
15921 if (flag_code
!= CODE_64BIT
)
15923 s_comm_internal (0, elf_common_parse
);
15924 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15928 static segT lbss_section
;
15929 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15930 asection
*saved_bss_section
= bss_section
;
15932 if (lbss_section
== NULL
)
15934 flagword applicable
;
15935 segT seg
= now_seg
;
15936 subsegT subseg
= now_subseg
;
15938 /* The .lbss section is for local .largecomm symbols. */
15939 lbss_section
= subseg_new (".lbss", 0);
15940 applicable
= bfd_applicable_section_flags (stdoutput
);
15941 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15942 seg_info (lbss_section
)->bss
= 1;
15944 subseg_set (seg
, subseg
);
15947 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15948 bss_section
= lbss_section
;
15950 s_comm_internal (0, elf_common_parse
);
15952 elf_com_section_ptr
= saved_com_section_ptr
;
15953 bss_section
= saved_bss_section
;
15956 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */