1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 /* We support four different modes. FLAG_CODE variable is used to distinguish
590 static enum flag_code flag_code
;
591 static unsigned int object_64bit
;
592 static unsigned int disallow_64bit_reloc
;
593 static int use_rela_relocations
= 0;
594 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
595 static const char *tls_get_addr
;
597 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
598 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
599 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
601 /* The ELF ABI to use. */
609 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
612 #if defined (TE_PE) || defined (TE_PEP)
613 /* Use big object file format. */
614 static int use_big_obj
= 0;
617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
618 /* 1 if generating code for a shared library. */
619 static int shared
= 0;
621 unsigned int x86_sframe_cfa_sp_reg
;
622 /* The other CFA base register for SFrame stack trace info. */
623 unsigned int x86_sframe_cfa_fp_reg
;
624 unsigned int x86_sframe_cfa_ra_reg
;
628 /* 1 for intel syntax,
630 static int intel_syntax
= 0;
632 static enum x86_64_isa
634 amd64
= 1, /* AMD64 ISA. */
635 intel64
/* Intel64 ISA. */
638 /* 1 for intel mnemonic,
639 0 if att mnemonic. */
640 static int intel_mnemonic
= !SYSV386_COMPAT
;
642 /* 1 if pseudo registers are permitted. */
643 static int allow_pseudo_reg
= 0;
645 /* 1 if register prefix % not required. */
646 static int allow_naked_reg
= 0;
648 /* 1 if the assembler should add BND prefix for all control-transferring
649 instructions supporting it, even if this prefix wasn't specified
651 static int add_bnd_prefix
= 0;
653 /* 1 if pseudo index register, eiz/riz, is allowed . */
654 static int allow_index_reg
= 0;
656 /* 1 if the assembler should ignore LOCK prefix, even if it was
657 specified explicitly. */
658 static int omit_lock_prefix
= 0;
660 /* 1 if the assembler should encode lfence, mfence, and sfence as
661 "lock addl $0, (%{re}sp)". */
662 static int avoid_fence
= 0;
664 /* 1 if lfence should be inserted after every load. */
665 static int lfence_after_load
= 0;
667 /* Non-zero if lfence should be inserted before indirect branch. */
668 static enum lfence_before_indirect_branch_kind
670 lfence_branch_none
= 0,
671 lfence_branch_register
,
672 lfence_branch_memory
,
675 lfence_before_indirect_branch
;
677 /* Non-zero if lfence should be inserted before ret. */
678 static enum lfence_before_ret_kind
680 lfence_before_ret_none
= 0,
681 lfence_before_ret_not
,
682 lfence_before_ret_or
,
683 lfence_before_ret_shl
687 /* Types of previous instruction is .byte or prefix. */
702 /* 1 if the assembler should generate relax relocations. */
704 static int generate_relax_relocations
705 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
707 static enum check_kind
713 sse_check
, operand_check
= check_warning
;
715 /* Non-zero if branches should be aligned within power of 2 boundary. */
716 static int align_branch_power
= 0;
718 /* Types of branches to align. */
719 enum align_branch_kind
721 align_branch_none
= 0,
722 align_branch_jcc
= 1,
723 align_branch_fused
= 2,
724 align_branch_jmp
= 3,
725 align_branch_call
= 4,
726 align_branch_indirect
= 5,
730 /* Type bits of branches to align. */
731 enum align_branch_bit
733 align_branch_jcc_bit
= 1 << align_branch_jcc
,
734 align_branch_fused_bit
= 1 << align_branch_fused
,
735 align_branch_jmp_bit
= 1 << align_branch_jmp
,
736 align_branch_call_bit
= 1 << align_branch_call
,
737 align_branch_indirect_bit
= 1 << align_branch_indirect
,
738 align_branch_ret_bit
= 1 << align_branch_ret
741 static unsigned int align_branch
= (align_branch_jcc_bit
742 | align_branch_fused_bit
743 | align_branch_jmp_bit
);
745 /* Types of condition jump used by macro-fusion. */
748 mf_jcc_jo
= 0, /* base opcode 0x70 */
749 mf_jcc_jc
, /* base opcode 0x72 */
750 mf_jcc_je
, /* base opcode 0x74 */
751 mf_jcc_jna
, /* base opcode 0x76 */
752 mf_jcc_js
, /* base opcode 0x78 */
753 mf_jcc_jp
, /* base opcode 0x7a */
754 mf_jcc_jl
, /* base opcode 0x7c */
755 mf_jcc_jle
, /* base opcode 0x7e */
758 /* Types of compare flag-modifying insntructions used by macro-fusion. */
761 mf_cmp_test_and
, /* test/cmp */
762 mf_cmp_alu_cmp
, /* add/sub/cmp */
763 mf_cmp_incdec
/* inc/dec */
766 /* The maximum padding size for fused jcc. CMP like instruction can
767 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
769 #define MAX_FUSED_JCC_PADDING_SIZE 20
771 /* The maximum number of prefixes added for an instruction. */
772 static unsigned int align_branch_prefix_size
= 5;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
779 static int optimize
= 0;
782 1. Clear the REX_W bit with register operand if possible.
783 2. Above plus use 128bit vector instruction to clear the full vector
785 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
788 static int optimize_for_space
= 0;
790 /* Register prefix used for error message. */
791 static const char *register_prefix
= "%";
793 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
794 leave, push, and pop instructions so that gcc has the same stack
795 frame as in 32 bit mode. */
796 static char stackop_size
= '\0';
798 /* Non-zero to optimize code alignment. */
799 int optimize_align_code
= 1;
801 /* Non-zero to quieten some warnings. */
802 static int quiet_warnings
= 0;
804 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
805 static bool pre_386_16bit_warned
;
808 static const char *cpu_arch_name
= NULL
;
809 static char *cpu_sub_arch_name
= NULL
;
811 /* CPU feature flags. */
812 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
814 /* If we have selected a cpu we are generating instructions for. */
815 static int cpu_arch_tune_set
= 0;
817 /* Cpu we are generating instructions for. */
818 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
820 /* CPU instruction set architecture used. */
821 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
823 /* CPU feature flags of instruction set architecture used. */
824 i386_cpu_flags cpu_arch_isa_flags
;
826 /* If set, conditional jumps are not automatically promoted to handle
827 larger than a byte offset. */
828 static bool no_cond_jump_promotion
= false;
830 /* This will be set from an expression parser hook if there's any
831 applicable operator involved in an expression. */
834 expr_operator_present
,
838 /* Encode SSE instructions with VEX prefix. */
839 static unsigned int sse2avx
;
841 /* Encode aligned vector move as unaligned vector move. */
842 static unsigned int use_unaligned_vector_move
;
844 /* Maximum permitted vector size. */
845 #define VSZ_DEFAULT VSZ512
846 static unsigned int vector_size
= VSZ_DEFAULT
;
848 /* Encode scalar AVX instructions with specific vector length. */
855 /* Encode VEX WIG instructions with specific vex.w. */
862 /* Encode scalar EVEX LIG instructions with specific vector length. */
870 /* Encode EVEX WIG instructions with specific evex.w. */
877 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
878 static enum rc_type evexrcig
= rne
;
880 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
881 static symbolS
*GOT_symbol
;
883 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
884 unsigned int x86_dwarf2_return_column
;
886 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
887 int x86_cie_data_alignment
;
889 /* Interface to relax_segment.
890 There are 3 major relax states for 386 jump insns because the
891 different types of jumps add different sizes to frags when we're
892 figuring out what sort of jump to choose to reach a given label.
894 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
895 branches which are handled by md_estimate_size_before_relax() and
896 i386_generic_table_relax_frag(). */
899 #define UNCOND_JUMP 0
901 #define COND_JUMP86 2
902 #define BRANCH_PADDING 3
903 #define BRANCH_PREFIX 4
904 #define FUSED_JCC_PADDING 5
909 #define SMALL16 (SMALL | CODE16)
911 #define BIG16 (BIG | CODE16)
915 #define INLINE __inline__
921 #define ENCODE_RELAX_STATE(type, size) \
922 ((relax_substateT) (((type) << 2) | (size)))
923 #define TYPE_FROM_RELAX_STATE(s) \
925 #define DISP_SIZE_FROM_RELAX_STATE(s) \
926 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
928 /* This table is used by relax_frag to promote short jumps to long
929 ones where necessary. SMALL (short) jumps may be promoted to BIG
930 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
931 don't allow a short jump in a 32 bit code segment to be promoted to
932 a 16 bit offset jump because it's slower (requires data size
933 prefix), and doesn't work, unless the destination is in the bottom
934 64k of the code segment (The top 16 bits of eip are zeroed). */
936 const relax_typeS md_relax_table
[] =
939 1) most positive reach of this state,
940 2) most negative reach of this state,
941 3) how many bytes this mode will have in the variable part of the frag
942 4) which index into the table to try if we can't fit into this one. */
944 /* UNCOND_JUMP states. */
945 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
946 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
947 /* dword jmp adds 4 bytes to frag:
948 0 extra opcode bytes, 4 displacement bytes. */
950 /* word jmp adds 2 byte2 to frag:
951 0 extra opcode bytes, 2 displacement bytes. */
954 /* COND_JUMP states. */
955 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
956 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
957 /* dword conditionals adds 5 bytes to frag:
958 1 extra opcode byte, 4 displacement bytes. */
960 /* word conditionals add 3 bytes to frag:
961 1 extra opcode byte, 2 displacement bytes. */
964 /* COND_JUMP86 states. */
965 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
966 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
967 /* dword conditionals adds 5 bytes to frag:
968 1 extra opcode byte, 4 displacement bytes. */
970 /* word conditionals add 4 bytes to frag:
971 1 displacement byte and a 3 byte long branch insn. */
975 #define ARCH(n, t, f, s) \
976 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
978 #define SUBARCH(n, e, d, s) \
979 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
980 CPU_ ## d ## _FLAGS }
981 #define VECARCH(n, e, d, v) \
982 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
983 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
985 static const arch_entry cpu_arch
[] =
987 /* Do not replace the first two entries - i386_target_format() and
988 set_cpu_arch() rely on them being there in this order. */
989 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
990 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
991 ARCH (i8086
, UNKNOWN
, NONE
, false),
992 ARCH (i186
, UNKNOWN
, 186, false),
993 ARCH (i286
, UNKNOWN
, 286, false),
994 ARCH (i386
, I386
, 386, false),
995 ARCH (i486
, I486
, 486, false),
996 ARCH (i586
, PENTIUM
, 586, false),
997 ARCH (i686
, PENTIUMPRO
, 686, false),
998 ARCH (pentium
, PENTIUM
, 586, false),
999 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
1000 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
1001 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
1002 ARCH (pentium4
, PENTIUM4
, P4
, false),
1003 ARCH (prescott
, NOCONA
, CORE
, false),
1004 ARCH (nocona
, NOCONA
, NOCONA
, false),
1005 ARCH (yonah
, CORE
, CORE
, true),
1006 ARCH (core
, CORE
, CORE
, false),
1007 ARCH (merom
, CORE2
, CORE2
, true),
1008 ARCH (core2
, CORE2
, CORE2
, false),
1009 ARCH (corei7
, COREI7
, COREI7
, false),
1010 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1011 ARCH (k6
, K6
, K6
, false),
1012 ARCH (k6_2
, K6
, K6_2
, false),
1013 ARCH (athlon
, ATHLON
, ATHLON
, false),
1014 ARCH (sledgehammer
, K8
, K8
, true),
1015 ARCH (opteron
, K8
, K8
, false),
1016 ARCH (k8
, K8
, K8
, false),
1017 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1018 ARCH (bdver1
, BD
, BDVER1
, false),
1019 ARCH (bdver2
, BD
, BDVER2
, false),
1020 ARCH (bdver3
, BD
, BDVER3
, false),
1021 ARCH (bdver4
, BD
, BDVER4
, false),
1022 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1023 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1024 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1025 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1026 ARCH (btver1
, BT
, BTVER1
, false),
1027 ARCH (btver2
, BT
, BTVER2
, false),
1029 SUBARCH (8087, 8087, ANY_8087
, false),
1030 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1031 SUBARCH (287, 287, ANY_287
, false),
1032 SUBARCH (387, 387, ANY_387
, false),
1033 SUBARCH (687, 687, ANY_687
, false),
1034 SUBARCH (cmov
, CMOV
, CMOV
, false),
1035 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1036 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1037 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1038 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1039 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1040 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1041 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1042 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1043 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1044 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1045 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1046 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1047 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1048 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1049 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1050 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1051 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1052 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1053 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1054 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1055 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1056 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1057 SUBARCH (smx
, SMX
, SMX
, false),
1058 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1059 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1060 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1061 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1062 SUBARCH (aes
, AES
, ANY_AES
, false),
1063 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1064 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1065 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1066 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1067 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1068 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1069 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1070 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1071 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1072 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1073 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1074 SUBARCH (cx16
, CX16
, CX16
, false),
1075 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1076 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1077 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1078 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1079 SUBARCH (hle
, HLE
, HLE
, false),
1080 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1081 SUBARCH (tsx
, TSX
, TSX
, false),
1082 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1083 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1084 SUBARCH (nop
, NOP
, NOP
, false),
1085 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1086 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1087 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1088 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1089 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1090 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1091 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1092 SUBARCH (abm
, ABM
, ABM
, false),
1093 SUBARCH (bmi
, BMI
, BMI
, false),
1094 SUBARCH (tbm
, TBM
, TBM
, false),
1095 SUBARCH (adx
, ADX
, ADX
, false),
1096 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1097 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1098 SUBARCH (smap
, SMAP
, SMAP
, false),
1099 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1100 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1101 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1102 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1103 SUBARCH (se1
, SE1
, SE1
, false),
1104 SUBARCH (clwb
, CLWB
, CLWB
, false),
1105 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1106 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1107 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1108 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1109 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1110 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1111 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1112 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1113 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1114 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1115 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1116 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1117 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1118 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1119 SUBARCH (ibt
, IBT
, IBT
, false),
1120 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1121 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1122 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1123 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1124 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1125 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1126 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1127 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1128 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1129 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1130 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1131 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1132 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1133 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1134 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1135 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1136 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1137 ANY_AVX512_VP2INTERSECT
, reset
),
1138 SUBARCH (tdx
, TDX
, TDX
, false),
1139 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1140 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1141 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1142 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1143 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1144 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1145 SUBARCH (kl
, KL
, ANY_KL
, false),
1146 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1147 SUBARCH (uintr
, UINTR
, UINTR
, false),
1148 SUBARCH (hreset
, HRESET
, HRESET
, false),
1149 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1150 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1151 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1152 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1153 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1154 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1155 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1156 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1157 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1158 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1159 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1160 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1161 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1162 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1163 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1164 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1165 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1166 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1173 /* Like s_lcomm_internal in gas/read.c but the alignment string
1174 is allowed to be optional. */
1177 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1184 && *input_line_pointer
== ',')
1186 align
= parse_align (needs_align
- 1);
1188 if (align
== (addressT
) -1)
1203 bss_alloc (symbolP
, size
, align
);
1208 pe_lcomm (int needs_align
)
1210 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1214 const pseudo_typeS md_pseudo_table
[] =
1216 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1217 {"align", s_align_bytes
, 0},
1219 {"align", s_align_ptwo
, 0},
1221 {"arch", set_cpu_arch
, 0},
1225 {"lcomm", pe_lcomm
, 1},
1227 {"ffloat", float_cons
, 'f'},
1228 {"dfloat", float_cons
, 'd'},
1229 {"tfloat", float_cons
, 'x'},
1230 {"hfloat", float_cons
, 'h'},
1231 {"bfloat16", float_cons
, 'b'},
1233 {"slong", signed_cons
, 4},
1234 {"insn", s_insn
, 0},
1235 {"noopt", s_ignore
, 0},
1236 {"optim", s_ignore
, 0},
1237 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1238 {"code16", set_code_flag
, CODE_16BIT
},
1239 {"code32", set_code_flag
, CODE_32BIT
},
1241 {"code64", set_code_flag
, CODE_64BIT
},
1243 {"intel_syntax", set_intel_syntax
, 1},
1244 {"att_syntax", set_intel_syntax
, 0},
1245 {"intel_mnemonic", set_intel_mnemonic
, 1},
1246 {"att_mnemonic", set_intel_mnemonic
, 0},
1247 {"allow_index_reg", set_allow_index_reg
, 1},
1248 {"disallow_index_reg", set_allow_index_reg
, 0},
1249 {"sse_check", set_check
, 0},
1250 {"operand_check", set_check
, 1},
1251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1252 {"largecomm", handle_large_common
, 0},
1254 {"file", dwarf2_directive_file
, 0},
1255 {"loc", dwarf2_directive_loc
, 0},
1256 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1259 {"secrel32", pe_directive_secrel
, 0},
1260 {"secidx", pe_directive_secidx
, 0},
1265 /* For interface with expression (). */
1266 extern char *input_line_pointer
;
1268 /* Hash table for instruction mnemonic lookup. */
1269 static htab_t op_hash
;
1271 /* Hash table for register lookup. */
1272 static htab_t reg_hash
;
1274 /* Various efficient no-op patterns for aligning code labels.
1275 Note: Don't try to assemble the instructions in the comments.
1276 0L and 0w are not legal. */
1277 static const unsigned char f32_1
[] =
1279 static const unsigned char f32_2
[] =
1280 {0x66,0x90}; /* xchg %ax,%ax */
1281 static const unsigned char f32_3
[] =
1282 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1283 static const unsigned char f32_4
[] =
1284 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1285 static const unsigned char f32_6
[] =
1286 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1287 static const unsigned char f32_7
[] =
1288 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1289 static const unsigned char f16_3
[] =
1290 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1291 static const unsigned char f16_4
[] =
1292 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1293 static const unsigned char jump_disp8
[] =
1294 {0xeb}; /* jmp disp8 */
1295 static const unsigned char jump32_disp32
[] =
1296 {0xe9}; /* jmp disp32 */
1297 static const unsigned char jump16_disp32
[] =
1298 {0x66,0xe9}; /* jmp disp32 */
1299 /* 32-bit NOPs patterns. */
1300 static const unsigned char *const f32_patt
[] = {
1301 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1303 /* 16-bit NOPs patterns. */
1304 static const unsigned char *const f16_patt
[] = {
1305 f32_1
, f32_2
, f16_3
, f16_4
1307 /* nopl (%[re]ax) */
1308 static const unsigned char alt_3
[] =
1310 /* nopl 0(%[re]ax) */
1311 static const unsigned char alt_4
[] =
1312 {0x0f,0x1f,0x40,0x00};
1313 /* nopl 0(%[re]ax,%[re]ax,1) */
1314 static const unsigned char alt_5
[] =
1315 {0x0f,0x1f,0x44,0x00,0x00};
1316 /* nopw 0(%[re]ax,%[re]ax,1) */
1317 static const unsigned char alt_6
[] =
1318 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1319 /* nopl 0L(%[re]ax) */
1320 static const unsigned char alt_7
[] =
1321 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1322 /* nopl 0L(%[re]ax,%[re]ax,1) */
1323 static const unsigned char alt_8
[] =
1324 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1325 /* nopw 0L(%[re]ax,%[re]ax,1) */
1326 static const unsigned char alt_9
[] =
1327 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1328 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1329 static const unsigned char alt_10
[] =
1330 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1331 /* data16 nopw %cs:0L(%eax,%eax,1) */
1332 static const unsigned char alt_11
[] =
1333 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1334 /* 32-bit and 64-bit NOPs patterns. */
1335 static const unsigned char *const alt_patt
[] = {
1336 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1337 alt_9
, alt_10
, alt_11
1340 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1341 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1344 i386_output_nops (char *where
, const unsigned char *const *patt
,
1345 int count
, int max_single_nop_size
)
1348 /* Place the longer NOP first. */
1351 const unsigned char *nops
;
1353 if (max_single_nop_size
< 1)
1355 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1356 max_single_nop_size
);
1360 nops
= patt
[max_single_nop_size
- 1];
1362 /* Use the smaller one if the requsted one isn't available. */
1365 max_single_nop_size
--;
1366 nops
= patt
[max_single_nop_size
- 1];
1369 last
= count
% max_single_nop_size
;
1372 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1373 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1377 nops
= patt
[last
- 1];
1380 /* Use the smaller one plus one-byte NOP if the needed one
1383 nops
= patt
[last
- 1];
1384 memcpy (where
+ offset
, nops
, last
);
1385 where
[offset
+ last
] = *patt
[0];
1388 memcpy (where
+ offset
, nops
, last
);
1393 fits_in_imm7 (offsetT num
)
1395 return (num
& 0x7f) == num
;
1399 fits_in_imm31 (offsetT num
)
1401 return (num
& 0x7fffffff) == num
;
1404 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1405 single NOP instruction LIMIT. */
1408 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1410 const unsigned char *const *patt
= NULL
;
1411 int max_single_nop_size
;
1412 /* Maximum number of NOPs before switching to jump over NOPs. */
1413 int max_number_of_nops
;
1415 switch (fragP
->fr_type
)
1420 case rs_machine_dependent
:
1421 /* Allow NOP padding for jumps and calls. */
1422 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1423 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1430 /* We need to decide which NOP sequence to use for 32bit and
1431 64bit. When -mtune= is used:
1433 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1434 PROCESSOR_GENERIC32, f32_patt will be used.
1435 2. For the rest, alt_patt will be used.
1437 When -mtune= isn't used, alt_patt will be used if
1438 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1441 When -march= or .arch is used, we can't use anything beyond
1442 cpu_arch_isa_flags. */
1444 if (flag_code
== CODE_16BIT
)
1447 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1448 /* Limit number of NOPs to 2 in 16-bit mode. */
1449 max_number_of_nops
= 2;
1453 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1455 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1456 switch (cpu_arch_tune
)
1458 case PROCESSOR_UNKNOWN
:
1459 /* We use cpu_arch_isa_flags to check if we SHOULD
1460 optimize with nops. */
1461 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1466 case PROCESSOR_PENTIUM4
:
1467 case PROCESSOR_NOCONA
:
1468 case PROCESSOR_CORE
:
1469 case PROCESSOR_CORE2
:
1470 case PROCESSOR_COREI7
:
1471 case PROCESSOR_GENERIC64
:
1473 case PROCESSOR_ATHLON
:
1475 case PROCESSOR_AMDFAM10
:
1477 case PROCESSOR_ZNVER
:
1481 case PROCESSOR_I386
:
1482 case PROCESSOR_I486
:
1483 case PROCESSOR_PENTIUM
:
1484 case PROCESSOR_PENTIUMPRO
:
1485 case PROCESSOR_IAMCU
:
1486 case PROCESSOR_GENERIC32
:
1489 case PROCESSOR_NONE
:
1495 switch (fragP
->tc_frag_data
.tune
)
1497 case PROCESSOR_UNKNOWN
:
1498 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1499 PROCESSOR_UNKNOWN. */
1503 case PROCESSOR_I386
:
1504 case PROCESSOR_I486
:
1505 case PROCESSOR_PENTIUM
:
1506 case PROCESSOR_IAMCU
:
1508 case PROCESSOR_ATHLON
:
1510 case PROCESSOR_AMDFAM10
:
1512 case PROCESSOR_ZNVER
:
1514 case PROCESSOR_GENERIC32
:
1515 /* We use cpu_arch_isa_flags to check if we CAN optimize
1517 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1522 case PROCESSOR_PENTIUMPRO
:
1523 case PROCESSOR_PENTIUM4
:
1524 case PROCESSOR_NOCONA
:
1525 case PROCESSOR_CORE
:
1526 case PROCESSOR_CORE2
:
1527 case PROCESSOR_COREI7
:
1528 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1533 case PROCESSOR_GENERIC64
:
1536 case PROCESSOR_NONE
:
1541 if (patt
== f32_patt
)
1543 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1544 /* Limit number of NOPs to 2 for older processors. */
1545 max_number_of_nops
= 2;
1549 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1550 /* Limit number of NOPs to 7 for newer processors. */
1551 max_number_of_nops
= 7;
1556 limit
= max_single_nop_size
;
1558 if (fragP
->fr_type
== rs_fill_nop
)
1560 /* Output NOPs for .nop directive. */
1561 if (limit
> max_single_nop_size
)
1563 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1564 _("invalid single nop size: %d "
1565 "(expect within [0, %d])"),
1566 limit
, max_single_nop_size
);
1570 else if (fragP
->fr_type
!= rs_machine_dependent
)
1571 fragP
->fr_var
= count
;
1573 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1575 /* Generate jump over NOPs. */
1576 offsetT disp
= count
- 2;
1577 if (fits_in_imm7 (disp
))
1579 /* Use "jmp disp8" if possible. */
1581 where
[0] = jump_disp8
[0];
1587 unsigned int size_of_jump
;
1589 if (flag_code
== CODE_16BIT
)
1591 where
[0] = jump16_disp32
[0];
1592 where
[1] = jump16_disp32
[1];
1597 where
[0] = jump32_disp32
[0];
1601 count
-= size_of_jump
+ 4;
1602 if (!fits_in_imm31 (count
))
1604 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1605 _("jump over nop padding out of range"));
1609 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1610 where
+= size_of_jump
+ 4;
1614 /* Generate multiple NOPs. */
1615 i386_output_nops (where
, patt
, count
, limit
);
1619 operand_type_all_zero (const union i386_operand_type
*x
)
1621 switch (ARRAY_SIZE(x
->array
))
1632 return !x
->array
[0];
1639 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1641 switch (ARRAY_SIZE(x
->array
))
1657 x
->bitfield
.class = ClassNone
;
1658 x
->bitfield
.instance
= InstanceNone
;
1662 operand_type_equal (const union i386_operand_type
*x
,
1663 const union i386_operand_type
*y
)
1665 switch (ARRAY_SIZE(x
->array
))
1668 if (x
->array
[2] != y
->array
[2])
1672 if (x
->array
[1] != y
->array
[1])
1676 return x
->array
[0] == y
->array
[0];
1684 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1688 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1689 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1690 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1691 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1692 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1693 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1694 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1695 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1696 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1697 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1699 gas_assert (cpu
< CpuAttrEnums
);
1701 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1704 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1706 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1707 i386_cpu_flags f
= { .array
[0] = 0 };
1709 switch (ARRAY_SIZE(a
.array
))
1712 f
.array
[CpuAttrEnums
/ bps
]
1713 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1714 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1715 f
.array
[CpuAttrEnums
/ bps
+ 1]
1716 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1723 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1729 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1731 switch (ARRAY_SIZE(x
->array
))
1750 return !x
->array
[0];
1757 cpu_flags_equal (const union i386_cpu_flags
*x
,
1758 const union i386_cpu_flags
*y
)
1760 switch (ARRAY_SIZE(x
->array
))
1763 if (x
->array
[4] != y
->array
[4])
1767 if (x
->array
[3] != y
->array
[3])
1771 if (x
->array
[2] != y
->array
[2])
1775 if (x
->array
[1] != y
->array
[1])
1779 return x
->array
[0] == y
->array
[0];
1787 cpu_flags_check_cpu64 (const insn_template
*t
)
1789 return flag_code
== CODE_64BIT
1790 ? !t
->cpu
.bitfield
.cpuno64
1791 : !t
->cpu
.bitfield
.cpu64
;
1794 static INLINE i386_cpu_flags
1795 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1797 switch (ARRAY_SIZE (x
.array
))
1800 x
.array
[4] &= y
.array
[4];
1803 x
.array
[3] &= y
.array
[3];
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_cpu_flags
1821 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[4] |= y
.array
[4];
1829 x
.array
[3] |= y
.array
[3];
1832 x
.array
[2] |= y
.array
[2];
1835 x
.array
[1] |= y
.array
[1];
1838 x
.array
[0] |= y
.array
[0];
1846 static INLINE i386_cpu_flags
1847 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1849 switch (ARRAY_SIZE (x
.array
))
1852 x
.array
[4] &= ~y
.array
[4];
1855 x
.array
[3] &= ~y
.array
[3];
1858 x
.array
[2] &= ~y
.array
[2];
1861 x
.array
[1] &= ~y
.array
[1];
1864 x
.array
[0] &= ~y
.array
[0];
1872 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1874 static INLINE
bool need_evex_encoding (void)
1876 return i
.vec_encoding
== vex_encoding_evex
1877 || i
.vec_encoding
== vex_encoding_evex512
1881 #define CPU_FLAGS_ARCH_MATCH 0x1
1882 #define CPU_FLAGS_64BIT_MATCH 0x2
1884 #define CPU_FLAGS_PERFECT_MATCH \
1885 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1887 /* Return CPU flags match bits. */
1890 cpu_flags_match (const insn_template
*t
)
1892 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1893 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1895 x
.bitfield
.cpu64
= 0;
1896 x
.bitfield
.cpuno64
= 0;
1898 if (cpu_flags_all_zero (&x
))
1900 /* This instruction is available on all archs. */
1901 match
|= CPU_FLAGS_ARCH_MATCH
;
1905 /* This instruction is available only on some archs. */
1906 i386_cpu_flags cpu
= cpu_arch_flags
;
1908 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1909 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1911 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1912 know that EVEX encoding will be needed. */
1913 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1914 && x
.bitfield
.cpuavx512f
)
1916 if (need_evex_encoding ())
1918 x
.bitfield
.cpuavx
= 0;
1919 x
.bitfield
.cpuavx2
= 0;
1921 /* need_evex_encoding() isn't reliable before operands were
1923 else if (i
.operands
)
1925 x
.bitfield
.cpuavx512f
= 0;
1926 x
.bitfield
.cpuavx512vl
= 0;
1927 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1928 x
.bitfield
.cpuavx
= 0;
1933 /* AVX512VL is no standalone feature - match it and then strip it. */
1934 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1936 x
.bitfield
.cpuavx512vl
= 0;
1938 /* AVX and AVX2 present at the same time express an operand size
1939 dependency - strip AVX2 for the purposes here. The operand size
1940 dependent check occurs in check_vecOperands(). */
1941 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1942 x
.bitfield
.cpuavx2
= 0;
1944 cpu
= cpu_flags_and (x
, cpu
);
1945 if (!cpu_flags_all_zero (&cpu
))
1947 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1949 if ((need_evex_encoding ()
1950 ? cpu
.bitfield
.cpuavx512f
1951 : cpu
.bitfield
.cpuavx
)
1952 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1953 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1954 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1955 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1956 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1957 match
|= CPU_FLAGS_ARCH_MATCH
;
1959 else if (x
.bitfield
.cpuavx
)
1961 /* We need to check a few extra flags with AVX. */
1962 if (cpu
.bitfield
.cpuavx
1963 && (!t
->opcode_modifier
.sse2avx
1964 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1965 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1966 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1967 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1968 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1971 match
|= CPU_FLAGS_ARCH_MATCH
;
1972 else if (x
.bitfield
.cpuavx512f
)
1974 /* We need to check a few extra flags with AVX512F. */
1975 if (cpu
.bitfield
.cpuavx512f
1976 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1977 match
|= CPU_FLAGS_ARCH_MATCH
;
1980 match
|= CPU_FLAGS_ARCH_MATCH
;
1986 static INLINE i386_operand_type
1987 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1989 if (x
.bitfield
.class != y
.bitfield
.class)
1990 x
.bitfield
.class = ClassNone
;
1991 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1992 x
.bitfield
.instance
= InstanceNone
;
1994 switch (ARRAY_SIZE (x
.array
))
1997 x
.array
[2] &= y
.array
[2];
2000 x
.array
[1] &= y
.array
[1];
2003 x
.array
[0] &= y
.array
[0];
2011 static INLINE i386_operand_type
2012 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2014 gas_assert (y
.bitfield
.class == ClassNone
);
2015 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2017 switch (ARRAY_SIZE (x
.array
))
2020 x
.array
[2] &= ~y
.array
[2];
2023 x
.array
[1] &= ~y
.array
[1];
2026 x
.array
[0] &= ~y
.array
[0];
2034 static INLINE i386_operand_type
2035 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2037 gas_assert (x
.bitfield
.class == ClassNone
||
2038 y
.bitfield
.class == ClassNone
||
2039 x
.bitfield
.class == y
.bitfield
.class);
2040 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2041 y
.bitfield
.instance
== InstanceNone
||
2042 x
.bitfield
.instance
== y
.bitfield
.instance
);
2044 switch (ARRAY_SIZE (x
.array
))
2047 x
.array
[2] |= y
.array
[2];
2050 x
.array
[1] |= y
.array
[1];
2053 x
.array
[0] |= y
.array
[0];
2061 static INLINE i386_operand_type
2062 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2064 gas_assert (y
.bitfield
.class == ClassNone
);
2065 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2067 switch (ARRAY_SIZE (x
.array
))
2070 x
.array
[2] ^= y
.array
[2];
2073 x
.array
[1] ^= y
.array
[1];
2076 x
.array
[0] ^= y
.array
[0];
2084 static const i386_operand_type anydisp
= {
2085 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2097 operand_type_check (i386_operand_type t
, enum operand_type c
)
2102 return t
.bitfield
.class == Reg
;
2105 return (t
.bitfield
.imm8
2109 || t
.bitfield
.imm32s
2110 || t
.bitfield
.imm64
);
2113 return (t
.bitfield
.disp8
2114 || t
.bitfield
.disp16
2115 || t
.bitfield
.disp32
2116 || t
.bitfield
.disp64
);
2119 return (t
.bitfield
.disp8
2120 || t
.bitfield
.disp16
2121 || t
.bitfield
.disp32
2122 || t
.bitfield
.disp64
2123 || t
.bitfield
.baseindex
);
2132 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2133 between operand GIVEN and opeand WANTED for instruction template T. */
2136 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2139 return !((i
.types
[given
].bitfield
.byte
2140 && !t
->operand_types
[wanted
].bitfield
.byte
)
2141 || (i
.types
[given
].bitfield
.word
2142 && !t
->operand_types
[wanted
].bitfield
.word
)
2143 || (i
.types
[given
].bitfield
.dword
2144 && !t
->operand_types
[wanted
].bitfield
.dword
)
2145 || (i
.types
[given
].bitfield
.qword
2146 && (!t
->operand_types
[wanted
].bitfield
.qword
2147 /* Don't allow 64-bit (memory) operands outside of 64-bit
2148 mode, when they're used where a 64-bit GPR could also
2149 be used. Checking is needed for Intel Syntax only. */
2151 && flag_code
!= CODE_64BIT
2152 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2153 || t
->operand_types
[wanted
].bitfield
.class == Accum
2154 || t
->opcode_modifier
.isstring
))))
2155 || (i
.types
[given
].bitfield
.tbyte
2156 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2159 /* Return 1 if there is no conflict in SIMD register between operand
2160 GIVEN and opeand WANTED for instruction template T. */
2163 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2166 return !((i
.types
[given
].bitfield
.xmmword
2167 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2168 || (i
.types
[given
].bitfield
.ymmword
2169 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2170 || (i
.types
[given
].bitfield
.zmmword
2171 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2172 || (i
.types
[given
].bitfield
.tmmword
2173 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2176 /* Return 1 if there is no conflict in any size between operand GIVEN
2177 and opeand WANTED for instruction template T. */
2180 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2183 return (match_operand_size (t
, wanted
, given
)
2184 && !((i
.types
[given
].bitfield
.unspecified
2185 && !i
.broadcast
.type
2186 && !i
.broadcast
.bytes
2187 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2188 || (i
.types
[given
].bitfield
.fword
2189 && !t
->operand_types
[wanted
].bitfield
.fword
)
2190 /* For scalar opcode templates to allow register and memory
2191 operands at the same time, some special casing is needed
2192 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2193 down-conversion vpmov*. */
2194 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2195 && t
->operand_types
[wanted
].bitfield
.byte
2196 + t
->operand_types
[wanted
].bitfield
.word
2197 + t
->operand_types
[wanted
].bitfield
.dword
2198 + t
->operand_types
[wanted
].bitfield
.qword
2199 > !!t
->opcode_modifier
.broadcast
)
2200 ? (i
.types
[given
].bitfield
.xmmword
2201 || i
.types
[given
].bitfield
.ymmword
2202 || i
.types
[given
].bitfield
.zmmword
)
2203 : !match_simd_size(t
, wanted
, given
))));
2206 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2207 operands for instruction template T, and it has MATCH_REVERSE set if there
2208 is no size conflict on any operands for the template with operands reversed
2209 (and the template allows for reversing in the first place). */
2211 #define MATCH_STRAIGHT 1
2212 #define MATCH_REVERSE 2
2214 static INLINE
unsigned int
2215 operand_size_match (const insn_template
*t
)
2217 unsigned int j
, match
= MATCH_STRAIGHT
;
2219 /* Don't check non-absolute jump instructions. */
2220 if (t
->opcode_modifier
.jump
2221 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2224 /* Check memory and accumulator operand size. */
2225 for (j
= 0; j
< i
.operands
; j
++)
2227 if (i
.types
[j
].bitfield
.class != Reg
2228 && i
.types
[j
].bitfield
.class != RegSIMD
2229 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2232 if (t
->operand_types
[j
].bitfield
.class == Reg
2233 && !match_operand_size (t
, j
, j
))
2239 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2240 && !match_simd_size (t
, j
, j
))
2246 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2247 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2253 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2260 if (!t
->opcode_modifier
.d
)
2263 /* Check reverse. */
2264 gas_assert (i
.operands
>= 2);
2266 for (j
= 0; j
< i
.operands
; j
++)
2268 unsigned int given
= i
.operands
- j
- 1;
2270 /* For FMA4 and XOP insns VEX.W controls just the first two
2271 register operands. */
2272 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2273 given
= j
< 2 ? 1 - j
: j
;
2275 if (t
->operand_types
[j
].bitfield
.class == Reg
2276 && !match_operand_size (t
, j
, given
))
2279 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2280 && !match_simd_size (t
, j
, given
))
2283 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2284 && (!match_operand_size (t
, j
, given
)
2285 || !match_simd_size (t
, j
, given
)))
2288 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2292 return match
| MATCH_REVERSE
;
2296 operand_type_match (i386_operand_type overlap
,
2297 i386_operand_type given
)
2299 i386_operand_type temp
= overlap
;
2301 temp
.bitfield
.unspecified
= 0;
2302 temp
.bitfield
.byte
= 0;
2303 temp
.bitfield
.word
= 0;
2304 temp
.bitfield
.dword
= 0;
2305 temp
.bitfield
.fword
= 0;
2306 temp
.bitfield
.qword
= 0;
2307 temp
.bitfield
.tbyte
= 0;
2308 temp
.bitfield
.xmmword
= 0;
2309 temp
.bitfield
.ymmword
= 0;
2310 temp
.bitfield
.zmmword
= 0;
2311 temp
.bitfield
.tmmword
= 0;
2312 if (operand_type_all_zero (&temp
))
2315 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2319 i
.error
= operand_type_mismatch
;
2323 /* If given types g0 and g1 are registers they must be of the same type
2324 unless the expected operand type register overlap is null.
2325 Intel syntax sized memory operands are also checked here. */
2328 operand_type_register_match (i386_operand_type g0
,
2329 i386_operand_type t0
,
2330 i386_operand_type g1
,
2331 i386_operand_type t1
)
2333 if (g0
.bitfield
.class != Reg
2334 && g0
.bitfield
.class != RegSIMD
2335 && (g0
.bitfield
.unspecified
2336 || !operand_type_check (g0
, anymem
)))
2339 if (g1
.bitfield
.class != Reg
2340 && g1
.bitfield
.class != RegSIMD
2341 && (g1
.bitfield
.unspecified
2342 || !operand_type_check (g1
, anymem
)))
2345 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2346 && g0
.bitfield
.word
== g1
.bitfield
.word
2347 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2348 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2349 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2350 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2351 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2354 /* If expectations overlap in no more than a single size, all is fine. */
2355 g0
= operand_type_and (t0
, t1
);
2356 if (g0
.bitfield
.byte
2360 + g0
.bitfield
.xmmword
2361 + g0
.bitfield
.ymmword
2362 + g0
.bitfield
.zmmword
<= 1)
2365 i
.error
= register_type_mismatch
;
2370 static INLINE
unsigned int
2371 register_number (const reg_entry
*r
)
2373 unsigned int nr
= r
->reg_num
;
2375 if (r
->reg_flags
& RegRex
)
2378 if (r
->reg_flags
& RegVRex
)
2384 static INLINE
unsigned int
2385 mode_from_disp_size (i386_operand_type t
)
2387 if (t
.bitfield
.disp8
)
2389 else if (t
.bitfield
.disp16
2390 || t
.bitfield
.disp32
)
2397 fits_in_signed_byte (addressT num
)
2399 return num
+ 0x80 <= 0xff;
2403 fits_in_unsigned_byte (addressT num
)
2409 fits_in_unsigned_word (addressT num
)
2411 return num
<= 0xffff;
2415 fits_in_signed_word (addressT num
)
2417 return num
+ 0x8000 <= 0xffff;
2421 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2426 return num
+ 0x80000000 <= 0xffffffff;
2428 } /* fits_in_signed_long() */
2431 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2436 return num
<= 0xffffffff;
2438 } /* fits_in_unsigned_long() */
2440 static INLINE valueT
extend_to_32bit_address (addressT num
)
2443 if (fits_in_unsigned_long(num
))
2444 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2446 if (!fits_in_signed_long (num
))
2447 return num
& 0xffffffff;
2454 fits_in_disp8 (offsetT num
)
2456 int shift
= i
.memshift
;
2462 mask
= (1 << shift
) - 1;
2464 /* Return 0 if NUM isn't properly aligned. */
2468 /* Check if NUM will fit in 8bit after shift. */
2469 return fits_in_signed_byte (num
>> shift
);
2473 fits_in_imm4 (offsetT num
)
2475 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2476 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2479 static i386_operand_type
2480 smallest_imm_type (offsetT num
)
2482 i386_operand_type t
;
2484 operand_type_set (&t
, 0);
2485 t
.bitfield
.imm64
= 1;
2487 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2489 /* This code is disabled on the 486 because all the Imm1 forms
2490 in the opcode table are slower on the i486. They're the
2491 versions with the implicitly specified single-position
2492 displacement, which has another syntax if you really want to
2494 t
.bitfield
.imm1
= 1;
2495 t
.bitfield
.imm8
= 1;
2496 t
.bitfield
.imm8s
= 1;
2497 t
.bitfield
.imm16
= 1;
2498 t
.bitfield
.imm32
= 1;
2499 t
.bitfield
.imm32s
= 1;
2501 else if (fits_in_signed_byte (num
))
2503 if (fits_in_unsigned_byte (num
))
2504 t
.bitfield
.imm8
= 1;
2505 t
.bitfield
.imm8s
= 1;
2506 t
.bitfield
.imm16
= 1;
2507 t
.bitfield
.imm32
= 1;
2508 t
.bitfield
.imm32s
= 1;
2510 else if (fits_in_unsigned_byte (num
))
2512 t
.bitfield
.imm8
= 1;
2513 t
.bitfield
.imm16
= 1;
2514 t
.bitfield
.imm32
= 1;
2515 t
.bitfield
.imm32s
= 1;
2517 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2519 t
.bitfield
.imm16
= 1;
2520 t
.bitfield
.imm32
= 1;
2521 t
.bitfield
.imm32s
= 1;
2523 else if (fits_in_signed_long (num
))
2525 t
.bitfield
.imm32
= 1;
2526 t
.bitfield
.imm32s
= 1;
2528 else if (fits_in_unsigned_long (num
))
2529 t
.bitfield
.imm32
= 1;
2535 offset_in_range (offsetT val
, int size
)
2541 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2542 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2544 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2546 case sizeof (val
): return val
;
2550 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2551 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2552 (uint64_t) val
, (uint64_t) (val
& mask
));
2557 static INLINE
const char *insn_name (const insn_template
*t
)
2559 return &i386_mnemonics
[t
->mnem_off
];
2572 a. PREFIX_EXIST if attempting to add a prefix where one from the
2573 same class already exists.
2574 b. PREFIX_LOCK if lock prefix is added.
2575 c. PREFIX_REP if rep/repne prefix is added.
2576 d. PREFIX_DS if ds prefix is added.
2577 e. PREFIX_OTHER if other prefix is added.
2580 static enum PREFIX_GROUP
2581 add_prefix (unsigned int prefix
)
2583 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2586 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2587 && flag_code
== CODE_64BIT
)
2589 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2590 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2591 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2592 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2603 case DS_PREFIX_OPCODE
:
2606 case CS_PREFIX_OPCODE
:
2607 case ES_PREFIX_OPCODE
:
2608 case FS_PREFIX_OPCODE
:
2609 case GS_PREFIX_OPCODE
:
2610 case SS_PREFIX_OPCODE
:
2614 case REPNE_PREFIX_OPCODE
:
2615 case REPE_PREFIX_OPCODE
:
2620 case LOCK_PREFIX_OPCODE
:
2629 case ADDR_PREFIX_OPCODE
:
2633 case DATA_PREFIX_OPCODE
:
2637 if (i
.prefix
[q
] != 0)
2645 i
.prefix
[q
] |= prefix
;
2648 as_bad (_("same type of prefix used twice"));
2654 update_code_flag (int value
, int check
)
2656 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2658 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2660 as_error (_("64bit mode not supported on `%s'."),
2661 cpu_arch_name
? cpu_arch_name
: default_arch
);
2665 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2667 as_error (_("32bit mode not supported on `%s'."),
2668 cpu_arch_name
? cpu_arch_name
: default_arch
);
2672 flag_code
= (enum flag_code
) value
;
2674 stackop_size
= '\0';
2678 set_code_flag (int value
)
2680 update_code_flag (value
, 0);
2684 set_16bit_gcc_code_flag (int new_code_flag
)
2686 flag_code
= (enum flag_code
) new_code_flag
;
2687 if (flag_code
!= CODE_16BIT
)
2689 stackop_size
= LONG_MNEM_SUFFIX
;
2693 set_intel_syntax (int syntax_flag
)
2695 /* Find out if register prefixing is specified. */
2696 int ask_naked_reg
= 0;
2699 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2702 int e
= get_symbol_name (&string
);
2704 if (strcmp (string
, "prefix") == 0)
2706 else if (strcmp (string
, "noprefix") == 0)
2709 as_bad (_("bad argument to syntax directive."));
2710 (void) restore_line_pointer (e
);
2712 demand_empty_rest_of_line ();
2714 intel_syntax
= syntax_flag
;
2716 if (ask_naked_reg
== 0)
2717 allow_naked_reg
= (intel_syntax
2718 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2720 allow_naked_reg
= (ask_naked_reg
< 0);
2722 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2724 register_prefix
= allow_naked_reg
? "" : "%";
2728 set_intel_mnemonic (int mnemonic_flag
)
2730 intel_mnemonic
= mnemonic_flag
;
2734 set_allow_index_reg (int flag
)
2736 allow_index_reg
= flag
;
2740 set_check (int what
)
2742 enum check_kind
*kind
;
2747 kind
= &operand_check
;
2758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2761 int e
= get_symbol_name (&string
);
2763 if (strcmp (string
, "none") == 0)
2765 else if (strcmp (string
, "warning") == 0)
2766 *kind
= check_warning
;
2767 else if (strcmp (string
, "error") == 0)
2768 *kind
= check_error
;
2770 as_bad (_("bad argument to %s_check directive."), str
);
2771 (void) restore_line_pointer (e
);
2774 as_bad (_("missing argument for %s_check directive"), str
);
2776 demand_empty_rest_of_line ();
2780 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2781 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2784 static const char *arch
;
2786 /* Intel MCU is only supported on ELF. */
2792 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2793 use default_arch. */
2794 arch
= cpu_arch_name
;
2796 arch
= default_arch
;
2799 /* If we are targeting Intel MCU, we must enable it. */
2800 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2801 == new_flag
.bitfield
.cpuiamcu
)
2804 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2809 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2811 if (cpu_sub_arch_name
)
2812 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2813 pfx
, name
, (const char *) NULL
);
2815 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2818 static void isa_enable (unsigned int idx
)
2820 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2822 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2824 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2825 cpu_arch_flags
= flags
;
2828 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2831 static void isa_disable (unsigned int idx
)
2833 i386_cpu_flags flags
2834 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2836 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2838 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2839 cpu_arch_flags
= flags
;
2843 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2847 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2849 typedef struct arch_stack_entry
2851 const struct arch_stack_entry
*prev
;
2854 i386_cpu_flags flags
;
2855 i386_cpu_flags isa_flags
;
2856 enum processor_type isa
;
2857 enum flag_code flag_code
;
2858 unsigned int vector_size
;
2860 bool no_cond_jump_promotion
;
2862 static const arch_stack_entry
*arch_stack_top
;
2870 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2872 as_bad (_("missing cpu architecture"));
2873 input_line_pointer
++;
2877 e
= get_symbol_name (&s
);
2880 if (strcmp (string
, "push") == 0)
2882 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2884 top
->name
= cpu_arch_name
;
2885 if (cpu_sub_arch_name
)
2886 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2888 top
->sub_name
= NULL
;
2889 top
->flags
= cpu_arch_flags
;
2890 top
->isa
= cpu_arch_isa
;
2891 top
->isa_flags
= cpu_arch_isa_flags
;
2892 top
->flag_code
= flag_code
;
2893 top
->vector_size
= vector_size
;
2894 top
->stackop_size
= stackop_size
;
2895 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2897 top
->prev
= arch_stack_top
;
2898 arch_stack_top
= top
;
2900 (void) restore_line_pointer (e
);
2901 demand_empty_rest_of_line ();
2905 if (strcmp (string
, "pop") == 0)
2907 const arch_stack_entry
*top
= arch_stack_top
;
2910 as_bad (_(".arch stack is empty"));
2911 else if (top
->flag_code
!= flag_code
2912 || top
->stackop_size
!= stackop_size
)
2914 static const unsigned int bits
[] = {
2920 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2921 bits
[top
->flag_code
],
2922 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2926 arch_stack_top
= top
->prev
;
2928 cpu_arch_name
= top
->name
;
2929 free (cpu_sub_arch_name
);
2930 cpu_sub_arch_name
= top
->sub_name
;
2931 cpu_arch_flags
= top
->flags
;
2932 cpu_arch_isa
= top
->isa
;
2933 cpu_arch_isa_flags
= top
->isa_flags
;
2934 vector_size
= top
->vector_size
;
2935 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2940 (void) restore_line_pointer (e
);
2941 demand_empty_rest_of_line ();
2945 if (strcmp (string
, "default") == 0)
2947 if (strcmp (default_arch
, "iamcu") == 0)
2948 string
= default_arch
;
2951 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2953 cpu_arch_name
= NULL
;
2954 free (cpu_sub_arch_name
);
2955 cpu_sub_arch_name
= NULL
;
2956 cpu_arch_flags
= cpu_unknown_flags
;
2957 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2958 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2959 if (!cpu_arch_tune_set
)
2960 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2962 vector_size
= VSZ_DEFAULT
;
2964 j
= ARRAY_SIZE (cpu_arch
) + 1;
2968 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2970 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2971 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2975 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2977 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2979 as_bad (_("64bit mode not supported on `%s'."),
2981 (void) restore_line_pointer (e
);
2982 ignore_rest_of_line ();
2986 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2988 as_bad (_("32bit mode not supported on `%s'."),
2990 (void) restore_line_pointer (e
);
2991 ignore_rest_of_line ();
2995 cpu_arch_name
= cpu_arch
[j
].name
;
2996 free (cpu_sub_arch_name
);
2997 cpu_sub_arch_name
= NULL
;
2998 cpu_arch_flags
= cpu_arch
[j
].enable
;
2999 cpu_arch_isa
= cpu_arch
[j
].type
;
3000 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
3001 if (!cpu_arch_tune_set
)
3002 cpu_arch_tune
= cpu_arch_isa
;
3004 vector_size
= VSZ_DEFAULT
;
3006 pre_386_16bit_warned
= false;
3010 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
3015 (void) restore_line_pointer (e
);
3017 switch (cpu_arch
[j
].vsz
)
3023 #ifdef SVR4_COMMENT_CHARS
3024 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3026 if (*input_line_pointer
== '/')
3029 ++input_line_pointer
;
3030 switch (get_absolute_expression ())
3032 case 512: vector_size
= VSZ512
; break;
3033 case 256: vector_size
= VSZ256
; break;
3034 case 128: vector_size
= VSZ128
; break;
3036 as_bad (_("Unrecognized vector size specifier"));
3037 ignore_rest_of_line ();
3044 vector_size
= VSZ_DEFAULT
;
3048 demand_empty_rest_of_line ();
3053 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3055 /* Disable an ISA extension. */
3056 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3057 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3058 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3062 if (cpu_arch
[j
].vsz
== vsz_set
)
3063 vector_size
= VSZ_DEFAULT
;
3065 (void) restore_line_pointer (e
);
3066 demand_empty_rest_of_line ();
3071 if (j
== ARRAY_SIZE (cpu_arch
))
3072 as_bad (_("no such architecture: `%s'"), string
);
3074 *input_line_pointer
= e
;
3076 no_cond_jump_promotion
= 0;
3077 if (*input_line_pointer
== ','
3078 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3080 ++input_line_pointer
;
3081 e
= get_symbol_name (&s
);
3084 if (strcmp (string
, "nojumps") == 0)
3085 no_cond_jump_promotion
= 1;
3086 else if (strcmp (string
, "jumps") == 0)
3089 as_bad (_("no such architecture modifier: `%s'"), string
);
3091 (void) restore_line_pointer (e
);
3094 demand_empty_rest_of_line ();
3097 enum bfd_architecture
3100 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3102 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3103 || flag_code
== CODE_64BIT
)
3104 as_fatal (_("Intel MCU is 32bit ELF only"));
3105 return bfd_arch_iamcu
;
3108 return bfd_arch_i386
;
3114 if (startswith (default_arch
, "x86_64"))
3116 if (default_arch
[6] == '\0')
3117 return bfd_mach_x86_64
;
3119 return bfd_mach_x64_32
;
3121 else if (!strcmp (default_arch
, "i386")
3122 || !strcmp (default_arch
, "iamcu"))
3124 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3126 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3127 as_fatal (_("Intel MCU is 32bit ELF only"));
3128 return bfd_mach_i386_iamcu
;
3131 return bfd_mach_i386_i386
;
3134 as_fatal (_("unknown architecture"));
3137 #include "opcodes/i386-tbl.h"
3142 /* Support pseudo prefixes like {disp32}. */
3143 lex_type
['{'] = LEX_BEGIN_NAME
;
3145 /* Initialize op_hash hash table. */
3146 op_hash
= str_htab_create ();
3149 const insn_template
*const *sets
= i386_op_sets
;
3150 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3152 /* Type checks to compensate for the conversion through void * which
3153 occurs during hash table insertion / lookup. */
3154 (void) sizeof (sets
== ¤t_templates
->start
);
3155 (void) sizeof (end
== ¤t_templates
->end
);
3156 for (; sets
< end
; ++sets
)
3157 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3158 as_fatal (_("duplicate %s"), insn_name (*sets
));
3161 /* Initialize reg_hash hash table. */
3162 reg_hash
= str_htab_create ();
3164 const reg_entry
*regtab
;
3165 unsigned int regtab_size
= i386_regtab_size
;
3167 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3169 switch (regtab
->reg_type
.bitfield
.class)
3172 if (regtab
->reg_type
.bitfield
.dword
)
3174 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3177 else if (regtab
->reg_type
.bitfield
.tbyte
)
3179 /* There's no point inserting st(<N>) in the hash table, as
3180 parentheses aren't included in register_chars[] anyway. */
3181 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3188 switch (regtab
->reg_num
)
3190 case 0: reg_es
= regtab
; break;
3191 case 2: reg_ss
= regtab
; break;
3192 case 3: reg_ds
= regtab
; break;
3197 if (!regtab
->reg_num
)
3202 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3203 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3207 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3212 for (c
= 0; c
< 256; c
++)
3214 if (ISDIGIT (c
) || ISLOWER (c
))
3216 mnemonic_chars
[c
] = c
;
3217 register_chars
[c
] = c
;
3218 operand_chars
[c
] = c
;
3220 else if (ISUPPER (c
))
3222 mnemonic_chars
[c
] = TOLOWER (c
);
3223 register_chars
[c
] = mnemonic_chars
[c
];
3224 operand_chars
[c
] = c
;
3226 #ifdef SVR4_COMMENT_CHARS
3227 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3228 operand_chars
[c
] = c
;
3232 operand_chars
[c
] = c
;
3235 mnemonic_chars
['_'] = '_';
3236 mnemonic_chars
['-'] = '-';
3237 mnemonic_chars
['.'] = '.';
3239 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3240 operand_chars
[(unsigned char) *p
] = *p
;
3241 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3242 operand_chars
[(unsigned char) *p
] = *p
;
3245 if (flag_code
== CODE_64BIT
)
3247 #if defined (OBJ_COFF) && defined (TE_PE)
3248 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3251 x86_dwarf2_return_column
= 16;
3253 x86_cie_data_alignment
= -8;
3254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3255 x86_sframe_cfa_sp_reg
= 7;
3256 x86_sframe_cfa_fp_reg
= 6;
3261 x86_dwarf2_return_column
= 8;
3262 x86_cie_data_alignment
= -4;
3265 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3266 can be turned into BRANCH_PREFIX frag. */
3267 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3272 i386_print_statistics (FILE *file
)
3274 htab_print_statistics (file
, "i386 opcode", op_hash
);
3275 htab_print_statistics (file
, "i386 register", reg_hash
);
3281 htab_delete (op_hash
);
3282 htab_delete (reg_hash
);
3287 /* Debugging routines for md_assemble. */
3288 static void pte (insn_template
*);
3289 static void pt (i386_operand_type
);
3290 static void pe (expressionS
*);
3291 static void ps (symbolS
*);
3294 pi (const char *line
, i386_insn
*x
)
3298 fprintf (stdout
, "%s: template ", line
);
3300 fprintf (stdout
, " address: base %s index %s scale %x\n",
3301 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3302 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3303 x
->log2_scale_factor
);
3304 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3305 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3306 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3307 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3308 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3309 (x
->rex
& REX_W
) != 0,
3310 (x
->rex
& REX_R
) != 0,
3311 (x
->rex
& REX_X
) != 0,
3312 (x
->rex
& REX_B
) != 0);
3313 for (j
= 0; j
< x
->operands
; j
++)
3315 fprintf (stdout
, " #%d: ", j
+ 1);
3317 fprintf (stdout
, "\n");
3318 if (x
->types
[j
].bitfield
.class == Reg
3319 || x
->types
[j
].bitfield
.class == RegMMX
3320 || x
->types
[j
].bitfield
.class == RegSIMD
3321 || x
->types
[j
].bitfield
.class == RegMask
3322 || x
->types
[j
].bitfield
.class == SReg
3323 || x
->types
[j
].bitfield
.class == RegCR
3324 || x
->types
[j
].bitfield
.class == RegDR
3325 || x
->types
[j
].bitfield
.class == RegTR
3326 || x
->types
[j
].bitfield
.class == RegBND
)
3327 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3328 if (operand_type_check (x
->types
[j
], imm
))
3330 if (operand_type_check (x
->types
[j
], disp
))
3331 pe (x
->op
[j
].disps
);
3336 pte (insn_template
*t
)
3338 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3339 static const char *const opc_spc
[] = {
3340 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3341 "XOP08", "XOP09", "XOP0A",
3345 fprintf (stdout
, " %d operands ", t
->operands
);
3346 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3347 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3348 if (opc_spc
[t
->opcode_space
])
3349 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3350 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3351 if (t
->extension_opcode
!= None
)
3352 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3353 if (t
->opcode_modifier
.d
)
3354 fprintf (stdout
, "D");
3355 if (t
->opcode_modifier
.w
)
3356 fprintf (stdout
, "W");
3357 fprintf (stdout
, "\n");
3358 for (j
= 0; j
< t
->operands
; j
++)
3360 fprintf (stdout
, " #%d type ", j
+ 1);
3361 pt (t
->operand_types
[j
]);
3362 fprintf (stdout
, "\n");
3369 fprintf (stdout
, " operation %d\n", e
->X_op
);
3370 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3371 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3372 if (e
->X_add_symbol
)
3374 fprintf (stdout
, " add_symbol ");
3375 ps (e
->X_add_symbol
);
3376 fprintf (stdout
, "\n");
3380 fprintf (stdout
, " op_symbol ");
3381 ps (e
->X_op_symbol
);
3382 fprintf (stdout
, "\n");
3389 fprintf (stdout
, "%s type %s%s",
3391 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3392 segment_name (S_GET_SEGMENT (s
)));
3395 static struct type_name
3397 i386_operand_type mask
;
3400 const type_names
[] =
3402 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3403 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3404 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3405 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3406 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3407 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3408 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3409 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3410 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3411 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3412 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3413 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3414 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3415 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3416 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3417 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3418 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3419 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3420 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3421 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3422 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3423 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3424 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3425 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3426 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3427 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3428 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3429 { { .bitfield
= { .class = SReg
} }, "SReg" },
3430 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3431 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3432 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3433 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3434 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3435 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3439 pt (i386_operand_type t
)
3442 i386_operand_type a
;
3444 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3446 a
= operand_type_and (t
, type_names
[j
].mask
);
3447 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3448 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3453 #endif /* DEBUG386 */
3455 static bfd_reloc_code_real_type
3456 reloc (unsigned int size
,
3459 bfd_reloc_code_real_type other
)
3461 if (other
!= NO_RELOC
)
3463 reloc_howto_type
*rel
;
3468 case BFD_RELOC_X86_64_GOT32
:
3469 return BFD_RELOC_X86_64_GOT64
;
3471 case BFD_RELOC_X86_64_GOTPLT64
:
3472 return BFD_RELOC_X86_64_GOTPLT64
;
3474 case BFD_RELOC_X86_64_PLTOFF64
:
3475 return BFD_RELOC_X86_64_PLTOFF64
;
3477 case BFD_RELOC_X86_64_GOTPC32
:
3478 other
= BFD_RELOC_X86_64_GOTPC64
;
3480 case BFD_RELOC_X86_64_GOTPCREL
:
3481 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3483 case BFD_RELOC_X86_64_TPOFF32
:
3484 other
= BFD_RELOC_X86_64_TPOFF64
;
3486 case BFD_RELOC_X86_64_DTPOFF32
:
3487 other
= BFD_RELOC_X86_64_DTPOFF64
;
3493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3494 if (other
== BFD_RELOC_SIZE32
)
3497 other
= BFD_RELOC_SIZE64
;
3500 as_bad (_("there are no pc-relative size relocations"));
3506 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3507 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3510 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3512 as_bad (_("unknown relocation (%u)"), other
);
3513 else if (size
!= bfd_get_reloc_size (rel
))
3514 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3515 bfd_get_reloc_size (rel
),
3517 else if (pcrel
&& !rel
->pc_relative
)
3518 as_bad (_("non-pc-relative relocation for pc-relative field"));
3519 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3521 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3523 as_bad (_("relocated field and relocation type differ in signedness"));
3532 as_bad (_("there are no unsigned pc-relative relocations"));
3535 case 1: return BFD_RELOC_8_PCREL
;
3536 case 2: return BFD_RELOC_16_PCREL
;
3537 case 4: return BFD_RELOC_32_PCREL
;
3538 case 8: return BFD_RELOC_64_PCREL
;
3540 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3547 case 4: return BFD_RELOC_X86_64_32S
;
3552 case 1: return BFD_RELOC_8
;
3553 case 2: return BFD_RELOC_16
;
3554 case 4: return BFD_RELOC_32
;
3555 case 8: return BFD_RELOC_64
;
3557 as_bad (_("cannot do %s %u byte relocation"),
3558 sign
> 0 ? "signed" : "unsigned", size
);
3564 /* Here we decide which fixups can be adjusted to make them relative to
3565 the beginning of the section instead of the symbol. Basically we need
3566 to make sure that the dynamic relocations are done correctly, so in
3567 some cases we force the original symbol to be used. */
3570 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3576 /* Don't adjust pc-relative references to merge sections in 64-bit
3578 if (use_rela_relocations
3579 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3583 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3584 and changed later by validate_fix. */
3585 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3586 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3589 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3590 for size relocations. */
3591 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3592 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3593 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3594 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3595 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3596 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3597 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3598 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3599 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3600 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3601 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3602 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3603 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3604 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3606 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3607 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3608 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3609 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3610 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3611 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3612 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3613 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3620 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3621 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3628 want_disp32 (const insn_template
*t
)
3630 return flag_code
!= CODE_64BIT
3631 || i
.prefix
[ADDR_PREFIX
]
3632 || (t
->mnem_off
== MN_lea
3633 && (!i
.types
[1].bitfield
.qword
3634 || t
->opcode_modifier
.size
== SIZE32
));
3638 intel_float_operand (const char *mnemonic
)
3640 /* Note that the value returned is meaningful only for opcodes with (memory)
3641 operands, hence the code here is free to improperly handle opcodes that
3642 have no operands (for better performance and smaller code). */
3644 if (mnemonic
[0] != 'f')
3645 return 0; /* non-math */
3647 switch (mnemonic
[1])
3649 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3650 the fs segment override prefix not currently handled because no
3651 call path can make opcodes without operands get here */
3653 return 2 /* integer op */;
3655 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3656 return 3; /* fldcw/fldenv */
3659 if (mnemonic
[2] != 'o' /* fnop */)
3660 return 3; /* non-waiting control op */
3663 if (mnemonic
[2] == 's')
3664 return 3; /* frstor/frstpm */
3667 if (mnemonic
[2] == 'a')
3668 return 3; /* fsave */
3669 if (mnemonic
[2] == 't')
3671 switch (mnemonic
[3])
3673 case 'c': /* fstcw */
3674 case 'd': /* fstdw */
3675 case 'e': /* fstenv */
3676 case 's': /* fsts[gw] */
3682 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3683 return 0; /* fxsave/fxrstor are not really math ops */
3691 install_template (const insn_template
*t
)
3697 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3698 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3700 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3701 && is_cpu (t
, CpuAVX512F
))
3703 if (need_evex_encoding ())
3705 i
.tm
.opcode_modifier
.vex
= 0;
3706 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3707 if (is_cpu (&i
.tm
, CpuAVX2
))
3708 i
.tm
.cpu
.bitfield
.isa
= 0;
3712 i
.tm
.opcode_modifier
.evex
= 0;
3713 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3718 /* Note that for pseudo prefixes this produces a length of 1. But for them
3719 the length isn't interesting at all. */
3720 for (l
= 1; l
< 4; ++l
)
3721 if (!(t
->base_opcode
>> (8 * l
)))
3724 i
.opcode_length
= l
;
3727 /* Build the VEX prefix. */
3730 build_vex_prefix (const insn_template
*t
)
3732 unsigned int register_specifier
;
3733 unsigned int vector_length
;
3736 /* Check register specifier. */
3737 if (i
.vex
.register_specifier
)
3739 register_specifier
=
3740 ~register_number (i
.vex
.register_specifier
) & 0xf;
3741 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3744 register_specifier
= 0xf;
3746 /* Use 2-byte VEX prefix by swapping destination and source operand
3747 if there are more than 1 register operand. */
3748 if (i
.reg_operands
> 1
3749 && i
.vec_encoding
!= vex_encoding_vex3
3750 && i
.dir_encoding
== dir_encoding_default
3751 && i
.operands
== i
.reg_operands
3752 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3753 && i
.tm
.opcode_space
== SPACE_0F
3754 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3759 swap_2_operands (0, i
.operands
- 1);
3761 gas_assert (i
.rm
.mode
== 3);
3765 i
.rm
.regmem
= i
.rm
.reg
;
3768 if (i
.tm
.opcode_modifier
.d
)
3769 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3770 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3771 else /* Use the next insn. */
3772 install_template (&t
[1]);
3775 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3776 are no memory operands and at least 3 register ones. */
3777 if (i
.reg_operands
>= 3
3778 && i
.vec_encoding
!= vex_encoding_vex3
3779 && i
.reg_operands
== i
.operands
- i
.imm_operands
3780 && i
.tm
.opcode_modifier
.vex
3781 && i
.tm
.opcode_modifier
.commutative
3782 && (i
.tm
.opcode_modifier
.sse2avx
3783 || (optimize
> 1 && !i
.no_optimize
))
3785 && i
.vex
.register_specifier
3786 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3788 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3790 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3791 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3792 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3793 &i
.types
[i
.operands
- 3]));
3794 gas_assert (i
.rm
.mode
== 3);
3796 swap_2_operands (xchg
, xchg
+ 1);
3799 xchg
= i
.rm
.regmem
| 8;
3800 i
.rm
.regmem
= ~register_specifier
& 0xf;
3801 gas_assert (!(i
.rm
.regmem
& 8));
3802 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3803 register_specifier
= ~xchg
& 0xf;
3806 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3807 vector_length
= avxscalar
;
3808 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3810 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3816 /* Determine vector length from the last multi-length vector
3819 for (op
= t
->operands
; op
--;)
3820 if (t
->operand_types
[op
].bitfield
.xmmword
3821 && t
->operand_types
[op
].bitfield
.ymmword
3822 && i
.types
[op
].bitfield
.ymmword
)
3829 /* Check the REX.W bit and VEXW. */
3830 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3831 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3832 else if (i
.tm
.opcode_modifier
.vexw
)
3833 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3835 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3837 /* Use 2-byte VEX prefix if possible. */
3839 && i
.vec_encoding
!= vex_encoding_vex3
3840 && i
.tm
.opcode_space
== SPACE_0F
3841 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3843 /* 2-byte VEX prefix. */
3847 i
.vex
.bytes
[0] = 0xc5;
3849 /* Check the REX.R bit. */
3850 r
= (i
.rex
& REX_R
) ? 0 : 1;
3851 i
.vex
.bytes
[1] = (r
<< 7
3852 | register_specifier
<< 3
3853 | vector_length
<< 2
3854 | i
.tm
.opcode_modifier
.opcodeprefix
);
3858 /* 3-byte VEX prefix. */
3861 switch (i
.tm
.opcode_space
)
3866 i
.vex
.bytes
[0] = 0xc4;
3871 i
.vex
.bytes
[0] = 0x8f;
3877 /* The high 3 bits of the second VEX byte are 1's compliment
3878 of RXB bits from REX. */
3879 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3880 | (!dot_insn () ? i
.tm
.opcode_space
3881 : i
.insn_opcode_space
);
3883 i
.vex
.bytes
[2] = (w
<< 7
3884 | register_specifier
<< 3
3885 | vector_length
<< 2
3886 | i
.tm
.opcode_modifier
.opcodeprefix
);
3891 is_evex_encoding (const insn_template
*t
)
3893 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3894 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3895 || t
->opcode_modifier
.sae
;
3899 is_any_vex_encoding (const insn_template
*t
)
3901 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3905 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3907 unsigned int op
, bytes
;
3908 const i386_operand_type
*types
;
3910 if (i
.broadcast
.type
)
3911 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3913 gas_assert (intel_syntax
);
3915 for (op
= 0; op
< t
->operands
; ++op
)
3916 if (t
->operand_types
[op
].bitfield
.baseindex
)
3919 gas_assert (op
< t
->operands
);
3921 if (t
->opcode_modifier
.evex
3922 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3923 switch (i
.broadcast
.bytes
)
3926 if (t
->operand_types
[op
].bitfield
.word
)
3930 if (t
->operand_types
[op
].bitfield
.dword
)
3934 if (t
->operand_types
[op
].bitfield
.qword
)
3938 if (t
->operand_types
[op
].bitfield
.xmmword
)
3940 if (t
->operand_types
[op
].bitfield
.ymmword
)
3942 if (t
->operand_types
[op
].bitfield
.zmmword
)
3949 gas_assert (op
+ 1 < t
->operands
);
3951 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3952 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3953 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3955 types
= &i
.types
[op
+ 1];
3958 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3959 types
= &t
->operand_types
[op
];
3961 if (types
->bitfield
.zmmword
)
3963 else if (types
->bitfield
.ymmword
)
3969 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3970 insn_name (t
), bytes
* 8);
3975 /* Build the EVEX prefix. */
3978 build_evex_prefix (void)
3980 unsigned int register_specifier
, w
;
3981 rex_byte vrex_used
= 0;
3983 /* Check register specifier. */
3984 if (i
.vex
.register_specifier
)
3986 gas_assert ((i
.vrex
& REX_X
) == 0);
3988 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3989 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3990 register_specifier
+= 8;
3991 /* The upper 16 registers are encoded in the fourth byte of the
3993 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3994 i
.vex
.bytes
[3] = 0x8;
3995 register_specifier
= ~register_specifier
& 0xf;
3999 register_specifier
= 0xf;
4001 /* Encode upper 16 vector index register in the fourth byte of
4003 if (!(i
.vrex
& REX_X
))
4004 i
.vex
.bytes
[3] = 0x8;
4009 /* 4 byte EVEX prefix. */
4011 i
.vex
.bytes
[0] = 0x62;
4013 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4015 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
4016 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
4017 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4018 | (!dot_insn () ? i
.tm
.opcode_space
4019 : i
.insn_opcode_space
);
4021 /* The fifth bit of the second EVEX byte is 1's compliment of the
4022 REX_R bit in VREX. */
4023 if (!(i
.vrex
& REX_R
))
4024 i
.vex
.bytes
[1] |= 0x10;
4028 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4030 /* When all operands are registers, the REX_X bit in REX is not
4031 used. We reuse it to encode the upper 16 registers, which is
4032 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4033 as 1's compliment. */
4034 if ((i
.vrex
& REX_B
))
4037 i
.vex
.bytes
[1] &= ~0x40;
4041 /* EVEX instructions shouldn't need the REX prefix. */
4042 i
.vrex
&= ~vrex_used
;
4043 gas_assert (i
.vrex
== 0);
4045 /* Check the REX.W bit and VEXW. */
4046 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4047 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4048 else if (i
.tm
.opcode_modifier
.vexw
)
4049 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4051 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4053 /* The third byte of the EVEX prefix. */
4054 i
.vex
.bytes
[2] = ((w
<< 7)
4055 | (register_specifier
<< 3)
4056 | 4 /* Encode the U bit. */
4057 | i
.tm
.opcode_modifier
.opcodeprefix
);
4059 /* The fourth byte of the EVEX prefix. */
4060 /* The zeroing-masking bit. */
4061 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4062 i
.vex
.bytes
[3] |= 0x80;
4064 /* Don't always set the broadcast bit if there is no RC. */
4065 if (i
.rounding
.type
== rc_none
)
4067 /* Encode the vector length. */
4068 unsigned int vec_length
;
4070 if (!i
.tm
.opcode_modifier
.evex
4071 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4075 /* Determine vector length from the last multi-length vector
4077 for (op
= i
.operands
; op
--;)
4078 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4079 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4080 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4082 if (i
.types
[op
].bitfield
.zmmword
)
4084 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4087 else if (i
.types
[op
].bitfield
.ymmword
)
4089 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4092 else if (i
.types
[op
].bitfield
.xmmword
)
4094 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4097 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4098 && op
== i
.broadcast
.operand
)
4100 switch (get_broadcast_bytes (&i
.tm
, true))
4103 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4106 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4109 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4118 if (op
>= MAX_OPERANDS
)
4122 switch (i
.tm
.opcode_modifier
.evex
)
4124 case EVEXLIG
: /* LL' is ignored */
4125 vec_length
= evexlig
<< 5;
4128 vec_length
= 0 << 5;
4131 vec_length
= 1 << 5;
4134 vec_length
= 2 << 5;
4139 vec_length
= 3 << 5;
4147 i
.vex
.bytes
[3] |= vec_length
;
4148 /* Encode the broadcast bit. */
4149 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4150 i
.vex
.bytes
[3] |= 0x10;
4152 else if (i
.rounding
.type
!= saeonly
)
4153 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4155 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4158 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4162 process_immext (void)
4166 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4167 which is coded in the same place as an 8-bit immediate field
4168 would be. Here we fake an 8-bit immediate operand from the
4169 opcode suffix stored in tm.extension_opcode.
4171 AVX instructions also use this encoding, for some of
4172 3 argument instructions. */
4174 gas_assert (i
.imm_operands
<= 1
4176 || (is_any_vex_encoding (&i
.tm
)
4177 && i
.operands
<= 4)));
4179 exp
= &im_expressions
[i
.imm_operands
++];
4180 i
.op
[i
.operands
].imms
= exp
;
4181 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4183 exp
->X_op
= O_constant
;
4184 exp
->X_add_number
= i
.tm
.extension_opcode
;
4185 i
.tm
.extension_opcode
= None
;
4192 switch (i
.tm
.opcode_modifier
.prefixok
)
4200 as_bad (_("invalid instruction `%s' after `%s'"),
4201 insn_name (&i
.tm
), i
.hle_prefix
);
4204 if (i
.prefix
[LOCK_PREFIX
])
4206 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4210 case PrefixHLERelease
:
4211 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4213 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4217 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4219 as_bad (_("memory destination needed for instruction `%s'"
4220 " after `xrelease'"), insn_name (&i
.tm
));
4227 /* Encode aligned vector move as unaligned vector move. */
4230 encode_with_unaligned_vector_move (void)
4232 switch (i
.tm
.base_opcode
)
4234 case 0x28: /* Load instructions. */
4235 case 0x29: /* Store instructions. */
4236 /* movaps/movapd/vmovaps/vmovapd. */
4237 if (i
.tm
.opcode_space
== SPACE_0F
4238 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4239 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4241 case 0x6f: /* Load instructions. */
4242 case 0x7f: /* Store instructions. */
4243 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4244 if (i
.tm
.opcode_space
== SPACE_0F
4245 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4246 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4253 /* Try the shortest encoding by shortening operand size. */
4256 optimize_encoding (void)
4260 if (i
.tm
.mnem_off
== MN_lea
)
4263 lea symbol, %rN -> mov $symbol, %rN
4264 lea (%rM), %rN -> mov %rM, %rN
4265 lea (,%rM,1), %rN -> mov %rM, %rN
4267 and in 32-bit mode for 16-bit addressing
4269 lea (%rM), %rN -> movzx %rM, %rN
4271 and in 64-bit mode zap 32-bit addressing in favor of using a
4272 32-bit (or less) destination.
4274 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4276 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4277 i
.tm
.opcode_modifier
.size
= SIZE32
;
4278 i
.prefix
[ADDR_PREFIX
] = 0;
4281 if (!i
.index_reg
&& !i
.base_reg
)
4284 lea symbol, %rN -> mov $symbol, %rN
4286 if (flag_code
== CODE_64BIT
)
4288 /* Don't transform a relocation to a 16-bit one. */
4290 && i
.op
[0].disps
->X_op
!= O_constant
4291 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4294 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4295 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4297 i
.tm
.base_opcode
= 0xb8;
4298 i
.tm
.opcode_modifier
.modrm
= 0;
4299 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4300 i
.types
[0].bitfield
.imm32
= 1;
4303 i
.tm
.opcode_modifier
.size
= SIZE16
;
4304 i
.types
[0].bitfield
.imm16
= 1;
4309 /* Subject to further optimization below. */
4310 i
.tm
.base_opcode
= 0xc7;
4311 i
.tm
.extension_opcode
= 0;
4312 i
.types
[0].bitfield
.imm32s
= 1;
4313 i
.types
[0].bitfield
.baseindex
= 0;
4316 /* Outside of 64-bit mode address and operand sizes have to match if
4317 a relocation is involved, as otherwise we wouldn't (currently) or
4318 even couldn't express the relocation correctly. */
4319 else if (i
.op
[0].disps
4320 && i
.op
[0].disps
->X_op
!= O_constant
4321 && ((!i
.prefix
[ADDR_PREFIX
])
4322 != (flag_code
== CODE_32BIT
4323 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4324 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4326 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4327 destination is going to grow encoding size. */
4328 else if (flag_code
== CODE_16BIT
4329 && (optimize
<= 1 || optimize_for_space
)
4330 && !i
.prefix
[ADDR_PREFIX
]
4331 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4335 i
.tm
.base_opcode
= 0xb8;
4336 i
.tm
.opcode_modifier
.modrm
= 0;
4337 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4338 i
.types
[0].bitfield
.imm32
= 1;
4340 i
.types
[0].bitfield
.imm16
= 1;
4343 && i
.op
[0].disps
->X_op
== O_constant
4344 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4345 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4347 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4348 i
.op
[0].disps
->X_add_number
&= 0xffff;
4351 i
.tm
.operand_types
[0] = i
.types
[0];
4355 i
.op
[0].imms
= &im_expressions
[0];
4356 i
.op
[0].imms
->X_op
= O_absent
;
4359 else if (i
.op
[0].disps
4360 && (i
.op
[0].disps
->X_op
!= O_constant
4361 || i
.op
[0].disps
->X_add_number
))
4366 lea (%rM), %rN -> mov %rM, %rN
4367 lea (,%rM,1), %rN -> mov %rM, %rN
4368 lea (%rM), %rN -> movzx %rM, %rN
4370 const reg_entry
*addr_reg
;
4372 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4373 addr_reg
= i
.base_reg
;
4374 else if (!i
.base_reg
4375 && i
.index_reg
->reg_num
!= RegIZ
4376 && !i
.log2_scale_factor
)
4377 addr_reg
= i
.index_reg
;
4381 if (addr_reg
->reg_type
.bitfield
.word
4382 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4384 if (flag_code
!= CODE_32BIT
)
4386 i
.tm
.opcode_space
= SPACE_0F
;
4387 i
.tm
.base_opcode
= 0xb7;
4390 i
.tm
.base_opcode
= 0x8b;
4392 if (addr_reg
->reg_type
.bitfield
.dword
4393 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4394 i
.tm
.opcode_modifier
.size
= SIZE32
;
4396 i
.op
[0].regs
= addr_reg
;
4401 i
.disp_operands
= 0;
4402 i
.prefix
[ADDR_PREFIX
] = 0;
4403 i
.prefix
[SEG_PREFIX
] = 0;
4407 if (optimize_for_space
4408 && i
.tm
.mnem_off
== MN_test
4409 && i
.reg_operands
== 1
4410 && i
.imm_operands
== 1
4411 && !i
.types
[1].bitfield
.byte
4412 && i
.op
[0].imms
->X_op
== O_constant
4413 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4416 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4418 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4419 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4421 i
.types
[1].bitfield
.byte
= 1;
4422 /* Ignore the suffix. */
4424 /* Convert to byte registers. */
4425 if (i
.types
[1].bitfield
.word
)
4427 else if (i
.types
[1].bitfield
.dword
)
4431 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4436 else if (flag_code
== CODE_64BIT
4437 && i
.tm
.opcode_space
== SPACE_BASE
4438 && ((i
.types
[1].bitfield
.qword
4439 && i
.reg_operands
== 1
4440 && i
.imm_operands
== 1
4441 && i
.op
[0].imms
->X_op
== O_constant
4442 && ((i
.tm
.base_opcode
== 0xb8
4443 && i
.tm
.extension_opcode
== None
4444 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4445 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4446 && (i
.tm
.base_opcode
== 0x24
4447 || (i
.tm
.base_opcode
== 0x80
4448 && i
.tm
.extension_opcode
== 0x4)
4449 || i
.tm
.mnem_off
== MN_test
4450 || ((i
.tm
.base_opcode
| 1) == 0xc7
4451 && i
.tm
.extension_opcode
== 0x0)))
4452 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4453 && i
.tm
.base_opcode
== 0x83
4454 && i
.tm
.extension_opcode
== 0x4)))
4455 || (i
.types
[0].bitfield
.qword
4456 && ((i
.reg_operands
== 2
4457 && i
.op
[0].regs
== i
.op
[1].regs
4458 && (i
.tm
.mnem_off
== MN_xor
4459 || i
.tm
.mnem_off
== MN_sub
))
4460 || i
.tm
.mnem_off
== MN_clr
))))
4463 andq $imm31, %r64 -> andl $imm31, %r32
4464 andq $imm7, %r64 -> andl $imm7, %r32
4465 testq $imm31, %r64 -> testl $imm31, %r32
4466 xorq %r64, %r64 -> xorl %r32, %r32
4467 subq %r64, %r64 -> subl %r32, %r32
4468 movq $imm31, %r64 -> movl $imm31, %r32
4469 movq $imm32, %r64 -> movl $imm32, %r32
4471 i
.tm
.opcode_modifier
.size
= SIZE32
;
4474 i
.types
[0].bitfield
.imm32
= 1;
4475 i
.types
[0].bitfield
.imm32s
= 0;
4476 i
.types
[0].bitfield
.imm64
= 0;
4480 i
.types
[0].bitfield
.dword
= 1;
4481 i
.types
[0].bitfield
.qword
= 0;
4483 i
.types
[1].bitfield
.dword
= 1;
4484 i
.types
[1].bitfield
.qword
= 0;
4485 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4488 movq $imm31, %r64 -> movl $imm31, %r32
4489 movq $imm32, %r64 -> movl $imm32, %r32
4491 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4492 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4493 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4494 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4497 movq $imm31, %r64 -> movl $imm31, %r32
4499 i
.tm
.base_opcode
= 0xb8;
4500 i
.tm
.extension_opcode
= None
;
4501 i
.tm
.opcode_modifier
.w
= 0;
4502 i
.tm
.opcode_modifier
.modrm
= 0;
4506 else if (optimize
> 1
4507 && !optimize_for_space
4508 && i
.reg_operands
== 2
4509 && i
.op
[0].regs
== i
.op
[1].regs
4510 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4511 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4514 andb %rN, %rN -> testb %rN, %rN
4515 andw %rN, %rN -> testw %rN, %rN
4516 andq %rN, %rN -> testq %rN, %rN
4517 orb %rN, %rN -> testb %rN, %rN
4518 orw %rN, %rN -> testw %rN, %rN
4519 orq %rN, %rN -> testq %rN, %rN
4521 and outside of 64-bit mode
4523 andl %rN, %rN -> testl %rN, %rN
4524 orl %rN, %rN -> testl %rN, %rN
4526 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4528 else if (i
.tm
.base_opcode
== 0xba
4529 && i
.tm
.opcode_space
== SPACE_0F
4530 && i
.reg_operands
== 1
4531 && i
.op
[0].imms
->X_op
== O_constant
4532 && i
.op
[0].imms
->X_add_number
>= 0)
4535 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4536 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4537 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4539 With <BT> one of bts, btr, and bts also:
4540 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4541 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4546 if (i
.tm
.extension_opcode
!= 4)
4548 if (i
.types
[1].bitfield
.qword
4549 && i
.op
[0].imms
->X_add_number
< 32
4550 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4551 i
.tm
.opcode_modifier
.size
= SIZE32
;
4554 if (i
.types
[1].bitfield
.word
4555 && i
.op
[0].imms
->X_add_number
< 16)
4556 i
.tm
.opcode_modifier
.size
= SIZE32
;
4559 if (i
.op
[0].imms
->X_add_number
< 16)
4560 i
.tm
.opcode_modifier
.size
= SIZE16
;
4564 else if (i
.reg_operands
== 3
4565 && i
.op
[0].regs
== i
.op
[1].regs
4566 && !i
.types
[2].bitfield
.xmmword
4567 && (i
.tm
.opcode_modifier
.vex
4568 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4569 && is_evex_encoding (&i
.tm
)
4570 && (i
.vec_encoding
!= vex_encoding_evex
4571 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4572 || is_cpu (&i
.tm
, CpuAVX512VL
)
4573 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4574 && i
.types
[2].bitfield
.ymmword
))))
4575 && i
.tm
.opcode_space
== SPACE_0F
4576 && ((i
.tm
.base_opcode
| 2) == 0x57
4577 || i
.tm
.base_opcode
== 0xdf
4578 || i
.tm
.base_opcode
== 0xef
4579 || (i
.tm
.base_opcode
| 3) == 0xfb
4580 || i
.tm
.base_opcode
== 0x42
4581 || i
.tm
.base_opcode
== 0x47))
4584 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4586 EVEX VOP %zmmM, %zmmM, %zmmN
4587 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4588 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4589 EVEX VOP %ymmM, %ymmM, %ymmN
4590 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4591 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4592 VEX VOP %ymmM, %ymmM, %ymmN
4593 -> VEX VOP %xmmM, %xmmM, %xmmN
4594 VOP, one of vpandn and vpxor:
4595 VEX VOP %ymmM, %ymmM, %ymmN
4596 -> VEX VOP %xmmM, %xmmM, %xmmN
4597 VOP, one of vpandnd and vpandnq:
4598 EVEX VOP %zmmM, %zmmM, %zmmN
4599 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4600 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4601 EVEX VOP %ymmM, %ymmM, %ymmN
4602 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4603 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4604 VOP, one of vpxord and vpxorq:
4605 EVEX VOP %zmmM, %zmmM, %zmmN
4606 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4607 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4608 EVEX VOP %ymmM, %ymmM, %ymmN
4609 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4610 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4611 VOP, one of kxord and kxorq:
4612 VEX VOP %kM, %kM, %kN
4613 -> VEX kxorw %kM, %kM, %kN
4614 VOP, one of kandnd and kandnq:
4615 VEX VOP %kM, %kM, %kN
4616 -> VEX kandnw %kM, %kM, %kN
4618 if (is_evex_encoding (&i
.tm
))
4620 if (i
.vec_encoding
!= vex_encoding_evex
)
4622 i
.tm
.opcode_modifier
.vex
= VEX128
;
4623 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4624 i
.tm
.opcode_modifier
.evex
= 0;
4625 i
.vec_encoding
= vex_encoding_vex
;
4628 else if (optimize
> 1)
4629 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4633 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4635 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4636 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4639 i
.tm
.opcode_modifier
.vex
= VEX128
;
4641 if (i
.tm
.opcode_modifier
.vex
)
4642 for (j
= 0; j
< 3; j
++)
4644 i
.types
[j
].bitfield
.xmmword
= 1;
4645 i
.types
[j
].bitfield
.ymmword
= 0;
4648 else if (i
.vec_encoding
!= vex_encoding_evex
4649 && !i
.types
[0].bitfield
.zmmword
4650 && !i
.types
[1].bitfield
.zmmword
4652 && !i
.broadcast
.type
4653 && !i
.broadcast
.bytes
4654 && is_evex_encoding (&i
.tm
)
4655 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4656 || (i
.tm
.base_opcode
& ~4) == 0xdb
4657 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4658 && i
.tm
.extension_opcode
== None
)
4661 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4662 vmovdqu32 and vmovdqu64:
4663 EVEX VOP %xmmM, %xmmN
4664 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4665 EVEX VOP %ymmM, %ymmN
4666 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4668 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4670 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4672 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4674 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4675 VOP, one of vpand, vpandn, vpor, vpxor:
4676 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4677 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4678 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4679 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4680 EVEX VOP{d,q} mem, %xmmM, %xmmN
4681 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4682 EVEX VOP{d,q} mem, %ymmM, %ymmN
4683 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4685 for (j
= 0; j
< i
.operands
; j
++)
4686 if (operand_type_check (i
.types
[j
], disp
)
4687 && i
.op
[j
].disps
->X_op
== O_constant
)
4689 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4690 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4691 bytes, we choose EVEX Disp8 over VEX Disp32. */
4692 int evex_disp8
, vex_disp8
;
4693 unsigned int memshift
= i
.memshift
;
4694 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4696 evex_disp8
= fits_in_disp8 (n
);
4698 vex_disp8
= fits_in_disp8 (n
);
4699 if (evex_disp8
!= vex_disp8
)
4701 i
.memshift
= memshift
;
4705 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4708 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4709 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4710 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4711 i
.tm
.opcode_modifier
.vex
4712 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4713 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4714 /* VPAND, VPOR, and VPXOR are commutative. */
4715 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4716 i
.tm
.opcode_modifier
.commutative
= 1;
4717 i
.tm
.opcode_modifier
.evex
= 0;
4718 i
.tm
.opcode_modifier
.masking
= 0;
4719 i
.tm
.opcode_modifier
.broadcast
= 0;
4720 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4723 i
.types
[j
].bitfield
.disp8
4724 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4726 else if (optimize_for_space
4727 && i
.tm
.base_opcode
== 0x29
4728 && i
.tm
.opcode_space
== SPACE_0F38
4729 && i
.operands
== i
.reg_operands
4730 && i
.op
[0].regs
== i
.op
[1].regs
4731 && (!i
.tm
.opcode_modifier
.vex
4732 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4733 && !is_evex_encoding (&i
.tm
))
4736 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4737 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4738 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4740 i
.tm
.opcode_space
= SPACE_0F
;
4741 i
.tm
.base_opcode
= 0x76;
4743 else if (((i
.tm
.base_opcode
>= 0x64
4744 && i
.tm
.base_opcode
<= 0x66
4745 && i
.tm
.opcode_space
== SPACE_0F
)
4746 || (i
.tm
.base_opcode
== 0x37
4747 && i
.tm
.opcode_space
== SPACE_0F38
))
4748 && i
.operands
== i
.reg_operands
4749 && i
.op
[0].regs
== i
.op
[1].regs
4750 && !is_evex_encoding (&i
.tm
))
4753 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4754 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4755 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4756 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4757 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4758 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4760 i
.tm
.opcode_space
= SPACE_0F
;
4761 i
.tm
.base_opcode
= 0xef;
4762 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4764 if (i
.operands
== 2)
4766 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4772 i
.op
[2].regs
= i
.op
[0].regs
;
4773 i
.types
[2] = i
.types
[0];
4774 i
.flags
[2] = i
.flags
[0];
4775 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4777 i
.tm
.opcode_modifier
.sse2avx
= 0;
4779 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4780 i
.op
[1].regs
= i
.op
[0].regs
;
4783 else if (optimize_for_space
4784 && i
.tm
.base_opcode
== 0x59
4785 && i
.tm
.opcode_space
== SPACE_0F38
4786 && i
.operands
== i
.reg_operands
4787 && i
.tm
.opcode_modifier
.vex
4788 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4789 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4790 && i
.vec_encoding
!= vex_encoding_vex3
)
4793 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4795 i
.tm
.opcode_space
= SPACE_0F
;
4796 i
.tm
.base_opcode
= 0x6c;
4797 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4803 i
.op
[2].regs
= i
.op
[0].regs
;
4804 i
.types
[2] = i
.types
[0];
4805 i
.flags
[2] = i
.flags
[0];
4806 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4808 swap_2_operands (1, 2);
4812 /* Return non-zero for load instruction. */
4818 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4819 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4823 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4824 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4825 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4829 if (i
.tm
.mnem_off
== MN_pop
)
4833 if (i
.tm
.opcode_space
== SPACE_BASE
)
4836 if (i
.tm
.base_opcode
== 0x9d
4837 || i
.tm
.base_opcode
== 0x61)
4840 /* movs, cmps, lods, scas. */
4841 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4845 if (base_opcode
== 0x6f
4846 || i
.tm
.base_opcode
== 0xd7)
4848 /* NB: For AMD-specific insns with implicit memory operands,
4849 they're intentionally not covered. */
4852 /* No memory operand. */
4853 if (!i
.mem_operands
)
4858 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4861 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4863 /* test, not, neg, mul, imul, div, idiv. */
4864 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4868 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4871 /* add, or, adc, sbb, and, sub, xor, cmp. */
4872 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4875 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4876 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4877 && i
.tm
.extension_opcode
!= 6)
4880 /* Check for x87 instructions. */
4881 if ((base_opcode
| 6) == 0xdf)
4883 /* Skip fst, fstp, fstenv, fstcw. */
4884 if (i
.tm
.base_opcode
== 0xd9
4885 && (i
.tm
.extension_opcode
== 2
4886 || i
.tm
.extension_opcode
== 3
4887 || i
.tm
.extension_opcode
== 6
4888 || i
.tm
.extension_opcode
== 7))
4891 /* Skip fisttp, fist, fistp, fstp. */
4892 if (i
.tm
.base_opcode
== 0xdb
4893 && (i
.tm
.extension_opcode
== 1
4894 || i
.tm
.extension_opcode
== 2
4895 || i
.tm
.extension_opcode
== 3
4896 || i
.tm
.extension_opcode
== 7))
4899 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4900 if (i
.tm
.base_opcode
== 0xdd
4901 && (i
.tm
.extension_opcode
== 1
4902 || i
.tm
.extension_opcode
== 2
4903 || i
.tm
.extension_opcode
== 3
4904 || i
.tm
.extension_opcode
== 6
4905 || i
.tm
.extension_opcode
== 7))
4908 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4909 if (i
.tm
.base_opcode
== 0xdf
4910 && (i
.tm
.extension_opcode
== 1
4911 || i
.tm
.extension_opcode
== 2
4912 || i
.tm
.extension_opcode
== 3
4913 || i
.tm
.extension_opcode
== 6
4914 || i
.tm
.extension_opcode
== 7))
4920 else if (i
.tm
.opcode_space
== SPACE_0F
)
4922 /* bt, bts, btr, btc. */
4923 if (i
.tm
.base_opcode
== 0xba
4924 && (i
.tm
.extension_opcode
| 3) == 7)
4927 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4928 if (i
.tm
.base_opcode
== 0xc7
4929 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4930 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4931 || i
.tm
.extension_opcode
== 6))
4934 /* fxrstor, ldmxcsr, xrstor. */
4935 if (i
.tm
.base_opcode
== 0xae
4936 && (i
.tm
.extension_opcode
== 1
4937 || i
.tm
.extension_opcode
== 2
4938 || i
.tm
.extension_opcode
== 5))
4941 /* lgdt, lidt, lmsw. */
4942 if (i
.tm
.base_opcode
== 0x01
4943 && (i
.tm
.extension_opcode
== 2
4944 || i
.tm
.extension_opcode
== 3
4945 || i
.tm
.extension_opcode
== 6))
4949 dest
= i
.operands
- 1;
4951 /* Check fake imm8 operand and 3 source operands. */
4952 if ((i
.tm
.opcode_modifier
.immext
4953 || i
.reg_operands
+ i
.mem_operands
== 4)
4954 && i
.types
[dest
].bitfield
.imm8
)
4957 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4958 if (i
.tm
.opcode_space
== SPACE_BASE
4959 && ((base_opcode
| 0x38) == 0x39
4960 || (base_opcode
| 2) == 0x87))
4963 if (i
.tm
.mnem_off
== MN_xadd
)
4966 /* Check for load instruction. */
4967 return (i
.types
[dest
].bitfield
.class != ClassNone
4968 || i
.types
[dest
].bitfield
.instance
== Accum
);
4971 /* Output lfence, 0xfaee8, after instruction. */
4974 insert_lfence_after (void)
4976 if (lfence_after_load
&& load_insn_p ())
4978 /* There are also two REP string instructions that require
4979 special treatment. Specifically, the compare string (CMPS)
4980 and scan string (SCAS) instructions set EFLAGS in a manner
4981 that depends on the data being compared/scanned. When used
4982 with a REP prefix, the number of iterations may therefore
4983 vary depending on this data. If the data is a program secret
4984 chosen by the adversary using an LVI method,
4985 then this data-dependent behavior may leak some aspect
4987 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4988 && i
.prefix
[REP_PREFIX
])
4990 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4993 char *p
= frag_more (3);
5000 /* Output lfence, 0xfaee8, before instruction. */
5003 insert_lfence_before (void)
5007 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5010 if (i
.tm
.base_opcode
== 0xff
5011 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
5013 /* Insert lfence before indirect branch if needed. */
5015 if (lfence_before_indirect_branch
== lfence_branch_none
)
5018 if (i
.operands
!= 1)
5021 if (i
.reg_operands
== 1)
5023 /* Indirect branch via register. Don't insert lfence with
5024 -mlfence-after-load=yes. */
5025 if (lfence_after_load
5026 || lfence_before_indirect_branch
== lfence_branch_memory
)
5029 else if (i
.mem_operands
== 1
5030 && lfence_before_indirect_branch
!= lfence_branch_register
)
5032 as_warn (_("indirect `%s` with memory operand should be avoided"),
5039 if (last_insn
.kind
!= last_insn_other
5040 && last_insn
.seg
== now_seg
)
5042 as_warn_where (last_insn
.file
, last_insn
.line
,
5043 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5044 last_insn
.name
, insn_name (&i
.tm
));
5055 /* Output or/not/shl and lfence before near ret. */
5056 if (lfence_before_ret
!= lfence_before_ret_none
5057 && (i
.tm
.base_opcode
| 1) == 0xc3)
5059 if (last_insn
.kind
!= last_insn_other
5060 && last_insn
.seg
== now_seg
)
5062 as_warn_where (last_insn
.file
, last_insn
.line
,
5063 _("`%s` skips -mlfence-before-ret on `%s`"),
5064 last_insn
.name
, insn_name (&i
.tm
));
5068 /* Near ret ingore operand size override under CPU64. */
5069 char prefix
= flag_code
== CODE_64BIT
5071 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5073 if (lfence_before_ret
== lfence_before_ret_not
)
5075 /* not: 0xf71424, may add prefix
5076 for operand size override or 64-bit code. */
5077 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5091 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5094 if (lfence_before_ret
== lfence_before_ret_or
)
5096 /* or: 0x830c2400, may add prefix
5097 for operand size override or 64-bit code. */
5103 /* shl: 0xc1242400, may add prefix
5104 for operand size override or 64-bit code. */
5119 /* Shared helper for md_assemble() and s_insn(). */
5120 static void init_globals (void)
5124 memset (&i
, '\0', sizeof (i
));
5125 i
.rounding
.type
= rc_none
;
5126 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5127 i
.reloc
[j
] = NO_RELOC
;
5128 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5129 memset (im_expressions
, '\0', sizeof (im_expressions
));
5130 save_stack_p
= save_stack
;
5133 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5134 parsing pass. Instead of introducing a rarely use new insn attribute this
5135 utilizes a common pattern between affected templates. It is deemed
5136 acceptable that this will lead to unnecessary pass 2 preparations in a
5137 limited set of cases. */
5138 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5140 return t
->opcode_modifier
.sse2avx
5141 /* Note that all SSE2AVX templates have at least one operand. */
5142 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5143 : (t
->opcode_space
== SPACE_0F
5144 && (t
->base_opcode
| 1) == 0xbf)
5145 || (t
->opcode_space
== SPACE_BASE
5146 && t
->base_opcode
== 0x63);
5149 /* This is the guts of the machine-dependent assembler. LINE points to a
5150 machine dependent instruction. This function is supposed to emit
5151 the frags/bytes it assembles to. */
5154 md_assemble (char *line
)
5157 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5158 const char *end
, *pass1_mnem
= NULL
;
5159 enum i386_error pass1_err
= 0;
5160 const insn_template
*t
;
5162 /* Initialize globals. */
5163 current_templates
= NULL
;
5167 /* First parse an instruction mnemonic & call i386_operand for the operands.
5168 We assume that the scrubber has arranged it so that line[0] is the valid
5169 start of a (possibly prefixed) mnemonic. */
5171 end
= parse_insn (line
, mnemonic
, false);
5174 if (pass1_mnem
!= NULL
)
5176 if (i
.error
!= no_error
)
5178 gas_assert (current_templates
!= NULL
);
5179 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5181 /* No point in trying a 2nd pass - it'll only find the same suffix
5183 mnem_suffix
= i
.suffix
;
5188 t
= current_templates
->start
;
5189 if (may_need_pass2 (t
))
5191 /* Make a copy of the full line in case we need to retry. */
5192 copy
= xstrdup (line
);
5195 mnem_suffix
= i
.suffix
;
5197 line
= parse_operands (line
, mnemonic
);
5205 /* Now we've parsed the mnemonic into a set of templates, and have the
5206 operands at hand. */
5208 /* All Intel opcodes have reversed operands except for "bound", "enter",
5209 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5210 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5211 intersegment "jmp" and "call" instructions with 2 immediate operands so
5212 that the immediate segment precedes the offset consistently in Intel and
5216 && (t
->mnem_off
!= MN_bound
)
5217 && !startswith (mnemonic
, "invlpg")
5218 && !startswith (mnemonic
, "monitor")
5219 && !startswith (mnemonic
, "mwait")
5220 && (t
->mnem_off
!= MN_pvalidate
)
5221 && !startswith (mnemonic
, "rmp")
5222 && (t
->mnem_off
!= MN_tpause
)
5223 && (t
->mnem_off
!= MN_umwait
)
5224 && !(i
.operands
== 2
5225 && operand_type_check (i
.types
[0], imm
)
5226 && operand_type_check (i
.types
[1], imm
)))
5229 /* The order of the immediates should be reversed
5230 for 2 immediates extrq and insertq instructions */
5231 if (i
.imm_operands
== 2
5232 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5233 swap_2_operands (0, 1);
5238 if (i
.disp_operands
&& !optimize_disp (t
))
5241 /* Next, we find a template that matches the given insn,
5242 making sure the overlap of the given operands types is consistent
5243 with the template operand types. */
5245 if (!(t
= match_template (mnem_suffix
)))
5247 const char *err_msg
;
5249 if (copy
&& !mnem_suffix
)
5254 pass1_err
= i
.error
;
5255 pass1_mnem
= insn_name (current_templates
->start
);
5259 /* If a non-/only-64bit template (group) was found in pass 1, and if
5260 _some_ template (group) was found in pass 2, squash pass 1's
5262 if (pass1_err
== unsupported_64bit
)
5268 switch (pass1_mnem
? pass1_err
: i
.error
)
5272 case operand_size_mismatch
:
5273 err_msg
= _("operand size mismatch");
5275 case operand_type_mismatch
:
5276 err_msg
= _("operand type mismatch");
5278 case register_type_mismatch
:
5279 err_msg
= _("register type mismatch");
5281 case number_of_operands_mismatch
:
5282 err_msg
= _("number of operands mismatch");
5284 case invalid_instruction_suffix
:
5285 err_msg
= _("invalid instruction suffix");
5288 err_msg
= _("constant doesn't fit in 4 bits");
5290 case unsupported_with_intel_mnemonic
:
5291 err_msg
= _("unsupported with Intel mnemonic");
5293 case unsupported_syntax
:
5294 err_msg
= _("unsupported syntax");
5297 as_bad (_("unsupported instruction `%s'"),
5298 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5300 case unsupported_on_arch
:
5301 as_bad (_("`%s' is not supported on `%s%s'"),
5302 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5303 cpu_arch_name
? cpu_arch_name
: default_arch
,
5304 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5306 case unsupported_64bit
:
5307 if (ISLOWER (mnem_suffix
))
5309 if (flag_code
== CODE_64BIT
)
5310 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5311 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5314 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5315 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5320 if (flag_code
== CODE_64BIT
)
5321 as_bad (_("`%s' is not supported in 64-bit mode"),
5322 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5324 as_bad (_("`%s' is only supported in 64-bit mode"),
5325 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5328 case invalid_sib_address
:
5329 err_msg
= _("invalid SIB address");
5331 case invalid_vsib_address
:
5332 err_msg
= _("invalid VSIB address");
5334 case invalid_vector_register_set
:
5335 err_msg
= _("mask, index, and destination registers must be distinct");
5337 case invalid_tmm_register_set
:
5338 err_msg
= _("all tmm registers must be distinct");
5340 case invalid_dest_and_src_register_set
:
5341 err_msg
= _("destination and source registers must be distinct");
5343 case unsupported_vector_index_register
:
5344 err_msg
= _("unsupported vector index register");
5346 case unsupported_broadcast
:
5347 err_msg
= _("unsupported broadcast");
5349 case broadcast_needed
:
5350 err_msg
= _("broadcast is needed for operand of such type");
5352 case unsupported_masking
:
5353 err_msg
= _("unsupported masking");
5355 case mask_not_on_destination
:
5356 err_msg
= _("mask not on destination operand");
5358 case no_default_mask
:
5359 err_msg
= _("default mask isn't allowed");
5361 case unsupported_rc_sae
:
5362 err_msg
= _("unsupported static rounding/sae");
5364 case invalid_register_operand
:
5365 err_msg
= _("invalid register operand");
5367 case internal_error
:
5368 err_msg
= _("internal error");
5371 as_bad (_("%s for `%s'"), err_msg
,
5372 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5378 if (sse_check
!= check_none
5379 /* The opcode space check isn't strictly needed; it's there only to
5380 bypass the logic below when easily possible. */
5381 && t
->opcode_space
>= SPACE_0F
5382 && t
->opcode_space
<= SPACE_0F3A
5383 && !is_cpu (&i
.tm
, CpuSSE4a
)
5384 && !is_any_vex_encoding (t
))
5388 for (j
= 0; j
< t
->operands
; ++j
)
5390 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5392 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5396 if (j
>= t
->operands
&& simd
)
5397 (sse_check
== check_warning
5399 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5402 if (i
.tm
.opcode_modifier
.fwait
)
5403 if (!add_prefix (FWAIT_OPCODE
))
5406 /* Check if REP prefix is OK. */
5407 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5409 as_bad (_("invalid instruction `%s' after `%s'"),
5410 insn_name (&i
.tm
), i
.rep_prefix
);
5414 /* Check for lock without a lockable instruction. Destination operand
5415 must be memory unless it is xchg (0x86). */
5416 if (i
.prefix
[LOCK_PREFIX
])
5418 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5419 || i
.mem_operands
== 0
5420 || (i
.tm
.base_opcode
!= 0x86
5421 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5423 as_bad (_("expecting lockable instruction after `lock'"));
5427 /* Zap the redundant prefix from XCHG when optimizing. */
5428 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5429 i
.prefix
[LOCK_PREFIX
] = 0;
5432 if (is_any_vex_encoding (&i
.tm
)
5433 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5434 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5436 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5437 if (i
.prefix
[DATA_PREFIX
])
5439 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5443 /* Don't allow e.g. KMOV in TLS code sequences. */
5444 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5447 case BFD_RELOC_386_TLS_GOTIE
:
5448 case BFD_RELOC_386_TLS_LE_32
:
5449 case BFD_RELOC_X86_64_GOTTPOFF
:
5450 case BFD_RELOC_X86_64_TLSLD
:
5451 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5458 /* Check if HLE prefix is OK. */
5459 if (i
.hle_prefix
&& !check_hle ())
5462 /* Check BND prefix. */
5463 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5464 as_bad (_("expecting valid branch instruction after `bnd'"));
5466 /* Check NOTRACK prefix. */
5467 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5468 as_bad (_("expecting indirect branch instruction after `notrack'"));
5470 if (is_cpu (&i
.tm
, CpuMPX
))
5472 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5473 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5474 else if (flag_code
!= CODE_16BIT
5475 ? i
.prefix
[ADDR_PREFIX
]
5476 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5477 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5480 /* Insert BND prefix. */
5481 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5483 if (!i
.prefix
[BND_PREFIX
])
5484 add_prefix (BND_PREFIX_OPCODE
);
5485 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5487 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5488 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5492 /* Check string instruction segment overrides. */
5493 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5495 gas_assert (i
.mem_operands
);
5496 if (!check_string ())
5498 i
.disp_operands
= 0;
5501 /* The memory operand of (%dx) should be only used with input/output
5502 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5503 if (i
.input_output_operand
5504 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5505 || i
.tm
.opcode_space
!= SPACE_BASE
))
5507 as_bad (_("input/output port address isn't allowed with `%s'"),
5512 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5513 optimize_encoding ();
5515 /* Past optimization there's no need to distinguish vex_encoding_evex and
5516 vex_encoding_evex512 anymore. */
5517 if (i
.vec_encoding
== vex_encoding_evex512
)
5518 i
.vec_encoding
= vex_encoding_evex
;
5520 if (use_unaligned_vector_move
)
5521 encode_with_unaligned_vector_move ();
5523 if (!process_suffix ())
5526 /* Check if IP-relative addressing requirements can be satisfied. */
5527 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5528 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5529 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5531 /* Update operand types and check extended states. */
5532 for (j
= 0; j
< i
.operands
; j
++)
5534 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5535 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5540 i
.xstate
|= xstate_mmx
;
5543 i
.xstate
|= xstate_mask
;
5546 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5547 i
.xstate
|= xstate_tmm
;
5548 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5549 && !i
.tm
.opcode_modifier
.vex
5550 && vector_size
>= VSZ512
)
5551 i
.xstate
|= xstate_zmm
;
5552 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5553 && vector_size
>= VSZ256
)
5554 i
.xstate
|= xstate_ymm
;
5555 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5556 i
.xstate
|= xstate_xmm
;
5561 /* Make still unresolved immediate matches conform to size of immediate
5562 given in i.suffix. */
5563 if (!finalize_imm ())
5566 if (i
.types
[0].bitfield
.imm1
)
5567 i
.imm_operands
= 0; /* kludge for shift insns. */
5569 /* For insns with operands there are more diddles to do to the opcode. */
5572 if (!process_operands ())
5575 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5577 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5578 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5581 if (is_any_vex_encoding (&i
.tm
))
5583 if (!cpu_arch_flags
.bitfield
.cpui286
)
5585 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5590 /* Check for explicit REX prefix. */
5591 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5593 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5597 if (i
.tm
.opcode_modifier
.vex
)
5598 build_vex_prefix (t
);
5600 build_evex_prefix ();
5602 /* The individual REX.RXBW bits got consumed. */
5603 i
.rex
&= REX_OPCODE
;
5606 /* Handle conversion of 'int $3' --> special int3 insn. */
5607 if (i
.tm
.mnem_off
== MN_int
5608 && i
.op
[0].imms
->X_add_number
== 3)
5610 i
.tm
.base_opcode
= INT3_OPCODE
;
5614 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5615 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5616 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5617 && i
.op
[0].disps
->X_op
== O_constant
)
5619 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5620 the absolute address given by the constant. Since ix86 jumps and
5621 calls are pc relative, we need to generate a reloc. */
5622 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5623 i
.op
[0].disps
->X_op
= O_symbol
;
5626 /* For 8 bit registers we need an empty rex prefix. Also if the
5627 instruction already has a prefix, we need to convert old
5628 registers to new ones. */
5630 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5631 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5632 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5633 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5634 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5635 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5640 i
.rex
|= REX_OPCODE
;
5641 for (x
= 0; x
< 2; x
++)
5643 /* Look for 8 bit operand that uses old registers. */
5644 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5645 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5647 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5648 /* In case it is "hi" register, give up. */
5649 if (i
.op
[x
].regs
->reg_num
> 3)
5650 as_bad (_("can't encode register '%s%s' in an "
5651 "instruction requiring REX prefix."),
5652 register_prefix
, i
.op
[x
].regs
->reg_name
);
5654 /* Otherwise it is equivalent to the extended register.
5655 Since the encoding doesn't change this is merely
5656 cosmetic cleanup for debug output. */
5658 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5663 if (i
.rex
== 0 && i
.rex_encoding
)
5665 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5666 that uses legacy register. If it is "hi" register, don't add
5667 the REX_OPCODE byte. */
5669 for (x
= 0; x
< 2; x
++)
5670 if (i
.types
[x
].bitfield
.class == Reg
5671 && i
.types
[x
].bitfield
.byte
5672 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5673 && i
.op
[x
].regs
->reg_num
> 3)
5675 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5676 i
.rex_encoding
= false;
5685 add_prefix (REX_OPCODE
| i
.rex
);
5687 insert_lfence_before ();
5689 /* We are ready to output the insn. */
5692 insert_lfence_after ();
5694 last_insn
.seg
= now_seg
;
5696 if (i
.tm
.opcode_modifier
.isprefix
)
5698 last_insn
.kind
= last_insn_prefix
;
5699 last_insn
.name
= insn_name (&i
.tm
);
5700 last_insn
.file
= as_where (&last_insn
.line
);
5703 last_insn
.kind
= last_insn_other
;
5706 /* The Q suffix is generally valid only in 64-bit mode, with very few
5707 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5708 and fisttp only one of their two templates is matched below: That's
5709 sufficient since other relevant attributes are the same between both
5710 respective templates. */
5711 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5713 return flag_code
== CODE_64BIT
5714 || (t
->opcode_space
== SPACE_BASE
5715 && t
->base_opcode
== 0xdf
5716 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5717 || t
->mnem_off
== MN_cmpxchg8b
;
5721 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5723 const char *l
= line
, *token_start
= l
;
5725 bool pass1
= !current_templates
;
5727 const insn_template
*t
;
5733 /* Pseudo-prefixes start with an opening figure brace. */
5734 if ((*mnem_p
= *l
) == '{')
5739 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5744 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5747 as_bad (_("no such instruction: `%s'"), token_start
);
5752 /* Pseudo-prefixes end with a closing figure brace. */
5753 if (*mnemonic
== '{' && *l
== '}')
5756 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5760 /* Point l at the closing brace if there's no other separator. */
5761 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5762 && *l
!= PREFIX_SEPARATOR
)
5765 else if (!is_space_char (*l
)
5766 && *l
!= END_OF_INSN
5768 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5772 as_bad (_("invalid character %s in mnemonic"),
5773 output_invalid (*l
));
5776 if (token_start
== l
)
5778 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5779 as_bad (_("expecting prefix; got nothing"));
5781 as_bad (_("expecting mnemonic; got nothing"));
5785 /* Look up instruction (or prefix) via hash table. */
5786 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5788 if (*l
!= END_OF_INSN
5789 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5790 && current_templates
5791 && current_templates
->start
->opcode_modifier
.isprefix
)
5793 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5795 as_bad ((flag_code
!= CODE_64BIT
5796 ? _("`%s' is only supported in 64-bit mode")
5797 : _("`%s' is not supported in 64-bit mode")),
5798 insn_name (current_templates
->start
));
5801 /* If we are in 16-bit mode, do not allow addr16 or data16.
5802 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5803 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5804 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5805 && flag_code
!= CODE_64BIT
5806 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5807 ^ (flag_code
== CODE_16BIT
)))
5809 as_bad (_("redundant %s prefix"),
5810 insn_name (current_templates
->start
));
5814 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5816 /* Handle pseudo prefixes. */
5817 switch (current_templates
->start
->extension_opcode
)
5821 i
.disp_encoding
= disp_encoding_8bit
;
5825 i
.disp_encoding
= disp_encoding_16bit
;
5829 i
.disp_encoding
= disp_encoding_32bit
;
5833 i
.dir_encoding
= dir_encoding_load
;
5837 i
.dir_encoding
= dir_encoding_store
;
5841 i
.vec_encoding
= vex_encoding_vex
;
5845 i
.vec_encoding
= vex_encoding_vex3
;
5849 i
.vec_encoding
= vex_encoding_evex
;
5853 i
.rex_encoding
= true;
5855 case Prefix_NoOptimize
:
5857 i
.no_optimize
= true;
5865 /* Add prefix, checking for repeated prefixes. */
5866 switch (add_prefix (current_templates
->start
->base_opcode
))
5871 if (is_cpu (current_templates
->start
, CpuIBT
))
5872 i
.notrack_prefix
= insn_name (current_templates
->start
);
5875 if (is_cpu (current_templates
->start
, CpuHLE
))
5876 i
.hle_prefix
= insn_name (current_templates
->start
);
5877 else if (is_cpu (current_templates
->start
, CpuMPX
))
5878 i
.bnd_prefix
= insn_name (current_templates
->start
);
5880 i
.rep_prefix
= insn_name (current_templates
->start
);
5886 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5896 if (!current_templates
)
5898 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5899 Check if we should swap operand or force 32bit displacement in
5901 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5902 i
.dir_encoding
= dir_encoding_swap
;
5903 else if (mnem_p
- 3 == dot_p
5906 i
.disp_encoding
= disp_encoding_8bit
;
5907 else if (mnem_p
- 4 == dot_p
5911 i
.disp_encoding
= disp_encoding_32bit
;
5916 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5919 if (!current_templates
|| !pass1
)
5921 current_templates
= NULL
;
5924 if (mnem_p
> mnemonic
)
5926 /* See if we can get a match by trimming off a suffix. */
5929 case WORD_MNEM_SUFFIX
:
5930 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5931 i
.suffix
= SHORT_MNEM_SUFFIX
;
5934 case BYTE_MNEM_SUFFIX
:
5935 case QWORD_MNEM_SUFFIX
:
5936 i
.suffix
= mnem_p
[-1];
5939 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5941 case SHORT_MNEM_SUFFIX
:
5942 case LONG_MNEM_SUFFIX
:
5945 i
.suffix
= mnem_p
[-1];
5948 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5956 if (intel_float_operand (mnemonic
) == 1)
5957 i
.suffix
= SHORT_MNEM_SUFFIX
;
5959 i
.suffix
= LONG_MNEM_SUFFIX
;
5962 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5964 /* For compatibility reasons accept MOVSD and CMPSD without
5965 operands even in AT&T mode. */
5966 else if (*l
== END_OF_INSN
5967 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5971 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5972 if (current_templates
!= NULL
5974 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5975 && current_templates
->start
->opcode_space
5977 && mnem_p
[-2] == 's')
5979 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5980 mnemonic
, mnemonic
);
5981 i
.suffix
= LONG_MNEM_SUFFIX
;
5985 current_templates
= NULL
;
5993 if (!current_templates
)
5996 as_bad (_("no such instruction: `%s'"), token_start
);
6001 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
6002 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
6004 /* Check for a branch hint. We allow ",pt" and ",pn" for
6005 predict taken and predict not taken respectively.
6006 I'm not sure that branch hints actually do anything on loop
6007 and jcxz insns (JumpByte) for current Pentium4 chips. They
6008 may work in the future and it doesn't hurt to accept them
6010 if (l
[0] == ',' && l
[1] == 'p')
6014 if (!add_prefix (DS_PREFIX_OPCODE
))
6018 else if (l
[2] == 'n')
6020 if (!add_prefix (CS_PREFIX_OPCODE
))
6026 /* Any other comma loses. */
6029 as_bad (_("invalid character %s in mnemonic"),
6030 output_invalid (*l
));
6034 /* Check if instruction is supported on specified architecture. */
6036 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6038 supported
|= cpu_flags_match (t
);
6040 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6041 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6043 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6049 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6050 i
.error
= unsupported_on_arch
;
6052 i
.error
= unsupported_64bit
;
6059 parse_operands (char *l
, const char *mnemonic
)
6063 /* 1 if operand is pending after ','. */
6064 unsigned int expecting_operand
= 0;
6066 while (*l
!= END_OF_INSN
)
6068 /* Non-zero if operand parens not balanced. */
6069 unsigned int paren_not_balanced
= 0;
6070 /* True if inside double quotes. */
6071 bool in_quotes
= false;
6073 /* Skip optional white space before operand. */
6074 if (is_space_char (*l
))
6076 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6078 as_bad (_("invalid character %s before operand %d"),
6079 output_invalid (*l
),
6083 token_start
= l
; /* After white space. */
6084 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6086 if (*l
== END_OF_INSN
)
6090 as_bad (_("unbalanced double quotes in operand %d."),
6094 if (paren_not_balanced
)
6096 know (!intel_syntax
);
6097 as_bad (_("unbalanced parenthesis in operand %d."),
6102 break; /* we are done */
6104 else if (*l
== '\\' && l
[1] == '"')
6107 in_quotes
= !in_quotes
;
6108 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6110 as_bad (_("invalid character %s in operand %d"),
6111 output_invalid (*l
),
6115 if (!intel_syntax
&& !in_quotes
)
6118 ++paren_not_balanced
;
6120 --paren_not_balanced
;
6124 if (l
!= token_start
)
6125 { /* Yes, we've read in another operand. */
6126 unsigned int operand_ok
;
6127 this_operand
= i
.operands
++;
6128 if (i
.operands
> MAX_OPERANDS
)
6130 as_bad (_("spurious operands; (%d operands/instruction max)"),
6134 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6135 /* Now parse operand adding info to 'i' as we go along. */
6136 END_STRING_AND_SAVE (l
);
6138 if (i
.mem_operands
> 1)
6140 as_bad (_("too many memory references for `%s'"),
6147 i386_intel_operand (token_start
,
6148 intel_float_operand (mnemonic
));
6150 operand_ok
= i386_att_operand (token_start
);
6152 RESTORE_END_STRING (l
);
6158 if (expecting_operand
)
6160 expecting_operand_after_comma
:
6161 as_bad (_("expecting operand after ','; got nothing"));
6166 as_bad (_("expecting operand before ','; got nothing"));
6171 /* Now *l must be either ',' or END_OF_INSN. */
6174 if (*++l
== END_OF_INSN
)
6176 /* Just skip it, if it's \n complain. */
6177 goto expecting_operand_after_comma
;
6179 expecting_operand
= 1;
6186 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6188 union i386_op temp_op
;
6189 i386_operand_type temp_type
;
6190 unsigned int temp_flags
;
6191 enum bfd_reloc_code_real temp_reloc
;
6193 temp_type
= i
.types
[xchg2
];
6194 i
.types
[xchg2
] = i
.types
[xchg1
];
6195 i
.types
[xchg1
] = temp_type
;
6197 temp_flags
= i
.flags
[xchg2
];
6198 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6199 i
.flags
[xchg1
] = temp_flags
;
6201 temp_op
= i
.op
[xchg2
];
6202 i
.op
[xchg2
] = i
.op
[xchg1
];
6203 i
.op
[xchg1
] = temp_op
;
6205 temp_reloc
= i
.reloc
[xchg2
];
6206 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6207 i
.reloc
[xchg1
] = temp_reloc
;
6209 temp_flags
= i
.imm_bits
[xchg2
];
6210 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6211 i
.imm_bits
[xchg1
] = temp_flags
;
6215 if (i
.mask
.operand
== xchg1
)
6216 i
.mask
.operand
= xchg2
;
6217 else if (i
.mask
.operand
== xchg2
)
6218 i
.mask
.operand
= xchg1
;
6220 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6222 if (i
.broadcast
.operand
== xchg1
)
6223 i
.broadcast
.operand
= xchg2
;
6224 else if (i
.broadcast
.operand
== xchg2
)
6225 i
.broadcast
.operand
= xchg1
;
6230 swap_operands (void)
6236 swap_2_operands (1, i
.operands
- 2);
6240 swap_2_operands (0, i
.operands
- 1);
6246 if (i
.mem_operands
== 2)
6248 const reg_entry
*temp_seg
;
6249 temp_seg
= i
.seg
[0];
6250 i
.seg
[0] = i
.seg
[1];
6251 i
.seg
[1] = temp_seg
;
6255 /* Try to ensure constant immediates are represented in the smallest
6260 char guess_suffix
= 0;
6264 guess_suffix
= i
.suffix
;
6265 else if (i
.reg_operands
)
6267 /* Figure out a suffix from the last register operand specified.
6268 We can't do this properly yet, i.e. excluding special register
6269 instances, but the following works for instructions with
6270 immediates. In any case, we can't set i.suffix yet. */
6271 for (op
= i
.operands
; --op
>= 0;)
6272 if (i
.types
[op
].bitfield
.class != Reg
)
6274 else if (i
.types
[op
].bitfield
.byte
)
6276 guess_suffix
= BYTE_MNEM_SUFFIX
;
6279 else if (i
.types
[op
].bitfield
.word
)
6281 guess_suffix
= WORD_MNEM_SUFFIX
;
6284 else if (i
.types
[op
].bitfield
.dword
)
6286 guess_suffix
= LONG_MNEM_SUFFIX
;
6289 else if (i
.types
[op
].bitfield
.qword
)
6291 guess_suffix
= QWORD_MNEM_SUFFIX
;
6295 else if ((flag_code
== CODE_16BIT
)
6296 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6297 guess_suffix
= WORD_MNEM_SUFFIX
;
6298 else if (flag_code
!= CODE_64BIT
6299 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6300 /* A more generic (but also more involved) way of dealing
6301 with the special case(s) would be to go look for
6302 DefaultSize attributes on any of the templates. */
6303 && current_templates
->start
->mnem_off
!= MN_push
))
6304 guess_suffix
= LONG_MNEM_SUFFIX
;
6306 for (op
= i
.operands
; --op
>= 0;)
6307 if (operand_type_check (i
.types
[op
], imm
))
6309 switch (i
.op
[op
].imms
->X_op
)
6312 /* If a suffix is given, this operand may be shortened. */
6313 switch (guess_suffix
)
6315 case LONG_MNEM_SUFFIX
:
6316 i
.types
[op
].bitfield
.imm32
= 1;
6317 i
.types
[op
].bitfield
.imm64
= 1;
6319 case WORD_MNEM_SUFFIX
:
6320 i
.types
[op
].bitfield
.imm16
= 1;
6321 i
.types
[op
].bitfield
.imm32
= 1;
6322 i
.types
[op
].bitfield
.imm32s
= 1;
6323 i
.types
[op
].bitfield
.imm64
= 1;
6325 case BYTE_MNEM_SUFFIX
:
6326 i
.types
[op
].bitfield
.imm8
= 1;
6327 i
.types
[op
].bitfield
.imm8s
= 1;
6328 i
.types
[op
].bitfield
.imm16
= 1;
6329 i
.types
[op
].bitfield
.imm32
= 1;
6330 i
.types
[op
].bitfield
.imm32s
= 1;
6331 i
.types
[op
].bitfield
.imm64
= 1;
6335 /* If this operand is at most 16 bits, convert it
6336 to a signed 16 bit number before trying to see
6337 whether it will fit in an even smaller size.
6338 This allows a 16-bit operand such as $0xffe0 to
6339 be recognised as within Imm8S range. */
6340 if ((i
.types
[op
].bitfield
.imm16
)
6341 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6343 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6344 ^ 0x8000) - 0x8000);
6347 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6348 if ((i
.types
[op
].bitfield
.imm32
)
6349 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6351 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6352 ^ ((offsetT
) 1 << 31))
6353 - ((offsetT
) 1 << 31));
6357 = operand_type_or (i
.types
[op
],
6358 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6360 /* We must avoid matching of Imm32 templates when 64bit
6361 only immediate is available. */
6362 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6363 i
.types
[op
].bitfield
.imm32
= 0;
6370 /* Symbols and expressions. */
6372 /* Convert symbolic operand to proper sizes for matching, but don't
6373 prevent matching a set of insns that only supports sizes other
6374 than those matching the insn suffix. */
6376 i386_operand_type mask
, allowed
;
6377 const insn_template
*t
= current_templates
->start
;
6379 operand_type_set (&mask
, 0);
6380 switch (guess_suffix
)
6382 case QWORD_MNEM_SUFFIX
:
6383 mask
.bitfield
.imm64
= 1;
6384 mask
.bitfield
.imm32s
= 1;
6386 case LONG_MNEM_SUFFIX
:
6387 mask
.bitfield
.imm32
= 1;
6389 case WORD_MNEM_SUFFIX
:
6390 mask
.bitfield
.imm16
= 1;
6392 case BYTE_MNEM_SUFFIX
:
6393 mask
.bitfield
.imm8
= 1;
6399 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6400 while (++t
< current_templates
->end
)
6402 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6403 allowed
= operand_type_and (allowed
, mask
);
6406 if (!operand_type_all_zero (&allowed
))
6407 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6414 /* Try to use the smallest displacement type too. */
6416 optimize_disp (const insn_template
*t
)
6420 if (!want_disp32 (t
)
6421 && (!t
->opcode_modifier
.jump
6422 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6424 for (op
= 0; op
< i
.operands
; ++op
)
6426 const expressionS
*exp
= i
.op
[op
].disps
;
6428 if (!operand_type_check (i
.types
[op
], disp
))
6431 if (exp
->X_op
!= O_constant
)
6434 /* Since displacement is signed extended to 64bit, don't allow
6435 disp32 if it is out of range. */
6436 if (fits_in_signed_long (exp
->X_add_number
))
6439 i
.types
[op
].bitfield
.disp32
= 0;
6440 if (i
.types
[op
].bitfield
.baseindex
)
6442 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6443 (uint64_t) exp
->X_add_number
);
6449 /* Don't optimize displacement for movabs since it only takes 64bit
6451 if (i
.disp_encoding
> disp_encoding_8bit
6452 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6455 for (op
= i
.operands
; op
-- > 0;)
6456 if (operand_type_check (i
.types
[op
], disp
))
6458 if (i
.op
[op
].disps
->X_op
== O_constant
)
6460 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6462 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6464 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6465 i
.op
[op
].disps
= NULL
;
6470 if (i
.types
[op
].bitfield
.disp16
6471 && fits_in_unsigned_word (op_disp
))
6473 /* If this operand is at most 16 bits, convert
6474 to a signed 16 bit number and don't use 64bit
6476 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6477 i
.types
[op
].bitfield
.disp64
= 0;
6481 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6482 if ((flag_code
!= CODE_64BIT
6483 ? i
.types
[op
].bitfield
.disp32
6485 && (!t
->opcode_modifier
.jump
6486 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6487 && fits_in_unsigned_long (op_disp
))
6489 /* If this operand is at most 32 bits, convert
6490 to a signed 32 bit number and don't use 64bit
6492 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6493 i
.types
[op
].bitfield
.disp64
= 0;
6494 i
.types
[op
].bitfield
.disp32
= 1;
6497 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6499 i
.types
[op
].bitfield
.disp64
= 0;
6500 i
.types
[op
].bitfield
.disp32
= 1;
6503 if ((i
.types
[op
].bitfield
.disp32
6504 || i
.types
[op
].bitfield
.disp16
)
6505 && fits_in_disp8 (op_disp
))
6506 i
.types
[op
].bitfield
.disp8
= 1;
6508 i
.op
[op
].disps
->X_add_number
= op_disp
;
6510 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6511 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6513 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6514 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6515 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6518 /* We only support 64bit displacement on constants. */
6519 i
.types
[op
].bitfield
.disp64
= 0;
6525 /* Return 1 if there is a match in broadcast bytes between operand
6526 GIVEN and instruction template T. */
6529 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6531 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6532 && i
.types
[given
].bitfield
.byte
)
6533 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6534 && i
.types
[given
].bitfield
.word
)
6535 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6536 && i
.types
[given
].bitfield
.dword
)
6537 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6538 && i
.types
[given
].bitfield
.qword
));
6541 /* Check if operands are valid for the instruction. */
6544 check_VecOperands (const insn_template
*t
)
6549 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6550 any one operand are implicity requiring AVX512VL support if the actual
6551 operand size is YMMword or XMMword. Since this function runs after
6552 template matching, there's no need to check for YMMword/XMMword in
6554 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6555 if (!cpu_flags_all_zero (&cpu
)
6556 && !is_cpu (t
, CpuAVX512VL
)
6557 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6558 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6560 for (op
= 0; op
< t
->operands
; ++op
)
6562 if (t
->operand_types
[op
].bitfield
.zmmword
6563 && (i
.types
[op
].bitfield
.ymmword
6564 || i
.types
[op
].bitfield
.xmmword
))
6566 i
.error
= unsupported
;
6572 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6573 requiring AVX2 support if the actual operand size is YMMword. */
6574 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6575 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6577 for (op
= 0; op
< t
->operands
; ++op
)
6579 if (t
->operand_types
[op
].bitfield
.xmmword
6580 && i
.types
[op
].bitfield
.ymmword
)
6582 i
.error
= unsupported
;
6588 /* Without VSIB byte, we can't have a vector register for index. */
6589 if (!t
->opcode_modifier
.sib
6591 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6592 || i
.index_reg
->reg_type
.bitfield
.ymmword
6593 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6595 i
.error
= unsupported_vector_index_register
;
6599 /* Check if default mask is allowed. */
6600 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6601 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6603 i
.error
= no_default_mask
;
6607 /* For VSIB byte, we need a vector register for index, and all vector
6608 registers must be distinct. */
6609 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6612 || !((t
->opcode_modifier
.sib
== VECSIB128
6613 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6614 || (t
->opcode_modifier
.sib
== VECSIB256
6615 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6616 || (t
->opcode_modifier
.sib
== VECSIB512
6617 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6619 i
.error
= invalid_vsib_address
;
6623 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6624 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6626 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6627 gas_assert (i
.types
[0].bitfield
.xmmword
6628 || i
.types
[0].bitfield
.ymmword
);
6629 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6630 gas_assert (i
.types
[2].bitfield
.xmmword
6631 || i
.types
[2].bitfield
.ymmword
);
6632 if (operand_check
== check_none
)
6634 if (register_number (i
.op
[0].regs
)
6635 != register_number (i
.index_reg
)
6636 && register_number (i
.op
[2].regs
)
6637 != register_number (i
.index_reg
)
6638 && register_number (i
.op
[0].regs
)
6639 != register_number (i
.op
[2].regs
))
6641 if (operand_check
== check_error
)
6643 i
.error
= invalid_vector_register_set
;
6646 as_warn (_("mask, index, and destination registers should be distinct"));
6648 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6650 if (i
.types
[1].bitfield
.class == RegSIMD
6651 && (i
.types
[1].bitfield
.xmmword
6652 || i
.types
[1].bitfield
.ymmword
6653 || i
.types
[1].bitfield
.zmmword
)
6654 && (register_number (i
.op
[1].regs
)
6655 == register_number (i
.index_reg
)))
6657 if (operand_check
== check_error
)
6659 i
.error
= invalid_vector_register_set
;
6662 if (operand_check
!= check_none
)
6663 as_warn (_("index and destination registers should be distinct"));
6668 /* For AMX instructions with 3 TMM register operands, all operands
6669 must be distinct. */
6670 if (i
.reg_operands
== 3
6671 && t
->operand_types
[0].bitfield
.tmmword
6672 && (i
.op
[0].regs
== i
.op
[1].regs
6673 || i
.op
[0].regs
== i
.op
[2].regs
6674 || i
.op
[1].regs
== i
.op
[2].regs
))
6676 i
.error
= invalid_tmm_register_set
;
6680 /* For some special instructions require that destination must be distinct
6681 from source registers. */
6682 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6684 unsigned int dest_reg
= i
.operands
- 1;
6686 know (i
.operands
>= 3);
6688 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6689 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6690 || (i
.reg_operands
> 2
6691 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6693 i
.error
= invalid_dest_and_src_register_set
;
6698 /* Check if broadcast is supported by the instruction and is applied
6699 to the memory operand. */
6700 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6702 i386_operand_type type
, overlap
;
6704 /* Check if specified broadcast is supported in this instruction,
6705 and its broadcast bytes match the memory operand. */
6706 op
= i
.broadcast
.operand
;
6707 if (!t
->opcode_modifier
.broadcast
6708 || !(i
.flags
[op
] & Operand_Mem
)
6709 || (!i
.types
[op
].bitfield
.unspecified
6710 && !match_broadcast_size (t
, op
)))
6713 i
.error
= unsupported_broadcast
;
6717 operand_type_set (&type
, 0);
6718 switch (get_broadcast_bytes (t
, false))
6721 type
.bitfield
.word
= 1;
6724 type
.bitfield
.dword
= 1;
6727 type
.bitfield
.qword
= 1;
6730 type
.bitfield
.xmmword
= 1;
6733 if (vector_size
< VSZ256
)
6735 type
.bitfield
.ymmword
= 1;
6738 if (vector_size
< VSZ512
)
6740 type
.bitfield
.zmmword
= 1;
6746 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6747 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6748 && t
->operand_types
[op
].bitfield
.byte
6749 + t
->operand_types
[op
].bitfield
.word
6750 + t
->operand_types
[op
].bitfield
.dword
6751 + t
->operand_types
[op
].bitfield
.qword
> 1)
6753 overlap
.bitfield
.xmmword
= 0;
6754 overlap
.bitfield
.ymmword
= 0;
6755 overlap
.bitfield
.zmmword
= 0;
6757 if (operand_type_all_zero (&overlap
))
6760 if (t
->opcode_modifier
.checkoperandsize
)
6764 type
.bitfield
.baseindex
= 1;
6765 for (j
= 0; j
< i
.operands
; ++j
)
6768 && !operand_type_register_match(i
.types
[j
],
6769 t
->operand_types
[j
],
6771 t
->operand_types
[op
]))
6776 /* If broadcast is supported in this instruction, we need to check if
6777 operand of one-element size isn't specified without broadcast. */
6778 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6780 /* Find memory operand. */
6781 for (op
= 0; op
< i
.operands
; op
++)
6782 if (i
.flags
[op
] & Operand_Mem
)
6784 gas_assert (op
< i
.operands
);
6785 /* Check size of the memory operand. */
6786 if (match_broadcast_size (t
, op
))
6788 i
.error
= broadcast_needed
;
6793 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6795 /* Check if requested masking is supported. */
6798 if (!t
->opcode_modifier
.masking
)
6800 i
.error
= unsupported_masking
;
6804 /* Common rules for masking:
6805 - mask register destinations permit only zeroing-masking, without
6806 that actually being expressed by a {z} operand suffix or EVEX.z,
6807 - memory destinations allow only merging-masking,
6808 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6811 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6812 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6813 || t
->opcode_modifier
.sib
))
6815 i
.error
= unsupported_masking
;
6820 /* Check if masking is applied to dest operand. */
6821 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6823 i
.error
= mask_not_on_destination
;
6828 if (i
.rounding
.type
!= rc_none
)
6830 if (!t
->opcode_modifier
.sae
6831 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6834 i
.error
= unsupported_rc_sae
;
6838 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6840 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6842 for (op
= 0; op
< t
->operands
; ++op
)
6843 if (i
.types
[op
].bitfield
.zmmword
)
6845 if (op
>= t
->operands
)
6847 i
.error
= operand_size_mismatch
;
6853 /* Check the special Imm4 cases; must be the first operand. */
6854 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6856 if (i
.op
[0].imms
->X_op
!= O_constant
6857 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6863 /* Turn off Imm<N> so that update_imm won't complain. */
6864 operand_type_set (&i
.types
[0], 0);
6867 /* Check vector Disp8 operand. */
6868 if (t
->opcode_modifier
.disp8memshift
6869 && (!t
->opcode_modifier
.vex
6870 || need_evex_encoding ())
6871 && i
.disp_encoding
<= disp_encoding_8bit
)
6873 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6874 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6875 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6876 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6879 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6882 for (op
= 0; op
< i
.operands
; op
++)
6883 if (i
.flags
[op
] & Operand_Mem
)
6885 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6886 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6887 else if (t
->operand_types
[op
].bitfield
.xmmword
6888 + t
->operand_types
[op
].bitfield
.ymmword
6889 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6890 type
= &t
->operand_types
[op
];
6891 else if (!i
.types
[op
].bitfield
.unspecified
)
6892 type
= &i
.types
[op
];
6893 else /* Ambiguities get resolved elsewhere. */
6894 fallback
= &t
->operand_types
[op
];
6896 else if (i
.types
[op
].bitfield
.class == RegSIMD
6897 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6899 if (i
.types
[op
].bitfield
.zmmword
)
6901 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6903 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6907 if (!type
&& !i
.memshift
)
6911 if (type
->bitfield
.zmmword
)
6913 else if (type
->bitfield
.ymmword
)
6915 else if (type
->bitfield
.xmmword
)
6919 /* For the check in fits_in_disp8(). */
6920 if (i
.memshift
== 0)
6924 for (op
= 0; op
< i
.operands
; op
++)
6925 if (operand_type_check (i
.types
[op
], disp
)
6926 && i
.op
[op
].disps
->X_op
== O_constant
)
6928 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6930 i
.types
[op
].bitfield
.disp8
= 1;
6933 i
.types
[op
].bitfield
.disp8
= 0;
6942 /* Check if encoding requirements are met by the instruction. */
6945 VEX_check_encoding (const insn_template
*t
)
6947 if (i
.vec_encoding
== vex_encoding_error
)
6949 i
.error
= unsupported
;
6953 /* Vector size restrictions. */
6954 if ((vector_size
< VSZ512
6955 && (t
->opcode_modifier
.evex
== EVEX512
6956 || t
->opcode_modifier
.vsz
>= VSZ512
))
6957 || (vector_size
< VSZ256
6958 && (t
->opcode_modifier
.evex
== EVEX256
6959 || t
->opcode_modifier
.vex
== VEX256
6960 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6962 i
.error
= unsupported
;
6966 if (i
.vec_encoding
== vex_encoding_evex
6967 || i
.vec_encoding
== vex_encoding_evex512
)
6969 /* This instruction must be encoded with EVEX prefix. */
6970 if (!is_evex_encoding (t
))
6972 i
.error
= unsupported
;
6978 if (!t
->opcode_modifier
.vex
)
6980 /* This instruction template doesn't have VEX prefix. */
6981 if (i
.vec_encoding
!= vex_encoding_default
)
6983 i
.error
= unsupported
;
6992 /* Helper function for the progress() macro in match_template(). */
6993 static INLINE
enum i386_error
progress (enum i386_error
new,
6994 enum i386_error last
,
6995 unsigned int line
, unsigned int *line_p
)
6997 if (line
<= *line_p
)
7003 static const insn_template
*
7004 match_template (char mnem_suffix
)
7006 /* Points to template once we've found it. */
7007 const insn_template
*t
;
7008 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
7009 i386_operand_type overlap4
;
7010 unsigned int found_reverse_match
;
7011 i386_operand_type operand_types
[MAX_OPERANDS
];
7012 int addr_prefix_disp
;
7013 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7014 enum i386_error specific_error
= number_of_operands_mismatch
;
7015 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7017 #if MAX_OPERANDS != 5
7018 # error "MAX_OPERANDS must be 5."
7021 found_reverse_match
= 0;
7022 addr_prefix_disp
= -1;
7024 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7026 addr_prefix_disp
= -1;
7027 found_reverse_match
= 0;
7029 /* Must have right number of operands. */
7030 if (i
.operands
!= t
->operands
)
7033 /* Check processor support. */
7034 specific_error
= progress (unsupported
);
7035 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7038 /* Check AT&T mnemonic. */
7039 specific_error
= progress (unsupported_with_intel_mnemonic
);
7040 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7043 /* Check AT&T/Intel syntax. */
7044 specific_error
= progress (unsupported_syntax
);
7045 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7046 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7049 /* Check Intel64/AMD64 ISA. */
7053 /* Default: Don't accept Intel64. */
7054 if (t
->opcode_modifier
.isa64
== INTEL64
)
7058 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7059 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7063 /* -mintel64: Don't accept AMD64. */
7064 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7069 /* Check the suffix. */
7070 specific_error
= progress (invalid_instruction_suffix
);
7071 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7072 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7073 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7074 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7075 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7078 specific_error
= progress (operand_size_mismatch
);
7079 size_match
= operand_size_match (t
);
7083 /* This is intentionally not
7085 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7087 as the case of a missing * on the operand is accepted (perhaps with
7088 a warning, issued further down). */
7089 specific_error
= progress (operand_type_mismatch
);
7090 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7093 /* In Intel syntax, normally we can check for memory operand size when
7094 there is no mnemonic suffix. But jmp and call have 2 different
7095 encodings with Dword memory operand size. Skip the "near" one
7096 (permitting a register operand) when "far" was requested. */
7098 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7099 && t
->operand_types
[0].bitfield
.class == Reg
)
7102 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7103 operand_types
[j
] = t
->operand_types
[j
];
7105 /* In general, don't allow 32-bit operands on pre-386. */
7106 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7107 : operand_size_mismatch
);
7108 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7109 if (i
.suffix
== LONG_MNEM_SUFFIX
7110 && !cpu_arch_flags
.bitfield
.cpui386
7112 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7113 && !intel_float_operand (insn_name (t
)))
7114 : intel_float_operand (insn_name (t
)) != 2)
7115 && (t
->operands
== i
.imm_operands
7116 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7117 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7118 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7119 || (operand_types
[j
].bitfield
.class != RegMMX
7120 && operand_types
[j
].bitfield
.class != RegSIMD
7121 && operand_types
[j
].bitfield
.class != RegMask
))
7122 && !t
->opcode_modifier
.sib
)
7125 /* Do not verify operands when there are none. */
7128 if (VEX_check_encoding (t
))
7130 specific_error
= progress (i
.error
);
7134 /* We've found a match; break out of loop. */
7138 if (!t
->opcode_modifier
.jump
7139 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7141 /* There should be only one Disp operand. */
7142 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7143 if (operand_type_check (operand_types
[j
], disp
))
7145 if (j
< MAX_OPERANDS
)
7147 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7149 addr_prefix_disp
= j
;
7151 /* Address size prefix will turn Disp64 operand into Disp32 and
7152 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7156 override
= !override
;
7159 if (operand_types
[j
].bitfield
.disp32
7160 && operand_types
[j
].bitfield
.disp16
)
7162 operand_types
[j
].bitfield
.disp16
= override
;
7163 operand_types
[j
].bitfield
.disp32
= !override
;
7165 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7169 if (operand_types
[j
].bitfield
.disp64
)
7171 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7172 operand_types
[j
].bitfield
.disp32
= override
;
7173 operand_types
[j
].bitfield
.disp64
= !override
;
7175 operand_types
[j
].bitfield
.disp16
= 0;
7181 /* We check register size if needed. */
7182 if (t
->opcode_modifier
.checkoperandsize
)
7184 check_register
= (1 << t
->operands
) - 1;
7185 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7186 check_register
&= ~(1 << i
.broadcast
.operand
);
7191 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7192 switch (t
->operands
)
7195 if (!operand_type_match (overlap0
, i
.types
[0]))
7198 /* Allow the ModR/M encoding to be requested by using the {load} or
7199 {store} pseudo prefix on an applicable insn. */
7200 if (!t
->opcode_modifier
.modrm
7201 && i
.reg_operands
== 1
7202 && ((i
.dir_encoding
== dir_encoding_load
7203 && t
->mnem_off
!= MN_pop
)
7204 || (i
.dir_encoding
== dir_encoding_store
7205 && t
->mnem_off
!= MN_push
))
7207 && t
->mnem_off
!= MN_bswap
)
7212 /* xchg %eax, %eax is a special case. It is an alias for nop
7213 only in 32bit mode and we can use opcode 0x90. In 64bit
7214 mode, we can't use 0x90 for xchg %eax, %eax since it should
7215 zero-extend %eax to %rax. */
7216 if (t
->base_opcode
== 0x90
7217 && t
->opcode_space
== SPACE_BASE
)
7219 if (flag_code
== CODE_64BIT
7220 && i
.types
[0].bitfield
.instance
== Accum
7221 && i
.types
[0].bitfield
.dword
7222 && i
.types
[1].bitfield
.instance
== Accum
)
7225 /* Allow the ModR/M encoding to be requested by using the
7226 {load} or {store} pseudo prefix. */
7227 if (i
.dir_encoding
== dir_encoding_load
7228 || i
.dir_encoding
== dir_encoding_store
)
7232 if (t
->base_opcode
== MOV_AX_DISP32
7233 && t
->opcode_space
== SPACE_BASE
7234 && t
->mnem_off
!= MN_movabs
)
7236 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7237 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7240 /* xrelease mov %eax, <disp> is another special case. It must not
7241 match the accumulator-only encoding of mov. */
7245 /* Allow the ModR/M encoding to be requested by using a suitable
7246 {load} or {store} pseudo prefix. */
7247 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7248 ? dir_encoding_store
7249 : dir_encoding_load
)
7250 && !i
.types
[0].bitfield
.disp64
7251 && !i
.types
[1].bitfield
.disp64
)
7255 /* Allow the ModR/M encoding to be requested by using the {load} or
7256 {store} pseudo prefix on an applicable insn. */
7257 if (!t
->opcode_modifier
.modrm
7258 && i
.reg_operands
== 1
7259 && i
.imm_operands
== 1
7260 && (i
.dir_encoding
== dir_encoding_load
7261 || i
.dir_encoding
== dir_encoding_store
)
7262 && t
->opcode_space
== SPACE_BASE
)
7264 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7265 && i
.dir_encoding
== dir_encoding_store
)
7268 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7269 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7270 || i
.dir_encoding
== dir_encoding_load
))
7273 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7274 && i
.dir_encoding
== dir_encoding_load
)
7280 if (!(size_match
& MATCH_STRAIGHT
))
7282 /* Reverse direction of operands if swapping is possible in the first
7283 place (operands need to be symmetric) and
7284 - the load form is requested, and the template is a store form,
7285 - the store form is requested, and the template is a load form,
7286 - the non-default (swapped) form is requested. */
7287 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7288 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7289 && !operand_type_all_zero (&overlap1
))
7290 switch (i
.dir_encoding
)
7292 case dir_encoding_load
:
7293 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7294 || t
->opcode_modifier
.regmem
)
7298 case dir_encoding_store
:
7299 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7300 && !t
->opcode_modifier
.regmem
)
7304 case dir_encoding_swap
:
7307 case dir_encoding_default
:
7310 /* If we want store form, we skip the current load. */
7311 if ((i
.dir_encoding
== dir_encoding_store
7312 || i
.dir_encoding
== dir_encoding_swap
)
7313 && i
.mem_operands
== 0
7314 && t
->opcode_modifier
.load
)
7319 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7320 if (!operand_type_match (overlap0
, i
.types
[0])
7321 || !operand_type_match (overlap1
, i
.types
[1])
7322 || ((check_register
& 3) == 3
7323 && !operand_type_register_match (i
.types
[0],
7328 specific_error
= progress (i
.error
);
7330 /* Check if other direction is valid ... */
7331 if (!t
->opcode_modifier
.d
)
7335 if (!(size_match
& MATCH_REVERSE
))
7337 /* Try reversing direction of operands. */
7338 j
= is_cpu (t
, CpuFMA4
)
7339 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7340 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7341 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7342 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7343 gas_assert (t
->operands
!= 3 || !check_register
);
7344 if (!operand_type_match (overlap0
, i
.types
[0])
7345 || !operand_type_match (overlap1
, i
.types
[j
])
7346 || (t
->operands
== 3
7347 && !operand_type_match (overlap2
, i
.types
[1]))
7349 && !operand_type_register_match (i
.types
[0],
7354 /* Does not match either direction. */
7355 specific_error
= progress (i
.error
);
7358 /* found_reverse_match holds which variant of D
7360 if (!t
->opcode_modifier
.d
)
7361 found_reverse_match
= 0;
7362 else if (operand_types
[0].bitfield
.tbyte
)
7364 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7365 found_reverse_match
= Opcode_FloatD
;
7367 found_reverse_match
= ~0;
7368 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7369 if ((t
->extension_opcode
& 4)
7370 && (intel_syntax
|| intel_mnemonic
))
7371 found_reverse_match
|= Opcode_FloatR
;
7373 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7375 found_reverse_match
= Opcode_VexW
;
7376 goto check_operands_345
;
7378 else if (t
->opcode_space
!= SPACE_BASE
7379 && (t
->opcode_space
!= SPACE_0F
7380 /* MOV to/from CR/DR/TR, as an exception, follow
7381 the base opcode space encoding model. */
7382 || (t
->base_opcode
| 7) != 0x27))
7383 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7384 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7385 else if (!t
->opcode_modifier
.commutative
)
7386 found_reverse_match
= Opcode_D
;
7388 found_reverse_match
= ~0;
7392 /* Found a forward 2 operand match here. */
7394 switch (t
->operands
)
7397 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7398 if (!operand_type_match (overlap4
, i
.types
[4])
7399 || !operand_type_register_match (i
.types
[3],
7404 specific_error
= progress (i
.error
);
7409 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7410 if (!operand_type_match (overlap3
, i
.types
[3])
7411 || ((check_register
& 0xa) == 0xa
7412 && !operand_type_register_match (i
.types
[1],
7416 || ((check_register
& 0xc) == 0xc
7417 && !operand_type_register_match (i
.types
[2],
7422 specific_error
= progress (i
.error
);
7427 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7428 if (!operand_type_match (overlap2
, i
.types
[2])
7429 || ((check_register
& 5) == 5
7430 && !operand_type_register_match (i
.types
[0],
7434 || ((check_register
& 6) == 6
7435 && !operand_type_register_match (i
.types
[1],
7440 specific_error
= progress (i
.error
);
7446 /* Found either forward/reverse 2, 3 or 4 operand match here:
7447 slip through to break. */
7450 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7451 if (VEX_check_encoding (t
))
7453 specific_error
= progress (i
.error
);
7457 /* Check if vector operands are valid. */
7458 if (check_VecOperands (t
))
7460 specific_error
= progress (i
.error
);
7464 /* Check whether to use the shorter VEX encoding for certain insns where
7465 the EVEX enconding comes first in the table. This requires the respective
7466 AVX-* feature to be explicitly enabled. */
7467 if (t
== current_templates
->start
7468 && t
->opcode_modifier
.disp8memshift
7469 && !t
->opcode_modifier
.vex
7470 && !need_evex_encoding ()
7471 && t
+ 1 < current_templates
->end
7472 && t
[1].opcode_modifier
.vex
)
7475 unsigned int memshift
= i
.memshift
;
7478 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7479 if (!cpu_flags_all_zero (&cpu
)
7480 && (!i
.types
[0].bitfield
.disp8
7481 || !operand_type_check (i
.types
[0], disp
)
7482 || i
.op
[0].disps
->X_op
!= O_constant
7483 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7485 specific_error
= progress (internal_error
);
7488 i
.memshift
= memshift
;
7491 /* We've found a match; break out of loop. */
7497 if (t
== current_templates
->end
)
7499 /* We found no match. */
7500 i
.error
= specific_error
;
7504 if (!quiet_warnings
)
7507 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7508 as_warn (_("indirect %s without `*'"), insn_name (t
));
7510 if (t
->opcode_modifier
.isprefix
7511 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7513 /* Warn them that a data or address size prefix doesn't
7514 affect assembly of the next line of code. */
7515 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7519 /* Copy the template we found. */
7520 install_template (t
);
7522 if (addr_prefix_disp
!= -1)
7523 i
.tm
.operand_types
[addr_prefix_disp
]
7524 = operand_types
[addr_prefix_disp
];
7526 switch (found_reverse_match
)
7532 case Opcode_FloatR
| Opcode_FloatD
:
7533 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7534 found_reverse_match
&= Opcode_FloatD
;
7538 /* If we found a reverse match we must alter the opcode direction
7539 bit and clear/flip the regmem modifier one. found_reverse_match
7540 holds bits to change (different for int & float insns). */
7542 i
.tm
.base_opcode
^= found_reverse_match
;
7544 /* Certain SIMD insns have their load forms specified in the opcode
7545 table, and hence we need to _set_ RegMem instead of clearing it.
7546 We need to avoid setting the bit though on insns like KMOVW. */
7547 i
.tm
.opcode_modifier
.regmem
7548 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7549 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7550 && !i
.tm
.opcode_modifier
.regmem
;
7554 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7555 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7559 /* Only the first two register operands need reversing, alongside
7561 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7563 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7564 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7565 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7575 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7576 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7578 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7580 as_bad (_("`%s' operand %u must use `%ses' segment"),
7582 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7587 /* There's only ever one segment override allowed per instruction.
7588 This instruction possibly has a legal segment override on the
7589 second operand, so copy the segment to where non-string
7590 instructions store it, allowing common code. */
7591 i
.seg
[op
] = i
.seg
[1];
7597 process_suffix (void)
7599 bool is_movx
= false;
7601 /* If matched instruction specifies an explicit instruction mnemonic
7603 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7604 i
.suffix
= WORD_MNEM_SUFFIX
;
7605 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7606 i
.suffix
= LONG_MNEM_SUFFIX
;
7607 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7608 i
.suffix
= QWORD_MNEM_SUFFIX
;
7609 else if (i
.reg_operands
7610 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7611 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7613 unsigned int numop
= i
.operands
;
7616 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7617 && (i
.tm
.base_opcode
| 8) == 0xbe)
7618 || (i
.tm
.opcode_space
== SPACE_BASE
7619 && i
.tm
.base_opcode
== 0x63
7620 && is_cpu (&i
.tm
, Cpu64
));
7622 /* movsx/movzx want only their source operand considered here, for the
7623 ambiguity checking below. The suffix will be replaced afterwards
7624 to represent the destination (register). */
7625 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7628 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7629 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7632 /* If there's no instruction mnemonic suffix we try to invent one
7633 based on GPR operands. */
7636 /* We take i.suffix from the last register operand specified,
7637 Destination register type is more significant than source
7638 register type. crc32 in SSE4.2 prefers source register
7640 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7643 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7644 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7646 if (i
.types
[op
].bitfield
.class != Reg
)
7648 if (i
.types
[op
].bitfield
.byte
)
7649 i
.suffix
= BYTE_MNEM_SUFFIX
;
7650 else if (i
.types
[op
].bitfield
.word
)
7651 i
.suffix
= WORD_MNEM_SUFFIX
;
7652 else if (i
.types
[op
].bitfield
.dword
)
7653 i
.suffix
= LONG_MNEM_SUFFIX
;
7654 else if (i
.types
[op
].bitfield
.qword
)
7655 i
.suffix
= QWORD_MNEM_SUFFIX
;
7661 /* As an exception, movsx/movzx silently default to a byte source
7663 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7664 i
.suffix
= BYTE_MNEM_SUFFIX
;
7666 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7668 if (!check_byte_reg ())
7671 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7673 if (!check_long_reg ())
7676 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7678 if (!check_qword_reg ())
7681 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7683 if (!check_word_reg ())
7686 else if (intel_syntax
7687 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7688 /* Do nothing if the instruction is going to ignore the prefix. */
7693 /* Undo the movsx/movzx change done above. */
7696 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7699 i
.suffix
= stackop_size
;
7700 if (stackop_size
== LONG_MNEM_SUFFIX
)
7702 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7703 .code16gcc directive to support 16-bit mode with
7704 32-bit address. For IRET without a suffix, generate
7705 16-bit IRET (opcode 0xcf) to return from an interrupt
7707 if (i
.tm
.base_opcode
== 0xcf)
7709 i
.suffix
= WORD_MNEM_SUFFIX
;
7710 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7712 /* Warn about changed behavior for segment register push/pop. */
7713 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7714 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7719 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7720 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7721 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7722 || (i
.tm
.opcode_space
== SPACE_0F
7723 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7724 && i
.tm
.extension_opcode
<= 3)))
7729 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7731 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7732 || i
.tm
.opcode_modifier
.no_lsuf
)
7733 i
.suffix
= QWORD_MNEM_SUFFIX
;
7738 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7739 i
.suffix
= LONG_MNEM_SUFFIX
;
7742 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7743 i
.suffix
= WORD_MNEM_SUFFIX
;
7749 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7750 /* Also cover lret/retf/iret in 64-bit mode. */
7751 || (flag_code
== CODE_64BIT
7752 && !i
.tm
.opcode_modifier
.no_lsuf
7753 && !i
.tm
.opcode_modifier
.no_qsuf
))
7754 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7755 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7756 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7757 /* Accept FLDENV et al without suffix. */
7758 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7760 unsigned int suffixes
, evex
= 0;
7762 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7763 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7765 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7767 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7769 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7772 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7773 also suitable for AT&T syntax mode, it was requested that this be
7774 restricted to just Intel syntax. */
7775 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7776 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7780 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7782 if (vector_size
< VSZ512
)
7784 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7785 if (vector_size
< VSZ256
)
7787 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7788 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7789 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7790 || (!i
.tm
.opcode_modifier
.evex
7791 && is_evex_encoding (&i
.tm
))))
7792 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7794 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7795 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7796 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7797 || (!i
.tm
.opcode_modifier
.evex
7798 && is_evex_encoding (&i
.tm
))))
7799 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7801 else if (is_evex_encoding (&i
.tm
)
7802 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7804 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7805 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7806 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7807 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7808 if (!i
.tm
.opcode_modifier
.evex
7809 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7810 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7813 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7814 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7815 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7818 /* Any properly sized operand disambiguates the insn. */
7819 if (i
.types
[op
].bitfield
.xmmword
7820 || i
.types
[op
].bitfield
.ymmword
7821 || i
.types
[op
].bitfield
.zmmword
)
7823 suffixes
&= ~(7 << 6);
7828 if ((i
.flags
[op
] & Operand_Mem
)
7829 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7831 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7833 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7835 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7837 if (is_evex_encoding (&i
.tm
))
7843 /* Are multiple suffixes / operand sizes allowed? */
7844 if (suffixes
& (suffixes
- 1))
7847 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7848 || operand_check
== check_error
))
7850 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7853 if (operand_check
== check_error
)
7855 as_bad (_("no instruction mnemonic suffix given and "
7856 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7859 if (operand_check
== check_warning
)
7860 as_warn (_("%s; using default for `%s'"),
7862 ? _("ambiguous operand size")
7863 : _("no instruction mnemonic suffix given and "
7864 "no register operands"),
7867 if (i
.tm
.opcode_modifier
.floatmf
)
7868 i
.suffix
= SHORT_MNEM_SUFFIX
;
7870 /* handled below */;
7872 i
.tm
.opcode_modifier
.evex
= evex
;
7873 else if (flag_code
== CODE_16BIT
)
7874 i
.suffix
= WORD_MNEM_SUFFIX
;
7875 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7876 i
.suffix
= LONG_MNEM_SUFFIX
;
7878 i
.suffix
= QWORD_MNEM_SUFFIX
;
7884 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7885 In AT&T syntax, if there is no suffix (warned about above), the default
7886 will be byte extension. */
7887 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7888 i
.tm
.base_opcode
|= 1;
7890 /* For further processing, the suffix should represent the destination
7891 (register). This is already the case when one was used with
7892 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7893 no suffix to begin with. */
7894 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7896 if (i
.types
[1].bitfield
.word
)
7897 i
.suffix
= WORD_MNEM_SUFFIX
;
7898 else if (i
.types
[1].bitfield
.qword
)
7899 i
.suffix
= QWORD_MNEM_SUFFIX
;
7901 i
.suffix
= LONG_MNEM_SUFFIX
;
7903 i
.tm
.opcode_modifier
.w
= 0;
7907 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7908 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7909 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7911 /* Change the opcode based on the operand size given by i.suffix. */
7914 /* Size floating point instruction. */
7915 case LONG_MNEM_SUFFIX
:
7916 if (i
.tm
.opcode_modifier
.floatmf
)
7918 i
.tm
.base_opcode
^= 4;
7922 case WORD_MNEM_SUFFIX
:
7923 case QWORD_MNEM_SUFFIX
:
7924 /* It's not a byte, select word/dword operation. */
7925 if (i
.tm
.opcode_modifier
.w
)
7928 i
.tm
.base_opcode
|= 8;
7930 i
.tm
.base_opcode
|= 1;
7933 case SHORT_MNEM_SUFFIX
:
7934 /* Now select between word & dword operations via the operand
7935 size prefix, except for instructions that will ignore this
7937 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7938 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7939 && !i
.tm
.opcode_modifier
.floatmf
7940 && !is_any_vex_encoding (&i
.tm
)
7941 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7942 || (flag_code
== CODE_64BIT
7943 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7945 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7947 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7948 prefix
= ADDR_PREFIX_OPCODE
;
7950 if (!add_prefix (prefix
))
7954 /* Set mode64 for an operand. */
7955 if (i
.suffix
== QWORD_MNEM_SUFFIX
7956 && flag_code
== CODE_64BIT
7957 && !i
.tm
.opcode_modifier
.norex64
7958 && !i
.tm
.opcode_modifier
.vexw
7959 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7961 && ! (i
.operands
== 2
7962 && i
.tm
.base_opcode
== 0x90
7963 && i
.tm
.opcode_space
== SPACE_BASE
7964 && i
.types
[0].bitfield
.instance
== Accum
7965 && i
.types
[0].bitfield
.qword
7966 && i
.types
[1].bitfield
.instance
== Accum
))
7972 /* Select word/dword/qword operation with explicit data sizing prefix
7973 when there are no suitable register operands. */
7974 if (i
.tm
.opcode_modifier
.w
7975 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7977 || (i
.reg_operands
== 1
7979 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7981 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7982 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7983 || i
.tm
.mnem_off
== MN_crc32
))))
7984 i
.tm
.base_opcode
|= 1;
7988 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7990 gas_assert (!i
.suffix
);
7991 gas_assert (i
.reg_operands
);
7993 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7996 /* The address size override prefix changes the size of the
7998 if (flag_code
== CODE_64BIT
7999 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
8001 as_bad (_("16-bit addressing unavailable for `%s'"),
8006 if ((flag_code
== CODE_32BIT
8007 ? i
.op
[0].regs
->reg_type
.bitfield
.word
8008 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
8009 && !add_prefix (ADDR_PREFIX_OPCODE
))
8014 /* Check invalid register operand when the address size override
8015 prefix changes the size of register operands. */
8017 enum { need_word
, need_dword
, need_qword
} need
;
8019 /* Check the register operand for the address size prefix if
8020 the memory operand has no real registers, like symbol, DISP
8021 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8022 if (i
.mem_operands
== 1
8023 && i
.reg_operands
== 1
8025 && i
.types
[1].bitfield
.class == Reg
8026 && (flag_code
== CODE_32BIT
8027 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8028 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8029 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8030 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8031 || (x86_elf_abi
== X86_64_X32_ABI
8033 && i
.base_reg
->reg_num
== RegIP
8034 && i
.base_reg
->reg_type
.bitfield
.qword
))
8038 && !add_prefix (ADDR_PREFIX_OPCODE
))
8041 if (flag_code
== CODE_32BIT
)
8042 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8043 else if (i
.prefix
[ADDR_PREFIX
])
8046 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8048 for (op
= 0; op
< i
.operands
; op
++)
8050 if (i
.types
[op
].bitfield
.class != Reg
)
8056 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8060 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8064 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8069 as_bad (_("invalid register operand size for `%s'"),
8080 check_byte_reg (void)
8084 for (op
= i
.operands
; --op
>= 0;)
8086 /* Skip non-register operands. */
8087 if (i
.types
[op
].bitfield
.class != Reg
)
8090 /* If this is an eight bit register, it's OK. If it's the 16 or
8091 32 bit version of an eight bit register, we will just use the
8092 low portion, and that's OK too. */
8093 if (i
.types
[op
].bitfield
.byte
)
8096 /* I/O port address operands are OK too. */
8097 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8098 && i
.tm
.operand_types
[op
].bitfield
.word
)
8101 /* crc32 only wants its source operand checked here. */
8102 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8105 /* Any other register is bad. */
8106 as_bad (_("`%s%s' not allowed with `%s%c'"),
8107 register_prefix
, i
.op
[op
].regs
->reg_name
,
8108 insn_name (&i
.tm
), i
.suffix
);
8115 check_long_reg (void)
8119 for (op
= i
.operands
; --op
>= 0;)
8120 /* Skip non-register operands. */
8121 if (i
.types
[op
].bitfield
.class != Reg
)
8123 /* Reject eight bit registers, except where the template requires
8124 them. (eg. movzb) */
8125 else if (i
.types
[op
].bitfield
.byte
8126 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8127 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8128 && (i
.tm
.operand_types
[op
].bitfield
.word
8129 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8131 as_bad (_("`%s%s' not allowed with `%s%c'"),
8133 i
.op
[op
].regs
->reg_name
,
8138 /* Error if the e prefix on a general reg is missing. */
8139 else if (i
.types
[op
].bitfield
.word
8140 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8141 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8142 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8144 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8145 register_prefix
, i
.op
[op
].regs
->reg_name
,
8149 /* Warn if the r prefix on a general reg is present. */
8150 else if (i
.types
[op
].bitfield
.qword
8151 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8152 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8153 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8155 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8156 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8163 check_qword_reg (void)
8167 for (op
= i
.operands
; --op
>= 0; )
8168 /* Skip non-register operands. */
8169 if (i
.types
[op
].bitfield
.class != Reg
)
8171 /* Reject eight bit registers, except where the template requires
8172 them. (eg. movzb) */
8173 else if (i
.types
[op
].bitfield
.byte
8174 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8175 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8176 && (i
.tm
.operand_types
[op
].bitfield
.word
8177 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8179 as_bad (_("`%s%s' not allowed with `%s%c'"),
8181 i
.op
[op
].regs
->reg_name
,
8186 /* Warn if the r prefix on a general reg is missing. */
8187 else if ((i
.types
[op
].bitfield
.word
8188 || i
.types
[op
].bitfield
.dword
)
8189 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8190 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8191 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8193 /* Prohibit these changes in the 64bit mode, since the
8194 lowering is more complicated. */
8195 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8196 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8203 check_word_reg (void)
8206 for (op
= i
.operands
; --op
>= 0;)
8207 /* Skip non-register operands. */
8208 if (i
.types
[op
].bitfield
.class != Reg
)
8210 /* Reject eight bit registers, except where the template requires
8211 them. (eg. movzb) */
8212 else if (i
.types
[op
].bitfield
.byte
8213 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8214 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8215 && (i
.tm
.operand_types
[op
].bitfield
.word
8216 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8218 as_bad (_("`%s%s' not allowed with `%s%c'"),
8220 i
.op
[op
].regs
->reg_name
,
8225 /* Error if the e or r prefix on a general reg is present. */
8226 else if ((i
.types
[op
].bitfield
.dword
8227 || i
.types
[op
].bitfield
.qword
)
8228 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8229 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8230 && i
.tm
.operand_types
[op
].bitfield
.word
)
8232 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8233 register_prefix
, i
.op
[op
].regs
->reg_name
,
8241 update_imm (unsigned int j
)
8243 i386_operand_type overlap
= i
.types
[j
];
8245 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8246 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8247 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8249 /* This combination is used on 8-bit immediates where e.g. $~0 is
8250 desirable to permit. We're past operand type matching, so simply
8251 put things back in the shape they were before introducing the
8252 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8253 overlap
.bitfield
.imm8s
= 0;
8256 if (overlap
.bitfield
.imm8
8257 + overlap
.bitfield
.imm8s
8258 + overlap
.bitfield
.imm16
8259 + overlap
.bitfield
.imm32
8260 + overlap
.bitfield
.imm32s
8261 + overlap
.bitfield
.imm64
> 1)
8263 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8264 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8265 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8266 static const i386_operand_type imm16_32
= { .bitfield
=
8267 { .imm16
= 1, .imm32
= 1 }
8269 static const i386_operand_type imm16_32s
= { .bitfield
=
8270 { .imm16
= 1, .imm32s
= 1 }
8272 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8273 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8278 i386_operand_type temp
;
8280 operand_type_set (&temp
, 0);
8281 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8283 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8284 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8286 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8287 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8288 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8290 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8291 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8294 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8297 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8298 || operand_type_equal (&overlap
, &imm16_32
)
8299 || operand_type_equal (&overlap
, &imm16_32s
))
8301 if ((flag_code
== CODE_16BIT
)
8302 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8307 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8308 overlap
= operand_type_and (overlap
, imm32s
);
8309 else if (i
.prefix
[DATA_PREFIX
])
8310 overlap
= operand_type_and (overlap
,
8311 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8312 if (overlap
.bitfield
.imm8
8313 + overlap
.bitfield
.imm8s
8314 + overlap
.bitfield
.imm16
8315 + overlap
.bitfield
.imm32
8316 + overlap
.bitfield
.imm32s
8317 + overlap
.bitfield
.imm64
!= 1)
8319 as_bad (_("no instruction mnemonic suffix given; "
8320 "can't determine immediate size"));
8324 i
.types
[j
] = overlap
;
8334 /* Update the first 2 immediate operands. */
8335 n
= i
.operands
> 2 ? 2 : i
.operands
;
8338 for (j
= 0; j
< n
; j
++)
8339 if (update_imm (j
) == 0)
8342 /* The 3rd operand can't be immediate operand. */
8343 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8349 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8352 if (r
->reg_flags
& RegRex
)
8354 if (i
.rex
& rex_bit
)
8355 as_bad (_("same type of prefix used twice"));
8358 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8360 gas_assert (i
.vex
.register_specifier
== r
);
8361 i
.vex
.register_specifier
+= 8;
8364 if (r
->reg_flags
& RegVRex
)
8369 process_operands (void)
8371 /* Default segment register this instruction will use for memory
8372 accesses. 0 means unknown. This is only for optimizing out
8373 unnecessary segment overrides. */
8374 const reg_entry
*default_seg
= NULL
;
8376 /* We only need to check those implicit registers for instructions
8377 with 3 operands or less. */
8378 if (i
.operands
<= 3)
8379 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8380 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8383 if (i
.tm
.opcode_modifier
.sse2avx
)
8385 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8387 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8388 i
.prefix
[REX_PREFIX
] = 0;
8391 /* ImmExt should be processed after SSE2AVX. */
8392 else if (i
.tm
.opcode_modifier
.immext
)
8395 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8396 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8397 new destination operand here, while converting the source one to register
8399 if (i
.tm
.mnem_off
== MN_tilezero
)
8401 i
.op
[1].regs
= i
.op
[0].regs
;
8402 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8403 i
.types
[1] = i
.types
[0];
8404 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8405 i
.flags
[1] = i
.flags
[0];
8411 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8413 static const i386_operand_type regxmm
= {
8414 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8416 unsigned int dupl
= i
.operands
;
8417 unsigned int dest
= dupl
- 1;
8420 /* The destination must be an xmm register. */
8421 gas_assert (i
.reg_operands
8422 && MAX_OPERANDS
> dupl
8423 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8425 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8426 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8428 /* Keep xmm0 for instructions with VEX prefix and 3
8430 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8431 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8436 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8438 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8440 /* Add the implicit xmm0 for instructions with VEX prefix
8442 for (j
= i
.operands
; j
> 0; j
--)
8444 i
.op
[j
] = i
.op
[j
- 1];
8445 i
.types
[j
] = i
.types
[j
- 1];
8446 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8447 i
.flags
[j
] = i
.flags
[j
- 1];
8450 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8451 i
.types
[0] = regxmm
;
8452 i
.tm
.operand_types
[0] = regxmm
;
8455 i
.reg_operands
+= 2;
8460 i
.op
[dupl
] = i
.op
[dest
];
8461 i
.types
[dupl
] = i
.types
[dest
];
8462 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8463 i
.flags
[dupl
] = i
.flags
[dest
];
8472 i
.op
[dupl
] = i
.op
[dest
];
8473 i
.types
[dupl
] = i
.types
[dest
];
8474 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8475 i
.flags
[dupl
] = i
.flags
[dest
];
8478 if (i
.tm
.opcode_modifier
.immext
)
8481 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8482 && i
.tm
.opcode_modifier
.modrm
)
8486 for (j
= 1; j
< i
.operands
; j
++)
8488 i
.op
[j
- 1] = i
.op
[j
];
8489 i
.types
[j
- 1] = i
.types
[j
];
8491 /* We need to adjust fields in i.tm since they are used by
8492 build_modrm_byte. */
8493 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8495 i
.flags
[j
- 1] = i
.flags
[j
];
8498 /* No adjustment to i.reg_operands: This was already done at the top
8503 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8505 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8507 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8508 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8509 regnum
= register_number (i
.op
[1].regs
);
8510 first_reg_in_group
= regnum
& ~3;
8511 last_reg_in_group
= first_reg_in_group
+ 3;
8512 if (regnum
!= first_reg_in_group
)
8513 as_warn (_("source register `%s%s' implicitly denotes"
8514 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8515 register_prefix
, i
.op
[1].regs
->reg_name
,
8516 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8517 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8520 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8522 /* The imul $imm, %reg instruction is converted into
8523 imul $imm, %reg, %reg, and the clr %reg instruction
8524 is converted into xor %reg, %reg. */
8526 unsigned int first_reg_op
;
8528 if (operand_type_check (i
.types
[0], reg
))
8532 /* Pretend we saw the extra register operand. */
8533 gas_assert (i
.reg_operands
== 1
8534 && i
.op
[first_reg_op
+ 1].regs
== 0);
8535 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8536 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8541 if (i
.tm
.opcode_modifier
.modrm
)
8543 /* The opcode is completed (modulo i.tm.extension_opcode which
8544 must be put into the modrm byte). Now, we make the modrm and
8545 index base bytes based on all the info we've collected. */
8547 default_seg
= build_modrm_byte ();
8549 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8551 /* Warn about some common errors, but press on regardless. */
8552 if (i
.operands
== 2)
8554 /* Reversed arguments on faddp or fmulp. */
8555 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8556 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8557 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8559 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8561 /* Extraneous `l' suffix on fp insn. */
8562 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8563 register_prefix
, i
.op
[0].regs
->reg_name
);
8567 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8569 if (flag_code
!= CODE_64BIT
8570 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8571 && i
.op
[0].regs
->reg_num
== 1
8572 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8573 && i
.op
[0].regs
->reg_num
< 4)
8575 as_bad (_("you can't `%s %s%s'"),
8576 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8579 if (i
.op
[0].regs
->reg_num
> 3
8580 && i
.tm
.opcode_space
== SPACE_BASE
)
8582 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8583 i
.tm
.opcode_space
= SPACE_0F
;
8585 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8587 else if (i
.tm
.opcode_space
== SPACE_BASE
8588 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8590 default_seg
= reg_ds
;
8592 else if (i
.tm
.opcode_modifier
.isstring
)
8594 /* For the string instructions that allow a segment override
8595 on one of their operands, the default segment is ds. */
8596 default_seg
= reg_ds
;
8598 else if (i
.short_form
)
8600 /* The register operand is in the 1st or 2nd non-immediate operand. */
8601 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8604 && r
->reg_type
.bitfield
.instance
== Accum
8605 && i
.op
[i
.imm_operands
+ 1].regs
)
8606 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8607 /* Register goes in low 3 bits of opcode. */
8608 i
.tm
.base_opcode
|= r
->reg_num
;
8609 set_rex_vrex (r
, REX_B
, false);
8611 if (dot_insn () && i
.reg_operands
== 2)
8613 gas_assert (is_any_vex_encoding (&i
.tm
)
8614 || i
.vec_encoding
!= vex_encoding_default
);
8615 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8618 else if (i
.reg_operands
== 1
8619 && !i
.flags
[i
.operands
- 1]
8620 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8623 gas_assert (is_any_vex_encoding (&i
.tm
)
8624 || i
.vec_encoding
!= vex_encoding_default
);
8625 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8628 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8629 && i
.tm
.mnem_off
== MN_lea
)
8631 if (!quiet_warnings
)
8632 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8633 if (optimize
&& !i
.no_optimize
)
8636 i
.prefix
[SEG_PREFIX
] = 0;
8640 /* If a segment was explicitly specified, and the specified segment
8641 is neither the default nor the one already recorded from a prefix,
8642 use an opcode prefix to select it. If we never figured out what
8643 the default segment is, then default_seg will be zero at this
8644 point, and the specified segment prefix will always be used. */
8646 && i
.seg
[0] != default_seg
8647 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8649 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8655 static const reg_entry
*
8656 build_modrm_byte (void)
8658 const reg_entry
*default_seg
= NULL
;
8659 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8660 /* Compensate for kludge in md_assemble(). */
8661 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8662 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8663 unsigned int v
, op
, reg_slot
= ~0;
8665 /* Accumulator (in particular %st), shift count (%cl), and alike need
8666 to be skipped just like immediate operands do. */
8667 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8669 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8672 for (op
= source
; op
< i
.operands
; ++op
)
8673 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8676 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8680 /* There are 2 kinds of instructions:
8681 1. 5 operands: 4 register operands or 3 register operands
8682 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8683 VexW0 or VexW1. The destination must be either XMM, YMM or
8685 2. 4 operands: 4 register operands or 3 register operands
8686 plus 1 memory operand, with VexXDS.
8687 3. Other equivalent combinations when coming from s_insn(). */
8688 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8689 && i
.tm
.opcode_modifier
.vexw
);
8690 gas_assert (dot_insn ()
8691 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8693 /* Of the first two non-immediate operands the one with the template
8694 not allowing for a memory one is encoded in the immediate operand. */
8696 reg_slot
= source
+ 1;
8698 reg_slot
= source
++;
8702 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8703 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8706 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8708 if (i
.imm_operands
== 0)
8710 /* When there is no immediate operand, generate an 8bit
8711 immediate operand to encode the first operand. */
8712 exp
= &im_expressions
[i
.imm_operands
++];
8713 i
.op
[i
.operands
].imms
= exp
;
8714 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8717 exp
->X_op
= O_constant
;
8721 gas_assert (i
.imm_operands
== 1);
8722 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8723 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8725 /* Turn on Imm8 again so that output_imm will generate it. */
8726 i
.types
[0].bitfield
.imm8
= 1;
8730 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8731 << (3 + !(is_evex_encoding (&i
.tm
)
8732 || i
.vec_encoding
== vex_encoding_evex
));
8735 for (v
= source
+ 1; v
< dest
; ++v
)
8740 if (i
.tm
.extension_opcode
!= None
)
8746 gas_assert (source
< dest
);
8747 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8750 unsigned int tmp
= source
;
8756 if (v
< MAX_OPERANDS
)
8758 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8759 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8762 if (op
< i
.operands
)
8766 unsigned int fake_zero_displacement
= 0;
8768 gas_assert (i
.flags
[op
] & Operand_Mem
);
8770 if (i
.tm
.opcode_modifier
.sib
)
8772 /* The index register of VSIB shouldn't be RegIZ. */
8773 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8774 && i
.index_reg
->reg_num
== RegIZ
)
8777 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8780 i
.sib
.base
= NO_BASE_REGISTER
;
8781 i
.sib
.scale
= i
.log2_scale_factor
;
8782 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8783 i
.types
[op
].bitfield
.disp32
= 1;
8786 /* Since the mandatory SIB always has index register, so
8787 the code logic remains unchanged. The non-mandatory SIB
8788 without index register is allowed and will be handled
8792 if (i
.index_reg
->reg_num
== RegIZ
)
8793 i
.sib
.index
= NO_INDEX_REGISTER
;
8795 i
.sib
.index
= i
.index_reg
->reg_num
;
8796 set_rex_vrex (i
.index_reg
, REX_X
, false);
8800 default_seg
= reg_ds
;
8802 if (i
.base_reg
== 0)
8805 if (!i
.disp_operands
)
8806 fake_zero_displacement
= 1;
8807 if (i
.index_reg
== 0)
8809 /* Both check for VSIB and mandatory non-vector SIB. */
8810 gas_assert (!i
.tm
.opcode_modifier
.sib
8811 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8812 /* Operand is just <disp> */
8813 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8814 if (flag_code
== CODE_64BIT
)
8816 /* 64bit mode overwrites the 32bit absolute
8817 addressing by RIP relative addressing and
8818 absolute addressing is encoded by one of the
8819 redundant SIB forms. */
8820 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8821 i
.sib
.base
= NO_BASE_REGISTER
;
8822 i
.sib
.index
= NO_INDEX_REGISTER
;
8823 i
.types
[op
].bitfield
.disp32
= 1;
8825 else if ((flag_code
== CODE_16BIT
)
8826 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8828 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8829 i
.types
[op
].bitfield
.disp16
= 1;
8833 i
.rm
.regmem
= NO_BASE_REGISTER
;
8834 i
.types
[op
].bitfield
.disp32
= 1;
8837 else if (!i
.tm
.opcode_modifier
.sib
)
8839 /* !i.base_reg && i.index_reg */
8840 if (i
.index_reg
->reg_num
== RegIZ
)
8841 i
.sib
.index
= NO_INDEX_REGISTER
;
8843 i
.sib
.index
= i
.index_reg
->reg_num
;
8844 i
.sib
.base
= NO_BASE_REGISTER
;
8845 i
.sib
.scale
= i
.log2_scale_factor
;
8846 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8847 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8848 i
.types
[op
].bitfield
.disp32
= 1;
8849 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8853 /* RIP addressing for 64bit mode. */
8854 else if (i
.base_reg
->reg_num
== RegIP
)
8856 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8857 i
.rm
.regmem
= NO_BASE_REGISTER
;
8858 i
.types
[op
].bitfield
.disp8
= 0;
8859 i
.types
[op
].bitfield
.disp16
= 0;
8860 i
.types
[op
].bitfield
.disp32
= 1;
8861 i
.types
[op
].bitfield
.disp64
= 0;
8862 i
.flags
[op
] |= Operand_PCrel
;
8863 if (! i
.disp_operands
)
8864 fake_zero_displacement
= 1;
8866 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8868 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8869 switch (i
.base_reg
->reg_num
)
8872 if (i
.index_reg
== 0)
8874 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8875 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8878 default_seg
= reg_ss
;
8879 if (i
.index_reg
== 0)
8882 if (operand_type_check (i
.types
[op
], disp
) == 0)
8884 /* fake (%bp) into 0(%bp) */
8885 if (i
.disp_encoding
== disp_encoding_16bit
)
8886 i
.types
[op
].bitfield
.disp16
= 1;
8888 i
.types
[op
].bitfield
.disp8
= 1;
8889 fake_zero_displacement
= 1;
8892 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8893 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8895 default: /* (%si) -> 4 or (%di) -> 5 */
8896 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8898 if (!fake_zero_displacement
8902 fake_zero_displacement
= 1;
8903 if (i
.disp_encoding
== disp_encoding_8bit
)
8904 i
.types
[op
].bitfield
.disp8
= 1;
8906 i
.types
[op
].bitfield
.disp16
= 1;
8908 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8910 else /* i.base_reg and 32/64 bit mode */
8912 if (operand_type_check (i
.types
[op
], disp
))
8914 i
.types
[op
].bitfield
.disp16
= 0;
8915 i
.types
[op
].bitfield
.disp64
= 0;
8916 i
.types
[op
].bitfield
.disp32
= 1;
8919 if (!i
.tm
.opcode_modifier
.sib
)
8920 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8921 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8923 i
.sib
.base
= i
.base_reg
->reg_num
;
8924 /* x86-64 ignores REX prefix bit here to avoid decoder
8926 if (!(i
.base_reg
->reg_flags
& RegRex
)
8927 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8928 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8929 default_seg
= reg_ss
;
8930 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8932 fake_zero_displacement
= 1;
8933 if (i
.disp_encoding
== disp_encoding_32bit
)
8934 i
.types
[op
].bitfield
.disp32
= 1;
8936 i
.types
[op
].bitfield
.disp8
= 1;
8938 i
.sib
.scale
= i
.log2_scale_factor
;
8939 if (i
.index_reg
== 0)
8941 /* Only check for VSIB. */
8942 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8943 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8944 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8946 /* <disp>(%esp) becomes two byte modrm with no index
8947 register. We've already stored the code for esp
8948 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8949 Any base register besides %esp will not use the
8950 extra modrm byte. */
8951 i
.sib
.index
= NO_INDEX_REGISTER
;
8953 else if (!i
.tm
.opcode_modifier
.sib
)
8955 if (i
.index_reg
->reg_num
== RegIZ
)
8956 i
.sib
.index
= NO_INDEX_REGISTER
;
8958 i
.sib
.index
= i
.index_reg
->reg_num
;
8959 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8960 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8965 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8966 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8970 if (!fake_zero_displacement
8974 fake_zero_displacement
= 1;
8975 if (i
.disp_encoding
== disp_encoding_8bit
)
8976 i
.types
[op
].bitfield
.disp8
= 1;
8978 i
.types
[op
].bitfield
.disp32
= 1;
8980 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8984 if (fake_zero_displacement
)
8986 /* Fakes a zero displacement assuming that i.types[op]
8987 holds the correct displacement size. */
8990 gas_assert (i
.op
[op
].disps
== 0);
8991 exp
= &disp_expressions
[i
.disp_operands
++];
8992 i
.op
[op
].disps
= exp
;
8993 exp
->X_op
= O_constant
;
8994 exp
->X_add_number
= 0;
8995 exp
->X_add_symbol
= (symbolS
*) 0;
8996 exp
->X_op_symbol
= (symbolS
*) 0;
9002 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
9003 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
9014 if (!i
.tm
.opcode_modifier
.regmem
)
9016 gas_assert (source
< MAX_OPERANDS
);
9017 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9018 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9019 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9024 gas_assert (dest
< MAX_OPERANDS
);
9025 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9026 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9031 /* Fill in i.rm.reg field with extension opcode (if any) or the
9032 appropriate register. */
9033 if (i
.tm
.extension_opcode
!= None
)
9034 i
.rm
.reg
= i
.tm
.extension_opcode
;
9035 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9037 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9038 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9042 gas_assert (source
< MAX_OPERANDS
);
9043 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9044 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9047 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9049 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9051 add_prefix (LOCK_PREFIX_OPCODE
);
9058 frag_opcode_byte (unsigned char byte
)
9060 if (now_seg
!= absolute_section
)
9061 FRAG_APPEND_1_CHAR (byte
);
9063 ++abs_section_offset
;
9067 flip_code16 (unsigned int code16
)
9069 gas_assert (i
.tm
.operands
== 1);
9071 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9072 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9073 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9078 output_branch (void)
9084 relax_substateT subtype
;
9088 if (now_seg
== absolute_section
)
9090 as_bad (_("relaxable branches not supported in absolute section"));
9094 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9095 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9098 if (i
.prefix
[DATA_PREFIX
] != 0)
9102 code16
^= flip_code16(code16
);
9104 /* Pentium4 branch hints. */
9105 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9106 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9111 if (i
.prefix
[REX_PREFIX
] != 0)
9117 /* BND prefixed jump. */
9118 if (i
.prefix
[BND_PREFIX
] != 0)
9124 if (i
.prefixes
!= 0)
9125 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9127 /* It's always a symbol; End frag & setup for relax.
9128 Make sure there is enough room in this frag for the largest
9129 instruction we may generate in md_convert_frag. This is 2
9130 bytes for the opcode and room for the prefix and largest
9132 frag_grow (prefix
+ 2 + 4);
9133 /* Prefix and 1 opcode byte go in fr_fix. */
9134 p
= frag_more (prefix
+ 1);
9135 if (i
.prefix
[DATA_PREFIX
] != 0)
9136 *p
++ = DATA_PREFIX_OPCODE
;
9137 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9138 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9139 *p
++ = i
.prefix
[SEG_PREFIX
];
9140 if (i
.prefix
[BND_PREFIX
] != 0)
9141 *p
++ = BND_PREFIX_OPCODE
;
9142 if (i
.prefix
[REX_PREFIX
] != 0)
9143 *p
++ = i
.prefix
[REX_PREFIX
];
9144 *p
= i
.tm
.base_opcode
;
9146 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9147 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9148 else if (cpu_arch_flags
.bitfield
.cpui386
)
9149 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9151 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9154 sym
= i
.op
[0].disps
->X_add_symbol
;
9155 off
= i
.op
[0].disps
->X_add_number
;
9157 if (i
.op
[0].disps
->X_op
!= O_constant
9158 && i
.op
[0].disps
->X_op
!= O_symbol
)
9160 /* Handle complex expressions. */
9161 sym
= make_expr_symbol (i
.op
[0].disps
);
9165 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
9167 /* 1 possible extra opcode + 4 byte displacement go in var part.
9168 Pass reloc in fr_var. */
9169 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9173 /* Return TRUE iff PLT32 relocation should be used for branching to
9177 need_plt32_p (symbolS
*s
)
9179 /* PLT32 relocation is ELF only. */
9184 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9185 krtld support it. */
9189 /* Since there is no need to prepare for PLT branch on x86-64, we
9190 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9191 be used as a marker for 32-bit PC-relative branches. */
9198 /* Weak or undefined symbol need PLT32 relocation. */
9199 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9202 /* Non-global symbol doesn't need PLT32 relocation. */
9203 if (! S_IS_EXTERNAL (s
))
9206 /* Other global symbols need PLT32 relocation. NB: Symbol with
9207 non-default visibilities are treated as normal global symbol
9208 so that PLT32 relocation can be used as a marker for 32-bit
9209 PC-relative branches. It is useful for linker relaxation. */
9220 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9222 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9224 /* This is a loop or jecxz type instruction. */
9226 if (i
.prefix
[ADDR_PREFIX
] != 0)
9228 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9231 /* Pentium4 branch hints. */
9232 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9233 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9235 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9244 if (flag_code
== CODE_16BIT
)
9247 if (i
.prefix
[DATA_PREFIX
] != 0)
9249 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9251 code16
^= flip_code16(code16
);
9259 /* BND prefixed jump. */
9260 if (i
.prefix
[BND_PREFIX
] != 0)
9262 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9266 if (i
.prefix
[REX_PREFIX
] != 0)
9268 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9272 if (i
.prefixes
!= 0)
9273 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9275 if (now_seg
== absolute_section
)
9277 abs_section_offset
+= i
.opcode_length
+ size
;
9281 p
= frag_more (i
.opcode_length
+ size
);
9282 switch (i
.opcode_length
)
9285 *p
++ = i
.tm
.base_opcode
>> 8;
9288 *p
++ = i
.tm
.base_opcode
;
9294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9295 if (flag_code
== CODE_64BIT
&& size
== 4
9296 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9297 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9298 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9301 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9303 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9304 i
.op
[0].disps
, 1, jump_reloc
);
9306 /* All jumps handled here are signed, but don't unconditionally use a
9307 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9308 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9313 fixP
->fx_signed
= 1;
9317 if (i
.tm
.mnem_off
== MN_xbegin
)
9318 fixP
->fx_signed
= 1;
9322 if (flag_code
== CODE_64BIT
)
9323 fixP
->fx_signed
= 1;
9329 output_interseg_jump (void)
9337 if (flag_code
== CODE_16BIT
)
9341 if (i
.prefix
[DATA_PREFIX
] != 0)
9348 gas_assert (!i
.prefix
[REX_PREFIX
]);
9354 if (i
.prefixes
!= 0)
9355 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9357 if (now_seg
== absolute_section
)
9359 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9363 /* 1 opcode; 2 segment; offset */
9364 p
= frag_more (prefix
+ 1 + 2 + size
);
9366 if (i
.prefix
[DATA_PREFIX
] != 0)
9367 *p
++ = DATA_PREFIX_OPCODE
;
9369 if (i
.prefix
[REX_PREFIX
] != 0)
9370 *p
++ = i
.prefix
[REX_PREFIX
];
9372 *p
++ = i
.tm
.base_opcode
;
9373 if (i
.op
[1].imms
->X_op
== O_constant
)
9375 offsetT n
= i
.op
[1].imms
->X_add_number
;
9378 && !fits_in_unsigned_word (n
)
9379 && !fits_in_signed_word (n
))
9381 as_bad (_("16-bit jump out of range"));
9384 md_number_to_chars (p
, n
, size
);
9387 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9388 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9391 if (i
.op
[0].imms
->X_op
== O_constant
)
9392 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9394 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9395 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9403 asection
*seg
= now_seg
;
9404 subsegT subseg
= now_subseg
;
9406 unsigned int alignment
, align_size_1
;
9407 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9408 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9409 unsigned int padding
;
9411 if (!IS_ELF
|| !x86_used_note
)
9414 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9416 /* The .note.gnu.property section layout:
9418 Field Length Contents
9421 n_descsz 4 The note descriptor size
9422 n_type 4 NT_GNU_PROPERTY_TYPE_0
9424 n_desc n_descsz The program property array
9428 /* Create the .note.gnu.property section. */
9429 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9430 bfd_set_section_flags (sec
,
9437 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9448 bfd_set_section_alignment (sec
, alignment
);
9449 elf_section_type (sec
) = SHT_NOTE
;
9451 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9453 isa_1_descsz_raw
= 4 + 4 + 4;
9454 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9455 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9457 feature_2_descsz_raw
= isa_1_descsz
;
9458 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9460 feature_2_descsz_raw
+= 4 + 4 + 4;
9461 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9462 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9465 descsz
= feature_2_descsz
;
9466 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9467 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9469 /* Write n_namsz. */
9470 md_number_to_chars (p
, (valueT
) 4, 4);
9472 /* Write n_descsz. */
9473 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9476 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9479 memcpy (p
+ 4 * 3, "GNU", 4);
9481 /* Write 4-byte type. */
9482 md_number_to_chars (p
+ 4 * 4,
9483 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9485 /* Write 4-byte data size. */
9486 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9488 /* Write 4-byte data. */
9489 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9491 /* Zero out paddings. */
9492 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9494 memset (p
+ 4 * 7, 0, padding
);
9496 /* Write 4-byte type. */
9497 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9498 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9500 /* Write 4-byte data size. */
9501 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9503 /* Write 4-byte data. */
9504 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9505 (valueT
) x86_feature_2_used
, 4);
9507 /* Zero out paddings. */
9508 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9510 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9512 /* We probably can't restore the current segment, for there likely
9515 subseg_set (seg
, subseg
);
9519 x86_support_sframe_p (void)
9521 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9522 return (x86_elf_abi
== X86_64_ABI
);
9526 x86_sframe_ra_tracking_p (void)
9528 /* In AMD64, return address is always stored on the stack at a fixed offset
9529 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9530 Do not track explicitly via an SFrame Frame Row Entry. */
9535 x86_sframe_cfa_ra_offset (void)
9537 gas_assert (x86_elf_abi
== X86_64_ABI
);
9538 return (offsetT
) -8;
9542 x86_sframe_get_abi_arch (void)
9544 unsigned char sframe_abi_arch
= 0;
9546 if (x86_support_sframe_p ())
9548 gas_assert (!target_big_endian
);
9549 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9552 return sframe_abi_arch
;
9558 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9559 const char *frag_now_ptr
)
9561 unsigned int len
= 0;
9563 if (start_frag
!= frag_now
)
9565 const fragS
*fr
= start_frag
;
9570 } while (fr
&& fr
!= frag_now
);
9573 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9576 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9577 be macro-fused with conditional jumps.
9578 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9579 or is one of the following format:
9592 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9594 /* No RIP address. */
9595 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9598 /* No opcodes outside of base encoding space. */
9599 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9602 /* add, sub without add/sub m, imm. */
9603 if (i
.tm
.base_opcode
<= 5
9604 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9605 || ((i
.tm
.base_opcode
| 3) == 0x83
9606 && (i
.tm
.extension_opcode
== 0x5
9607 || i
.tm
.extension_opcode
== 0x0)))
9609 *mf_cmp_p
= mf_cmp_alu_cmp
;
9610 return !(i
.mem_operands
&& i
.imm_operands
);
9613 /* and without and m, imm. */
9614 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9615 || ((i
.tm
.base_opcode
| 3) == 0x83
9616 && i
.tm
.extension_opcode
== 0x4))
9618 *mf_cmp_p
= mf_cmp_test_and
;
9619 return !(i
.mem_operands
&& i
.imm_operands
);
9622 /* test without test m imm. */
9623 if ((i
.tm
.base_opcode
| 1) == 0x85
9624 || (i
.tm
.base_opcode
| 1) == 0xa9
9625 || ((i
.tm
.base_opcode
| 1) == 0xf7
9626 && i
.tm
.extension_opcode
== 0))
9628 *mf_cmp_p
= mf_cmp_test_and
;
9629 return !(i
.mem_operands
&& i
.imm_operands
);
9632 /* cmp without cmp m, imm. */
9633 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9634 || ((i
.tm
.base_opcode
| 3) == 0x83
9635 && (i
.tm
.extension_opcode
== 0x7)))
9637 *mf_cmp_p
= mf_cmp_alu_cmp
;
9638 return !(i
.mem_operands
&& i
.imm_operands
);
9641 /* inc, dec without inc/dec m. */
9642 if ((is_cpu (&i
.tm
, CpuNo64
)
9643 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9644 || ((i
.tm
.base_opcode
| 1) == 0xff
9645 && i
.tm
.extension_opcode
<= 0x1))
9647 *mf_cmp_p
= mf_cmp_incdec
;
9648 return !i
.mem_operands
;
9654 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9657 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9659 /* NB: Don't work with COND_JUMP86 without i386. */
9660 if (!align_branch_power
9661 || now_seg
== absolute_section
9662 || !cpu_arch_flags
.bitfield
.cpui386
9663 || !(align_branch
& align_branch_fused_bit
))
9666 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9668 if (last_insn
.kind
== last_insn_other
9669 || last_insn
.seg
!= now_seg
)
9672 as_warn_where (last_insn
.file
, last_insn
.line
,
9673 _("`%s` skips -malign-branch-boundary on `%s`"),
9674 last_insn
.name
, insn_name (&i
.tm
));
9680 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9683 add_branch_prefix_frag_p (void)
9685 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9686 to PadLock instructions since they include prefixes in opcode. */
9687 if (!align_branch_power
9688 || !align_branch_prefix_size
9689 || now_seg
== absolute_section
9690 || is_cpu (&i
.tm
, CpuPadLock
)
9691 || !cpu_arch_flags
.bitfield
.cpui386
)
9694 /* Don't add prefix if it is a prefix or there is no operand in case
9695 that segment prefix is special. */
9696 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9699 if (last_insn
.kind
== last_insn_other
9700 || last_insn
.seg
!= now_seg
)
9704 as_warn_where (last_insn
.file
, last_insn
.line
,
9705 _("`%s` skips -malign-branch-boundary on `%s`"),
9706 last_insn
.name
, insn_name (&i
.tm
));
9711 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9714 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9715 enum mf_jcc_kind
*mf_jcc_p
)
9719 /* NB: Don't work with COND_JUMP86 without i386. */
9720 if (!align_branch_power
9721 || now_seg
== absolute_section
9722 || !cpu_arch_flags
.bitfield
.cpui386
9723 || i
.tm
.opcode_space
!= SPACE_BASE
)
9728 /* Check for jcc and direct jmp. */
9729 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9731 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9733 *branch_p
= align_branch_jmp
;
9734 add_padding
= align_branch
& align_branch_jmp_bit
;
9738 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9739 igore the lowest bit. */
9740 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9741 *branch_p
= align_branch_jcc
;
9742 if ((align_branch
& align_branch_jcc_bit
))
9746 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9749 *branch_p
= align_branch_ret
;
9750 if ((align_branch
& align_branch_ret_bit
))
9755 /* Check for indirect jmp, direct and indirect calls. */
9756 if (i
.tm
.base_opcode
== 0xe8)
9759 *branch_p
= align_branch_call
;
9760 if ((align_branch
& align_branch_call_bit
))
9763 else if (i
.tm
.base_opcode
== 0xff
9764 && (i
.tm
.extension_opcode
== 2
9765 || i
.tm
.extension_opcode
== 4))
9767 /* Indirect call and jmp. */
9768 *branch_p
= align_branch_indirect
;
9769 if ((align_branch
& align_branch_indirect_bit
))
9776 && (i
.op
[0].disps
->X_op
== O_symbol
9777 || (i
.op
[0].disps
->X_op
== O_subtract
9778 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9780 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9781 /* No padding to call to global or undefined tls_get_addr. */
9782 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9783 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9789 && last_insn
.kind
!= last_insn_other
9790 && last_insn
.seg
== now_seg
)
9793 as_warn_where (last_insn
.file
, last_insn
.line
,
9794 _("`%s` skips -malign-branch-boundary on `%s`"),
9795 last_insn
.name
, insn_name (&i
.tm
));
9805 fragS
*insn_start_frag
;
9806 offsetT insn_start_off
;
9807 fragS
*fragP
= NULL
;
9808 enum align_branch_kind branch
= align_branch_none
;
9809 /* The initializer is arbitrary just to avoid uninitialized error.
9810 it's actually either assigned in add_branch_padding_frag_p
9811 or never be used. */
9812 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9815 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9817 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9818 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9819 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9821 if (is_cpu (&i
.tm
, Cpu8087
)
9822 || is_cpu (&i
.tm
, Cpu287
)
9823 || is_cpu (&i
.tm
, Cpu387
)
9824 || is_cpu (&i
.tm
, Cpu687
)
9825 || is_cpu (&i
.tm
, CpuFISTTP
))
9826 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9828 if ((i
.xstate
& xstate_mmx
)
9829 || i
.tm
.mnem_off
== MN_emms
9830 || i
.tm
.mnem_off
== MN_femms
)
9831 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9835 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9836 i
.xstate
|= xstate_zmm
;
9837 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9838 i
.xstate
|= xstate_ymm
;
9839 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9840 i
.xstate
|= xstate_xmm
;
9843 /* vzeroall / vzeroupper */
9844 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9845 i
.xstate
|= xstate_ymm
;
9847 if ((i
.xstate
& xstate_xmm
)
9848 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9849 || (i
.tm
.base_opcode
== 0xae
9850 && (is_cpu (&i
.tm
, CpuSSE
)
9851 || is_cpu (&i
.tm
, CpuAVX
)))
9852 || is_cpu (&i
.tm
, CpuWideKL
)
9853 || is_cpu (&i
.tm
, CpuKL
))
9854 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9856 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9857 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9858 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9859 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9860 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9861 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9862 if (is_cpu (&i
.tm
, CpuFXSR
))
9863 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9864 if (is_cpu (&i
.tm
, CpuXsave
))
9865 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9866 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9867 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9868 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9869 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9871 if (x86_feature_2_used
9872 || is_cpu (&i
.tm
, CpuCMOV
)
9873 || is_cpu (&i
.tm
, CpuSYSCALL
)
9874 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9875 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9876 if (is_cpu (&i
.tm
, CpuSSE3
)
9877 || is_cpu (&i
.tm
, CpuSSSE3
)
9878 || is_cpu (&i
.tm
, CpuSSE4_1
)
9879 || is_cpu (&i
.tm
, CpuSSE4_2
)
9880 || is_cpu (&i
.tm
, CpuCX16
)
9881 || is_cpu (&i
.tm
, CpuPOPCNT
)
9882 /* LAHF-SAHF insns in 64-bit mode. */
9883 || (flag_code
== CODE_64BIT
9884 && (i
.tm
.base_opcode
| 1) == 0x9f
9885 && i
.tm
.opcode_space
== SPACE_BASE
))
9886 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9887 if (is_cpu (&i
.tm
, CpuAVX
)
9888 || is_cpu (&i
.tm
, CpuAVX2
)
9889 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9890 XOP, FMA4, LPW, TBM, and AMX. */
9891 || (i
.tm
.opcode_modifier
.vex
9892 && !is_cpu (&i
.tm
, CpuAVX512F
)
9893 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9894 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9895 && !is_cpu (&i
.tm
, CpuXOP
)
9896 && !is_cpu (&i
.tm
, CpuFMA4
)
9897 && !is_cpu (&i
.tm
, CpuLWP
)
9898 && !is_cpu (&i
.tm
, CpuTBM
)
9899 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9900 || is_cpu (&i
.tm
, CpuF16C
)
9901 || is_cpu (&i
.tm
, CpuFMA
)
9902 || is_cpu (&i
.tm
, CpuLZCNT
)
9903 || is_cpu (&i
.tm
, CpuMovbe
)
9904 || is_cpu (&i
.tm
, CpuXSAVES
)
9905 || (x86_feature_2_used
9906 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9907 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9908 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9909 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9910 if (is_cpu (&i
.tm
, CpuAVX512F
)
9911 || is_cpu (&i
.tm
, CpuAVX512BW
)
9912 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9913 || is_cpu (&i
.tm
, CpuAVX512VL
)
9914 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9915 AVX512-4FMAPS, and AVX512-4VNNIW. */
9916 || (i
.tm
.opcode_modifier
.evex
9917 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9918 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9919 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9920 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9921 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9925 /* Tie dwarf2 debug info to the address at the start of the insn.
9926 We can't do this after the insn has been output as the current
9927 frag may have been closed off. eg. by frag_var. */
9928 dwarf2_emit_insn (0);
9930 insn_start_frag
= frag_now
;
9931 insn_start_off
= frag_now_fix ();
9933 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9936 /* Branch can be 8 bytes. Leave some room for prefixes. */
9937 unsigned int max_branch_padding_size
= 14;
9939 /* Align section to boundary. */
9940 record_alignment (now_seg
, align_branch_power
);
9942 /* Make room for padding. */
9943 frag_grow (max_branch_padding_size
);
9945 /* Start of the padding. */
9950 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9951 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9954 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9955 fragP
->tc_frag_data
.branch_type
= branch
;
9956 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9959 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9960 && !pre_386_16bit_warned
)
9962 as_warn (_("use .code16 to ensure correct addressing mode"));
9963 pre_386_16bit_warned
= true;
9967 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9969 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9970 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9972 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9973 output_interseg_jump ();
9976 /* Output normal instructions here. */
9980 enum mf_cmp_kind mf_cmp
;
9983 && (i
.tm
.base_opcode
== 0xaee8
9984 || i
.tm
.base_opcode
== 0xaef0
9985 || i
.tm
.base_opcode
== 0xaef8))
9987 /* Encode lfence, mfence, and sfence as
9988 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9989 if (flag_code
== CODE_16BIT
)
9990 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9991 else if (omit_lock_prefix
)
9992 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9994 else if (now_seg
!= absolute_section
)
9996 offsetT val
= 0x240483f0ULL
;
9999 md_number_to_chars (p
, val
, 5);
10002 abs_section_offset
+= 5;
10006 /* Some processors fail on LOCK prefix. This options makes
10007 assembler ignore LOCK prefix and serves as a workaround. */
10008 if (omit_lock_prefix
)
10010 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
10011 && i
.tm
.opcode_modifier
.isprefix
)
10013 i
.prefix
[LOCK_PREFIX
] = 0;
10017 /* Skip if this is a branch. */
10019 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10021 /* Make room for padding. */
10022 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10027 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10028 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10031 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10032 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10033 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10035 else if (add_branch_prefix_frag_p ())
10037 unsigned int max_prefix_size
= align_branch_prefix_size
;
10039 /* Make room for padding. */
10040 frag_grow (max_prefix_size
);
10045 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10046 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10049 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10052 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10053 don't need the explicit prefix. */
10054 if (!is_any_vex_encoding (&i
.tm
))
10056 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10065 if (!is_cpu (&i
.tm
, CpuPadLock
)
10066 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10070 switch (i
.opcode_length
)
10075 /* Check for pseudo prefixes. */
10076 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10078 as_bad_where (insn_start_frag
->fr_file
,
10079 insn_start_frag
->fr_line
,
10080 _("pseudo prefix without instruction"));
10090 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10091 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10092 R_X86_64_GOTTPOFF relocation so that linker can safely
10093 perform IE->LE optimization. A dummy REX_OPCODE prefix
10094 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10095 relocation for GDesc -> IE/LE optimization. */
10096 if (x86_elf_abi
== X86_64_X32_ABI
10098 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10099 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10100 && i
.prefix
[REX_PREFIX
] == 0)
10101 add_prefix (REX_OPCODE
);
10104 /* The prefix bytes. */
10105 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10107 frag_opcode_byte (*q
);
10111 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10117 frag_opcode_byte (*q
);
10120 /* There should be no other prefixes for instructions
10121 with VEX prefix. */
10125 /* For EVEX instructions i.vrex should become 0 after
10126 build_evex_prefix. For VEX instructions upper 16 registers
10127 aren't available, so VREX should be 0. */
10130 /* Now the VEX prefix. */
10131 if (now_seg
!= absolute_section
)
10133 p
= frag_more (i
.vex
.length
);
10134 for (j
= 0; j
< i
.vex
.length
; j
++)
10135 p
[j
] = i
.vex
.bytes
[j
];
10138 abs_section_offset
+= i
.vex
.length
;
10141 /* Now the opcode; be careful about word order here! */
10142 j
= i
.opcode_length
;
10144 switch (i
.tm
.opcode_space
)
10159 if (now_seg
== absolute_section
)
10160 abs_section_offset
+= j
;
10163 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10169 && i
.tm
.opcode_space
!= SPACE_BASE
)
10172 if (i
.tm
.opcode_space
!= SPACE_0F
)
10173 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10177 switch (i
.opcode_length
)
10180 /* Put out high byte first: can't use md_number_to_chars! */
10181 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10182 /* Fall through. */
10184 *p
= i
.tm
.base_opcode
& 0xff;
10193 /* Now the modrm byte and sib byte (if present). */
10194 if (i
.tm
.opcode_modifier
.modrm
)
10196 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10198 | (i
.rm
.mode
<< 6));
10199 /* If i.rm.regmem == ESP (4)
10200 && i.rm.mode != (Register mode)
10202 ==> need second modrm byte. */
10203 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10205 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10206 frag_opcode_byte ((i
.sib
.base
<< 0)
10207 | (i
.sib
.index
<< 3)
10208 | (i
.sib
.scale
<< 6));
10211 if (i
.disp_operands
)
10212 output_disp (insn_start_frag
, insn_start_off
);
10214 if (i
.imm_operands
)
10215 output_imm (insn_start_frag
, insn_start_off
);
10218 * frag_now_fix () returning plain abs_section_offset when we're in the
10219 * absolute section, and abs_section_offset not getting updated as data
10220 * gets added to the frag breaks the logic below.
10222 if (now_seg
!= absolute_section
)
10224 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10226 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10230 /* NB: Don't add prefix with GOTPC relocation since
10231 output_disp() above depends on the fixed encoding
10232 length. Can't add prefix with TLS relocation since
10233 it breaks TLS linker optimization. */
10234 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10235 /* Prefix count on the current instruction. */
10236 unsigned int count
= i
.vex
.length
;
10238 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10239 /* REX byte is encoded in VEX/EVEX prefix. */
10240 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10243 /* Count prefixes for extended opcode maps. */
10245 switch (i
.tm
.opcode_space
)
10260 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10263 /* Set the maximum prefix size in BRANCH_PREFIX
10265 if (fragP
->tc_frag_data
.max_bytes
> max
)
10266 fragP
->tc_frag_data
.max_bytes
= max
;
10267 if (fragP
->tc_frag_data
.max_bytes
> count
)
10268 fragP
->tc_frag_data
.max_bytes
-= count
;
10270 fragP
->tc_frag_data
.max_bytes
= 0;
10274 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10276 unsigned int max_prefix_size
;
10277 if (align_branch_prefix_size
> max
)
10278 max_prefix_size
= max
;
10280 max_prefix_size
= align_branch_prefix_size
;
10281 if (max_prefix_size
> count
)
10282 fragP
->tc_frag_data
.max_prefix_length
10283 = max_prefix_size
- count
;
10286 /* Use existing segment prefix if possible. Use CS
10287 segment prefix in 64-bit mode. In 32-bit mode, use SS
10288 segment prefix with ESP/EBP base register and use DS
10289 segment prefix without ESP/EBP base register. */
10290 if (i
.prefix
[SEG_PREFIX
])
10291 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10292 else if (flag_code
== CODE_64BIT
)
10293 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10294 else if (i
.base_reg
10295 && (i
.base_reg
->reg_num
== 4
10296 || i
.base_reg
->reg_num
== 5))
10297 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10299 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10304 /* NB: Don't work with COND_JUMP86 without i386. */
10305 if (align_branch_power
10306 && now_seg
!= absolute_section
10307 && cpu_arch_flags
.bitfield
.cpui386
)
10309 /* Terminate each frag so that we can add prefix and check for
10311 frag_wane (frag_now
);
10318 pi ("" /*line*/, &i
);
10320 #endif /* DEBUG386 */
10323 /* Return the size of the displacement operand N. */
10326 disp_size (unsigned int n
)
10330 if (i
.types
[n
].bitfield
.disp64
)
10332 else if (i
.types
[n
].bitfield
.disp8
)
10334 else if (i
.types
[n
].bitfield
.disp16
)
10339 /* Return the size of the immediate operand N. */
10342 imm_size (unsigned int n
)
10345 if (i
.types
[n
].bitfield
.imm64
)
10347 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10349 else if (i
.types
[n
].bitfield
.imm16
)
10355 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10360 for (n
= 0; n
< i
.operands
; n
++)
10362 if (operand_type_check (i
.types
[n
], disp
))
10364 int size
= disp_size (n
);
10366 if (now_seg
== absolute_section
)
10367 abs_section_offset
+= size
;
10368 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10370 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10372 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10374 p
= frag_more (size
);
10375 md_number_to_chars (p
, val
, size
);
10379 enum bfd_reloc_code_real reloc_type
;
10380 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10381 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10382 && (!want_disp32 (&i
.tm
)
10383 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10384 && !i
.types
[n
].bitfield
.baseindex
)))
10388 /* We can't have 8 bit displacement here. */
10389 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10391 /* The PC relative address is computed relative
10392 to the instruction boundary, so in case immediate
10393 fields follows, we need to adjust the value. */
10394 if (pcrel
&& i
.imm_operands
)
10399 for (n1
= 0; n1
< i
.operands
; n1
++)
10400 if (operand_type_check (i
.types
[n1
], imm
))
10402 /* Only one immediate is allowed for PC
10403 relative address, except with .insn. */
10404 gas_assert (sz
== 0 || dot_insn ());
10405 sz
+= imm_size (n1
);
10407 /* We should find at least one immediate. */
10408 gas_assert (sz
!= 0);
10409 i
.op
[n
].disps
->X_add_number
-= sz
;
10412 p
= frag_more (size
);
10413 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10415 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10416 && (((reloc_type
== BFD_RELOC_32
10417 || reloc_type
== BFD_RELOC_X86_64_32S
10418 || (reloc_type
== BFD_RELOC_64
10420 && (i
.op
[n
].disps
->X_op
== O_symbol
10421 || (i
.op
[n
].disps
->X_op
== O_add
10422 && ((symbol_get_value_expression
10423 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10425 || reloc_type
== BFD_RELOC_32_PCREL
))
10429 reloc_type
= BFD_RELOC_386_GOTPC
;
10430 i
.has_gotpc_tls_reloc
= true;
10431 i
.op
[n
].disps
->X_add_number
+=
10432 encoding_length (insn_start_frag
, insn_start_off
, p
);
10434 else if (reloc_type
== BFD_RELOC_64
)
10435 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10437 /* Don't do the adjustment for x86-64, as there
10438 the pcrel addressing is relative to the _next_
10439 insn, and that is taken care of in other code. */
10440 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10442 else if (align_branch_power
)
10444 switch (reloc_type
)
10446 case BFD_RELOC_386_TLS_GD
:
10447 case BFD_RELOC_386_TLS_LDM
:
10448 case BFD_RELOC_386_TLS_IE
:
10449 case BFD_RELOC_386_TLS_IE_32
:
10450 case BFD_RELOC_386_TLS_GOTIE
:
10451 case BFD_RELOC_386_TLS_GOTDESC
:
10452 case BFD_RELOC_386_TLS_DESC_CALL
:
10453 case BFD_RELOC_X86_64_TLSGD
:
10454 case BFD_RELOC_X86_64_TLSLD
:
10455 case BFD_RELOC_X86_64_GOTTPOFF
:
10456 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10457 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10458 i
.has_gotpc_tls_reloc
= true;
10463 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10464 size
, i
.op
[n
].disps
, pcrel
,
10467 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10468 && !i
.prefix
[ADDR_PREFIX
])
10469 fixP
->fx_signed
= 1;
10471 /* Check for "call/jmp *mem", "mov mem, %reg",
10472 "test %reg, mem" and "binop mem, %reg" where binop
10473 is one of adc, add, and, cmp, or, sbb, sub, xor
10474 instructions without data prefix. Always generate
10475 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10476 if (i
.prefix
[DATA_PREFIX
] == 0
10477 && (generate_relax_relocations
10480 && i
.rm
.regmem
== 5))
10482 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10483 && i
.tm
.opcode_space
== SPACE_BASE
10484 && ((i
.operands
== 1
10485 && i
.tm
.base_opcode
== 0xff
10486 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10487 || (i
.operands
== 2
10488 && (i
.tm
.base_opcode
== 0x8b
10489 || i
.tm
.base_opcode
== 0x85
10490 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10494 fixP
->fx_tcbit
= i
.rex
!= 0;
10496 && (i
.base_reg
->reg_num
== RegIP
))
10497 fixP
->fx_tcbit2
= 1;
10500 fixP
->fx_tcbit2
= 1;
10508 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10513 for (n
= 0; n
< i
.operands
; n
++)
10515 if (operand_type_check (i
.types
[n
], imm
))
10517 int size
= imm_size (n
);
10519 if (now_seg
== absolute_section
)
10520 abs_section_offset
+= size
;
10521 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10525 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10527 p
= frag_more (size
);
10528 md_number_to_chars (p
, val
, size
);
10532 /* Not absolute_section.
10533 Need a 32-bit fixup (don't support 8bit
10534 non-absolute imms). Try to support other
10536 enum bfd_reloc_code_real reloc_type
;
10539 if (i
.types
[n
].bitfield
.imm32s
10540 && (i
.suffix
== QWORD_MNEM_SUFFIX
10541 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10542 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10548 p
= frag_more (size
);
10549 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10551 /* This is tough to explain. We end up with this one if we
10552 * have operands that look like
10553 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10554 * obtain the absolute address of the GOT, and it is strongly
10555 * preferable from a performance point of view to avoid using
10556 * a runtime relocation for this. The actual sequence of
10557 * instructions often look something like:
10562 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10564 * The call and pop essentially return the absolute address
10565 * of the label .L66 and store it in %ebx. The linker itself
10566 * will ultimately change the first operand of the addl so
10567 * that %ebx points to the GOT, but to keep things simple, the
10568 * .o file must have this operand set so that it generates not
10569 * the absolute address of .L66, but the absolute address of
10570 * itself. This allows the linker itself simply treat a GOTPC
10571 * relocation as asking for a pcrel offset to the GOT to be
10572 * added in, and the addend of the relocation is stored in the
10573 * operand field for the instruction itself.
10575 * Our job here is to fix the operand so that it would add
10576 * the correct offset so that %ebx would point to itself. The
10577 * thing that is tricky is that .-.L66 will point to the
10578 * beginning of the instruction, so we need to further modify
10579 * the operand so that it will point to itself. There are
10580 * other cases where you have something like:
10582 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10584 * and here no correction would be required. Internally in
10585 * the assembler we treat operands of this form as not being
10586 * pcrel since the '.' is explicitly mentioned, and I wonder
10587 * whether it would simplify matters to do it this way. Who
10588 * knows. In earlier versions of the PIC patches, the
10589 * pcrel_adjust field was used to store the correction, but
10590 * since the expression is not pcrel, I felt it would be
10591 * confusing to do it this way. */
10593 if ((reloc_type
== BFD_RELOC_32
10594 || reloc_type
== BFD_RELOC_X86_64_32S
10595 || reloc_type
== BFD_RELOC_64
)
10597 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10598 && (i
.op
[n
].imms
->X_op
== O_symbol
10599 || (i
.op
[n
].imms
->X_op
== O_add
10600 && ((symbol_get_value_expression
10601 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10605 reloc_type
= BFD_RELOC_386_GOTPC
;
10606 else if (size
== 4)
10607 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10608 else if (size
== 8)
10609 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10610 i
.has_gotpc_tls_reloc
= true;
10611 i
.op
[n
].imms
->X_add_number
+=
10612 encoding_length (insn_start_frag
, insn_start_off
, p
);
10614 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10615 i
.op
[n
].imms
, 0, reloc_type
);
10621 /* x86_cons_fix_new is called via the expression parsing code when a
10622 reloc is needed. We use this hook to get the correct .got reloc. */
10623 static int cons_sign
= -1;
10626 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10627 expressionS
*exp
, bfd_reloc_code_real_type r
)
10629 r
= reloc (len
, 0, cons_sign
, r
);
10632 if (exp
->X_op
== O_secrel
)
10634 exp
->X_op
= O_symbol
;
10635 r
= BFD_RELOC_32_SECREL
;
10637 else if (exp
->X_op
== O_secidx
)
10638 r
= BFD_RELOC_16_SECIDX
;
10641 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10644 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10645 purpose of the `.dc.a' internal pseudo-op. */
10648 x86_address_bytes (void)
10650 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10652 return stdoutput
->arch_info
->bits_per_address
/ 8;
10655 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10656 || defined (LEX_AT)) && !defined (TE_PE)
10657 # define lex_got(reloc, adjust, types) NULL
10659 /* Parse operands of the form
10660 <symbol>@GOTOFF+<nnn>
10661 and similar .plt or .got references.
10663 If we find one, set up the correct relocation in RELOC and copy the
10664 input string, minus the `@GOTOFF' into a malloc'd buffer for
10665 parsing by the calling routine. Return this buffer, and if ADJUST
10666 is non-null set it to the length of the string we removed from the
10667 input line. Otherwise return NULL. */
10669 lex_got (enum bfd_reloc_code_real
*rel
,
10671 i386_operand_type
*types
)
10673 /* Some of the relocations depend on the size of what field is to
10674 be relocated. But in our callers i386_immediate and i386_displacement
10675 we don't yet know the operand size (this will be set by insn
10676 matching). Hence we record the word32 relocation here,
10677 and adjust the reloc according to the real size in reloc(). */
10678 static const struct
10682 const enum bfd_reloc_code_real rel
[2];
10683 const i386_operand_type types64
;
10684 bool need_GOT_symbol
;
10689 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10690 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10691 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10692 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10693 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10694 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10695 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10696 { .imm64 = 1, .disp64 = 1 } }
10699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10700 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10701 BFD_RELOC_SIZE32
},
10702 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10704 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10705 BFD_RELOC_X86_64_PLTOFF64
},
10706 { .bitfield
= { .imm64
= 1 } }, true },
10707 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10708 BFD_RELOC_X86_64_PLT32
},
10709 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10710 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10711 BFD_RELOC_X86_64_GOTPLT64
},
10712 OPERAND_TYPE_IMM64_DISP64
, true },
10713 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10714 BFD_RELOC_X86_64_GOTOFF64
},
10715 OPERAND_TYPE_IMM64_DISP64
, true },
10716 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10717 BFD_RELOC_X86_64_GOTPCREL
},
10718 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10719 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10720 BFD_RELOC_X86_64_TLSGD
},
10721 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10722 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10723 _dummy_first_bfd_reloc_code_real
},
10724 OPERAND_TYPE_NONE
, true },
10725 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10726 BFD_RELOC_X86_64_TLSLD
},
10727 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10728 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10729 BFD_RELOC_X86_64_GOTTPOFF
},
10730 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10731 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10732 BFD_RELOC_X86_64_TPOFF32
},
10733 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10734 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10735 _dummy_first_bfd_reloc_code_real
},
10736 OPERAND_TYPE_NONE
, true },
10737 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10738 BFD_RELOC_X86_64_DTPOFF32
},
10739 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10740 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10741 _dummy_first_bfd_reloc_code_real
},
10742 OPERAND_TYPE_NONE
, true },
10743 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10744 _dummy_first_bfd_reloc_code_real
},
10745 OPERAND_TYPE_NONE
, true },
10746 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10747 BFD_RELOC_X86_64_GOT32
},
10748 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10749 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10750 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10751 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10752 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10753 BFD_RELOC_X86_64_TLSDESC_CALL
},
10754 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10756 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10757 BFD_RELOC_32_SECREL
},
10758 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10761 #undef OPERAND_TYPE_IMM32_32S_DISP32
10762 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10763 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10764 #undef OPERAND_TYPE_IMM64_DISP64
10770 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10775 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10776 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10779 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10781 int len
= gotrel
[j
].len
;
10782 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10784 if (gotrel
[j
].rel
[object_64bit
] != 0)
10787 char *tmpbuf
, *past_reloc
;
10789 *rel
= gotrel
[j
].rel
[object_64bit
];
10793 if (flag_code
!= CODE_64BIT
)
10795 types
->bitfield
.imm32
= 1;
10796 types
->bitfield
.disp32
= 1;
10799 *types
= gotrel
[j
].types64
;
10802 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10803 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10805 /* The length of the first part of our input line. */
10806 first
= cp
- input_line_pointer
;
10808 /* The second part goes from after the reloc token until
10809 (and including) an end_of_line char or comma. */
10810 past_reloc
= cp
+ 1 + len
;
10812 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10814 second
= cp
+ 1 - past_reloc
;
10816 /* Allocate and copy string. The trailing NUL shouldn't
10817 be necessary, but be safe. */
10818 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10819 memcpy (tmpbuf
, input_line_pointer
, first
);
10820 if (second
!= 0 && *past_reloc
!= ' ')
10821 /* Replace the relocation token with ' ', so that
10822 errors like foo@GOTOFF1 will be detected. */
10823 tmpbuf
[first
++] = ' ';
10825 /* Increment length by 1 if the relocation token is
10830 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10831 tmpbuf
[first
+ second
] = '\0';
10835 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10836 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10841 /* Might be a symbol version string. Don't as_bad here. */
10846 bfd_reloc_code_real_type
10847 x86_cons (expressionS
*exp
, int size
)
10849 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10851 intel_syntax
= -intel_syntax
;
10853 expr_mode
= expr_operator_none
;
10855 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10856 && !defined (LEX_AT)) \
10858 if (size
== 4 || (object_64bit
&& size
== 8))
10860 /* Handle @GOTOFF and the like in an expression. */
10862 char *gotfree_input_line
;
10865 save
= input_line_pointer
;
10866 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10867 if (gotfree_input_line
)
10868 input_line_pointer
= gotfree_input_line
;
10872 if (gotfree_input_line
)
10874 /* expression () has merrily parsed up to the end of line,
10875 or a comma - in the wrong buffer. Transfer how far
10876 input_line_pointer has moved to the right buffer. */
10877 input_line_pointer
= (save
10878 + (input_line_pointer
- gotfree_input_line
)
10880 free (gotfree_input_line
);
10881 if (exp
->X_op
== O_constant
10882 || exp
->X_op
== O_absent
10883 || exp
->X_op
== O_illegal
10884 || exp
->X_op
== O_register
10885 || exp
->X_op
== O_big
)
10887 char c
= *input_line_pointer
;
10888 *input_line_pointer
= 0;
10889 as_bad (_("missing or invalid expression `%s'"), save
);
10890 *input_line_pointer
= c
;
10892 else if ((got_reloc
== BFD_RELOC_386_PLT32
10893 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10894 && exp
->X_op
!= O_symbol
)
10896 char c
= *input_line_pointer
;
10897 *input_line_pointer
= 0;
10898 as_bad (_("invalid PLT expression `%s'"), save
);
10899 *input_line_pointer
= c
;
10907 intel_syntax
= -intel_syntax
;
10910 i386_intel_simplify (exp
);
10912 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10913 if (size
<= 4 && expr_mode
== expr_operator_present
10914 && exp
->X_op
== O_constant
&& !object_64bit
)
10915 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10921 signed_cons (int size
)
10930 s_insn (int dummy ATTRIBUTE_UNUSED
)
10932 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10933 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10937 bool vex
= false, xop
= false, evex
= false;
10938 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10942 saved_char
= *saved_ilp
;
10945 end
= parse_insn (line
, mnemonic
, true);
10949 *saved_ilp
= saved_char
;
10950 ignore_rest_of_line ();
10954 line
+= end
- line
;
10956 current_templates
= &tt
;
10957 i
.tm
.mnem_off
= MN__insn
;
10958 i
.tm
.extension_opcode
= None
;
10960 if (startswith (line
, "VEX")
10961 && (line
[3] == '.' || is_space_char (line
[3])))
10966 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10969 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10971 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10972 && (*e
== '.' || is_space_char (*e
)))
10975 /* Arrange for build_vex_prefix() to emit 0x8f. */
10976 i
.tm
.opcode_space
= SPACE_XOP08
;
10977 i
.insn_opcode_space
= n
;
10981 else if (startswith (line
, "EVEX")
10982 && (line
[4] == '.' || is_space_char (line
[4])))
10989 ? i
.vec_encoding
== vex_encoding_evex
10991 ? i
.vec_encoding
== vex_encoding_vex
10992 || i
.vec_encoding
== vex_encoding_vex3
10993 : i
.vec_encoding
!= vex_encoding_default
)
10995 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10999 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
11000 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
11002 if (i
.vec_encoding
!= vex_encoding_default
)
11004 /* Only address size and segment override prefixes are permitted with
11005 VEX/XOP/EVEX encodings. */
11006 const unsigned char *p
= i
.prefix
;
11008 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11019 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11025 if (line
> end
&& *line
== '.')
11027 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11035 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11037 i
.tm
.opcode_modifier
.vex
= VEX128
;
11042 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11044 i
.tm
.opcode_modifier
.vex
= VEX256
;
11049 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11054 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11058 if (line
[3] == 'G')
11061 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11063 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11069 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11074 if (line
[2] == '2' && line
[3] == '8')
11077 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11079 i
.tm
.opcode_modifier
.vex
= VEX128
;
11085 if (line
[2] == '5' && line
[3] == '6')
11088 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11090 i
.tm
.opcode_modifier
.vex
= VEX256
;
11096 if (evex
&& line
[2] == '1' && line
[3] == '2')
11098 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11105 if (line
> end
&& *line
== '.')
11107 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11111 if (line
[2] == 'P')
11116 if (line
[2] == '6')
11118 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11123 case 'F': case 'f':
11124 if (line
[2] == '3')
11126 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11129 else if (line
[2] == '2')
11131 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11138 if (line
> end
&& !xop
&& *line
== '.')
11140 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11144 if (TOUPPER (line
[2]) != 'F')
11146 if (line
[3] == '.' || is_space_char (line
[3]))
11148 i
.insn_opcode_space
= SPACE_0F
;
11151 else if (line
[3] == '3'
11152 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11153 && (line
[5] == '.' || is_space_char (line
[5])))
11155 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11161 if (ISDIGIT (line
[2]) && line
[2] != '0')
11164 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11166 if (n
<= (evex
? 15 : 31)
11167 && (*e
== '.' || is_space_char (*e
)))
11169 i
.insn_opcode_space
= n
;
11177 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11179 /* VEX.W, XOP.W, EVEX.W */
11183 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11187 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11191 if (line
[3] == 'G')
11193 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11199 if (i
.tm
.opcode_modifier
.vexw
)
11203 if (line
> end
&& *line
&& !is_space_char (*line
))
11205 /* Improve diagnostic a little. */
11206 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11211 /* Before processing the opcode expression, find trailing "+r" or
11212 "/<digit>" specifiers. */
11213 for (ptr
= line
; ; ++ptr
)
11218 ptr
= strpbrk (ptr
, "+/,");
11219 if (ptr
== NULL
|| *ptr
== ',')
11222 if (*ptr
== '+' && ptr
[1] == 'r'
11223 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11227 i
.short_form
= true;
11231 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11232 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11234 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11238 i
.tm
.extension_opcode
= n
;
11239 i
.tm
.opcode_modifier
.modrm
= 1;
11244 input_line_pointer
= line
;
11245 val
= get_absolute_expression ();
11246 line
= input_line_pointer
;
11248 if (i
.short_form
&& (val
& 7))
11249 as_warn ("`+r' assumes low three opcode bits to be clear");
11251 for (j
= 1; j
< sizeof(val
); ++j
)
11252 if (!(val
>> (j
* 8)))
11255 /* Trim off a prefix if present. */
11256 if (j
> 1 && !vex
&& !xop
&& !evex
)
11258 uint8_t byte
= val
>> ((j
- 1) * 8);
11262 case DATA_PREFIX_OPCODE
:
11263 case REPE_PREFIX_OPCODE
:
11264 case REPNE_PREFIX_OPCODE
:
11265 if (!add_prefix (byte
))
11267 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11272 /* Trim off encoding space. */
11273 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11275 uint8_t byte
= val
>> ((--j
- 1) * 8);
11277 i
.insn_opcode_space
= SPACE_0F
;
11278 switch (byte
& -(j
> 1))
11281 i
.insn_opcode_space
= SPACE_0F38
;
11285 i
.insn_opcode_space
= SPACE_0F3A
;
11289 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11290 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11292 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11293 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11294 Also avoid hitting abort() there or in build_evex_prefix(). */
11295 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11300 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11303 i
.opcode_length
= j
;
11305 /* Handle operands, if any. */
11308 i386_operand_type combined
;
11309 expressionS
*disp_exp
= NULL
;
11314 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11322 as_bad (_("expecting operand after ','; got nothing"));
11326 if (i
.mem_operands
> 1)
11328 as_bad (_("too many memory references for `%s'"),
11329 &i386_mnemonics
[MN__insn
]);
11333 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11334 if (i
.vec_encoding
== vex_encoding_evex512
)
11335 i
.vec_encoding
= vex_encoding_evex
;
11337 /* Are we to emit ModR/M encoding? */
11340 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11341 || i
.tm
.extension_opcode
!= None
))
11342 i
.tm
.opcode_modifier
.modrm
= 1;
11344 if (!i
.tm
.opcode_modifier
.modrm
11346 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11347 || i
.mem_operands
))
11349 as_bad (_("too many register/memory operands"));
11353 /* Enforce certain constraints on operands. */
11354 switch (i
.reg_operands
+ i
.mem_operands
11355 + (i
.tm
.extension_opcode
!= None
))
11360 as_bad (_("too few register/memory operands"));
11363 /* Fall through. */
11365 if (i
.tm
.opcode_modifier
.modrm
)
11367 as_bad (_("too few register/memory operands"));
11377 && (i
.op
[0].imms
->X_op
!= O_constant
11378 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11380 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11383 /* Fall through. */
11385 if (i
.vec_encoding
!= vex_encoding_default
)
11387 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11390 /* Fall through. */
11392 as_bad (_("too many register/memory operands"));
11396 /* Bring operands into canonical order (imm, mem, reg). */
11401 for (j
= 1; j
< i
.operands
; ++j
)
11403 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11404 && operand_type_check (i
.types
[j
], imm
))
11405 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11406 && i
.types
[j
].bitfield
.class == ClassNone
))
11408 swap_2_operands (j
- 1, j
);
11415 /* For Intel syntax swap the order of register operands. */
11417 switch (i
.reg_operands
)
11424 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11425 /* Fall through. */
11428 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11435 /* Enforce constraints when using VSIB. */
11437 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11438 || i
.index_reg
->reg_type
.bitfield
.ymmword
11439 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11441 if (i
.vec_encoding
== vex_encoding_default
)
11443 as_bad (_("VSIB unavailable with legacy encoding"));
11447 if (i
.vec_encoding
== vex_encoding_evex
11448 && i
.reg_operands
> 1)
11450 /* We could allow two register operands, encoding the 2nd one in
11451 an 8-bit immediate like for 4-register-operand insns, but that
11452 would require ugly fiddling with process_operands() and/or
11453 build_modrm_byte(). */
11454 as_bad (_("too many register operands with VSIB"));
11458 i
.tm
.opcode_modifier
.sib
= 1;
11461 /* Establish operand size encoding. */
11462 operand_type_set (&combined
, 0);
11464 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11466 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11468 if (operand_type_check (i
.types
[j
], disp
))
11470 i
.types
[j
].bitfield
.baseindex
= 1;
11471 disp_exp
= i
.op
[j
].disps
;
11474 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11476 unsigned int n
= i
.memshift
;
11478 if (i
.types
[j
].bitfield
.byte
)
11480 else if (i
.types
[j
].bitfield
.word
)
11482 else if (i
.types
[j
].bitfield
.dword
)
11484 else if (i
.types
[j
].bitfield
.qword
)
11486 else if (i
.types
[j
].bitfield
.xmmword
)
11488 else if (i
.types
[j
].bitfield
.ymmword
)
11490 else if (i
.types
[j
].bitfield
.zmmword
)
11493 if (i
.memshift
< 32 && n
!= i
.memshift
)
11494 as_warn ("conflicting memory operand size specifiers");
11498 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11499 && j
== i
.broadcast
.operand
)
11502 combined
= operand_type_or (combined
, i
.types
[j
]);
11503 combined
.bitfield
.class = ClassNone
;
11506 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11507 << (i
.memshift
< 32 ? i
.memshift
: 0))
11509 case 64: combined
.bitfield
.zmmword
= 1; break;
11510 case 32: combined
.bitfield
.ymmword
= 1; break;
11511 case 16: combined
.bitfield
.xmmword
= 1; break;
11512 case 8: combined
.bitfield
.qword
= 1; break;
11513 case 4: combined
.bitfield
.dword
= 1; break;
11516 if (i
.vec_encoding
== vex_encoding_default
)
11518 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11520 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11521 : combined
.bitfield
.word
)
11522 && !add_prefix (DATA_PREFIX_OPCODE
))
11525 else if (!i
.tm
.opcode_modifier
.vexw
)
11527 if (flag_code
== CODE_64BIT
)
11529 if (combined
.bitfield
.qword
)
11530 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11531 else if (combined
.bitfield
.dword
)
11532 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11535 if (!i
.tm
.opcode_modifier
.vexw
)
11536 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11541 if (!i
.tm
.opcode_modifier
.vex
)
11543 if (combined
.bitfield
.ymmword
)
11544 i
.tm
.opcode_modifier
.vex
= VEX256
;
11545 else if (combined
.bitfield
.xmmword
)
11546 i
.tm
.opcode_modifier
.vex
= VEX128
;
11551 if (!i
.tm
.opcode_modifier
.evex
)
11553 /* Do _not_ consider AVX512VL here. */
11554 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11555 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11556 else if (combined
.bitfield
.ymmword
)
11557 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11558 else if (combined
.bitfield
.xmmword
)
11559 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11562 if (i
.memshift
>= 32)
11564 unsigned int n
= 0;
11566 switch (i
.tm
.opcode_modifier
.evex
)
11568 case EVEX512
: n
= 64; break;
11569 case EVEX256
: n
= 32; break;
11570 case EVEX128
: n
= 16; break;
11573 if (i
.broadcast
.type
)
11574 n
/= i
.broadcast
.type
;
11577 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11579 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11580 && disp_exp
->X_add_number
!= 0
11581 && i
.disp_encoding
!= disp_encoding_32bit
)
11583 if (!quiet_warnings
)
11584 as_warn ("cannot determine memory operand size");
11585 i
.disp_encoding
= disp_encoding_32bit
;
11590 if (i
.memshift
>= 32)
11593 i
.vec_encoding
= vex_encoding_error
;
11595 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11598 /* Establish size for immediate operands. */
11599 for (j
= 0; j
< i
.imm_operands
; ++j
)
11601 expressionS
*expP
= i
.op
[j
].imms
;
11603 gas_assert (operand_type_check (i
.types
[j
], imm
));
11604 operand_type_set (&i
.types
[j
], 0);
11606 if (i
.imm_bits
[j
] > 32)
11607 i
.types
[j
].bitfield
.imm64
= 1;
11608 else if (i
.imm_bits
[j
] > 16)
11610 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11611 i
.types
[j
].bitfield
.imm32s
= 1;
11613 i
.types
[j
].bitfield
.imm32
= 1;
11615 else if (i
.imm_bits
[j
] > 8)
11616 i
.types
[j
].bitfield
.imm16
= 1;
11617 else if (i
.imm_bits
[j
] > 0)
11619 if (i
.flags
[j
] & Operand_Signed
)
11620 i
.types
[j
].bitfield
.imm8s
= 1;
11622 i
.types
[j
].bitfield
.imm8
= 1;
11624 else if (expP
->X_op
== O_constant
)
11626 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11627 i
.types
[j
].bitfield
.imm1
= 0;
11628 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11629 zapping since smallest_imm_type() sets it unconditionally. */
11630 if (flag_code
!= CODE_64BIT
)
11632 i
.types
[j
].bitfield
.imm64
= 0;
11633 i
.types
[j
].bitfield
.imm32s
= 0;
11634 i
.types
[j
].bitfield
.imm32
= 1;
11636 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11637 i
.types
[j
].bitfield
.imm64
= 0;
11640 /* Non-constant expressions are sized heuristically. */
11643 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11644 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11645 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11649 for (j
= 0; j
< i
.operands
; ++j
)
11650 i
.tm
.operand_types
[j
] = i
.types
[j
];
11652 process_operands ();
11655 /* Don't set opcode until after processing operands, to avoid any
11656 potential special casing there. */
11657 i
.tm
.base_opcode
|= val
;
11659 if (i
.vec_encoding
== vex_encoding_error
11660 || (i
.vec_encoding
!= vex_encoding_evex
11661 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11662 || i
.rounding
.type
!= rc_none
11664 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11665 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11666 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11668 as_bad (_("conflicting .insn operands"));
11674 if (!i
.tm
.opcode_modifier
.vex
)
11675 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11677 build_vex_prefix (NULL
);
11678 i
.rex
&= REX_OPCODE
;
11682 if (!i
.tm
.opcode_modifier
.evex
)
11683 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11685 build_evex_prefix ();
11686 i
.rex
&= REX_OPCODE
;
11688 else if (i
.rex
!= 0)
11689 add_prefix (REX_OPCODE
| i
.rex
);
11694 *saved_ilp
= saved_char
;
11695 input_line_pointer
= line
;
11697 demand_empty_rest_of_line ();
11699 /* Make sure dot_insn() won't yield "true" anymore. */
11705 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11712 if (exp
.X_op
== O_symbol
)
11713 exp
.X_op
= O_secrel
;
11715 emit_expr (&exp
, 4);
11717 while (*input_line_pointer
++ == ',');
11719 input_line_pointer
--;
11720 demand_empty_rest_of_line ();
11724 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11731 if (exp
.X_op
== O_symbol
)
11732 exp
.X_op
= O_secidx
;
11734 emit_expr (&exp
, 2);
11736 while (*input_line_pointer
++ == ',');
11738 input_line_pointer
--;
11739 demand_empty_rest_of_line ();
11743 /* Handle Rounding Control / SAE specifiers. */
11746 RC_SAE_specifier (const char *pstr
)
11750 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11752 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11754 if (i
.rounding
.type
!= rc_none
)
11756 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11760 if (i
.vec_encoding
== vex_encoding_default
)
11761 i
.vec_encoding
= vex_encoding_evex512
;
11762 else if (i
.vec_encoding
!= vex_encoding_evex
11763 && i
.vec_encoding
!= vex_encoding_evex512
)
11766 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11768 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11775 /* Handle Vector operations. */
11778 check_VecOperations (char *op_string
)
11780 const reg_entry
*mask
;
11787 if (*op_string
== '{')
11791 /* Check broadcasts. */
11792 if (startswith (op_string
, "1to"))
11794 unsigned int bcst_type
;
11796 if (i
.broadcast
.type
)
11797 goto duplicated_vec_op
;
11800 if (*op_string
== '8')
11802 else if (*op_string
== '4')
11804 else if (*op_string
== '2')
11806 else if (*op_string
== '1'
11807 && *(op_string
+1) == '6')
11812 else if (*op_string
== '3'
11813 && *(op_string
+1) == '2')
11820 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11825 if (i
.vec_encoding
== vex_encoding_default
)
11826 i
.vec_encoding
= vex_encoding_evex
;
11827 else if (i
.vec_encoding
!= vex_encoding_evex
11828 && i
.vec_encoding
!= vex_encoding_evex512
)
11829 goto unknown_vec_op
;
11831 i
.broadcast
.type
= bcst_type
;
11832 i
.broadcast
.operand
= this_operand
;
11834 /* For .insn a data size specifier may be appended. */
11835 if (dot_insn () && *op_string
== ':')
11836 goto dot_insn_modifier
;
11838 /* Check .insn special cases. */
11839 else if (dot_insn () && *op_string
== ':')
11842 switch (op_string
[1])
11847 if (i
.memshift
< 32)
11848 goto duplicated_vec_op
;
11850 n
= strtoul (op_string
+ 2, &end_op
, 0);
11852 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11854 if (i
.memshift
< 32 && n
== 1)
11855 op_string
= end_op
;
11858 case 's': case 'u':
11859 /* This isn't really a "vector" operation, but a sign/size
11860 specifier for immediate operands of .insn. Note that AT&T
11861 syntax handles the same in i386_immediate(). */
11865 if (i
.imm_bits
[this_operand
])
11866 goto duplicated_vec_op
;
11868 n
= strtoul (op_string
+ 2, &end_op
, 0);
11869 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11871 i
.imm_bits
[this_operand
] = n
;
11872 if (op_string
[1] == 's')
11873 i
.flags
[this_operand
] |= Operand_Signed
;
11874 op_string
= end_op
;
11879 /* Check masking operation. */
11880 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11882 if (mask
== &bad_reg
)
11885 /* k0 can't be used for write mask. */
11886 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11888 as_bad (_("`%s%s' can't be used for write mask"),
11889 register_prefix
, mask
->reg_name
);
11896 i
.mask
.operand
= this_operand
;
11898 else if (i
.mask
.reg
->reg_num
)
11899 goto duplicated_vec_op
;
11904 /* Only "{z}" is allowed here. No need to check
11905 zeroing mask explicitly. */
11906 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11908 as_bad (_("invalid write mask `%s'"), saved
);
11913 op_string
= end_op
;
11915 /* Check zeroing-flag for masking operation. */
11916 else if (*op_string
== 'z')
11920 i
.mask
.reg
= reg_k0
;
11921 i
.mask
.zeroing
= 1;
11922 i
.mask
.operand
= this_operand
;
11926 if (i
.mask
.zeroing
)
11929 as_bad (_("duplicated `%s'"), saved
);
11933 i
.mask
.zeroing
= 1;
11935 /* Only "{%k}" is allowed here. No need to check mask
11936 register explicitly. */
11937 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11939 as_bad (_("invalid zeroing-masking `%s'"),
11947 else if (intel_syntax
11948 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11949 i
.rounding
.modifier
= true;
11951 goto unknown_vec_op
;
11953 if (*op_string
!= '}')
11955 as_bad (_("missing `}' in `%s'"), saved
);
11960 /* Strip whitespace since the addition of pseudo prefixes
11961 changed how the scrubber treats '{'. */
11962 if (is_space_char (*op_string
))
11968 /* We don't know this one. */
11969 as_bad (_("unknown vector operation: `%s'"), saved
);
11973 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11975 as_bad (_("zeroing-masking only allowed with write mask"));
11983 i386_immediate (char *imm_start
)
11985 char *save_input_line_pointer
;
11986 char *gotfree_input_line
;
11989 i386_operand_type types
;
11991 operand_type_set (&types
, ~0);
11993 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11995 as_bad (_("at most %d immediate operands are allowed"),
11996 MAX_IMMEDIATE_OPERANDS
);
12000 exp
= &im_expressions
[i
.imm_operands
++];
12001 i
.op
[this_operand
].imms
= exp
;
12003 if (is_space_char (*imm_start
))
12006 save_input_line_pointer
= input_line_pointer
;
12007 input_line_pointer
= imm_start
;
12009 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12010 if (gotfree_input_line
)
12011 input_line_pointer
= gotfree_input_line
;
12013 expr_mode
= expr_operator_none
;
12014 exp_seg
= expression (exp
);
12016 /* For .insn immediates there may be a size specifier. */
12017 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12018 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12021 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12023 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12025 i
.imm_bits
[this_operand
] = n
;
12026 if (input_line_pointer
[2] == 's')
12027 i
.flags
[this_operand
] |= Operand_Signed
;
12028 input_line_pointer
= e
+ 1;
12032 SKIP_WHITESPACE ();
12033 if (*input_line_pointer
)
12034 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12036 input_line_pointer
= save_input_line_pointer
;
12037 if (gotfree_input_line
)
12039 free (gotfree_input_line
);
12041 if (exp
->X_op
== O_constant
)
12042 exp
->X_op
= O_illegal
;
12045 if (exp_seg
== reg_section
)
12047 as_bad (_("illegal immediate register operand %s"), imm_start
);
12051 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12055 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12056 i386_operand_type types
, const char *imm_start
)
12058 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12061 as_bad (_("missing or invalid immediate expression `%s'"),
12065 else if (exp
->X_op
== O_constant
)
12067 /* Size it properly later. */
12068 i
.types
[this_operand
].bitfield
.imm64
= 1;
12070 /* If not 64bit, sign/zero extend val, to account for wraparound
12072 if (expr_mode
== expr_operator_present
12073 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12074 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12076 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12077 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12078 && exp_seg
!= absolute_section
12079 && exp_seg
!= text_section
12080 && exp_seg
!= data_section
12081 && exp_seg
!= bss_section
12082 && exp_seg
!= undefined_section
12083 && !bfd_is_com_section (exp_seg
))
12085 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12091 /* This is an address. The size of the address will be
12092 determined later, depending on destination register,
12093 suffix, or the default for the section. */
12094 i
.types
[this_operand
].bitfield
.imm8
= 1;
12095 i
.types
[this_operand
].bitfield
.imm16
= 1;
12096 i
.types
[this_operand
].bitfield
.imm32
= 1;
12097 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12098 i
.types
[this_operand
].bitfield
.imm64
= 1;
12099 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12107 i386_scale (char *scale
)
12110 char *save
= input_line_pointer
;
12112 input_line_pointer
= scale
;
12113 val
= get_absolute_expression ();
12118 i
.log2_scale_factor
= 0;
12121 i
.log2_scale_factor
= 1;
12124 i
.log2_scale_factor
= 2;
12127 i
.log2_scale_factor
= 3;
12131 char sep
= *input_line_pointer
;
12133 *input_line_pointer
= '\0';
12134 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12136 *input_line_pointer
= sep
;
12137 input_line_pointer
= save
;
12141 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12143 as_warn (_("scale factor of %d without an index register"),
12144 1 << i
.log2_scale_factor
);
12145 i
.log2_scale_factor
= 0;
12147 scale
= input_line_pointer
;
12148 input_line_pointer
= save
;
12153 i386_displacement (char *disp_start
, char *disp_end
)
12157 char *save_input_line_pointer
;
12158 char *gotfree_input_line
;
12160 i386_operand_type bigdisp
, types
= anydisp
;
12163 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12165 as_bad (_("at most %d displacement operands are allowed"),
12166 MAX_MEMORY_OPERANDS
);
12170 operand_type_set (&bigdisp
, 0);
12172 || i
.types
[this_operand
].bitfield
.baseindex
12173 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12174 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12176 i386_addressing_mode ();
12177 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12178 if (flag_code
== CODE_64BIT
)
12180 bigdisp
.bitfield
.disp32
= 1;
12182 bigdisp
.bitfield
.disp64
= 1;
12184 else if ((flag_code
== CODE_16BIT
) ^ override
)
12185 bigdisp
.bitfield
.disp16
= 1;
12187 bigdisp
.bitfield
.disp32
= 1;
12191 /* For PC-relative branches, the width of the displacement may be
12192 dependent upon data size, but is never dependent upon address size.
12193 Also make sure to not unintentionally match against a non-PC-relative
12194 branch template. */
12195 static templates aux_templates
;
12196 const insn_template
*t
= current_templates
->start
;
12197 bool has_intel64
= false;
12199 aux_templates
.start
= t
;
12200 while (++t
< current_templates
->end
)
12202 if (t
->opcode_modifier
.jump
12203 != current_templates
->start
->opcode_modifier
.jump
)
12205 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12206 has_intel64
= true;
12208 if (t
< current_templates
->end
)
12210 aux_templates
.end
= t
;
12211 current_templates
= &aux_templates
;
12214 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12215 if (flag_code
== CODE_64BIT
)
12217 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12218 && (!intel64
|| !has_intel64
))
12219 bigdisp
.bitfield
.disp16
= 1;
12221 bigdisp
.bitfield
.disp32
= 1;
12226 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12228 : LONG_MNEM_SUFFIX
));
12229 bigdisp
.bitfield
.disp32
= 1;
12230 if ((flag_code
== CODE_16BIT
) ^ override
)
12232 bigdisp
.bitfield
.disp32
= 0;
12233 bigdisp
.bitfield
.disp16
= 1;
12237 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12240 exp
= &disp_expressions
[i
.disp_operands
];
12241 i
.op
[this_operand
].disps
= exp
;
12243 save_input_line_pointer
= input_line_pointer
;
12244 input_line_pointer
= disp_start
;
12245 END_STRING_AND_SAVE (disp_end
);
12247 #ifndef GCC_ASM_O_HACK
12248 #define GCC_ASM_O_HACK 0
12251 END_STRING_AND_SAVE (disp_end
+ 1);
12252 if (i
.types
[this_operand
].bitfield
.baseIndex
12253 && displacement_string_end
[-1] == '+')
12255 /* This hack is to avoid a warning when using the "o"
12256 constraint within gcc asm statements.
12259 #define _set_tssldt_desc(n,addr,limit,type) \
12260 __asm__ __volatile__ ( \
12261 "movw %w2,%0\n\t" \
12262 "movw %w1,2+%0\n\t" \
12263 "rorl $16,%1\n\t" \
12264 "movb %b1,4+%0\n\t" \
12265 "movb %4,5+%0\n\t" \
12266 "movb $0,6+%0\n\t" \
12267 "movb %h1,7+%0\n\t" \
12269 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12271 This works great except that the output assembler ends
12272 up looking a bit weird if it turns out that there is
12273 no offset. You end up producing code that looks like:
12286 So here we provide the missing zero. */
12288 *displacement_string_end
= '0';
12291 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12292 if (gotfree_input_line
)
12293 input_line_pointer
= gotfree_input_line
;
12295 expr_mode
= expr_operator_none
;
12296 exp_seg
= expression (exp
);
12298 SKIP_WHITESPACE ();
12299 if (*input_line_pointer
)
12300 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12302 RESTORE_END_STRING (disp_end
+ 1);
12304 input_line_pointer
= save_input_line_pointer
;
12305 if (gotfree_input_line
)
12307 free (gotfree_input_line
);
12309 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12310 exp
->X_op
= O_illegal
;
12313 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12315 RESTORE_END_STRING (disp_end
);
12321 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12322 i386_operand_type types
, const char *disp_start
)
12326 /* We do this to make sure that the section symbol is in
12327 the symbol table. We will ultimately change the relocation
12328 to be relative to the beginning of the section. */
12329 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12330 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12331 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12333 if (exp
->X_op
!= O_symbol
)
12336 if (S_IS_LOCAL (exp
->X_add_symbol
)
12337 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12338 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12339 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12340 exp
->X_op
= O_subtract
;
12341 exp
->X_op_symbol
= GOT_symbol
;
12342 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12343 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12344 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12345 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12347 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12350 else if (exp
->X_op
== O_absent
12351 || exp
->X_op
== O_illegal
12352 || exp
->X_op
== O_big
)
12355 as_bad (_("missing or invalid displacement expression `%s'"),
12360 else if (exp
->X_op
== O_constant
)
12362 /* Sizing gets taken care of by optimize_disp().
12364 If not 64bit, sign/zero extend val, to account for wraparound
12366 if (expr_mode
== expr_operator_present
12367 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12368 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12371 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12372 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12373 && exp_seg
!= absolute_section
12374 && exp_seg
!= text_section
12375 && exp_seg
!= data_section
12376 && exp_seg
!= bss_section
12377 && exp_seg
!= undefined_section
12378 && !bfd_is_com_section (exp_seg
))
12380 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12385 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12386 i
.types
[this_operand
].bitfield
.disp8
= 1;
12388 /* Check if this is a displacement only operand. */
12389 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12390 i
.types
[this_operand
] =
12391 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12392 operand_type_and (i
.types
[this_operand
], types
));
12397 /* Return the active addressing mode, taking address override and
12398 registers forming the address into consideration. Update the
12399 address override prefix if necessary. */
12401 static enum flag_code
12402 i386_addressing_mode (void)
12404 enum flag_code addr_mode
;
12406 if (i
.prefix
[ADDR_PREFIX
])
12407 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12408 else if (flag_code
== CODE_16BIT
12409 && is_cpu (current_templates
->start
, CpuMPX
)
12410 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12411 from md_assemble() by "is not a valid base/index expression"
12412 when there is a base and/or index. */
12413 && !i
.types
[this_operand
].bitfield
.baseindex
)
12415 /* MPX insn memory operands with neither base nor index must be forced
12416 to use 32-bit addressing in 16-bit mode. */
12417 addr_mode
= CODE_32BIT
;
12418 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12420 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12421 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12425 addr_mode
= flag_code
;
12427 #if INFER_ADDR_PREFIX
12428 if (i
.mem_operands
== 0)
12430 /* Infer address prefix from the first memory operand. */
12431 const reg_entry
*addr_reg
= i
.base_reg
;
12433 if (addr_reg
== NULL
)
12434 addr_reg
= i
.index_reg
;
12438 if (addr_reg
->reg_type
.bitfield
.dword
)
12439 addr_mode
= CODE_32BIT
;
12440 else if (flag_code
!= CODE_64BIT
12441 && addr_reg
->reg_type
.bitfield
.word
)
12442 addr_mode
= CODE_16BIT
;
12444 if (addr_mode
!= flag_code
)
12446 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12448 /* Change the size of any displacement too. At most one
12449 of Disp16 or Disp32 is set.
12450 FIXME. There doesn't seem to be any real need for
12451 separate Disp16 and Disp32 flags. The same goes for
12452 Imm16 and Imm32. Removing them would probably clean
12453 up the code quite a lot. */
12454 if (flag_code
!= CODE_64BIT
12455 && (i
.types
[this_operand
].bitfield
.disp16
12456 || i
.types
[this_operand
].bitfield
.disp32
))
12458 static const i386_operand_type disp16_32
= {
12459 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12462 i
.types
[this_operand
]
12463 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12474 /* Make sure the memory operand we've been dealt is valid.
12475 Return 1 on success, 0 on a failure. */
12478 i386_index_check (const char *operand_string
)
12480 const char *kind
= "base/index";
12481 enum flag_code addr_mode
= i386_addressing_mode ();
12482 const insn_template
*t
= current_templates
->end
- 1;
12484 if (t
->opcode_modifier
.isstring
)
12486 /* Memory operands of string insns are special in that they only allow
12487 a single register (rDI, rSI, or rBX) as their memory address. */
12488 const reg_entry
*expected_reg
;
12489 static const char di_si
[][2][4] =
12495 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12497 kind
= "string address";
12499 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12501 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12504 if (!t
->operand_types
[0].bitfield
.baseindex
12505 || ((!i
.mem_operands
!= !intel_syntax
)
12506 && t
->operand_types
[1].bitfield
.baseindex
))
12509 = (const reg_entry
*) str_hash_find (reg_hash
,
12510 di_si
[addr_mode
][op
== es_op
]);
12514 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12516 if (i
.base_reg
!= expected_reg
12518 || operand_type_check (i
.types
[this_operand
], disp
))
12520 /* The second memory operand must have the same size as
12524 && !((addr_mode
== CODE_64BIT
12525 && i
.base_reg
->reg_type
.bitfield
.qword
)
12526 || (addr_mode
== CODE_32BIT
12527 ? i
.base_reg
->reg_type
.bitfield
.dword
12528 : i
.base_reg
->reg_type
.bitfield
.word
)))
12531 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12533 intel_syntax
? '[' : '(',
12535 expected_reg
->reg_name
,
12536 intel_syntax
? ']' : ')');
12543 as_bad (_("`%s' is not a valid %s expression"),
12544 operand_string
, kind
);
12549 t
= current_templates
->start
;
12551 if (addr_mode
!= CODE_16BIT
)
12553 /* 32-bit/64-bit checks. */
12554 if (i
.disp_encoding
== disp_encoding_16bit
)
12557 as_bad (_("invalid `%s' prefix"),
12558 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12563 && ((addr_mode
== CODE_64BIT
12564 ? !i
.base_reg
->reg_type
.bitfield
.qword
12565 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12566 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12567 || i
.base_reg
->reg_num
== RegIZ
))
12569 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12570 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12571 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12572 && ((addr_mode
== CODE_64BIT
12573 ? !i
.index_reg
->reg_type
.bitfield
.qword
12574 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12575 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12578 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12579 if (t
->mnem_off
== MN_bndmk
12580 || t
->mnem_off
== MN_bndldx
12581 || t
->mnem_off
== MN_bndstx
12582 || t
->opcode_modifier
.sib
== SIBMEM
)
12584 /* They cannot use RIP-relative addressing. */
12585 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12587 as_bad (_("`%s' cannot be used here"), operand_string
);
12591 /* bndldx and bndstx ignore their scale factor. */
12592 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12593 && i
.log2_scale_factor
)
12594 as_warn (_("register scaling is being ignored here"));
12599 /* 16-bit checks. */
12600 if (i
.disp_encoding
== disp_encoding_32bit
)
12604 && (!i
.base_reg
->reg_type
.bitfield
.word
12605 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12607 && (!i
.index_reg
->reg_type
.bitfield
.word
12608 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12610 && i
.base_reg
->reg_num
< 6
12611 && i
.index_reg
->reg_num
>= 6
12612 && i
.log2_scale_factor
== 0))))
12619 /* Handle vector immediates. */
12622 RC_SAE_immediate (const char *imm_start
)
12624 const char *pstr
= imm_start
;
12629 pstr
= RC_SAE_specifier (pstr
+ 1);
12633 if (*pstr
++ != '}')
12635 as_bad (_("Missing '}': '%s'"), imm_start
);
12638 /* RC/SAE immediate string should contain nothing more. */;
12641 as_bad (_("Junk after '}': '%s'"), imm_start
);
12645 /* Internally this doesn't count as an operand. */
12651 static INLINE
bool starts_memory_operand (char c
)
12654 || is_name_beginner (c
)
12655 || strchr ("([\"+-!~", c
);
12658 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12662 i386_att_operand (char *operand_string
)
12664 const reg_entry
*r
;
12666 char *op_string
= operand_string
;
12668 if (is_space_char (*op_string
))
12671 /* We check for an absolute prefix (differentiating,
12672 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12673 if (*op_string
== ABSOLUTE_PREFIX
12674 && current_templates
->start
->opcode_modifier
.jump
)
12677 if (is_space_char (*op_string
))
12679 i
.jumpabsolute
= true;
12682 /* Check if operand is a register. */
12683 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12685 i386_operand_type temp
;
12690 /* Check for a segment override by searching for ':' after a
12691 segment register. */
12692 op_string
= end_op
;
12693 if (is_space_char (*op_string
))
12695 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12697 i
.seg
[i
.mem_operands
] = r
;
12699 /* Skip the ':' and whitespace. */
12701 if (is_space_char (*op_string
))
12704 /* Handle case of %es:*foo. */
12705 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12706 && current_templates
->start
->opcode_modifier
.jump
)
12709 if (is_space_char (*op_string
))
12711 i
.jumpabsolute
= true;
12714 if (!starts_memory_operand (*op_string
))
12716 as_bad (_("bad memory operand `%s'"), op_string
);
12719 goto do_memory_reference
;
12722 /* Handle vector operations. */
12723 if (*op_string
== '{')
12725 op_string
= check_VecOperations (op_string
);
12726 if (op_string
== NULL
)
12732 as_bad (_("junk `%s' after register"), op_string
);
12736 /* Reject pseudo registers for .insn. */
12737 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12739 as_bad (_("`%s%s' cannot be used here"),
12740 register_prefix
, r
->reg_name
);
12744 temp
= r
->reg_type
;
12745 temp
.bitfield
.baseindex
= 0;
12746 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12748 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12749 i
.op
[this_operand
].regs
= r
;
12752 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12753 operand was also present earlier on. */
12754 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12755 && i
.reg_operands
== 1)
12759 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12760 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12762 as_bad (_("`%s': misplaced `{%s}'"),
12763 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12767 else if (*op_string
== REGISTER_PREFIX
)
12769 as_bad (_("bad register name `%s'"), op_string
);
12772 else if (*op_string
== IMMEDIATE_PREFIX
)
12775 if (i
.jumpabsolute
)
12777 as_bad (_("immediate operand illegal with absolute jump"));
12780 if (!i386_immediate (op_string
))
12782 if (i
.rounding
.type
!= rc_none
)
12784 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12785 insn_name (current_templates
->start
));
12789 else if (RC_SAE_immediate (operand_string
))
12791 /* If it is a RC or SAE immediate, do the necessary placement check:
12792 Only another immediate or a GPR may precede it. */
12793 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12794 || (i
.reg_operands
== 1
12795 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12797 as_bad (_("`%s': misplaced `%s'"),
12798 insn_name (current_templates
->start
), operand_string
);
12802 else if (starts_memory_operand (*op_string
))
12804 /* This is a memory reference of some sort. */
12807 /* Start and end of displacement string expression (if found). */
12808 char *displacement_string_start
;
12809 char *displacement_string_end
;
12811 do_memory_reference
:
12812 /* Check for base index form. We detect the base index form by
12813 looking for an ')' at the end of the operand, searching
12814 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12816 base_string
= op_string
+ strlen (op_string
);
12818 /* Handle vector operations. */
12820 if (is_space_char (*base_string
))
12823 if (*base_string
== '}')
12825 char *vop_start
= NULL
;
12827 while (base_string
-- > op_string
)
12829 if (*base_string
== '"')
12831 if (*base_string
!= '{')
12834 vop_start
= base_string
;
12837 if (is_space_char (*base_string
))
12840 if (*base_string
!= '}')
12848 as_bad (_("unbalanced figure braces"));
12852 if (check_VecOperations (vop_start
) == NULL
)
12856 /* If we only have a displacement, set-up for it to be parsed later. */
12857 displacement_string_start
= op_string
;
12858 displacement_string_end
= base_string
+ 1;
12860 if (*base_string
== ')')
12863 unsigned int parens_not_balanced
= 0;
12864 bool in_quotes
= false;
12866 /* We've already checked that the number of left & right ()'s are
12867 equal, and that there's a matching set of double quotes. */
12868 end_op
= base_string
;
12869 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12871 if (*temp_string
== '\\' && temp_string
[1] == '"')
12873 else if (*temp_string
== '"')
12874 in_quotes
= !in_quotes
;
12875 else if (!in_quotes
)
12877 if (*temp_string
== '(' && !parens_not_balanced
++)
12878 base_string
= temp_string
;
12879 if (*temp_string
== ')')
12880 --parens_not_balanced
;
12884 temp_string
= base_string
;
12886 /* Skip past '(' and whitespace. */
12887 gas_assert (*base_string
== '(');
12889 if (is_space_char (*base_string
))
12892 if (*base_string
== ','
12893 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12896 displacement_string_end
= temp_string
;
12898 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12902 if (i
.base_reg
== &bad_reg
)
12904 base_string
= end_op
;
12905 if (is_space_char (*base_string
))
12909 /* There may be an index reg or scale factor here. */
12910 if (*base_string
== ',')
12913 if (is_space_char (*base_string
))
12916 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12919 if (i
.index_reg
== &bad_reg
)
12921 base_string
= end_op
;
12922 if (is_space_char (*base_string
))
12924 if (*base_string
== ',')
12927 if (is_space_char (*base_string
))
12930 else if (*base_string
!= ')')
12932 as_bad (_("expecting `,' or `)' "
12933 "after index register in `%s'"),
12938 else if (*base_string
== REGISTER_PREFIX
)
12940 end_op
= strchr (base_string
, ',');
12943 as_bad (_("bad register name `%s'"), base_string
);
12947 /* Check for scale factor. */
12948 if (*base_string
!= ')')
12950 char *end_scale
= i386_scale (base_string
);
12955 base_string
= end_scale
;
12956 if (is_space_char (*base_string
))
12958 if (*base_string
!= ')')
12960 as_bad (_("expecting `)' "
12961 "after scale factor in `%s'"),
12966 else if (!i
.index_reg
)
12968 as_bad (_("expecting index register or scale factor "
12969 "after `,'; got '%c'"),
12974 else if (*base_string
!= ')')
12976 as_bad (_("expecting `,' or `)' "
12977 "after base register in `%s'"),
12982 else if (*base_string
== REGISTER_PREFIX
)
12984 end_op
= strchr (base_string
, ',');
12987 as_bad (_("bad register name `%s'"), base_string
);
12992 /* If there's an expression beginning the operand, parse it,
12993 assuming displacement_string_start and
12994 displacement_string_end are meaningful. */
12995 if (displacement_string_start
!= displacement_string_end
)
12997 if (!i386_displacement (displacement_string_start
,
12998 displacement_string_end
))
13002 /* Special case for (%dx) while doing input/output op. */
13004 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
13005 && i
.base_reg
->reg_type
.bitfield
.word
13006 && i
.index_reg
== 0
13007 && i
.log2_scale_factor
== 0
13008 && i
.seg
[i
.mem_operands
] == 0
13009 && !operand_type_check (i
.types
[this_operand
], disp
))
13011 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
13012 i
.input_output_operand
= true;
13016 if (i386_index_check (operand_string
) == 0)
13018 i
.flags
[this_operand
] |= Operand_Mem
;
13023 /* It's not a memory operand; argh! */
13024 as_bad (_("invalid char %s beginning operand %d `%s'"),
13025 output_invalid (*op_string
),
13030 return 1; /* Normal return. */
13033 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13034 that an rs_machine_dependent frag may reach. */
13037 i386_frag_max_var (fragS
*frag
)
13039 /* The only relaxable frags are for jumps.
13040 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13041 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13042 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13047 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13049 /* STT_GNU_IFUNC symbol must go through PLT. */
13050 if ((symbol_get_bfdsym (fr_symbol
)->flags
13051 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13054 if (!S_IS_EXTERNAL (fr_symbol
))
13055 /* Symbol may be weak or local. */
13056 return !S_IS_WEAK (fr_symbol
);
13058 /* Global symbols with non-default visibility can't be preempted. */
13059 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13062 if (fr_var
!= NO_RELOC
)
13063 switch ((enum bfd_reloc_code_real
) fr_var
)
13065 case BFD_RELOC_386_PLT32
:
13066 case BFD_RELOC_X86_64_PLT32
:
13067 /* Symbol with PLT relocation may be preempted. */
13073 /* Global symbols with default visibility in a shared library may be
13074 preempted by another definition. */
13079 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13080 Note also work for Skylake and Cascadelake.
13081 ---------------------------------------------------------------------
13082 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13083 | ------ | ----------- | ------- | -------- |
13085 | Jno | N | N | Y |
13086 | Jc/Jb | Y | N | Y |
13087 | Jae/Jnb | Y | N | Y |
13088 | Je/Jz | Y | Y | Y |
13089 | Jne/Jnz | Y | Y | Y |
13090 | Jna/Jbe | Y | N | Y |
13091 | Ja/Jnbe | Y | N | Y |
13093 | Jns | N | N | Y |
13094 | Jp/Jpe | N | N | Y |
13095 | Jnp/Jpo | N | N | Y |
13096 | Jl/Jnge | Y | Y | Y |
13097 | Jge/Jnl | Y | Y | Y |
13098 | Jle/Jng | Y | Y | Y |
13099 | Jg/Jnle | Y | Y | Y |
13100 --------------------------------------------------------------------- */
13102 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13104 if (mf_cmp
== mf_cmp_alu_cmp
)
13105 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13106 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13107 if (mf_cmp
== mf_cmp_incdec
)
13108 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13109 || mf_jcc
== mf_jcc_jle
);
13110 if (mf_cmp
== mf_cmp_test_and
)
13115 /* Return the next non-empty frag. */
13118 i386_next_non_empty_frag (fragS
*fragP
)
13120 /* There may be a frag with a ".fill 0" when there is no room in
13121 the current frag for frag_grow in output_insn. */
13122 for (fragP
= fragP
->fr_next
;
13124 && fragP
->fr_type
== rs_fill
13125 && fragP
->fr_fix
== 0);
13126 fragP
= fragP
->fr_next
)
13131 /* Return the next jcc frag after BRANCH_PADDING. */
13134 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13136 fragS
*branch_fragP
;
13140 if (pad_fragP
->fr_type
== rs_machine_dependent
13141 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13142 == BRANCH_PADDING
))
13144 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13145 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13147 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13148 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13149 pad_fragP
->tc_frag_data
.mf_type
))
13150 return branch_fragP
;
13156 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13159 i386_classify_machine_dependent_frag (fragS
*fragP
)
13163 fragS
*branch_fragP
;
13165 unsigned int max_prefix_length
;
13167 if (fragP
->tc_frag_data
.classified
)
13170 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13171 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13172 for (next_fragP
= fragP
;
13173 next_fragP
!= NULL
;
13174 next_fragP
= next_fragP
->fr_next
)
13176 next_fragP
->tc_frag_data
.classified
= 1;
13177 if (next_fragP
->fr_type
== rs_machine_dependent
)
13178 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13180 case BRANCH_PADDING
:
13181 /* The BRANCH_PADDING frag must be followed by a branch
13183 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13184 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13186 case FUSED_JCC_PADDING
:
13187 /* Check if this is a fused jcc:
13189 CMP like instruction
13193 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13194 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13195 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13198 /* The BRANCH_PADDING frag is merged with the
13199 FUSED_JCC_PADDING frag. */
13200 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13201 /* CMP like instruction size. */
13202 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13203 frag_wane (pad_fragP
);
13204 /* Skip to branch_fragP. */
13205 next_fragP
= branch_fragP
;
13207 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13209 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13211 next_fragP
->fr_subtype
13212 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13213 next_fragP
->tc_frag_data
.max_bytes
13214 = next_fragP
->tc_frag_data
.max_prefix_length
;
13215 /* This will be updated in the BRANCH_PREFIX scan. */
13216 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13219 frag_wane (next_fragP
);
13224 /* Stop if there is no BRANCH_PREFIX. */
13225 if (!align_branch_prefix_size
)
13228 /* Scan for BRANCH_PREFIX. */
13229 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13231 if (fragP
->fr_type
!= rs_machine_dependent
13232 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13236 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13237 COND_JUMP_PREFIX. */
13238 max_prefix_length
= 0;
13239 for (next_fragP
= fragP
;
13240 next_fragP
!= NULL
;
13241 next_fragP
= next_fragP
->fr_next
)
13243 if (next_fragP
->fr_type
== rs_fill
)
13244 /* Skip rs_fill frags. */
13246 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13247 /* Stop for all other frags. */
13250 /* rs_machine_dependent frags. */
13251 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13254 /* Count BRANCH_PREFIX frags. */
13255 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13257 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13258 frag_wane (next_fragP
);
13262 += next_fragP
->tc_frag_data
.max_bytes
;
13264 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13266 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13267 == FUSED_JCC_PADDING
))
13269 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13270 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13274 /* Stop for other rs_machine_dependent frags. */
13278 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13280 /* Skip to the next frag. */
13281 fragP
= next_fragP
;
13285 /* Compute padding size for
13288 CMP like instruction
13290 COND_JUMP/UNCOND_JUMP
13295 COND_JUMP/UNCOND_JUMP
13299 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13301 unsigned int offset
, size
, padding_size
;
13302 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13304 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13306 address
= fragP
->fr_address
;
13307 address
+= fragP
->fr_fix
;
13309 /* CMP like instrunction size. */
13310 size
= fragP
->tc_frag_data
.cmp_size
;
13312 /* The base size of the branch frag. */
13313 size
+= branch_fragP
->fr_fix
;
13315 /* Add opcode and displacement bytes for the rs_machine_dependent
13317 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13318 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13320 /* Check if branch is within boundary and doesn't end at the last
13322 offset
= address
& ((1U << align_branch_power
) - 1);
13323 if ((offset
+ size
) >= (1U << align_branch_power
))
13324 /* Padding needed to avoid crossing boundary. */
13325 padding_size
= (1U << align_branch_power
) - offset
;
13327 /* No padding needed. */
13330 /* The return value may be saved in tc_frag_data.length which is
13332 if (!fits_in_unsigned_byte (padding_size
))
13335 return padding_size
;
13338 /* i386_generic_table_relax_frag()
13340 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13341 grow/shrink padding to align branch frags. Hand others to
13345 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13347 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13348 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13350 long padding_size
= i386_branch_padding_size (fragP
, 0);
13351 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13353 /* When the BRANCH_PREFIX frag is used, the computed address
13354 must match the actual address and there should be no padding. */
13355 if (fragP
->tc_frag_data
.padding_address
13356 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13360 /* Update the padding size. */
13362 fragP
->tc_frag_data
.length
= padding_size
;
13366 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13368 fragS
*padding_fragP
, *next_fragP
;
13369 long padding_size
, left_size
, last_size
;
13371 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13372 if (!padding_fragP
)
13373 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13374 return (fragP
->tc_frag_data
.length
13375 - fragP
->tc_frag_data
.last_length
);
13377 /* Compute the relative address of the padding frag in the very
13378 first time where the BRANCH_PREFIX frag sizes are zero. */
13379 if (!fragP
->tc_frag_data
.padding_address
)
13380 fragP
->tc_frag_data
.padding_address
13381 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13383 /* First update the last length from the previous interation. */
13384 left_size
= fragP
->tc_frag_data
.prefix_length
;
13385 for (next_fragP
= fragP
;
13386 next_fragP
!= padding_fragP
;
13387 next_fragP
= next_fragP
->fr_next
)
13388 if (next_fragP
->fr_type
== rs_machine_dependent
13389 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13394 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13398 if (max
> left_size
)
13403 next_fragP
->tc_frag_data
.last_length
= size
;
13407 next_fragP
->tc_frag_data
.last_length
= 0;
13410 /* Check the padding size for the padding frag. */
13411 padding_size
= i386_branch_padding_size
13412 (padding_fragP
, (fragP
->fr_address
13413 + fragP
->tc_frag_data
.padding_address
));
13415 last_size
= fragP
->tc_frag_data
.prefix_length
;
13416 /* Check if there is change from the last interation. */
13417 if (padding_size
== last_size
)
13419 /* Update the expected address of the padding frag. */
13420 padding_fragP
->tc_frag_data
.padding_address
13421 = (fragP
->fr_address
+ padding_size
13422 + fragP
->tc_frag_data
.padding_address
);
13426 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13428 /* No padding if there is no sufficient room. Clear the
13429 expected address of the padding frag. */
13430 padding_fragP
->tc_frag_data
.padding_address
= 0;
13434 /* Store the expected address of the padding frag. */
13435 padding_fragP
->tc_frag_data
.padding_address
13436 = (fragP
->fr_address
+ padding_size
13437 + fragP
->tc_frag_data
.padding_address
);
13439 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13441 /* Update the length for the current interation. */
13442 left_size
= padding_size
;
13443 for (next_fragP
= fragP
;
13444 next_fragP
!= padding_fragP
;
13445 next_fragP
= next_fragP
->fr_next
)
13446 if (next_fragP
->fr_type
== rs_machine_dependent
13447 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13452 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13456 if (max
> left_size
)
13461 next_fragP
->tc_frag_data
.length
= size
;
13465 next_fragP
->tc_frag_data
.length
= 0;
13468 return (fragP
->tc_frag_data
.length
13469 - fragP
->tc_frag_data
.last_length
);
13471 return relax_frag (segment
, fragP
, stretch
);
13474 /* md_estimate_size_before_relax()
13476 Called just before relax() for rs_machine_dependent frags. The x86
13477 assembler uses these frags to handle variable size jump
13480 Any symbol that is now undefined will not become defined.
13481 Return the correct fr_subtype in the frag.
13482 Return the initial "guess for variable size of frag" to caller.
13483 The guess is actually the growth beyond the fixed part. Whatever
13484 we do to grow the fixed or variable part contributes to our
13488 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13490 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13491 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13492 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13494 i386_classify_machine_dependent_frag (fragP
);
13495 return fragP
->tc_frag_data
.length
;
13498 /* We've already got fragP->fr_subtype right; all we have to do is
13499 check for un-relaxable symbols. On an ELF system, we can't relax
13500 an externally visible symbol, because it may be overridden by a
13502 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13505 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13508 #if defined (OBJ_COFF) && defined (TE_PE)
13509 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13510 && S_IS_WEAK (fragP
->fr_symbol
))
13514 /* Symbol is undefined in this segment, or we need to keep a
13515 reloc so that weak symbols can be overridden. */
13516 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13517 enum bfd_reloc_code_real reloc_type
;
13518 unsigned char *opcode
;
13522 if (fragP
->fr_var
!= NO_RELOC
)
13523 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13524 else if (size
== 2)
13525 reloc_type
= BFD_RELOC_16_PCREL
;
13526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13527 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13528 && need_plt32_p (fragP
->fr_symbol
))
13529 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13532 reloc_type
= BFD_RELOC_32_PCREL
;
13534 old_fr_fix
= fragP
->fr_fix
;
13535 opcode
= (unsigned char *) fragP
->fr_opcode
;
13537 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13540 /* Make jmp (0xeb) a (d)word displacement jump. */
13542 fragP
->fr_fix
+= size
;
13543 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13545 fragP
->fr_offset
, 1,
13551 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13553 /* Negate the condition, and branch past an
13554 unconditional jump. */
13557 /* Insert an unconditional jump. */
13559 /* We added two extra opcode bytes, and have a two byte
13561 fragP
->fr_fix
+= 2 + 2;
13562 fix_new (fragP
, old_fr_fix
+ 2, 2,
13564 fragP
->fr_offset
, 1,
13568 /* Fall through. */
13571 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13573 fragP
->fr_fix
+= 1;
13574 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13576 fragP
->fr_offset
, 1,
13577 BFD_RELOC_8_PCREL
);
13578 fixP
->fx_signed
= 1;
13582 /* This changes the byte-displacement jump 0x7N
13583 to the (d)word-displacement jump 0x0f,0x8N. */
13584 opcode
[1] = opcode
[0] + 0x10;
13585 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13586 /* We've added an opcode byte. */
13587 fragP
->fr_fix
+= 1 + size
;
13588 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13590 fragP
->fr_offset
, 1,
13595 BAD_CASE (fragP
->fr_subtype
);
13599 /* All jumps handled here are signed, but don't unconditionally use a
13600 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13601 around at 4G (outside of 64-bit mode) and 64k. */
13602 if (size
== 4 && flag_code
== CODE_64BIT
)
13603 fixP
->fx_signed
= 1;
13606 return fragP
->fr_fix
- old_fr_fix
;
13609 /* Guess size depending on current relax state. Initially the relax
13610 state will correspond to a short jump and we return 1, because
13611 the variable part of the frag (the branch offset) is one byte
13612 long. However, we can relax a section more than once and in that
13613 case we must either set fr_subtype back to the unrelaxed state,
13614 or return the value for the appropriate branch. */
13615 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13618 /* Called after relax() is finished.
13620 In: Address of frag.
13621 fr_type == rs_machine_dependent.
13622 fr_subtype is what the address relaxed to.
13624 Out: Any fixSs and constants are set up.
13625 Caller will turn frag into a ".space 0". */
13628 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13631 unsigned char *opcode
;
13632 unsigned char *where_to_put_displacement
= NULL
;
13633 offsetT target_address
;
13634 offsetT opcode_address
;
13635 unsigned int extension
= 0;
13636 offsetT displacement_from_opcode_start
;
13638 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13639 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13640 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13642 /* Generate nop padding. */
13643 unsigned int size
= fragP
->tc_frag_data
.length
;
13646 if (size
> fragP
->tc_frag_data
.max_bytes
)
13652 const char *branch
= "branch";
13653 const char *prefix
= "";
13654 fragS
*padding_fragP
;
13655 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13658 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13659 switch (fragP
->tc_frag_data
.default_prefix
)
13664 case CS_PREFIX_OPCODE
:
13667 case DS_PREFIX_OPCODE
:
13670 case ES_PREFIX_OPCODE
:
13673 case FS_PREFIX_OPCODE
:
13676 case GS_PREFIX_OPCODE
:
13679 case SS_PREFIX_OPCODE
:
13684 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13685 "%s within %d-byte boundary\n");
13687 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13688 "align %s within %d-byte boundary\n");
13692 padding_fragP
= fragP
;
13693 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13694 "%s within %d-byte boundary\n");
13698 switch (padding_fragP
->tc_frag_data
.branch_type
)
13700 case align_branch_jcc
:
13703 case align_branch_fused
:
13704 branch
= "fused jcc";
13706 case align_branch_jmp
:
13709 case align_branch_call
:
13712 case align_branch_indirect
:
13713 branch
= "indiret branch";
13715 case align_branch_ret
:
13722 fprintf (stdout
, msg
,
13723 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13724 (long long) fragP
->fr_address
, branch
,
13725 1 << align_branch_power
);
13727 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13728 memset (fragP
->fr_opcode
,
13729 fragP
->tc_frag_data
.default_prefix
, size
);
13731 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13733 fragP
->fr_fix
+= size
;
13738 opcode
= (unsigned char *) fragP
->fr_opcode
;
13740 /* Address we want to reach in file space. */
13741 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13743 /* Address opcode resides at in file space. */
13744 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13746 /* Displacement from opcode start to fill into instruction. */
13747 displacement_from_opcode_start
= target_address
- opcode_address
;
13749 if ((fragP
->fr_subtype
& BIG
) == 0)
13751 /* Don't have to change opcode. */
13752 extension
= 1; /* 1 opcode + 1 displacement */
13753 where_to_put_displacement
= &opcode
[1];
13757 if (no_cond_jump_promotion
13758 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13759 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13760 _("long jump required"));
13762 switch (fragP
->fr_subtype
)
13764 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13765 extension
= 4; /* 1 opcode + 4 displacement */
13767 where_to_put_displacement
= &opcode
[1];
13770 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13771 extension
= 2; /* 1 opcode + 2 displacement */
13773 where_to_put_displacement
= &opcode
[1];
13776 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13777 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13778 extension
= 5; /* 2 opcode + 4 displacement */
13779 opcode
[1] = opcode
[0] + 0x10;
13780 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13781 where_to_put_displacement
= &opcode
[2];
13784 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13785 extension
= 3; /* 2 opcode + 2 displacement */
13786 opcode
[1] = opcode
[0] + 0x10;
13787 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13788 where_to_put_displacement
= &opcode
[2];
13791 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13796 where_to_put_displacement
= &opcode
[3];
13800 BAD_CASE (fragP
->fr_subtype
);
13805 /* If size if less then four we are sure that the operand fits,
13806 but if it's 4, then it could be that the displacement is larger
13808 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13810 && ((addressT
) (displacement_from_opcode_start
- extension
13811 + ((addressT
) 1 << 31))
13812 > (((addressT
) 2 << 31) - 1)))
13814 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13815 _("jump target out of range"));
13816 /* Make us emit 0. */
13817 displacement_from_opcode_start
= extension
;
13819 /* Now put displacement after opcode. */
13820 md_number_to_chars ((char *) where_to_put_displacement
,
13821 (valueT
) (displacement_from_opcode_start
- extension
),
13822 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13823 fragP
->fr_fix
+= extension
;
13826 /* Apply a fixup (fixP) to segment data, once it has been determined
13827 by our caller that we have all the info we need to fix it up.
13829 Parameter valP is the pointer to the value of the bits.
13831 On the 386, immediates, displacements, and data pointers are all in
13832 the same (little-endian) format, so we don't need to care about which
13833 we are handling. */
13836 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13838 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13839 valueT value
= *valP
;
13841 #if !defined (TE_Mach)
13842 if (fixP
->fx_pcrel
)
13844 switch (fixP
->fx_r_type
)
13850 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13853 case BFD_RELOC_X86_64_32S
:
13854 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13857 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13860 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13865 if (fixP
->fx_addsy
!= NULL
13866 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13867 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13868 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13869 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13870 && !use_rela_relocations
)
13872 /* This is a hack. There should be a better way to handle this.
13873 This covers for the fact that bfd_install_relocation will
13874 subtract the current location (for partial_inplace, PC relative
13875 relocations); see more below. */
13879 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13882 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13887 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13889 if ((sym_seg
== seg
13890 || (symbol_section_p (fixP
->fx_addsy
)
13891 && sym_seg
!= absolute_section
))
13892 && !generic_force_reloc (fixP
))
13894 /* Yes, we add the values in twice. This is because
13895 bfd_install_relocation subtracts them out again. I think
13896 bfd_install_relocation is broken, but I don't dare change
13898 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13902 #if defined (OBJ_COFF) && defined (TE_PE)
13903 /* For some reason, the PE format does not store a
13904 section address offset for a PC relative symbol. */
13905 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13906 || S_IS_WEAK (fixP
->fx_addsy
))
13907 value
+= md_pcrel_from (fixP
);
13910 #if defined (OBJ_COFF) && defined (TE_PE)
13911 if (fixP
->fx_addsy
!= NULL
13912 && S_IS_WEAK (fixP
->fx_addsy
)
13913 /* PR 16858: Do not modify weak function references. */
13914 && ! fixP
->fx_pcrel
)
13916 #if !defined (TE_PEP)
13917 /* For x86 PE weak function symbols are neither PC-relative
13918 nor do they set S_IS_FUNCTION. So the only reliable way
13919 to detect them is to check the flags of their containing
13921 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13922 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13926 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13930 /* Fix a few things - the dynamic linker expects certain values here,
13931 and we must not disappoint it. */
13932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13933 if (IS_ELF
&& fixP
->fx_addsy
)
13934 switch (fixP
->fx_r_type
)
13936 case BFD_RELOC_386_PLT32
:
13937 case BFD_RELOC_X86_64_PLT32
:
13938 /* Make the jump instruction point to the address of the operand.
13939 At runtime we merely add the offset to the actual PLT entry.
13940 NB: Subtract the offset size only for jump instructions. */
13941 if (fixP
->fx_pcrel
)
13945 case BFD_RELOC_386_TLS_GD
:
13946 case BFD_RELOC_386_TLS_LDM
:
13947 case BFD_RELOC_386_TLS_IE_32
:
13948 case BFD_RELOC_386_TLS_IE
:
13949 case BFD_RELOC_386_TLS_GOTIE
:
13950 case BFD_RELOC_386_TLS_GOTDESC
:
13951 case BFD_RELOC_X86_64_TLSGD
:
13952 case BFD_RELOC_X86_64_TLSLD
:
13953 case BFD_RELOC_X86_64_GOTTPOFF
:
13954 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13955 value
= 0; /* Fully resolved at runtime. No addend. */
13957 case BFD_RELOC_386_TLS_LE
:
13958 case BFD_RELOC_386_TLS_LDO_32
:
13959 case BFD_RELOC_386_TLS_LE_32
:
13960 case BFD_RELOC_X86_64_DTPOFF32
:
13961 case BFD_RELOC_X86_64_DTPOFF64
:
13962 case BFD_RELOC_X86_64_TPOFF32
:
13963 case BFD_RELOC_X86_64_TPOFF64
:
13964 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13967 case BFD_RELOC_386_TLS_DESC_CALL
:
13968 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13969 value
= 0; /* Fully resolved at runtime. No addend. */
13970 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13974 case BFD_RELOC_VTABLE_INHERIT
:
13975 case BFD_RELOC_VTABLE_ENTRY
:
13982 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13984 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13986 value
= extend_to_32bit_address (value
);
13989 #endif /* !defined (TE_Mach) */
13991 /* Are we finished with this relocation now? */
13992 if (fixP
->fx_addsy
== NULL
)
13995 switch (fixP
->fx_r_type
)
13997 case BFD_RELOC_X86_64_32S
:
13998 fixP
->fx_signed
= 1;
14005 #if defined (OBJ_COFF) && defined (TE_PE)
14006 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
14009 /* Remember value for tc_gen_reloc. */
14010 fixP
->fx_addnumber
= value
;
14011 /* Clear out the frag for now. */
14015 else if (use_rela_relocations
)
14017 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14018 fixP
->fx_no_overflow
= 1;
14019 /* Remember value for tc_gen_reloc. */
14020 fixP
->fx_addnumber
= value
;
14024 md_number_to_chars (p
, value
, fixP
->fx_size
);
14028 md_atof (int type
, char *litP
, int *sizeP
)
14030 /* This outputs the LITTLENUMs in REVERSE order;
14031 in accord with the bigendian 386. */
14032 return ieee_md_atof (type
, litP
, sizeP
, false);
14035 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14038 output_invalid (int c
)
14041 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14044 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14045 "(0x%x)", (unsigned char) c
);
14046 return output_invalid_buf
;
14049 /* Verify that @r can be used in the current context. */
14051 static bool check_register (const reg_entry
*r
)
14053 if (allow_pseudo_reg
)
14056 if (operand_type_all_zero (&r
->reg_type
))
14059 if ((r
->reg_type
.bitfield
.dword
14060 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14061 || r
->reg_type
.bitfield
.class == RegCR
14062 || r
->reg_type
.bitfield
.class == RegDR
)
14063 && !cpu_arch_flags
.bitfield
.cpui386
)
14066 if (r
->reg_type
.bitfield
.class == RegTR
14067 && (flag_code
== CODE_64BIT
14068 || !cpu_arch_flags
.bitfield
.cpui386
14069 || cpu_arch_isa_flags
.bitfield
.cpui586
14070 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14073 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14076 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14078 if (r
->reg_type
.bitfield
.zmmword
14079 || r
->reg_type
.bitfield
.class == RegMask
)
14082 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14084 if (r
->reg_type
.bitfield
.ymmword
)
14087 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14092 if (r
->reg_type
.bitfield
.zmmword
)
14094 if (vector_size
< VSZ512
)
14097 if (i
.vec_encoding
== vex_encoding_default
)
14098 i
.vec_encoding
= vex_encoding_evex512
;
14099 else if (i
.vec_encoding
!= vex_encoding_evex
14100 && i
.vec_encoding
!= vex_encoding_evex512
)
14101 i
.vec_encoding
= vex_encoding_error
;
14104 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14107 if (r
->reg_type
.bitfield
.tmmword
14108 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14109 || flag_code
!= CODE_64BIT
))
14112 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14115 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14116 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14119 /* Upper 16 vector registers are only available with VREX in 64bit
14120 mode, and require EVEX encoding. */
14121 if (r
->reg_flags
& RegVRex
)
14123 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14124 || flag_code
!= CODE_64BIT
)
14127 if (i
.vec_encoding
== vex_encoding_default
14128 || i
.vec_encoding
== vex_encoding_evex512
)
14129 i
.vec_encoding
= vex_encoding_evex
;
14130 else if (i
.vec_encoding
!= vex_encoding_evex
)
14131 i
.vec_encoding
= vex_encoding_error
;
14134 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14135 && (!cpu_arch_flags
.bitfield
.cpu64
14136 || r
->reg_type
.bitfield
.class != RegCR
14138 && flag_code
!= CODE_64BIT
)
14141 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14148 /* REG_STRING starts *before* REGISTER_PREFIX. */
14150 static const reg_entry
*
14151 parse_real_register (const char *reg_string
, char **end_op
)
14153 const char *s
= reg_string
;
14155 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14156 const reg_entry
*r
;
14158 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14159 if (*s
== REGISTER_PREFIX
)
14162 if (is_space_char (*s
))
14165 p
= reg_name_given
;
14166 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14168 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14169 return (const reg_entry
*) NULL
;
14173 if (is_part_of_name (*s
))
14174 return (const reg_entry
*) NULL
;
14176 *end_op
= (char *) s
;
14178 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14180 /* Handle floating point regs, allowing spaces in the (i) part. */
14183 if (!cpu_arch_flags
.bitfield
.cpu8087
14184 && !cpu_arch_flags
.bitfield
.cpu287
14185 && !cpu_arch_flags
.bitfield
.cpu387
14186 && !allow_pseudo_reg
)
14187 return (const reg_entry
*) NULL
;
14189 if (is_space_char (*s
))
14194 if (is_space_char (*s
))
14196 if (*s
>= '0' && *s
<= '7')
14198 int fpr
= *s
- '0';
14200 if (is_space_char (*s
))
14204 *end_op
= (char *) s
+ 1;
14205 know (r
[fpr
].reg_num
== fpr
);
14209 /* We have "%st(" then garbage. */
14210 return (const reg_entry
*) NULL
;
14214 return r
&& check_register (r
) ? r
: NULL
;
14217 /* REG_STRING starts *before* REGISTER_PREFIX. */
14219 static const reg_entry
*
14220 parse_register (const char *reg_string
, char **end_op
)
14222 const reg_entry
*r
;
14224 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14225 r
= parse_real_register (reg_string
, end_op
);
14230 char *save
= input_line_pointer
;
14231 char *buf
= xstrdup (reg_string
), *name
;
14234 input_line_pointer
= buf
;
14235 get_symbol_name (&name
);
14236 symbolP
= symbol_find (name
);
14237 while (symbolP
&& symbol_equated_p (symbolP
))
14239 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14241 if (e
->X_add_number
)
14243 symbolP
= e
->X_add_symbol
;
14245 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14247 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14249 if (e
->X_op
== O_register
)
14251 know (e
->X_add_number
>= 0
14252 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14253 r
= i386_regtab
+ e
->X_add_number
;
14254 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14256 if (r
&& !check_register (r
))
14258 as_bad (_("register '%s%s' cannot be used here"),
14259 register_prefix
, r
->reg_name
);
14263 input_line_pointer
= save
;
14270 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14272 const reg_entry
*r
= NULL
;
14273 char *end
= input_line_pointer
;
14275 /* We only know the terminating character here. It being double quote could
14276 be the closing one of a quoted symbol name, or an opening one from a
14277 following string (or another quoted symbol name). Since the latter can't
14278 be valid syntax for anything, bailing in either case is good enough. */
14279 if (*nextcharP
== '"')
14283 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14284 r
= parse_real_register (name
, &input_line_pointer
);
14285 if (r
&& end
<= input_line_pointer
)
14287 *nextcharP
= *input_line_pointer
;
14288 *input_line_pointer
= 0;
14289 e
->X_op
= O_register
;
14290 e
->X_add_number
= r
- i386_regtab
;
14293 input_line_pointer
= end
;
14295 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14299 md_operand (expressionS
*e
)
14302 const reg_entry
*r
;
14304 switch (*input_line_pointer
)
14306 case REGISTER_PREFIX
:
14307 r
= parse_real_register (input_line_pointer
, &end
);
14310 e
->X_op
= O_register
;
14311 e
->X_add_number
= r
- i386_regtab
;
14312 input_line_pointer
= end
;
14317 gas_assert (intel_syntax
);
14318 end
= input_line_pointer
++;
14320 if (*input_line_pointer
== ']')
14322 ++input_line_pointer
;
14323 e
->X_op_symbol
= make_expr_symbol (e
);
14324 e
->X_add_symbol
= NULL
;
14325 e
->X_add_number
= 0;
14330 e
->X_op
= O_absent
;
14331 input_line_pointer
= end
;
14338 /* To maintain consistency with !BFD64 builds of gas record, whether any
14339 (binary) operator was involved in an expression. As expressions are
14340 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14341 truncate results. */
14342 bool i386_record_operator (operatorT op
,
14343 const expressionS
*left
,
14344 const expressionS
*right
)
14346 if (op
== O_absent
)
14351 /* Since the expression parser applies unary operators fine to bignum
14352 operands, we don't need to be concerned of respective operands not
14353 fitting in 32 bits. */
14354 if (right
->X_op
== O_constant
&& right
->X_unsigned
14355 && !fits_in_unsigned_long (right
->X_add_number
))
14358 /* This isn't entirely right: The pattern can also result when constant
14359 expressions are folded (e.g. 0xffffffff + 1). */
14360 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14361 && !fits_in_unsigned_long (left
->X_add_number
))
14362 || (right
->X_op
== O_constant
&& right
->X_unsigned
14363 && !fits_in_unsigned_long (right
->X_add_number
)))
14364 expr_mode
= expr_large_value
;
14366 if (expr_mode
!= expr_large_value
)
14367 expr_mode
= expr_operator_present
;
14373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14374 const char *md_shortopts
= "kVQ:sqnO::";
14376 const char *md_shortopts
= "qnO::";
14379 #define OPTION_32 (OPTION_MD_BASE + 0)
14380 #define OPTION_64 (OPTION_MD_BASE + 1)
14381 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14382 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14383 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14384 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14385 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14386 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14387 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14388 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14389 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14390 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14391 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14392 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14393 #define OPTION_X32 (OPTION_MD_BASE + 14)
14394 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14395 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14396 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14397 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14398 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14399 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14400 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14401 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14402 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14403 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14404 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14405 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14406 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14407 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14408 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14409 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14410 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14411 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14412 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14413 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14415 struct option md_longopts
[] =
14417 {"32", no_argument
, NULL
, OPTION_32
},
14418 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14419 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14420 {"64", no_argument
, NULL
, OPTION_64
},
14422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14423 {"x32", no_argument
, NULL
, OPTION_X32
},
14424 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14425 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14427 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14428 {"march", required_argument
, NULL
, OPTION_MARCH
},
14429 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14430 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14431 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14432 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14433 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14434 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14435 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14436 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14437 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14438 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14439 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14440 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14441 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14442 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14443 # if defined (TE_PE) || defined (TE_PEP)
14444 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14446 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14447 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14448 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14449 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14450 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14451 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14452 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14453 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14454 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14455 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14456 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14457 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14458 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14459 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14460 {NULL
, no_argument
, NULL
, 0}
14462 size_t md_longopts_size
= sizeof (md_longopts
);
14465 md_parse_option (int c
, const char *arg
)
14468 char *arch
, *next
, *saved
, *type
;
14473 optimize_align_code
= 0;
14477 quiet_warnings
= 1;
14480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14481 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14482 should be emitted or not. FIXME: Not implemented. */
14484 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14488 /* -V: SVR4 argument to print version ID. */
14490 print_version_id ();
14493 /* -k: Ignore for FreeBSD compatibility. */
14498 /* -s: On i386 Solaris, this tells the native assembler to use
14499 .stab instead of .stab.excl. We always use .stab anyhow. */
14502 case OPTION_MSHARED
:
14506 case OPTION_X86_USED_NOTE
:
14507 if (strcasecmp (arg
, "yes") == 0)
14509 else if (strcasecmp (arg
, "no") == 0)
14512 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14517 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14518 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14521 const char **list
, **l
;
14523 list
= bfd_target_list ();
14524 for (l
= list
; *l
!= NULL
; l
++)
14525 if (startswith (*l
, "elf64-x86-64")
14526 || strcmp (*l
, "coff-x86-64") == 0
14527 || strcmp (*l
, "pe-x86-64") == 0
14528 || strcmp (*l
, "pei-x86-64") == 0
14529 || strcmp (*l
, "mach-o-x86-64") == 0)
14531 default_arch
= "x86_64";
14535 as_fatal (_("no compiled in support for x86_64"));
14541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14545 const char **list
, **l
;
14547 list
= bfd_target_list ();
14548 for (l
= list
; *l
!= NULL
; l
++)
14549 if (startswith (*l
, "elf32-x86-64"))
14551 default_arch
= "x86_64:32";
14555 as_fatal (_("no compiled in support for 32bit x86_64"));
14559 as_fatal (_("32bit x86_64 is only supported for ELF"));
14565 const char **list
, **l
;
14567 list
= bfd_target_list ();
14568 for (l
= list
; *l
!= NULL
; l
++)
14569 if (strstr (*l
, "-i386")
14570 || strstr (*l
, "-go32"))
14572 default_arch
= "i386";
14576 as_fatal (_("no compiled in support for ix86"));
14581 case OPTION_DIVIDE
:
14582 #ifdef SVR4_COMMENT_CHARS
14587 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14589 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14593 i386_comment_chars
= n
;
14599 saved
= xstrdup (arg
);
14601 /* Allow -march=+nosse. */
14609 as_fatal (_("invalid -march= option: `%s'"), arg
);
14610 next
= strchr (arch
, '+');
14613 vsz
= strchr (arch
, '/');
14616 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14618 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14621 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14622 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14625 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14628 cpu_arch_name
= cpu_arch
[j
].name
;
14629 free (cpu_sub_arch_name
);
14630 cpu_sub_arch_name
= NULL
;
14631 cpu_arch_flags
= cpu_arch
[j
].enable
;
14632 cpu_arch_isa
= cpu_arch
[j
].type
;
14633 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14634 if (!cpu_arch_tune_set
)
14635 cpu_arch_tune
= cpu_arch_isa
;
14636 vector_size
= VSZ_DEFAULT
;
14639 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14640 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14641 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14643 /* ISA extension. */
14646 switch (cpu_arch
[j
].vsz
)
14655 unsigned long val
= strtoul (vsz
, &end
, 0);
14661 case 512: vector_size
= VSZ512
; break;
14662 case 256: vector_size
= VSZ256
; break;
14663 case 128: vector_size
= VSZ128
; break;
14665 as_warn (_("Unrecognized vector size specifier ignored"));
14670 /* Fall through. */
14672 vector_size
= VSZ_DEFAULT
;
14680 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14682 /* Disable an ISA extension. */
14683 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14684 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14685 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14688 if (cpu_arch
[j
].vsz
== vsz_set
)
14689 vector_size
= VSZ_DEFAULT
;
14694 if (j
>= ARRAY_SIZE (cpu_arch
))
14695 as_fatal (_("invalid -march= option: `%s'"), arg
);
14699 while (next
!= NULL
);
14705 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14706 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14708 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14709 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14711 cpu_arch_tune_set
= 1;
14712 cpu_arch_tune
= cpu_arch
[j
].type
;
14716 if (j
>= ARRAY_SIZE (cpu_arch
))
14717 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14720 case OPTION_MMNEMONIC
:
14721 if (strcasecmp (arg
, "att") == 0)
14722 intel_mnemonic
= 0;
14723 else if (strcasecmp (arg
, "intel") == 0)
14724 intel_mnemonic
= 1;
14726 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14729 case OPTION_MSYNTAX
:
14730 if (strcasecmp (arg
, "att") == 0)
14732 else if (strcasecmp (arg
, "intel") == 0)
14735 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14738 case OPTION_MINDEX_REG
:
14739 allow_index_reg
= 1;
14742 case OPTION_MNAKED_REG
:
14743 allow_naked_reg
= 1;
14746 case OPTION_MSSE2AVX
:
14750 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14751 use_unaligned_vector_move
= 1;
14754 case OPTION_MSSE_CHECK
:
14755 if (strcasecmp (arg
, "error") == 0)
14756 sse_check
= check_error
;
14757 else if (strcasecmp (arg
, "warning") == 0)
14758 sse_check
= check_warning
;
14759 else if (strcasecmp (arg
, "none") == 0)
14760 sse_check
= check_none
;
14762 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14765 case OPTION_MOPERAND_CHECK
:
14766 if (strcasecmp (arg
, "error") == 0)
14767 operand_check
= check_error
;
14768 else if (strcasecmp (arg
, "warning") == 0)
14769 operand_check
= check_warning
;
14770 else if (strcasecmp (arg
, "none") == 0)
14771 operand_check
= check_none
;
14773 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14776 case OPTION_MAVXSCALAR
:
14777 if (strcasecmp (arg
, "128") == 0)
14778 avxscalar
= vex128
;
14779 else if (strcasecmp (arg
, "256") == 0)
14780 avxscalar
= vex256
;
14782 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14785 case OPTION_MVEXWIG
:
14786 if (strcmp (arg
, "0") == 0)
14788 else if (strcmp (arg
, "1") == 0)
14791 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14794 case OPTION_MADD_BND_PREFIX
:
14795 add_bnd_prefix
= 1;
14798 case OPTION_MEVEXLIG
:
14799 if (strcmp (arg
, "128") == 0)
14800 evexlig
= evexl128
;
14801 else if (strcmp (arg
, "256") == 0)
14802 evexlig
= evexl256
;
14803 else if (strcmp (arg
, "512") == 0)
14804 evexlig
= evexl512
;
14806 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14809 case OPTION_MEVEXRCIG
:
14810 if (strcmp (arg
, "rne") == 0)
14812 else if (strcmp (arg
, "rd") == 0)
14814 else if (strcmp (arg
, "ru") == 0)
14816 else if (strcmp (arg
, "rz") == 0)
14819 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14822 case OPTION_MEVEXWIG
:
14823 if (strcmp (arg
, "0") == 0)
14825 else if (strcmp (arg
, "1") == 0)
14828 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14831 # if defined (TE_PE) || defined (TE_PEP)
14832 case OPTION_MBIG_OBJ
:
14837 case OPTION_MOMIT_LOCK_PREFIX
:
14838 if (strcasecmp (arg
, "yes") == 0)
14839 omit_lock_prefix
= 1;
14840 else if (strcasecmp (arg
, "no") == 0)
14841 omit_lock_prefix
= 0;
14843 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14846 case OPTION_MFENCE_AS_LOCK_ADD
:
14847 if (strcasecmp (arg
, "yes") == 0)
14849 else if (strcasecmp (arg
, "no") == 0)
14852 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14855 case OPTION_MLFENCE_AFTER_LOAD
:
14856 if (strcasecmp (arg
, "yes") == 0)
14857 lfence_after_load
= 1;
14858 else if (strcasecmp (arg
, "no") == 0)
14859 lfence_after_load
= 0;
14861 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14864 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14865 if (strcasecmp (arg
, "all") == 0)
14867 lfence_before_indirect_branch
= lfence_branch_all
;
14868 if (lfence_before_ret
== lfence_before_ret_none
)
14869 lfence_before_ret
= lfence_before_ret_shl
;
14871 else if (strcasecmp (arg
, "memory") == 0)
14872 lfence_before_indirect_branch
= lfence_branch_memory
;
14873 else if (strcasecmp (arg
, "register") == 0)
14874 lfence_before_indirect_branch
= lfence_branch_register
;
14875 else if (strcasecmp (arg
, "none") == 0)
14876 lfence_before_indirect_branch
= lfence_branch_none
;
14878 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14882 case OPTION_MLFENCE_BEFORE_RET
:
14883 if (strcasecmp (arg
, "or") == 0)
14884 lfence_before_ret
= lfence_before_ret_or
;
14885 else if (strcasecmp (arg
, "not") == 0)
14886 lfence_before_ret
= lfence_before_ret_not
;
14887 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14888 lfence_before_ret
= lfence_before_ret_shl
;
14889 else if (strcasecmp (arg
, "none") == 0)
14890 lfence_before_ret
= lfence_before_ret_none
;
14892 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14896 case OPTION_MRELAX_RELOCATIONS
:
14897 if (strcasecmp (arg
, "yes") == 0)
14898 generate_relax_relocations
= 1;
14899 else if (strcasecmp (arg
, "no") == 0)
14900 generate_relax_relocations
= 0;
14902 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14905 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14908 long int align
= strtoul (arg
, &end
, 0);
14913 align_branch_power
= 0;
14916 else if (align
>= 16)
14919 for (align_power
= 0;
14921 align
>>= 1, align_power
++)
14923 /* Limit alignment power to 31. */
14924 if (align
== 1 && align_power
< 32)
14926 align_branch_power
= align_power
;
14931 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14935 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14938 int align
= strtoul (arg
, &end
, 0);
14939 /* Some processors only support 5 prefixes. */
14940 if (*end
== '\0' && align
>= 0 && align
< 6)
14942 align_branch_prefix_size
= align
;
14945 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14950 case OPTION_MALIGN_BRANCH
:
14952 saved
= xstrdup (arg
);
14956 next
= strchr (type
, '+');
14959 if (strcasecmp (type
, "jcc") == 0)
14960 align_branch
|= align_branch_jcc_bit
;
14961 else if (strcasecmp (type
, "fused") == 0)
14962 align_branch
|= align_branch_fused_bit
;
14963 else if (strcasecmp (type
, "jmp") == 0)
14964 align_branch
|= align_branch_jmp_bit
;
14965 else if (strcasecmp (type
, "call") == 0)
14966 align_branch
|= align_branch_call_bit
;
14967 else if (strcasecmp (type
, "ret") == 0)
14968 align_branch
|= align_branch_ret_bit
;
14969 else if (strcasecmp (type
, "indirect") == 0)
14970 align_branch
|= align_branch_indirect_bit
;
14972 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14975 while (next
!= NULL
);
14979 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14980 align_branch_power
= 5;
14981 align_branch_prefix_size
= 5;
14982 align_branch
= (align_branch_jcc_bit
14983 | align_branch_fused_bit
14984 | align_branch_jmp_bit
);
14987 case OPTION_MAMD64
:
14991 case OPTION_MINTEL64
:
14999 /* Turn off -Os. */
15000 optimize_for_space
= 0;
15002 else if (*arg
== 's')
15004 optimize_for_space
= 1;
15005 /* Turn on all encoding optimizations. */
15006 optimize
= INT_MAX
;
15010 optimize
= atoi (arg
);
15011 /* Turn off -Os. */
15012 optimize_for_space
= 0;
15022 #define MESSAGE_TEMPLATE \
15026 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15027 int *left_p
, const char *name
, int len
)
15029 int size
= sizeof (MESSAGE_TEMPLATE
);
15030 int left
= *left_p
;
15032 /* Reserve 2 spaces for ", " or ",\0" */
15035 /* Check if there is any room. */
15043 p
= mempcpy (p
, name
, len
);
15047 /* Output the current message now and start a new one. */
15050 fprintf (stream
, "%s\n", message
);
15052 left
= size
- (start
- message
) - len
- 2;
15054 gas_assert (left
>= 0);
15056 p
= mempcpy (p
, name
, len
);
15064 show_arch (FILE *stream
, int ext
, int check
)
15066 static char message
[] = MESSAGE_TEMPLATE
;
15067 char *start
= message
+ 27;
15069 int size
= sizeof (MESSAGE_TEMPLATE
);
15076 left
= size
- (start
- message
);
15080 p
= output_message (stream
, p
, message
, start
, &left
,
15081 STRING_COMMA_LEN ("default"));
15082 p
= output_message (stream
, p
, message
, start
, &left
,
15083 STRING_COMMA_LEN ("push"));
15084 p
= output_message (stream
, p
, message
, start
, &left
,
15085 STRING_COMMA_LEN ("pop"));
15088 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15090 /* Should it be skipped? */
15091 if (cpu_arch
[j
].skip
)
15094 name
= cpu_arch
[j
].name
;
15095 len
= cpu_arch
[j
].len
;
15096 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15098 /* It is an extension. Skip if we aren't asked to show it. */
15099 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15104 /* It is an processor. Skip if we show only extension. */
15107 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15109 /* It is an impossible processor - skip. */
15113 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15116 /* Display disabled extensions. */
15118 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15122 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15123 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15125 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15126 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15132 fprintf (stream
, "%s\n", message
);
15136 md_show_usage (FILE *stream
)
15138 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15139 fprintf (stream
, _("\
15140 -Qy, -Qn ignored\n\
15141 -V print assembler version number\n\
15144 fprintf (stream
, _("\
15145 -n do not optimize code alignment\n\
15146 -O{012s} attempt some code optimizations\n\
15147 -q quieten some warnings\n"));
15148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15149 fprintf (stream
, _("\
15153 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15154 fprintf (stream
, _("\
15155 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15156 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15157 fprintf (stream
, _("\
15158 --32/--64 generate 32bit/64bit object\n"));
15161 #ifdef SVR4_COMMENT_CHARS
15162 fprintf (stream
, _("\
15163 --divide do not treat `/' as a comment character\n"));
15165 fprintf (stream
, _("\
15166 --divide ignored\n"));
15168 fprintf (stream
, _("\
15169 -march=CPU[,+EXTENSION...]\n\
15170 generate code for CPU and EXTENSION, CPU is one of:\n"));
15171 show_arch (stream
, 0, 1);
15172 fprintf (stream
, _("\
15173 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15174 show_arch (stream
, 1, 0);
15175 fprintf (stream
, _("\
15176 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15177 show_arch (stream
, 0, 0);
15178 fprintf (stream
, _("\
15179 -msse2avx encode SSE instructions with VEX prefix\n"));
15180 fprintf (stream
, _("\
15181 -muse-unaligned-vector-move\n\
15182 encode aligned vector move as unaligned vector move\n"));
15183 fprintf (stream
, _("\
15184 -msse-check=[none|error|warning] (default: warning)\n\
15185 check SSE instructions\n"));
15186 fprintf (stream
, _("\
15187 -moperand-check=[none|error|warning] (default: warning)\n\
15188 check operand combinations for validity\n"));
15189 fprintf (stream
, _("\
15190 -mavxscalar=[128|256] (default: 128)\n\
15191 encode scalar AVX instructions with specific vector\n\
15193 fprintf (stream
, _("\
15194 -mvexwig=[0|1] (default: 0)\n\
15195 encode VEX instructions with specific VEX.W value\n\
15196 for VEX.W bit ignored instructions\n"));
15197 fprintf (stream
, _("\
15198 -mevexlig=[128|256|512] (default: 128)\n\
15199 encode scalar EVEX instructions with specific vector\n\
15201 fprintf (stream
, _("\
15202 -mevexwig=[0|1] (default: 0)\n\
15203 encode EVEX instructions with specific EVEX.W value\n\
15204 for EVEX.W bit ignored instructions\n"));
15205 fprintf (stream
, _("\
15206 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15207 encode EVEX instructions with specific EVEX.RC value\n\
15208 for SAE-only ignored instructions\n"));
15209 fprintf (stream
, _("\
15210 -mmnemonic=[att|intel] "));
15211 if (SYSV386_COMPAT
)
15212 fprintf (stream
, _("(default: att)\n"));
15214 fprintf (stream
, _("(default: intel)\n"));
15215 fprintf (stream
, _("\
15216 use AT&T/Intel mnemonic\n"));
15217 fprintf (stream
, _("\
15218 -msyntax=[att|intel] (default: att)\n\
15219 use AT&T/Intel syntax\n"));
15220 fprintf (stream
, _("\
15221 -mindex-reg support pseudo index registers\n"));
15222 fprintf (stream
, _("\
15223 -mnaked-reg don't require `%%' prefix for registers\n"));
15224 fprintf (stream
, _("\
15225 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15227 fprintf (stream
, _("\
15228 -mshared disable branch optimization for shared code\n"));
15229 fprintf (stream
, _("\
15230 -mx86-used-note=[no|yes] "));
15231 if (DEFAULT_X86_USED_NOTE
)
15232 fprintf (stream
, _("(default: yes)\n"));
15234 fprintf (stream
, _("(default: no)\n"));
15235 fprintf (stream
, _("\
15236 generate x86 used ISA and feature properties\n"));
15238 #if defined (TE_PE) || defined (TE_PEP)
15239 fprintf (stream
, _("\
15240 -mbig-obj generate big object files\n"));
15242 fprintf (stream
, _("\
15243 -momit-lock-prefix=[no|yes] (default: no)\n\
15244 strip all lock prefixes\n"));
15245 fprintf (stream
, _("\
15246 -mfence-as-lock-add=[no|yes] (default: no)\n\
15247 encode lfence, mfence and sfence as\n\
15248 lock addl $0x0, (%%{re}sp)\n"));
15249 fprintf (stream
, _("\
15250 -mrelax-relocations=[no|yes] "));
15251 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15252 fprintf (stream
, _("(default: yes)\n"));
15254 fprintf (stream
, _("(default: no)\n"));
15255 fprintf (stream
, _("\
15256 generate relax relocations\n"));
15257 fprintf (stream
, _("\
15258 -malign-branch-boundary=NUM (default: 0)\n\
15259 align branches within NUM byte boundary\n"));
15260 fprintf (stream
, _("\
15261 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15262 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15264 specify types of branches to align\n"));
15265 fprintf (stream
, _("\
15266 -malign-branch-prefix-size=NUM (default: 5)\n\
15267 align branches with NUM prefixes per instruction\n"));
15268 fprintf (stream
, _("\
15269 -mbranches-within-32B-boundaries\n\
15270 align branches within 32 byte boundary\n"));
15271 fprintf (stream
, _("\
15272 -mlfence-after-load=[no|yes] (default: no)\n\
15273 generate lfence after load\n"));
15274 fprintf (stream
, _("\
15275 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15276 generate lfence before indirect near branch\n"));
15277 fprintf (stream
, _("\
15278 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15279 generate lfence before ret\n"));
15280 fprintf (stream
, _("\
15281 -mamd64 accept only AMD64 ISA [default]\n"));
15282 fprintf (stream
, _("\
15283 -mintel64 accept only Intel64 ISA\n"));
15286 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15287 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15288 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15290 /* Pick the target format to use. */
15293 i386_target_format (void)
15295 if (startswith (default_arch
, "x86_64"))
15297 update_code_flag (CODE_64BIT
, 1);
15298 if (default_arch
[6] == '\0')
15299 x86_elf_abi
= X86_64_ABI
;
15301 x86_elf_abi
= X86_64_X32_ABI
;
15303 else if (!strcmp (default_arch
, "i386"))
15304 update_code_flag (CODE_32BIT
, 1);
15305 else if (!strcmp (default_arch
, "iamcu"))
15307 update_code_flag (CODE_32BIT
, 1);
15308 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15310 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15311 cpu_arch_name
= "iamcu";
15312 free (cpu_sub_arch_name
);
15313 cpu_sub_arch_name
= NULL
;
15314 cpu_arch_flags
= iamcu_flags
;
15315 cpu_arch_isa
= PROCESSOR_IAMCU
;
15316 cpu_arch_isa_flags
= iamcu_flags
;
15317 if (!cpu_arch_tune_set
)
15318 cpu_arch_tune
= PROCESSOR_IAMCU
;
15320 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15321 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15325 as_fatal (_("unknown architecture"));
15327 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15328 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15330 switch (OUTPUT_FLAVOR
)
15332 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15333 case bfd_target_aout_flavour
:
15334 return AOUT_TARGET_FORMAT
;
15336 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15337 # if defined (TE_PE) || defined (TE_PEP)
15338 case bfd_target_coff_flavour
:
15339 if (flag_code
== CODE_64BIT
)
15342 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15344 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15345 # elif defined (TE_GO32)
15346 case bfd_target_coff_flavour
:
15347 return "coff-go32";
15349 case bfd_target_coff_flavour
:
15350 return "coff-i386";
15353 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15354 case bfd_target_elf_flavour
:
15356 const char *format
;
15358 switch (x86_elf_abi
)
15361 format
= ELF_TARGET_FORMAT
;
15363 tls_get_addr
= "___tls_get_addr";
15367 use_rela_relocations
= 1;
15370 tls_get_addr
= "__tls_get_addr";
15372 format
= ELF_TARGET_FORMAT64
;
15374 case X86_64_X32_ABI
:
15375 use_rela_relocations
= 1;
15378 tls_get_addr
= "__tls_get_addr";
15380 disallow_64bit_reloc
= 1;
15381 format
= ELF_TARGET_FORMAT32
;
15384 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15386 if (x86_elf_abi
!= I386_ABI
)
15387 as_fatal (_("Intel MCU is 32bit only"));
15388 return ELF_TARGET_IAMCU_FORMAT
;
15394 #if defined (OBJ_MACH_O)
15395 case bfd_target_mach_o_flavour
:
15396 if (flag_code
== CODE_64BIT
)
15398 use_rela_relocations
= 1;
15400 return "mach-o-x86-64";
15403 return "mach-o-i386";
15411 #endif /* OBJ_MAYBE_ more than one */
15414 md_undefined_symbol (char *name
)
15416 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15417 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15418 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15419 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15423 if (symbol_find (name
))
15424 as_bad (_("GOT already in symbol table"));
15425 GOT_symbol
= symbol_new (name
, undefined_section
,
15426 &zero_address_frag
, 0);
15433 /* Round up a section size to the appropriate boundary. */
15436 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15438 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15439 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15441 /* For a.out, force the section size to be aligned. If we don't do
15442 this, BFD will align it for us, but it will not write out the
15443 final bytes of the section. This may be a bug in BFD, but it is
15444 easier to fix it here since that is how the other a.out targets
15448 align
= bfd_section_alignment (segment
);
15449 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15456 /* On the i386, PC-relative offsets are relative to the start of the
15457 next instruction. That is, the address of the offset, plus its
15458 size, since the offset is always the last part of the insn. */
15461 md_pcrel_from (fixS
*fixP
)
15463 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15469 s_bss (int ignore ATTRIBUTE_UNUSED
)
15473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15475 obj_elf_section_change_hook ();
15477 temp
= get_absolute_expression ();
15478 subseg_set (bss_section
, (subsegT
) temp
);
15479 demand_empty_rest_of_line ();
15484 /* Remember constant directive. */
15487 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15489 if (last_insn
.kind
!= last_insn_directive
15490 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15492 last_insn
.seg
= now_seg
;
15493 last_insn
.kind
= last_insn_directive
;
15494 last_insn
.name
= "constant directive";
15495 last_insn
.file
= as_where (&last_insn
.line
);
15496 if (lfence_before_ret
!= lfence_before_ret_none
)
15498 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15499 as_warn (_("constant directive skips -mlfence-before-ret "
15500 "and -mlfence-before-indirect-branch"));
15502 as_warn (_("constant directive skips -mlfence-before-ret"));
15504 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15505 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15510 i386_validate_fix (fixS
*fixp
)
15512 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15514 reloc_howto_type
*howto
;
15516 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15517 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15518 _("invalid %s relocation against register"),
15519 howto
? howto
->name
: "<unknown>");
15523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15524 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15525 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15526 return IS_ELF
&& fixp
->fx_addsy
15527 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15528 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15531 if (fixp
->fx_subsy
)
15533 if (fixp
->fx_subsy
== GOT_symbol
)
15535 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15540 if (fixp
->fx_tcbit2
)
15541 fixp
->fx_r_type
= (fixp
->fx_tcbit
15542 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15543 : BFD_RELOC_X86_64_GOTPCRELX
);
15546 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15551 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15553 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15555 fixp
->fx_subsy
= 0;
15558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15561 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15562 to section. Since PLT32 relocation must be against symbols,
15563 turn such PLT32 relocation into PC32 relocation. */
15565 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15566 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15567 && symbol_section_p (fixp
->fx_addsy
))
15568 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15571 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15572 && fixp
->fx_tcbit2
)
15573 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15582 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15585 bfd_reloc_code_real_type code
;
15587 switch (fixp
->fx_r_type
)
15589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15592 case BFD_RELOC_SIZE32
:
15593 case BFD_RELOC_SIZE64
:
15595 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15596 && (!fixp
->fx_subsy
15597 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15598 sym
= fixp
->fx_addsy
;
15599 else if (fixp
->fx_subsy
15600 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15601 && (!fixp
->fx_addsy
15602 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15603 sym
= fixp
->fx_subsy
;
15606 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15608 /* Resolve size relocation against local symbol to size of
15609 the symbol plus addend. */
15610 valueT value
= S_GET_SIZE (sym
);
15612 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15613 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15614 if (sym
== fixp
->fx_subsy
)
15617 if (fixp
->fx_addsy
)
15618 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15620 else if (fixp
->fx_subsy
)
15621 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15622 value
+= fixp
->fx_offset
;
15623 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15625 && !fits_in_unsigned_long (value
))
15626 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15627 _("symbol size computation overflow"));
15628 fixp
->fx_addsy
= NULL
;
15629 fixp
->fx_subsy
= NULL
;
15630 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15633 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15635 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15636 "unsupported expression involving @size");
15640 /* Fall through. */
15642 case BFD_RELOC_X86_64_PLT32
:
15643 case BFD_RELOC_X86_64_GOT32
:
15644 case BFD_RELOC_X86_64_GOTPCREL
:
15645 case BFD_RELOC_X86_64_GOTPCRELX
:
15646 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15647 case BFD_RELOC_386_PLT32
:
15648 case BFD_RELOC_386_GOT32
:
15649 case BFD_RELOC_386_GOT32X
:
15650 case BFD_RELOC_386_GOTOFF
:
15651 case BFD_RELOC_386_GOTPC
:
15652 case BFD_RELOC_386_TLS_GD
:
15653 case BFD_RELOC_386_TLS_LDM
:
15654 case BFD_RELOC_386_TLS_LDO_32
:
15655 case BFD_RELOC_386_TLS_IE_32
:
15656 case BFD_RELOC_386_TLS_IE
:
15657 case BFD_RELOC_386_TLS_GOTIE
:
15658 case BFD_RELOC_386_TLS_LE_32
:
15659 case BFD_RELOC_386_TLS_LE
:
15660 case BFD_RELOC_386_TLS_GOTDESC
:
15661 case BFD_RELOC_386_TLS_DESC_CALL
:
15662 case BFD_RELOC_X86_64_TLSGD
:
15663 case BFD_RELOC_X86_64_TLSLD
:
15664 case BFD_RELOC_X86_64_DTPOFF32
:
15665 case BFD_RELOC_X86_64_DTPOFF64
:
15666 case BFD_RELOC_X86_64_GOTTPOFF
:
15667 case BFD_RELOC_X86_64_TPOFF32
:
15668 case BFD_RELOC_X86_64_TPOFF64
:
15669 case BFD_RELOC_X86_64_GOTOFF64
:
15670 case BFD_RELOC_X86_64_GOTPC32
:
15671 case BFD_RELOC_X86_64_GOT64
:
15672 case BFD_RELOC_X86_64_GOTPCREL64
:
15673 case BFD_RELOC_X86_64_GOTPC64
:
15674 case BFD_RELOC_X86_64_GOTPLT64
:
15675 case BFD_RELOC_X86_64_PLTOFF64
:
15676 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15677 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15678 case BFD_RELOC_RVA
:
15679 case BFD_RELOC_VTABLE_ENTRY
:
15680 case BFD_RELOC_VTABLE_INHERIT
:
15682 case BFD_RELOC_32_SECREL
:
15683 case BFD_RELOC_16_SECIDX
:
15685 code
= fixp
->fx_r_type
;
15687 case BFD_RELOC_X86_64_32S
:
15688 if (!fixp
->fx_pcrel
)
15690 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15691 code
= fixp
->fx_r_type
;
15694 /* Fall through. */
15696 if (fixp
->fx_pcrel
)
15698 switch (fixp
->fx_size
)
15701 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15702 _("can not do %d byte pc-relative relocation"),
15704 code
= BFD_RELOC_32_PCREL
;
15706 case 1: code
= BFD_RELOC_8_PCREL
; break;
15707 case 2: code
= BFD_RELOC_16_PCREL
; break;
15708 case 4: code
= BFD_RELOC_32_PCREL
; break;
15710 case 8: code
= BFD_RELOC_64_PCREL
; break;
15716 switch (fixp
->fx_size
)
15719 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15720 _("can not do %d byte relocation"),
15722 code
= BFD_RELOC_32
;
15724 case 1: code
= BFD_RELOC_8
; break;
15725 case 2: code
= BFD_RELOC_16
; break;
15726 case 4: code
= BFD_RELOC_32
; break;
15728 case 8: code
= BFD_RELOC_64
; break;
15735 if ((code
== BFD_RELOC_32
15736 || code
== BFD_RELOC_32_PCREL
15737 || code
== BFD_RELOC_X86_64_32S
)
15739 && fixp
->fx_addsy
== GOT_symbol
)
15742 code
= BFD_RELOC_386_GOTPC
;
15744 code
= BFD_RELOC_X86_64_GOTPC32
;
15746 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15748 && fixp
->fx_addsy
== GOT_symbol
)
15750 code
= BFD_RELOC_X86_64_GOTPC64
;
15753 rel
= XNEW (arelent
);
15754 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15755 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15757 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15759 if (!use_rela_relocations
)
15761 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15762 vtable entry to be used in the relocation's section offset. */
15763 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15764 rel
->address
= fixp
->fx_offset
;
15765 #if defined (OBJ_COFF) && defined (TE_PE)
15766 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15767 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15772 /* Use the rela in 64bit mode. */
15775 if (disallow_64bit_reloc
)
15778 case BFD_RELOC_X86_64_DTPOFF64
:
15779 case BFD_RELOC_X86_64_TPOFF64
:
15780 case BFD_RELOC_64_PCREL
:
15781 case BFD_RELOC_X86_64_GOTOFF64
:
15782 case BFD_RELOC_X86_64_GOT64
:
15783 case BFD_RELOC_X86_64_GOTPCREL64
:
15784 case BFD_RELOC_X86_64_GOTPC64
:
15785 case BFD_RELOC_X86_64_GOTPLT64
:
15786 case BFD_RELOC_X86_64_PLTOFF64
:
15787 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15788 _("cannot represent relocation type %s in x32 mode"),
15789 bfd_get_reloc_code_name (code
));
15795 if (!fixp
->fx_pcrel
)
15796 rel
->addend
= fixp
->fx_offset
;
15800 case BFD_RELOC_X86_64_PLT32
:
15801 case BFD_RELOC_X86_64_GOT32
:
15802 case BFD_RELOC_X86_64_GOTPCREL
:
15803 case BFD_RELOC_X86_64_GOTPCRELX
:
15804 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15805 case BFD_RELOC_X86_64_TLSGD
:
15806 case BFD_RELOC_X86_64_TLSLD
:
15807 case BFD_RELOC_X86_64_GOTTPOFF
:
15808 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15809 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15810 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15813 rel
->addend
= (section
->vma
15815 + fixp
->fx_addnumber
15816 + md_pcrel_from (fixp
));
15821 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15822 if (rel
->howto
== NULL
)
15824 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15825 _("cannot represent relocation type %s"),
15826 bfd_get_reloc_code_name (code
));
15827 /* Set howto to a garbage value so that we can keep going. */
15828 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15829 gas_assert (rel
->howto
!= NULL
);
15835 #include "tc-i386-intel.c"
15838 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15840 int saved_naked_reg
;
15841 char saved_register_dot
;
15843 saved_naked_reg
= allow_naked_reg
;
15844 allow_naked_reg
= 1;
15845 saved_register_dot
= register_chars
['.'];
15846 register_chars
['.'] = '.';
15847 allow_pseudo_reg
= 1;
15848 expression_and_evaluate (exp
);
15849 allow_pseudo_reg
= 0;
15850 register_chars
['.'] = saved_register_dot
;
15851 allow_naked_reg
= saved_naked_reg
;
15853 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15855 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15857 exp
->X_op
= O_constant
;
15858 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15859 .dw2_regnum
[flag_code
>> 1];
15862 exp
->X_op
= O_illegal
;
15867 tc_x86_frame_initial_instructions (void)
15869 static unsigned int sp_regno
[2];
15871 if (!sp_regno
[flag_code
>> 1])
15873 char *saved_input
= input_line_pointer
;
15874 char sp
[][4] = {"esp", "rsp"};
15877 input_line_pointer
= sp
[flag_code
>> 1];
15878 tc_x86_parse_to_dw2regnum (&exp
);
15879 gas_assert (exp
.X_op
== O_constant
);
15880 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15881 input_line_pointer
= saved_input
;
15884 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15885 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15889 x86_dwarf2_addr_size (void)
15891 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15892 if (x86_elf_abi
== X86_64_X32_ABI
)
15895 return bfd_arch_bits_per_address (stdoutput
) / 8;
15899 i386_elf_section_type (const char *str
, size_t len
)
15901 if (flag_code
== CODE_64BIT
15902 && len
== sizeof ("unwind") - 1
15903 && startswith (str
, "unwind"))
15904 return SHT_X86_64_UNWIND
;
15911 i386_solaris_fix_up_eh_frame (segT sec
)
15913 if (flag_code
== CODE_64BIT
)
15914 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15920 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15924 exp
.X_op
= O_secrel
;
15925 exp
.X_add_symbol
= symbol
;
15926 exp
.X_add_number
= 0;
15927 emit_expr (&exp
, size
);
15931 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15932 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15935 x86_64_section_letter (int letter
, const char **ptr_msg
)
15937 if (flag_code
== CODE_64BIT
)
15940 return SHF_X86_64_LARGE
;
15942 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15945 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15950 handle_large_common (int small ATTRIBUTE_UNUSED
)
15952 if (flag_code
!= CODE_64BIT
)
15954 s_comm_internal (0, elf_common_parse
);
15955 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15959 static segT lbss_section
;
15960 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15961 asection
*saved_bss_section
= bss_section
;
15963 if (lbss_section
== NULL
)
15965 flagword applicable
;
15966 segT seg
= now_seg
;
15967 subsegT subseg
= now_subseg
;
15969 /* The .lbss section is for local .largecomm symbols. */
15970 lbss_section
= subseg_new (".lbss", 0);
15971 applicable
= bfd_applicable_section_flags (stdoutput
);
15972 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15973 seg_info (lbss_section
)->bss
= 1;
15975 subseg_set (seg
, subseg
);
15978 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15979 bss_section
= lbss_section
;
15981 s_comm_internal (0, elf_common_parse
);
15983 elf_com_section_ptr
= saved_com_section_ptr
;
15984 bss_section
= saved_bss_section
;
15987 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */