1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 enum processor_type type
; /* arch type */
132 i386_cpu_flags flags
; /* cpu feature flags */
136 static void set_code_flag (int);
137 static void set_16bit_gcc_code_flag (int);
138 static void set_intel_syntax (int);
139 static void set_intel_mnemonic (int);
140 static void set_allow_index_reg (int);
141 static void set_sse_check (int);
142 static void set_cpu_arch (int);
144 static void pe_directive_secrel (int);
146 static void signed_cons (int);
147 static char *output_invalid (int c
);
148 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
150 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
152 static int i386_att_operand (char *);
153 static int i386_intel_operand (char *, int);
154 static int i386_intel_simplify (expressionS
*);
155 static int i386_intel_parse_name (const char *, expressionS
*);
156 static const reg_entry
*parse_register (char *, char **);
157 static char *parse_insn (char *, char *);
158 static char *parse_operands (char *, const char *);
159 static void swap_operands (void);
160 static void swap_2_operands (int, int);
161 static void optimize_imm (void);
162 static void optimize_disp (void);
163 static const insn_template
*match_template (void);
164 static int check_string (void);
165 static int process_suffix (void);
166 static int check_byte_reg (void);
167 static int check_long_reg (void);
168 static int check_qword_reg (void);
169 static int check_word_reg (void);
170 static int finalize_imm (void);
171 static int process_operands (void);
172 static const seg_entry
*build_modrm_byte (void);
173 static void output_insn (void);
174 static void output_imm (fragS
*, offsetT
);
175 static void output_disp (fragS
*, offsetT
);
177 static void s_bss (int);
179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
180 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
183 static const char *default_arch
= DEFAULT_ARCH
;
188 /* VEX prefix is either 2 byte or 3 byte. */
189 unsigned char bytes
[3];
191 /* Destination or source register specifier. */
192 const reg_entry
*register_specifier
;
195 /* 'md_assemble ()' gathers together information and puts it into a
202 const reg_entry
*regs
;
207 /* TM holds the template for the insn were currently assembling. */
210 /* SUFFIX holds the instruction size suffix for byte, word, dword
211 or qword, if given. */
214 /* OPERANDS gives the number of given operands. */
215 unsigned int operands
;
217 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
218 of given register, displacement, memory operands and immediate
220 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
222 /* TYPES [i] is the type (see above #defines) which tells us how to
223 use OP[i] for the corresponding operand. */
224 i386_operand_type types
[MAX_OPERANDS
];
226 /* Displacement expression, immediate expression, or register for each
228 union i386_op op
[MAX_OPERANDS
];
230 /* Flags for operands. */
231 unsigned int flags
[MAX_OPERANDS
];
232 #define Operand_PCrel 1
234 /* Relocation type for operand */
235 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
237 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
238 the base index byte below. */
239 const reg_entry
*base_reg
;
240 const reg_entry
*index_reg
;
241 unsigned int log2_scale_factor
;
243 /* SEG gives the seg_entries of this insn. They are zero unless
244 explicit segment overrides are given. */
245 const seg_entry
*seg
[2];
247 /* PREFIX holds all the given prefix opcodes (usually null).
248 PREFIXES is the number of prefix opcodes. */
249 unsigned int prefixes
;
250 unsigned char prefix
[MAX_PREFIXES
];
252 /* RM and SIB are the modrm byte and the sib byte where the
253 addressing modes of this insn are encoded. */
259 /* Swap operand in encoding. */
260 unsigned int swap_operand
;
263 typedef struct _i386_insn i386_insn
;
265 /* List of chars besides those in app.c:symbol_chars that can start an
266 operand. Used to prevent the scrubber eating vital white-space. */
267 const char extra_symbol_chars
[] = "*%-(["
276 #if (defined (TE_I386AIX) \
277 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
278 && !defined (TE_GNU) \
279 && !defined (TE_LINUX) \
280 && !defined (TE_NETWARE) \
281 && !defined (TE_FreeBSD) \
282 && !defined (TE_NetBSD)))
283 /* This array holds the chars that always start a comment. If the
284 pre-processor is disabled, these aren't very useful. The option
285 --divide will remove '/' from this list. */
286 const char *i386_comment_chars
= "#/";
287 #define SVR4_COMMENT_CHARS 1
288 #define PREFIX_SEPARATOR '\\'
291 const char *i386_comment_chars
= "#";
292 #define PREFIX_SEPARATOR '/'
295 /* This array holds the chars that only start a comment at the beginning of
296 a line. If the line seems to have the form '# 123 filename'
297 .line and .file directives will appear in the pre-processed output.
298 Note that input_file.c hand checks for '#' at the beginning of the
299 first line of the input file. This is because the compiler outputs
300 #NO_APP at the beginning of its output.
301 Also note that comments started like this one will always work if
302 '/' isn't otherwise defined. */
303 const char line_comment_chars
[] = "#/";
305 const char line_separator_chars
[] = ";";
307 /* Chars that can be used to separate mant from exp in floating point
309 const char EXP_CHARS
[] = "eE";
311 /* Chars that mean this number is a floating point constant
314 const char FLT_CHARS
[] = "fFdDxX";
316 /* Tables for lexical analysis. */
317 static char mnemonic_chars
[256];
318 static char register_chars
[256];
319 static char operand_chars
[256];
320 static char identifier_chars
[256];
321 static char digit_chars
[256];
323 /* Lexical macros. */
324 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
325 #define is_operand_char(x) (operand_chars[(unsigned char) x])
326 #define is_register_char(x) (register_chars[(unsigned char) x])
327 #define is_space_char(x) ((x) == ' ')
328 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
329 #define is_digit_char(x) (digit_chars[(unsigned char) x])
331 /* All non-digit non-letter characters that may occur in an operand. */
332 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
334 /* md_assemble() always leaves the strings it's passed unaltered. To
335 effect this we maintain a stack of saved characters that we've smashed
336 with '\0's (indicating end of strings for various sub-fields of the
337 assembler instruction). */
338 static char save_stack
[32];
339 static char *save_stack_p
;
340 #define END_STRING_AND_SAVE(s) \
341 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
342 #define RESTORE_END_STRING(s) \
343 do { *(s) = *--save_stack_p; } while (0)
345 /* The instruction we're assembling. */
348 /* Possible templates for current insn. */
349 static const templates
*current_templates
;
351 /* Per instruction expressionS buffers: max displacements & immediates. */
352 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
353 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
355 /* Current operand we are working on. */
356 static int this_operand
= -1;
358 /* We support four different modes. FLAG_CODE variable is used to distinguish
366 static enum flag_code flag_code
;
367 static unsigned int object_64bit
;
368 static int use_rela_relocations
= 0;
370 /* The names used to print error messages. */
371 static const char *flag_code_names
[] =
378 /* 1 for intel syntax,
380 static int intel_syntax
= 0;
382 /* 1 for intel mnemonic,
383 0 if att mnemonic. */
384 static int intel_mnemonic
= !SYSV386_COMPAT
;
386 /* 1 if support old (<= 2.8.1) versions of gcc. */
387 static int old_gcc
= OLDGCC_COMPAT
;
389 /* 1 if pseudo registers are permitted. */
390 static int allow_pseudo_reg
= 0;
392 /* 1 if register prefix % not required. */
393 static int allow_naked_reg
= 0;
395 /* 1 if pseudo index register, eiz/riz, is allowed . */
396 static int allow_index_reg
= 0;
406 /* Register prefix used for error message. */
407 static const char *register_prefix
= "%";
409 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
410 leave, push, and pop instructions so that gcc has the same stack
411 frame as in 32 bit mode. */
412 static char stackop_size
= '\0';
414 /* Non-zero to optimize code alignment. */
415 int optimize_align_code
= 1;
417 /* Non-zero to quieten some warnings. */
418 static int quiet_warnings
= 0;
421 static const char *cpu_arch_name
= NULL
;
422 static char *cpu_sub_arch_name
= NULL
;
424 /* CPU feature flags. */
425 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
427 /* If we have selected a cpu we are generating instructions for. */
428 static int cpu_arch_tune_set
= 0;
430 /* Cpu we are generating instructions for. */
431 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
433 /* CPU feature flags of cpu we are generating instructions for. */
434 static i386_cpu_flags cpu_arch_tune_flags
;
436 /* CPU instruction set architecture used. */
437 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
439 /* CPU feature flags of instruction set architecture used. */
440 i386_cpu_flags cpu_arch_isa_flags
;
442 /* If set, conditional jumps are not automatically promoted to handle
443 larger than a byte offset. */
444 static unsigned int no_cond_jump_promotion
= 0;
446 /* Encode SSE instructions with VEX prefix. */
447 static unsigned int sse2avx
;
449 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
450 static symbolS
*GOT_symbol
;
452 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
453 unsigned int x86_dwarf2_return_column
;
455 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
456 int x86_cie_data_alignment
;
458 /* Interface to relax_segment.
459 There are 3 major relax states for 386 jump insns because the
460 different types of jumps add different sizes to frags when we're
461 figuring out what sort of jump to choose to reach a given label. */
464 #define UNCOND_JUMP 0
466 #define COND_JUMP86 2
471 #define SMALL16 (SMALL | CODE16)
473 #define BIG16 (BIG | CODE16)
477 #define INLINE __inline__
483 #define ENCODE_RELAX_STATE(type, size) \
484 ((relax_substateT) (((type) << 2) | (size)))
485 #define TYPE_FROM_RELAX_STATE(s) \
487 #define DISP_SIZE_FROM_RELAX_STATE(s) \
488 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
490 /* This table is used by relax_frag to promote short jumps to long
491 ones where necessary. SMALL (short) jumps may be promoted to BIG
492 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
493 don't allow a short jump in a 32 bit code segment to be promoted to
494 a 16 bit offset jump because it's slower (requires data size
495 prefix), and doesn't work, unless the destination is in the bottom
496 64k of the code segment (The top 16 bits of eip are zeroed). */
498 const relax_typeS md_relax_table
[] =
501 1) most positive reach of this state,
502 2) most negative reach of this state,
503 3) how many bytes this mode will have in the variable part of the frag
504 4) which index into the table to try if we can't fit into this one. */
506 /* UNCOND_JUMP states. */
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
508 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
509 /* dword jmp adds 4 bytes to frag:
510 0 extra opcode bytes, 4 displacement bytes. */
512 /* word jmp adds 2 byte2 to frag:
513 0 extra opcode bytes, 2 displacement bytes. */
516 /* COND_JUMP states. */
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
518 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
519 /* dword conditionals adds 5 bytes to frag:
520 1 extra opcode byte, 4 displacement bytes. */
522 /* word conditionals add 3 bytes to frag:
523 1 extra opcode byte, 2 displacement bytes. */
526 /* COND_JUMP86 states. */
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
529 /* dword conditionals adds 5 bytes to frag:
530 1 extra opcode byte, 4 displacement bytes. */
532 /* word conditionals add 4 bytes to frag:
533 1 displacement byte and a 3 byte long branch insn. */
537 static const arch_entry cpu_arch
[] =
539 { "generic32", PROCESSOR_GENERIC32
,
540 CPU_GENERIC32_FLAGS
},
541 { "generic64", PROCESSOR_GENERIC64
,
542 CPU_GENERIC64_FLAGS
},
543 { "i8086", PROCESSOR_UNKNOWN
,
545 { "i186", PROCESSOR_UNKNOWN
,
547 { "i286", PROCESSOR_UNKNOWN
,
549 { "i386", PROCESSOR_I386
,
551 { "i486", PROCESSOR_I486
,
553 { "i586", PROCESSOR_PENTIUM
,
555 { "i686", PROCESSOR_PENTIUMPRO
,
557 { "pentium", PROCESSOR_PENTIUM
,
559 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
561 { "pentiumii", PROCESSOR_PENTIUMPRO
,
563 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
565 { "pentium4", PROCESSOR_PENTIUM4
,
567 { "prescott", PROCESSOR_NOCONA
,
569 { "nocona", PROCESSOR_NOCONA
,
571 { "yonah", PROCESSOR_CORE
,
573 { "core", PROCESSOR_CORE
,
575 { "merom", PROCESSOR_CORE2
,
577 { "core2", PROCESSOR_CORE2
,
579 { "corei7", PROCESSOR_COREI7
,
581 { "l1om", PROCESSOR_L1OM
,
583 { "k6", PROCESSOR_K6
,
585 { "k6_2", PROCESSOR_K6
,
587 { "athlon", PROCESSOR_ATHLON
,
589 { "sledgehammer", PROCESSOR_K8
,
591 { "opteron", PROCESSOR_K8
,
593 { "k8", PROCESSOR_K8
,
595 { "amdfam10", PROCESSOR_AMDFAM10
,
596 CPU_AMDFAM10_FLAGS
},
597 { ".8087", PROCESSOR_UNKNOWN
,
599 { ".287", PROCESSOR_UNKNOWN
,
601 { ".387", PROCESSOR_UNKNOWN
,
603 { ".no87", PROCESSOR_UNKNOWN
,
605 { ".mmx", PROCESSOR_UNKNOWN
,
607 { ".nommx", PROCESSOR_UNKNOWN
,
609 { ".sse", PROCESSOR_UNKNOWN
,
611 { ".sse2", PROCESSOR_UNKNOWN
,
613 { ".sse3", PROCESSOR_UNKNOWN
,
615 { ".ssse3", PROCESSOR_UNKNOWN
,
617 { ".sse4.1", PROCESSOR_UNKNOWN
,
619 { ".sse4.2", PROCESSOR_UNKNOWN
,
621 { ".sse4", PROCESSOR_UNKNOWN
,
623 { ".nosse", PROCESSOR_UNKNOWN
,
625 { ".avx", PROCESSOR_UNKNOWN
,
627 { ".noavx", PROCESSOR_UNKNOWN
,
629 { ".vmx", PROCESSOR_UNKNOWN
,
631 { ".smx", PROCESSOR_UNKNOWN
,
633 { ".xsave", PROCESSOR_UNKNOWN
,
635 { ".aes", PROCESSOR_UNKNOWN
,
637 { ".pclmul", PROCESSOR_UNKNOWN
,
639 { ".clmul", PROCESSOR_UNKNOWN
,
641 { ".fma", PROCESSOR_UNKNOWN
,
643 { ".fma4", PROCESSOR_UNKNOWN
,
645 { ".lwp", PROCESSOR_UNKNOWN
,
647 { ".movbe", PROCESSOR_UNKNOWN
,
649 { ".ept", PROCESSOR_UNKNOWN
,
651 { ".clflush", PROCESSOR_UNKNOWN
,
653 { ".syscall", PROCESSOR_UNKNOWN
,
655 { ".rdtscp", PROCESSOR_UNKNOWN
,
657 { ".3dnow", PROCESSOR_UNKNOWN
,
659 { ".3dnowa", PROCESSOR_UNKNOWN
,
661 { ".padlock", PROCESSOR_UNKNOWN
,
663 { ".pacifica", PROCESSOR_UNKNOWN
,
665 { ".svme", PROCESSOR_UNKNOWN
,
667 { ".sse4a", PROCESSOR_UNKNOWN
,
669 { ".abm", PROCESSOR_UNKNOWN
,
674 /* Like s_lcomm_internal in gas/read.c but the alignment string
675 is allowed to be optional. */
678 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
685 && *input_line_pointer
== ',')
687 align
= parse_align (needs_align
- 1);
689 if (align
== (addressT
) -1)
704 bss_alloc (symbolP
, size
, align
);
709 pe_lcomm (int needs_align
)
711 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
715 const pseudo_typeS md_pseudo_table
[] =
717 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
718 {"align", s_align_bytes
, 0},
720 {"align", s_align_ptwo
, 0},
722 {"arch", set_cpu_arch
, 0},
726 {"lcomm", pe_lcomm
, 1},
728 {"ffloat", float_cons
, 'f'},
729 {"dfloat", float_cons
, 'd'},
730 {"tfloat", float_cons
, 'x'},
732 {"slong", signed_cons
, 4},
733 {"noopt", s_ignore
, 0},
734 {"optim", s_ignore
, 0},
735 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
736 {"code16", set_code_flag
, CODE_16BIT
},
737 {"code32", set_code_flag
, CODE_32BIT
},
738 {"code64", set_code_flag
, CODE_64BIT
},
739 {"intel_syntax", set_intel_syntax
, 1},
740 {"att_syntax", set_intel_syntax
, 0},
741 {"intel_mnemonic", set_intel_mnemonic
, 1},
742 {"att_mnemonic", set_intel_mnemonic
, 0},
743 {"allow_index_reg", set_allow_index_reg
, 1},
744 {"disallow_index_reg", set_allow_index_reg
, 0},
745 {"sse_check", set_sse_check
, 0},
746 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
747 {"largecomm", handle_large_common
, 0},
749 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
750 {"loc", dwarf2_directive_loc
, 0},
751 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
754 {"secrel32", pe_directive_secrel
, 0},
759 /* For interface with expression (). */
760 extern char *input_line_pointer
;
762 /* Hash table for instruction mnemonic lookup. */
763 static struct hash_control
*op_hash
;
765 /* Hash table for register lookup. */
766 static struct hash_control
*reg_hash
;
769 i386_align_code (fragS
*fragP
, int count
)
771 /* Various efficient no-op patterns for aligning code labels.
772 Note: Don't try to assemble the instructions in the comments.
773 0L and 0w are not legal. */
774 static const char f32_1
[] =
776 static const char f32_2
[] =
777 {0x66,0x90}; /* xchg %ax,%ax */
778 static const char f32_3
[] =
779 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
780 static const char f32_4
[] =
781 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_5
[] =
784 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
785 static const char f32_6
[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
787 static const char f32_7
[] =
788 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_8
[] =
791 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
792 static const char f32_9
[] =
793 {0x89,0xf6, /* movl %esi,%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_10
[] =
796 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_11
[] =
799 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_12
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
804 static const char f32_13
[] =
805 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_14
[] =
808 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
809 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
810 static const char f16_3
[] =
811 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
812 static const char f16_4
[] =
813 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_5
[] =
816 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
817 static const char f16_6
[] =
818 {0x89,0xf6, /* mov %si,%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_7
[] =
821 {0x8d,0x74,0x00, /* lea 0(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char f16_8
[] =
824 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char jump_31
[] =
827 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
829 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
830 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
831 static const char *const f32_patt
[] = {
832 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
833 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
835 static const char *const f16_patt
[] = {
836 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
839 static const char alt_3
[] =
841 /* nopl 0(%[re]ax) */
842 static const char alt_4
[] =
843 {0x0f,0x1f,0x40,0x00};
844 /* nopl 0(%[re]ax,%[re]ax,1) */
845 static const char alt_5
[] =
846 {0x0f,0x1f,0x44,0x00,0x00};
847 /* nopw 0(%[re]ax,%[re]ax,1) */
848 static const char alt_6
[] =
849 {0x66,0x0f,0x1f,0x44,0x00,0x00};
850 /* nopl 0L(%[re]ax) */
851 static const char alt_7
[] =
852 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_8
[] =
855 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw 0L(%[re]ax,%[re]ax,1) */
857 static const char alt_9
[] =
858 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
859 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
860 static const char alt_10
[] =
861 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_long_11
[] =
866 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_12
[] =
873 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 nopw %cs:0L(%[re]ax,%[re]ax,1) */
878 static const char alt_long_13
[] =
882 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 nopw %cs:0L(%[re]ax,%[re]ax,1) */
888 static const char alt_long_14
[] =
893 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_15
[] =
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 /* nopl 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_11
[] =
910 {0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
913 nopw 0(%[re]ax,%[re]ax,1) */
914 static const char alt_short_12
[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x66,0x0f,0x1f,0x44,0x00,0x00};
917 /* nopw 0(%[re]ax,%[re]ax,1)
919 static const char alt_short_13
[] =
920 {0x66,0x0f,0x1f,0x44,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
924 static const char alt_short_14
[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 nopl 0L(%[re]ax,%[re]ax,1) */
929 static const char alt_short_15
[] =
930 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
931 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
932 static const char *const alt_short_patt
[] = {
933 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
934 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
935 alt_short_14
, alt_short_15
937 static const char *const alt_long_patt
[] = {
938 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
939 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
940 alt_long_14
, alt_long_15
943 /* Only align for at least a positive non-zero boundary. */
944 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
947 /* We need to decide which NOP sequence to use for 32bit and
948 64bit. When -mtune= is used:
950 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
951 PROCESSOR_GENERIC32, f32_patt will be used.
952 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
953 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
954 PROCESSOR_GENERIC64, alt_long_patt will be used.
955 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
956 PROCESSOR_AMDFAM10, alt_short_patt will be used.
958 When -mtune= isn't used, alt_long_patt will be used if
959 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
962 When -march= or .arch is used, we can't use anything beyond
963 cpu_arch_isa_flags. */
965 if (flag_code
== CODE_16BIT
)
969 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
971 /* Adjust jump offset. */
972 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
976 f16_patt
[count
- 1], count
);
980 const char *const *patt
= NULL
;
982 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
984 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
985 switch (cpu_arch_tune
)
987 case PROCESSOR_UNKNOWN
:
988 /* We use cpu_arch_isa_flags to check if we SHOULD
989 optimize for Cpu686. */
990 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
991 patt
= alt_long_patt
;
995 case PROCESSOR_PENTIUMPRO
:
996 case PROCESSOR_PENTIUM4
:
997 case PROCESSOR_NOCONA
:
999 case PROCESSOR_CORE2
:
1000 case PROCESSOR_COREI7
:
1001 case PROCESSOR_L1OM
:
1002 case PROCESSOR_GENERIC64
:
1003 patt
= alt_long_patt
;
1006 case PROCESSOR_ATHLON
:
1008 case PROCESSOR_AMDFAM10
:
1009 patt
= alt_short_patt
;
1011 case PROCESSOR_I386
:
1012 case PROCESSOR_I486
:
1013 case PROCESSOR_PENTIUM
:
1014 case PROCESSOR_GENERIC32
:
1021 switch (fragP
->tc_frag_data
.tune
)
1023 case PROCESSOR_UNKNOWN
:
1024 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1025 PROCESSOR_UNKNOWN. */
1029 case PROCESSOR_I386
:
1030 case PROCESSOR_I486
:
1031 case PROCESSOR_PENTIUM
:
1033 case PROCESSOR_ATHLON
:
1035 case PROCESSOR_AMDFAM10
:
1036 case PROCESSOR_GENERIC32
:
1037 /* We use cpu_arch_isa_flags to check if we CAN optimize
1039 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1040 patt
= alt_short_patt
;
1044 case PROCESSOR_PENTIUMPRO
:
1045 case PROCESSOR_PENTIUM4
:
1046 case PROCESSOR_NOCONA
:
1047 case PROCESSOR_CORE
:
1048 case PROCESSOR_CORE2
:
1049 case PROCESSOR_COREI7
:
1050 case PROCESSOR_L1OM
:
1051 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1052 patt
= alt_long_patt
;
1056 case PROCESSOR_GENERIC64
:
1057 patt
= alt_long_patt
;
1062 if (patt
== f32_patt
)
1064 /* If the padding is less than 15 bytes, we use the normal
1065 ones. Otherwise, we use a jump instruction and adjust
1069 /* For 64bit, the limit is 3 bytes. */
1070 if (flag_code
== CODE_64BIT
1071 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1076 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1077 patt
[count
- 1], count
);
1080 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1082 /* Adjust jump offset. */
1083 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1088 /* Maximum length of an instruction is 15 byte. If the
1089 padding is greater than 15 bytes and we don't use jump,
1090 we have to break it into smaller pieces. */
1091 int padding
= count
;
1092 while (padding
> 15)
1095 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1100 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1101 patt
[padding
- 1], padding
);
1104 fragP
->fr_var
= count
;
1108 operand_type_all_zero (const union i386_operand_type
*x
)
1110 switch (ARRAY_SIZE(x
->array
))
1119 return !x
->array
[0];
1126 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1128 switch (ARRAY_SIZE(x
->array
))
1143 operand_type_equal (const union i386_operand_type
*x
,
1144 const union i386_operand_type
*y
)
1146 switch (ARRAY_SIZE(x
->array
))
1149 if (x
->array
[2] != y
->array
[2])
1152 if (x
->array
[1] != y
->array
[1])
1155 return x
->array
[0] == y
->array
[0];
1163 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1165 switch (ARRAY_SIZE(x
->array
))
1174 return !x
->array
[0];
1181 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1183 switch (ARRAY_SIZE(x
->array
))
1198 cpu_flags_equal (const union i386_cpu_flags
*x
,
1199 const union i386_cpu_flags
*y
)
1201 switch (ARRAY_SIZE(x
->array
))
1204 if (x
->array
[2] != y
->array
[2])
1207 if (x
->array
[1] != y
->array
[1])
1210 return x
->array
[0] == y
->array
[0];
1218 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1220 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1221 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1224 static INLINE i386_cpu_flags
1225 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1227 switch (ARRAY_SIZE (x
.array
))
1230 x
.array
[2] &= y
.array
[2];
1232 x
.array
[1] &= y
.array
[1];
1234 x
.array
[0] &= y
.array
[0];
1242 static INLINE i386_cpu_flags
1243 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1245 switch (ARRAY_SIZE (x
.array
))
1248 x
.array
[2] |= y
.array
[2];
1250 x
.array
[1] |= y
.array
[1];
1252 x
.array
[0] |= y
.array
[0];
1260 static INLINE i386_cpu_flags
1261 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1263 switch (ARRAY_SIZE (x
.array
))
1266 x
.array
[2] &= ~y
.array
[2];
1268 x
.array
[1] &= ~y
.array
[1];
1270 x
.array
[0] &= ~y
.array
[0];
1278 #define CPU_FLAGS_ARCH_MATCH 0x1
1279 #define CPU_FLAGS_64BIT_MATCH 0x2
1280 #define CPU_FLAGS_AES_MATCH 0x4
1281 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1282 #define CPU_FLAGS_AVX_MATCH 0x10
1284 #define CPU_FLAGS_32BIT_MATCH \
1285 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1286 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1287 #define CPU_FLAGS_PERFECT_MATCH \
1288 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1290 /* Return CPU flags match bits. */
1293 cpu_flags_match (const insn_template
*t
)
1295 i386_cpu_flags x
= t
->cpu_flags
;
1296 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1298 x
.bitfield
.cpu64
= 0;
1299 x
.bitfield
.cpuno64
= 0;
1301 if (cpu_flags_all_zero (&x
))
1303 /* This instruction is available on all archs. */
1304 match
|= CPU_FLAGS_32BIT_MATCH
;
1308 /* This instruction is available only on some archs. */
1309 i386_cpu_flags cpu
= cpu_arch_flags
;
1311 cpu
.bitfield
.cpu64
= 0;
1312 cpu
.bitfield
.cpuno64
= 0;
1313 cpu
= cpu_flags_and (x
, cpu
);
1314 if (!cpu_flags_all_zero (&cpu
))
1316 if (x
.bitfield
.cpuavx
)
1318 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1319 if (cpu
.bitfield
.cpuavx
)
1321 /* Check SSE2AVX. */
1322 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1324 match
|= (CPU_FLAGS_ARCH_MATCH
1325 | CPU_FLAGS_AVX_MATCH
);
1327 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1328 match
|= CPU_FLAGS_AES_MATCH
;
1330 if (!x
.bitfield
.cpupclmul
1331 || cpu
.bitfield
.cpupclmul
)
1332 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1336 match
|= CPU_FLAGS_ARCH_MATCH
;
1339 match
|= CPU_FLAGS_32BIT_MATCH
;
1345 static INLINE i386_operand_type
1346 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1348 switch (ARRAY_SIZE (x
.array
))
1351 x
.array
[2] &= y
.array
[2];
1353 x
.array
[1] &= y
.array
[1];
1355 x
.array
[0] &= y
.array
[0];
1363 static INLINE i386_operand_type
1364 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1366 switch (ARRAY_SIZE (x
.array
))
1369 x
.array
[2] |= y
.array
[2];
1371 x
.array
[1] |= y
.array
[1];
1373 x
.array
[0] |= y
.array
[0];
1381 static INLINE i386_operand_type
1382 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1384 switch (ARRAY_SIZE (x
.array
))
1387 x
.array
[2] ^= y
.array
[2];
1389 x
.array
[1] ^= y
.array
[1];
1391 x
.array
[0] ^= y
.array
[0];
1399 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1400 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1401 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1402 static const i386_operand_type inoutportreg
1403 = OPERAND_TYPE_INOUTPORTREG
;
1404 static const i386_operand_type reg16_inoutportreg
1405 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1406 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1407 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1408 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1409 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1410 static const i386_operand_type anydisp
1411 = OPERAND_TYPE_ANYDISP
;
1412 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1413 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1414 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1415 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1416 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1417 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1418 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1419 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1420 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1421 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1422 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1433 operand_type_check (i386_operand_type t
, enum operand_type c
)
1438 return (t
.bitfield
.reg8
1441 || t
.bitfield
.reg64
);
1444 return (t
.bitfield
.imm8
1448 || t
.bitfield
.imm32s
1449 || t
.bitfield
.imm64
);
1452 return (t
.bitfield
.disp8
1453 || t
.bitfield
.disp16
1454 || t
.bitfield
.disp32
1455 || t
.bitfield
.disp32s
1456 || t
.bitfield
.disp64
);
1459 return (t
.bitfield
.disp8
1460 || t
.bitfield
.disp16
1461 || t
.bitfield
.disp32
1462 || t
.bitfield
.disp32s
1463 || t
.bitfield
.disp64
1464 || t
.bitfield
.baseindex
);
1473 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1474 operand J for instruction template T. */
1477 match_reg_size (const insn_template
*t
, unsigned int j
)
1479 return !((i
.types
[j
].bitfield
.byte
1480 && !t
->operand_types
[j
].bitfield
.byte
)
1481 || (i
.types
[j
].bitfield
.word
1482 && !t
->operand_types
[j
].bitfield
.word
)
1483 || (i
.types
[j
].bitfield
.dword
1484 && !t
->operand_types
[j
].bitfield
.dword
)
1485 || (i
.types
[j
].bitfield
.qword
1486 && !t
->operand_types
[j
].bitfield
.qword
));
1489 /* Return 1 if there is no conflict in any size on operand J for
1490 instruction template T. */
1493 match_mem_size (const insn_template
*t
, unsigned int j
)
1495 return (match_reg_size (t
, j
)
1496 && !((i
.types
[j
].bitfield
.unspecified
1497 && !t
->operand_types
[j
].bitfield
.unspecified
)
1498 || (i
.types
[j
].bitfield
.fword
1499 && !t
->operand_types
[j
].bitfield
.fword
)
1500 || (i
.types
[j
].bitfield
.tbyte
1501 && !t
->operand_types
[j
].bitfield
.tbyte
)
1502 || (i
.types
[j
].bitfield
.xmmword
1503 && !t
->operand_types
[j
].bitfield
.xmmword
)
1504 || (i
.types
[j
].bitfield
.ymmword
1505 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1508 /* Return 1 if there is no size conflict on any operands for
1509 instruction template T. */
1512 operand_size_match (const insn_template
*t
)
1517 /* Don't check jump instructions. */
1518 if (t
->opcode_modifier
.jump
1519 || t
->opcode_modifier
.jumpbyte
1520 || t
->opcode_modifier
.jumpdword
1521 || t
->opcode_modifier
.jumpintersegment
)
1524 /* Check memory and accumulator operand size. */
1525 for (j
= 0; j
< i
.operands
; j
++)
1527 if (t
->operand_types
[j
].bitfield
.anysize
)
1530 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1536 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1544 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1547 /* Check reverse. */
1548 gas_assert (i
.operands
== 2);
1551 for (j
= 0; j
< 2; j
++)
1553 if (t
->operand_types
[j
].bitfield
.acc
1554 && !match_reg_size (t
, j
? 0 : 1))
1560 if (i
.types
[j
].bitfield
.mem
1561 && !match_mem_size (t
, j
? 0 : 1))
1572 operand_type_match (i386_operand_type overlap
,
1573 i386_operand_type given
)
1575 i386_operand_type temp
= overlap
;
1577 temp
.bitfield
.jumpabsolute
= 0;
1578 temp
.bitfield
.unspecified
= 0;
1579 temp
.bitfield
.byte
= 0;
1580 temp
.bitfield
.word
= 0;
1581 temp
.bitfield
.dword
= 0;
1582 temp
.bitfield
.fword
= 0;
1583 temp
.bitfield
.qword
= 0;
1584 temp
.bitfield
.tbyte
= 0;
1585 temp
.bitfield
.xmmword
= 0;
1586 temp
.bitfield
.ymmword
= 0;
1587 if (operand_type_all_zero (&temp
))
1590 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1591 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1594 /* If given types g0 and g1 are registers they must be of the same type
1595 unless the expected operand type register overlap is null.
1596 Note that Acc in a template matches every size of reg. */
1599 operand_type_register_match (i386_operand_type m0
,
1600 i386_operand_type g0
,
1601 i386_operand_type t0
,
1602 i386_operand_type m1
,
1603 i386_operand_type g1
,
1604 i386_operand_type t1
)
1606 if (!operand_type_check (g0
, reg
))
1609 if (!operand_type_check (g1
, reg
))
1612 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1613 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1614 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1615 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1618 if (m0
.bitfield
.acc
)
1620 t0
.bitfield
.reg8
= 1;
1621 t0
.bitfield
.reg16
= 1;
1622 t0
.bitfield
.reg32
= 1;
1623 t0
.bitfield
.reg64
= 1;
1626 if (m1
.bitfield
.acc
)
1628 t1
.bitfield
.reg8
= 1;
1629 t1
.bitfield
.reg16
= 1;
1630 t1
.bitfield
.reg32
= 1;
1631 t1
.bitfield
.reg64
= 1;
1634 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1635 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1636 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1637 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1640 static INLINE
unsigned int
1641 mode_from_disp_size (i386_operand_type t
)
1643 if (t
.bitfield
.disp8
)
1645 else if (t
.bitfield
.disp16
1646 || t
.bitfield
.disp32
1647 || t
.bitfield
.disp32s
)
1654 fits_in_signed_byte (offsetT num
)
1656 return (num
>= -128) && (num
<= 127);
1660 fits_in_unsigned_byte (offsetT num
)
1662 return (num
& 0xff) == num
;
1666 fits_in_unsigned_word (offsetT num
)
1668 return (num
& 0xffff) == num
;
1672 fits_in_signed_word (offsetT num
)
1674 return (-32768 <= num
) && (num
<= 32767);
1678 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1683 return (!(((offsetT
) -1 << 31) & num
)
1684 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1686 } /* fits_in_signed_long() */
1689 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1694 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1696 } /* fits_in_unsigned_long() */
1698 static i386_operand_type
1699 smallest_imm_type (offsetT num
)
1701 i386_operand_type t
;
1703 operand_type_set (&t
, 0);
1704 t
.bitfield
.imm64
= 1;
1706 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1708 /* This code is disabled on the 486 because all the Imm1 forms
1709 in the opcode table are slower on the i486. They're the
1710 versions with the implicitly specified single-position
1711 displacement, which has another syntax if you really want to
1713 t
.bitfield
.imm1
= 1;
1714 t
.bitfield
.imm8
= 1;
1715 t
.bitfield
.imm8s
= 1;
1716 t
.bitfield
.imm16
= 1;
1717 t
.bitfield
.imm32
= 1;
1718 t
.bitfield
.imm32s
= 1;
1720 else if (fits_in_signed_byte (num
))
1722 t
.bitfield
.imm8
= 1;
1723 t
.bitfield
.imm8s
= 1;
1724 t
.bitfield
.imm16
= 1;
1725 t
.bitfield
.imm32
= 1;
1726 t
.bitfield
.imm32s
= 1;
1728 else if (fits_in_unsigned_byte (num
))
1730 t
.bitfield
.imm8
= 1;
1731 t
.bitfield
.imm16
= 1;
1732 t
.bitfield
.imm32
= 1;
1733 t
.bitfield
.imm32s
= 1;
1735 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1737 t
.bitfield
.imm16
= 1;
1738 t
.bitfield
.imm32
= 1;
1739 t
.bitfield
.imm32s
= 1;
1741 else if (fits_in_signed_long (num
))
1743 t
.bitfield
.imm32
= 1;
1744 t
.bitfield
.imm32s
= 1;
1746 else if (fits_in_unsigned_long (num
))
1747 t
.bitfield
.imm32
= 1;
1753 offset_in_range (offsetT val
, int size
)
1759 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1760 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1761 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1763 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1769 /* If BFD64, sign extend val for 32bit address mode. */
1770 if (flag_code
!= CODE_64BIT
1771 || i
.prefix
[ADDR_PREFIX
])
1772 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1773 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1776 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1778 char buf1
[40], buf2
[40];
1780 sprint_value (buf1
, val
);
1781 sprint_value (buf2
, val
& mask
);
1782 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1796 a. PREFIX_EXIST if attempting to add a prefix where one from the
1797 same class already exists.
1798 b. PREFIX_LOCK if lock prefix is added.
1799 c. PREFIX_REP if rep/repne prefix is added.
1800 d. PREFIX_OTHER if other prefix is added.
1803 static enum PREFIX_GROUP
1804 add_prefix (unsigned int prefix
)
1806 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1809 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1810 && flag_code
== CODE_64BIT
)
1812 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1813 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1814 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1825 case CS_PREFIX_OPCODE
:
1826 case DS_PREFIX_OPCODE
:
1827 case ES_PREFIX_OPCODE
:
1828 case FS_PREFIX_OPCODE
:
1829 case GS_PREFIX_OPCODE
:
1830 case SS_PREFIX_OPCODE
:
1834 case REPNE_PREFIX_OPCODE
:
1835 case REPE_PREFIX_OPCODE
:
1840 case LOCK_PREFIX_OPCODE
:
1849 case ADDR_PREFIX_OPCODE
:
1853 case DATA_PREFIX_OPCODE
:
1857 if (i
.prefix
[q
] != 0)
1865 i
.prefix
[q
] |= prefix
;
1868 as_bad (_("same type of prefix used twice"));
1874 set_code_flag (int value
)
1876 flag_code
= (enum flag_code
) value
;
1877 if (flag_code
== CODE_64BIT
)
1879 cpu_arch_flags
.bitfield
.cpu64
= 1;
1880 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1884 cpu_arch_flags
.bitfield
.cpu64
= 0;
1885 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1887 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1889 as_bad (_("64bit mode not supported on this CPU."));
1891 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1893 as_bad (_("32bit mode not supported on this CPU."));
1895 stackop_size
= '\0';
1899 set_16bit_gcc_code_flag (int new_code_flag
)
1901 flag_code
= (enum flag_code
) new_code_flag
;
1902 if (flag_code
!= CODE_16BIT
)
1904 cpu_arch_flags
.bitfield
.cpu64
= 0;
1905 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1906 stackop_size
= LONG_MNEM_SUFFIX
;
1910 set_intel_syntax (int syntax_flag
)
1912 /* Find out if register prefixing is specified. */
1913 int ask_naked_reg
= 0;
1916 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1918 char *string
= input_line_pointer
;
1919 int e
= get_symbol_end ();
1921 if (strcmp (string
, "prefix") == 0)
1923 else if (strcmp (string
, "noprefix") == 0)
1926 as_bad (_("bad argument to syntax directive."));
1927 *input_line_pointer
= e
;
1929 demand_empty_rest_of_line ();
1931 intel_syntax
= syntax_flag
;
1933 if (ask_naked_reg
== 0)
1934 allow_naked_reg
= (intel_syntax
1935 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1937 allow_naked_reg
= (ask_naked_reg
< 0);
1939 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1941 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1942 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1943 register_prefix
= allow_naked_reg
? "" : "%";
1947 set_intel_mnemonic (int mnemonic_flag
)
1949 intel_mnemonic
= mnemonic_flag
;
1953 set_allow_index_reg (int flag
)
1955 allow_index_reg
= flag
;
1959 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1963 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1965 char *string
= input_line_pointer
;
1966 int e
= get_symbol_end ();
1968 if (strcmp (string
, "none") == 0)
1969 sse_check
= sse_check_none
;
1970 else if (strcmp (string
, "warning") == 0)
1971 sse_check
= sse_check_warning
;
1972 else if (strcmp (string
, "error") == 0)
1973 sse_check
= sse_check_error
;
1975 as_bad (_("bad argument to sse_check directive."));
1976 *input_line_pointer
= e
;
1979 as_bad (_("missing argument for sse_check directive"));
1981 demand_empty_rest_of_line ();
1985 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1986 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1989 static const char *arch
;
1991 /* Intel LIOM is only supported on ELF. */
1997 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1998 use default_arch. */
1999 arch
= cpu_arch_name
;
2001 arch
= default_arch
;
2004 /* If we are targeting Intel L1OM, we must enable it. */
2005 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2006 || new_flag
.bitfield
.cpul1om
)
2009 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2014 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2018 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2020 char *string
= input_line_pointer
;
2021 int e
= get_symbol_end ();
2023 i386_cpu_flags flags
;
2025 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2027 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2029 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2033 cpu_arch_name
= cpu_arch
[i
].name
;
2034 cpu_sub_arch_name
= NULL
;
2035 cpu_arch_flags
= cpu_arch
[i
].flags
;
2036 if (flag_code
== CODE_64BIT
)
2038 cpu_arch_flags
.bitfield
.cpu64
= 1;
2039 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2043 cpu_arch_flags
.bitfield
.cpu64
= 0;
2044 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2046 cpu_arch_isa
= cpu_arch
[i
].type
;
2047 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2048 if (!cpu_arch_tune_set
)
2050 cpu_arch_tune
= cpu_arch_isa
;
2051 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2056 if (strncmp (string
+ 1, "no", 2))
2057 flags
= cpu_flags_or (cpu_arch_flags
,
2060 flags
= cpu_flags_and_not (cpu_arch_flags
,
2062 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2064 if (cpu_sub_arch_name
)
2066 char *name
= cpu_sub_arch_name
;
2067 cpu_sub_arch_name
= concat (name
,
2069 (const char *) NULL
);
2073 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2074 cpu_arch_flags
= flags
;
2076 *input_line_pointer
= e
;
2077 demand_empty_rest_of_line ();
2081 if (i
>= ARRAY_SIZE (cpu_arch
))
2082 as_bad (_("no such architecture: `%s'"), string
);
2084 *input_line_pointer
= e
;
2087 as_bad (_("missing cpu architecture"));
2089 no_cond_jump_promotion
= 0;
2090 if (*input_line_pointer
== ','
2091 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2093 char *string
= ++input_line_pointer
;
2094 int e
= get_symbol_end ();
2096 if (strcmp (string
, "nojumps") == 0)
2097 no_cond_jump_promotion
= 1;
2098 else if (strcmp (string
, "jumps") == 0)
2101 as_bad (_("no such architecture modifier: `%s'"), string
);
2103 *input_line_pointer
= e
;
2106 demand_empty_rest_of_line ();
2109 enum bfd_architecture
2112 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2114 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2115 || flag_code
!= CODE_64BIT
)
2116 as_fatal (_("Intel L1OM is 64bit ELF only"));
2117 return bfd_arch_l1om
;
2120 return bfd_arch_i386
;
2126 if (!strcmp (default_arch
, "x86_64"))
2128 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2130 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2131 as_fatal (_("Intel L1OM is 64bit ELF only"));
2132 return bfd_mach_l1om
;
2135 return bfd_mach_x86_64
;
2137 else if (!strcmp (default_arch
, "i386"))
2138 return bfd_mach_i386_i386
;
2140 as_fatal (_("Unknown architecture"));
2146 const char *hash_err
;
2148 /* Initialize op_hash hash table. */
2149 op_hash
= hash_new ();
2152 const insn_template
*optab
;
2153 templates
*core_optab
;
2155 /* Setup for loop. */
2157 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2158 core_optab
->start
= optab
;
2163 if (optab
->name
== NULL
2164 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2166 /* different name --> ship out current template list;
2167 add to hash table; & begin anew. */
2168 core_optab
->end
= optab
;
2169 hash_err
= hash_insert (op_hash
,
2171 (void *) core_optab
);
2174 as_fatal (_("Internal Error: Can't hash %s: %s"),
2178 if (optab
->name
== NULL
)
2180 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2181 core_optab
->start
= optab
;
2186 /* Initialize reg_hash hash table. */
2187 reg_hash
= hash_new ();
2189 const reg_entry
*regtab
;
2190 unsigned int regtab_size
= i386_regtab_size
;
2192 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2194 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2196 as_fatal (_("Internal Error: Can't hash %s: %s"),
2202 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2207 for (c
= 0; c
< 256; c
++)
2212 mnemonic_chars
[c
] = c
;
2213 register_chars
[c
] = c
;
2214 operand_chars
[c
] = c
;
2216 else if (ISLOWER (c
))
2218 mnemonic_chars
[c
] = c
;
2219 register_chars
[c
] = c
;
2220 operand_chars
[c
] = c
;
2222 else if (ISUPPER (c
))
2224 mnemonic_chars
[c
] = TOLOWER (c
);
2225 register_chars
[c
] = mnemonic_chars
[c
];
2226 operand_chars
[c
] = c
;
2229 if (ISALPHA (c
) || ISDIGIT (c
))
2230 identifier_chars
[c
] = c
;
2233 identifier_chars
[c
] = c
;
2234 operand_chars
[c
] = c
;
2239 identifier_chars
['@'] = '@';
2242 identifier_chars
['?'] = '?';
2243 operand_chars
['?'] = '?';
2245 digit_chars
['-'] = '-';
2246 mnemonic_chars
['_'] = '_';
2247 mnemonic_chars
['-'] = '-';
2248 mnemonic_chars
['.'] = '.';
2249 identifier_chars
['_'] = '_';
2250 identifier_chars
['.'] = '.';
2252 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2253 operand_chars
[(unsigned char) *p
] = *p
;
2256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2259 record_alignment (text_section
, 2);
2260 record_alignment (data_section
, 2);
2261 record_alignment (bss_section
, 2);
2265 if (flag_code
== CODE_64BIT
)
2267 x86_dwarf2_return_column
= 16;
2268 x86_cie_data_alignment
= -8;
2272 x86_dwarf2_return_column
= 8;
2273 x86_cie_data_alignment
= -4;
2278 i386_print_statistics (FILE *file
)
2280 hash_print_statistics (file
, "i386 opcode", op_hash
);
2281 hash_print_statistics (file
, "i386 register", reg_hash
);
2286 /* Debugging routines for md_assemble. */
2287 static void pte (insn_template
*);
2288 static void pt (i386_operand_type
);
2289 static void pe (expressionS
*);
2290 static void ps (symbolS
*);
2293 pi (char *line
, i386_insn
*x
)
2297 fprintf (stdout
, "%s: template ", line
);
2299 fprintf (stdout
, " address: base %s index %s scale %x\n",
2300 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2301 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2302 x
->log2_scale_factor
);
2303 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2304 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2305 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2306 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2307 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2308 (x
->rex
& REX_W
) != 0,
2309 (x
->rex
& REX_R
) != 0,
2310 (x
->rex
& REX_X
) != 0,
2311 (x
->rex
& REX_B
) != 0);
2312 for (i
= 0; i
< x
->operands
; i
++)
2314 fprintf (stdout
, " #%d: ", i
+ 1);
2316 fprintf (stdout
, "\n");
2317 if (x
->types
[i
].bitfield
.reg8
2318 || x
->types
[i
].bitfield
.reg16
2319 || x
->types
[i
].bitfield
.reg32
2320 || x
->types
[i
].bitfield
.reg64
2321 || x
->types
[i
].bitfield
.regmmx
2322 || x
->types
[i
].bitfield
.regxmm
2323 || x
->types
[i
].bitfield
.regymm
2324 || x
->types
[i
].bitfield
.sreg2
2325 || x
->types
[i
].bitfield
.sreg3
2326 || x
->types
[i
].bitfield
.control
2327 || x
->types
[i
].bitfield
.debug
2328 || x
->types
[i
].bitfield
.test
)
2329 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2330 if (operand_type_check (x
->types
[i
], imm
))
2332 if (operand_type_check (x
->types
[i
], disp
))
2333 pe (x
->op
[i
].disps
);
2338 pte (insn_template
*t
)
2341 fprintf (stdout
, " %d operands ", t
->operands
);
2342 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2343 if (t
->extension_opcode
!= None
)
2344 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2345 if (t
->opcode_modifier
.d
)
2346 fprintf (stdout
, "D");
2347 if (t
->opcode_modifier
.w
)
2348 fprintf (stdout
, "W");
2349 fprintf (stdout
, "\n");
2350 for (i
= 0; i
< t
->operands
; i
++)
2352 fprintf (stdout
, " #%d type ", i
+ 1);
2353 pt (t
->operand_types
[i
]);
2354 fprintf (stdout
, "\n");
2361 fprintf (stdout
, " operation %d\n", e
->X_op
);
2362 fprintf (stdout
, " add_number %ld (%lx)\n",
2363 (long) e
->X_add_number
, (long) e
->X_add_number
);
2364 if (e
->X_add_symbol
)
2366 fprintf (stdout
, " add_symbol ");
2367 ps (e
->X_add_symbol
);
2368 fprintf (stdout
, "\n");
2372 fprintf (stdout
, " op_symbol ");
2373 ps (e
->X_op_symbol
);
2374 fprintf (stdout
, "\n");
2381 fprintf (stdout
, "%s type %s%s",
2383 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2384 segment_name (S_GET_SEGMENT (s
)));
2387 static struct type_name
2389 i386_operand_type mask
;
2392 const type_names
[] =
2394 { OPERAND_TYPE_REG8
, "r8" },
2395 { OPERAND_TYPE_REG16
, "r16" },
2396 { OPERAND_TYPE_REG32
, "r32" },
2397 { OPERAND_TYPE_REG64
, "r64" },
2398 { OPERAND_TYPE_IMM8
, "i8" },
2399 { OPERAND_TYPE_IMM8
, "i8s" },
2400 { OPERAND_TYPE_IMM16
, "i16" },
2401 { OPERAND_TYPE_IMM32
, "i32" },
2402 { OPERAND_TYPE_IMM32S
, "i32s" },
2403 { OPERAND_TYPE_IMM64
, "i64" },
2404 { OPERAND_TYPE_IMM1
, "i1" },
2405 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2406 { OPERAND_TYPE_DISP8
, "d8" },
2407 { OPERAND_TYPE_DISP16
, "d16" },
2408 { OPERAND_TYPE_DISP32
, "d32" },
2409 { OPERAND_TYPE_DISP32S
, "d32s" },
2410 { OPERAND_TYPE_DISP64
, "d64" },
2411 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2412 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2413 { OPERAND_TYPE_CONTROL
, "control reg" },
2414 { OPERAND_TYPE_TEST
, "test reg" },
2415 { OPERAND_TYPE_DEBUG
, "debug reg" },
2416 { OPERAND_TYPE_FLOATREG
, "FReg" },
2417 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2418 { OPERAND_TYPE_SREG2
, "SReg2" },
2419 { OPERAND_TYPE_SREG3
, "SReg3" },
2420 { OPERAND_TYPE_ACC
, "Acc" },
2421 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2422 { OPERAND_TYPE_REGMMX
, "rMMX" },
2423 { OPERAND_TYPE_REGXMM
, "rXMM" },
2424 { OPERAND_TYPE_REGYMM
, "rYMM" },
2425 { OPERAND_TYPE_ESSEG
, "es" },
2429 pt (i386_operand_type t
)
2432 i386_operand_type a
;
2434 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2436 a
= operand_type_and (t
, type_names
[j
].mask
);
2437 if (!operand_type_all_zero (&a
))
2438 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2443 #endif /* DEBUG386 */
2445 static bfd_reloc_code_real_type
2446 reloc (unsigned int size
,
2449 bfd_reloc_code_real_type other
)
2451 if (other
!= NO_RELOC
)
2453 reloc_howto_type
*reloc
;
2458 case BFD_RELOC_X86_64_GOT32
:
2459 return BFD_RELOC_X86_64_GOT64
;
2461 case BFD_RELOC_X86_64_PLTOFF64
:
2462 return BFD_RELOC_X86_64_PLTOFF64
;
2464 case BFD_RELOC_X86_64_GOTPC32
:
2465 other
= BFD_RELOC_X86_64_GOTPC64
;
2467 case BFD_RELOC_X86_64_GOTPCREL
:
2468 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2470 case BFD_RELOC_X86_64_TPOFF32
:
2471 other
= BFD_RELOC_X86_64_TPOFF64
;
2473 case BFD_RELOC_X86_64_DTPOFF32
:
2474 other
= BFD_RELOC_X86_64_DTPOFF64
;
2480 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2481 if (size
== 4 && flag_code
!= CODE_64BIT
)
2484 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2486 as_bad (_("unknown relocation (%u)"), other
);
2487 else if (size
!= bfd_get_reloc_size (reloc
))
2488 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2489 bfd_get_reloc_size (reloc
),
2491 else if (pcrel
&& !reloc
->pc_relative
)
2492 as_bad (_("non-pc-relative relocation for pc-relative field"));
2493 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2495 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2497 as_bad (_("relocated field and relocation type differ in signedness"));
2506 as_bad (_("there are no unsigned pc-relative relocations"));
2509 case 1: return BFD_RELOC_8_PCREL
;
2510 case 2: return BFD_RELOC_16_PCREL
;
2511 case 4: return BFD_RELOC_32_PCREL
;
2512 case 8: return BFD_RELOC_64_PCREL
;
2514 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2521 case 4: return BFD_RELOC_X86_64_32S
;
2526 case 1: return BFD_RELOC_8
;
2527 case 2: return BFD_RELOC_16
;
2528 case 4: return BFD_RELOC_32
;
2529 case 8: return BFD_RELOC_64
;
2531 as_bad (_("cannot do %s %u byte relocation"),
2532 sign
> 0 ? "signed" : "unsigned", size
);
2538 /* Here we decide which fixups can be adjusted to make them relative to
2539 the beginning of the section instead of the symbol. Basically we need
2540 to make sure that the dynamic relocations are done correctly, so in
2541 some cases we force the original symbol to be used. */
2544 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2550 /* Don't adjust pc-relative references to merge sections in 64-bit
2552 if (use_rela_relocations
2553 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2557 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2558 and changed later by validate_fix. */
2559 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2560 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2563 /* adjust_reloc_syms doesn't know about the GOT. */
2564 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2565 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2566 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2590 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2591 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2598 intel_float_operand (const char *mnemonic
)
2600 /* Note that the value returned is meaningful only for opcodes with (memory)
2601 operands, hence the code here is free to improperly handle opcodes that
2602 have no operands (for better performance and smaller code). */
2604 if (mnemonic
[0] != 'f')
2605 return 0; /* non-math */
2607 switch (mnemonic
[1])
2609 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2610 the fs segment override prefix not currently handled because no
2611 call path can make opcodes without operands get here */
2613 return 2 /* integer op */;
2615 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2616 return 3; /* fldcw/fldenv */
2619 if (mnemonic
[2] != 'o' /* fnop */)
2620 return 3; /* non-waiting control op */
2623 if (mnemonic
[2] == 's')
2624 return 3; /* frstor/frstpm */
2627 if (mnemonic
[2] == 'a')
2628 return 3; /* fsave */
2629 if (mnemonic
[2] == 't')
2631 switch (mnemonic
[3])
2633 case 'c': /* fstcw */
2634 case 'd': /* fstdw */
2635 case 'e': /* fstenv */
2636 case 's': /* fsts[gw] */
2642 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2643 return 0; /* fxsave/fxrstor are not really math ops */
2650 /* Build the VEX prefix. */
2653 build_vex_prefix (const insn_template
*t
)
2655 unsigned int register_specifier
;
2656 unsigned int implied_prefix
;
2657 unsigned int vector_length
;
2659 /* Check register specifier. */
2660 if (i
.vex
.register_specifier
)
2662 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2663 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2664 register_specifier
+= 8;
2665 register_specifier
= ~register_specifier
& 0xf;
2668 register_specifier
= 0xf;
2670 /* Use 2-byte VEX prefix by swappping destination and source
2673 && i
.operands
== i
.reg_operands
2674 && i
.tm
.opcode_modifier
.vex0f
2675 && i
.tm
.opcode_modifier
.s
2678 unsigned int xchg
= i
.operands
- 1;
2679 union i386_op temp_op
;
2680 i386_operand_type temp_type
;
2682 temp_type
= i
.types
[xchg
];
2683 i
.types
[xchg
] = i
.types
[0];
2684 i
.types
[0] = temp_type
;
2685 temp_op
= i
.op
[xchg
];
2686 i
.op
[xchg
] = i
.op
[0];
2689 gas_assert (i
.rm
.mode
== 3);
2693 i
.rm
.regmem
= i
.rm
.reg
;
2696 /* Use the next insn. */
2700 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2702 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2707 case DATA_PREFIX_OPCODE
:
2710 case REPE_PREFIX_OPCODE
:
2713 case REPNE_PREFIX_OPCODE
:
2720 /* Use 2-byte VEX prefix if possible. */
2721 if (i
.tm
.opcode_modifier
.vex0f
2722 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2724 /* 2-byte VEX prefix. */
2728 i
.vex
.bytes
[0] = 0xc5;
2730 /* Check the REX.R bit. */
2731 r
= (i
.rex
& REX_R
) ? 0 : 1;
2732 i
.vex
.bytes
[1] = (r
<< 7
2733 | register_specifier
<< 3
2734 | vector_length
<< 2
2739 /* 3-byte VEX prefix. */
2743 i
.vex
.bytes
[0] = 0xc4;
2745 if (i
.tm
.opcode_modifier
.vex0f
)
2747 else if (i
.tm
.opcode_modifier
.vex0f38
)
2749 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2751 else if (i
.tm
.opcode_modifier
.xop09
)
2754 i
.vex
.bytes
[0] = 0x8f;
2756 else if (i
.tm
.opcode_modifier
.xop0a
)
2759 i
.vex
.bytes
[0] = 0x8f;
2764 /* The high 3 bits of the second VEX byte are 1's compliment
2765 of RXB bits from REX. */
2766 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2768 /* Check the REX.W bit. */
2769 w
= (i
.rex
& REX_W
) ? 1 : 0;
2770 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2775 if (i
.tm
.opcode_modifier
.vexw1
)
2779 i
.vex
.bytes
[2] = (w
<< 7
2780 | register_specifier
<< 3
2781 | vector_length
<< 2
2787 process_immext (void)
2791 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2793 /* SSE3 Instructions have the fixed operands with an opcode
2794 suffix which is coded in the same place as an 8-bit immediate
2795 field would be. Here we check those operands and remove them
2799 for (x
= 0; x
< i
.operands
; x
++)
2800 if (i
.op
[x
].regs
->reg_num
!= x
)
2801 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2802 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2808 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2809 which is coded in the same place as an 8-bit immediate field
2810 would be. Here we fake an 8-bit immediate operand from the
2811 opcode suffix stored in tm.extension_opcode.
2813 AVX instructions also use this encoding, for some of
2814 3 argument instructions. */
2816 gas_assert (i
.imm_operands
== 0
2818 || (i
.tm
.opcode_modifier
.vex
2819 && i
.operands
<= 4)));
2821 exp
= &im_expressions
[i
.imm_operands
++];
2822 i
.op
[i
.operands
].imms
= exp
;
2823 i
.types
[i
.operands
] = imm8
;
2825 exp
->X_op
= O_constant
;
2826 exp
->X_add_number
= i
.tm
.extension_opcode
;
2827 i
.tm
.extension_opcode
= None
;
2830 /* This is the guts of the machine-dependent assembler. LINE points to a
2831 machine dependent instruction. This function is supposed to emit
2832 the frags/bytes it assembles to. */
2835 md_assemble (char *line
)
2838 char mnemonic
[MAX_MNEM_SIZE
];
2839 const insn_template
*t
;
2841 /* Initialize globals. */
2842 memset (&i
, '\0', sizeof (i
));
2843 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2844 i
.reloc
[j
] = NO_RELOC
;
2845 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2846 memset (im_expressions
, '\0', sizeof (im_expressions
));
2847 save_stack_p
= save_stack
;
2849 /* First parse an instruction mnemonic & call i386_operand for the operands.
2850 We assume that the scrubber has arranged it so that line[0] is the valid
2851 start of a (possibly prefixed) mnemonic. */
2853 line
= parse_insn (line
, mnemonic
);
2857 line
= parse_operands (line
, mnemonic
);
2862 /* Now we've parsed the mnemonic into a set of templates, and have the
2863 operands at hand. */
2865 /* All intel opcodes have reversed operands except for "bound" and
2866 "enter". We also don't reverse intersegment "jmp" and "call"
2867 instructions with 2 immediate operands so that the immediate segment
2868 precedes the offset, as it does when in AT&T mode. */
2871 && (strcmp (mnemonic
, "bound") != 0)
2872 && (strcmp (mnemonic
, "invlpga") != 0)
2873 && !(operand_type_check (i
.types
[0], imm
)
2874 && operand_type_check (i
.types
[1], imm
)))
2877 /* The order of the immediates should be reversed
2878 for 2 immediates extrq and insertq instructions */
2879 if (i
.imm_operands
== 2
2880 && (strcmp (mnemonic
, "extrq") == 0
2881 || strcmp (mnemonic
, "insertq") == 0))
2882 swap_2_operands (0, 1);
2887 /* Don't optimize displacement for movabs since it only takes 64bit
2890 && (flag_code
!= CODE_64BIT
2891 || strcmp (mnemonic
, "movabs") != 0))
2894 /* Next, we find a template that matches the given insn,
2895 making sure the overlap of the given operands types is consistent
2896 with the template operand types. */
2898 if (!(t
= match_template ()))
2901 if (sse_check
!= sse_check_none
2902 && !i
.tm
.opcode_modifier
.noavx
2903 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2904 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2905 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2906 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2907 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2908 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2910 (sse_check
== sse_check_warning
2912 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2915 /* Zap movzx and movsx suffix. The suffix has been set from
2916 "word ptr" or "byte ptr" on the source operand in Intel syntax
2917 or extracted from mnemonic in AT&T syntax. But we'll use
2918 the destination register to choose the suffix for encoding. */
2919 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2921 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2922 there is no suffix, the default will be byte extension. */
2923 if (i
.reg_operands
!= 2
2926 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2931 if (i
.tm
.opcode_modifier
.fwait
)
2932 if (!add_prefix (FWAIT_OPCODE
))
2935 /* Check for lock without a lockable instruction. Destination operand
2936 must be memory unless it is xchg (0x86). */
2937 if (i
.prefix
[LOCK_PREFIX
]
2938 && (!i
.tm
.opcode_modifier
.islockable
2939 || i
.mem_operands
== 0
2940 || (i
.tm
.base_opcode
!= 0x86
2941 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2943 as_bad (_("expecting lockable instruction after `lock'"));
2947 /* Check string instruction segment overrides. */
2948 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2950 if (!check_string ())
2952 i
.disp_operands
= 0;
2955 if (!process_suffix ())
2958 /* Update operand types. */
2959 for (j
= 0; j
< i
.operands
; j
++)
2960 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2962 /* Make still unresolved immediate matches conform to size of immediate
2963 given in i.suffix. */
2964 if (!finalize_imm ())
2967 if (i
.types
[0].bitfield
.imm1
)
2968 i
.imm_operands
= 0; /* kludge for shift insns. */
2970 /* We only need to check those implicit registers for instructions
2971 with 3 operands or less. */
2972 if (i
.operands
<= 3)
2973 for (j
= 0; j
< i
.operands
; j
++)
2974 if (i
.types
[j
].bitfield
.inoutportreg
2975 || i
.types
[j
].bitfield
.shiftcount
2976 || i
.types
[j
].bitfield
.acc
2977 || i
.types
[j
].bitfield
.floatacc
)
2980 /* ImmExt should be processed after SSE2AVX. */
2981 if (!i
.tm
.opcode_modifier
.sse2avx
2982 && i
.tm
.opcode_modifier
.immext
)
2985 /* For insns with operands there are more diddles to do to the opcode. */
2988 if (!process_operands ())
2991 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2993 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2994 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2997 if (i
.tm
.opcode_modifier
.vex
)
2998 build_vex_prefix (t
);
3000 /* Handle conversion of 'int $3' --> special int3 insn. */
3001 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
3003 i
.tm
.base_opcode
= INT3_OPCODE
;
3007 if ((i
.tm
.opcode_modifier
.jump
3008 || i
.tm
.opcode_modifier
.jumpbyte
3009 || i
.tm
.opcode_modifier
.jumpdword
)
3010 && i
.op
[0].disps
->X_op
== O_constant
)
3012 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3013 the absolute address given by the constant. Since ix86 jumps and
3014 calls are pc relative, we need to generate a reloc. */
3015 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3016 i
.op
[0].disps
->X_op
= O_symbol
;
3019 if (i
.tm
.opcode_modifier
.rex64
)
3022 /* For 8 bit registers we need an empty rex prefix. Also if the
3023 instruction already has a prefix, we need to convert old
3024 registers to new ones. */
3026 if ((i
.types
[0].bitfield
.reg8
3027 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3028 || (i
.types
[1].bitfield
.reg8
3029 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3030 || ((i
.types
[0].bitfield
.reg8
3031 || i
.types
[1].bitfield
.reg8
)
3036 i
.rex
|= REX_OPCODE
;
3037 for (x
= 0; x
< 2; x
++)
3039 /* Look for 8 bit operand that uses old registers. */
3040 if (i
.types
[x
].bitfield
.reg8
3041 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3043 /* In case it is "hi" register, give up. */
3044 if (i
.op
[x
].regs
->reg_num
> 3)
3045 as_bad (_("can't encode register '%s%s' in an "
3046 "instruction requiring REX prefix."),
3047 register_prefix
, i
.op
[x
].regs
->reg_name
);
3049 /* Otherwise it is equivalent to the extended register.
3050 Since the encoding doesn't change this is merely
3051 cosmetic cleanup for debug output. */
3053 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3059 add_prefix (REX_OPCODE
| i
.rex
);
3061 /* We are ready to output the insn. */
3066 parse_insn (char *line
, char *mnemonic
)
3069 char *token_start
= l
;
3072 const insn_template
*t
;
3075 /* Non-zero if we found a prefix only acceptable with string insns. */
3076 const char *expecting_string_instruction
= NULL
;
3081 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3086 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3088 as_bad (_("no such instruction: `%s'"), token_start
);
3093 if (!is_space_char (*l
)
3094 && *l
!= END_OF_INSN
3096 || (*l
!= PREFIX_SEPARATOR
3099 as_bad (_("invalid character %s in mnemonic"),
3100 output_invalid (*l
));
3103 if (token_start
== l
)
3105 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3106 as_bad (_("expecting prefix; got nothing"));
3108 as_bad (_("expecting mnemonic; got nothing"));
3112 /* Look up instruction (or prefix) via hash table. */
3113 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3115 if (*l
!= END_OF_INSN
3116 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3117 && current_templates
3118 && current_templates
->start
->opcode_modifier
.isprefix
)
3120 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3122 as_bad ((flag_code
!= CODE_64BIT
3123 ? _("`%s' is only supported in 64-bit mode")
3124 : _("`%s' is not supported in 64-bit mode")),
3125 current_templates
->start
->name
);
3128 /* If we are in 16-bit mode, do not allow addr16 or data16.
3129 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3130 if ((current_templates
->start
->opcode_modifier
.size16
3131 || current_templates
->start
->opcode_modifier
.size32
)
3132 && flag_code
!= CODE_64BIT
3133 && (current_templates
->start
->opcode_modifier
.size32
3134 ^ (flag_code
== CODE_16BIT
)))
3136 as_bad (_("redundant %s prefix"),
3137 current_templates
->start
->name
);
3140 /* Add prefix, checking for repeated prefixes. */
3141 switch (add_prefix (current_templates
->start
->base_opcode
))
3146 expecting_string_instruction
= current_templates
->start
->name
;
3151 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3158 if (!current_templates
)
3160 /* Check if we should swap operand in encoding. */
3161 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3167 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3170 if (!current_templates
)
3173 /* See if we can get a match by trimming off a suffix. */
3176 case WORD_MNEM_SUFFIX
:
3177 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3178 i
.suffix
= SHORT_MNEM_SUFFIX
;
3180 case BYTE_MNEM_SUFFIX
:
3181 case QWORD_MNEM_SUFFIX
:
3182 i
.suffix
= mnem_p
[-1];
3184 current_templates
= (const templates
*) hash_find (op_hash
,
3187 case SHORT_MNEM_SUFFIX
:
3188 case LONG_MNEM_SUFFIX
:
3191 i
.suffix
= mnem_p
[-1];
3193 current_templates
= (const templates
*) hash_find (op_hash
,
3202 if (intel_float_operand (mnemonic
) == 1)
3203 i
.suffix
= SHORT_MNEM_SUFFIX
;
3205 i
.suffix
= LONG_MNEM_SUFFIX
;
3207 current_templates
= (const templates
*) hash_find (op_hash
,
3212 if (!current_templates
)
3214 as_bad (_("no such instruction: `%s'"), token_start
);
3219 if (current_templates
->start
->opcode_modifier
.jump
3220 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3222 /* Check for a branch hint. We allow ",pt" and ",pn" for
3223 predict taken and predict not taken respectively.
3224 I'm not sure that branch hints actually do anything on loop
3225 and jcxz insns (JumpByte) for current Pentium4 chips. They
3226 may work in the future and it doesn't hurt to accept them
3228 if (l
[0] == ',' && l
[1] == 'p')
3232 if (!add_prefix (DS_PREFIX_OPCODE
))
3236 else if (l
[2] == 'n')
3238 if (!add_prefix (CS_PREFIX_OPCODE
))
3244 /* Any other comma loses. */
3247 as_bad (_("invalid character %s in mnemonic"),
3248 output_invalid (*l
));
3252 /* Check if instruction is supported on specified architecture. */
3254 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3256 supported
|= cpu_flags_match (t
);
3257 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3261 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3263 as_bad (flag_code
== CODE_64BIT
3264 ? _("`%s' is not supported in 64-bit mode")
3265 : _("`%s' is only supported in 64-bit mode"),
3266 current_templates
->start
->name
);
3269 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3271 as_bad (_("`%s' is not supported on `%s%s'"),
3272 current_templates
->start
->name
,
3273 cpu_arch_name
? cpu_arch_name
: default_arch
,
3274 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3279 if (!cpu_arch_flags
.bitfield
.cpui386
3280 && (flag_code
!= CODE_16BIT
))
3282 as_warn (_("use .code16 to ensure correct addressing mode"));
3285 /* Check for rep/repne without a string instruction. */
3286 if (expecting_string_instruction
)
3288 static templates override
;
3290 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3291 if (t
->opcode_modifier
.isstring
)
3293 if (t
>= current_templates
->end
)
3295 as_bad (_("expecting string instruction after `%s'"),
3296 expecting_string_instruction
);
3299 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3300 if (!t
->opcode_modifier
.isstring
)
3303 current_templates
= &override
;
3310 parse_operands (char *l
, const char *mnemonic
)
3314 /* 1 if operand is pending after ','. */
3315 unsigned int expecting_operand
= 0;
3317 /* Non-zero if operand parens not balanced. */
3318 unsigned int paren_not_balanced
;
3320 while (*l
!= END_OF_INSN
)
3322 /* Skip optional white space before operand. */
3323 if (is_space_char (*l
))
3325 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3327 as_bad (_("invalid character %s before operand %d"),
3328 output_invalid (*l
),
3332 token_start
= l
; /* after white space */
3333 paren_not_balanced
= 0;
3334 while (paren_not_balanced
|| *l
!= ',')
3336 if (*l
== END_OF_INSN
)
3338 if (paren_not_balanced
)
3341 as_bad (_("unbalanced parenthesis in operand %d."),
3344 as_bad (_("unbalanced brackets in operand %d."),
3349 break; /* we are done */
3351 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3353 as_bad (_("invalid character %s in operand %d"),
3354 output_invalid (*l
),
3361 ++paren_not_balanced
;
3363 --paren_not_balanced
;
3368 ++paren_not_balanced
;
3370 --paren_not_balanced
;
3374 if (l
!= token_start
)
3375 { /* Yes, we've read in another operand. */
3376 unsigned int operand_ok
;
3377 this_operand
= i
.operands
++;
3378 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3379 if (i
.operands
> MAX_OPERANDS
)
3381 as_bad (_("spurious operands; (%d operands/instruction max)"),
3385 /* Now parse operand adding info to 'i' as we go along. */
3386 END_STRING_AND_SAVE (l
);
3390 i386_intel_operand (token_start
,
3391 intel_float_operand (mnemonic
));
3393 operand_ok
= i386_att_operand (token_start
);
3395 RESTORE_END_STRING (l
);
3401 if (expecting_operand
)
3403 expecting_operand_after_comma
:
3404 as_bad (_("expecting operand after ','; got nothing"));
3409 as_bad (_("expecting operand before ','; got nothing"));
3414 /* Now *l must be either ',' or END_OF_INSN. */
3417 if (*++l
== END_OF_INSN
)
3419 /* Just skip it, if it's \n complain. */
3420 goto expecting_operand_after_comma
;
3422 expecting_operand
= 1;
3429 swap_2_operands (int xchg1
, int xchg2
)
3431 union i386_op temp_op
;
3432 i386_operand_type temp_type
;
3433 enum bfd_reloc_code_real temp_reloc
;
3435 temp_type
= i
.types
[xchg2
];
3436 i
.types
[xchg2
] = i
.types
[xchg1
];
3437 i
.types
[xchg1
] = temp_type
;
3438 temp_op
= i
.op
[xchg2
];
3439 i
.op
[xchg2
] = i
.op
[xchg1
];
3440 i
.op
[xchg1
] = temp_op
;
3441 temp_reloc
= i
.reloc
[xchg2
];
3442 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3443 i
.reloc
[xchg1
] = temp_reloc
;
3447 swap_operands (void)
3453 swap_2_operands (1, i
.operands
- 2);
3456 swap_2_operands (0, i
.operands
- 1);
3462 if (i
.mem_operands
== 2)
3464 const seg_entry
*temp_seg
;
3465 temp_seg
= i
.seg
[0];
3466 i
.seg
[0] = i
.seg
[1];
3467 i
.seg
[1] = temp_seg
;
3471 /* Try to ensure constant immediates are represented in the smallest
3476 char guess_suffix
= 0;
3480 guess_suffix
= i
.suffix
;
3481 else if (i
.reg_operands
)
3483 /* Figure out a suffix from the last register operand specified.
3484 We can't do this properly yet, ie. excluding InOutPortReg,
3485 but the following works for instructions with immediates.
3486 In any case, we can't set i.suffix yet. */
3487 for (op
= i
.operands
; --op
>= 0;)
3488 if (i
.types
[op
].bitfield
.reg8
)
3490 guess_suffix
= BYTE_MNEM_SUFFIX
;
3493 else if (i
.types
[op
].bitfield
.reg16
)
3495 guess_suffix
= WORD_MNEM_SUFFIX
;
3498 else if (i
.types
[op
].bitfield
.reg32
)
3500 guess_suffix
= LONG_MNEM_SUFFIX
;
3503 else if (i
.types
[op
].bitfield
.reg64
)
3505 guess_suffix
= QWORD_MNEM_SUFFIX
;
3509 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3510 guess_suffix
= WORD_MNEM_SUFFIX
;
3512 for (op
= i
.operands
; --op
>= 0;)
3513 if (operand_type_check (i
.types
[op
], imm
))
3515 switch (i
.op
[op
].imms
->X_op
)
3518 /* If a suffix is given, this operand may be shortened. */
3519 switch (guess_suffix
)
3521 case LONG_MNEM_SUFFIX
:
3522 i
.types
[op
].bitfield
.imm32
= 1;
3523 i
.types
[op
].bitfield
.imm64
= 1;
3525 case WORD_MNEM_SUFFIX
:
3526 i
.types
[op
].bitfield
.imm16
= 1;
3527 i
.types
[op
].bitfield
.imm32
= 1;
3528 i
.types
[op
].bitfield
.imm32s
= 1;
3529 i
.types
[op
].bitfield
.imm64
= 1;
3531 case BYTE_MNEM_SUFFIX
:
3532 i
.types
[op
].bitfield
.imm8
= 1;
3533 i
.types
[op
].bitfield
.imm8s
= 1;
3534 i
.types
[op
].bitfield
.imm16
= 1;
3535 i
.types
[op
].bitfield
.imm32
= 1;
3536 i
.types
[op
].bitfield
.imm32s
= 1;
3537 i
.types
[op
].bitfield
.imm64
= 1;
3541 /* If this operand is at most 16 bits, convert it
3542 to a signed 16 bit number before trying to see
3543 whether it will fit in an even smaller size.
3544 This allows a 16-bit operand such as $0xffe0 to
3545 be recognised as within Imm8S range. */
3546 if ((i
.types
[op
].bitfield
.imm16
)
3547 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3549 i
.op
[op
].imms
->X_add_number
=
3550 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3552 if ((i
.types
[op
].bitfield
.imm32
)
3553 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3556 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3557 ^ ((offsetT
) 1 << 31))
3558 - ((offsetT
) 1 << 31));
3561 = operand_type_or (i
.types
[op
],
3562 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3564 /* We must avoid matching of Imm32 templates when 64bit
3565 only immediate is available. */
3566 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3567 i
.types
[op
].bitfield
.imm32
= 0;
3574 /* Symbols and expressions. */
3576 /* Convert symbolic operand to proper sizes for matching, but don't
3577 prevent matching a set of insns that only supports sizes other
3578 than those matching the insn suffix. */
3580 i386_operand_type mask
, allowed
;
3581 const insn_template
*t
;
3583 operand_type_set (&mask
, 0);
3584 operand_type_set (&allowed
, 0);
3586 for (t
= current_templates
->start
;
3587 t
< current_templates
->end
;
3589 allowed
= operand_type_or (allowed
,
3590 t
->operand_types
[op
]);
3591 switch (guess_suffix
)
3593 case QWORD_MNEM_SUFFIX
:
3594 mask
.bitfield
.imm64
= 1;
3595 mask
.bitfield
.imm32s
= 1;
3597 case LONG_MNEM_SUFFIX
:
3598 mask
.bitfield
.imm32
= 1;
3600 case WORD_MNEM_SUFFIX
:
3601 mask
.bitfield
.imm16
= 1;
3603 case BYTE_MNEM_SUFFIX
:
3604 mask
.bitfield
.imm8
= 1;
3609 allowed
= operand_type_and (mask
, allowed
);
3610 if (!operand_type_all_zero (&allowed
))
3611 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3618 /* Try to use the smallest displacement type too. */
3620 optimize_disp (void)
3624 for (op
= i
.operands
; --op
>= 0;)
3625 if (operand_type_check (i
.types
[op
], disp
))
3627 if (i
.op
[op
].disps
->X_op
== O_constant
)
3629 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3631 if (i
.types
[op
].bitfield
.disp16
3632 && (disp
& ~(offsetT
) 0xffff) == 0)
3634 /* If this operand is at most 16 bits, convert
3635 to a signed 16 bit number and don't use 64bit
3637 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3638 i
.types
[op
].bitfield
.disp64
= 0;
3640 if (i
.types
[op
].bitfield
.disp32
3641 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3643 /* If this operand is at most 32 bits, convert
3644 to a signed 32 bit number and don't use 64bit
3646 disp
&= (((offsetT
) 2 << 31) - 1);
3647 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3648 i
.types
[op
].bitfield
.disp64
= 0;
3650 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3652 i
.types
[op
].bitfield
.disp8
= 0;
3653 i
.types
[op
].bitfield
.disp16
= 0;
3654 i
.types
[op
].bitfield
.disp32
= 0;
3655 i
.types
[op
].bitfield
.disp32s
= 0;
3656 i
.types
[op
].bitfield
.disp64
= 0;
3660 else if (flag_code
== CODE_64BIT
)
3662 if (fits_in_signed_long (disp
))
3664 i
.types
[op
].bitfield
.disp64
= 0;
3665 i
.types
[op
].bitfield
.disp32s
= 1;
3667 if (i
.prefix
[ADDR_PREFIX
]
3668 && fits_in_unsigned_long (disp
))
3669 i
.types
[op
].bitfield
.disp32
= 1;
3671 if ((i
.types
[op
].bitfield
.disp32
3672 || i
.types
[op
].bitfield
.disp32s
3673 || i
.types
[op
].bitfield
.disp16
)
3674 && fits_in_signed_byte (disp
))
3675 i
.types
[op
].bitfield
.disp8
= 1;
3677 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3678 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3680 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3681 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3682 i
.types
[op
].bitfield
.disp8
= 0;
3683 i
.types
[op
].bitfield
.disp16
= 0;
3684 i
.types
[op
].bitfield
.disp32
= 0;
3685 i
.types
[op
].bitfield
.disp32s
= 0;
3686 i
.types
[op
].bitfield
.disp64
= 0;
3689 /* We only support 64bit displacement on constants. */
3690 i
.types
[op
].bitfield
.disp64
= 0;
3694 static const insn_template
*
3695 match_template (void)
3697 /* Points to template once we've found it. */
3698 const insn_template
*t
;
3699 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3700 i386_operand_type overlap4
;
3701 unsigned int found_reverse_match
;
3702 i386_opcode_modifier suffix_check
;
3703 i386_operand_type operand_types
[MAX_OPERANDS
];
3704 int addr_prefix_disp
;
3706 unsigned int found_cpu_match
;
3707 unsigned int check_register
;
3709 #if MAX_OPERANDS != 5
3710 # error "MAX_OPERANDS must be 5."
3713 found_reverse_match
= 0;
3714 addr_prefix_disp
= -1;
3716 memset (&suffix_check
, 0, sizeof (suffix_check
));
3717 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3718 suffix_check
.no_bsuf
= 1;
3719 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3720 suffix_check
.no_wsuf
= 1;
3721 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3722 suffix_check
.no_ssuf
= 1;
3723 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3724 suffix_check
.no_lsuf
= 1;
3725 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3726 suffix_check
.no_qsuf
= 1;
3727 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3728 suffix_check
.no_ldsuf
= 1;
3730 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3732 addr_prefix_disp
= -1;
3734 /* Must have right number of operands. */
3735 if (i
.operands
!= t
->operands
)
3738 /* Check processor support. */
3739 found_cpu_match
= (cpu_flags_match (t
)
3740 == CPU_FLAGS_PERFECT_MATCH
);
3741 if (!found_cpu_match
)
3744 /* Check old gcc support. */
3745 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3748 /* Check AT&T mnemonic. */
3749 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3752 /* Check AT&T syntax Intel syntax. */
3753 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3754 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3757 /* Check the suffix, except for some instructions in intel mode. */
3758 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3759 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3760 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3761 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3762 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3763 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3764 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3767 if (!operand_size_match (t
))
3770 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3771 operand_types
[j
] = t
->operand_types
[j
];
3773 /* In general, don't allow 64-bit operands in 32-bit mode. */
3774 if (i
.suffix
== QWORD_MNEM_SUFFIX
3775 && flag_code
!= CODE_64BIT
3777 ? (!t
->opcode_modifier
.ignoresize
3778 && !intel_float_operand (t
->name
))
3779 : intel_float_operand (t
->name
) != 2)
3780 && ((!operand_types
[0].bitfield
.regmmx
3781 && !operand_types
[0].bitfield
.regxmm
3782 && !operand_types
[0].bitfield
.regymm
)
3783 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3784 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3785 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3786 && (t
->base_opcode
!= 0x0fc7
3787 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3790 /* In general, don't allow 32-bit operands on pre-386. */
3791 else if (i
.suffix
== LONG_MNEM_SUFFIX
3792 && !cpu_arch_flags
.bitfield
.cpui386
3794 ? (!t
->opcode_modifier
.ignoresize
3795 && !intel_float_operand (t
->name
))
3796 : intel_float_operand (t
->name
) != 2)
3797 && ((!operand_types
[0].bitfield
.regmmx
3798 && !operand_types
[0].bitfield
.regxmm
)
3799 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3800 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3803 /* Do not verify operands when there are none. */
3807 /* We've found a match; break out of loop. */
3811 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3812 into Disp32/Disp16/Disp32 operand. */
3813 if (i
.prefix
[ADDR_PREFIX
] != 0)
3815 /* There should be only one Disp operand. */
3819 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3821 if (operand_types
[j
].bitfield
.disp16
)
3823 addr_prefix_disp
= j
;
3824 operand_types
[j
].bitfield
.disp32
= 1;
3825 operand_types
[j
].bitfield
.disp16
= 0;
3831 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3833 if (operand_types
[j
].bitfield
.disp32
)
3835 addr_prefix_disp
= j
;
3836 operand_types
[j
].bitfield
.disp32
= 0;
3837 operand_types
[j
].bitfield
.disp16
= 1;
3843 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3845 if (operand_types
[j
].bitfield
.disp64
)
3847 addr_prefix_disp
= j
;
3848 operand_types
[j
].bitfield
.disp64
= 0;
3849 operand_types
[j
].bitfield
.disp32
= 1;
3857 /* We check register size only if size of operands can be
3858 encoded the canonical way. */
3859 check_register
= t
->opcode_modifier
.w
;
3860 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3861 switch (t
->operands
)
3864 if (!operand_type_match (overlap0
, i
.types
[0]))
3868 /* xchg %eax, %eax is a special case. It is an aliase for nop
3869 only in 32bit mode and we can use opcode 0x90. In 64bit
3870 mode, we can't use 0x90 for xchg %eax, %eax since it should
3871 zero-extend %eax to %rax. */
3872 if (flag_code
== CODE_64BIT
3873 && t
->base_opcode
== 0x90
3874 && operand_type_equal (&i
.types
[0], &acc32
)
3875 && operand_type_equal (&i
.types
[1], &acc32
))
3879 /* If we swap operand in encoding, we either match
3880 the next one or reverse direction of operands. */
3881 if (t
->opcode_modifier
.s
)
3883 else if (t
->opcode_modifier
.d
)
3888 /* If we swap operand in encoding, we match the next one. */
3889 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3893 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3894 if (!operand_type_match (overlap0
, i
.types
[0])
3895 || !operand_type_match (overlap1
, i
.types
[1])
3897 && !operand_type_register_match (overlap0
, i
.types
[0],
3899 overlap1
, i
.types
[1],
3902 /* Check if other direction is valid ... */
3903 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3907 /* Try reversing direction of operands. */
3908 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3909 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3910 if (!operand_type_match (overlap0
, i
.types
[0])
3911 || !operand_type_match (overlap1
, i
.types
[1])
3913 && !operand_type_register_match (overlap0
,
3920 /* Does not match either direction. */
3923 /* found_reverse_match holds which of D or FloatDR
3925 if (t
->opcode_modifier
.d
)
3926 found_reverse_match
= Opcode_D
;
3927 else if (t
->opcode_modifier
.floatd
)
3928 found_reverse_match
= Opcode_FloatD
;
3930 found_reverse_match
= 0;
3931 if (t
->opcode_modifier
.floatr
)
3932 found_reverse_match
|= Opcode_FloatR
;
3936 /* Found a forward 2 operand match here. */
3937 switch (t
->operands
)
3940 overlap4
= operand_type_and (i
.types
[4],
3943 overlap3
= operand_type_and (i
.types
[3],
3946 overlap2
= operand_type_and (i
.types
[2],
3951 switch (t
->operands
)
3954 if (!operand_type_match (overlap4
, i
.types
[4])
3955 || !operand_type_register_match (overlap3
,
3963 if (!operand_type_match (overlap3
, i
.types
[3])
3965 && !operand_type_register_match (overlap2
,
3973 /* Here we make use of the fact that there are no
3974 reverse match 3 operand instructions, and all 3
3975 operand instructions only need to be checked for
3976 register consistency between operands 2 and 3. */
3977 if (!operand_type_match (overlap2
, i
.types
[2])
3979 && !operand_type_register_match (overlap1
,
3989 /* Found either forward/reverse 2, 3 or 4 operand match here:
3990 slip through to break. */
3992 if (!found_cpu_match
)
3994 found_reverse_match
= 0;
3998 /* We've found a match; break out of loop. */
4002 if (t
== current_templates
->end
)
4004 /* We found no match. */
4006 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4007 current_templates
->start
->name
);
4009 as_bad (_("suffix or operands invalid for `%s'"),
4010 current_templates
->start
->name
);
4014 if (!quiet_warnings
)
4017 && (i
.types
[0].bitfield
.jumpabsolute
4018 != operand_types
[0].bitfield
.jumpabsolute
))
4020 as_warn (_("indirect %s without `*'"), t
->name
);
4023 if (t
->opcode_modifier
.isprefix
4024 && t
->opcode_modifier
.ignoresize
)
4026 /* Warn them that a data or address size prefix doesn't
4027 affect assembly of the next line of code. */
4028 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4032 /* Copy the template we found. */
4035 if (addr_prefix_disp
!= -1)
4036 i
.tm
.operand_types
[addr_prefix_disp
]
4037 = operand_types
[addr_prefix_disp
];
4039 if (found_reverse_match
)
4041 /* If we found a reverse match we must alter the opcode
4042 direction bit. found_reverse_match holds bits to change
4043 (different for int & float insns). */
4045 i
.tm
.base_opcode
^= found_reverse_match
;
4047 i
.tm
.operand_types
[0] = operand_types
[1];
4048 i
.tm
.operand_types
[1] = operand_types
[0];
4057 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4058 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4060 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4062 as_bad (_("`%s' operand %d must use `%ses' segment"),
4068 /* There's only ever one segment override allowed per instruction.
4069 This instruction possibly has a legal segment override on the
4070 second operand, so copy the segment to where non-string
4071 instructions store it, allowing common code. */
4072 i
.seg
[0] = i
.seg
[1];
4074 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4076 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4078 as_bad (_("`%s' operand %d must use `%ses' segment"),
4089 process_suffix (void)
4091 /* If matched instruction specifies an explicit instruction mnemonic
4093 if (i
.tm
.opcode_modifier
.size16
)
4094 i
.suffix
= WORD_MNEM_SUFFIX
;
4095 else if (i
.tm
.opcode_modifier
.size32
)
4096 i
.suffix
= LONG_MNEM_SUFFIX
;
4097 else if (i
.tm
.opcode_modifier
.size64
)
4098 i
.suffix
= QWORD_MNEM_SUFFIX
;
4099 else if (i
.reg_operands
)
4101 /* If there's no instruction mnemonic suffix we try to invent one
4102 based on register operands. */
4105 /* We take i.suffix from the last register operand specified,
4106 Destination register type is more significant than source
4107 register type. crc32 in SSE4.2 prefers source register
4109 if (i
.tm
.base_opcode
== 0xf20f38f1)
4111 if (i
.types
[0].bitfield
.reg16
)
4112 i
.suffix
= WORD_MNEM_SUFFIX
;
4113 else if (i
.types
[0].bitfield
.reg32
)
4114 i
.suffix
= LONG_MNEM_SUFFIX
;
4115 else if (i
.types
[0].bitfield
.reg64
)
4116 i
.suffix
= QWORD_MNEM_SUFFIX
;
4118 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4120 if (i
.types
[0].bitfield
.reg8
)
4121 i
.suffix
= BYTE_MNEM_SUFFIX
;
4128 if (i
.tm
.base_opcode
== 0xf20f38f1
4129 || i
.tm
.base_opcode
== 0xf20f38f0)
4131 /* We have to know the operand size for crc32. */
4132 as_bad (_("ambiguous memory operand size for `%s`"),
4137 for (op
= i
.operands
; --op
>= 0;)
4138 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4140 if (i
.types
[op
].bitfield
.reg8
)
4142 i
.suffix
= BYTE_MNEM_SUFFIX
;
4145 else if (i
.types
[op
].bitfield
.reg16
)
4147 i
.suffix
= WORD_MNEM_SUFFIX
;
4150 else if (i
.types
[op
].bitfield
.reg32
)
4152 i
.suffix
= LONG_MNEM_SUFFIX
;
4155 else if (i
.types
[op
].bitfield
.reg64
)
4157 i
.suffix
= QWORD_MNEM_SUFFIX
;
4163 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4165 if (!check_byte_reg ())
4168 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4170 if (!check_long_reg ())
4173 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4176 && i
.tm
.opcode_modifier
.ignoresize
4177 && i
.tm
.opcode_modifier
.no_qsuf
)
4179 else if (!check_qword_reg ())
4182 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4184 if (!check_word_reg ())
4187 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4188 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4190 /* Skip if the instruction has x/y suffix. match_template
4191 should check if it is a valid suffix. */
4193 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4194 /* Do nothing if the instruction is going to ignore the prefix. */
4199 else if (i
.tm
.opcode_modifier
.defaultsize
4201 /* exclude fldenv/frstor/fsave/fstenv */
4202 && i
.tm
.opcode_modifier
.no_ssuf
)
4204 i
.suffix
= stackop_size
;
4206 else if (intel_syntax
4208 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4209 || i
.tm
.opcode_modifier
.jumpbyte
4210 || i
.tm
.opcode_modifier
.jumpintersegment
4211 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4212 && i
.tm
.extension_opcode
<= 3)))
4217 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4219 i
.suffix
= QWORD_MNEM_SUFFIX
;
4223 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4224 i
.suffix
= LONG_MNEM_SUFFIX
;
4227 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4228 i
.suffix
= WORD_MNEM_SUFFIX
;
4237 if (i
.tm
.opcode_modifier
.w
)
4239 as_bad (_("no instruction mnemonic suffix given and "
4240 "no register operands; can't size instruction"));
4246 unsigned int suffixes
;
4248 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4249 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4251 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4253 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4255 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4257 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4260 /* There are more than suffix matches. */
4261 if (i
.tm
.opcode_modifier
.w
4262 || ((suffixes
& (suffixes
- 1))
4263 && !i
.tm
.opcode_modifier
.defaultsize
4264 && !i
.tm
.opcode_modifier
.ignoresize
))
4266 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4272 /* Change the opcode based on the operand size given by i.suffix;
4273 We don't need to change things for byte insns. */
4276 && i
.suffix
!= BYTE_MNEM_SUFFIX
4277 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4278 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4280 /* It's not a byte, select word/dword operation. */
4281 if (i
.tm
.opcode_modifier
.w
)
4283 if (i
.tm
.opcode_modifier
.shortform
)
4284 i
.tm
.base_opcode
|= 8;
4286 i
.tm
.base_opcode
|= 1;
4289 /* Now select between word & dword operations via the operand
4290 size prefix, except for instructions that will ignore this
4292 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4294 /* The address size override prefix changes the size of the
4296 if ((flag_code
== CODE_32BIT
4297 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4298 || (flag_code
!= CODE_32BIT
4299 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4300 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4303 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4304 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4305 && !i
.tm
.opcode_modifier
.ignoresize
4306 && !i
.tm
.opcode_modifier
.floatmf
4307 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4308 || (flag_code
== CODE_64BIT
4309 && i
.tm
.opcode_modifier
.jumpbyte
)))
4311 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4313 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4314 prefix
= ADDR_PREFIX_OPCODE
;
4316 if (!add_prefix (prefix
))
4320 /* Set mode64 for an operand. */
4321 if (i
.suffix
== QWORD_MNEM_SUFFIX
4322 && flag_code
== CODE_64BIT
4323 && !i
.tm
.opcode_modifier
.norex64
)
4325 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4326 need rex64. cmpxchg8b is also a special case. */
4327 if (! (i
.operands
== 2
4328 && i
.tm
.base_opcode
== 0x90
4329 && i
.tm
.extension_opcode
== None
4330 && operand_type_equal (&i
.types
[0], &acc64
)
4331 && operand_type_equal (&i
.types
[1], &acc64
))
4332 && ! (i
.operands
== 1
4333 && i
.tm
.base_opcode
== 0xfc7
4334 && i
.tm
.extension_opcode
== 1
4335 && !operand_type_check (i
.types
[0], reg
)
4336 && operand_type_check (i
.types
[0], anymem
)))
4340 /* Size floating point instruction. */
4341 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4342 if (i
.tm
.opcode_modifier
.floatmf
)
4343 i
.tm
.base_opcode
^= 4;
4350 check_byte_reg (void)
4354 for (op
= i
.operands
; --op
>= 0;)
4356 /* If this is an eight bit register, it's OK. If it's the 16 or
4357 32 bit version of an eight bit register, we will just use the
4358 low portion, and that's OK too. */
4359 if (i
.types
[op
].bitfield
.reg8
)
4362 /* Don't generate this warning if not needed. */
4363 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4366 /* crc32 doesn't generate this warning. */
4367 if (i
.tm
.base_opcode
== 0xf20f38f0)
4370 if ((i
.types
[op
].bitfield
.reg16
4371 || i
.types
[op
].bitfield
.reg32
4372 || i
.types
[op
].bitfield
.reg64
)
4373 && i
.op
[op
].regs
->reg_num
< 4)
4375 /* Prohibit these changes in the 64bit mode, since the
4376 lowering is more complicated. */
4377 if (flag_code
== CODE_64BIT
4378 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4380 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4381 register_prefix
, i
.op
[op
].regs
->reg_name
,
4385 #if REGISTER_WARNINGS
4387 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4388 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4390 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4391 ? REGNAM_AL
- REGNAM_AX
4392 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4394 i
.op
[op
].regs
->reg_name
,
4399 /* Any other register is bad. */
4400 if (i
.types
[op
].bitfield
.reg16
4401 || i
.types
[op
].bitfield
.reg32
4402 || i
.types
[op
].bitfield
.reg64
4403 || i
.types
[op
].bitfield
.regmmx
4404 || i
.types
[op
].bitfield
.regxmm
4405 || i
.types
[op
].bitfield
.regymm
4406 || i
.types
[op
].bitfield
.sreg2
4407 || i
.types
[op
].bitfield
.sreg3
4408 || i
.types
[op
].bitfield
.control
4409 || i
.types
[op
].bitfield
.debug
4410 || i
.types
[op
].bitfield
.test
4411 || i
.types
[op
].bitfield
.floatreg
4412 || i
.types
[op
].bitfield
.floatacc
)
4414 as_bad (_("`%s%s' not allowed with `%s%c'"),
4416 i
.op
[op
].regs
->reg_name
,
4426 check_long_reg (void)
4430 for (op
= i
.operands
; --op
>= 0;)
4431 /* Reject eight bit registers, except where the template requires
4432 them. (eg. movzb) */
4433 if (i
.types
[op
].bitfield
.reg8
4434 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4435 || i
.tm
.operand_types
[op
].bitfield
.reg32
4436 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4438 as_bad (_("`%s%s' not allowed with `%s%c'"),
4440 i
.op
[op
].regs
->reg_name
,
4445 /* Warn if the e prefix on a general reg is missing. */
4446 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4447 && i
.types
[op
].bitfield
.reg16
4448 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4449 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4451 /* Prohibit these changes in the 64bit mode, since the
4452 lowering is more complicated. */
4453 if (flag_code
== CODE_64BIT
)
4455 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4456 register_prefix
, i
.op
[op
].regs
->reg_name
,
4460 #if REGISTER_WARNINGS
4462 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4464 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4466 i
.op
[op
].regs
->reg_name
,
4470 /* Warn if the r prefix on a general reg is missing. */
4471 else if (i
.types
[op
].bitfield
.reg64
4472 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4473 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4476 && i
.tm
.opcode_modifier
.toqword
4477 && !i
.types
[0].bitfield
.regxmm
)
4479 /* Convert to QWORD. We want REX byte. */
4480 i
.suffix
= QWORD_MNEM_SUFFIX
;
4484 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4485 register_prefix
, i
.op
[op
].regs
->reg_name
,
4494 check_qword_reg (void)
4498 for (op
= i
.operands
; --op
>= 0; )
4499 /* Reject eight bit registers, except where the template requires
4500 them. (eg. movzb) */
4501 if (i
.types
[op
].bitfield
.reg8
4502 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4503 || i
.tm
.operand_types
[op
].bitfield
.reg32
4504 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4506 as_bad (_("`%s%s' not allowed with `%s%c'"),
4508 i
.op
[op
].regs
->reg_name
,
4513 /* Warn if the e prefix on a general reg is missing. */
4514 else if ((i
.types
[op
].bitfield
.reg16
4515 || i
.types
[op
].bitfield
.reg32
)
4516 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4517 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4519 /* Prohibit these changes in the 64bit mode, since the
4520 lowering is more complicated. */
4522 && i
.tm
.opcode_modifier
.todword
4523 && !i
.types
[0].bitfield
.regxmm
)
4525 /* Convert to DWORD. We don't want REX byte. */
4526 i
.suffix
= LONG_MNEM_SUFFIX
;
4530 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4531 register_prefix
, i
.op
[op
].regs
->reg_name
,
4540 check_word_reg (void)
4543 for (op
= i
.operands
; --op
>= 0;)
4544 /* Reject eight bit registers, except where the template requires
4545 them. (eg. movzb) */
4546 if (i
.types
[op
].bitfield
.reg8
4547 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4548 || i
.tm
.operand_types
[op
].bitfield
.reg32
4549 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4551 as_bad (_("`%s%s' not allowed with `%s%c'"),
4553 i
.op
[op
].regs
->reg_name
,
4558 /* Warn if the e prefix on a general reg is present. */
4559 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4560 && i
.types
[op
].bitfield
.reg32
4561 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4562 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4564 /* Prohibit these changes in the 64bit mode, since the
4565 lowering is more complicated. */
4566 if (flag_code
== CODE_64BIT
)
4568 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4569 register_prefix
, i
.op
[op
].regs
->reg_name
,
4574 #if REGISTER_WARNINGS
4575 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4577 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4579 i
.op
[op
].regs
->reg_name
,
4587 update_imm (unsigned int j
)
4589 i386_operand_type overlap
= i
.types
[j
];
4590 if ((overlap
.bitfield
.imm8
4591 || overlap
.bitfield
.imm8s
4592 || overlap
.bitfield
.imm16
4593 || overlap
.bitfield
.imm32
4594 || overlap
.bitfield
.imm32s
4595 || overlap
.bitfield
.imm64
)
4596 && !operand_type_equal (&overlap
, &imm8
)
4597 && !operand_type_equal (&overlap
, &imm8s
)
4598 && !operand_type_equal (&overlap
, &imm16
)
4599 && !operand_type_equal (&overlap
, &imm32
)
4600 && !operand_type_equal (&overlap
, &imm32s
)
4601 && !operand_type_equal (&overlap
, &imm64
))
4605 i386_operand_type temp
;
4607 operand_type_set (&temp
, 0);
4608 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4610 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4611 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4613 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4614 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4615 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4617 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4618 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4621 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4624 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4625 || operand_type_equal (&overlap
, &imm16_32
)
4626 || operand_type_equal (&overlap
, &imm16_32s
))
4628 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4633 if (!operand_type_equal (&overlap
, &imm8
)
4634 && !operand_type_equal (&overlap
, &imm8s
)
4635 && !operand_type_equal (&overlap
, &imm16
)
4636 && !operand_type_equal (&overlap
, &imm32
)
4637 && !operand_type_equal (&overlap
, &imm32s
)
4638 && !operand_type_equal (&overlap
, &imm64
))
4640 as_bad (_("no instruction mnemonic suffix given; "
4641 "can't determine immediate size"));
4645 i
.types
[j
] = overlap
;
4655 /* Update the first 2 immediate operands. */
4656 n
= i
.operands
> 2 ? 2 : i
.operands
;
4659 for (j
= 0; j
< n
; j
++)
4660 if (update_imm (j
) == 0)
4663 /* The 3rd operand can't be immediate operand. */
4664 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4671 bad_implicit_operand (int xmm
)
4673 const char *reg
= xmm
? "xmm0" : "ymm0";
4675 as_bad (_("the last operand of `%s' must be `%s%s'"),
4676 i
.tm
.name
, register_prefix
, reg
);
4678 as_bad (_("the first operand of `%s' must be `%s%s'"),
4679 i
.tm
.name
, register_prefix
, reg
);
4684 process_operands (void)
4686 /* Default segment register this instruction will use for memory
4687 accesses. 0 means unknown. This is only for optimizing out
4688 unnecessary segment overrides. */
4689 const seg_entry
*default_seg
= 0;
4691 if (i
.tm
.opcode_modifier
.sse2avx
4692 && (i
.tm
.opcode_modifier
.vexnds
4693 || i
.tm
.opcode_modifier
.vexndd
))
4695 unsigned int dup
= i
.operands
;
4696 unsigned int dest
= dup
- 1;
4699 /* The destination must be an xmm register. */
4700 gas_assert (i
.reg_operands
4701 && MAX_OPERANDS
> dup
4702 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4704 if (i
.tm
.opcode_modifier
.firstxmm0
)
4706 /* The first operand is implicit and must be xmm0. */
4707 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4708 if (i
.op
[0].regs
->reg_num
!= 0)
4709 return bad_implicit_operand (1);
4711 if (i
.tm
.opcode_modifier
.vex3sources
)
4713 /* Keep xmm0 for instructions with VEX prefix and 3
4719 /* We remove the first xmm0 and keep the number of
4720 operands unchanged, which in fact duplicates the
4722 for (j
= 1; j
< i
.operands
; j
++)
4724 i
.op
[j
- 1] = i
.op
[j
];
4725 i
.types
[j
- 1] = i
.types
[j
];
4726 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4730 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4732 gas_assert ((MAX_OPERANDS
- 1) > dup
4733 && i
.tm
.opcode_modifier
.vex3sources
);
4735 /* Add the implicit xmm0 for instructions with VEX prefix
4737 for (j
= i
.operands
; j
> 0; j
--)
4739 i
.op
[j
] = i
.op
[j
- 1];
4740 i
.types
[j
] = i
.types
[j
- 1];
4741 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4744 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4745 i
.types
[0] = regxmm
;
4746 i
.tm
.operand_types
[0] = regxmm
;
4749 i
.reg_operands
+= 2;
4754 i
.op
[dup
] = i
.op
[dest
];
4755 i
.types
[dup
] = i
.types
[dest
];
4756 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4765 i
.op
[dup
] = i
.op
[dest
];
4766 i
.types
[dup
] = i
.types
[dest
];
4767 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4770 if (i
.tm
.opcode_modifier
.immext
)
4773 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4777 /* The first operand is implicit and must be xmm0/ymm0. */
4778 gas_assert (i
.reg_operands
4779 && (operand_type_equal (&i
.types
[0], ®xmm
)
4780 || operand_type_equal (&i
.types
[0], ®ymm
)));
4781 if (i
.op
[0].regs
->reg_num
!= 0)
4782 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4784 for (j
= 1; j
< i
.operands
; j
++)
4786 i
.op
[j
- 1] = i
.op
[j
];
4787 i
.types
[j
- 1] = i
.types
[j
];
4789 /* We need to adjust fields in i.tm since they are used by
4790 build_modrm_byte. */
4791 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4798 else if (i
.tm
.opcode_modifier
.regkludge
)
4800 /* The imul $imm, %reg instruction is converted into
4801 imul $imm, %reg, %reg, and the clr %reg instruction
4802 is converted into xor %reg, %reg. */
4804 unsigned int first_reg_op
;
4806 if (operand_type_check (i
.types
[0], reg
))
4810 /* Pretend we saw the extra register operand. */
4811 gas_assert (i
.reg_operands
== 1
4812 && i
.op
[first_reg_op
+ 1].regs
== 0);
4813 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4814 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4819 if (i
.tm
.opcode_modifier
.shortform
)
4821 if (i
.types
[0].bitfield
.sreg2
4822 || i
.types
[0].bitfield
.sreg3
)
4824 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4825 && i
.op
[0].regs
->reg_num
== 1)
4827 as_bad (_("you can't `pop %scs'"), register_prefix
);
4830 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4831 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4836 /* The register or float register operand is in operand
4840 if (i
.types
[0].bitfield
.floatreg
4841 || operand_type_check (i
.types
[0], reg
))
4845 /* Register goes in low 3 bits of opcode. */
4846 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4847 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4849 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4851 /* Warn about some common errors, but press on regardless.
4852 The first case can be generated by gcc (<= 2.8.1). */
4853 if (i
.operands
== 2)
4855 /* Reversed arguments on faddp, fsubp, etc. */
4856 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4857 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4858 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4862 /* Extraneous `l' suffix on fp insn. */
4863 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4864 register_prefix
, i
.op
[0].regs
->reg_name
);
4869 else if (i
.tm
.opcode_modifier
.modrm
)
4871 /* The opcode is completed (modulo i.tm.extension_opcode which
4872 must be put into the modrm byte). Now, we make the modrm and
4873 index base bytes based on all the info we've collected. */
4875 default_seg
= build_modrm_byte ();
4877 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4881 else if (i
.tm
.opcode_modifier
.isstring
)
4883 /* For the string instructions that allow a segment override
4884 on one of their operands, the default segment is ds. */
4888 if (i
.tm
.base_opcode
== 0x8d /* lea */
4891 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4893 /* If a segment was explicitly specified, and the specified segment
4894 is not the default, use an opcode prefix to select it. If we
4895 never figured out what the default segment is, then default_seg
4896 will be zero at this point, and the specified segment prefix will
4898 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4900 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4906 static const seg_entry
*
4907 build_modrm_byte (void)
4909 const seg_entry
*default_seg
= 0;
4910 unsigned int source
, dest
;
4913 /* The first operand of instructions with VEX prefix and 3 sources
4914 must be VEX_Imm4. */
4915 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4918 unsigned int nds
, reg
;
4921 if (i
.tm
.opcode_modifier
.veximmext
4922 && i
.tm
.opcode_modifier
.immext
)
4924 dest
= i
.operands
- 2;
4925 gas_assert (dest
== 3);
4928 dest
= i
.operands
- 1;
4931 /* This instruction must have 4 register operands
4932 or 3 register operands plus 1 memory operand.
4933 It must have VexNDS and VexImmExt. */
4934 gas_assert ((i
.reg_operands
== 4
4935 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4936 && i
.tm
.opcode_modifier
.vexnds
4937 && i
.tm
.opcode_modifier
.veximmext
4938 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4939 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4941 /* Generate an 8bit immediate operand to encode the register
4943 exp
= &im_expressions
[i
.imm_operands
++];
4944 i
.op
[i
.operands
].imms
= exp
;
4945 i
.types
[i
.operands
] = imm8
;
4947 /* If VexW1 is set, the first operand is the source and
4948 the second operand is encoded in the immediate operand. */
4949 if (i
.tm
.opcode_modifier
.vexw1
)
4959 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4960 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4962 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4963 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4965 exp
->X_op
= O_constant
;
4967 = ((i
.op
[reg
].regs
->reg_num
4968 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4969 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4974 /* i.reg_operands MUST be the number of real register operands;
4975 implicit registers do not count. If there are 3 register
4976 operands, it must be a instruction with VexNDS. For a
4977 instruction with VexNDD, the destination register is encoded
4978 in VEX prefix. If there are 4 register operands, it must be
4979 a instruction with VEX prefix and 3 sources. */
4980 if (i
.mem_operands
== 0
4981 && ((i
.reg_operands
== 2
4982 && !i
.tm
.opcode_modifier
.vexndd
4983 && !i
.tm
.opcode_modifier
.vexlwp
)
4984 || (i
.reg_operands
== 3
4985 && i
.tm
.opcode_modifier
.vexnds
)
4986 || (i
.reg_operands
== 4 && vex_3_sources
)))
4994 /* When there are 3 operands, one of them may be immediate,
4995 which may be the first or the last operand. Otherwise,
4996 the first operand must be shift count register (cl) or it
4997 is an instruction with VexNDS. */
4998 gas_assert (i
.imm_operands
== 1
4999 || (i
.imm_operands
== 0
5000 && (i
.tm
.opcode_modifier
.vexnds
5001 || i
.types
[0].bitfield
.shiftcount
)));
5002 if (operand_type_check (i
.types
[0], imm
)
5003 || i
.types
[0].bitfield
.shiftcount
)
5009 /* When there are 4 operands, the first two must be 8bit
5010 immediate operands. The source operand will be the 3rd
5013 For instructions with VexNDS, if the first operand
5014 an imm8, the source operand is the 2nd one. If the last
5015 operand is imm8, the source operand is the first one. */
5016 gas_assert ((i
.imm_operands
== 2
5017 && i
.types
[0].bitfield
.imm8
5018 && i
.types
[1].bitfield
.imm8
)
5019 || (i
.tm
.opcode_modifier
.vexnds
5020 && i
.imm_operands
== 1
5021 && (i
.types
[0].bitfield
.imm8
5022 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5023 if (i
.tm
.opcode_modifier
.vexnds
)
5025 if (i
.types
[0].bitfield
.imm8
)
5043 if (i
.tm
.opcode_modifier
.vexnds
)
5045 /* For instructions with VexNDS, the register-only
5046 source operand must be XMM or YMM register. It is
5047 encoded in VEX prefix. We need to clear RegMem bit
5048 before calling operand_type_equal. */
5049 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5050 op
.bitfield
.regmem
= 0;
5051 if ((dest
+ 1) >= i
.operands
5052 || (!operand_type_equal (&op
, ®xmm
)
5053 && !operand_type_equal (&op
, ®ymm
)))
5055 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5061 /* One of the register operands will be encoded in the i.tm.reg
5062 field, the other in the combined i.tm.mode and i.tm.regmem
5063 fields. If no form of this instruction supports a memory
5064 destination operand, then we assume the source operand may
5065 sometimes be a memory operand and so we need to store the
5066 destination in the i.rm.reg field. */
5067 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5068 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5070 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5071 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5072 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5074 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5079 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5080 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5081 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5083 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5086 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5088 if (!i
.types
[0].bitfield
.control
5089 && !i
.types
[1].bitfield
.control
)
5091 i
.rex
&= ~(REX_R
| REX_B
);
5092 add_prefix (LOCK_PREFIX_OPCODE
);
5096 { /* If it's not 2 reg operands... */
5101 unsigned int fake_zero_displacement
= 0;
5104 for (op
= 0; op
< i
.operands
; op
++)
5105 if (operand_type_check (i
.types
[op
], anymem
))
5107 gas_assert (op
< i
.operands
);
5111 if (i
.base_reg
== 0)
5114 if (!i
.disp_operands
)
5115 fake_zero_displacement
= 1;
5116 if (i
.index_reg
== 0)
5118 /* Operand is just <disp> */
5119 if (flag_code
== CODE_64BIT
)
5121 /* 64bit mode overwrites the 32bit absolute
5122 addressing by RIP relative addressing and
5123 absolute addressing is encoded by one of the
5124 redundant SIB forms. */
5125 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5126 i
.sib
.base
= NO_BASE_REGISTER
;
5127 i
.sib
.index
= NO_INDEX_REGISTER
;
5128 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5129 ? disp32s
: disp32
);
5131 else if ((flag_code
== CODE_16BIT
)
5132 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5134 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5135 i
.types
[op
] = disp16
;
5139 i
.rm
.regmem
= NO_BASE_REGISTER
;
5140 i
.types
[op
] = disp32
;
5143 else /* !i.base_reg && i.index_reg */
5145 if (i
.index_reg
->reg_num
== RegEiz
5146 || i
.index_reg
->reg_num
== RegRiz
)
5147 i
.sib
.index
= NO_INDEX_REGISTER
;
5149 i
.sib
.index
= i
.index_reg
->reg_num
;
5150 i
.sib
.base
= NO_BASE_REGISTER
;
5151 i
.sib
.scale
= i
.log2_scale_factor
;
5152 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5153 i
.types
[op
].bitfield
.disp8
= 0;
5154 i
.types
[op
].bitfield
.disp16
= 0;
5155 i
.types
[op
].bitfield
.disp64
= 0;
5156 if (flag_code
!= CODE_64BIT
)
5158 /* Must be 32 bit */
5159 i
.types
[op
].bitfield
.disp32
= 1;
5160 i
.types
[op
].bitfield
.disp32s
= 0;
5164 i
.types
[op
].bitfield
.disp32
= 0;
5165 i
.types
[op
].bitfield
.disp32s
= 1;
5167 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5171 /* RIP addressing for 64bit mode. */
5172 else if (i
.base_reg
->reg_num
== RegRip
||
5173 i
.base_reg
->reg_num
== RegEip
)
5175 i
.rm
.regmem
= NO_BASE_REGISTER
;
5176 i
.types
[op
].bitfield
.disp8
= 0;
5177 i
.types
[op
].bitfield
.disp16
= 0;
5178 i
.types
[op
].bitfield
.disp32
= 0;
5179 i
.types
[op
].bitfield
.disp32s
= 1;
5180 i
.types
[op
].bitfield
.disp64
= 0;
5181 i
.flags
[op
] |= Operand_PCrel
;
5182 if (! i
.disp_operands
)
5183 fake_zero_displacement
= 1;
5185 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5187 switch (i
.base_reg
->reg_num
)
5190 if (i
.index_reg
== 0)
5192 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5193 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5197 if (i
.index_reg
== 0)
5200 if (operand_type_check (i
.types
[op
], disp
) == 0)
5202 /* fake (%bp) into 0(%bp) */
5203 i
.types
[op
].bitfield
.disp8
= 1;
5204 fake_zero_displacement
= 1;
5207 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5208 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5210 default: /* (%si) -> 4 or (%di) -> 5 */
5211 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5213 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5215 else /* i.base_reg and 32/64 bit mode */
5217 if (flag_code
== CODE_64BIT
5218 && operand_type_check (i
.types
[op
], disp
))
5220 i386_operand_type temp
;
5221 operand_type_set (&temp
, 0);
5222 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5224 if (i
.prefix
[ADDR_PREFIX
] == 0)
5225 i
.types
[op
].bitfield
.disp32s
= 1;
5227 i
.types
[op
].bitfield
.disp32
= 1;
5230 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5231 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5233 i
.sib
.base
= i
.base_reg
->reg_num
;
5234 /* x86-64 ignores REX prefix bit here to avoid decoder
5236 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5239 if (i
.disp_operands
== 0)
5241 fake_zero_displacement
= 1;
5242 i
.types
[op
].bitfield
.disp8
= 1;
5245 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5249 i
.sib
.scale
= i
.log2_scale_factor
;
5250 if (i
.index_reg
== 0)
5252 /* <disp>(%esp) becomes two byte modrm with no index
5253 register. We've already stored the code for esp
5254 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5255 Any base register besides %esp will not use the
5256 extra modrm byte. */
5257 i
.sib
.index
= NO_INDEX_REGISTER
;
5261 if (i
.index_reg
->reg_num
== RegEiz
5262 || i
.index_reg
->reg_num
== RegRiz
)
5263 i
.sib
.index
= NO_INDEX_REGISTER
;
5265 i
.sib
.index
= i
.index_reg
->reg_num
;
5266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5267 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5272 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5273 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5276 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5279 if (fake_zero_displacement
)
5281 /* Fakes a zero displacement assuming that i.types[op]
5282 holds the correct displacement size. */
5285 gas_assert (i
.op
[op
].disps
== 0);
5286 exp
= &disp_expressions
[i
.disp_operands
++];
5287 i
.op
[op
].disps
= exp
;
5288 exp
->X_op
= O_constant
;
5289 exp
->X_add_number
= 0;
5290 exp
->X_add_symbol
= (symbolS
*) 0;
5291 exp
->X_op_symbol
= (symbolS
*) 0;
5299 if (i
.tm
.opcode_modifier
.vexlwp
)
5301 i
.vex
.register_specifier
= i
.op
[2].regs
;
5302 if (!i
.mem_operands
)
5305 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5306 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5310 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5311 (if any) based on i.tm.extension_opcode. Again, we must be
5312 careful to make sure that segment/control/debug/test/MMX
5313 registers are coded into the i.rm.reg field. */
5314 else if (i
.reg_operands
)
5317 unsigned int vex_reg
= ~0;
5319 for (op
= 0; op
< i
.operands
; op
++)
5320 if (i
.types
[op
].bitfield
.reg8
5321 || i
.types
[op
].bitfield
.reg16
5322 || i
.types
[op
].bitfield
.reg32
5323 || i
.types
[op
].bitfield
.reg64
5324 || i
.types
[op
].bitfield
.regmmx
5325 || i
.types
[op
].bitfield
.regxmm
5326 || i
.types
[op
].bitfield
.regymm
5327 || i
.types
[op
].bitfield
.sreg2
5328 || i
.types
[op
].bitfield
.sreg3
5329 || i
.types
[op
].bitfield
.control
5330 || i
.types
[op
].bitfield
.debug
5331 || i
.types
[op
].bitfield
.test
)
5336 else if (i
.tm
.opcode_modifier
.vexnds
)
5338 /* For instructions with VexNDS, the register-only
5339 source operand is encoded in VEX prefix. */
5340 gas_assert (mem
!= (unsigned int) ~0);
5345 gas_assert (op
< i
.operands
);
5350 gas_assert (vex_reg
< i
.operands
);
5353 else if (i
.tm
.opcode_modifier
.vexndd
)
5355 /* For instructions with VexNDD, there should be
5356 no memory operand and the register destination
5357 is encoded in VEX prefix. */
5358 gas_assert (i
.mem_operands
== 0
5359 && (op
+ 2) == i
.operands
);
5363 gas_assert (op
< i
.operands
);
5365 if (vex_reg
!= (unsigned int) ~0)
5367 gas_assert (i
.reg_operands
== 2);
5369 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5371 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5375 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5378 /* Don't set OP operand twice. */
5381 /* If there is an extension opcode to put here, the
5382 register number must be put into the regmem field. */
5383 if (i
.tm
.extension_opcode
!= None
)
5385 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5386 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5391 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5392 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5397 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5398 must set it to 3 to indicate this is a register operand
5399 in the regmem field. */
5400 if (!i
.mem_operands
)
5404 /* Fill in i.rm.reg field with extension opcode (if any). */
5405 if (i
.tm
.extension_opcode
!= None
)
5406 i
.rm
.reg
= i
.tm
.extension_opcode
;
5412 output_branch (void)
5417 relax_substateT subtype
;
5422 if (flag_code
== CODE_16BIT
)
5426 if (i
.prefix
[DATA_PREFIX
] != 0)
5432 /* Pentium4 branch hints. */
5433 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5434 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5439 if (i
.prefix
[REX_PREFIX
] != 0)
5445 if (i
.prefixes
!= 0 && !intel_syntax
)
5446 as_warn (_("skipping prefixes on this instruction"));
5448 /* It's always a symbol; End frag & setup for relax.
5449 Make sure there is enough room in this frag for the largest
5450 instruction we may generate in md_convert_frag. This is 2
5451 bytes for the opcode and room for the prefix and largest
5453 frag_grow (prefix
+ 2 + 4);
5454 /* Prefix and 1 opcode byte go in fr_fix. */
5455 p
= frag_more (prefix
+ 1);
5456 if (i
.prefix
[DATA_PREFIX
] != 0)
5457 *p
++ = DATA_PREFIX_OPCODE
;
5458 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5459 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5460 *p
++ = i
.prefix
[SEG_PREFIX
];
5461 if (i
.prefix
[REX_PREFIX
] != 0)
5462 *p
++ = i
.prefix
[REX_PREFIX
];
5463 *p
= i
.tm
.base_opcode
;
5465 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5466 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5467 else if (cpu_arch_flags
.bitfield
.cpui386
)
5468 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5470 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5473 sym
= i
.op
[0].disps
->X_add_symbol
;
5474 off
= i
.op
[0].disps
->X_add_number
;
5476 if (i
.op
[0].disps
->X_op
!= O_constant
5477 && i
.op
[0].disps
->X_op
!= O_symbol
)
5479 /* Handle complex expressions. */
5480 sym
= make_expr_symbol (i
.op
[0].disps
);
5484 /* 1 possible extra opcode + 4 byte displacement go in var part.
5485 Pass reloc in fr_var. */
5486 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5496 if (i
.tm
.opcode_modifier
.jumpbyte
)
5498 /* This is a loop or jecxz type instruction. */
5500 if (i
.prefix
[ADDR_PREFIX
] != 0)
5502 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5505 /* Pentium4 branch hints. */
5506 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5507 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5509 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5518 if (flag_code
== CODE_16BIT
)
5521 if (i
.prefix
[DATA_PREFIX
] != 0)
5523 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5533 if (i
.prefix
[REX_PREFIX
] != 0)
5535 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5539 if (i
.prefixes
!= 0 && !intel_syntax
)
5540 as_warn (_("skipping prefixes on this instruction"));
5542 p
= frag_more (1 + size
);
5543 *p
++ = i
.tm
.base_opcode
;
5545 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5546 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5548 /* All jumps handled here are signed, but don't use a signed limit
5549 check for 32 and 16 bit jumps as we want to allow wrap around at
5550 4G and 64k respectively. */
5552 fixP
->fx_signed
= 1;
5556 output_interseg_jump (void)
5564 if (flag_code
== CODE_16BIT
)
5568 if (i
.prefix
[DATA_PREFIX
] != 0)
5574 if (i
.prefix
[REX_PREFIX
] != 0)
5584 if (i
.prefixes
!= 0 && !intel_syntax
)
5585 as_warn (_("skipping prefixes on this instruction"));
5587 /* 1 opcode; 2 segment; offset */
5588 p
= frag_more (prefix
+ 1 + 2 + size
);
5590 if (i
.prefix
[DATA_PREFIX
] != 0)
5591 *p
++ = DATA_PREFIX_OPCODE
;
5593 if (i
.prefix
[REX_PREFIX
] != 0)
5594 *p
++ = i
.prefix
[REX_PREFIX
];
5596 *p
++ = i
.tm
.base_opcode
;
5597 if (i
.op
[1].imms
->X_op
== O_constant
)
5599 offsetT n
= i
.op
[1].imms
->X_add_number
;
5602 && !fits_in_unsigned_word (n
)
5603 && !fits_in_signed_word (n
))
5605 as_bad (_("16-bit jump out of range"));
5608 md_number_to_chars (p
, n
, size
);
5611 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5612 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5613 if (i
.op
[0].imms
->X_op
!= O_constant
)
5614 as_bad (_("can't handle non absolute segment in `%s'"),
5616 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5622 fragS
*insn_start_frag
;
5623 offsetT insn_start_off
;
5625 /* Tie dwarf2 debug info to the address at the start of the insn.
5626 We can't do this after the insn has been output as the current
5627 frag may have been closed off. eg. by frag_var. */
5628 dwarf2_emit_insn (0);
5630 insn_start_frag
= frag_now
;
5631 insn_start_off
= frag_now_fix ();
5634 if (i
.tm
.opcode_modifier
.jump
)
5636 else if (i
.tm
.opcode_modifier
.jumpbyte
5637 || i
.tm
.opcode_modifier
.jumpdword
)
5639 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5640 output_interseg_jump ();
5643 /* Output normal instructions here. */
5647 unsigned int prefix
;
5649 /* Since the VEX prefix contains the implicit prefix, we don't
5650 need the explicit prefix. */
5651 if (!i
.tm
.opcode_modifier
.vex
)
5653 switch (i
.tm
.opcode_length
)
5656 if (i
.tm
.base_opcode
& 0xff000000)
5658 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5663 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5665 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5666 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5669 if (prefix
!= REPE_PREFIX_OPCODE
5670 || (i
.prefix
[REP_PREFIX
]
5671 != REPE_PREFIX_OPCODE
))
5672 add_prefix (prefix
);
5675 add_prefix (prefix
);
5684 /* The prefix bytes. */
5685 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5687 FRAG_APPEND_1_CHAR (*q
);
5690 if (i
.tm
.opcode_modifier
.vex
)
5692 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5697 /* REX byte is encoded in VEX prefix. */
5701 FRAG_APPEND_1_CHAR (*q
);
5704 /* There should be no other prefixes for instructions
5709 /* Now the VEX prefix. */
5710 p
= frag_more (i
.vex
.length
);
5711 for (j
= 0; j
< i
.vex
.length
; j
++)
5712 p
[j
] = i
.vex
.bytes
[j
];
5715 /* Now the opcode; be careful about word order here! */
5716 if (i
.tm
.opcode_length
== 1)
5718 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5722 switch (i
.tm
.opcode_length
)
5726 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5736 /* Put out high byte first: can't use md_number_to_chars! */
5737 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5738 *p
= i
.tm
.base_opcode
& 0xff;
5741 /* Now the modrm byte and sib byte (if present). */
5742 if (i
.tm
.opcode_modifier
.modrm
)
5744 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5747 /* If i.rm.regmem == ESP (4)
5748 && i.rm.mode != (Register mode)
5750 ==> need second modrm byte. */
5751 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5753 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5754 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5756 | i
.sib
.scale
<< 6));
5759 if (i
.disp_operands
)
5760 output_disp (insn_start_frag
, insn_start_off
);
5763 output_imm (insn_start_frag
, insn_start_off
);
5769 pi ("" /*line*/, &i
);
5771 #endif /* DEBUG386 */
5774 /* Return the size of the displacement operand N. */
5777 disp_size (unsigned int n
)
5780 if (i
.types
[n
].bitfield
.disp64
)
5782 else if (i
.types
[n
].bitfield
.disp8
)
5784 else if (i
.types
[n
].bitfield
.disp16
)
5789 /* Return the size of the immediate operand N. */
5792 imm_size (unsigned int n
)
5795 if (i
.types
[n
].bitfield
.imm64
)
5797 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5799 else if (i
.types
[n
].bitfield
.imm16
)
5805 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5810 for (n
= 0; n
< i
.operands
; n
++)
5812 if (operand_type_check (i
.types
[n
], disp
))
5814 if (i
.op
[n
].disps
->X_op
== O_constant
)
5816 int size
= disp_size (n
);
5819 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5821 p
= frag_more (size
);
5822 md_number_to_chars (p
, val
, size
);
5826 enum bfd_reloc_code_real reloc_type
;
5827 int size
= disp_size (n
);
5828 int sign
= i
.types
[n
].bitfield
.disp32s
;
5829 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5831 /* We can't have 8 bit displacement here. */
5832 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5834 /* The PC relative address is computed relative
5835 to the instruction boundary, so in case immediate
5836 fields follows, we need to adjust the value. */
5837 if (pcrel
&& i
.imm_operands
)
5842 for (n1
= 0; n1
< i
.operands
; n1
++)
5843 if (operand_type_check (i
.types
[n1
], imm
))
5845 /* Only one immediate is allowed for PC
5846 relative address. */
5847 gas_assert (sz
== 0);
5849 i
.op
[n
].disps
->X_add_number
-= sz
;
5851 /* We should find the immediate. */
5852 gas_assert (sz
!= 0);
5855 p
= frag_more (size
);
5856 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5858 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5859 && (((reloc_type
== BFD_RELOC_32
5860 || reloc_type
== BFD_RELOC_X86_64_32S
5861 || (reloc_type
== BFD_RELOC_64
5863 && (i
.op
[n
].disps
->X_op
== O_symbol
5864 || (i
.op
[n
].disps
->X_op
== O_add
5865 && ((symbol_get_value_expression
5866 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5868 || reloc_type
== BFD_RELOC_32_PCREL
))
5872 if (insn_start_frag
== frag_now
)
5873 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5878 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5879 for (fr
= insn_start_frag
->fr_next
;
5880 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5882 add
+= p
- frag_now
->fr_literal
;
5887 reloc_type
= BFD_RELOC_386_GOTPC
;
5888 i
.op
[n
].imms
->X_add_number
+= add
;
5890 else if (reloc_type
== BFD_RELOC_64
)
5891 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5893 /* Don't do the adjustment for x86-64, as there
5894 the pcrel addressing is relative to the _next_
5895 insn, and that is taken care of in other code. */
5896 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5898 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5899 i
.op
[n
].disps
, pcrel
, reloc_type
);
5906 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5911 for (n
= 0; n
< i
.operands
; n
++)
5913 if (operand_type_check (i
.types
[n
], imm
))
5915 if (i
.op
[n
].imms
->X_op
== O_constant
)
5917 int size
= imm_size (n
);
5920 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5922 p
= frag_more (size
);
5923 md_number_to_chars (p
, val
, size
);
5927 /* Not absolute_section.
5928 Need a 32-bit fixup (don't support 8bit
5929 non-absolute imms). Try to support other
5931 enum bfd_reloc_code_real reloc_type
;
5932 int size
= imm_size (n
);
5935 if (i
.types
[n
].bitfield
.imm32s
5936 && (i
.suffix
== QWORD_MNEM_SUFFIX
5937 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5942 p
= frag_more (size
);
5943 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5945 /* This is tough to explain. We end up with this one if we
5946 * have operands that look like
5947 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5948 * obtain the absolute address of the GOT, and it is strongly
5949 * preferable from a performance point of view to avoid using
5950 * a runtime relocation for this. The actual sequence of
5951 * instructions often look something like:
5956 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5958 * The call and pop essentially return the absolute address
5959 * of the label .L66 and store it in %ebx. The linker itself
5960 * will ultimately change the first operand of the addl so
5961 * that %ebx points to the GOT, but to keep things simple, the
5962 * .o file must have this operand set so that it generates not
5963 * the absolute address of .L66, but the absolute address of
5964 * itself. This allows the linker itself simply treat a GOTPC
5965 * relocation as asking for a pcrel offset to the GOT to be
5966 * added in, and the addend of the relocation is stored in the
5967 * operand field for the instruction itself.
5969 * Our job here is to fix the operand so that it would add
5970 * the correct offset so that %ebx would point to itself. The
5971 * thing that is tricky is that .-.L66 will point to the
5972 * beginning of the instruction, so we need to further modify
5973 * the operand so that it will point to itself. There are
5974 * other cases where you have something like:
5976 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5978 * and here no correction would be required. Internally in
5979 * the assembler we treat operands of this form as not being
5980 * pcrel since the '.' is explicitly mentioned, and I wonder
5981 * whether it would simplify matters to do it this way. Who
5982 * knows. In earlier versions of the PIC patches, the
5983 * pcrel_adjust field was used to store the correction, but
5984 * since the expression is not pcrel, I felt it would be
5985 * confusing to do it this way. */
5987 if ((reloc_type
== BFD_RELOC_32
5988 || reloc_type
== BFD_RELOC_X86_64_32S
5989 || reloc_type
== BFD_RELOC_64
)
5991 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5992 && (i
.op
[n
].imms
->X_op
== O_symbol
5993 || (i
.op
[n
].imms
->X_op
== O_add
5994 && ((symbol_get_value_expression
5995 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6000 if (insn_start_frag
== frag_now
)
6001 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6006 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6007 for (fr
= insn_start_frag
->fr_next
;
6008 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6010 add
+= p
- frag_now
->fr_literal
;
6014 reloc_type
= BFD_RELOC_386_GOTPC
;
6016 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6018 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6019 i
.op
[n
].imms
->X_add_number
+= add
;
6021 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6022 i
.op
[n
].imms
, 0, reloc_type
);
6028 /* x86_cons_fix_new is called via the expression parsing code when a
6029 reloc is needed. We use this hook to get the correct .got reloc. */
6030 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6031 static int cons_sign
= -1;
6034 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6037 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6039 got_reloc
= NO_RELOC
;
6042 if (exp
->X_op
== O_secrel
)
6044 exp
->X_op
= O_symbol
;
6045 r
= BFD_RELOC_32_SECREL
;
6049 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6052 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6053 # define lex_got(reloc, adjust, types) NULL
6055 /* Parse operands of the form
6056 <symbol>@GOTOFF+<nnn>
6057 and similar .plt or .got references.
6059 If we find one, set up the correct relocation in RELOC and copy the
6060 input string, minus the `@GOTOFF' into a malloc'd buffer for
6061 parsing by the calling routine. Return this buffer, and if ADJUST
6062 is non-null set it to the length of the string we removed from the
6063 input line. Otherwise return NULL. */
6065 lex_got (enum bfd_reloc_code_real
*reloc
,
6067 i386_operand_type
*types
)
6069 /* Some of the relocations depend on the size of what field is to
6070 be relocated. But in our callers i386_immediate and i386_displacement
6071 we don't yet know the operand size (this will be set by insn
6072 matching). Hence we record the word32 relocation here,
6073 and adjust the reloc according to the real size in reloc(). */
6074 static const struct {
6076 const enum bfd_reloc_code_real rel
[2];
6077 const i386_operand_type types64
;
6079 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6080 BFD_RELOC_X86_64_PLTOFF64
},
6081 OPERAND_TYPE_IMM64
},
6082 { "PLT", { BFD_RELOC_386_PLT32
,
6083 BFD_RELOC_X86_64_PLT32
},
6084 OPERAND_TYPE_IMM32_32S_DISP32
},
6085 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6086 BFD_RELOC_X86_64_GOTPLT64
},
6087 OPERAND_TYPE_IMM64_DISP64
},
6088 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6089 BFD_RELOC_X86_64_GOTOFF64
},
6090 OPERAND_TYPE_IMM64_DISP64
},
6091 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6092 BFD_RELOC_X86_64_GOTPCREL
},
6093 OPERAND_TYPE_IMM32_32S_DISP32
},
6094 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6095 BFD_RELOC_X86_64_TLSGD
},
6096 OPERAND_TYPE_IMM32_32S_DISP32
},
6097 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6098 _dummy_first_bfd_reloc_code_real
},
6099 OPERAND_TYPE_NONE
},
6100 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6101 BFD_RELOC_X86_64_TLSLD
},
6102 OPERAND_TYPE_IMM32_32S_DISP32
},
6103 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6104 BFD_RELOC_X86_64_GOTTPOFF
},
6105 OPERAND_TYPE_IMM32_32S_DISP32
},
6106 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6107 BFD_RELOC_X86_64_TPOFF32
},
6108 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6109 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6110 _dummy_first_bfd_reloc_code_real
},
6111 OPERAND_TYPE_NONE
},
6112 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6113 BFD_RELOC_X86_64_DTPOFF32
},
6115 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6116 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6117 _dummy_first_bfd_reloc_code_real
},
6118 OPERAND_TYPE_NONE
},
6119 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6120 _dummy_first_bfd_reloc_code_real
},
6121 OPERAND_TYPE_NONE
},
6122 { "GOT", { BFD_RELOC_386_GOT32
,
6123 BFD_RELOC_X86_64_GOT32
},
6124 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6125 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6126 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6127 OPERAND_TYPE_IMM32_32S_DISP32
},
6128 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6129 BFD_RELOC_X86_64_TLSDESC_CALL
},
6130 OPERAND_TYPE_IMM32_32S_DISP32
},
6138 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6139 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6142 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6146 len
= strlen (gotrel
[j
].str
);
6147 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6149 if (gotrel
[j
].rel
[object_64bit
] != 0)
6152 char *tmpbuf
, *past_reloc
;
6154 *reloc
= gotrel
[j
].rel
[object_64bit
];
6160 if (flag_code
!= CODE_64BIT
)
6162 types
->bitfield
.imm32
= 1;
6163 types
->bitfield
.disp32
= 1;
6166 *types
= gotrel
[j
].types64
;
6169 if (GOT_symbol
== NULL
)
6170 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6172 /* The length of the first part of our input line. */
6173 first
= cp
- input_line_pointer
;
6175 /* The second part goes from after the reloc token until
6176 (and including) an end_of_line char or comma. */
6177 past_reloc
= cp
+ 1 + len
;
6179 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6181 second
= cp
+ 1 - past_reloc
;
6183 /* Allocate and copy string. The trailing NUL shouldn't
6184 be necessary, but be safe. */
6185 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6186 memcpy (tmpbuf
, input_line_pointer
, first
);
6187 if (second
!= 0 && *past_reloc
!= ' ')
6188 /* Replace the relocation token with ' ', so that
6189 errors like foo@GOTOFF1 will be detected. */
6190 tmpbuf
[first
++] = ' ';
6191 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6192 tmpbuf
[first
+ second
] = '\0';
6196 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6197 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6202 /* Might be a symbol version string. Don't as_bad here. */
6207 x86_cons (expressionS
*exp
, int size
)
6209 intel_syntax
= -intel_syntax
;
6211 if (size
== 4 || (object_64bit
&& size
== 8))
6213 /* Handle @GOTOFF and the like in an expression. */
6215 char *gotfree_input_line
;
6218 save
= input_line_pointer
;
6219 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6220 if (gotfree_input_line
)
6221 input_line_pointer
= gotfree_input_line
;
6225 if (gotfree_input_line
)
6227 /* expression () has merrily parsed up to the end of line,
6228 or a comma - in the wrong buffer. Transfer how far
6229 input_line_pointer has moved to the right buffer. */
6230 input_line_pointer
= (save
6231 + (input_line_pointer
- gotfree_input_line
)
6233 free (gotfree_input_line
);
6234 if (exp
->X_op
== O_constant
6235 || exp
->X_op
== O_absent
6236 || exp
->X_op
== O_illegal
6237 || exp
->X_op
== O_register
6238 || exp
->X_op
== O_big
)
6240 char c
= *input_line_pointer
;
6241 *input_line_pointer
= 0;
6242 as_bad (_("missing or invalid expression `%s'"), save
);
6243 *input_line_pointer
= c
;
6250 intel_syntax
= -intel_syntax
;
6253 i386_intel_simplify (exp
);
6258 signed_cons (int size
)
6260 if (flag_code
== CODE_64BIT
)
6268 pe_directive_secrel (dummy
)
6269 int dummy ATTRIBUTE_UNUSED
;
6276 if (exp
.X_op
== O_symbol
)
6277 exp
.X_op
= O_secrel
;
6279 emit_expr (&exp
, 4);
6281 while (*input_line_pointer
++ == ',');
6283 input_line_pointer
--;
6284 demand_empty_rest_of_line ();
6289 i386_immediate (char *imm_start
)
6291 char *save_input_line_pointer
;
6292 char *gotfree_input_line
;
6295 i386_operand_type types
;
6297 operand_type_set (&types
, ~0);
6299 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6301 as_bad (_("at most %d immediate operands are allowed"),
6302 MAX_IMMEDIATE_OPERANDS
);
6306 exp
= &im_expressions
[i
.imm_operands
++];
6307 i
.op
[this_operand
].imms
= exp
;
6309 if (is_space_char (*imm_start
))
6312 save_input_line_pointer
= input_line_pointer
;
6313 input_line_pointer
= imm_start
;
6315 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6316 if (gotfree_input_line
)
6317 input_line_pointer
= gotfree_input_line
;
6319 exp_seg
= expression (exp
);
6322 if (*input_line_pointer
)
6323 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6325 input_line_pointer
= save_input_line_pointer
;
6326 if (gotfree_input_line
)
6328 free (gotfree_input_line
);
6330 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6331 exp
->X_op
= O_illegal
;
6334 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6338 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6339 i386_operand_type types
, const char *imm_start
)
6341 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6344 as_bad (_("missing or invalid immediate expression `%s'"),
6348 else if (exp
->X_op
== O_constant
)
6350 /* Size it properly later. */
6351 i
.types
[this_operand
].bitfield
.imm64
= 1;
6352 /* If BFD64, sign extend val. */
6353 if (!use_rela_relocations
6354 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6356 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6358 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6359 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6360 && exp_seg
!= absolute_section
6361 && exp_seg
!= text_section
6362 && exp_seg
!= data_section
6363 && exp_seg
!= bss_section
6364 && exp_seg
!= undefined_section
6365 && !bfd_is_com_section (exp_seg
))
6367 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6371 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6374 as_bad (_("illegal immediate register operand %s"), imm_start
);
6379 /* This is an address. The size of the address will be
6380 determined later, depending on destination register,
6381 suffix, or the default for the section. */
6382 i
.types
[this_operand
].bitfield
.imm8
= 1;
6383 i
.types
[this_operand
].bitfield
.imm16
= 1;
6384 i
.types
[this_operand
].bitfield
.imm32
= 1;
6385 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6386 i
.types
[this_operand
].bitfield
.imm64
= 1;
6387 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6395 i386_scale (char *scale
)
6398 char *save
= input_line_pointer
;
6400 input_line_pointer
= scale
;
6401 val
= get_absolute_expression ();
6406 i
.log2_scale_factor
= 0;
6409 i
.log2_scale_factor
= 1;
6412 i
.log2_scale_factor
= 2;
6415 i
.log2_scale_factor
= 3;
6419 char sep
= *input_line_pointer
;
6421 *input_line_pointer
= '\0';
6422 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6424 *input_line_pointer
= sep
;
6425 input_line_pointer
= save
;
6429 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6431 as_warn (_("scale factor of %d without an index register"),
6432 1 << i
.log2_scale_factor
);
6433 i
.log2_scale_factor
= 0;
6435 scale
= input_line_pointer
;
6436 input_line_pointer
= save
;
6441 i386_displacement (char *disp_start
, char *disp_end
)
6445 char *save_input_line_pointer
;
6446 char *gotfree_input_line
;
6448 i386_operand_type bigdisp
, types
= anydisp
;
6451 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6453 as_bad (_("at most %d displacement operands are allowed"),
6454 MAX_MEMORY_OPERANDS
);
6458 operand_type_set (&bigdisp
, 0);
6459 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6460 || (!current_templates
->start
->opcode_modifier
.jump
6461 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6463 bigdisp
.bitfield
.disp32
= 1;
6464 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6465 if (flag_code
== CODE_64BIT
)
6469 bigdisp
.bitfield
.disp32s
= 1;
6470 bigdisp
.bitfield
.disp64
= 1;
6473 else if ((flag_code
== CODE_16BIT
) ^ override
)
6475 bigdisp
.bitfield
.disp32
= 0;
6476 bigdisp
.bitfield
.disp16
= 1;
6481 /* For PC-relative branches, the width of the displacement
6482 is dependent upon data size, not address size. */
6483 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6484 if (flag_code
== CODE_64BIT
)
6486 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6487 bigdisp
.bitfield
.disp16
= 1;
6490 bigdisp
.bitfield
.disp32
= 1;
6491 bigdisp
.bitfield
.disp32s
= 1;
6497 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6499 : LONG_MNEM_SUFFIX
));
6500 bigdisp
.bitfield
.disp32
= 1;
6501 if ((flag_code
== CODE_16BIT
) ^ override
)
6503 bigdisp
.bitfield
.disp32
= 0;
6504 bigdisp
.bitfield
.disp16
= 1;
6508 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6511 exp
= &disp_expressions
[i
.disp_operands
];
6512 i
.op
[this_operand
].disps
= exp
;
6514 save_input_line_pointer
= input_line_pointer
;
6515 input_line_pointer
= disp_start
;
6516 END_STRING_AND_SAVE (disp_end
);
6518 #ifndef GCC_ASM_O_HACK
6519 #define GCC_ASM_O_HACK 0
6522 END_STRING_AND_SAVE (disp_end
+ 1);
6523 if (i
.types
[this_operand
].bitfield
.baseIndex
6524 && displacement_string_end
[-1] == '+')
6526 /* This hack is to avoid a warning when using the "o"
6527 constraint within gcc asm statements.
6530 #define _set_tssldt_desc(n,addr,limit,type) \
6531 __asm__ __volatile__ ( \
6533 "movw %w1,2+%0\n\t" \
6535 "movb %b1,4+%0\n\t" \
6536 "movb %4,5+%0\n\t" \
6537 "movb $0,6+%0\n\t" \
6538 "movb %h1,7+%0\n\t" \
6540 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6542 This works great except that the output assembler ends
6543 up looking a bit weird if it turns out that there is
6544 no offset. You end up producing code that looks like:
6557 So here we provide the missing zero. */
6559 *displacement_string_end
= '0';
6562 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6563 if (gotfree_input_line
)
6564 input_line_pointer
= gotfree_input_line
;
6566 exp_seg
= expression (exp
);
6569 if (*input_line_pointer
)
6570 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6572 RESTORE_END_STRING (disp_end
+ 1);
6574 input_line_pointer
= save_input_line_pointer
;
6575 if (gotfree_input_line
)
6577 free (gotfree_input_line
);
6579 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6580 exp
->X_op
= O_illegal
;
6583 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6585 RESTORE_END_STRING (disp_end
);
6591 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6592 i386_operand_type types
, const char *disp_start
)
6594 i386_operand_type bigdisp
;
6597 /* We do this to make sure that the section symbol is in
6598 the symbol table. We will ultimately change the relocation
6599 to be relative to the beginning of the section. */
6600 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6601 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6602 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6604 if (exp
->X_op
!= O_symbol
)
6607 if (S_IS_LOCAL (exp
->X_add_symbol
)
6608 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6609 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6610 exp
->X_op
= O_subtract
;
6611 exp
->X_op_symbol
= GOT_symbol
;
6612 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6613 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6614 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6615 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6617 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6620 else if (exp
->X_op
== O_absent
6621 || exp
->X_op
== O_illegal
6622 || exp
->X_op
== O_big
)
6625 as_bad (_("missing or invalid displacement expression `%s'"),
6630 else if (flag_code
== CODE_64BIT
6631 && !i
.prefix
[ADDR_PREFIX
]
6632 && exp
->X_op
== O_constant
)
6634 /* Since displacement is signed extended to 64bit, don't allow
6635 disp32 and turn off disp32s if they are out of range. */
6636 i
.types
[this_operand
].bitfield
.disp32
= 0;
6637 if (!fits_in_signed_long (exp
->X_add_number
))
6639 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6640 if (i
.types
[this_operand
].bitfield
.baseindex
)
6642 as_bad (_("0x%lx out range of signed 32bit displacement"),
6643 (long) exp
->X_add_number
);
6649 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6650 else if (exp
->X_op
!= O_constant
6651 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6652 && exp_seg
!= absolute_section
6653 && exp_seg
!= text_section
6654 && exp_seg
!= data_section
6655 && exp_seg
!= bss_section
6656 && exp_seg
!= undefined_section
6657 && !bfd_is_com_section (exp_seg
))
6659 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6664 /* Check if this is a displacement only operand. */
6665 bigdisp
= i
.types
[this_operand
];
6666 bigdisp
.bitfield
.disp8
= 0;
6667 bigdisp
.bitfield
.disp16
= 0;
6668 bigdisp
.bitfield
.disp32
= 0;
6669 bigdisp
.bitfield
.disp32s
= 0;
6670 bigdisp
.bitfield
.disp64
= 0;
6671 if (operand_type_all_zero (&bigdisp
))
6672 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6678 /* Make sure the memory operand we've been dealt is valid.
6679 Return 1 on success, 0 on a failure. */
6682 i386_index_check (const char *operand_string
)
6685 const char *kind
= "base/index";
6686 #if INFER_ADDR_PREFIX
6692 if (current_templates
->start
->opcode_modifier
.isstring
6693 && !current_templates
->start
->opcode_modifier
.immext
6694 && (current_templates
->end
[-1].opcode_modifier
.isstring
6697 /* Memory operands of string insns are special in that they only allow
6698 a single register (rDI, rSI, or rBX) as their memory address. */
6699 unsigned int expected
;
6701 kind
= "string address";
6703 if (current_templates
->start
->opcode_modifier
.w
)
6705 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6707 if (!type
.bitfield
.baseindex
6708 || ((!i
.mem_operands
!= !intel_syntax
)
6709 && current_templates
->end
[-1].operand_types
[1]
6710 .bitfield
.baseindex
))
6711 type
= current_templates
->end
[-1].operand_types
[1];
6712 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6715 expected
= 3 /* rBX */;
6717 if (!i
.base_reg
|| i
.index_reg
6718 || operand_type_check (i
.types
[this_operand
], disp
))
6720 else if (!(flag_code
== CODE_64BIT
6721 ? i
.prefix
[ADDR_PREFIX
]
6722 ? i
.base_reg
->reg_type
.bitfield
.reg32
6723 : i
.base_reg
->reg_type
.bitfield
.reg64
6724 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6725 ? i
.base_reg
->reg_type
.bitfield
.reg32
6726 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6728 else if (i
.base_reg
->reg_num
!= expected
)
6735 for (j
= 0; j
< i386_regtab_size
; ++j
)
6736 if ((flag_code
== CODE_64BIT
6737 ? i
.prefix
[ADDR_PREFIX
]
6738 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6739 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6740 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6741 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6742 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6743 && i386_regtab
[j
].reg_num
== expected
)
6745 gas_assert (j
< i386_regtab_size
);
6746 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6748 intel_syntax
? '[' : '(',
6750 i386_regtab
[j
].reg_name
,
6751 intel_syntax
? ']' : ')');
6755 else if (flag_code
== CODE_64BIT
)
6758 && ((i
.prefix
[ADDR_PREFIX
] == 0
6759 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6760 || (i
.prefix
[ADDR_PREFIX
]
6761 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6763 || i
.base_reg
->reg_num
!=
6764 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6766 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6767 || (i
.prefix
[ADDR_PREFIX
] == 0
6768 && i
.index_reg
->reg_num
!= RegRiz
6769 && !i
.index_reg
->reg_type
.bitfield
.reg64
6771 || (i
.prefix
[ADDR_PREFIX
]
6772 && i
.index_reg
->reg_num
!= RegEiz
6773 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6778 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6782 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6783 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6785 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6786 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6788 && i
.base_reg
->reg_num
< 6
6789 && i
.index_reg
->reg_num
>= 6
6790 && i
.log2_scale_factor
== 0))))
6797 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6799 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6800 && i
.index_reg
->reg_num
!= RegEiz
)
6801 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6807 #if INFER_ADDR_PREFIX
6808 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6810 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6812 /* Change the size of any displacement too. At most one of
6813 Disp16 or Disp32 is set.
6814 FIXME. There doesn't seem to be any real need for separate
6815 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6816 Removing them would probably clean up the code quite a lot. */
6817 if (flag_code
!= CODE_64BIT
6818 && (i
.types
[this_operand
].bitfield
.disp16
6819 || i
.types
[this_operand
].bitfield
.disp32
))
6820 i
.types
[this_operand
]
6821 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6826 as_bad (_("`%s' is not a valid %s expression"),
6831 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6833 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6834 ? flag_code
== CODE_32BIT
6843 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6847 i386_att_operand (char *operand_string
)
6851 char *op_string
= operand_string
;
6853 if (is_space_char (*op_string
))
6856 /* We check for an absolute prefix (differentiating,
6857 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6858 if (*op_string
== ABSOLUTE_PREFIX
)
6861 if (is_space_char (*op_string
))
6863 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6866 /* Check if operand is a register. */
6867 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6869 i386_operand_type temp
;
6871 /* Check for a segment override by searching for ':' after a
6872 segment register. */
6874 if (is_space_char (*op_string
))
6876 if (*op_string
== ':'
6877 && (r
->reg_type
.bitfield
.sreg2
6878 || r
->reg_type
.bitfield
.sreg3
))
6883 i
.seg
[i
.mem_operands
] = &es
;
6886 i
.seg
[i
.mem_operands
] = &cs
;
6889 i
.seg
[i
.mem_operands
] = &ss
;
6892 i
.seg
[i
.mem_operands
] = &ds
;
6895 i
.seg
[i
.mem_operands
] = &fs
;
6898 i
.seg
[i
.mem_operands
] = &gs
;
6902 /* Skip the ':' and whitespace. */
6904 if (is_space_char (*op_string
))
6907 if (!is_digit_char (*op_string
)
6908 && !is_identifier_char (*op_string
)
6909 && *op_string
!= '('
6910 && *op_string
!= ABSOLUTE_PREFIX
)
6912 as_bad (_("bad memory operand `%s'"), op_string
);
6915 /* Handle case of %es:*foo. */
6916 if (*op_string
== ABSOLUTE_PREFIX
)
6919 if (is_space_char (*op_string
))
6921 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6923 goto do_memory_reference
;
6927 as_bad (_("junk `%s' after register"), op_string
);
6931 temp
.bitfield
.baseindex
= 0;
6932 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6934 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6935 i
.op
[this_operand
].regs
= r
;
6938 else if (*op_string
== REGISTER_PREFIX
)
6940 as_bad (_("bad register name `%s'"), op_string
);
6943 else if (*op_string
== IMMEDIATE_PREFIX
)
6946 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6948 as_bad (_("immediate operand illegal with absolute jump"));
6951 if (!i386_immediate (op_string
))
6954 else if (is_digit_char (*op_string
)
6955 || is_identifier_char (*op_string
)
6956 || *op_string
== '(')
6958 /* This is a memory reference of some sort. */
6961 /* Start and end of displacement string expression (if found). */
6962 char *displacement_string_start
;
6963 char *displacement_string_end
;
6965 do_memory_reference
:
6966 if ((i
.mem_operands
== 1
6967 && !current_templates
->start
->opcode_modifier
.isstring
)
6968 || i
.mem_operands
== 2)
6970 as_bad (_("too many memory references for `%s'"),
6971 current_templates
->start
->name
);
6975 /* Check for base index form. We detect the base index form by
6976 looking for an ')' at the end of the operand, searching
6977 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6979 base_string
= op_string
+ strlen (op_string
);
6982 if (is_space_char (*base_string
))
6985 /* If we only have a displacement, set-up for it to be parsed later. */
6986 displacement_string_start
= op_string
;
6987 displacement_string_end
= base_string
+ 1;
6989 if (*base_string
== ')')
6992 unsigned int parens_balanced
= 1;
6993 /* We've already checked that the number of left & right ()'s are
6994 equal, so this loop will not be infinite. */
6998 if (*base_string
== ')')
7000 if (*base_string
== '(')
7003 while (parens_balanced
);
7005 temp_string
= base_string
;
7007 /* Skip past '(' and whitespace. */
7009 if (is_space_char (*base_string
))
7012 if (*base_string
== ','
7013 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7016 displacement_string_end
= temp_string
;
7018 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7022 base_string
= end_op
;
7023 if (is_space_char (*base_string
))
7027 /* There may be an index reg or scale factor here. */
7028 if (*base_string
== ',')
7031 if (is_space_char (*base_string
))
7034 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7037 base_string
= end_op
;
7038 if (is_space_char (*base_string
))
7040 if (*base_string
== ',')
7043 if (is_space_char (*base_string
))
7046 else if (*base_string
!= ')')
7048 as_bad (_("expecting `,' or `)' "
7049 "after index register in `%s'"),
7054 else if (*base_string
== REGISTER_PREFIX
)
7056 as_bad (_("bad register name `%s'"), base_string
);
7060 /* Check for scale factor. */
7061 if (*base_string
!= ')')
7063 char *end_scale
= i386_scale (base_string
);
7068 base_string
= end_scale
;
7069 if (is_space_char (*base_string
))
7071 if (*base_string
!= ')')
7073 as_bad (_("expecting `)' "
7074 "after scale factor in `%s'"),
7079 else if (!i
.index_reg
)
7081 as_bad (_("expecting index register or scale factor "
7082 "after `,'; got '%c'"),
7087 else if (*base_string
!= ')')
7089 as_bad (_("expecting `,' or `)' "
7090 "after base register in `%s'"),
7095 else if (*base_string
== REGISTER_PREFIX
)
7097 as_bad (_("bad register name `%s'"), base_string
);
7102 /* If there's an expression beginning the operand, parse it,
7103 assuming displacement_string_start and
7104 displacement_string_end are meaningful. */
7105 if (displacement_string_start
!= displacement_string_end
)
7107 if (!i386_displacement (displacement_string_start
,
7108 displacement_string_end
))
7112 /* Special case for (%dx) while doing input/output op. */
7114 && operand_type_equal (&i
.base_reg
->reg_type
,
7115 ®16_inoutportreg
)
7117 && i
.log2_scale_factor
== 0
7118 && i
.seg
[i
.mem_operands
] == 0
7119 && !operand_type_check (i
.types
[this_operand
], disp
))
7121 i
.types
[this_operand
] = inoutportreg
;
7125 if (i386_index_check (operand_string
) == 0)
7127 i
.types
[this_operand
].bitfield
.mem
= 1;
7132 /* It's not a memory operand; argh! */
7133 as_bad (_("invalid char %s beginning operand %d `%s'"),
7134 output_invalid (*op_string
),
7139 return 1; /* Normal return. */
7142 /* md_estimate_size_before_relax()
7144 Called just before relax() for rs_machine_dependent frags. The x86
7145 assembler uses these frags to handle variable size jump
7148 Any symbol that is now undefined will not become defined.
7149 Return the correct fr_subtype in the frag.
7150 Return the initial "guess for variable size of frag" to caller.
7151 The guess is actually the growth beyond the fixed part. Whatever
7152 we do to grow the fixed or variable part contributes to our
7156 md_estimate_size_before_relax (fragP
, segment
)
7160 /* We've already got fragP->fr_subtype right; all we have to do is
7161 check for un-relaxable symbols. On an ELF system, we can't relax
7162 an externally visible symbol, because it may be overridden by a
7164 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7165 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7167 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7168 || S_IS_WEAK (fragP
->fr_symbol
)
7169 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7170 & BSF_GNU_INDIRECT_FUNCTION
))))
7172 #if defined (OBJ_COFF) && defined (TE_PE)
7173 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7174 && S_IS_WEAK (fragP
->fr_symbol
))
7178 /* Symbol is undefined in this segment, or we need to keep a
7179 reloc so that weak symbols can be overridden. */
7180 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7181 enum bfd_reloc_code_real reloc_type
;
7182 unsigned char *opcode
;
7185 if (fragP
->fr_var
!= NO_RELOC
)
7186 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7188 reloc_type
= BFD_RELOC_16_PCREL
;
7190 reloc_type
= BFD_RELOC_32_PCREL
;
7192 old_fr_fix
= fragP
->fr_fix
;
7193 opcode
= (unsigned char *) fragP
->fr_opcode
;
7195 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7198 /* Make jmp (0xeb) a (d)word displacement jump. */
7200 fragP
->fr_fix
+= size
;
7201 fix_new (fragP
, old_fr_fix
, size
,
7203 fragP
->fr_offset
, 1,
7209 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7211 /* Negate the condition, and branch past an
7212 unconditional jump. */
7215 /* Insert an unconditional jump. */
7217 /* We added two extra opcode bytes, and have a two byte
7219 fragP
->fr_fix
+= 2 + 2;
7220 fix_new (fragP
, old_fr_fix
+ 2, 2,
7222 fragP
->fr_offset
, 1,
7229 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7234 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7236 fragP
->fr_offset
, 1,
7238 fixP
->fx_signed
= 1;
7242 /* This changes the byte-displacement jump 0x7N
7243 to the (d)word-displacement jump 0x0f,0x8N. */
7244 opcode
[1] = opcode
[0] + 0x10;
7245 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7246 /* We've added an opcode byte. */
7247 fragP
->fr_fix
+= 1 + size
;
7248 fix_new (fragP
, old_fr_fix
+ 1, size
,
7250 fragP
->fr_offset
, 1,
7255 BAD_CASE (fragP
->fr_subtype
);
7259 return fragP
->fr_fix
- old_fr_fix
;
7262 /* Guess size depending on current relax state. Initially the relax
7263 state will correspond to a short jump and we return 1, because
7264 the variable part of the frag (the branch offset) is one byte
7265 long. However, we can relax a section more than once and in that
7266 case we must either set fr_subtype back to the unrelaxed state,
7267 or return the value for the appropriate branch. */
7268 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7271 /* Called after relax() is finished.
7273 In: Address of frag.
7274 fr_type == rs_machine_dependent.
7275 fr_subtype is what the address relaxed to.
7277 Out: Any fixSs and constants are set up.
7278 Caller will turn frag into a ".space 0". */
7281 md_convert_frag (abfd
, sec
, fragP
)
7282 bfd
*abfd ATTRIBUTE_UNUSED
;
7283 segT sec ATTRIBUTE_UNUSED
;
7286 unsigned char *opcode
;
7287 unsigned char *where_to_put_displacement
= NULL
;
7288 offsetT target_address
;
7289 offsetT opcode_address
;
7290 unsigned int extension
= 0;
7291 offsetT displacement_from_opcode_start
;
7293 opcode
= (unsigned char *) fragP
->fr_opcode
;
7295 /* Address we want to reach in file space. */
7296 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7298 /* Address opcode resides at in file space. */
7299 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7301 /* Displacement from opcode start to fill into instruction. */
7302 displacement_from_opcode_start
= target_address
- opcode_address
;
7304 if ((fragP
->fr_subtype
& BIG
) == 0)
7306 /* Don't have to change opcode. */
7307 extension
= 1; /* 1 opcode + 1 displacement */
7308 where_to_put_displacement
= &opcode
[1];
7312 if (no_cond_jump_promotion
7313 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7314 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7315 _("long jump required"));
7317 switch (fragP
->fr_subtype
)
7319 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7320 extension
= 4; /* 1 opcode + 4 displacement */
7322 where_to_put_displacement
= &opcode
[1];
7325 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7326 extension
= 2; /* 1 opcode + 2 displacement */
7328 where_to_put_displacement
= &opcode
[1];
7331 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7332 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7333 extension
= 5; /* 2 opcode + 4 displacement */
7334 opcode
[1] = opcode
[0] + 0x10;
7335 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7336 where_to_put_displacement
= &opcode
[2];
7339 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7340 extension
= 3; /* 2 opcode + 2 displacement */
7341 opcode
[1] = opcode
[0] + 0x10;
7342 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7343 where_to_put_displacement
= &opcode
[2];
7346 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7351 where_to_put_displacement
= &opcode
[3];
7355 BAD_CASE (fragP
->fr_subtype
);
7360 /* If size if less then four we are sure that the operand fits,
7361 but if it's 4, then it could be that the displacement is larger
7363 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7365 && ((addressT
) (displacement_from_opcode_start
- extension
7366 + ((addressT
) 1 << 31))
7367 > (((addressT
) 2 << 31) - 1)))
7369 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7370 _("jump target out of range"));
7371 /* Make us emit 0. */
7372 displacement_from_opcode_start
= extension
;
7374 /* Now put displacement after opcode. */
7375 md_number_to_chars ((char *) where_to_put_displacement
,
7376 (valueT
) (displacement_from_opcode_start
- extension
),
7377 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7378 fragP
->fr_fix
+= extension
;
7381 /* Apply a fixup (fixS) to segment data, once it has been determined
7382 by our caller that we have all the info we need to fix it up.
7384 On the 386, immediates, displacements, and data pointers are all in
7385 the same (little-endian) format, so we don't need to care about which
7389 md_apply_fix (fixP
, valP
, seg
)
7390 /* The fix we're to put in. */
7392 /* Pointer to the value of the bits. */
7394 /* Segment fix is from. */
7395 segT seg ATTRIBUTE_UNUSED
;
7397 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7398 valueT value
= *valP
;
7400 #if !defined (TE_Mach)
7403 switch (fixP
->fx_r_type
)
7409 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7412 case BFD_RELOC_X86_64_32S
:
7413 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7416 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7419 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7424 if (fixP
->fx_addsy
!= NULL
7425 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7426 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7427 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7428 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7429 && !use_rela_relocations
)
7431 /* This is a hack. There should be a better way to handle this.
7432 This covers for the fact that bfd_install_relocation will
7433 subtract the current location (for partial_inplace, PC relative
7434 relocations); see more below. */
7438 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7441 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7446 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7449 || (symbol_section_p (fixP
->fx_addsy
)
7450 && sym_seg
!= absolute_section
))
7451 && !generic_force_reloc (fixP
))
7453 /* Yes, we add the values in twice. This is because
7454 bfd_install_relocation subtracts them out again. I think
7455 bfd_install_relocation is broken, but I don't dare change
7457 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7461 #if defined (OBJ_COFF) && defined (TE_PE)
7462 /* For some reason, the PE format does not store a
7463 section address offset for a PC relative symbol. */
7464 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7465 || S_IS_WEAK (fixP
->fx_addsy
))
7466 value
+= md_pcrel_from (fixP
);
7469 #if defined (OBJ_COFF) && defined (TE_PE)
7470 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7472 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7476 /* Fix a few things - the dynamic linker expects certain values here,
7477 and we must not disappoint it. */
7478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7479 if (IS_ELF
&& fixP
->fx_addsy
)
7480 switch (fixP
->fx_r_type
)
7482 case BFD_RELOC_386_PLT32
:
7483 case BFD_RELOC_X86_64_PLT32
:
7484 /* Make the jump instruction point to the address of the operand. At
7485 runtime we merely add the offset to the actual PLT entry. */
7489 case BFD_RELOC_386_TLS_GD
:
7490 case BFD_RELOC_386_TLS_LDM
:
7491 case BFD_RELOC_386_TLS_IE_32
:
7492 case BFD_RELOC_386_TLS_IE
:
7493 case BFD_RELOC_386_TLS_GOTIE
:
7494 case BFD_RELOC_386_TLS_GOTDESC
:
7495 case BFD_RELOC_X86_64_TLSGD
:
7496 case BFD_RELOC_X86_64_TLSLD
:
7497 case BFD_RELOC_X86_64_GOTTPOFF
:
7498 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7499 value
= 0; /* Fully resolved at runtime. No addend. */
7501 case BFD_RELOC_386_TLS_LE
:
7502 case BFD_RELOC_386_TLS_LDO_32
:
7503 case BFD_RELOC_386_TLS_LE_32
:
7504 case BFD_RELOC_X86_64_DTPOFF32
:
7505 case BFD_RELOC_X86_64_DTPOFF64
:
7506 case BFD_RELOC_X86_64_TPOFF32
:
7507 case BFD_RELOC_X86_64_TPOFF64
:
7508 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7511 case BFD_RELOC_386_TLS_DESC_CALL
:
7512 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7513 value
= 0; /* Fully resolved at runtime. No addend. */
7514 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7518 case BFD_RELOC_386_GOT32
:
7519 case BFD_RELOC_X86_64_GOT32
:
7520 value
= 0; /* Fully resolved at runtime. No addend. */
7523 case BFD_RELOC_VTABLE_INHERIT
:
7524 case BFD_RELOC_VTABLE_ENTRY
:
7531 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7533 #endif /* !defined (TE_Mach) */
7535 /* Are we finished with this relocation now? */
7536 if (fixP
->fx_addsy
== NULL
)
7538 #if defined (OBJ_COFF) && defined (TE_PE)
7539 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7542 /* Remember value for tc_gen_reloc. */
7543 fixP
->fx_addnumber
= value
;
7544 /* Clear out the frag for now. */
7548 else if (use_rela_relocations
)
7550 fixP
->fx_no_overflow
= 1;
7551 /* Remember value for tc_gen_reloc. */
7552 fixP
->fx_addnumber
= value
;
7556 md_number_to_chars (p
, value
, fixP
->fx_size
);
7560 md_atof (int type
, char *litP
, int *sizeP
)
7562 /* This outputs the LITTLENUMs in REVERSE order;
7563 in accord with the bigendian 386. */
7564 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7567 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7570 output_invalid (int c
)
7573 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7576 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7577 "(0x%x)", (unsigned char) c
);
7578 return output_invalid_buf
;
7581 /* REG_STRING starts *before* REGISTER_PREFIX. */
7583 static const reg_entry
*
7584 parse_real_register (char *reg_string
, char **end_op
)
7586 char *s
= reg_string
;
7588 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7591 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7592 if (*s
== REGISTER_PREFIX
)
7595 if (is_space_char (*s
))
7599 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7601 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7602 return (const reg_entry
*) NULL
;
7606 /* For naked regs, make sure that we are not dealing with an identifier.
7607 This prevents confusing an identifier like `eax_var' with register
7609 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7610 return (const reg_entry
*) NULL
;
7614 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7616 /* Handle floating point regs, allowing spaces in the (i) part. */
7617 if (r
== i386_regtab
/* %st is first entry of table */)
7619 if (is_space_char (*s
))
7624 if (is_space_char (*s
))
7626 if (*s
>= '0' && *s
<= '7')
7630 if (is_space_char (*s
))
7635 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7640 /* We have "%st(" then garbage. */
7641 return (const reg_entry
*) NULL
;
7645 if (r
== NULL
|| allow_pseudo_reg
)
7648 if (operand_type_all_zero (&r
->reg_type
))
7649 return (const reg_entry
*) NULL
;
7651 if ((r
->reg_type
.bitfield
.reg32
7652 || r
->reg_type
.bitfield
.sreg3
7653 || r
->reg_type
.bitfield
.control
7654 || r
->reg_type
.bitfield
.debug
7655 || r
->reg_type
.bitfield
.test
)
7656 && !cpu_arch_flags
.bitfield
.cpui386
)
7657 return (const reg_entry
*) NULL
;
7659 if (r
->reg_type
.bitfield
.floatreg
7660 && !cpu_arch_flags
.bitfield
.cpu8087
7661 && !cpu_arch_flags
.bitfield
.cpu287
7662 && !cpu_arch_flags
.bitfield
.cpu387
)
7663 return (const reg_entry
*) NULL
;
7665 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7666 return (const reg_entry
*) NULL
;
7668 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7669 return (const reg_entry
*) NULL
;
7671 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7672 return (const reg_entry
*) NULL
;
7674 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7675 if (!allow_index_reg
7676 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7677 return (const reg_entry
*) NULL
;
7679 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7680 || r
->reg_type
.bitfield
.reg64
)
7681 && (!cpu_arch_flags
.bitfield
.cpulm
7682 || !operand_type_equal (&r
->reg_type
, &control
))
7683 && flag_code
!= CODE_64BIT
)
7684 return (const reg_entry
*) NULL
;
7686 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7687 return (const reg_entry
*) NULL
;
7692 /* REG_STRING starts *before* REGISTER_PREFIX. */
7694 static const reg_entry
*
7695 parse_register (char *reg_string
, char **end_op
)
7699 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7700 r
= parse_real_register (reg_string
, end_op
);
7705 char *save
= input_line_pointer
;
7709 input_line_pointer
= reg_string
;
7710 c
= get_symbol_end ();
7711 symbolP
= symbol_find (reg_string
);
7712 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7714 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7716 know (e
->X_op
== O_register
);
7717 know (e
->X_add_number
>= 0
7718 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7719 r
= i386_regtab
+ e
->X_add_number
;
7720 *end_op
= input_line_pointer
;
7722 *input_line_pointer
= c
;
7723 input_line_pointer
= save
;
7729 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7732 char *end
= input_line_pointer
;
7735 r
= parse_register (name
, &input_line_pointer
);
7736 if (r
&& end
<= input_line_pointer
)
7738 *nextcharP
= *input_line_pointer
;
7739 *input_line_pointer
= 0;
7740 e
->X_op
= O_register
;
7741 e
->X_add_number
= r
- i386_regtab
;
7744 input_line_pointer
= end
;
7746 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7750 md_operand (expressionS
*e
)
7755 switch (*input_line_pointer
)
7757 case REGISTER_PREFIX
:
7758 r
= parse_real_register (input_line_pointer
, &end
);
7761 e
->X_op
= O_register
;
7762 e
->X_add_number
= r
- i386_regtab
;
7763 input_line_pointer
= end
;
7768 gas_assert (intel_syntax
);
7769 end
= input_line_pointer
++;
7771 if (*input_line_pointer
== ']')
7773 ++input_line_pointer
;
7774 e
->X_op_symbol
= make_expr_symbol (e
);
7775 e
->X_add_symbol
= NULL
;
7776 e
->X_add_number
= 0;
7782 input_line_pointer
= end
;
7789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7790 const char *md_shortopts
= "kVQ:sqn";
7792 const char *md_shortopts
= "qn";
7795 #define OPTION_32 (OPTION_MD_BASE + 0)
7796 #define OPTION_64 (OPTION_MD_BASE + 1)
7797 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7798 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7799 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7800 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7801 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7802 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7803 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7804 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7805 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7806 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7808 struct option md_longopts
[] =
7810 {"32", no_argument
, NULL
, OPTION_32
},
7811 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7812 || defined (TE_PE) || defined (TE_PEP))
7813 {"64", no_argument
, NULL
, OPTION_64
},
7815 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7816 {"march", required_argument
, NULL
, OPTION_MARCH
},
7817 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7818 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7819 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7820 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7821 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7822 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7823 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7824 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7825 {NULL
, no_argument
, NULL
, 0}
7827 size_t md_longopts_size
= sizeof (md_longopts
);
7830 md_parse_option (int c
, char *arg
)
7838 optimize_align_code
= 0;
7845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7846 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7847 should be emitted or not. FIXME: Not implemented. */
7851 /* -V: SVR4 argument to print version ID. */
7853 print_version_id ();
7856 /* -k: Ignore for FreeBSD compatibility. */
7861 /* -s: On i386 Solaris, this tells the native assembler to use
7862 .stab instead of .stab.excl. We always use .stab anyhow. */
7865 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7866 || defined (TE_PE) || defined (TE_PEP))
7869 const char **list
, **l
;
7871 list
= bfd_target_list ();
7872 for (l
= list
; *l
!= NULL
; l
++)
7873 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7874 || strcmp (*l
, "coff-x86-64") == 0
7875 || strcmp (*l
, "pe-x86-64") == 0
7876 || strcmp (*l
, "pei-x86-64") == 0)
7878 default_arch
= "x86_64";
7882 as_fatal (_("No compiled in support for x86_64"));
7889 default_arch
= "i386";
7893 #ifdef SVR4_COMMENT_CHARS
7898 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7900 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7904 i386_comment_chars
= n
;
7910 arch
= xstrdup (arg
);
7914 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7915 next
= strchr (arch
, '+');
7918 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7920 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7923 cpu_arch_name
= cpu_arch
[i
].name
;
7924 cpu_sub_arch_name
= NULL
;
7925 cpu_arch_flags
= cpu_arch
[i
].flags
;
7926 cpu_arch_isa
= cpu_arch
[i
].type
;
7927 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7928 if (!cpu_arch_tune_set
)
7930 cpu_arch_tune
= cpu_arch_isa
;
7931 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7935 else if (*cpu_arch
[i
].name
== '.'
7936 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7938 /* ISA entension. */
7939 i386_cpu_flags flags
;
7941 if (strncmp (arch
, "no", 2))
7942 flags
= cpu_flags_or (cpu_arch_flags
,
7945 flags
= cpu_flags_and_not (cpu_arch_flags
,
7947 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7949 if (cpu_sub_arch_name
)
7951 char *name
= cpu_sub_arch_name
;
7952 cpu_sub_arch_name
= concat (name
,
7954 (const char *) NULL
);
7958 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7959 cpu_arch_flags
= flags
;
7965 if (i
>= ARRAY_SIZE (cpu_arch
))
7966 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7970 while (next
!= NULL
);
7975 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7976 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7978 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7980 cpu_arch_tune_set
= 1;
7981 cpu_arch_tune
= cpu_arch
[i
].type
;
7982 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7986 if (i
>= ARRAY_SIZE (cpu_arch
))
7987 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7990 case OPTION_MMNEMONIC
:
7991 if (strcasecmp (arg
, "att") == 0)
7993 else if (strcasecmp (arg
, "intel") == 0)
7996 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7999 case OPTION_MSYNTAX
:
8000 if (strcasecmp (arg
, "att") == 0)
8002 else if (strcasecmp (arg
, "intel") == 0)
8005 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8008 case OPTION_MINDEX_REG
:
8009 allow_index_reg
= 1;
8012 case OPTION_MNAKED_REG
:
8013 allow_naked_reg
= 1;
8016 case OPTION_MOLD_GCC
:
8020 case OPTION_MSSE2AVX
:
8024 case OPTION_MSSE_CHECK
:
8025 if (strcasecmp (arg
, "error") == 0)
8026 sse_check
= sse_check_error
;
8027 else if (strcasecmp (arg
, "warning") == 0)
8028 sse_check
= sse_check_warning
;
8029 else if (strcasecmp (arg
, "none") == 0)
8030 sse_check
= sse_check_none
;
8032 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8042 md_show_usage (stream
)
8045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8046 fprintf (stream
, _("\
8048 -V print assembler version number\n\
8051 fprintf (stream
, _("\
8052 -n Do not optimize code alignment\n\
8053 -q quieten some warnings\n"));
8054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8055 fprintf (stream
, _("\
8058 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8059 || defined (TE_PE) || defined (TE_PEP))
8060 fprintf (stream
, _("\
8061 --32/--64 generate 32bit/64bit code\n"));
8063 #ifdef SVR4_COMMENT_CHARS
8064 fprintf (stream
, _("\
8065 --divide do not treat `/' as a comment character\n"));
8067 fprintf (stream
, _("\
8068 --divide ignored\n"));
8070 fprintf (stream
, _("\
8071 -march=CPU[,+EXTENSION...]\n\
8072 generate code for CPU and EXTENSION, CPU is one of:\n\
8073 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8074 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8075 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8076 amdfam10, generic32, generic64\n\
8077 EXTENSION is combination of:\n\
8078 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8079 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8080 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8081 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8082 svme, abm, padlock, fma4, lwp\n"));
8083 fprintf (stream
, _("\
8084 -mtune=CPU optimize for CPU, CPU is one of:\n\
8085 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8086 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8087 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8088 amdfam10, generic32, generic64\n"));
8089 fprintf (stream
, _("\
8090 -msse2avx encode SSE instructions with VEX prefix\n"));
8091 fprintf (stream
, _("\
8092 -msse-check=[none|error|warning]\n\
8093 check SSE instructions\n"));
8094 fprintf (stream
, _("\
8095 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8096 fprintf (stream
, _("\
8097 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8098 fprintf (stream
, _("\
8099 -mindex-reg support pseudo index registers\n"));
8100 fprintf (stream
, _("\
8101 -mnaked-reg don't require `%%' prefix for registers\n"));
8102 fprintf (stream
, _("\
8103 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8106 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8107 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8108 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8110 /* Pick the target format to use. */
8113 i386_target_format (void)
8115 if (!strcmp (default_arch
, "x86_64"))
8117 set_code_flag (CODE_64BIT
);
8118 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8120 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8121 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8122 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8123 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8124 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8125 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8126 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8127 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8128 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8129 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8130 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8132 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8134 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8135 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8136 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8137 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8138 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8139 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8140 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8141 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8142 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8143 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8146 else if (!strcmp (default_arch
, "i386"))
8148 set_code_flag (CODE_32BIT
);
8149 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8151 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8152 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8153 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8155 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8157 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8158 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8159 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8163 as_fatal (_("Unknown architecture"));
8164 switch (OUTPUT_FLAVOR
)
8166 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8167 case bfd_target_aout_flavour
:
8168 return AOUT_TARGET_FORMAT
;
8170 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8171 # if defined (TE_PE) || defined (TE_PEP)
8172 case bfd_target_coff_flavour
:
8173 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8174 # elif defined (TE_GO32)
8175 case bfd_target_coff_flavour
:
8178 case bfd_target_coff_flavour
:
8182 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8183 case bfd_target_elf_flavour
:
8185 if (flag_code
== CODE_64BIT
)
8188 use_rela_relocations
= 1;
8190 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8192 if (flag_code
!= CODE_64BIT
)
8193 as_fatal (_("Intel L1OM is 64bit only"));
8194 return ELF_TARGET_L1OM_FORMAT
;
8197 return (flag_code
== CODE_64BIT
8198 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8201 #if defined (OBJ_MACH_O)
8202 case bfd_target_mach_o_flavour
:
8203 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8211 #endif /* OBJ_MAYBE_ more than one */
8213 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8215 i386_elf_emit_arch_note (void)
8217 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8220 asection
*seg
= now_seg
;
8221 subsegT subseg
= now_subseg
;
8222 Elf_Internal_Note i_note
;
8223 Elf_External_Note e_note
;
8224 asection
*note_secp
;
8227 /* Create the .note section. */
8228 note_secp
= subseg_new (".note", 0);
8229 bfd_set_section_flags (stdoutput
,
8231 SEC_HAS_CONTENTS
| SEC_READONLY
);
8233 /* Process the arch string. */
8234 len
= strlen (cpu_arch_name
);
8236 i_note
.namesz
= len
+ 1;
8238 i_note
.type
= NT_ARCH
;
8239 p
= frag_more (sizeof (e_note
.namesz
));
8240 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8241 p
= frag_more (sizeof (e_note
.descsz
));
8242 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8243 p
= frag_more (sizeof (e_note
.type
));
8244 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8245 p
= frag_more (len
+ 1);
8246 strcpy (p
, cpu_arch_name
);
8248 frag_align (2, 0, 0);
8250 subseg_set (seg
, subseg
);
8256 md_undefined_symbol (name
)
8259 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8260 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8261 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8262 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8266 if (symbol_find (name
))
8267 as_bad (_("GOT already in symbol table"));
8268 GOT_symbol
= symbol_new (name
, undefined_section
,
8269 (valueT
) 0, &zero_address_frag
);
8276 /* Round up a section size to the appropriate boundary. */
8279 md_section_align (segment
, size
)
8280 segT segment ATTRIBUTE_UNUSED
;
8283 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8284 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8286 /* For a.out, force the section size to be aligned. If we don't do
8287 this, BFD will align it for us, but it will not write out the
8288 final bytes of the section. This may be a bug in BFD, but it is
8289 easier to fix it here since that is how the other a.out targets
8293 align
= bfd_get_section_alignment (stdoutput
, segment
);
8294 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8301 /* On the i386, PC-relative offsets are relative to the start of the
8302 next instruction. That is, the address of the offset, plus its
8303 size, since the offset is always the last part of the insn. */
8306 md_pcrel_from (fixS
*fixP
)
8308 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8314 s_bss (int ignore ATTRIBUTE_UNUSED
)
8318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8320 obj_elf_section_change_hook ();
8322 temp
= get_absolute_expression ();
8323 subseg_set (bss_section
, (subsegT
) temp
);
8324 demand_empty_rest_of_line ();
8330 i386_validate_fix (fixS
*fixp
)
8332 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8334 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8338 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8343 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8345 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8352 tc_gen_reloc (section
, fixp
)
8353 asection
*section ATTRIBUTE_UNUSED
;
8357 bfd_reloc_code_real_type code
;
8359 switch (fixp
->fx_r_type
)
8361 case BFD_RELOC_X86_64_PLT32
:
8362 case BFD_RELOC_X86_64_GOT32
:
8363 case BFD_RELOC_X86_64_GOTPCREL
:
8364 case BFD_RELOC_386_PLT32
:
8365 case BFD_RELOC_386_GOT32
:
8366 case BFD_RELOC_386_GOTOFF
:
8367 case BFD_RELOC_386_GOTPC
:
8368 case BFD_RELOC_386_TLS_GD
:
8369 case BFD_RELOC_386_TLS_LDM
:
8370 case BFD_RELOC_386_TLS_LDO_32
:
8371 case BFD_RELOC_386_TLS_IE_32
:
8372 case BFD_RELOC_386_TLS_IE
:
8373 case BFD_RELOC_386_TLS_GOTIE
:
8374 case BFD_RELOC_386_TLS_LE_32
:
8375 case BFD_RELOC_386_TLS_LE
:
8376 case BFD_RELOC_386_TLS_GOTDESC
:
8377 case BFD_RELOC_386_TLS_DESC_CALL
:
8378 case BFD_RELOC_X86_64_TLSGD
:
8379 case BFD_RELOC_X86_64_TLSLD
:
8380 case BFD_RELOC_X86_64_DTPOFF32
:
8381 case BFD_RELOC_X86_64_DTPOFF64
:
8382 case BFD_RELOC_X86_64_GOTTPOFF
:
8383 case BFD_RELOC_X86_64_TPOFF32
:
8384 case BFD_RELOC_X86_64_TPOFF64
:
8385 case BFD_RELOC_X86_64_GOTOFF64
:
8386 case BFD_RELOC_X86_64_GOTPC32
:
8387 case BFD_RELOC_X86_64_GOT64
:
8388 case BFD_RELOC_X86_64_GOTPCREL64
:
8389 case BFD_RELOC_X86_64_GOTPC64
:
8390 case BFD_RELOC_X86_64_GOTPLT64
:
8391 case BFD_RELOC_X86_64_PLTOFF64
:
8392 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8393 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8395 case BFD_RELOC_VTABLE_ENTRY
:
8396 case BFD_RELOC_VTABLE_INHERIT
:
8398 case BFD_RELOC_32_SECREL
:
8400 code
= fixp
->fx_r_type
;
8402 case BFD_RELOC_X86_64_32S
:
8403 if (!fixp
->fx_pcrel
)
8405 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8406 code
= fixp
->fx_r_type
;
8412 switch (fixp
->fx_size
)
8415 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8416 _("can not do %d byte pc-relative relocation"),
8418 code
= BFD_RELOC_32_PCREL
;
8420 case 1: code
= BFD_RELOC_8_PCREL
; break;
8421 case 2: code
= BFD_RELOC_16_PCREL
; break;
8422 case 4: code
= BFD_RELOC_32_PCREL
; break;
8424 case 8: code
= BFD_RELOC_64_PCREL
; break;
8430 switch (fixp
->fx_size
)
8433 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8434 _("can not do %d byte relocation"),
8436 code
= BFD_RELOC_32
;
8438 case 1: code
= BFD_RELOC_8
; break;
8439 case 2: code
= BFD_RELOC_16
; break;
8440 case 4: code
= BFD_RELOC_32
; break;
8442 case 8: code
= BFD_RELOC_64
; break;
8449 if ((code
== BFD_RELOC_32
8450 || code
== BFD_RELOC_32_PCREL
8451 || code
== BFD_RELOC_X86_64_32S
)
8453 && fixp
->fx_addsy
== GOT_symbol
)
8456 code
= BFD_RELOC_386_GOTPC
;
8458 code
= BFD_RELOC_X86_64_GOTPC32
;
8460 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8462 && fixp
->fx_addsy
== GOT_symbol
)
8464 code
= BFD_RELOC_X86_64_GOTPC64
;
8467 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8468 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8469 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8471 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8473 if (!use_rela_relocations
)
8475 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8476 vtable entry to be used in the relocation's section offset. */
8477 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8478 rel
->address
= fixp
->fx_offset
;
8479 #if defined (OBJ_COFF) && defined (TE_PE)
8480 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8481 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8486 /* Use the rela in 64bit mode. */
8489 if (!fixp
->fx_pcrel
)
8490 rel
->addend
= fixp
->fx_offset
;
8494 case BFD_RELOC_X86_64_PLT32
:
8495 case BFD_RELOC_X86_64_GOT32
:
8496 case BFD_RELOC_X86_64_GOTPCREL
:
8497 case BFD_RELOC_X86_64_TLSGD
:
8498 case BFD_RELOC_X86_64_TLSLD
:
8499 case BFD_RELOC_X86_64_GOTTPOFF
:
8500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8501 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8502 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8505 rel
->addend
= (section
->vma
8507 + fixp
->fx_addnumber
8508 + md_pcrel_from (fixp
));
8513 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8514 if (rel
->howto
== NULL
)
8516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8517 _("cannot represent relocation type %s"),
8518 bfd_get_reloc_code_name (code
));
8519 /* Set howto to a garbage value so that we can keep going. */
8520 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8521 gas_assert (rel
->howto
!= NULL
);
8527 #include "tc-i386-intel.c"
8530 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8532 int saved_naked_reg
;
8533 char saved_register_dot
;
8535 saved_naked_reg
= allow_naked_reg
;
8536 allow_naked_reg
= 1;
8537 saved_register_dot
= register_chars
['.'];
8538 register_chars
['.'] = '.';
8539 allow_pseudo_reg
= 1;
8540 expression_and_evaluate (exp
);
8541 allow_pseudo_reg
= 0;
8542 register_chars
['.'] = saved_register_dot
;
8543 allow_naked_reg
= saved_naked_reg
;
8545 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8547 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8549 exp
->X_op
= O_constant
;
8550 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8551 .dw2_regnum
[flag_code
>> 1];
8554 exp
->X_op
= O_illegal
;
8559 tc_x86_frame_initial_instructions (void)
8561 static unsigned int sp_regno
[2];
8563 if (!sp_regno
[flag_code
>> 1])
8565 char *saved_input
= input_line_pointer
;
8566 char sp
[][4] = {"esp", "rsp"};
8569 input_line_pointer
= sp
[flag_code
>> 1];
8570 tc_x86_parse_to_dw2regnum (&exp
);
8571 gas_assert (exp
.X_op
== O_constant
);
8572 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8573 input_line_pointer
= saved_input
;
8576 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8577 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8581 i386_elf_section_type (const char *str
, size_t len
)
8583 if (flag_code
== CODE_64BIT
8584 && len
== sizeof ("unwind") - 1
8585 && strncmp (str
, "unwind", 6) == 0)
8586 return SHT_X86_64_UNWIND
;
8593 i386_solaris_fix_up_eh_frame (segT sec
)
8595 if (flag_code
== CODE_64BIT
)
8596 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8602 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8606 expr
.X_op
= O_secrel
;
8607 expr
.X_add_symbol
= symbol
;
8608 expr
.X_add_number
= 0;
8609 emit_expr (&expr
, size
);
8613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8614 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8617 x86_64_section_letter (int letter
, char **ptr_msg
)
8619 if (flag_code
== CODE_64BIT
)
8622 return SHF_X86_64_LARGE
;
8624 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8627 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8632 x86_64_section_word (char *str
, size_t len
)
8634 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8635 return SHF_X86_64_LARGE
;
8641 handle_large_common (int small ATTRIBUTE_UNUSED
)
8643 if (flag_code
!= CODE_64BIT
)
8645 s_comm_internal (0, elf_common_parse
);
8646 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8650 static segT lbss_section
;
8651 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8652 asection
*saved_bss_section
= bss_section
;
8654 if (lbss_section
== NULL
)
8656 flagword applicable
;
8658 subsegT subseg
= now_subseg
;
8660 /* The .lbss section is for local .largecomm symbols. */
8661 lbss_section
= subseg_new (".lbss", 0);
8662 applicable
= bfd_applicable_section_flags (stdoutput
);
8663 bfd_set_section_flags (stdoutput
, lbss_section
,
8664 applicable
& SEC_ALLOC
);
8665 seg_info (lbss_section
)->bss
= 1;
8667 subseg_set (seg
, subseg
);
8670 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8671 bss_section
= lbss_section
;
8673 s_comm_internal (0, elf_common_parse
);
8675 elf_com_section_ptr
= saved_com_section_ptr
;
8676 bss_section
= saved_bss_section
;
8679 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */