1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void optimize_imm
PARAMS ((void));
93 static void optimize_disp
PARAMS ((void));
94 static int match_template
PARAMS ((void));
95 static int check_string
PARAMS ((void));
96 static int process_suffix
PARAMS ((void));
97 static int check_byte_reg
PARAMS ((void));
98 static int check_long_reg
PARAMS ((void));
99 static int check_qword_reg
PARAMS ((void));
100 static int check_word_reg
PARAMS ((void));
101 static int finalize_imm
PARAMS ((void));
102 static int process_operands
PARAMS ((void));
103 static const seg_entry
*build_modrm_byte
PARAMS ((void));
104 static void output_insn
PARAMS ((void));
105 static void output_branch
PARAMS ((void));
106 static void output_jump
PARAMS ((void));
107 static void output_interseg_jump
PARAMS ((void));
108 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
110 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
111 offsetT insn_start_off
));
113 static void s_bss
PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
119 static const char *default_arch
= DEFAULT_ARCH
;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry
*regs
;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands
;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types
[MAX_OPERANDS
];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op
[MAX_OPERANDS
];
156 /* Flags for operands. */
157 unsigned int flags
[MAX_OPERANDS
];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry
*base_reg
;
166 const reg_entry
*index_reg
;
167 unsigned int log2_scale_factor
;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry
*seg
[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes
;
176 unsigned char prefix
[MAX_PREFIXES
];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn
;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars
[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_LINUX) \
202 && !defined (TE_NETWARE) \
203 && !defined (TE_FreeBSD) \
204 && !defined (TE_NetBSD)))
205 /* This array holds the chars that always start a comment. If the
206 pre-processor is disabled, these aren't very useful. */
207 const char comment_chars
[] = "#/";
208 #define PREFIX_SEPARATOR '\\'
210 /* This array holds the chars that only start a comment at the beginning of
211 a line. If the line seems to have the form '# 123 filename'
212 .line and .file directives will appear in the pre-processed output.
213 Note that input_file.c hand checks for '#' at the beginning of the
214 first line of the input file. This is because the compiler outputs
215 #NO_APP at the beginning of its output.
216 Also note that comments started like this one will always work if
217 '/' isn't otherwise defined. */
218 const char line_comment_chars
[] = "#";
221 /* Putting '/' here makes it impossible to use the divide operator.
222 However, we need it for compatibility with SVR4 systems. */
223 const char comment_chars
[] = "#";
224 #define PREFIX_SEPARATOR '/'
226 const char line_comment_chars
[] = "/#";
229 const char line_separator_chars
[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS
[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS
[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars
[256];
242 static char register_chars
[256];
243 static char operand_chars
[256];
244 static char identifier_chars
[256];
245 static char digit_chars
[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack
[32];
263 static char *save_stack_p
;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates
*current_templates
;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions
[2], im_expressions
[2];
278 /* Current operand we are working on. */
279 static int this_operand
;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code
;
291 static unsigned int object_64bit
;
292 static int use_rela_relocations
= 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names
[] =
302 /* 1 for intel syntax,
304 static int intel_syntax
= 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg
= 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size
= '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code
= 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings
= 0;
321 static const char *cpu_arch_name
= NULL
;
322 static const char *cpu_sub_arch_name
= NULL
;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
327 /* If set, conditional jumps are not automatically promoted to handle
328 larger than a byte offset. */
329 static unsigned int no_cond_jump_promotion
= 0;
331 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
332 static symbolS
*GOT_symbol
;
334 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
335 unsigned int x86_dwarf2_return_column
;
337 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
338 int x86_cie_data_alignment
;
340 /* Interface to relax_segment.
341 There are 3 major relax states for 386 jump insns because the
342 different types of jumps add different sizes to frags when we're
343 figuring out what sort of jump to choose to reach a given label. */
346 #define UNCOND_JUMP 0
348 #define COND_JUMP86 2
353 #define SMALL16 (SMALL | CODE16)
355 #define BIG16 (BIG | CODE16)
359 #define INLINE __inline__
365 #define ENCODE_RELAX_STATE(type, size) \
366 ((relax_substateT) (((type) << 2) | (size)))
367 #define TYPE_FROM_RELAX_STATE(s) \
369 #define DISP_SIZE_FROM_RELAX_STATE(s) \
370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
372 /* This table is used by relax_frag to promote short jumps to long
373 ones where necessary. SMALL (short) jumps may be promoted to BIG
374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
375 don't allow a short jump in a 32 bit code segment to be promoted to
376 a 16 bit offset jump because it's slower (requires data size
377 prefix), and doesn't work, unless the destination is in the bottom
378 64k of the code segment (The top 16 bits of eip are zeroed). */
380 const relax_typeS md_relax_table
[] =
383 1) most positive reach of this state,
384 2) most negative reach of this state,
385 3) how many bytes this mode will have in the variable part of the frag
386 4) which index into the table to try if we can't fit into this one. */
388 /* UNCOND_JUMP states. */
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
391 /* dword jmp adds 4 bytes to frag:
392 0 extra opcode bytes, 4 displacement bytes. */
394 /* word jmp adds 2 byte2 to frag:
395 0 extra opcode bytes, 2 displacement bytes. */
398 /* COND_JUMP states. */
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
401 /* dword conditionals adds 5 bytes to frag:
402 1 extra opcode byte, 4 displacement bytes. */
404 /* word conditionals add 3 bytes to frag:
405 1 extra opcode byte, 2 displacement bytes. */
408 /* COND_JUMP86 states. */
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
411 /* dword conditionals adds 5 bytes to frag:
412 1 extra opcode byte, 4 displacement bytes. */
414 /* word conditionals add 4 bytes to frag:
415 1 displacement byte and a 3 byte long branch insn. */
419 static const arch_entry cpu_arch
[] = {
421 {"i186", Cpu086
|Cpu186
},
422 {"i286", Cpu086
|Cpu186
|Cpu286
},
423 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
424 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
425 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
426 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
427 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
428 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
429 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
430 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
431 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
432 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
433 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
434 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
435 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
436 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
437 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
439 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
440 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
441 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
442 {".3dnow", CpuMMX
|Cpu3dnow
},
443 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
444 {".padlock", CpuPadLock
},
445 {".pacifica", CpuSVME
},
450 const pseudo_typeS md_pseudo_table
[] =
452 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
453 {"align", s_align_bytes
, 0},
455 {"align", s_align_ptwo
, 0},
457 {"arch", set_cpu_arch
, 0},
461 {"ffloat", float_cons
, 'f'},
462 {"dfloat", float_cons
, 'd'},
463 {"tfloat", float_cons
, 'x'},
465 {"slong", signed_cons
, 4},
466 {"noopt", s_ignore
, 0},
467 {"optim", s_ignore
, 0},
468 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
469 {"code16", set_code_flag
, CODE_16BIT
},
470 {"code32", set_code_flag
, CODE_32BIT
},
471 {"code64", set_code_flag
, CODE_64BIT
},
472 {"intel_syntax", set_intel_syntax
, 1},
473 {"att_syntax", set_intel_syntax
, 0},
474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
475 {"largecomm", handle_large_common
, 0},
477 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
478 {"loc", dwarf2_directive_loc
, 0},
479 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
482 {"secrel32", pe_directive_secrel
, 0},
487 /* For interface with expression (). */
488 extern char *input_line_pointer
;
490 /* Hash table for instruction mnemonic lookup. */
491 static struct hash_control
*op_hash
;
493 /* Hash table for register lookup. */
494 static struct hash_control
*reg_hash
;
497 i386_align_code (fragP
, count
)
501 /* Various efficient no-op patterns for aligning code labels.
502 Note: Don't try to assemble the instructions in the comments.
503 0L and 0w are not legal. */
504 static const char f32_1
[] =
506 static const char f32_2
[] =
507 {0x89,0xf6}; /* movl %esi,%esi */
508 static const char f32_3
[] =
509 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
510 static const char f32_4
[] =
511 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
512 static const char f32_5
[] =
514 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
515 static const char f32_6
[] =
516 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
517 static const char f32_7
[] =
518 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
519 static const char f32_8
[] =
521 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
522 static const char f32_9
[] =
523 {0x89,0xf6, /* movl %esi,%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_10
[] =
526 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
527 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
528 static const char f32_11
[] =
529 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
530 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
531 static const char f32_12
[] =
532 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
533 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
534 static const char f32_13
[] =
535 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
536 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
537 static const char f32_14
[] =
538 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
539 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
540 static const char f32_15
[] =
541 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
542 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
543 static const char f16_3
[] =
544 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
545 static const char f16_4
[] =
546 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
547 static const char f16_5
[] =
549 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
550 static const char f16_6
[] =
551 {0x89,0xf6, /* mov %si,%si */
552 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
553 static const char f16_7
[] =
554 {0x8d,0x74,0x00, /* lea 0(%si),%si */
555 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
556 static const char f16_8
[] =
557 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
558 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
559 static const char *const f32_patt
[] = {
560 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
561 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
563 static const char *const f16_patt
[] = {
564 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
565 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
568 if (count
<= 0 || count
> 15)
571 /* The recommended way to pad 64bit code is to use NOPs preceded by
572 maximally four 0x66 prefixes. Balance the size of nops. */
573 if (flag_code
== CODE_64BIT
)
576 int nnops
= (count
+ 3) / 4;
577 int len
= count
/ nnops
;
578 int remains
= count
- nnops
* len
;
581 for (i
= 0; i
< remains
; i
++)
583 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
584 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
587 for (; i
< nnops
; i
++)
589 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
590 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
595 if (flag_code
== CODE_16BIT
)
597 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
598 f16_patt
[count
- 1], count
);
600 /* Adjust jump offset. */
601 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
604 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
605 f32_patt
[count
- 1], count
);
606 fragP
->fr_var
= count
;
609 static INLINE
unsigned int
610 mode_from_disp_size (t
)
613 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
617 fits_in_signed_byte (num
)
620 return (num
>= -128) && (num
<= 127);
624 fits_in_unsigned_byte (num
)
627 return (num
& 0xff) == num
;
631 fits_in_unsigned_word (num
)
634 return (num
& 0xffff) == num
;
638 fits_in_signed_word (num
)
641 return (-32768 <= num
) && (num
<= 32767);
644 fits_in_signed_long (num
)
645 offsetT num ATTRIBUTE_UNUSED
;
650 return (!(((offsetT
) -1 << 31) & num
)
651 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
653 } /* fits_in_signed_long() */
655 fits_in_unsigned_long (num
)
656 offsetT num ATTRIBUTE_UNUSED
;
661 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
663 } /* fits_in_unsigned_long() */
666 smallest_imm_type (num
)
669 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
671 /* This code is disabled on the 486 because all the Imm1 forms
672 in the opcode table are slower on the i486. They're the
673 versions with the implicitly specified single-position
674 displacement, which has another syntax if you really want to
677 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
679 return (fits_in_signed_byte (num
)
680 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
681 : fits_in_unsigned_byte (num
)
682 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
683 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
684 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
685 : fits_in_signed_long (num
)
686 ? (Imm32
| Imm32S
| Imm64
)
687 : fits_in_unsigned_long (num
)
693 offset_in_range (val
, size
)
701 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
702 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
703 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
705 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
710 /* If BFD64, sign extend val. */
711 if (!use_rela_relocations
)
712 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
713 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
715 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
717 char buf1
[40], buf2
[40];
719 sprint_value (buf1
, val
);
720 sprint_value (buf2
, val
& mask
);
721 as_warn (_("%s shortened to %s"), buf1
, buf2
);
726 /* Returns 0 if attempting to add a prefix where one from the same
727 class already exists, 1 if non rep/repne added, 2 if rep/repne
736 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
737 && flag_code
== CODE_64BIT
)
745 case CS_PREFIX_OPCODE
:
746 case DS_PREFIX_OPCODE
:
747 case ES_PREFIX_OPCODE
:
748 case FS_PREFIX_OPCODE
:
749 case GS_PREFIX_OPCODE
:
750 case SS_PREFIX_OPCODE
:
754 case REPNE_PREFIX_OPCODE
:
755 case REPE_PREFIX_OPCODE
:
758 case LOCK_PREFIX_OPCODE
:
766 case ADDR_PREFIX_OPCODE
:
770 case DATA_PREFIX_OPCODE
:
775 if (i
.prefix
[q
] != 0)
777 as_bad (_("same type of prefix used twice"));
782 i
.prefix
[q
] = prefix
;
787 set_code_flag (value
)
791 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
792 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
793 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
795 as_bad (_("64bit mode not supported on this CPU."));
797 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
799 as_bad (_("32bit mode not supported on this CPU."));
805 set_16bit_gcc_code_flag (new_code_flag
)
808 flag_code
= new_code_flag
;
809 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
810 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
811 stackop_size
= LONG_MNEM_SUFFIX
;
815 set_intel_syntax (syntax_flag
)
818 /* Find out if register prefixing is specified. */
819 int ask_naked_reg
= 0;
822 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
824 char *string
= input_line_pointer
;
825 int e
= get_symbol_end ();
827 if (strcmp (string
, "prefix") == 0)
829 else if (strcmp (string
, "noprefix") == 0)
832 as_bad (_("bad argument to syntax directive."));
833 *input_line_pointer
= e
;
835 demand_empty_rest_of_line ();
837 intel_syntax
= syntax_flag
;
839 if (ask_naked_reg
== 0)
840 allow_naked_reg
= (intel_syntax
841 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
843 allow_naked_reg
= (ask_naked_reg
< 0);
845 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
846 identifier_chars
['$'] = intel_syntax
? '$' : 0;
851 int dummy ATTRIBUTE_UNUSED
;
855 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
857 char *string
= input_line_pointer
;
858 int e
= get_symbol_end ();
861 for (i
= 0; cpu_arch
[i
].name
; i
++)
863 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
867 cpu_arch_name
= cpu_arch
[i
].name
;
868 cpu_sub_arch_name
= NULL
;
869 cpu_arch_flags
= (cpu_arch
[i
].flags
870 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
873 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
875 cpu_sub_arch_name
= cpu_arch
[i
].name
;
876 cpu_arch_flags
|= cpu_arch
[i
].flags
;
878 *input_line_pointer
= e
;
879 demand_empty_rest_of_line ();
883 if (!cpu_arch
[i
].name
)
884 as_bad (_("no such architecture: `%s'"), string
);
886 *input_line_pointer
= e
;
889 as_bad (_("missing cpu architecture"));
891 no_cond_jump_promotion
= 0;
892 if (*input_line_pointer
== ','
893 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
895 char *string
= ++input_line_pointer
;
896 int e
= get_symbol_end ();
898 if (strcmp (string
, "nojumps") == 0)
899 no_cond_jump_promotion
= 1;
900 else if (strcmp (string
, "jumps") == 0)
903 as_bad (_("no such architecture modifier: `%s'"), string
);
905 *input_line_pointer
= e
;
908 demand_empty_rest_of_line ();
914 if (!strcmp (default_arch
, "x86_64"))
915 return bfd_mach_x86_64
;
916 else if (!strcmp (default_arch
, "i386"))
917 return bfd_mach_i386_i386
;
919 as_fatal (_("Unknown architecture"));
925 const char *hash_err
;
927 /* Initialize op_hash hash table. */
928 op_hash
= hash_new ();
931 const template *optab
;
932 templates
*core_optab
;
934 /* Setup for loop. */
936 core_optab
= (templates
*) xmalloc (sizeof (templates
));
937 core_optab
->start
= optab
;
942 if (optab
->name
== NULL
943 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
945 /* different name --> ship out current template list;
946 add to hash table; & begin anew. */
947 core_optab
->end
= optab
;
948 hash_err
= hash_insert (op_hash
,
953 as_fatal (_("Internal Error: Can't hash %s: %s"),
957 if (optab
->name
== NULL
)
959 core_optab
= (templates
*) xmalloc (sizeof (templates
));
960 core_optab
->start
= optab
;
965 /* Initialize reg_hash hash table. */
966 reg_hash
= hash_new ();
968 const reg_entry
*regtab
;
970 for (regtab
= i386_regtab
;
971 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
974 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
976 as_fatal (_("Internal Error: Can't hash %s: %s"),
982 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
987 for (c
= 0; c
< 256; c
++)
992 mnemonic_chars
[c
] = c
;
993 register_chars
[c
] = c
;
994 operand_chars
[c
] = c
;
996 else if (ISLOWER (c
))
998 mnemonic_chars
[c
] = c
;
999 register_chars
[c
] = c
;
1000 operand_chars
[c
] = c
;
1002 else if (ISUPPER (c
))
1004 mnemonic_chars
[c
] = TOLOWER (c
);
1005 register_chars
[c
] = mnemonic_chars
[c
];
1006 operand_chars
[c
] = c
;
1009 if (ISALPHA (c
) || ISDIGIT (c
))
1010 identifier_chars
[c
] = c
;
1013 identifier_chars
[c
] = c
;
1014 operand_chars
[c
] = c
;
1019 identifier_chars
['@'] = '@';
1022 identifier_chars
['?'] = '?';
1023 operand_chars
['?'] = '?';
1025 digit_chars
['-'] = '-';
1026 mnemonic_chars
['-'] = '-';
1027 identifier_chars
['_'] = '_';
1028 identifier_chars
['.'] = '.';
1030 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1031 operand_chars
[(unsigned char) *p
] = *p
;
1034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1037 record_alignment (text_section
, 2);
1038 record_alignment (data_section
, 2);
1039 record_alignment (bss_section
, 2);
1043 if (flag_code
== CODE_64BIT
)
1045 x86_dwarf2_return_column
= 16;
1046 x86_cie_data_alignment
= -8;
1050 x86_dwarf2_return_column
= 8;
1051 x86_cie_data_alignment
= -4;
1056 i386_print_statistics (file
)
1059 hash_print_statistics (file
, "i386 opcode", op_hash
);
1060 hash_print_statistics (file
, "i386 register", reg_hash
);
1065 /* Debugging routines for md_assemble. */
1066 static void pi
PARAMS ((char *, i386_insn
*));
1067 static void pte
PARAMS ((template *));
1068 static void pt
PARAMS ((unsigned int));
1069 static void pe
PARAMS ((expressionS
*));
1070 static void ps
PARAMS ((symbolS
*));
1079 fprintf (stdout
, "%s: template ", line
);
1081 fprintf (stdout
, " address: base %s index %s scale %x\n",
1082 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1083 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1084 x
->log2_scale_factor
);
1085 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1086 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1087 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1088 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1089 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1090 (x
->rex
& REX_MODE64
) != 0,
1091 (x
->rex
& REX_EXTX
) != 0,
1092 (x
->rex
& REX_EXTY
) != 0,
1093 (x
->rex
& REX_EXTZ
) != 0);
1094 for (i
= 0; i
< x
->operands
; i
++)
1096 fprintf (stdout
, " #%d: ", i
+ 1);
1098 fprintf (stdout
, "\n");
1100 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1101 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1102 if (x
->types
[i
] & Imm
)
1104 if (x
->types
[i
] & Disp
)
1105 pe (x
->op
[i
].disps
);
1114 fprintf (stdout
, " %d operands ", t
->operands
);
1115 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1116 if (t
->extension_opcode
!= None
)
1117 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1118 if (t
->opcode_modifier
& D
)
1119 fprintf (stdout
, "D");
1120 if (t
->opcode_modifier
& W
)
1121 fprintf (stdout
, "W");
1122 fprintf (stdout
, "\n");
1123 for (i
= 0; i
< t
->operands
; i
++)
1125 fprintf (stdout
, " #%d type ", i
+ 1);
1126 pt (t
->operand_types
[i
]);
1127 fprintf (stdout
, "\n");
1135 fprintf (stdout
, " operation %d\n", e
->X_op
);
1136 fprintf (stdout
, " add_number %ld (%lx)\n",
1137 (long) e
->X_add_number
, (long) e
->X_add_number
);
1138 if (e
->X_add_symbol
)
1140 fprintf (stdout
, " add_symbol ");
1141 ps (e
->X_add_symbol
);
1142 fprintf (stdout
, "\n");
1146 fprintf (stdout
, " op_symbol ");
1147 ps (e
->X_op_symbol
);
1148 fprintf (stdout
, "\n");
1156 fprintf (stdout
, "%s type %s%s",
1158 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1159 segment_name (S_GET_SEGMENT (s
)));
1168 static const type_names
[] =
1181 { BaseIndex
, "BaseIndex" },
1185 { Disp32S
, "d32s" },
1187 { InOutPortReg
, "InOutPortReg" },
1188 { ShiftCount
, "ShiftCount" },
1189 { Control
, "control reg" },
1190 { Test
, "test reg" },
1191 { Debug
, "debug reg" },
1192 { FloatReg
, "FReg" },
1193 { FloatAcc
, "FAcc" },
1197 { JumpAbsolute
, "Jump Absolute" },
1208 const struct type_name
*ty
;
1210 for (ty
= type_names
; ty
->mask
; ty
++)
1212 fprintf (stdout
, "%s, ", ty
->tname
);
1216 #endif /* DEBUG386 */
1218 static bfd_reloc_code_real_type
1219 reloc (unsigned int size
,
1222 bfd_reloc_code_real_type other
)
1224 if (other
!= NO_RELOC
)
1226 reloc_howto_type
*reloc
;
1231 case BFD_RELOC_X86_64_TPOFF32
:
1232 other
= BFD_RELOC_X86_64_TPOFF64
;
1234 case BFD_RELOC_X86_64_DTPOFF32
:
1235 other
= BFD_RELOC_X86_64_DTPOFF64
;
1240 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1242 as_bad (_("unknown relocation (%u)"), other
);
1243 else if (size
!= bfd_get_reloc_size (reloc
))
1244 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1245 bfd_get_reloc_size (reloc
),
1247 else if (pcrel
&& !reloc
->pc_relative
)
1248 as_bad (_("non-pc-relative relocation for pc-relative field"));
1249 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1251 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1253 as_bad (_("relocated field and relocation type differ in signedness"));
1262 as_bad (_("there are no unsigned pc-relative relocations"));
1265 case 1: return BFD_RELOC_8_PCREL
;
1266 case 2: return BFD_RELOC_16_PCREL
;
1267 case 4: return BFD_RELOC_32_PCREL
;
1268 case 8: return BFD_RELOC_64_PCREL
;
1270 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1277 case 4: return BFD_RELOC_X86_64_32S
;
1282 case 1: return BFD_RELOC_8
;
1283 case 2: return BFD_RELOC_16
;
1284 case 4: return BFD_RELOC_32
;
1285 case 8: return BFD_RELOC_64
;
1287 as_bad (_("cannot do %s %u byte relocation"),
1288 sign
> 0 ? "signed" : "unsigned", size
);
1292 return BFD_RELOC_NONE
;
1295 /* Here we decide which fixups can be adjusted to make them relative to
1296 the beginning of the section instead of the symbol. Basically we need
1297 to make sure that the dynamic relocations are done correctly, so in
1298 some cases we force the original symbol to be used. */
1301 tc_i386_fix_adjustable (fixP
)
1302 fixS
*fixP ATTRIBUTE_UNUSED
;
1304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1308 /* Don't adjust pc-relative references to merge sections in 64-bit
1310 if (use_rela_relocations
1311 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1315 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1316 and changed later by validate_fix. */
1317 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1318 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1321 /* adjust_reloc_syms doesn't know about the GOT. */
1322 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1323 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1324 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1328 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1329 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1330 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1331 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1332 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1343 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1344 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1345 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1351 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1354 intel_float_operand (mnemonic
)
1355 const char *mnemonic
;
1357 /* Note that the value returned is meaningful only for opcodes with (memory)
1358 operands, hence the code here is free to improperly handle opcodes that
1359 have no operands (for better performance and smaller code). */
1361 if (mnemonic
[0] != 'f')
1362 return 0; /* non-math */
1364 switch (mnemonic
[1])
1366 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1367 the fs segment override prefix not currently handled because no
1368 call path can make opcodes without operands get here */
1370 return 2 /* integer op */;
1372 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1373 return 3; /* fldcw/fldenv */
1376 if (mnemonic
[2] != 'o' /* fnop */)
1377 return 3; /* non-waiting control op */
1380 if (mnemonic
[2] == 's')
1381 return 3; /* frstor/frstpm */
1384 if (mnemonic
[2] == 'a')
1385 return 3; /* fsave */
1386 if (mnemonic
[2] == 't')
1388 switch (mnemonic
[3])
1390 case 'c': /* fstcw */
1391 case 'd': /* fstdw */
1392 case 'e': /* fstenv */
1393 case 's': /* fsts[gw] */
1399 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1400 return 0; /* fxsave/fxrstor are not really math ops */
1407 /* This is the guts of the machine-dependent assembler. LINE points to a
1408 machine dependent instruction. This function is supposed to emit
1409 the frags/bytes it assembles to. */
1416 char mnemonic
[MAX_MNEM_SIZE
];
1418 /* Initialize globals. */
1419 memset (&i
, '\0', sizeof (i
));
1420 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1421 i
.reloc
[j
] = NO_RELOC
;
1422 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1423 memset (im_expressions
, '\0', sizeof (im_expressions
));
1424 save_stack_p
= save_stack
;
1426 /* First parse an instruction mnemonic & call i386_operand for the operands.
1427 We assume that the scrubber has arranged it so that line[0] is the valid
1428 start of a (possibly prefixed) mnemonic. */
1430 line
= parse_insn (line
, mnemonic
);
1434 line
= parse_operands (line
, mnemonic
);
1438 /* Now we've parsed the mnemonic into a set of templates, and have the
1439 operands at hand. */
1441 /* All intel opcodes have reversed operands except for "bound" and
1442 "enter". We also don't reverse intersegment "jmp" and "call"
1443 instructions with 2 immediate operands so that the immediate segment
1444 precedes the offset, as it does when in AT&T mode. "enter" and the
1445 intersegment "jmp" and "call" instructions are the only ones that
1446 have two immediate operands. */
1447 if (intel_syntax
&& i
.operands
> 1
1448 && (strcmp (mnemonic
, "bound") != 0)
1449 && (strcmp (mnemonic
, "invlpga") != 0)
1450 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1456 /* Don't optimize displacement for movabs since it only takes 64bit
1459 && (flag_code
!= CODE_64BIT
1460 || strcmp (mnemonic
, "movabs") != 0))
1463 /* Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
1467 if (!match_template ())
1472 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1474 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1475 i
.tm
.base_opcode
^= FloatR
;
1477 /* Zap movzx and movsx suffix. The suffix may have been set from
1478 "word ptr" or "byte ptr" on the source operand, but we'll use
1479 the suffix later to choose the destination register. */
1480 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1482 if (i
.reg_operands
< 2
1484 && (~i
.tm
.opcode_modifier
1491 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1497 if (i
.tm
.opcode_modifier
& FWait
)
1498 if (!add_prefix (FWAIT_OPCODE
))
1501 /* Check string instruction segment overrides. */
1502 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1504 if (!check_string ())
1508 if (!process_suffix ())
1511 /* Make still unresolved immediate matches conform to size of immediate
1512 given in i.suffix. */
1513 if (!finalize_imm ())
1516 if (i
.types
[0] & Imm1
)
1517 i
.imm_operands
= 0; /* kludge for shift insns. */
1518 if (i
.types
[0] & ImplicitRegister
)
1520 if (i
.types
[1] & ImplicitRegister
)
1522 if (i
.types
[2] & ImplicitRegister
)
1525 if (i
.tm
.opcode_modifier
& ImmExt
)
1529 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1531 /* These Intel Prescott New Instructions have the fixed
1532 operands with an opcode suffix which is coded in the same
1533 place as an 8-bit immediate field would be. Here we check
1534 those operands and remove them afterwards. */
1537 for (x
= 0; x
< i
.operands
; x
++)
1538 if (i
.op
[x
].regs
->reg_num
!= x
)
1539 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1540 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1544 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1545 opcode suffix which is coded in the same place as an 8-bit
1546 immediate field would be. Here we fake an 8-bit immediate
1547 operand from the opcode suffix stored in tm.extension_opcode. */
1549 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1551 exp
= &im_expressions
[i
.imm_operands
++];
1552 i
.op
[i
.operands
].imms
= exp
;
1553 i
.types
[i
.operands
++] = Imm8
;
1554 exp
->X_op
= O_constant
;
1555 exp
->X_add_number
= i
.tm
.extension_opcode
;
1556 i
.tm
.extension_opcode
= None
;
1559 /* For insns with operands there are more diddles to do to the opcode. */
1562 if (!process_operands ())
1565 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1567 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1568 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1571 /* Handle conversion of 'int $3' --> special int3 insn. */
1572 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1574 i
.tm
.base_opcode
= INT3_OPCODE
;
1578 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1579 && i
.op
[0].disps
->X_op
== O_constant
)
1581 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1582 the absolute address given by the constant. Since ix86 jumps and
1583 calls are pc relative, we need to generate a reloc. */
1584 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1585 i
.op
[0].disps
->X_op
= O_symbol
;
1588 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1589 i
.rex
|= REX_MODE64
;
1591 /* For 8 bit registers we need an empty rex prefix. Also if the
1592 instruction already has a prefix, we need to convert old
1593 registers to new ones. */
1595 if (((i
.types
[0] & Reg8
) != 0
1596 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1597 || ((i
.types
[1] & Reg8
) != 0
1598 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1599 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1604 i
.rex
|= REX_OPCODE
;
1605 for (x
= 0; x
< 2; x
++)
1607 /* Look for 8 bit operand that uses old registers. */
1608 if ((i
.types
[x
] & Reg8
) != 0
1609 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1611 /* In case it is "hi" register, give up. */
1612 if (i
.op
[x
].regs
->reg_num
> 3)
1613 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1614 i
.op
[x
].regs
->reg_name
);
1616 /* Otherwise it is equivalent to the extended register.
1617 Since the encoding doesn't change this is merely
1618 cosmetic cleanup for debug output. */
1620 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1626 add_prefix (REX_OPCODE
| i
.rex
);
1628 /* We are ready to output the insn. */
1633 parse_insn (line
, mnemonic
)
1638 char *token_start
= l
;
1643 /* Non-zero if we found a prefix only acceptable with string insns. */
1644 const char *expecting_string_instruction
= NULL
;
1649 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1652 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1654 as_bad (_("no such instruction: `%s'"), token_start
);
1659 if (!is_space_char (*l
)
1660 && *l
!= END_OF_INSN
1662 || (*l
!= PREFIX_SEPARATOR
1665 as_bad (_("invalid character %s in mnemonic"),
1666 output_invalid (*l
));
1669 if (token_start
== l
)
1671 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1672 as_bad (_("expecting prefix; got nothing"));
1674 as_bad (_("expecting mnemonic; got nothing"));
1678 /* Look up instruction (or prefix) via hash table. */
1679 current_templates
= hash_find (op_hash
, mnemonic
);
1681 if (*l
!= END_OF_INSN
1682 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1683 && current_templates
1684 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1686 if (current_templates
->start
->cpu_flags
1687 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1689 as_bad ((flag_code
!= CODE_64BIT
1690 ? _("`%s' is only supported in 64-bit mode")
1691 : _("`%s' is not supported in 64-bit mode")),
1692 current_templates
->start
->name
);
1695 /* If we are in 16-bit mode, do not allow addr16 or data16.
1696 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1697 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1698 && flag_code
!= CODE_64BIT
1699 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1700 ^ (flag_code
== CODE_16BIT
)))
1702 as_bad (_("redundant %s prefix"),
1703 current_templates
->start
->name
);
1706 /* Add prefix, checking for repeated prefixes. */
1707 switch (add_prefix (current_templates
->start
->base_opcode
))
1712 expecting_string_instruction
= current_templates
->start
->name
;
1715 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1722 if (!current_templates
)
1724 /* See if we can get a match by trimming off a suffix. */
1727 case WORD_MNEM_SUFFIX
:
1728 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1729 i
.suffix
= SHORT_MNEM_SUFFIX
;
1731 case BYTE_MNEM_SUFFIX
:
1732 case QWORD_MNEM_SUFFIX
:
1733 i
.suffix
= mnem_p
[-1];
1735 current_templates
= hash_find (op_hash
, mnemonic
);
1737 case SHORT_MNEM_SUFFIX
:
1738 case LONG_MNEM_SUFFIX
:
1741 i
.suffix
= mnem_p
[-1];
1743 current_templates
= hash_find (op_hash
, mnemonic
);
1751 if (intel_float_operand (mnemonic
) == 1)
1752 i
.suffix
= SHORT_MNEM_SUFFIX
;
1754 i
.suffix
= LONG_MNEM_SUFFIX
;
1756 current_templates
= hash_find (op_hash
, mnemonic
);
1760 if (!current_templates
)
1762 as_bad (_("no such instruction: `%s'"), token_start
);
1767 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1769 /* Check for a branch hint. We allow ",pt" and ",pn" for
1770 predict taken and predict not taken respectively.
1771 I'm not sure that branch hints actually do anything on loop
1772 and jcxz insns (JumpByte) for current Pentium4 chips. They
1773 may work in the future and it doesn't hurt to accept them
1775 if (l
[0] == ',' && l
[1] == 'p')
1779 if (!add_prefix (DS_PREFIX_OPCODE
))
1783 else if (l
[2] == 'n')
1785 if (!add_prefix (CS_PREFIX_OPCODE
))
1791 /* Any other comma loses. */
1794 as_bad (_("invalid character %s in mnemonic"),
1795 output_invalid (*l
));
1799 /* Check if instruction is supported on specified architecture. */
1801 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1803 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1804 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1806 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1809 if (!(supported
& 2))
1811 as_bad (flag_code
== CODE_64BIT
1812 ? _("`%s' is not supported in 64-bit mode")
1813 : _("`%s' is only supported in 64-bit mode"),
1814 current_templates
->start
->name
);
1817 if (!(supported
& 1))
1819 as_warn (_("`%s' is not supported on `%s%s'"),
1820 current_templates
->start
->name
,
1822 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1824 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1826 as_warn (_("use .code16 to ensure correct addressing mode"));
1829 /* Check for rep/repne without a string instruction. */
1830 if (expecting_string_instruction
)
1832 static templates override
;
1834 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1835 if (t
->opcode_modifier
& IsString
)
1837 if (t
>= current_templates
->end
)
1839 as_bad (_("expecting string instruction after `%s'"),
1840 expecting_string_instruction
);
1843 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1844 if (!(t
->opcode_modifier
& IsString
))
1847 current_templates
= &override
;
1854 parse_operands (l
, mnemonic
)
1856 const char *mnemonic
;
1860 /* 1 if operand is pending after ','. */
1861 unsigned int expecting_operand
= 0;
1863 /* Non-zero if operand parens not balanced. */
1864 unsigned int paren_not_balanced
;
1866 while (*l
!= END_OF_INSN
)
1868 /* Skip optional white space before operand. */
1869 if (is_space_char (*l
))
1871 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1873 as_bad (_("invalid character %s before operand %d"),
1874 output_invalid (*l
),
1878 token_start
= l
; /* after white space */
1879 paren_not_balanced
= 0;
1880 while (paren_not_balanced
|| *l
!= ',')
1882 if (*l
== END_OF_INSN
)
1884 if (paren_not_balanced
)
1887 as_bad (_("unbalanced parenthesis in operand %d."),
1890 as_bad (_("unbalanced brackets in operand %d."),
1895 break; /* we are done */
1897 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1899 as_bad (_("invalid character %s in operand %d"),
1900 output_invalid (*l
),
1907 ++paren_not_balanced
;
1909 --paren_not_balanced
;
1914 ++paren_not_balanced
;
1916 --paren_not_balanced
;
1920 if (l
!= token_start
)
1921 { /* Yes, we've read in another operand. */
1922 unsigned int operand_ok
;
1923 this_operand
= i
.operands
++;
1924 if (i
.operands
> MAX_OPERANDS
)
1926 as_bad (_("spurious operands; (%d operands/instruction max)"),
1930 /* Now parse operand adding info to 'i' as we go along. */
1931 END_STRING_AND_SAVE (l
);
1935 i386_intel_operand (token_start
,
1936 intel_float_operand (mnemonic
));
1938 operand_ok
= i386_operand (token_start
);
1940 RESTORE_END_STRING (l
);
1946 if (expecting_operand
)
1948 expecting_operand_after_comma
:
1949 as_bad (_("expecting operand after ','; got nothing"));
1954 as_bad (_("expecting operand before ','; got nothing"));
1959 /* Now *l must be either ',' or END_OF_INSN. */
1962 if (*++l
== END_OF_INSN
)
1964 /* Just skip it, if it's \n complain. */
1965 goto expecting_operand_after_comma
;
1967 expecting_operand
= 1;
1976 union i386_op temp_op
;
1977 unsigned int temp_type
;
1978 enum bfd_reloc_code_real temp_reloc
;
1982 if (i
.operands
== 2)
1987 else if (i
.operands
== 3)
1992 temp_type
= i
.types
[xchg2
];
1993 i
.types
[xchg2
] = i
.types
[xchg1
];
1994 i
.types
[xchg1
] = temp_type
;
1995 temp_op
= i
.op
[xchg2
];
1996 i
.op
[xchg2
] = i
.op
[xchg1
];
1997 i
.op
[xchg1
] = temp_op
;
1998 temp_reloc
= i
.reloc
[xchg2
];
1999 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2000 i
.reloc
[xchg1
] = temp_reloc
;
2002 if (i
.mem_operands
== 2)
2004 const seg_entry
*temp_seg
;
2005 temp_seg
= i
.seg
[0];
2006 i
.seg
[0] = i
.seg
[1];
2007 i
.seg
[1] = temp_seg
;
2011 /* Try to ensure constant immediates are represented in the smallest
2016 char guess_suffix
= 0;
2020 guess_suffix
= i
.suffix
;
2021 else if (i
.reg_operands
)
2023 /* Figure out a suffix from the last register operand specified.
2024 We can't do this properly yet, ie. excluding InOutPortReg,
2025 but the following works for instructions with immediates.
2026 In any case, we can't set i.suffix yet. */
2027 for (op
= i
.operands
; --op
>= 0;)
2028 if (i
.types
[op
] & Reg
)
2030 if (i
.types
[op
] & Reg8
)
2031 guess_suffix
= BYTE_MNEM_SUFFIX
;
2032 else if (i
.types
[op
] & Reg16
)
2033 guess_suffix
= WORD_MNEM_SUFFIX
;
2034 else if (i
.types
[op
] & Reg32
)
2035 guess_suffix
= LONG_MNEM_SUFFIX
;
2036 else if (i
.types
[op
] & Reg64
)
2037 guess_suffix
= QWORD_MNEM_SUFFIX
;
2041 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2042 guess_suffix
= WORD_MNEM_SUFFIX
;
2044 for (op
= i
.operands
; --op
>= 0;)
2045 if (i
.types
[op
] & Imm
)
2047 switch (i
.op
[op
].imms
->X_op
)
2050 /* If a suffix is given, this operand may be shortened. */
2051 switch (guess_suffix
)
2053 case LONG_MNEM_SUFFIX
:
2054 i
.types
[op
] |= Imm32
| Imm64
;
2056 case WORD_MNEM_SUFFIX
:
2057 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2059 case BYTE_MNEM_SUFFIX
:
2060 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2064 /* If this operand is at most 16 bits, convert it
2065 to a signed 16 bit number before trying to see
2066 whether it will fit in an even smaller size.
2067 This allows a 16-bit operand such as $0xffe0 to
2068 be recognised as within Imm8S range. */
2069 if ((i
.types
[op
] & Imm16
)
2070 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2072 i
.op
[op
].imms
->X_add_number
=
2073 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2075 if ((i
.types
[op
] & Imm32
)
2076 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2079 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2080 ^ ((offsetT
) 1 << 31))
2081 - ((offsetT
) 1 << 31));
2083 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2085 /* We must avoid matching of Imm32 templates when 64bit
2086 only immediate is available. */
2087 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2088 i
.types
[op
] &= ~Imm32
;
2095 /* Symbols and expressions. */
2097 /* Convert symbolic operand to proper sizes for matching, but don't
2098 prevent matching a set of insns that only supports sizes other
2099 than those matching the insn suffix. */
2101 unsigned int mask
, allowed
= 0;
2104 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2105 allowed
|= t
->operand_types
[op
];
2106 switch (guess_suffix
)
2108 case QWORD_MNEM_SUFFIX
:
2109 mask
= Imm64
| Imm32S
;
2111 case LONG_MNEM_SUFFIX
:
2114 case WORD_MNEM_SUFFIX
:
2117 case BYTE_MNEM_SUFFIX
:
2125 i
.types
[op
] &= mask
;
2132 /* Try to use the smallest displacement type too. */
2138 for (op
= i
.operands
; --op
>= 0;)
2139 if (i
.types
[op
] & Disp
)
2141 if (i
.op
[op
].disps
->X_op
== O_constant
)
2143 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2145 if ((i
.types
[op
] & Disp16
)
2146 && (disp
& ~(offsetT
) 0xffff) == 0)
2148 /* If this operand is at most 16 bits, convert
2149 to a signed 16 bit number and don't use 64bit
2151 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2152 i
.types
[op
] &= ~Disp64
;
2154 if ((i
.types
[op
] & Disp32
)
2155 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2157 /* If this operand is at most 32 bits, convert
2158 to a signed 32 bit number and don't use 64bit
2160 disp
&= (((offsetT
) 2 << 31) - 1);
2161 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2162 i
.types
[op
] &= ~Disp64
;
2164 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2166 i
.types
[op
] &= ~Disp
;
2170 else if (flag_code
== CODE_64BIT
)
2172 if (fits_in_signed_long (disp
))
2174 i
.types
[op
] &= ~Disp64
;
2175 i
.types
[op
] |= Disp32S
;
2177 if (fits_in_unsigned_long (disp
))
2178 i
.types
[op
] |= Disp32
;
2180 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2181 && fits_in_signed_byte (disp
))
2182 i
.types
[op
] |= Disp8
;
2185 /* We only support 64bit displacement on constants. */
2186 i
.types
[op
] &= ~Disp64
;
2193 /* Points to template once we've found it. */
2195 unsigned int overlap0
, overlap1
, overlap2
;
2196 unsigned int found_reverse_match
;
2199 #define MATCH(overlap, given, template) \
2200 ((overlap & ~JumpAbsolute) \
2201 && (((given) & (BaseIndex | JumpAbsolute)) \
2202 == ((overlap) & (BaseIndex | JumpAbsolute))))
2204 /* If given types r0 and r1 are registers they must be of the same type
2205 unless the expected operand type register overlap is null.
2206 Note that Acc in a template matches every size of reg. */
2207 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2208 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2209 || ((g0) & Reg) == ((g1) & Reg) \
2210 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2215 found_reverse_match
= 0;
2216 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2218 : (i
.suffix
== WORD_MNEM_SUFFIX
2220 : (i
.suffix
== SHORT_MNEM_SUFFIX
2222 : (i
.suffix
== LONG_MNEM_SUFFIX
2224 : (i
.suffix
== QWORD_MNEM_SUFFIX
2226 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2227 ? No_xSuf
: 0))))));
2229 t
= current_templates
->start
;
2230 if (i
.suffix
== QWORD_MNEM_SUFFIX
2231 && flag_code
!= CODE_64BIT
2233 ? !(t
->opcode_modifier
& IgnoreSize
)
2234 && !intel_float_operand (t
->name
)
2235 : intel_float_operand (t
->name
) != 2)
2236 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2237 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2238 && (t
->base_opcode
!= 0x0fc7
2239 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2240 t
= current_templates
->end
;
2241 for (; t
< current_templates
->end
; t
++)
2243 /* Must have right number of operands. */
2244 if (i
.operands
!= t
->operands
)
2247 /* Check the suffix, except for some instructions in intel mode. */
2248 if ((t
->opcode_modifier
& suffix_check
)
2250 && (t
->opcode_modifier
& IgnoreSize
)))
2253 /* Do not verify operands when there are none. */
2254 else if (!t
->operands
)
2256 if (t
->cpu_flags
& ~cpu_arch_flags
)
2258 /* We've found a match; break out of loop. */
2262 overlap0
= i
.types
[0] & t
->operand_types
[0];
2263 switch (t
->operands
)
2266 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2271 overlap1
= i
.types
[1] & t
->operand_types
[1];
2272 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2273 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2274 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2275 t
->operand_types
[0],
2276 overlap1
, i
.types
[1],
2277 t
->operand_types
[1]))
2279 /* Check if other direction is valid ... */
2280 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2283 /* Try reversing direction of operands. */
2284 overlap0
= i
.types
[0] & t
->operand_types
[1];
2285 overlap1
= i
.types
[1] & t
->operand_types
[0];
2286 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2287 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2288 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2289 t
->operand_types
[1],
2290 overlap1
, i
.types
[1],
2291 t
->operand_types
[0]))
2293 /* Does not match either direction. */
2296 /* found_reverse_match holds which of D or FloatDR
2298 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2300 /* Found a forward 2 operand match here. */
2301 else if (t
->operands
== 3)
2303 /* Here we make use of the fact that there are no
2304 reverse match 3 operand instructions, and all 3
2305 operand instructions only need to be checked for
2306 register consistency between operands 2 and 3. */
2307 overlap2
= i
.types
[2] & t
->operand_types
[2];
2308 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2309 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2310 t
->operand_types
[1],
2311 overlap2
, i
.types
[2],
2312 t
->operand_types
[2]))
2316 /* Found either forward/reverse 2 or 3 operand match here:
2317 slip through to break. */
2319 if (t
->cpu_flags
& ~cpu_arch_flags
)
2321 found_reverse_match
= 0;
2324 /* We've found a match; break out of loop. */
2328 if (t
== current_templates
->end
)
2330 /* We found no match. */
2331 as_bad (_("suffix or operands invalid for `%s'"),
2332 current_templates
->start
->name
);
2336 if (!quiet_warnings
)
2339 && ((i
.types
[0] & JumpAbsolute
)
2340 != (t
->operand_types
[0] & JumpAbsolute
)))
2342 as_warn (_("indirect %s without `*'"), t
->name
);
2345 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2346 == (IsPrefix
| IgnoreSize
))
2348 /* Warn them that a data or address size prefix doesn't
2349 affect assembly of the next line of code. */
2350 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2354 /* Copy the template we found. */
2356 if (found_reverse_match
)
2358 /* If we found a reverse match we must alter the opcode
2359 direction bit. found_reverse_match holds bits to change
2360 (different for int & float insns). */
2362 i
.tm
.base_opcode
^= found_reverse_match
;
2364 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2365 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2374 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2375 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2377 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2379 as_bad (_("`%s' operand %d must use `%%es' segment"),
2384 /* There's only ever one segment override allowed per instruction.
2385 This instruction possibly has a legal segment override on the
2386 second operand, so copy the segment to where non-string
2387 instructions store it, allowing common code. */
2388 i
.seg
[0] = i
.seg
[1];
2390 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2392 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2394 as_bad (_("`%s' operand %d must use `%%es' segment"),
2404 process_suffix (void)
2406 /* If matched instruction specifies an explicit instruction mnemonic
2408 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2410 if (i
.tm
.opcode_modifier
& Size16
)
2411 i
.suffix
= WORD_MNEM_SUFFIX
;
2412 else if (i
.tm
.opcode_modifier
& Size64
)
2413 i
.suffix
= QWORD_MNEM_SUFFIX
;
2415 i
.suffix
= LONG_MNEM_SUFFIX
;
2417 else if (i
.reg_operands
)
2419 /* If there's no instruction mnemonic suffix we try to invent one
2420 based on register operands. */
2423 /* We take i.suffix from the last register operand specified,
2424 Destination register type is more significant than source
2428 for (op
= i
.operands
; --op
>= 0;)
2429 if ((i
.types
[op
] & Reg
)
2430 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2432 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2433 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2434 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2439 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2441 if (!check_byte_reg ())
2444 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2446 if (!check_long_reg ())
2449 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2451 if (!check_qword_reg ())
2454 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2456 if (!check_word_reg ())
2459 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2460 /* Do nothing if the instruction is going to ignore the prefix. */
2465 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2467 /* exclude fldenv/frstor/fsave/fstenv */
2468 && (i
.tm
.opcode_modifier
& No_sSuf
))
2470 i
.suffix
= stackop_size
;
2472 else if (intel_syntax
2474 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2475 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2476 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2477 && i
.tm
.extension_opcode
<= 3)))
2482 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2484 i
.suffix
= QWORD_MNEM_SUFFIX
;
2488 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2489 i
.suffix
= LONG_MNEM_SUFFIX
;
2492 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2493 i
.suffix
= WORD_MNEM_SUFFIX
;
2502 if (i
.tm
.opcode_modifier
& W
)
2504 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2510 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2518 if ((i
.tm
.opcode_modifier
& W
)
2519 || ((suffixes
& (suffixes
- 1))
2520 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2522 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2528 /* Change the opcode based on the operand size given by i.suffix;
2529 We don't need to change things for byte insns. */
2531 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2533 /* It's not a byte, select word/dword operation. */
2534 if (i
.tm
.opcode_modifier
& W
)
2536 if (i
.tm
.opcode_modifier
& ShortForm
)
2537 i
.tm
.base_opcode
|= 8;
2539 i
.tm
.base_opcode
|= 1;
2542 /* Now select between word & dword operations via the operand
2543 size prefix, except for instructions that will ignore this
2545 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2546 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2547 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2548 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2549 || (flag_code
== CODE_64BIT
2550 && (i
.tm
.opcode_modifier
& JumpByte
))))
2552 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2554 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2555 prefix
= ADDR_PREFIX_OPCODE
;
2557 if (!add_prefix (prefix
))
2561 /* Set mode64 for an operand. */
2562 if (i
.suffix
== QWORD_MNEM_SUFFIX
2563 && flag_code
== CODE_64BIT
2564 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2565 i
.rex
|= REX_MODE64
;
2567 /* Size floating point instruction. */
2568 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2569 if (i
.tm
.opcode_modifier
& FloatMF
)
2570 i
.tm
.base_opcode
^= 4;
2577 check_byte_reg (void)
2581 for (op
= i
.operands
; --op
>= 0;)
2583 /* If this is an eight bit register, it's OK. If it's the 16 or
2584 32 bit version of an eight bit register, we will just use the
2585 low portion, and that's OK too. */
2586 if (i
.types
[op
] & Reg8
)
2589 /* movzx and movsx should not generate this warning. */
2591 && (i
.tm
.base_opcode
== 0xfb7
2592 || i
.tm
.base_opcode
== 0xfb6
2593 || i
.tm
.base_opcode
== 0x63
2594 || i
.tm
.base_opcode
== 0xfbe
2595 || i
.tm
.base_opcode
== 0xfbf))
2598 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2600 /* Prohibit these changes in the 64bit mode, since the
2601 lowering is more complicated. */
2602 if (flag_code
== CODE_64BIT
2603 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2605 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2606 i
.op
[op
].regs
->reg_name
,
2610 #if REGISTER_WARNINGS
2612 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2613 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2614 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2615 ? REGNAM_AL
- REGNAM_AX
2616 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2617 i
.op
[op
].regs
->reg_name
,
2622 /* Any other register is bad. */
2623 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2625 | Control
| Debug
| Test
2626 | FloatReg
| FloatAcc
))
2628 as_bad (_("`%%%s' not allowed with `%s%c'"),
2629 i
.op
[op
].regs
->reg_name
,
2643 for (op
= i
.operands
; --op
>= 0;)
2644 /* Reject eight bit registers, except where the template requires
2645 them. (eg. movzb) */
2646 if ((i
.types
[op
] & Reg8
) != 0
2647 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2649 as_bad (_("`%%%s' not allowed with `%s%c'"),
2650 i
.op
[op
].regs
->reg_name
,
2655 /* Warn if the e prefix on a general reg is missing. */
2656 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2657 && (i
.types
[op
] & Reg16
) != 0
2658 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2660 /* Prohibit these changes in the 64bit mode, since the
2661 lowering is more complicated. */
2662 if (flag_code
== CODE_64BIT
)
2664 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2665 i
.op
[op
].regs
->reg_name
,
2669 #if REGISTER_WARNINGS
2671 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2672 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2673 i
.op
[op
].regs
->reg_name
,
2677 /* Warn if the r prefix on a general reg is missing. */
2678 else if ((i
.types
[op
] & Reg64
) != 0
2679 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2681 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2682 i
.op
[op
].regs
->reg_name
,
2694 for (op
= i
.operands
; --op
>= 0; )
2695 /* Reject eight bit registers, except where the template requires
2696 them. (eg. movzb) */
2697 if ((i
.types
[op
] & Reg8
) != 0
2698 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2700 as_bad (_("`%%%s' not allowed with `%s%c'"),
2701 i
.op
[op
].regs
->reg_name
,
2706 /* Warn if the e prefix on a general reg is missing. */
2707 else if (((i
.types
[op
] & Reg16
) != 0
2708 || (i
.types
[op
] & Reg32
) != 0)
2709 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2711 /* Prohibit these changes in the 64bit mode, since the
2712 lowering is more complicated. */
2713 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2714 i
.op
[op
].regs
->reg_name
,
2725 for (op
= i
.operands
; --op
>= 0;)
2726 /* Reject eight bit registers, except where the template requires
2727 them. (eg. movzb) */
2728 if ((i
.types
[op
] & Reg8
) != 0
2729 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2731 as_bad (_("`%%%s' not allowed with `%s%c'"),
2732 i
.op
[op
].regs
->reg_name
,
2737 /* Warn if the e prefix on a general reg is present. */
2738 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2739 && (i
.types
[op
] & Reg32
) != 0
2740 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2742 /* Prohibit these changes in the 64bit mode, since the
2743 lowering is more complicated. */
2744 if (flag_code
== CODE_64BIT
)
2746 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2747 i
.op
[op
].regs
->reg_name
,
2752 #if REGISTER_WARNINGS
2753 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2754 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2755 i
.op
[op
].regs
->reg_name
,
2765 unsigned int overlap0
, overlap1
, overlap2
;
2767 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2768 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2769 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2770 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2771 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2775 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2777 : (i
.suffix
== WORD_MNEM_SUFFIX
2779 : (i
.suffix
== QWORD_MNEM_SUFFIX
2783 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2784 || overlap0
== (Imm16
| Imm32
)
2785 || overlap0
== (Imm16
| Imm32S
))
2787 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2790 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2791 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2792 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2794 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2798 i
.types
[0] = overlap0
;
2800 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2801 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2802 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2803 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2804 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2808 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2810 : (i
.suffix
== WORD_MNEM_SUFFIX
2812 : (i
.suffix
== QWORD_MNEM_SUFFIX
2816 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2817 || overlap1
== (Imm16
| Imm32
)
2818 || overlap1
== (Imm16
| Imm32S
))
2820 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2823 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2824 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2825 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2827 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2831 i
.types
[1] = overlap1
;
2833 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2834 assert ((overlap2
& Imm
) == 0);
2835 i
.types
[2] = overlap2
;
2843 /* Default segment register this instruction will use for memory
2844 accesses. 0 means unknown. This is only for optimizing out
2845 unnecessary segment overrides. */
2846 const seg_entry
*default_seg
= 0;
2848 /* The imul $imm, %reg instruction is converted into
2849 imul $imm, %reg, %reg, and the clr %reg instruction
2850 is converted into xor %reg, %reg. */
2851 if (i
.tm
.opcode_modifier
& regKludge
)
2853 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2854 /* Pretend we saw the extra register operand. */
2855 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2856 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2857 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2861 if (i
.tm
.opcode_modifier
& ShortForm
)
2863 /* The register or float register operand is in operand 0 or 1. */
2864 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2865 /* Register goes in low 3 bits of opcode. */
2866 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2867 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2869 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2871 /* Warn about some common errors, but press on regardless.
2872 The first case can be generated by gcc (<= 2.8.1). */
2873 if (i
.operands
== 2)
2875 /* Reversed arguments on faddp, fsubp, etc. */
2876 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2877 i
.op
[1].regs
->reg_name
,
2878 i
.op
[0].regs
->reg_name
);
2882 /* Extraneous `l' suffix on fp insn. */
2883 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2884 i
.op
[0].regs
->reg_name
);
2888 else if (i
.tm
.opcode_modifier
& Modrm
)
2890 /* The opcode is completed (modulo i.tm.extension_opcode which
2891 must be put into the modrm byte). Now, we make the modrm and
2892 index base bytes based on all the info we've collected. */
2894 default_seg
= build_modrm_byte ();
2896 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2898 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2899 && i
.op
[0].regs
->reg_num
== 1)
2901 as_bad (_("you can't `pop %%cs'"));
2904 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2905 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2908 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2912 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2914 /* For the string instructions that allow a segment override
2915 on one of their operands, the default segment is ds. */
2919 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2920 || (i
.tm
.cpu_flags
& CpuSVME
))
2921 && i
.seg
[0] && !quiet_warnings
)
2922 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2924 /* If a segment was explicitly specified, and the specified segment
2925 is not the default, use an opcode prefix to select it. If we
2926 never figured out what the default segment is, then default_seg
2927 will be zero at this point, and the specified segment prefix will
2929 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2931 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2937 static const seg_entry
*
2940 const seg_entry
*default_seg
= 0;
2942 /* i.reg_operands MUST be the number of real register operands;
2943 implicit registers do not count. */
2944 if (i
.reg_operands
== 2)
2946 unsigned int source
, dest
;
2947 source
= ((i
.types
[0]
2948 & (Reg
| RegMMX
| RegXMM
2950 | Control
| Debug
| Test
))
2955 /* One of the register operands will be encoded in the i.tm.reg
2956 field, the other in the combined i.tm.mode and i.tm.regmem
2957 fields. If no form of this instruction supports a memory
2958 destination operand, then we assume the source operand may
2959 sometimes be a memory operand and so we need to store the
2960 destination in the i.rm.reg field. */
2961 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2963 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2964 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2965 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2967 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2972 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2973 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2974 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2976 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2979 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2981 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2983 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2984 add_prefix (LOCK_PREFIX_OPCODE
);
2988 { /* If it's not 2 reg operands... */
2991 unsigned int fake_zero_displacement
= 0;
2992 unsigned int op
= ((i
.types
[0] & AnyMem
)
2994 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2998 if (i
.base_reg
== 0)
3001 if (!i
.disp_operands
)
3002 fake_zero_displacement
= 1;
3003 if (i
.index_reg
== 0)
3005 /* Operand is just <disp> */
3006 if (flag_code
== CODE_64BIT
)
3008 /* 64bit mode overwrites the 32bit absolute
3009 addressing by RIP relative addressing and
3010 absolute addressing is encoded by one of the
3011 redundant SIB forms. */
3012 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3013 i
.sib
.base
= NO_BASE_REGISTER
;
3014 i
.sib
.index
= NO_INDEX_REGISTER
;
3015 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3017 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3019 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3020 i
.types
[op
] = Disp16
;
3024 i
.rm
.regmem
= NO_BASE_REGISTER
;
3025 i
.types
[op
] = Disp32
;
3028 else /* !i.base_reg && i.index_reg */
3030 i
.sib
.index
= i
.index_reg
->reg_num
;
3031 i
.sib
.base
= NO_BASE_REGISTER
;
3032 i
.sib
.scale
= i
.log2_scale_factor
;
3033 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3034 i
.types
[op
] &= ~Disp
;
3035 if (flag_code
!= CODE_64BIT
)
3036 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3038 i
.types
[op
] |= Disp32S
;
3039 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3043 /* RIP addressing for 64bit mode. */
3044 else if (i
.base_reg
->reg_type
== BaseIndex
)
3046 i
.rm
.regmem
= NO_BASE_REGISTER
;
3047 i
.types
[op
] &= ~ Disp
;
3048 i
.types
[op
] |= Disp32S
;
3049 i
.flags
[op
] = Operand_PCrel
;
3050 if (! i
.disp_operands
)
3051 fake_zero_displacement
= 1;
3053 else if (i
.base_reg
->reg_type
& Reg16
)
3055 switch (i
.base_reg
->reg_num
)
3058 if (i
.index_reg
== 0)
3060 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3061 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3065 if (i
.index_reg
== 0)
3068 if ((i
.types
[op
] & Disp
) == 0)
3070 /* fake (%bp) into 0(%bp) */
3071 i
.types
[op
] |= Disp8
;
3072 fake_zero_displacement
= 1;
3075 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3076 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3078 default: /* (%si) -> 4 or (%di) -> 5 */
3079 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3081 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3083 else /* i.base_reg and 32/64 bit mode */
3085 if (flag_code
== CODE_64BIT
3086 && (i
.types
[op
] & Disp
))
3087 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3089 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3090 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3092 i
.sib
.base
= i
.base_reg
->reg_num
;
3093 /* x86-64 ignores REX prefix bit here to avoid decoder
3095 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3098 if (i
.disp_operands
== 0)
3100 fake_zero_displacement
= 1;
3101 i
.types
[op
] |= Disp8
;
3104 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3108 i
.sib
.scale
= i
.log2_scale_factor
;
3109 if (i
.index_reg
== 0)
3111 /* <disp>(%esp) becomes two byte modrm with no index
3112 register. We've already stored the code for esp
3113 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3114 Any base register besides %esp will not use the
3115 extra modrm byte. */
3116 i
.sib
.index
= NO_INDEX_REGISTER
;
3117 #if !SCALE1_WHEN_NO_INDEX
3118 /* Another case where we force the second modrm byte. */
3119 if (i
.log2_scale_factor
)
3120 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3125 i
.sib
.index
= i
.index_reg
->reg_num
;
3126 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3127 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3130 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3133 if (fake_zero_displacement
)
3135 /* Fakes a zero displacement assuming that i.types[op]
3136 holds the correct displacement size. */
3139 assert (i
.op
[op
].disps
== 0);
3140 exp
= &disp_expressions
[i
.disp_operands
++];
3141 i
.op
[op
].disps
= exp
;
3142 exp
->X_op
= O_constant
;
3143 exp
->X_add_number
= 0;
3144 exp
->X_add_symbol
= (symbolS
*) 0;
3145 exp
->X_op_symbol
= (symbolS
*) 0;
3149 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3150 (if any) based on i.tm.extension_opcode. Again, we must be
3151 careful to make sure that segment/control/debug/test/MMX
3152 registers are coded into the i.rm.reg field. */
3157 & (Reg
| RegMMX
| RegXMM
3159 | Control
| Debug
| Test
))
3162 & (Reg
| RegMMX
| RegXMM
3164 | Control
| Debug
| Test
))
3167 /* If there is an extension opcode to put here, the register
3168 number must be put into the regmem field. */
3169 if (i
.tm
.extension_opcode
!= None
)
3171 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3172 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3177 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3178 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3182 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3183 must set it to 3 to indicate this is a register operand
3184 in the regmem field. */
3185 if (!i
.mem_operands
)
3189 /* Fill in i.rm.reg field with extension opcode (if any). */
3190 if (i
.tm
.extension_opcode
!= None
)
3191 i
.rm
.reg
= i
.tm
.extension_opcode
;
3202 relax_substateT subtype
;
3207 if (flag_code
== CODE_16BIT
)
3211 if (i
.prefix
[DATA_PREFIX
] != 0)
3217 /* Pentium4 branch hints. */
3218 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3219 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3224 if (i
.prefix
[REX_PREFIX
] != 0)
3230 if (i
.prefixes
!= 0 && !intel_syntax
)
3231 as_warn (_("skipping prefixes on this instruction"));
3233 /* It's always a symbol; End frag & setup for relax.
3234 Make sure there is enough room in this frag for the largest
3235 instruction we may generate in md_convert_frag. This is 2
3236 bytes for the opcode and room for the prefix and largest
3238 frag_grow (prefix
+ 2 + 4);
3239 /* Prefix and 1 opcode byte go in fr_fix. */
3240 p
= frag_more (prefix
+ 1);
3241 if (i
.prefix
[DATA_PREFIX
] != 0)
3242 *p
++ = DATA_PREFIX_OPCODE
;
3243 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3244 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3245 *p
++ = i
.prefix
[SEG_PREFIX
];
3246 if (i
.prefix
[REX_PREFIX
] != 0)
3247 *p
++ = i
.prefix
[REX_PREFIX
];
3248 *p
= i
.tm
.base_opcode
;
3250 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3251 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3252 else if ((cpu_arch_flags
& Cpu386
) != 0)
3253 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3255 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3258 sym
= i
.op
[0].disps
->X_add_symbol
;
3259 off
= i
.op
[0].disps
->X_add_number
;
3261 if (i
.op
[0].disps
->X_op
!= O_constant
3262 && i
.op
[0].disps
->X_op
!= O_symbol
)
3264 /* Handle complex expressions. */
3265 sym
= make_expr_symbol (i
.op
[0].disps
);
3269 /* 1 possible extra opcode + 4 byte displacement go in var part.
3270 Pass reloc in fr_var. */
3271 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3281 if (i
.tm
.opcode_modifier
& JumpByte
)
3283 /* This is a loop or jecxz type instruction. */
3285 if (i
.prefix
[ADDR_PREFIX
] != 0)
3287 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3290 /* Pentium4 branch hints. */
3291 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3292 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3294 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3303 if (flag_code
== CODE_16BIT
)
3306 if (i
.prefix
[DATA_PREFIX
] != 0)
3308 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3318 if (i
.prefix
[REX_PREFIX
] != 0)
3320 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3324 if (i
.prefixes
!= 0 && !intel_syntax
)
3325 as_warn (_("skipping prefixes on this instruction"));
3327 p
= frag_more (1 + size
);
3328 *p
++ = i
.tm
.base_opcode
;
3330 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3331 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3333 /* All jumps handled here are signed, but don't use a signed limit
3334 check for 32 and 16 bit jumps as we want to allow wrap around at
3335 4G and 64k respectively. */
3337 fixP
->fx_signed
= 1;
3341 output_interseg_jump ()
3349 if (flag_code
== CODE_16BIT
)
3353 if (i
.prefix
[DATA_PREFIX
] != 0)
3359 if (i
.prefix
[REX_PREFIX
] != 0)
3369 if (i
.prefixes
!= 0 && !intel_syntax
)
3370 as_warn (_("skipping prefixes on this instruction"));
3372 /* 1 opcode; 2 segment; offset */
3373 p
= frag_more (prefix
+ 1 + 2 + size
);
3375 if (i
.prefix
[DATA_PREFIX
] != 0)
3376 *p
++ = DATA_PREFIX_OPCODE
;
3378 if (i
.prefix
[REX_PREFIX
] != 0)
3379 *p
++ = i
.prefix
[REX_PREFIX
];
3381 *p
++ = i
.tm
.base_opcode
;
3382 if (i
.op
[1].imms
->X_op
== O_constant
)
3384 offsetT n
= i
.op
[1].imms
->X_add_number
;
3387 && !fits_in_unsigned_word (n
)
3388 && !fits_in_signed_word (n
))
3390 as_bad (_("16-bit jump out of range"));
3393 md_number_to_chars (p
, n
, size
);
3396 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3397 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3398 if (i
.op
[0].imms
->X_op
!= O_constant
)
3399 as_bad (_("can't handle non absolute segment in `%s'"),
3401 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3407 fragS
*insn_start_frag
;
3408 offsetT insn_start_off
;
3410 /* Tie dwarf2 debug info to the address at the start of the insn.
3411 We can't do this after the insn has been output as the current
3412 frag may have been closed off. eg. by frag_var. */
3413 dwarf2_emit_insn (0);
3415 insn_start_frag
= frag_now
;
3416 insn_start_off
= frag_now_fix ();
3419 if (i
.tm
.opcode_modifier
& Jump
)
3421 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3423 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3424 output_interseg_jump ();
3427 /* Output normal instructions here. */
3431 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3432 more higher byte to specify a prefix the instruction
3434 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3436 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3438 unsigned int prefix
;
3439 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3441 if (prefix
!= REPE_PREFIX_OPCODE
3442 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3443 add_prefix (prefix
);
3446 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3449 /* The prefix bytes. */
3451 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3457 md_number_to_chars (p
, (valueT
) *q
, 1);
3461 /* Now the opcode; be careful about word order here! */
3462 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3464 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3470 /* Put out high byte first: can't use md_number_to_chars! */
3471 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3472 *p
= i
.tm
.base_opcode
& 0xff;
3475 /* Now the modrm byte and sib byte (if present). */
3476 if (i
.tm
.opcode_modifier
& Modrm
)
3479 md_number_to_chars (p
,
3480 (valueT
) (i
.rm
.regmem
<< 0
3484 /* If i.rm.regmem == ESP (4)
3485 && i.rm.mode != (Register mode)
3487 ==> need second modrm byte. */
3488 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3490 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3493 md_number_to_chars (p
,
3494 (valueT
) (i
.sib
.base
<< 0
3496 | i
.sib
.scale
<< 6),
3501 if (i
.disp_operands
)
3502 output_disp (insn_start_frag
, insn_start_off
);
3505 output_imm (insn_start_frag
, insn_start_off
);
3513 #endif /* DEBUG386 */
3517 output_disp (insn_start_frag
, insn_start_off
)
3518 fragS
*insn_start_frag
;
3519 offsetT insn_start_off
;
3524 for (n
= 0; n
< i
.operands
; n
++)
3526 if (i
.types
[n
] & Disp
)
3528 if (i
.op
[n
].disps
->X_op
== O_constant
)
3534 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3537 if (i
.types
[n
] & Disp8
)
3539 if (i
.types
[n
] & Disp64
)
3542 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3544 p
= frag_more (size
);
3545 md_number_to_chars (p
, val
, size
);
3549 enum bfd_reloc_code_real reloc_type
;
3552 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3554 /* The PC relative address is computed relative
3555 to the instruction boundary, so in case immediate
3556 fields follows, we need to adjust the value. */
3557 if (pcrel
&& i
.imm_operands
)
3562 for (n1
= 0; n1
< i
.operands
; n1
++)
3563 if (i
.types
[n1
] & Imm
)
3565 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3568 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3570 if (i
.types
[n1
] & Imm64
)
3575 /* We should find the immediate. */
3576 if (n1
== i
.operands
)
3578 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3581 if (i
.types
[n
] & Disp32S
)
3584 if (i
.types
[n
] & (Disp16
| Disp64
))
3587 if (i
.types
[n
] & Disp64
)
3591 p
= frag_more (size
);
3592 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3594 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3595 && (((reloc_type
== BFD_RELOC_32
3596 || reloc_type
== BFD_RELOC_X86_64_32S
)
3597 && (i
.op
[n
].disps
->X_op
== O_symbol
3598 || (i
.op
[n
].disps
->X_op
== O_add
3599 && ((symbol_get_value_expression
3600 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3602 || reloc_type
== BFD_RELOC_32_PCREL
))
3606 if (insn_start_frag
== frag_now
)
3607 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3612 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3613 for (fr
= insn_start_frag
->fr_next
;
3614 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3616 add
+= p
- frag_now
->fr_literal
;
3620 reloc_type
= BFD_RELOC_386_GOTPC
;
3622 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3623 i
.op
[n
].disps
->X_add_number
+= add
;
3625 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3626 i
.op
[n
].disps
, pcrel
, reloc_type
);
3633 output_imm (insn_start_frag
, insn_start_off
)
3634 fragS
*insn_start_frag
;
3635 offsetT insn_start_off
;
3640 for (n
= 0; n
< i
.operands
; n
++)
3642 if (i
.types
[n
] & Imm
)
3644 if (i
.op
[n
].imms
->X_op
== O_constant
)
3650 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3653 if (i
.types
[n
] & (Imm8
| Imm8S
))
3655 else if (i
.types
[n
] & Imm64
)
3658 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3660 p
= frag_more (size
);
3661 md_number_to_chars (p
, val
, size
);
3665 /* Not absolute_section.
3666 Need a 32-bit fixup (don't support 8bit
3667 non-absolute imms). Try to support other
3669 enum bfd_reloc_code_real reloc_type
;
3673 if ((i
.types
[n
] & (Imm32S
))
3674 && (i
.suffix
== QWORD_MNEM_SUFFIX
3675 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3677 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3680 if (i
.types
[n
] & (Imm8
| Imm8S
))
3682 if (i
.types
[n
] & Imm64
)
3686 p
= frag_more (size
);
3687 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3689 /* This is tough to explain. We end up with this one if we
3690 * have operands that look like
3691 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3692 * obtain the absolute address of the GOT, and it is strongly
3693 * preferable from a performance point of view to avoid using
3694 * a runtime relocation for this. The actual sequence of
3695 * instructions often look something like:
3700 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3702 * The call and pop essentially return the absolute address
3703 * of the label .L66 and store it in %ebx. The linker itself
3704 * will ultimately change the first operand of the addl so
3705 * that %ebx points to the GOT, but to keep things simple, the
3706 * .o file must have this operand set so that it generates not
3707 * the absolute address of .L66, but the absolute address of
3708 * itself. This allows the linker itself simply treat a GOTPC
3709 * relocation as asking for a pcrel offset to the GOT to be
3710 * added in, and the addend of the relocation is stored in the
3711 * operand field for the instruction itself.
3713 * Our job here is to fix the operand so that it would add
3714 * the correct offset so that %ebx would point to itself. The
3715 * thing that is tricky is that .-.L66 will point to the
3716 * beginning of the instruction, so we need to further modify
3717 * the operand so that it will point to itself. There are
3718 * other cases where you have something like:
3720 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3722 * and here no correction would be required. Internally in
3723 * the assembler we treat operands of this form as not being
3724 * pcrel since the '.' is explicitly mentioned, and I wonder
3725 * whether it would simplify matters to do it this way. Who
3726 * knows. In earlier versions of the PIC patches, the
3727 * pcrel_adjust field was used to store the correction, but
3728 * since the expression is not pcrel, I felt it would be
3729 * confusing to do it this way. */
3731 if ((reloc_type
== BFD_RELOC_32
3732 || reloc_type
== BFD_RELOC_X86_64_32S
)
3734 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3735 && (i
.op
[n
].imms
->X_op
== O_symbol
3736 || (i
.op
[n
].imms
->X_op
== O_add
3737 && ((symbol_get_value_expression
3738 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3743 if (insn_start_frag
== frag_now
)
3744 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3749 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3750 for (fr
= insn_start_frag
->fr_next
;
3751 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3753 add
+= p
- frag_now
->fr_literal
;
3757 reloc_type
= BFD_RELOC_386_GOTPC
;
3759 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3760 i
.op
[n
].imms
->X_add_number
+= add
;
3762 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3763 i
.op
[n
].imms
, 0, reloc_type
);
3769 /* x86_cons_fix_new is called via the expression parsing code when a
3770 reloc is needed. We use this hook to get the correct .got reloc. */
3771 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3772 static int cons_sign
= -1;
3775 x86_cons_fix_new (fragS
*frag
,
3780 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
3782 got_reloc
= NO_RELOC
;
3785 if (exp
->X_op
== O_secrel
)
3787 exp
->X_op
= O_symbol
;
3788 r
= BFD_RELOC_32_SECREL
;
3792 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3795 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3796 # define lex_got(reloc, adjust, types) NULL
3798 /* Parse operands of the form
3799 <symbol>@GOTOFF+<nnn>
3800 and similar .plt or .got references.
3802 If we find one, set up the correct relocation in RELOC and copy the
3803 input string, minus the `@GOTOFF' into a malloc'd buffer for
3804 parsing by the calling routine. Return this buffer, and if ADJUST
3805 is non-null set it to the length of the string we removed from the
3806 input line. Otherwise return NULL. */
3808 lex_got (enum bfd_reloc_code_real
*reloc
,
3810 unsigned int *types
)
3812 static const struct {
3814 const enum bfd_reloc_code_real rel
[2];
3815 const unsigned int types64
;
3817 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3818 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3819 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3820 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3821 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
3822 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3823 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3824 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3825 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
3826 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3827 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
3828 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
3829 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
}
3837 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3838 if (is_end_of_line
[(unsigned char) *cp
])
3841 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3845 len
= strlen (gotrel
[j
].str
);
3846 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3848 if (gotrel
[j
].rel
[object_64bit
] != 0)
3851 char *tmpbuf
, *past_reloc
;
3853 *reloc
= gotrel
[j
].rel
[object_64bit
];
3859 if (flag_code
!= CODE_64BIT
)
3860 *types
= Imm32
|Disp32
;
3862 *types
= gotrel
[j
].types64
;
3865 if (GOT_symbol
== NULL
)
3866 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3868 /* Replace the relocation token with ' ', so that
3869 errors like foo@GOTOFF1 will be detected. */
3871 /* The length of the first part of our input line. */
3872 first
= cp
- input_line_pointer
;
3874 /* The second part goes from after the reloc token until
3875 (and including) an end_of_line char. Don't use strlen
3876 here as the end_of_line char may not be a NUL. */
3877 past_reloc
= cp
+ 1 + len
;
3878 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3880 second
= cp
- past_reloc
;
3882 /* Allocate and copy string. The trailing NUL shouldn't
3883 be necessary, but be safe. */
3884 tmpbuf
= xmalloc (first
+ second
+ 2);
3885 memcpy (tmpbuf
, input_line_pointer
, first
);
3886 tmpbuf
[first
] = ' ';
3887 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3888 tmpbuf
[first
+ second
+ 1] = '\0';
3892 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3893 gotrel
[j
].str
, 1 << (5 + object_64bit
));
3898 /* Might be a symbol version string. Don't as_bad here. */
3903 x86_cons (exp
, size
)
3907 if (size
== 4 || (object_64bit
&& size
== 8))
3909 /* Handle @GOTOFF and the like in an expression. */
3911 char *gotfree_input_line
;
3914 save
= input_line_pointer
;
3915 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
3916 if (gotfree_input_line
)
3917 input_line_pointer
= gotfree_input_line
;
3921 if (gotfree_input_line
)
3923 /* expression () has merrily parsed up to the end of line,
3924 or a comma - in the wrong buffer. Transfer how far
3925 input_line_pointer has moved to the right buffer. */
3926 input_line_pointer
= (save
3927 + (input_line_pointer
- gotfree_input_line
)
3929 free (gotfree_input_line
);
3937 static void signed_cons (int size
)
3939 if (flag_code
== CODE_64BIT
)
3947 pe_directive_secrel (dummy
)
3948 int dummy ATTRIBUTE_UNUSED
;
3955 if (exp
.X_op
== O_symbol
)
3956 exp
.X_op
= O_secrel
;
3958 emit_expr (&exp
, 4);
3960 while (*input_line_pointer
++ == ',');
3962 input_line_pointer
--;
3963 demand_empty_rest_of_line ();
3967 static int i386_immediate
PARAMS ((char *));
3970 i386_immediate (imm_start
)
3973 char *save_input_line_pointer
;
3974 char *gotfree_input_line
;
3977 unsigned int types
= ~0U;
3979 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3981 as_bad (_("only 1 or 2 immediate operands are allowed"));
3985 exp
= &im_expressions
[i
.imm_operands
++];
3986 i
.op
[this_operand
].imms
= exp
;
3988 if (is_space_char (*imm_start
))
3991 save_input_line_pointer
= input_line_pointer
;
3992 input_line_pointer
= imm_start
;
3994 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
3995 if (gotfree_input_line
)
3996 input_line_pointer
= gotfree_input_line
;
3998 exp_seg
= expression (exp
);
4001 if (*input_line_pointer
)
4002 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4004 input_line_pointer
= save_input_line_pointer
;
4005 if (gotfree_input_line
)
4006 free (gotfree_input_line
);
4008 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4010 /* Missing or bad expr becomes absolute 0. */
4011 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4013 exp
->X_op
= O_constant
;
4014 exp
->X_add_number
= 0;
4015 exp
->X_add_symbol
= (symbolS
*) 0;
4016 exp
->X_op_symbol
= (symbolS
*) 0;
4018 else if (exp
->X_op
== O_constant
)
4020 /* Size it properly later. */
4021 i
.types
[this_operand
] |= Imm64
;
4022 /* If BFD64, sign extend val. */
4023 if (!use_rela_relocations
)
4024 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4025 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4027 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4028 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4029 && exp_seg
!= absolute_section
4030 && exp_seg
!= text_section
4031 && exp_seg
!= data_section
4032 && exp_seg
!= bss_section
4033 && exp_seg
!= undefined_section
4034 && !bfd_is_com_section (exp_seg
))
4036 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4042 /* This is an address. The size of the address will be
4043 determined later, depending on destination register,
4044 suffix, or the default for the section. */
4045 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4046 i
.types
[this_operand
] &= types
;
4052 static char *i386_scale
PARAMS ((char *));
4059 char *save
= input_line_pointer
;
4061 input_line_pointer
= scale
;
4062 val
= get_absolute_expression ();
4067 i
.log2_scale_factor
= 0;
4070 i
.log2_scale_factor
= 1;
4073 i
.log2_scale_factor
= 2;
4076 i
.log2_scale_factor
= 3;
4080 char sep
= *input_line_pointer
;
4082 *input_line_pointer
= '\0';
4083 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4085 *input_line_pointer
= sep
;
4086 input_line_pointer
= save
;
4090 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4092 as_warn (_("scale factor of %d without an index register"),
4093 1 << i
.log2_scale_factor
);
4094 #if SCALE1_WHEN_NO_INDEX
4095 i
.log2_scale_factor
= 0;
4098 scale
= input_line_pointer
;
4099 input_line_pointer
= save
;
4103 static int i386_displacement
PARAMS ((char *, char *));
4106 i386_displacement (disp_start
, disp_end
)
4112 char *save_input_line_pointer
;
4113 char *gotfree_input_line
;
4114 int bigdisp
= Disp32
;
4115 unsigned int types
= Disp
;
4117 if (flag_code
== CODE_64BIT
)
4119 if (i
.prefix
[ADDR_PREFIX
] == 0)
4120 bigdisp
= Disp64
| Disp32S
| Disp32
;
4122 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4124 i
.types
[this_operand
] |= bigdisp
;
4126 exp
= &disp_expressions
[i
.disp_operands
];
4127 i
.op
[this_operand
].disps
= exp
;
4129 save_input_line_pointer
= input_line_pointer
;
4130 input_line_pointer
= disp_start
;
4131 END_STRING_AND_SAVE (disp_end
);
4133 #ifndef GCC_ASM_O_HACK
4134 #define GCC_ASM_O_HACK 0
4137 END_STRING_AND_SAVE (disp_end
+ 1);
4138 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4139 && displacement_string_end
[-1] == '+')
4141 /* This hack is to avoid a warning when using the "o"
4142 constraint within gcc asm statements.
4145 #define _set_tssldt_desc(n,addr,limit,type) \
4146 __asm__ __volatile__ ( \
4148 "movw %w1,2+%0\n\t" \
4150 "movb %b1,4+%0\n\t" \
4151 "movb %4,5+%0\n\t" \
4152 "movb $0,6+%0\n\t" \
4153 "movb %h1,7+%0\n\t" \
4155 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4157 This works great except that the output assembler ends
4158 up looking a bit weird if it turns out that there is
4159 no offset. You end up producing code that looks like:
4172 So here we provide the missing zero. */
4174 *displacement_string_end
= '0';
4177 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4178 if (gotfree_input_line
)
4179 input_line_pointer
= gotfree_input_line
;
4181 exp_seg
= expression (exp
);
4184 if (*input_line_pointer
)
4185 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4187 RESTORE_END_STRING (disp_end
+ 1);
4189 RESTORE_END_STRING (disp_end
);
4190 input_line_pointer
= save_input_line_pointer
;
4191 if (gotfree_input_line
)
4192 free (gotfree_input_line
);
4194 /* We do this to make sure that the section symbol is in
4195 the symbol table. We will ultimately change the relocation
4196 to be relative to the beginning of the section. */
4197 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4198 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4199 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4201 if (exp
->X_op
!= O_symbol
)
4203 as_bad (_("bad expression used with @%s"),
4204 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4210 if (S_IS_LOCAL (exp
->X_add_symbol
)
4211 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4212 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4213 exp
->X_op
= O_subtract
;
4214 exp
->X_op_symbol
= GOT_symbol
;
4215 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4216 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4217 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4218 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4220 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4223 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4225 /* Missing or bad expr becomes absolute 0. */
4226 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4228 exp
->X_op
= O_constant
;
4229 exp
->X_add_number
= 0;
4230 exp
->X_add_symbol
= (symbolS
*) 0;
4231 exp
->X_op_symbol
= (symbolS
*) 0;
4234 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4235 if (exp
->X_op
!= O_constant
4236 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4237 && exp_seg
!= absolute_section
4238 && exp_seg
!= text_section
4239 && exp_seg
!= data_section
4240 && exp_seg
!= bss_section
4241 && exp_seg
!= undefined_section
4242 && !bfd_is_com_section (exp_seg
))
4244 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4249 if (!(i
.types
[this_operand
] & ~Disp
))
4250 i
.types
[this_operand
] &= types
;
4255 static int i386_index_check
PARAMS ((const char *));
4257 /* Make sure the memory operand we've been dealt is valid.
4258 Return 1 on success, 0 on a failure. */
4261 i386_index_check (operand_string
)
4262 const char *operand_string
;
4265 #if INFER_ADDR_PREFIX
4271 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4272 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4274 /* Memory operands of SVME insns are special in that they only allow
4275 rAX as their memory address and ignore any segment override. */
4278 /* SKINIT is even more restrictive: it always requires EAX. */
4279 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4281 else if (flag_code
== CODE_64BIT
)
4282 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4284 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4288 || !(i
.base_reg
->reg_type
& Acc
)
4289 || !(i
.base_reg
->reg_type
& RegXX
)
4291 || (i
.types
[0] & Disp
))
4294 else if (flag_code
== CODE_64BIT
)
4296 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4299 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4300 && (i
.base_reg
->reg_type
!= BaseIndex
4303 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4304 != (RegXX
| BaseIndex
))))
4309 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4313 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4314 != (Reg16
| BaseIndex
)))
4316 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4317 != (Reg16
| BaseIndex
))
4319 && i
.base_reg
->reg_num
< 6
4320 && i
.index_reg
->reg_num
>= 6
4321 && i
.log2_scale_factor
== 0))))
4328 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4330 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4331 != (Reg32
| BaseIndex
))))
4337 #if INFER_ADDR_PREFIX
4338 if (i
.prefix
[ADDR_PREFIX
] == 0)
4340 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4342 /* Change the size of any displacement too. At most one of
4343 Disp16 or Disp32 is set.
4344 FIXME. There doesn't seem to be any real need for separate
4345 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4346 Removing them would probably clean up the code quite a lot. */
4347 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4348 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4353 as_bad (_("`%s' is not a valid base/index expression"),
4357 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4359 flag_code_names
[flag_code
]);
4364 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4368 i386_operand (operand_string
)
4369 char *operand_string
;
4373 char *op_string
= operand_string
;
4375 if (is_space_char (*op_string
))
4378 /* We check for an absolute prefix (differentiating,
4379 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4380 if (*op_string
== ABSOLUTE_PREFIX
)
4383 if (is_space_char (*op_string
))
4385 i
.types
[this_operand
] |= JumpAbsolute
;
4388 /* Check if operand is a register. */
4389 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4390 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4392 /* Check for a segment override by searching for ':' after a
4393 segment register. */
4395 if (is_space_char (*op_string
))
4397 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4402 i
.seg
[i
.mem_operands
] = &es
;
4405 i
.seg
[i
.mem_operands
] = &cs
;
4408 i
.seg
[i
.mem_operands
] = &ss
;
4411 i
.seg
[i
.mem_operands
] = &ds
;
4414 i
.seg
[i
.mem_operands
] = &fs
;
4417 i
.seg
[i
.mem_operands
] = &gs
;
4421 /* Skip the ':' and whitespace. */
4423 if (is_space_char (*op_string
))
4426 if (!is_digit_char (*op_string
)
4427 && !is_identifier_char (*op_string
)
4428 && *op_string
!= '('
4429 && *op_string
!= ABSOLUTE_PREFIX
)
4431 as_bad (_("bad memory operand `%s'"), op_string
);
4434 /* Handle case of %es:*foo. */
4435 if (*op_string
== ABSOLUTE_PREFIX
)
4438 if (is_space_char (*op_string
))
4440 i
.types
[this_operand
] |= JumpAbsolute
;
4442 goto do_memory_reference
;
4446 as_bad (_("junk `%s' after register"), op_string
);
4449 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4450 i
.op
[this_operand
].regs
= r
;
4453 else if (*op_string
== REGISTER_PREFIX
)
4455 as_bad (_("bad register name `%s'"), op_string
);
4458 else if (*op_string
== IMMEDIATE_PREFIX
)
4461 if (i
.types
[this_operand
] & JumpAbsolute
)
4463 as_bad (_("immediate operand illegal with absolute jump"));
4466 if (!i386_immediate (op_string
))
4469 else if (is_digit_char (*op_string
)
4470 || is_identifier_char (*op_string
)
4471 || *op_string
== '(')
4473 /* This is a memory reference of some sort. */
4476 /* Start and end of displacement string expression (if found). */
4477 char *displacement_string_start
;
4478 char *displacement_string_end
;
4480 do_memory_reference
:
4481 if ((i
.mem_operands
== 1
4482 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4483 || i
.mem_operands
== 2)
4485 as_bad (_("too many memory references for `%s'"),
4486 current_templates
->start
->name
);
4490 /* Check for base index form. We detect the base index form by
4491 looking for an ')' at the end of the operand, searching
4492 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4494 base_string
= op_string
+ strlen (op_string
);
4497 if (is_space_char (*base_string
))
4500 /* If we only have a displacement, set-up for it to be parsed later. */
4501 displacement_string_start
= op_string
;
4502 displacement_string_end
= base_string
+ 1;
4504 if (*base_string
== ')')
4507 unsigned int parens_balanced
= 1;
4508 /* We've already checked that the number of left & right ()'s are
4509 equal, so this loop will not be infinite. */
4513 if (*base_string
== ')')
4515 if (*base_string
== '(')
4518 while (parens_balanced
);
4520 temp_string
= base_string
;
4522 /* Skip past '(' and whitespace. */
4524 if (is_space_char (*base_string
))
4527 if (*base_string
== ','
4528 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4529 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4531 displacement_string_end
= temp_string
;
4533 i
.types
[this_operand
] |= BaseIndex
;
4537 base_string
= end_op
;
4538 if (is_space_char (*base_string
))
4542 /* There may be an index reg or scale factor here. */
4543 if (*base_string
== ',')
4546 if (is_space_char (*base_string
))
4549 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4550 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4552 base_string
= end_op
;
4553 if (is_space_char (*base_string
))
4555 if (*base_string
== ',')
4558 if (is_space_char (*base_string
))
4561 else if (*base_string
!= ')')
4563 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4568 else if (*base_string
== REGISTER_PREFIX
)
4570 as_bad (_("bad register name `%s'"), base_string
);
4574 /* Check for scale factor. */
4575 if (*base_string
!= ')')
4577 char *end_scale
= i386_scale (base_string
);
4582 base_string
= end_scale
;
4583 if (is_space_char (*base_string
))
4585 if (*base_string
!= ')')
4587 as_bad (_("expecting `)' after scale factor in `%s'"),
4592 else if (!i
.index_reg
)
4594 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4599 else if (*base_string
!= ')')
4601 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4606 else if (*base_string
== REGISTER_PREFIX
)
4608 as_bad (_("bad register name `%s'"), base_string
);
4613 /* If there's an expression beginning the operand, parse it,
4614 assuming displacement_string_start and
4615 displacement_string_end are meaningful. */
4616 if (displacement_string_start
!= displacement_string_end
)
4618 if (!i386_displacement (displacement_string_start
,
4619 displacement_string_end
))
4623 /* Special case for (%dx) while doing input/output op. */
4625 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4627 && i
.log2_scale_factor
== 0
4628 && i
.seg
[i
.mem_operands
] == 0
4629 && (i
.types
[this_operand
] & Disp
) == 0)
4631 i
.types
[this_operand
] = InOutPortReg
;
4635 if (i386_index_check (operand_string
) == 0)
4641 /* It's not a memory operand; argh! */
4642 as_bad (_("invalid char %s beginning operand %d `%s'"),
4643 output_invalid (*op_string
),
4648 return 1; /* Normal return. */
4651 /* md_estimate_size_before_relax()
4653 Called just before relax() for rs_machine_dependent frags. The x86
4654 assembler uses these frags to handle variable size jump
4657 Any symbol that is now undefined will not become defined.
4658 Return the correct fr_subtype in the frag.
4659 Return the initial "guess for variable size of frag" to caller.
4660 The guess is actually the growth beyond the fixed part. Whatever
4661 we do to grow the fixed or variable part contributes to our
4665 md_estimate_size_before_relax (fragP
, segment
)
4669 /* We've already got fragP->fr_subtype right; all we have to do is
4670 check for un-relaxable symbols. On an ELF system, we can't relax
4671 an externally visible symbol, because it may be overridden by a
4673 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4676 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4677 || S_IS_WEAK (fragP
->fr_symbol
)))
4681 /* Symbol is undefined in this segment, or we need to keep a
4682 reloc so that weak symbols can be overridden. */
4683 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4684 enum bfd_reloc_code_real reloc_type
;
4685 unsigned char *opcode
;
4688 if (fragP
->fr_var
!= NO_RELOC
)
4689 reloc_type
= fragP
->fr_var
;
4691 reloc_type
= BFD_RELOC_16_PCREL
;
4693 reloc_type
= BFD_RELOC_32_PCREL
;
4695 old_fr_fix
= fragP
->fr_fix
;
4696 opcode
= (unsigned char *) fragP
->fr_opcode
;
4698 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4701 /* Make jmp (0xeb) a (d)word displacement jump. */
4703 fragP
->fr_fix
+= size
;
4704 fix_new (fragP
, old_fr_fix
, size
,
4706 fragP
->fr_offset
, 1,
4712 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4714 /* Negate the condition, and branch past an
4715 unconditional jump. */
4718 /* Insert an unconditional jump. */
4720 /* We added two extra opcode bytes, and have a two byte
4722 fragP
->fr_fix
+= 2 + 2;
4723 fix_new (fragP
, old_fr_fix
+ 2, 2,
4725 fragP
->fr_offset
, 1,
4732 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4737 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4739 fragP
->fr_offset
, 1,
4741 fixP
->fx_signed
= 1;
4745 /* This changes the byte-displacement jump 0x7N
4746 to the (d)word-displacement jump 0x0f,0x8N. */
4747 opcode
[1] = opcode
[0] + 0x10;
4748 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4749 /* We've added an opcode byte. */
4750 fragP
->fr_fix
+= 1 + size
;
4751 fix_new (fragP
, old_fr_fix
+ 1, size
,
4753 fragP
->fr_offset
, 1,
4758 BAD_CASE (fragP
->fr_subtype
);
4762 return fragP
->fr_fix
- old_fr_fix
;
4765 /* Guess size depending on current relax state. Initially the relax
4766 state will correspond to a short jump and we return 1, because
4767 the variable part of the frag (the branch offset) is one byte
4768 long. However, we can relax a section more than once and in that
4769 case we must either set fr_subtype back to the unrelaxed state,
4770 or return the value for the appropriate branch. */
4771 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4774 /* Called after relax() is finished.
4776 In: Address of frag.
4777 fr_type == rs_machine_dependent.
4778 fr_subtype is what the address relaxed to.
4780 Out: Any fixSs and constants are set up.
4781 Caller will turn frag into a ".space 0". */
4784 md_convert_frag (abfd
, sec
, fragP
)
4785 bfd
*abfd ATTRIBUTE_UNUSED
;
4786 segT sec ATTRIBUTE_UNUSED
;
4789 unsigned char *opcode
;
4790 unsigned char *where_to_put_displacement
= NULL
;
4791 offsetT target_address
;
4792 offsetT opcode_address
;
4793 unsigned int extension
= 0;
4794 offsetT displacement_from_opcode_start
;
4796 opcode
= (unsigned char *) fragP
->fr_opcode
;
4798 /* Address we want to reach in file space. */
4799 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4801 /* Address opcode resides at in file space. */
4802 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4804 /* Displacement from opcode start to fill into instruction. */
4805 displacement_from_opcode_start
= target_address
- opcode_address
;
4807 if ((fragP
->fr_subtype
& BIG
) == 0)
4809 /* Don't have to change opcode. */
4810 extension
= 1; /* 1 opcode + 1 displacement */
4811 where_to_put_displacement
= &opcode
[1];
4815 if (no_cond_jump_promotion
4816 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4817 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4819 switch (fragP
->fr_subtype
)
4821 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4822 extension
= 4; /* 1 opcode + 4 displacement */
4824 where_to_put_displacement
= &opcode
[1];
4827 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4828 extension
= 2; /* 1 opcode + 2 displacement */
4830 where_to_put_displacement
= &opcode
[1];
4833 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4834 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4835 extension
= 5; /* 2 opcode + 4 displacement */
4836 opcode
[1] = opcode
[0] + 0x10;
4837 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4838 where_to_put_displacement
= &opcode
[2];
4841 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4842 extension
= 3; /* 2 opcode + 2 displacement */
4843 opcode
[1] = opcode
[0] + 0x10;
4844 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4845 where_to_put_displacement
= &opcode
[2];
4848 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4853 where_to_put_displacement
= &opcode
[3];
4857 BAD_CASE (fragP
->fr_subtype
);
4862 /* Now put displacement after opcode. */
4863 md_number_to_chars ((char *) where_to_put_displacement
,
4864 (valueT
) (displacement_from_opcode_start
- extension
),
4865 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4866 fragP
->fr_fix
+= extension
;
4869 /* Size of byte displacement jmp. */
4870 int md_short_jump_size
= 2;
4872 /* Size of dword displacement jmp. */
4873 int md_long_jump_size
= 5;
4876 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4878 addressT from_addr
, to_addr
;
4879 fragS
*frag ATTRIBUTE_UNUSED
;
4880 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4884 offset
= to_addr
- (from_addr
+ 2);
4885 /* Opcode for byte-disp jump. */
4886 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4887 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4891 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4893 addressT from_addr
, to_addr
;
4894 fragS
*frag ATTRIBUTE_UNUSED
;
4895 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4899 offset
= to_addr
- (from_addr
+ 5);
4900 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4901 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4904 /* Apply a fixup (fixS) to segment data, once it has been determined
4905 by our caller that we have all the info we need to fix it up.
4907 On the 386, immediates, displacements, and data pointers are all in
4908 the same (little-endian) format, so we don't need to care about which
4912 md_apply_fix (fixP
, valP
, seg
)
4913 /* The fix we're to put in. */
4915 /* Pointer to the value of the bits. */
4917 /* Segment fix is from. */
4918 segT seg ATTRIBUTE_UNUSED
;
4920 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4921 valueT value
= *valP
;
4923 #if !defined (TE_Mach)
4926 switch (fixP
->fx_r_type
)
4932 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4935 case BFD_RELOC_X86_64_32S
:
4936 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4939 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4942 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4947 if (fixP
->fx_addsy
!= NULL
4948 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4949 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4950 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4951 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4952 && !use_rela_relocations
)
4954 /* This is a hack. There should be a better way to handle this.
4955 This covers for the fact that bfd_install_relocation will
4956 subtract the current location (for partial_inplace, PC relative
4957 relocations); see more below. */
4961 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4964 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4969 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4972 || (symbol_section_p (fixP
->fx_addsy
)
4973 && sym_seg
!= absolute_section
))
4974 && !generic_force_reloc (fixP
))
4976 /* Yes, we add the values in twice. This is because
4977 bfd_install_relocation subtracts them out again. I think
4978 bfd_install_relocation is broken, but I don't dare change
4980 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4984 #if defined (OBJ_COFF) && defined (TE_PE)
4985 /* For some reason, the PE format does not store a
4986 section address offset for a PC relative symbol. */
4987 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4988 || S_IS_WEAK (fixP
->fx_addsy
))
4989 value
+= md_pcrel_from (fixP
);
4993 /* Fix a few things - the dynamic linker expects certain values here,
4994 and we must not disappoint it. */
4995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4996 if (IS_ELF
&& fixP
->fx_addsy
)
4997 switch (fixP
->fx_r_type
)
4999 case BFD_RELOC_386_PLT32
:
5000 case BFD_RELOC_X86_64_PLT32
:
5001 /* Make the jump instruction point to the address of the operand. At
5002 runtime we merely add the offset to the actual PLT entry. */
5006 case BFD_RELOC_386_TLS_GD
:
5007 case BFD_RELOC_386_TLS_LDM
:
5008 case BFD_RELOC_386_TLS_IE_32
:
5009 case BFD_RELOC_386_TLS_IE
:
5010 case BFD_RELOC_386_TLS_GOTIE
:
5011 case BFD_RELOC_X86_64_TLSGD
:
5012 case BFD_RELOC_X86_64_TLSLD
:
5013 case BFD_RELOC_X86_64_GOTTPOFF
:
5014 value
= 0; /* Fully resolved at runtime. No addend. */
5016 case BFD_RELOC_386_TLS_LE
:
5017 case BFD_RELOC_386_TLS_LDO_32
:
5018 case BFD_RELOC_386_TLS_LE_32
:
5019 case BFD_RELOC_X86_64_DTPOFF32
:
5020 case BFD_RELOC_X86_64_DTPOFF64
:
5021 case BFD_RELOC_X86_64_TPOFF32
:
5022 case BFD_RELOC_X86_64_TPOFF64
:
5023 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5026 case BFD_RELOC_386_GOT32
:
5027 case BFD_RELOC_X86_64_GOT32
:
5028 value
= 0; /* Fully resolved at runtime. No addend. */
5031 case BFD_RELOC_VTABLE_INHERIT
:
5032 case BFD_RELOC_VTABLE_ENTRY
:
5039 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5041 #endif /* !defined (TE_Mach) */
5043 /* Are we finished with this relocation now? */
5044 if (fixP
->fx_addsy
== NULL
)
5046 else if (use_rela_relocations
)
5048 fixP
->fx_no_overflow
= 1;
5049 /* Remember value for tc_gen_reloc. */
5050 fixP
->fx_addnumber
= value
;
5054 md_number_to_chars (p
, value
, fixP
->fx_size
);
5057 #define MAX_LITTLENUMS 6
5059 /* Turn the string pointed to by litP into a floating point constant
5060 of type TYPE, and emit the appropriate bytes. The number of
5061 LITTLENUMS emitted is stored in *SIZEP. An error message is
5062 returned, or NULL on OK. */
5065 md_atof (type
, litP
, sizeP
)
5071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5072 LITTLENUM_TYPE
*wordP
;
5094 return _("Bad call to md_atof ()");
5096 t
= atof_ieee (input_line_pointer
, type
, words
);
5098 input_line_pointer
= t
;
5100 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5101 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5102 the bigendian 386. */
5103 for (wordP
= words
+ prec
- 1; prec
--;)
5105 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5106 litP
+= sizeof (LITTLENUM_TYPE
);
5111 static char output_invalid_buf
[8];
5118 sprintf (output_invalid_buf
, "'%c'", c
);
5120 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5121 return output_invalid_buf
;
5124 /* REG_STRING starts *before* REGISTER_PREFIX. */
5126 static const reg_entry
*
5127 parse_register (reg_string
, end_op
)
5131 char *s
= reg_string
;
5133 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5136 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5137 if (*s
== REGISTER_PREFIX
)
5140 if (is_space_char (*s
))
5144 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5146 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5147 return (const reg_entry
*) NULL
;
5151 /* For naked regs, make sure that we are not dealing with an identifier.
5152 This prevents confusing an identifier like `eax_var' with register
5154 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5155 return (const reg_entry
*) NULL
;
5159 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5161 /* Handle floating point regs, allowing spaces in the (i) part. */
5162 if (r
== i386_regtab
/* %st is first entry of table */)
5164 if (is_space_char (*s
))
5169 if (is_space_char (*s
))
5171 if (*s
>= '0' && *s
<= '7')
5173 r
= &i386_float_regtab
[*s
- '0'];
5175 if (is_space_char (*s
))
5183 /* We have "%st(" then garbage. */
5184 return (const reg_entry
*) NULL
;
5189 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5190 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5191 && flag_code
!= CODE_64BIT
)
5192 return (const reg_entry
*) NULL
;
5197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5198 const char *md_shortopts
= "kVQ:sqn";
5200 const char *md_shortopts
= "qn";
5203 struct option md_longopts
[] = {
5204 #define OPTION_32 (OPTION_MD_BASE + 0)
5205 {"32", no_argument
, NULL
, OPTION_32
},
5206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5207 #define OPTION_64 (OPTION_MD_BASE + 1)
5208 {"64", no_argument
, NULL
, OPTION_64
},
5210 {NULL
, no_argument
, NULL
, 0}
5212 size_t md_longopts_size
= sizeof (md_longopts
);
5215 md_parse_option (c
, arg
)
5217 char *arg ATTRIBUTE_UNUSED
;
5222 optimize_align_code
= 0;
5229 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5230 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5231 should be emitted or not. FIXME: Not implemented. */
5235 /* -V: SVR4 argument to print version ID. */
5237 print_version_id ();
5240 /* -k: Ignore for FreeBSD compatibility. */
5245 /* -s: On i386 Solaris, this tells the native assembler to use
5246 .stab instead of .stab.excl. We always use .stab anyhow. */
5251 const char **list
, **l
;
5253 list
= bfd_target_list ();
5254 for (l
= list
; *l
!= NULL
; l
++)
5255 if (strcmp (*l
, "elf64-x86-64") == 0)
5257 default_arch
= "x86_64";
5261 as_fatal (_("No compiled in support for x86_64"));
5268 default_arch
= "i386";
5278 md_show_usage (stream
)
5281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5282 fprintf (stream
, _("\
5284 -V print assembler version number\n\
5286 -n Do not optimize code alignment\n\
5287 -q quieten some warnings\n\
5290 fprintf (stream
, _("\
5291 -n Do not optimize code alignment\n\
5292 -q quieten some warnings\n"));
5296 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5297 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5299 /* Pick the target format to use. */
5302 i386_target_format ()
5304 if (!strcmp (default_arch
, "x86_64"))
5305 set_code_flag (CODE_64BIT
);
5306 else if (!strcmp (default_arch
, "i386"))
5307 set_code_flag (CODE_32BIT
);
5309 as_fatal (_("Unknown architecture"));
5310 switch (OUTPUT_FLAVOR
)
5312 #ifdef OBJ_MAYBE_AOUT
5313 case bfd_target_aout_flavour
:
5314 return AOUT_TARGET_FORMAT
;
5316 #ifdef OBJ_MAYBE_COFF
5317 case bfd_target_coff_flavour
:
5320 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5321 case bfd_target_elf_flavour
:
5323 if (flag_code
== CODE_64BIT
)
5326 use_rela_relocations
= 1;
5328 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5337 #endif /* OBJ_MAYBE_ more than one */
5339 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5340 void i386_elf_emit_arch_note ()
5342 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5345 asection
*seg
= now_seg
;
5346 subsegT subseg
= now_subseg
;
5347 Elf_Internal_Note i_note
;
5348 Elf_External_Note e_note
;
5349 asection
*note_secp
;
5352 /* Create the .note section. */
5353 note_secp
= subseg_new (".note", 0);
5354 bfd_set_section_flags (stdoutput
,
5356 SEC_HAS_CONTENTS
| SEC_READONLY
);
5358 /* Process the arch string. */
5359 len
= strlen (cpu_arch_name
);
5361 i_note
.namesz
= len
+ 1;
5363 i_note
.type
= NT_ARCH
;
5364 p
= frag_more (sizeof (e_note
.namesz
));
5365 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5366 p
= frag_more (sizeof (e_note
.descsz
));
5367 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5368 p
= frag_more (sizeof (e_note
.type
));
5369 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5370 p
= frag_more (len
+ 1);
5371 strcpy (p
, cpu_arch_name
);
5373 frag_align (2, 0, 0);
5375 subseg_set (seg
, subseg
);
5381 md_undefined_symbol (name
)
5384 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5385 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5386 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5387 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5391 if (symbol_find (name
))
5392 as_bad (_("GOT already in symbol table"));
5393 GOT_symbol
= symbol_new (name
, undefined_section
,
5394 (valueT
) 0, &zero_address_frag
);
5401 /* Round up a section size to the appropriate boundary. */
5404 md_section_align (segment
, size
)
5405 segT segment ATTRIBUTE_UNUSED
;
5408 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5409 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5411 /* For a.out, force the section size to be aligned. If we don't do
5412 this, BFD will align it for us, but it will not write out the
5413 final bytes of the section. This may be a bug in BFD, but it is
5414 easier to fix it here since that is how the other a.out targets
5418 align
= bfd_get_section_alignment (stdoutput
, segment
);
5419 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5426 /* On the i386, PC-relative offsets are relative to the start of the
5427 next instruction. That is, the address of the offset, plus its
5428 size, since the offset is always the last part of the insn. */
5431 md_pcrel_from (fixP
)
5434 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5441 int ignore ATTRIBUTE_UNUSED
;
5445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5447 obj_elf_section_change_hook ();
5449 temp
= get_absolute_expression ();
5450 subseg_set (bss_section
, (subsegT
) temp
);
5451 demand_empty_rest_of_line ();
5457 i386_validate_fix (fixp
)
5460 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5462 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5466 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5471 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5473 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5480 tc_gen_reloc (section
, fixp
)
5481 asection
*section ATTRIBUTE_UNUSED
;
5485 bfd_reloc_code_real_type code
;
5487 switch (fixp
->fx_r_type
)
5489 case BFD_RELOC_X86_64_PLT32
:
5490 case BFD_RELOC_X86_64_GOT32
:
5491 case BFD_RELOC_X86_64_GOTPCREL
:
5492 case BFD_RELOC_386_PLT32
:
5493 case BFD_RELOC_386_GOT32
:
5494 case BFD_RELOC_386_GOTOFF
:
5495 case BFD_RELOC_386_GOTPC
:
5496 case BFD_RELOC_386_TLS_GD
:
5497 case BFD_RELOC_386_TLS_LDM
:
5498 case BFD_RELOC_386_TLS_LDO_32
:
5499 case BFD_RELOC_386_TLS_IE_32
:
5500 case BFD_RELOC_386_TLS_IE
:
5501 case BFD_RELOC_386_TLS_GOTIE
:
5502 case BFD_RELOC_386_TLS_LE_32
:
5503 case BFD_RELOC_386_TLS_LE
:
5504 case BFD_RELOC_X86_64_TLSGD
:
5505 case BFD_RELOC_X86_64_TLSLD
:
5506 case BFD_RELOC_X86_64_DTPOFF32
:
5507 case BFD_RELOC_X86_64_DTPOFF64
:
5508 case BFD_RELOC_X86_64_GOTTPOFF
:
5509 case BFD_RELOC_X86_64_TPOFF32
:
5510 case BFD_RELOC_X86_64_TPOFF64
:
5511 case BFD_RELOC_X86_64_GOTOFF64
:
5512 case BFD_RELOC_X86_64_GOTPC32
:
5514 case BFD_RELOC_VTABLE_ENTRY
:
5515 case BFD_RELOC_VTABLE_INHERIT
:
5517 case BFD_RELOC_32_SECREL
:
5519 code
= fixp
->fx_r_type
;
5521 case BFD_RELOC_X86_64_32S
:
5522 if (!fixp
->fx_pcrel
)
5524 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5525 code
= fixp
->fx_r_type
;
5531 switch (fixp
->fx_size
)
5534 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5535 _("can not do %d byte pc-relative relocation"),
5537 code
= BFD_RELOC_32_PCREL
;
5539 case 1: code
= BFD_RELOC_8_PCREL
; break;
5540 case 2: code
= BFD_RELOC_16_PCREL
; break;
5541 case 4: code
= BFD_RELOC_32_PCREL
; break;
5543 case 8: code
= BFD_RELOC_64_PCREL
; break;
5549 switch (fixp
->fx_size
)
5552 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5553 _("can not do %d byte relocation"),
5555 code
= BFD_RELOC_32
;
5557 case 1: code
= BFD_RELOC_8
; break;
5558 case 2: code
= BFD_RELOC_16
; break;
5559 case 4: code
= BFD_RELOC_32
; break;
5561 case 8: code
= BFD_RELOC_64
; break;
5568 if ((code
== BFD_RELOC_32
5569 || code
== BFD_RELOC_32_PCREL
5570 || code
== BFD_RELOC_X86_64_32S
)
5572 && fixp
->fx_addsy
== GOT_symbol
)
5575 code
= BFD_RELOC_386_GOTPC
;
5577 code
= BFD_RELOC_X86_64_GOTPC32
;
5580 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5581 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5582 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5584 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5586 if (!use_rela_relocations
)
5588 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5589 vtable entry to be used in the relocation's section offset. */
5590 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5591 rel
->address
= fixp
->fx_offset
;
5595 /* Use the rela in 64bit mode. */
5598 if (!fixp
->fx_pcrel
)
5599 rel
->addend
= fixp
->fx_offset
;
5603 case BFD_RELOC_X86_64_PLT32
:
5604 case BFD_RELOC_X86_64_GOT32
:
5605 case BFD_RELOC_X86_64_GOTPCREL
:
5606 case BFD_RELOC_X86_64_TLSGD
:
5607 case BFD_RELOC_X86_64_TLSLD
:
5608 case BFD_RELOC_X86_64_GOTTPOFF
:
5609 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5612 rel
->addend
= (section
->vma
5614 + fixp
->fx_addnumber
5615 + md_pcrel_from (fixp
));
5620 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5621 if (rel
->howto
== NULL
)
5623 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5624 _("cannot represent relocation type %s"),
5625 bfd_get_reloc_code_name (code
));
5626 /* Set howto to a garbage value so that we can keep going. */
5627 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5628 assert (rel
->howto
!= NULL
);
5635 /* Parse operands using Intel syntax. This implements a recursive descent
5636 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5639 FIXME: We do not recognize the full operand grammar defined in the MASM
5640 documentation. In particular, all the structure/union and
5641 high-level macro operands are missing.
5643 Uppercase words are terminals, lower case words are non-terminals.
5644 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5645 bars '|' denote choices. Most grammar productions are implemented in
5646 functions called 'intel_<production>'.
5648 Initial production is 'expr'.
5654 binOp & | AND | \| | OR | ^ | XOR
5656 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5658 constant digits [[ radixOverride ]]
5660 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5698 => expr expr cmpOp e04
5701 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5702 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5704 hexdigit a | b | c | d | e | f
5705 | A | B | C | D | E | F
5711 mulOp * | / | % | MOD | << | SHL | >> | SHR
5715 register specialRegister
5719 segmentRegister CS | DS | ES | FS | GS | SS
5721 specialRegister CR0 | CR2 | CR3 | CR4
5722 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5723 | TR3 | TR4 | TR5 | TR6 | TR7
5725 We simplify the grammar in obvious places (e.g., register parsing is
5726 done by calling parse_register) and eliminate immediate left recursion
5727 to implement a recursive-descent parser.
5731 expr' cmpOp e04 expr'
5782 /* Parsing structure for the intel syntax parser. Used to implement the
5783 semantic actions for the operand grammar. */
5784 struct intel_parser_s
5786 char *op_string
; /* The string being parsed. */
5787 int got_a_float
; /* Whether the operand is a float. */
5788 int op_modifier
; /* Operand modifier. */
5789 int is_mem
; /* 1 if operand is memory reference. */
5790 int in_offset
; /* >=1 if parsing operand of offset. */
5791 int in_bracket
; /* >=1 if parsing operand in brackets. */
5792 const reg_entry
*reg
; /* Last register reference found. */
5793 char *disp
; /* Displacement string being built. */
5794 char *next_operand
; /* Resume point when splitting operands. */
5797 static struct intel_parser_s intel_parser
;
5799 /* Token structure for parsing intel syntax. */
5802 int code
; /* Token code. */
5803 const reg_entry
*reg
; /* Register entry for register tokens. */
5804 char *str
; /* String representation. */
5807 static struct intel_token cur_token
, prev_token
;
5809 /* Token codes for the intel parser. Since T_SHORT is already used
5810 by COFF, undefine it first to prevent a warning. */
5829 /* Prototypes for intel parser functions. */
5830 static int intel_match_token
PARAMS ((int code
));
5831 static void intel_get_token
PARAMS ((void));
5832 static void intel_putback_token
PARAMS ((void));
5833 static int intel_expr
PARAMS ((void));
5834 static int intel_e04
PARAMS ((void));
5835 static int intel_e05
PARAMS ((void));
5836 static int intel_e06
PARAMS ((void));
5837 static int intel_e09
PARAMS ((void));
5838 static int intel_bracket_expr
PARAMS ((void));
5839 static int intel_e10
PARAMS ((void));
5840 static int intel_e11
PARAMS ((void));
5843 i386_intel_operand (operand_string
, got_a_float
)
5844 char *operand_string
;
5850 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5851 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5855 /* Initialize token holders. */
5856 cur_token
.code
= prev_token
.code
= T_NIL
;
5857 cur_token
.reg
= prev_token
.reg
= NULL
;
5858 cur_token
.str
= prev_token
.str
= NULL
;
5860 /* Initialize parser structure. */
5861 intel_parser
.got_a_float
= got_a_float
;
5862 intel_parser
.op_modifier
= 0;
5863 intel_parser
.is_mem
= 0;
5864 intel_parser
.in_offset
= 0;
5865 intel_parser
.in_bracket
= 0;
5866 intel_parser
.reg
= NULL
;
5867 intel_parser
.disp
[0] = '\0';
5868 intel_parser
.next_operand
= NULL
;
5870 /* Read the first token and start the parser. */
5872 ret
= intel_expr ();
5877 if (cur_token
.code
!= T_NIL
)
5879 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5880 current_templates
->start
->name
, cur_token
.str
);
5883 /* If we found a memory reference, hand it over to i386_displacement
5884 to fill in the rest of the operand fields. */
5885 else if (intel_parser
.is_mem
)
5887 if ((i
.mem_operands
== 1
5888 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5889 || i
.mem_operands
== 2)
5891 as_bad (_("too many memory references for '%s'"),
5892 current_templates
->start
->name
);
5897 char *s
= intel_parser
.disp
;
5900 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5901 /* See the comments in intel_bracket_expr. */
5902 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5904 /* Add the displacement expression. */
5906 ret
= i386_displacement (s
, s
+ strlen (s
));
5909 /* Swap base and index in 16-bit memory operands like
5910 [si+bx]. Since i386_index_check is also used in AT&T
5911 mode we have to do that here. */
5914 && (i
.base_reg
->reg_type
& Reg16
)
5915 && (i
.index_reg
->reg_type
& Reg16
)
5916 && i
.base_reg
->reg_num
>= 6
5917 && i
.index_reg
->reg_num
< 6)
5919 const reg_entry
*base
= i
.index_reg
;
5921 i
.index_reg
= i
.base_reg
;
5924 ret
= i386_index_check (operand_string
);
5929 /* Constant and OFFSET expressions are handled by i386_immediate. */
5930 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5931 || intel_parser
.reg
== NULL
)
5932 ret
= i386_immediate (intel_parser
.disp
);
5934 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5936 if (!ret
|| !intel_parser
.next_operand
)
5938 intel_parser
.op_string
= intel_parser
.next_operand
;
5939 this_operand
= i
.operands
++;
5943 free (intel_parser
.disp
);
5948 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5952 expr' cmpOp e04 expr'
5957 /* XXX Implement the comparison operators. */
5958 return intel_e04 ();
5975 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5976 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5978 if (cur_token
.code
== '+')
5980 else if (cur_token
.code
== '-')
5981 nregs
= NUM_ADDRESS_REGS
;
5985 strcat (intel_parser
.disp
, cur_token
.str
);
5986 intel_match_token (cur_token
.code
);
5997 int nregs
= ~NUM_ADDRESS_REGS
;
6004 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6008 str
[0] = cur_token
.code
;
6010 strcat (intel_parser
.disp
, str
);
6015 intel_match_token (cur_token
.code
);
6020 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6021 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6032 int nregs
= ~NUM_ADDRESS_REGS
;
6039 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6043 str
[0] = cur_token
.code
;
6045 strcat (intel_parser
.disp
, str
);
6047 else if (cur_token
.code
== T_SHL
)
6048 strcat (intel_parser
.disp
, "<<");
6049 else if (cur_token
.code
== T_SHR
)
6050 strcat (intel_parser
.disp
, ">>");
6054 intel_match_token (cur_token
.code
);
6059 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6060 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6078 int nregs
= ~NUM_ADDRESS_REGS
;
6083 /* Don't consume constants here. */
6084 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6086 /* Need to look one token ahead - if the next token
6087 is a constant, the current token is its sign. */
6090 intel_match_token (cur_token
.code
);
6091 next_code
= cur_token
.code
;
6092 intel_putback_token ();
6093 if (next_code
== T_CONST
)
6097 /* e09 OFFSET e09 */
6098 if (cur_token
.code
== T_OFFSET
)
6101 ++intel_parser
.in_offset
;
6105 else if (cur_token
.code
== T_SHORT
)
6106 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6109 else if (cur_token
.code
== '+')
6110 strcat (intel_parser
.disp
, "+");
6115 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6121 str
[0] = cur_token
.code
;
6123 strcat (intel_parser
.disp
, str
);
6130 intel_match_token (cur_token
.code
);
6138 /* e09' PTR e10 e09' */
6139 if (cur_token
.code
== T_PTR
)
6143 if (prev_token
.code
== T_BYTE
)
6144 suffix
= BYTE_MNEM_SUFFIX
;
6146 else if (prev_token
.code
== T_WORD
)
6148 if (current_templates
->start
->name
[0] == 'l'
6149 && current_templates
->start
->name
[2] == 's'
6150 && current_templates
->start
->name
[3] == 0)
6151 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6152 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6153 suffix
= SHORT_MNEM_SUFFIX
;
6155 suffix
= WORD_MNEM_SUFFIX
;
6158 else if (prev_token
.code
== T_DWORD
)
6160 if (current_templates
->start
->name
[0] == 'l'
6161 && current_templates
->start
->name
[2] == 's'
6162 && current_templates
->start
->name
[3] == 0)
6163 suffix
= WORD_MNEM_SUFFIX
;
6164 else if (flag_code
== CODE_16BIT
6165 && (current_templates
->start
->opcode_modifier
6166 & (Jump
| JumpDword
)))
6167 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6168 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6169 suffix
= SHORT_MNEM_SUFFIX
;
6171 suffix
= LONG_MNEM_SUFFIX
;
6174 else if (prev_token
.code
== T_FWORD
)
6176 if (current_templates
->start
->name
[0] == 'l'
6177 && current_templates
->start
->name
[2] == 's'
6178 && current_templates
->start
->name
[3] == 0)
6179 suffix
= LONG_MNEM_SUFFIX
;
6180 else if (!intel_parser
.got_a_float
)
6182 if (flag_code
== CODE_16BIT
)
6183 add_prefix (DATA_PREFIX_OPCODE
);
6184 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6187 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6190 else if (prev_token
.code
== T_QWORD
)
6192 if (intel_parser
.got_a_float
== 1) /* "f..." */
6193 suffix
= LONG_MNEM_SUFFIX
;
6195 suffix
= QWORD_MNEM_SUFFIX
;
6198 else if (prev_token
.code
== T_TBYTE
)
6200 if (intel_parser
.got_a_float
== 1)
6201 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6203 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6206 else if (prev_token
.code
== T_XMMWORD
)
6208 /* XXX ignored for now, but accepted since gcc uses it */
6214 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6218 /* Operands for jump/call using 'ptr' notation denote absolute
6220 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6221 i
.types
[this_operand
] |= JumpAbsolute
;
6223 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6227 else if (i
.suffix
!= suffix
)
6229 as_bad (_("Conflicting operand modifiers"));
6235 /* e09' : e10 e09' */
6236 else if (cur_token
.code
== ':')
6238 if (prev_token
.code
!= T_REG
)
6240 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6241 segment/group identifier (which we don't have), using comma
6242 as the operand separator there is even less consistent, since
6243 there all branches only have a single operand. */
6244 if (this_operand
!= 0
6245 || intel_parser
.in_offset
6246 || intel_parser
.in_bracket
6247 || (!(current_templates
->start
->opcode_modifier
6248 & (Jump
|JumpDword
|JumpInterSegment
))
6249 && !(current_templates
->start
->operand_types
[0]
6251 return intel_match_token (T_NIL
);
6252 /* Remember the start of the 2nd operand and terminate 1st
6254 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6255 another expression), but it gets at least the simplest case
6256 (a plain number or symbol on the left side) right. */
6257 intel_parser
.next_operand
= intel_parser
.op_string
;
6258 *--intel_parser
.op_string
= '\0';
6259 return intel_match_token (':');
6267 intel_match_token (cur_token
.code
);
6273 --intel_parser
.in_offset
;
6276 if (NUM_ADDRESS_REGS
> nregs
)
6278 as_bad (_("Invalid operand to `OFFSET'"));
6281 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6284 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6285 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6290 intel_bracket_expr ()
6292 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6293 const char *start
= intel_parser
.op_string
;
6296 if (i
.op
[this_operand
].regs
)
6297 return intel_match_token (T_NIL
);
6299 intel_match_token ('[');
6301 /* Mark as a memory operand only if it's not already known to be an
6302 offset expression. If it's an offset expression, we need to keep
6304 if (!intel_parser
.in_offset
)
6306 ++intel_parser
.in_bracket
;
6308 /* Operands for jump/call inside brackets denote absolute addresses. */
6309 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6310 i
.types
[this_operand
] |= JumpAbsolute
;
6312 /* Unfortunately gas always diverged from MASM in a respect that can't
6313 be easily fixed without risking to break code sequences likely to be
6314 encountered (the testsuite even check for this): MASM doesn't consider
6315 an expression inside brackets unconditionally as a memory reference.
6316 When that is e.g. a constant, an offset expression, or the sum of the
6317 two, this is still taken as a constant load. gas, however, always
6318 treated these as memory references. As a compromise, we'll try to make
6319 offset expressions inside brackets work the MASM way (since that's
6320 less likely to be found in real world code), but make constants alone
6321 continue to work the traditional gas way. In either case, issue a
6323 intel_parser
.op_modifier
&= ~was_offset
;
6326 strcat (intel_parser
.disp
, "[");
6328 /* Add a '+' to the displacement string if necessary. */
6329 if (*intel_parser
.disp
!= '\0'
6330 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6331 strcat (intel_parser
.disp
, "+");
6334 && (len
= intel_parser
.op_string
- start
- 1,
6335 intel_match_token (']')))
6337 /* Preserve brackets when the operand is an offset expression. */
6338 if (intel_parser
.in_offset
)
6339 strcat (intel_parser
.disp
, "]");
6342 --intel_parser
.in_bracket
;
6343 if (i
.base_reg
|| i
.index_reg
)
6344 intel_parser
.is_mem
= 1;
6345 if (!intel_parser
.is_mem
)
6347 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6348 /* Defer the warning until all of the operand was parsed. */
6349 intel_parser
.is_mem
= -1;
6350 else if (!quiet_warnings
)
6351 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6354 intel_parser
.op_modifier
|= was_offset
;
6371 while (cur_token
.code
== '[')
6373 if (!intel_bracket_expr ())
6398 switch (cur_token
.code
)
6402 intel_match_token ('(');
6403 strcat (intel_parser
.disp
, "(");
6405 if (intel_expr () && intel_match_token (')'))
6407 strcat (intel_parser
.disp
, ")");
6414 return intel_bracket_expr ();
6419 strcat (intel_parser
.disp
, cur_token
.str
);
6420 intel_match_token (cur_token
.code
);
6422 /* Mark as a memory operand only if it's not already known to be an
6423 offset expression. */
6424 if (!intel_parser
.in_offset
)
6425 intel_parser
.is_mem
= 1;
6432 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6434 intel_match_token (T_REG
);
6436 /* Check for segment change. */
6437 if (cur_token
.code
== ':')
6439 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6441 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6444 else if (i
.seg
[i
.mem_operands
])
6445 as_warn (_("Extra segment override ignored"));
6448 if (!intel_parser
.in_offset
)
6449 intel_parser
.is_mem
= 1;
6450 switch (reg
->reg_num
)
6453 i
.seg
[i
.mem_operands
] = &es
;
6456 i
.seg
[i
.mem_operands
] = &cs
;
6459 i
.seg
[i
.mem_operands
] = &ss
;
6462 i
.seg
[i
.mem_operands
] = &ds
;
6465 i
.seg
[i
.mem_operands
] = &fs
;
6468 i
.seg
[i
.mem_operands
] = &gs
;
6474 /* Not a segment register. Check for register scaling. */
6475 else if (cur_token
.code
== '*')
6477 if (!intel_parser
.in_bracket
)
6479 as_bad (_("Register scaling only allowed in memory operands"));
6483 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6484 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6485 else if (i
.index_reg
)
6486 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6488 /* What follows must be a valid scale. */
6489 intel_match_token ('*');
6491 i
.types
[this_operand
] |= BaseIndex
;
6493 /* Set the scale after setting the register (otherwise,
6494 i386_scale will complain) */
6495 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6497 char *str
, sign
= cur_token
.code
;
6498 intel_match_token (cur_token
.code
);
6499 if (cur_token
.code
!= T_CONST
)
6501 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6505 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6506 strcpy (str
+ 1, cur_token
.str
);
6508 if (!i386_scale (str
))
6512 else if (!i386_scale (cur_token
.str
))
6514 intel_match_token (cur_token
.code
);
6517 /* No scaling. If this is a memory operand, the register is either a
6518 base register (first occurrence) or an index register (second
6520 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6525 else if (!i
.index_reg
)
6529 as_bad (_("Too many register references in memory operand"));
6533 i
.types
[this_operand
] |= BaseIndex
;
6536 /* Offset modifier. Add the register to the displacement string to be
6537 parsed as an immediate expression after we're done. */
6538 else if (intel_parser
.in_offset
)
6540 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6541 strcat (intel_parser
.disp
, reg
->reg_name
);
6544 /* It's neither base nor index nor offset. */
6545 else if (!intel_parser
.is_mem
)
6547 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6548 i
.op
[this_operand
].regs
= reg
;
6553 as_bad (_("Invalid use of register"));
6557 /* Since registers are not part of the displacement string (except
6558 when we're parsing offset operands), we may need to remove any
6559 preceding '+' from the displacement string. */
6560 if (*intel_parser
.disp
!= '\0'
6561 && !intel_parser
.in_offset
)
6563 char *s
= intel_parser
.disp
;
6564 s
+= strlen (s
) - 1;
6587 intel_match_token (cur_token
.code
);
6589 if (cur_token
.code
== T_PTR
)
6592 /* It must have been an identifier. */
6593 intel_putback_token ();
6594 cur_token
.code
= T_ID
;
6600 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6604 /* The identifier represents a memory reference only if it's not
6605 preceded by an offset modifier and if it's not an equate. */
6606 symbolP
= symbol_find(cur_token
.str
);
6607 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6608 intel_parser
.is_mem
= 1;
6616 char *save_str
, sign
= 0;
6618 /* Allow constants that start with `+' or `-'. */
6619 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6621 sign
= cur_token
.code
;
6622 intel_match_token (cur_token
.code
);
6623 if (cur_token
.code
!= T_CONST
)
6625 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6631 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6632 strcpy (save_str
+ !!sign
, cur_token
.str
);
6636 /* Get the next token to check for register scaling. */
6637 intel_match_token (cur_token
.code
);
6639 /* Check if this constant is a scaling factor for an index register. */
6640 if (cur_token
.code
== '*')
6642 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6644 const reg_entry
*reg
= cur_token
.reg
;
6646 if (!intel_parser
.in_bracket
)
6648 as_bad (_("Register scaling only allowed in memory operands"));
6652 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6653 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6654 else if (i
.index_reg
)
6655 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6657 /* The constant is followed by `* reg', so it must be
6660 i
.types
[this_operand
] |= BaseIndex
;
6662 /* Set the scale after setting the register (otherwise,
6663 i386_scale will complain) */
6664 if (!i386_scale (save_str
))
6666 intel_match_token (T_REG
);
6668 /* Since registers are not part of the displacement
6669 string, we may need to remove any preceding '+' from
6670 the displacement string. */
6671 if (*intel_parser
.disp
!= '\0')
6673 char *s
= intel_parser
.disp
;
6674 s
+= strlen (s
) - 1;
6684 /* The constant was not used for register scaling. Since we have
6685 already consumed the token following `*' we now need to put it
6686 back in the stream. */
6687 intel_putback_token ();
6690 /* Add the constant to the displacement string. */
6691 strcat (intel_parser
.disp
, save_str
);
6698 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6702 /* Match the given token against cur_token. If they match, read the next
6703 token from the operand string. */
6705 intel_match_token (code
)
6708 if (cur_token
.code
== code
)
6715 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6720 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6725 const reg_entry
*reg
;
6726 struct intel_token new_token
;
6728 new_token
.code
= T_NIL
;
6729 new_token
.reg
= NULL
;
6730 new_token
.str
= NULL
;
6732 /* Free the memory allocated to the previous token and move
6733 cur_token to prev_token. */
6735 free (prev_token
.str
);
6737 prev_token
= cur_token
;
6739 /* Skip whitespace. */
6740 while (is_space_char (*intel_parser
.op_string
))
6741 intel_parser
.op_string
++;
6743 /* Return an empty token if we find nothing else on the line. */
6744 if (*intel_parser
.op_string
== '\0')
6746 cur_token
= new_token
;
6750 /* The new token cannot be larger than the remainder of the operand
6752 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6753 new_token
.str
[0] = '\0';
6755 if (strchr ("0123456789", *intel_parser
.op_string
))
6757 char *p
= new_token
.str
;
6758 char *q
= intel_parser
.op_string
;
6759 new_token
.code
= T_CONST
;
6761 /* Allow any kind of identifier char to encompass floating point and
6762 hexadecimal numbers. */
6763 while (is_identifier_char (*q
))
6767 /* Recognize special symbol names [0-9][bf]. */
6768 if (strlen (intel_parser
.op_string
) == 2
6769 && (intel_parser
.op_string
[1] == 'b'
6770 || intel_parser
.op_string
[1] == 'f'))
6771 new_token
.code
= T_ID
;
6774 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6775 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6777 new_token
.code
= T_REG
;
6778 new_token
.reg
= reg
;
6780 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6782 new_token
.str
[0] = REGISTER_PREFIX
;
6783 new_token
.str
[1] = '\0';
6786 strcat (new_token
.str
, reg
->reg_name
);
6789 else if (is_identifier_char (*intel_parser
.op_string
))
6791 char *p
= new_token
.str
;
6792 char *q
= intel_parser
.op_string
;
6794 /* A '.' or '$' followed by an identifier char is an identifier.
6795 Otherwise, it's operator '.' followed by an expression. */
6796 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6798 new_token
.code
= '.';
6799 new_token
.str
[0] = '.';
6800 new_token
.str
[1] = '\0';
6804 while (is_identifier_char (*q
) || *q
== '@')
6808 if (strcasecmp (new_token
.str
, "NOT") == 0)
6809 new_token
.code
= '~';
6811 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6812 new_token
.code
= '%';
6814 else if (strcasecmp (new_token
.str
, "AND") == 0)
6815 new_token
.code
= '&';
6817 else if (strcasecmp (new_token
.str
, "OR") == 0)
6818 new_token
.code
= '|';
6820 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6821 new_token
.code
= '^';
6823 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6824 new_token
.code
= T_SHL
;
6826 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6827 new_token
.code
= T_SHR
;
6829 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6830 new_token
.code
= T_BYTE
;
6832 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6833 new_token
.code
= T_WORD
;
6835 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6836 new_token
.code
= T_DWORD
;
6838 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6839 new_token
.code
= T_FWORD
;
6841 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6842 new_token
.code
= T_QWORD
;
6844 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6845 /* XXX remove (gcc still uses it) */
6846 || strcasecmp (new_token
.str
, "XWORD") == 0)
6847 new_token
.code
= T_TBYTE
;
6849 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6850 || strcasecmp (new_token
.str
, "OWORD") == 0)
6851 new_token
.code
= T_XMMWORD
;
6853 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6854 new_token
.code
= T_PTR
;
6856 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6857 new_token
.code
= T_SHORT
;
6859 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6861 new_token
.code
= T_OFFSET
;
6863 /* ??? This is not mentioned in the MASM grammar but gcc
6864 makes use of it with -mintel-syntax. OFFSET may be
6865 followed by FLAT: */
6866 if (strncasecmp (q
, " FLAT:", 6) == 0)
6867 strcat (new_token
.str
, " FLAT:");
6870 /* ??? This is not mentioned in the MASM grammar. */
6871 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6873 new_token
.code
= T_OFFSET
;
6875 strcat (new_token
.str
, ":");
6877 as_bad (_("`:' expected"));
6881 new_token
.code
= T_ID
;
6885 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6887 new_token
.code
= *intel_parser
.op_string
;
6888 new_token
.str
[0] = *intel_parser
.op_string
;
6889 new_token
.str
[1] = '\0';
6892 else if (strchr ("<>", *intel_parser
.op_string
)
6893 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6895 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6896 new_token
.str
[0] = *intel_parser
.op_string
;
6897 new_token
.str
[1] = *intel_parser
.op_string
;
6898 new_token
.str
[2] = '\0';
6902 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6904 intel_parser
.op_string
+= strlen (new_token
.str
);
6905 cur_token
= new_token
;
6908 /* Put cur_token back into the token stream and make cur_token point to
6911 intel_putback_token ()
6913 if (cur_token
.code
!= T_NIL
)
6915 intel_parser
.op_string
-= strlen (cur_token
.str
);
6916 free (cur_token
.str
);
6918 cur_token
= prev_token
;
6920 /* Forget prev_token. */
6921 prev_token
.code
= T_NIL
;
6922 prev_token
.reg
= NULL
;
6923 prev_token
.str
= NULL
;
6927 tc_x86_regname_to_dw2regnum (const char *regname
)
6929 unsigned int regnum
;
6930 unsigned int regnames_count
;
6931 static const char *const regnames_32
[] =
6933 "eax", "ecx", "edx", "ebx",
6934 "esp", "ebp", "esi", "edi",
6935 "eip", "eflags", NULL
,
6936 "st0", "st1", "st2", "st3",
6937 "st4", "st5", "st6", "st7",
6939 "xmm0", "xmm1", "xmm2", "xmm3",
6940 "xmm4", "xmm5", "xmm6", "xmm7",
6941 "mm0", "mm1", "mm2", "mm3",
6942 "mm4", "mm5", "mm6", "mm7",
6943 "fcw", "fsw", "mxcsr",
6944 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
6947 static const char *const regnames_64
[] =
6949 "rax", "rdx", "rcx", "rbx",
6950 "rsi", "rdi", "rbp", "rsp",
6951 "r8", "r9", "r10", "r11",
6952 "r12", "r13", "r14", "r15",
6954 "xmm0", "xmm1", "xmm2", "xmm3",
6955 "xmm4", "xmm5", "xmm6", "xmm7",
6956 "xmm8", "xmm9", "xmm10", "xmm11",
6957 "xmm12", "xmm13", "xmm14", "xmm15",
6958 "st0", "st1", "st2", "st3",
6959 "st4", "st5", "st6", "st7",
6960 "mm0", "mm1", "mm2", "mm3",
6961 "mm4", "mm5", "mm6", "mm7",
6963 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
6964 "fs.base", "gs.base", NULL
, NULL
,
6966 "mxcsr", "fcw", "fsw"
6968 const char *const *regnames
;
6970 if (flag_code
== CODE_64BIT
)
6972 regnames
= regnames_64
;
6973 regnames_count
= ARRAY_SIZE (regnames_64
);
6977 regnames
= regnames_32
;
6978 regnames_count
= ARRAY_SIZE (regnames_32
);
6981 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6982 if (regnames
[regnum
] != NULL
6983 && strcmp (regname
, regnames
[regnum
]) == 0)
6990 tc_x86_frame_initial_instructions (void)
6992 static unsigned int sp_regno
;
6995 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6998 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6999 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7003 i386_elf_section_type (const char *str
, size_t len
)
7005 if (flag_code
== CODE_64BIT
7006 && len
== sizeof ("unwind") - 1
7007 && strncmp (str
, "unwind", 6) == 0)
7008 return SHT_X86_64_UNWIND
;
7015 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7019 expr
.X_op
= O_secrel
;
7020 expr
.X_add_symbol
= symbol
;
7021 expr
.X_add_number
= 0;
7022 emit_expr (&expr
, size
);
7026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7027 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7030 x86_64_section_letter (int letter
, char **ptr_msg
)
7032 if (flag_code
== CODE_64BIT
)
7035 return SHF_X86_64_LARGE
;
7037 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7040 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7045 x86_64_section_word (char *str
, size_t len
)
7047 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7048 return SHF_X86_64_LARGE
;
7054 handle_large_common (int small ATTRIBUTE_UNUSED
)
7056 if (flag_code
!= CODE_64BIT
)
7058 s_comm_internal (0, elf_common_parse
);
7059 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7063 static segT lbss_section
;
7064 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7065 asection
*saved_bss_section
= bss_section
;
7067 if (lbss_section
== NULL
)
7069 flagword applicable
;
7071 subsegT subseg
= now_subseg
;
7073 /* The .lbss section is for local .largecomm symbols. */
7074 lbss_section
= subseg_new (".lbss", 0);
7075 applicable
= bfd_applicable_section_flags (stdoutput
);
7076 bfd_set_section_flags (stdoutput
, lbss_section
,
7077 applicable
& SEC_ALLOC
);
7078 seg_info (lbss_section
)->bss
= 1;
7080 subseg_set (seg
, subseg
);
7083 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7084 bss_section
= lbss_section
;
7086 s_comm_internal (0, elf_common_parse
);
7088 elf_com_section_ptr
= saved_com_section_ptr
;
7089 bss_section
= saved_bss_section
;
7092 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */