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[binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
381 /* REP prefix. */
382 const char *rep_prefix;
383
384 /* HLE prefix. */
385 const char *hle_prefix;
386
387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
393 /* Error message. */
394 enum i386_error error;
395 };
396
397 typedef struct _i386_insn i386_insn;
398
399 /* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401 struct RC_name
402 {
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406 };
407
408 static const struct RC_name RC_NamesTable[] =
409 {
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415 };
416
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars[] = "*%-([{}"
420 #ifdef LEX_AT
421 "@"
422 #endif
423 #ifdef LEX_QM
424 "?"
425 #endif
426 ;
427
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars = "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
443
444 #else
445 const char *i386_comment_chars = "#";
446 #define PREFIX_SEPARATOR '/'
447 #endif
448
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars[] = "#/";
458
459 const char line_separator_chars[] = ";";
460
461 /* Chars that can be used to separate mant from exp in floating point
462 nums. */
463 const char EXP_CHARS[] = "eE";
464
465 /* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
468 const char FLT_CHARS[] = "fFdDxX";
469
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars[256];
472 static char register_chars[256];
473 static char operand_chars[256];
474 static char identifier_chars[256];
475 static char digit_chars[256];
476
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
484
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack[32];
493 static char *save_stack_p;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
499 /* The instruction we're assembling. */
500 static i386_insn i;
501
502 /* Possible templates for current insn. */
503 static const templates *current_templates;
504
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
508
509 /* Current operand we are working on. */
510 static int this_operand = -1;
511
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515 enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520 static enum flag_code flag_code;
521 static unsigned int object_64bit;
522 static unsigned int disallow_64bit_reloc;
523 static int use_rela_relocations = 0;
524
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
529 /* The ELF ABI to use. */
530 enum x86_elf_abi
531 {
532 I386_ABI,
533 X86_64_ABI,
534 X86_64_X32_ABI
535 };
536
537 static enum x86_elf_abi x86_elf_abi = I386_ABI;
538 #endif
539
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj = 0;
543 #endif
544
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared = 0;
548 #endif
549
550 /* 1 for intel syntax,
551 0 if att syntax. */
552 static int intel_syntax = 0;
553
554 /* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556 static int intel64;
557
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic = !SYSV386_COMPAT;
561
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc = OLDGCC_COMPAT;
564
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
567
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
570
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574 static int add_bnd_prefix = 0;
575
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
578
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
582
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
586
587 /* 1 if the assembler should generate relax relocations. */
588
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
592 static enum check_kind
593 {
594 check_none = 0,
595 check_warning,
596 check_error
597 }
598 sse_check, operand_check = check_warning;
599
600 /* Register prefix used for error message. */
601 static const char *register_prefix = "%";
602
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size = '\0';
607
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code = 1;
610
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings = 0;
613
614 /* CPU name. */
615 static const char *cpu_arch_name = NULL;
616 static char *cpu_sub_arch_name = NULL;
617
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set = 0;
623
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
626
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags;
629
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
632
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags;
635
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion = 0;
639
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx;
642
643 /* Encode scalar AVX instructions with specific vector length. */
644 static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
651 static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658 /* Encode EVEX WIG instructions with specific evex.w. */
659 static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig = rne;
667
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS *GOT_symbol;
670
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column;
673
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment;
676
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
681
682 /* Types. */
683 #define UNCOND_JUMP 0
684 #define COND_JUMP 1
685 #define COND_JUMP86 2
686
687 /* Sizes. */
688 #define CODE16 1
689 #define SMALL 0
690 #define SMALL16 (SMALL | CODE16)
691 #define BIG 2
692 #define BIG16 (BIG | CODE16)
693
694 #ifndef INLINE
695 #ifdef __GNUC__
696 #define INLINE __inline__
697 #else
698 #define INLINE
699 #endif
700 #endif
701
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
708
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717 const relax_typeS md_relax_table[] =
718 {
719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
724
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
730 {0, 0, 4, 0},
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
733 {0, 0, 2, 0},
734
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
754 };
755
756 static const arch_entry cpu_arch[] =
757 {
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
761 CPU_GENERIC32_FLAGS, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
763 CPU_GENERIC64_FLAGS, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
765 CPU_NONE_FLAGS, 0 },
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
767 CPU_I186_FLAGS, 0 },
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
769 CPU_I286_FLAGS, 0 },
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
771 CPU_I386_FLAGS, 0 },
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
773 CPU_I486_FLAGS, 0 },
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
775 CPU_I586_FLAGS, 0 },
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
777 CPU_I686_FLAGS, 0 },
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
779 CPU_I586_FLAGS, 0 },
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
781 CPU_PENTIUMPRO_FLAGS, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
783 CPU_P2_FLAGS, 0 },
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
785 CPU_P3_FLAGS, 0 },
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
787 CPU_P4_FLAGS, 0 },
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
789 CPU_CORE_FLAGS, 0 },
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
791 CPU_NOCONA_FLAGS, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
793 CPU_CORE_FLAGS, 1 },
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
795 CPU_CORE_FLAGS, 0 },
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
797 CPU_CORE2_FLAGS, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
799 CPU_CORE2_FLAGS, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
801 CPU_COREI7_FLAGS, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
803 CPU_L1OM_FLAGS, 0 },
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
805 CPU_K1OM_FLAGS, 0 },
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
807 CPU_IAMCU_FLAGS, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
809 CPU_K6_FLAGS, 0 },
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
811 CPU_K6_2_FLAGS, 0 },
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
813 CPU_ATHLON_FLAGS, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
815 CPU_K8_FLAGS, 1 },
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
817 CPU_K8_FLAGS, 0 },
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
819 CPU_K8_FLAGS, 0 },
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
821 CPU_AMDFAM10_FLAGS, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
823 CPU_BDVER1_FLAGS, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
825 CPU_BDVER2_FLAGS, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
827 CPU_BDVER3_FLAGS, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
829 CPU_BDVER4_FLAGS, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
831 CPU_ZNVER1_FLAGS, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
833 CPU_BTVER1_FLAGS, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
835 CPU_BTVER2_FLAGS, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
837 CPU_8087_FLAGS, 0 },
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
839 CPU_287_FLAGS, 0 },
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
841 CPU_387_FLAGS, 0 },
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
845 CPU_MMX_FLAGS, 0 },
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
847 CPU_SSE_FLAGS, 0 },
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
849 CPU_SSE2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
851 CPU_SSE3_FLAGS, 0 },
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
853 CPU_SSSE3_FLAGS, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
855 CPU_SSE4_1_FLAGS, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
857 CPU_SSE4_2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
859 CPU_SSE4_2_FLAGS, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
861 CPU_AVX_FLAGS, 0 },
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
863 CPU_AVX2_FLAGS, 0 },
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
865 CPU_AVX512F_FLAGS, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
867 CPU_AVX512CD_FLAGS, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
869 CPU_AVX512ER_FLAGS, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
871 CPU_AVX512PF_FLAGS, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
873 CPU_AVX512DQ_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
875 CPU_AVX512BW_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
877 CPU_AVX512VL_FLAGS, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
879 CPU_VMX_FLAGS, 0 },
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
881 CPU_VMFUNC_FLAGS, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
883 CPU_SMX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
885 CPU_XSAVE_FLAGS, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
887 CPU_XSAVEOPT_FLAGS, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
889 CPU_XSAVEC_FLAGS, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
891 CPU_XSAVES_FLAGS, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
893 CPU_AES_FLAGS, 0 },
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
895 CPU_PCLMUL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
897 CPU_PCLMUL_FLAGS, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
899 CPU_FSGSBASE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
901 CPU_RDRND_FLAGS, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
903 CPU_F16C_FLAGS, 0 },
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
905 CPU_BMI2_FLAGS, 0 },
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
907 CPU_FMA_FLAGS, 0 },
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
909 CPU_FMA4_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
911 CPU_XOP_FLAGS, 0 },
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
913 CPU_LWP_FLAGS, 0 },
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
915 CPU_MOVBE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
917 CPU_CX16_FLAGS, 0 },
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
919 CPU_EPT_FLAGS, 0 },
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
921 CPU_LZCNT_FLAGS, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
923 CPU_HLE_FLAGS, 0 },
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
925 CPU_RTM_FLAGS, 0 },
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
927 CPU_INVPCID_FLAGS, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
929 CPU_CLFLUSH_FLAGS, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
931 CPU_NOP_FLAGS, 0 },
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
933 CPU_SYSCALL_FLAGS, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
935 CPU_RDTSCP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
937 CPU_3DNOW_FLAGS, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
939 CPU_3DNOWA_FLAGS, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
941 CPU_PADLOCK_FLAGS, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
943 CPU_SVME_FLAGS, 1 },
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
945 CPU_SVME_FLAGS, 0 },
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
947 CPU_SSE4A_FLAGS, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
949 CPU_ABM_FLAGS, 0 },
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
951 CPU_BMI_FLAGS, 0 },
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
953 CPU_TBM_FLAGS, 0 },
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
955 CPU_ADX_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
957 CPU_RDSEED_FLAGS, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
959 CPU_PRFCHW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
961 CPU_SMAP_FLAGS, 0 },
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
963 CPU_MPX_FLAGS, 0 },
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
965 CPU_SHA_FLAGS, 0 },
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
967 CPU_CLFLUSHOPT_FLAGS, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
969 CPU_PREFETCHWT1_FLAGS, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
971 CPU_SE1_FLAGS, 0 },
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
973 CPU_CLWB_FLAGS, 0 },
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
975 CPU_AVX512IFMA_FLAGS, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
977 CPU_AVX512VBMI_FLAGS, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
991 CPU_CLZERO_FLAGS, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
993 CPU_MWAITX_FLAGS, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
995 CPU_OSPKE_FLAGS, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
997 CPU_RDPID_FLAGS, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1001 CPU_CET_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1003 CPU_GFNI_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1005 CPU_VAES_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1007 CPU_VPCLMULQDQ_FLAGS, 0 },
1008 };
1009
1010 static const noarch_entry cpu_noarch[] =
1011 {
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1041 };
1042
1043 #ifdef I386COFF
1044 /* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1046
1047 static symbolS *
1048 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1049 {
1050 addressT align = 0;
1051
1052 SKIP_WHITESPACE ();
1053
1054 if (needs_align
1055 && *input_line_pointer == ',')
1056 {
1057 align = parse_align (needs_align - 1);
1058
1059 if (align == (addressT) -1)
1060 return NULL;
1061 }
1062 else
1063 {
1064 if (size >= 8)
1065 align = 3;
1066 else if (size >= 4)
1067 align = 2;
1068 else if (size >= 2)
1069 align = 1;
1070 else
1071 align = 0;
1072 }
1073
1074 bss_alloc (symbolP, size, align);
1075 return symbolP;
1076 }
1077
1078 static void
1079 pe_lcomm (int needs_align)
1080 {
1081 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1082 }
1083 #endif
1084
1085 const pseudo_typeS md_pseudo_table[] =
1086 {
1087 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes, 0},
1089 #else
1090 {"align", s_align_ptwo, 0},
1091 #endif
1092 {"arch", set_cpu_arch, 0},
1093 #ifndef I386COFF
1094 {"bss", s_bss, 0},
1095 #else
1096 {"lcomm", pe_lcomm, 1},
1097 #endif
1098 {"ffloat", float_cons, 'f'},
1099 {"dfloat", float_cons, 'd'},
1100 {"tfloat", float_cons, 'x'},
1101 {"value", cons, 2},
1102 {"slong", signed_cons, 4},
1103 {"noopt", s_ignore, 0},
1104 {"optim", s_ignore, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1106 {"code16", set_code_flag, CODE_16BIT},
1107 {"code32", set_code_flag, CODE_32BIT},
1108 #ifdef BFD64
1109 {"code64", set_code_flag, CODE_64BIT},
1110 #endif
1111 {"intel_syntax", set_intel_syntax, 1},
1112 {"att_syntax", set_intel_syntax, 0},
1113 {"intel_mnemonic", set_intel_mnemonic, 1},
1114 {"att_mnemonic", set_intel_mnemonic, 0},
1115 {"allow_index_reg", set_allow_index_reg, 1},
1116 {"disallow_index_reg", set_allow_index_reg, 0},
1117 {"sse_check", set_check, 0},
1118 {"operand_check", set_check, 1},
1119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common, 0},
1121 #else
1122 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1123 {"loc", dwarf2_directive_loc, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1125 #endif
1126 #ifdef TE_PE
1127 {"secrel32", pe_directive_secrel, 0},
1128 #endif
1129 {0, 0, 0}
1130 };
1131
1132 /* For interface with expression (). */
1133 extern char *input_line_pointer;
1134
1135 /* Hash table for instruction mnemonic lookup. */
1136 static struct hash_control *op_hash;
1137
1138 /* Hash table for register lookup. */
1139 static struct hash_control *reg_hash;
1140 \f
1141 void
1142 i386_align_code (fragS *fragP, int count)
1143 {
1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
1147 static const unsigned char f32_1[] =
1148 {0x90}; /* nop */
1149 static const unsigned char f32_2[] =
1150 {0x66,0x90}; /* xchg %ax,%ax */
1151 static const unsigned char f32_3[] =
1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1153 static const unsigned char f32_4[] =
1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1155 static const unsigned char f32_5[] =
1156 {0x90, /* nop */
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1158 static const unsigned char f32_6[] =
1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1160 static const unsigned char f32_7[] =
1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1162 static const unsigned char f32_8[] =
1163 {0x90, /* nop */
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1165 static const unsigned char f32_9[] =
1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1168 static const unsigned char f32_10[] =
1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1171 static const unsigned char f32_11[] =
1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1174 static const unsigned char f32_12[] =
1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1177 static const unsigned char f32_13[] =
1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1180 static const unsigned char f32_14[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1183 static const unsigned char f16_3[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1185 static const unsigned char f16_4[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1187 static const unsigned char f16_5[] =
1188 {0x90, /* nop */
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1190 static const unsigned char f16_6[] =
1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1193 static const unsigned char f16_7[] =
1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1196 static const unsigned char f16_8[] =
1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1199 static const unsigned char jump_31[] =
1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1204 static const unsigned char *const f32_patt[] = {
1205 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1206 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1207 };
1208 static const unsigned char *const f16_patt[] = {
1209 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1210 };
1211 /* nopl (%[re]ax) */
1212 static const unsigned char alt_3[] =
1213 {0x0f,0x1f,0x00};
1214 /* nopl 0(%[re]ax) */
1215 static const unsigned char alt_4[] =
1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_5[] =
1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
1221 static const unsigned char alt_6[] =
1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
1224 static const unsigned char alt_7[] =
1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_8[] =
1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_9[] =
1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1233 static const unsigned char alt_10[] =
1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 static const unsigned char *const alt_patt[] = {
1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1237 alt_9, alt_10
1238 };
1239
1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1242 return;
1243
1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
1246
1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
1249 2. For the rest, alt_patt will be used.
1250
1251 When -mtune= isn't used, alt_patt will be used if
1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1253 be used.
1254
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1257
1258 if (flag_code == CODE_16BIT)
1259 {
1260 if (count > 8)
1261 {
1262 memcpy (fragP->fr_literal + fragP->fr_fix,
1263 jump_31, count);
1264 /* Adjust jump offset. */
1265 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1266 }
1267 else
1268 memcpy (fragP->fr_literal + fragP->fr_fix,
1269 f16_patt[count - 1], count);
1270 }
1271 else
1272 {
1273 const unsigned char *const *patt = NULL;
1274
1275 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1276 {
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune)
1279 {
1280 case PROCESSOR_UNKNOWN:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
1282 optimize with nops. */
1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1284 patt = alt_patt;
1285 else
1286 patt = f32_patt;
1287 break;
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
1291 case PROCESSOR_CORE2:
1292 case PROCESSOR_COREI7:
1293 case PROCESSOR_L1OM:
1294 case PROCESSOR_K1OM:
1295 case PROCESSOR_GENERIC64:
1296 case PROCESSOR_K6:
1297 case PROCESSOR_ATHLON:
1298 case PROCESSOR_K8:
1299 case PROCESSOR_AMDFAM10:
1300 case PROCESSOR_BD:
1301 case PROCESSOR_ZNVER:
1302 case PROCESSOR_BT:
1303 patt = alt_patt;
1304 break;
1305 case PROCESSOR_I386:
1306 case PROCESSOR_I486:
1307 case PROCESSOR_PENTIUM:
1308 case PROCESSOR_PENTIUMPRO:
1309 case PROCESSOR_IAMCU:
1310 case PROCESSOR_GENERIC32:
1311 patt = f32_patt;
1312 break;
1313 }
1314 }
1315 else
1316 {
1317 switch (fragP->tc_frag_data.tune)
1318 {
1319 case PROCESSOR_UNKNOWN:
1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1321 PROCESSOR_UNKNOWN. */
1322 abort ();
1323 break;
1324
1325 case PROCESSOR_I386:
1326 case PROCESSOR_I486:
1327 case PROCESSOR_PENTIUM:
1328 case PROCESSOR_IAMCU:
1329 case PROCESSOR_K6:
1330 case PROCESSOR_ATHLON:
1331 case PROCESSOR_K8:
1332 case PROCESSOR_AMDFAM10:
1333 case PROCESSOR_BD:
1334 case PROCESSOR_ZNVER:
1335 case PROCESSOR_BT:
1336 case PROCESSOR_GENERIC32:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
1338 with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1340 patt = alt_patt;
1341 else
1342 patt = f32_patt;
1343 break;
1344 case PROCESSOR_PENTIUMPRO:
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
1348 case PROCESSOR_CORE2:
1349 case PROCESSOR_COREI7:
1350 case PROCESSOR_L1OM:
1351 case PROCESSOR_K1OM:
1352 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1353 patt = alt_patt;
1354 else
1355 patt = f32_patt;
1356 break;
1357 case PROCESSOR_GENERIC64:
1358 patt = alt_patt;
1359 break;
1360 }
1361 }
1362
1363 if (patt == f32_patt)
1364 {
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
1367 its offset. */
1368 int limit;
1369
1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code == CODE_64BIT
1372 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1373 limit = 3;
1374 else
1375 limit = 15;
1376 if (count < limit)
1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt[count - 1], count);
1379 else
1380 {
1381 memcpy (fragP->fr_literal + fragP->fr_fix,
1382 jump_31, count);
1383 /* Adjust jump offset. */
1384 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1385 }
1386 }
1387 else
1388 {
1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
1391 we have to break it into smaller pieces. */
1392 int padding = count;
1393 while (padding > 10)
1394 {
1395 padding -= 10;
1396 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1397 patt [9], 10);
1398 }
1399
1400 if (padding)
1401 memcpy (fragP->fr_literal + fragP->fr_fix,
1402 patt [padding - 1], padding);
1403 }
1404 }
1405 fragP->fr_var = count;
1406 }
1407
1408 static INLINE int
1409 operand_type_all_zero (const union i386_operand_type *x)
1410 {
1411 switch (ARRAY_SIZE(x->array))
1412 {
1413 case 3:
1414 if (x->array[2])
1415 return 0;
1416 /* Fall through. */
1417 case 2:
1418 if (x->array[1])
1419 return 0;
1420 /* Fall through. */
1421 case 1:
1422 return !x->array[0];
1423 default:
1424 abort ();
1425 }
1426 }
1427
1428 static INLINE void
1429 operand_type_set (union i386_operand_type *x, unsigned int v)
1430 {
1431 switch (ARRAY_SIZE(x->array))
1432 {
1433 case 3:
1434 x->array[2] = v;
1435 /* Fall through. */
1436 case 2:
1437 x->array[1] = v;
1438 /* Fall through. */
1439 case 1:
1440 x->array[0] = v;
1441 /* Fall through. */
1442 break;
1443 default:
1444 abort ();
1445 }
1446 }
1447
1448 static INLINE int
1449 operand_type_equal (const union i386_operand_type *x,
1450 const union i386_operand_type *y)
1451 {
1452 switch (ARRAY_SIZE(x->array))
1453 {
1454 case 3:
1455 if (x->array[2] != y->array[2])
1456 return 0;
1457 /* Fall through. */
1458 case 2:
1459 if (x->array[1] != y->array[1])
1460 return 0;
1461 /* Fall through. */
1462 case 1:
1463 return x->array[0] == y->array[0];
1464 break;
1465 default:
1466 abort ();
1467 }
1468 }
1469
1470 static INLINE int
1471 cpu_flags_all_zero (const union i386_cpu_flags *x)
1472 {
1473 switch (ARRAY_SIZE(x->array))
1474 {
1475 case 4:
1476 if (x->array[3])
1477 return 0;
1478 /* Fall through. */
1479 case 3:
1480 if (x->array[2])
1481 return 0;
1482 /* Fall through. */
1483 case 2:
1484 if (x->array[1])
1485 return 0;
1486 /* Fall through. */
1487 case 1:
1488 return !x->array[0];
1489 default:
1490 abort ();
1491 }
1492 }
1493
1494 static INLINE int
1495 cpu_flags_equal (const union i386_cpu_flags *x,
1496 const union i386_cpu_flags *y)
1497 {
1498 switch (ARRAY_SIZE(x->array))
1499 {
1500 case 4:
1501 if (x->array[3] != y->array[3])
1502 return 0;
1503 /* Fall through. */
1504 case 3:
1505 if (x->array[2] != y->array[2])
1506 return 0;
1507 /* Fall through. */
1508 case 2:
1509 if (x->array[1] != y->array[1])
1510 return 0;
1511 /* Fall through. */
1512 case 1:
1513 return x->array[0] == y->array[0];
1514 break;
1515 default:
1516 abort ();
1517 }
1518 }
1519
1520 static INLINE int
1521 cpu_flags_check_cpu64 (i386_cpu_flags f)
1522 {
1523 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1524 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1525 }
1526
1527 static INLINE i386_cpu_flags
1528 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1529 {
1530 switch (ARRAY_SIZE (x.array))
1531 {
1532 case 4:
1533 x.array [3] &= y.array [3];
1534 /* Fall through. */
1535 case 3:
1536 x.array [2] &= y.array [2];
1537 /* Fall through. */
1538 case 2:
1539 x.array [1] &= y.array [1];
1540 /* Fall through. */
1541 case 1:
1542 x.array [0] &= y.array [0];
1543 break;
1544 default:
1545 abort ();
1546 }
1547 return x;
1548 }
1549
1550 static INLINE i386_cpu_flags
1551 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1552 {
1553 switch (ARRAY_SIZE (x.array))
1554 {
1555 case 4:
1556 x.array [3] |= y.array [3];
1557 /* Fall through. */
1558 case 3:
1559 x.array [2] |= y.array [2];
1560 /* Fall through. */
1561 case 2:
1562 x.array [1] |= y.array [1];
1563 /* Fall through. */
1564 case 1:
1565 x.array [0] |= y.array [0];
1566 break;
1567 default:
1568 abort ();
1569 }
1570 return x;
1571 }
1572
1573 static INLINE i386_cpu_flags
1574 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1575 {
1576 switch (ARRAY_SIZE (x.array))
1577 {
1578 case 4:
1579 x.array [3] &= ~y.array [3];
1580 /* Fall through. */
1581 case 3:
1582 x.array [2] &= ~y.array [2];
1583 /* Fall through. */
1584 case 2:
1585 x.array [1] &= ~y.array [1];
1586 /* Fall through. */
1587 case 1:
1588 x.array [0] &= ~y.array [0];
1589 break;
1590 default:
1591 abort ();
1592 }
1593 return x;
1594 }
1595
1596 #define CPU_FLAGS_ARCH_MATCH 0x1
1597 #define CPU_FLAGS_64BIT_MATCH 0x2
1598 #define CPU_FLAGS_AES_MATCH 0x4
1599 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1600 #define CPU_FLAGS_AVX_MATCH 0x10
1601
1602 #define CPU_FLAGS_32BIT_MATCH \
1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1605 #define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1607
1608 /* Return CPU flags match bits. */
1609
1610 static int
1611 cpu_flags_match (const insn_template *t)
1612 {
1613 i386_cpu_flags x = t->cpu_flags;
1614 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1615
1616 x.bitfield.cpu64 = 0;
1617 x.bitfield.cpuno64 = 0;
1618
1619 if (cpu_flags_all_zero (&x))
1620 {
1621 /* This instruction is available on all archs. */
1622 match |= CPU_FLAGS_32BIT_MATCH;
1623 }
1624 else
1625 {
1626 /* This instruction is available only on some archs. */
1627 i386_cpu_flags cpu = cpu_arch_flags;
1628
1629 cpu = cpu_flags_and (x, cpu);
1630 if (!cpu_flags_all_zero (&cpu))
1631 {
1632 if (x.bitfield.cpuavx)
1633 {
1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1635 if (cpu.bitfield.cpuavx)
1636 {
1637 /* Check SSE2AVX. */
1638 if (!t->opcode_modifier.sse2avx|| sse2avx)
1639 {
1640 match |= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH);
1642 /* Check AES. */
1643 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1644 match |= CPU_FLAGS_AES_MATCH;
1645 /* Check PCLMUL. */
1646 if (!x.bitfield.cpupclmul
1647 || cpu.bitfield.cpupclmul)
1648 match |= CPU_FLAGS_PCLMUL_MATCH;
1649 }
1650 }
1651 else
1652 match |= CPU_FLAGS_ARCH_MATCH;
1653 }
1654 else if (x.bitfield.cpuavx512vl)
1655 {
1656 /* Match AVX512VL. */
1657 if (cpu.bitfield.cpuavx512vl)
1658 {
1659 /* Need another match. */
1660 cpu.bitfield.cpuavx512vl = 0;
1661 if (!cpu_flags_all_zero (&cpu))
1662 match |= CPU_FLAGS_32BIT_MATCH;
1663 else
1664 match |= CPU_FLAGS_ARCH_MATCH;
1665 }
1666 else
1667 match |= CPU_FLAGS_ARCH_MATCH;
1668 }
1669 else
1670 match |= CPU_FLAGS_32BIT_MATCH;
1671 }
1672 }
1673 return match;
1674 }
1675
1676 static INLINE i386_operand_type
1677 operand_type_and (i386_operand_type x, i386_operand_type y)
1678 {
1679 switch (ARRAY_SIZE (x.array))
1680 {
1681 case 3:
1682 x.array [2] &= y.array [2];
1683 /* Fall through. */
1684 case 2:
1685 x.array [1] &= y.array [1];
1686 /* Fall through. */
1687 case 1:
1688 x.array [0] &= y.array [0];
1689 break;
1690 default:
1691 abort ();
1692 }
1693 return x;
1694 }
1695
1696 static INLINE i386_operand_type
1697 operand_type_or (i386_operand_type x, i386_operand_type y)
1698 {
1699 switch (ARRAY_SIZE (x.array))
1700 {
1701 case 3:
1702 x.array [2] |= y.array [2];
1703 /* Fall through. */
1704 case 2:
1705 x.array [1] |= y.array [1];
1706 /* Fall through. */
1707 case 1:
1708 x.array [0] |= y.array [0];
1709 break;
1710 default:
1711 abort ();
1712 }
1713 return x;
1714 }
1715
1716 static INLINE i386_operand_type
1717 operand_type_xor (i386_operand_type x, i386_operand_type y)
1718 {
1719 switch (ARRAY_SIZE (x.array))
1720 {
1721 case 3:
1722 x.array [2] ^= y.array [2];
1723 /* Fall through. */
1724 case 2:
1725 x.array [1] ^= y.array [1];
1726 /* Fall through. */
1727 case 1:
1728 x.array [0] ^= y.array [0];
1729 break;
1730 default:
1731 abort ();
1732 }
1733 return x;
1734 }
1735
1736 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1737 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1738 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1739 static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG;
1741 static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG;
1743 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1744 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1745 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1746 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1747 static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP;
1749 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1750 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1751 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1752 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1753 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1754 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1755 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1756 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1757 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1758 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1759 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1760 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1761 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1762 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1763
1764 enum operand_type
1765 {
1766 reg,
1767 imm,
1768 disp,
1769 anymem
1770 };
1771
1772 static INLINE int
1773 operand_type_check (i386_operand_type t, enum operand_type c)
1774 {
1775 switch (c)
1776 {
1777 case reg:
1778 return t.bitfield.reg;
1779
1780 case imm:
1781 return (t.bitfield.imm8
1782 || t.bitfield.imm8s
1783 || t.bitfield.imm16
1784 || t.bitfield.imm32
1785 || t.bitfield.imm32s
1786 || t.bitfield.imm64);
1787
1788 case disp:
1789 return (t.bitfield.disp8
1790 || t.bitfield.disp16
1791 || t.bitfield.disp32
1792 || t.bitfield.disp32s
1793 || t.bitfield.disp64);
1794
1795 case anymem:
1796 return (t.bitfield.disp8
1797 || t.bitfield.disp16
1798 || t.bitfield.disp32
1799 || t.bitfield.disp32s
1800 || t.bitfield.disp64
1801 || t.bitfield.baseindex);
1802
1803 default:
1804 abort ();
1805 }
1806
1807 return 0;
1808 }
1809
1810 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1811 operand J for instruction template T. */
1812
1813 static INLINE int
1814 match_reg_size (const insn_template *t, unsigned int j)
1815 {
1816 return !((i.types[j].bitfield.byte
1817 && !t->operand_types[j].bitfield.byte)
1818 || (i.types[j].bitfield.word
1819 && !t->operand_types[j].bitfield.word)
1820 || (i.types[j].bitfield.dword
1821 && !t->operand_types[j].bitfield.dword)
1822 || (i.types[j].bitfield.qword
1823 && !t->operand_types[j].bitfield.qword)
1824 || (i.types[j].bitfield.tbyte
1825 && !t->operand_types[j].bitfield.tbyte));
1826 }
1827
1828 /* Return 1 if there is no conflict in any size on operand J for
1829 instruction template T. */
1830
1831 static INLINE int
1832 match_mem_size (const insn_template *t, unsigned int j)
1833 {
1834 return (match_reg_size (t, j)
1835 && !((i.types[j].bitfield.unspecified
1836 && !i.broadcast
1837 && !t->operand_types[j].bitfield.unspecified)
1838 || (i.types[j].bitfield.fword
1839 && !t->operand_types[j].bitfield.fword)
1840 || (i.types[j].bitfield.xmmword
1841 && !t->operand_types[j].bitfield.xmmword)
1842 || (i.types[j].bitfield.ymmword
1843 && !t->operand_types[j].bitfield.ymmword)
1844 || (i.types[j].bitfield.zmmword
1845 && !t->operand_types[j].bitfield.zmmword)));
1846 }
1847
1848 /* Return 1 if there is no size conflict on any operands for
1849 instruction template T. */
1850
1851 static INLINE int
1852 operand_size_match (const insn_template *t)
1853 {
1854 unsigned int j;
1855 int match = 1;
1856
1857 /* Don't check jump instructions. */
1858 if (t->opcode_modifier.jump
1859 || t->opcode_modifier.jumpbyte
1860 || t->opcode_modifier.jumpdword
1861 || t->opcode_modifier.jumpintersegment)
1862 return match;
1863
1864 /* Check memory and accumulator operand size. */
1865 for (j = 0; j < i.operands; j++)
1866 {
1867 if (!i.types[j].bitfield.reg && t->operand_types[j].bitfield.anysize)
1868 continue;
1869
1870 if ((t->operand_types[j].bitfield.reg
1871 || t->operand_types[j].bitfield.acc)
1872 && !match_reg_size (t, j))
1873 {
1874 match = 0;
1875 break;
1876 }
1877
1878 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1879 {
1880 match = 0;
1881 break;
1882 }
1883 }
1884
1885 if (match)
1886 return match;
1887 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1888 {
1889 mismatch:
1890 i.error = operand_size_mismatch;
1891 return 0;
1892 }
1893
1894 /* Check reverse. */
1895 gas_assert (i.operands == 2);
1896
1897 match = 1;
1898 for (j = 0; j < 2; j++)
1899 {
1900 if ((t->operand_types[j].bitfield.reg
1901 || t->operand_types[j].bitfield.acc)
1902 && !match_reg_size (t, j ? 0 : 1))
1903 goto mismatch;
1904
1905 if (i.types[j].bitfield.mem
1906 && !match_mem_size (t, j ? 0 : 1))
1907 goto mismatch;
1908 }
1909
1910 return match;
1911 }
1912
1913 static INLINE int
1914 operand_type_match (i386_operand_type overlap,
1915 i386_operand_type given)
1916 {
1917 i386_operand_type temp = overlap;
1918
1919 temp.bitfield.jumpabsolute = 0;
1920 temp.bitfield.unspecified = 0;
1921 temp.bitfield.byte = 0;
1922 temp.bitfield.word = 0;
1923 temp.bitfield.dword = 0;
1924 temp.bitfield.fword = 0;
1925 temp.bitfield.qword = 0;
1926 temp.bitfield.tbyte = 0;
1927 temp.bitfield.xmmword = 0;
1928 temp.bitfield.ymmword = 0;
1929 temp.bitfield.zmmword = 0;
1930 if (operand_type_all_zero (&temp))
1931 goto mismatch;
1932
1933 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1934 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1935 return 1;
1936
1937 mismatch:
1938 i.error = operand_type_mismatch;
1939 return 0;
1940 }
1941
1942 /* If given types g0 and g1 are registers they must be of the same type
1943 unless the expected operand type register overlap is null. */
1944
1945 static INLINE int
1946 operand_type_register_match (i386_operand_type g0,
1947 i386_operand_type t0,
1948 i386_operand_type g1,
1949 i386_operand_type t1)
1950 {
1951 if (!operand_type_check (g0, reg))
1952 return 1;
1953
1954 if (!operand_type_check (g1, reg))
1955 return 1;
1956
1957 if (g0.bitfield.byte == g1.bitfield.byte
1958 && g0.bitfield.word == g1.bitfield.word
1959 && g0.bitfield.dword == g1.bitfield.dword
1960 && g0.bitfield.qword == g1.bitfield.qword)
1961 return 1;
1962
1963 if (!(t0.bitfield.byte & t1.bitfield.byte)
1964 && !(t0.bitfield.word & t1.bitfield.word)
1965 && !(t0.bitfield.dword & t1.bitfield.dword)
1966 && !(t0.bitfield.qword & t1.bitfield.qword))
1967 return 1;
1968
1969 i.error = register_type_mismatch;
1970
1971 return 0;
1972 }
1973
1974 static INLINE unsigned int
1975 register_number (const reg_entry *r)
1976 {
1977 unsigned int nr = r->reg_num;
1978
1979 if (r->reg_flags & RegRex)
1980 nr += 8;
1981
1982 if (r->reg_flags & RegVRex)
1983 nr += 16;
1984
1985 return nr;
1986 }
1987
1988 static INLINE unsigned int
1989 mode_from_disp_size (i386_operand_type t)
1990 {
1991 if (t.bitfield.disp8)
1992 return 1;
1993 else if (t.bitfield.disp16
1994 || t.bitfield.disp32
1995 || t.bitfield.disp32s)
1996 return 2;
1997 else
1998 return 0;
1999 }
2000
2001 static INLINE int
2002 fits_in_signed_byte (addressT num)
2003 {
2004 return num + 0x80 <= 0xff;
2005 }
2006
2007 static INLINE int
2008 fits_in_unsigned_byte (addressT num)
2009 {
2010 return num <= 0xff;
2011 }
2012
2013 static INLINE int
2014 fits_in_unsigned_word (addressT num)
2015 {
2016 return num <= 0xffff;
2017 }
2018
2019 static INLINE int
2020 fits_in_signed_word (addressT num)
2021 {
2022 return num + 0x8000 <= 0xffff;
2023 }
2024
2025 static INLINE int
2026 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2027 {
2028 #ifndef BFD64
2029 return 1;
2030 #else
2031 return num + 0x80000000 <= 0xffffffff;
2032 #endif
2033 } /* fits_in_signed_long() */
2034
2035 static INLINE int
2036 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2037 {
2038 #ifndef BFD64
2039 return 1;
2040 #else
2041 return num <= 0xffffffff;
2042 #endif
2043 } /* fits_in_unsigned_long() */
2044
2045 static INLINE int
2046 fits_in_disp8 (offsetT num)
2047 {
2048 int shift = i.memshift;
2049 unsigned int mask;
2050
2051 if (shift == -1)
2052 abort ();
2053
2054 mask = (1 << shift) - 1;
2055
2056 /* Return 0 if NUM isn't properly aligned. */
2057 if ((num & mask))
2058 return 0;
2059
2060 /* Check if NUM will fit in 8bit after shift. */
2061 return fits_in_signed_byte (num >> shift);
2062 }
2063
2064 static INLINE int
2065 fits_in_imm4 (offsetT num)
2066 {
2067 return (num & 0xf) == num;
2068 }
2069
2070 static i386_operand_type
2071 smallest_imm_type (offsetT num)
2072 {
2073 i386_operand_type t;
2074
2075 operand_type_set (&t, 0);
2076 t.bitfield.imm64 = 1;
2077
2078 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2079 {
2080 /* This code is disabled on the 486 because all the Imm1 forms
2081 in the opcode table are slower on the i486. They're the
2082 versions with the implicitly specified single-position
2083 displacement, which has another syntax if you really want to
2084 use that form. */
2085 t.bitfield.imm1 = 1;
2086 t.bitfield.imm8 = 1;
2087 t.bitfield.imm8s = 1;
2088 t.bitfield.imm16 = 1;
2089 t.bitfield.imm32 = 1;
2090 t.bitfield.imm32s = 1;
2091 }
2092 else if (fits_in_signed_byte (num))
2093 {
2094 t.bitfield.imm8 = 1;
2095 t.bitfield.imm8s = 1;
2096 t.bitfield.imm16 = 1;
2097 t.bitfield.imm32 = 1;
2098 t.bitfield.imm32s = 1;
2099 }
2100 else if (fits_in_unsigned_byte (num))
2101 {
2102 t.bitfield.imm8 = 1;
2103 t.bitfield.imm16 = 1;
2104 t.bitfield.imm32 = 1;
2105 t.bitfield.imm32s = 1;
2106 }
2107 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2108 {
2109 t.bitfield.imm16 = 1;
2110 t.bitfield.imm32 = 1;
2111 t.bitfield.imm32s = 1;
2112 }
2113 else if (fits_in_signed_long (num))
2114 {
2115 t.bitfield.imm32 = 1;
2116 t.bitfield.imm32s = 1;
2117 }
2118 else if (fits_in_unsigned_long (num))
2119 t.bitfield.imm32 = 1;
2120
2121 return t;
2122 }
2123
2124 static offsetT
2125 offset_in_range (offsetT val, int size)
2126 {
2127 addressT mask;
2128
2129 switch (size)
2130 {
2131 case 1: mask = ((addressT) 1 << 8) - 1; break;
2132 case 2: mask = ((addressT) 1 << 16) - 1; break;
2133 case 4: mask = ((addressT) 2 << 31) - 1; break;
2134 #ifdef BFD64
2135 case 8: mask = ((addressT) 2 << 63) - 1; break;
2136 #endif
2137 default: abort ();
2138 }
2139
2140 #ifdef BFD64
2141 /* If BFD64, sign extend val for 32bit address mode. */
2142 if (flag_code != CODE_64BIT
2143 || i.prefix[ADDR_PREFIX])
2144 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2145 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2146 #endif
2147
2148 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2149 {
2150 char buf1[40], buf2[40];
2151
2152 sprint_value (buf1, val);
2153 sprint_value (buf2, val & mask);
2154 as_warn (_("%s shortened to %s"), buf1, buf2);
2155 }
2156 return val & mask;
2157 }
2158
2159 enum PREFIX_GROUP
2160 {
2161 PREFIX_EXIST = 0,
2162 PREFIX_LOCK,
2163 PREFIX_REP,
2164 PREFIX_DS,
2165 PREFIX_OTHER
2166 };
2167
2168 /* Returns
2169 a. PREFIX_EXIST if attempting to add a prefix where one from the
2170 same class already exists.
2171 b. PREFIX_LOCK if lock prefix is added.
2172 c. PREFIX_REP if rep/repne prefix is added.
2173 d. PREFIX_DS if ds prefix is added.
2174 e. PREFIX_OTHER if other prefix is added.
2175 */
2176
2177 static enum PREFIX_GROUP
2178 add_prefix (unsigned int prefix)
2179 {
2180 enum PREFIX_GROUP ret = PREFIX_OTHER;
2181 unsigned int q;
2182
2183 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2184 && flag_code == CODE_64BIT)
2185 {
2186 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2187 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2188 && (prefix & (REX_R | REX_X | REX_B))))
2189 ret = PREFIX_EXIST;
2190 q = REX_PREFIX;
2191 }
2192 else
2193 {
2194 switch (prefix)
2195 {
2196 default:
2197 abort ();
2198
2199 case DS_PREFIX_OPCODE:
2200 ret = PREFIX_DS;
2201 /* Fall through. */
2202 case CS_PREFIX_OPCODE:
2203 case ES_PREFIX_OPCODE:
2204 case FS_PREFIX_OPCODE:
2205 case GS_PREFIX_OPCODE:
2206 case SS_PREFIX_OPCODE:
2207 q = SEG_PREFIX;
2208 break;
2209
2210 case REPNE_PREFIX_OPCODE:
2211 case REPE_PREFIX_OPCODE:
2212 q = REP_PREFIX;
2213 ret = PREFIX_REP;
2214 break;
2215
2216 case LOCK_PREFIX_OPCODE:
2217 q = LOCK_PREFIX;
2218 ret = PREFIX_LOCK;
2219 break;
2220
2221 case FWAIT_OPCODE:
2222 q = WAIT_PREFIX;
2223 break;
2224
2225 case ADDR_PREFIX_OPCODE:
2226 q = ADDR_PREFIX;
2227 break;
2228
2229 case DATA_PREFIX_OPCODE:
2230 q = DATA_PREFIX;
2231 break;
2232 }
2233 if (i.prefix[q] != 0)
2234 ret = PREFIX_EXIST;
2235 }
2236
2237 if (ret)
2238 {
2239 if (!i.prefix[q])
2240 ++i.prefixes;
2241 i.prefix[q] |= prefix;
2242 }
2243 else
2244 as_bad (_("same type of prefix used twice"));
2245
2246 return ret;
2247 }
2248
2249 static void
2250 update_code_flag (int value, int check)
2251 {
2252 PRINTF_LIKE ((*as_error));
2253
2254 flag_code = (enum flag_code) value;
2255 if (flag_code == CODE_64BIT)
2256 {
2257 cpu_arch_flags.bitfield.cpu64 = 1;
2258 cpu_arch_flags.bitfield.cpuno64 = 0;
2259 }
2260 else
2261 {
2262 cpu_arch_flags.bitfield.cpu64 = 0;
2263 cpu_arch_flags.bitfield.cpuno64 = 1;
2264 }
2265 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2266 {
2267 if (check)
2268 as_error = as_fatal;
2269 else
2270 as_error = as_bad;
2271 (*as_error) (_("64bit mode not supported on `%s'."),
2272 cpu_arch_name ? cpu_arch_name : default_arch);
2273 }
2274 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2275 {
2276 if (check)
2277 as_error = as_fatal;
2278 else
2279 as_error = as_bad;
2280 (*as_error) (_("32bit mode not supported on `%s'."),
2281 cpu_arch_name ? cpu_arch_name : default_arch);
2282 }
2283 stackop_size = '\0';
2284 }
2285
2286 static void
2287 set_code_flag (int value)
2288 {
2289 update_code_flag (value, 0);
2290 }
2291
2292 static void
2293 set_16bit_gcc_code_flag (int new_code_flag)
2294 {
2295 flag_code = (enum flag_code) new_code_flag;
2296 if (flag_code != CODE_16BIT)
2297 abort ();
2298 cpu_arch_flags.bitfield.cpu64 = 0;
2299 cpu_arch_flags.bitfield.cpuno64 = 1;
2300 stackop_size = LONG_MNEM_SUFFIX;
2301 }
2302
2303 static void
2304 set_intel_syntax (int syntax_flag)
2305 {
2306 /* Find out if register prefixing is specified. */
2307 int ask_naked_reg = 0;
2308
2309 SKIP_WHITESPACE ();
2310 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2311 {
2312 char *string;
2313 int e = get_symbol_name (&string);
2314
2315 if (strcmp (string, "prefix") == 0)
2316 ask_naked_reg = 1;
2317 else if (strcmp (string, "noprefix") == 0)
2318 ask_naked_reg = -1;
2319 else
2320 as_bad (_("bad argument to syntax directive."));
2321 (void) restore_line_pointer (e);
2322 }
2323 demand_empty_rest_of_line ();
2324
2325 intel_syntax = syntax_flag;
2326
2327 if (ask_naked_reg == 0)
2328 allow_naked_reg = (intel_syntax
2329 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2330 else
2331 allow_naked_reg = (ask_naked_reg < 0);
2332
2333 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2334
2335 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2336 identifier_chars['$'] = intel_syntax ? '$' : 0;
2337 register_prefix = allow_naked_reg ? "" : "%";
2338 }
2339
2340 static void
2341 set_intel_mnemonic (int mnemonic_flag)
2342 {
2343 intel_mnemonic = mnemonic_flag;
2344 }
2345
2346 static void
2347 set_allow_index_reg (int flag)
2348 {
2349 allow_index_reg = flag;
2350 }
2351
2352 static void
2353 set_check (int what)
2354 {
2355 enum check_kind *kind;
2356 const char *str;
2357
2358 if (what)
2359 {
2360 kind = &operand_check;
2361 str = "operand";
2362 }
2363 else
2364 {
2365 kind = &sse_check;
2366 str = "sse";
2367 }
2368
2369 SKIP_WHITESPACE ();
2370
2371 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2372 {
2373 char *string;
2374 int e = get_symbol_name (&string);
2375
2376 if (strcmp (string, "none") == 0)
2377 *kind = check_none;
2378 else if (strcmp (string, "warning") == 0)
2379 *kind = check_warning;
2380 else if (strcmp (string, "error") == 0)
2381 *kind = check_error;
2382 else
2383 as_bad (_("bad argument to %s_check directive."), str);
2384 (void) restore_line_pointer (e);
2385 }
2386 else
2387 as_bad (_("missing argument for %s_check directive"), str);
2388
2389 demand_empty_rest_of_line ();
2390 }
2391
2392 static void
2393 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2394 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2395 {
2396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2397 static const char *arch;
2398
2399 /* Intel LIOM is only supported on ELF. */
2400 if (!IS_ELF)
2401 return;
2402
2403 if (!arch)
2404 {
2405 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2406 use default_arch. */
2407 arch = cpu_arch_name;
2408 if (!arch)
2409 arch = default_arch;
2410 }
2411
2412 /* If we are targeting Intel MCU, we must enable it. */
2413 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2414 || new_flag.bitfield.cpuiamcu)
2415 return;
2416
2417 /* If we are targeting Intel L1OM, we must enable it. */
2418 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2419 || new_flag.bitfield.cpul1om)
2420 return;
2421
2422 /* If we are targeting Intel K1OM, we must enable it. */
2423 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2424 || new_flag.bitfield.cpuk1om)
2425 return;
2426
2427 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2428 #endif
2429 }
2430
2431 static void
2432 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2433 {
2434 SKIP_WHITESPACE ();
2435
2436 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2437 {
2438 char *string;
2439 int e = get_symbol_name (&string);
2440 unsigned int j;
2441 i386_cpu_flags flags;
2442
2443 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2444 {
2445 if (strcmp (string, cpu_arch[j].name) == 0)
2446 {
2447 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2448
2449 if (*string != '.')
2450 {
2451 cpu_arch_name = cpu_arch[j].name;
2452 cpu_sub_arch_name = NULL;
2453 cpu_arch_flags = cpu_arch[j].flags;
2454 if (flag_code == CODE_64BIT)
2455 {
2456 cpu_arch_flags.bitfield.cpu64 = 1;
2457 cpu_arch_flags.bitfield.cpuno64 = 0;
2458 }
2459 else
2460 {
2461 cpu_arch_flags.bitfield.cpu64 = 0;
2462 cpu_arch_flags.bitfield.cpuno64 = 1;
2463 }
2464 cpu_arch_isa = cpu_arch[j].type;
2465 cpu_arch_isa_flags = cpu_arch[j].flags;
2466 if (!cpu_arch_tune_set)
2467 {
2468 cpu_arch_tune = cpu_arch_isa;
2469 cpu_arch_tune_flags = cpu_arch_isa_flags;
2470 }
2471 break;
2472 }
2473
2474 flags = cpu_flags_or (cpu_arch_flags,
2475 cpu_arch[j].flags);
2476
2477 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2478 {
2479 if (cpu_sub_arch_name)
2480 {
2481 char *name = cpu_sub_arch_name;
2482 cpu_sub_arch_name = concat (name,
2483 cpu_arch[j].name,
2484 (const char *) NULL);
2485 free (name);
2486 }
2487 else
2488 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2489 cpu_arch_flags = flags;
2490 cpu_arch_isa_flags = flags;
2491 }
2492 (void) restore_line_pointer (e);
2493 demand_empty_rest_of_line ();
2494 return;
2495 }
2496 }
2497
2498 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2499 {
2500 /* Disable an ISA extension. */
2501 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2502 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2503 {
2504 flags = cpu_flags_and_not (cpu_arch_flags,
2505 cpu_noarch[j].flags);
2506 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2507 {
2508 if (cpu_sub_arch_name)
2509 {
2510 char *name = cpu_sub_arch_name;
2511 cpu_sub_arch_name = concat (name, string,
2512 (const char *) NULL);
2513 free (name);
2514 }
2515 else
2516 cpu_sub_arch_name = xstrdup (string);
2517 cpu_arch_flags = flags;
2518 cpu_arch_isa_flags = flags;
2519 }
2520 (void) restore_line_pointer (e);
2521 demand_empty_rest_of_line ();
2522 return;
2523 }
2524
2525 j = ARRAY_SIZE (cpu_arch);
2526 }
2527
2528 if (j >= ARRAY_SIZE (cpu_arch))
2529 as_bad (_("no such architecture: `%s'"), string);
2530
2531 *input_line_pointer = e;
2532 }
2533 else
2534 as_bad (_("missing cpu architecture"));
2535
2536 no_cond_jump_promotion = 0;
2537 if (*input_line_pointer == ','
2538 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2539 {
2540 char *string;
2541 char e;
2542
2543 ++input_line_pointer;
2544 e = get_symbol_name (&string);
2545
2546 if (strcmp (string, "nojumps") == 0)
2547 no_cond_jump_promotion = 1;
2548 else if (strcmp (string, "jumps") == 0)
2549 ;
2550 else
2551 as_bad (_("no such architecture modifier: `%s'"), string);
2552
2553 (void) restore_line_pointer (e);
2554 }
2555
2556 demand_empty_rest_of_line ();
2557 }
2558
2559 enum bfd_architecture
2560 i386_arch (void)
2561 {
2562 if (cpu_arch_isa == PROCESSOR_L1OM)
2563 {
2564 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2565 || flag_code != CODE_64BIT)
2566 as_fatal (_("Intel L1OM is 64bit ELF only"));
2567 return bfd_arch_l1om;
2568 }
2569 else if (cpu_arch_isa == PROCESSOR_K1OM)
2570 {
2571 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2572 || flag_code != CODE_64BIT)
2573 as_fatal (_("Intel K1OM is 64bit ELF only"));
2574 return bfd_arch_k1om;
2575 }
2576 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2577 {
2578 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2579 || flag_code == CODE_64BIT)
2580 as_fatal (_("Intel MCU is 32bit ELF only"));
2581 return bfd_arch_iamcu;
2582 }
2583 else
2584 return bfd_arch_i386;
2585 }
2586
2587 unsigned long
2588 i386_mach (void)
2589 {
2590 if (!strncmp (default_arch, "x86_64", 6))
2591 {
2592 if (cpu_arch_isa == PROCESSOR_L1OM)
2593 {
2594 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2595 || default_arch[6] != '\0')
2596 as_fatal (_("Intel L1OM is 64bit ELF only"));
2597 return bfd_mach_l1om;
2598 }
2599 else if (cpu_arch_isa == PROCESSOR_K1OM)
2600 {
2601 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2602 || default_arch[6] != '\0')
2603 as_fatal (_("Intel K1OM is 64bit ELF only"));
2604 return bfd_mach_k1om;
2605 }
2606 else if (default_arch[6] == '\0')
2607 return bfd_mach_x86_64;
2608 else
2609 return bfd_mach_x64_32;
2610 }
2611 else if (!strcmp (default_arch, "i386")
2612 || !strcmp (default_arch, "iamcu"))
2613 {
2614 if (cpu_arch_isa == PROCESSOR_IAMCU)
2615 {
2616 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2617 as_fatal (_("Intel MCU is 32bit ELF only"));
2618 return bfd_mach_i386_iamcu;
2619 }
2620 else
2621 return bfd_mach_i386_i386;
2622 }
2623 else
2624 as_fatal (_("unknown architecture"));
2625 }
2626 \f
2627 void
2628 md_begin (void)
2629 {
2630 const char *hash_err;
2631
2632 /* Support pseudo prefixes like {disp32}. */
2633 lex_type ['{'] = LEX_BEGIN_NAME;
2634
2635 /* Initialize op_hash hash table. */
2636 op_hash = hash_new ();
2637
2638 {
2639 const insn_template *optab;
2640 templates *core_optab;
2641
2642 /* Setup for loop. */
2643 optab = i386_optab;
2644 core_optab = XNEW (templates);
2645 core_optab->start = optab;
2646
2647 while (1)
2648 {
2649 ++optab;
2650 if (optab->name == NULL
2651 || strcmp (optab->name, (optab - 1)->name) != 0)
2652 {
2653 /* different name --> ship out current template list;
2654 add to hash table; & begin anew. */
2655 core_optab->end = optab;
2656 hash_err = hash_insert (op_hash,
2657 (optab - 1)->name,
2658 (void *) core_optab);
2659 if (hash_err)
2660 {
2661 as_fatal (_("can't hash %s: %s"),
2662 (optab - 1)->name,
2663 hash_err);
2664 }
2665 if (optab->name == NULL)
2666 break;
2667 core_optab = XNEW (templates);
2668 core_optab->start = optab;
2669 }
2670 }
2671 }
2672
2673 /* Initialize reg_hash hash table. */
2674 reg_hash = hash_new ();
2675 {
2676 const reg_entry *regtab;
2677 unsigned int regtab_size = i386_regtab_size;
2678
2679 for (regtab = i386_regtab; regtab_size--; regtab++)
2680 {
2681 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2682 if (hash_err)
2683 as_fatal (_("can't hash %s: %s"),
2684 regtab->reg_name,
2685 hash_err);
2686 }
2687 }
2688
2689 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2690 {
2691 int c;
2692 char *p;
2693
2694 for (c = 0; c < 256; c++)
2695 {
2696 if (ISDIGIT (c))
2697 {
2698 digit_chars[c] = c;
2699 mnemonic_chars[c] = c;
2700 register_chars[c] = c;
2701 operand_chars[c] = c;
2702 }
2703 else if (ISLOWER (c))
2704 {
2705 mnemonic_chars[c] = c;
2706 register_chars[c] = c;
2707 operand_chars[c] = c;
2708 }
2709 else if (ISUPPER (c))
2710 {
2711 mnemonic_chars[c] = TOLOWER (c);
2712 register_chars[c] = mnemonic_chars[c];
2713 operand_chars[c] = c;
2714 }
2715 else if (c == '{' || c == '}')
2716 {
2717 mnemonic_chars[c] = c;
2718 operand_chars[c] = c;
2719 }
2720
2721 if (ISALPHA (c) || ISDIGIT (c))
2722 identifier_chars[c] = c;
2723 else if (c >= 128)
2724 {
2725 identifier_chars[c] = c;
2726 operand_chars[c] = c;
2727 }
2728 }
2729
2730 #ifdef LEX_AT
2731 identifier_chars['@'] = '@';
2732 #endif
2733 #ifdef LEX_QM
2734 identifier_chars['?'] = '?';
2735 operand_chars['?'] = '?';
2736 #endif
2737 digit_chars['-'] = '-';
2738 mnemonic_chars['_'] = '_';
2739 mnemonic_chars['-'] = '-';
2740 mnemonic_chars['.'] = '.';
2741 identifier_chars['_'] = '_';
2742 identifier_chars['.'] = '.';
2743
2744 for (p = operand_special_chars; *p != '\0'; p++)
2745 operand_chars[(unsigned char) *p] = *p;
2746 }
2747
2748 if (flag_code == CODE_64BIT)
2749 {
2750 #if defined (OBJ_COFF) && defined (TE_PE)
2751 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2752 ? 32 : 16);
2753 #else
2754 x86_dwarf2_return_column = 16;
2755 #endif
2756 x86_cie_data_alignment = -8;
2757 }
2758 else
2759 {
2760 x86_dwarf2_return_column = 8;
2761 x86_cie_data_alignment = -4;
2762 }
2763 }
2764
2765 void
2766 i386_print_statistics (FILE *file)
2767 {
2768 hash_print_statistics (file, "i386 opcode", op_hash);
2769 hash_print_statistics (file, "i386 register", reg_hash);
2770 }
2771 \f
2772 #ifdef DEBUG386
2773
2774 /* Debugging routines for md_assemble. */
2775 static void pte (insn_template *);
2776 static void pt (i386_operand_type);
2777 static void pe (expressionS *);
2778 static void ps (symbolS *);
2779
2780 static void
2781 pi (char *line, i386_insn *x)
2782 {
2783 unsigned int j;
2784
2785 fprintf (stdout, "%s: template ", line);
2786 pte (&x->tm);
2787 fprintf (stdout, " address: base %s index %s scale %x\n",
2788 x->base_reg ? x->base_reg->reg_name : "none",
2789 x->index_reg ? x->index_reg->reg_name : "none",
2790 x->log2_scale_factor);
2791 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2792 x->rm.mode, x->rm.reg, x->rm.regmem);
2793 fprintf (stdout, " sib: base %x index %x scale %x\n",
2794 x->sib.base, x->sib.index, x->sib.scale);
2795 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2796 (x->rex & REX_W) != 0,
2797 (x->rex & REX_R) != 0,
2798 (x->rex & REX_X) != 0,
2799 (x->rex & REX_B) != 0);
2800 for (j = 0; j < x->operands; j++)
2801 {
2802 fprintf (stdout, " #%d: ", j + 1);
2803 pt (x->types[j]);
2804 fprintf (stdout, "\n");
2805 if (x->types[j].bitfield.reg
2806 || x->types[j].bitfield.regmmx
2807 || x->types[j].bitfield.regxmm
2808 || x->types[j].bitfield.regymm
2809 || x->types[j].bitfield.regzmm
2810 || x->types[j].bitfield.sreg2
2811 || x->types[j].bitfield.sreg3
2812 || x->types[j].bitfield.control
2813 || x->types[j].bitfield.debug
2814 || x->types[j].bitfield.test)
2815 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2816 if (operand_type_check (x->types[j], imm))
2817 pe (x->op[j].imms);
2818 if (operand_type_check (x->types[j], disp))
2819 pe (x->op[j].disps);
2820 }
2821 }
2822
2823 static void
2824 pte (insn_template *t)
2825 {
2826 unsigned int j;
2827 fprintf (stdout, " %d operands ", t->operands);
2828 fprintf (stdout, "opcode %x ", t->base_opcode);
2829 if (t->extension_opcode != None)
2830 fprintf (stdout, "ext %x ", t->extension_opcode);
2831 if (t->opcode_modifier.d)
2832 fprintf (stdout, "D");
2833 if (t->opcode_modifier.w)
2834 fprintf (stdout, "W");
2835 fprintf (stdout, "\n");
2836 for (j = 0; j < t->operands; j++)
2837 {
2838 fprintf (stdout, " #%d type ", j + 1);
2839 pt (t->operand_types[j]);
2840 fprintf (stdout, "\n");
2841 }
2842 }
2843
2844 static void
2845 pe (expressionS *e)
2846 {
2847 fprintf (stdout, " operation %d\n", e->X_op);
2848 fprintf (stdout, " add_number %ld (%lx)\n",
2849 (long) e->X_add_number, (long) e->X_add_number);
2850 if (e->X_add_symbol)
2851 {
2852 fprintf (stdout, " add_symbol ");
2853 ps (e->X_add_symbol);
2854 fprintf (stdout, "\n");
2855 }
2856 if (e->X_op_symbol)
2857 {
2858 fprintf (stdout, " op_symbol ");
2859 ps (e->X_op_symbol);
2860 fprintf (stdout, "\n");
2861 }
2862 }
2863
2864 static void
2865 ps (symbolS *s)
2866 {
2867 fprintf (stdout, "%s type %s%s",
2868 S_GET_NAME (s),
2869 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2870 segment_name (S_GET_SEGMENT (s)));
2871 }
2872
2873 static struct type_name
2874 {
2875 i386_operand_type mask;
2876 const char *name;
2877 }
2878 const type_names[] =
2879 {
2880 { OPERAND_TYPE_REG8, "r8" },
2881 { OPERAND_TYPE_REG16, "r16" },
2882 { OPERAND_TYPE_REG32, "r32" },
2883 { OPERAND_TYPE_REG64, "r64" },
2884 { OPERAND_TYPE_IMM8, "i8" },
2885 { OPERAND_TYPE_IMM8, "i8s" },
2886 { OPERAND_TYPE_IMM16, "i16" },
2887 { OPERAND_TYPE_IMM32, "i32" },
2888 { OPERAND_TYPE_IMM32S, "i32s" },
2889 { OPERAND_TYPE_IMM64, "i64" },
2890 { OPERAND_TYPE_IMM1, "i1" },
2891 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2892 { OPERAND_TYPE_DISP8, "d8" },
2893 { OPERAND_TYPE_DISP16, "d16" },
2894 { OPERAND_TYPE_DISP32, "d32" },
2895 { OPERAND_TYPE_DISP32S, "d32s" },
2896 { OPERAND_TYPE_DISP64, "d64" },
2897 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2898 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2899 { OPERAND_TYPE_CONTROL, "control reg" },
2900 { OPERAND_TYPE_TEST, "test reg" },
2901 { OPERAND_TYPE_DEBUG, "debug reg" },
2902 { OPERAND_TYPE_FLOATREG, "FReg" },
2903 { OPERAND_TYPE_FLOATACC, "FAcc" },
2904 { OPERAND_TYPE_SREG2, "SReg2" },
2905 { OPERAND_TYPE_SREG3, "SReg3" },
2906 { OPERAND_TYPE_ACC, "Acc" },
2907 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2908 { OPERAND_TYPE_REGMMX, "rMMX" },
2909 { OPERAND_TYPE_REGXMM, "rXMM" },
2910 { OPERAND_TYPE_REGYMM, "rYMM" },
2911 { OPERAND_TYPE_REGZMM, "rZMM" },
2912 { OPERAND_TYPE_REGMASK, "Mask reg" },
2913 { OPERAND_TYPE_ESSEG, "es" },
2914 };
2915
2916 static void
2917 pt (i386_operand_type t)
2918 {
2919 unsigned int j;
2920 i386_operand_type a;
2921
2922 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2923 {
2924 a = operand_type_and (t, type_names[j].mask);
2925 if (!operand_type_all_zero (&a))
2926 fprintf (stdout, "%s, ", type_names[j].name);
2927 }
2928 fflush (stdout);
2929 }
2930
2931 #endif /* DEBUG386 */
2932 \f
2933 static bfd_reloc_code_real_type
2934 reloc (unsigned int size,
2935 int pcrel,
2936 int sign,
2937 bfd_reloc_code_real_type other)
2938 {
2939 if (other != NO_RELOC)
2940 {
2941 reloc_howto_type *rel;
2942
2943 if (size == 8)
2944 switch (other)
2945 {
2946 case BFD_RELOC_X86_64_GOT32:
2947 return BFD_RELOC_X86_64_GOT64;
2948 break;
2949 case BFD_RELOC_X86_64_GOTPLT64:
2950 return BFD_RELOC_X86_64_GOTPLT64;
2951 break;
2952 case BFD_RELOC_X86_64_PLTOFF64:
2953 return BFD_RELOC_X86_64_PLTOFF64;
2954 break;
2955 case BFD_RELOC_X86_64_GOTPC32:
2956 other = BFD_RELOC_X86_64_GOTPC64;
2957 break;
2958 case BFD_RELOC_X86_64_GOTPCREL:
2959 other = BFD_RELOC_X86_64_GOTPCREL64;
2960 break;
2961 case BFD_RELOC_X86_64_TPOFF32:
2962 other = BFD_RELOC_X86_64_TPOFF64;
2963 break;
2964 case BFD_RELOC_X86_64_DTPOFF32:
2965 other = BFD_RELOC_X86_64_DTPOFF64;
2966 break;
2967 default:
2968 break;
2969 }
2970
2971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2972 if (other == BFD_RELOC_SIZE32)
2973 {
2974 if (size == 8)
2975 other = BFD_RELOC_SIZE64;
2976 if (pcrel)
2977 {
2978 as_bad (_("there are no pc-relative size relocations"));
2979 return NO_RELOC;
2980 }
2981 }
2982 #endif
2983
2984 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2985 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2986 sign = -1;
2987
2988 rel = bfd_reloc_type_lookup (stdoutput, other);
2989 if (!rel)
2990 as_bad (_("unknown relocation (%u)"), other);
2991 else if (size != bfd_get_reloc_size (rel))
2992 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2993 bfd_get_reloc_size (rel),
2994 size);
2995 else if (pcrel && !rel->pc_relative)
2996 as_bad (_("non-pc-relative relocation for pc-relative field"));
2997 else if ((rel->complain_on_overflow == complain_overflow_signed
2998 && !sign)
2999 || (rel->complain_on_overflow == complain_overflow_unsigned
3000 && sign > 0))
3001 as_bad (_("relocated field and relocation type differ in signedness"));
3002 else
3003 return other;
3004 return NO_RELOC;
3005 }
3006
3007 if (pcrel)
3008 {
3009 if (!sign)
3010 as_bad (_("there are no unsigned pc-relative relocations"));
3011 switch (size)
3012 {
3013 case 1: return BFD_RELOC_8_PCREL;
3014 case 2: return BFD_RELOC_16_PCREL;
3015 case 4: return BFD_RELOC_32_PCREL;
3016 case 8: return BFD_RELOC_64_PCREL;
3017 }
3018 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3019 }
3020 else
3021 {
3022 if (sign > 0)
3023 switch (size)
3024 {
3025 case 4: return BFD_RELOC_X86_64_32S;
3026 }
3027 else
3028 switch (size)
3029 {
3030 case 1: return BFD_RELOC_8;
3031 case 2: return BFD_RELOC_16;
3032 case 4: return BFD_RELOC_32;
3033 case 8: return BFD_RELOC_64;
3034 }
3035 as_bad (_("cannot do %s %u byte relocation"),
3036 sign > 0 ? "signed" : "unsigned", size);
3037 }
3038
3039 return NO_RELOC;
3040 }
3041
3042 /* Here we decide which fixups can be adjusted to make them relative to
3043 the beginning of the section instead of the symbol. Basically we need
3044 to make sure that the dynamic relocations are done correctly, so in
3045 some cases we force the original symbol to be used. */
3046
3047 int
3048 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3049 {
3050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3051 if (!IS_ELF)
3052 return 1;
3053
3054 /* Don't adjust pc-relative references to merge sections in 64-bit
3055 mode. */
3056 if (use_rela_relocations
3057 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3058 && fixP->fx_pcrel)
3059 return 0;
3060
3061 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3062 and changed later by validate_fix. */
3063 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3064 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3065 return 0;
3066
3067 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3068 for size relocations. */
3069 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3070 || fixP->fx_r_type == BFD_RELOC_SIZE64
3071 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3072 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3073 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3074 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3075 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3076 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3077 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3078 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3079 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3080 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3081 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3082 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3083 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3084 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3085 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3086 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3087 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3088 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3089 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3090 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3091 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3092 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3093 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3094 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3095 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3096 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3097 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3098 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3099 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3100 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3101 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3102 return 0;
3103 #endif
3104 return 1;
3105 }
3106
3107 static int
3108 intel_float_operand (const char *mnemonic)
3109 {
3110 /* Note that the value returned is meaningful only for opcodes with (memory)
3111 operands, hence the code here is free to improperly handle opcodes that
3112 have no operands (for better performance and smaller code). */
3113
3114 if (mnemonic[0] != 'f')
3115 return 0; /* non-math */
3116
3117 switch (mnemonic[1])
3118 {
3119 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3120 the fs segment override prefix not currently handled because no
3121 call path can make opcodes without operands get here */
3122 case 'i':
3123 return 2 /* integer op */;
3124 case 'l':
3125 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3126 return 3; /* fldcw/fldenv */
3127 break;
3128 case 'n':
3129 if (mnemonic[2] != 'o' /* fnop */)
3130 return 3; /* non-waiting control op */
3131 break;
3132 case 'r':
3133 if (mnemonic[2] == 's')
3134 return 3; /* frstor/frstpm */
3135 break;
3136 case 's':
3137 if (mnemonic[2] == 'a')
3138 return 3; /* fsave */
3139 if (mnemonic[2] == 't')
3140 {
3141 switch (mnemonic[3])
3142 {
3143 case 'c': /* fstcw */
3144 case 'd': /* fstdw */
3145 case 'e': /* fstenv */
3146 case 's': /* fsts[gw] */
3147 return 3;
3148 }
3149 }
3150 break;
3151 case 'x':
3152 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3153 return 0; /* fxsave/fxrstor are not really math ops */
3154 break;
3155 }
3156
3157 return 1;
3158 }
3159
3160 /* Build the VEX prefix. */
3161
3162 static void
3163 build_vex_prefix (const insn_template *t)
3164 {
3165 unsigned int register_specifier;
3166 unsigned int implied_prefix;
3167 unsigned int vector_length;
3168
3169 /* Check register specifier. */
3170 if (i.vex.register_specifier)
3171 {
3172 register_specifier =
3173 ~register_number (i.vex.register_specifier) & 0xf;
3174 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3175 }
3176 else
3177 register_specifier = 0xf;
3178
3179 /* Use 2-byte VEX prefix by swapping destination and source
3180 operand. */
3181 if (i.vec_encoding != vex_encoding_vex3
3182 && i.dir_encoding == dir_encoding_default
3183 && i.operands == i.reg_operands
3184 && i.tm.opcode_modifier.vexopcode == VEX0F
3185 && i.tm.opcode_modifier.load
3186 && i.rex == REX_B)
3187 {
3188 unsigned int xchg = i.operands - 1;
3189 union i386_op temp_op;
3190 i386_operand_type temp_type;
3191
3192 temp_type = i.types[xchg];
3193 i.types[xchg] = i.types[0];
3194 i.types[0] = temp_type;
3195 temp_op = i.op[xchg];
3196 i.op[xchg] = i.op[0];
3197 i.op[0] = temp_op;
3198
3199 gas_assert (i.rm.mode == 3);
3200
3201 i.rex = REX_R;
3202 xchg = i.rm.regmem;
3203 i.rm.regmem = i.rm.reg;
3204 i.rm.reg = xchg;
3205
3206 /* Use the next insn. */
3207 i.tm = t[1];
3208 }
3209
3210 if (i.tm.opcode_modifier.vex == VEXScalar)
3211 vector_length = avxscalar;
3212 else
3213 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3214
3215 switch ((i.tm.base_opcode >> 8) & 0xff)
3216 {
3217 case 0:
3218 implied_prefix = 0;
3219 break;
3220 case DATA_PREFIX_OPCODE:
3221 implied_prefix = 1;
3222 break;
3223 case REPE_PREFIX_OPCODE:
3224 implied_prefix = 2;
3225 break;
3226 case REPNE_PREFIX_OPCODE:
3227 implied_prefix = 3;
3228 break;
3229 default:
3230 abort ();
3231 }
3232
3233 /* Use 2-byte VEX prefix if possible. */
3234 if (i.vec_encoding != vex_encoding_vex3
3235 && i.tm.opcode_modifier.vexopcode == VEX0F
3236 && i.tm.opcode_modifier.vexw != VEXW1
3237 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3238 {
3239 /* 2-byte VEX prefix. */
3240 unsigned int r;
3241
3242 i.vex.length = 2;
3243 i.vex.bytes[0] = 0xc5;
3244
3245 /* Check the REX.R bit. */
3246 r = (i.rex & REX_R) ? 0 : 1;
3247 i.vex.bytes[1] = (r << 7
3248 | register_specifier << 3
3249 | vector_length << 2
3250 | implied_prefix);
3251 }
3252 else
3253 {
3254 /* 3-byte VEX prefix. */
3255 unsigned int m, w;
3256
3257 i.vex.length = 3;
3258
3259 switch (i.tm.opcode_modifier.vexopcode)
3260 {
3261 case VEX0F:
3262 m = 0x1;
3263 i.vex.bytes[0] = 0xc4;
3264 break;
3265 case VEX0F38:
3266 m = 0x2;
3267 i.vex.bytes[0] = 0xc4;
3268 break;
3269 case VEX0F3A:
3270 m = 0x3;
3271 i.vex.bytes[0] = 0xc4;
3272 break;
3273 case XOP08:
3274 m = 0x8;
3275 i.vex.bytes[0] = 0x8f;
3276 break;
3277 case XOP09:
3278 m = 0x9;
3279 i.vex.bytes[0] = 0x8f;
3280 break;
3281 case XOP0A:
3282 m = 0xa;
3283 i.vex.bytes[0] = 0x8f;
3284 break;
3285 default:
3286 abort ();
3287 }
3288
3289 /* The high 3 bits of the second VEX byte are 1's compliment
3290 of RXB bits from REX. */
3291 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3292
3293 /* Check the REX.W bit. */
3294 w = (i.rex & REX_W) ? 1 : 0;
3295 if (i.tm.opcode_modifier.vexw == VEXW1)
3296 w = 1;
3297
3298 i.vex.bytes[2] = (w << 7
3299 | register_specifier << 3
3300 | vector_length << 2
3301 | implied_prefix);
3302 }
3303 }
3304
3305 /* Build the EVEX prefix. */
3306
3307 static void
3308 build_evex_prefix (void)
3309 {
3310 unsigned int register_specifier;
3311 unsigned int implied_prefix;
3312 unsigned int m, w;
3313 rex_byte vrex_used = 0;
3314
3315 /* Check register specifier. */
3316 if (i.vex.register_specifier)
3317 {
3318 gas_assert ((i.vrex & REX_X) == 0);
3319
3320 register_specifier = i.vex.register_specifier->reg_num;
3321 if ((i.vex.register_specifier->reg_flags & RegRex))
3322 register_specifier += 8;
3323 /* The upper 16 registers are encoded in the fourth byte of the
3324 EVEX prefix. */
3325 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3326 i.vex.bytes[3] = 0x8;
3327 register_specifier = ~register_specifier & 0xf;
3328 }
3329 else
3330 {
3331 register_specifier = 0xf;
3332
3333 /* Encode upper 16 vector index register in the fourth byte of
3334 the EVEX prefix. */
3335 if (!(i.vrex & REX_X))
3336 i.vex.bytes[3] = 0x8;
3337 else
3338 vrex_used |= REX_X;
3339 }
3340
3341 switch ((i.tm.base_opcode >> 8) & 0xff)
3342 {
3343 case 0:
3344 implied_prefix = 0;
3345 break;
3346 case DATA_PREFIX_OPCODE:
3347 implied_prefix = 1;
3348 break;
3349 case REPE_PREFIX_OPCODE:
3350 implied_prefix = 2;
3351 break;
3352 case REPNE_PREFIX_OPCODE:
3353 implied_prefix = 3;
3354 break;
3355 default:
3356 abort ();
3357 }
3358
3359 /* 4 byte EVEX prefix. */
3360 i.vex.length = 4;
3361 i.vex.bytes[0] = 0x62;
3362
3363 /* mmmm bits. */
3364 switch (i.tm.opcode_modifier.vexopcode)
3365 {
3366 case VEX0F:
3367 m = 1;
3368 break;
3369 case VEX0F38:
3370 m = 2;
3371 break;
3372 case VEX0F3A:
3373 m = 3;
3374 break;
3375 default:
3376 abort ();
3377 break;
3378 }
3379
3380 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3381 bits from REX. */
3382 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3383
3384 /* The fifth bit of the second EVEX byte is 1's compliment of the
3385 REX_R bit in VREX. */
3386 if (!(i.vrex & REX_R))
3387 i.vex.bytes[1] |= 0x10;
3388 else
3389 vrex_used |= REX_R;
3390
3391 if ((i.reg_operands + i.imm_operands) == i.operands)
3392 {
3393 /* When all operands are registers, the REX_X bit in REX is not
3394 used. We reuse it to encode the upper 16 registers, which is
3395 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3396 as 1's compliment. */
3397 if ((i.vrex & REX_B))
3398 {
3399 vrex_used |= REX_B;
3400 i.vex.bytes[1] &= ~0x40;
3401 }
3402 }
3403
3404 /* EVEX instructions shouldn't need the REX prefix. */
3405 i.vrex &= ~vrex_used;
3406 gas_assert (i.vrex == 0);
3407
3408 /* Check the REX.W bit. */
3409 w = (i.rex & REX_W) ? 1 : 0;
3410 if (i.tm.opcode_modifier.vexw)
3411 {
3412 if (i.tm.opcode_modifier.vexw == VEXW1)
3413 w = 1;
3414 }
3415 /* If w is not set it means we are dealing with WIG instruction. */
3416 else if (!w)
3417 {
3418 if (evexwig == evexw1)
3419 w = 1;
3420 }
3421
3422 /* Encode the U bit. */
3423 implied_prefix |= 0x4;
3424
3425 /* The third byte of the EVEX prefix. */
3426 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3427
3428 /* The fourth byte of the EVEX prefix. */
3429 /* The zeroing-masking bit. */
3430 if (i.mask && i.mask->zeroing)
3431 i.vex.bytes[3] |= 0x80;
3432
3433 /* Don't always set the broadcast bit if there is no RC. */
3434 if (!i.rounding)
3435 {
3436 /* Encode the vector length. */
3437 unsigned int vec_length;
3438
3439 switch (i.tm.opcode_modifier.evex)
3440 {
3441 case EVEXLIG: /* LL' is ignored */
3442 vec_length = evexlig << 5;
3443 break;
3444 case EVEX128:
3445 vec_length = 0 << 5;
3446 break;
3447 case EVEX256:
3448 vec_length = 1 << 5;
3449 break;
3450 case EVEX512:
3451 vec_length = 2 << 5;
3452 break;
3453 default:
3454 abort ();
3455 break;
3456 }
3457 i.vex.bytes[3] |= vec_length;
3458 /* Encode the broadcast bit. */
3459 if (i.broadcast)
3460 i.vex.bytes[3] |= 0x10;
3461 }
3462 else
3463 {
3464 if (i.rounding->type != saeonly)
3465 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3466 else
3467 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3468 }
3469
3470 if (i.mask && i.mask->mask)
3471 i.vex.bytes[3] |= i.mask->mask->reg_num;
3472 }
3473
3474 static void
3475 process_immext (void)
3476 {
3477 expressionS *exp;
3478
3479 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3480 && i.operands > 0)
3481 {
3482 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3483 with an opcode suffix which is coded in the same place as an
3484 8-bit immediate field would be.
3485 Here we check those operands and remove them afterwards. */
3486 unsigned int x;
3487
3488 for (x = 0; x < i.operands; x++)
3489 if (register_number (i.op[x].regs) != x)
3490 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3491 register_prefix, i.op[x].regs->reg_name, x + 1,
3492 i.tm.name);
3493
3494 i.operands = 0;
3495 }
3496
3497 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3498 {
3499 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3500 suffix which is coded in the same place as an 8-bit immediate
3501 field would be.
3502 Here we check those operands and remove them afterwards. */
3503 unsigned int x;
3504
3505 if (i.operands != 3)
3506 abort();
3507
3508 for (x = 0; x < 2; x++)
3509 if (register_number (i.op[x].regs) != x)
3510 goto bad_register_operand;
3511
3512 /* Check for third operand for mwaitx/monitorx insn. */
3513 if (register_number (i.op[x].regs)
3514 != (x + (i.tm.extension_opcode == 0xfb)))
3515 {
3516 bad_register_operand:
3517 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3518 register_prefix, i.op[x].regs->reg_name, x+1,
3519 i.tm.name);
3520 }
3521
3522 i.operands = 0;
3523 }
3524
3525 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3526 which is coded in the same place as an 8-bit immediate field
3527 would be. Here we fake an 8-bit immediate operand from the
3528 opcode suffix stored in tm.extension_opcode.
3529
3530 AVX instructions also use this encoding, for some of
3531 3 argument instructions. */
3532
3533 gas_assert (i.imm_operands <= 1
3534 && (i.operands <= 2
3535 || ((i.tm.opcode_modifier.vex
3536 || i.tm.opcode_modifier.evex)
3537 && i.operands <= 4)));
3538
3539 exp = &im_expressions[i.imm_operands++];
3540 i.op[i.operands].imms = exp;
3541 i.types[i.operands] = imm8;
3542 i.operands++;
3543 exp->X_op = O_constant;
3544 exp->X_add_number = i.tm.extension_opcode;
3545 i.tm.extension_opcode = None;
3546 }
3547
3548
3549 static int
3550 check_hle (void)
3551 {
3552 switch (i.tm.opcode_modifier.hleprefixok)
3553 {
3554 default:
3555 abort ();
3556 case HLEPrefixNone:
3557 as_bad (_("invalid instruction `%s' after `%s'"),
3558 i.tm.name, i.hle_prefix);
3559 return 0;
3560 case HLEPrefixLock:
3561 if (i.prefix[LOCK_PREFIX])
3562 return 1;
3563 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3564 return 0;
3565 case HLEPrefixAny:
3566 return 1;
3567 case HLEPrefixRelease:
3568 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3569 {
3570 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3571 i.tm.name);
3572 return 0;
3573 }
3574 if (i.mem_operands == 0
3575 || !operand_type_check (i.types[i.operands - 1], anymem))
3576 {
3577 as_bad (_("memory destination needed for instruction `%s'"
3578 " after `xrelease'"), i.tm.name);
3579 return 0;
3580 }
3581 return 1;
3582 }
3583 }
3584
3585 /* This is the guts of the machine-dependent assembler. LINE points to a
3586 machine dependent instruction. This function is supposed to emit
3587 the frags/bytes it assembles to. */
3588
3589 void
3590 md_assemble (char *line)
3591 {
3592 unsigned int j;
3593 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3594 const insn_template *t;
3595
3596 /* Initialize globals. */
3597 memset (&i, '\0', sizeof (i));
3598 for (j = 0; j < MAX_OPERANDS; j++)
3599 i.reloc[j] = NO_RELOC;
3600 memset (disp_expressions, '\0', sizeof (disp_expressions));
3601 memset (im_expressions, '\0', sizeof (im_expressions));
3602 save_stack_p = save_stack;
3603
3604 /* First parse an instruction mnemonic & call i386_operand for the operands.
3605 We assume that the scrubber has arranged it so that line[0] is the valid
3606 start of a (possibly prefixed) mnemonic. */
3607
3608 line = parse_insn (line, mnemonic);
3609 if (line == NULL)
3610 return;
3611 mnem_suffix = i.suffix;
3612
3613 line = parse_operands (line, mnemonic);
3614 this_operand = -1;
3615 xfree (i.memop1_string);
3616 i.memop1_string = NULL;
3617 if (line == NULL)
3618 return;
3619
3620 /* Now we've parsed the mnemonic into a set of templates, and have the
3621 operands at hand. */
3622
3623 /* All intel opcodes have reversed operands except for "bound" and
3624 "enter". We also don't reverse intersegment "jmp" and "call"
3625 instructions with 2 immediate operands so that the immediate segment
3626 precedes the offset, as it does when in AT&T mode. */
3627 if (intel_syntax
3628 && i.operands > 1
3629 && (strcmp (mnemonic, "bound") != 0)
3630 && (strcmp (mnemonic, "invlpga") != 0)
3631 && !(operand_type_check (i.types[0], imm)
3632 && operand_type_check (i.types[1], imm)))
3633 swap_operands ();
3634
3635 /* The order of the immediates should be reversed
3636 for 2 immediates extrq and insertq instructions */
3637 if (i.imm_operands == 2
3638 && (strcmp (mnemonic, "extrq") == 0
3639 || strcmp (mnemonic, "insertq") == 0))
3640 swap_2_operands (0, 1);
3641
3642 if (i.imm_operands)
3643 optimize_imm ();
3644
3645 /* Don't optimize displacement for movabs since it only takes 64bit
3646 displacement. */
3647 if (i.disp_operands
3648 && i.disp_encoding != disp_encoding_32bit
3649 && (flag_code != CODE_64BIT
3650 || strcmp (mnemonic, "movabs") != 0))
3651 optimize_disp ();
3652
3653 /* Next, we find a template that matches the given insn,
3654 making sure the overlap of the given operands types is consistent
3655 with the template operand types. */
3656
3657 if (!(t = match_template (mnem_suffix)))
3658 return;
3659
3660 if (sse_check != check_none
3661 && !i.tm.opcode_modifier.noavx
3662 && (i.tm.cpu_flags.bitfield.cpusse
3663 || i.tm.cpu_flags.bitfield.cpusse2
3664 || i.tm.cpu_flags.bitfield.cpusse3
3665 || i.tm.cpu_flags.bitfield.cpussse3
3666 || i.tm.cpu_flags.bitfield.cpusse4_1
3667 || i.tm.cpu_flags.bitfield.cpusse4_2))
3668 {
3669 (sse_check == check_warning
3670 ? as_warn
3671 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3672 }
3673
3674 /* Zap movzx and movsx suffix. The suffix has been set from
3675 "word ptr" or "byte ptr" on the source operand in Intel syntax
3676 or extracted from mnemonic in AT&T syntax. But we'll use
3677 the destination register to choose the suffix for encoding. */
3678 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3679 {
3680 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3681 there is no suffix, the default will be byte extension. */
3682 if (i.reg_operands != 2
3683 && !i.suffix
3684 && intel_syntax)
3685 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3686
3687 i.suffix = 0;
3688 }
3689
3690 if (i.tm.opcode_modifier.fwait)
3691 if (!add_prefix (FWAIT_OPCODE))
3692 return;
3693
3694 /* Check if REP prefix is OK. */
3695 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3696 {
3697 as_bad (_("invalid instruction `%s' after `%s'"),
3698 i.tm.name, i.rep_prefix);
3699 return;
3700 }
3701
3702 /* Check for lock without a lockable instruction. Destination operand
3703 must be memory unless it is xchg (0x86). */
3704 if (i.prefix[LOCK_PREFIX]
3705 && (!i.tm.opcode_modifier.islockable
3706 || i.mem_operands == 0
3707 || (i.tm.base_opcode != 0x86
3708 && !operand_type_check (i.types[i.operands - 1], anymem))))
3709 {
3710 as_bad (_("expecting lockable instruction after `lock'"));
3711 return;
3712 }
3713
3714 /* Check if HLE prefix is OK. */
3715 if (i.hle_prefix && !check_hle ())
3716 return;
3717
3718 /* Check BND prefix. */
3719 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3720 as_bad (_("expecting valid branch instruction after `bnd'"));
3721
3722 /* Check NOTRACK prefix. */
3723 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3724 as_bad (_("expecting indirect branch instruction after `notrack'"));
3725
3726 if (i.tm.cpu_flags.bitfield.cpumpx)
3727 {
3728 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3729 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3730 else if (flag_code != CODE_16BIT
3731 ? i.prefix[ADDR_PREFIX]
3732 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3733 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3734 }
3735
3736 /* Insert BND prefix. */
3737 if (add_bnd_prefix
3738 && i.tm.opcode_modifier.bndprefixok
3739 && !i.prefix[BND_PREFIX])
3740 add_prefix (BND_PREFIX_OPCODE);
3741
3742 /* Check string instruction segment overrides. */
3743 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3744 {
3745 if (!check_string ())
3746 return;
3747 i.disp_operands = 0;
3748 }
3749
3750 if (!process_suffix ())
3751 return;
3752
3753 /* Update operand types. */
3754 for (j = 0; j < i.operands; j++)
3755 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3756
3757 /* Make still unresolved immediate matches conform to size of immediate
3758 given in i.suffix. */
3759 if (!finalize_imm ())
3760 return;
3761
3762 if (i.types[0].bitfield.imm1)
3763 i.imm_operands = 0; /* kludge for shift insns. */
3764
3765 /* We only need to check those implicit registers for instructions
3766 with 3 operands or less. */
3767 if (i.operands <= 3)
3768 for (j = 0; j < i.operands; j++)
3769 if (i.types[j].bitfield.inoutportreg
3770 || i.types[j].bitfield.shiftcount
3771 || i.types[j].bitfield.acc)
3772 i.reg_operands--;
3773
3774 /* ImmExt should be processed after SSE2AVX. */
3775 if (!i.tm.opcode_modifier.sse2avx
3776 && i.tm.opcode_modifier.immext)
3777 process_immext ();
3778
3779 /* For insns with operands there are more diddles to do to the opcode. */
3780 if (i.operands)
3781 {
3782 if (!process_operands ())
3783 return;
3784 }
3785 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3786 {
3787 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3788 as_warn (_("translating to `%sp'"), i.tm.name);
3789 }
3790
3791 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3792 {
3793 if (flag_code == CODE_16BIT)
3794 {
3795 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3796 i.tm.name);
3797 return;
3798 }
3799
3800 if (i.tm.opcode_modifier.vex)
3801 build_vex_prefix (t);
3802 else
3803 build_evex_prefix ();
3804 }
3805
3806 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3807 instructions may define INT_OPCODE as well, so avoid this corner
3808 case for those instructions that use MODRM. */
3809 if (i.tm.base_opcode == INT_OPCODE
3810 && !i.tm.opcode_modifier.modrm
3811 && i.op[0].imms->X_add_number == 3)
3812 {
3813 i.tm.base_opcode = INT3_OPCODE;
3814 i.imm_operands = 0;
3815 }
3816
3817 if ((i.tm.opcode_modifier.jump
3818 || i.tm.opcode_modifier.jumpbyte
3819 || i.tm.opcode_modifier.jumpdword)
3820 && i.op[0].disps->X_op == O_constant)
3821 {
3822 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3823 the absolute address given by the constant. Since ix86 jumps and
3824 calls are pc relative, we need to generate a reloc. */
3825 i.op[0].disps->X_add_symbol = &abs_symbol;
3826 i.op[0].disps->X_op = O_symbol;
3827 }
3828
3829 if (i.tm.opcode_modifier.rex64)
3830 i.rex |= REX_W;
3831
3832 /* For 8 bit registers we need an empty rex prefix. Also if the
3833 instruction already has a prefix, we need to convert old
3834 registers to new ones. */
3835
3836 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
3837 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3838 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
3839 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3840 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3841 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
3842 && i.rex != 0))
3843 {
3844 int x;
3845
3846 i.rex |= REX_OPCODE;
3847 for (x = 0; x < 2; x++)
3848 {
3849 /* Look for 8 bit operand that uses old registers. */
3850 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
3851 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3852 {
3853 /* In case it is "hi" register, give up. */
3854 if (i.op[x].regs->reg_num > 3)
3855 as_bad (_("can't encode register '%s%s' in an "
3856 "instruction requiring REX prefix."),
3857 register_prefix, i.op[x].regs->reg_name);
3858
3859 /* Otherwise it is equivalent to the extended register.
3860 Since the encoding doesn't change this is merely
3861 cosmetic cleanup for debug output. */
3862
3863 i.op[x].regs = i.op[x].regs + 8;
3864 }
3865 }
3866 }
3867
3868 if (i.rex != 0)
3869 add_prefix (REX_OPCODE | i.rex);
3870
3871 /* We are ready to output the insn. */
3872 output_insn ();
3873 }
3874
3875 static char *
3876 parse_insn (char *line, char *mnemonic)
3877 {
3878 char *l = line;
3879 char *token_start = l;
3880 char *mnem_p;
3881 int supported;
3882 const insn_template *t;
3883 char *dot_p = NULL;
3884
3885 while (1)
3886 {
3887 mnem_p = mnemonic;
3888 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3889 {
3890 if (*mnem_p == '.')
3891 dot_p = mnem_p;
3892 mnem_p++;
3893 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3894 {
3895 as_bad (_("no such instruction: `%s'"), token_start);
3896 return NULL;
3897 }
3898 l++;
3899 }
3900 if (!is_space_char (*l)
3901 && *l != END_OF_INSN
3902 && (intel_syntax
3903 || (*l != PREFIX_SEPARATOR
3904 && *l != ',')))
3905 {
3906 as_bad (_("invalid character %s in mnemonic"),
3907 output_invalid (*l));
3908 return NULL;
3909 }
3910 if (token_start == l)
3911 {
3912 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3913 as_bad (_("expecting prefix; got nothing"));
3914 else
3915 as_bad (_("expecting mnemonic; got nothing"));
3916 return NULL;
3917 }
3918
3919 /* Look up instruction (or prefix) via hash table. */
3920 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3921
3922 if (*l != END_OF_INSN
3923 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3924 && current_templates
3925 && current_templates->start->opcode_modifier.isprefix)
3926 {
3927 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3928 {
3929 as_bad ((flag_code != CODE_64BIT
3930 ? _("`%s' is only supported in 64-bit mode")
3931 : _("`%s' is not supported in 64-bit mode")),
3932 current_templates->start->name);
3933 return NULL;
3934 }
3935 /* If we are in 16-bit mode, do not allow addr16 or data16.
3936 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3937 if ((current_templates->start->opcode_modifier.size16
3938 || current_templates->start->opcode_modifier.size32)
3939 && flag_code != CODE_64BIT
3940 && (current_templates->start->opcode_modifier.size32
3941 ^ (flag_code == CODE_16BIT)))
3942 {
3943 as_bad (_("redundant %s prefix"),
3944 current_templates->start->name);
3945 return NULL;
3946 }
3947 if (current_templates->start->opcode_length == 0)
3948 {
3949 /* Handle pseudo prefixes. */
3950 switch (current_templates->start->base_opcode)
3951 {
3952 case 0x0:
3953 /* {disp8} */
3954 i.disp_encoding = disp_encoding_8bit;
3955 break;
3956 case 0x1:
3957 /* {disp32} */
3958 i.disp_encoding = disp_encoding_32bit;
3959 break;
3960 case 0x2:
3961 /* {load} */
3962 i.dir_encoding = dir_encoding_load;
3963 break;
3964 case 0x3:
3965 /* {store} */
3966 i.dir_encoding = dir_encoding_store;
3967 break;
3968 case 0x4:
3969 /* {vex2} */
3970 i.vec_encoding = vex_encoding_vex2;
3971 break;
3972 case 0x5:
3973 /* {vex3} */
3974 i.vec_encoding = vex_encoding_vex3;
3975 break;
3976 case 0x6:
3977 /* {evex} */
3978 i.vec_encoding = vex_encoding_evex;
3979 break;
3980 default:
3981 abort ();
3982 }
3983 }
3984 else
3985 {
3986 /* Add prefix, checking for repeated prefixes. */
3987 switch (add_prefix (current_templates->start->base_opcode))
3988 {
3989 case PREFIX_EXIST:
3990 return NULL;
3991 case PREFIX_DS:
3992 if (current_templates->start->cpu_flags.bitfield.cpucet)
3993 i.notrack_prefix = current_templates->start->name;
3994 break;
3995 case PREFIX_REP:
3996 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3997 i.hle_prefix = current_templates->start->name;
3998 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3999 i.bnd_prefix = current_templates->start->name;
4000 else
4001 i.rep_prefix = current_templates->start->name;
4002 break;
4003 default:
4004 break;
4005 }
4006 }
4007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4008 token_start = ++l;
4009 }
4010 else
4011 break;
4012 }
4013
4014 if (!current_templates)
4015 {
4016 /* Check if we should swap operand or force 32bit displacement in
4017 encoding. */
4018 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4019 i.dir_encoding = dir_encoding_store;
4020 else if (mnem_p - 3 == dot_p
4021 && dot_p[1] == 'd'
4022 && dot_p[2] == '8')
4023 i.disp_encoding = disp_encoding_8bit;
4024 else if (mnem_p - 4 == dot_p
4025 && dot_p[1] == 'd'
4026 && dot_p[2] == '3'
4027 && dot_p[3] == '2')
4028 i.disp_encoding = disp_encoding_32bit;
4029 else
4030 goto check_suffix;
4031 mnem_p = dot_p;
4032 *dot_p = '\0';
4033 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4034 }
4035
4036 if (!current_templates)
4037 {
4038 check_suffix:
4039 /* See if we can get a match by trimming off a suffix. */
4040 switch (mnem_p[-1])
4041 {
4042 case WORD_MNEM_SUFFIX:
4043 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4044 i.suffix = SHORT_MNEM_SUFFIX;
4045 else
4046 /* Fall through. */
4047 case BYTE_MNEM_SUFFIX:
4048 case QWORD_MNEM_SUFFIX:
4049 i.suffix = mnem_p[-1];
4050 mnem_p[-1] = '\0';
4051 current_templates = (const templates *) hash_find (op_hash,
4052 mnemonic);
4053 break;
4054 case SHORT_MNEM_SUFFIX:
4055 case LONG_MNEM_SUFFIX:
4056 if (!intel_syntax)
4057 {
4058 i.suffix = mnem_p[-1];
4059 mnem_p[-1] = '\0';
4060 current_templates = (const templates *) hash_find (op_hash,
4061 mnemonic);
4062 }
4063 break;
4064
4065 /* Intel Syntax. */
4066 case 'd':
4067 if (intel_syntax)
4068 {
4069 if (intel_float_operand (mnemonic) == 1)
4070 i.suffix = SHORT_MNEM_SUFFIX;
4071 else
4072 i.suffix = LONG_MNEM_SUFFIX;
4073 mnem_p[-1] = '\0';
4074 current_templates = (const templates *) hash_find (op_hash,
4075 mnemonic);
4076 }
4077 break;
4078 }
4079 if (!current_templates)
4080 {
4081 as_bad (_("no such instruction: `%s'"), token_start);
4082 return NULL;
4083 }
4084 }
4085
4086 if (current_templates->start->opcode_modifier.jump
4087 || current_templates->start->opcode_modifier.jumpbyte)
4088 {
4089 /* Check for a branch hint. We allow ",pt" and ",pn" for
4090 predict taken and predict not taken respectively.
4091 I'm not sure that branch hints actually do anything on loop
4092 and jcxz insns (JumpByte) for current Pentium4 chips. They
4093 may work in the future and it doesn't hurt to accept them
4094 now. */
4095 if (l[0] == ',' && l[1] == 'p')
4096 {
4097 if (l[2] == 't')
4098 {
4099 if (!add_prefix (DS_PREFIX_OPCODE))
4100 return NULL;
4101 l += 3;
4102 }
4103 else if (l[2] == 'n')
4104 {
4105 if (!add_prefix (CS_PREFIX_OPCODE))
4106 return NULL;
4107 l += 3;
4108 }
4109 }
4110 }
4111 /* Any other comma loses. */
4112 if (*l == ',')
4113 {
4114 as_bad (_("invalid character %s in mnemonic"),
4115 output_invalid (*l));
4116 return NULL;
4117 }
4118
4119 /* Check if instruction is supported on specified architecture. */
4120 supported = 0;
4121 for (t = current_templates->start; t < current_templates->end; ++t)
4122 {
4123 supported |= cpu_flags_match (t);
4124 if (supported == CPU_FLAGS_PERFECT_MATCH)
4125 goto skip;
4126 }
4127
4128 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4129 {
4130 as_bad (flag_code == CODE_64BIT
4131 ? _("`%s' is not supported in 64-bit mode")
4132 : _("`%s' is only supported in 64-bit mode"),
4133 current_templates->start->name);
4134 return NULL;
4135 }
4136 if (supported != CPU_FLAGS_PERFECT_MATCH)
4137 {
4138 as_bad (_("`%s' is not supported on `%s%s'"),
4139 current_templates->start->name,
4140 cpu_arch_name ? cpu_arch_name : default_arch,
4141 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4142 return NULL;
4143 }
4144
4145 skip:
4146 if (!cpu_arch_flags.bitfield.cpui386
4147 && (flag_code != CODE_16BIT))
4148 {
4149 as_warn (_("use .code16 to ensure correct addressing mode"));
4150 }
4151
4152 return l;
4153 }
4154
4155 static char *
4156 parse_operands (char *l, const char *mnemonic)
4157 {
4158 char *token_start;
4159
4160 /* 1 if operand is pending after ','. */
4161 unsigned int expecting_operand = 0;
4162
4163 /* Non-zero if operand parens not balanced. */
4164 unsigned int paren_not_balanced;
4165
4166 while (*l != END_OF_INSN)
4167 {
4168 /* Skip optional white space before operand. */
4169 if (is_space_char (*l))
4170 ++l;
4171 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4172 {
4173 as_bad (_("invalid character %s before operand %d"),
4174 output_invalid (*l),
4175 i.operands + 1);
4176 return NULL;
4177 }
4178 token_start = l; /* After white space. */
4179 paren_not_balanced = 0;
4180 while (paren_not_balanced || *l != ',')
4181 {
4182 if (*l == END_OF_INSN)
4183 {
4184 if (paren_not_balanced)
4185 {
4186 if (!intel_syntax)
4187 as_bad (_("unbalanced parenthesis in operand %d."),
4188 i.operands + 1);
4189 else
4190 as_bad (_("unbalanced brackets in operand %d."),
4191 i.operands + 1);
4192 return NULL;
4193 }
4194 else
4195 break; /* we are done */
4196 }
4197 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4198 {
4199 as_bad (_("invalid character %s in operand %d"),
4200 output_invalid (*l),
4201 i.operands + 1);
4202 return NULL;
4203 }
4204 if (!intel_syntax)
4205 {
4206 if (*l == '(')
4207 ++paren_not_balanced;
4208 if (*l == ')')
4209 --paren_not_balanced;
4210 }
4211 else
4212 {
4213 if (*l == '[')
4214 ++paren_not_balanced;
4215 if (*l == ']')
4216 --paren_not_balanced;
4217 }
4218 l++;
4219 }
4220 if (l != token_start)
4221 { /* Yes, we've read in another operand. */
4222 unsigned int operand_ok;
4223 this_operand = i.operands++;
4224 if (i.operands > MAX_OPERANDS)
4225 {
4226 as_bad (_("spurious operands; (%d operands/instruction max)"),
4227 MAX_OPERANDS);
4228 return NULL;
4229 }
4230 i.types[this_operand].bitfield.unspecified = 1;
4231 /* Now parse operand adding info to 'i' as we go along. */
4232 END_STRING_AND_SAVE (l);
4233
4234 if (intel_syntax)
4235 operand_ok =
4236 i386_intel_operand (token_start,
4237 intel_float_operand (mnemonic));
4238 else
4239 operand_ok = i386_att_operand (token_start);
4240
4241 RESTORE_END_STRING (l);
4242 if (!operand_ok)
4243 return NULL;
4244 }
4245 else
4246 {
4247 if (expecting_operand)
4248 {
4249 expecting_operand_after_comma:
4250 as_bad (_("expecting operand after ','; got nothing"));
4251 return NULL;
4252 }
4253 if (*l == ',')
4254 {
4255 as_bad (_("expecting operand before ','; got nothing"));
4256 return NULL;
4257 }
4258 }
4259
4260 /* Now *l must be either ',' or END_OF_INSN. */
4261 if (*l == ',')
4262 {
4263 if (*++l == END_OF_INSN)
4264 {
4265 /* Just skip it, if it's \n complain. */
4266 goto expecting_operand_after_comma;
4267 }
4268 expecting_operand = 1;
4269 }
4270 }
4271 return l;
4272 }
4273
4274 static void
4275 swap_2_operands (int xchg1, int xchg2)
4276 {
4277 union i386_op temp_op;
4278 i386_operand_type temp_type;
4279 enum bfd_reloc_code_real temp_reloc;
4280
4281 temp_type = i.types[xchg2];
4282 i.types[xchg2] = i.types[xchg1];
4283 i.types[xchg1] = temp_type;
4284 temp_op = i.op[xchg2];
4285 i.op[xchg2] = i.op[xchg1];
4286 i.op[xchg1] = temp_op;
4287 temp_reloc = i.reloc[xchg2];
4288 i.reloc[xchg2] = i.reloc[xchg1];
4289 i.reloc[xchg1] = temp_reloc;
4290
4291 if (i.mask)
4292 {
4293 if (i.mask->operand == xchg1)
4294 i.mask->operand = xchg2;
4295 else if (i.mask->operand == xchg2)
4296 i.mask->operand = xchg1;
4297 }
4298 if (i.broadcast)
4299 {
4300 if (i.broadcast->operand == xchg1)
4301 i.broadcast->operand = xchg2;
4302 else if (i.broadcast->operand == xchg2)
4303 i.broadcast->operand = xchg1;
4304 }
4305 if (i.rounding)
4306 {
4307 if (i.rounding->operand == xchg1)
4308 i.rounding->operand = xchg2;
4309 else if (i.rounding->operand == xchg2)
4310 i.rounding->operand = xchg1;
4311 }
4312 }
4313
4314 static void
4315 swap_operands (void)
4316 {
4317 switch (i.operands)
4318 {
4319 case 5:
4320 case 4:
4321 swap_2_operands (1, i.operands - 2);
4322 /* Fall through. */
4323 case 3:
4324 case 2:
4325 swap_2_operands (0, i.operands - 1);
4326 break;
4327 default:
4328 abort ();
4329 }
4330
4331 if (i.mem_operands == 2)
4332 {
4333 const seg_entry *temp_seg;
4334 temp_seg = i.seg[0];
4335 i.seg[0] = i.seg[1];
4336 i.seg[1] = temp_seg;
4337 }
4338 }
4339
4340 /* Try to ensure constant immediates are represented in the smallest
4341 opcode possible. */
4342 static void
4343 optimize_imm (void)
4344 {
4345 char guess_suffix = 0;
4346 int op;
4347
4348 if (i.suffix)
4349 guess_suffix = i.suffix;
4350 else if (i.reg_operands)
4351 {
4352 /* Figure out a suffix from the last register operand specified.
4353 We can't do this properly yet, ie. excluding InOutPortReg,
4354 but the following works for instructions with immediates.
4355 In any case, we can't set i.suffix yet. */
4356 for (op = i.operands; --op >= 0;)
4357 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4358 {
4359 guess_suffix = BYTE_MNEM_SUFFIX;
4360 break;
4361 }
4362 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4363 {
4364 guess_suffix = WORD_MNEM_SUFFIX;
4365 break;
4366 }
4367 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4368 {
4369 guess_suffix = LONG_MNEM_SUFFIX;
4370 break;
4371 }
4372 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4373 {
4374 guess_suffix = QWORD_MNEM_SUFFIX;
4375 break;
4376 }
4377 }
4378 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4379 guess_suffix = WORD_MNEM_SUFFIX;
4380
4381 for (op = i.operands; --op >= 0;)
4382 if (operand_type_check (i.types[op], imm))
4383 {
4384 switch (i.op[op].imms->X_op)
4385 {
4386 case O_constant:
4387 /* If a suffix is given, this operand may be shortened. */
4388 switch (guess_suffix)
4389 {
4390 case LONG_MNEM_SUFFIX:
4391 i.types[op].bitfield.imm32 = 1;
4392 i.types[op].bitfield.imm64 = 1;
4393 break;
4394 case WORD_MNEM_SUFFIX:
4395 i.types[op].bitfield.imm16 = 1;
4396 i.types[op].bitfield.imm32 = 1;
4397 i.types[op].bitfield.imm32s = 1;
4398 i.types[op].bitfield.imm64 = 1;
4399 break;
4400 case BYTE_MNEM_SUFFIX:
4401 i.types[op].bitfield.imm8 = 1;
4402 i.types[op].bitfield.imm8s = 1;
4403 i.types[op].bitfield.imm16 = 1;
4404 i.types[op].bitfield.imm32 = 1;
4405 i.types[op].bitfield.imm32s = 1;
4406 i.types[op].bitfield.imm64 = 1;
4407 break;
4408 }
4409
4410 /* If this operand is at most 16 bits, convert it
4411 to a signed 16 bit number before trying to see
4412 whether it will fit in an even smaller size.
4413 This allows a 16-bit operand such as $0xffe0 to
4414 be recognised as within Imm8S range. */
4415 if ((i.types[op].bitfield.imm16)
4416 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4417 {
4418 i.op[op].imms->X_add_number =
4419 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4420 }
4421 #ifdef BFD64
4422 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4423 if ((i.types[op].bitfield.imm32)
4424 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4425 == 0))
4426 {
4427 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4428 ^ ((offsetT) 1 << 31))
4429 - ((offsetT) 1 << 31));
4430 }
4431 #endif
4432 i.types[op]
4433 = operand_type_or (i.types[op],
4434 smallest_imm_type (i.op[op].imms->X_add_number));
4435
4436 /* We must avoid matching of Imm32 templates when 64bit
4437 only immediate is available. */
4438 if (guess_suffix == QWORD_MNEM_SUFFIX)
4439 i.types[op].bitfield.imm32 = 0;
4440 break;
4441
4442 case O_absent:
4443 case O_register:
4444 abort ();
4445
4446 /* Symbols and expressions. */
4447 default:
4448 /* Convert symbolic operand to proper sizes for matching, but don't
4449 prevent matching a set of insns that only supports sizes other
4450 than those matching the insn suffix. */
4451 {
4452 i386_operand_type mask, allowed;
4453 const insn_template *t;
4454
4455 operand_type_set (&mask, 0);
4456 operand_type_set (&allowed, 0);
4457
4458 for (t = current_templates->start;
4459 t < current_templates->end;
4460 ++t)
4461 allowed = operand_type_or (allowed,
4462 t->operand_types[op]);
4463 switch (guess_suffix)
4464 {
4465 case QWORD_MNEM_SUFFIX:
4466 mask.bitfield.imm64 = 1;
4467 mask.bitfield.imm32s = 1;
4468 break;
4469 case LONG_MNEM_SUFFIX:
4470 mask.bitfield.imm32 = 1;
4471 break;
4472 case WORD_MNEM_SUFFIX:
4473 mask.bitfield.imm16 = 1;
4474 break;
4475 case BYTE_MNEM_SUFFIX:
4476 mask.bitfield.imm8 = 1;
4477 break;
4478 default:
4479 break;
4480 }
4481 allowed = operand_type_and (mask, allowed);
4482 if (!operand_type_all_zero (&allowed))
4483 i.types[op] = operand_type_and (i.types[op], mask);
4484 }
4485 break;
4486 }
4487 }
4488 }
4489
4490 /* Try to use the smallest displacement type too. */
4491 static void
4492 optimize_disp (void)
4493 {
4494 int op;
4495
4496 for (op = i.operands; --op >= 0;)
4497 if (operand_type_check (i.types[op], disp))
4498 {
4499 if (i.op[op].disps->X_op == O_constant)
4500 {
4501 offsetT op_disp = i.op[op].disps->X_add_number;
4502
4503 if (i.types[op].bitfield.disp16
4504 && (op_disp & ~(offsetT) 0xffff) == 0)
4505 {
4506 /* If this operand is at most 16 bits, convert
4507 to a signed 16 bit number and don't use 64bit
4508 displacement. */
4509 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4510 i.types[op].bitfield.disp64 = 0;
4511 }
4512 #ifdef BFD64
4513 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4514 if (i.types[op].bitfield.disp32
4515 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4516 {
4517 /* If this operand is at most 32 bits, convert
4518 to a signed 32 bit number and don't use 64bit
4519 displacement. */
4520 op_disp &= (((offsetT) 2 << 31) - 1);
4521 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4522 i.types[op].bitfield.disp64 = 0;
4523 }
4524 #endif
4525 if (!op_disp && i.types[op].bitfield.baseindex)
4526 {
4527 i.types[op].bitfield.disp8 = 0;
4528 i.types[op].bitfield.disp16 = 0;
4529 i.types[op].bitfield.disp32 = 0;
4530 i.types[op].bitfield.disp32s = 0;
4531 i.types[op].bitfield.disp64 = 0;
4532 i.op[op].disps = 0;
4533 i.disp_operands--;
4534 }
4535 else if (flag_code == CODE_64BIT)
4536 {
4537 if (fits_in_signed_long (op_disp))
4538 {
4539 i.types[op].bitfield.disp64 = 0;
4540 i.types[op].bitfield.disp32s = 1;
4541 }
4542 if (i.prefix[ADDR_PREFIX]
4543 && fits_in_unsigned_long (op_disp))
4544 i.types[op].bitfield.disp32 = 1;
4545 }
4546 if ((i.types[op].bitfield.disp32
4547 || i.types[op].bitfield.disp32s
4548 || i.types[op].bitfield.disp16)
4549 && fits_in_disp8 (op_disp))
4550 i.types[op].bitfield.disp8 = 1;
4551 }
4552 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4553 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4554 {
4555 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4556 i.op[op].disps, 0, i.reloc[op]);
4557 i.types[op].bitfield.disp8 = 0;
4558 i.types[op].bitfield.disp16 = 0;
4559 i.types[op].bitfield.disp32 = 0;
4560 i.types[op].bitfield.disp32s = 0;
4561 i.types[op].bitfield.disp64 = 0;
4562 }
4563 else
4564 /* We only support 64bit displacement on constants. */
4565 i.types[op].bitfield.disp64 = 0;
4566 }
4567 }
4568
4569 /* Check if operands are valid for the instruction. */
4570
4571 static int
4572 check_VecOperands (const insn_template *t)
4573 {
4574 unsigned int op;
4575
4576 /* Without VSIB byte, we can't have a vector register for index. */
4577 if (!t->opcode_modifier.vecsib
4578 && i.index_reg
4579 && (i.index_reg->reg_type.bitfield.regxmm
4580 || i.index_reg->reg_type.bitfield.regymm
4581 || i.index_reg->reg_type.bitfield.regzmm))
4582 {
4583 i.error = unsupported_vector_index_register;
4584 return 1;
4585 }
4586
4587 /* Check if default mask is allowed. */
4588 if (t->opcode_modifier.nodefmask
4589 && (!i.mask || i.mask->mask->reg_num == 0))
4590 {
4591 i.error = no_default_mask;
4592 return 1;
4593 }
4594
4595 /* For VSIB byte, we need a vector register for index, and all vector
4596 registers must be distinct. */
4597 if (t->opcode_modifier.vecsib)
4598 {
4599 if (!i.index_reg
4600 || !((t->opcode_modifier.vecsib == VecSIB128
4601 && i.index_reg->reg_type.bitfield.regxmm)
4602 || (t->opcode_modifier.vecsib == VecSIB256
4603 && i.index_reg->reg_type.bitfield.regymm)
4604 || (t->opcode_modifier.vecsib == VecSIB512
4605 && i.index_reg->reg_type.bitfield.regzmm)))
4606 {
4607 i.error = invalid_vsib_address;
4608 return 1;
4609 }
4610
4611 gas_assert (i.reg_operands == 2 || i.mask);
4612 if (i.reg_operands == 2 && !i.mask)
4613 {
4614 gas_assert (i.types[0].bitfield.regxmm
4615 || i.types[0].bitfield.regymm);
4616 gas_assert (i.types[2].bitfield.regxmm
4617 || i.types[2].bitfield.regymm);
4618 if (operand_check == check_none)
4619 return 0;
4620 if (register_number (i.op[0].regs)
4621 != register_number (i.index_reg)
4622 && register_number (i.op[2].regs)
4623 != register_number (i.index_reg)
4624 && register_number (i.op[0].regs)
4625 != register_number (i.op[2].regs))
4626 return 0;
4627 if (operand_check == check_error)
4628 {
4629 i.error = invalid_vector_register_set;
4630 return 1;
4631 }
4632 as_warn (_("mask, index, and destination registers should be distinct"));
4633 }
4634 else if (i.reg_operands == 1 && i.mask)
4635 {
4636 if ((i.types[1].bitfield.regxmm
4637 || i.types[1].bitfield.regymm
4638 || i.types[1].bitfield.regzmm)
4639 && (register_number (i.op[1].regs)
4640 == register_number (i.index_reg)))
4641 {
4642 if (operand_check == check_error)
4643 {
4644 i.error = invalid_vector_register_set;
4645 return 1;
4646 }
4647 if (operand_check != check_none)
4648 as_warn (_("index and destination registers should be distinct"));
4649 }
4650 }
4651 }
4652
4653 /* Check if broadcast is supported by the instruction and is applied
4654 to the memory operand. */
4655 if (i.broadcast)
4656 {
4657 int broadcasted_opnd_size;
4658
4659 /* Check if specified broadcast is supported in this instruction,
4660 and it's applied to memory operand of DWORD or QWORD type,
4661 depending on VecESize. */
4662 if (i.broadcast->type != t->opcode_modifier.broadcast
4663 || !i.types[i.broadcast->operand].bitfield.mem
4664 || (t->opcode_modifier.vecesize == 0
4665 && !i.types[i.broadcast->operand].bitfield.dword
4666 && !i.types[i.broadcast->operand].bitfield.unspecified)
4667 || (t->opcode_modifier.vecesize == 1
4668 && !i.types[i.broadcast->operand].bitfield.qword
4669 && !i.types[i.broadcast->operand].bitfield.unspecified))
4670 goto bad_broadcast;
4671
4672 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4673 if (i.broadcast->type == BROADCAST_1TO16)
4674 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4675 else if (i.broadcast->type == BROADCAST_1TO8)
4676 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4677 else if (i.broadcast->type == BROADCAST_1TO4)
4678 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4679 else if (i.broadcast->type == BROADCAST_1TO2)
4680 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4681 else
4682 goto bad_broadcast;
4683
4684 if ((broadcasted_opnd_size == 256
4685 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4686 || (broadcasted_opnd_size == 512
4687 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4688 {
4689 bad_broadcast:
4690 i.error = unsupported_broadcast;
4691 return 1;
4692 }
4693 }
4694 /* If broadcast is supported in this instruction, we need to check if
4695 operand of one-element size isn't specified without broadcast. */
4696 else if (t->opcode_modifier.broadcast && i.mem_operands)
4697 {
4698 /* Find memory operand. */
4699 for (op = 0; op < i.operands; op++)
4700 if (operand_type_check (i.types[op], anymem))
4701 break;
4702 gas_assert (op < i.operands);
4703 /* Check size of the memory operand. */
4704 if ((t->opcode_modifier.vecesize == 0
4705 && i.types[op].bitfield.dword)
4706 || (t->opcode_modifier.vecesize == 1
4707 && i.types[op].bitfield.qword))
4708 {
4709 i.error = broadcast_needed;
4710 return 1;
4711 }
4712 }
4713
4714 /* Check if requested masking is supported. */
4715 if (i.mask
4716 && (!t->opcode_modifier.masking
4717 || (i.mask->zeroing
4718 && t->opcode_modifier.masking == MERGING_MASKING)))
4719 {
4720 i.error = unsupported_masking;
4721 return 1;
4722 }
4723
4724 /* Check if masking is applied to dest operand. */
4725 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4726 {
4727 i.error = mask_not_on_destination;
4728 return 1;
4729 }
4730
4731 /* Check RC/SAE. */
4732 if (i.rounding)
4733 {
4734 if ((i.rounding->type != saeonly
4735 && !t->opcode_modifier.staticrounding)
4736 || (i.rounding->type == saeonly
4737 && (t->opcode_modifier.staticrounding
4738 || !t->opcode_modifier.sae)))
4739 {
4740 i.error = unsupported_rc_sae;
4741 return 1;
4742 }
4743 /* If the instruction has several immediate operands and one of
4744 them is rounding, the rounding operand should be the last
4745 immediate operand. */
4746 if (i.imm_operands > 1
4747 && i.rounding->operand != (int) (i.imm_operands - 1))
4748 {
4749 i.error = rc_sae_operand_not_last_imm;
4750 return 1;
4751 }
4752 }
4753
4754 /* Check vector Disp8 operand. */
4755 if (t->opcode_modifier.disp8memshift
4756 && i.disp_encoding != disp_encoding_32bit)
4757 {
4758 if (i.broadcast)
4759 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4760 else
4761 i.memshift = t->opcode_modifier.disp8memshift;
4762
4763 for (op = 0; op < i.operands; op++)
4764 if (operand_type_check (i.types[op], disp)
4765 && i.op[op].disps->X_op == O_constant)
4766 {
4767 if (fits_in_disp8 (i.op[op].disps->X_add_number))
4768 {
4769 i.types[op].bitfield.disp8 = 1;
4770 return 0;
4771 }
4772 i.types[op].bitfield.disp8 = 0;
4773 }
4774 }
4775
4776 i.memshift = 0;
4777
4778 return 0;
4779 }
4780
4781 /* Check if operands are valid for the instruction. Update VEX
4782 operand types. */
4783
4784 static int
4785 VEX_check_operands (const insn_template *t)
4786 {
4787 if (i.vec_encoding == vex_encoding_evex)
4788 {
4789 /* This instruction must be encoded with EVEX prefix. */
4790 if (!t->opcode_modifier.evex)
4791 {
4792 i.error = unsupported;
4793 return 1;
4794 }
4795 return 0;
4796 }
4797
4798 if (!t->opcode_modifier.vex)
4799 {
4800 /* This instruction template doesn't have VEX prefix. */
4801 if (i.vec_encoding != vex_encoding_default)
4802 {
4803 i.error = unsupported;
4804 return 1;
4805 }
4806 return 0;
4807 }
4808
4809 /* Only check VEX_Imm4, which must be the first operand. */
4810 if (t->operand_types[0].bitfield.vec_imm4)
4811 {
4812 if (i.op[0].imms->X_op != O_constant
4813 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4814 {
4815 i.error = bad_imm4;
4816 return 1;
4817 }
4818
4819 /* Turn off Imm8 so that update_imm won't complain. */
4820 i.types[0] = vec_imm4;
4821 }
4822
4823 return 0;
4824 }
4825
4826 static const insn_template *
4827 match_template (char mnem_suffix)
4828 {
4829 /* Points to template once we've found it. */
4830 const insn_template *t;
4831 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4832 i386_operand_type overlap4;
4833 unsigned int found_reverse_match;
4834 i386_opcode_modifier suffix_check, mnemsuf_check;
4835 i386_operand_type operand_types [MAX_OPERANDS];
4836 int addr_prefix_disp;
4837 unsigned int j;
4838 unsigned int found_cpu_match;
4839 unsigned int check_register;
4840 enum i386_error specific_error = 0;
4841
4842 #if MAX_OPERANDS != 5
4843 # error "MAX_OPERANDS must be 5."
4844 #endif
4845
4846 found_reverse_match = 0;
4847 addr_prefix_disp = -1;
4848
4849 memset (&suffix_check, 0, sizeof (suffix_check));
4850 if (i.suffix == BYTE_MNEM_SUFFIX)
4851 suffix_check.no_bsuf = 1;
4852 else if (i.suffix == WORD_MNEM_SUFFIX)
4853 suffix_check.no_wsuf = 1;
4854 else if (i.suffix == SHORT_MNEM_SUFFIX)
4855 suffix_check.no_ssuf = 1;
4856 else if (i.suffix == LONG_MNEM_SUFFIX)
4857 suffix_check.no_lsuf = 1;
4858 else if (i.suffix == QWORD_MNEM_SUFFIX)
4859 suffix_check.no_qsuf = 1;
4860 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4861 suffix_check.no_ldsuf = 1;
4862
4863 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4864 if (intel_syntax)
4865 {
4866 switch (mnem_suffix)
4867 {
4868 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4869 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4870 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4871 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4872 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4873 }
4874 }
4875
4876 /* Must have right number of operands. */
4877 i.error = number_of_operands_mismatch;
4878
4879 for (t = current_templates->start; t < current_templates->end; t++)
4880 {
4881 addr_prefix_disp = -1;
4882
4883 if (i.operands != t->operands)
4884 continue;
4885
4886 /* Check processor support. */
4887 i.error = unsupported;
4888 found_cpu_match = (cpu_flags_match (t)
4889 == CPU_FLAGS_PERFECT_MATCH);
4890 if (!found_cpu_match)
4891 continue;
4892
4893 /* Check old gcc support. */
4894 i.error = old_gcc_only;
4895 if (!old_gcc && t->opcode_modifier.oldgcc)
4896 continue;
4897
4898 /* Check AT&T mnemonic. */
4899 i.error = unsupported_with_intel_mnemonic;
4900 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4901 continue;
4902
4903 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4904 i.error = unsupported_syntax;
4905 if ((intel_syntax && t->opcode_modifier.attsyntax)
4906 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4907 || (intel64 && t->opcode_modifier.amd64)
4908 || (!intel64 && t->opcode_modifier.intel64))
4909 continue;
4910
4911 /* Check the suffix, except for some instructions in intel mode. */
4912 i.error = invalid_instruction_suffix;
4913 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4914 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4915 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4916 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4917 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4918 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4919 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4920 continue;
4921 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4922 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4923 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4924 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4925 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4926 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4927 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4928 continue;
4929
4930 if (!operand_size_match (t))
4931 continue;
4932
4933 for (j = 0; j < MAX_OPERANDS; j++)
4934 operand_types[j] = t->operand_types[j];
4935
4936 /* In general, don't allow 64-bit operands in 32-bit mode. */
4937 if (i.suffix == QWORD_MNEM_SUFFIX
4938 && flag_code != CODE_64BIT
4939 && (intel_syntax
4940 ? (!t->opcode_modifier.ignoresize
4941 && !intel_float_operand (t->name))
4942 : intel_float_operand (t->name) != 2)
4943 && ((!operand_types[0].bitfield.regmmx
4944 && !operand_types[0].bitfield.regxmm
4945 && !operand_types[0].bitfield.regymm
4946 && !operand_types[0].bitfield.regzmm)
4947 || (!operand_types[t->operands > 1].bitfield.regmmx
4948 && !operand_types[t->operands > 1].bitfield.regxmm
4949 && !operand_types[t->operands > 1].bitfield.regymm
4950 && !operand_types[t->operands > 1].bitfield.regzmm))
4951 && (t->base_opcode != 0x0fc7
4952 || t->extension_opcode != 1 /* cmpxchg8b */))
4953 continue;
4954
4955 /* In general, don't allow 32-bit operands on pre-386. */
4956 else if (i.suffix == LONG_MNEM_SUFFIX
4957 && !cpu_arch_flags.bitfield.cpui386
4958 && (intel_syntax
4959 ? (!t->opcode_modifier.ignoresize
4960 && !intel_float_operand (t->name))
4961 : intel_float_operand (t->name) != 2)
4962 && ((!operand_types[0].bitfield.regmmx
4963 && !operand_types[0].bitfield.regxmm)
4964 || (!operand_types[t->operands > 1].bitfield.regmmx
4965 && !operand_types[t->operands > 1].bitfield.regxmm)))
4966 continue;
4967
4968 /* Do not verify operands when there are none. */
4969 else
4970 {
4971 if (!t->operands)
4972 /* We've found a match; break out of loop. */
4973 break;
4974 }
4975
4976 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4977 into Disp32/Disp16/Disp32 operand. */
4978 if (i.prefix[ADDR_PREFIX] != 0)
4979 {
4980 /* There should be only one Disp operand. */
4981 switch (flag_code)
4982 {
4983 case CODE_16BIT:
4984 for (j = 0; j < MAX_OPERANDS; j++)
4985 {
4986 if (operand_types[j].bitfield.disp16)
4987 {
4988 addr_prefix_disp = j;
4989 operand_types[j].bitfield.disp32 = 1;
4990 operand_types[j].bitfield.disp16 = 0;
4991 break;
4992 }
4993 }
4994 break;
4995 case CODE_32BIT:
4996 for (j = 0; j < MAX_OPERANDS; j++)
4997 {
4998 if (operand_types[j].bitfield.disp32)
4999 {
5000 addr_prefix_disp = j;
5001 operand_types[j].bitfield.disp32 = 0;
5002 operand_types[j].bitfield.disp16 = 1;
5003 break;
5004 }
5005 }
5006 break;
5007 case CODE_64BIT:
5008 for (j = 0; j < MAX_OPERANDS; j++)
5009 {
5010 if (operand_types[j].bitfield.disp64)
5011 {
5012 addr_prefix_disp = j;
5013 operand_types[j].bitfield.disp64 = 0;
5014 operand_types[j].bitfield.disp32 = 1;
5015 break;
5016 }
5017 }
5018 break;
5019 }
5020 }
5021
5022 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5023 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5024 continue;
5025
5026 /* We check register size if needed. */
5027 check_register = t->opcode_modifier.checkregsize;
5028 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5029 switch (t->operands)
5030 {
5031 case 1:
5032 if (!operand_type_match (overlap0, i.types[0]))
5033 continue;
5034 break;
5035 case 2:
5036 /* xchg %eax, %eax is a special case. It is an alias for nop
5037 only in 32bit mode and we can use opcode 0x90. In 64bit
5038 mode, we can't use 0x90 for xchg %eax, %eax since it should
5039 zero-extend %eax to %rax. */
5040 if (flag_code == CODE_64BIT
5041 && t->base_opcode == 0x90
5042 && operand_type_equal (&i.types [0], &acc32)
5043 && operand_type_equal (&i.types [1], &acc32))
5044 continue;
5045 /* If we want store form, we reverse direction of operands. */
5046 if (i.dir_encoding == dir_encoding_store
5047 && t->opcode_modifier.d)
5048 goto check_reverse;
5049 /* Fall through. */
5050
5051 case 3:
5052 /* If we want store form, we skip the current load. */
5053 if (i.dir_encoding == dir_encoding_store
5054 && i.mem_operands == 0
5055 && t->opcode_modifier.load)
5056 continue;
5057 /* Fall through. */
5058 case 4:
5059 case 5:
5060 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5061 if (!operand_type_match (overlap0, i.types[0])
5062 || !operand_type_match (overlap1, i.types[1])
5063 || (check_register
5064 && !operand_type_register_match (i.types[0],
5065 operand_types[0],
5066 i.types[1],
5067 operand_types[1])))
5068 {
5069 /* Check if other direction is valid ... */
5070 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5071 continue;
5072
5073 check_reverse:
5074 /* Try reversing direction of operands. */
5075 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5076 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5077 if (!operand_type_match (overlap0, i.types[0])
5078 || !operand_type_match (overlap1, i.types[1])
5079 || (check_register
5080 && !operand_type_register_match (i.types[0],
5081 operand_types[1],
5082 i.types[1],
5083 operand_types[0])))
5084 {
5085 /* Does not match either direction. */
5086 continue;
5087 }
5088 /* found_reverse_match holds which of D or FloatDR
5089 we've found. */
5090 if (t->opcode_modifier.d)
5091 found_reverse_match = Opcode_D;
5092 else if (t->opcode_modifier.floatd)
5093 found_reverse_match = Opcode_FloatD;
5094 else
5095 found_reverse_match = 0;
5096 if (t->opcode_modifier.floatr)
5097 found_reverse_match |= Opcode_FloatR;
5098 }
5099 else
5100 {
5101 /* Found a forward 2 operand match here. */
5102 switch (t->operands)
5103 {
5104 case 5:
5105 overlap4 = operand_type_and (i.types[4],
5106 operand_types[4]);
5107 /* Fall through. */
5108 case 4:
5109 overlap3 = operand_type_and (i.types[3],
5110 operand_types[3]);
5111 /* Fall through. */
5112 case 3:
5113 overlap2 = operand_type_and (i.types[2],
5114 operand_types[2]);
5115 break;
5116 }
5117
5118 switch (t->operands)
5119 {
5120 case 5:
5121 if (!operand_type_match (overlap4, i.types[4])
5122 || !operand_type_register_match (i.types[3],
5123 operand_types[3],
5124 i.types[4],
5125 operand_types[4]))
5126 continue;
5127 /* Fall through. */
5128 case 4:
5129 if (!operand_type_match (overlap3, i.types[3])
5130 || (check_register
5131 && !operand_type_register_match (i.types[2],
5132 operand_types[2],
5133 i.types[3],
5134 operand_types[3])))
5135 continue;
5136 /* Fall through. */
5137 case 3:
5138 /* Here we make use of the fact that there are no
5139 reverse match 3 operand instructions, and all 3
5140 operand instructions only need to be checked for
5141 register consistency between operands 2 and 3. */
5142 if (!operand_type_match (overlap2, i.types[2])
5143 || (check_register
5144 && !operand_type_register_match (i.types[1],
5145 operand_types[1],
5146 i.types[2],
5147 operand_types[2])))
5148 continue;
5149 break;
5150 }
5151 }
5152 /* Found either forward/reverse 2, 3 or 4 operand match here:
5153 slip through to break. */
5154 }
5155 if (!found_cpu_match)
5156 {
5157 found_reverse_match = 0;
5158 continue;
5159 }
5160
5161 /* Check if vector and VEX operands are valid. */
5162 if (check_VecOperands (t) || VEX_check_operands (t))
5163 {
5164 specific_error = i.error;
5165 continue;
5166 }
5167
5168 /* We've found a match; break out of loop. */
5169 break;
5170 }
5171
5172 if (t == current_templates->end)
5173 {
5174 /* We found no match. */
5175 const char *err_msg;
5176 switch (specific_error ? specific_error : i.error)
5177 {
5178 default:
5179 abort ();
5180 case operand_size_mismatch:
5181 err_msg = _("operand size mismatch");
5182 break;
5183 case operand_type_mismatch:
5184 err_msg = _("operand type mismatch");
5185 break;
5186 case register_type_mismatch:
5187 err_msg = _("register type mismatch");
5188 break;
5189 case number_of_operands_mismatch:
5190 err_msg = _("number of operands mismatch");
5191 break;
5192 case invalid_instruction_suffix:
5193 err_msg = _("invalid instruction suffix");
5194 break;
5195 case bad_imm4:
5196 err_msg = _("constant doesn't fit in 4 bits");
5197 break;
5198 case old_gcc_only:
5199 err_msg = _("only supported with old gcc");
5200 break;
5201 case unsupported_with_intel_mnemonic:
5202 err_msg = _("unsupported with Intel mnemonic");
5203 break;
5204 case unsupported_syntax:
5205 err_msg = _("unsupported syntax");
5206 break;
5207 case unsupported:
5208 as_bad (_("unsupported instruction `%s'"),
5209 current_templates->start->name);
5210 return NULL;
5211 case invalid_vsib_address:
5212 err_msg = _("invalid VSIB address");
5213 break;
5214 case invalid_vector_register_set:
5215 err_msg = _("mask, index, and destination registers must be distinct");
5216 break;
5217 case unsupported_vector_index_register:
5218 err_msg = _("unsupported vector index register");
5219 break;
5220 case unsupported_broadcast:
5221 err_msg = _("unsupported broadcast");
5222 break;
5223 case broadcast_not_on_src_operand:
5224 err_msg = _("broadcast not on source memory operand");
5225 break;
5226 case broadcast_needed:
5227 err_msg = _("broadcast is needed for operand of such type");
5228 break;
5229 case unsupported_masking:
5230 err_msg = _("unsupported masking");
5231 break;
5232 case mask_not_on_destination:
5233 err_msg = _("mask not on destination operand");
5234 break;
5235 case no_default_mask:
5236 err_msg = _("default mask isn't allowed");
5237 break;
5238 case unsupported_rc_sae:
5239 err_msg = _("unsupported static rounding/sae");
5240 break;
5241 case rc_sae_operand_not_last_imm:
5242 if (intel_syntax)
5243 err_msg = _("RC/SAE operand must precede immediate operands");
5244 else
5245 err_msg = _("RC/SAE operand must follow immediate operands");
5246 break;
5247 case invalid_register_operand:
5248 err_msg = _("invalid register operand");
5249 break;
5250 }
5251 as_bad (_("%s for `%s'"), err_msg,
5252 current_templates->start->name);
5253 return NULL;
5254 }
5255
5256 if (!quiet_warnings)
5257 {
5258 if (!intel_syntax
5259 && (i.types[0].bitfield.jumpabsolute
5260 != operand_types[0].bitfield.jumpabsolute))
5261 {
5262 as_warn (_("indirect %s without `*'"), t->name);
5263 }
5264
5265 if (t->opcode_modifier.isprefix
5266 && t->opcode_modifier.ignoresize)
5267 {
5268 /* Warn them that a data or address size prefix doesn't
5269 affect assembly of the next line of code. */
5270 as_warn (_("stand-alone `%s' prefix"), t->name);
5271 }
5272 }
5273
5274 /* Copy the template we found. */
5275 i.tm = *t;
5276
5277 if (addr_prefix_disp != -1)
5278 i.tm.operand_types[addr_prefix_disp]
5279 = operand_types[addr_prefix_disp];
5280
5281 if (found_reverse_match)
5282 {
5283 /* If we found a reverse match we must alter the opcode
5284 direction bit. found_reverse_match holds bits to change
5285 (different for int & float insns). */
5286
5287 i.tm.base_opcode ^= found_reverse_match;
5288
5289 i.tm.operand_types[0] = operand_types[1];
5290 i.tm.operand_types[1] = operand_types[0];
5291 }
5292
5293 return t;
5294 }
5295
5296 static int
5297 check_string (void)
5298 {
5299 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5300 if (i.tm.operand_types[mem_op].bitfield.esseg)
5301 {
5302 if (i.seg[0] != NULL && i.seg[0] != &es)
5303 {
5304 as_bad (_("`%s' operand %d must use `%ses' segment"),
5305 i.tm.name,
5306 mem_op + 1,
5307 register_prefix);
5308 return 0;
5309 }
5310 /* There's only ever one segment override allowed per instruction.
5311 This instruction possibly has a legal segment override on the
5312 second operand, so copy the segment to where non-string
5313 instructions store it, allowing common code. */
5314 i.seg[0] = i.seg[1];
5315 }
5316 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5317 {
5318 if (i.seg[1] != NULL && i.seg[1] != &es)
5319 {
5320 as_bad (_("`%s' operand %d must use `%ses' segment"),
5321 i.tm.name,
5322 mem_op + 2,
5323 register_prefix);
5324 return 0;
5325 }
5326 }
5327 return 1;
5328 }
5329
5330 static int
5331 process_suffix (void)
5332 {
5333 /* If matched instruction specifies an explicit instruction mnemonic
5334 suffix, use it. */
5335 if (i.tm.opcode_modifier.size16)
5336 i.suffix = WORD_MNEM_SUFFIX;
5337 else if (i.tm.opcode_modifier.size32)
5338 i.suffix = LONG_MNEM_SUFFIX;
5339 else if (i.tm.opcode_modifier.size64)
5340 i.suffix = QWORD_MNEM_SUFFIX;
5341 else if (i.reg_operands)
5342 {
5343 /* If there's no instruction mnemonic suffix we try to invent one
5344 based on register operands. */
5345 if (!i.suffix)
5346 {
5347 /* We take i.suffix from the last register operand specified,
5348 Destination register type is more significant than source
5349 register type. crc32 in SSE4.2 prefers source register
5350 type. */
5351 if (i.tm.base_opcode == 0xf20f38f1)
5352 {
5353 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5354 i.suffix = WORD_MNEM_SUFFIX;
5355 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5356 i.suffix = LONG_MNEM_SUFFIX;
5357 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5358 i.suffix = QWORD_MNEM_SUFFIX;
5359 }
5360 else if (i.tm.base_opcode == 0xf20f38f0)
5361 {
5362 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5363 i.suffix = BYTE_MNEM_SUFFIX;
5364 }
5365
5366 if (!i.suffix)
5367 {
5368 int op;
5369
5370 if (i.tm.base_opcode == 0xf20f38f1
5371 || i.tm.base_opcode == 0xf20f38f0)
5372 {
5373 /* We have to know the operand size for crc32. */
5374 as_bad (_("ambiguous memory operand size for `%s`"),
5375 i.tm.name);
5376 return 0;
5377 }
5378
5379 for (op = i.operands; --op >= 0;)
5380 if (!i.tm.operand_types[op].bitfield.inoutportreg
5381 && !i.tm.operand_types[op].bitfield.shiftcount)
5382 {
5383 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5384 {
5385 i.suffix = BYTE_MNEM_SUFFIX;
5386 break;
5387 }
5388 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5389 {
5390 i.suffix = WORD_MNEM_SUFFIX;
5391 break;
5392 }
5393 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5394 {
5395 i.suffix = LONG_MNEM_SUFFIX;
5396 break;
5397 }
5398 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5399 {
5400 i.suffix = QWORD_MNEM_SUFFIX;
5401 break;
5402 }
5403 }
5404 }
5405 }
5406 else if (i.suffix == BYTE_MNEM_SUFFIX)
5407 {
5408 if (intel_syntax
5409 && i.tm.opcode_modifier.ignoresize
5410 && i.tm.opcode_modifier.no_bsuf)
5411 i.suffix = 0;
5412 else if (!check_byte_reg ())
5413 return 0;
5414 }
5415 else if (i.suffix == LONG_MNEM_SUFFIX)
5416 {
5417 if (intel_syntax
5418 && i.tm.opcode_modifier.ignoresize
5419 && i.tm.opcode_modifier.no_lsuf)
5420 i.suffix = 0;
5421 else if (!check_long_reg ())
5422 return 0;
5423 }
5424 else if (i.suffix == QWORD_MNEM_SUFFIX)
5425 {
5426 if (intel_syntax
5427 && i.tm.opcode_modifier.ignoresize
5428 && i.tm.opcode_modifier.no_qsuf)
5429 i.suffix = 0;
5430 else if (!check_qword_reg ())
5431 return 0;
5432 }
5433 else if (i.suffix == WORD_MNEM_SUFFIX)
5434 {
5435 if (intel_syntax
5436 && i.tm.opcode_modifier.ignoresize
5437 && i.tm.opcode_modifier.no_wsuf)
5438 i.suffix = 0;
5439 else if (!check_word_reg ())
5440 return 0;
5441 }
5442 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5443 || i.suffix == YMMWORD_MNEM_SUFFIX
5444 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5445 {
5446 /* Skip if the instruction has x/y/z suffix. match_template
5447 should check if it is a valid suffix. */
5448 }
5449 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5450 /* Do nothing if the instruction is going to ignore the prefix. */
5451 ;
5452 else
5453 abort ();
5454 }
5455 else if (i.tm.opcode_modifier.defaultsize
5456 && !i.suffix
5457 /* exclude fldenv/frstor/fsave/fstenv */
5458 && i.tm.opcode_modifier.no_ssuf)
5459 {
5460 i.suffix = stackop_size;
5461 }
5462 else if (intel_syntax
5463 && !i.suffix
5464 && (i.tm.operand_types[0].bitfield.jumpabsolute
5465 || i.tm.opcode_modifier.jumpbyte
5466 || i.tm.opcode_modifier.jumpintersegment
5467 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5468 && i.tm.extension_opcode <= 3)))
5469 {
5470 switch (flag_code)
5471 {
5472 case CODE_64BIT:
5473 if (!i.tm.opcode_modifier.no_qsuf)
5474 {
5475 i.suffix = QWORD_MNEM_SUFFIX;
5476 break;
5477 }
5478 /* Fall through. */
5479 case CODE_32BIT:
5480 if (!i.tm.opcode_modifier.no_lsuf)
5481 i.suffix = LONG_MNEM_SUFFIX;
5482 break;
5483 case CODE_16BIT:
5484 if (!i.tm.opcode_modifier.no_wsuf)
5485 i.suffix = WORD_MNEM_SUFFIX;
5486 break;
5487 }
5488 }
5489
5490 if (!i.suffix)
5491 {
5492 if (!intel_syntax)
5493 {
5494 if (i.tm.opcode_modifier.w)
5495 {
5496 as_bad (_("no instruction mnemonic suffix given and "
5497 "no register operands; can't size instruction"));
5498 return 0;
5499 }
5500 }
5501 else
5502 {
5503 unsigned int suffixes;
5504
5505 suffixes = !i.tm.opcode_modifier.no_bsuf;
5506 if (!i.tm.opcode_modifier.no_wsuf)
5507 suffixes |= 1 << 1;
5508 if (!i.tm.opcode_modifier.no_lsuf)
5509 suffixes |= 1 << 2;
5510 if (!i.tm.opcode_modifier.no_ldsuf)
5511 suffixes |= 1 << 3;
5512 if (!i.tm.opcode_modifier.no_ssuf)
5513 suffixes |= 1 << 4;
5514 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5515 suffixes |= 1 << 5;
5516
5517 /* There are more than suffix matches. */
5518 if (i.tm.opcode_modifier.w
5519 || ((suffixes & (suffixes - 1))
5520 && !i.tm.opcode_modifier.defaultsize
5521 && !i.tm.opcode_modifier.ignoresize))
5522 {
5523 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5524 return 0;
5525 }
5526 }
5527 }
5528
5529 /* Change the opcode based on the operand size given by i.suffix;
5530 We don't need to change things for byte insns. */
5531
5532 if (i.suffix
5533 && i.suffix != BYTE_MNEM_SUFFIX
5534 && i.suffix != XMMWORD_MNEM_SUFFIX
5535 && i.suffix != YMMWORD_MNEM_SUFFIX
5536 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5537 {
5538 /* It's not a byte, select word/dword operation. */
5539 if (i.tm.opcode_modifier.w)
5540 {
5541 if (i.tm.opcode_modifier.shortform)
5542 i.tm.base_opcode |= 8;
5543 else
5544 i.tm.base_opcode |= 1;
5545 }
5546
5547 /* Now select between word & dword operations via the operand
5548 size prefix, except for instructions that will ignore this
5549 prefix anyway. */
5550 if (i.tm.opcode_modifier.addrprefixop0)
5551 {
5552 /* The address size override prefix changes the size of the
5553 first operand. */
5554 if ((flag_code == CODE_32BIT
5555 && i.op->regs[0].reg_type.bitfield.word)
5556 || (flag_code != CODE_32BIT
5557 && i.op->regs[0].reg_type.bitfield.dword))
5558 if (!add_prefix (ADDR_PREFIX_OPCODE))
5559 return 0;
5560 }
5561 else if (i.suffix != QWORD_MNEM_SUFFIX
5562 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5563 && !i.tm.opcode_modifier.ignoresize
5564 && !i.tm.opcode_modifier.floatmf
5565 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5566 || (flag_code == CODE_64BIT
5567 && i.tm.opcode_modifier.jumpbyte)))
5568 {
5569 unsigned int prefix = DATA_PREFIX_OPCODE;
5570
5571 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5572 prefix = ADDR_PREFIX_OPCODE;
5573
5574 if (!add_prefix (prefix))
5575 return 0;
5576 }
5577
5578 /* Set mode64 for an operand. */
5579 if (i.suffix == QWORD_MNEM_SUFFIX
5580 && flag_code == CODE_64BIT
5581 && !i.tm.opcode_modifier.norex64)
5582 {
5583 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5584 need rex64. cmpxchg8b is also a special case. */
5585 if (! (i.operands == 2
5586 && i.tm.base_opcode == 0x90
5587 && i.tm.extension_opcode == None
5588 && operand_type_equal (&i.types [0], &acc64)
5589 && operand_type_equal (&i.types [1], &acc64))
5590 && ! (i.operands == 1
5591 && i.tm.base_opcode == 0xfc7
5592 && i.tm.extension_opcode == 1
5593 && !operand_type_check (i.types [0], reg)
5594 && operand_type_check (i.types [0], anymem)))
5595 i.rex |= REX_W;
5596 }
5597
5598 /* Size floating point instruction. */
5599 if (i.suffix == LONG_MNEM_SUFFIX)
5600 if (i.tm.opcode_modifier.floatmf)
5601 i.tm.base_opcode ^= 4;
5602 }
5603
5604 return 1;
5605 }
5606
5607 static int
5608 check_byte_reg (void)
5609 {
5610 int op;
5611
5612 for (op = i.operands; --op >= 0;)
5613 {
5614 /* Skip non-register operands. */
5615 if (!i.types[op].bitfield.reg)
5616 continue;
5617
5618 /* If this is an eight bit register, it's OK. If it's the 16 or
5619 32 bit version of an eight bit register, we will just use the
5620 low portion, and that's OK too. */
5621 if (i.types[op].bitfield.byte)
5622 continue;
5623
5624 /* I/O port address operands are OK too. */
5625 if (i.tm.operand_types[op].bitfield.inoutportreg)
5626 continue;
5627
5628 /* crc32 doesn't generate this warning. */
5629 if (i.tm.base_opcode == 0xf20f38f0)
5630 continue;
5631
5632 if ((i.types[op].bitfield.word
5633 || i.types[op].bitfield.dword
5634 || i.types[op].bitfield.qword)
5635 && i.op[op].regs->reg_num < 4
5636 /* Prohibit these changes in 64bit mode, since the lowering
5637 would be more complicated. */
5638 && flag_code != CODE_64BIT)
5639 {
5640 #if REGISTER_WARNINGS
5641 if (!quiet_warnings)
5642 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5643 register_prefix,
5644 (i.op[op].regs + (i.types[op].bitfield.word
5645 ? REGNAM_AL - REGNAM_AX
5646 : REGNAM_AL - REGNAM_EAX))->reg_name,
5647 register_prefix,
5648 i.op[op].regs->reg_name,
5649 i.suffix);
5650 #endif
5651 continue;
5652 }
5653 /* Any other register is bad. */
5654 if (i.types[op].bitfield.reg
5655 || i.types[op].bitfield.regmmx
5656 || i.types[op].bitfield.regxmm
5657 || i.types[op].bitfield.regymm
5658 || i.types[op].bitfield.regzmm
5659 || i.types[op].bitfield.sreg2
5660 || i.types[op].bitfield.sreg3
5661 || i.types[op].bitfield.control
5662 || i.types[op].bitfield.debug
5663 || i.types[op].bitfield.test)
5664 {
5665 as_bad (_("`%s%s' not allowed with `%s%c'"),
5666 register_prefix,
5667 i.op[op].regs->reg_name,
5668 i.tm.name,
5669 i.suffix);
5670 return 0;
5671 }
5672 }
5673 return 1;
5674 }
5675
5676 static int
5677 check_long_reg (void)
5678 {
5679 int op;
5680
5681 for (op = i.operands; --op >= 0;)
5682 /* Skip non-register operands. */
5683 if (!i.types[op].bitfield.reg)
5684 continue;
5685 /* Reject eight bit registers, except where the template requires
5686 them. (eg. movzb) */
5687 else if (i.types[op].bitfield.byte
5688 && (i.tm.operand_types[op].bitfield.reg
5689 || i.tm.operand_types[op].bitfield.acc)
5690 && (i.tm.operand_types[op].bitfield.word
5691 || i.tm.operand_types[op].bitfield.dword))
5692 {
5693 as_bad (_("`%s%s' not allowed with `%s%c'"),
5694 register_prefix,
5695 i.op[op].regs->reg_name,
5696 i.tm.name,
5697 i.suffix);
5698 return 0;
5699 }
5700 /* Warn if the e prefix on a general reg is missing. */
5701 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5702 && i.types[op].bitfield.word
5703 && (i.tm.operand_types[op].bitfield.reg
5704 || i.tm.operand_types[op].bitfield.acc)
5705 && i.tm.operand_types[op].bitfield.dword)
5706 {
5707 /* Prohibit these changes in the 64bit mode, since the
5708 lowering is more complicated. */
5709 if (flag_code == CODE_64BIT)
5710 {
5711 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5712 register_prefix, i.op[op].regs->reg_name,
5713 i.suffix);
5714 return 0;
5715 }
5716 #if REGISTER_WARNINGS
5717 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5718 register_prefix,
5719 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5720 register_prefix, i.op[op].regs->reg_name, i.suffix);
5721 #endif
5722 }
5723 /* Warn if the r prefix on a general reg is present. */
5724 else if (i.types[op].bitfield.qword
5725 && (i.tm.operand_types[op].bitfield.reg
5726 || i.tm.operand_types[op].bitfield.acc)
5727 && i.tm.operand_types[op].bitfield.dword)
5728 {
5729 if (intel_syntax
5730 && i.tm.opcode_modifier.toqword
5731 && !i.types[0].bitfield.regxmm)
5732 {
5733 /* Convert to QWORD. We want REX byte. */
5734 i.suffix = QWORD_MNEM_SUFFIX;
5735 }
5736 else
5737 {
5738 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5739 register_prefix, i.op[op].regs->reg_name,
5740 i.suffix);
5741 return 0;
5742 }
5743 }
5744 return 1;
5745 }
5746
5747 static int
5748 check_qword_reg (void)
5749 {
5750 int op;
5751
5752 for (op = i.operands; --op >= 0; )
5753 /* Skip non-register operands. */
5754 if (!i.types[op].bitfield.reg)
5755 continue;
5756 /* Reject eight bit registers, except where the template requires
5757 them. (eg. movzb) */
5758 else if (i.types[op].bitfield.byte
5759 && (i.tm.operand_types[op].bitfield.reg
5760 || i.tm.operand_types[op].bitfield.acc)
5761 && (i.tm.operand_types[op].bitfield.word
5762 || i.tm.operand_types[op].bitfield.dword))
5763 {
5764 as_bad (_("`%s%s' not allowed with `%s%c'"),
5765 register_prefix,
5766 i.op[op].regs->reg_name,
5767 i.tm.name,
5768 i.suffix);
5769 return 0;
5770 }
5771 /* Warn if the r prefix on a general reg is missing. */
5772 else if ((i.types[op].bitfield.word
5773 || i.types[op].bitfield.dword)
5774 && (i.tm.operand_types[op].bitfield.reg
5775 || i.tm.operand_types[op].bitfield.acc)
5776 && i.tm.operand_types[op].bitfield.qword)
5777 {
5778 /* Prohibit these changes in the 64bit mode, since the
5779 lowering is more complicated. */
5780 if (intel_syntax
5781 && i.tm.opcode_modifier.todword
5782 && !i.types[0].bitfield.regxmm)
5783 {
5784 /* Convert to DWORD. We don't want REX byte. */
5785 i.suffix = LONG_MNEM_SUFFIX;
5786 }
5787 else
5788 {
5789 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5790 register_prefix, i.op[op].regs->reg_name,
5791 i.suffix);
5792 return 0;
5793 }
5794 }
5795 return 1;
5796 }
5797
5798 static int
5799 check_word_reg (void)
5800 {
5801 int op;
5802 for (op = i.operands; --op >= 0;)
5803 /* Skip non-register operands. */
5804 if (!i.types[op].bitfield.reg)
5805 continue;
5806 /* Reject eight bit registers, except where the template requires
5807 them. (eg. movzb) */
5808 else if (i.types[op].bitfield.byte
5809 && (i.tm.operand_types[op].bitfield.reg
5810 || i.tm.operand_types[op].bitfield.acc)
5811 && (i.tm.operand_types[op].bitfield.word
5812 || i.tm.operand_types[op].bitfield.dword))
5813 {
5814 as_bad (_("`%s%s' not allowed with `%s%c'"),
5815 register_prefix,
5816 i.op[op].regs->reg_name,
5817 i.tm.name,
5818 i.suffix);
5819 return 0;
5820 }
5821 /* Warn if the e or r prefix on a general reg is present. */
5822 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5823 && (i.types[op].bitfield.dword
5824 || i.types[op].bitfield.qword)
5825 && (i.tm.operand_types[op].bitfield.reg
5826 || i.tm.operand_types[op].bitfield.acc)
5827 && i.tm.operand_types[op].bitfield.word)
5828 {
5829 /* Prohibit these changes in the 64bit mode, since the
5830 lowering is more complicated. */
5831 if (flag_code == CODE_64BIT)
5832 {
5833 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5834 register_prefix, i.op[op].regs->reg_name,
5835 i.suffix);
5836 return 0;
5837 }
5838 #if REGISTER_WARNINGS
5839 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5840 register_prefix,
5841 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5842 register_prefix, i.op[op].regs->reg_name, i.suffix);
5843 #endif
5844 }
5845 return 1;
5846 }
5847
5848 static int
5849 update_imm (unsigned int j)
5850 {
5851 i386_operand_type overlap = i.types[j];
5852 if ((overlap.bitfield.imm8
5853 || overlap.bitfield.imm8s
5854 || overlap.bitfield.imm16
5855 || overlap.bitfield.imm32
5856 || overlap.bitfield.imm32s
5857 || overlap.bitfield.imm64)
5858 && !operand_type_equal (&overlap, &imm8)
5859 && !operand_type_equal (&overlap, &imm8s)
5860 && !operand_type_equal (&overlap, &imm16)
5861 && !operand_type_equal (&overlap, &imm32)
5862 && !operand_type_equal (&overlap, &imm32s)
5863 && !operand_type_equal (&overlap, &imm64))
5864 {
5865 if (i.suffix)
5866 {
5867 i386_operand_type temp;
5868
5869 operand_type_set (&temp, 0);
5870 if (i.suffix == BYTE_MNEM_SUFFIX)
5871 {
5872 temp.bitfield.imm8 = overlap.bitfield.imm8;
5873 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5874 }
5875 else if (i.suffix == WORD_MNEM_SUFFIX)
5876 temp.bitfield.imm16 = overlap.bitfield.imm16;
5877 else if (i.suffix == QWORD_MNEM_SUFFIX)
5878 {
5879 temp.bitfield.imm64 = overlap.bitfield.imm64;
5880 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5881 }
5882 else
5883 temp.bitfield.imm32 = overlap.bitfield.imm32;
5884 overlap = temp;
5885 }
5886 else if (operand_type_equal (&overlap, &imm16_32_32s)
5887 || operand_type_equal (&overlap, &imm16_32)
5888 || operand_type_equal (&overlap, &imm16_32s))
5889 {
5890 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5891 overlap = imm16;
5892 else
5893 overlap = imm32s;
5894 }
5895 if (!operand_type_equal (&overlap, &imm8)
5896 && !operand_type_equal (&overlap, &imm8s)
5897 && !operand_type_equal (&overlap, &imm16)
5898 && !operand_type_equal (&overlap, &imm32)
5899 && !operand_type_equal (&overlap, &imm32s)
5900 && !operand_type_equal (&overlap, &imm64))
5901 {
5902 as_bad (_("no instruction mnemonic suffix given; "
5903 "can't determine immediate size"));
5904 return 0;
5905 }
5906 }
5907 i.types[j] = overlap;
5908
5909 return 1;
5910 }
5911
5912 static int
5913 finalize_imm (void)
5914 {
5915 unsigned int j, n;
5916
5917 /* Update the first 2 immediate operands. */
5918 n = i.operands > 2 ? 2 : i.operands;
5919 if (n)
5920 {
5921 for (j = 0; j < n; j++)
5922 if (update_imm (j) == 0)
5923 return 0;
5924
5925 /* The 3rd operand can't be immediate operand. */
5926 gas_assert (operand_type_check (i.types[2], imm) == 0);
5927 }
5928
5929 return 1;
5930 }
5931
5932 static int
5933 bad_implicit_operand (int xmm)
5934 {
5935 const char *ireg = xmm ? "xmm0" : "ymm0";
5936
5937 if (intel_syntax)
5938 as_bad (_("the last operand of `%s' must be `%s%s'"),
5939 i.tm.name, register_prefix, ireg);
5940 else
5941 as_bad (_("the first operand of `%s' must be `%s%s'"),
5942 i.tm.name, register_prefix, ireg);
5943 return 0;
5944 }
5945
5946 static int
5947 process_operands (void)
5948 {
5949 /* Default segment register this instruction will use for memory
5950 accesses. 0 means unknown. This is only for optimizing out
5951 unnecessary segment overrides. */
5952 const seg_entry *default_seg = 0;
5953
5954 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5955 {
5956 unsigned int dupl = i.operands;
5957 unsigned int dest = dupl - 1;
5958 unsigned int j;
5959
5960 /* The destination must be an xmm register. */
5961 gas_assert (i.reg_operands
5962 && MAX_OPERANDS > dupl
5963 && operand_type_equal (&i.types[dest], &regxmm));
5964
5965 if (i.tm.opcode_modifier.firstxmm0)
5966 {
5967 /* The first operand is implicit and must be xmm0. */
5968 gas_assert (operand_type_equal (&i.types[0], &regxmm));
5969 if (register_number (i.op[0].regs) != 0)
5970 return bad_implicit_operand (1);
5971
5972 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5973 {
5974 /* Keep xmm0 for instructions with VEX prefix and 3
5975 sources. */
5976 goto duplicate;
5977 }
5978 else
5979 {
5980 /* We remove the first xmm0 and keep the number of
5981 operands unchanged, which in fact duplicates the
5982 destination. */
5983 for (j = 1; j < i.operands; j++)
5984 {
5985 i.op[j - 1] = i.op[j];
5986 i.types[j - 1] = i.types[j];
5987 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5988 }
5989 }
5990 }
5991 else if (i.tm.opcode_modifier.implicit1stxmm0)
5992 {
5993 gas_assert ((MAX_OPERANDS - 1) > dupl
5994 && (i.tm.opcode_modifier.vexsources
5995 == VEX3SOURCES));
5996
5997 /* Add the implicit xmm0 for instructions with VEX prefix
5998 and 3 sources. */
5999 for (j = i.operands; j > 0; j--)
6000 {
6001 i.op[j] = i.op[j - 1];
6002 i.types[j] = i.types[j - 1];
6003 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6004 }
6005 i.op[0].regs
6006 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6007 i.types[0] = regxmm;
6008 i.tm.operand_types[0] = regxmm;
6009
6010 i.operands += 2;
6011 i.reg_operands += 2;
6012 i.tm.operands += 2;
6013
6014 dupl++;
6015 dest++;
6016 i.op[dupl] = i.op[dest];
6017 i.types[dupl] = i.types[dest];
6018 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6019 }
6020 else
6021 {
6022 duplicate:
6023 i.operands++;
6024 i.reg_operands++;
6025 i.tm.operands++;
6026
6027 i.op[dupl] = i.op[dest];
6028 i.types[dupl] = i.types[dest];
6029 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6030 }
6031
6032 if (i.tm.opcode_modifier.immext)
6033 process_immext ();
6034 }
6035 else if (i.tm.opcode_modifier.firstxmm0)
6036 {
6037 unsigned int j;
6038
6039 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6040 gas_assert (i.reg_operands
6041 && (operand_type_equal (&i.types[0], &regxmm)
6042 || operand_type_equal (&i.types[0], &regymm)
6043 || operand_type_equal (&i.types[0], &regzmm)));
6044 if (register_number (i.op[0].regs) != 0)
6045 return bad_implicit_operand (i.types[0].bitfield.regxmm);
6046
6047 for (j = 1; j < i.operands; j++)
6048 {
6049 i.op[j - 1] = i.op[j];
6050 i.types[j - 1] = i.types[j];
6051
6052 /* We need to adjust fields in i.tm since they are used by
6053 build_modrm_byte. */
6054 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6055 }
6056
6057 i.operands--;
6058 i.reg_operands--;
6059 i.tm.operands--;
6060 }
6061 else if (i.tm.opcode_modifier.implicitquadgroup)
6062 {
6063 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6064 gas_assert (i.operands >= 2
6065 && (operand_type_equal (&i.types[1], &regxmm)
6066 || operand_type_equal (&i.types[1], &regymm)
6067 || operand_type_equal (&i.types[1], &regzmm)));
6068 unsigned int regnum = register_number (i.op[1].regs);
6069 unsigned int first_reg_in_group = regnum & ~3;
6070 unsigned int last_reg_in_group = first_reg_in_group + 3;
6071 if (regnum != first_reg_in_group) {
6072 as_warn (_("the second source register `%s%s' implicitly denotes"
6073 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6074 register_prefix, i.op[1].regs->reg_name,
6075 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6076 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6077 i.tm.name);
6078 }
6079 }
6080 else if (i.tm.opcode_modifier.regkludge)
6081 {
6082 /* The imul $imm, %reg instruction is converted into
6083 imul $imm, %reg, %reg, and the clr %reg instruction
6084 is converted into xor %reg, %reg. */
6085
6086 unsigned int first_reg_op;
6087
6088 if (operand_type_check (i.types[0], reg))
6089 first_reg_op = 0;
6090 else
6091 first_reg_op = 1;
6092 /* Pretend we saw the extra register operand. */
6093 gas_assert (i.reg_operands == 1
6094 && i.op[first_reg_op + 1].regs == 0);
6095 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6096 i.types[first_reg_op + 1] = i.types[first_reg_op];
6097 i.operands++;
6098 i.reg_operands++;
6099 }
6100
6101 if (i.tm.opcode_modifier.shortform)
6102 {
6103 if (i.types[0].bitfield.sreg2
6104 || i.types[0].bitfield.sreg3)
6105 {
6106 if (i.tm.base_opcode == POP_SEG_SHORT
6107 && i.op[0].regs->reg_num == 1)
6108 {
6109 as_bad (_("you can't `pop %scs'"), register_prefix);
6110 return 0;
6111 }
6112 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6113 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6114 i.rex |= REX_B;
6115 }
6116 else
6117 {
6118 /* The register or float register operand is in operand
6119 0 or 1. */
6120 unsigned int op;
6121
6122 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6123 || operand_type_check (i.types[0], reg))
6124 op = 0;
6125 else
6126 op = 1;
6127 /* Register goes in low 3 bits of opcode. */
6128 i.tm.base_opcode |= i.op[op].regs->reg_num;
6129 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6130 i.rex |= REX_B;
6131 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6132 {
6133 /* Warn about some common errors, but press on regardless.
6134 The first case can be generated by gcc (<= 2.8.1). */
6135 if (i.operands == 2)
6136 {
6137 /* Reversed arguments on faddp, fsubp, etc. */
6138 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6139 register_prefix, i.op[!intel_syntax].regs->reg_name,
6140 register_prefix, i.op[intel_syntax].regs->reg_name);
6141 }
6142 else
6143 {
6144 /* Extraneous `l' suffix on fp insn. */
6145 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6146 register_prefix, i.op[0].regs->reg_name);
6147 }
6148 }
6149 }
6150 }
6151 else if (i.tm.opcode_modifier.modrm)
6152 {
6153 /* The opcode is completed (modulo i.tm.extension_opcode which
6154 must be put into the modrm byte). Now, we make the modrm and
6155 index base bytes based on all the info we've collected. */
6156
6157 default_seg = build_modrm_byte ();
6158 }
6159 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6160 {
6161 default_seg = &ds;
6162 }
6163 else if (i.tm.opcode_modifier.isstring)
6164 {
6165 /* For the string instructions that allow a segment override
6166 on one of their operands, the default segment is ds. */
6167 default_seg = &ds;
6168 }
6169
6170 if (i.tm.base_opcode == 0x8d /* lea */
6171 && i.seg[0]
6172 && !quiet_warnings)
6173 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6174
6175 /* If a segment was explicitly specified, and the specified segment
6176 is not the default, use an opcode prefix to select it. If we
6177 never figured out what the default segment is, then default_seg
6178 will be zero at this point, and the specified segment prefix will
6179 always be used. */
6180 if ((i.seg[0]) && (i.seg[0] != default_seg))
6181 {
6182 if (!add_prefix (i.seg[0]->seg_prefix))
6183 return 0;
6184 }
6185 return 1;
6186 }
6187
6188 static const seg_entry *
6189 build_modrm_byte (void)
6190 {
6191 const seg_entry *default_seg = 0;
6192 unsigned int source, dest;
6193 int vex_3_sources;
6194
6195 /* The first operand of instructions with VEX prefix and 3 sources
6196 must be VEX_Imm4. */
6197 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6198 if (vex_3_sources)
6199 {
6200 unsigned int nds, reg_slot;
6201 expressionS *exp;
6202
6203 if (i.tm.opcode_modifier.veximmext
6204 && i.tm.opcode_modifier.immext)
6205 {
6206 dest = i.operands - 2;
6207 gas_assert (dest == 3);
6208 }
6209 else
6210 dest = i.operands - 1;
6211 nds = dest - 1;
6212
6213 /* There are 2 kinds of instructions:
6214 1. 5 operands: 4 register operands or 3 register operands
6215 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6216 VexW0 or VexW1. The destination must be either XMM, YMM or
6217 ZMM register.
6218 2. 4 operands: 4 register operands or 3 register operands
6219 plus 1 memory operand, VexXDS, and VexImmExt */
6220 gas_assert ((i.reg_operands == 4
6221 || (i.reg_operands == 3 && i.mem_operands == 1))
6222 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6223 && (i.tm.opcode_modifier.veximmext
6224 || (i.imm_operands == 1
6225 && i.types[0].bitfield.vec_imm4
6226 && (i.tm.opcode_modifier.vexw == VEXW0
6227 || i.tm.opcode_modifier.vexw == VEXW1)
6228 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
6229 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6230 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
6231
6232 if (i.imm_operands == 0)
6233 {
6234 /* When there is no immediate operand, generate an 8bit
6235 immediate operand to encode the first operand. */
6236 exp = &im_expressions[i.imm_operands++];
6237 i.op[i.operands].imms = exp;
6238 i.types[i.operands] = imm8;
6239 i.operands++;
6240 /* If VexW1 is set, the first operand is the source and
6241 the second operand is encoded in the immediate operand. */
6242 if (i.tm.opcode_modifier.vexw == VEXW1)
6243 {
6244 source = 0;
6245 reg_slot = 1;
6246 }
6247 else
6248 {
6249 source = 1;
6250 reg_slot = 0;
6251 }
6252
6253 /* FMA swaps REG and NDS. */
6254 if (i.tm.cpu_flags.bitfield.cpufma)
6255 {
6256 unsigned int tmp;
6257 tmp = reg_slot;
6258 reg_slot = nds;
6259 nds = tmp;
6260 }
6261
6262 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6263 &regxmm)
6264 || operand_type_equal (&i.tm.operand_types[reg_slot],
6265 &regymm)
6266 || operand_type_equal (&i.tm.operand_types[reg_slot],
6267 &regzmm));
6268 exp->X_op = O_constant;
6269 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6270 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6271 }
6272 else
6273 {
6274 unsigned int imm_slot;
6275
6276 if (i.tm.opcode_modifier.vexw == VEXW0)
6277 {
6278 /* If VexW0 is set, the third operand is the source and
6279 the second operand is encoded in the immediate
6280 operand. */
6281 source = 2;
6282 reg_slot = 1;
6283 }
6284 else
6285 {
6286 /* VexW1 is set, the second operand is the source and
6287 the third operand is encoded in the immediate
6288 operand. */
6289 source = 1;
6290 reg_slot = 2;
6291 }
6292
6293 if (i.tm.opcode_modifier.immext)
6294 {
6295 /* When ImmExt is set, the immediate byte is the last
6296 operand. */
6297 imm_slot = i.operands - 1;
6298 source--;
6299 reg_slot--;
6300 }
6301 else
6302 {
6303 imm_slot = 0;
6304
6305 /* Turn on Imm8 so that output_imm will generate it. */
6306 i.types[imm_slot].bitfield.imm8 = 1;
6307 }
6308
6309 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6310 &regxmm)
6311 || operand_type_equal (&i.tm.operand_types[reg_slot],
6312 &regymm)
6313 || operand_type_equal (&i.tm.operand_types[reg_slot],
6314 &regzmm));
6315 i.op[imm_slot].imms->X_add_number
6316 |= register_number (i.op[reg_slot].regs) << 4;
6317 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6318 }
6319
6320 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6321 || operand_type_equal (&i.tm.operand_types[nds],
6322 &regymm)
6323 || operand_type_equal (&i.tm.operand_types[nds],
6324 &regzmm));
6325 i.vex.register_specifier = i.op[nds].regs;
6326 }
6327 else
6328 source = dest = 0;
6329
6330 /* i.reg_operands MUST be the number of real register operands;
6331 implicit registers do not count. If there are 3 register
6332 operands, it must be a instruction with VexNDS. For a
6333 instruction with VexNDD, the destination register is encoded
6334 in VEX prefix. If there are 4 register operands, it must be
6335 a instruction with VEX prefix and 3 sources. */
6336 if (i.mem_operands == 0
6337 && ((i.reg_operands == 2
6338 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6339 || (i.reg_operands == 3
6340 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6341 || (i.reg_operands == 4 && vex_3_sources)))
6342 {
6343 switch (i.operands)
6344 {
6345 case 2:
6346 source = 0;
6347 break;
6348 case 3:
6349 /* When there are 3 operands, one of them may be immediate,
6350 which may be the first or the last operand. Otherwise,
6351 the first operand must be shift count register (cl) or it
6352 is an instruction with VexNDS. */
6353 gas_assert (i.imm_operands == 1
6354 || (i.imm_operands == 0
6355 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6356 || i.types[0].bitfield.shiftcount)));
6357 if (operand_type_check (i.types[0], imm)
6358 || i.types[0].bitfield.shiftcount)
6359 source = 1;
6360 else
6361 source = 0;
6362 break;
6363 case 4:
6364 /* When there are 4 operands, the first two must be 8bit
6365 immediate operands. The source operand will be the 3rd
6366 one.
6367
6368 For instructions with VexNDS, if the first operand
6369 an imm8, the source operand is the 2nd one. If the last
6370 operand is imm8, the source operand is the first one. */
6371 gas_assert ((i.imm_operands == 2
6372 && i.types[0].bitfield.imm8
6373 && i.types[1].bitfield.imm8)
6374 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6375 && i.imm_operands == 1
6376 && (i.types[0].bitfield.imm8
6377 || i.types[i.operands - 1].bitfield.imm8
6378 || i.rounding)));
6379 if (i.imm_operands == 2)
6380 source = 2;
6381 else
6382 {
6383 if (i.types[0].bitfield.imm8)
6384 source = 1;
6385 else
6386 source = 0;
6387 }
6388 break;
6389 case 5:
6390 if (i.tm.opcode_modifier.evex)
6391 {
6392 /* For EVEX instructions, when there are 5 operands, the
6393 first one must be immediate operand. If the second one
6394 is immediate operand, the source operand is the 3th
6395 one. If the last one is immediate operand, the source
6396 operand is the 2nd one. */
6397 gas_assert (i.imm_operands == 2
6398 && i.tm.opcode_modifier.sae
6399 && operand_type_check (i.types[0], imm));
6400 if (operand_type_check (i.types[1], imm))
6401 source = 2;
6402 else if (operand_type_check (i.types[4], imm))
6403 source = 1;
6404 else
6405 abort ();
6406 }
6407 break;
6408 default:
6409 abort ();
6410 }
6411
6412 if (!vex_3_sources)
6413 {
6414 dest = source + 1;
6415
6416 /* RC/SAE operand could be between DEST and SRC. That happens
6417 when one operand is GPR and the other one is XMM/YMM/ZMM
6418 register. */
6419 if (i.rounding && i.rounding->operand == (int) dest)
6420 dest++;
6421
6422 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6423 {
6424 /* For instructions with VexNDS, the register-only source
6425 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6426 register. It is encoded in VEX prefix. We need to
6427 clear RegMem bit before calling operand_type_equal. */
6428
6429 i386_operand_type op;
6430 unsigned int vvvv;
6431
6432 /* Check register-only source operand when two source
6433 operands are swapped. */
6434 if (!i.tm.operand_types[source].bitfield.baseindex
6435 && i.tm.operand_types[dest].bitfield.baseindex)
6436 {
6437 vvvv = source;
6438 source = dest;
6439 }
6440 else
6441 vvvv = dest;
6442
6443 op = i.tm.operand_types[vvvv];
6444 op.bitfield.regmem = 0;
6445 if ((dest + 1) >= i.operands
6446 || ((!op.bitfield.reg
6447 || (!op.bitfield.dword && !op.bitfield.qword))
6448 && !operand_type_equal (&op, &regxmm)
6449 && !operand_type_equal (&op, &regymm)
6450 && !operand_type_equal (&op, &regzmm)
6451 && !operand_type_equal (&op, &regmask)))
6452 abort ();
6453 i.vex.register_specifier = i.op[vvvv].regs;
6454 dest++;
6455 }
6456 }
6457
6458 i.rm.mode = 3;
6459 /* One of the register operands will be encoded in the i.tm.reg
6460 field, the other in the combined i.tm.mode and i.tm.regmem
6461 fields. If no form of this instruction supports a memory
6462 destination operand, then we assume the source operand may
6463 sometimes be a memory operand and so we need to store the
6464 destination in the i.rm.reg field. */
6465 if (!i.tm.operand_types[dest].bitfield.regmem
6466 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6467 {
6468 i.rm.reg = i.op[dest].regs->reg_num;
6469 i.rm.regmem = i.op[source].regs->reg_num;
6470 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6471 i.rex |= REX_R;
6472 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6473 i.vrex |= REX_R;
6474 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6475 i.rex |= REX_B;
6476 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6477 i.vrex |= REX_B;
6478 }
6479 else
6480 {
6481 i.rm.reg = i.op[source].regs->reg_num;
6482 i.rm.regmem = i.op[dest].regs->reg_num;
6483 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6484 i.rex |= REX_B;
6485 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6486 i.vrex |= REX_B;
6487 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6488 i.rex |= REX_R;
6489 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6490 i.vrex |= REX_R;
6491 }
6492 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6493 {
6494 if (!i.types[0].bitfield.control
6495 && !i.types[1].bitfield.control)
6496 abort ();
6497 i.rex &= ~(REX_R | REX_B);
6498 add_prefix (LOCK_PREFIX_OPCODE);
6499 }
6500 }
6501 else
6502 { /* If it's not 2 reg operands... */
6503 unsigned int mem;
6504
6505 if (i.mem_operands)
6506 {
6507 unsigned int fake_zero_displacement = 0;
6508 unsigned int op;
6509
6510 for (op = 0; op < i.operands; op++)
6511 if (operand_type_check (i.types[op], anymem))
6512 break;
6513 gas_assert (op < i.operands);
6514
6515 if (i.tm.opcode_modifier.vecsib)
6516 {
6517 if (i.index_reg->reg_num == RegEiz
6518 || i.index_reg->reg_num == RegRiz)
6519 abort ();
6520
6521 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6522 if (!i.base_reg)
6523 {
6524 i.sib.base = NO_BASE_REGISTER;
6525 i.sib.scale = i.log2_scale_factor;
6526 i.types[op].bitfield.disp8 = 0;
6527 i.types[op].bitfield.disp16 = 0;
6528 i.types[op].bitfield.disp64 = 0;
6529 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6530 {
6531 /* Must be 32 bit */
6532 i.types[op].bitfield.disp32 = 1;
6533 i.types[op].bitfield.disp32s = 0;
6534 }
6535 else
6536 {
6537 i.types[op].bitfield.disp32 = 0;
6538 i.types[op].bitfield.disp32s = 1;
6539 }
6540 }
6541 i.sib.index = i.index_reg->reg_num;
6542 if ((i.index_reg->reg_flags & RegRex) != 0)
6543 i.rex |= REX_X;
6544 if ((i.index_reg->reg_flags & RegVRex) != 0)
6545 i.vrex |= REX_X;
6546 }
6547
6548 default_seg = &ds;
6549
6550 if (i.base_reg == 0)
6551 {
6552 i.rm.mode = 0;
6553 if (!i.disp_operands)
6554 fake_zero_displacement = 1;
6555 if (i.index_reg == 0)
6556 {
6557 gas_assert (!i.tm.opcode_modifier.vecsib);
6558 /* Operand is just <disp> */
6559 if (flag_code == CODE_64BIT)
6560 {
6561 /* 64bit mode overwrites the 32bit absolute
6562 addressing by RIP relative addressing and
6563 absolute addressing is encoded by one of the
6564 redundant SIB forms. */
6565 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6566 i.sib.base = NO_BASE_REGISTER;
6567 i.sib.index = NO_INDEX_REGISTER;
6568 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6569 ? disp32s : disp32);
6570 }
6571 else if ((flag_code == CODE_16BIT)
6572 ^ (i.prefix[ADDR_PREFIX] != 0))
6573 {
6574 i.rm.regmem = NO_BASE_REGISTER_16;
6575 i.types[op] = disp16;
6576 }
6577 else
6578 {
6579 i.rm.regmem = NO_BASE_REGISTER;
6580 i.types[op] = disp32;
6581 }
6582 }
6583 else if (!i.tm.opcode_modifier.vecsib)
6584 {
6585 /* !i.base_reg && i.index_reg */
6586 if (i.index_reg->reg_num == RegEiz
6587 || i.index_reg->reg_num == RegRiz)
6588 i.sib.index = NO_INDEX_REGISTER;
6589 else
6590 i.sib.index = i.index_reg->reg_num;
6591 i.sib.base = NO_BASE_REGISTER;
6592 i.sib.scale = i.log2_scale_factor;
6593 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6594 i.types[op].bitfield.disp8 = 0;
6595 i.types[op].bitfield.disp16 = 0;
6596 i.types[op].bitfield.disp64 = 0;
6597 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6598 {
6599 /* Must be 32 bit */
6600 i.types[op].bitfield.disp32 = 1;
6601 i.types[op].bitfield.disp32s = 0;
6602 }
6603 else
6604 {
6605 i.types[op].bitfield.disp32 = 0;
6606 i.types[op].bitfield.disp32s = 1;
6607 }
6608 if ((i.index_reg->reg_flags & RegRex) != 0)
6609 i.rex |= REX_X;
6610 }
6611 }
6612 /* RIP addressing for 64bit mode. */
6613 else if (i.base_reg->reg_num == RegRip ||
6614 i.base_reg->reg_num == RegEip)
6615 {
6616 gas_assert (!i.tm.opcode_modifier.vecsib);
6617 i.rm.regmem = NO_BASE_REGISTER;
6618 i.types[op].bitfield.disp8 = 0;
6619 i.types[op].bitfield.disp16 = 0;
6620 i.types[op].bitfield.disp32 = 0;
6621 i.types[op].bitfield.disp32s = 1;
6622 i.types[op].bitfield.disp64 = 0;
6623 i.flags[op] |= Operand_PCrel;
6624 if (! i.disp_operands)
6625 fake_zero_displacement = 1;
6626 }
6627 else if (i.base_reg->reg_type.bitfield.word)
6628 {
6629 gas_assert (!i.tm.opcode_modifier.vecsib);
6630 switch (i.base_reg->reg_num)
6631 {
6632 case 3: /* (%bx) */
6633 if (i.index_reg == 0)
6634 i.rm.regmem = 7;
6635 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6636 i.rm.regmem = i.index_reg->reg_num - 6;
6637 break;
6638 case 5: /* (%bp) */
6639 default_seg = &ss;
6640 if (i.index_reg == 0)
6641 {
6642 i.rm.regmem = 6;
6643 if (operand_type_check (i.types[op], disp) == 0)
6644 {
6645 /* fake (%bp) into 0(%bp) */
6646 i.types[op].bitfield.disp8 = 1;
6647 fake_zero_displacement = 1;
6648 }
6649 }
6650 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6651 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6652 break;
6653 default: /* (%si) -> 4 or (%di) -> 5 */
6654 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6655 }
6656 i.rm.mode = mode_from_disp_size (i.types[op]);
6657 }
6658 else /* i.base_reg and 32/64 bit mode */
6659 {
6660 if (flag_code == CODE_64BIT
6661 && operand_type_check (i.types[op], disp))
6662 {
6663 i386_operand_type temp;
6664 operand_type_set (&temp, 0);
6665 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6666 i.types[op] = temp;
6667 if (i.prefix[ADDR_PREFIX] == 0)
6668 i.types[op].bitfield.disp32s = 1;
6669 else
6670 i.types[op].bitfield.disp32 = 1;
6671 }
6672
6673 if (!i.tm.opcode_modifier.vecsib)
6674 i.rm.regmem = i.base_reg->reg_num;
6675 if ((i.base_reg->reg_flags & RegRex) != 0)
6676 i.rex |= REX_B;
6677 i.sib.base = i.base_reg->reg_num;
6678 /* x86-64 ignores REX prefix bit here to avoid decoder
6679 complications. */
6680 if (!(i.base_reg->reg_flags & RegRex)
6681 && (i.base_reg->reg_num == EBP_REG_NUM
6682 || i.base_reg->reg_num == ESP_REG_NUM))
6683 default_seg = &ss;
6684 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6685 {
6686 fake_zero_displacement = 1;
6687 i.types[op].bitfield.disp8 = 1;
6688 }
6689 i.sib.scale = i.log2_scale_factor;
6690 if (i.index_reg == 0)
6691 {
6692 gas_assert (!i.tm.opcode_modifier.vecsib);
6693 /* <disp>(%esp) becomes two byte modrm with no index
6694 register. We've already stored the code for esp
6695 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6696 Any base register besides %esp will not use the
6697 extra modrm byte. */
6698 i.sib.index = NO_INDEX_REGISTER;
6699 }
6700 else if (!i.tm.opcode_modifier.vecsib)
6701 {
6702 if (i.index_reg->reg_num == RegEiz
6703 || i.index_reg->reg_num == RegRiz)
6704 i.sib.index = NO_INDEX_REGISTER;
6705 else
6706 i.sib.index = i.index_reg->reg_num;
6707 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6708 if ((i.index_reg->reg_flags & RegRex) != 0)
6709 i.rex |= REX_X;
6710 }
6711
6712 if (i.disp_operands
6713 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6714 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6715 i.rm.mode = 0;
6716 else
6717 {
6718 if (!fake_zero_displacement
6719 && !i.disp_operands
6720 && i.disp_encoding)
6721 {
6722 fake_zero_displacement = 1;
6723 if (i.disp_encoding == disp_encoding_8bit)
6724 i.types[op].bitfield.disp8 = 1;
6725 else
6726 i.types[op].bitfield.disp32 = 1;
6727 }
6728 i.rm.mode = mode_from_disp_size (i.types[op]);
6729 }
6730 }
6731
6732 if (fake_zero_displacement)
6733 {
6734 /* Fakes a zero displacement assuming that i.types[op]
6735 holds the correct displacement size. */
6736 expressionS *exp;
6737
6738 gas_assert (i.op[op].disps == 0);
6739 exp = &disp_expressions[i.disp_operands++];
6740 i.op[op].disps = exp;
6741 exp->X_op = O_constant;
6742 exp->X_add_number = 0;
6743 exp->X_add_symbol = (symbolS *) 0;
6744 exp->X_op_symbol = (symbolS *) 0;
6745 }
6746
6747 mem = op;
6748 }
6749 else
6750 mem = ~0;
6751
6752 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6753 {
6754 if (operand_type_check (i.types[0], imm))
6755 i.vex.register_specifier = NULL;
6756 else
6757 {
6758 /* VEX.vvvv encodes one of the sources when the first
6759 operand is not an immediate. */
6760 if (i.tm.opcode_modifier.vexw == VEXW0)
6761 i.vex.register_specifier = i.op[0].regs;
6762 else
6763 i.vex.register_specifier = i.op[1].regs;
6764 }
6765
6766 /* Destination is a XMM register encoded in the ModRM.reg
6767 and VEX.R bit. */
6768 i.rm.reg = i.op[2].regs->reg_num;
6769 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6770 i.rex |= REX_R;
6771
6772 /* ModRM.rm and VEX.B encodes the other source. */
6773 if (!i.mem_operands)
6774 {
6775 i.rm.mode = 3;
6776
6777 if (i.tm.opcode_modifier.vexw == VEXW0)
6778 i.rm.regmem = i.op[1].regs->reg_num;
6779 else
6780 i.rm.regmem = i.op[0].regs->reg_num;
6781
6782 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6783 i.rex |= REX_B;
6784 }
6785 }
6786 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6787 {
6788 i.vex.register_specifier = i.op[2].regs;
6789 if (!i.mem_operands)
6790 {
6791 i.rm.mode = 3;
6792 i.rm.regmem = i.op[1].regs->reg_num;
6793 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6794 i.rex |= REX_B;
6795 }
6796 }
6797 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6798 (if any) based on i.tm.extension_opcode. Again, we must be
6799 careful to make sure that segment/control/debug/test/MMX
6800 registers are coded into the i.rm.reg field. */
6801 else if (i.reg_operands)
6802 {
6803 unsigned int op;
6804 unsigned int vex_reg = ~0;
6805
6806 for (op = 0; op < i.operands; op++)
6807 if (i.types[op].bitfield.reg
6808 || i.types[op].bitfield.regmmx
6809 || i.types[op].bitfield.regxmm
6810 || i.types[op].bitfield.regymm
6811 || i.types[op].bitfield.regbnd
6812 || i.types[op].bitfield.regzmm
6813 || i.types[op].bitfield.regmask
6814 || i.types[op].bitfield.sreg2
6815 || i.types[op].bitfield.sreg3
6816 || i.types[op].bitfield.control
6817 || i.types[op].bitfield.debug
6818 || i.types[op].bitfield.test)
6819 break;
6820
6821 if (vex_3_sources)
6822 op = dest;
6823 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6824 {
6825 /* For instructions with VexNDS, the register-only
6826 source operand is encoded in VEX prefix. */
6827 gas_assert (mem != (unsigned int) ~0);
6828
6829 if (op > mem)
6830 {
6831 vex_reg = op++;
6832 gas_assert (op < i.operands);
6833 }
6834 else
6835 {
6836 /* Check register-only source operand when two source
6837 operands are swapped. */
6838 if (!i.tm.operand_types[op].bitfield.baseindex
6839 && i.tm.operand_types[op + 1].bitfield.baseindex)
6840 {
6841 vex_reg = op;
6842 op += 2;
6843 gas_assert (mem == (vex_reg + 1)
6844 && op < i.operands);
6845 }
6846 else
6847 {
6848 vex_reg = op + 1;
6849 gas_assert (vex_reg < i.operands);
6850 }
6851 }
6852 }
6853 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6854 {
6855 /* For instructions with VexNDD, the register destination
6856 is encoded in VEX prefix. */
6857 if (i.mem_operands == 0)
6858 {
6859 /* There is no memory operand. */
6860 gas_assert ((op + 2) == i.operands);
6861 vex_reg = op + 1;
6862 }
6863 else
6864 {
6865 /* There are only 2 operands. */
6866 gas_assert (op < 2 && i.operands == 2);
6867 vex_reg = 1;
6868 }
6869 }
6870 else
6871 gas_assert (op < i.operands);
6872
6873 if (vex_reg != (unsigned int) ~0)
6874 {
6875 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6876
6877 if ((!type->bitfield.reg
6878 || (!type->bitfield.dword && !type->bitfield.qword))
6879 && !operand_type_equal (type, &regxmm)
6880 && !operand_type_equal (type, &regymm)
6881 && !operand_type_equal (type, &regzmm)
6882 && !operand_type_equal (type, &regmask))
6883 abort ();
6884
6885 i.vex.register_specifier = i.op[vex_reg].regs;
6886 }
6887
6888 /* Don't set OP operand twice. */
6889 if (vex_reg != op)
6890 {
6891 /* If there is an extension opcode to put here, the
6892 register number must be put into the regmem field. */
6893 if (i.tm.extension_opcode != None)
6894 {
6895 i.rm.regmem = i.op[op].regs->reg_num;
6896 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6897 i.rex |= REX_B;
6898 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6899 i.vrex |= REX_B;
6900 }
6901 else
6902 {
6903 i.rm.reg = i.op[op].regs->reg_num;
6904 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6905 i.rex |= REX_R;
6906 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6907 i.vrex |= REX_R;
6908 }
6909 }
6910
6911 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6912 must set it to 3 to indicate this is a register operand
6913 in the regmem field. */
6914 if (!i.mem_operands)
6915 i.rm.mode = 3;
6916 }
6917
6918 /* Fill in i.rm.reg field with extension opcode (if any). */
6919 if (i.tm.extension_opcode != None)
6920 i.rm.reg = i.tm.extension_opcode;
6921 }
6922 return default_seg;
6923 }
6924
6925 static void
6926 output_branch (void)
6927 {
6928 char *p;
6929 int size;
6930 int code16;
6931 int prefix;
6932 relax_substateT subtype;
6933 symbolS *sym;
6934 offsetT off;
6935
6936 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6937 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6938
6939 prefix = 0;
6940 if (i.prefix[DATA_PREFIX] != 0)
6941 {
6942 prefix = 1;
6943 i.prefixes -= 1;
6944 code16 ^= CODE16;
6945 }
6946 /* Pentium4 branch hints. */
6947 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6948 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6949 {
6950 prefix++;
6951 i.prefixes--;
6952 }
6953 if (i.prefix[REX_PREFIX] != 0)
6954 {
6955 prefix++;
6956 i.prefixes--;
6957 }
6958
6959 /* BND prefixed jump. */
6960 if (i.prefix[BND_PREFIX] != 0)
6961 {
6962 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6963 i.prefixes -= 1;
6964 }
6965
6966 if (i.prefixes != 0 && !intel_syntax)
6967 as_warn (_("skipping prefixes on this instruction"));
6968
6969 /* It's always a symbol; End frag & setup for relax.
6970 Make sure there is enough room in this frag for the largest
6971 instruction we may generate in md_convert_frag. This is 2
6972 bytes for the opcode and room for the prefix and largest
6973 displacement. */
6974 frag_grow (prefix + 2 + 4);
6975 /* Prefix and 1 opcode byte go in fr_fix. */
6976 p = frag_more (prefix + 1);
6977 if (i.prefix[DATA_PREFIX] != 0)
6978 *p++ = DATA_PREFIX_OPCODE;
6979 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6980 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6981 *p++ = i.prefix[SEG_PREFIX];
6982 if (i.prefix[REX_PREFIX] != 0)
6983 *p++ = i.prefix[REX_PREFIX];
6984 *p = i.tm.base_opcode;
6985
6986 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6987 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6988 else if (cpu_arch_flags.bitfield.cpui386)
6989 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6990 else
6991 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6992 subtype |= code16;
6993
6994 sym = i.op[0].disps->X_add_symbol;
6995 off = i.op[0].disps->X_add_number;
6996
6997 if (i.op[0].disps->X_op != O_constant
6998 && i.op[0].disps->X_op != O_symbol)
6999 {
7000 /* Handle complex expressions. */
7001 sym = make_expr_symbol (i.op[0].disps);
7002 off = 0;
7003 }
7004
7005 /* 1 possible extra opcode + 4 byte displacement go in var part.
7006 Pass reloc in fr_var. */
7007 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7008 }
7009
7010 static void
7011 output_jump (void)
7012 {
7013 char *p;
7014 int size;
7015 fixS *fixP;
7016
7017 if (i.tm.opcode_modifier.jumpbyte)
7018 {
7019 /* This is a loop or jecxz type instruction. */
7020 size = 1;
7021 if (i.prefix[ADDR_PREFIX] != 0)
7022 {
7023 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7024 i.prefixes -= 1;
7025 }
7026 /* Pentium4 branch hints. */
7027 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7028 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7029 {
7030 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7031 i.prefixes--;
7032 }
7033 }
7034 else
7035 {
7036 int code16;
7037
7038 code16 = 0;
7039 if (flag_code == CODE_16BIT)
7040 code16 = CODE16;
7041
7042 if (i.prefix[DATA_PREFIX] != 0)
7043 {
7044 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7045 i.prefixes -= 1;
7046 code16 ^= CODE16;
7047 }
7048
7049 size = 4;
7050 if (code16)
7051 size = 2;
7052 }
7053
7054 if (i.prefix[REX_PREFIX] != 0)
7055 {
7056 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7057 i.prefixes -= 1;
7058 }
7059
7060 /* BND prefixed jump. */
7061 if (i.prefix[BND_PREFIX] != 0)
7062 {
7063 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7064 i.prefixes -= 1;
7065 }
7066
7067 if (i.prefixes != 0 && !intel_syntax)
7068 as_warn (_("skipping prefixes on this instruction"));
7069
7070 p = frag_more (i.tm.opcode_length + size);
7071 switch (i.tm.opcode_length)
7072 {
7073 case 2:
7074 *p++ = i.tm.base_opcode >> 8;
7075 /* Fall through. */
7076 case 1:
7077 *p++ = i.tm.base_opcode;
7078 break;
7079 default:
7080 abort ();
7081 }
7082
7083 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7084 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
7085
7086 /* All jumps handled here are signed, but don't use a signed limit
7087 check for 32 and 16 bit jumps as we want to allow wrap around at
7088 4G and 64k respectively. */
7089 if (size == 1)
7090 fixP->fx_signed = 1;
7091 }
7092
7093 static void
7094 output_interseg_jump (void)
7095 {
7096 char *p;
7097 int size;
7098 int prefix;
7099 int code16;
7100
7101 code16 = 0;
7102 if (flag_code == CODE_16BIT)
7103 code16 = CODE16;
7104
7105 prefix = 0;
7106 if (i.prefix[DATA_PREFIX] != 0)
7107 {
7108 prefix = 1;
7109 i.prefixes -= 1;
7110 code16 ^= CODE16;
7111 }
7112 if (i.prefix[REX_PREFIX] != 0)
7113 {
7114 prefix++;
7115 i.prefixes -= 1;
7116 }
7117
7118 size = 4;
7119 if (code16)
7120 size = 2;
7121
7122 if (i.prefixes != 0 && !intel_syntax)
7123 as_warn (_("skipping prefixes on this instruction"));
7124
7125 /* 1 opcode; 2 segment; offset */
7126 p = frag_more (prefix + 1 + 2 + size);
7127
7128 if (i.prefix[DATA_PREFIX] != 0)
7129 *p++ = DATA_PREFIX_OPCODE;
7130
7131 if (i.prefix[REX_PREFIX] != 0)
7132 *p++ = i.prefix[REX_PREFIX];
7133
7134 *p++ = i.tm.base_opcode;
7135 if (i.op[1].imms->X_op == O_constant)
7136 {
7137 offsetT n = i.op[1].imms->X_add_number;
7138
7139 if (size == 2
7140 && !fits_in_unsigned_word (n)
7141 && !fits_in_signed_word (n))
7142 {
7143 as_bad (_("16-bit jump out of range"));
7144 return;
7145 }
7146 md_number_to_chars (p, n, size);
7147 }
7148 else
7149 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7150 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7151 if (i.op[0].imms->X_op != O_constant)
7152 as_bad (_("can't handle non absolute segment in `%s'"),
7153 i.tm.name);
7154 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7155 }
7156
7157 static void
7158 output_insn (void)
7159 {
7160 fragS *insn_start_frag;
7161 offsetT insn_start_off;
7162
7163 /* Tie dwarf2 debug info to the address at the start of the insn.
7164 We can't do this after the insn has been output as the current
7165 frag may have been closed off. eg. by frag_var. */
7166 dwarf2_emit_insn (0);
7167
7168 insn_start_frag = frag_now;
7169 insn_start_off = frag_now_fix ();
7170
7171 /* Output jumps. */
7172 if (i.tm.opcode_modifier.jump)
7173 output_branch ();
7174 else if (i.tm.opcode_modifier.jumpbyte
7175 || i.tm.opcode_modifier.jumpdword)
7176 output_jump ();
7177 else if (i.tm.opcode_modifier.jumpintersegment)
7178 output_interseg_jump ();
7179 else
7180 {
7181 /* Output normal instructions here. */
7182 char *p;
7183 unsigned char *q;
7184 unsigned int j;
7185 unsigned int prefix;
7186
7187 if (avoid_fence
7188 && i.tm.base_opcode == 0xfae
7189 && i.operands == 1
7190 && i.imm_operands == 1
7191 && (i.op[0].imms->X_add_number == 0xe8
7192 || i.op[0].imms->X_add_number == 0xf0
7193 || i.op[0].imms->X_add_number == 0xf8))
7194 {
7195 /* Encode lfence, mfence, and sfence as
7196 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7197 offsetT val = 0x240483f0ULL;
7198 p = frag_more (5);
7199 md_number_to_chars (p, val, 5);
7200 return;
7201 }
7202
7203 /* Some processors fail on LOCK prefix. This options makes
7204 assembler ignore LOCK prefix and serves as a workaround. */
7205 if (omit_lock_prefix)
7206 {
7207 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7208 return;
7209 i.prefix[LOCK_PREFIX] = 0;
7210 }
7211
7212 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7213 don't need the explicit prefix. */
7214 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7215 {
7216 switch (i.tm.opcode_length)
7217 {
7218 case 3:
7219 if (i.tm.base_opcode & 0xff000000)
7220 {
7221 prefix = (i.tm.base_opcode >> 24) & 0xff;
7222 goto check_prefix;
7223 }
7224 break;
7225 case 2:
7226 if ((i.tm.base_opcode & 0xff0000) != 0)
7227 {
7228 prefix = (i.tm.base_opcode >> 16) & 0xff;
7229 if (i.tm.cpu_flags.bitfield.cpupadlock)
7230 {
7231 check_prefix:
7232 if (prefix != REPE_PREFIX_OPCODE
7233 || (i.prefix[REP_PREFIX]
7234 != REPE_PREFIX_OPCODE))
7235 add_prefix (prefix);
7236 }
7237 else
7238 add_prefix (prefix);
7239 }
7240 break;
7241 case 1:
7242 break;
7243 case 0:
7244 /* Check for pseudo prefixes. */
7245 as_bad_where (insn_start_frag->fr_file,
7246 insn_start_frag->fr_line,
7247 _("pseudo prefix without instruction"));
7248 return;
7249 default:
7250 abort ();
7251 }
7252
7253 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7254 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7255 R_X86_64_GOTTPOFF relocation so that linker can safely
7256 perform IE->LE optimization. */
7257 if (x86_elf_abi == X86_64_X32_ABI
7258 && i.operands == 2
7259 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7260 && i.prefix[REX_PREFIX] == 0)
7261 add_prefix (REX_OPCODE);
7262 #endif
7263
7264 /* The prefix bytes. */
7265 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7266 if (*q)
7267 FRAG_APPEND_1_CHAR (*q);
7268 }
7269 else
7270 {
7271 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7272 if (*q)
7273 switch (j)
7274 {
7275 case REX_PREFIX:
7276 /* REX byte is encoded in VEX prefix. */
7277 break;
7278 case SEG_PREFIX:
7279 case ADDR_PREFIX:
7280 FRAG_APPEND_1_CHAR (*q);
7281 break;
7282 default:
7283 /* There should be no other prefixes for instructions
7284 with VEX prefix. */
7285 abort ();
7286 }
7287
7288 /* For EVEX instructions i.vrex should become 0 after
7289 build_evex_prefix. For VEX instructions upper 16 registers
7290 aren't available, so VREX should be 0. */
7291 if (i.vrex)
7292 abort ();
7293 /* Now the VEX prefix. */
7294 p = frag_more (i.vex.length);
7295 for (j = 0; j < i.vex.length; j++)
7296 p[j] = i.vex.bytes[j];
7297 }
7298
7299 /* Now the opcode; be careful about word order here! */
7300 if (i.tm.opcode_length == 1)
7301 {
7302 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7303 }
7304 else
7305 {
7306 switch (i.tm.opcode_length)
7307 {
7308 case 4:
7309 p = frag_more (4);
7310 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7311 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7312 break;
7313 case 3:
7314 p = frag_more (3);
7315 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7316 break;
7317 case 2:
7318 p = frag_more (2);
7319 break;
7320 default:
7321 abort ();
7322 break;
7323 }
7324
7325 /* Put out high byte first: can't use md_number_to_chars! */
7326 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7327 *p = i.tm.base_opcode & 0xff;
7328 }
7329
7330 /* Now the modrm byte and sib byte (if present). */
7331 if (i.tm.opcode_modifier.modrm)
7332 {
7333 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7334 | i.rm.reg << 3
7335 | i.rm.mode << 6));
7336 /* If i.rm.regmem == ESP (4)
7337 && i.rm.mode != (Register mode)
7338 && not 16 bit
7339 ==> need second modrm byte. */
7340 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7341 && i.rm.mode != 3
7342 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7343 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7344 | i.sib.index << 3
7345 | i.sib.scale << 6));
7346 }
7347
7348 if (i.disp_operands)
7349 output_disp (insn_start_frag, insn_start_off);
7350
7351 if (i.imm_operands)
7352 output_imm (insn_start_frag, insn_start_off);
7353 }
7354
7355 #ifdef DEBUG386
7356 if (flag_debug)
7357 {
7358 pi ("" /*line*/, &i);
7359 }
7360 #endif /* DEBUG386 */
7361 }
7362
7363 /* Return the size of the displacement operand N. */
7364
7365 static int
7366 disp_size (unsigned int n)
7367 {
7368 int size = 4;
7369
7370 if (i.types[n].bitfield.disp64)
7371 size = 8;
7372 else if (i.types[n].bitfield.disp8)
7373 size = 1;
7374 else if (i.types[n].bitfield.disp16)
7375 size = 2;
7376 return size;
7377 }
7378
7379 /* Return the size of the immediate operand N. */
7380
7381 static int
7382 imm_size (unsigned int n)
7383 {
7384 int size = 4;
7385 if (i.types[n].bitfield.imm64)
7386 size = 8;
7387 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7388 size = 1;
7389 else if (i.types[n].bitfield.imm16)
7390 size = 2;
7391 return size;
7392 }
7393
7394 static void
7395 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7396 {
7397 char *p;
7398 unsigned int n;
7399
7400 for (n = 0; n < i.operands; n++)
7401 {
7402 if (operand_type_check (i.types[n], disp))
7403 {
7404 if (i.op[n].disps->X_op == O_constant)
7405 {
7406 int size = disp_size (n);
7407 offsetT val = i.op[n].disps->X_add_number;
7408
7409 val = offset_in_range (val >> i.memshift, size);
7410 p = frag_more (size);
7411 md_number_to_chars (p, val, size);
7412 }
7413 else
7414 {
7415 enum bfd_reloc_code_real reloc_type;
7416 int size = disp_size (n);
7417 int sign = i.types[n].bitfield.disp32s;
7418 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7419 fixS *fixP;
7420
7421 /* We can't have 8 bit displacement here. */
7422 gas_assert (!i.types[n].bitfield.disp8);
7423
7424 /* The PC relative address is computed relative
7425 to the instruction boundary, so in case immediate
7426 fields follows, we need to adjust the value. */
7427 if (pcrel && i.imm_operands)
7428 {
7429 unsigned int n1;
7430 int sz = 0;
7431
7432 for (n1 = 0; n1 < i.operands; n1++)
7433 if (operand_type_check (i.types[n1], imm))
7434 {
7435 /* Only one immediate is allowed for PC
7436 relative address. */
7437 gas_assert (sz == 0);
7438 sz = imm_size (n1);
7439 i.op[n].disps->X_add_number -= sz;
7440 }
7441 /* We should find the immediate. */
7442 gas_assert (sz != 0);
7443 }
7444
7445 p = frag_more (size);
7446 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7447 if (GOT_symbol
7448 && GOT_symbol == i.op[n].disps->X_add_symbol
7449 && (((reloc_type == BFD_RELOC_32
7450 || reloc_type == BFD_RELOC_X86_64_32S
7451 || (reloc_type == BFD_RELOC_64
7452 && object_64bit))
7453 && (i.op[n].disps->X_op == O_symbol
7454 || (i.op[n].disps->X_op == O_add
7455 && ((symbol_get_value_expression
7456 (i.op[n].disps->X_op_symbol)->X_op)
7457 == O_subtract))))
7458 || reloc_type == BFD_RELOC_32_PCREL))
7459 {
7460 offsetT add;
7461
7462 if (insn_start_frag == frag_now)
7463 add = (p - frag_now->fr_literal) - insn_start_off;
7464 else
7465 {
7466 fragS *fr;
7467
7468 add = insn_start_frag->fr_fix - insn_start_off;
7469 for (fr = insn_start_frag->fr_next;
7470 fr && fr != frag_now; fr = fr->fr_next)
7471 add += fr->fr_fix;
7472 add += p - frag_now->fr_literal;
7473 }
7474
7475 if (!object_64bit)
7476 {
7477 reloc_type = BFD_RELOC_386_GOTPC;
7478 i.op[n].imms->X_add_number += add;
7479 }
7480 else if (reloc_type == BFD_RELOC_64)
7481 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7482 else
7483 /* Don't do the adjustment for x86-64, as there
7484 the pcrel addressing is relative to the _next_
7485 insn, and that is taken care of in other code. */
7486 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7487 }
7488 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7489 size, i.op[n].disps, pcrel,
7490 reloc_type);
7491 /* Check for "call/jmp *mem", "mov mem, %reg",
7492 "test %reg, mem" and "binop mem, %reg" where binop
7493 is one of adc, add, and, cmp, or, sbb, sub, xor
7494 instructions. Always generate R_386_GOT32X for
7495 "sym*GOT" operand in 32-bit mode. */
7496 if ((generate_relax_relocations
7497 || (!object_64bit
7498 && i.rm.mode == 0
7499 && i.rm.regmem == 5))
7500 && (i.rm.mode == 2
7501 || (i.rm.mode == 0 && i.rm.regmem == 5))
7502 && ((i.operands == 1
7503 && i.tm.base_opcode == 0xff
7504 && (i.rm.reg == 2 || i.rm.reg == 4))
7505 || (i.operands == 2
7506 && (i.tm.base_opcode == 0x8b
7507 || i.tm.base_opcode == 0x85
7508 || (i.tm.base_opcode & 0xc7) == 0x03))))
7509 {
7510 if (object_64bit)
7511 {
7512 fixP->fx_tcbit = i.rex != 0;
7513 if (i.base_reg
7514 && (i.base_reg->reg_num == RegRip
7515 || i.base_reg->reg_num == RegEip))
7516 fixP->fx_tcbit2 = 1;
7517 }
7518 else
7519 fixP->fx_tcbit2 = 1;
7520 }
7521 }
7522 }
7523 }
7524 }
7525
7526 static void
7527 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7528 {
7529 char *p;
7530 unsigned int n;
7531
7532 for (n = 0; n < i.operands; n++)
7533 {
7534 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7535 if (i.rounding && (int) n == i.rounding->operand)
7536 continue;
7537
7538 if (operand_type_check (i.types[n], imm))
7539 {
7540 if (i.op[n].imms->X_op == O_constant)
7541 {
7542 int size = imm_size (n);
7543 offsetT val;
7544
7545 val = offset_in_range (i.op[n].imms->X_add_number,
7546 size);
7547 p = frag_more (size);
7548 md_number_to_chars (p, val, size);
7549 }
7550 else
7551 {
7552 /* Not absolute_section.
7553 Need a 32-bit fixup (don't support 8bit
7554 non-absolute imms). Try to support other
7555 sizes ... */
7556 enum bfd_reloc_code_real reloc_type;
7557 int size = imm_size (n);
7558 int sign;
7559
7560 if (i.types[n].bitfield.imm32s
7561 && (i.suffix == QWORD_MNEM_SUFFIX
7562 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7563 sign = 1;
7564 else
7565 sign = 0;
7566
7567 p = frag_more (size);
7568 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7569
7570 /* This is tough to explain. We end up with this one if we
7571 * have operands that look like
7572 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7573 * obtain the absolute address of the GOT, and it is strongly
7574 * preferable from a performance point of view to avoid using
7575 * a runtime relocation for this. The actual sequence of
7576 * instructions often look something like:
7577 *
7578 * call .L66
7579 * .L66:
7580 * popl %ebx
7581 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7582 *
7583 * The call and pop essentially return the absolute address
7584 * of the label .L66 and store it in %ebx. The linker itself
7585 * will ultimately change the first operand of the addl so
7586 * that %ebx points to the GOT, but to keep things simple, the
7587 * .o file must have this operand set so that it generates not
7588 * the absolute address of .L66, but the absolute address of
7589 * itself. This allows the linker itself simply treat a GOTPC
7590 * relocation as asking for a pcrel offset to the GOT to be
7591 * added in, and the addend of the relocation is stored in the
7592 * operand field for the instruction itself.
7593 *
7594 * Our job here is to fix the operand so that it would add
7595 * the correct offset so that %ebx would point to itself. The
7596 * thing that is tricky is that .-.L66 will point to the
7597 * beginning of the instruction, so we need to further modify
7598 * the operand so that it will point to itself. There are
7599 * other cases where you have something like:
7600 *
7601 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7602 *
7603 * and here no correction would be required. Internally in
7604 * the assembler we treat operands of this form as not being
7605 * pcrel since the '.' is explicitly mentioned, and I wonder
7606 * whether it would simplify matters to do it this way. Who
7607 * knows. In earlier versions of the PIC patches, the
7608 * pcrel_adjust field was used to store the correction, but
7609 * since the expression is not pcrel, I felt it would be
7610 * confusing to do it this way. */
7611
7612 if ((reloc_type == BFD_RELOC_32
7613 || reloc_type == BFD_RELOC_X86_64_32S
7614 || reloc_type == BFD_RELOC_64)
7615 && GOT_symbol
7616 && GOT_symbol == i.op[n].imms->X_add_symbol
7617 && (i.op[n].imms->X_op == O_symbol
7618 || (i.op[n].imms->X_op == O_add
7619 && ((symbol_get_value_expression
7620 (i.op[n].imms->X_op_symbol)->X_op)
7621 == O_subtract))))
7622 {
7623 offsetT add;
7624
7625 if (insn_start_frag == frag_now)
7626 add = (p - frag_now->fr_literal) - insn_start_off;
7627 else
7628 {
7629 fragS *fr;
7630
7631 add = insn_start_frag->fr_fix - insn_start_off;
7632 for (fr = insn_start_frag->fr_next;
7633 fr && fr != frag_now; fr = fr->fr_next)
7634 add += fr->fr_fix;
7635 add += p - frag_now->fr_literal;
7636 }
7637
7638 if (!object_64bit)
7639 reloc_type = BFD_RELOC_386_GOTPC;
7640 else if (size == 4)
7641 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7642 else if (size == 8)
7643 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7644 i.op[n].imms->X_add_number += add;
7645 }
7646 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7647 i.op[n].imms, 0, reloc_type);
7648 }
7649 }
7650 }
7651 }
7652 \f
7653 /* x86_cons_fix_new is called via the expression parsing code when a
7654 reloc is needed. We use this hook to get the correct .got reloc. */
7655 static int cons_sign = -1;
7656
7657 void
7658 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7659 expressionS *exp, bfd_reloc_code_real_type r)
7660 {
7661 r = reloc (len, 0, cons_sign, r);
7662
7663 #ifdef TE_PE
7664 if (exp->X_op == O_secrel)
7665 {
7666 exp->X_op = O_symbol;
7667 r = BFD_RELOC_32_SECREL;
7668 }
7669 #endif
7670
7671 fix_new_exp (frag, off, len, exp, 0, r);
7672 }
7673
7674 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7675 purpose of the `.dc.a' internal pseudo-op. */
7676
7677 int
7678 x86_address_bytes (void)
7679 {
7680 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7681 return 4;
7682 return stdoutput->arch_info->bits_per_address / 8;
7683 }
7684
7685 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7686 || defined (LEX_AT)
7687 # define lex_got(reloc, adjust, types) NULL
7688 #else
7689 /* Parse operands of the form
7690 <symbol>@GOTOFF+<nnn>
7691 and similar .plt or .got references.
7692
7693 If we find one, set up the correct relocation in RELOC and copy the
7694 input string, minus the `@GOTOFF' into a malloc'd buffer for
7695 parsing by the calling routine. Return this buffer, and if ADJUST
7696 is non-null set it to the length of the string we removed from the
7697 input line. Otherwise return NULL. */
7698 static char *
7699 lex_got (enum bfd_reloc_code_real *rel,
7700 int *adjust,
7701 i386_operand_type *types)
7702 {
7703 /* Some of the relocations depend on the size of what field is to
7704 be relocated. But in our callers i386_immediate and i386_displacement
7705 we don't yet know the operand size (this will be set by insn
7706 matching). Hence we record the word32 relocation here,
7707 and adjust the reloc according to the real size in reloc(). */
7708 static const struct {
7709 const char *str;
7710 int len;
7711 const enum bfd_reloc_code_real rel[2];
7712 const i386_operand_type types64;
7713 } gotrel[] = {
7714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7715 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7716 BFD_RELOC_SIZE32 },
7717 OPERAND_TYPE_IMM32_64 },
7718 #endif
7719 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7720 BFD_RELOC_X86_64_PLTOFF64 },
7721 OPERAND_TYPE_IMM64 },
7722 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7723 BFD_RELOC_X86_64_PLT32 },
7724 OPERAND_TYPE_IMM32_32S_DISP32 },
7725 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7726 BFD_RELOC_X86_64_GOTPLT64 },
7727 OPERAND_TYPE_IMM64_DISP64 },
7728 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7729 BFD_RELOC_X86_64_GOTOFF64 },
7730 OPERAND_TYPE_IMM64_DISP64 },
7731 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7732 BFD_RELOC_X86_64_GOTPCREL },
7733 OPERAND_TYPE_IMM32_32S_DISP32 },
7734 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7735 BFD_RELOC_X86_64_TLSGD },
7736 OPERAND_TYPE_IMM32_32S_DISP32 },
7737 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7738 _dummy_first_bfd_reloc_code_real },
7739 OPERAND_TYPE_NONE },
7740 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7741 BFD_RELOC_X86_64_TLSLD },
7742 OPERAND_TYPE_IMM32_32S_DISP32 },
7743 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7744 BFD_RELOC_X86_64_GOTTPOFF },
7745 OPERAND_TYPE_IMM32_32S_DISP32 },
7746 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7747 BFD_RELOC_X86_64_TPOFF32 },
7748 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7749 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7750 _dummy_first_bfd_reloc_code_real },
7751 OPERAND_TYPE_NONE },
7752 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7753 BFD_RELOC_X86_64_DTPOFF32 },
7754 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7755 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7756 _dummy_first_bfd_reloc_code_real },
7757 OPERAND_TYPE_NONE },
7758 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7759 _dummy_first_bfd_reloc_code_real },
7760 OPERAND_TYPE_NONE },
7761 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7762 BFD_RELOC_X86_64_GOT32 },
7763 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7764 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7765 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7766 OPERAND_TYPE_IMM32_32S_DISP32 },
7767 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7768 BFD_RELOC_X86_64_TLSDESC_CALL },
7769 OPERAND_TYPE_IMM32_32S_DISP32 },
7770 };
7771 char *cp;
7772 unsigned int j;
7773
7774 #if defined (OBJ_MAYBE_ELF)
7775 if (!IS_ELF)
7776 return NULL;
7777 #endif
7778
7779 for (cp = input_line_pointer; *cp != '@'; cp++)
7780 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7781 return NULL;
7782
7783 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7784 {
7785 int len = gotrel[j].len;
7786 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7787 {
7788 if (gotrel[j].rel[object_64bit] != 0)
7789 {
7790 int first, second;
7791 char *tmpbuf, *past_reloc;
7792
7793 *rel = gotrel[j].rel[object_64bit];
7794
7795 if (types)
7796 {
7797 if (flag_code != CODE_64BIT)
7798 {
7799 types->bitfield.imm32 = 1;
7800 types->bitfield.disp32 = 1;
7801 }
7802 else
7803 *types = gotrel[j].types64;
7804 }
7805
7806 if (j != 0 && GOT_symbol == NULL)
7807 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7808
7809 /* The length of the first part of our input line. */
7810 first = cp - input_line_pointer;
7811
7812 /* The second part goes from after the reloc token until
7813 (and including) an end_of_line char or comma. */
7814 past_reloc = cp + 1 + len;
7815 cp = past_reloc;
7816 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7817 ++cp;
7818 second = cp + 1 - past_reloc;
7819
7820 /* Allocate and copy string. The trailing NUL shouldn't
7821 be necessary, but be safe. */
7822 tmpbuf = XNEWVEC (char, first + second + 2);
7823 memcpy (tmpbuf, input_line_pointer, first);
7824 if (second != 0 && *past_reloc != ' ')
7825 /* Replace the relocation token with ' ', so that
7826 errors like foo@GOTOFF1 will be detected. */
7827 tmpbuf[first++] = ' ';
7828 else
7829 /* Increment length by 1 if the relocation token is
7830 removed. */
7831 len++;
7832 if (adjust)
7833 *adjust = len;
7834 memcpy (tmpbuf + first, past_reloc, second);
7835 tmpbuf[first + second] = '\0';
7836 return tmpbuf;
7837 }
7838
7839 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7840 gotrel[j].str, 1 << (5 + object_64bit));
7841 return NULL;
7842 }
7843 }
7844
7845 /* Might be a symbol version string. Don't as_bad here. */
7846 return NULL;
7847 }
7848 #endif
7849
7850 #ifdef TE_PE
7851 #ifdef lex_got
7852 #undef lex_got
7853 #endif
7854 /* Parse operands of the form
7855 <symbol>@SECREL32+<nnn>
7856
7857 If we find one, set up the correct relocation in RELOC and copy the
7858 input string, minus the `@SECREL32' into a malloc'd buffer for
7859 parsing by the calling routine. Return this buffer, and if ADJUST
7860 is non-null set it to the length of the string we removed from the
7861 input line. Otherwise return NULL.
7862
7863 This function is copied from the ELF version above adjusted for PE targets. */
7864
7865 static char *
7866 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7867 int *adjust ATTRIBUTE_UNUSED,
7868 i386_operand_type *types)
7869 {
7870 static const struct
7871 {
7872 const char *str;
7873 int len;
7874 const enum bfd_reloc_code_real rel[2];
7875 const i386_operand_type types64;
7876 }
7877 gotrel[] =
7878 {
7879 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7880 BFD_RELOC_32_SECREL },
7881 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7882 };
7883
7884 char *cp;
7885 unsigned j;
7886
7887 for (cp = input_line_pointer; *cp != '@'; cp++)
7888 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7889 return NULL;
7890
7891 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7892 {
7893 int len = gotrel[j].len;
7894
7895 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7896 {
7897 if (gotrel[j].rel[object_64bit] != 0)
7898 {
7899 int first, second;
7900 char *tmpbuf, *past_reloc;
7901
7902 *rel = gotrel[j].rel[object_64bit];
7903 if (adjust)
7904 *adjust = len;
7905
7906 if (types)
7907 {
7908 if (flag_code != CODE_64BIT)
7909 {
7910 types->bitfield.imm32 = 1;
7911 types->bitfield.disp32 = 1;
7912 }
7913 else
7914 *types = gotrel[j].types64;
7915 }
7916
7917 /* The length of the first part of our input line. */
7918 first = cp - input_line_pointer;
7919
7920 /* The second part goes from after the reloc token until
7921 (and including) an end_of_line char or comma. */
7922 past_reloc = cp + 1 + len;
7923 cp = past_reloc;
7924 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7925 ++cp;
7926 second = cp + 1 - past_reloc;
7927
7928 /* Allocate and copy string. The trailing NUL shouldn't
7929 be necessary, but be safe. */
7930 tmpbuf = XNEWVEC (char, first + second + 2);
7931 memcpy (tmpbuf, input_line_pointer, first);
7932 if (second != 0 && *past_reloc != ' ')
7933 /* Replace the relocation token with ' ', so that
7934 errors like foo@SECLREL321 will be detected. */
7935 tmpbuf[first++] = ' ';
7936 memcpy (tmpbuf + first, past_reloc, second);
7937 tmpbuf[first + second] = '\0';
7938 return tmpbuf;
7939 }
7940
7941 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7942 gotrel[j].str, 1 << (5 + object_64bit));
7943 return NULL;
7944 }
7945 }
7946
7947 /* Might be a symbol version string. Don't as_bad here. */
7948 return NULL;
7949 }
7950
7951 #endif /* TE_PE */
7952
7953 bfd_reloc_code_real_type
7954 x86_cons (expressionS *exp, int size)
7955 {
7956 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7957
7958 intel_syntax = -intel_syntax;
7959
7960 exp->X_md = 0;
7961 if (size == 4 || (object_64bit && size == 8))
7962 {
7963 /* Handle @GOTOFF and the like in an expression. */
7964 char *save;
7965 char *gotfree_input_line;
7966 int adjust = 0;
7967
7968 save = input_line_pointer;
7969 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
7970 if (gotfree_input_line)
7971 input_line_pointer = gotfree_input_line;
7972
7973 expression (exp);
7974
7975 if (gotfree_input_line)
7976 {
7977 /* expression () has merrily parsed up to the end of line,
7978 or a comma - in the wrong buffer. Transfer how far
7979 input_line_pointer has moved to the right buffer. */
7980 input_line_pointer = (save
7981 + (input_line_pointer - gotfree_input_line)
7982 + adjust);
7983 free (gotfree_input_line);
7984 if (exp->X_op == O_constant
7985 || exp->X_op == O_absent
7986 || exp->X_op == O_illegal
7987 || exp->X_op == O_register
7988 || exp->X_op == O_big)
7989 {
7990 char c = *input_line_pointer;
7991 *input_line_pointer = 0;
7992 as_bad (_("missing or invalid expression `%s'"), save);
7993 *input_line_pointer = c;
7994 }
7995 }
7996 }
7997 else
7998 expression (exp);
7999
8000 intel_syntax = -intel_syntax;
8001
8002 if (intel_syntax)
8003 i386_intel_simplify (exp);
8004
8005 return got_reloc;
8006 }
8007
8008 static void
8009 signed_cons (int size)
8010 {
8011 if (flag_code == CODE_64BIT)
8012 cons_sign = 1;
8013 cons (size);
8014 cons_sign = -1;
8015 }
8016
8017 #ifdef TE_PE
8018 static void
8019 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8020 {
8021 expressionS exp;
8022
8023 do
8024 {
8025 expression (&exp);
8026 if (exp.X_op == O_symbol)
8027 exp.X_op = O_secrel;
8028
8029 emit_expr (&exp, 4);
8030 }
8031 while (*input_line_pointer++ == ',');
8032
8033 input_line_pointer--;
8034 demand_empty_rest_of_line ();
8035 }
8036 #endif
8037
8038 /* Handle Vector operations. */
8039
8040 static char *
8041 check_VecOperations (char *op_string, char *op_end)
8042 {
8043 const reg_entry *mask;
8044 const char *saved;
8045 char *end_op;
8046
8047 while (*op_string
8048 && (op_end == NULL || op_string < op_end))
8049 {
8050 saved = op_string;
8051 if (*op_string == '{')
8052 {
8053 op_string++;
8054
8055 /* Check broadcasts. */
8056 if (strncmp (op_string, "1to", 3) == 0)
8057 {
8058 int bcst_type;
8059
8060 if (i.broadcast)
8061 goto duplicated_vec_op;
8062
8063 op_string += 3;
8064 if (*op_string == '8')
8065 bcst_type = BROADCAST_1TO8;
8066 else if (*op_string == '4')
8067 bcst_type = BROADCAST_1TO4;
8068 else if (*op_string == '2')
8069 bcst_type = BROADCAST_1TO2;
8070 else if (*op_string == '1'
8071 && *(op_string+1) == '6')
8072 {
8073 bcst_type = BROADCAST_1TO16;
8074 op_string++;
8075 }
8076 else
8077 {
8078 as_bad (_("Unsupported broadcast: `%s'"), saved);
8079 return NULL;
8080 }
8081 op_string++;
8082
8083 broadcast_op.type = bcst_type;
8084 broadcast_op.operand = this_operand;
8085 i.broadcast = &broadcast_op;
8086 }
8087 /* Check masking operation. */
8088 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8089 {
8090 /* k0 can't be used for write mask. */
8091 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8092 {
8093 as_bad (_("`%s%s' can't be used for write mask"),
8094 register_prefix, mask->reg_name);
8095 return NULL;
8096 }
8097
8098 if (!i.mask)
8099 {
8100 mask_op.mask = mask;
8101 mask_op.zeroing = 0;
8102 mask_op.operand = this_operand;
8103 i.mask = &mask_op;
8104 }
8105 else
8106 {
8107 if (i.mask->mask)
8108 goto duplicated_vec_op;
8109
8110 i.mask->mask = mask;
8111
8112 /* Only "{z}" is allowed here. No need to check
8113 zeroing mask explicitly. */
8114 if (i.mask->operand != this_operand)
8115 {
8116 as_bad (_("invalid write mask `%s'"), saved);
8117 return NULL;
8118 }
8119 }
8120
8121 op_string = end_op;
8122 }
8123 /* Check zeroing-flag for masking operation. */
8124 else if (*op_string == 'z')
8125 {
8126 if (!i.mask)
8127 {
8128 mask_op.mask = NULL;
8129 mask_op.zeroing = 1;
8130 mask_op.operand = this_operand;
8131 i.mask = &mask_op;
8132 }
8133 else
8134 {
8135 if (i.mask->zeroing)
8136 {
8137 duplicated_vec_op:
8138 as_bad (_("duplicated `%s'"), saved);
8139 return NULL;
8140 }
8141
8142 i.mask->zeroing = 1;
8143
8144 /* Only "{%k}" is allowed here. No need to check mask
8145 register explicitly. */
8146 if (i.mask->operand != this_operand)
8147 {
8148 as_bad (_("invalid zeroing-masking `%s'"),
8149 saved);
8150 return NULL;
8151 }
8152 }
8153
8154 op_string++;
8155 }
8156 else
8157 goto unknown_vec_op;
8158
8159 if (*op_string != '}')
8160 {
8161 as_bad (_("missing `}' in `%s'"), saved);
8162 return NULL;
8163 }
8164 op_string++;
8165 continue;
8166 }
8167 unknown_vec_op:
8168 /* We don't know this one. */
8169 as_bad (_("unknown vector operation: `%s'"), saved);
8170 return NULL;
8171 }
8172
8173 if (i.mask && i.mask->zeroing && !i.mask->mask)
8174 {
8175 as_bad (_("zeroing-masking only allowed with write mask"));
8176 return NULL;
8177 }
8178
8179 return op_string;
8180 }
8181
8182 static int
8183 i386_immediate (char *imm_start)
8184 {
8185 char *save_input_line_pointer;
8186 char *gotfree_input_line;
8187 segT exp_seg = 0;
8188 expressionS *exp;
8189 i386_operand_type types;
8190
8191 operand_type_set (&types, ~0);
8192
8193 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8194 {
8195 as_bad (_("at most %d immediate operands are allowed"),
8196 MAX_IMMEDIATE_OPERANDS);
8197 return 0;
8198 }
8199
8200 exp = &im_expressions[i.imm_operands++];
8201 i.op[this_operand].imms = exp;
8202
8203 if (is_space_char (*imm_start))
8204 ++imm_start;
8205
8206 save_input_line_pointer = input_line_pointer;
8207 input_line_pointer = imm_start;
8208
8209 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8210 if (gotfree_input_line)
8211 input_line_pointer = gotfree_input_line;
8212
8213 exp_seg = expression (exp);
8214
8215 SKIP_WHITESPACE ();
8216
8217 /* Handle vector operations. */
8218 if (*input_line_pointer == '{')
8219 {
8220 input_line_pointer = check_VecOperations (input_line_pointer,
8221 NULL);
8222 if (input_line_pointer == NULL)
8223 return 0;
8224 }
8225
8226 if (*input_line_pointer)
8227 as_bad (_("junk `%s' after expression"), input_line_pointer);
8228
8229 input_line_pointer = save_input_line_pointer;
8230 if (gotfree_input_line)
8231 {
8232 free (gotfree_input_line);
8233
8234 if (exp->X_op == O_constant || exp->X_op == O_register)
8235 exp->X_op = O_illegal;
8236 }
8237
8238 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8239 }
8240
8241 static int
8242 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8243 i386_operand_type types, const char *imm_start)
8244 {
8245 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8246 {
8247 if (imm_start)
8248 as_bad (_("missing or invalid immediate expression `%s'"),
8249 imm_start);
8250 return 0;
8251 }
8252 else if (exp->X_op == O_constant)
8253 {
8254 /* Size it properly later. */
8255 i.types[this_operand].bitfield.imm64 = 1;
8256 /* If not 64bit, sign extend val. */
8257 if (flag_code != CODE_64BIT
8258 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8259 exp->X_add_number
8260 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8261 }
8262 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8263 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8264 && exp_seg != absolute_section
8265 && exp_seg != text_section
8266 && exp_seg != data_section
8267 && exp_seg != bss_section
8268 && exp_seg != undefined_section
8269 && !bfd_is_com_section (exp_seg))
8270 {
8271 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8272 return 0;
8273 }
8274 #endif
8275 else if (!intel_syntax && exp_seg == reg_section)
8276 {
8277 if (imm_start)
8278 as_bad (_("illegal immediate register operand %s"), imm_start);
8279 return 0;
8280 }
8281 else
8282 {
8283 /* This is an address. The size of the address will be
8284 determined later, depending on destination register,
8285 suffix, or the default for the section. */
8286 i.types[this_operand].bitfield.imm8 = 1;
8287 i.types[this_operand].bitfield.imm16 = 1;
8288 i.types[this_operand].bitfield.imm32 = 1;
8289 i.types[this_operand].bitfield.imm32s = 1;
8290 i.types[this_operand].bitfield.imm64 = 1;
8291 i.types[this_operand] = operand_type_and (i.types[this_operand],
8292 types);
8293 }
8294
8295 return 1;
8296 }
8297
8298 static char *
8299 i386_scale (char *scale)
8300 {
8301 offsetT val;
8302 char *save = input_line_pointer;
8303
8304 input_line_pointer = scale;
8305 val = get_absolute_expression ();
8306
8307 switch (val)
8308 {
8309 case 1:
8310 i.log2_scale_factor = 0;
8311 break;
8312 case 2:
8313 i.log2_scale_factor = 1;
8314 break;
8315 case 4:
8316 i.log2_scale_factor = 2;
8317 break;
8318 case 8:
8319 i.log2_scale_factor = 3;
8320 break;
8321 default:
8322 {
8323 char sep = *input_line_pointer;
8324
8325 *input_line_pointer = '\0';
8326 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8327 scale);
8328 *input_line_pointer = sep;
8329 input_line_pointer = save;
8330 return NULL;
8331 }
8332 }
8333 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8334 {
8335 as_warn (_("scale factor of %d without an index register"),
8336 1 << i.log2_scale_factor);
8337 i.log2_scale_factor = 0;
8338 }
8339 scale = input_line_pointer;
8340 input_line_pointer = save;
8341 return scale;
8342 }
8343
8344 static int
8345 i386_displacement (char *disp_start, char *disp_end)
8346 {
8347 expressionS *exp;
8348 segT exp_seg = 0;
8349 char *save_input_line_pointer;
8350 char *gotfree_input_line;
8351 int override;
8352 i386_operand_type bigdisp, types = anydisp;
8353 int ret;
8354
8355 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8356 {
8357 as_bad (_("at most %d displacement operands are allowed"),
8358 MAX_MEMORY_OPERANDS);
8359 return 0;
8360 }
8361
8362 operand_type_set (&bigdisp, 0);
8363 if ((i.types[this_operand].bitfield.jumpabsolute)
8364 || (!current_templates->start->opcode_modifier.jump
8365 && !current_templates->start->opcode_modifier.jumpdword))
8366 {
8367 bigdisp.bitfield.disp32 = 1;
8368 override = (i.prefix[ADDR_PREFIX] != 0);
8369 if (flag_code == CODE_64BIT)
8370 {
8371 if (!override)
8372 {
8373 bigdisp.bitfield.disp32s = 1;
8374 bigdisp.bitfield.disp64 = 1;
8375 }
8376 }
8377 else if ((flag_code == CODE_16BIT) ^ override)
8378 {
8379 bigdisp.bitfield.disp32 = 0;
8380 bigdisp.bitfield.disp16 = 1;
8381 }
8382 }
8383 else
8384 {
8385 /* For PC-relative branches, the width of the displacement
8386 is dependent upon data size, not address size. */
8387 override = (i.prefix[DATA_PREFIX] != 0);
8388 if (flag_code == CODE_64BIT)
8389 {
8390 if (override || i.suffix == WORD_MNEM_SUFFIX)
8391 bigdisp.bitfield.disp16 = 1;
8392 else
8393 {
8394 bigdisp.bitfield.disp32 = 1;
8395 bigdisp.bitfield.disp32s = 1;
8396 }
8397 }
8398 else
8399 {
8400 if (!override)
8401 override = (i.suffix == (flag_code != CODE_16BIT
8402 ? WORD_MNEM_SUFFIX
8403 : LONG_MNEM_SUFFIX));
8404 bigdisp.bitfield.disp32 = 1;
8405 if ((flag_code == CODE_16BIT) ^ override)
8406 {
8407 bigdisp.bitfield.disp32 = 0;
8408 bigdisp.bitfield.disp16 = 1;
8409 }
8410 }
8411 }
8412 i.types[this_operand] = operand_type_or (i.types[this_operand],
8413 bigdisp);
8414
8415 exp = &disp_expressions[i.disp_operands];
8416 i.op[this_operand].disps = exp;
8417 i.disp_operands++;
8418 save_input_line_pointer = input_line_pointer;
8419 input_line_pointer = disp_start;
8420 END_STRING_AND_SAVE (disp_end);
8421
8422 #ifndef GCC_ASM_O_HACK
8423 #define GCC_ASM_O_HACK 0
8424 #endif
8425 #if GCC_ASM_O_HACK
8426 END_STRING_AND_SAVE (disp_end + 1);
8427 if (i.types[this_operand].bitfield.baseIndex
8428 && displacement_string_end[-1] == '+')
8429 {
8430 /* This hack is to avoid a warning when using the "o"
8431 constraint within gcc asm statements.
8432 For instance:
8433
8434 #define _set_tssldt_desc(n,addr,limit,type) \
8435 __asm__ __volatile__ ( \
8436 "movw %w2,%0\n\t" \
8437 "movw %w1,2+%0\n\t" \
8438 "rorl $16,%1\n\t" \
8439 "movb %b1,4+%0\n\t" \
8440 "movb %4,5+%0\n\t" \
8441 "movb $0,6+%0\n\t" \
8442 "movb %h1,7+%0\n\t" \
8443 "rorl $16,%1" \
8444 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8445
8446 This works great except that the output assembler ends
8447 up looking a bit weird if it turns out that there is
8448 no offset. You end up producing code that looks like:
8449
8450 #APP
8451 movw $235,(%eax)
8452 movw %dx,2+(%eax)
8453 rorl $16,%edx
8454 movb %dl,4+(%eax)
8455 movb $137,5+(%eax)
8456 movb $0,6+(%eax)
8457 movb %dh,7+(%eax)
8458 rorl $16,%edx
8459 #NO_APP
8460
8461 So here we provide the missing zero. */
8462
8463 *displacement_string_end = '0';
8464 }
8465 #endif
8466 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8467 if (gotfree_input_line)
8468 input_line_pointer = gotfree_input_line;
8469
8470 exp_seg = expression (exp);
8471
8472 SKIP_WHITESPACE ();
8473 if (*input_line_pointer)
8474 as_bad (_("junk `%s' after expression"), input_line_pointer);
8475 #if GCC_ASM_O_HACK
8476 RESTORE_END_STRING (disp_end + 1);
8477 #endif
8478 input_line_pointer = save_input_line_pointer;
8479 if (gotfree_input_line)
8480 {
8481 free (gotfree_input_line);
8482
8483 if (exp->X_op == O_constant || exp->X_op == O_register)
8484 exp->X_op = O_illegal;
8485 }
8486
8487 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8488
8489 RESTORE_END_STRING (disp_end);
8490
8491 return ret;
8492 }
8493
8494 static int
8495 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8496 i386_operand_type types, const char *disp_start)
8497 {
8498 i386_operand_type bigdisp;
8499 int ret = 1;
8500
8501 /* We do this to make sure that the section symbol is in
8502 the symbol table. We will ultimately change the relocation
8503 to be relative to the beginning of the section. */
8504 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8505 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8506 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8507 {
8508 if (exp->X_op != O_symbol)
8509 goto inv_disp;
8510
8511 if (S_IS_LOCAL (exp->X_add_symbol)
8512 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8513 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8514 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8515 exp->X_op = O_subtract;
8516 exp->X_op_symbol = GOT_symbol;
8517 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8518 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8519 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8520 i.reloc[this_operand] = BFD_RELOC_64;
8521 else
8522 i.reloc[this_operand] = BFD_RELOC_32;
8523 }
8524
8525 else if (exp->X_op == O_absent
8526 || exp->X_op == O_illegal
8527 || exp->X_op == O_big)
8528 {
8529 inv_disp:
8530 as_bad (_("missing or invalid displacement expression `%s'"),
8531 disp_start);
8532 ret = 0;
8533 }
8534
8535 else if (flag_code == CODE_64BIT
8536 && !i.prefix[ADDR_PREFIX]
8537 && exp->X_op == O_constant)
8538 {
8539 /* Since displacement is signed extended to 64bit, don't allow
8540 disp32 and turn off disp32s if they are out of range. */
8541 i.types[this_operand].bitfield.disp32 = 0;
8542 if (!fits_in_signed_long (exp->X_add_number))
8543 {
8544 i.types[this_operand].bitfield.disp32s = 0;
8545 if (i.types[this_operand].bitfield.baseindex)
8546 {
8547 as_bad (_("0x%lx out range of signed 32bit displacement"),
8548 (long) exp->X_add_number);
8549 ret = 0;
8550 }
8551 }
8552 }
8553
8554 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8555 else if (exp->X_op != O_constant
8556 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8557 && exp_seg != absolute_section
8558 && exp_seg != text_section
8559 && exp_seg != data_section
8560 && exp_seg != bss_section
8561 && exp_seg != undefined_section
8562 && !bfd_is_com_section (exp_seg))
8563 {
8564 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8565 ret = 0;
8566 }
8567 #endif
8568
8569 /* Check if this is a displacement only operand. */
8570 bigdisp = i.types[this_operand];
8571 bigdisp.bitfield.disp8 = 0;
8572 bigdisp.bitfield.disp16 = 0;
8573 bigdisp.bitfield.disp32 = 0;
8574 bigdisp.bitfield.disp32s = 0;
8575 bigdisp.bitfield.disp64 = 0;
8576 if (operand_type_all_zero (&bigdisp))
8577 i.types[this_operand] = operand_type_and (i.types[this_operand],
8578 types);
8579
8580 return ret;
8581 }
8582
8583 /* Return the active addressing mode, taking address override and
8584 registers forming the address into consideration. Update the
8585 address override prefix if necessary. */
8586
8587 static enum flag_code
8588 i386_addressing_mode (void)
8589 {
8590 enum flag_code addr_mode;
8591
8592 if (i.prefix[ADDR_PREFIX])
8593 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8594 else
8595 {
8596 addr_mode = flag_code;
8597
8598 #if INFER_ADDR_PREFIX
8599 if (i.mem_operands == 0)
8600 {
8601 /* Infer address prefix from the first memory operand. */
8602 const reg_entry *addr_reg = i.base_reg;
8603
8604 if (addr_reg == NULL)
8605 addr_reg = i.index_reg;
8606
8607 if (addr_reg)
8608 {
8609 if (addr_reg->reg_num == RegEip
8610 || addr_reg->reg_num == RegEiz
8611 || addr_reg->reg_type.bitfield.dword)
8612 addr_mode = CODE_32BIT;
8613 else if (flag_code != CODE_64BIT
8614 && addr_reg->reg_type.bitfield.word)
8615 addr_mode = CODE_16BIT;
8616
8617 if (addr_mode != flag_code)
8618 {
8619 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8620 i.prefixes += 1;
8621 /* Change the size of any displacement too. At most one
8622 of Disp16 or Disp32 is set.
8623 FIXME. There doesn't seem to be any real need for
8624 separate Disp16 and Disp32 flags. The same goes for
8625 Imm16 and Imm32. Removing them would probably clean
8626 up the code quite a lot. */
8627 if (flag_code != CODE_64BIT
8628 && (i.types[this_operand].bitfield.disp16
8629 || i.types[this_operand].bitfield.disp32))
8630 i.types[this_operand]
8631 = operand_type_xor (i.types[this_operand], disp16_32);
8632 }
8633 }
8634 }
8635 #endif
8636 }
8637
8638 return addr_mode;
8639 }
8640
8641 /* Make sure the memory operand we've been dealt is valid.
8642 Return 1 on success, 0 on a failure. */
8643
8644 static int
8645 i386_index_check (const char *operand_string)
8646 {
8647 const char *kind = "base/index";
8648 enum flag_code addr_mode = i386_addressing_mode ();
8649
8650 if (current_templates->start->opcode_modifier.isstring
8651 && !current_templates->start->opcode_modifier.immext
8652 && (current_templates->end[-1].opcode_modifier.isstring
8653 || i.mem_operands))
8654 {
8655 /* Memory operands of string insns are special in that they only allow
8656 a single register (rDI, rSI, or rBX) as their memory address. */
8657 const reg_entry *expected_reg;
8658 static const char *di_si[][2] =
8659 {
8660 { "esi", "edi" },
8661 { "si", "di" },
8662 { "rsi", "rdi" }
8663 };
8664 static const char *bx[] = { "ebx", "bx", "rbx" };
8665
8666 kind = "string address";
8667
8668 if (current_templates->start->opcode_modifier.repprefixok)
8669 {
8670 i386_operand_type type = current_templates->end[-1].operand_types[0];
8671
8672 if (!type.bitfield.baseindex
8673 || ((!i.mem_operands != !intel_syntax)
8674 && current_templates->end[-1].operand_types[1]
8675 .bitfield.baseindex))
8676 type = current_templates->end[-1].operand_types[1];
8677 expected_reg = hash_find (reg_hash,
8678 di_si[addr_mode][type.bitfield.esseg]);
8679
8680 }
8681 else
8682 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8683
8684 if (i.base_reg != expected_reg
8685 || i.index_reg
8686 || operand_type_check (i.types[this_operand], disp))
8687 {
8688 /* The second memory operand must have the same size as
8689 the first one. */
8690 if (i.mem_operands
8691 && i.base_reg
8692 && !((addr_mode == CODE_64BIT
8693 && i.base_reg->reg_type.bitfield.qword)
8694 || (addr_mode == CODE_32BIT
8695 ? i.base_reg->reg_type.bitfield.dword
8696 : i.base_reg->reg_type.bitfield.word)))
8697 goto bad_address;
8698
8699 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8700 operand_string,
8701 intel_syntax ? '[' : '(',
8702 register_prefix,
8703 expected_reg->reg_name,
8704 intel_syntax ? ']' : ')');
8705 return 1;
8706 }
8707 else
8708 return 1;
8709
8710 bad_address:
8711 as_bad (_("`%s' is not a valid %s expression"),
8712 operand_string, kind);
8713 return 0;
8714 }
8715 else
8716 {
8717 if (addr_mode != CODE_16BIT)
8718 {
8719 /* 32-bit/64-bit checks. */
8720 if ((i.base_reg
8721 && (addr_mode == CODE_64BIT
8722 ? !i.base_reg->reg_type.bitfield.qword
8723 : !i.base_reg->reg_type.bitfield.dword)
8724 && (i.index_reg
8725 || (i.base_reg->reg_num
8726 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8727 || (i.index_reg
8728 && !i.index_reg->reg_type.bitfield.regxmm
8729 && !i.index_reg->reg_type.bitfield.regymm
8730 && !i.index_reg->reg_type.bitfield.regzmm
8731 && ((addr_mode == CODE_64BIT
8732 ? !(i.index_reg->reg_type.bitfield.qword
8733 || i.index_reg->reg_num == RegRiz)
8734 : !(i.index_reg->reg_type.bitfield.dword
8735 || i.index_reg->reg_num == RegEiz))
8736 || !i.index_reg->reg_type.bitfield.baseindex)))
8737 goto bad_address;
8738
8739 /* bndmk, bndldx, and bndstx have special restrictions. */
8740 if (current_templates->start->base_opcode == 0xf30f1b
8741 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8742 {
8743 /* They cannot use RIP-relative addressing. */
8744 if (i.base_reg && i.base_reg->reg_num == RegRip)
8745 {
8746 as_bad (_("`%s' cannot be used here"), operand_string);
8747 return 0;
8748 }
8749
8750 /* bndldx and bndstx ignore their scale factor. */
8751 if (current_templates->start->base_opcode != 0xf30f1b
8752 && i.log2_scale_factor)
8753 as_warn (_("register scaling is being ignored here"));
8754 }
8755 }
8756 else
8757 {
8758 /* 16-bit checks. */
8759 if ((i.base_reg
8760 && (!i.base_reg->reg_type.bitfield.word
8761 || !i.base_reg->reg_type.bitfield.baseindex))
8762 || (i.index_reg
8763 && (!i.index_reg->reg_type.bitfield.word
8764 || !i.index_reg->reg_type.bitfield.baseindex
8765 || !(i.base_reg
8766 && i.base_reg->reg_num < 6
8767 && i.index_reg->reg_num >= 6
8768 && i.log2_scale_factor == 0))))
8769 goto bad_address;
8770 }
8771 }
8772 return 1;
8773 }
8774
8775 /* Handle vector immediates. */
8776
8777 static int
8778 RC_SAE_immediate (const char *imm_start)
8779 {
8780 unsigned int match_found, j;
8781 const char *pstr = imm_start;
8782 expressionS *exp;
8783
8784 if (*pstr != '{')
8785 return 0;
8786
8787 pstr++;
8788 match_found = 0;
8789 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8790 {
8791 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8792 {
8793 if (!i.rounding)
8794 {
8795 rc_op.type = RC_NamesTable[j].type;
8796 rc_op.operand = this_operand;
8797 i.rounding = &rc_op;
8798 }
8799 else
8800 {
8801 as_bad (_("duplicated `%s'"), imm_start);
8802 return 0;
8803 }
8804 pstr += RC_NamesTable[j].len;
8805 match_found = 1;
8806 break;
8807 }
8808 }
8809 if (!match_found)
8810 return 0;
8811
8812 if (*pstr++ != '}')
8813 {
8814 as_bad (_("Missing '}': '%s'"), imm_start);
8815 return 0;
8816 }
8817 /* RC/SAE immediate string should contain nothing more. */;
8818 if (*pstr != 0)
8819 {
8820 as_bad (_("Junk after '}': '%s'"), imm_start);
8821 return 0;
8822 }
8823
8824 exp = &im_expressions[i.imm_operands++];
8825 i.op[this_operand].imms = exp;
8826
8827 exp->X_op = O_constant;
8828 exp->X_add_number = 0;
8829 exp->X_add_symbol = (symbolS *) 0;
8830 exp->X_op_symbol = (symbolS *) 0;
8831
8832 i.types[this_operand].bitfield.imm8 = 1;
8833 return 1;
8834 }
8835
8836 /* Only string instructions can have a second memory operand, so
8837 reduce current_templates to just those if it contains any. */
8838 static int
8839 maybe_adjust_templates (void)
8840 {
8841 const insn_template *t;
8842
8843 gas_assert (i.mem_operands == 1);
8844
8845 for (t = current_templates->start; t < current_templates->end; ++t)
8846 if (t->opcode_modifier.isstring)
8847 break;
8848
8849 if (t < current_templates->end)
8850 {
8851 static templates aux_templates;
8852 bfd_boolean recheck;
8853
8854 aux_templates.start = t;
8855 for (; t < current_templates->end; ++t)
8856 if (!t->opcode_modifier.isstring)
8857 break;
8858 aux_templates.end = t;
8859
8860 /* Determine whether to re-check the first memory operand. */
8861 recheck = (aux_templates.start != current_templates->start
8862 || t != current_templates->end);
8863
8864 current_templates = &aux_templates;
8865
8866 if (recheck)
8867 {
8868 i.mem_operands = 0;
8869 if (i.memop1_string != NULL
8870 && i386_index_check (i.memop1_string) == 0)
8871 return 0;
8872 i.mem_operands = 1;
8873 }
8874 }
8875
8876 return 1;
8877 }
8878
8879 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8880 on error. */
8881
8882 static int
8883 i386_att_operand (char *operand_string)
8884 {
8885 const reg_entry *r;
8886 char *end_op;
8887 char *op_string = operand_string;
8888
8889 if (is_space_char (*op_string))
8890 ++op_string;
8891
8892 /* We check for an absolute prefix (differentiating,
8893 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8894 if (*op_string == ABSOLUTE_PREFIX)
8895 {
8896 ++op_string;
8897 if (is_space_char (*op_string))
8898 ++op_string;
8899 i.types[this_operand].bitfield.jumpabsolute = 1;
8900 }
8901
8902 /* Check if operand is a register. */
8903 if ((r = parse_register (op_string, &end_op)) != NULL)
8904 {
8905 i386_operand_type temp;
8906
8907 /* Check for a segment override by searching for ':' after a
8908 segment register. */
8909 op_string = end_op;
8910 if (is_space_char (*op_string))
8911 ++op_string;
8912 if (*op_string == ':'
8913 && (r->reg_type.bitfield.sreg2
8914 || r->reg_type.bitfield.sreg3))
8915 {
8916 switch (r->reg_num)
8917 {
8918 case 0:
8919 i.seg[i.mem_operands] = &es;
8920 break;
8921 case 1:
8922 i.seg[i.mem_operands] = &cs;
8923 break;
8924 case 2:
8925 i.seg[i.mem_operands] = &ss;
8926 break;
8927 case 3:
8928 i.seg[i.mem_operands] = &ds;
8929 break;
8930 case 4:
8931 i.seg[i.mem_operands] = &fs;
8932 break;
8933 case 5:
8934 i.seg[i.mem_operands] = &gs;
8935 break;
8936 }
8937
8938 /* Skip the ':' and whitespace. */
8939 ++op_string;
8940 if (is_space_char (*op_string))
8941 ++op_string;
8942
8943 if (!is_digit_char (*op_string)
8944 && !is_identifier_char (*op_string)
8945 && *op_string != '('
8946 && *op_string != ABSOLUTE_PREFIX)
8947 {
8948 as_bad (_("bad memory operand `%s'"), op_string);
8949 return 0;
8950 }
8951 /* Handle case of %es:*foo. */
8952 if (*op_string == ABSOLUTE_PREFIX)
8953 {
8954 ++op_string;
8955 if (is_space_char (*op_string))
8956 ++op_string;
8957 i.types[this_operand].bitfield.jumpabsolute = 1;
8958 }
8959 goto do_memory_reference;
8960 }
8961
8962 /* Handle vector operations. */
8963 if (*op_string == '{')
8964 {
8965 op_string = check_VecOperations (op_string, NULL);
8966 if (op_string == NULL)
8967 return 0;
8968 }
8969
8970 if (*op_string)
8971 {
8972 as_bad (_("junk `%s' after register"), op_string);
8973 return 0;
8974 }
8975 temp = r->reg_type;
8976 temp.bitfield.baseindex = 0;
8977 i.types[this_operand] = operand_type_or (i.types[this_operand],
8978 temp);
8979 i.types[this_operand].bitfield.unspecified = 0;
8980 i.op[this_operand].regs = r;
8981 i.reg_operands++;
8982 }
8983 else if (*op_string == REGISTER_PREFIX)
8984 {
8985 as_bad (_("bad register name `%s'"), op_string);
8986 return 0;
8987 }
8988 else if (*op_string == IMMEDIATE_PREFIX)
8989 {
8990 ++op_string;
8991 if (i.types[this_operand].bitfield.jumpabsolute)
8992 {
8993 as_bad (_("immediate operand illegal with absolute jump"));
8994 return 0;
8995 }
8996 if (!i386_immediate (op_string))
8997 return 0;
8998 }
8999 else if (RC_SAE_immediate (operand_string))
9000 {
9001 /* If it is a RC or SAE immediate, do nothing. */
9002 ;
9003 }
9004 else if (is_digit_char (*op_string)
9005 || is_identifier_char (*op_string)
9006 || *op_string == '"'
9007 || *op_string == '(')
9008 {
9009 /* This is a memory reference of some sort. */
9010 char *base_string;
9011
9012 /* Start and end of displacement string expression (if found). */
9013 char *displacement_string_start;
9014 char *displacement_string_end;
9015 char *vop_start;
9016
9017 do_memory_reference:
9018 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9019 return 0;
9020 if ((i.mem_operands == 1
9021 && !current_templates->start->opcode_modifier.isstring)
9022 || i.mem_operands == 2)
9023 {
9024 as_bad (_("too many memory references for `%s'"),
9025 current_templates->start->name);
9026 return 0;
9027 }
9028
9029 /* Check for base index form. We detect the base index form by
9030 looking for an ')' at the end of the operand, searching
9031 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9032 after the '('. */
9033 base_string = op_string + strlen (op_string);
9034
9035 /* Handle vector operations. */
9036 vop_start = strchr (op_string, '{');
9037 if (vop_start && vop_start < base_string)
9038 {
9039 if (check_VecOperations (vop_start, base_string) == NULL)
9040 return 0;
9041 base_string = vop_start;
9042 }
9043
9044 --base_string;
9045 if (is_space_char (*base_string))
9046 --base_string;
9047
9048 /* If we only have a displacement, set-up for it to be parsed later. */
9049 displacement_string_start = op_string;
9050 displacement_string_end = base_string + 1;
9051
9052 if (*base_string == ')')
9053 {
9054 char *temp_string;
9055 unsigned int parens_balanced = 1;
9056 /* We've already checked that the number of left & right ()'s are
9057 equal, so this loop will not be infinite. */
9058 do
9059 {
9060 base_string--;
9061 if (*base_string == ')')
9062 parens_balanced++;
9063 if (*base_string == '(')
9064 parens_balanced--;
9065 }
9066 while (parens_balanced);
9067
9068 temp_string = base_string;
9069
9070 /* Skip past '(' and whitespace. */
9071 ++base_string;
9072 if (is_space_char (*base_string))
9073 ++base_string;
9074
9075 if (*base_string == ','
9076 || ((i.base_reg = parse_register (base_string, &end_op))
9077 != NULL))
9078 {
9079 displacement_string_end = temp_string;
9080
9081 i.types[this_operand].bitfield.baseindex = 1;
9082
9083 if (i.base_reg)
9084 {
9085 base_string = end_op;
9086 if (is_space_char (*base_string))
9087 ++base_string;
9088 }
9089
9090 /* There may be an index reg or scale factor here. */
9091 if (*base_string == ',')
9092 {
9093 ++base_string;
9094 if (is_space_char (*base_string))
9095 ++base_string;
9096
9097 if ((i.index_reg = parse_register (base_string, &end_op))
9098 != NULL)
9099 {
9100 base_string = end_op;
9101 if (is_space_char (*base_string))
9102 ++base_string;
9103 if (*base_string == ',')
9104 {
9105 ++base_string;
9106 if (is_space_char (*base_string))
9107 ++base_string;
9108 }
9109 else if (*base_string != ')')
9110 {
9111 as_bad (_("expecting `,' or `)' "
9112 "after index register in `%s'"),
9113 operand_string);
9114 return 0;
9115 }
9116 }
9117 else if (*base_string == REGISTER_PREFIX)
9118 {
9119 end_op = strchr (base_string, ',');
9120 if (end_op)
9121 *end_op = '\0';
9122 as_bad (_("bad register name `%s'"), base_string);
9123 return 0;
9124 }
9125
9126 /* Check for scale factor. */
9127 if (*base_string != ')')
9128 {
9129 char *end_scale = i386_scale (base_string);
9130
9131 if (!end_scale)
9132 return 0;
9133
9134 base_string = end_scale;
9135 if (is_space_char (*base_string))
9136 ++base_string;
9137 if (*base_string != ')')
9138 {
9139 as_bad (_("expecting `)' "
9140 "after scale factor in `%s'"),
9141 operand_string);
9142 return 0;
9143 }
9144 }
9145 else if (!i.index_reg)
9146 {
9147 as_bad (_("expecting index register or scale factor "
9148 "after `,'; got '%c'"),
9149 *base_string);
9150 return 0;
9151 }
9152 }
9153 else if (*base_string != ')')
9154 {
9155 as_bad (_("expecting `,' or `)' "
9156 "after base register in `%s'"),
9157 operand_string);
9158 return 0;
9159 }
9160 }
9161 else if (*base_string == REGISTER_PREFIX)
9162 {
9163 end_op = strchr (base_string, ',');
9164 if (end_op)
9165 *end_op = '\0';
9166 as_bad (_("bad register name `%s'"), base_string);
9167 return 0;
9168 }
9169 }
9170
9171 /* If there's an expression beginning the operand, parse it,
9172 assuming displacement_string_start and
9173 displacement_string_end are meaningful. */
9174 if (displacement_string_start != displacement_string_end)
9175 {
9176 if (!i386_displacement (displacement_string_start,
9177 displacement_string_end))
9178 return 0;
9179 }
9180
9181 /* Special case for (%dx) while doing input/output op. */
9182 if (i.base_reg
9183 && operand_type_equal (&i.base_reg->reg_type,
9184 &reg16_inoutportreg)
9185 && i.index_reg == 0
9186 && i.log2_scale_factor == 0
9187 && i.seg[i.mem_operands] == 0
9188 && !operand_type_check (i.types[this_operand], disp))
9189 {
9190 i.types[this_operand] = inoutportreg;
9191 return 1;
9192 }
9193
9194 if (i386_index_check (operand_string) == 0)
9195 return 0;
9196 i.types[this_operand].bitfield.mem = 1;
9197 if (i.mem_operands == 0)
9198 i.memop1_string = xstrdup (operand_string);
9199 i.mem_operands++;
9200 }
9201 else
9202 {
9203 /* It's not a memory operand; argh! */
9204 as_bad (_("invalid char %s beginning operand %d `%s'"),
9205 output_invalid (*op_string),
9206 this_operand + 1,
9207 op_string);
9208 return 0;
9209 }
9210 return 1; /* Normal return. */
9211 }
9212 \f
9213 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9214 that an rs_machine_dependent frag may reach. */
9215
9216 unsigned int
9217 i386_frag_max_var (fragS *frag)
9218 {
9219 /* The only relaxable frags are for jumps.
9220 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9221 gas_assert (frag->fr_type == rs_machine_dependent);
9222 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9223 }
9224
9225 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9226 static int
9227 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9228 {
9229 /* STT_GNU_IFUNC symbol must go through PLT. */
9230 if ((symbol_get_bfdsym (fr_symbol)->flags
9231 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9232 return 0;
9233
9234 if (!S_IS_EXTERNAL (fr_symbol))
9235 /* Symbol may be weak or local. */
9236 return !S_IS_WEAK (fr_symbol);
9237
9238 /* Global symbols with non-default visibility can't be preempted. */
9239 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9240 return 1;
9241
9242 if (fr_var != NO_RELOC)
9243 switch ((enum bfd_reloc_code_real) fr_var)
9244 {
9245 case BFD_RELOC_386_PLT32:
9246 case BFD_RELOC_X86_64_PLT32:
9247 /* Symbol with PLT relocation may be preempted. */
9248 return 0;
9249 default:
9250 abort ();
9251 }
9252
9253 /* Global symbols with default visibility in a shared library may be
9254 preempted by another definition. */
9255 return !shared;
9256 }
9257 #endif
9258
9259 /* md_estimate_size_before_relax()
9260
9261 Called just before relax() for rs_machine_dependent frags. The x86
9262 assembler uses these frags to handle variable size jump
9263 instructions.
9264
9265 Any symbol that is now undefined will not become defined.
9266 Return the correct fr_subtype in the frag.
9267 Return the initial "guess for variable size of frag" to caller.
9268 The guess is actually the growth beyond the fixed part. Whatever
9269 we do to grow the fixed or variable part contributes to our
9270 returned value. */
9271
9272 int
9273 md_estimate_size_before_relax (fragS *fragP, segT segment)
9274 {
9275 /* We've already got fragP->fr_subtype right; all we have to do is
9276 check for un-relaxable symbols. On an ELF system, we can't relax
9277 an externally visible symbol, because it may be overridden by a
9278 shared library. */
9279 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9280 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9281 || (IS_ELF
9282 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9283 fragP->fr_var))
9284 #endif
9285 #if defined (OBJ_COFF) && defined (TE_PE)
9286 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9287 && S_IS_WEAK (fragP->fr_symbol))
9288 #endif
9289 )
9290 {
9291 /* Symbol is undefined in this segment, or we need to keep a
9292 reloc so that weak symbols can be overridden. */
9293 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9294 enum bfd_reloc_code_real reloc_type;
9295 unsigned char *opcode;
9296 int old_fr_fix;
9297
9298 if (fragP->fr_var != NO_RELOC)
9299 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9300 else if (size == 2)
9301 reloc_type = BFD_RELOC_16_PCREL;
9302 else
9303 reloc_type = BFD_RELOC_32_PCREL;
9304
9305 old_fr_fix = fragP->fr_fix;
9306 opcode = (unsigned char *) fragP->fr_opcode;
9307
9308 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9309 {
9310 case UNCOND_JUMP:
9311 /* Make jmp (0xeb) a (d)word displacement jump. */
9312 opcode[0] = 0xe9;
9313 fragP->fr_fix += size;
9314 fix_new (fragP, old_fr_fix, size,
9315 fragP->fr_symbol,
9316 fragP->fr_offset, 1,
9317 reloc_type);
9318 break;
9319
9320 case COND_JUMP86:
9321 if (size == 2
9322 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9323 {
9324 /* Negate the condition, and branch past an
9325 unconditional jump. */
9326 opcode[0] ^= 1;
9327 opcode[1] = 3;
9328 /* Insert an unconditional jump. */
9329 opcode[2] = 0xe9;
9330 /* We added two extra opcode bytes, and have a two byte
9331 offset. */
9332 fragP->fr_fix += 2 + 2;
9333 fix_new (fragP, old_fr_fix + 2, 2,
9334 fragP->fr_symbol,
9335 fragP->fr_offset, 1,
9336 reloc_type);
9337 break;
9338 }
9339 /* Fall through. */
9340
9341 case COND_JUMP:
9342 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9343 {
9344 fixS *fixP;
9345
9346 fragP->fr_fix += 1;
9347 fixP = fix_new (fragP, old_fr_fix, 1,
9348 fragP->fr_symbol,
9349 fragP->fr_offset, 1,
9350 BFD_RELOC_8_PCREL);
9351 fixP->fx_signed = 1;
9352 break;
9353 }
9354
9355 /* This changes the byte-displacement jump 0x7N
9356 to the (d)word-displacement jump 0x0f,0x8N. */
9357 opcode[1] = opcode[0] + 0x10;
9358 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9359 /* We've added an opcode byte. */
9360 fragP->fr_fix += 1 + size;
9361 fix_new (fragP, old_fr_fix + 1, size,
9362 fragP->fr_symbol,
9363 fragP->fr_offset, 1,
9364 reloc_type);
9365 break;
9366
9367 default:
9368 BAD_CASE (fragP->fr_subtype);
9369 break;
9370 }
9371 frag_wane (fragP);
9372 return fragP->fr_fix - old_fr_fix;
9373 }
9374
9375 /* Guess size depending on current relax state. Initially the relax
9376 state will correspond to a short jump and we return 1, because
9377 the variable part of the frag (the branch offset) is one byte
9378 long. However, we can relax a section more than once and in that
9379 case we must either set fr_subtype back to the unrelaxed state,
9380 or return the value for the appropriate branch. */
9381 return md_relax_table[fragP->fr_subtype].rlx_length;
9382 }
9383
9384 /* Called after relax() is finished.
9385
9386 In: Address of frag.
9387 fr_type == rs_machine_dependent.
9388 fr_subtype is what the address relaxed to.
9389
9390 Out: Any fixSs and constants are set up.
9391 Caller will turn frag into a ".space 0". */
9392
9393 void
9394 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9395 fragS *fragP)
9396 {
9397 unsigned char *opcode;
9398 unsigned char *where_to_put_displacement = NULL;
9399 offsetT target_address;
9400 offsetT opcode_address;
9401 unsigned int extension = 0;
9402 offsetT displacement_from_opcode_start;
9403
9404 opcode = (unsigned char *) fragP->fr_opcode;
9405
9406 /* Address we want to reach in file space. */
9407 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9408
9409 /* Address opcode resides at in file space. */
9410 opcode_address = fragP->fr_address + fragP->fr_fix;
9411
9412 /* Displacement from opcode start to fill into instruction. */
9413 displacement_from_opcode_start = target_address - opcode_address;
9414
9415 if ((fragP->fr_subtype & BIG) == 0)
9416 {
9417 /* Don't have to change opcode. */
9418 extension = 1; /* 1 opcode + 1 displacement */
9419 where_to_put_displacement = &opcode[1];
9420 }
9421 else
9422 {
9423 if (no_cond_jump_promotion
9424 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9425 as_warn_where (fragP->fr_file, fragP->fr_line,
9426 _("long jump required"));
9427
9428 switch (fragP->fr_subtype)
9429 {
9430 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9431 extension = 4; /* 1 opcode + 4 displacement */
9432 opcode[0] = 0xe9;
9433 where_to_put_displacement = &opcode[1];
9434 break;
9435
9436 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9437 extension = 2; /* 1 opcode + 2 displacement */
9438 opcode[0] = 0xe9;
9439 where_to_put_displacement = &opcode[1];
9440 break;
9441
9442 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9443 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9444 extension = 5; /* 2 opcode + 4 displacement */
9445 opcode[1] = opcode[0] + 0x10;
9446 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9447 where_to_put_displacement = &opcode[2];
9448 break;
9449
9450 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9451 extension = 3; /* 2 opcode + 2 displacement */
9452 opcode[1] = opcode[0] + 0x10;
9453 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9454 where_to_put_displacement = &opcode[2];
9455 break;
9456
9457 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9458 extension = 4;
9459 opcode[0] ^= 1;
9460 opcode[1] = 3;
9461 opcode[2] = 0xe9;
9462 where_to_put_displacement = &opcode[3];
9463 break;
9464
9465 default:
9466 BAD_CASE (fragP->fr_subtype);
9467 break;
9468 }
9469 }
9470
9471 /* If size if less then four we are sure that the operand fits,
9472 but if it's 4, then it could be that the displacement is larger
9473 then -/+ 2GB. */
9474 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9475 && object_64bit
9476 && ((addressT) (displacement_from_opcode_start - extension
9477 + ((addressT) 1 << 31))
9478 > (((addressT) 2 << 31) - 1)))
9479 {
9480 as_bad_where (fragP->fr_file, fragP->fr_line,
9481 _("jump target out of range"));
9482 /* Make us emit 0. */
9483 displacement_from_opcode_start = extension;
9484 }
9485 /* Now put displacement after opcode. */
9486 md_number_to_chars ((char *) where_to_put_displacement,
9487 (valueT) (displacement_from_opcode_start - extension),
9488 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9489 fragP->fr_fix += extension;
9490 }
9491 \f
9492 /* Apply a fixup (fixP) to segment data, once it has been determined
9493 by our caller that we have all the info we need to fix it up.
9494
9495 Parameter valP is the pointer to the value of the bits.
9496
9497 On the 386, immediates, displacements, and data pointers are all in
9498 the same (little-endian) format, so we don't need to care about which
9499 we are handling. */
9500
9501 void
9502 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9503 {
9504 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9505 valueT value = *valP;
9506
9507 #if !defined (TE_Mach)
9508 if (fixP->fx_pcrel)
9509 {
9510 switch (fixP->fx_r_type)
9511 {
9512 default:
9513 break;
9514
9515 case BFD_RELOC_64:
9516 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9517 break;
9518 case BFD_RELOC_32:
9519 case BFD_RELOC_X86_64_32S:
9520 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9521 break;
9522 case BFD_RELOC_16:
9523 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9524 break;
9525 case BFD_RELOC_8:
9526 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9527 break;
9528 }
9529 }
9530
9531 if (fixP->fx_addsy != NULL
9532 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9533 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9534 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9535 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9536 && !use_rela_relocations)
9537 {
9538 /* This is a hack. There should be a better way to handle this.
9539 This covers for the fact that bfd_install_relocation will
9540 subtract the current location (for partial_inplace, PC relative
9541 relocations); see more below. */
9542 #ifndef OBJ_AOUT
9543 if (IS_ELF
9544 #ifdef TE_PE
9545 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9546 #endif
9547 )
9548 value += fixP->fx_where + fixP->fx_frag->fr_address;
9549 #endif
9550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9551 if (IS_ELF)
9552 {
9553 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9554
9555 if ((sym_seg == seg
9556 || (symbol_section_p (fixP->fx_addsy)
9557 && sym_seg != absolute_section))
9558 && !generic_force_reloc (fixP))
9559 {
9560 /* Yes, we add the values in twice. This is because
9561 bfd_install_relocation subtracts them out again. I think
9562 bfd_install_relocation is broken, but I don't dare change
9563 it. FIXME. */
9564 value += fixP->fx_where + fixP->fx_frag->fr_address;
9565 }
9566 }
9567 #endif
9568 #if defined (OBJ_COFF) && defined (TE_PE)
9569 /* For some reason, the PE format does not store a
9570 section address offset for a PC relative symbol. */
9571 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9572 || S_IS_WEAK (fixP->fx_addsy))
9573 value += md_pcrel_from (fixP);
9574 #endif
9575 }
9576 #if defined (OBJ_COFF) && defined (TE_PE)
9577 if (fixP->fx_addsy != NULL
9578 && S_IS_WEAK (fixP->fx_addsy)
9579 /* PR 16858: Do not modify weak function references. */
9580 && ! fixP->fx_pcrel)
9581 {
9582 #if !defined (TE_PEP)
9583 /* For x86 PE weak function symbols are neither PC-relative
9584 nor do they set S_IS_FUNCTION. So the only reliable way
9585 to detect them is to check the flags of their containing
9586 section. */
9587 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9588 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9589 ;
9590 else
9591 #endif
9592 value -= S_GET_VALUE (fixP->fx_addsy);
9593 }
9594 #endif
9595
9596 /* Fix a few things - the dynamic linker expects certain values here,
9597 and we must not disappoint it. */
9598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9599 if (IS_ELF && fixP->fx_addsy)
9600 switch (fixP->fx_r_type)
9601 {
9602 case BFD_RELOC_386_PLT32:
9603 case BFD_RELOC_X86_64_PLT32:
9604 /* Make the jump instruction point to the address of the operand. At
9605 runtime we merely add the offset to the actual PLT entry. */
9606 value = -4;
9607 break;
9608
9609 case BFD_RELOC_386_TLS_GD:
9610 case BFD_RELOC_386_TLS_LDM:
9611 case BFD_RELOC_386_TLS_IE_32:
9612 case BFD_RELOC_386_TLS_IE:
9613 case BFD_RELOC_386_TLS_GOTIE:
9614 case BFD_RELOC_386_TLS_GOTDESC:
9615 case BFD_RELOC_X86_64_TLSGD:
9616 case BFD_RELOC_X86_64_TLSLD:
9617 case BFD_RELOC_X86_64_GOTTPOFF:
9618 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9619 value = 0; /* Fully resolved at runtime. No addend. */
9620 /* Fallthrough */
9621 case BFD_RELOC_386_TLS_LE:
9622 case BFD_RELOC_386_TLS_LDO_32:
9623 case BFD_RELOC_386_TLS_LE_32:
9624 case BFD_RELOC_X86_64_DTPOFF32:
9625 case BFD_RELOC_X86_64_DTPOFF64:
9626 case BFD_RELOC_X86_64_TPOFF32:
9627 case BFD_RELOC_X86_64_TPOFF64:
9628 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9629 break;
9630
9631 case BFD_RELOC_386_TLS_DESC_CALL:
9632 case BFD_RELOC_X86_64_TLSDESC_CALL:
9633 value = 0; /* Fully resolved at runtime. No addend. */
9634 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9635 fixP->fx_done = 0;
9636 return;
9637
9638 case BFD_RELOC_VTABLE_INHERIT:
9639 case BFD_RELOC_VTABLE_ENTRY:
9640 fixP->fx_done = 0;
9641 return;
9642
9643 default:
9644 break;
9645 }
9646 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9647 *valP = value;
9648 #endif /* !defined (TE_Mach) */
9649
9650 /* Are we finished with this relocation now? */
9651 if (fixP->fx_addsy == NULL)
9652 fixP->fx_done = 1;
9653 #if defined (OBJ_COFF) && defined (TE_PE)
9654 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9655 {
9656 fixP->fx_done = 0;
9657 /* Remember value for tc_gen_reloc. */
9658 fixP->fx_addnumber = value;
9659 /* Clear out the frag for now. */
9660 value = 0;
9661 }
9662 #endif
9663 else if (use_rela_relocations)
9664 {
9665 fixP->fx_no_overflow = 1;
9666 /* Remember value for tc_gen_reloc. */
9667 fixP->fx_addnumber = value;
9668 value = 0;
9669 }
9670
9671 md_number_to_chars (p, value, fixP->fx_size);
9672 }
9673 \f
9674 const char *
9675 md_atof (int type, char *litP, int *sizeP)
9676 {
9677 /* This outputs the LITTLENUMs in REVERSE order;
9678 in accord with the bigendian 386. */
9679 return ieee_md_atof (type, litP, sizeP, FALSE);
9680 }
9681 \f
9682 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9683
9684 static char *
9685 output_invalid (int c)
9686 {
9687 if (ISPRINT (c))
9688 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9689 "'%c'", c);
9690 else
9691 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9692 "(0x%x)", (unsigned char) c);
9693 return output_invalid_buf;
9694 }
9695
9696 /* REG_STRING starts *before* REGISTER_PREFIX. */
9697
9698 static const reg_entry *
9699 parse_real_register (char *reg_string, char **end_op)
9700 {
9701 char *s = reg_string;
9702 char *p;
9703 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9704 const reg_entry *r;
9705
9706 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9707 if (*s == REGISTER_PREFIX)
9708 ++s;
9709
9710 if (is_space_char (*s))
9711 ++s;
9712
9713 p = reg_name_given;
9714 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9715 {
9716 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9717 return (const reg_entry *) NULL;
9718 s++;
9719 }
9720
9721 /* For naked regs, make sure that we are not dealing with an identifier.
9722 This prevents confusing an identifier like `eax_var' with register
9723 `eax'. */
9724 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9725 return (const reg_entry *) NULL;
9726
9727 *end_op = s;
9728
9729 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9730
9731 /* Handle floating point regs, allowing spaces in the (i) part. */
9732 if (r == i386_regtab /* %st is first entry of table */)
9733 {
9734 if (is_space_char (*s))
9735 ++s;
9736 if (*s == '(')
9737 {
9738 ++s;
9739 if (is_space_char (*s))
9740 ++s;
9741 if (*s >= '0' && *s <= '7')
9742 {
9743 int fpr = *s - '0';
9744 ++s;
9745 if (is_space_char (*s))
9746 ++s;
9747 if (*s == ')')
9748 {
9749 *end_op = s + 1;
9750 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9751 know (r);
9752 return r + fpr;
9753 }
9754 }
9755 /* We have "%st(" then garbage. */
9756 return (const reg_entry *) NULL;
9757 }
9758 }
9759
9760 if (r == NULL || allow_pseudo_reg)
9761 return r;
9762
9763 if (operand_type_all_zero (&r->reg_type))
9764 return (const reg_entry *) NULL;
9765
9766 if ((r->reg_type.bitfield.dword
9767 || r->reg_type.bitfield.sreg3
9768 || r->reg_type.bitfield.control
9769 || r->reg_type.bitfield.debug
9770 || r->reg_type.bitfield.test)
9771 && !cpu_arch_flags.bitfield.cpui386)
9772 return (const reg_entry *) NULL;
9773
9774 if (r->reg_type.bitfield.tbyte
9775 && !cpu_arch_flags.bitfield.cpu8087
9776 && !cpu_arch_flags.bitfield.cpu287
9777 && !cpu_arch_flags.bitfield.cpu387)
9778 return (const reg_entry *) NULL;
9779
9780 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9781 return (const reg_entry *) NULL;
9782
9783 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
9784 return (const reg_entry *) NULL;
9785
9786 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
9787 return (const reg_entry *) NULL;
9788
9789 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9790 return (const reg_entry *) NULL;
9791
9792 if (r->reg_type.bitfield.regmask
9793 && !cpu_arch_flags.bitfield.cpuregmask)
9794 return (const reg_entry *) NULL;
9795
9796 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9797 if (!allow_index_reg
9798 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9799 return (const reg_entry *) NULL;
9800
9801 /* Upper 16 vector register is only available with VREX in 64bit
9802 mode. */
9803 if ((r->reg_flags & RegVRex))
9804 {
9805 if (i.vec_encoding == vex_encoding_default)
9806 i.vec_encoding = vex_encoding_evex;
9807
9808 if (!cpu_arch_flags.bitfield.cpuvrex
9809 || i.vec_encoding != vex_encoding_evex
9810 || flag_code != CODE_64BIT)
9811 return (const reg_entry *) NULL;
9812 }
9813
9814 if (((r->reg_flags & (RegRex64 | RegRex))
9815 || r->reg_type.bitfield.qword)
9816 && (!cpu_arch_flags.bitfield.cpulm
9817 || !operand_type_equal (&r->reg_type, &control))
9818 && flag_code != CODE_64BIT)
9819 return (const reg_entry *) NULL;
9820
9821 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9822 return (const reg_entry *) NULL;
9823
9824 return r;
9825 }
9826
9827 /* REG_STRING starts *before* REGISTER_PREFIX. */
9828
9829 static const reg_entry *
9830 parse_register (char *reg_string, char **end_op)
9831 {
9832 const reg_entry *r;
9833
9834 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9835 r = parse_real_register (reg_string, end_op);
9836 else
9837 r = NULL;
9838 if (!r)
9839 {
9840 char *save = input_line_pointer;
9841 char c;
9842 symbolS *symbolP;
9843
9844 input_line_pointer = reg_string;
9845 c = get_symbol_name (&reg_string);
9846 symbolP = symbol_find (reg_string);
9847 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9848 {
9849 const expressionS *e = symbol_get_value_expression (symbolP);
9850
9851 know (e->X_op == O_register);
9852 know (e->X_add_number >= 0
9853 && (valueT) e->X_add_number < i386_regtab_size);
9854 r = i386_regtab + e->X_add_number;
9855 if ((r->reg_flags & RegVRex))
9856 i.vec_encoding = vex_encoding_evex;
9857 *end_op = input_line_pointer;
9858 }
9859 *input_line_pointer = c;
9860 input_line_pointer = save;
9861 }
9862 return r;
9863 }
9864
9865 int
9866 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9867 {
9868 const reg_entry *r;
9869 char *end = input_line_pointer;
9870
9871 *end = *nextcharP;
9872 r = parse_register (name, &input_line_pointer);
9873 if (r && end <= input_line_pointer)
9874 {
9875 *nextcharP = *input_line_pointer;
9876 *input_line_pointer = 0;
9877 e->X_op = O_register;
9878 e->X_add_number = r - i386_regtab;
9879 return 1;
9880 }
9881 input_line_pointer = end;
9882 *end = 0;
9883 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9884 }
9885
9886 void
9887 md_operand (expressionS *e)
9888 {
9889 char *end;
9890 const reg_entry *r;
9891
9892 switch (*input_line_pointer)
9893 {
9894 case REGISTER_PREFIX:
9895 r = parse_real_register (input_line_pointer, &end);
9896 if (r)
9897 {
9898 e->X_op = O_register;
9899 e->X_add_number = r - i386_regtab;
9900 input_line_pointer = end;
9901 }
9902 break;
9903
9904 case '[':
9905 gas_assert (intel_syntax);
9906 end = input_line_pointer++;
9907 expression (e);
9908 if (*input_line_pointer == ']')
9909 {
9910 ++input_line_pointer;
9911 e->X_op_symbol = make_expr_symbol (e);
9912 e->X_add_symbol = NULL;
9913 e->X_add_number = 0;
9914 e->X_op = O_index;
9915 }
9916 else
9917 {
9918 e->X_op = O_absent;
9919 input_line_pointer = end;
9920 }
9921 break;
9922 }
9923 }
9924
9925 \f
9926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9927 const char *md_shortopts = "kVQ:sqn";
9928 #else
9929 const char *md_shortopts = "qn";
9930 #endif
9931
9932 #define OPTION_32 (OPTION_MD_BASE + 0)
9933 #define OPTION_64 (OPTION_MD_BASE + 1)
9934 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9935 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9936 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9937 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9938 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9939 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9940 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9941 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9942 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9943 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9944 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9945 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9946 #define OPTION_X32 (OPTION_MD_BASE + 14)
9947 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9948 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9949 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9950 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9951 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9952 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9953 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9954 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9955 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9956 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9957 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9958
9959 struct option md_longopts[] =
9960 {
9961 {"32", no_argument, NULL, OPTION_32},
9962 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9963 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9964 {"64", no_argument, NULL, OPTION_64},
9965 #endif
9966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9967 {"x32", no_argument, NULL, OPTION_X32},
9968 {"mshared", no_argument, NULL, OPTION_MSHARED},
9969 #endif
9970 {"divide", no_argument, NULL, OPTION_DIVIDE},
9971 {"march", required_argument, NULL, OPTION_MARCH},
9972 {"mtune", required_argument, NULL, OPTION_MTUNE},
9973 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9974 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9975 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9976 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9977 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9978 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9979 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9980 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9981 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9982 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9983 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9984 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9985 # if defined (TE_PE) || defined (TE_PEP)
9986 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9987 #endif
9988 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
9989 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
9990 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
9991 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
9992 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9993 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
9994 {NULL, no_argument, NULL, 0}
9995 };
9996 size_t md_longopts_size = sizeof (md_longopts);
9997
9998 int
9999 md_parse_option (int c, const char *arg)
10000 {
10001 unsigned int j;
10002 char *arch, *next, *saved;
10003
10004 switch (c)
10005 {
10006 case 'n':
10007 optimize_align_code = 0;
10008 break;
10009
10010 case 'q':
10011 quiet_warnings = 1;
10012 break;
10013
10014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10015 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10016 should be emitted or not. FIXME: Not implemented. */
10017 case 'Q':
10018 break;
10019
10020 /* -V: SVR4 argument to print version ID. */
10021 case 'V':
10022 print_version_id ();
10023 break;
10024
10025 /* -k: Ignore for FreeBSD compatibility. */
10026 case 'k':
10027 break;
10028
10029 case 's':
10030 /* -s: On i386 Solaris, this tells the native assembler to use
10031 .stab instead of .stab.excl. We always use .stab anyhow. */
10032 break;
10033
10034 case OPTION_MSHARED:
10035 shared = 1;
10036 break;
10037 #endif
10038 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10039 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10040 case OPTION_64:
10041 {
10042 const char **list, **l;
10043
10044 list = bfd_target_list ();
10045 for (l = list; *l != NULL; l++)
10046 if (CONST_STRNEQ (*l, "elf64-x86-64")
10047 || strcmp (*l, "coff-x86-64") == 0
10048 || strcmp (*l, "pe-x86-64") == 0
10049 || strcmp (*l, "pei-x86-64") == 0
10050 || strcmp (*l, "mach-o-x86-64") == 0)
10051 {
10052 default_arch = "x86_64";
10053 break;
10054 }
10055 if (*l == NULL)
10056 as_fatal (_("no compiled in support for x86_64"));
10057 free (list);
10058 }
10059 break;
10060 #endif
10061
10062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10063 case OPTION_X32:
10064 if (IS_ELF)
10065 {
10066 const char **list, **l;
10067
10068 list = bfd_target_list ();
10069 for (l = list; *l != NULL; l++)
10070 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10071 {
10072 default_arch = "x86_64:32";
10073 break;
10074 }
10075 if (*l == NULL)
10076 as_fatal (_("no compiled in support for 32bit x86_64"));
10077 free (list);
10078 }
10079 else
10080 as_fatal (_("32bit x86_64 is only supported for ELF"));
10081 break;
10082 #endif
10083
10084 case OPTION_32:
10085 default_arch = "i386";
10086 break;
10087
10088 case OPTION_DIVIDE:
10089 #ifdef SVR4_COMMENT_CHARS
10090 {
10091 char *n, *t;
10092 const char *s;
10093
10094 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10095 t = n;
10096 for (s = i386_comment_chars; *s != '\0'; s++)
10097 if (*s != '/')
10098 *t++ = *s;
10099 *t = '\0';
10100 i386_comment_chars = n;
10101 }
10102 #endif
10103 break;
10104
10105 case OPTION_MARCH:
10106 saved = xstrdup (arg);
10107 arch = saved;
10108 /* Allow -march=+nosse. */
10109 if (*arch == '+')
10110 arch++;
10111 do
10112 {
10113 if (*arch == '.')
10114 as_fatal (_("invalid -march= option: `%s'"), arg);
10115 next = strchr (arch, '+');
10116 if (next)
10117 *next++ = '\0';
10118 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10119 {
10120 if (strcmp (arch, cpu_arch [j].name) == 0)
10121 {
10122 /* Processor. */
10123 if (! cpu_arch[j].flags.bitfield.cpui386)
10124 continue;
10125
10126 cpu_arch_name = cpu_arch[j].name;
10127 cpu_sub_arch_name = NULL;
10128 cpu_arch_flags = cpu_arch[j].flags;
10129 cpu_arch_isa = cpu_arch[j].type;
10130 cpu_arch_isa_flags = cpu_arch[j].flags;
10131 if (!cpu_arch_tune_set)
10132 {
10133 cpu_arch_tune = cpu_arch_isa;
10134 cpu_arch_tune_flags = cpu_arch_isa_flags;
10135 }
10136 break;
10137 }
10138 else if (*cpu_arch [j].name == '.'
10139 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10140 {
10141 /* ISA extension. */
10142 i386_cpu_flags flags;
10143
10144 flags = cpu_flags_or (cpu_arch_flags,
10145 cpu_arch[j].flags);
10146
10147 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10148 {
10149 if (cpu_sub_arch_name)
10150 {
10151 char *name = cpu_sub_arch_name;
10152 cpu_sub_arch_name = concat (name,
10153 cpu_arch[j].name,
10154 (const char *) NULL);
10155 free (name);
10156 }
10157 else
10158 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10159 cpu_arch_flags = flags;
10160 cpu_arch_isa_flags = flags;
10161 }
10162 break;
10163 }
10164 }
10165
10166 if (j >= ARRAY_SIZE (cpu_arch))
10167 {
10168 /* Disable an ISA extension. */
10169 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10170 if (strcmp (arch, cpu_noarch [j].name) == 0)
10171 {
10172 i386_cpu_flags flags;
10173
10174 flags = cpu_flags_and_not (cpu_arch_flags,
10175 cpu_noarch[j].flags);
10176 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10177 {
10178 if (cpu_sub_arch_name)
10179 {
10180 char *name = cpu_sub_arch_name;
10181 cpu_sub_arch_name = concat (arch,
10182 (const char *) NULL);
10183 free (name);
10184 }
10185 else
10186 cpu_sub_arch_name = xstrdup (arch);
10187 cpu_arch_flags = flags;
10188 cpu_arch_isa_flags = flags;
10189 }
10190 break;
10191 }
10192
10193 if (j >= ARRAY_SIZE (cpu_noarch))
10194 j = ARRAY_SIZE (cpu_arch);
10195 }
10196
10197 if (j >= ARRAY_SIZE (cpu_arch))
10198 as_fatal (_("invalid -march= option: `%s'"), arg);
10199
10200 arch = next;
10201 }
10202 while (next != NULL);
10203 free (saved);
10204 break;
10205
10206 case OPTION_MTUNE:
10207 if (*arg == '.')
10208 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10209 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10210 {
10211 if (strcmp (arg, cpu_arch [j].name) == 0)
10212 {
10213 cpu_arch_tune_set = 1;
10214 cpu_arch_tune = cpu_arch [j].type;
10215 cpu_arch_tune_flags = cpu_arch[j].flags;
10216 break;
10217 }
10218 }
10219 if (j >= ARRAY_SIZE (cpu_arch))
10220 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10221 break;
10222
10223 case OPTION_MMNEMONIC:
10224 if (strcasecmp (arg, "att") == 0)
10225 intel_mnemonic = 0;
10226 else if (strcasecmp (arg, "intel") == 0)
10227 intel_mnemonic = 1;
10228 else
10229 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10230 break;
10231
10232 case OPTION_MSYNTAX:
10233 if (strcasecmp (arg, "att") == 0)
10234 intel_syntax = 0;
10235 else if (strcasecmp (arg, "intel") == 0)
10236 intel_syntax = 1;
10237 else
10238 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10239 break;
10240
10241 case OPTION_MINDEX_REG:
10242 allow_index_reg = 1;
10243 break;
10244
10245 case OPTION_MNAKED_REG:
10246 allow_naked_reg = 1;
10247 break;
10248
10249 case OPTION_MOLD_GCC:
10250 old_gcc = 1;
10251 break;
10252
10253 case OPTION_MSSE2AVX:
10254 sse2avx = 1;
10255 break;
10256
10257 case OPTION_MSSE_CHECK:
10258 if (strcasecmp (arg, "error") == 0)
10259 sse_check = check_error;
10260 else if (strcasecmp (arg, "warning") == 0)
10261 sse_check = check_warning;
10262 else if (strcasecmp (arg, "none") == 0)
10263 sse_check = check_none;
10264 else
10265 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10266 break;
10267
10268 case OPTION_MOPERAND_CHECK:
10269 if (strcasecmp (arg, "error") == 0)
10270 operand_check = check_error;
10271 else if (strcasecmp (arg, "warning") == 0)
10272 operand_check = check_warning;
10273 else if (strcasecmp (arg, "none") == 0)
10274 operand_check = check_none;
10275 else
10276 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10277 break;
10278
10279 case OPTION_MAVXSCALAR:
10280 if (strcasecmp (arg, "128") == 0)
10281 avxscalar = vex128;
10282 else if (strcasecmp (arg, "256") == 0)
10283 avxscalar = vex256;
10284 else
10285 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10286 break;
10287
10288 case OPTION_MADD_BND_PREFIX:
10289 add_bnd_prefix = 1;
10290 break;
10291
10292 case OPTION_MEVEXLIG:
10293 if (strcmp (arg, "128") == 0)
10294 evexlig = evexl128;
10295 else if (strcmp (arg, "256") == 0)
10296 evexlig = evexl256;
10297 else if (strcmp (arg, "512") == 0)
10298 evexlig = evexl512;
10299 else
10300 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10301 break;
10302
10303 case OPTION_MEVEXRCIG:
10304 if (strcmp (arg, "rne") == 0)
10305 evexrcig = rne;
10306 else if (strcmp (arg, "rd") == 0)
10307 evexrcig = rd;
10308 else if (strcmp (arg, "ru") == 0)
10309 evexrcig = ru;
10310 else if (strcmp (arg, "rz") == 0)
10311 evexrcig = rz;
10312 else
10313 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10314 break;
10315
10316 case OPTION_MEVEXWIG:
10317 if (strcmp (arg, "0") == 0)
10318 evexwig = evexw0;
10319 else if (strcmp (arg, "1") == 0)
10320 evexwig = evexw1;
10321 else
10322 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10323 break;
10324
10325 # if defined (TE_PE) || defined (TE_PEP)
10326 case OPTION_MBIG_OBJ:
10327 use_big_obj = 1;
10328 break;
10329 #endif
10330
10331 case OPTION_MOMIT_LOCK_PREFIX:
10332 if (strcasecmp (arg, "yes") == 0)
10333 omit_lock_prefix = 1;
10334 else if (strcasecmp (arg, "no") == 0)
10335 omit_lock_prefix = 0;
10336 else
10337 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10338 break;
10339
10340 case OPTION_MFENCE_AS_LOCK_ADD:
10341 if (strcasecmp (arg, "yes") == 0)
10342 avoid_fence = 1;
10343 else if (strcasecmp (arg, "no") == 0)
10344 avoid_fence = 0;
10345 else
10346 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10347 break;
10348
10349 case OPTION_MRELAX_RELOCATIONS:
10350 if (strcasecmp (arg, "yes") == 0)
10351 generate_relax_relocations = 1;
10352 else if (strcasecmp (arg, "no") == 0)
10353 generate_relax_relocations = 0;
10354 else
10355 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10356 break;
10357
10358 case OPTION_MAMD64:
10359 intel64 = 0;
10360 break;
10361
10362 case OPTION_MINTEL64:
10363 intel64 = 1;
10364 break;
10365
10366 default:
10367 return 0;
10368 }
10369 return 1;
10370 }
10371
10372 #define MESSAGE_TEMPLATE \
10373 " "
10374
10375 static char *
10376 output_message (FILE *stream, char *p, char *message, char *start,
10377 int *left_p, const char *name, int len)
10378 {
10379 int size = sizeof (MESSAGE_TEMPLATE);
10380 int left = *left_p;
10381
10382 /* Reserve 2 spaces for ", " or ",\0" */
10383 left -= len + 2;
10384
10385 /* Check if there is any room. */
10386 if (left >= 0)
10387 {
10388 if (p != start)
10389 {
10390 *p++ = ',';
10391 *p++ = ' ';
10392 }
10393 p = mempcpy (p, name, len);
10394 }
10395 else
10396 {
10397 /* Output the current message now and start a new one. */
10398 *p++ = ',';
10399 *p = '\0';
10400 fprintf (stream, "%s\n", message);
10401 p = start;
10402 left = size - (start - message) - len - 2;
10403
10404 gas_assert (left >= 0);
10405
10406 p = mempcpy (p, name, len);
10407 }
10408
10409 *left_p = left;
10410 return p;
10411 }
10412
10413 static void
10414 show_arch (FILE *stream, int ext, int check)
10415 {
10416 static char message[] = MESSAGE_TEMPLATE;
10417 char *start = message + 27;
10418 char *p;
10419 int size = sizeof (MESSAGE_TEMPLATE);
10420 int left;
10421 const char *name;
10422 int len;
10423 unsigned int j;
10424
10425 p = start;
10426 left = size - (start - message);
10427 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10428 {
10429 /* Should it be skipped? */
10430 if (cpu_arch [j].skip)
10431 continue;
10432
10433 name = cpu_arch [j].name;
10434 len = cpu_arch [j].len;
10435 if (*name == '.')
10436 {
10437 /* It is an extension. Skip if we aren't asked to show it. */
10438 if (ext)
10439 {
10440 name++;
10441 len--;
10442 }
10443 else
10444 continue;
10445 }
10446 else if (ext)
10447 {
10448 /* It is an processor. Skip if we show only extension. */
10449 continue;
10450 }
10451 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10452 {
10453 /* It is an impossible processor - skip. */
10454 continue;
10455 }
10456
10457 p = output_message (stream, p, message, start, &left, name, len);
10458 }
10459
10460 /* Display disabled extensions. */
10461 if (ext)
10462 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10463 {
10464 name = cpu_noarch [j].name;
10465 len = cpu_noarch [j].len;
10466 p = output_message (stream, p, message, start, &left, name,
10467 len);
10468 }
10469
10470 *p = '\0';
10471 fprintf (stream, "%s\n", message);
10472 }
10473
10474 void
10475 md_show_usage (FILE *stream)
10476 {
10477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10478 fprintf (stream, _("\
10479 -Q ignored\n\
10480 -V print assembler version number\n\
10481 -k ignored\n"));
10482 #endif
10483 fprintf (stream, _("\
10484 -n Do not optimize code alignment\n\
10485 -q quieten some warnings\n"));
10486 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10487 fprintf (stream, _("\
10488 -s ignored\n"));
10489 #endif
10490 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10491 || defined (TE_PE) || defined (TE_PEP))
10492 fprintf (stream, _("\
10493 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10494 #endif
10495 #ifdef SVR4_COMMENT_CHARS
10496 fprintf (stream, _("\
10497 --divide do not treat `/' as a comment character\n"));
10498 #else
10499 fprintf (stream, _("\
10500 --divide ignored\n"));
10501 #endif
10502 fprintf (stream, _("\
10503 -march=CPU[,+EXTENSION...]\n\
10504 generate code for CPU and EXTENSION, CPU is one of:\n"));
10505 show_arch (stream, 0, 1);
10506 fprintf (stream, _("\
10507 EXTENSION is combination of:\n"));
10508 show_arch (stream, 1, 0);
10509 fprintf (stream, _("\
10510 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10511 show_arch (stream, 0, 0);
10512 fprintf (stream, _("\
10513 -msse2avx encode SSE instructions with VEX prefix\n"));
10514 fprintf (stream, _("\
10515 -msse-check=[none|error|warning]\n\
10516 check SSE instructions\n"));
10517 fprintf (stream, _("\
10518 -moperand-check=[none|error|warning]\n\
10519 check operand combinations for validity\n"));
10520 fprintf (stream, _("\
10521 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10522 length\n"));
10523 fprintf (stream, _("\
10524 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10525 length\n"));
10526 fprintf (stream, _("\
10527 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10528 for EVEX.W bit ignored instructions\n"));
10529 fprintf (stream, _("\
10530 -mevexrcig=[rne|rd|ru|rz]\n\
10531 encode EVEX instructions with specific EVEX.RC value\n\
10532 for SAE-only ignored instructions\n"));
10533 fprintf (stream, _("\
10534 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10535 fprintf (stream, _("\
10536 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10537 fprintf (stream, _("\
10538 -mindex-reg support pseudo index registers\n"));
10539 fprintf (stream, _("\
10540 -mnaked-reg don't require `%%' prefix for registers\n"));
10541 fprintf (stream, _("\
10542 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10543 fprintf (stream, _("\
10544 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10545 fprintf (stream, _("\
10546 -mshared disable branch optimization for shared code\n"));
10547 # if defined (TE_PE) || defined (TE_PEP)
10548 fprintf (stream, _("\
10549 -mbig-obj generate big object files\n"));
10550 #endif
10551 fprintf (stream, _("\
10552 -momit-lock-prefix=[no|yes]\n\
10553 strip all lock prefixes\n"));
10554 fprintf (stream, _("\
10555 -mfence-as-lock-add=[no|yes]\n\
10556 encode lfence, mfence and sfence as\n\
10557 lock addl $0x0, (%%{re}sp)\n"));
10558 fprintf (stream, _("\
10559 -mrelax-relocations=[no|yes]\n\
10560 generate relax relocations\n"));
10561 fprintf (stream, _("\
10562 -mamd64 accept only AMD64 ISA\n"));
10563 fprintf (stream, _("\
10564 -mintel64 accept only Intel64 ISA\n"));
10565 }
10566
10567 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10568 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10569 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10570
10571 /* Pick the target format to use. */
10572
10573 const char *
10574 i386_target_format (void)
10575 {
10576 if (!strncmp (default_arch, "x86_64", 6))
10577 {
10578 update_code_flag (CODE_64BIT, 1);
10579 if (default_arch[6] == '\0')
10580 x86_elf_abi = X86_64_ABI;
10581 else
10582 x86_elf_abi = X86_64_X32_ABI;
10583 }
10584 else if (!strcmp (default_arch, "i386"))
10585 update_code_flag (CODE_32BIT, 1);
10586 else if (!strcmp (default_arch, "iamcu"))
10587 {
10588 update_code_flag (CODE_32BIT, 1);
10589 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10590 {
10591 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10592 cpu_arch_name = "iamcu";
10593 cpu_sub_arch_name = NULL;
10594 cpu_arch_flags = iamcu_flags;
10595 cpu_arch_isa = PROCESSOR_IAMCU;
10596 cpu_arch_isa_flags = iamcu_flags;
10597 if (!cpu_arch_tune_set)
10598 {
10599 cpu_arch_tune = cpu_arch_isa;
10600 cpu_arch_tune_flags = cpu_arch_isa_flags;
10601 }
10602 }
10603 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10604 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10605 cpu_arch_name);
10606 }
10607 else
10608 as_fatal (_("unknown architecture"));
10609
10610 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10611 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10612 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10613 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10614
10615 switch (OUTPUT_FLAVOR)
10616 {
10617 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10618 case bfd_target_aout_flavour:
10619 return AOUT_TARGET_FORMAT;
10620 #endif
10621 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10622 # if defined (TE_PE) || defined (TE_PEP)
10623 case bfd_target_coff_flavour:
10624 if (flag_code == CODE_64BIT)
10625 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10626 else
10627 return "pe-i386";
10628 # elif defined (TE_GO32)
10629 case bfd_target_coff_flavour:
10630 return "coff-go32";
10631 # else
10632 case bfd_target_coff_flavour:
10633 return "coff-i386";
10634 # endif
10635 #endif
10636 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10637 case bfd_target_elf_flavour:
10638 {
10639 const char *format;
10640
10641 switch (x86_elf_abi)
10642 {
10643 default:
10644 format = ELF_TARGET_FORMAT;
10645 break;
10646 case X86_64_ABI:
10647 use_rela_relocations = 1;
10648 object_64bit = 1;
10649 format = ELF_TARGET_FORMAT64;
10650 break;
10651 case X86_64_X32_ABI:
10652 use_rela_relocations = 1;
10653 object_64bit = 1;
10654 disallow_64bit_reloc = 1;
10655 format = ELF_TARGET_FORMAT32;
10656 break;
10657 }
10658 if (cpu_arch_isa == PROCESSOR_L1OM)
10659 {
10660 if (x86_elf_abi != X86_64_ABI)
10661 as_fatal (_("Intel L1OM is 64bit only"));
10662 return ELF_TARGET_L1OM_FORMAT;
10663 }
10664 else if (cpu_arch_isa == PROCESSOR_K1OM)
10665 {
10666 if (x86_elf_abi != X86_64_ABI)
10667 as_fatal (_("Intel K1OM is 64bit only"));
10668 return ELF_TARGET_K1OM_FORMAT;
10669 }
10670 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10671 {
10672 if (x86_elf_abi != I386_ABI)
10673 as_fatal (_("Intel MCU is 32bit only"));
10674 return ELF_TARGET_IAMCU_FORMAT;
10675 }
10676 else
10677 return format;
10678 }
10679 #endif
10680 #if defined (OBJ_MACH_O)
10681 case bfd_target_mach_o_flavour:
10682 if (flag_code == CODE_64BIT)
10683 {
10684 use_rela_relocations = 1;
10685 object_64bit = 1;
10686 return "mach-o-x86-64";
10687 }
10688 else
10689 return "mach-o-i386";
10690 #endif
10691 default:
10692 abort ();
10693 return NULL;
10694 }
10695 }
10696
10697 #endif /* OBJ_MAYBE_ more than one */
10698 \f
10699 symbolS *
10700 md_undefined_symbol (char *name)
10701 {
10702 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10703 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10704 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10705 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10706 {
10707 if (!GOT_symbol)
10708 {
10709 if (symbol_find (name))
10710 as_bad (_("GOT already in symbol table"));
10711 GOT_symbol = symbol_new (name, undefined_section,
10712 (valueT) 0, &zero_address_frag);
10713 };
10714 return GOT_symbol;
10715 }
10716 return 0;
10717 }
10718
10719 /* Round up a section size to the appropriate boundary. */
10720
10721 valueT
10722 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10723 {
10724 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10725 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10726 {
10727 /* For a.out, force the section size to be aligned. If we don't do
10728 this, BFD will align it for us, but it will not write out the
10729 final bytes of the section. This may be a bug in BFD, but it is
10730 easier to fix it here since that is how the other a.out targets
10731 work. */
10732 int align;
10733
10734 align = bfd_get_section_alignment (stdoutput, segment);
10735 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10736 }
10737 #endif
10738
10739 return size;
10740 }
10741
10742 /* On the i386, PC-relative offsets are relative to the start of the
10743 next instruction. That is, the address of the offset, plus its
10744 size, since the offset is always the last part of the insn. */
10745
10746 long
10747 md_pcrel_from (fixS *fixP)
10748 {
10749 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10750 }
10751
10752 #ifndef I386COFF
10753
10754 static void
10755 s_bss (int ignore ATTRIBUTE_UNUSED)
10756 {
10757 int temp;
10758
10759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10760 if (IS_ELF)
10761 obj_elf_section_change_hook ();
10762 #endif
10763 temp = get_absolute_expression ();
10764 subseg_set (bss_section, (subsegT) temp);
10765 demand_empty_rest_of_line ();
10766 }
10767
10768 #endif
10769
10770 void
10771 i386_validate_fix (fixS *fixp)
10772 {
10773 if (fixp->fx_subsy)
10774 {
10775 if (fixp->fx_subsy == GOT_symbol)
10776 {
10777 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10778 {
10779 if (!object_64bit)
10780 abort ();
10781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10782 if (fixp->fx_tcbit2)
10783 fixp->fx_r_type = (fixp->fx_tcbit
10784 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10785 : BFD_RELOC_X86_64_GOTPCRELX);
10786 else
10787 #endif
10788 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10789 }
10790 else
10791 {
10792 if (!object_64bit)
10793 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10794 else
10795 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10796 }
10797 fixp->fx_subsy = 0;
10798 }
10799 }
10800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10801 else if (!object_64bit)
10802 {
10803 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10804 && fixp->fx_tcbit2)
10805 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10806 }
10807 #endif
10808 }
10809
10810 arelent *
10811 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10812 {
10813 arelent *rel;
10814 bfd_reloc_code_real_type code;
10815
10816 switch (fixp->fx_r_type)
10817 {
10818 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10819 case BFD_RELOC_SIZE32:
10820 case BFD_RELOC_SIZE64:
10821 if (S_IS_DEFINED (fixp->fx_addsy)
10822 && !S_IS_EXTERNAL (fixp->fx_addsy))
10823 {
10824 /* Resolve size relocation against local symbol to size of
10825 the symbol plus addend. */
10826 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10827 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10828 && !fits_in_unsigned_long (value))
10829 as_bad_where (fixp->fx_file, fixp->fx_line,
10830 _("symbol size computation overflow"));
10831 fixp->fx_addsy = NULL;
10832 fixp->fx_subsy = NULL;
10833 md_apply_fix (fixp, (valueT *) &value, NULL);
10834 return NULL;
10835 }
10836 #endif
10837 /* Fall through. */
10838
10839 case BFD_RELOC_X86_64_PLT32:
10840 case BFD_RELOC_X86_64_GOT32:
10841 case BFD_RELOC_X86_64_GOTPCREL:
10842 case BFD_RELOC_X86_64_GOTPCRELX:
10843 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10844 case BFD_RELOC_386_PLT32:
10845 case BFD_RELOC_386_GOT32:
10846 case BFD_RELOC_386_GOT32X:
10847 case BFD_RELOC_386_GOTOFF:
10848 case BFD_RELOC_386_GOTPC:
10849 case BFD_RELOC_386_TLS_GD:
10850 case BFD_RELOC_386_TLS_LDM:
10851 case BFD_RELOC_386_TLS_LDO_32:
10852 case BFD_RELOC_386_TLS_IE_32:
10853 case BFD_RELOC_386_TLS_IE:
10854 case BFD_RELOC_386_TLS_GOTIE:
10855 case BFD_RELOC_386_TLS_LE_32:
10856 case BFD_RELOC_386_TLS_LE:
10857 case BFD_RELOC_386_TLS_GOTDESC:
10858 case BFD_RELOC_386_TLS_DESC_CALL:
10859 case BFD_RELOC_X86_64_TLSGD:
10860 case BFD_RELOC_X86_64_TLSLD:
10861 case BFD_RELOC_X86_64_DTPOFF32:
10862 case BFD_RELOC_X86_64_DTPOFF64:
10863 case BFD_RELOC_X86_64_GOTTPOFF:
10864 case BFD_RELOC_X86_64_TPOFF32:
10865 case BFD_RELOC_X86_64_TPOFF64:
10866 case BFD_RELOC_X86_64_GOTOFF64:
10867 case BFD_RELOC_X86_64_GOTPC32:
10868 case BFD_RELOC_X86_64_GOT64:
10869 case BFD_RELOC_X86_64_GOTPCREL64:
10870 case BFD_RELOC_X86_64_GOTPC64:
10871 case BFD_RELOC_X86_64_GOTPLT64:
10872 case BFD_RELOC_X86_64_PLTOFF64:
10873 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10874 case BFD_RELOC_X86_64_TLSDESC_CALL:
10875 case BFD_RELOC_RVA:
10876 case BFD_RELOC_VTABLE_ENTRY:
10877 case BFD_RELOC_VTABLE_INHERIT:
10878 #ifdef TE_PE
10879 case BFD_RELOC_32_SECREL:
10880 #endif
10881 code = fixp->fx_r_type;
10882 break;
10883 case BFD_RELOC_X86_64_32S:
10884 if (!fixp->fx_pcrel)
10885 {
10886 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10887 code = fixp->fx_r_type;
10888 break;
10889 }
10890 /* Fall through. */
10891 default:
10892 if (fixp->fx_pcrel)
10893 {
10894 switch (fixp->fx_size)
10895 {
10896 default:
10897 as_bad_where (fixp->fx_file, fixp->fx_line,
10898 _("can not do %d byte pc-relative relocation"),
10899 fixp->fx_size);
10900 code = BFD_RELOC_32_PCREL;
10901 break;
10902 case 1: code = BFD_RELOC_8_PCREL; break;
10903 case 2: code = BFD_RELOC_16_PCREL; break;
10904 case 4: code = BFD_RELOC_32_PCREL; break;
10905 #ifdef BFD64
10906 case 8: code = BFD_RELOC_64_PCREL; break;
10907 #endif
10908 }
10909 }
10910 else
10911 {
10912 switch (fixp->fx_size)
10913 {
10914 default:
10915 as_bad_where (fixp->fx_file, fixp->fx_line,
10916 _("can not do %d byte relocation"),
10917 fixp->fx_size);
10918 code = BFD_RELOC_32;
10919 break;
10920 case 1: code = BFD_RELOC_8; break;
10921 case 2: code = BFD_RELOC_16; break;
10922 case 4: code = BFD_RELOC_32; break;
10923 #ifdef BFD64
10924 case 8: code = BFD_RELOC_64; break;
10925 #endif
10926 }
10927 }
10928 break;
10929 }
10930
10931 if ((code == BFD_RELOC_32
10932 || code == BFD_RELOC_32_PCREL
10933 || code == BFD_RELOC_X86_64_32S)
10934 && GOT_symbol
10935 && fixp->fx_addsy == GOT_symbol)
10936 {
10937 if (!object_64bit)
10938 code = BFD_RELOC_386_GOTPC;
10939 else
10940 code = BFD_RELOC_X86_64_GOTPC32;
10941 }
10942 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10943 && GOT_symbol
10944 && fixp->fx_addsy == GOT_symbol)
10945 {
10946 code = BFD_RELOC_X86_64_GOTPC64;
10947 }
10948
10949 rel = XNEW (arelent);
10950 rel->sym_ptr_ptr = XNEW (asymbol *);
10951 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10952
10953 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10954
10955 if (!use_rela_relocations)
10956 {
10957 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10958 vtable entry to be used in the relocation's section offset. */
10959 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10960 rel->address = fixp->fx_offset;
10961 #if defined (OBJ_COFF) && defined (TE_PE)
10962 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10963 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10964 else
10965 #endif
10966 rel->addend = 0;
10967 }
10968 /* Use the rela in 64bit mode. */
10969 else
10970 {
10971 if (disallow_64bit_reloc)
10972 switch (code)
10973 {
10974 case BFD_RELOC_X86_64_DTPOFF64:
10975 case BFD_RELOC_X86_64_TPOFF64:
10976 case BFD_RELOC_64_PCREL:
10977 case BFD_RELOC_X86_64_GOTOFF64:
10978 case BFD_RELOC_X86_64_GOT64:
10979 case BFD_RELOC_X86_64_GOTPCREL64:
10980 case BFD_RELOC_X86_64_GOTPC64:
10981 case BFD_RELOC_X86_64_GOTPLT64:
10982 case BFD_RELOC_X86_64_PLTOFF64:
10983 as_bad_where (fixp->fx_file, fixp->fx_line,
10984 _("cannot represent relocation type %s in x32 mode"),
10985 bfd_get_reloc_code_name (code));
10986 break;
10987 default:
10988 break;
10989 }
10990
10991 if (!fixp->fx_pcrel)
10992 rel->addend = fixp->fx_offset;
10993 else
10994 switch (code)
10995 {
10996 case BFD_RELOC_X86_64_PLT32:
10997 case BFD_RELOC_X86_64_GOT32:
10998 case BFD_RELOC_X86_64_GOTPCREL:
10999 case BFD_RELOC_X86_64_GOTPCRELX:
11000 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11001 case BFD_RELOC_X86_64_TLSGD:
11002 case BFD_RELOC_X86_64_TLSLD:
11003 case BFD_RELOC_X86_64_GOTTPOFF:
11004 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11005 case BFD_RELOC_X86_64_TLSDESC_CALL:
11006 rel->addend = fixp->fx_offset - fixp->fx_size;
11007 break;
11008 default:
11009 rel->addend = (section->vma
11010 - fixp->fx_size
11011 + fixp->fx_addnumber
11012 + md_pcrel_from (fixp));
11013 break;
11014 }
11015 }
11016
11017 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11018 if (rel->howto == NULL)
11019 {
11020 as_bad_where (fixp->fx_file, fixp->fx_line,
11021 _("cannot represent relocation type %s"),
11022 bfd_get_reloc_code_name (code));
11023 /* Set howto to a garbage value so that we can keep going. */
11024 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11025 gas_assert (rel->howto != NULL);
11026 }
11027
11028 return rel;
11029 }
11030
11031 #include "tc-i386-intel.c"
11032
11033 void
11034 tc_x86_parse_to_dw2regnum (expressionS *exp)
11035 {
11036 int saved_naked_reg;
11037 char saved_register_dot;
11038
11039 saved_naked_reg = allow_naked_reg;
11040 allow_naked_reg = 1;
11041 saved_register_dot = register_chars['.'];
11042 register_chars['.'] = '.';
11043 allow_pseudo_reg = 1;
11044 expression_and_evaluate (exp);
11045 allow_pseudo_reg = 0;
11046 register_chars['.'] = saved_register_dot;
11047 allow_naked_reg = saved_naked_reg;
11048
11049 if (exp->X_op == O_register && exp->X_add_number >= 0)
11050 {
11051 if ((addressT) exp->X_add_number < i386_regtab_size)
11052 {
11053 exp->X_op = O_constant;
11054 exp->X_add_number = i386_regtab[exp->X_add_number]
11055 .dw2_regnum[flag_code >> 1];
11056 }
11057 else
11058 exp->X_op = O_illegal;
11059 }
11060 }
11061
11062 void
11063 tc_x86_frame_initial_instructions (void)
11064 {
11065 static unsigned int sp_regno[2];
11066
11067 if (!sp_regno[flag_code >> 1])
11068 {
11069 char *saved_input = input_line_pointer;
11070 char sp[][4] = {"esp", "rsp"};
11071 expressionS exp;
11072
11073 input_line_pointer = sp[flag_code >> 1];
11074 tc_x86_parse_to_dw2regnum (&exp);
11075 gas_assert (exp.X_op == O_constant);
11076 sp_regno[flag_code >> 1] = exp.X_add_number;
11077 input_line_pointer = saved_input;
11078 }
11079
11080 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11081 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11082 }
11083
11084 int
11085 x86_dwarf2_addr_size (void)
11086 {
11087 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11088 if (x86_elf_abi == X86_64_X32_ABI)
11089 return 4;
11090 #endif
11091 return bfd_arch_bits_per_address (stdoutput) / 8;
11092 }
11093
11094 int
11095 i386_elf_section_type (const char *str, size_t len)
11096 {
11097 if (flag_code == CODE_64BIT
11098 && len == sizeof ("unwind") - 1
11099 && strncmp (str, "unwind", 6) == 0)
11100 return SHT_X86_64_UNWIND;
11101
11102 return -1;
11103 }
11104
11105 #ifdef TE_SOLARIS
11106 void
11107 i386_solaris_fix_up_eh_frame (segT sec)
11108 {
11109 if (flag_code == CODE_64BIT)
11110 elf_section_type (sec) = SHT_X86_64_UNWIND;
11111 }
11112 #endif
11113
11114 #ifdef TE_PE
11115 void
11116 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11117 {
11118 expressionS exp;
11119
11120 exp.X_op = O_secrel;
11121 exp.X_add_symbol = symbol;
11122 exp.X_add_number = 0;
11123 emit_expr (&exp, size);
11124 }
11125 #endif
11126
11127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11128 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11129
11130 bfd_vma
11131 x86_64_section_letter (int letter, const char **ptr_msg)
11132 {
11133 if (flag_code == CODE_64BIT)
11134 {
11135 if (letter == 'l')
11136 return SHF_X86_64_LARGE;
11137
11138 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11139 }
11140 else
11141 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11142 return -1;
11143 }
11144
11145 bfd_vma
11146 x86_64_section_word (char *str, size_t len)
11147 {
11148 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11149 return SHF_X86_64_LARGE;
11150
11151 return -1;
11152 }
11153
11154 static void
11155 handle_large_common (int small ATTRIBUTE_UNUSED)
11156 {
11157 if (flag_code != CODE_64BIT)
11158 {
11159 s_comm_internal (0, elf_common_parse);
11160 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11161 }
11162 else
11163 {
11164 static segT lbss_section;
11165 asection *saved_com_section_ptr = elf_com_section_ptr;
11166 asection *saved_bss_section = bss_section;
11167
11168 if (lbss_section == NULL)
11169 {
11170 flagword applicable;
11171 segT seg = now_seg;
11172 subsegT subseg = now_subseg;
11173
11174 /* The .lbss section is for local .largecomm symbols. */
11175 lbss_section = subseg_new (".lbss", 0);
11176 applicable = bfd_applicable_section_flags (stdoutput);
11177 bfd_set_section_flags (stdoutput, lbss_section,
11178 applicable & SEC_ALLOC);
11179 seg_info (lbss_section)->bss = 1;
11180
11181 subseg_set (seg, subseg);
11182 }
11183
11184 elf_com_section_ptr = &_bfd_elf_large_com_section;
11185 bss_section = lbss_section;
11186
11187 s_comm_internal (0, elf_common_parse);
11188
11189 elf_com_section_ptr = saved_com_section_ptr;
11190 bss_section = saved_bss_section;
11191 }
11192 }
11193 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */