1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1018 CPU_ZNVER3_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1020 CPU_BTVER1_FLAGS
, 0 },
1021 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1022 CPU_BTVER2_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1024 CPU_8087_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1032 CPU_CMOV_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1034 CPU_FXSR_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE2_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4A_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1046 CPU_SSSE3_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_1_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1052 CPU_SSE4_2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1055 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX2_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512F_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512CD_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512ER_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512PF_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512DQ_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512BW_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1070 CPU_AVX512VL_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1074 CPU_VMFUNC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEOPT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVEC_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1084 CPU_XSAVES_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1090 CPU_PCLMUL_FLAGS
, 1 },
1091 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1092 CPU_FSGSBASE_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1094 CPU_RDRND_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1096 CPU_F16C_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1098 CPU_BMI2_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1102 CPU_FMA4_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1107 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1108 CPU_MOVBE_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1110 CPU_CX16_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_LZCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1116 CPU_POPCNT_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1121 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1122 CPU_INVPCID_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1124 CPU_CLFLUSH_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1127 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1128 CPU_SYSCALL_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1130 CPU_RDTSCP_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOW_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1134 CPU_3DNOWA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1136 CPU_PADLOCK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 1 },
1139 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1140 CPU_SVME_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1142 CPU_SSE4A_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1152 CPU_RDSEED_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1154 CPU_PRFCHW_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1156 CPU_SMAP_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1162 CPU_CLFLUSHOPT_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1164 CPU_PREFETCHWT1_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1167 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1168 CPU_CLWB_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512IFMA_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512VBMI_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VBMI2_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_VNNI_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_BITALG_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1186 CPU_AVX_VNNI_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1188 CPU_CLZERO_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1190 CPU_MWAITX_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1192 CPU_OSPKE_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1194 CPU_RDPID_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1196 CPU_PTWRITE_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1199 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1200 CPU_SHSTK_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1202 CPU_GFNI_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1204 CPU_VAES_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1206 CPU_VPCLMULQDQ_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1208 CPU_WBNOINVD_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1210 CPU_PCONFIG_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1212 CPU_WAITPKG_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1214 CPU_CLDEMOTE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_INT8_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1218 CPU_AMX_BF16_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1220 CPU_AMX_TILE_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1222 CPU_MOVDIRI_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1224 CPU_MOVDIR64B_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1226 CPU_AVX512_BF16_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1228 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1231 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1232 CPU_ENQCMD_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1234 CPU_SERIALIZE_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1236 CPU_RDPRU_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1238 CPU_MCOMMIT_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1240 CPU_SEV_ES_FLAGS
, 0 },
1241 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1242 CPU_TSXLDTRK_FLAGS
, 0 },
1243 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1245 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1246 CPU_WIDEKL_FLAGS
, 0 },
1247 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1248 CPU_UINTR_FLAGS
, 0 },
1249 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1250 CPU_HRESET_FLAGS
, 0 },
1253 static const noarch_entry cpu_noarch
[] =
1255 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1256 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1257 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1258 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1259 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1260 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1261 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1262 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1263 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1264 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1266 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1269 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1288 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1289 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1290 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1291 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1292 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1293 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1294 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1295 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1296 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1297 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1298 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1299 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1300 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1301 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1302 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1303 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1304 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1305 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1309 /* Like s_lcomm_internal in gas/read.c but the alignment string
1310 is allowed to be optional. */
1313 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1320 && *input_line_pointer
== ',')
1322 align
= parse_align (needs_align
- 1);
1324 if (align
== (addressT
) -1)
1339 bss_alloc (symbolP
, size
, align
);
1344 pe_lcomm (int needs_align
)
1346 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1350 const pseudo_typeS md_pseudo_table
[] =
1352 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1353 {"align", s_align_bytes
, 0},
1355 {"align", s_align_ptwo
, 0},
1357 {"arch", set_cpu_arch
, 0},
1361 {"lcomm", pe_lcomm
, 1},
1363 {"ffloat", float_cons
, 'f'},
1364 {"dfloat", float_cons
, 'd'},
1365 {"tfloat", float_cons
, 'x'},
1367 {"slong", signed_cons
, 4},
1368 {"noopt", s_ignore
, 0},
1369 {"optim", s_ignore
, 0},
1370 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1371 {"code16", set_code_flag
, CODE_16BIT
},
1372 {"code32", set_code_flag
, CODE_32BIT
},
1374 {"code64", set_code_flag
, CODE_64BIT
},
1376 {"intel_syntax", set_intel_syntax
, 1},
1377 {"att_syntax", set_intel_syntax
, 0},
1378 {"intel_mnemonic", set_intel_mnemonic
, 1},
1379 {"att_mnemonic", set_intel_mnemonic
, 0},
1380 {"allow_index_reg", set_allow_index_reg
, 1},
1381 {"disallow_index_reg", set_allow_index_reg
, 0},
1382 {"sse_check", set_check
, 0},
1383 {"operand_check", set_check
, 1},
1384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1385 {"largecomm", handle_large_common
, 0},
1387 {"file", dwarf2_directive_file
, 0},
1388 {"loc", dwarf2_directive_loc
, 0},
1389 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1392 {"secrel32", pe_directive_secrel
, 0},
1397 /* For interface with expression (). */
1398 extern char *input_line_pointer
;
1400 /* Hash table for instruction mnemonic lookup. */
1401 static htab_t op_hash
;
1403 /* Hash table for register lookup. */
1404 static htab_t reg_hash
;
1406 /* Various efficient no-op patterns for aligning code labels.
1407 Note: Don't try to assemble the instructions in the comments.
1408 0L and 0w are not legal. */
1409 static const unsigned char f32_1
[] =
1411 static const unsigned char f32_2
[] =
1412 {0x66,0x90}; /* xchg %ax,%ax */
1413 static const unsigned char f32_3
[] =
1414 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1415 static const unsigned char f32_4
[] =
1416 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1417 static const unsigned char f32_6
[] =
1418 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1419 static const unsigned char f32_7
[] =
1420 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1421 static const unsigned char f16_3
[] =
1422 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1423 static const unsigned char f16_4
[] =
1424 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1425 static const unsigned char jump_disp8
[] =
1426 {0xeb}; /* jmp disp8 */
1427 static const unsigned char jump32_disp32
[] =
1428 {0xe9}; /* jmp disp32 */
1429 static const unsigned char jump16_disp32
[] =
1430 {0x66,0xe9}; /* jmp disp32 */
1431 /* 32-bit NOPs patterns. */
1432 static const unsigned char *const f32_patt
[] = {
1433 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1435 /* 16-bit NOPs patterns. */
1436 static const unsigned char *const f16_patt
[] = {
1437 f32_1
, f32_2
, f16_3
, f16_4
1439 /* nopl (%[re]ax) */
1440 static const unsigned char alt_3
[] =
1442 /* nopl 0(%[re]ax) */
1443 static const unsigned char alt_4
[] =
1444 {0x0f,0x1f,0x40,0x00};
1445 /* nopl 0(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_5
[] =
1447 {0x0f,0x1f,0x44,0x00,0x00};
1448 /* nopw 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_6
[] =
1450 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopl 0L(%[re]ax) */
1452 static const unsigned char alt_7
[] =
1453 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1454 /* nopl 0L(%[re]ax,%[re]ax,1) */
1455 static const unsigned char alt_8
[] =
1456 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* nopw 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_9
[] =
1459 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_10
[] =
1462 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* data16 nopw %cs:0L(%eax,%eax,1) */
1464 static const unsigned char alt_11
[] =
1465 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* 32-bit and 64-bit NOPs patterns. */
1467 static const unsigned char *const alt_patt
[] = {
1468 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1469 alt_9
, alt_10
, alt_11
1472 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1473 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1476 i386_output_nops (char *where
, const unsigned char *const *patt
,
1477 int count
, int max_single_nop_size
)
1480 /* Place the longer NOP first. */
1483 const unsigned char *nops
;
1485 if (max_single_nop_size
< 1)
1487 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1488 max_single_nop_size
);
1492 nops
= patt
[max_single_nop_size
- 1];
1494 /* Use the smaller one if the requsted one isn't available. */
1497 max_single_nop_size
--;
1498 nops
= patt
[max_single_nop_size
- 1];
1501 last
= count
% max_single_nop_size
;
1504 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1505 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1509 nops
= patt
[last
- 1];
1512 /* Use the smaller one plus one-byte NOP if the needed one
1515 nops
= patt
[last
- 1];
1516 memcpy (where
+ offset
, nops
, last
);
1517 where
[offset
+ last
] = *patt
[0];
1520 memcpy (where
+ offset
, nops
, last
);
1525 fits_in_imm7 (offsetT num
)
1527 return (num
& 0x7f) == num
;
1531 fits_in_imm31 (offsetT num
)
1533 return (num
& 0x7fffffff) == num
;
1536 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1537 single NOP instruction LIMIT. */
1540 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1542 const unsigned char *const *patt
= NULL
;
1543 int max_single_nop_size
;
1544 /* Maximum number of NOPs before switching to jump over NOPs. */
1545 int max_number_of_nops
;
1547 switch (fragP
->fr_type
)
1552 case rs_machine_dependent
:
1553 /* Allow NOP padding for jumps and calls. */
1554 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1555 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1562 /* We need to decide which NOP sequence to use for 32bit and
1563 64bit. When -mtune= is used:
1565 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1566 PROCESSOR_GENERIC32, f32_patt will be used.
1567 2. For the rest, alt_patt will be used.
1569 When -mtune= isn't used, alt_patt will be used if
1570 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1573 When -march= or .arch is used, we can't use anything beyond
1574 cpu_arch_isa_flags. */
1576 if (flag_code
== CODE_16BIT
)
1579 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1580 /* Limit number of NOPs to 2 in 16-bit mode. */
1581 max_number_of_nops
= 2;
1585 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1587 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1588 switch (cpu_arch_tune
)
1590 case PROCESSOR_UNKNOWN
:
1591 /* We use cpu_arch_isa_flags to check if we SHOULD
1592 optimize with nops. */
1593 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1598 case PROCESSOR_PENTIUM4
:
1599 case PROCESSOR_NOCONA
:
1600 case PROCESSOR_CORE
:
1601 case PROCESSOR_CORE2
:
1602 case PROCESSOR_COREI7
:
1603 case PROCESSOR_L1OM
:
1604 case PROCESSOR_K1OM
:
1605 case PROCESSOR_GENERIC64
:
1607 case PROCESSOR_ATHLON
:
1609 case PROCESSOR_AMDFAM10
:
1611 case PROCESSOR_ZNVER
:
1615 case PROCESSOR_I386
:
1616 case PROCESSOR_I486
:
1617 case PROCESSOR_PENTIUM
:
1618 case PROCESSOR_PENTIUMPRO
:
1619 case PROCESSOR_IAMCU
:
1620 case PROCESSOR_GENERIC32
:
1627 switch (fragP
->tc_frag_data
.tune
)
1629 case PROCESSOR_UNKNOWN
:
1630 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1631 PROCESSOR_UNKNOWN. */
1635 case PROCESSOR_I386
:
1636 case PROCESSOR_I486
:
1637 case PROCESSOR_PENTIUM
:
1638 case PROCESSOR_IAMCU
:
1640 case PROCESSOR_ATHLON
:
1642 case PROCESSOR_AMDFAM10
:
1644 case PROCESSOR_ZNVER
:
1646 case PROCESSOR_GENERIC32
:
1647 /* We use cpu_arch_isa_flags to check if we CAN optimize
1649 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1654 case PROCESSOR_PENTIUMPRO
:
1655 case PROCESSOR_PENTIUM4
:
1656 case PROCESSOR_NOCONA
:
1657 case PROCESSOR_CORE
:
1658 case PROCESSOR_CORE2
:
1659 case PROCESSOR_COREI7
:
1660 case PROCESSOR_L1OM
:
1661 case PROCESSOR_K1OM
:
1662 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1667 case PROCESSOR_GENERIC64
:
1673 if (patt
== f32_patt
)
1675 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1676 /* Limit number of NOPs to 2 for older processors. */
1677 max_number_of_nops
= 2;
1681 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1682 /* Limit number of NOPs to 7 for newer processors. */
1683 max_number_of_nops
= 7;
1688 limit
= max_single_nop_size
;
1690 if (fragP
->fr_type
== rs_fill_nop
)
1692 /* Output NOPs for .nop directive. */
1693 if (limit
> max_single_nop_size
)
1695 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1696 _("invalid single nop size: %d "
1697 "(expect within [0, %d])"),
1698 limit
, max_single_nop_size
);
1702 else if (fragP
->fr_type
!= rs_machine_dependent
)
1703 fragP
->fr_var
= count
;
1705 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1707 /* Generate jump over NOPs. */
1708 offsetT disp
= count
- 2;
1709 if (fits_in_imm7 (disp
))
1711 /* Use "jmp disp8" if possible. */
1713 where
[0] = jump_disp8
[0];
1719 unsigned int size_of_jump
;
1721 if (flag_code
== CODE_16BIT
)
1723 where
[0] = jump16_disp32
[0];
1724 where
[1] = jump16_disp32
[1];
1729 where
[0] = jump32_disp32
[0];
1733 count
-= size_of_jump
+ 4;
1734 if (!fits_in_imm31 (count
))
1736 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1737 _("jump over nop padding out of range"));
1741 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1742 where
+= size_of_jump
+ 4;
1746 /* Generate multiple NOPs. */
1747 i386_output_nops (where
, patt
, count
, limit
);
1751 operand_type_all_zero (const union i386_operand_type
*x
)
1753 switch (ARRAY_SIZE(x
->array
))
1764 return !x
->array
[0];
1771 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1773 switch (ARRAY_SIZE(x
->array
))
1789 x
->bitfield
.class = ClassNone
;
1790 x
->bitfield
.instance
= InstanceNone
;
1794 operand_type_equal (const union i386_operand_type
*x
,
1795 const union i386_operand_type
*y
)
1797 switch (ARRAY_SIZE(x
->array
))
1800 if (x
->array
[2] != y
->array
[2])
1804 if (x
->array
[1] != y
->array
[1])
1808 return x
->array
[0] == y
->array
[0];
1816 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1818 switch (ARRAY_SIZE(x
->array
))
1833 return !x
->array
[0];
1840 cpu_flags_equal (const union i386_cpu_flags
*x
,
1841 const union i386_cpu_flags
*y
)
1843 switch (ARRAY_SIZE(x
->array
))
1846 if (x
->array
[3] != y
->array
[3])
1850 if (x
->array
[2] != y
->array
[2])
1854 if (x
->array
[1] != y
->array
[1])
1858 return x
->array
[0] == y
->array
[0];
1866 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1868 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1869 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1872 static INLINE i386_cpu_flags
1873 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1875 switch (ARRAY_SIZE (x
.array
))
1878 x
.array
[3] &= y
.array
[3];
1881 x
.array
[2] &= y
.array
[2];
1884 x
.array
[1] &= y
.array
[1];
1887 x
.array
[0] &= y
.array
[0];
1895 static INLINE i386_cpu_flags
1896 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1898 switch (ARRAY_SIZE (x
.array
))
1901 x
.array
[3] |= y
.array
[3];
1904 x
.array
[2] |= y
.array
[2];
1907 x
.array
[1] |= y
.array
[1];
1910 x
.array
[0] |= y
.array
[0];
1918 static INLINE i386_cpu_flags
1919 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1921 switch (ARRAY_SIZE (x
.array
))
1924 x
.array
[3] &= ~y
.array
[3];
1927 x
.array
[2] &= ~y
.array
[2];
1930 x
.array
[1] &= ~y
.array
[1];
1933 x
.array
[0] &= ~y
.array
[0];
1941 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1943 #define CPU_FLAGS_ARCH_MATCH 0x1
1944 #define CPU_FLAGS_64BIT_MATCH 0x2
1946 #define CPU_FLAGS_PERFECT_MATCH \
1947 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1949 /* Return CPU flags match bits. */
1952 cpu_flags_match (const insn_template
*t
)
1954 i386_cpu_flags x
= t
->cpu_flags
;
1955 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1957 x
.bitfield
.cpu64
= 0;
1958 x
.bitfield
.cpuno64
= 0;
1960 if (cpu_flags_all_zero (&x
))
1962 /* This instruction is available on all archs. */
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 /* This instruction is available only on some archs. */
1968 i386_cpu_flags cpu
= cpu_arch_flags
;
1970 /* AVX512VL is no standalone feature - match it and then strip it. */
1971 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1973 x
.bitfield
.cpuavx512vl
= 0;
1975 cpu
= cpu_flags_and (x
, cpu
);
1976 if (!cpu_flags_all_zero (&cpu
))
1978 if (x
.bitfield
.cpuavx
)
1980 /* We need to check a few extra flags with AVX. */
1981 if (cpu
.bitfield
.cpuavx
1982 && (!t
->opcode_modifier
.sse2avx
1983 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1984 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1985 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1986 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1989 else if (x
.bitfield
.cpuavx512f
)
1991 /* We need to check a few extra flags with AVX512F. */
1992 if (cpu
.bitfield
.cpuavx512f
1993 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1994 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1995 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1996 match
|= CPU_FLAGS_ARCH_MATCH
;
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2005 static INLINE i386_operand_type
2006 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2008 if (x
.bitfield
.class != y
.bitfield
.class)
2009 x
.bitfield
.class = ClassNone
;
2010 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2011 x
.bitfield
.instance
= InstanceNone
;
2013 switch (ARRAY_SIZE (x
.array
))
2016 x
.array
[2] &= y
.array
[2];
2019 x
.array
[1] &= y
.array
[1];
2022 x
.array
[0] &= y
.array
[0];
2030 static INLINE i386_operand_type
2031 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2033 gas_assert (y
.bitfield
.class == ClassNone
);
2034 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2036 switch (ARRAY_SIZE (x
.array
))
2039 x
.array
[2] &= ~y
.array
[2];
2042 x
.array
[1] &= ~y
.array
[1];
2045 x
.array
[0] &= ~y
.array
[0];
2053 static INLINE i386_operand_type
2054 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2056 gas_assert (x
.bitfield
.class == ClassNone
||
2057 y
.bitfield
.class == ClassNone
||
2058 x
.bitfield
.class == y
.bitfield
.class);
2059 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2060 y
.bitfield
.instance
== InstanceNone
||
2061 x
.bitfield
.instance
== y
.bitfield
.instance
);
2063 switch (ARRAY_SIZE (x
.array
))
2066 x
.array
[2] |= y
.array
[2];
2069 x
.array
[1] |= y
.array
[1];
2072 x
.array
[0] |= y
.array
[0];
2080 static INLINE i386_operand_type
2081 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2083 gas_assert (y
.bitfield
.class == ClassNone
);
2084 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2086 switch (ARRAY_SIZE (x
.array
))
2089 x
.array
[2] ^= y
.array
[2];
2092 x
.array
[1] ^= y
.array
[1];
2095 x
.array
[0] ^= y
.array
[0];
2103 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2104 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2105 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2106 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2107 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2108 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2109 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2110 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2111 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2112 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2113 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2114 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2115 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2116 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2117 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2118 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2119 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2130 operand_type_check (i386_operand_type t
, enum operand_type c
)
2135 return t
.bitfield
.class == Reg
;
2138 return (t
.bitfield
.imm8
2142 || t
.bitfield
.imm32s
2143 || t
.bitfield
.imm64
);
2146 return (t
.bitfield
.disp8
2147 || t
.bitfield
.disp16
2148 || t
.bitfield
.disp32
2149 || t
.bitfield
.disp32s
2150 || t
.bitfield
.disp64
);
2153 return (t
.bitfield
.disp8
2154 || t
.bitfield
.disp16
2155 || t
.bitfield
.disp32
2156 || t
.bitfield
.disp32s
2157 || t
.bitfield
.disp64
2158 || t
.bitfield
.baseindex
);
2167 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2168 between operand GIVEN and opeand WANTED for instruction template T. */
2171 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2174 return !((i
.types
[given
].bitfield
.byte
2175 && !t
->operand_types
[wanted
].bitfield
.byte
)
2176 || (i
.types
[given
].bitfield
.word
2177 && !t
->operand_types
[wanted
].bitfield
.word
)
2178 || (i
.types
[given
].bitfield
.dword
2179 && !t
->operand_types
[wanted
].bitfield
.dword
)
2180 || (i
.types
[given
].bitfield
.qword
2181 && !t
->operand_types
[wanted
].bitfield
.qword
)
2182 || (i
.types
[given
].bitfield
.tbyte
2183 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2186 /* Return 1 if there is no conflict in SIMD register between operand
2187 GIVEN and opeand WANTED for instruction template T. */
2190 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2193 return !((i
.types
[given
].bitfield
.xmmword
2194 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2195 || (i
.types
[given
].bitfield
.ymmword
2196 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2197 || (i
.types
[given
].bitfield
.zmmword
2198 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2199 || (i
.types
[given
].bitfield
.tmmword
2200 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2203 /* Return 1 if there is no conflict in any size between operand GIVEN
2204 and opeand WANTED for instruction template T. */
2207 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2210 return (match_operand_size (t
, wanted
, given
)
2211 && !((i
.types
[given
].bitfield
.unspecified
2213 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2214 || (i
.types
[given
].bitfield
.fword
2215 && !t
->operand_types
[wanted
].bitfield
.fword
)
2216 /* For scalar opcode templates to allow register and memory
2217 operands at the same time, some special casing is needed
2218 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2219 down-conversion vpmov*. */
2220 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2221 && t
->operand_types
[wanted
].bitfield
.byte
2222 + t
->operand_types
[wanted
].bitfield
.word
2223 + t
->operand_types
[wanted
].bitfield
.dword
2224 + t
->operand_types
[wanted
].bitfield
.qword
2225 > !!t
->opcode_modifier
.broadcast
)
2226 ? (i
.types
[given
].bitfield
.xmmword
2227 || i
.types
[given
].bitfield
.ymmword
2228 || i
.types
[given
].bitfield
.zmmword
)
2229 : !match_simd_size(t
, wanted
, given
))));
2232 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2233 operands for instruction template T, and it has MATCH_REVERSE set if there
2234 is no size conflict on any operands for the template with operands reversed
2235 (and the template allows for reversing in the first place). */
2237 #define MATCH_STRAIGHT 1
2238 #define MATCH_REVERSE 2
2240 static INLINE
unsigned int
2241 operand_size_match (const insn_template
*t
)
2243 unsigned int j
, match
= MATCH_STRAIGHT
;
2245 /* Don't check non-absolute jump instructions. */
2246 if (t
->opcode_modifier
.jump
2247 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2250 /* Check memory and accumulator operand size. */
2251 for (j
= 0; j
< i
.operands
; j
++)
2253 if (i
.types
[j
].bitfield
.class != Reg
2254 && i
.types
[j
].bitfield
.class != RegSIMD
2255 && t
->opcode_modifier
.anysize
)
2258 if (t
->operand_types
[j
].bitfield
.class == Reg
2259 && !match_operand_size (t
, j
, j
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, j
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2279 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2286 if (!t
->opcode_modifier
.d
)
2290 i
.error
= operand_size_mismatch
;
2294 /* Check reverse. */
2295 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2297 for (j
= 0; j
< i
.operands
; j
++)
2299 unsigned int given
= i
.operands
- j
- 1;
2301 if (t
->operand_types
[j
].bitfield
.class == Reg
2302 && !match_operand_size (t
, j
, given
))
2305 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2306 && !match_simd_size (t
, j
, given
))
2309 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2310 && (!match_operand_size (t
, j
, given
)
2311 || !match_simd_size (t
, j
, given
)))
2314 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2318 return match
| MATCH_REVERSE
;
2322 operand_type_match (i386_operand_type overlap
,
2323 i386_operand_type given
)
2325 i386_operand_type temp
= overlap
;
2327 temp
.bitfield
.unspecified
= 0;
2328 temp
.bitfield
.byte
= 0;
2329 temp
.bitfield
.word
= 0;
2330 temp
.bitfield
.dword
= 0;
2331 temp
.bitfield
.fword
= 0;
2332 temp
.bitfield
.qword
= 0;
2333 temp
.bitfield
.tbyte
= 0;
2334 temp
.bitfield
.xmmword
= 0;
2335 temp
.bitfield
.ymmword
= 0;
2336 temp
.bitfield
.zmmword
= 0;
2337 temp
.bitfield
.tmmword
= 0;
2338 if (operand_type_all_zero (&temp
))
2341 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2345 i
.error
= operand_type_mismatch
;
2349 /* If given types g0 and g1 are registers they must be of the same type
2350 unless the expected operand type register overlap is null.
2351 Some Intel syntax memory operand size checking also happens here. */
2354 operand_type_register_match (i386_operand_type g0
,
2355 i386_operand_type t0
,
2356 i386_operand_type g1
,
2357 i386_operand_type t1
)
2359 if (g0
.bitfield
.class != Reg
2360 && g0
.bitfield
.class != RegSIMD
2361 && (!operand_type_check (g0
, anymem
)
2362 || g0
.bitfield
.unspecified
2363 || (t0
.bitfield
.class != Reg
2364 && t0
.bitfield
.class != RegSIMD
)))
2367 if (g1
.bitfield
.class != Reg
2368 && g1
.bitfield
.class != RegSIMD
2369 && (!operand_type_check (g1
, anymem
)
2370 || g1
.bitfield
.unspecified
2371 || (t1
.bitfield
.class != Reg
2372 && t1
.bitfield
.class != RegSIMD
)))
2375 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2376 && g0
.bitfield
.word
== g1
.bitfield
.word
2377 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2378 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2379 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2380 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2381 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2384 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2385 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2386 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2387 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2388 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2389 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2390 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2393 i
.error
= register_type_mismatch
;
2398 static INLINE
unsigned int
2399 register_number (const reg_entry
*r
)
2401 unsigned int nr
= r
->reg_num
;
2403 if (r
->reg_flags
& RegRex
)
2406 if (r
->reg_flags
& RegVRex
)
2412 static INLINE
unsigned int
2413 mode_from_disp_size (i386_operand_type t
)
2415 if (t
.bitfield
.disp8
)
2417 else if (t
.bitfield
.disp16
2418 || t
.bitfield
.disp32
2419 || t
.bitfield
.disp32s
)
2426 fits_in_signed_byte (addressT num
)
2428 return num
+ 0x80 <= 0xff;
2432 fits_in_unsigned_byte (addressT num
)
2438 fits_in_unsigned_word (addressT num
)
2440 return num
<= 0xffff;
2444 fits_in_signed_word (addressT num
)
2446 return num
+ 0x8000 <= 0xffff;
2450 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2455 return num
+ 0x80000000 <= 0xffffffff;
2457 } /* fits_in_signed_long() */
2460 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2465 return num
<= 0xffffffff;
2467 } /* fits_in_unsigned_long() */
2470 fits_in_disp8 (offsetT num
)
2472 int shift
= i
.memshift
;
2478 mask
= (1 << shift
) - 1;
2480 /* Return 0 if NUM isn't properly aligned. */
2484 /* Check if NUM will fit in 8bit after shift. */
2485 return fits_in_signed_byte (num
>> shift
);
2489 fits_in_imm4 (offsetT num
)
2491 return (num
& 0xf) == num
;
2494 static i386_operand_type
2495 smallest_imm_type (offsetT num
)
2497 i386_operand_type t
;
2499 operand_type_set (&t
, 0);
2500 t
.bitfield
.imm64
= 1;
2502 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2504 /* This code is disabled on the 486 because all the Imm1 forms
2505 in the opcode table are slower on the i486. They're the
2506 versions with the implicitly specified single-position
2507 displacement, which has another syntax if you really want to
2509 t
.bitfield
.imm1
= 1;
2510 t
.bitfield
.imm8
= 1;
2511 t
.bitfield
.imm8s
= 1;
2512 t
.bitfield
.imm16
= 1;
2513 t
.bitfield
.imm32
= 1;
2514 t
.bitfield
.imm32s
= 1;
2516 else if (fits_in_signed_byte (num
))
2518 t
.bitfield
.imm8
= 1;
2519 t
.bitfield
.imm8s
= 1;
2520 t
.bitfield
.imm16
= 1;
2521 t
.bitfield
.imm32
= 1;
2522 t
.bitfield
.imm32s
= 1;
2524 else if (fits_in_unsigned_byte (num
))
2526 t
.bitfield
.imm8
= 1;
2527 t
.bitfield
.imm16
= 1;
2528 t
.bitfield
.imm32
= 1;
2529 t
.bitfield
.imm32s
= 1;
2531 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2533 t
.bitfield
.imm16
= 1;
2534 t
.bitfield
.imm32
= 1;
2535 t
.bitfield
.imm32s
= 1;
2537 else if (fits_in_signed_long (num
))
2539 t
.bitfield
.imm32
= 1;
2540 t
.bitfield
.imm32s
= 1;
2542 else if (fits_in_unsigned_long (num
))
2543 t
.bitfield
.imm32
= 1;
2549 offset_in_range (offsetT val
, int size
)
2555 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2556 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2557 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2559 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2564 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2566 char buf1
[40], buf2
[40];
2568 sprint_value (buf1
, val
);
2569 sprint_value (buf2
, val
& mask
);
2570 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2585 a. PREFIX_EXIST if attempting to add a prefix where one from the
2586 same class already exists.
2587 b. PREFIX_LOCK if lock prefix is added.
2588 c. PREFIX_REP if rep/repne prefix is added.
2589 d. PREFIX_DS if ds prefix is added.
2590 e. PREFIX_OTHER if other prefix is added.
2593 static enum PREFIX_GROUP
2594 add_prefix (unsigned int prefix
)
2596 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2599 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2600 && flag_code
== CODE_64BIT
)
2602 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2603 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2604 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2605 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2616 case DS_PREFIX_OPCODE
:
2619 case CS_PREFIX_OPCODE
:
2620 case ES_PREFIX_OPCODE
:
2621 case FS_PREFIX_OPCODE
:
2622 case GS_PREFIX_OPCODE
:
2623 case SS_PREFIX_OPCODE
:
2627 case REPNE_PREFIX_OPCODE
:
2628 case REPE_PREFIX_OPCODE
:
2633 case LOCK_PREFIX_OPCODE
:
2642 case ADDR_PREFIX_OPCODE
:
2646 case DATA_PREFIX_OPCODE
:
2650 if (i
.prefix
[q
] != 0)
2658 i
.prefix
[q
] |= prefix
;
2661 as_bad (_("same type of prefix used twice"));
2667 update_code_flag (int value
, int check
)
2669 PRINTF_LIKE ((*as_error
));
2671 flag_code
= (enum flag_code
) value
;
2672 if (flag_code
== CODE_64BIT
)
2674 cpu_arch_flags
.bitfield
.cpu64
= 1;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2679 cpu_arch_flags
.bitfield
.cpu64
= 0;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2682 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2685 as_error
= as_fatal
;
2688 (*as_error
) (_("64bit mode not supported on `%s'."),
2689 cpu_arch_name
? cpu_arch_name
: default_arch
);
2691 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2694 as_error
= as_fatal
;
2697 (*as_error
) (_("32bit mode not supported on `%s'."),
2698 cpu_arch_name
? cpu_arch_name
: default_arch
);
2700 stackop_size
= '\0';
2704 set_code_flag (int value
)
2706 update_code_flag (value
, 0);
2710 set_16bit_gcc_code_flag (int new_code_flag
)
2712 flag_code
= (enum flag_code
) new_code_flag
;
2713 if (flag_code
!= CODE_16BIT
)
2715 cpu_arch_flags
.bitfield
.cpu64
= 0;
2716 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2717 stackop_size
= LONG_MNEM_SUFFIX
;
2721 set_intel_syntax (int syntax_flag
)
2723 /* Find out if register prefixing is specified. */
2724 int ask_naked_reg
= 0;
2727 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2730 int e
= get_symbol_name (&string
);
2732 if (strcmp (string
, "prefix") == 0)
2734 else if (strcmp (string
, "noprefix") == 0)
2737 as_bad (_("bad argument to syntax directive."));
2738 (void) restore_line_pointer (e
);
2740 demand_empty_rest_of_line ();
2742 intel_syntax
= syntax_flag
;
2744 if (ask_naked_reg
== 0)
2745 allow_naked_reg
= (intel_syntax
2746 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2748 allow_naked_reg
= (ask_naked_reg
< 0);
2750 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2752 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2753 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2754 register_prefix
= allow_naked_reg
? "" : "%";
2758 set_intel_mnemonic (int mnemonic_flag
)
2760 intel_mnemonic
= mnemonic_flag
;
2764 set_allow_index_reg (int flag
)
2766 allow_index_reg
= flag
;
2770 set_check (int what
)
2772 enum check_kind
*kind
;
2777 kind
= &operand_check
;
2788 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2791 int e
= get_symbol_name (&string
);
2793 if (strcmp (string
, "none") == 0)
2795 else if (strcmp (string
, "warning") == 0)
2796 *kind
= check_warning
;
2797 else if (strcmp (string
, "error") == 0)
2798 *kind
= check_error
;
2800 as_bad (_("bad argument to %s_check directive."), str
);
2801 (void) restore_line_pointer (e
);
2804 as_bad (_("missing argument for %s_check directive"), str
);
2806 demand_empty_rest_of_line ();
2810 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2811 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2814 static const char *arch
;
2816 /* Intel LIOM is only supported on ELF. */
2822 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2823 use default_arch. */
2824 arch
= cpu_arch_name
;
2826 arch
= default_arch
;
2829 /* If we are targeting Intel MCU, we must enable it. */
2830 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2831 || new_flag
.bitfield
.cpuiamcu
)
2834 /* If we are targeting Intel L1OM, we must enable it. */
2835 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2836 || new_flag
.bitfield
.cpul1om
)
2839 /* If we are targeting Intel K1OM, we must enable it. */
2840 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2841 || new_flag
.bitfield
.cpuk1om
)
2844 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2849 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2853 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2856 int e
= get_symbol_name (&string
);
2858 i386_cpu_flags flags
;
2860 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2862 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2864 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2868 cpu_arch_name
= cpu_arch
[j
].name
;
2869 cpu_sub_arch_name
= NULL
;
2870 cpu_arch_flags
= cpu_arch
[j
].flags
;
2871 if (flag_code
== CODE_64BIT
)
2873 cpu_arch_flags
.bitfield
.cpu64
= 1;
2874 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2878 cpu_arch_flags
.bitfield
.cpu64
= 0;
2879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2881 cpu_arch_isa
= cpu_arch
[j
].type
;
2882 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2883 if (!cpu_arch_tune_set
)
2885 cpu_arch_tune
= cpu_arch_isa
;
2886 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2891 flags
= cpu_flags_or (cpu_arch_flags
,
2894 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2896 if (cpu_sub_arch_name
)
2898 char *name
= cpu_sub_arch_name
;
2899 cpu_sub_arch_name
= concat (name
,
2901 (const char *) NULL
);
2905 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2906 cpu_arch_flags
= flags
;
2907 cpu_arch_isa_flags
= flags
;
2911 = cpu_flags_or (cpu_arch_isa_flags
,
2913 (void) restore_line_pointer (e
);
2914 demand_empty_rest_of_line ();
2919 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2921 /* Disable an ISA extension. */
2922 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2923 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2925 flags
= cpu_flags_and_not (cpu_arch_flags
,
2926 cpu_noarch
[j
].flags
);
2927 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2929 if (cpu_sub_arch_name
)
2931 char *name
= cpu_sub_arch_name
;
2932 cpu_sub_arch_name
= concat (name
, string
,
2933 (const char *) NULL
);
2937 cpu_sub_arch_name
= xstrdup (string
);
2938 cpu_arch_flags
= flags
;
2939 cpu_arch_isa_flags
= flags
;
2941 (void) restore_line_pointer (e
);
2942 demand_empty_rest_of_line ();
2946 j
= ARRAY_SIZE (cpu_arch
);
2949 if (j
>= ARRAY_SIZE (cpu_arch
))
2950 as_bad (_("no such architecture: `%s'"), string
);
2952 *input_line_pointer
= e
;
2955 as_bad (_("missing cpu architecture"));
2957 no_cond_jump_promotion
= 0;
2958 if (*input_line_pointer
== ','
2959 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2964 ++input_line_pointer
;
2965 e
= get_symbol_name (&string
);
2967 if (strcmp (string
, "nojumps") == 0)
2968 no_cond_jump_promotion
= 1;
2969 else if (strcmp (string
, "jumps") == 0)
2972 as_bad (_("no such architecture modifier: `%s'"), string
);
2974 (void) restore_line_pointer (e
);
2977 demand_empty_rest_of_line ();
2980 enum bfd_architecture
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || flag_code
!= CODE_64BIT
)
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_arch_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || flag_code
!= CODE_64BIT
)
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_arch_k1om
;
2997 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2999 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3000 || flag_code
== CODE_64BIT
)
3001 as_fatal (_("Intel MCU is 32bit ELF only"));
3002 return bfd_arch_iamcu
;
3005 return bfd_arch_i386
;
3011 if (!strncmp (default_arch
, "x86_64", 6))
3013 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3016 || default_arch
[6] != '\0')
3017 as_fatal (_("Intel L1OM is 64bit ELF only"));
3018 return bfd_mach_l1om
;
3020 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3022 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3023 || default_arch
[6] != '\0')
3024 as_fatal (_("Intel K1OM is 64bit ELF only"));
3025 return bfd_mach_k1om
;
3027 else if (default_arch
[6] == '\0')
3028 return bfd_mach_x86_64
;
3030 return bfd_mach_x64_32
;
3032 else if (!strcmp (default_arch
, "i386")
3033 || !strcmp (default_arch
, "iamcu"))
3035 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3037 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3038 as_fatal (_("Intel MCU is 32bit ELF only"));
3039 return bfd_mach_i386_iamcu
;
3042 return bfd_mach_i386_i386
;
3045 as_fatal (_("unknown architecture"));
3051 /* Support pseudo prefixes like {disp32}. */
3052 lex_type
['{'] = LEX_BEGIN_NAME
;
3054 /* Initialize op_hash hash table. */
3055 op_hash
= str_htab_create ();
3058 const insn_template
*optab
;
3059 templates
*core_optab
;
3061 /* Setup for loop. */
3063 core_optab
= XNEW (templates
);
3064 core_optab
->start
= optab
;
3069 if (optab
->name
== NULL
3070 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3072 /* different name --> ship out current template list;
3073 add to hash table; & begin anew. */
3074 core_optab
->end
= optab
;
3075 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3076 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3078 if (optab
->name
== NULL
)
3080 core_optab
= XNEW (templates
);
3081 core_optab
->start
= optab
;
3086 /* Initialize reg_hash hash table. */
3087 reg_hash
= str_htab_create ();
3089 const reg_entry
*regtab
;
3090 unsigned int regtab_size
= i386_regtab_size
;
3092 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3093 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3094 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3097 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3102 for (c
= 0; c
< 256; c
++)
3107 mnemonic_chars
[c
] = c
;
3108 register_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3111 else if (ISLOWER (c
))
3113 mnemonic_chars
[c
] = c
;
3114 register_chars
[c
] = c
;
3115 operand_chars
[c
] = c
;
3117 else if (ISUPPER (c
))
3119 mnemonic_chars
[c
] = TOLOWER (c
);
3120 register_chars
[c
] = mnemonic_chars
[c
];
3121 operand_chars
[c
] = c
;
3123 else if (c
== '{' || c
== '}')
3125 mnemonic_chars
[c
] = c
;
3126 operand_chars
[c
] = c
;
3128 #ifdef SVR4_COMMENT_CHARS
3129 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3130 operand_chars
[c
] = c
;
3133 if (ISALPHA (c
) || ISDIGIT (c
))
3134 identifier_chars
[c
] = c
;
3137 identifier_chars
[c
] = c
;
3138 operand_chars
[c
] = c
;
3143 identifier_chars
['@'] = '@';
3146 identifier_chars
['?'] = '?';
3147 operand_chars
['?'] = '?';
3149 digit_chars
['-'] = '-';
3150 mnemonic_chars
['_'] = '_';
3151 mnemonic_chars
['-'] = '-';
3152 mnemonic_chars
['.'] = '.';
3153 identifier_chars
['_'] = '_';
3154 identifier_chars
['.'] = '.';
3156 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3157 operand_chars
[(unsigned char) *p
] = *p
;
3160 if (flag_code
== CODE_64BIT
)
3162 #if defined (OBJ_COFF) && defined (TE_PE)
3163 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3166 x86_dwarf2_return_column
= 16;
3168 x86_cie_data_alignment
= -8;
3172 x86_dwarf2_return_column
= 8;
3173 x86_cie_data_alignment
= -4;
3176 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3177 can be turned into BRANCH_PREFIX frag. */
3178 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3183 i386_print_statistics (FILE *file
)
3185 htab_print_statistics (file
, "i386 opcode", op_hash
);
3186 htab_print_statistics (file
, "i386 register", reg_hash
);
3191 /* Debugging routines for md_assemble. */
3192 static void pte (insn_template
*);
3193 static void pt (i386_operand_type
);
3194 static void pe (expressionS
*);
3195 static void ps (symbolS
*);
3198 pi (const char *line
, i386_insn
*x
)
3202 fprintf (stdout
, "%s: template ", line
);
3204 fprintf (stdout
, " address: base %s index %s scale %x\n",
3205 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3206 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3207 x
->log2_scale_factor
);
3208 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3209 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3210 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3211 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3212 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3213 (x
->rex
& REX_W
) != 0,
3214 (x
->rex
& REX_R
) != 0,
3215 (x
->rex
& REX_X
) != 0,
3216 (x
->rex
& REX_B
) != 0);
3217 for (j
= 0; j
< x
->operands
; j
++)
3219 fprintf (stdout
, " #%d: ", j
+ 1);
3221 fprintf (stdout
, "\n");
3222 if (x
->types
[j
].bitfield
.class == Reg
3223 || x
->types
[j
].bitfield
.class == RegMMX
3224 || x
->types
[j
].bitfield
.class == RegSIMD
3225 || x
->types
[j
].bitfield
.class == RegMask
3226 || x
->types
[j
].bitfield
.class == SReg
3227 || x
->types
[j
].bitfield
.class == RegCR
3228 || x
->types
[j
].bitfield
.class == RegDR
3229 || x
->types
[j
].bitfield
.class == RegTR
3230 || x
->types
[j
].bitfield
.class == RegBND
)
3231 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3232 if (operand_type_check (x
->types
[j
], imm
))
3234 if (operand_type_check (x
->types
[j
], disp
))
3235 pe (x
->op
[j
].disps
);
3240 pte (insn_template
*t
)
3243 fprintf (stdout
, " %d operands ", t
->operands
);
3244 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3245 if (t
->extension_opcode
!= None
)
3246 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3247 if (t
->opcode_modifier
.d
)
3248 fprintf (stdout
, "D");
3249 if (t
->opcode_modifier
.w
)
3250 fprintf (stdout
, "W");
3251 fprintf (stdout
, "\n");
3252 for (j
= 0; j
< t
->operands
; j
++)
3254 fprintf (stdout
, " #%d type ", j
+ 1);
3255 pt (t
->operand_types
[j
]);
3256 fprintf (stdout
, "\n");
3263 fprintf (stdout
, " operation %d\n", e
->X_op
);
3264 fprintf (stdout
, " add_number %ld (%lx)\n",
3265 (long) e
->X_add_number
, (long) e
->X_add_number
);
3266 if (e
->X_add_symbol
)
3268 fprintf (stdout
, " add_symbol ");
3269 ps (e
->X_add_symbol
);
3270 fprintf (stdout
, "\n");
3274 fprintf (stdout
, " op_symbol ");
3275 ps (e
->X_op_symbol
);
3276 fprintf (stdout
, "\n");
3283 fprintf (stdout
, "%s type %s%s",
3285 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3286 segment_name (S_GET_SEGMENT (s
)));
3289 static struct type_name
3291 i386_operand_type mask
;
3294 const type_names
[] =
3296 { OPERAND_TYPE_REG8
, "r8" },
3297 { OPERAND_TYPE_REG16
, "r16" },
3298 { OPERAND_TYPE_REG32
, "r32" },
3299 { OPERAND_TYPE_REG64
, "r64" },
3300 { OPERAND_TYPE_ACC8
, "acc8" },
3301 { OPERAND_TYPE_ACC16
, "acc16" },
3302 { OPERAND_TYPE_ACC32
, "acc32" },
3303 { OPERAND_TYPE_ACC64
, "acc64" },
3304 { OPERAND_TYPE_IMM8
, "i8" },
3305 { OPERAND_TYPE_IMM8
, "i8s" },
3306 { OPERAND_TYPE_IMM16
, "i16" },
3307 { OPERAND_TYPE_IMM32
, "i32" },
3308 { OPERAND_TYPE_IMM32S
, "i32s" },
3309 { OPERAND_TYPE_IMM64
, "i64" },
3310 { OPERAND_TYPE_IMM1
, "i1" },
3311 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3312 { OPERAND_TYPE_DISP8
, "d8" },
3313 { OPERAND_TYPE_DISP16
, "d16" },
3314 { OPERAND_TYPE_DISP32
, "d32" },
3315 { OPERAND_TYPE_DISP32S
, "d32s" },
3316 { OPERAND_TYPE_DISP64
, "d64" },
3317 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3318 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3319 { OPERAND_TYPE_CONTROL
, "control reg" },
3320 { OPERAND_TYPE_TEST
, "test reg" },
3321 { OPERAND_TYPE_DEBUG
, "debug reg" },
3322 { OPERAND_TYPE_FLOATREG
, "FReg" },
3323 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3324 { OPERAND_TYPE_SREG
, "SReg" },
3325 { OPERAND_TYPE_REGMMX
, "rMMX" },
3326 { OPERAND_TYPE_REGXMM
, "rXMM" },
3327 { OPERAND_TYPE_REGYMM
, "rYMM" },
3328 { OPERAND_TYPE_REGZMM
, "rZMM" },
3329 { OPERAND_TYPE_REGTMM
, "rTMM" },
3330 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3334 pt (i386_operand_type t
)
3337 i386_operand_type a
;
3339 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3341 a
= operand_type_and (t
, type_names
[j
].mask
);
3342 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3343 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3348 #endif /* DEBUG386 */
3350 static bfd_reloc_code_real_type
3351 reloc (unsigned int size
,
3354 bfd_reloc_code_real_type other
)
3356 if (other
!= NO_RELOC
)
3358 reloc_howto_type
*rel
;
3363 case BFD_RELOC_X86_64_GOT32
:
3364 return BFD_RELOC_X86_64_GOT64
;
3366 case BFD_RELOC_X86_64_GOTPLT64
:
3367 return BFD_RELOC_X86_64_GOTPLT64
;
3369 case BFD_RELOC_X86_64_PLTOFF64
:
3370 return BFD_RELOC_X86_64_PLTOFF64
;
3372 case BFD_RELOC_X86_64_GOTPC32
:
3373 other
= BFD_RELOC_X86_64_GOTPC64
;
3375 case BFD_RELOC_X86_64_GOTPCREL
:
3376 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3378 case BFD_RELOC_X86_64_TPOFF32
:
3379 other
= BFD_RELOC_X86_64_TPOFF64
;
3381 case BFD_RELOC_X86_64_DTPOFF32
:
3382 other
= BFD_RELOC_X86_64_DTPOFF64
;
3388 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3389 if (other
== BFD_RELOC_SIZE32
)
3392 other
= BFD_RELOC_SIZE64
;
3395 as_bad (_("there are no pc-relative size relocations"));
3401 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3402 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3405 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3407 as_bad (_("unknown relocation (%u)"), other
);
3408 else if (size
!= bfd_get_reloc_size (rel
))
3409 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3410 bfd_get_reloc_size (rel
),
3412 else if (pcrel
&& !rel
->pc_relative
)
3413 as_bad (_("non-pc-relative relocation for pc-relative field"));
3414 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3416 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3418 as_bad (_("relocated field and relocation type differ in signedness"));
3427 as_bad (_("there are no unsigned pc-relative relocations"));
3430 case 1: return BFD_RELOC_8_PCREL
;
3431 case 2: return BFD_RELOC_16_PCREL
;
3432 case 4: return BFD_RELOC_32_PCREL
;
3433 case 8: return BFD_RELOC_64_PCREL
;
3435 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3442 case 4: return BFD_RELOC_X86_64_32S
;
3447 case 1: return BFD_RELOC_8
;
3448 case 2: return BFD_RELOC_16
;
3449 case 4: return BFD_RELOC_32
;
3450 case 8: return BFD_RELOC_64
;
3452 as_bad (_("cannot do %s %u byte relocation"),
3453 sign
> 0 ? "signed" : "unsigned", size
);
3459 /* Here we decide which fixups can be adjusted to make them relative to
3460 the beginning of the section instead of the symbol. Basically we need
3461 to make sure that the dynamic relocations are done correctly, so in
3462 some cases we force the original symbol to be used. */
3465 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3467 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3471 /* Don't adjust pc-relative references to merge sections in 64-bit
3473 if (use_rela_relocations
3474 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3478 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3479 and changed later by validate_fix. */
3480 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3481 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3484 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3485 for size relocations. */
3486 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3487 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3488 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3489 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3490 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3492 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3493 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3494 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3495 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3496 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3497 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3498 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3499 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3500 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3506 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3507 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3508 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3509 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3510 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3511 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3512 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3513 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3515 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3516 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3523 intel_float_operand (const char *mnemonic
)
3525 /* Note that the value returned is meaningful only for opcodes with (memory)
3526 operands, hence the code here is free to improperly handle opcodes that
3527 have no operands (for better performance and smaller code). */
3529 if (mnemonic
[0] != 'f')
3530 return 0; /* non-math */
3532 switch (mnemonic
[1])
3534 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3535 the fs segment override prefix not currently handled because no
3536 call path can make opcodes without operands get here */
3538 return 2 /* integer op */;
3540 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3541 return 3; /* fldcw/fldenv */
3544 if (mnemonic
[2] != 'o' /* fnop */)
3545 return 3; /* non-waiting control op */
3548 if (mnemonic
[2] == 's')
3549 return 3; /* frstor/frstpm */
3552 if (mnemonic
[2] == 'a')
3553 return 3; /* fsave */
3554 if (mnemonic
[2] == 't')
3556 switch (mnemonic
[3])
3558 case 'c': /* fstcw */
3559 case 'd': /* fstdw */
3560 case 'e': /* fstenv */
3561 case 's': /* fsts[gw] */
3567 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3568 return 0; /* fxsave/fxrstor are not really math ops */
3575 /* Build the VEX prefix. */
3578 build_vex_prefix (const insn_template
*t
)
3580 unsigned int register_specifier
;
3581 unsigned int implied_prefix
;
3582 unsigned int vector_length
;
3585 /* Check register specifier. */
3586 if (i
.vex
.register_specifier
)
3588 register_specifier
=
3589 ~register_number (i
.vex
.register_specifier
) & 0xf;
3590 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3593 register_specifier
= 0xf;
3595 /* Use 2-byte VEX prefix by swapping destination and source operand
3596 if there are more than 1 register operand. */
3597 if (i
.reg_operands
> 1
3598 && i
.vec_encoding
!= vex_encoding_vex3
3599 && i
.dir_encoding
== dir_encoding_default
3600 && i
.operands
== i
.reg_operands
3601 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3602 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3603 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3606 unsigned int xchg
= i
.operands
- 1;
3607 union i386_op temp_op
;
3608 i386_operand_type temp_type
;
3610 temp_type
= i
.types
[xchg
];
3611 i
.types
[xchg
] = i
.types
[0];
3612 i
.types
[0] = temp_type
;
3613 temp_op
= i
.op
[xchg
];
3614 i
.op
[xchg
] = i
.op
[0];
3617 gas_assert (i
.rm
.mode
== 3);
3621 i
.rm
.regmem
= i
.rm
.reg
;
3624 if (i
.tm
.opcode_modifier
.d
)
3625 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3626 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3627 else /* Use the next insn. */
3631 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3632 are no memory operands and at least 3 register ones. */
3633 if (i
.reg_operands
>= 3
3634 && i
.vec_encoding
!= vex_encoding_vex3
3635 && i
.reg_operands
== i
.operands
- i
.imm_operands
3636 && i
.tm
.opcode_modifier
.vex
3637 && i
.tm
.opcode_modifier
.commutative
3638 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3640 && i
.vex
.register_specifier
3641 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3643 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3644 union i386_op temp_op
;
3645 i386_operand_type temp_type
;
3647 gas_assert (i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
);
3648 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3649 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3650 &i
.types
[i
.operands
- 3]));
3651 gas_assert (i
.rm
.mode
== 3);
3653 temp_type
= i
.types
[xchg
];
3654 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3655 i
.types
[xchg
+ 1] = temp_type
;
3656 temp_op
= i
.op
[xchg
];
3657 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3658 i
.op
[xchg
+ 1] = temp_op
;
3661 xchg
= i
.rm
.regmem
| 8;
3662 i
.rm
.regmem
= ~register_specifier
& 0xf;
3663 gas_assert (!(i
.rm
.regmem
& 8));
3664 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3665 register_specifier
= ~xchg
& 0xf;
3668 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3669 vector_length
= avxscalar
;
3670 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3676 /* Determine vector length from the last multi-length vector
3679 for (op
= t
->operands
; op
--;)
3680 if (t
->operand_types
[op
].bitfield
.xmmword
3681 && t
->operand_types
[op
].bitfield
.ymmword
3682 && i
.types
[op
].bitfield
.ymmword
)
3689 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3694 case DATA_PREFIX_OPCODE
:
3697 case REPE_PREFIX_OPCODE
:
3700 case REPNE_PREFIX_OPCODE
:
3707 /* Check the REX.W bit and VEXW. */
3708 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3709 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3710 else if (i
.tm
.opcode_modifier
.vexw
)
3711 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3713 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3715 /* Use 2-byte VEX prefix if possible. */
3717 && i
.vec_encoding
!= vex_encoding_vex3
3718 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3719 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3721 /* 2-byte VEX prefix. */
3725 i
.vex
.bytes
[0] = 0xc5;
3727 /* Check the REX.R bit. */
3728 r
= (i
.rex
& REX_R
) ? 0 : 1;
3729 i
.vex
.bytes
[1] = (r
<< 7
3730 | register_specifier
<< 3
3731 | vector_length
<< 2
3736 /* 3-byte VEX prefix. */
3741 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3745 i
.vex
.bytes
[0] = 0xc4;
3749 i
.vex
.bytes
[0] = 0xc4;
3753 i
.vex
.bytes
[0] = 0xc4;
3757 i
.vex
.bytes
[0] = 0x8f;
3761 i
.vex
.bytes
[0] = 0x8f;
3765 i
.vex
.bytes
[0] = 0x8f;
3771 /* The high 3 bits of the second VEX byte are 1's compliment
3772 of RXB bits from REX. */
3773 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3775 i
.vex
.bytes
[2] = (w
<< 7
3776 | register_specifier
<< 3
3777 | vector_length
<< 2
3782 static INLINE bfd_boolean
3783 is_evex_encoding (const insn_template
*t
)
3785 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3786 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3787 || t
->opcode_modifier
.sae
;
3790 static INLINE bfd_boolean
3791 is_any_vex_encoding (const insn_template
*t
)
3793 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3796 /* Build the EVEX prefix. */
3799 build_evex_prefix (void)
3801 unsigned int register_specifier
;
3802 unsigned int implied_prefix
;
3804 rex_byte vrex_used
= 0;
3806 /* Check register specifier. */
3807 if (i
.vex
.register_specifier
)
3809 gas_assert ((i
.vrex
& REX_X
) == 0);
3811 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3812 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3813 register_specifier
+= 8;
3814 /* The upper 16 registers are encoded in the fourth byte of the
3816 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3817 i
.vex
.bytes
[3] = 0x8;
3818 register_specifier
= ~register_specifier
& 0xf;
3822 register_specifier
= 0xf;
3824 /* Encode upper 16 vector index register in the fourth byte of
3826 if (!(i
.vrex
& REX_X
))
3827 i
.vex
.bytes
[3] = 0x8;
3832 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3837 case DATA_PREFIX_OPCODE
:
3840 case REPE_PREFIX_OPCODE
:
3843 case REPNE_PREFIX_OPCODE
:
3850 /* 4 byte EVEX prefix. */
3852 i
.vex
.bytes
[0] = 0x62;
3855 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3871 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3873 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3875 /* The fifth bit of the second EVEX byte is 1's compliment of the
3876 REX_R bit in VREX. */
3877 if (!(i
.vrex
& REX_R
))
3878 i
.vex
.bytes
[1] |= 0x10;
3882 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3884 /* When all operands are registers, the REX_X bit in REX is not
3885 used. We reuse it to encode the upper 16 registers, which is
3886 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3887 as 1's compliment. */
3888 if ((i
.vrex
& REX_B
))
3891 i
.vex
.bytes
[1] &= ~0x40;
3895 /* EVEX instructions shouldn't need the REX prefix. */
3896 i
.vrex
&= ~vrex_used
;
3897 gas_assert (i
.vrex
== 0);
3899 /* Check the REX.W bit and VEXW. */
3900 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3901 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3902 else if (i
.tm
.opcode_modifier
.vexw
)
3903 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3905 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3907 /* Encode the U bit. */
3908 implied_prefix
|= 0x4;
3910 /* The third byte of the EVEX prefix. */
3911 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3913 /* The fourth byte of the EVEX prefix. */
3914 /* The zeroing-masking bit. */
3915 if (i
.mask
&& i
.mask
->zeroing
)
3916 i
.vex
.bytes
[3] |= 0x80;
3918 /* Don't always set the broadcast bit if there is no RC. */
3921 /* Encode the vector length. */
3922 unsigned int vec_length
;
3924 if (!i
.tm
.opcode_modifier
.evex
3925 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3929 /* Determine vector length from the last multi-length vector
3931 for (op
= i
.operands
; op
--;)
3932 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3933 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3934 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3936 if (i
.types
[op
].bitfield
.zmmword
)
3938 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3941 else if (i
.types
[op
].bitfield
.ymmword
)
3943 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3946 else if (i
.types
[op
].bitfield
.xmmword
)
3948 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3951 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3953 switch (i
.broadcast
->bytes
)
3956 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3959 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3962 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3971 if (op
>= MAX_OPERANDS
)
3975 switch (i
.tm
.opcode_modifier
.evex
)
3977 case EVEXLIG
: /* LL' is ignored */
3978 vec_length
= evexlig
<< 5;
3981 vec_length
= 0 << 5;
3984 vec_length
= 1 << 5;
3987 vec_length
= 2 << 5;
3993 i
.vex
.bytes
[3] |= vec_length
;
3994 /* Encode the broadcast bit. */
3996 i
.vex
.bytes
[3] |= 0x10;
4000 if (i
.rounding
->type
!= saeonly
)
4001 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
4003 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4006 if (i
.mask
&& i
.mask
->mask
)
4007 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4011 process_immext (void)
4015 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4016 which is coded in the same place as an 8-bit immediate field
4017 would be. Here we fake an 8-bit immediate operand from the
4018 opcode suffix stored in tm.extension_opcode.
4020 AVX instructions also use this encoding, for some of
4021 3 argument instructions. */
4023 gas_assert (i
.imm_operands
<= 1
4025 || (is_any_vex_encoding (&i
.tm
)
4026 && i
.operands
<= 4)));
4028 exp
= &im_expressions
[i
.imm_operands
++];
4029 i
.op
[i
.operands
].imms
= exp
;
4030 i
.types
[i
.operands
] = imm8
;
4032 exp
->X_op
= O_constant
;
4033 exp
->X_add_number
= i
.tm
.extension_opcode
;
4034 i
.tm
.extension_opcode
= None
;
4041 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4046 as_bad (_("invalid instruction `%s' after `%s'"),
4047 i
.tm
.name
, i
.hle_prefix
);
4050 if (i
.prefix
[LOCK_PREFIX
])
4052 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4056 case HLEPrefixRelease
:
4057 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4059 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4063 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4065 as_bad (_("memory destination needed for instruction `%s'"
4066 " after `xrelease'"), i
.tm
.name
);
4073 /* Try the shortest encoding by shortening operand size. */
4076 optimize_encoding (void)
4080 if (optimize_for_space
4081 && !is_any_vex_encoding (&i
.tm
)
4082 && i
.reg_operands
== 1
4083 && i
.imm_operands
== 1
4084 && !i
.types
[1].bitfield
.byte
4085 && i
.op
[0].imms
->X_op
== O_constant
4086 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4087 && (i
.tm
.base_opcode
== 0xa8
4088 || (i
.tm
.base_opcode
== 0xf6
4089 && i
.tm
.extension_opcode
== 0x0)))
4092 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4094 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4095 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4097 i
.types
[1].bitfield
.byte
= 1;
4098 /* Ignore the suffix. */
4100 /* Convert to byte registers. */
4101 if (i
.types
[1].bitfield
.word
)
4103 else if (i
.types
[1].bitfield
.dword
)
4107 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4112 else if (flag_code
== CODE_64BIT
4113 && !is_any_vex_encoding (&i
.tm
)
4114 && ((i
.types
[1].bitfield
.qword
4115 && i
.reg_operands
== 1
4116 && i
.imm_operands
== 1
4117 && i
.op
[0].imms
->X_op
== O_constant
4118 && ((i
.tm
.base_opcode
== 0xb8
4119 && i
.tm
.extension_opcode
== None
4120 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4121 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4122 && ((i
.tm
.base_opcode
== 0x24
4123 || i
.tm
.base_opcode
== 0xa8)
4124 || (i
.tm
.base_opcode
== 0x80
4125 && i
.tm
.extension_opcode
== 0x4)
4126 || ((i
.tm
.base_opcode
== 0xf6
4127 || (i
.tm
.base_opcode
| 1) == 0xc7)
4128 && i
.tm
.extension_opcode
== 0x0)))
4129 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4130 && i
.tm
.base_opcode
== 0x83
4131 && i
.tm
.extension_opcode
== 0x4)))
4132 || (i
.types
[0].bitfield
.qword
4133 && ((i
.reg_operands
== 2
4134 && i
.op
[0].regs
== i
.op
[1].regs
4135 && (i
.tm
.base_opcode
== 0x30
4136 || i
.tm
.base_opcode
== 0x28))
4137 || (i
.reg_operands
== 1
4139 && i
.tm
.base_opcode
== 0x30)))))
4142 andq $imm31, %r64 -> andl $imm31, %r32
4143 andq $imm7, %r64 -> andl $imm7, %r32
4144 testq $imm31, %r64 -> testl $imm31, %r32
4145 xorq %r64, %r64 -> xorl %r32, %r32
4146 subq %r64, %r64 -> subl %r32, %r32
4147 movq $imm31, %r64 -> movl $imm31, %r32
4148 movq $imm32, %r64 -> movl $imm32, %r32
4150 i
.tm
.opcode_modifier
.norex64
= 1;
4151 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4154 movq $imm31, %r64 -> movl $imm31, %r32
4155 movq $imm32, %r64 -> movl $imm32, %r32
4157 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4158 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4159 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4160 i
.types
[0].bitfield
.imm32
= 1;
4161 i
.types
[0].bitfield
.imm32s
= 0;
4162 i
.types
[0].bitfield
.imm64
= 0;
4163 i
.types
[1].bitfield
.dword
= 1;
4164 i
.types
[1].bitfield
.qword
= 0;
4165 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4168 movq $imm31, %r64 -> movl $imm31, %r32
4170 i
.tm
.base_opcode
= 0xb8;
4171 i
.tm
.extension_opcode
= None
;
4172 i
.tm
.opcode_modifier
.w
= 0;
4173 i
.tm
.opcode_modifier
.modrm
= 0;
4177 else if (optimize
> 1
4178 && !optimize_for_space
4179 && !is_any_vex_encoding (&i
.tm
)
4180 && i
.reg_operands
== 2
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4183 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4184 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4187 andb %rN, %rN -> testb %rN, %rN
4188 andw %rN, %rN -> testw %rN, %rN
4189 andq %rN, %rN -> testq %rN, %rN
4190 orb %rN, %rN -> testb %rN, %rN
4191 orw %rN, %rN -> testw %rN, %rN
4192 orq %rN, %rN -> testq %rN, %rN
4194 and outside of 64-bit mode
4196 andl %rN, %rN -> testl %rN, %rN
4197 orl %rN, %rN -> testl %rN, %rN
4199 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4201 else if (i
.reg_operands
== 3
4202 && i
.op
[0].regs
== i
.op
[1].regs
4203 && !i
.types
[2].bitfield
.xmmword
4204 && (i
.tm
.opcode_modifier
.vex
4205 || ((!i
.mask
|| i
.mask
->zeroing
)
4207 && is_evex_encoding (&i
.tm
)
4208 && (i
.vec_encoding
!= vex_encoding_evex
4209 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4210 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4211 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4212 && i
.types
[2].bitfield
.ymmword
))))
4213 && ((i
.tm
.base_opcode
== 0x55
4214 || i
.tm
.base_opcode
== 0x6655
4215 || i
.tm
.base_opcode
== 0x66df
4216 || i
.tm
.base_opcode
== 0x57
4217 || i
.tm
.base_opcode
== 0x6657
4218 || i
.tm
.base_opcode
== 0x66ef
4219 || i
.tm
.base_opcode
== 0x66f8
4220 || i
.tm
.base_opcode
== 0x66f9
4221 || i
.tm
.base_opcode
== 0x66fa
4222 || i
.tm
.base_opcode
== 0x66fb
4223 || i
.tm
.base_opcode
== 0x42
4224 || i
.tm
.base_opcode
== 0x6642
4225 || i
.tm
.base_opcode
== 0x47
4226 || i
.tm
.base_opcode
== 0x6647)
4227 && i
.tm
.extension_opcode
== None
))
4230 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4232 EVEX VOP %zmmM, %zmmM, %zmmN
4233 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4234 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4235 EVEX VOP %ymmM, %ymmM, %ymmN
4236 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4237 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4238 VEX VOP %ymmM, %ymmM, %ymmN
4239 -> VEX VOP %xmmM, %xmmM, %xmmN
4240 VOP, one of vpandn and vpxor:
4241 VEX VOP %ymmM, %ymmM, %ymmN
4242 -> VEX VOP %xmmM, %xmmM, %xmmN
4243 VOP, one of vpandnd and vpandnq:
4244 EVEX VOP %zmmM, %zmmM, %zmmN
4245 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4246 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4247 EVEX VOP %ymmM, %ymmM, %ymmN
4248 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4249 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4250 VOP, one of vpxord and vpxorq:
4251 EVEX VOP %zmmM, %zmmM, %zmmN
4252 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4253 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4254 EVEX VOP %ymmM, %ymmM, %ymmN
4255 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4256 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4257 VOP, one of kxord and kxorq:
4258 VEX VOP %kM, %kM, %kN
4259 -> VEX kxorw %kM, %kM, %kN
4260 VOP, one of kandnd and kandnq:
4261 VEX VOP %kM, %kM, %kN
4262 -> VEX kandnw %kM, %kM, %kN
4264 if (is_evex_encoding (&i
.tm
))
4266 if (i
.vec_encoding
!= vex_encoding_evex
)
4268 i
.tm
.opcode_modifier
.vex
= VEX128
;
4269 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4270 i
.tm
.opcode_modifier
.evex
= 0;
4272 else if (optimize
> 1)
4273 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4277 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4279 i
.tm
.base_opcode
&= 0xff;
4280 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4283 i
.tm
.opcode_modifier
.vex
= VEX128
;
4285 if (i
.tm
.opcode_modifier
.vex
)
4286 for (j
= 0; j
< 3; j
++)
4288 i
.types
[j
].bitfield
.xmmword
= 1;
4289 i
.types
[j
].bitfield
.ymmword
= 0;
4292 else if (i
.vec_encoding
!= vex_encoding_evex
4293 && !i
.types
[0].bitfield
.zmmword
4294 && !i
.types
[1].bitfield
.zmmword
4297 && is_evex_encoding (&i
.tm
)
4298 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4299 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4300 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4301 || (i
.tm
.base_opcode
& ~4) == 0x66db
4302 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4303 && i
.tm
.extension_opcode
== None
)
4306 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4307 vmovdqu32 and vmovdqu64:
4308 EVEX VOP %xmmM, %xmmN
4309 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4310 EVEX VOP %ymmM, %ymmN
4311 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4313 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4315 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4317 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4319 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4320 VOP, one of vpand, vpandn, vpor, vpxor:
4321 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4322 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4323 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4324 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4325 EVEX VOP{d,q} mem, %xmmM, %xmmN
4326 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4327 EVEX VOP{d,q} mem, %ymmM, %ymmN
4328 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4330 for (j
= 0; j
< i
.operands
; j
++)
4331 if (operand_type_check (i
.types
[j
], disp
)
4332 && i
.op
[j
].disps
->X_op
== O_constant
)
4334 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4335 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4336 bytes, we choose EVEX Disp8 over VEX Disp32. */
4337 int evex_disp8
, vex_disp8
;
4338 unsigned int memshift
= i
.memshift
;
4339 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4341 evex_disp8
= fits_in_disp8 (n
);
4343 vex_disp8
= fits_in_disp8 (n
);
4344 if (evex_disp8
!= vex_disp8
)
4346 i
.memshift
= memshift
;
4350 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4353 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4354 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4355 i
.tm
.opcode_modifier
.vex
4356 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4357 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4358 /* VPAND, VPOR, and VPXOR are commutative. */
4359 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4360 i
.tm
.opcode_modifier
.commutative
= 1;
4361 i
.tm
.opcode_modifier
.evex
= 0;
4362 i
.tm
.opcode_modifier
.masking
= 0;
4363 i
.tm
.opcode_modifier
.broadcast
= 0;
4364 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4367 i
.types
[j
].bitfield
.disp8
4368 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4372 /* Return non-zero for load instruction. */
4378 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4379 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4383 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4384 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4385 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4386 if (i
.tm
.opcode_modifier
.anysize
)
4389 /* pop, popf, popa. */
4390 if (strcmp (i
.tm
.name
, "pop") == 0
4391 || i
.tm
.base_opcode
== 0x9d
4392 || i
.tm
.base_opcode
== 0x61)
4395 /* movs, cmps, lods, scas. */
4396 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4400 if (base_opcode
== 0x6f
4401 || i
.tm
.base_opcode
== 0xd7)
4403 /* NB: For AMD-specific insns with implicit memory operands,
4404 they're intentionally not covered. */
4407 /* No memory operand. */
4408 if (!i
.mem_operands
)
4414 if (i
.tm
.base_opcode
== 0xae
4415 && i
.tm
.opcode_modifier
.vex
4416 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
4417 && i
.tm
.extension_opcode
== 2)
4422 /* test, not, neg, mul, imul, div, idiv. */
4423 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4424 && i
.tm
.extension_opcode
!= 1)
4428 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4431 /* add, or, adc, sbb, and, sub, xor, cmp. */
4432 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4435 /* bt, bts, btr, btc. */
4436 if (i
.tm
.base_opcode
== 0xfba
4437 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4440 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4441 if ((base_opcode
== 0xc1
4442 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4443 && i
.tm
.extension_opcode
!= 6)
4446 /* cmpxchg8b, cmpxchg16b, xrstors. */
4447 if (i
.tm
.base_opcode
== 0xfc7
4448 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4449 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4452 /* fxrstor, ldmxcsr, xrstor. */
4453 if (i
.tm
.base_opcode
== 0xfae
4454 && (i
.tm
.extension_opcode
== 1
4455 || i
.tm
.extension_opcode
== 2
4456 || i
.tm
.extension_opcode
== 5))
4459 /* lgdt, lidt, lmsw. */
4460 if (i
.tm
.base_opcode
== 0xf01
4461 && (i
.tm
.extension_opcode
== 2
4462 || i
.tm
.extension_opcode
== 3
4463 || i
.tm
.extension_opcode
== 6))
4467 if (i
.tm
.base_opcode
== 0xfc7
4468 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
4469 && i
.tm
.extension_opcode
== 6)
4472 /* Check for x87 instructions. */
4473 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4475 /* Skip fst, fstp, fstenv, fstcw. */
4476 if (i
.tm
.base_opcode
== 0xd9
4477 && (i
.tm
.extension_opcode
== 2
4478 || i
.tm
.extension_opcode
== 3
4479 || i
.tm
.extension_opcode
== 6
4480 || i
.tm
.extension_opcode
== 7))
4483 /* Skip fisttp, fist, fistp, fstp. */
4484 if (i
.tm
.base_opcode
== 0xdb
4485 && (i
.tm
.extension_opcode
== 1
4486 || i
.tm
.extension_opcode
== 2
4487 || i
.tm
.extension_opcode
== 3
4488 || i
.tm
.extension_opcode
== 7))
4491 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4492 if (i
.tm
.base_opcode
== 0xdd
4493 && (i
.tm
.extension_opcode
== 1
4494 || i
.tm
.extension_opcode
== 2
4495 || i
.tm
.extension_opcode
== 3
4496 || i
.tm
.extension_opcode
== 6
4497 || i
.tm
.extension_opcode
== 7))
4500 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4501 if (i
.tm
.base_opcode
== 0xdf
4502 && (i
.tm
.extension_opcode
== 1
4503 || i
.tm
.extension_opcode
== 2
4504 || i
.tm
.extension_opcode
== 3
4505 || i
.tm
.extension_opcode
== 6
4506 || i
.tm
.extension_opcode
== 7))
4513 dest
= i
.operands
- 1;
4515 /* Check fake imm8 operand and 3 source operands. */
4516 if ((i
.tm
.opcode_modifier
.immext
4517 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4518 && i
.types
[dest
].bitfield
.imm8
)
4521 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4523 && (base_opcode
== 0x1
4524 || base_opcode
== 0x9
4525 || base_opcode
== 0x11
4526 || base_opcode
== 0x19
4527 || base_opcode
== 0x21
4528 || base_opcode
== 0x29
4529 || base_opcode
== 0x31
4530 || base_opcode
== 0x39
4531 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4532 || base_opcode
== 0xfc1))
4535 /* Check for load instruction. */
4536 return (i
.types
[dest
].bitfield
.class != ClassNone
4537 || i
.types
[dest
].bitfield
.instance
== Accum
);
4540 /* Output lfence, 0xfaee8, after instruction. */
4543 insert_lfence_after (void)
4545 if (lfence_after_load
&& load_insn_p ())
4547 /* There are also two REP string instructions that require
4548 special treatment. Specifically, the compare string (CMPS)
4549 and scan string (SCAS) instructions set EFLAGS in a manner
4550 that depends on the data being compared/scanned. When used
4551 with a REP prefix, the number of iterations may therefore
4552 vary depending on this data. If the data is a program secret
4553 chosen by the adversary using an LVI method,
4554 then this data-dependent behavior may leak some aspect
4556 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4557 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4558 && i
.prefix
[REP_PREFIX
])
4560 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4563 char *p
= frag_more (3);
4570 /* Output lfence, 0xfaee8, before instruction. */
4573 insert_lfence_before (void)
4577 if (is_any_vex_encoding (&i
.tm
))
4580 if (i
.tm
.base_opcode
== 0xff
4581 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4583 /* Insert lfence before indirect branch if needed. */
4585 if (lfence_before_indirect_branch
== lfence_branch_none
)
4588 if (i
.operands
!= 1)
4591 if (i
.reg_operands
== 1)
4593 /* Indirect branch via register. Don't insert lfence with
4594 -mlfence-after-load=yes. */
4595 if (lfence_after_load
4596 || lfence_before_indirect_branch
== lfence_branch_memory
)
4599 else if (i
.mem_operands
== 1
4600 && lfence_before_indirect_branch
!= lfence_branch_register
)
4602 as_warn (_("indirect `%s` with memory operand should be avoided"),
4609 if (last_insn
.kind
!= last_insn_other
4610 && last_insn
.seg
== now_seg
)
4612 as_warn_where (last_insn
.file
, last_insn
.line
,
4613 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4614 last_insn
.name
, i
.tm
.name
);
4625 /* Output or/not/shl and lfence before near ret. */
4626 if (lfence_before_ret
!= lfence_before_ret_none
4627 && (i
.tm
.base_opcode
== 0xc2
4628 || i
.tm
.base_opcode
== 0xc3))
4630 if (last_insn
.kind
!= last_insn_other
4631 && last_insn
.seg
== now_seg
)
4633 as_warn_where (last_insn
.file
, last_insn
.line
,
4634 _("`%s` skips -mlfence-before-ret on `%s`"),
4635 last_insn
.name
, i
.tm
.name
);
4639 /* Near ret ingore operand size override under CPU64. */
4640 char prefix
= flag_code
== CODE_64BIT
4642 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4644 if (lfence_before_ret
== lfence_before_ret_not
)
4646 /* not: 0xf71424, may add prefix
4647 for operand size override or 64-bit code. */
4648 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4662 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4665 if (lfence_before_ret
== lfence_before_ret_or
)
4667 /* or: 0x830c2400, may add prefix
4668 for operand size override or 64-bit code. */
4674 /* shl: 0xc1242400, may add prefix
4675 for operand size override or 64-bit code. */
4690 /* This is the guts of the machine-dependent assembler. LINE points to a
4691 machine dependent instruction. This function is supposed to emit
4692 the frags/bytes it assembles to. */
4695 md_assemble (char *line
)
4698 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4699 const insn_template
*t
;
4701 /* Initialize globals. */
4702 memset (&i
, '\0', sizeof (i
));
4703 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4704 i
.reloc
[j
] = NO_RELOC
;
4705 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4706 memset (im_expressions
, '\0', sizeof (im_expressions
));
4707 save_stack_p
= save_stack
;
4709 /* First parse an instruction mnemonic & call i386_operand for the operands.
4710 We assume that the scrubber has arranged it so that line[0] is the valid
4711 start of a (possibly prefixed) mnemonic. */
4713 line
= parse_insn (line
, mnemonic
);
4716 mnem_suffix
= i
.suffix
;
4718 line
= parse_operands (line
, mnemonic
);
4720 xfree (i
.memop1_string
);
4721 i
.memop1_string
= NULL
;
4725 /* Now we've parsed the mnemonic into a set of templates, and have the
4726 operands at hand. */
4728 /* All Intel opcodes have reversed operands except for "bound", "enter",
4729 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4730 intersegment "jmp" and "call" instructions with 2 immediate operands so
4731 that the immediate segment precedes the offset, as it does when in AT&T
4735 && (strcmp (mnemonic
, "bound") != 0)
4736 && (strcmp (mnemonic
, "invlpga") != 0)
4737 && (strncmp (mnemonic
, "monitor", 7) != 0)
4738 && (strncmp (mnemonic
, "mwait", 5) != 0)
4739 && (strcmp (mnemonic
, "tpause") != 0)
4740 && (strcmp (mnemonic
, "umwait") != 0)
4741 && !(operand_type_check (i
.types
[0], imm
)
4742 && operand_type_check (i
.types
[1], imm
)))
4745 /* The order of the immediates should be reversed
4746 for 2 immediates extrq and insertq instructions */
4747 if (i
.imm_operands
== 2
4748 && (strcmp (mnemonic
, "extrq") == 0
4749 || strcmp (mnemonic
, "insertq") == 0))
4750 swap_2_operands (0, 1);
4755 /* Don't optimize displacement for movabs since it only takes 64bit
4758 && i
.disp_encoding
!= disp_encoding_32bit
4759 && (flag_code
!= CODE_64BIT
4760 || strcmp (mnemonic
, "movabs") != 0))
4763 /* Next, we find a template that matches the given insn,
4764 making sure the overlap of the given operands types is consistent
4765 with the template operand types. */
4767 if (!(t
= match_template (mnem_suffix
)))
4770 if (sse_check
!= check_none
4771 && !i
.tm
.opcode_modifier
.noavx
4772 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4773 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4774 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4775 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4776 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4777 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4778 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4779 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4780 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4781 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4782 || i
.tm
.cpu_flags
.bitfield
.cpusha
4783 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4785 (sse_check
== check_warning
4787 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4790 if (i
.tm
.opcode_modifier
.fwait
)
4791 if (!add_prefix (FWAIT_OPCODE
))
4794 /* Check if REP prefix is OK. */
4795 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4797 as_bad (_("invalid instruction `%s' after `%s'"),
4798 i
.tm
.name
, i
.rep_prefix
);
4802 /* Check for lock without a lockable instruction. Destination operand
4803 must be memory unless it is xchg (0x86). */
4804 if (i
.prefix
[LOCK_PREFIX
]
4805 && (!i
.tm
.opcode_modifier
.islockable
4806 || i
.mem_operands
== 0
4807 || (i
.tm
.base_opcode
!= 0x86
4808 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4810 as_bad (_("expecting lockable instruction after `lock'"));
4814 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4815 if (i
.prefix
[DATA_PREFIX
]
4816 && (is_any_vex_encoding (&i
.tm
)
4817 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4818 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4820 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4824 /* Check if HLE prefix is OK. */
4825 if (i
.hle_prefix
&& !check_hle ())
4828 /* Check BND prefix. */
4829 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4830 as_bad (_("expecting valid branch instruction after `bnd'"));
4832 /* Check NOTRACK prefix. */
4833 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4834 as_bad (_("expecting indirect branch instruction after `notrack'"));
4836 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4838 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4839 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4840 else if (flag_code
!= CODE_16BIT
4841 ? i
.prefix
[ADDR_PREFIX
]
4842 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4843 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4846 /* Insert BND prefix. */
4847 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4849 if (!i
.prefix
[BND_PREFIX
])
4850 add_prefix (BND_PREFIX_OPCODE
);
4851 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4853 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4854 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4858 /* Check string instruction segment overrides. */
4859 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4861 gas_assert (i
.mem_operands
);
4862 if (!check_string ())
4864 i
.disp_operands
= 0;
4867 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4868 optimize_encoding ();
4870 if (!process_suffix ())
4873 /* Update operand types and check extended states. */
4874 for (j
= 0; j
< i
.operands
; j
++)
4876 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4877 switch (i
.types
[j
].bitfield
.class)
4882 i
.xstate
|= xstate_mmx
;
4885 i
.xstate
|= xstate_mask
;
4888 if (i
.types
[j
].bitfield
.tmmword
)
4889 i
.xstate
|= xstate_tmm
;
4890 else if (i
.types
[j
].bitfield
.zmmword
)
4891 i
.xstate
|= xstate_zmm
;
4892 else if (i
.types
[j
].bitfield
.ymmword
)
4893 i
.xstate
|= xstate_ymm
;
4894 else if (i
.types
[j
].bitfield
.xmmword
)
4895 i
.xstate
|= xstate_xmm
;
4900 /* Make still unresolved immediate matches conform to size of immediate
4901 given in i.suffix. */
4902 if (!finalize_imm ())
4905 if (i
.types
[0].bitfield
.imm1
)
4906 i
.imm_operands
= 0; /* kludge for shift insns. */
4908 /* We only need to check those implicit registers for instructions
4909 with 3 operands or less. */
4910 if (i
.operands
<= 3)
4911 for (j
= 0; j
< i
.operands
; j
++)
4912 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4913 && !i
.types
[j
].bitfield
.xmmword
)
4916 /* For insns with operands there are more diddles to do to the opcode. */
4919 if (!process_operands ())
4922 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4924 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4925 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4928 if (is_any_vex_encoding (&i
.tm
))
4930 if (!cpu_arch_flags
.bitfield
.cpui286
)
4932 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4937 /* Check for explicit REX prefix. */
4938 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4940 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4944 if (i
.tm
.opcode_modifier
.vex
)
4945 build_vex_prefix (t
);
4947 build_evex_prefix ();
4949 /* The individual REX.RXBW bits got consumed. */
4950 i
.rex
&= REX_OPCODE
;
4953 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4954 instructions may define INT_OPCODE as well, so avoid this corner
4955 case for those instructions that use MODRM. */
4956 if (i
.tm
.base_opcode
== INT_OPCODE
4957 && !i
.tm
.opcode_modifier
.modrm
4958 && i
.op
[0].imms
->X_add_number
== 3)
4960 i
.tm
.base_opcode
= INT3_OPCODE
;
4964 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4965 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4966 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4967 && i
.op
[0].disps
->X_op
== O_constant
)
4969 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4970 the absolute address given by the constant. Since ix86 jumps and
4971 calls are pc relative, we need to generate a reloc. */
4972 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4973 i
.op
[0].disps
->X_op
= O_symbol
;
4976 /* For 8 bit registers we need an empty rex prefix. Also if the
4977 instruction already has a prefix, we need to convert old
4978 registers to new ones. */
4980 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4981 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4982 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4983 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4984 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4985 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4990 i
.rex
|= REX_OPCODE
;
4991 for (x
= 0; x
< 2; x
++)
4993 /* Look for 8 bit operand that uses old registers. */
4994 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4995 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4997 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4998 /* In case it is "hi" register, give up. */
4999 if (i
.op
[x
].regs
->reg_num
> 3)
5000 as_bad (_("can't encode register '%s%s' in an "
5001 "instruction requiring REX prefix."),
5002 register_prefix
, i
.op
[x
].regs
->reg_name
);
5004 /* Otherwise it is equivalent to the extended register.
5005 Since the encoding doesn't change this is merely
5006 cosmetic cleanup for debug output. */
5008 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5013 if (i
.rex
== 0 && i
.rex_encoding
)
5015 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5016 that uses legacy register. If it is "hi" register, don't add
5017 the REX_OPCODE byte. */
5019 for (x
= 0; x
< 2; x
++)
5020 if (i
.types
[x
].bitfield
.class == Reg
5021 && i
.types
[x
].bitfield
.byte
5022 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5023 && i
.op
[x
].regs
->reg_num
> 3)
5025 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5026 i
.rex_encoding
= FALSE
;
5035 add_prefix (REX_OPCODE
| i
.rex
);
5037 insert_lfence_before ();
5039 /* We are ready to output the insn. */
5042 insert_lfence_after ();
5044 last_insn
.seg
= now_seg
;
5046 if (i
.tm
.opcode_modifier
.isprefix
)
5048 last_insn
.kind
= last_insn_prefix
;
5049 last_insn
.name
= i
.tm
.name
;
5050 last_insn
.file
= as_where (&last_insn
.line
);
5053 last_insn
.kind
= last_insn_other
;
5057 parse_insn (char *line
, char *mnemonic
)
5060 char *token_start
= l
;
5063 const insn_template
*t
;
5069 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5074 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5076 as_bad (_("no such instruction: `%s'"), token_start
);
5081 if (!is_space_char (*l
)
5082 && *l
!= END_OF_INSN
5084 || (*l
!= PREFIX_SEPARATOR
5087 as_bad (_("invalid character %s in mnemonic"),
5088 output_invalid (*l
));
5091 if (token_start
== l
)
5093 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5094 as_bad (_("expecting prefix; got nothing"));
5096 as_bad (_("expecting mnemonic; got nothing"));
5100 /* Look up instruction (or prefix) via hash table. */
5101 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5103 if (*l
!= END_OF_INSN
5104 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5105 && current_templates
5106 && current_templates
->start
->opcode_modifier
.isprefix
)
5108 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5110 as_bad ((flag_code
!= CODE_64BIT
5111 ? _("`%s' is only supported in 64-bit mode")
5112 : _("`%s' is not supported in 64-bit mode")),
5113 current_templates
->start
->name
);
5116 /* If we are in 16-bit mode, do not allow addr16 or data16.
5117 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5118 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5119 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5120 && flag_code
!= CODE_64BIT
5121 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5122 ^ (flag_code
== CODE_16BIT
)))
5124 as_bad (_("redundant %s prefix"),
5125 current_templates
->start
->name
);
5128 if (current_templates
->start
->opcode_length
== 0)
5130 /* Handle pseudo prefixes. */
5131 switch (current_templates
->start
->base_opcode
)
5135 i
.disp_encoding
= disp_encoding_8bit
;
5139 i
.disp_encoding
= disp_encoding_16bit
;
5143 i
.disp_encoding
= disp_encoding_32bit
;
5147 i
.dir_encoding
= dir_encoding_load
;
5151 i
.dir_encoding
= dir_encoding_store
;
5155 i
.vec_encoding
= vex_encoding_vex
;
5159 i
.vec_encoding
= vex_encoding_vex3
;
5163 i
.vec_encoding
= vex_encoding_evex
;
5167 i
.rex_encoding
= TRUE
;
5169 case Prefix_NoOptimize
:
5171 i
.no_optimize
= TRUE
;
5179 /* Add prefix, checking for repeated prefixes. */
5180 switch (add_prefix (current_templates
->start
->base_opcode
))
5185 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5186 i
.notrack_prefix
= current_templates
->start
->name
;
5189 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5190 i
.hle_prefix
= current_templates
->start
->name
;
5191 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5192 i
.bnd_prefix
= current_templates
->start
->name
;
5194 i
.rep_prefix
= current_templates
->start
->name
;
5200 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5207 if (!current_templates
)
5209 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5210 Check if we should swap operand or force 32bit displacement in
5212 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5213 i
.dir_encoding
= dir_encoding_swap
;
5214 else if (mnem_p
- 3 == dot_p
5217 i
.disp_encoding
= disp_encoding_8bit
;
5218 else if (mnem_p
- 4 == dot_p
5222 i
.disp_encoding
= disp_encoding_32bit
;
5227 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5230 if (!current_templates
)
5233 if (mnem_p
> mnemonic
)
5235 /* See if we can get a match by trimming off a suffix. */
5238 case WORD_MNEM_SUFFIX
:
5239 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5240 i
.suffix
= SHORT_MNEM_SUFFIX
;
5243 case BYTE_MNEM_SUFFIX
:
5244 case QWORD_MNEM_SUFFIX
:
5245 i
.suffix
= mnem_p
[-1];
5248 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5250 case SHORT_MNEM_SUFFIX
:
5251 case LONG_MNEM_SUFFIX
:
5254 i
.suffix
= mnem_p
[-1];
5257 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5265 if (intel_float_operand (mnemonic
) == 1)
5266 i
.suffix
= SHORT_MNEM_SUFFIX
;
5268 i
.suffix
= LONG_MNEM_SUFFIX
;
5271 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5277 if (!current_templates
)
5279 as_bad (_("no such instruction: `%s'"), token_start
);
5284 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5285 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5287 /* Check for a branch hint. We allow ",pt" and ",pn" for
5288 predict taken and predict not taken respectively.
5289 I'm not sure that branch hints actually do anything on loop
5290 and jcxz insns (JumpByte) for current Pentium4 chips. They
5291 may work in the future and it doesn't hurt to accept them
5293 if (l
[0] == ',' && l
[1] == 'p')
5297 if (!add_prefix (DS_PREFIX_OPCODE
))
5301 else if (l
[2] == 'n')
5303 if (!add_prefix (CS_PREFIX_OPCODE
))
5309 /* Any other comma loses. */
5312 as_bad (_("invalid character %s in mnemonic"),
5313 output_invalid (*l
));
5317 /* Check if instruction is supported on specified architecture. */
5319 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5321 supported
|= cpu_flags_match (t
);
5322 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5324 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5325 as_warn (_("use .code16 to ensure correct addressing mode"));
5331 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5332 as_bad (flag_code
== CODE_64BIT
5333 ? _("`%s' is not supported in 64-bit mode")
5334 : _("`%s' is only supported in 64-bit mode"),
5335 current_templates
->start
->name
);
5337 as_bad (_("`%s' is not supported on `%s%s'"),
5338 current_templates
->start
->name
,
5339 cpu_arch_name
? cpu_arch_name
: default_arch
,
5340 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5346 parse_operands (char *l
, const char *mnemonic
)
5350 /* 1 if operand is pending after ','. */
5351 unsigned int expecting_operand
= 0;
5353 /* Non-zero if operand parens not balanced. */
5354 unsigned int paren_not_balanced
;
5356 while (*l
!= END_OF_INSN
)
5358 /* Skip optional white space before operand. */
5359 if (is_space_char (*l
))
5361 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5363 as_bad (_("invalid character %s before operand %d"),
5364 output_invalid (*l
),
5368 token_start
= l
; /* After white space. */
5369 paren_not_balanced
= 0;
5370 while (paren_not_balanced
|| *l
!= ',')
5372 if (*l
== END_OF_INSN
)
5374 if (paren_not_balanced
)
5377 as_bad (_("unbalanced parenthesis in operand %d."),
5380 as_bad (_("unbalanced brackets in operand %d."),
5385 break; /* we are done */
5387 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5389 as_bad (_("invalid character %s in operand %d"),
5390 output_invalid (*l
),
5397 ++paren_not_balanced
;
5399 --paren_not_balanced
;
5404 ++paren_not_balanced
;
5406 --paren_not_balanced
;
5410 if (l
!= token_start
)
5411 { /* Yes, we've read in another operand. */
5412 unsigned int operand_ok
;
5413 this_operand
= i
.operands
++;
5414 if (i
.operands
> MAX_OPERANDS
)
5416 as_bad (_("spurious operands; (%d operands/instruction max)"),
5420 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5421 /* Now parse operand adding info to 'i' as we go along. */
5422 END_STRING_AND_SAVE (l
);
5424 if (i
.mem_operands
> 1)
5426 as_bad (_("too many memory references for `%s'"),
5433 i386_intel_operand (token_start
,
5434 intel_float_operand (mnemonic
));
5436 operand_ok
= i386_att_operand (token_start
);
5438 RESTORE_END_STRING (l
);
5444 if (expecting_operand
)
5446 expecting_operand_after_comma
:
5447 as_bad (_("expecting operand after ','; got nothing"));
5452 as_bad (_("expecting operand before ','; got nothing"));
5457 /* Now *l must be either ',' or END_OF_INSN. */
5460 if (*++l
== END_OF_INSN
)
5462 /* Just skip it, if it's \n complain. */
5463 goto expecting_operand_after_comma
;
5465 expecting_operand
= 1;
5472 swap_2_operands (int xchg1
, int xchg2
)
5474 union i386_op temp_op
;
5475 i386_operand_type temp_type
;
5476 unsigned int temp_flags
;
5477 enum bfd_reloc_code_real temp_reloc
;
5479 temp_type
= i
.types
[xchg2
];
5480 i
.types
[xchg2
] = i
.types
[xchg1
];
5481 i
.types
[xchg1
] = temp_type
;
5483 temp_flags
= i
.flags
[xchg2
];
5484 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5485 i
.flags
[xchg1
] = temp_flags
;
5487 temp_op
= i
.op
[xchg2
];
5488 i
.op
[xchg2
] = i
.op
[xchg1
];
5489 i
.op
[xchg1
] = temp_op
;
5491 temp_reloc
= i
.reloc
[xchg2
];
5492 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5493 i
.reloc
[xchg1
] = temp_reloc
;
5497 if (i
.mask
->operand
== xchg1
)
5498 i
.mask
->operand
= xchg2
;
5499 else if (i
.mask
->operand
== xchg2
)
5500 i
.mask
->operand
= xchg1
;
5504 if (i
.broadcast
->operand
== xchg1
)
5505 i
.broadcast
->operand
= xchg2
;
5506 else if (i
.broadcast
->operand
== xchg2
)
5507 i
.broadcast
->operand
= xchg1
;
5511 if (i
.rounding
->operand
== xchg1
)
5512 i
.rounding
->operand
= xchg2
;
5513 else if (i
.rounding
->operand
== xchg2
)
5514 i
.rounding
->operand
= xchg1
;
5519 swap_operands (void)
5525 swap_2_operands (1, i
.operands
- 2);
5529 swap_2_operands (0, i
.operands
- 1);
5535 if (i
.mem_operands
== 2)
5537 const seg_entry
*temp_seg
;
5538 temp_seg
= i
.seg
[0];
5539 i
.seg
[0] = i
.seg
[1];
5540 i
.seg
[1] = temp_seg
;
5544 /* Try to ensure constant immediates are represented in the smallest
5549 char guess_suffix
= 0;
5553 guess_suffix
= i
.suffix
;
5554 else if (i
.reg_operands
)
5556 /* Figure out a suffix from the last register operand specified.
5557 We can't do this properly yet, i.e. excluding special register
5558 instances, but the following works for instructions with
5559 immediates. In any case, we can't set i.suffix yet. */
5560 for (op
= i
.operands
; --op
>= 0;)
5561 if (i
.types
[op
].bitfield
.class != Reg
)
5563 else if (i
.types
[op
].bitfield
.byte
)
5565 guess_suffix
= BYTE_MNEM_SUFFIX
;
5568 else if (i
.types
[op
].bitfield
.word
)
5570 guess_suffix
= WORD_MNEM_SUFFIX
;
5573 else if (i
.types
[op
].bitfield
.dword
)
5575 guess_suffix
= LONG_MNEM_SUFFIX
;
5578 else if (i
.types
[op
].bitfield
.qword
)
5580 guess_suffix
= QWORD_MNEM_SUFFIX
;
5584 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5585 guess_suffix
= WORD_MNEM_SUFFIX
;
5587 for (op
= i
.operands
; --op
>= 0;)
5588 if (operand_type_check (i
.types
[op
], imm
))
5590 switch (i
.op
[op
].imms
->X_op
)
5593 /* If a suffix is given, this operand may be shortened. */
5594 switch (guess_suffix
)
5596 case LONG_MNEM_SUFFIX
:
5597 i
.types
[op
].bitfield
.imm32
= 1;
5598 i
.types
[op
].bitfield
.imm64
= 1;
5600 case WORD_MNEM_SUFFIX
:
5601 i
.types
[op
].bitfield
.imm16
= 1;
5602 i
.types
[op
].bitfield
.imm32
= 1;
5603 i
.types
[op
].bitfield
.imm32s
= 1;
5604 i
.types
[op
].bitfield
.imm64
= 1;
5606 case BYTE_MNEM_SUFFIX
:
5607 i
.types
[op
].bitfield
.imm8
= 1;
5608 i
.types
[op
].bitfield
.imm8s
= 1;
5609 i
.types
[op
].bitfield
.imm16
= 1;
5610 i
.types
[op
].bitfield
.imm32
= 1;
5611 i
.types
[op
].bitfield
.imm32s
= 1;
5612 i
.types
[op
].bitfield
.imm64
= 1;
5616 /* If this operand is at most 16 bits, convert it
5617 to a signed 16 bit number before trying to see
5618 whether it will fit in an even smaller size.
5619 This allows a 16-bit operand such as $0xffe0 to
5620 be recognised as within Imm8S range. */
5621 if ((i
.types
[op
].bitfield
.imm16
)
5622 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5624 i
.op
[op
].imms
->X_add_number
=
5625 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5628 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5629 if ((i
.types
[op
].bitfield
.imm32
)
5630 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5633 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5634 ^ ((offsetT
) 1 << 31))
5635 - ((offsetT
) 1 << 31));
5639 = operand_type_or (i
.types
[op
],
5640 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5642 /* We must avoid matching of Imm32 templates when 64bit
5643 only immediate is available. */
5644 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5645 i
.types
[op
].bitfield
.imm32
= 0;
5652 /* Symbols and expressions. */
5654 /* Convert symbolic operand to proper sizes for matching, but don't
5655 prevent matching a set of insns that only supports sizes other
5656 than those matching the insn suffix. */
5658 i386_operand_type mask
, allowed
;
5659 const insn_template
*t
;
5661 operand_type_set (&mask
, 0);
5662 operand_type_set (&allowed
, 0);
5664 for (t
= current_templates
->start
;
5665 t
< current_templates
->end
;
5668 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5669 allowed
= operand_type_and (allowed
, anyimm
);
5671 switch (guess_suffix
)
5673 case QWORD_MNEM_SUFFIX
:
5674 mask
.bitfield
.imm64
= 1;
5675 mask
.bitfield
.imm32s
= 1;
5677 case LONG_MNEM_SUFFIX
:
5678 mask
.bitfield
.imm32
= 1;
5680 case WORD_MNEM_SUFFIX
:
5681 mask
.bitfield
.imm16
= 1;
5683 case BYTE_MNEM_SUFFIX
:
5684 mask
.bitfield
.imm8
= 1;
5689 allowed
= operand_type_and (mask
, allowed
);
5690 if (!operand_type_all_zero (&allowed
))
5691 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5698 /* Try to use the smallest displacement type too. */
5700 optimize_disp (void)
5704 for (op
= i
.operands
; --op
>= 0;)
5705 if (operand_type_check (i
.types
[op
], disp
))
5707 if (i
.op
[op
].disps
->X_op
== O_constant
)
5709 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5711 if (i
.types
[op
].bitfield
.disp16
5712 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5714 /* If this operand is at most 16 bits, convert
5715 to a signed 16 bit number and don't use 64bit
5717 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5718 i
.types
[op
].bitfield
.disp64
= 0;
5721 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5722 if (i
.types
[op
].bitfield
.disp32
5723 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5725 /* If this operand is at most 32 bits, convert
5726 to a signed 32 bit number and don't use 64bit
5728 op_disp
&= (((offsetT
) 2 << 31) - 1);
5729 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5730 i
.types
[op
].bitfield
.disp64
= 0;
5733 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5735 i
.types
[op
].bitfield
.disp8
= 0;
5736 i
.types
[op
].bitfield
.disp16
= 0;
5737 i
.types
[op
].bitfield
.disp32
= 0;
5738 i
.types
[op
].bitfield
.disp32s
= 0;
5739 i
.types
[op
].bitfield
.disp64
= 0;
5743 else if (flag_code
== CODE_64BIT
)
5745 if (fits_in_signed_long (op_disp
))
5747 i
.types
[op
].bitfield
.disp64
= 0;
5748 i
.types
[op
].bitfield
.disp32s
= 1;
5750 if (i
.prefix
[ADDR_PREFIX
]
5751 && fits_in_unsigned_long (op_disp
))
5752 i
.types
[op
].bitfield
.disp32
= 1;
5754 if ((i
.types
[op
].bitfield
.disp32
5755 || i
.types
[op
].bitfield
.disp32s
5756 || i
.types
[op
].bitfield
.disp16
)
5757 && fits_in_disp8 (op_disp
))
5758 i
.types
[op
].bitfield
.disp8
= 1;
5760 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5761 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5763 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5764 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5765 i
.types
[op
].bitfield
.disp8
= 0;
5766 i
.types
[op
].bitfield
.disp16
= 0;
5767 i
.types
[op
].bitfield
.disp32
= 0;
5768 i
.types
[op
].bitfield
.disp32s
= 0;
5769 i
.types
[op
].bitfield
.disp64
= 0;
5772 /* We only support 64bit displacement on constants. */
5773 i
.types
[op
].bitfield
.disp64
= 0;
5777 /* Return 1 if there is a match in broadcast bytes between operand
5778 GIVEN and instruction template T. */
5781 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5783 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5784 && i
.types
[given
].bitfield
.byte
)
5785 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5786 && i
.types
[given
].bitfield
.word
)
5787 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5788 && i
.types
[given
].bitfield
.dword
)
5789 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5790 && i
.types
[given
].bitfield
.qword
));
5793 /* Check if operands are valid for the instruction. */
5796 check_VecOperands (const insn_template
*t
)
5801 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5802 any one operand are implicity requiring AVX512VL support if the actual
5803 operand size is YMMword or XMMword. Since this function runs after
5804 template matching, there's no need to check for YMMword/XMMword in
5806 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5807 if (!cpu_flags_all_zero (&cpu
)
5808 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5809 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5811 for (op
= 0; op
< t
->operands
; ++op
)
5813 if (t
->operand_types
[op
].bitfield
.zmmword
5814 && (i
.types
[op
].bitfield
.ymmword
5815 || i
.types
[op
].bitfield
.xmmword
))
5817 i
.error
= unsupported
;
5823 /* Without VSIB byte, we can't have a vector register for index. */
5824 if (!t
->opcode_modifier
.sib
5826 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5827 || i
.index_reg
->reg_type
.bitfield
.ymmword
5828 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5830 i
.error
= unsupported_vector_index_register
;
5834 /* Check if default mask is allowed. */
5835 if (t
->opcode_modifier
.nodefmask
5836 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5838 i
.error
= no_default_mask
;
5842 /* For VSIB byte, we need a vector register for index, and all vector
5843 registers must be distinct. */
5844 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5847 || !((t
->opcode_modifier
.sib
== VECSIB128
5848 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5849 || (t
->opcode_modifier
.sib
== VECSIB256
5850 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5851 || (t
->opcode_modifier
.sib
== VECSIB512
5852 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5854 i
.error
= invalid_vsib_address
;
5858 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5859 if (i
.reg_operands
== 2 && !i
.mask
)
5861 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5862 gas_assert (i
.types
[0].bitfield
.xmmword
5863 || i
.types
[0].bitfield
.ymmword
);
5864 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5865 gas_assert (i
.types
[2].bitfield
.xmmword
5866 || i
.types
[2].bitfield
.ymmword
);
5867 if (operand_check
== check_none
)
5869 if (register_number (i
.op
[0].regs
)
5870 != register_number (i
.index_reg
)
5871 && register_number (i
.op
[2].regs
)
5872 != register_number (i
.index_reg
)
5873 && register_number (i
.op
[0].regs
)
5874 != register_number (i
.op
[2].regs
))
5876 if (operand_check
== check_error
)
5878 i
.error
= invalid_vector_register_set
;
5881 as_warn (_("mask, index, and destination registers should be distinct"));
5883 else if (i
.reg_operands
== 1 && i
.mask
)
5885 if (i
.types
[1].bitfield
.class == RegSIMD
5886 && (i
.types
[1].bitfield
.xmmword
5887 || i
.types
[1].bitfield
.ymmword
5888 || i
.types
[1].bitfield
.zmmword
)
5889 && (register_number (i
.op
[1].regs
)
5890 == register_number (i
.index_reg
)))
5892 if (operand_check
== check_error
)
5894 i
.error
= invalid_vector_register_set
;
5897 if (operand_check
!= check_none
)
5898 as_warn (_("index and destination registers should be distinct"));
5903 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5905 if (t
->operand_types
[0].bitfield
.tmmword
5906 && i
.reg_operands
== 3)
5908 if (register_number (i
.op
[0].regs
)
5909 == register_number (i
.op
[1].regs
)
5910 || register_number (i
.op
[0].regs
)
5911 == register_number (i
.op
[2].regs
)
5912 || register_number (i
.op
[1].regs
)
5913 == register_number (i
.op
[2].regs
))
5915 i
.error
= invalid_tmm_register_set
;
5920 /* Check if broadcast is supported by the instruction and is applied
5921 to the memory operand. */
5924 i386_operand_type type
, overlap
;
5926 /* Check if specified broadcast is supported in this instruction,
5927 and its broadcast bytes match the memory operand. */
5928 op
= i
.broadcast
->operand
;
5929 if (!t
->opcode_modifier
.broadcast
5930 || !(i
.flags
[op
] & Operand_Mem
)
5931 || (!i
.types
[op
].bitfield
.unspecified
5932 && !match_broadcast_size (t
, op
)))
5935 i
.error
= unsupported_broadcast
;
5939 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5940 * i
.broadcast
->type
);
5941 operand_type_set (&type
, 0);
5942 switch (i
.broadcast
->bytes
)
5945 type
.bitfield
.word
= 1;
5948 type
.bitfield
.dword
= 1;
5951 type
.bitfield
.qword
= 1;
5954 type
.bitfield
.xmmword
= 1;
5957 type
.bitfield
.ymmword
= 1;
5960 type
.bitfield
.zmmword
= 1;
5966 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5967 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5968 && t
->operand_types
[op
].bitfield
.byte
5969 + t
->operand_types
[op
].bitfield
.word
5970 + t
->operand_types
[op
].bitfield
.dword
5971 + t
->operand_types
[op
].bitfield
.qword
> 1)
5973 overlap
.bitfield
.xmmword
= 0;
5974 overlap
.bitfield
.ymmword
= 0;
5975 overlap
.bitfield
.zmmword
= 0;
5977 if (operand_type_all_zero (&overlap
))
5980 if (t
->opcode_modifier
.checkregsize
)
5984 type
.bitfield
.baseindex
= 1;
5985 for (j
= 0; j
< i
.operands
; ++j
)
5988 && !operand_type_register_match(i
.types
[j
],
5989 t
->operand_types
[j
],
5991 t
->operand_types
[op
]))
5996 /* If broadcast is supported in this instruction, we need to check if
5997 operand of one-element size isn't specified without broadcast. */
5998 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6000 /* Find memory operand. */
6001 for (op
= 0; op
< i
.operands
; op
++)
6002 if (i
.flags
[op
] & Operand_Mem
)
6004 gas_assert (op
< i
.operands
);
6005 /* Check size of the memory operand. */
6006 if (match_broadcast_size (t
, op
))
6008 i
.error
= broadcast_needed
;
6013 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6015 /* Check if requested masking is supported. */
6018 switch (t
->opcode_modifier
.masking
)
6022 case MERGING_MASKING
:
6023 if (i
.mask
->zeroing
)
6026 i
.error
= unsupported_masking
;
6030 case DYNAMIC_MASKING
:
6031 /* Memory destinations allow only merging masking. */
6032 if (i
.mask
->zeroing
&& i
.mem_operands
)
6034 /* Find memory operand. */
6035 for (op
= 0; op
< i
.operands
; op
++)
6036 if (i
.flags
[op
] & Operand_Mem
)
6038 gas_assert (op
< i
.operands
);
6039 if (op
== i
.operands
- 1)
6041 i
.error
= unsupported_masking
;
6051 /* Check if masking is applied to dest operand. */
6052 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6054 i
.error
= mask_not_on_destination
;
6061 if (!t
->opcode_modifier
.sae
6062 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6064 i
.error
= unsupported_rc_sae
;
6067 /* If the instruction has several immediate operands and one of
6068 them is rounding, the rounding operand should be the last
6069 immediate operand. */
6070 if (i
.imm_operands
> 1
6071 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6073 i
.error
= rc_sae_operand_not_last_imm
;
6078 /* Check the special Imm4 cases; must be the first operand. */
6079 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6081 if (i
.op
[0].imms
->X_op
!= O_constant
6082 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6088 /* Turn off Imm<N> so that update_imm won't complain. */
6089 operand_type_set (&i
.types
[0], 0);
6092 /* Check vector Disp8 operand. */
6093 if (t
->opcode_modifier
.disp8memshift
6094 && i
.disp_encoding
!= disp_encoding_32bit
)
6097 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6098 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6099 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6102 const i386_operand_type
*type
= NULL
;
6105 for (op
= 0; op
< i
.operands
; op
++)
6106 if (i
.flags
[op
] & Operand_Mem
)
6108 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6109 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6110 else if (t
->operand_types
[op
].bitfield
.xmmword
6111 + t
->operand_types
[op
].bitfield
.ymmword
6112 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6113 type
= &t
->operand_types
[op
];
6114 else if (!i
.types
[op
].bitfield
.unspecified
)
6115 type
= &i
.types
[op
];
6117 else if (i
.types
[op
].bitfield
.class == RegSIMD
6118 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6120 if (i
.types
[op
].bitfield
.zmmword
)
6122 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6124 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6130 if (type
->bitfield
.zmmword
)
6132 else if (type
->bitfield
.ymmword
)
6134 else if (type
->bitfield
.xmmword
)
6138 /* For the check in fits_in_disp8(). */
6139 if (i
.memshift
== 0)
6143 for (op
= 0; op
< i
.operands
; op
++)
6144 if (operand_type_check (i
.types
[op
], disp
)
6145 && i
.op
[op
].disps
->X_op
== O_constant
)
6147 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6149 i
.types
[op
].bitfield
.disp8
= 1;
6152 i
.types
[op
].bitfield
.disp8
= 0;
6161 /* Check if encoding requirements are met by the instruction. */
6164 VEX_check_encoding (const insn_template
*t
)
6166 if (i
.vec_encoding
== vex_encoding_error
)
6168 i
.error
= unsupported
;
6172 if (i
.vec_encoding
== vex_encoding_evex
)
6174 /* This instruction must be encoded with EVEX prefix. */
6175 if (!is_evex_encoding (t
))
6177 i
.error
= unsupported
;
6183 if (!t
->opcode_modifier
.vex
)
6185 /* This instruction template doesn't have VEX prefix. */
6186 if (i
.vec_encoding
!= vex_encoding_default
)
6188 i
.error
= unsupported
;
6197 static const insn_template
*
6198 match_template (char mnem_suffix
)
6200 /* Points to template once we've found it. */
6201 const insn_template
*t
;
6202 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6203 i386_operand_type overlap4
;
6204 unsigned int found_reverse_match
;
6205 i386_opcode_modifier suffix_check
;
6206 i386_operand_type operand_types
[MAX_OPERANDS
];
6207 int addr_prefix_disp
;
6208 unsigned int j
, size_match
, check_register
;
6209 enum i386_error specific_error
= 0;
6211 #if MAX_OPERANDS != 5
6212 # error "MAX_OPERANDS must be 5."
6215 found_reverse_match
= 0;
6216 addr_prefix_disp
= -1;
6218 /* Prepare for mnemonic suffix check. */
6219 memset (&suffix_check
, 0, sizeof (suffix_check
));
6220 switch (mnem_suffix
)
6222 case BYTE_MNEM_SUFFIX
:
6223 suffix_check
.no_bsuf
= 1;
6225 case WORD_MNEM_SUFFIX
:
6226 suffix_check
.no_wsuf
= 1;
6228 case SHORT_MNEM_SUFFIX
:
6229 suffix_check
.no_ssuf
= 1;
6231 case LONG_MNEM_SUFFIX
:
6232 suffix_check
.no_lsuf
= 1;
6234 case QWORD_MNEM_SUFFIX
:
6235 suffix_check
.no_qsuf
= 1;
6238 /* NB: In Intel syntax, normally we can check for memory operand
6239 size when there is no mnemonic suffix. But jmp and call have
6240 2 different encodings with Dword memory operand size, one with
6241 No_ldSuf and the other without. i.suffix is set to
6242 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6243 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6244 suffix_check
.no_ldsuf
= 1;
6247 /* Must have right number of operands. */
6248 i
.error
= number_of_operands_mismatch
;
6250 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6252 addr_prefix_disp
= -1;
6253 found_reverse_match
= 0;
6255 if (i
.operands
!= t
->operands
)
6258 /* Check processor support. */
6259 i
.error
= unsupported
;
6260 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6263 /* Check Pseudo Prefix. */
6264 i
.error
= unsupported
;
6265 if (t
->opcode_modifier
.pseudovexprefix
6266 && !(i
.vec_encoding
== vex_encoding_vex
6267 || i
.vec_encoding
== vex_encoding_vex3
))
6270 /* Check AT&T mnemonic. */
6271 i
.error
= unsupported_with_intel_mnemonic
;
6272 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6275 /* Check AT&T/Intel syntax. */
6276 i
.error
= unsupported_syntax
;
6277 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6278 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6281 /* Check Intel64/AMD64 ISA. */
6285 /* Default: Don't accept Intel64. */
6286 if (t
->opcode_modifier
.isa64
== INTEL64
)
6290 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6291 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6295 /* -mintel64: Don't accept AMD64. */
6296 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6301 /* Check the suffix. */
6302 i
.error
= invalid_instruction_suffix
;
6303 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6304 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6305 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6306 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6307 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6308 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6311 size_match
= operand_size_match (t
);
6315 /* This is intentionally not
6317 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6319 as the case of a missing * on the operand is accepted (perhaps with
6320 a warning, issued further down). */
6321 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6323 i
.error
= operand_type_mismatch
;
6327 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6328 operand_types
[j
] = t
->operand_types
[j
];
6330 /* In general, don't allow
6331 - 64-bit operands outside of 64-bit mode,
6332 - 32-bit operands on pre-386. */
6333 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6334 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6335 && flag_code
!= CODE_64BIT
6336 && !(t
->base_opcode
== 0xfc7
6337 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
6338 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6339 || (i
.suffix
== LONG_MNEM_SUFFIX
6340 && !cpu_arch_flags
.bitfield
.cpui386
))
6342 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6343 && !intel_float_operand (t
->name
))
6344 : intel_float_operand (t
->name
) != 2)
6345 && (t
->operands
== i
.imm_operands
6346 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6347 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6348 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6349 || (operand_types
[j
].bitfield
.class != RegMMX
6350 && operand_types
[j
].bitfield
.class != RegSIMD
6351 && operand_types
[j
].bitfield
.class != RegMask
))
6352 && !t
->opcode_modifier
.sib
)
6355 /* Do not verify operands when there are none. */
6358 if (VEX_check_encoding (t
))
6360 specific_error
= i
.error
;
6364 /* We've found a match; break out of loop. */
6368 if (!t
->opcode_modifier
.jump
6369 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6371 /* There should be only one Disp operand. */
6372 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6373 if (operand_type_check (operand_types
[j
], disp
))
6375 if (j
< MAX_OPERANDS
)
6377 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6379 addr_prefix_disp
= j
;
6381 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6382 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6386 override
= !override
;
6389 if (operand_types
[j
].bitfield
.disp32
6390 && operand_types
[j
].bitfield
.disp16
)
6392 operand_types
[j
].bitfield
.disp16
= override
;
6393 operand_types
[j
].bitfield
.disp32
= !override
;
6395 operand_types
[j
].bitfield
.disp32s
= 0;
6396 operand_types
[j
].bitfield
.disp64
= 0;
6400 if (operand_types
[j
].bitfield
.disp32s
6401 || operand_types
[j
].bitfield
.disp64
)
6403 operand_types
[j
].bitfield
.disp64
&= !override
;
6404 operand_types
[j
].bitfield
.disp32s
&= !override
;
6405 operand_types
[j
].bitfield
.disp32
= override
;
6407 operand_types
[j
].bitfield
.disp16
= 0;
6413 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6414 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6417 /* We check register size if needed. */
6418 if (t
->opcode_modifier
.checkregsize
)
6420 check_register
= (1 << t
->operands
) - 1;
6422 check_register
&= ~(1 << i
.broadcast
->operand
);
6427 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6428 switch (t
->operands
)
6431 if (!operand_type_match (overlap0
, i
.types
[0]))
6435 /* xchg %eax, %eax is a special case. It is an alias for nop
6436 only in 32bit mode and we can use opcode 0x90. In 64bit
6437 mode, we can't use 0x90 for xchg %eax, %eax since it should
6438 zero-extend %eax to %rax. */
6439 if (flag_code
== CODE_64BIT
6440 && t
->base_opcode
== 0x90
6441 && i
.types
[0].bitfield
.instance
== Accum
6442 && i
.types
[0].bitfield
.dword
6443 && i
.types
[1].bitfield
.instance
== Accum
6444 && i
.types
[1].bitfield
.dword
)
6446 /* xrelease mov %eax, <disp> is another special case. It must not
6447 match the accumulator-only encoding of mov. */
6448 if (flag_code
!= CODE_64BIT
6450 && t
->base_opcode
== 0xa0
6451 && i
.types
[0].bitfield
.instance
== Accum
6452 && (i
.flags
[1] & Operand_Mem
))
6457 if (!(size_match
& MATCH_STRAIGHT
))
6459 /* Reverse direction of operands if swapping is possible in the first
6460 place (operands need to be symmetric) and
6461 - the load form is requested, and the template is a store form,
6462 - the store form is requested, and the template is a load form,
6463 - the non-default (swapped) form is requested. */
6464 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6465 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6466 && !operand_type_all_zero (&overlap1
))
6467 switch (i
.dir_encoding
)
6469 case dir_encoding_load
:
6470 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6471 || t
->opcode_modifier
.regmem
)
6475 case dir_encoding_store
:
6476 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6477 && !t
->opcode_modifier
.regmem
)
6481 case dir_encoding_swap
:
6484 case dir_encoding_default
:
6487 /* If we want store form, we skip the current load. */
6488 if ((i
.dir_encoding
== dir_encoding_store
6489 || i
.dir_encoding
== dir_encoding_swap
)
6490 && i
.mem_operands
== 0
6491 && t
->opcode_modifier
.load
)
6496 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6497 if (!operand_type_match (overlap0
, i
.types
[0])
6498 || !operand_type_match (overlap1
, i
.types
[1])
6499 || ((check_register
& 3) == 3
6500 && !operand_type_register_match (i
.types
[0],
6505 /* Check if other direction is valid ... */
6506 if (!t
->opcode_modifier
.d
)
6510 if (!(size_match
& MATCH_REVERSE
))
6512 /* Try reversing direction of operands. */
6513 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6514 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6515 if (!operand_type_match (overlap0
, i
.types
[0])
6516 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6518 && !operand_type_register_match (i
.types
[0],
6519 operand_types
[i
.operands
- 1],
6520 i
.types
[i
.operands
- 1],
6523 /* Does not match either direction. */
6526 /* found_reverse_match holds which of D or FloatR
6528 if (!t
->opcode_modifier
.d
)
6529 found_reverse_match
= 0;
6530 else if (operand_types
[0].bitfield
.tbyte
)
6531 found_reverse_match
= Opcode_FloatD
;
6532 else if (operand_types
[0].bitfield
.xmmword
6533 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6534 || operand_types
[0].bitfield
.class == RegMMX
6535 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6536 || is_any_vex_encoding(t
))
6537 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6538 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6540 found_reverse_match
= Opcode_D
;
6541 if (t
->opcode_modifier
.floatr
)
6542 found_reverse_match
|= Opcode_FloatR
;
6546 /* Found a forward 2 operand match here. */
6547 switch (t
->operands
)
6550 overlap4
= operand_type_and (i
.types
[4],
6554 overlap3
= operand_type_and (i
.types
[3],
6558 overlap2
= operand_type_and (i
.types
[2],
6563 switch (t
->operands
)
6566 if (!operand_type_match (overlap4
, i
.types
[4])
6567 || !operand_type_register_match (i
.types
[3],
6574 if (!operand_type_match (overlap3
, i
.types
[3])
6575 || ((check_register
& 0xa) == 0xa
6576 && !operand_type_register_match (i
.types
[1],
6580 || ((check_register
& 0xc) == 0xc
6581 && !operand_type_register_match (i
.types
[2],
6588 /* Here we make use of the fact that there are no
6589 reverse match 3 operand instructions. */
6590 if (!operand_type_match (overlap2
, i
.types
[2])
6591 || ((check_register
& 5) == 5
6592 && !operand_type_register_match (i
.types
[0],
6596 || ((check_register
& 6) == 6
6597 && !operand_type_register_match (i
.types
[1],
6605 /* Found either forward/reverse 2, 3 or 4 operand match here:
6606 slip through to break. */
6609 /* Check if vector operands are valid. */
6610 if (check_VecOperands (t
))
6612 specific_error
= i
.error
;
6616 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6617 if (VEX_check_encoding (t
))
6619 specific_error
= i
.error
;
6623 /* We've found a match; break out of loop. */
6627 if (t
== current_templates
->end
)
6629 /* We found no match. */
6630 const char *err_msg
;
6631 switch (specific_error
? specific_error
: i
.error
)
6635 case operand_size_mismatch
:
6636 err_msg
= _("operand size mismatch");
6638 case operand_type_mismatch
:
6639 err_msg
= _("operand type mismatch");
6641 case register_type_mismatch
:
6642 err_msg
= _("register type mismatch");
6644 case number_of_operands_mismatch
:
6645 err_msg
= _("number of operands mismatch");
6647 case invalid_instruction_suffix
:
6648 err_msg
= _("invalid instruction suffix");
6651 err_msg
= _("constant doesn't fit in 4 bits");
6653 case unsupported_with_intel_mnemonic
:
6654 err_msg
= _("unsupported with Intel mnemonic");
6656 case unsupported_syntax
:
6657 err_msg
= _("unsupported syntax");
6660 as_bad (_("unsupported instruction `%s'"),
6661 current_templates
->start
->name
);
6663 case invalid_sib_address
:
6664 err_msg
= _("invalid SIB address");
6666 case invalid_vsib_address
:
6667 err_msg
= _("invalid VSIB address");
6669 case invalid_vector_register_set
:
6670 err_msg
= _("mask, index, and destination registers must be distinct");
6672 case invalid_tmm_register_set
:
6673 err_msg
= _("all tmm registers must be distinct");
6675 case unsupported_vector_index_register
:
6676 err_msg
= _("unsupported vector index register");
6678 case unsupported_broadcast
:
6679 err_msg
= _("unsupported broadcast");
6681 case broadcast_needed
:
6682 err_msg
= _("broadcast is needed for operand of such type");
6684 case unsupported_masking
:
6685 err_msg
= _("unsupported masking");
6687 case mask_not_on_destination
:
6688 err_msg
= _("mask not on destination operand");
6690 case no_default_mask
:
6691 err_msg
= _("default mask isn't allowed");
6693 case unsupported_rc_sae
:
6694 err_msg
= _("unsupported static rounding/sae");
6696 case rc_sae_operand_not_last_imm
:
6698 err_msg
= _("RC/SAE operand must precede immediate operands");
6700 err_msg
= _("RC/SAE operand must follow immediate operands");
6702 case invalid_register_operand
:
6703 err_msg
= _("invalid register operand");
6706 as_bad (_("%s for `%s'"), err_msg
,
6707 current_templates
->start
->name
);
6711 if (!quiet_warnings
)
6714 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6715 as_warn (_("indirect %s without `*'"), t
->name
);
6717 if (t
->opcode_modifier
.isprefix
6718 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6720 /* Warn them that a data or address size prefix doesn't
6721 affect assembly of the next line of code. */
6722 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6726 /* Copy the template we found. */
6729 if (addr_prefix_disp
!= -1)
6730 i
.tm
.operand_types
[addr_prefix_disp
]
6731 = operand_types
[addr_prefix_disp
];
6733 if (found_reverse_match
)
6735 /* If we found a reverse match we must alter the opcode direction
6736 bit and clear/flip the regmem modifier one. found_reverse_match
6737 holds bits to change (different for int & float insns). */
6739 i
.tm
.base_opcode
^= found_reverse_match
;
6741 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6742 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6744 /* Certain SIMD insns have their load forms specified in the opcode
6745 table, and hence we need to _set_ RegMem instead of clearing it.
6746 We need to avoid setting the bit though on insns like KMOVW. */
6747 i
.tm
.opcode_modifier
.regmem
6748 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6749 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6750 && !i
.tm
.opcode_modifier
.regmem
;
6759 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6760 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6762 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6764 as_bad (_("`%s' operand %u must use `%ses' segment"),
6766 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6771 /* There's only ever one segment override allowed per instruction.
6772 This instruction possibly has a legal segment override on the
6773 second operand, so copy the segment to where non-string
6774 instructions store it, allowing common code. */
6775 i
.seg
[op
] = i
.seg
[1];
6781 process_suffix (void)
6783 bfd_boolean is_crc32
= FALSE
;
6785 /* If matched instruction specifies an explicit instruction mnemonic
6787 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6788 i
.suffix
= WORD_MNEM_SUFFIX
;
6789 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6790 i
.suffix
= LONG_MNEM_SUFFIX
;
6791 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6792 i
.suffix
= QWORD_MNEM_SUFFIX
;
6793 else if (i
.reg_operands
6794 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6795 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6797 unsigned int numop
= i
.operands
;
6799 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6800 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6802 /* movsx/movzx want only their source operand considered here, for the
6803 ambiguity checking below. The suffix will be replaced afterwards
6804 to represent the destination (register). */
6805 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6806 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6809 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6810 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6813 /* If there's no instruction mnemonic suffix we try to invent one
6814 based on GPR operands. */
6817 /* We take i.suffix from the last register operand specified,
6818 Destination register type is more significant than source
6819 register type. crc32 in SSE4.2 prefers source register
6821 unsigned int op
= is_crc32
? 1 : i
.operands
;
6824 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6825 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6827 if (i
.types
[op
].bitfield
.class != Reg
)
6829 if (i
.types
[op
].bitfield
.byte
)
6830 i
.suffix
= BYTE_MNEM_SUFFIX
;
6831 else if (i
.types
[op
].bitfield
.word
)
6832 i
.suffix
= WORD_MNEM_SUFFIX
;
6833 else if (i
.types
[op
].bitfield
.dword
)
6834 i
.suffix
= LONG_MNEM_SUFFIX
;
6835 else if (i
.types
[op
].bitfield
.qword
)
6836 i
.suffix
= QWORD_MNEM_SUFFIX
;
6842 /* As an exception, movsx/movzx silently default to a byte source
6844 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6845 && !i
.suffix
&& !intel_syntax
)
6846 i
.suffix
= BYTE_MNEM_SUFFIX
;
6848 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6851 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6852 && i
.tm
.opcode_modifier
.no_bsuf
)
6854 else if (!check_byte_reg ())
6857 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6860 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6861 && i
.tm
.opcode_modifier
.no_lsuf
6862 && !i
.tm
.opcode_modifier
.todword
6863 && !i
.tm
.opcode_modifier
.toqword
)
6865 else if (!check_long_reg ())
6868 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6871 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6872 && i
.tm
.opcode_modifier
.no_qsuf
6873 && !i
.tm
.opcode_modifier
.todword
6874 && !i
.tm
.opcode_modifier
.toqword
)
6876 else if (!check_qword_reg ())
6879 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6882 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6883 && i
.tm
.opcode_modifier
.no_wsuf
)
6885 else if (!check_word_reg ())
6888 else if (intel_syntax
6889 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6890 /* Do nothing if the instruction is going to ignore the prefix. */
6895 /* Undo the movsx/movzx change done above. */
6898 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6901 i
.suffix
= stackop_size
;
6902 if (stackop_size
== LONG_MNEM_SUFFIX
)
6904 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6905 .code16gcc directive to support 16-bit mode with
6906 32-bit address. For IRET without a suffix, generate
6907 16-bit IRET (opcode 0xcf) to return from an interrupt
6909 if (i
.tm
.base_opcode
== 0xcf)
6911 i
.suffix
= WORD_MNEM_SUFFIX
;
6912 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6914 /* Warn about changed behavior for segment register push/pop. */
6915 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6916 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6921 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6922 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6923 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6924 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6925 && i
.tm
.extension_opcode
<= 3)))
6930 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6932 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6933 || i
.tm
.opcode_modifier
.no_lsuf
)
6934 i
.suffix
= QWORD_MNEM_SUFFIX
;
6939 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6940 i
.suffix
= LONG_MNEM_SUFFIX
;
6943 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6944 i
.suffix
= WORD_MNEM_SUFFIX
;
6950 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6951 /* Also cover lret/retf/iret in 64-bit mode. */
6952 || (flag_code
== CODE_64BIT
6953 && !i
.tm
.opcode_modifier
.no_lsuf
6954 && !i
.tm
.opcode_modifier
.no_qsuf
))
6955 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6956 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6957 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6958 /* Accept FLDENV et al without suffix. */
6959 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6961 unsigned int suffixes
, evex
= 0;
6963 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6964 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6966 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6968 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6970 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6972 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6975 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6976 also suitable for AT&T syntax mode, it was requested that this be
6977 restricted to just Intel syntax. */
6978 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6982 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6984 if (is_evex_encoding (&i
.tm
)
6985 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6987 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6988 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6989 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6990 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6991 if (!i
.tm
.opcode_modifier
.evex
6992 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6993 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6996 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6997 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6998 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7001 /* Any properly sized operand disambiguates the insn. */
7002 if (i
.types
[op
].bitfield
.xmmword
7003 || i
.types
[op
].bitfield
.ymmword
7004 || i
.types
[op
].bitfield
.zmmword
)
7006 suffixes
&= ~(7 << 6);
7011 if ((i
.flags
[op
] & Operand_Mem
)
7012 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7014 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7016 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7018 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7020 if (is_evex_encoding (&i
.tm
))
7026 /* Are multiple suffixes / operand sizes allowed? */
7027 if (suffixes
& (suffixes
- 1))
7030 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7031 || operand_check
== check_error
))
7033 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7036 if (operand_check
== check_error
)
7038 as_bad (_("no instruction mnemonic suffix given and "
7039 "no register operands; can't size `%s'"), i
.tm
.name
);
7042 if (operand_check
== check_warning
)
7043 as_warn (_("%s; using default for `%s'"),
7045 ? _("ambiguous operand size")
7046 : _("no instruction mnemonic suffix given and "
7047 "no register operands"),
7050 if (i
.tm
.opcode_modifier
.floatmf
)
7051 i
.suffix
= SHORT_MNEM_SUFFIX
;
7052 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7053 || (i
.tm
.base_opcode
== 0x63
7054 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7055 /* handled below */;
7057 i
.tm
.opcode_modifier
.evex
= evex
;
7058 else if (flag_code
== CODE_16BIT
)
7059 i
.suffix
= WORD_MNEM_SUFFIX
;
7060 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7061 i
.suffix
= LONG_MNEM_SUFFIX
;
7063 i
.suffix
= QWORD_MNEM_SUFFIX
;
7067 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7068 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7070 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7071 In AT&T syntax, if there is no suffix (warned about above), the default
7072 will be byte extension. */
7073 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7074 i
.tm
.base_opcode
|= 1;
7076 /* For further processing, the suffix should represent the destination
7077 (register). This is already the case when one was used with
7078 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7079 no suffix to begin with. */
7080 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7082 if (i
.types
[1].bitfield
.word
)
7083 i
.suffix
= WORD_MNEM_SUFFIX
;
7084 else if (i
.types
[1].bitfield
.qword
)
7085 i
.suffix
= QWORD_MNEM_SUFFIX
;
7087 i
.suffix
= LONG_MNEM_SUFFIX
;
7089 i
.tm
.opcode_modifier
.w
= 0;
7093 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7094 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7095 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7097 /* Change the opcode based on the operand size given by i.suffix. */
7100 /* Size floating point instruction. */
7101 case LONG_MNEM_SUFFIX
:
7102 if (i
.tm
.opcode_modifier
.floatmf
)
7104 i
.tm
.base_opcode
^= 4;
7108 case WORD_MNEM_SUFFIX
:
7109 case QWORD_MNEM_SUFFIX
:
7110 /* It's not a byte, select word/dword operation. */
7111 if (i
.tm
.opcode_modifier
.w
)
7114 i
.tm
.base_opcode
|= 8;
7116 i
.tm
.base_opcode
|= 1;
7119 case SHORT_MNEM_SUFFIX
:
7120 /* Now select between word & dword operations via the operand
7121 size prefix, except for instructions that will ignore this
7123 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7124 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7125 && !i
.tm
.opcode_modifier
.floatmf
7126 && !is_any_vex_encoding (&i
.tm
)
7127 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7128 || (flag_code
== CODE_64BIT
7129 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7131 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7133 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7134 prefix
= ADDR_PREFIX_OPCODE
;
7136 if (!add_prefix (prefix
))
7140 /* Set mode64 for an operand. */
7141 if (i
.suffix
== QWORD_MNEM_SUFFIX
7142 && flag_code
== CODE_64BIT
7143 && !i
.tm
.opcode_modifier
.norex64
7144 && !i
.tm
.opcode_modifier
.vexw
7145 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7147 && ! (i
.operands
== 2
7148 && i
.tm
.base_opcode
== 0x90
7149 && i
.tm
.extension_opcode
== None
7150 && i
.types
[0].bitfield
.instance
== Accum
7151 && i
.types
[0].bitfield
.qword
7152 && i
.types
[1].bitfield
.instance
== Accum
7153 && i
.types
[1].bitfield
.qword
))
7159 /* Select word/dword/qword operation with explicit data sizing prefix
7160 when there are no suitable register operands. */
7161 if (i
.tm
.opcode_modifier
.w
7162 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7164 || (i
.reg_operands
== 1
7166 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7168 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7169 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7172 i
.tm
.base_opcode
|= 1;
7176 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7178 gas_assert (!i
.suffix
);
7179 gas_assert (i
.reg_operands
);
7181 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7184 /* The address size override prefix changes the size of the
7186 if (flag_code
== CODE_64BIT
7187 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7189 as_bad (_("16-bit addressing unavailable for `%s'"),
7194 if ((flag_code
== CODE_32BIT
7195 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7196 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7197 && !add_prefix (ADDR_PREFIX_OPCODE
))
7202 /* Check invalid register operand when the address size override
7203 prefix changes the size of register operands. */
7205 enum { need_word
, need_dword
, need_qword
} need
;
7207 /* Check the register operand for the address size prefix if
7208 the memory operand has no real registers, like symbol, DISP
7210 if (i
.mem_operands
== 1
7211 && i
.reg_operands
== 1
7213 && i
.types
[1].bitfield
.class == Reg
7214 && (flag_code
== CODE_32BIT
7215 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7216 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7217 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7219 && i
.base_reg
->reg_num
== RegIP
7220 && i
.base_reg
->reg_type
.bitfield
.qword
))
7221 && !add_prefix (ADDR_PREFIX_OPCODE
))
7224 if (flag_code
== CODE_32BIT
)
7225 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7226 else if (i
.prefix
[ADDR_PREFIX
])
7229 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7231 for (op
= 0; op
< i
.operands
; op
++)
7233 if (i
.types
[op
].bitfield
.class != Reg
)
7239 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7243 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7247 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7252 as_bad (_("invalid register operand size for `%s'"),
7263 check_byte_reg (void)
7267 for (op
= i
.operands
; --op
>= 0;)
7269 /* Skip non-register operands. */
7270 if (i
.types
[op
].bitfield
.class != Reg
)
7273 /* If this is an eight bit register, it's OK. If it's the 16 or
7274 32 bit version of an eight bit register, we will just use the
7275 low portion, and that's OK too. */
7276 if (i
.types
[op
].bitfield
.byte
)
7279 /* I/O port address operands are OK too. */
7280 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7281 && i
.tm
.operand_types
[op
].bitfield
.word
)
7284 /* crc32 only wants its source operand checked here. */
7285 if (i
.tm
.base_opcode
== 0xf38f0
7286 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7290 /* Any other register is bad. */
7291 as_bad (_("`%s%s' not allowed with `%s%c'"),
7292 register_prefix
, i
.op
[op
].regs
->reg_name
,
7293 i
.tm
.name
, i
.suffix
);
7300 check_long_reg (void)
7304 for (op
= i
.operands
; --op
>= 0;)
7305 /* Skip non-register operands. */
7306 if (i
.types
[op
].bitfield
.class != Reg
)
7308 /* Reject eight bit registers, except where the template requires
7309 them. (eg. movzb) */
7310 else if (i
.types
[op
].bitfield
.byte
7311 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7312 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7313 && (i
.tm
.operand_types
[op
].bitfield
.word
7314 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7316 as_bad (_("`%s%s' not allowed with `%s%c'"),
7318 i
.op
[op
].regs
->reg_name
,
7323 /* Error if the e prefix on a general reg is missing. */
7324 else if (i
.types
[op
].bitfield
.word
7325 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7326 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7327 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7329 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7330 register_prefix
, i
.op
[op
].regs
->reg_name
,
7334 /* Warn if the r prefix on a general reg is present. */
7335 else if (i
.types
[op
].bitfield
.qword
7336 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7337 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7338 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7341 && i
.tm
.opcode_modifier
.toqword
7342 && i
.types
[0].bitfield
.class != RegSIMD
)
7344 /* Convert to QWORD. We want REX byte. */
7345 i
.suffix
= QWORD_MNEM_SUFFIX
;
7349 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7350 register_prefix
, i
.op
[op
].regs
->reg_name
,
7359 check_qword_reg (void)
7363 for (op
= i
.operands
; --op
>= 0; )
7364 /* Skip non-register operands. */
7365 if (i
.types
[op
].bitfield
.class != Reg
)
7367 /* Reject eight bit registers, except where the template requires
7368 them. (eg. movzb) */
7369 else if (i
.types
[op
].bitfield
.byte
7370 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7371 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7372 && (i
.tm
.operand_types
[op
].bitfield
.word
7373 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7375 as_bad (_("`%s%s' not allowed with `%s%c'"),
7377 i
.op
[op
].regs
->reg_name
,
7382 /* Warn if the r prefix on a general reg is missing. */
7383 else if ((i
.types
[op
].bitfield
.word
7384 || i
.types
[op
].bitfield
.dword
)
7385 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7386 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7387 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7389 /* Prohibit these changes in the 64bit mode, since the
7390 lowering is more complicated. */
7392 && i
.tm
.opcode_modifier
.todword
7393 && i
.types
[0].bitfield
.class != RegSIMD
)
7395 /* Convert to DWORD. We don't want REX byte. */
7396 i
.suffix
= LONG_MNEM_SUFFIX
;
7400 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7401 register_prefix
, i
.op
[op
].regs
->reg_name
,
7410 check_word_reg (void)
7413 for (op
= i
.operands
; --op
>= 0;)
7414 /* Skip non-register operands. */
7415 if (i
.types
[op
].bitfield
.class != Reg
)
7417 /* Reject eight bit registers, except where the template requires
7418 them. (eg. movzb) */
7419 else if (i
.types
[op
].bitfield
.byte
7420 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7421 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7422 && (i
.tm
.operand_types
[op
].bitfield
.word
7423 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7425 as_bad (_("`%s%s' not allowed with `%s%c'"),
7427 i
.op
[op
].regs
->reg_name
,
7432 /* Error if the e or r prefix on a general reg is present. */
7433 else if ((i
.types
[op
].bitfield
.dword
7434 || i
.types
[op
].bitfield
.qword
)
7435 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7436 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7437 && i
.tm
.operand_types
[op
].bitfield
.word
)
7439 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7440 register_prefix
, i
.op
[op
].regs
->reg_name
,
7448 update_imm (unsigned int j
)
7450 i386_operand_type overlap
= i
.types
[j
];
7451 if ((overlap
.bitfield
.imm8
7452 || overlap
.bitfield
.imm8s
7453 || overlap
.bitfield
.imm16
7454 || overlap
.bitfield
.imm32
7455 || overlap
.bitfield
.imm32s
7456 || overlap
.bitfield
.imm64
)
7457 && !operand_type_equal (&overlap
, &imm8
)
7458 && !operand_type_equal (&overlap
, &imm8s
)
7459 && !operand_type_equal (&overlap
, &imm16
)
7460 && !operand_type_equal (&overlap
, &imm32
)
7461 && !operand_type_equal (&overlap
, &imm32s
)
7462 && !operand_type_equal (&overlap
, &imm64
))
7466 i386_operand_type temp
;
7468 operand_type_set (&temp
, 0);
7469 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7471 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7472 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7474 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7475 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7476 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7478 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7479 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7482 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7485 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7486 || operand_type_equal (&overlap
, &imm16_32
)
7487 || operand_type_equal (&overlap
, &imm16_32s
))
7489 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7494 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7495 overlap
= operand_type_and (overlap
, imm32s
);
7496 else if (i
.prefix
[DATA_PREFIX
])
7497 overlap
= operand_type_and (overlap
,
7498 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7499 if (!operand_type_equal (&overlap
, &imm8
)
7500 && !operand_type_equal (&overlap
, &imm8s
)
7501 && !operand_type_equal (&overlap
, &imm16
)
7502 && !operand_type_equal (&overlap
, &imm32
)
7503 && !operand_type_equal (&overlap
, &imm32s
)
7504 && !operand_type_equal (&overlap
, &imm64
))
7506 as_bad (_("no instruction mnemonic suffix given; "
7507 "can't determine immediate size"));
7511 i
.types
[j
] = overlap
;
7521 /* Update the first 2 immediate operands. */
7522 n
= i
.operands
> 2 ? 2 : i
.operands
;
7525 for (j
= 0; j
< n
; j
++)
7526 if (update_imm (j
) == 0)
7529 /* The 3rd operand can't be immediate operand. */
7530 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7537 process_operands (void)
7539 /* Default segment register this instruction will use for memory
7540 accesses. 0 means unknown. This is only for optimizing out
7541 unnecessary segment overrides. */
7542 const seg_entry
*default_seg
= 0;
7544 if (i
.tm
.opcode_modifier
.sse2avx
)
7546 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7548 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7549 i
.prefix
[REX_PREFIX
] = 0;
7552 /* ImmExt should be processed after SSE2AVX. */
7553 else if (i
.tm
.opcode_modifier
.immext
)
7556 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7558 unsigned int dupl
= i
.operands
;
7559 unsigned int dest
= dupl
- 1;
7562 /* The destination must be an xmm register. */
7563 gas_assert (i
.reg_operands
7564 && MAX_OPERANDS
> dupl
7565 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7567 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7568 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7570 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7572 /* Keep xmm0 for instructions with VEX prefix and 3
7574 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7575 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7580 /* We remove the first xmm0 and keep the number of
7581 operands unchanged, which in fact duplicates the
7583 for (j
= 1; j
< i
.operands
; j
++)
7585 i
.op
[j
- 1] = i
.op
[j
];
7586 i
.types
[j
- 1] = i
.types
[j
];
7587 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7588 i
.flags
[j
- 1] = i
.flags
[j
];
7592 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7594 gas_assert ((MAX_OPERANDS
- 1) > dupl
7595 && (i
.tm
.opcode_modifier
.vexsources
7598 /* Add the implicit xmm0 for instructions with VEX prefix
7600 for (j
= i
.operands
; j
> 0; j
--)
7602 i
.op
[j
] = i
.op
[j
- 1];
7603 i
.types
[j
] = i
.types
[j
- 1];
7604 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7605 i
.flags
[j
] = i
.flags
[j
- 1];
7608 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7609 i
.types
[0] = regxmm
;
7610 i
.tm
.operand_types
[0] = regxmm
;
7613 i
.reg_operands
+= 2;
7618 i
.op
[dupl
] = i
.op
[dest
];
7619 i
.types
[dupl
] = i
.types
[dest
];
7620 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7621 i
.flags
[dupl
] = i
.flags
[dest
];
7630 i
.op
[dupl
] = i
.op
[dest
];
7631 i
.types
[dupl
] = i
.types
[dest
];
7632 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7633 i
.flags
[dupl
] = i
.flags
[dest
];
7636 if (i
.tm
.opcode_modifier
.immext
)
7639 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7640 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7644 for (j
= 1; j
< i
.operands
; j
++)
7646 i
.op
[j
- 1] = i
.op
[j
];
7647 i
.types
[j
- 1] = i
.types
[j
];
7649 /* We need to adjust fields in i.tm since they are used by
7650 build_modrm_byte. */
7651 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7653 i
.flags
[j
- 1] = i
.flags
[j
];
7660 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7662 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7664 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7665 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7666 regnum
= register_number (i
.op
[1].regs
);
7667 first_reg_in_group
= regnum
& ~3;
7668 last_reg_in_group
= first_reg_in_group
+ 3;
7669 if (regnum
!= first_reg_in_group
)
7670 as_warn (_("source register `%s%s' implicitly denotes"
7671 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7672 register_prefix
, i
.op
[1].regs
->reg_name
,
7673 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7674 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7677 else if (i
.tm
.opcode_modifier
.regkludge
)
7679 /* The imul $imm, %reg instruction is converted into
7680 imul $imm, %reg, %reg, and the clr %reg instruction
7681 is converted into xor %reg, %reg. */
7683 unsigned int first_reg_op
;
7685 if (operand_type_check (i
.types
[0], reg
))
7689 /* Pretend we saw the extra register operand. */
7690 gas_assert (i
.reg_operands
== 1
7691 && i
.op
[first_reg_op
+ 1].regs
== 0);
7692 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7693 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7698 if (i
.tm
.opcode_modifier
.modrm
)
7700 /* The opcode is completed (modulo i.tm.extension_opcode which
7701 must be put into the modrm byte). Now, we make the modrm and
7702 index base bytes based on all the info we've collected. */
7704 default_seg
= build_modrm_byte ();
7706 else if (i
.types
[0].bitfield
.class == SReg
)
7708 if (flag_code
!= CODE_64BIT
7709 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7710 && i
.op
[0].regs
->reg_num
== 1
7711 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7712 && i
.op
[0].regs
->reg_num
< 4)
7714 as_bad (_("you can't `%s %s%s'"),
7715 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7718 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7720 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7721 i
.tm
.opcode_length
= 2;
7723 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7725 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7729 else if (i
.tm
.opcode_modifier
.isstring
)
7731 /* For the string instructions that allow a segment override
7732 on one of their operands, the default segment is ds. */
7735 else if (i
.short_form
)
7737 /* The register or float register operand is in operand
7739 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7741 /* Register goes in low 3 bits of opcode. */
7742 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7743 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7745 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7747 /* Warn about some common errors, but press on regardless.
7748 The first case can be generated by gcc (<= 2.8.1). */
7749 if (i
.operands
== 2)
7751 /* Reversed arguments on faddp, fsubp, etc. */
7752 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7753 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7754 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7758 /* Extraneous `l' suffix on fp insn. */
7759 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7760 register_prefix
, i
.op
[0].regs
->reg_name
);
7765 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7766 && i
.tm
.base_opcode
== 0x8d /* lea */
7767 && !is_any_vex_encoding(&i
.tm
))
7769 if (!quiet_warnings
)
7770 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7774 i
.prefix
[SEG_PREFIX
] = 0;
7778 /* If a segment was explicitly specified, and the specified segment
7779 is neither the default nor the one already recorded from a prefix,
7780 use an opcode prefix to select it. If we never figured out what
7781 the default segment is, then default_seg will be zero at this
7782 point, and the specified segment prefix will always be used. */
7784 && i
.seg
[0] != default_seg
7785 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7787 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7793 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7794 bfd_boolean do_sse2avx
)
7796 if (r
->reg_flags
& RegRex
)
7798 if (i
.rex
& rex_bit
)
7799 as_bad (_("same type of prefix used twice"));
7802 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7804 gas_assert (i
.vex
.register_specifier
== r
);
7805 i
.vex
.register_specifier
+= 8;
7808 if (r
->reg_flags
& RegVRex
)
7812 static const seg_entry
*
7813 build_modrm_byte (void)
7815 const seg_entry
*default_seg
= 0;
7816 unsigned int source
, dest
;
7819 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7822 unsigned int nds
, reg_slot
;
7825 dest
= i
.operands
- 1;
7828 /* There are 2 kinds of instructions:
7829 1. 5 operands: 4 register operands or 3 register operands
7830 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7831 VexW0 or VexW1. The destination must be either XMM, YMM or
7833 2. 4 operands: 4 register operands or 3 register operands
7834 plus 1 memory operand, with VexXDS. */
7835 gas_assert ((i
.reg_operands
== 4
7836 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7837 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7838 && i
.tm
.opcode_modifier
.vexw
7839 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7841 /* If VexW1 is set, the first non-immediate operand is the source and
7842 the second non-immediate one is encoded in the immediate operand. */
7843 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7845 source
= i
.imm_operands
;
7846 reg_slot
= i
.imm_operands
+ 1;
7850 source
= i
.imm_operands
+ 1;
7851 reg_slot
= i
.imm_operands
;
7854 if (i
.imm_operands
== 0)
7856 /* When there is no immediate operand, generate an 8bit
7857 immediate operand to encode the first operand. */
7858 exp
= &im_expressions
[i
.imm_operands
++];
7859 i
.op
[i
.operands
].imms
= exp
;
7860 i
.types
[i
.operands
] = imm8
;
7863 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7864 exp
->X_op
= O_constant
;
7865 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7866 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7870 gas_assert (i
.imm_operands
== 1);
7871 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7872 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7874 /* Turn on Imm8 again so that output_imm will generate it. */
7875 i
.types
[0].bitfield
.imm8
= 1;
7877 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7878 i
.op
[0].imms
->X_add_number
7879 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7880 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7883 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7884 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7889 /* i.reg_operands MUST be the number of real register operands;
7890 implicit registers do not count. If there are 3 register
7891 operands, it must be a instruction with VexNDS. For a
7892 instruction with VexNDD, the destination register is encoded
7893 in VEX prefix. If there are 4 register operands, it must be
7894 a instruction with VEX prefix and 3 sources. */
7895 if (i
.mem_operands
== 0
7896 && ((i
.reg_operands
== 2
7897 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7898 || (i
.reg_operands
== 3
7899 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7900 || (i
.reg_operands
== 4 && vex_3_sources
)))
7908 /* When there are 3 operands, one of them may be immediate,
7909 which may be the first or the last operand. Otherwise,
7910 the first operand must be shift count register (cl) or it
7911 is an instruction with VexNDS. */
7912 gas_assert (i
.imm_operands
== 1
7913 || (i
.imm_operands
== 0
7914 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7915 || (i
.types
[0].bitfield
.instance
== RegC
7916 && i
.types
[0].bitfield
.byte
))));
7917 if (operand_type_check (i
.types
[0], imm
)
7918 || (i
.types
[0].bitfield
.instance
== RegC
7919 && i
.types
[0].bitfield
.byte
))
7925 /* When there are 4 operands, the first two must be 8bit
7926 immediate operands. The source operand will be the 3rd
7929 For instructions with VexNDS, if the first operand
7930 an imm8, the source operand is the 2nd one. If the last
7931 operand is imm8, the source operand is the first one. */
7932 gas_assert ((i
.imm_operands
== 2
7933 && i
.types
[0].bitfield
.imm8
7934 && i
.types
[1].bitfield
.imm8
)
7935 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7936 && i
.imm_operands
== 1
7937 && (i
.types
[0].bitfield
.imm8
7938 || i
.types
[i
.operands
- 1].bitfield
.imm8
7940 if (i
.imm_operands
== 2)
7944 if (i
.types
[0].bitfield
.imm8
)
7951 if (is_evex_encoding (&i
.tm
))
7953 /* For EVEX instructions, when there are 5 operands, the
7954 first one must be immediate operand. If the second one
7955 is immediate operand, the source operand is the 3th
7956 one. If the last one is immediate operand, the source
7957 operand is the 2nd one. */
7958 gas_assert (i
.imm_operands
== 2
7959 && i
.tm
.opcode_modifier
.sae
7960 && operand_type_check (i
.types
[0], imm
));
7961 if (operand_type_check (i
.types
[1], imm
))
7963 else if (operand_type_check (i
.types
[4], imm
))
7977 /* RC/SAE operand could be between DEST and SRC. That happens
7978 when one operand is GPR and the other one is XMM/YMM/ZMM
7980 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7983 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7985 /* For instructions with VexNDS, the register-only source
7986 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7987 register. It is encoded in VEX prefix. */
7989 i386_operand_type op
;
7992 /* Swap two source operands if needed. */
7993 if (i
.tm
.opcode_modifier
.swapsources
)
8001 op
= i
.tm
.operand_types
[vvvv
];
8002 if ((dest
+ 1) >= i
.operands
8003 || ((op
.bitfield
.class != Reg
8004 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8005 && op
.bitfield
.class != RegSIMD
8006 && !operand_type_equal (&op
, ®mask
)))
8008 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8014 /* One of the register operands will be encoded in the i.rm.reg
8015 field, the other in the combined i.rm.mode and i.rm.regmem
8016 fields. If no form of this instruction supports a memory
8017 destination operand, then we assume the source operand may
8018 sometimes be a memory operand and so we need to store the
8019 destination in the i.rm.reg field. */
8020 if (!i
.tm
.opcode_modifier
.regmem
8021 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8023 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8024 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8025 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8026 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8030 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8031 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8032 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8033 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8035 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8037 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8040 add_prefix (LOCK_PREFIX_OPCODE
);
8044 { /* If it's not 2 reg operands... */
8049 unsigned int fake_zero_displacement
= 0;
8052 for (op
= 0; op
< i
.operands
; op
++)
8053 if (i
.flags
[op
] & Operand_Mem
)
8055 gas_assert (op
< i
.operands
);
8057 if (i
.tm
.opcode_modifier
.sib
)
8059 /* The index register of VSIB shouldn't be RegIZ. */
8060 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8061 && i
.index_reg
->reg_num
== RegIZ
)
8064 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8067 i
.sib
.base
= NO_BASE_REGISTER
;
8068 i
.sib
.scale
= i
.log2_scale_factor
;
8069 i
.types
[op
].bitfield
.disp8
= 0;
8070 i
.types
[op
].bitfield
.disp16
= 0;
8071 i
.types
[op
].bitfield
.disp64
= 0;
8072 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8074 /* Must be 32 bit */
8075 i
.types
[op
].bitfield
.disp32
= 1;
8076 i
.types
[op
].bitfield
.disp32s
= 0;
8080 i
.types
[op
].bitfield
.disp32
= 0;
8081 i
.types
[op
].bitfield
.disp32s
= 1;
8085 /* Since the mandatory SIB always has index register, so
8086 the code logic remains unchanged. The non-mandatory SIB
8087 without index register is allowed and will be handled
8091 if (i
.index_reg
->reg_num
== RegIZ
)
8092 i
.sib
.index
= NO_INDEX_REGISTER
;
8094 i
.sib
.index
= i
.index_reg
->reg_num
;
8095 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8101 if (i
.base_reg
== 0)
8104 if (!i
.disp_operands
)
8105 fake_zero_displacement
= 1;
8106 if (i
.index_reg
== 0)
8108 i386_operand_type newdisp
;
8110 /* Both check for VSIB and mandatory non-vector SIB. */
8111 gas_assert (!i
.tm
.opcode_modifier
.sib
8112 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8113 /* Operand is just <disp> */
8114 if (flag_code
== CODE_64BIT
)
8116 /* 64bit mode overwrites the 32bit absolute
8117 addressing by RIP relative addressing and
8118 absolute addressing is encoded by one of the
8119 redundant SIB forms. */
8120 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8121 i
.sib
.base
= NO_BASE_REGISTER
;
8122 i
.sib
.index
= NO_INDEX_REGISTER
;
8123 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8125 else if ((flag_code
== CODE_16BIT
)
8126 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8128 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8133 i
.rm
.regmem
= NO_BASE_REGISTER
;
8136 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8137 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8139 else if (!i
.tm
.opcode_modifier
.sib
)
8141 /* !i.base_reg && i.index_reg */
8142 if (i
.index_reg
->reg_num
== RegIZ
)
8143 i
.sib
.index
= NO_INDEX_REGISTER
;
8145 i
.sib
.index
= i
.index_reg
->reg_num
;
8146 i
.sib
.base
= NO_BASE_REGISTER
;
8147 i
.sib
.scale
= i
.log2_scale_factor
;
8148 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8149 i
.types
[op
].bitfield
.disp8
= 0;
8150 i
.types
[op
].bitfield
.disp16
= 0;
8151 i
.types
[op
].bitfield
.disp64
= 0;
8152 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8154 /* Must be 32 bit */
8155 i
.types
[op
].bitfield
.disp32
= 1;
8156 i
.types
[op
].bitfield
.disp32s
= 0;
8160 i
.types
[op
].bitfield
.disp32
= 0;
8161 i
.types
[op
].bitfield
.disp32s
= 1;
8163 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8167 /* RIP addressing for 64bit mode. */
8168 else if (i
.base_reg
->reg_num
== RegIP
)
8170 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8171 i
.rm
.regmem
= NO_BASE_REGISTER
;
8172 i
.types
[op
].bitfield
.disp8
= 0;
8173 i
.types
[op
].bitfield
.disp16
= 0;
8174 i
.types
[op
].bitfield
.disp32
= 0;
8175 i
.types
[op
].bitfield
.disp32s
= 1;
8176 i
.types
[op
].bitfield
.disp64
= 0;
8177 i
.flags
[op
] |= Operand_PCrel
;
8178 if (! i
.disp_operands
)
8179 fake_zero_displacement
= 1;
8181 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8183 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8184 switch (i
.base_reg
->reg_num
)
8187 if (i
.index_reg
== 0)
8189 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8190 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8194 if (i
.index_reg
== 0)
8197 if (operand_type_check (i
.types
[op
], disp
) == 0)
8199 /* fake (%bp) into 0(%bp) */
8200 if (i
.disp_encoding
== disp_encoding_16bit
)
8201 i
.types
[op
].bitfield
.disp16
= 1;
8203 i
.types
[op
].bitfield
.disp8
= 1;
8204 fake_zero_displacement
= 1;
8207 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8208 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8210 default: /* (%si) -> 4 or (%di) -> 5 */
8211 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8213 if (!fake_zero_displacement
8217 fake_zero_displacement
= 1;
8218 if (i
.disp_encoding
== disp_encoding_8bit
)
8219 i
.types
[op
].bitfield
.disp8
= 1;
8221 i
.types
[op
].bitfield
.disp16
= 1;
8223 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8225 else /* i.base_reg and 32/64 bit mode */
8227 if (flag_code
== CODE_64BIT
8228 && operand_type_check (i
.types
[op
], disp
))
8230 i
.types
[op
].bitfield
.disp16
= 0;
8231 i
.types
[op
].bitfield
.disp64
= 0;
8232 if (i
.prefix
[ADDR_PREFIX
] == 0)
8234 i
.types
[op
].bitfield
.disp32
= 0;
8235 i
.types
[op
].bitfield
.disp32s
= 1;
8239 i
.types
[op
].bitfield
.disp32
= 1;
8240 i
.types
[op
].bitfield
.disp32s
= 0;
8244 if (!i
.tm
.opcode_modifier
.sib
)
8245 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8246 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8248 i
.sib
.base
= i
.base_reg
->reg_num
;
8249 /* x86-64 ignores REX prefix bit here to avoid decoder
8251 if (!(i
.base_reg
->reg_flags
& RegRex
)
8252 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8253 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8255 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8257 fake_zero_displacement
= 1;
8258 if (i
.disp_encoding
== disp_encoding_32bit
)
8259 i
.types
[op
].bitfield
.disp32
= 1;
8261 i
.types
[op
].bitfield
.disp8
= 1;
8263 i
.sib
.scale
= i
.log2_scale_factor
;
8264 if (i
.index_reg
== 0)
8266 /* Only check for VSIB. */
8267 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8268 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8269 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8271 /* <disp>(%esp) becomes two byte modrm with no index
8272 register. We've already stored the code for esp
8273 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8274 Any base register besides %esp will not use the
8275 extra modrm byte. */
8276 i
.sib
.index
= NO_INDEX_REGISTER
;
8278 else if (!i
.tm
.opcode_modifier
.sib
)
8280 if (i
.index_reg
->reg_num
== RegIZ
)
8281 i
.sib
.index
= NO_INDEX_REGISTER
;
8283 i
.sib
.index
= i
.index_reg
->reg_num
;
8284 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8285 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8290 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8291 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8295 if (!fake_zero_displacement
8299 fake_zero_displacement
= 1;
8300 if (i
.disp_encoding
== disp_encoding_8bit
)
8301 i
.types
[op
].bitfield
.disp8
= 1;
8303 i
.types
[op
].bitfield
.disp32
= 1;
8305 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8309 if (fake_zero_displacement
)
8311 /* Fakes a zero displacement assuming that i.types[op]
8312 holds the correct displacement size. */
8315 gas_assert (i
.op
[op
].disps
== 0);
8316 exp
= &disp_expressions
[i
.disp_operands
++];
8317 i
.op
[op
].disps
= exp
;
8318 exp
->X_op
= O_constant
;
8319 exp
->X_add_number
= 0;
8320 exp
->X_add_symbol
= (symbolS
*) 0;
8321 exp
->X_op_symbol
= (symbolS
*) 0;
8329 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8331 if (operand_type_check (i
.types
[0], imm
))
8332 i
.vex
.register_specifier
= NULL
;
8335 /* VEX.vvvv encodes one of the sources when the first
8336 operand is not an immediate. */
8337 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8338 i
.vex
.register_specifier
= i
.op
[0].regs
;
8340 i
.vex
.register_specifier
= i
.op
[1].regs
;
8343 /* Destination is a XMM register encoded in the ModRM.reg
8345 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8346 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8349 /* ModRM.rm and VEX.B encodes the other source. */
8350 if (!i
.mem_operands
)
8354 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8355 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8357 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8359 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8363 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8365 i
.vex
.register_specifier
= i
.op
[2].regs
;
8366 if (!i
.mem_operands
)
8369 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8370 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8374 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8375 (if any) based on i.tm.extension_opcode. Again, we must be
8376 careful to make sure that segment/control/debug/test/MMX
8377 registers are coded into the i.rm.reg field. */
8378 else if (i
.reg_operands
)
8381 unsigned int vex_reg
= ~0;
8383 for (op
= 0; op
< i
.operands
; op
++)
8384 if (i
.types
[op
].bitfield
.class == Reg
8385 || i
.types
[op
].bitfield
.class == RegBND
8386 || i
.types
[op
].bitfield
.class == RegMask
8387 || i
.types
[op
].bitfield
.class == SReg
8388 || i
.types
[op
].bitfield
.class == RegCR
8389 || i
.types
[op
].bitfield
.class == RegDR
8390 || i
.types
[op
].bitfield
.class == RegTR
8391 || i
.types
[op
].bitfield
.class == RegSIMD
8392 || i
.types
[op
].bitfield
.class == RegMMX
)
8397 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8399 /* For instructions with VexNDS, the register-only
8400 source operand is encoded in VEX prefix. */
8401 gas_assert (mem
!= (unsigned int) ~0);
8406 gas_assert (op
< i
.operands
);
8410 /* Check register-only source operand when two source
8411 operands are swapped. */
8412 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8413 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8417 gas_assert (mem
== (vex_reg
+ 1)
8418 && op
< i
.operands
);
8423 gas_assert (vex_reg
< i
.operands
);
8427 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8429 /* For instructions with VexNDD, the register destination
8430 is encoded in VEX prefix. */
8431 if (i
.mem_operands
== 0)
8433 /* There is no memory operand. */
8434 gas_assert ((op
+ 2) == i
.operands
);
8439 /* There are only 2 non-immediate operands. */
8440 gas_assert (op
< i
.imm_operands
+ 2
8441 && i
.operands
== i
.imm_operands
+ 2);
8442 vex_reg
= i
.imm_operands
+ 1;
8446 gas_assert (op
< i
.operands
);
8448 if (vex_reg
!= (unsigned int) ~0)
8450 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8452 if ((type
->bitfield
.class != Reg
8453 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8454 && type
->bitfield
.class != RegSIMD
8455 && !operand_type_equal (type
, ®mask
))
8458 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8461 /* Don't set OP operand twice. */
8464 /* If there is an extension opcode to put here, the
8465 register number must be put into the regmem field. */
8466 if (i
.tm
.extension_opcode
!= None
)
8468 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8469 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8470 i
.tm
.opcode_modifier
.sse2avx
);
8474 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8475 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8476 i
.tm
.opcode_modifier
.sse2avx
);
8480 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8481 must set it to 3 to indicate this is a register operand
8482 in the regmem field. */
8483 if (!i
.mem_operands
)
8487 /* Fill in i.rm.reg field with extension opcode (if any). */
8488 if (i
.tm
.extension_opcode
!= None
)
8489 i
.rm
.reg
= i
.tm
.extension_opcode
;
8495 frag_opcode_byte (unsigned char byte
)
8497 if (now_seg
!= absolute_section
)
8498 FRAG_APPEND_1_CHAR (byte
);
8500 ++abs_section_offset
;
8504 flip_code16 (unsigned int code16
)
8506 gas_assert (i
.tm
.operands
== 1);
8508 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8509 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8510 || i
.tm
.operand_types
[0].bitfield
.disp32s
8511 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8516 output_branch (void)
8522 relax_substateT subtype
;
8526 if (now_seg
== absolute_section
)
8528 as_bad (_("relaxable branches not supported in absolute section"));
8532 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8533 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8536 if (i
.prefix
[DATA_PREFIX
] != 0)
8540 code16
^= flip_code16(code16
);
8542 /* Pentium4 branch hints. */
8543 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8544 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8549 if (i
.prefix
[REX_PREFIX
] != 0)
8555 /* BND prefixed jump. */
8556 if (i
.prefix
[BND_PREFIX
] != 0)
8562 if (i
.prefixes
!= 0)
8563 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8565 /* It's always a symbol; End frag & setup for relax.
8566 Make sure there is enough room in this frag for the largest
8567 instruction we may generate in md_convert_frag. This is 2
8568 bytes for the opcode and room for the prefix and largest
8570 frag_grow (prefix
+ 2 + 4);
8571 /* Prefix and 1 opcode byte go in fr_fix. */
8572 p
= frag_more (prefix
+ 1);
8573 if (i
.prefix
[DATA_PREFIX
] != 0)
8574 *p
++ = DATA_PREFIX_OPCODE
;
8575 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8576 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8577 *p
++ = i
.prefix
[SEG_PREFIX
];
8578 if (i
.prefix
[BND_PREFIX
] != 0)
8579 *p
++ = BND_PREFIX_OPCODE
;
8580 if (i
.prefix
[REX_PREFIX
] != 0)
8581 *p
++ = i
.prefix
[REX_PREFIX
];
8582 *p
= i
.tm
.base_opcode
;
8584 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8585 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8586 else if (cpu_arch_flags
.bitfield
.cpui386
)
8587 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8589 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8592 sym
= i
.op
[0].disps
->X_add_symbol
;
8593 off
= i
.op
[0].disps
->X_add_number
;
8595 if (i
.op
[0].disps
->X_op
!= O_constant
8596 && i
.op
[0].disps
->X_op
!= O_symbol
)
8598 /* Handle complex expressions. */
8599 sym
= make_expr_symbol (i
.op
[0].disps
);
8603 /* 1 possible extra opcode + 4 byte displacement go in var part.
8604 Pass reloc in fr_var. */
8605 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8609 /* Return TRUE iff PLT32 relocation should be used for branching to
8613 need_plt32_p (symbolS
*s
)
8615 /* PLT32 relocation is ELF only. */
8620 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8621 krtld support it. */
8625 /* Since there is no need to prepare for PLT branch on x86-64, we
8626 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8627 be used as a marker for 32-bit PC-relative branches. */
8631 /* Weak or undefined symbol need PLT32 relocation. */
8632 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8635 /* Non-global symbol doesn't need PLT32 relocation. */
8636 if (! S_IS_EXTERNAL (s
))
8639 /* Other global symbols need PLT32 relocation. NB: Symbol with
8640 non-default visibilities are treated as normal global symbol
8641 so that PLT32 relocation can be used as a marker for 32-bit
8642 PC-relative branches. It is useful for linker relaxation. */
8653 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8655 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8657 /* This is a loop or jecxz type instruction. */
8659 if (i
.prefix
[ADDR_PREFIX
] != 0)
8661 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8664 /* Pentium4 branch hints. */
8665 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8666 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8668 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8677 if (flag_code
== CODE_16BIT
)
8680 if (i
.prefix
[DATA_PREFIX
] != 0)
8682 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8684 code16
^= flip_code16(code16
);
8692 /* BND prefixed jump. */
8693 if (i
.prefix
[BND_PREFIX
] != 0)
8695 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8699 if (i
.prefix
[REX_PREFIX
] != 0)
8701 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8705 if (i
.prefixes
!= 0)
8706 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8708 if (now_seg
== absolute_section
)
8710 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8714 p
= frag_more (i
.tm
.opcode_length
+ size
);
8715 switch (i
.tm
.opcode_length
)
8718 *p
++ = i
.tm
.base_opcode
>> 8;
8721 *p
++ = i
.tm
.base_opcode
;
8727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8729 && jump_reloc
== NO_RELOC
8730 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8731 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8734 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8736 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8737 i
.op
[0].disps
, 1, jump_reloc
);
8739 /* All jumps handled here are signed, but don't use a signed limit
8740 check for 32 and 16 bit jumps as we want to allow wrap around at
8741 4G and 64k respectively. */
8743 fixP
->fx_signed
= 1;
8747 output_interseg_jump (void)
8755 if (flag_code
== CODE_16BIT
)
8759 if (i
.prefix
[DATA_PREFIX
] != 0)
8766 gas_assert (!i
.prefix
[REX_PREFIX
]);
8772 if (i
.prefixes
!= 0)
8773 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8775 if (now_seg
== absolute_section
)
8777 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8781 /* 1 opcode; 2 segment; offset */
8782 p
= frag_more (prefix
+ 1 + 2 + size
);
8784 if (i
.prefix
[DATA_PREFIX
] != 0)
8785 *p
++ = DATA_PREFIX_OPCODE
;
8787 if (i
.prefix
[REX_PREFIX
] != 0)
8788 *p
++ = i
.prefix
[REX_PREFIX
];
8790 *p
++ = i
.tm
.base_opcode
;
8791 if (i
.op
[1].imms
->X_op
== O_constant
)
8793 offsetT n
= i
.op
[1].imms
->X_add_number
;
8796 && !fits_in_unsigned_word (n
)
8797 && !fits_in_signed_word (n
))
8799 as_bad (_("16-bit jump out of range"));
8802 md_number_to_chars (p
, n
, size
);
8805 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8806 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8809 if (i
.op
[0].imms
->X_op
== O_constant
)
8810 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8812 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8813 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8821 asection
*seg
= now_seg
;
8822 subsegT subseg
= now_subseg
;
8824 unsigned int alignment
, align_size_1
;
8825 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8826 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8827 unsigned int padding
;
8829 if (!IS_ELF
|| !x86_used_note
)
8832 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8834 /* The .note.gnu.property section layout:
8836 Field Length Contents
8839 n_descsz 4 The note descriptor size
8840 n_type 4 NT_GNU_PROPERTY_TYPE_0
8842 n_desc n_descsz The program property array
8846 /* Create the .note.gnu.property section. */
8847 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8848 bfd_set_section_flags (sec
,
8855 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8866 bfd_set_section_alignment (sec
, alignment
);
8867 elf_section_type (sec
) = SHT_NOTE
;
8869 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8871 isa_1_descsz_raw
= 4 + 4 + 4;
8872 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8873 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8875 feature_2_descsz_raw
= isa_1_descsz
;
8876 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8878 feature_2_descsz_raw
+= 4 + 4 + 4;
8879 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8880 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8883 descsz
= feature_2_descsz
;
8884 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8885 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8887 /* Write n_namsz. */
8888 md_number_to_chars (p
, (valueT
) 4, 4);
8890 /* Write n_descsz. */
8891 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8894 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8897 memcpy (p
+ 4 * 3, "GNU", 4);
8899 /* Write 4-byte type. */
8900 md_number_to_chars (p
+ 4 * 4,
8901 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8903 /* Write 4-byte data size. */
8904 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8906 /* Write 4-byte data. */
8907 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8909 /* Zero out paddings. */
8910 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8912 memset (p
+ 4 * 7, 0, padding
);
8914 /* Write 4-byte type. */
8915 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8916 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8918 /* Write 4-byte data size. */
8919 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8921 /* Write 4-byte data. */
8922 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8923 (valueT
) x86_feature_2_used
, 4);
8925 /* Zero out paddings. */
8926 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8928 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8930 /* We probably can't restore the current segment, for there likely
8933 subseg_set (seg
, subseg
);
8938 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8939 const char *frag_now_ptr
)
8941 unsigned int len
= 0;
8943 if (start_frag
!= frag_now
)
8945 const fragS
*fr
= start_frag
;
8950 } while (fr
&& fr
!= frag_now
);
8953 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8956 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8957 be macro-fused with conditional jumps.
8958 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8959 or is one of the following format:
8972 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8974 /* No RIP address. */
8975 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8978 /* No VEX/EVEX encoding. */
8979 if (is_any_vex_encoding (&i
.tm
))
8982 /* add, sub without add/sub m, imm. */
8983 if (i
.tm
.base_opcode
<= 5
8984 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8985 || ((i
.tm
.base_opcode
| 3) == 0x83
8986 && (i
.tm
.extension_opcode
== 0x5
8987 || i
.tm
.extension_opcode
== 0x0)))
8989 *mf_cmp_p
= mf_cmp_alu_cmp
;
8990 return !(i
.mem_operands
&& i
.imm_operands
);
8993 /* and without and m, imm. */
8994 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8995 || ((i
.tm
.base_opcode
| 3) == 0x83
8996 && i
.tm
.extension_opcode
== 0x4))
8998 *mf_cmp_p
= mf_cmp_test_and
;
8999 return !(i
.mem_operands
&& i
.imm_operands
);
9002 /* test without test m imm. */
9003 if ((i
.tm
.base_opcode
| 1) == 0x85
9004 || (i
.tm
.base_opcode
| 1) == 0xa9
9005 || ((i
.tm
.base_opcode
| 1) == 0xf7
9006 && i
.tm
.extension_opcode
== 0))
9008 *mf_cmp_p
= mf_cmp_test_and
;
9009 return !(i
.mem_operands
&& i
.imm_operands
);
9012 /* cmp without cmp m, imm. */
9013 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9014 || ((i
.tm
.base_opcode
| 3) == 0x83
9015 && (i
.tm
.extension_opcode
== 0x7)))
9017 *mf_cmp_p
= mf_cmp_alu_cmp
;
9018 return !(i
.mem_operands
&& i
.imm_operands
);
9021 /* inc, dec without inc/dec m. */
9022 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9023 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9024 || ((i
.tm
.base_opcode
| 1) == 0xff
9025 && i
.tm
.extension_opcode
<= 0x1))
9027 *mf_cmp_p
= mf_cmp_incdec
;
9028 return !i
.mem_operands
;
9034 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9037 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9039 /* NB: Don't work with COND_JUMP86 without i386. */
9040 if (!align_branch_power
9041 || now_seg
== absolute_section
9042 || !cpu_arch_flags
.bitfield
.cpui386
9043 || !(align_branch
& align_branch_fused_bit
))
9046 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9048 if (last_insn
.kind
== last_insn_other
9049 || last_insn
.seg
!= now_seg
)
9052 as_warn_where (last_insn
.file
, last_insn
.line
,
9053 _("`%s` skips -malign-branch-boundary on `%s`"),
9054 last_insn
.name
, i
.tm
.name
);
9060 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9063 add_branch_prefix_frag_p (void)
9065 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9066 to PadLock instructions since they include prefixes in opcode. */
9067 if (!align_branch_power
9068 || !align_branch_prefix_size
9069 || now_seg
== absolute_section
9070 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9071 || !cpu_arch_flags
.bitfield
.cpui386
)
9074 /* Don't add prefix if it is a prefix or there is no operand in case
9075 that segment prefix is special. */
9076 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9079 if (last_insn
.kind
== last_insn_other
9080 || last_insn
.seg
!= now_seg
)
9084 as_warn_where (last_insn
.file
, last_insn
.line
,
9085 _("`%s` skips -malign-branch-boundary on `%s`"),
9086 last_insn
.name
, i
.tm
.name
);
9091 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9094 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9095 enum mf_jcc_kind
*mf_jcc_p
)
9099 /* NB: Don't work with COND_JUMP86 without i386. */
9100 if (!align_branch_power
9101 || now_seg
== absolute_section
9102 || !cpu_arch_flags
.bitfield
.cpui386
)
9107 /* Check for jcc and direct jmp. */
9108 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9110 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9112 *branch_p
= align_branch_jmp
;
9113 add_padding
= align_branch
& align_branch_jmp_bit
;
9117 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9118 igore the lowest bit. */
9119 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9120 *branch_p
= align_branch_jcc
;
9121 if ((align_branch
& align_branch_jcc_bit
))
9125 else if (is_any_vex_encoding (&i
.tm
))
9127 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9130 *branch_p
= align_branch_ret
;
9131 if ((align_branch
& align_branch_ret_bit
))
9136 /* Check for indirect jmp, direct and indirect calls. */
9137 if (i
.tm
.base_opcode
== 0xe8)
9140 *branch_p
= align_branch_call
;
9141 if ((align_branch
& align_branch_call_bit
))
9144 else if (i
.tm
.base_opcode
== 0xff
9145 && (i
.tm
.extension_opcode
== 2
9146 || i
.tm
.extension_opcode
== 4))
9148 /* Indirect call and jmp. */
9149 *branch_p
= align_branch_indirect
;
9150 if ((align_branch
& align_branch_indirect_bit
))
9157 && (i
.op
[0].disps
->X_op
== O_symbol
9158 || (i
.op
[0].disps
->X_op
== O_subtract
9159 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9161 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9162 /* No padding to call to global or undefined tls_get_addr. */
9163 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9164 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9170 && last_insn
.kind
!= last_insn_other
9171 && last_insn
.seg
== now_seg
)
9174 as_warn_where (last_insn
.file
, last_insn
.line
,
9175 _("`%s` skips -malign-branch-boundary on `%s`"),
9176 last_insn
.name
, i
.tm
.name
);
9186 fragS
*insn_start_frag
;
9187 offsetT insn_start_off
;
9188 fragS
*fragP
= NULL
;
9189 enum align_branch_kind branch
= align_branch_none
;
9190 /* The initializer is arbitrary just to avoid uninitialized error.
9191 it's actually either assigned in add_branch_padding_frag_p
9192 or never be used. */
9193 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9196 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9198 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9199 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9200 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9202 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9203 || i
.tm
.cpu_flags
.bitfield
.cpu287
9204 || i
.tm
.cpu_flags
.bitfield
.cpu387
9205 || i
.tm
.cpu_flags
.bitfield
.cpu687
9206 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9207 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9208 if ((i
.xstate
& xstate_mmx
)
9209 || i
.tm
.base_opcode
== 0xf77 /* emms */
9210 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9211 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9214 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9215 i
.xstate
|= xstate_zmm
;
9216 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9217 i
.xstate
|= xstate_ymm
;
9218 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9219 i
.xstate
|= xstate_xmm
;
9221 if ((i
.xstate
& xstate_xmm
)
9222 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9223 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9224 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9225 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9226 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9227 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9228 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9229 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9230 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9231 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9232 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9233 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9234 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9235 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9236 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9237 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9238 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9240 if (x86_feature_2_used
9241 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9242 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9243 || (i
.tm
.base_opcode
== 0xfc7
9244 && i
.tm
.opcode_modifier
.opcodeprefix
== 0
9245 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9247 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9248 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9249 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9250 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9251 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9252 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9253 /* LAHF-SAHF insns in 64-bit mode. */
9254 || (flag_code
== CODE_64BIT
9255 && (i
.tm
.base_opcode
| 1) == 0x9f))
9256 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9257 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9258 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9259 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9260 CpuAVX512DQ, LPW, TBM and AMX. */
9261 || (i
.tm
.opcode_modifier
.vex
9262 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9263 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9264 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9265 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9266 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9267 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9268 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9269 || i
.tm
.cpu_flags
.bitfield
.cpufma
9270 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9271 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9272 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9273 || (x86_feature_2_used
9274 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9275 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9276 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9277 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9278 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9279 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9280 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9281 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9282 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9284 || (i
.tm
.opcode_modifier
.evex
9285 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9286 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9287 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9288 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9292 /* Tie dwarf2 debug info to the address at the start of the insn.
9293 We can't do this after the insn has been output as the current
9294 frag may have been closed off. eg. by frag_var. */
9295 dwarf2_emit_insn (0);
9297 insn_start_frag
= frag_now
;
9298 insn_start_off
= frag_now_fix ();
9300 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9303 /* Branch can be 8 bytes. Leave some room for prefixes. */
9304 unsigned int max_branch_padding_size
= 14;
9306 /* Align section to boundary. */
9307 record_alignment (now_seg
, align_branch_power
);
9309 /* Make room for padding. */
9310 frag_grow (max_branch_padding_size
);
9312 /* Start of the padding. */
9317 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9318 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9321 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9322 fragP
->tc_frag_data
.branch_type
= branch
;
9323 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9327 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9329 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9330 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9332 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9333 output_interseg_jump ();
9336 /* Output normal instructions here. */
9340 enum mf_cmp_kind mf_cmp
;
9343 && (i
.tm
.base_opcode
== 0xfaee8
9344 || i
.tm
.base_opcode
== 0xfaef0
9345 || i
.tm
.base_opcode
== 0xfaef8))
9347 /* Encode lfence, mfence, and sfence as
9348 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9349 if (now_seg
!= absolute_section
)
9351 offsetT val
= 0x240483f0ULL
;
9354 md_number_to_chars (p
, val
, 5);
9357 abs_section_offset
+= 5;
9361 /* Some processors fail on LOCK prefix. This options makes
9362 assembler ignore LOCK prefix and serves as a workaround. */
9363 if (omit_lock_prefix
)
9365 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9367 i
.prefix
[LOCK_PREFIX
] = 0;
9371 /* Skip if this is a branch. */
9373 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9375 /* Make room for padding. */
9376 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9381 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9382 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9385 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9386 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9387 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9389 else if (add_branch_prefix_frag_p ())
9391 unsigned int max_prefix_size
= align_branch_prefix_size
;
9393 /* Make room for padding. */
9394 frag_grow (max_prefix_size
);
9399 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9400 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9403 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9406 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9407 don't need the explicit prefix. */
9408 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9410 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9419 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9420 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9424 switch (i
.tm
.opcode_length
)
9431 /* Check for pseudo prefixes. */
9432 as_bad_where (insn_start_frag
->fr_file
,
9433 insn_start_frag
->fr_line
,
9434 _("pseudo prefix without instruction"));
9444 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9445 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9446 R_X86_64_GOTTPOFF relocation so that linker can safely
9447 perform IE->LE optimization. A dummy REX_OPCODE prefix
9448 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9449 relocation for GDesc -> IE/LE optimization. */
9450 if (x86_elf_abi
== X86_64_X32_ABI
9452 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9453 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9454 && i
.prefix
[REX_PREFIX
] == 0)
9455 add_prefix (REX_OPCODE
);
9458 /* The prefix bytes. */
9459 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9461 frag_opcode_byte (*q
);
9465 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9471 frag_opcode_byte (*q
);
9474 /* There should be no other prefixes for instructions
9479 /* For EVEX instructions i.vrex should become 0 after
9480 build_evex_prefix. For VEX instructions upper 16 registers
9481 aren't available, so VREX should be 0. */
9484 /* Now the VEX prefix. */
9485 if (now_seg
!= absolute_section
)
9487 p
= frag_more (i
.vex
.length
);
9488 for (j
= 0; j
< i
.vex
.length
; j
++)
9489 p
[j
] = i
.vex
.bytes
[j
];
9492 abs_section_offset
+= i
.vex
.length
;
9495 /* Now the opcode; be careful about word order here! */
9496 if (now_seg
== absolute_section
)
9497 abs_section_offset
+= i
.tm
.opcode_length
;
9498 else if (i
.tm
.opcode_length
== 1)
9500 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9504 switch (i
.tm
.opcode_length
)
9508 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9509 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9513 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9523 /* Put out high byte first: can't use md_number_to_chars! */
9524 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9525 *p
= i
.tm
.base_opcode
& 0xff;
9528 /* Now the modrm byte and sib byte (if present). */
9529 if (i
.tm
.opcode_modifier
.modrm
)
9531 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9533 | (i
.rm
.mode
<< 6));
9534 /* If i.rm.regmem == ESP (4)
9535 && i.rm.mode != (Register mode)
9537 ==> need second modrm byte. */
9538 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9540 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9541 frag_opcode_byte ((i
.sib
.base
<< 0)
9542 | (i
.sib
.index
<< 3)
9543 | (i
.sib
.scale
<< 6));
9546 if (i
.disp_operands
)
9547 output_disp (insn_start_frag
, insn_start_off
);
9550 output_imm (insn_start_frag
, insn_start_off
);
9553 * frag_now_fix () returning plain abs_section_offset when we're in the
9554 * absolute section, and abs_section_offset not getting updated as data
9555 * gets added to the frag breaks the logic below.
9557 if (now_seg
!= absolute_section
)
9559 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9561 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9565 /* NB: Don't add prefix with GOTPC relocation since
9566 output_disp() above depends on the fixed encoding
9567 length. Can't add prefix with TLS relocation since
9568 it breaks TLS linker optimization. */
9569 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9570 /* Prefix count on the current instruction. */
9571 unsigned int count
= i
.vex
.length
;
9573 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9574 /* REX byte is encoded in VEX/EVEX prefix. */
9575 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9578 /* Count prefixes for extended opcode maps. */
9580 switch (i
.tm
.opcode_length
)
9583 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9586 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9598 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9607 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9610 /* Set the maximum prefix size in BRANCH_PREFIX
9612 if (fragP
->tc_frag_data
.max_bytes
> max
)
9613 fragP
->tc_frag_data
.max_bytes
= max
;
9614 if (fragP
->tc_frag_data
.max_bytes
> count
)
9615 fragP
->tc_frag_data
.max_bytes
-= count
;
9617 fragP
->tc_frag_data
.max_bytes
= 0;
9621 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9623 unsigned int max_prefix_size
;
9624 if (align_branch_prefix_size
> max
)
9625 max_prefix_size
= max
;
9627 max_prefix_size
= align_branch_prefix_size
;
9628 if (max_prefix_size
> count
)
9629 fragP
->tc_frag_data
.max_prefix_length
9630 = max_prefix_size
- count
;
9633 /* Use existing segment prefix if possible. Use CS
9634 segment prefix in 64-bit mode. In 32-bit mode, use SS
9635 segment prefix with ESP/EBP base register and use DS
9636 segment prefix without ESP/EBP base register. */
9637 if (i
.prefix
[SEG_PREFIX
])
9638 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9639 else if (flag_code
== CODE_64BIT
)
9640 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9642 && (i
.base_reg
->reg_num
== 4
9643 || i
.base_reg
->reg_num
== 5))
9644 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9646 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9651 /* NB: Don't work with COND_JUMP86 without i386. */
9652 if (align_branch_power
9653 && now_seg
!= absolute_section
9654 && cpu_arch_flags
.bitfield
.cpui386
)
9656 /* Terminate each frag so that we can add prefix and check for
9658 frag_wane (frag_now
);
9665 pi ("" /*line*/, &i
);
9667 #endif /* DEBUG386 */
9670 /* Return the size of the displacement operand N. */
9673 disp_size (unsigned int n
)
9677 if (i
.types
[n
].bitfield
.disp64
)
9679 else if (i
.types
[n
].bitfield
.disp8
)
9681 else if (i
.types
[n
].bitfield
.disp16
)
9686 /* Return the size of the immediate operand N. */
9689 imm_size (unsigned int n
)
9692 if (i
.types
[n
].bitfield
.imm64
)
9694 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9696 else if (i
.types
[n
].bitfield
.imm16
)
9702 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9707 for (n
= 0; n
< i
.operands
; n
++)
9709 if (operand_type_check (i
.types
[n
], disp
))
9711 int size
= disp_size (n
);
9713 if (now_seg
== absolute_section
)
9714 abs_section_offset
+= size
;
9715 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9717 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9719 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9721 p
= frag_more (size
);
9722 md_number_to_chars (p
, val
, size
);
9726 enum bfd_reloc_code_real reloc_type
;
9727 int sign
= i
.types
[n
].bitfield
.disp32s
;
9728 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9731 /* We can't have 8 bit displacement here. */
9732 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9734 /* The PC relative address is computed relative
9735 to the instruction boundary, so in case immediate
9736 fields follows, we need to adjust the value. */
9737 if (pcrel
&& i
.imm_operands
)
9742 for (n1
= 0; n1
< i
.operands
; n1
++)
9743 if (operand_type_check (i
.types
[n1
], imm
))
9745 /* Only one immediate is allowed for PC
9746 relative address. */
9747 gas_assert (sz
== 0);
9749 i
.op
[n
].disps
->X_add_number
-= sz
;
9751 /* We should find the immediate. */
9752 gas_assert (sz
!= 0);
9755 p
= frag_more (size
);
9756 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9758 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9759 && (((reloc_type
== BFD_RELOC_32
9760 || reloc_type
== BFD_RELOC_X86_64_32S
9761 || (reloc_type
== BFD_RELOC_64
9763 && (i
.op
[n
].disps
->X_op
== O_symbol
9764 || (i
.op
[n
].disps
->X_op
== O_add
9765 && ((symbol_get_value_expression
9766 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9768 || reloc_type
== BFD_RELOC_32_PCREL
))
9772 reloc_type
= BFD_RELOC_386_GOTPC
;
9773 i
.has_gotpc_tls_reloc
= TRUE
;
9774 i
.op
[n
].imms
->X_add_number
+=
9775 encoding_length (insn_start_frag
, insn_start_off
, p
);
9777 else if (reloc_type
== BFD_RELOC_64
)
9778 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9780 /* Don't do the adjustment for x86-64, as there
9781 the pcrel addressing is relative to the _next_
9782 insn, and that is taken care of in other code. */
9783 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9785 else if (align_branch_power
)
9789 case BFD_RELOC_386_TLS_GD
:
9790 case BFD_RELOC_386_TLS_LDM
:
9791 case BFD_RELOC_386_TLS_IE
:
9792 case BFD_RELOC_386_TLS_IE_32
:
9793 case BFD_RELOC_386_TLS_GOTIE
:
9794 case BFD_RELOC_386_TLS_GOTDESC
:
9795 case BFD_RELOC_386_TLS_DESC_CALL
:
9796 case BFD_RELOC_X86_64_TLSGD
:
9797 case BFD_RELOC_X86_64_TLSLD
:
9798 case BFD_RELOC_X86_64_GOTTPOFF
:
9799 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9800 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9801 i
.has_gotpc_tls_reloc
= TRUE
;
9806 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9807 size
, i
.op
[n
].disps
, pcrel
,
9809 /* Check for "call/jmp *mem", "mov mem, %reg",
9810 "test %reg, mem" and "binop mem, %reg" where binop
9811 is one of adc, add, and, cmp, or, sbb, sub, xor
9812 instructions without data prefix. Always generate
9813 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9814 if (i
.prefix
[DATA_PREFIX
] == 0
9815 && (generate_relax_relocations
9818 && i
.rm
.regmem
== 5))
9820 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9821 && !is_any_vex_encoding(&i
.tm
)
9822 && ((i
.operands
== 1
9823 && i
.tm
.base_opcode
== 0xff
9824 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9826 && (i
.tm
.base_opcode
== 0x8b
9827 || i
.tm
.base_opcode
== 0x85
9828 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9832 fixP
->fx_tcbit
= i
.rex
!= 0;
9834 && (i
.base_reg
->reg_num
== RegIP
))
9835 fixP
->fx_tcbit2
= 1;
9838 fixP
->fx_tcbit2
= 1;
9846 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9851 for (n
= 0; n
< i
.operands
; n
++)
9853 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9854 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9857 if (operand_type_check (i
.types
[n
], imm
))
9859 int size
= imm_size (n
);
9861 if (now_seg
== absolute_section
)
9862 abs_section_offset
+= size
;
9863 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9867 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9869 p
= frag_more (size
);
9870 md_number_to_chars (p
, val
, size
);
9874 /* Not absolute_section.
9875 Need a 32-bit fixup (don't support 8bit
9876 non-absolute imms). Try to support other
9878 enum bfd_reloc_code_real reloc_type
;
9881 if (i
.types
[n
].bitfield
.imm32s
9882 && (i
.suffix
== QWORD_MNEM_SUFFIX
9883 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9888 p
= frag_more (size
);
9889 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9891 /* This is tough to explain. We end up with this one if we
9892 * have operands that look like
9893 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9894 * obtain the absolute address of the GOT, and it is strongly
9895 * preferable from a performance point of view to avoid using
9896 * a runtime relocation for this. The actual sequence of
9897 * instructions often look something like:
9902 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9904 * The call and pop essentially return the absolute address
9905 * of the label .L66 and store it in %ebx. The linker itself
9906 * will ultimately change the first operand of the addl so
9907 * that %ebx points to the GOT, but to keep things simple, the
9908 * .o file must have this operand set so that it generates not
9909 * the absolute address of .L66, but the absolute address of
9910 * itself. This allows the linker itself simply treat a GOTPC
9911 * relocation as asking for a pcrel offset to the GOT to be
9912 * added in, and the addend of the relocation is stored in the
9913 * operand field for the instruction itself.
9915 * Our job here is to fix the operand so that it would add
9916 * the correct offset so that %ebx would point to itself. The
9917 * thing that is tricky is that .-.L66 will point to the
9918 * beginning of the instruction, so we need to further modify
9919 * the operand so that it will point to itself. There are
9920 * other cases where you have something like:
9922 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9924 * and here no correction would be required. Internally in
9925 * the assembler we treat operands of this form as not being
9926 * pcrel since the '.' is explicitly mentioned, and I wonder
9927 * whether it would simplify matters to do it this way. Who
9928 * knows. In earlier versions of the PIC patches, the
9929 * pcrel_adjust field was used to store the correction, but
9930 * since the expression is not pcrel, I felt it would be
9931 * confusing to do it this way. */
9933 if ((reloc_type
== BFD_RELOC_32
9934 || reloc_type
== BFD_RELOC_X86_64_32S
9935 || reloc_type
== BFD_RELOC_64
)
9937 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9938 && (i
.op
[n
].imms
->X_op
== O_symbol
9939 || (i
.op
[n
].imms
->X_op
== O_add
9940 && ((symbol_get_value_expression
9941 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9945 reloc_type
= BFD_RELOC_386_GOTPC
;
9947 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9949 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9950 i
.has_gotpc_tls_reloc
= TRUE
;
9951 i
.op
[n
].imms
->X_add_number
+=
9952 encoding_length (insn_start_frag
, insn_start_off
, p
);
9954 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9955 i
.op
[n
].imms
, 0, reloc_type
);
9961 /* x86_cons_fix_new is called via the expression parsing code when a
9962 reloc is needed. We use this hook to get the correct .got reloc. */
9963 static int cons_sign
= -1;
9966 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9967 expressionS
*exp
, bfd_reloc_code_real_type r
)
9969 r
= reloc (len
, 0, cons_sign
, r
);
9972 if (exp
->X_op
== O_secrel
)
9974 exp
->X_op
= O_symbol
;
9975 r
= BFD_RELOC_32_SECREL
;
9979 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9982 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9983 purpose of the `.dc.a' internal pseudo-op. */
9986 x86_address_bytes (void)
9988 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9990 return stdoutput
->arch_info
->bits_per_address
/ 8;
9993 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9995 # define lex_got(reloc, adjust, types) NULL
9997 /* Parse operands of the form
9998 <symbol>@GOTOFF+<nnn>
9999 and similar .plt or .got references.
10001 If we find one, set up the correct relocation in RELOC and copy the
10002 input string, minus the `@GOTOFF' into a malloc'd buffer for
10003 parsing by the calling routine. Return this buffer, and if ADJUST
10004 is non-null set it to the length of the string we removed from the
10005 input line. Otherwise return NULL. */
10007 lex_got (enum bfd_reloc_code_real
*rel
,
10009 i386_operand_type
*types
)
10011 /* Some of the relocations depend on the size of what field is to
10012 be relocated. But in our callers i386_immediate and i386_displacement
10013 we don't yet know the operand size (this will be set by insn
10014 matching). Hence we record the word32 relocation here,
10015 and adjust the reloc according to the real size in reloc(). */
10016 static const struct {
10019 const enum bfd_reloc_code_real rel
[2];
10020 const i386_operand_type types64
;
10021 bfd_boolean need_GOT_symbol
;
10023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10024 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10025 BFD_RELOC_SIZE32
},
10026 OPERAND_TYPE_IMM32_64
, FALSE
},
10028 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10029 BFD_RELOC_X86_64_PLTOFF64
},
10030 OPERAND_TYPE_IMM64
, TRUE
},
10031 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10032 BFD_RELOC_X86_64_PLT32
},
10033 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10034 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10035 BFD_RELOC_X86_64_GOTPLT64
},
10036 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10037 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10038 BFD_RELOC_X86_64_GOTOFF64
},
10039 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10040 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10041 BFD_RELOC_X86_64_GOTPCREL
},
10042 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10043 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10044 BFD_RELOC_X86_64_TLSGD
},
10045 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10046 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10047 _dummy_first_bfd_reloc_code_real
},
10048 OPERAND_TYPE_NONE
, TRUE
},
10049 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10050 BFD_RELOC_X86_64_TLSLD
},
10051 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10052 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10053 BFD_RELOC_X86_64_GOTTPOFF
},
10054 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10055 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10056 BFD_RELOC_X86_64_TPOFF32
},
10057 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10058 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10059 _dummy_first_bfd_reloc_code_real
},
10060 OPERAND_TYPE_NONE
, TRUE
},
10061 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10062 BFD_RELOC_X86_64_DTPOFF32
},
10063 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10064 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10065 _dummy_first_bfd_reloc_code_real
},
10066 OPERAND_TYPE_NONE
, TRUE
},
10067 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10068 _dummy_first_bfd_reloc_code_real
},
10069 OPERAND_TYPE_NONE
, TRUE
},
10070 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10071 BFD_RELOC_X86_64_GOT32
},
10072 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10073 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10074 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10075 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10076 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10077 BFD_RELOC_X86_64_TLSDESC_CALL
},
10078 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10083 #if defined (OBJ_MAYBE_ELF)
10088 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10089 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10092 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10094 int len
= gotrel
[j
].len
;
10095 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10097 if (gotrel
[j
].rel
[object_64bit
] != 0)
10100 char *tmpbuf
, *past_reloc
;
10102 *rel
= gotrel
[j
].rel
[object_64bit
];
10106 if (flag_code
!= CODE_64BIT
)
10108 types
->bitfield
.imm32
= 1;
10109 types
->bitfield
.disp32
= 1;
10112 *types
= gotrel
[j
].types64
;
10115 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10116 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10118 /* The length of the first part of our input line. */
10119 first
= cp
- input_line_pointer
;
10121 /* The second part goes from after the reloc token until
10122 (and including) an end_of_line char or comma. */
10123 past_reloc
= cp
+ 1 + len
;
10125 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10127 second
= cp
+ 1 - past_reloc
;
10129 /* Allocate and copy string. The trailing NUL shouldn't
10130 be necessary, but be safe. */
10131 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10132 memcpy (tmpbuf
, input_line_pointer
, first
);
10133 if (second
!= 0 && *past_reloc
!= ' ')
10134 /* Replace the relocation token with ' ', so that
10135 errors like foo@GOTOFF1 will be detected. */
10136 tmpbuf
[first
++] = ' ';
10138 /* Increment length by 1 if the relocation token is
10143 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10144 tmpbuf
[first
+ second
] = '\0';
10148 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10149 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10154 /* Might be a symbol version string. Don't as_bad here. */
10163 /* Parse operands of the form
10164 <symbol>@SECREL32+<nnn>
10166 If we find one, set up the correct relocation in RELOC and copy the
10167 input string, minus the `@SECREL32' into a malloc'd buffer for
10168 parsing by the calling routine. Return this buffer, and if ADJUST
10169 is non-null set it to the length of the string we removed from the
10170 input line. Otherwise return NULL.
10172 This function is copied from the ELF version above adjusted for PE targets. */
10175 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10176 int *adjust ATTRIBUTE_UNUSED
,
10177 i386_operand_type
*types
)
10179 static const struct
10183 const enum bfd_reloc_code_real rel
[2];
10184 const i386_operand_type types64
;
10188 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10189 BFD_RELOC_32_SECREL
},
10190 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10196 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10197 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10200 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10202 int len
= gotrel
[j
].len
;
10204 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10206 if (gotrel
[j
].rel
[object_64bit
] != 0)
10209 char *tmpbuf
, *past_reloc
;
10211 *rel
= gotrel
[j
].rel
[object_64bit
];
10217 if (flag_code
!= CODE_64BIT
)
10219 types
->bitfield
.imm32
= 1;
10220 types
->bitfield
.disp32
= 1;
10223 *types
= gotrel
[j
].types64
;
10226 /* The length of the first part of our input line. */
10227 first
= cp
- input_line_pointer
;
10229 /* The second part goes from after the reloc token until
10230 (and including) an end_of_line char or comma. */
10231 past_reloc
= cp
+ 1 + len
;
10233 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10235 second
= cp
+ 1 - past_reloc
;
10237 /* Allocate and copy string. The trailing NUL shouldn't
10238 be necessary, but be safe. */
10239 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10240 memcpy (tmpbuf
, input_line_pointer
, first
);
10241 if (second
!= 0 && *past_reloc
!= ' ')
10242 /* Replace the relocation token with ' ', so that
10243 errors like foo@SECLREL321 will be detected. */
10244 tmpbuf
[first
++] = ' ';
10245 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10246 tmpbuf
[first
+ second
] = '\0';
10250 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10251 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10256 /* Might be a symbol version string. Don't as_bad here. */
10262 bfd_reloc_code_real_type
10263 x86_cons (expressionS
*exp
, int size
)
10265 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10267 intel_syntax
= -intel_syntax
;
10270 if (size
== 4 || (object_64bit
&& size
== 8))
10272 /* Handle @GOTOFF and the like in an expression. */
10274 char *gotfree_input_line
;
10277 save
= input_line_pointer
;
10278 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10279 if (gotfree_input_line
)
10280 input_line_pointer
= gotfree_input_line
;
10284 if (gotfree_input_line
)
10286 /* expression () has merrily parsed up to the end of line,
10287 or a comma - in the wrong buffer. Transfer how far
10288 input_line_pointer has moved to the right buffer. */
10289 input_line_pointer
= (save
10290 + (input_line_pointer
- gotfree_input_line
)
10292 free (gotfree_input_line
);
10293 if (exp
->X_op
== O_constant
10294 || exp
->X_op
== O_absent
10295 || exp
->X_op
== O_illegal
10296 || exp
->X_op
== O_register
10297 || exp
->X_op
== O_big
)
10299 char c
= *input_line_pointer
;
10300 *input_line_pointer
= 0;
10301 as_bad (_("missing or invalid expression `%s'"), save
);
10302 *input_line_pointer
= c
;
10304 else if ((got_reloc
== BFD_RELOC_386_PLT32
10305 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10306 && exp
->X_op
!= O_symbol
)
10308 char c
= *input_line_pointer
;
10309 *input_line_pointer
= 0;
10310 as_bad (_("invalid PLT expression `%s'"), save
);
10311 *input_line_pointer
= c
;
10318 intel_syntax
= -intel_syntax
;
10321 i386_intel_simplify (exp
);
10327 signed_cons (int size
)
10329 if (flag_code
== CODE_64BIT
)
10337 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10344 if (exp
.X_op
== O_symbol
)
10345 exp
.X_op
= O_secrel
;
10347 emit_expr (&exp
, 4);
10349 while (*input_line_pointer
++ == ',');
10351 input_line_pointer
--;
10352 demand_empty_rest_of_line ();
10356 /* Handle Vector operations. */
10359 check_VecOperations (char *op_string
, char *op_end
)
10361 const reg_entry
*mask
;
10366 && (op_end
== NULL
|| op_string
< op_end
))
10369 if (*op_string
== '{')
10373 /* Check broadcasts. */
10374 if (strncmp (op_string
, "1to", 3) == 0)
10379 goto duplicated_vec_op
;
10382 if (*op_string
== '8')
10384 else if (*op_string
== '4')
10386 else if (*op_string
== '2')
10388 else if (*op_string
== '1'
10389 && *(op_string
+1) == '6')
10396 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10401 broadcast_op
.type
= bcst_type
;
10402 broadcast_op
.operand
= this_operand
;
10403 broadcast_op
.bytes
= 0;
10404 i
.broadcast
= &broadcast_op
;
10406 /* Check masking operation. */
10407 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10409 if (mask
== &bad_reg
)
10412 /* k0 can't be used for write mask. */
10413 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10415 as_bad (_("`%s%s' can't be used for write mask"),
10416 register_prefix
, mask
->reg_name
);
10422 mask_op
.mask
= mask
;
10423 mask_op
.zeroing
= 0;
10424 mask_op
.operand
= this_operand
;
10430 goto duplicated_vec_op
;
10432 i
.mask
->mask
= mask
;
10434 /* Only "{z}" is allowed here. No need to check
10435 zeroing mask explicitly. */
10436 if (i
.mask
->operand
!= this_operand
)
10438 as_bad (_("invalid write mask `%s'"), saved
);
10443 op_string
= end_op
;
10445 /* Check zeroing-flag for masking operation. */
10446 else if (*op_string
== 'z')
10450 mask_op
.mask
= NULL
;
10451 mask_op
.zeroing
= 1;
10452 mask_op
.operand
= this_operand
;
10457 if (i
.mask
->zeroing
)
10460 as_bad (_("duplicated `%s'"), saved
);
10464 i
.mask
->zeroing
= 1;
10466 /* Only "{%k}" is allowed here. No need to check mask
10467 register explicitly. */
10468 if (i
.mask
->operand
!= this_operand
)
10470 as_bad (_("invalid zeroing-masking `%s'"),
10479 goto unknown_vec_op
;
10481 if (*op_string
!= '}')
10483 as_bad (_("missing `}' in `%s'"), saved
);
10488 /* Strip whitespace since the addition of pseudo prefixes
10489 changed how the scrubber treats '{'. */
10490 if (is_space_char (*op_string
))
10496 /* We don't know this one. */
10497 as_bad (_("unknown vector operation: `%s'"), saved
);
10501 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10503 as_bad (_("zeroing-masking only allowed with write mask"));
10511 i386_immediate (char *imm_start
)
10513 char *save_input_line_pointer
;
10514 char *gotfree_input_line
;
10517 i386_operand_type types
;
10519 operand_type_set (&types
, ~0);
10521 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10523 as_bad (_("at most %d immediate operands are allowed"),
10524 MAX_IMMEDIATE_OPERANDS
);
10528 exp
= &im_expressions
[i
.imm_operands
++];
10529 i
.op
[this_operand
].imms
= exp
;
10531 if (is_space_char (*imm_start
))
10534 save_input_line_pointer
= input_line_pointer
;
10535 input_line_pointer
= imm_start
;
10537 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10538 if (gotfree_input_line
)
10539 input_line_pointer
= gotfree_input_line
;
10541 exp_seg
= expression (exp
);
10543 SKIP_WHITESPACE ();
10545 /* Handle vector operations. */
10546 if (*input_line_pointer
== '{')
10548 input_line_pointer
= check_VecOperations (input_line_pointer
,
10550 if (input_line_pointer
== NULL
)
10554 if (*input_line_pointer
)
10555 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10557 input_line_pointer
= save_input_line_pointer
;
10558 if (gotfree_input_line
)
10560 free (gotfree_input_line
);
10562 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10563 exp
->X_op
= O_illegal
;
10566 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10570 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10571 i386_operand_type types
, const char *imm_start
)
10573 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10576 as_bad (_("missing or invalid immediate expression `%s'"),
10580 else if (exp
->X_op
== O_constant
)
10582 /* Size it properly later. */
10583 i
.types
[this_operand
].bitfield
.imm64
= 1;
10584 /* If not 64bit, sign extend val. */
10585 if (flag_code
!= CODE_64BIT
10586 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10588 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10590 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10591 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10592 && exp_seg
!= absolute_section
10593 && exp_seg
!= text_section
10594 && exp_seg
!= data_section
10595 && exp_seg
!= bss_section
10596 && exp_seg
!= undefined_section
10597 && !bfd_is_com_section (exp_seg
))
10599 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10603 else if (!intel_syntax
&& exp_seg
== reg_section
)
10606 as_bad (_("illegal immediate register operand %s"), imm_start
);
10611 /* This is an address. The size of the address will be
10612 determined later, depending on destination register,
10613 suffix, or the default for the section. */
10614 i
.types
[this_operand
].bitfield
.imm8
= 1;
10615 i
.types
[this_operand
].bitfield
.imm16
= 1;
10616 i
.types
[this_operand
].bitfield
.imm32
= 1;
10617 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10618 i
.types
[this_operand
].bitfield
.imm64
= 1;
10619 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10627 i386_scale (char *scale
)
10630 char *save
= input_line_pointer
;
10632 input_line_pointer
= scale
;
10633 val
= get_absolute_expression ();
10638 i
.log2_scale_factor
= 0;
10641 i
.log2_scale_factor
= 1;
10644 i
.log2_scale_factor
= 2;
10647 i
.log2_scale_factor
= 3;
10651 char sep
= *input_line_pointer
;
10653 *input_line_pointer
= '\0';
10654 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10656 *input_line_pointer
= sep
;
10657 input_line_pointer
= save
;
10661 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10663 as_warn (_("scale factor of %d without an index register"),
10664 1 << i
.log2_scale_factor
);
10665 i
.log2_scale_factor
= 0;
10667 scale
= input_line_pointer
;
10668 input_line_pointer
= save
;
10673 i386_displacement (char *disp_start
, char *disp_end
)
10677 char *save_input_line_pointer
;
10678 char *gotfree_input_line
;
10680 i386_operand_type bigdisp
, types
= anydisp
;
10683 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10685 as_bad (_("at most %d displacement operands are allowed"),
10686 MAX_MEMORY_OPERANDS
);
10690 operand_type_set (&bigdisp
, 0);
10692 || i
.types
[this_operand
].bitfield
.baseindex
10693 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10694 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10696 i386_addressing_mode ();
10697 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10698 if (flag_code
== CODE_64BIT
)
10702 bigdisp
.bitfield
.disp32s
= 1;
10703 bigdisp
.bitfield
.disp64
= 1;
10706 bigdisp
.bitfield
.disp32
= 1;
10708 else if ((flag_code
== CODE_16BIT
) ^ override
)
10709 bigdisp
.bitfield
.disp16
= 1;
10711 bigdisp
.bitfield
.disp32
= 1;
10715 /* For PC-relative branches, the width of the displacement may be
10716 dependent upon data size, but is never dependent upon address size.
10717 Also make sure to not unintentionally match against a non-PC-relative
10718 branch template. */
10719 static templates aux_templates
;
10720 const insn_template
*t
= current_templates
->start
;
10721 bfd_boolean has_intel64
= FALSE
;
10723 aux_templates
.start
= t
;
10724 while (++t
< current_templates
->end
)
10726 if (t
->opcode_modifier
.jump
10727 != current_templates
->start
->opcode_modifier
.jump
)
10729 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10730 has_intel64
= TRUE
;
10732 if (t
< current_templates
->end
)
10734 aux_templates
.end
= t
;
10735 current_templates
= &aux_templates
;
10738 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10739 if (flag_code
== CODE_64BIT
)
10741 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10742 && (!intel64
|| !has_intel64
))
10743 bigdisp
.bitfield
.disp16
= 1;
10745 bigdisp
.bitfield
.disp32s
= 1;
10750 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10752 : LONG_MNEM_SUFFIX
));
10753 bigdisp
.bitfield
.disp32
= 1;
10754 if ((flag_code
== CODE_16BIT
) ^ override
)
10756 bigdisp
.bitfield
.disp32
= 0;
10757 bigdisp
.bitfield
.disp16
= 1;
10761 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10764 exp
= &disp_expressions
[i
.disp_operands
];
10765 i
.op
[this_operand
].disps
= exp
;
10767 save_input_line_pointer
= input_line_pointer
;
10768 input_line_pointer
= disp_start
;
10769 END_STRING_AND_SAVE (disp_end
);
10771 #ifndef GCC_ASM_O_HACK
10772 #define GCC_ASM_O_HACK 0
10775 END_STRING_AND_SAVE (disp_end
+ 1);
10776 if (i
.types
[this_operand
].bitfield
.baseIndex
10777 && displacement_string_end
[-1] == '+')
10779 /* This hack is to avoid a warning when using the "o"
10780 constraint within gcc asm statements.
10783 #define _set_tssldt_desc(n,addr,limit,type) \
10784 __asm__ __volatile__ ( \
10785 "movw %w2,%0\n\t" \
10786 "movw %w1,2+%0\n\t" \
10787 "rorl $16,%1\n\t" \
10788 "movb %b1,4+%0\n\t" \
10789 "movb %4,5+%0\n\t" \
10790 "movb $0,6+%0\n\t" \
10791 "movb %h1,7+%0\n\t" \
10793 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10795 This works great except that the output assembler ends
10796 up looking a bit weird if it turns out that there is
10797 no offset. You end up producing code that looks like:
10810 So here we provide the missing zero. */
10812 *displacement_string_end
= '0';
10815 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10816 if (gotfree_input_line
)
10817 input_line_pointer
= gotfree_input_line
;
10819 exp_seg
= expression (exp
);
10821 SKIP_WHITESPACE ();
10822 if (*input_line_pointer
)
10823 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10825 RESTORE_END_STRING (disp_end
+ 1);
10827 input_line_pointer
= save_input_line_pointer
;
10828 if (gotfree_input_line
)
10830 free (gotfree_input_line
);
10832 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10833 exp
->X_op
= O_illegal
;
10836 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10838 RESTORE_END_STRING (disp_end
);
10844 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10845 i386_operand_type types
, const char *disp_start
)
10847 i386_operand_type bigdisp
;
10850 /* We do this to make sure that the section symbol is in
10851 the symbol table. We will ultimately change the relocation
10852 to be relative to the beginning of the section. */
10853 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10854 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10855 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10857 if (exp
->X_op
!= O_symbol
)
10860 if (S_IS_LOCAL (exp
->X_add_symbol
)
10861 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10862 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10863 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10864 exp
->X_op
= O_subtract
;
10865 exp
->X_op_symbol
= GOT_symbol
;
10866 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10867 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10868 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10869 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10871 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10874 else if (exp
->X_op
== O_absent
10875 || exp
->X_op
== O_illegal
10876 || exp
->X_op
== O_big
)
10879 as_bad (_("missing or invalid displacement expression `%s'"),
10884 else if (flag_code
== CODE_64BIT
10885 && !i
.prefix
[ADDR_PREFIX
]
10886 && exp
->X_op
== O_constant
)
10888 /* Since displacement is signed extended to 64bit, don't allow
10889 disp32 and turn off disp32s if they are out of range. */
10890 i
.types
[this_operand
].bitfield
.disp32
= 0;
10891 if (!fits_in_signed_long (exp
->X_add_number
))
10893 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10894 if (i
.types
[this_operand
].bitfield
.baseindex
)
10896 as_bad (_("0x%lx out range of signed 32bit displacement"),
10897 (long) exp
->X_add_number
);
10903 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10904 else if (exp
->X_op
!= O_constant
10905 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10906 && exp_seg
!= absolute_section
10907 && exp_seg
!= text_section
10908 && exp_seg
!= data_section
10909 && exp_seg
!= bss_section
10910 && exp_seg
!= undefined_section
10911 && !bfd_is_com_section (exp_seg
))
10913 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10918 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10919 /* Constants get taken care of by optimize_disp(). */
10920 && exp
->X_op
!= O_constant
)
10921 i
.types
[this_operand
].bitfield
.disp8
= 1;
10923 /* Check if this is a displacement only operand. */
10924 bigdisp
= i
.types
[this_operand
];
10925 bigdisp
.bitfield
.disp8
= 0;
10926 bigdisp
.bitfield
.disp16
= 0;
10927 bigdisp
.bitfield
.disp32
= 0;
10928 bigdisp
.bitfield
.disp32s
= 0;
10929 bigdisp
.bitfield
.disp64
= 0;
10930 if (operand_type_all_zero (&bigdisp
))
10931 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10937 /* Return the active addressing mode, taking address override and
10938 registers forming the address into consideration. Update the
10939 address override prefix if necessary. */
10941 static enum flag_code
10942 i386_addressing_mode (void)
10944 enum flag_code addr_mode
;
10946 if (i
.prefix
[ADDR_PREFIX
])
10947 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10948 else if (flag_code
== CODE_16BIT
10949 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10950 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10951 from md_assemble() by "is not a valid base/index expression"
10952 when there is a base and/or index. */
10953 && !i
.types
[this_operand
].bitfield
.baseindex
)
10955 /* MPX insn memory operands with neither base nor index must be forced
10956 to use 32-bit addressing in 16-bit mode. */
10957 addr_mode
= CODE_32BIT
;
10958 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10960 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10961 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10965 addr_mode
= flag_code
;
10967 #if INFER_ADDR_PREFIX
10968 if (i
.mem_operands
== 0)
10970 /* Infer address prefix from the first memory operand. */
10971 const reg_entry
*addr_reg
= i
.base_reg
;
10973 if (addr_reg
== NULL
)
10974 addr_reg
= i
.index_reg
;
10978 if (addr_reg
->reg_type
.bitfield
.dword
)
10979 addr_mode
= CODE_32BIT
;
10980 else if (flag_code
!= CODE_64BIT
10981 && addr_reg
->reg_type
.bitfield
.word
)
10982 addr_mode
= CODE_16BIT
;
10984 if (addr_mode
!= flag_code
)
10986 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10988 /* Change the size of any displacement too. At most one
10989 of Disp16 or Disp32 is set.
10990 FIXME. There doesn't seem to be any real need for
10991 separate Disp16 and Disp32 flags. The same goes for
10992 Imm16 and Imm32. Removing them would probably clean
10993 up the code quite a lot. */
10994 if (flag_code
!= CODE_64BIT
10995 && (i
.types
[this_operand
].bitfield
.disp16
10996 || i
.types
[this_operand
].bitfield
.disp32
))
10997 i
.types
[this_operand
]
10998 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11008 /* Make sure the memory operand we've been dealt is valid.
11009 Return 1 on success, 0 on a failure. */
11012 i386_index_check (const char *operand_string
)
11014 const char *kind
= "base/index";
11015 enum flag_code addr_mode
= i386_addressing_mode ();
11017 if (current_templates
->start
->opcode_modifier
.isstring
11018 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
11019 && (current_templates
->end
[-1].opcode_modifier
.isstring
11020 || i
.mem_operands
))
11022 /* Memory operands of string insns are special in that they only allow
11023 a single register (rDI, rSI, or rBX) as their memory address. */
11024 const reg_entry
*expected_reg
;
11025 static const char *di_si
[][2] =
11031 static const char *bx
[] = { "ebx", "bx", "rbx" };
11033 kind
= "string address";
11035 if (current_templates
->start
->opcode_modifier
.repprefixok
)
11037 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11038 - IS_STRING_ES_OP0
;
11041 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11042 || ((!i
.mem_operands
!= !intel_syntax
)
11043 && current_templates
->end
[-1].operand_types
[1]
11044 .bitfield
.baseindex
))
11047 = (const reg_entry
*) str_hash_find (reg_hash
,
11048 di_si
[addr_mode
][op
== es_op
]);
11052 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11054 if (i
.base_reg
!= expected_reg
11056 || operand_type_check (i
.types
[this_operand
], disp
))
11058 /* The second memory operand must have the same size as
11062 && !((addr_mode
== CODE_64BIT
11063 && i
.base_reg
->reg_type
.bitfield
.qword
)
11064 || (addr_mode
== CODE_32BIT
11065 ? i
.base_reg
->reg_type
.bitfield
.dword
11066 : i
.base_reg
->reg_type
.bitfield
.word
)))
11069 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11071 intel_syntax
? '[' : '(',
11073 expected_reg
->reg_name
,
11074 intel_syntax
? ']' : ')');
11081 as_bad (_("`%s' is not a valid %s expression"),
11082 operand_string
, kind
);
11087 if (addr_mode
!= CODE_16BIT
)
11089 /* 32-bit/64-bit checks. */
11090 if (i
.disp_encoding
== disp_encoding_16bit
)
11093 as_bad (_("invalid `%s' prefix"),
11094 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11099 && ((addr_mode
== CODE_64BIT
11100 ? !i
.base_reg
->reg_type
.bitfield
.qword
11101 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11102 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11103 || i
.base_reg
->reg_num
== RegIZ
))
11105 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11106 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11107 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11108 && ((addr_mode
== CODE_64BIT
11109 ? !i
.index_reg
->reg_type
.bitfield
.qword
11110 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11111 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11114 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11115 if (current_templates
->start
->base_opcode
== 0xf30f1b
11116 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11117 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11119 /* They cannot use RIP-relative addressing. */
11120 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11122 as_bad (_("`%s' cannot be used here"), operand_string
);
11126 /* bndldx and bndstx ignore their scale factor. */
11127 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11128 && i
.log2_scale_factor
)
11129 as_warn (_("register scaling is being ignored here"));
11134 /* 16-bit checks. */
11135 if (i
.disp_encoding
== disp_encoding_32bit
)
11139 && (!i
.base_reg
->reg_type
.bitfield
.word
11140 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11142 && (!i
.index_reg
->reg_type
.bitfield
.word
11143 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11145 && i
.base_reg
->reg_num
< 6
11146 && i
.index_reg
->reg_num
>= 6
11147 && i
.log2_scale_factor
== 0))))
11154 /* Handle vector immediates. */
11157 RC_SAE_immediate (const char *imm_start
)
11159 unsigned int match_found
, j
;
11160 const char *pstr
= imm_start
;
11168 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11170 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11174 rc_op
.type
= RC_NamesTable
[j
].type
;
11175 rc_op
.operand
= this_operand
;
11176 i
.rounding
= &rc_op
;
11180 as_bad (_("duplicated `%s'"), imm_start
);
11183 pstr
+= RC_NamesTable
[j
].len
;
11191 if (*pstr
++ != '}')
11193 as_bad (_("Missing '}': '%s'"), imm_start
);
11196 /* RC/SAE immediate string should contain nothing more. */;
11199 as_bad (_("Junk after '}': '%s'"), imm_start
);
11203 exp
= &im_expressions
[i
.imm_operands
++];
11204 i
.op
[this_operand
].imms
= exp
;
11206 exp
->X_op
= O_constant
;
11207 exp
->X_add_number
= 0;
11208 exp
->X_add_symbol
= (symbolS
*) 0;
11209 exp
->X_op_symbol
= (symbolS
*) 0;
11211 i
.types
[this_operand
].bitfield
.imm8
= 1;
11215 /* Only string instructions can have a second memory operand, so
11216 reduce current_templates to just those if it contains any. */
11218 maybe_adjust_templates (void)
11220 const insn_template
*t
;
11222 gas_assert (i
.mem_operands
== 1);
11224 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11225 if (t
->opcode_modifier
.isstring
)
11228 if (t
< current_templates
->end
)
11230 static templates aux_templates
;
11231 bfd_boolean recheck
;
11233 aux_templates
.start
= t
;
11234 for (; t
< current_templates
->end
; ++t
)
11235 if (!t
->opcode_modifier
.isstring
)
11237 aux_templates
.end
= t
;
11239 /* Determine whether to re-check the first memory operand. */
11240 recheck
= (aux_templates
.start
!= current_templates
->start
11241 || t
!= current_templates
->end
);
11243 current_templates
= &aux_templates
;
11247 i
.mem_operands
= 0;
11248 if (i
.memop1_string
!= NULL
11249 && i386_index_check (i
.memop1_string
) == 0)
11251 i
.mem_operands
= 1;
11258 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11262 i386_att_operand (char *operand_string
)
11264 const reg_entry
*r
;
11266 char *op_string
= operand_string
;
11268 if (is_space_char (*op_string
))
11271 /* We check for an absolute prefix (differentiating,
11272 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11273 if (*op_string
== ABSOLUTE_PREFIX
)
11276 if (is_space_char (*op_string
))
11278 i
.jumpabsolute
= TRUE
;
11281 /* Check if operand is a register. */
11282 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11284 i386_operand_type temp
;
11289 /* Check for a segment override by searching for ':' after a
11290 segment register. */
11291 op_string
= end_op
;
11292 if (is_space_char (*op_string
))
11294 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11296 switch (r
->reg_num
)
11299 i
.seg
[i
.mem_operands
] = &es
;
11302 i
.seg
[i
.mem_operands
] = &cs
;
11305 i
.seg
[i
.mem_operands
] = &ss
;
11308 i
.seg
[i
.mem_operands
] = &ds
;
11311 i
.seg
[i
.mem_operands
] = &fs
;
11314 i
.seg
[i
.mem_operands
] = &gs
;
11318 /* Skip the ':' and whitespace. */
11320 if (is_space_char (*op_string
))
11323 if (!is_digit_char (*op_string
)
11324 && !is_identifier_char (*op_string
)
11325 && *op_string
!= '('
11326 && *op_string
!= ABSOLUTE_PREFIX
)
11328 as_bad (_("bad memory operand `%s'"), op_string
);
11331 /* Handle case of %es:*foo. */
11332 if (*op_string
== ABSOLUTE_PREFIX
)
11335 if (is_space_char (*op_string
))
11337 i
.jumpabsolute
= TRUE
;
11339 goto do_memory_reference
;
11342 /* Handle vector operations. */
11343 if (*op_string
== '{')
11345 op_string
= check_VecOperations (op_string
, NULL
);
11346 if (op_string
== NULL
)
11352 as_bad (_("junk `%s' after register"), op_string
);
11355 temp
= r
->reg_type
;
11356 temp
.bitfield
.baseindex
= 0;
11357 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11359 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11360 i
.op
[this_operand
].regs
= r
;
11363 else if (*op_string
== REGISTER_PREFIX
)
11365 as_bad (_("bad register name `%s'"), op_string
);
11368 else if (*op_string
== IMMEDIATE_PREFIX
)
11371 if (i
.jumpabsolute
)
11373 as_bad (_("immediate operand illegal with absolute jump"));
11376 if (!i386_immediate (op_string
))
11379 else if (RC_SAE_immediate (operand_string
))
11381 /* If it is a RC or SAE immediate, do nothing. */
11384 else if (is_digit_char (*op_string
)
11385 || is_identifier_char (*op_string
)
11386 || *op_string
== '"'
11387 || *op_string
== '(')
11389 /* This is a memory reference of some sort. */
11392 /* Start and end of displacement string expression (if found). */
11393 char *displacement_string_start
;
11394 char *displacement_string_end
;
11397 do_memory_reference
:
11398 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11400 if ((i
.mem_operands
== 1
11401 && !current_templates
->start
->opcode_modifier
.isstring
)
11402 || i
.mem_operands
== 2)
11404 as_bad (_("too many memory references for `%s'"),
11405 current_templates
->start
->name
);
11409 /* Check for base index form. We detect the base index form by
11410 looking for an ')' at the end of the operand, searching
11411 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11413 base_string
= op_string
+ strlen (op_string
);
11415 /* Handle vector operations. */
11416 vop_start
= strchr (op_string
, '{');
11417 if (vop_start
&& vop_start
< base_string
)
11419 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11421 base_string
= vop_start
;
11425 if (is_space_char (*base_string
))
11428 /* If we only have a displacement, set-up for it to be parsed later. */
11429 displacement_string_start
= op_string
;
11430 displacement_string_end
= base_string
+ 1;
11432 if (*base_string
== ')')
11435 unsigned int parens_balanced
= 1;
11436 /* We've already checked that the number of left & right ()'s are
11437 equal, so this loop will not be infinite. */
11441 if (*base_string
== ')')
11443 if (*base_string
== '(')
11446 while (parens_balanced
);
11448 temp_string
= base_string
;
11450 /* Skip past '(' and whitespace. */
11452 if (is_space_char (*base_string
))
11455 if (*base_string
== ','
11456 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11459 displacement_string_end
= temp_string
;
11461 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11465 if (i
.base_reg
== &bad_reg
)
11467 base_string
= end_op
;
11468 if (is_space_char (*base_string
))
11472 /* There may be an index reg or scale factor here. */
11473 if (*base_string
== ',')
11476 if (is_space_char (*base_string
))
11479 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11482 if (i
.index_reg
== &bad_reg
)
11484 base_string
= end_op
;
11485 if (is_space_char (*base_string
))
11487 if (*base_string
== ',')
11490 if (is_space_char (*base_string
))
11493 else if (*base_string
!= ')')
11495 as_bad (_("expecting `,' or `)' "
11496 "after index register in `%s'"),
11501 else if (*base_string
== REGISTER_PREFIX
)
11503 end_op
= strchr (base_string
, ',');
11506 as_bad (_("bad register name `%s'"), base_string
);
11510 /* Check for scale factor. */
11511 if (*base_string
!= ')')
11513 char *end_scale
= i386_scale (base_string
);
11518 base_string
= end_scale
;
11519 if (is_space_char (*base_string
))
11521 if (*base_string
!= ')')
11523 as_bad (_("expecting `)' "
11524 "after scale factor in `%s'"),
11529 else if (!i
.index_reg
)
11531 as_bad (_("expecting index register or scale factor "
11532 "after `,'; got '%c'"),
11537 else if (*base_string
!= ')')
11539 as_bad (_("expecting `,' or `)' "
11540 "after base register in `%s'"),
11545 else if (*base_string
== REGISTER_PREFIX
)
11547 end_op
= strchr (base_string
, ',');
11550 as_bad (_("bad register name `%s'"), base_string
);
11555 /* If there's an expression beginning the operand, parse it,
11556 assuming displacement_string_start and
11557 displacement_string_end are meaningful. */
11558 if (displacement_string_start
!= displacement_string_end
)
11560 if (!i386_displacement (displacement_string_start
,
11561 displacement_string_end
))
11565 /* Special case for (%dx) while doing input/output op. */
11567 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11568 && i
.base_reg
->reg_type
.bitfield
.word
11569 && i
.index_reg
== 0
11570 && i
.log2_scale_factor
== 0
11571 && i
.seg
[i
.mem_operands
] == 0
11572 && !operand_type_check (i
.types
[this_operand
], disp
))
11574 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11578 if (i386_index_check (operand_string
) == 0)
11580 i
.flags
[this_operand
] |= Operand_Mem
;
11581 if (i
.mem_operands
== 0)
11582 i
.memop1_string
= xstrdup (operand_string
);
11587 /* It's not a memory operand; argh! */
11588 as_bad (_("invalid char %s beginning operand %d `%s'"),
11589 output_invalid (*op_string
),
11594 return 1; /* Normal return. */
11597 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11598 that an rs_machine_dependent frag may reach. */
11601 i386_frag_max_var (fragS
*frag
)
11603 /* The only relaxable frags are for jumps.
11604 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11605 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11606 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11609 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11611 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11613 /* STT_GNU_IFUNC symbol must go through PLT. */
11614 if ((symbol_get_bfdsym (fr_symbol
)->flags
11615 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11618 if (!S_IS_EXTERNAL (fr_symbol
))
11619 /* Symbol may be weak or local. */
11620 return !S_IS_WEAK (fr_symbol
);
11622 /* Global symbols with non-default visibility can't be preempted. */
11623 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11626 if (fr_var
!= NO_RELOC
)
11627 switch ((enum bfd_reloc_code_real
) fr_var
)
11629 case BFD_RELOC_386_PLT32
:
11630 case BFD_RELOC_X86_64_PLT32
:
11631 /* Symbol with PLT relocation may be preempted. */
11637 /* Global symbols with default visibility in a shared library may be
11638 preempted by another definition. */
11643 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11644 Note also work for Skylake and Cascadelake.
11645 ---------------------------------------------------------------------
11646 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11647 | ------ | ----------- | ------- | -------- |
11649 | Jno | N | N | Y |
11650 | Jc/Jb | Y | N | Y |
11651 | Jae/Jnb | Y | N | Y |
11652 | Je/Jz | Y | Y | Y |
11653 | Jne/Jnz | Y | Y | Y |
11654 | Jna/Jbe | Y | N | Y |
11655 | Ja/Jnbe | Y | N | Y |
11657 | Jns | N | N | Y |
11658 | Jp/Jpe | N | N | Y |
11659 | Jnp/Jpo | N | N | Y |
11660 | Jl/Jnge | Y | Y | Y |
11661 | Jge/Jnl | Y | Y | Y |
11662 | Jle/Jng | Y | Y | Y |
11663 | Jg/Jnle | Y | Y | Y |
11664 --------------------------------------------------------------------- */
11666 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11668 if (mf_cmp
== mf_cmp_alu_cmp
)
11669 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11670 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11671 if (mf_cmp
== mf_cmp_incdec
)
11672 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11673 || mf_jcc
== mf_jcc_jle
);
11674 if (mf_cmp
== mf_cmp_test_and
)
11679 /* Return the next non-empty frag. */
11682 i386_next_non_empty_frag (fragS
*fragP
)
11684 /* There may be a frag with a ".fill 0" when there is no room in
11685 the current frag for frag_grow in output_insn. */
11686 for (fragP
= fragP
->fr_next
;
11688 && fragP
->fr_type
== rs_fill
11689 && fragP
->fr_fix
== 0);
11690 fragP
= fragP
->fr_next
)
11695 /* Return the next jcc frag after BRANCH_PADDING. */
11698 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11700 fragS
*branch_fragP
;
11704 if (pad_fragP
->fr_type
== rs_machine_dependent
11705 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11706 == BRANCH_PADDING
))
11708 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11709 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11711 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11712 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11713 pad_fragP
->tc_frag_data
.mf_type
))
11714 return branch_fragP
;
11720 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11723 i386_classify_machine_dependent_frag (fragS
*fragP
)
11727 fragS
*branch_fragP
;
11729 unsigned int max_prefix_length
;
11731 if (fragP
->tc_frag_data
.classified
)
11734 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11735 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11736 for (next_fragP
= fragP
;
11737 next_fragP
!= NULL
;
11738 next_fragP
= next_fragP
->fr_next
)
11740 next_fragP
->tc_frag_data
.classified
= 1;
11741 if (next_fragP
->fr_type
== rs_machine_dependent
)
11742 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11744 case BRANCH_PADDING
:
11745 /* The BRANCH_PADDING frag must be followed by a branch
11747 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11748 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11750 case FUSED_JCC_PADDING
:
11751 /* Check if this is a fused jcc:
11753 CMP like instruction
11757 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11758 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11759 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11762 /* The BRANCH_PADDING frag is merged with the
11763 FUSED_JCC_PADDING frag. */
11764 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11765 /* CMP like instruction size. */
11766 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11767 frag_wane (pad_fragP
);
11768 /* Skip to branch_fragP. */
11769 next_fragP
= branch_fragP
;
11771 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11773 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11775 next_fragP
->fr_subtype
11776 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11777 next_fragP
->tc_frag_data
.max_bytes
11778 = next_fragP
->tc_frag_data
.max_prefix_length
;
11779 /* This will be updated in the BRANCH_PREFIX scan. */
11780 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11783 frag_wane (next_fragP
);
11788 /* Stop if there is no BRANCH_PREFIX. */
11789 if (!align_branch_prefix_size
)
11792 /* Scan for BRANCH_PREFIX. */
11793 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11795 if (fragP
->fr_type
!= rs_machine_dependent
11796 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11800 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11801 COND_JUMP_PREFIX. */
11802 max_prefix_length
= 0;
11803 for (next_fragP
= fragP
;
11804 next_fragP
!= NULL
;
11805 next_fragP
= next_fragP
->fr_next
)
11807 if (next_fragP
->fr_type
== rs_fill
)
11808 /* Skip rs_fill frags. */
11810 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11811 /* Stop for all other frags. */
11814 /* rs_machine_dependent frags. */
11815 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11818 /* Count BRANCH_PREFIX frags. */
11819 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11821 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11822 frag_wane (next_fragP
);
11826 += next_fragP
->tc_frag_data
.max_bytes
;
11828 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11830 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11831 == FUSED_JCC_PADDING
))
11833 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11834 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11838 /* Stop for other rs_machine_dependent frags. */
11842 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11844 /* Skip to the next frag. */
11845 fragP
= next_fragP
;
11849 /* Compute padding size for
11852 CMP like instruction
11854 COND_JUMP/UNCOND_JUMP
11859 COND_JUMP/UNCOND_JUMP
11863 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11865 unsigned int offset
, size
, padding_size
;
11866 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11868 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11870 address
= fragP
->fr_address
;
11871 address
+= fragP
->fr_fix
;
11873 /* CMP like instrunction size. */
11874 size
= fragP
->tc_frag_data
.cmp_size
;
11876 /* The base size of the branch frag. */
11877 size
+= branch_fragP
->fr_fix
;
11879 /* Add opcode and displacement bytes for the rs_machine_dependent
11881 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11882 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11884 /* Check if branch is within boundary and doesn't end at the last
11886 offset
= address
& ((1U << align_branch_power
) - 1);
11887 if ((offset
+ size
) >= (1U << align_branch_power
))
11888 /* Padding needed to avoid crossing boundary. */
11889 padding_size
= (1U << align_branch_power
) - offset
;
11891 /* No padding needed. */
11894 /* The return value may be saved in tc_frag_data.length which is
11896 if (!fits_in_unsigned_byte (padding_size
))
11899 return padding_size
;
11902 /* i386_generic_table_relax_frag()
11904 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11905 grow/shrink padding to align branch frags. Hand others to
11909 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11911 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11912 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11914 long padding_size
= i386_branch_padding_size (fragP
, 0);
11915 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11917 /* When the BRANCH_PREFIX frag is used, the computed address
11918 must match the actual address and there should be no padding. */
11919 if (fragP
->tc_frag_data
.padding_address
11920 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11924 /* Update the padding size. */
11926 fragP
->tc_frag_data
.length
= padding_size
;
11930 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11932 fragS
*padding_fragP
, *next_fragP
;
11933 long padding_size
, left_size
, last_size
;
11935 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11936 if (!padding_fragP
)
11937 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11938 return (fragP
->tc_frag_data
.length
11939 - fragP
->tc_frag_data
.last_length
);
11941 /* Compute the relative address of the padding frag in the very
11942 first time where the BRANCH_PREFIX frag sizes are zero. */
11943 if (!fragP
->tc_frag_data
.padding_address
)
11944 fragP
->tc_frag_data
.padding_address
11945 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11947 /* First update the last length from the previous interation. */
11948 left_size
= fragP
->tc_frag_data
.prefix_length
;
11949 for (next_fragP
= fragP
;
11950 next_fragP
!= padding_fragP
;
11951 next_fragP
= next_fragP
->fr_next
)
11952 if (next_fragP
->fr_type
== rs_machine_dependent
11953 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11958 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11962 if (max
> left_size
)
11967 next_fragP
->tc_frag_data
.last_length
= size
;
11971 next_fragP
->tc_frag_data
.last_length
= 0;
11974 /* Check the padding size for the padding frag. */
11975 padding_size
= i386_branch_padding_size
11976 (padding_fragP
, (fragP
->fr_address
11977 + fragP
->tc_frag_data
.padding_address
));
11979 last_size
= fragP
->tc_frag_data
.prefix_length
;
11980 /* Check if there is change from the last interation. */
11981 if (padding_size
== last_size
)
11983 /* Update the expected address of the padding frag. */
11984 padding_fragP
->tc_frag_data
.padding_address
11985 = (fragP
->fr_address
+ padding_size
11986 + fragP
->tc_frag_data
.padding_address
);
11990 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11992 /* No padding if there is no sufficient room. Clear the
11993 expected address of the padding frag. */
11994 padding_fragP
->tc_frag_data
.padding_address
= 0;
11998 /* Store the expected address of the padding frag. */
11999 padding_fragP
->tc_frag_data
.padding_address
12000 = (fragP
->fr_address
+ padding_size
12001 + fragP
->tc_frag_data
.padding_address
);
12003 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12005 /* Update the length for the current interation. */
12006 left_size
= padding_size
;
12007 for (next_fragP
= fragP
;
12008 next_fragP
!= padding_fragP
;
12009 next_fragP
= next_fragP
->fr_next
)
12010 if (next_fragP
->fr_type
== rs_machine_dependent
12011 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12016 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12020 if (max
> left_size
)
12025 next_fragP
->tc_frag_data
.length
= size
;
12029 next_fragP
->tc_frag_data
.length
= 0;
12032 return (fragP
->tc_frag_data
.length
12033 - fragP
->tc_frag_data
.last_length
);
12035 return relax_frag (segment
, fragP
, stretch
);
12038 /* md_estimate_size_before_relax()
12040 Called just before relax() for rs_machine_dependent frags. The x86
12041 assembler uses these frags to handle variable size jump
12044 Any symbol that is now undefined will not become defined.
12045 Return the correct fr_subtype in the frag.
12046 Return the initial "guess for variable size of frag" to caller.
12047 The guess is actually the growth beyond the fixed part. Whatever
12048 we do to grow the fixed or variable part contributes to our
12052 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12054 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12055 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12056 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12058 i386_classify_machine_dependent_frag (fragP
);
12059 return fragP
->tc_frag_data
.length
;
12062 /* We've already got fragP->fr_subtype right; all we have to do is
12063 check for un-relaxable symbols. On an ELF system, we can't relax
12064 an externally visible symbol, because it may be overridden by a
12066 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12069 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12072 #if defined (OBJ_COFF) && defined (TE_PE)
12073 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12074 && S_IS_WEAK (fragP
->fr_symbol
))
12078 /* Symbol is undefined in this segment, or we need to keep a
12079 reloc so that weak symbols can be overridden. */
12080 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12081 enum bfd_reloc_code_real reloc_type
;
12082 unsigned char *opcode
;
12085 if (fragP
->fr_var
!= NO_RELOC
)
12086 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12087 else if (size
== 2)
12088 reloc_type
= BFD_RELOC_16_PCREL
;
12089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12090 else if (need_plt32_p (fragP
->fr_symbol
))
12091 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12094 reloc_type
= BFD_RELOC_32_PCREL
;
12096 old_fr_fix
= fragP
->fr_fix
;
12097 opcode
= (unsigned char *) fragP
->fr_opcode
;
12099 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12102 /* Make jmp (0xeb) a (d)word displacement jump. */
12104 fragP
->fr_fix
+= size
;
12105 fix_new (fragP
, old_fr_fix
, size
,
12107 fragP
->fr_offset
, 1,
12113 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12115 /* Negate the condition, and branch past an
12116 unconditional jump. */
12119 /* Insert an unconditional jump. */
12121 /* We added two extra opcode bytes, and have a two byte
12123 fragP
->fr_fix
+= 2 + 2;
12124 fix_new (fragP
, old_fr_fix
+ 2, 2,
12126 fragP
->fr_offset
, 1,
12130 /* Fall through. */
12133 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12137 fragP
->fr_fix
+= 1;
12138 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12140 fragP
->fr_offset
, 1,
12141 BFD_RELOC_8_PCREL
);
12142 fixP
->fx_signed
= 1;
12146 /* This changes the byte-displacement jump 0x7N
12147 to the (d)word-displacement jump 0x0f,0x8N. */
12148 opcode
[1] = opcode
[0] + 0x10;
12149 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12150 /* We've added an opcode byte. */
12151 fragP
->fr_fix
+= 1 + size
;
12152 fix_new (fragP
, old_fr_fix
+ 1, size
,
12154 fragP
->fr_offset
, 1,
12159 BAD_CASE (fragP
->fr_subtype
);
12163 return fragP
->fr_fix
- old_fr_fix
;
12166 /* Guess size depending on current relax state. Initially the relax
12167 state will correspond to a short jump and we return 1, because
12168 the variable part of the frag (the branch offset) is one byte
12169 long. However, we can relax a section more than once and in that
12170 case we must either set fr_subtype back to the unrelaxed state,
12171 or return the value for the appropriate branch. */
12172 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12175 /* Called after relax() is finished.
12177 In: Address of frag.
12178 fr_type == rs_machine_dependent.
12179 fr_subtype is what the address relaxed to.
12181 Out: Any fixSs and constants are set up.
12182 Caller will turn frag into a ".space 0". */
12185 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12188 unsigned char *opcode
;
12189 unsigned char *where_to_put_displacement
= NULL
;
12190 offsetT target_address
;
12191 offsetT opcode_address
;
12192 unsigned int extension
= 0;
12193 offsetT displacement_from_opcode_start
;
12195 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12196 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12197 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12199 /* Generate nop padding. */
12200 unsigned int size
= fragP
->tc_frag_data
.length
;
12203 if (size
> fragP
->tc_frag_data
.max_bytes
)
12209 const char *branch
= "branch";
12210 const char *prefix
= "";
12211 fragS
*padding_fragP
;
12212 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12215 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12216 switch (fragP
->tc_frag_data
.default_prefix
)
12221 case CS_PREFIX_OPCODE
:
12224 case DS_PREFIX_OPCODE
:
12227 case ES_PREFIX_OPCODE
:
12230 case FS_PREFIX_OPCODE
:
12233 case GS_PREFIX_OPCODE
:
12236 case SS_PREFIX_OPCODE
:
12241 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12242 "%s within %d-byte boundary\n");
12244 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12245 "align %s within %d-byte boundary\n");
12249 padding_fragP
= fragP
;
12250 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12251 "%s within %d-byte boundary\n");
12255 switch (padding_fragP
->tc_frag_data
.branch_type
)
12257 case align_branch_jcc
:
12260 case align_branch_fused
:
12261 branch
= "fused jcc";
12263 case align_branch_jmp
:
12266 case align_branch_call
:
12269 case align_branch_indirect
:
12270 branch
= "indiret branch";
12272 case align_branch_ret
:
12279 fprintf (stdout
, msg
,
12280 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12281 (long long) fragP
->fr_address
, branch
,
12282 1 << align_branch_power
);
12284 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12285 memset (fragP
->fr_opcode
,
12286 fragP
->tc_frag_data
.default_prefix
, size
);
12288 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12290 fragP
->fr_fix
+= size
;
12295 opcode
= (unsigned char *) fragP
->fr_opcode
;
12297 /* Address we want to reach in file space. */
12298 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12300 /* Address opcode resides at in file space. */
12301 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12303 /* Displacement from opcode start to fill into instruction. */
12304 displacement_from_opcode_start
= target_address
- opcode_address
;
12306 if ((fragP
->fr_subtype
& BIG
) == 0)
12308 /* Don't have to change opcode. */
12309 extension
= 1; /* 1 opcode + 1 displacement */
12310 where_to_put_displacement
= &opcode
[1];
12314 if (no_cond_jump_promotion
12315 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12316 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12317 _("long jump required"));
12319 switch (fragP
->fr_subtype
)
12321 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12322 extension
= 4; /* 1 opcode + 4 displacement */
12324 where_to_put_displacement
= &opcode
[1];
12327 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12328 extension
= 2; /* 1 opcode + 2 displacement */
12330 where_to_put_displacement
= &opcode
[1];
12333 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12334 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12335 extension
= 5; /* 2 opcode + 4 displacement */
12336 opcode
[1] = opcode
[0] + 0x10;
12337 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12338 where_to_put_displacement
= &opcode
[2];
12341 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12342 extension
= 3; /* 2 opcode + 2 displacement */
12343 opcode
[1] = opcode
[0] + 0x10;
12344 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12345 where_to_put_displacement
= &opcode
[2];
12348 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12353 where_to_put_displacement
= &opcode
[3];
12357 BAD_CASE (fragP
->fr_subtype
);
12362 /* If size if less then four we are sure that the operand fits,
12363 but if it's 4, then it could be that the displacement is larger
12365 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12367 && ((addressT
) (displacement_from_opcode_start
- extension
12368 + ((addressT
) 1 << 31))
12369 > (((addressT
) 2 << 31) - 1)))
12371 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12372 _("jump target out of range"));
12373 /* Make us emit 0. */
12374 displacement_from_opcode_start
= extension
;
12376 /* Now put displacement after opcode. */
12377 md_number_to_chars ((char *) where_to_put_displacement
,
12378 (valueT
) (displacement_from_opcode_start
- extension
),
12379 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12380 fragP
->fr_fix
+= extension
;
12383 /* Apply a fixup (fixP) to segment data, once it has been determined
12384 by our caller that we have all the info we need to fix it up.
12386 Parameter valP is the pointer to the value of the bits.
12388 On the 386, immediates, displacements, and data pointers are all in
12389 the same (little-endian) format, so we don't need to care about which
12390 we are handling. */
12393 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12395 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12396 valueT value
= *valP
;
12398 #if !defined (TE_Mach)
12399 if (fixP
->fx_pcrel
)
12401 switch (fixP
->fx_r_type
)
12407 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12410 case BFD_RELOC_X86_64_32S
:
12411 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12414 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12417 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12422 if (fixP
->fx_addsy
!= NULL
12423 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12424 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12425 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12426 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12427 && !use_rela_relocations
)
12429 /* This is a hack. There should be a better way to handle this.
12430 This covers for the fact that bfd_install_relocation will
12431 subtract the current location (for partial_inplace, PC relative
12432 relocations); see more below. */
12436 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12439 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12444 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12446 if ((sym_seg
== seg
12447 || (symbol_section_p (fixP
->fx_addsy
)
12448 && sym_seg
!= absolute_section
))
12449 && !generic_force_reloc (fixP
))
12451 /* Yes, we add the values in twice. This is because
12452 bfd_install_relocation subtracts them out again. I think
12453 bfd_install_relocation is broken, but I don't dare change
12455 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12459 #if defined (OBJ_COFF) && defined (TE_PE)
12460 /* For some reason, the PE format does not store a
12461 section address offset for a PC relative symbol. */
12462 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12463 || S_IS_WEAK (fixP
->fx_addsy
))
12464 value
+= md_pcrel_from (fixP
);
12467 #if defined (OBJ_COFF) && defined (TE_PE)
12468 if (fixP
->fx_addsy
!= NULL
12469 && S_IS_WEAK (fixP
->fx_addsy
)
12470 /* PR 16858: Do not modify weak function references. */
12471 && ! fixP
->fx_pcrel
)
12473 #if !defined (TE_PEP)
12474 /* For x86 PE weak function symbols are neither PC-relative
12475 nor do they set S_IS_FUNCTION. So the only reliable way
12476 to detect them is to check the flags of their containing
12478 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12479 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12483 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12487 /* Fix a few things - the dynamic linker expects certain values here,
12488 and we must not disappoint it. */
12489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12490 if (IS_ELF
&& fixP
->fx_addsy
)
12491 switch (fixP
->fx_r_type
)
12493 case BFD_RELOC_386_PLT32
:
12494 case BFD_RELOC_X86_64_PLT32
:
12495 /* Make the jump instruction point to the address of the operand.
12496 At runtime we merely add the offset to the actual PLT entry.
12497 NB: Subtract the offset size only for jump instructions. */
12498 if (fixP
->fx_pcrel
)
12502 case BFD_RELOC_386_TLS_GD
:
12503 case BFD_RELOC_386_TLS_LDM
:
12504 case BFD_RELOC_386_TLS_IE_32
:
12505 case BFD_RELOC_386_TLS_IE
:
12506 case BFD_RELOC_386_TLS_GOTIE
:
12507 case BFD_RELOC_386_TLS_GOTDESC
:
12508 case BFD_RELOC_X86_64_TLSGD
:
12509 case BFD_RELOC_X86_64_TLSLD
:
12510 case BFD_RELOC_X86_64_GOTTPOFF
:
12511 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12512 value
= 0; /* Fully resolved at runtime. No addend. */
12514 case BFD_RELOC_386_TLS_LE
:
12515 case BFD_RELOC_386_TLS_LDO_32
:
12516 case BFD_RELOC_386_TLS_LE_32
:
12517 case BFD_RELOC_X86_64_DTPOFF32
:
12518 case BFD_RELOC_X86_64_DTPOFF64
:
12519 case BFD_RELOC_X86_64_TPOFF32
:
12520 case BFD_RELOC_X86_64_TPOFF64
:
12521 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12524 case BFD_RELOC_386_TLS_DESC_CALL
:
12525 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12526 value
= 0; /* Fully resolved at runtime. No addend. */
12527 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12531 case BFD_RELOC_VTABLE_INHERIT
:
12532 case BFD_RELOC_VTABLE_ENTRY
:
12539 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12541 #endif /* !defined (TE_Mach) */
12543 /* Are we finished with this relocation now? */
12544 if (fixP
->fx_addsy
== NULL
)
12546 #if defined (OBJ_COFF) && defined (TE_PE)
12547 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12550 /* Remember value for tc_gen_reloc. */
12551 fixP
->fx_addnumber
= value
;
12552 /* Clear out the frag for now. */
12556 else if (use_rela_relocations
)
12558 fixP
->fx_no_overflow
= 1;
12559 /* Remember value for tc_gen_reloc. */
12560 fixP
->fx_addnumber
= value
;
12564 md_number_to_chars (p
, value
, fixP
->fx_size
);
12568 md_atof (int type
, char *litP
, int *sizeP
)
12570 /* This outputs the LITTLENUMs in REVERSE order;
12571 in accord with the bigendian 386. */
12572 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12575 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12578 output_invalid (int c
)
12581 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12584 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12585 "(0x%x)", (unsigned char) c
);
12586 return output_invalid_buf
;
12589 /* Verify that @r can be used in the current context. */
12591 static bfd_boolean
check_register (const reg_entry
*r
)
12593 if (allow_pseudo_reg
)
12596 if (operand_type_all_zero (&r
->reg_type
))
12599 if ((r
->reg_type
.bitfield
.dword
12600 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12601 || r
->reg_type
.bitfield
.class == RegCR
12602 || r
->reg_type
.bitfield
.class == RegDR
)
12603 && !cpu_arch_flags
.bitfield
.cpui386
)
12606 if (r
->reg_type
.bitfield
.class == RegTR
12607 && (flag_code
== CODE_64BIT
12608 || !cpu_arch_flags
.bitfield
.cpui386
12609 || cpu_arch_isa_flags
.bitfield
.cpui586
12610 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12613 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12616 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12618 if (r
->reg_type
.bitfield
.zmmword
12619 || r
->reg_type
.bitfield
.class == RegMask
)
12622 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12624 if (r
->reg_type
.bitfield
.ymmword
)
12627 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12632 if (r
->reg_type
.bitfield
.tmmword
12633 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12634 || flag_code
!= CODE_64BIT
))
12637 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12640 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12641 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12644 /* Upper 16 vector registers are only available with VREX in 64bit
12645 mode, and require EVEX encoding. */
12646 if (r
->reg_flags
& RegVRex
)
12648 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12649 || flag_code
!= CODE_64BIT
)
12652 if (i
.vec_encoding
== vex_encoding_default
)
12653 i
.vec_encoding
= vex_encoding_evex
;
12654 else if (i
.vec_encoding
!= vex_encoding_evex
)
12655 i
.vec_encoding
= vex_encoding_error
;
12658 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12659 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12660 && flag_code
!= CODE_64BIT
)
12663 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12670 /* REG_STRING starts *before* REGISTER_PREFIX. */
12672 static const reg_entry
*
12673 parse_real_register (char *reg_string
, char **end_op
)
12675 char *s
= reg_string
;
12677 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12678 const reg_entry
*r
;
12680 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12681 if (*s
== REGISTER_PREFIX
)
12684 if (is_space_char (*s
))
12687 p
= reg_name_given
;
12688 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12690 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12691 return (const reg_entry
*) NULL
;
12695 /* For naked regs, make sure that we are not dealing with an identifier.
12696 This prevents confusing an identifier like `eax_var' with register
12698 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12699 return (const reg_entry
*) NULL
;
12703 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12705 /* Handle floating point regs, allowing spaces in the (i) part. */
12706 if (r
== i386_regtab
/* %st is first entry of table */)
12708 if (!cpu_arch_flags
.bitfield
.cpu8087
12709 && !cpu_arch_flags
.bitfield
.cpu287
12710 && !cpu_arch_flags
.bitfield
.cpu387
12711 && !allow_pseudo_reg
)
12712 return (const reg_entry
*) NULL
;
12714 if (is_space_char (*s
))
12719 if (is_space_char (*s
))
12721 if (*s
>= '0' && *s
<= '7')
12723 int fpr
= *s
- '0';
12725 if (is_space_char (*s
))
12730 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12735 /* We have "%st(" then garbage. */
12736 return (const reg_entry
*) NULL
;
12740 return r
&& check_register (r
) ? r
: NULL
;
12743 /* REG_STRING starts *before* REGISTER_PREFIX. */
12745 static const reg_entry
*
12746 parse_register (char *reg_string
, char **end_op
)
12748 const reg_entry
*r
;
12750 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12751 r
= parse_real_register (reg_string
, end_op
);
12756 char *save
= input_line_pointer
;
12760 input_line_pointer
= reg_string
;
12761 c
= get_symbol_name (®_string
);
12762 symbolP
= symbol_find (reg_string
);
12763 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12765 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12767 know (e
->X_op
== O_register
);
12768 know (e
->X_add_number
>= 0
12769 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12770 r
= i386_regtab
+ e
->X_add_number
;
12771 if (!check_register (r
))
12773 as_bad (_("register '%s%s' cannot be used here"),
12774 register_prefix
, r
->reg_name
);
12777 *end_op
= input_line_pointer
;
12779 *input_line_pointer
= c
;
12780 input_line_pointer
= save
;
12786 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12788 const reg_entry
*r
;
12789 char *end
= input_line_pointer
;
12792 r
= parse_register (name
, &input_line_pointer
);
12793 if (r
&& end
<= input_line_pointer
)
12795 *nextcharP
= *input_line_pointer
;
12796 *input_line_pointer
= 0;
12799 e
->X_op
= O_register
;
12800 e
->X_add_number
= r
- i386_regtab
;
12803 e
->X_op
= O_illegal
;
12806 input_line_pointer
= end
;
12808 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12812 md_operand (expressionS
*e
)
12815 const reg_entry
*r
;
12817 switch (*input_line_pointer
)
12819 case REGISTER_PREFIX
:
12820 r
= parse_real_register (input_line_pointer
, &end
);
12823 e
->X_op
= O_register
;
12824 e
->X_add_number
= r
- i386_regtab
;
12825 input_line_pointer
= end
;
12830 gas_assert (intel_syntax
);
12831 end
= input_line_pointer
++;
12833 if (*input_line_pointer
== ']')
12835 ++input_line_pointer
;
12836 e
->X_op_symbol
= make_expr_symbol (e
);
12837 e
->X_add_symbol
= NULL
;
12838 e
->X_add_number
= 0;
12843 e
->X_op
= O_absent
;
12844 input_line_pointer
= end
;
12851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12852 const char *md_shortopts
= "kVQ:sqnO::";
12854 const char *md_shortopts
= "qnO::";
12857 #define OPTION_32 (OPTION_MD_BASE + 0)
12858 #define OPTION_64 (OPTION_MD_BASE + 1)
12859 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12860 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12861 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12862 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12863 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12864 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12865 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12866 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12867 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12868 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12869 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12870 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12871 #define OPTION_X32 (OPTION_MD_BASE + 14)
12872 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12873 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12874 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12875 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12876 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12877 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12878 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12879 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12880 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12881 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12882 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12883 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12884 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12885 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12886 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12887 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12888 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12889 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12890 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12892 struct option md_longopts
[] =
12894 {"32", no_argument
, NULL
, OPTION_32
},
12895 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12896 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12897 {"64", no_argument
, NULL
, OPTION_64
},
12899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12900 {"x32", no_argument
, NULL
, OPTION_X32
},
12901 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12902 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12904 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12905 {"march", required_argument
, NULL
, OPTION_MARCH
},
12906 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12907 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12908 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12909 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12910 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12911 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12912 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12913 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12914 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12915 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12916 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12917 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12918 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12919 # if defined (TE_PE) || defined (TE_PEP)
12920 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12922 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12923 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12924 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12925 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12926 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12927 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12928 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12929 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12930 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12931 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12932 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12933 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12934 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12935 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12936 {NULL
, no_argument
, NULL
, 0}
12938 size_t md_longopts_size
= sizeof (md_longopts
);
12941 md_parse_option (int c
, const char *arg
)
12944 char *arch
, *next
, *saved
, *type
;
12949 optimize_align_code
= 0;
12953 quiet_warnings
= 1;
12956 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12957 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12958 should be emitted or not. FIXME: Not implemented. */
12960 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12964 /* -V: SVR4 argument to print version ID. */
12966 print_version_id ();
12969 /* -k: Ignore for FreeBSD compatibility. */
12974 /* -s: On i386 Solaris, this tells the native assembler to use
12975 .stab instead of .stab.excl. We always use .stab anyhow. */
12978 case OPTION_MSHARED
:
12982 case OPTION_X86_USED_NOTE
:
12983 if (strcasecmp (arg
, "yes") == 0)
12985 else if (strcasecmp (arg
, "no") == 0)
12988 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12993 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12994 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12997 const char **list
, **l
;
12999 list
= bfd_target_list ();
13000 for (l
= list
; *l
!= NULL
; l
++)
13001 if (CONST_STRNEQ (*l
, "elf64-x86-64")
13002 || strcmp (*l
, "coff-x86-64") == 0
13003 || strcmp (*l
, "pe-x86-64") == 0
13004 || strcmp (*l
, "pei-x86-64") == 0
13005 || strcmp (*l
, "mach-o-x86-64") == 0)
13007 default_arch
= "x86_64";
13011 as_fatal (_("no compiled in support for x86_64"));
13017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13021 const char **list
, **l
;
13023 list
= bfd_target_list ();
13024 for (l
= list
; *l
!= NULL
; l
++)
13025 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
13027 default_arch
= "x86_64:32";
13031 as_fatal (_("no compiled in support for 32bit x86_64"));
13035 as_fatal (_("32bit x86_64 is only supported for ELF"));
13040 default_arch
= "i386";
13043 case OPTION_DIVIDE
:
13044 #ifdef SVR4_COMMENT_CHARS
13049 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13051 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13055 i386_comment_chars
= n
;
13061 saved
= xstrdup (arg
);
13063 /* Allow -march=+nosse. */
13069 as_fatal (_("invalid -march= option: `%s'"), arg
);
13070 next
= strchr (arch
, '+');
13073 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13075 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13078 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13081 cpu_arch_name
= cpu_arch
[j
].name
;
13082 cpu_sub_arch_name
= NULL
;
13083 cpu_arch_flags
= cpu_arch
[j
].flags
;
13084 cpu_arch_isa
= cpu_arch
[j
].type
;
13085 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13086 if (!cpu_arch_tune_set
)
13088 cpu_arch_tune
= cpu_arch_isa
;
13089 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13093 else if (*cpu_arch
[j
].name
== '.'
13094 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13096 /* ISA extension. */
13097 i386_cpu_flags flags
;
13099 flags
= cpu_flags_or (cpu_arch_flags
,
13100 cpu_arch
[j
].flags
);
13102 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13104 if (cpu_sub_arch_name
)
13106 char *name
= cpu_sub_arch_name
;
13107 cpu_sub_arch_name
= concat (name
,
13109 (const char *) NULL
);
13113 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13114 cpu_arch_flags
= flags
;
13115 cpu_arch_isa_flags
= flags
;
13119 = cpu_flags_or (cpu_arch_isa_flags
,
13120 cpu_arch
[j
].flags
);
13125 if (j
>= ARRAY_SIZE (cpu_arch
))
13127 /* Disable an ISA extension. */
13128 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13129 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13131 i386_cpu_flags flags
;
13133 flags
= cpu_flags_and_not (cpu_arch_flags
,
13134 cpu_noarch
[j
].flags
);
13135 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13137 if (cpu_sub_arch_name
)
13139 char *name
= cpu_sub_arch_name
;
13140 cpu_sub_arch_name
= concat (arch
,
13141 (const char *) NULL
);
13145 cpu_sub_arch_name
= xstrdup (arch
);
13146 cpu_arch_flags
= flags
;
13147 cpu_arch_isa_flags
= flags
;
13152 if (j
>= ARRAY_SIZE (cpu_noarch
))
13153 j
= ARRAY_SIZE (cpu_arch
);
13156 if (j
>= ARRAY_SIZE (cpu_arch
))
13157 as_fatal (_("invalid -march= option: `%s'"), arg
);
13161 while (next
!= NULL
);
13167 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13168 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13170 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13172 cpu_arch_tune_set
= 1;
13173 cpu_arch_tune
= cpu_arch
[j
].type
;
13174 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13178 if (j
>= ARRAY_SIZE (cpu_arch
))
13179 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13182 case OPTION_MMNEMONIC
:
13183 if (strcasecmp (arg
, "att") == 0)
13184 intel_mnemonic
= 0;
13185 else if (strcasecmp (arg
, "intel") == 0)
13186 intel_mnemonic
= 1;
13188 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13191 case OPTION_MSYNTAX
:
13192 if (strcasecmp (arg
, "att") == 0)
13194 else if (strcasecmp (arg
, "intel") == 0)
13197 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13200 case OPTION_MINDEX_REG
:
13201 allow_index_reg
= 1;
13204 case OPTION_MNAKED_REG
:
13205 allow_naked_reg
= 1;
13208 case OPTION_MSSE2AVX
:
13212 case OPTION_MSSE_CHECK
:
13213 if (strcasecmp (arg
, "error") == 0)
13214 sse_check
= check_error
;
13215 else if (strcasecmp (arg
, "warning") == 0)
13216 sse_check
= check_warning
;
13217 else if (strcasecmp (arg
, "none") == 0)
13218 sse_check
= check_none
;
13220 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13223 case OPTION_MOPERAND_CHECK
:
13224 if (strcasecmp (arg
, "error") == 0)
13225 operand_check
= check_error
;
13226 else if (strcasecmp (arg
, "warning") == 0)
13227 operand_check
= check_warning
;
13228 else if (strcasecmp (arg
, "none") == 0)
13229 operand_check
= check_none
;
13231 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13234 case OPTION_MAVXSCALAR
:
13235 if (strcasecmp (arg
, "128") == 0)
13236 avxscalar
= vex128
;
13237 else if (strcasecmp (arg
, "256") == 0)
13238 avxscalar
= vex256
;
13240 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13243 case OPTION_MVEXWIG
:
13244 if (strcmp (arg
, "0") == 0)
13246 else if (strcmp (arg
, "1") == 0)
13249 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13252 case OPTION_MADD_BND_PREFIX
:
13253 add_bnd_prefix
= 1;
13256 case OPTION_MEVEXLIG
:
13257 if (strcmp (arg
, "128") == 0)
13258 evexlig
= evexl128
;
13259 else if (strcmp (arg
, "256") == 0)
13260 evexlig
= evexl256
;
13261 else if (strcmp (arg
, "512") == 0)
13262 evexlig
= evexl512
;
13264 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13267 case OPTION_MEVEXRCIG
:
13268 if (strcmp (arg
, "rne") == 0)
13270 else if (strcmp (arg
, "rd") == 0)
13272 else if (strcmp (arg
, "ru") == 0)
13274 else if (strcmp (arg
, "rz") == 0)
13277 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13280 case OPTION_MEVEXWIG
:
13281 if (strcmp (arg
, "0") == 0)
13283 else if (strcmp (arg
, "1") == 0)
13286 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13289 # if defined (TE_PE) || defined (TE_PEP)
13290 case OPTION_MBIG_OBJ
:
13295 case OPTION_MOMIT_LOCK_PREFIX
:
13296 if (strcasecmp (arg
, "yes") == 0)
13297 omit_lock_prefix
= 1;
13298 else if (strcasecmp (arg
, "no") == 0)
13299 omit_lock_prefix
= 0;
13301 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13304 case OPTION_MFENCE_AS_LOCK_ADD
:
13305 if (strcasecmp (arg
, "yes") == 0)
13307 else if (strcasecmp (arg
, "no") == 0)
13310 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13313 case OPTION_MLFENCE_AFTER_LOAD
:
13314 if (strcasecmp (arg
, "yes") == 0)
13315 lfence_after_load
= 1;
13316 else if (strcasecmp (arg
, "no") == 0)
13317 lfence_after_load
= 0;
13319 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13322 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13323 if (strcasecmp (arg
, "all") == 0)
13325 lfence_before_indirect_branch
= lfence_branch_all
;
13326 if (lfence_before_ret
== lfence_before_ret_none
)
13327 lfence_before_ret
= lfence_before_ret_shl
;
13329 else if (strcasecmp (arg
, "memory") == 0)
13330 lfence_before_indirect_branch
= lfence_branch_memory
;
13331 else if (strcasecmp (arg
, "register") == 0)
13332 lfence_before_indirect_branch
= lfence_branch_register
;
13333 else if (strcasecmp (arg
, "none") == 0)
13334 lfence_before_indirect_branch
= lfence_branch_none
;
13336 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13340 case OPTION_MLFENCE_BEFORE_RET
:
13341 if (strcasecmp (arg
, "or") == 0)
13342 lfence_before_ret
= lfence_before_ret_or
;
13343 else if (strcasecmp (arg
, "not") == 0)
13344 lfence_before_ret
= lfence_before_ret_not
;
13345 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13346 lfence_before_ret
= lfence_before_ret_shl
;
13347 else if (strcasecmp (arg
, "none") == 0)
13348 lfence_before_ret
= lfence_before_ret_none
;
13350 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13354 case OPTION_MRELAX_RELOCATIONS
:
13355 if (strcasecmp (arg
, "yes") == 0)
13356 generate_relax_relocations
= 1;
13357 else if (strcasecmp (arg
, "no") == 0)
13358 generate_relax_relocations
= 0;
13360 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13363 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13366 long int align
= strtoul (arg
, &end
, 0);
13371 align_branch_power
= 0;
13374 else if (align
>= 16)
13377 for (align_power
= 0;
13379 align
>>= 1, align_power
++)
13381 /* Limit alignment power to 31. */
13382 if (align
== 1 && align_power
< 32)
13384 align_branch_power
= align_power
;
13389 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13393 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13396 int align
= strtoul (arg
, &end
, 0);
13397 /* Some processors only support 5 prefixes. */
13398 if (*end
== '\0' && align
>= 0 && align
< 6)
13400 align_branch_prefix_size
= align
;
13403 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13408 case OPTION_MALIGN_BRANCH
:
13410 saved
= xstrdup (arg
);
13414 next
= strchr (type
, '+');
13417 if (strcasecmp (type
, "jcc") == 0)
13418 align_branch
|= align_branch_jcc_bit
;
13419 else if (strcasecmp (type
, "fused") == 0)
13420 align_branch
|= align_branch_fused_bit
;
13421 else if (strcasecmp (type
, "jmp") == 0)
13422 align_branch
|= align_branch_jmp_bit
;
13423 else if (strcasecmp (type
, "call") == 0)
13424 align_branch
|= align_branch_call_bit
;
13425 else if (strcasecmp (type
, "ret") == 0)
13426 align_branch
|= align_branch_ret_bit
;
13427 else if (strcasecmp (type
, "indirect") == 0)
13428 align_branch
|= align_branch_indirect_bit
;
13430 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13433 while (next
!= NULL
);
13437 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13438 align_branch_power
= 5;
13439 align_branch_prefix_size
= 5;
13440 align_branch
= (align_branch_jcc_bit
13441 | align_branch_fused_bit
13442 | align_branch_jmp_bit
);
13445 case OPTION_MAMD64
:
13449 case OPTION_MINTEL64
:
13457 /* Turn off -Os. */
13458 optimize_for_space
= 0;
13460 else if (*arg
== 's')
13462 optimize_for_space
= 1;
13463 /* Turn on all encoding optimizations. */
13464 optimize
= INT_MAX
;
13468 optimize
= atoi (arg
);
13469 /* Turn off -Os. */
13470 optimize_for_space
= 0;
13480 #define MESSAGE_TEMPLATE \
13484 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13485 int *left_p
, const char *name
, int len
)
13487 int size
= sizeof (MESSAGE_TEMPLATE
);
13488 int left
= *left_p
;
13490 /* Reserve 2 spaces for ", " or ",\0" */
13493 /* Check if there is any room. */
13501 p
= mempcpy (p
, name
, len
);
13505 /* Output the current message now and start a new one. */
13508 fprintf (stream
, "%s\n", message
);
13510 left
= size
- (start
- message
) - len
- 2;
13512 gas_assert (left
>= 0);
13514 p
= mempcpy (p
, name
, len
);
13522 show_arch (FILE *stream
, int ext
, int check
)
13524 static char message
[] = MESSAGE_TEMPLATE
;
13525 char *start
= message
+ 27;
13527 int size
= sizeof (MESSAGE_TEMPLATE
);
13534 left
= size
- (start
- message
);
13535 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13537 /* Should it be skipped? */
13538 if (cpu_arch
[j
].skip
)
13541 name
= cpu_arch
[j
].name
;
13542 len
= cpu_arch
[j
].len
;
13545 /* It is an extension. Skip if we aren't asked to show it. */
13556 /* It is an processor. Skip if we show only extension. */
13559 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13561 /* It is an impossible processor - skip. */
13565 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13568 /* Display disabled extensions. */
13570 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13572 name
= cpu_noarch
[j
].name
;
13573 len
= cpu_noarch
[j
].len
;
13574 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13579 fprintf (stream
, "%s\n", message
);
13583 md_show_usage (FILE *stream
)
13585 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13586 fprintf (stream
, _("\
13587 -Qy, -Qn ignored\n\
13588 -V print assembler version number\n\
13591 fprintf (stream
, _("\
13592 -n Do not optimize code alignment\n\
13593 -q quieten some warnings\n"));
13594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13595 fprintf (stream
, _("\
13598 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13599 || defined (TE_PE) || defined (TE_PEP))
13600 fprintf (stream
, _("\
13601 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13603 #ifdef SVR4_COMMENT_CHARS
13604 fprintf (stream
, _("\
13605 --divide do not treat `/' as a comment character\n"));
13607 fprintf (stream
, _("\
13608 --divide ignored\n"));
13610 fprintf (stream
, _("\
13611 -march=CPU[,+EXTENSION...]\n\
13612 generate code for CPU and EXTENSION, CPU is one of:\n"));
13613 show_arch (stream
, 0, 1);
13614 fprintf (stream
, _("\
13615 EXTENSION is combination of:\n"));
13616 show_arch (stream
, 1, 0);
13617 fprintf (stream
, _("\
13618 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13619 show_arch (stream
, 0, 0);
13620 fprintf (stream
, _("\
13621 -msse2avx encode SSE instructions with VEX prefix\n"));
13622 fprintf (stream
, _("\
13623 -msse-check=[none|error|warning] (default: warning)\n\
13624 check SSE instructions\n"));
13625 fprintf (stream
, _("\
13626 -moperand-check=[none|error|warning] (default: warning)\n\
13627 check operand combinations for validity\n"));
13628 fprintf (stream
, _("\
13629 -mavxscalar=[128|256] (default: 128)\n\
13630 encode scalar AVX instructions with specific vector\n\
13632 fprintf (stream
, _("\
13633 -mvexwig=[0|1] (default: 0)\n\
13634 encode VEX instructions with specific VEX.W value\n\
13635 for VEX.W bit ignored instructions\n"));
13636 fprintf (stream
, _("\
13637 -mevexlig=[128|256|512] (default: 128)\n\
13638 encode scalar EVEX instructions with specific vector\n\
13640 fprintf (stream
, _("\
13641 -mevexwig=[0|1] (default: 0)\n\
13642 encode EVEX instructions with specific EVEX.W value\n\
13643 for EVEX.W bit ignored instructions\n"));
13644 fprintf (stream
, _("\
13645 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13646 encode EVEX instructions with specific EVEX.RC value\n\
13647 for SAE-only ignored instructions\n"));
13648 fprintf (stream
, _("\
13649 -mmnemonic=[att|intel] "));
13650 if (SYSV386_COMPAT
)
13651 fprintf (stream
, _("(default: att)\n"));
13653 fprintf (stream
, _("(default: intel)\n"));
13654 fprintf (stream
, _("\
13655 use AT&T/Intel mnemonic\n"));
13656 fprintf (stream
, _("\
13657 -msyntax=[att|intel] (default: att)\n\
13658 use AT&T/Intel syntax\n"));
13659 fprintf (stream
, _("\
13660 -mindex-reg support pseudo index registers\n"));
13661 fprintf (stream
, _("\
13662 -mnaked-reg don't require `%%' prefix for registers\n"));
13663 fprintf (stream
, _("\
13664 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13666 fprintf (stream
, _("\
13667 -mshared disable branch optimization for shared code\n"));
13668 fprintf (stream
, _("\
13669 -mx86-used-note=[no|yes] "));
13670 if (DEFAULT_X86_USED_NOTE
)
13671 fprintf (stream
, _("(default: yes)\n"));
13673 fprintf (stream
, _("(default: no)\n"));
13674 fprintf (stream
, _("\
13675 generate x86 used ISA and feature properties\n"));
13677 #if defined (TE_PE) || defined (TE_PEP)
13678 fprintf (stream
, _("\
13679 -mbig-obj generate big object files\n"));
13681 fprintf (stream
, _("\
13682 -momit-lock-prefix=[no|yes] (default: no)\n\
13683 strip all lock prefixes\n"));
13684 fprintf (stream
, _("\
13685 -mfence-as-lock-add=[no|yes] (default: no)\n\
13686 encode lfence, mfence and sfence as\n\
13687 lock addl $0x0, (%%{re}sp)\n"));
13688 fprintf (stream
, _("\
13689 -mrelax-relocations=[no|yes] "));
13690 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13691 fprintf (stream
, _("(default: yes)\n"));
13693 fprintf (stream
, _("(default: no)\n"));
13694 fprintf (stream
, _("\
13695 generate relax relocations\n"));
13696 fprintf (stream
, _("\
13697 -malign-branch-boundary=NUM (default: 0)\n\
13698 align branches within NUM byte boundary\n"));
13699 fprintf (stream
, _("\
13700 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13701 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13703 specify types of branches to align\n"));
13704 fprintf (stream
, _("\
13705 -malign-branch-prefix-size=NUM (default: 5)\n\
13706 align branches with NUM prefixes per instruction\n"));
13707 fprintf (stream
, _("\
13708 -mbranches-within-32B-boundaries\n\
13709 align branches within 32 byte boundary\n"));
13710 fprintf (stream
, _("\
13711 -mlfence-after-load=[no|yes] (default: no)\n\
13712 generate lfence after load\n"));
13713 fprintf (stream
, _("\
13714 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13715 generate lfence before indirect near branch\n"));
13716 fprintf (stream
, _("\
13717 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13718 generate lfence before ret\n"));
13719 fprintf (stream
, _("\
13720 -mamd64 accept only AMD64 ISA [default]\n"));
13721 fprintf (stream
, _("\
13722 -mintel64 accept only Intel64 ISA\n"));
13725 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13726 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13727 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13729 /* Pick the target format to use. */
13732 i386_target_format (void)
13734 if (!strncmp (default_arch
, "x86_64", 6))
13736 update_code_flag (CODE_64BIT
, 1);
13737 if (default_arch
[6] == '\0')
13738 x86_elf_abi
= X86_64_ABI
;
13740 x86_elf_abi
= X86_64_X32_ABI
;
13742 else if (!strcmp (default_arch
, "i386"))
13743 update_code_flag (CODE_32BIT
, 1);
13744 else if (!strcmp (default_arch
, "iamcu"))
13746 update_code_flag (CODE_32BIT
, 1);
13747 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13749 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13750 cpu_arch_name
= "iamcu";
13751 cpu_sub_arch_name
= NULL
;
13752 cpu_arch_flags
= iamcu_flags
;
13753 cpu_arch_isa
= PROCESSOR_IAMCU
;
13754 cpu_arch_isa_flags
= iamcu_flags
;
13755 if (!cpu_arch_tune_set
)
13757 cpu_arch_tune
= cpu_arch_isa
;
13758 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13761 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13762 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13766 as_fatal (_("unknown architecture"));
13768 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13769 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13770 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13771 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13773 switch (OUTPUT_FLAVOR
)
13775 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13776 case bfd_target_aout_flavour
:
13777 return AOUT_TARGET_FORMAT
;
13779 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13780 # if defined (TE_PE) || defined (TE_PEP)
13781 case bfd_target_coff_flavour
:
13782 if (flag_code
== CODE_64BIT
)
13783 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13785 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13786 # elif defined (TE_GO32)
13787 case bfd_target_coff_flavour
:
13788 return "coff-go32";
13790 case bfd_target_coff_flavour
:
13791 return "coff-i386";
13794 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13795 case bfd_target_elf_flavour
:
13797 const char *format
;
13799 switch (x86_elf_abi
)
13802 format
= ELF_TARGET_FORMAT
;
13804 tls_get_addr
= "___tls_get_addr";
13808 use_rela_relocations
= 1;
13811 tls_get_addr
= "__tls_get_addr";
13813 format
= ELF_TARGET_FORMAT64
;
13815 case X86_64_X32_ABI
:
13816 use_rela_relocations
= 1;
13819 tls_get_addr
= "__tls_get_addr";
13821 disallow_64bit_reloc
= 1;
13822 format
= ELF_TARGET_FORMAT32
;
13825 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13827 if (x86_elf_abi
!= X86_64_ABI
)
13828 as_fatal (_("Intel L1OM is 64bit only"));
13829 return ELF_TARGET_L1OM_FORMAT
;
13831 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13833 if (x86_elf_abi
!= X86_64_ABI
)
13834 as_fatal (_("Intel K1OM is 64bit only"));
13835 return ELF_TARGET_K1OM_FORMAT
;
13837 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13839 if (x86_elf_abi
!= I386_ABI
)
13840 as_fatal (_("Intel MCU is 32bit only"));
13841 return ELF_TARGET_IAMCU_FORMAT
;
13847 #if defined (OBJ_MACH_O)
13848 case bfd_target_mach_o_flavour
:
13849 if (flag_code
== CODE_64BIT
)
13851 use_rela_relocations
= 1;
13853 return "mach-o-x86-64";
13856 return "mach-o-i386";
13864 #endif /* OBJ_MAYBE_ more than one */
13867 md_undefined_symbol (char *name
)
13869 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13870 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13871 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13872 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13876 if (symbol_find (name
))
13877 as_bad (_("GOT already in symbol table"));
13878 GOT_symbol
= symbol_new (name
, undefined_section
,
13879 &zero_address_frag
, 0);
13886 /* Round up a section size to the appropriate boundary. */
13889 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13891 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13892 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13894 /* For a.out, force the section size to be aligned. If we don't do
13895 this, BFD will align it for us, but it will not write out the
13896 final bytes of the section. This may be a bug in BFD, but it is
13897 easier to fix it here since that is how the other a.out targets
13901 align
= bfd_section_alignment (segment
);
13902 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13909 /* On the i386, PC-relative offsets are relative to the start of the
13910 next instruction. That is, the address of the offset, plus its
13911 size, since the offset is always the last part of the insn. */
13914 md_pcrel_from (fixS
*fixP
)
13916 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13922 s_bss (int ignore ATTRIBUTE_UNUSED
)
13926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13928 obj_elf_section_change_hook ();
13930 temp
= get_absolute_expression ();
13931 subseg_set (bss_section
, (subsegT
) temp
);
13932 demand_empty_rest_of_line ();
13937 /* Remember constant directive. */
13940 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13942 if (last_insn
.kind
!= last_insn_directive
13943 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13945 last_insn
.seg
= now_seg
;
13946 last_insn
.kind
= last_insn_directive
;
13947 last_insn
.name
= "constant directive";
13948 last_insn
.file
= as_where (&last_insn
.line
);
13949 if (lfence_before_ret
!= lfence_before_ret_none
)
13951 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13952 as_warn (_("constant directive skips -mlfence-before-ret "
13953 "and -mlfence-before-indirect-branch"));
13955 as_warn (_("constant directive skips -mlfence-before-ret"));
13957 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13958 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13963 i386_validate_fix (fixS
*fixp
)
13965 if (fixp
->fx_subsy
)
13967 if (fixp
->fx_subsy
== GOT_symbol
)
13969 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13974 if (fixp
->fx_tcbit2
)
13975 fixp
->fx_r_type
= (fixp
->fx_tcbit
13976 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13977 : BFD_RELOC_X86_64_GOTPCRELX
);
13980 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13985 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13987 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13989 fixp
->fx_subsy
= 0;
13992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13995 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13996 to section. Since PLT32 relocation must be against symbols,
13997 turn such PLT32 relocation into PC32 relocation. */
13999 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14000 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14001 && symbol_section_p (fixp
->fx_addsy
))
14002 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14005 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14006 && fixp
->fx_tcbit2
)
14007 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14014 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14017 bfd_reloc_code_real_type code
;
14019 switch (fixp
->fx_r_type
)
14021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14022 case BFD_RELOC_SIZE32
:
14023 case BFD_RELOC_SIZE64
:
14024 if (S_IS_DEFINED (fixp
->fx_addsy
)
14025 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14027 /* Resolve size relocation against local symbol to size of
14028 the symbol plus addend. */
14029 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14030 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14031 && !fits_in_unsigned_long (value
))
14032 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14033 _("symbol size computation overflow"));
14034 fixp
->fx_addsy
= NULL
;
14035 fixp
->fx_subsy
= NULL
;
14036 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14040 /* Fall through. */
14042 case BFD_RELOC_X86_64_PLT32
:
14043 case BFD_RELOC_X86_64_GOT32
:
14044 case BFD_RELOC_X86_64_GOTPCREL
:
14045 case BFD_RELOC_X86_64_GOTPCRELX
:
14046 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14047 case BFD_RELOC_386_PLT32
:
14048 case BFD_RELOC_386_GOT32
:
14049 case BFD_RELOC_386_GOT32X
:
14050 case BFD_RELOC_386_GOTOFF
:
14051 case BFD_RELOC_386_GOTPC
:
14052 case BFD_RELOC_386_TLS_GD
:
14053 case BFD_RELOC_386_TLS_LDM
:
14054 case BFD_RELOC_386_TLS_LDO_32
:
14055 case BFD_RELOC_386_TLS_IE_32
:
14056 case BFD_RELOC_386_TLS_IE
:
14057 case BFD_RELOC_386_TLS_GOTIE
:
14058 case BFD_RELOC_386_TLS_LE_32
:
14059 case BFD_RELOC_386_TLS_LE
:
14060 case BFD_RELOC_386_TLS_GOTDESC
:
14061 case BFD_RELOC_386_TLS_DESC_CALL
:
14062 case BFD_RELOC_X86_64_TLSGD
:
14063 case BFD_RELOC_X86_64_TLSLD
:
14064 case BFD_RELOC_X86_64_DTPOFF32
:
14065 case BFD_RELOC_X86_64_DTPOFF64
:
14066 case BFD_RELOC_X86_64_GOTTPOFF
:
14067 case BFD_RELOC_X86_64_TPOFF32
:
14068 case BFD_RELOC_X86_64_TPOFF64
:
14069 case BFD_RELOC_X86_64_GOTOFF64
:
14070 case BFD_RELOC_X86_64_GOTPC32
:
14071 case BFD_RELOC_X86_64_GOT64
:
14072 case BFD_RELOC_X86_64_GOTPCREL64
:
14073 case BFD_RELOC_X86_64_GOTPC64
:
14074 case BFD_RELOC_X86_64_GOTPLT64
:
14075 case BFD_RELOC_X86_64_PLTOFF64
:
14076 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14077 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14078 case BFD_RELOC_RVA
:
14079 case BFD_RELOC_VTABLE_ENTRY
:
14080 case BFD_RELOC_VTABLE_INHERIT
:
14082 case BFD_RELOC_32_SECREL
:
14084 code
= fixp
->fx_r_type
;
14086 case BFD_RELOC_X86_64_32S
:
14087 if (!fixp
->fx_pcrel
)
14089 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14090 code
= fixp
->fx_r_type
;
14093 /* Fall through. */
14095 if (fixp
->fx_pcrel
)
14097 switch (fixp
->fx_size
)
14100 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14101 _("can not do %d byte pc-relative relocation"),
14103 code
= BFD_RELOC_32_PCREL
;
14105 case 1: code
= BFD_RELOC_8_PCREL
; break;
14106 case 2: code
= BFD_RELOC_16_PCREL
; break;
14107 case 4: code
= BFD_RELOC_32_PCREL
; break;
14109 case 8: code
= BFD_RELOC_64_PCREL
; break;
14115 switch (fixp
->fx_size
)
14118 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14119 _("can not do %d byte relocation"),
14121 code
= BFD_RELOC_32
;
14123 case 1: code
= BFD_RELOC_8
; break;
14124 case 2: code
= BFD_RELOC_16
; break;
14125 case 4: code
= BFD_RELOC_32
; break;
14127 case 8: code
= BFD_RELOC_64
; break;
14134 if ((code
== BFD_RELOC_32
14135 || code
== BFD_RELOC_32_PCREL
14136 || code
== BFD_RELOC_X86_64_32S
)
14138 && fixp
->fx_addsy
== GOT_symbol
)
14141 code
= BFD_RELOC_386_GOTPC
;
14143 code
= BFD_RELOC_X86_64_GOTPC32
;
14145 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14147 && fixp
->fx_addsy
== GOT_symbol
)
14149 code
= BFD_RELOC_X86_64_GOTPC64
;
14152 rel
= XNEW (arelent
);
14153 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14154 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14156 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14158 if (!use_rela_relocations
)
14160 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14161 vtable entry to be used in the relocation's section offset. */
14162 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14163 rel
->address
= fixp
->fx_offset
;
14164 #if defined (OBJ_COFF) && defined (TE_PE)
14165 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14166 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14171 /* Use the rela in 64bit mode. */
14174 if (disallow_64bit_reloc
)
14177 case BFD_RELOC_X86_64_DTPOFF64
:
14178 case BFD_RELOC_X86_64_TPOFF64
:
14179 case BFD_RELOC_64_PCREL
:
14180 case BFD_RELOC_X86_64_GOTOFF64
:
14181 case BFD_RELOC_X86_64_GOT64
:
14182 case BFD_RELOC_X86_64_GOTPCREL64
:
14183 case BFD_RELOC_X86_64_GOTPC64
:
14184 case BFD_RELOC_X86_64_GOTPLT64
:
14185 case BFD_RELOC_X86_64_PLTOFF64
:
14186 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14187 _("cannot represent relocation type %s in x32 mode"),
14188 bfd_get_reloc_code_name (code
));
14194 if (!fixp
->fx_pcrel
)
14195 rel
->addend
= fixp
->fx_offset
;
14199 case BFD_RELOC_X86_64_PLT32
:
14200 case BFD_RELOC_X86_64_GOT32
:
14201 case BFD_RELOC_X86_64_GOTPCREL
:
14202 case BFD_RELOC_X86_64_GOTPCRELX
:
14203 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14204 case BFD_RELOC_X86_64_TLSGD
:
14205 case BFD_RELOC_X86_64_TLSLD
:
14206 case BFD_RELOC_X86_64_GOTTPOFF
:
14207 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14208 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14209 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14212 rel
->addend
= (section
->vma
14214 + fixp
->fx_addnumber
14215 + md_pcrel_from (fixp
));
14220 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14221 if (rel
->howto
== NULL
)
14223 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14224 _("cannot represent relocation type %s"),
14225 bfd_get_reloc_code_name (code
));
14226 /* Set howto to a garbage value so that we can keep going. */
14227 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14228 gas_assert (rel
->howto
!= NULL
);
14234 #include "tc-i386-intel.c"
14237 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14239 int saved_naked_reg
;
14240 char saved_register_dot
;
14242 saved_naked_reg
= allow_naked_reg
;
14243 allow_naked_reg
= 1;
14244 saved_register_dot
= register_chars
['.'];
14245 register_chars
['.'] = '.';
14246 allow_pseudo_reg
= 1;
14247 expression_and_evaluate (exp
);
14248 allow_pseudo_reg
= 0;
14249 register_chars
['.'] = saved_register_dot
;
14250 allow_naked_reg
= saved_naked_reg
;
14252 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14254 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14256 exp
->X_op
= O_constant
;
14257 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14258 .dw2_regnum
[flag_code
>> 1];
14261 exp
->X_op
= O_illegal
;
14266 tc_x86_frame_initial_instructions (void)
14268 static unsigned int sp_regno
[2];
14270 if (!sp_regno
[flag_code
>> 1])
14272 char *saved_input
= input_line_pointer
;
14273 char sp
[][4] = {"esp", "rsp"};
14276 input_line_pointer
= sp
[flag_code
>> 1];
14277 tc_x86_parse_to_dw2regnum (&exp
);
14278 gas_assert (exp
.X_op
== O_constant
);
14279 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14280 input_line_pointer
= saved_input
;
14283 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14284 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14288 x86_dwarf2_addr_size (void)
14290 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14291 if (x86_elf_abi
== X86_64_X32_ABI
)
14294 return bfd_arch_bits_per_address (stdoutput
) / 8;
14298 i386_elf_section_type (const char *str
, size_t len
)
14300 if (flag_code
== CODE_64BIT
14301 && len
== sizeof ("unwind") - 1
14302 && strncmp (str
, "unwind", 6) == 0)
14303 return SHT_X86_64_UNWIND
;
14310 i386_solaris_fix_up_eh_frame (segT sec
)
14312 if (flag_code
== CODE_64BIT
)
14313 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14319 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14323 exp
.X_op
= O_secrel
;
14324 exp
.X_add_symbol
= symbol
;
14325 exp
.X_add_number
= 0;
14326 emit_expr (&exp
, size
);
14330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14331 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14334 x86_64_section_letter (int letter
, const char **ptr_msg
)
14336 if (flag_code
== CODE_64BIT
)
14339 return SHF_X86_64_LARGE
;
14341 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14344 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14349 x86_64_section_word (char *str
, size_t len
)
14351 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14352 return SHF_X86_64_LARGE
;
14358 handle_large_common (int small ATTRIBUTE_UNUSED
)
14360 if (flag_code
!= CODE_64BIT
)
14362 s_comm_internal (0, elf_common_parse
);
14363 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14367 static segT lbss_section
;
14368 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14369 asection
*saved_bss_section
= bss_section
;
14371 if (lbss_section
== NULL
)
14373 flagword applicable
;
14374 segT seg
= now_seg
;
14375 subsegT subseg
= now_subseg
;
14377 /* The .lbss section is for local .largecomm symbols. */
14378 lbss_section
= subseg_new (".lbss", 0);
14379 applicable
= bfd_applicable_section_flags (stdoutput
);
14380 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14381 seg_info (lbss_section
)->bss
= 1;
14383 subseg_set (seg
, subseg
);
14386 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14387 bss_section
= lbss_section
;
14389 s_comm_internal (0, elf_common_parse
);
14391 elf_com_section_ptr
= saved_com_section_ptr
;
14392 bss_section
= saved_bss_section
;
14395 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */