1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
58 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
59 static int fits_in_signed_byte
PARAMS ((offsetT
));
60 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
61 static int fits_in_unsigned_word
PARAMS ((offsetT
));
62 static int fits_in_signed_word
PARAMS ((offsetT
));
63 static int fits_in_unsigned_long
PARAMS ((offsetT
));
64 static int fits_in_signed_long
PARAMS ((offsetT
));
65 static int smallest_imm_type
PARAMS ((offsetT
));
66 static offsetT offset_in_range
PARAMS ((offsetT
, int));
67 static int add_prefix
PARAMS ((unsigned int));
68 static void set_code_flag
PARAMS ((int));
69 static void set_16bit_gcc_code_flag
PARAMS ((int));
70 static void set_intel_syntax
PARAMS ((int));
71 static void set_cpu_arch
PARAMS ((int));
74 static bfd_reloc_code_real_type reloc
75 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
76 #define RELOC_ENUM enum bfd_reloc_code_real
78 #define RELOC_ENUM int
82 #define DEFAULT_ARCH "i386"
84 static const char *default_arch
= DEFAULT_ARCH
;
86 /* 'md_assemble ()' gathers together information and puts it into a
93 const reg_entry
*regs
;
98 /* TM holds the template for the insn were currently assembling. */
101 /* SUFFIX holds the instruction mnemonic suffix if given.
102 (e.g. 'l' for 'movl') */
105 /* OPERANDS gives the number of given operands. */
106 unsigned int operands
;
108 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
109 of given register, displacement, memory operands and immediate
111 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
113 /* TYPES [i] is the type (see above #defines) which tells us how to
114 use OP[i] for the corresponding operand. */
115 unsigned int types
[MAX_OPERANDS
];
117 /* Displacement expression, immediate expression, or register for each
119 union i386_op op
[MAX_OPERANDS
];
121 /* Flags for operands. */
122 unsigned int flags
[MAX_OPERANDS
];
123 #define Operand_PCrel 1
125 /* Relocation type for operand */
126 RELOC_ENUM reloc
[MAX_OPERANDS
];
128 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
129 the base index byte below. */
130 const reg_entry
*base_reg
;
131 const reg_entry
*index_reg
;
132 unsigned int log2_scale_factor
;
134 /* SEG gives the seg_entries of this insn. They are zero unless
135 explicit segment overrides are given. */
136 const seg_entry
*seg
[2];
138 /* PREFIX holds all the given prefix opcodes (usually null).
139 PREFIXES is the number of prefix opcodes. */
140 unsigned int prefixes
;
141 unsigned char prefix
[MAX_PREFIXES
];
143 /* RM and SIB are the modrm byte and the sib byte where the
144 addressing modes of this insn are encoded. */
151 typedef struct _i386_insn i386_insn
;
153 /* List of chars besides those in app.c:symbol_chars that can start an
154 operand. Used to prevent the scrubber eating vital white-space. */
156 const char extra_symbol_chars
[] = "*%-(@";
158 const char extra_symbol_chars
[] = "*%-(";
161 /* This array holds the chars that always start a comment. If the
162 pre-processor is disabled, these aren't very useful. */
163 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
164 /* Putting '/' here makes it impossible to use the divide operator.
165 However, we need it for compatibility with SVR4 systems. */
166 const char comment_chars
[] = "#/";
167 #define PREFIX_SEPARATOR '\\'
169 const char comment_chars
[] = "#";
170 #define PREFIX_SEPARATOR '/'
173 /* This array holds the chars that only start a comment at the beginning of
174 a line. If the line seems to have the form '# 123 filename'
175 .line and .file directives will appear in the pre-processed output.
176 Note that input_file.c hand checks for '#' at the beginning of the
177 first line of the input file. This is because the compiler outputs
178 #NO_APP at the beginning of its output.
179 Also note that comments started like this one will always work if
180 '/' isn't otherwise defined. */
181 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
182 const char line_comment_chars
[] = "";
184 const char line_comment_chars
[] = "/";
187 const char line_separator_chars
[] = ";";
189 /* Chars that can be used to separate mant from exp in floating point
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant
196 const char FLT_CHARS
[] = "fFdDxX";
198 /* Tables for lexical analysis. */
199 static char mnemonic_chars
[256];
200 static char register_chars
[256];
201 static char operand_chars
[256];
202 static char identifier_chars
[256];
203 static char digit_chars
[256];
205 /* Lexical macros. */
206 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
207 #define is_operand_char(x) (operand_chars[(unsigned char) x])
208 #define is_register_char(x) (register_chars[(unsigned char) x])
209 #define is_space_char(x) ((x) == ' ')
210 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
211 #define is_digit_char(x) (digit_chars[(unsigned char) x])
213 /* All non-digit non-letter charcters that may occur in an operand. */
214 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
216 /* md_assemble() always leaves the strings it's passed unaltered. To
217 effect this we maintain a stack of saved characters that we've smashed
218 with '\0's (indicating end of strings for various sub-fields of the
219 assembler instruction). */
220 static char save_stack
[32];
221 static char *save_stack_p
;
222 #define END_STRING_AND_SAVE(s) \
223 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
224 #define RESTORE_END_STRING(s) \
225 do { *(s) = *--save_stack_p; } while (0)
227 /* The instruction we're assembling. */
230 /* Possible templates for current insn. */
231 static const templates
*current_templates
;
233 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
234 static expressionS disp_expressions
[2], im_expressions
[2];
236 /* Current operand we are working on. */
237 static int this_operand
;
239 /* We support four different modes. FLAG_CODE variable is used to distinguish
246 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
248 static enum flag_code flag_code
;
249 static int use_rela_relocations
= 0;
251 /* The names used to print error messages. */
252 static const char *flag_code_names
[] =
259 /* 1 for intel syntax,
261 static int intel_syntax
= 0;
263 /* 1 if register prefix % not required. */
264 static int allow_naked_reg
= 0;
266 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
267 leave, push, and pop instructions so that gcc has the same stack
268 frame as in 32 bit mode. */
269 static char stackop_size
= '\0';
271 /* Non-zero to quieten some warnings. */
272 static int quiet_warnings
= 0;
275 static const char *cpu_arch_name
= NULL
;
277 /* CPU feature flags. */
278 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
280 /* If set, conditional jumps are not automatically promoted to handle
281 larger than a byte offset. */
282 static unsigned int no_cond_jump_promotion
= 0;
284 /* Interface to relax_segment.
285 There are 3 major relax states for 386 jump insns because the
286 different types of jumps add different sizes to frags when we're
287 figuring out what sort of jump to choose to reach a given label. */
290 #define UNCOND_JUMP 0
292 #define COND_JUMP86 2
297 #define SMALL16 (SMALL|CODE16)
299 #define BIG16 (BIG|CODE16)
303 #define INLINE __inline__
309 #define ENCODE_RELAX_STATE(type, size) \
310 ((relax_substateT) (((type) << 2) | (size)))
311 #define TYPE_FROM_RELAX_STATE(s) \
313 #define DISP_SIZE_FROM_RELAX_STATE(s) \
314 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
316 /* This table is used by relax_frag to promote short jumps to long
317 ones where necessary. SMALL (short) jumps may be promoted to BIG
318 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
319 don't allow a short jump in a 32 bit code segment to be promoted to
320 a 16 bit offset jump because it's slower (requires data size
321 prefix), and doesn't work, unless the destination is in the bottom
322 64k of the code segment (The top 16 bits of eip are zeroed). */
324 const relax_typeS md_relax_table
[] =
327 1) most positive reach of this state,
328 2) most negative reach of this state,
329 3) how many bytes this mode will have in the variable part of the frag
330 4) which index into the table to try if we can't fit into this one. */
332 /* UNCOND_JUMP states. */
333 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
334 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
335 /* dword jmp adds 4 bytes to frag:
336 0 extra opcode bytes, 4 displacement bytes. */
338 /* word jmp adds 2 byte2 to frag:
339 0 extra opcode bytes, 2 displacement bytes. */
342 /* COND_JUMP states. */
343 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
344 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
345 /* dword conditionals adds 5 bytes to frag:
346 1 extra opcode byte, 4 displacement bytes. */
348 /* word conditionals add 3 bytes to frag:
349 1 extra opcode byte, 2 displacement bytes. */
352 /* COND_JUMP86 states. */
353 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
354 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
355 /* dword conditionals adds 5 bytes to frag:
356 1 extra opcode byte, 4 displacement bytes. */
358 /* word conditionals add 4 bytes to frag:
359 1 displacement byte and a 3 byte long branch insn. */
363 static const arch_entry cpu_arch
[] = {
365 {"i186", Cpu086
|Cpu186
},
366 {"i286", Cpu086
|Cpu186
|Cpu286
},
367 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
368 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
369 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
370 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
371 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
372 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
373 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
374 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
375 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
376 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
381 i386_align_code (fragP
, count
)
385 /* Various efficient no-op patterns for aligning code labels.
386 Note: Don't try to assemble the instructions in the comments.
387 0L and 0w are not legal. */
388 static const char f32_1
[] =
390 static const char f32_2
[] =
391 {0x89,0xf6}; /* movl %esi,%esi */
392 static const char f32_3
[] =
393 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
394 static const char f32_4
[] =
395 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_5
[] =
398 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
399 static const char f32_6
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
401 static const char f32_7
[] =
402 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_8
[] =
405 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
406 static const char f32_9
[] =
407 {0x89,0xf6, /* movl %esi,%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_10
[] =
410 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_11
[] =
413 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
414 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
415 static const char f32_12
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
418 static const char f32_13
[] =
419 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_14
[] =
422 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
423 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
424 static const char f32_15
[] =
425 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
426 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
427 static const char f16_3
[] =
428 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
429 static const char f16_4
[] =
430 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_5
[] =
433 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
434 static const char f16_6
[] =
435 {0x89,0xf6, /* mov %si,%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_7
[] =
438 {0x8d,0x74,0x00, /* lea 0(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char f16_8
[] =
441 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
442 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
443 static const char *const f32_patt
[] = {
444 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
445 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
447 static const char *const f16_patt
[] = {
448 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
449 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
452 /* ??? We can't use these fillers for x86_64, since they often kills the
453 upper halves. Solve later. */
454 if (flag_code
== CODE_64BIT
)
457 if (count
> 0 && count
<= 15)
459 if (flag_code
== CODE_16BIT
)
461 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
462 f16_patt
[count
- 1], count
);
464 /* Adjust jump offset. */
465 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
468 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
469 f32_patt
[count
- 1], count
);
470 fragP
->fr_var
= count
;
474 static char *output_invalid
PARAMS ((int c
));
475 static int i386_operand
PARAMS ((char *operand_string
));
476 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
477 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
481 static void s_bss
PARAMS ((int));
484 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
486 static INLINE
unsigned int
487 mode_from_disp_size (t
)
490 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
494 fits_in_signed_byte (num
)
497 return (num
>= -128) && (num
<= 127);
501 fits_in_unsigned_byte (num
)
504 return (num
& 0xff) == num
;
508 fits_in_unsigned_word (num
)
511 return (num
& 0xffff) == num
;
515 fits_in_signed_word (num
)
518 return (-32768 <= num
) && (num
<= 32767);
521 fits_in_signed_long (num
)
522 offsetT num ATTRIBUTE_UNUSED
;
527 return (!(((offsetT
) -1 << 31) & num
)
528 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
530 } /* fits_in_signed_long() */
532 fits_in_unsigned_long (num
)
533 offsetT num ATTRIBUTE_UNUSED
;
538 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
540 } /* fits_in_unsigned_long() */
543 smallest_imm_type (num
)
546 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
548 /* This code is disabled on the 486 because all the Imm1 forms
549 in the opcode table are slower on the i486. They're the
550 versions with the implicitly specified single-position
551 displacement, which has another syntax if you really want to
554 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
556 return (fits_in_signed_byte (num
)
557 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
558 : fits_in_unsigned_byte (num
)
559 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
560 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
561 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
562 : fits_in_signed_long (num
)
563 ? (Imm32
| Imm32S
| Imm64
)
564 : fits_in_unsigned_long (num
)
570 offset_in_range (val
, size
)
578 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
579 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
580 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
582 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
587 /* If BFD64, sign extend val. */
588 if (!use_rela_relocations
)
589 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
590 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
592 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
594 char buf1
[40], buf2
[40];
596 sprint_value (buf1
, val
);
597 sprint_value (buf2
, val
& mask
);
598 as_warn (_("%s shortened to %s"), buf1
, buf2
);
603 /* Returns 0 if attempting to add a prefix where one from the same
604 class already exists, 1 if non rep/repne added, 2 if rep/repne
613 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
621 case CS_PREFIX_OPCODE
:
622 case DS_PREFIX_OPCODE
:
623 case ES_PREFIX_OPCODE
:
624 case FS_PREFIX_OPCODE
:
625 case GS_PREFIX_OPCODE
:
626 case SS_PREFIX_OPCODE
:
630 case REPNE_PREFIX_OPCODE
:
631 case REPE_PREFIX_OPCODE
:
634 case LOCK_PREFIX_OPCODE
:
642 case ADDR_PREFIX_OPCODE
:
646 case DATA_PREFIX_OPCODE
:
653 as_bad (_("same type of prefix used twice"));
658 i
.prefix
[q
] = prefix
;
663 set_code_flag (value
)
667 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
668 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
669 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
671 as_bad (_("64bit mode not supported on this CPU."));
673 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
675 as_bad (_("32bit mode not supported on this CPU."));
681 set_16bit_gcc_code_flag (new_code_flag
)
684 flag_code
= new_code_flag
;
685 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
686 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
691 set_intel_syntax (syntax_flag
)
694 /* Find out if register prefixing is specified. */
695 int ask_naked_reg
= 0;
698 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
700 char *string
= input_line_pointer
;
701 int e
= get_symbol_end ();
703 if (strcmp (string
, "prefix") == 0)
705 else if (strcmp (string
, "noprefix") == 0)
708 as_bad (_("bad argument to syntax directive."));
709 *input_line_pointer
= e
;
711 demand_empty_rest_of_line ();
713 intel_syntax
= syntax_flag
;
715 if (ask_naked_reg
== 0)
718 allow_naked_reg
= (intel_syntax
719 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
721 /* Conservative default. */
726 allow_naked_reg
= (ask_naked_reg
< 0);
731 int dummy ATTRIBUTE_UNUSED
;
735 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
737 char *string
= input_line_pointer
;
738 int e
= get_symbol_end ();
741 for (i
= 0; cpu_arch
[i
].name
; i
++)
743 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
745 cpu_arch_name
= cpu_arch
[i
].name
;
746 cpu_arch_flags
= (cpu_arch
[i
].flags
747 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
751 if (!cpu_arch
[i
].name
)
752 as_bad (_("no such architecture: `%s'"), string
);
754 *input_line_pointer
= e
;
757 as_bad (_("missing cpu architecture"));
759 no_cond_jump_promotion
= 0;
760 if (*input_line_pointer
== ','
761 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
763 char *string
= ++input_line_pointer
;
764 int e
= get_symbol_end ();
766 if (strcmp (string
, "nojumps") == 0)
767 no_cond_jump_promotion
= 1;
768 else if (strcmp (string
, "jumps") == 0)
771 as_bad (_("no such architecture modifier: `%s'"), string
);
773 *input_line_pointer
= e
;
776 demand_empty_rest_of_line ();
779 const pseudo_typeS md_pseudo_table
[] =
781 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
782 {"align", s_align_bytes
, 0},
784 {"align", s_align_ptwo
, 0},
786 {"arch", set_cpu_arch
, 0},
790 {"ffloat", float_cons
, 'f'},
791 {"dfloat", float_cons
, 'd'},
792 {"tfloat", float_cons
, 'x'},
794 {"noopt", s_ignore
, 0},
795 {"optim", s_ignore
, 0},
796 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
797 {"code16", set_code_flag
, CODE_16BIT
},
798 {"code32", set_code_flag
, CODE_32BIT
},
799 {"code64", set_code_flag
, CODE_64BIT
},
800 {"intel_syntax", set_intel_syntax
, 1},
801 {"att_syntax", set_intel_syntax
, 0},
802 {"file", dwarf2_directive_file
, 0},
803 {"loc", dwarf2_directive_loc
, 0},
807 /* For interface with expression (). */
808 extern char *input_line_pointer
;
810 /* Hash table for instruction mnemonic lookup. */
811 static struct hash_control
*op_hash
;
813 /* Hash table for register lookup. */
814 static struct hash_control
*reg_hash
;
820 if (!strcmp (default_arch
, "x86_64"))
821 return bfd_mach_x86_64
;
822 else if (!strcmp (default_arch
, "i386"))
823 return bfd_mach_i386_i386
;
825 as_fatal (_("Unknown architecture"));
832 const char *hash_err
;
834 /* Initialize op_hash hash table. */
835 op_hash
= hash_new ();
838 register const template *optab
;
839 register templates
*core_optab
;
841 /* Setup for loop. */
843 core_optab
= (templates
*) xmalloc (sizeof (templates
));
844 core_optab
->start
= optab
;
849 if (optab
->name
== NULL
850 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
852 /* different name --> ship out current template list;
853 add to hash table; & begin anew. */
854 core_optab
->end
= optab
;
855 hash_err
= hash_insert (op_hash
,
860 as_fatal (_("Internal Error: Can't hash %s: %s"),
864 if (optab
->name
== NULL
)
866 core_optab
= (templates
*) xmalloc (sizeof (templates
));
867 core_optab
->start
= optab
;
872 /* Initialize reg_hash hash table. */
873 reg_hash
= hash_new ();
875 register const reg_entry
*regtab
;
877 for (regtab
= i386_regtab
;
878 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
881 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
883 as_fatal (_("Internal Error: Can't hash %s: %s"),
889 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
894 for (c
= 0; c
< 256; c
++)
899 mnemonic_chars
[c
] = c
;
900 register_chars
[c
] = c
;
901 operand_chars
[c
] = c
;
903 else if (ISLOWER (c
))
905 mnemonic_chars
[c
] = c
;
906 register_chars
[c
] = c
;
907 operand_chars
[c
] = c
;
909 else if (ISUPPER (c
))
911 mnemonic_chars
[c
] = TOLOWER (c
);
912 register_chars
[c
] = mnemonic_chars
[c
];
913 operand_chars
[c
] = c
;
916 if (ISALPHA (c
) || ISDIGIT (c
))
917 identifier_chars
[c
] = c
;
920 identifier_chars
[c
] = c
;
921 operand_chars
[c
] = c
;
926 identifier_chars
['@'] = '@';
928 digit_chars
['-'] = '-';
929 identifier_chars
['_'] = '_';
930 identifier_chars
['.'] = '.';
932 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
933 operand_chars
[(unsigned char) *p
] = *p
;
936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
937 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
939 record_alignment (text_section
, 2);
940 record_alignment (data_section
, 2);
941 record_alignment (bss_section
, 2);
947 i386_print_statistics (file
)
950 hash_print_statistics (file
, "i386 opcode", op_hash
);
951 hash_print_statistics (file
, "i386 register", reg_hash
);
956 /* Debugging routines for md_assemble. */
957 static void pi
PARAMS ((char *, i386_insn
*));
958 static void pte
PARAMS ((template *));
959 static void pt
PARAMS ((unsigned int));
960 static void pe
PARAMS ((expressionS
*));
961 static void ps
PARAMS ((symbolS
*));
970 fprintf (stdout
, "%s: template ", line
);
972 fprintf (stdout
, " address: base %s index %s scale %x\n",
973 x
->base_reg
? x
->base_reg
->reg_name
: "none",
974 x
->index_reg
? x
->index_reg
->reg_name
: "none",
975 x
->log2_scale_factor
);
976 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
977 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
978 fprintf (stdout
, " sib: base %x index %x scale %x\n",
979 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
980 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
981 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
982 for (i
= 0; i
< x
->operands
; i
++)
984 fprintf (stdout
, " #%d: ", i
+ 1);
986 fprintf (stdout
, "\n");
988 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
989 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
990 if (x
->types
[i
] & Imm
)
992 if (x
->types
[i
] & Disp
)
1002 fprintf (stdout
, " %d operands ", t
->operands
);
1003 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1004 if (t
->extension_opcode
!= None
)
1005 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1006 if (t
->opcode_modifier
& D
)
1007 fprintf (stdout
, "D");
1008 if (t
->opcode_modifier
& W
)
1009 fprintf (stdout
, "W");
1010 fprintf (stdout
, "\n");
1011 for (i
= 0; i
< t
->operands
; i
++)
1013 fprintf (stdout
, " #%d type ", i
+ 1);
1014 pt (t
->operand_types
[i
]);
1015 fprintf (stdout
, "\n");
1023 fprintf (stdout
, " operation %d\n", e
->X_op
);
1024 fprintf (stdout
, " add_number %ld (%lx)\n",
1025 (long) e
->X_add_number
, (long) e
->X_add_number
);
1026 if (e
->X_add_symbol
)
1028 fprintf (stdout
, " add_symbol ");
1029 ps (e
->X_add_symbol
);
1030 fprintf (stdout
, "\n");
1034 fprintf (stdout
, " op_symbol ");
1035 ps (e
->X_op_symbol
);
1036 fprintf (stdout
, "\n");
1044 fprintf (stdout
, "%s type %s%s",
1046 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1047 segment_name (S_GET_SEGMENT (s
)));
1069 { BaseIndex
, "BaseIndex" },
1073 { Disp32S
, "d32s" },
1075 { InOutPortReg
, "InOutPortReg" },
1076 { ShiftCount
, "ShiftCount" },
1077 { Control
, "control reg" },
1078 { Test
, "test reg" },
1079 { Debug
, "debug reg" },
1080 { FloatReg
, "FReg" },
1081 { FloatAcc
, "FAcc" },
1085 { JumpAbsolute
, "Jump Absolute" },
1096 register struct type_name
*ty
;
1098 for (ty
= type_names
; ty
->mask
; ty
++)
1100 fprintf (stdout
, "%s, ", ty
->tname
);
1104 #endif /* DEBUG386 */
1107 tc_i386_force_relocation (fixp
)
1110 #ifdef BFD_ASSEMBLER
1111 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1112 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1117 return fixp
->fx_r_type
== 7;
1121 #ifdef BFD_ASSEMBLER
1123 static bfd_reloc_code_real_type
1124 reloc (size
, pcrel
, sign
, other
)
1128 bfd_reloc_code_real_type other
;
1130 if (other
!= NO_RELOC
)
1136 as_bad (_("There are no unsigned pc-relative relocations"));
1139 case 1: return BFD_RELOC_8_PCREL
;
1140 case 2: return BFD_RELOC_16_PCREL
;
1141 case 4: return BFD_RELOC_32_PCREL
;
1143 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1150 case 4: return BFD_RELOC_X86_64_32S
;
1155 case 1: return BFD_RELOC_8
;
1156 case 2: return BFD_RELOC_16
;
1157 case 4: return BFD_RELOC_32
;
1158 case 8: return BFD_RELOC_64
;
1160 as_bad (_("can not do %s %d byte relocation"),
1161 sign
? "signed" : "unsigned", size
);
1165 return BFD_RELOC_NONE
;
1168 /* Here we decide which fixups can be adjusted to make them relative to
1169 the beginning of the section instead of the symbol. Basically we need
1170 to make sure that the dynamic relocations are done correctly, so in
1171 some cases we force the original symbol to be used. */
1174 tc_i386_fix_adjustable (fixP
)
1177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1178 /* Prevent all adjustments to global symbols, or else dynamic
1179 linking will not work correctly. */
1180 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1181 || S_IS_WEAK (fixP
->fx_addsy
))
1184 /* adjust_reloc_syms doesn't know about the GOT. */
1185 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1186 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1187 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1188 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1189 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1190 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1191 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1192 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1197 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1198 #define BFD_RELOC_16 0
1199 #define BFD_RELOC_32 0
1200 #define BFD_RELOC_16_PCREL 0
1201 #define BFD_RELOC_32_PCREL 0
1202 #define BFD_RELOC_386_PLT32 0
1203 #define BFD_RELOC_386_GOT32 0
1204 #define BFD_RELOC_386_GOTOFF 0
1205 #define BFD_RELOC_X86_64_PLT32 0
1206 #define BFD_RELOC_X86_64_GOT32 0
1207 #define BFD_RELOC_X86_64_GOTPCREL 0
1210 static int intel_float_operand
PARAMS ((char *mnemonic
));
1213 intel_float_operand (mnemonic
)
1216 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1219 if (mnemonic
[0] == 'f')
1225 /* This is the guts of the machine-dependent assembler. LINE points to a
1226 machine dependent instruction. This function is supposed to emit
1227 the frags/bytes it assembles to. */
1233 /* Points to template once we've found it. */
1238 char mnemonic
[MAX_MNEM_SIZE
];
1240 /* Initialize globals. */
1241 memset (&i
, '\0', sizeof (i
));
1242 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1243 i
.reloc
[j
] = NO_RELOC
;
1244 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1245 memset (im_expressions
, '\0', sizeof (im_expressions
));
1246 save_stack_p
= save_stack
;
1248 /* First parse an instruction mnemonic & call i386_operand for the operands.
1249 We assume that the scrubber has arranged it so that line[0] is the valid
1250 start of a (possibly prefixed) mnemonic. */
1253 char *token_start
= l
;
1256 /* Non-zero if we found a prefix only acceptable with string insns. */
1257 const char *expecting_string_instruction
= NULL
;
1262 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1265 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1267 as_bad (_("no such instruction: `%s'"), token_start
);
1272 if (!is_space_char (*l
)
1273 && *l
!= END_OF_INSN
1274 && *l
!= PREFIX_SEPARATOR
1277 as_bad (_("invalid character %s in mnemonic"),
1278 output_invalid (*l
));
1281 if (token_start
== l
)
1283 if (*l
== PREFIX_SEPARATOR
)
1284 as_bad (_("expecting prefix; got nothing"));
1286 as_bad (_("expecting mnemonic; got nothing"));
1290 /* Look up instruction (or prefix) via hash table. */
1291 current_templates
= hash_find (op_hash
, mnemonic
);
1293 if (*l
!= END_OF_INSN
1294 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1295 && current_templates
1296 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1298 /* If we are in 16-bit mode, do not allow addr16 or data16.
1299 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1300 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1301 && flag_code
!= CODE_64BIT
1302 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1303 ^ (flag_code
== CODE_16BIT
)))
1305 as_bad (_("redundant %s prefix"),
1306 current_templates
->start
->name
);
1309 /* Add prefix, checking for repeated prefixes. */
1310 switch (add_prefix (current_templates
->start
->base_opcode
))
1315 expecting_string_instruction
= current_templates
->start
->name
;
1318 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1325 if (!current_templates
)
1327 /* See if we can get a match by trimming off a suffix. */
1330 case WORD_MNEM_SUFFIX
:
1331 case BYTE_MNEM_SUFFIX
:
1332 case QWORD_MNEM_SUFFIX
:
1333 i
.suffix
= mnem_p
[-1];
1335 current_templates
= hash_find (op_hash
, mnemonic
);
1337 case SHORT_MNEM_SUFFIX
:
1338 case LONG_MNEM_SUFFIX
:
1341 i
.suffix
= mnem_p
[-1];
1343 current_templates
= hash_find (op_hash
, mnemonic
);
1351 if (intel_float_operand (mnemonic
))
1352 i
.suffix
= SHORT_MNEM_SUFFIX
;
1354 i
.suffix
= LONG_MNEM_SUFFIX
;
1356 current_templates
= hash_find (op_hash
, mnemonic
);
1360 if (!current_templates
)
1362 as_bad (_("no such instruction: `%s'"), token_start
);
1367 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1369 /* Check for a branch hint. We allow ",pt" and ",pn" for
1370 predict taken and predict not taken respectively.
1371 I'm not sure that branch hints actually do anything on loop
1372 and jcxz insns (JumpByte) for current Pentium4 chips. They
1373 may work in the future and it doesn't hurt to accept them
1375 if (l
[0] == ',' && l
[1] == 'p')
1379 if (! add_prefix (DS_PREFIX_OPCODE
))
1383 else if (l
[2] == 'n')
1385 if (! add_prefix (CS_PREFIX_OPCODE
))
1391 /* Any other comma loses. */
1394 as_bad (_("invalid character %s in mnemonic"),
1395 output_invalid (*l
));
1399 /* Check if instruction is supported on specified architecture. */
1400 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1401 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1403 as_warn (_("`%s' is not supported on `%s'"),
1404 current_templates
->start
->name
, cpu_arch_name
);
1406 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1408 as_warn (_("use .code16 to ensure correct addressing mode"));
1411 /* Check for rep/repne without a string instruction. */
1412 if (expecting_string_instruction
1413 && !(current_templates
->start
->opcode_modifier
& IsString
))
1415 as_bad (_("expecting string instruction after `%s'"),
1416 expecting_string_instruction
);
1420 /* There may be operands to parse. */
1421 if (*l
!= END_OF_INSN
)
1423 /* 1 if operand is pending after ','. */
1424 unsigned int expecting_operand
= 0;
1426 /* Non-zero if operand parens not balanced. */
1427 unsigned int paren_not_balanced
;
1431 /* Skip optional white space before operand. */
1432 if (is_space_char (*l
))
1434 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1436 as_bad (_("invalid character %s before operand %d"),
1437 output_invalid (*l
),
1441 token_start
= l
; /* after white space */
1442 paren_not_balanced
= 0;
1443 while (paren_not_balanced
|| *l
!= ',')
1445 if (*l
== END_OF_INSN
)
1447 if (paren_not_balanced
)
1450 as_bad (_("unbalanced parenthesis in operand %d."),
1453 as_bad (_("unbalanced brackets in operand %d."),
1458 break; /* we are done */
1460 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1462 as_bad (_("invalid character %s in operand %d"),
1463 output_invalid (*l
),
1470 ++paren_not_balanced
;
1472 --paren_not_balanced
;
1477 ++paren_not_balanced
;
1479 --paren_not_balanced
;
1483 if (l
!= token_start
)
1484 { /* Yes, we've read in another operand. */
1485 unsigned int operand_ok
;
1486 this_operand
= i
.operands
++;
1487 if (i
.operands
> MAX_OPERANDS
)
1489 as_bad (_("spurious operands; (%d operands/instruction max)"),
1493 /* Now parse operand adding info to 'i' as we go along. */
1494 END_STRING_AND_SAVE (l
);
1498 i386_intel_operand (token_start
,
1499 intel_float_operand (mnemonic
));
1501 operand_ok
= i386_operand (token_start
);
1503 RESTORE_END_STRING (l
);
1509 if (expecting_operand
)
1511 expecting_operand_after_comma
:
1512 as_bad (_("expecting operand after ','; got nothing"));
1517 as_bad (_("expecting operand before ','; got nothing"));
1522 /* Now *l must be either ',' or END_OF_INSN. */
1525 if (*++l
== END_OF_INSN
)
1527 /* Just skip it, if it's \n complain. */
1528 goto expecting_operand_after_comma
;
1530 expecting_operand
= 1;
1533 while (*l
!= END_OF_INSN
);
1537 /* Now we've parsed the mnemonic into a set of templates, and have the
1540 Next, we find a template that matches the given insn,
1541 making sure the overlap of the given operands types is consistent
1542 with the template operand types. */
1544 #define MATCH(overlap, given, template) \
1545 ((overlap & ~JumpAbsolute) \
1546 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1548 /* If given types r0 and r1 are registers they must be of the same type
1549 unless the expected operand type register overlap is null.
1550 Note that Acc in a template matches every size of reg. */
1551 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1552 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1553 ((g0) & Reg) == ((g1) & Reg) || \
1554 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1557 register unsigned int overlap0
, overlap1
;
1558 unsigned int overlap2
;
1559 unsigned int found_reverse_match
;
1562 /* All intel opcodes have reversed operands except for "bound" and
1563 "enter". We also don't reverse intersegment "jmp" and "call"
1564 instructions with 2 immediate operands so that the immediate segment
1565 precedes the offset, as it does when in AT&T mode. "enter" and the
1566 intersegment "jmp" and "call" instructions are the only ones that
1567 have two immediate operands. */
1568 if (intel_syntax
&& i
.operands
> 1
1569 && (strcmp (mnemonic
, "bound") != 0)
1570 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1572 union i386_op temp_op
;
1573 unsigned int temp_type
;
1574 RELOC_ENUM temp_reloc
;
1578 if (i
.operands
== 2)
1583 else if (i
.operands
== 3)
1588 temp_type
= i
.types
[xchg2
];
1589 i
.types
[xchg2
] = i
.types
[xchg1
];
1590 i
.types
[xchg1
] = temp_type
;
1591 temp_op
= i
.op
[xchg2
];
1592 i
.op
[xchg2
] = i
.op
[xchg1
];
1593 i
.op
[xchg1
] = temp_op
;
1594 temp_reloc
= i
.reloc
[xchg2
];
1595 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1596 i
.reloc
[xchg1
] = temp_reloc
;
1598 if (i
.mem_operands
== 2)
1600 const seg_entry
*temp_seg
;
1601 temp_seg
= i
.seg
[0];
1602 i
.seg
[0] = i
.seg
[1];
1603 i
.seg
[1] = temp_seg
;
1609 /* Try to ensure constant immediates are represented in the smallest
1611 char guess_suffix
= 0;
1615 guess_suffix
= i
.suffix
;
1616 else if (i
.reg_operands
)
1618 /* Figure out a suffix from the last register operand specified.
1619 We can't do this properly yet, ie. excluding InOutPortReg,
1620 but the following works for instructions with immediates.
1621 In any case, we can't set i.suffix yet. */
1622 for (op
= i
.operands
; --op
>= 0;)
1623 if (i
.types
[op
] & Reg
)
1625 if (i
.types
[op
] & Reg8
)
1626 guess_suffix
= BYTE_MNEM_SUFFIX
;
1627 else if (i
.types
[op
] & Reg16
)
1628 guess_suffix
= WORD_MNEM_SUFFIX
;
1629 else if (i
.types
[op
] & Reg32
)
1630 guess_suffix
= LONG_MNEM_SUFFIX
;
1631 else if (i
.types
[op
] & Reg64
)
1632 guess_suffix
= QWORD_MNEM_SUFFIX
;
1636 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1637 guess_suffix
= WORD_MNEM_SUFFIX
;
1639 for (op
= i
.operands
; --op
>= 0;)
1640 if (i
.types
[op
] & Imm
)
1642 switch (i
.op
[op
].imms
->X_op
)
1645 /* If a suffix is given, this operand may be shortened. */
1646 switch (guess_suffix
)
1648 case LONG_MNEM_SUFFIX
:
1649 i
.types
[op
] |= Imm32
| Imm64
;
1651 case WORD_MNEM_SUFFIX
:
1652 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1654 case BYTE_MNEM_SUFFIX
:
1655 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1659 /* If this operand is at most 16 bits, convert it
1660 to a signed 16 bit number before trying to see
1661 whether it will fit in an even smaller size.
1662 This allows a 16-bit operand such as $0xffe0 to
1663 be recognised as within Imm8S range. */
1664 if ((i
.types
[op
] & Imm16
)
1665 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1667 i
.op
[op
].imms
->X_add_number
=
1668 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1670 if ((i
.types
[op
] & Imm32
)
1671 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1673 i
.op
[op
].imms
->X_add_number
=
1674 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1676 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1677 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1678 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1679 i
.types
[op
] &= ~Imm32
;
1684 /* Symbols and expressions. */
1686 /* Convert symbolic operand to proper sizes for matching. */
1687 switch (guess_suffix
)
1689 case QWORD_MNEM_SUFFIX
:
1690 i
.types
[op
] = Imm64
| Imm32S
;
1692 case LONG_MNEM_SUFFIX
:
1693 i
.types
[op
] = Imm32
| Imm64
;
1695 case WORD_MNEM_SUFFIX
:
1696 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1699 case BYTE_MNEM_SUFFIX
:
1700 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1709 if (i
.disp_operands
)
1711 /* Try to use the smallest displacement type too. */
1714 for (op
= i
.operands
; --op
>= 0;)
1715 if ((i
.types
[op
] & Disp
)
1716 && i
.op
[op
].disps
->X_op
== O_constant
)
1718 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1720 if (i
.types
[op
] & Disp16
)
1722 /* We know this operand is at most 16 bits, so
1723 convert to a signed 16 bit number before trying
1724 to see whether it will fit in an even smaller
1727 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1729 else if (i
.types
[op
] & Disp32
)
1731 /* We know this operand is at most 32 bits, so convert to a
1732 signed 32 bit number before trying to see whether it will
1733 fit in an even smaller size. */
1734 disp
&= (((offsetT
) 2 << 31) - 1);
1735 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1737 if (flag_code
== CODE_64BIT
)
1739 if (fits_in_signed_long (disp
))
1740 i
.types
[op
] |= Disp32S
;
1741 if (fits_in_unsigned_long (disp
))
1742 i
.types
[op
] |= Disp32
;
1744 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1745 && fits_in_signed_byte (disp
))
1746 i
.types
[op
] |= Disp8
;
1753 found_reverse_match
= 0;
1754 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1756 : (i
.suffix
== WORD_MNEM_SUFFIX
1758 : (i
.suffix
== SHORT_MNEM_SUFFIX
1760 : (i
.suffix
== LONG_MNEM_SUFFIX
1762 : (i
.suffix
== QWORD_MNEM_SUFFIX
1764 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1766 for (t
= current_templates
->start
;
1767 t
< current_templates
->end
;
1770 /* Must have right number of operands. */
1771 if (i
.operands
!= t
->operands
)
1774 /* Check the suffix, except for some instructions in intel mode. */
1775 if ((t
->opcode_modifier
& suffix_check
)
1777 && (t
->opcode_modifier
& IgnoreSize
))
1779 && t
->base_opcode
== 0xd9
1780 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1781 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1784 /* Do not verify operands when there are none. */
1785 else if (!t
->operands
)
1787 if (t
->cpu_flags
& ~cpu_arch_flags
)
1789 /* We've found a match; break out of loop. */
1793 overlap0
= i
.types
[0] & t
->operand_types
[0];
1794 switch (t
->operands
)
1797 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1802 overlap1
= i
.types
[1] & t
->operand_types
[1];
1803 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1804 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1805 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1806 t
->operand_types
[0],
1807 overlap1
, i
.types
[1],
1808 t
->operand_types
[1]))
1810 /* Check if other direction is valid ... */
1811 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1814 /* Try reversing direction of operands. */
1815 overlap0
= i
.types
[0] & t
->operand_types
[1];
1816 overlap1
= i
.types
[1] & t
->operand_types
[0];
1817 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1818 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1819 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1820 t
->operand_types
[1],
1821 overlap1
, i
.types
[1],
1822 t
->operand_types
[0]))
1824 /* Does not match either direction. */
1827 /* found_reverse_match holds which of D or FloatDR
1829 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1831 /* Found a forward 2 operand match here. */
1832 else if (t
->operands
== 3)
1834 /* Here we make use of the fact that there are no
1835 reverse match 3 operand instructions, and all 3
1836 operand instructions only need to be checked for
1837 register consistency between operands 2 and 3. */
1838 overlap2
= i
.types
[2] & t
->operand_types
[2];
1839 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1840 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1841 t
->operand_types
[1],
1842 overlap2
, i
.types
[2],
1843 t
->operand_types
[2]))
1847 /* Found either forward/reverse 2 or 3 operand match here:
1848 slip through to break. */
1850 if (t
->cpu_flags
& ~cpu_arch_flags
)
1852 found_reverse_match
= 0;
1855 /* We've found a match; break out of loop. */
1858 if (t
== current_templates
->end
)
1860 /* We found no match. */
1861 as_bad (_("suffix or operands invalid for `%s'"),
1862 current_templates
->start
->name
);
1866 if (!quiet_warnings
)
1869 && ((i
.types
[0] & JumpAbsolute
)
1870 != (t
->operand_types
[0] & JumpAbsolute
)))
1872 as_warn (_("indirect %s without `*'"), t
->name
);
1875 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1876 == (IsPrefix
|IgnoreSize
))
1878 /* Warn them that a data or address size prefix doesn't
1879 affect assembly of the next line of code. */
1880 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1884 /* Copy the template we found. */
1886 if (found_reverse_match
)
1888 /* If we found a reverse match we must alter the opcode
1889 direction bit. found_reverse_match holds bits to change
1890 (different for int & float insns). */
1892 i
.tm
.base_opcode
^= found_reverse_match
;
1894 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1895 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1898 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1901 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1902 i
.tm
.base_opcode
^= FloatR
;
1904 if (i
.tm
.opcode_modifier
& FWait
)
1905 if (! add_prefix (FWAIT_OPCODE
))
1908 /* Check string instruction segment overrides. */
1909 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1911 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1912 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1914 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1916 as_bad (_("`%s' operand %d must use `%%es' segment"),
1921 /* There's only ever one segment override allowed per instruction.
1922 This instruction possibly has a legal segment override on the
1923 second operand, so copy the segment to where non-string
1924 instructions store it, allowing common code. */
1925 i
.seg
[0] = i
.seg
[1];
1927 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1929 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1931 as_bad (_("`%s' operand %d must use `%%es' segment"),
1939 /* If matched instruction specifies an explicit instruction mnemonic
1941 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1943 if (i
.tm
.opcode_modifier
& Size16
)
1944 i
.suffix
= WORD_MNEM_SUFFIX
;
1945 else if (i
.tm
.opcode_modifier
& Size64
)
1946 i
.suffix
= QWORD_MNEM_SUFFIX
;
1948 i
.suffix
= LONG_MNEM_SUFFIX
;
1950 else if (i
.reg_operands
)
1952 /* If there's no instruction mnemonic suffix we try to invent one
1953 based on register operands. */
1956 /* We take i.suffix from the last register operand specified,
1957 Destination register type is more significant than source
1960 for (op
= i
.operands
; --op
>= 0;)
1961 if ((i
.types
[op
] & Reg
)
1962 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1964 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1965 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1966 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1971 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1974 for (op
= i
.operands
; --op
>= 0;)
1976 /* If this is an eight bit register, it's OK. If it's
1977 the 16 or 32 bit version of an eight bit register,
1978 we will just use the low portion, and that's OK too. */
1979 if (i
.types
[op
] & Reg8
)
1982 /* movzx and movsx should not generate this warning. */
1984 && (i
.tm
.base_opcode
== 0xfb7
1985 || i
.tm
.base_opcode
== 0xfb6
1986 || i
.tm
.base_opcode
== 0x63
1987 || i
.tm
.base_opcode
== 0xfbe
1988 || i
.tm
.base_opcode
== 0xfbf))
1991 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1993 /* Check that the template allows eight bit regs
1994 This kills insns such as `orb $1,%edx', which
1995 maybe should be allowed. */
1996 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
2000 /* Prohibit these changes in the 64bit mode, since
2001 the lowering is more complicated. */
2002 if (flag_code
== CODE_64BIT
2003 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2004 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2005 i
.op
[op
].regs
->reg_name
,
2007 #if REGISTER_WARNINGS
2009 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2010 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2012 + (i
.types
[op
] & Reg16
2013 ? REGNAM_AL
- REGNAM_AX
2014 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2015 i
.op
[op
].regs
->reg_name
,
2020 /* Any other register is bad. */
2021 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2023 | Control
| Debug
| Test
2024 | FloatReg
| FloatAcc
))
2026 as_bad (_("`%%%s' not allowed with `%s%c'"),
2027 i
.op
[op
].regs
->reg_name
,
2034 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2038 for (op
= i
.operands
; --op
>= 0;)
2039 /* Reject eight bit registers, except where the template
2040 requires them. (eg. movzb) */
2041 if ((i
.types
[op
] & Reg8
) != 0
2042 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2044 as_bad (_("`%%%s' not allowed with `%s%c'"),
2045 i
.op
[op
].regs
->reg_name
,
2050 /* Warn if the e prefix on a general reg is missing. */
2051 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2052 && (i
.types
[op
] & Reg16
) != 0
2053 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2055 /* Prohibit these changes in the 64bit mode, since
2056 the lowering is more complicated. */
2057 if (flag_code
== CODE_64BIT
)
2058 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2059 i
.op
[op
].regs
->reg_name
,
2061 #if REGISTER_WARNINGS
2063 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2064 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2065 i
.op
[op
].regs
->reg_name
,
2069 /* Warn if the r prefix on a general reg is missing. */
2070 else if ((i
.types
[op
] & Reg64
) != 0
2071 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2073 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2074 i
.op
[op
].regs
->reg_name
,
2078 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2082 for (op
= i
.operands
; --op
>= 0; )
2083 /* Reject eight bit registers, except where the template
2084 requires them. (eg. movzb) */
2085 if ((i
.types
[op
] & Reg8
) != 0
2086 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2088 as_bad (_("`%%%s' not allowed with `%s%c'"),
2089 i
.op
[op
].regs
->reg_name
,
2094 /* Warn if the e prefix on a general reg is missing. */
2095 else if (((i
.types
[op
] & Reg16
) != 0
2096 || (i
.types
[op
] & Reg32
) != 0)
2097 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2099 /* Prohibit these changes in the 64bit mode, since
2100 the lowering is more complicated. */
2101 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2102 i
.op
[op
].regs
->reg_name
,
2106 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2109 for (op
= i
.operands
; --op
>= 0;)
2110 /* Reject eight bit registers, except where the template
2111 requires them. (eg. movzb) */
2112 if ((i
.types
[op
] & Reg8
) != 0
2113 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2115 as_bad (_("`%%%s' not allowed with `%s%c'"),
2116 i
.op
[op
].regs
->reg_name
,
2121 /* Warn if the e prefix on a general reg is present. */
2122 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2123 && (i
.types
[op
] & Reg32
) != 0
2124 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2126 /* Prohibit these changes in the 64bit mode, since
2127 the lowering is more complicated. */
2128 if (flag_code
== CODE_64BIT
)
2129 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2130 i
.op
[op
].regs
->reg_name
,
2133 #if REGISTER_WARNINGS
2134 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2135 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2136 i
.op
[op
].regs
->reg_name
,
2141 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2142 /* Do nothing if the instruction is going to ignore the prefix. */
2147 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2149 i
.suffix
= stackop_size
;
2151 /* Make still unresolved immediate matches conform to size of immediate
2152 given in i.suffix. Note: overlap2 cannot be an immediate! */
2153 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2154 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2155 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2156 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2160 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2161 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2162 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2164 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2165 || overlap0
== (Imm16
| Imm32
)
2166 || overlap0
== (Imm16
| Imm32S
))
2169 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2171 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2172 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2173 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2175 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2179 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2180 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2181 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2182 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2186 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2187 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2188 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2190 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2191 || overlap1
== (Imm16
| Imm32
)
2192 || overlap1
== (Imm16
| Imm32S
))
2195 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2197 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2198 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2199 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2201 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2205 assert ((overlap2
& Imm
) == 0);
2207 i
.types
[0] = overlap0
;
2208 if (overlap0
& ImplicitRegister
)
2210 if (overlap0
& Imm1
)
2211 i
.imm_operands
= 0; /* kludge for shift insns. */
2213 i
.types
[1] = overlap1
;
2214 if (overlap1
& ImplicitRegister
)
2217 i
.types
[2] = overlap2
;
2218 if (overlap2
& ImplicitRegister
)
2221 /* Finalize opcode. First, we change the opcode based on the operand
2222 size given by i.suffix: We need not change things for byte insns. */
2224 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2226 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2230 /* For movzx and movsx, need to check the register type. */
2232 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2233 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2235 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2237 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2238 if (!add_prefix (prefix
))
2242 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2244 /* It's not a byte, select word/dword operation. */
2245 if (i
.tm
.opcode_modifier
& W
)
2247 if (i
.tm
.opcode_modifier
& ShortForm
)
2248 i
.tm
.base_opcode
|= 8;
2250 i
.tm
.base_opcode
|= 1;
2252 /* Now select between word & dword operations via the operand
2253 size prefix, except for instructions that will ignore this
2255 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2256 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2257 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2259 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2260 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2261 prefix
= ADDR_PREFIX_OPCODE
;
2263 if (! add_prefix (prefix
))
2267 if (i
.suffix
!= QWORD_MNEM_SUFFIX
&& (flag_code
== CODE_64BIT
)
2268 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2269 && (i
.tm
.opcode_modifier
& JumpByte
))
2271 if (! add_prefix (ADDR_PREFIX_OPCODE
))
2275 /* Set mode64 for an operand. */
2276 if (i
.suffix
== QWORD_MNEM_SUFFIX
2277 && !(i
.tm
.opcode_modifier
& NoRex64
))
2280 if (flag_code
< CODE_64BIT
)
2282 as_bad (_("64bit operations available only in 64bit modes."));
2287 /* Size floating point instruction. */
2288 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2290 if (i
.tm
.opcode_modifier
& FloatMF
)
2291 i
.tm
.base_opcode
^= 4;
2295 if (i
.tm
.opcode_modifier
& ImmExt
)
2297 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2298 opcode suffix which is coded in the same place as an 8-bit
2299 immediate field would be. Here we fake an 8-bit immediate
2300 operand from the opcode suffix stored in tm.extension_opcode. */
2304 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2306 exp
= &im_expressions
[i
.imm_operands
++];
2307 i
.op
[i
.operands
].imms
= exp
;
2308 i
.types
[i
.operands
++] = Imm8
;
2309 exp
->X_op
= O_constant
;
2310 exp
->X_add_number
= i
.tm
.extension_opcode
;
2311 i
.tm
.extension_opcode
= None
;
2314 /* For insns with operands there are more diddles to do to the opcode. */
2317 /* Default segment register this instruction will use
2318 for memory accesses. 0 means unknown.
2319 This is only for optimizing out unnecessary segment overrides. */
2320 const seg_entry
*default_seg
= 0;
2322 /* The imul $imm, %reg instruction is converted into
2323 imul $imm, %reg, %reg, and the clr %reg instruction
2324 is converted into xor %reg, %reg. */
2325 if (i
.tm
.opcode_modifier
& regKludge
)
2327 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2328 /* Pretend we saw the extra register operand. */
2329 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2330 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2331 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2335 if (i
.tm
.opcode_modifier
& ShortForm
)
2337 /* The register or float register operand is in operand 0 or 1. */
2338 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2339 /* Register goes in low 3 bits of opcode. */
2340 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2341 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2343 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2345 /* Warn about some common errors, but press on regardless.
2346 The first case can be generated by gcc (<= 2.8.1). */
2347 if (i
.operands
== 2)
2349 /* Reversed arguments on faddp, fsubp, etc. */
2350 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2351 i
.op
[1].regs
->reg_name
,
2352 i
.op
[0].regs
->reg_name
);
2356 /* Extraneous `l' suffix on fp insn. */
2357 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2358 i
.op
[0].regs
->reg_name
);
2362 else if (i
.tm
.opcode_modifier
& Modrm
)
2364 /* The opcode is completed (modulo i.tm.extension_opcode which
2365 must be put into the modrm byte).
2366 Now, we make the modrm & index base bytes based on all the
2367 info we've collected. */
2369 /* i.reg_operands MUST be the number of real register operands;
2370 implicit registers do not count. */
2371 if (i
.reg_operands
== 2)
2373 unsigned int source
, dest
;
2374 source
= ((i
.types
[0]
2375 & (Reg
| RegMMX
| RegXMM
2377 | Control
| Debug
| Test
))
2382 /* One of the register operands will be encoded in the
2383 i.tm.reg field, the other in the combined i.tm.mode
2384 and i.tm.regmem fields. If no form of this
2385 instruction supports a memory destination operand,
2386 then we assume the source operand may sometimes be
2387 a memory operand and so we need to store the
2388 destination in the i.rm.reg field. */
2389 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2391 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2392 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2393 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2395 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2400 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2401 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2402 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2404 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2409 { /* If it's not 2 reg operands... */
2412 unsigned int fake_zero_displacement
= 0;
2413 unsigned int op
= ((i
.types
[0] & AnyMem
)
2415 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2422 if (! i
.disp_operands
)
2423 fake_zero_displacement
= 1;
2426 /* Operand is just <disp> */
2427 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2428 && (flag_code
!= CODE_64BIT
))
2430 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2431 i
.types
[op
] &= ~Disp
;
2432 i
.types
[op
] |= Disp16
;
2434 else if (flag_code
!= CODE_64BIT
2435 || (i
.prefix
[ADDR_PREFIX
] != 0))
2437 i
.rm
.regmem
= NO_BASE_REGISTER
;
2438 i
.types
[op
] &= ~Disp
;
2439 i
.types
[op
] |= Disp32
;
2443 /* 64bit mode overwrites the 32bit
2444 absolute addressing by RIP relative
2445 addressing and absolute addressing
2446 is encoded by one of the redundant
2449 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2450 i
.sib
.base
= NO_BASE_REGISTER
;
2451 i
.sib
.index
= NO_INDEX_REGISTER
;
2452 i
.types
[op
] &= ~Disp
;
2453 i
.types
[op
] |= Disp32S
;
2456 else /* ! i.base_reg && i.index_reg */
2458 i
.sib
.index
= i
.index_reg
->reg_num
;
2459 i
.sib
.base
= NO_BASE_REGISTER
;
2460 i
.sib
.scale
= i
.log2_scale_factor
;
2461 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2462 i
.types
[op
] &= ~Disp
;
2463 if (flag_code
!= CODE_64BIT
)
2464 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2466 i
.types
[op
] |= Disp32S
;
2467 if (i
.index_reg
->reg_flags
& RegRex
)
2471 /* RIP addressing for 64bit mode. */
2472 else if (i
.base_reg
->reg_type
== BaseIndex
)
2474 i
.rm
.regmem
= NO_BASE_REGISTER
;
2475 i
.types
[op
] &= ~Disp
;
2476 i
.types
[op
] |= Disp32S
;
2477 i
.flags
[op
] = Operand_PCrel
;
2479 else if (i
.base_reg
->reg_type
& Reg16
)
2481 switch (i
.base_reg
->reg_num
)
2486 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2487 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2494 if ((i
.types
[op
] & Disp
) == 0)
2496 /* fake (%bp) into 0(%bp) */
2497 i
.types
[op
] |= Disp8
;
2498 fake_zero_displacement
= 1;
2501 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2502 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2504 default: /* (%si) -> 4 or (%di) -> 5 */
2505 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2507 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2509 else /* i.base_reg and 32/64 bit mode */
2511 if (flag_code
== CODE_64BIT
2512 && (i
.types
[op
] & Disp
))
2514 if (i
.types
[op
] & Disp8
)
2515 i
.types
[op
] = Disp8
| Disp32S
;
2517 i
.types
[op
] = Disp32S
;
2519 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2520 if (i
.base_reg
->reg_flags
& RegRex
)
2522 i
.sib
.base
= i
.base_reg
->reg_num
;
2523 /* x86-64 ignores REX prefix bit here to avoid
2524 decoder complications. */
2525 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2528 if (i
.disp_operands
== 0)
2530 fake_zero_displacement
= 1;
2531 i
.types
[op
] |= Disp8
;
2534 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2538 i
.sib
.scale
= i
.log2_scale_factor
;
2541 /* <disp>(%esp) becomes two byte modrm
2542 with no index register. We've already
2543 stored the code for esp in i.rm.regmem
2544 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2545 base register besides %esp will not use
2546 the extra modrm byte. */
2547 i
.sib
.index
= NO_INDEX_REGISTER
;
2548 #if ! SCALE1_WHEN_NO_INDEX
2549 /* Another case where we force the second
2551 if (i
.log2_scale_factor
)
2552 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2557 i
.sib
.index
= i
.index_reg
->reg_num
;
2558 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2559 if (i
.index_reg
->reg_flags
& RegRex
)
2562 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2565 if (fake_zero_displacement
)
2567 /* Fakes a zero displacement assuming that i.types[op]
2568 holds the correct displacement size. */
2571 assert (i
.op
[op
].disps
== 0);
2572 exp
= &disp_expressions
[i
.disp_operands
++];
2573 i
.op
[op
].disps
= exp
;
2574 exp
->X_op
= O_constant
;
2575 exp
->X_add_number
= 0;
2576 exp
->X_add_symbol
= (symbolS
*) 0;
2577 exp
->X_op_symbol
= (symbolS
*) 0;
2581 /* Fill in i.rm.reg or i.rm.regmem field with register
2582 operand (if any) based on i.tm.extension_opcode.
2583 Again, we must be careful to make sure that
2584 segment/control/debug/test/MMX registers are coded
2585 into the i.rm.reg field. */
2590 & (Reg
| RegMMX
| RegXMM
2592 | Control
| Debug
| Test
))
2595 & (Reg
| RegMMX
| RegXMM
2597 | Control
| Debug
| Test
))
2600 /* If there is an extension opcode to put here, the
2601 register number must be put into the regmem field. */
2602 if (i
.tm
.extension_opcode
!= None
)
2604 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2605 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2610 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2611 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2615 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2616 we must set it to 3 to indicate this is a register
2617 operand in the regmem field. */
2618 if (!i
.mem_operands
)
2622 /* Fill in i.rm.reg field with extension opcode (if any). */
2623 if (i
.tm
.extension_opcode
!= None
)
2624 i
.rm
.reg
= i
.tm
.extension_opcode
;
2627 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2629 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2630 && i
.op
[0].regs
->reg_num
== 1)
2632 as_bad (_("you can't `pop %%cs'"));
2635 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2636 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2639 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2643 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2645 /* For the string instructions that allow a segment override
2646 on one of their operands, the default segment is ds. */
2650 /* If a segment was explicitly specified,
2651 and the specified segment is not the default,
2652 use an opcode prefix to select it.
2653 If we never figured out what the default segment is,
2654 then default_seg will be zero at this point,
2655 and the specified segment prefix will always be used. */
2656 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2658 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2662 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2664 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2665 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2669 /* Handle conversion of 'int $3' --> special int3 insn. */
2670 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2672 i
.tm
.base_opcode
= INT3_OPCODE
;
2676 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2677 && i
.op
[0].disps
->X_op
== O_constant
)
2679 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2680 the absolute address given by the constant. Since ix86 jumps and
2681 calls are pc relative, we need to generate a reloc. */
2682 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2683 i
.op
[0].disps
->X_op
= O_symbol
;
2686 if (i
.tm
.opcode_modifier
& Rex64
)
2689 /* For 8bit registers we would need an empty rex prefix.
2690 Also in the case instruction is already having prefix,
2691 we need to convert old registers to new ones. */
2693 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2694 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2695 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2696 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2700 for (x
= 0; x
< 2; x
++)
2702 /* Look for 8bit operand that does use old registers. */
2703 if (i
.types
[x
] & Reg8
2704 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2706 /* In case it is "hi" register, give up. */
2707 if (i
.op
[x
].regs
->reg_num
> 3)
2708 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2709 i
.op
[x
].regs
->reg_name
);
2711 /* Otherwise it is equivalent to the extended register.
2712 Since the encoding don't change this is merely cosmetical
2713 cleanup for debug output. */
2715 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2720 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2722 | (i
.rex
.mode64
? 8 : 0)
2723 | (i
.rex
.extX
? 4 : 0)
2724 | (i
.rex
.extY
? 2 : 0)
2725 | (i
.rex
.extZ
? 1 : 0));
2727 /* We are ready to output the insn. */
2731 /* Tie dwarf2 debug info to the address at the start of the insn.
2732 We can't do this after the insn has been output as the current
2733 frag may have been closed off. eg. by frag_var. */
2734 dwarf2_emit_insn (0);
2737 if (i
.tm
.opcode_modifier
& Jump
)
2741 relax_substateT subtype
;
2746 if (flag_code
== CODE_16BIT
)
2750 if (i
.prefix
[DATA_PREFIX
])
2756 /* Pentium4 branch hints. */
2757 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2758 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2763 if (i
.prefix
[REX_PREFIX
])
2769 if (i
.prefixes
!= 0 && !intel_syntax
)
2770 as_warn (_("skipping prefixes on this instruction"));
2772 /* It's always a symbol; End frag & setup for relax.
2773 Make sure there is enough room in this frag for the largest
2774 instruction we may generate in md_convert_frag. This is 2
2775 bytes for the opcode and room for the prefix and largest
2777 frag_grow (prefix
+ 2 + 4);
2778 /* Prefix and 1 opcode byte go in fr_fix. */
2779 p
= frag_more (prefix
+ 1);
2780 if (i
.prefix
[DATA_PREFIX
])
2781 *p
++ = DATA_PREFIX_OPCODE
;
2782 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2783 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2784 *p
++ = i
.prefix
[SEG_PREFIX
];
2785 if (i
.prefix
[REX_PREFIX
])
2786 *p
++ = i
.prefix
[REX_PREFIX
];
2787 *p
= i
.tm
.base_opcode
;
2789 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2790 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2791 else if ((cpu_arch_flags
& Cpu386
) != 0)
2792 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2794 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2797 sym
= i
.op
[0].disps
->X_add_symbol
;
2798 off
= i
.op
[0].disps
->X_add_number
;
2800 if (i
.op
[0].disps
->X_op
!= O_constant
2801 && i
.op
[0].disps
->X_op
!= O_symbol
)
2803 /* Handle complex expressions. */
2804 sym
= make_expr_symbol (i
.op
[0].disps
);
2808 /* 1 possible extra opcode + 4 byte displacement go in var part.
2809 Pass reloc in fr_var. */
2810 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2812 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2816 if (i
.tm
.opcode_modifier
& JumpByte
)
2818 /* This is a loop or jecxz type instruction. */
2820 if (i
.prefix
[ADDR_PREFIX
])
2822 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2825 /* Pentium4 branch hints. */
2826 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2827 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2829 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2838 if (flag_code
== CODE_16BIT
)
2841 if (i
.prefix
[DATA_PREFIX
])
2843 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2853 if (i
.prefix
[REX_PREFIX
])
2855 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2859 if (i
.prefixes
!= 0 && !intel_syntax
)
2860 as_warn (_("skipping prefixes on this instruction"));
2862 p
= frag_more (1 + size
);
2863 *p
++ = i
.tm
.base_opcode
;
2865 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2866 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2868 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2875 if (flag_code
== CODE_16BIT
)
2879 if (i
.prefix
[DATA_PREFIX
])
2885 if (i
.prefix
[REX_PREFIX
])
2895 if (i
.prefixes
!= 0 && !intel_syntax
)
2896 as_warn (_("skipping prefixes on this instruction"));
2898 /* 1 opcode; 2 segment; offset */
2899 p
= frag_more (prefix
+ 1 + 2 + size
);
2901 if (i
.prefix
[DATA_PREFIX
])
2902 *p
++ = DATA_PREFIX_OPCODE
;
2904 if (i
.prefix
[REX_PREFIX
])
2905 *p
++ = i
.prefix
[REX_PREFIX
];
2907 *p
++ = i
.tm
.base_opcode
;
2908 if (i
.op
[1].imms
->X_op
== O_constant
)
2910 offsetT n
= i
.op
[1].imms
->X_add_number
;
2913 && !fits_in_unsigned_word (n
)
2914 && !fits_in_signed_word (n
))
2916 as_bad (_("16-bit jump out of range"));
2919 md_number_to_chars (p
, n
, size
);
2922 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2923 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2924 if (i
.op
[0].imms
->X_op
!= O_constant
)
2925 as_bad (_("can't handle non absolute segment in `%s'"),
2927 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2931 /* Output normal instructions here. */
2934 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2935 byte for the SSE instructions to specify prefix they require. */
2936 if (i
.tm
.base_opcode
& 0xff0000)
2937 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2939 /* The prefix bytes. */
2941 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2947 md_number_to_chars (p
, (valueT
) *q
, 1);
2951 /* Now the opcode; be careful about word order here! */
2952 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2954 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2959 /* Put out high byte first: can't use md_number_to_chars! */
2960 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2961 *p
= i
.tm
.base_opcode
& 0xff;
2964 /* Now the modrm byte and sib byte (if present). */
2965 if (i
.tm
.opcode_modifier
& Modrm
)
2968 md_number_to_chars (p
,
2969 (valueT
) (i
.rm
.regmem
<< 0
2973 /* If i.rm.regmem == ESP (4)
2974 && i.rm.mode != (Register mode)
2976 ==> need second modrm byte. */
2977 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2979 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2982 md_number_to_chars (p
,
2983 (valueT
) (i
.sib
.base
<< 0
2985 | i
.sib
.scale
<< 6),
2990 if (i
.disp_operands
)
2992 register unsigned int n
;
2994 for (n
= 0; n
< i
.operands
; n
++)
2996 if (i
.types
[n
] & Disp
)
2998 if (i
.op
[n
].disps
->X_op
== O_constant
)
3004 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3007 if (i
.types
[n
] & Disp8
)
3009 if (i
.types
[n
] & Disp64
)
3012 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3014 p
= frag_more (size
);
3015 md_number_to_chars (p
, val
, size
);
3021 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3023 /* The PC relative address is computed relative
3024 to the instruction boundary, so in case immediate
3025 fields follows, we need to adjust the value. */
3026 if (pcrel
&& i
.imm_operands
)
3029 register unsigned int n1
;
3031 for (n1
= 0; n1
< i
.operands
; n1
++)
3032 if (i
.types
[n1
] & Imm
)
3034 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3037 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3039 if (i
.types
[n1
] & Imm64
)
3044 /* We should find the immediate. */
3045 if (n1
== i
.operands
)
3047 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3050 if (i
.types
[n
] & Disp32S
)
3053 if (i
.types
[n
] & (Disp16
| Disp64
))
3056 if (i
.types
[n
] & Disp64
)
3060 p
= frag_more (size
);
3061 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3062 i
.op
[n
].disps
, pcrel
,
3063 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3069 /* Output immediate. */
3072 register unsigned int n
;
3074 for (n
= 0; n
< i
.operands
; n
++)
3076 if (i
.types
[n
] & Imm
)
3078 if (i
.op
[n
].imms
->X_op
== O_constant
)
3084 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3087 if (i
.types
[n
] & (Imm8
| Imm8S
))
3089 else if (i
.types
[n
] & Imm64
)
3092 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3094 p
= frag_more (size
);
3095 md_number_to_chars (p
, val
, size
);
3099 /* Not absolute_section.
3100 Need a 32-bit fixup (don't support 8bit
3101 non-absolute imms). Try to support other
3103 RELOC_ENUM reloc_type
;
3107 if ((i
.types
[n
] & (Imm32S
))
3108 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3110 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3113 if (i
.types
[n
] & (Imm8
| Imm8S
))
3115 if (i
.types
[n
] & Imm64
)
3119 p
= frag_more (size
);
3120 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3121 #ifdef BFD_ASSEMBLER
3122 if (reloc_type
== BFD_RELOC_32
3124 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3125 && (i
.op
[n
].imms
->X_op
== O_symbol
3126 || (i
.op
[n
].imms
->X_op
== O_add
3127 && ((symbol_get_value_expression
3128 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3131 /* We don't support dynamic linking on x86-64 yet. */
3132 if (flag_code
== CODE_64BIT
)
3134 reloc_type
= BFD_RELOC_386_GOTPC
;
3135 i
.op
[n
].imms
->X_add_number
+= 3;
3138 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3139 i
.op
[n
].imms
, 0, reloc_type
);
3151 #endif /* DEBUG386 */
3156 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3158 /* Parse operands of the form
3159 <symbol>@GOTOFF+<nnn>
3160 and similar .plt or .got references.
3162 If we find one, set up the correct relocation in RELOC and copy the
3163 input string, minus the `@GOTOFF' into a malloc'd buffer for
3164 parsing by the calling routine. Return this buffer, and if ADJUST
3165 is non-null set it to the length of the string we removed from the
3166 input line. Otherwise return NULL. */
3168 lex_got (reloc
, adjust
)
3172 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3173 static const struct {
3175 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3177 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3178 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3179 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3180 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3185 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3186 if (is_end_of_line
[(unsigned char) *cp
])
3189 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3193 len
= strlen (gotrel
[j
].str
);
3194 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3196 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3199 char *tmpbuf
, *past_reloc
;
3201 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3205 if (GOT_symbol
== NULL
)
3206 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3208 /* Replace the relocation token with ' ', so that
3209 errors like foo@GOTOFF1 will be detected. */
3211 /* The length of the first part of our input line. */
3212 first
= cp
- input_line_pointer
;
3214 /* The second part goes from after the reloc token until
3215 (and including) an end_of_line char. Don't use strlen
3216 here as the end_of_line char may not be a NUL. */
3217 past_reloc
= cp
+ 1 + len
;
3218 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3220 second
= cp
- past_reloc
;
3222 /* Allocate and copy string. The trailing NUL shouldn't
3223 be necessary, but be safe. */
3224 tmpbuf
= xmalloc (first
+ second
+ 2);
3225 memcpy (tmpbuf
, input_line_pointer
, first
);
3226 tmpbuf
[first
] = ' ';
3227 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3228 tmpbuf
[first
+ second
+ 1] = '\0';
3232 as_bad (_("@%s reloc is not supported in %s bit mode"),
3233 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3238 /* Might be a symbol version string. Don't as_bad here. */
3242 /* x86_cons_fix_new is called via the expression parsing code when a
3243 reloc is needed. We use this hook to get the correct .got reloc. */
3244 static RELOC_ENUM got_reloc
= NO_RELOC
;
3247 x86_cons_fix_new (frag
, off
, len
, exp
)
3253 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3254 got_reloc
= NO_RELOC
;
3255 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3259 x86_cons (exp
, size
)
3265 /* Handle @GOTOFF and the like in an expression. */
3267 char *gotfree_input_line
;
3270 save
= input_line_pointer
;
3271 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3272 if (gotfree_input_line
)
3273 input_line_pointer
= gotfree_input_line
;
3277 if (gotfree_input_line
)
3279 /* expression () has merrily parsed up to the end of line,
3280 or a comma - in the wrong buffer. Transfer how far
3281 input_line_pointer has moved to the right buffer. */
3282 input_line_pointer
= (save
3283 + (input_line_pointer
- gotfree_input_line
)
3285 free (gotfree_input_line
);
3293 static int i386_immediate
PARAMS ((char *));
3296 i386_immediate (imm_start
)
3299 char *save_input_line_pointer
;
3301 char *gotfree_input_line
;
3306 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3308 as_bad (_("only 1 or 2 immediate operands are allowed"));
3312 exp
= &im_expressions
[i
.imm_operands
++];
3313 i
.op
[this_operand
].imms
= exp
;
3315 if (is_space_char (*imm_start
))
3318 save_input_line_pointer
= input_line_pointer
;
3319 input_line_pointer
= imm_start
;
3322 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3323 if (gotfree_input_line
)
3324 input_line_pointer
= gotfree_input_line
;
3327 exp_seg
= expression (exp
);
3330 if (*input_line_pointer
)
3331 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3333 input_line_pointer
= save_input_line_pointer
;
3335 if (gotfree_input_line
)
3336 free (gotfree_input_line
);
3339 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3341 /* Missing or bad expr becomes absolute 0. */
3342 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3344 exp
->X_op
= O_constant
;
3345 exp
->X_add_number
= 0;
3346 exp
->X_add_symbol
= (symbolS
*) 0;
3347 exp
->X_op_symbol
= (symbolS
*) 0;
3349 else if (exp
->X_op
== O_constant
)
3351 /* Size it properly later. */
3352 i
.types
[this_operand
] |= Imm64
;
3353 /* If BFD64, sign extend val. */
3354 if (!use_rela_relocations
)
3355 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3356 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3358 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3360 #ifdef BFD_ASSEMBLER
3361 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3363 && exp_seg
!= text_section
3364 && exp_seg
!= data_section
3365 && exp_seg
!= bss_section
3366 && exp_seg
!= undefined_section
3367 #ifdef BFD_ASSEMBLER
3368 && !bfd_is_com_section (exp_seg
)
3372 #ifdef BFD_ASSEMBLER
3373 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3375 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3382 /* This is an address. The size of the address will be
3383 determined later, depending on destination register,
3384 suffix, or the default for the section. */
3385 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3391 static char *i386_scale
PARAMS ((char *));
3398 char *save
= input_line_pointer
;
3400 input_line_pointer
= scale
;
3401 val
= get_absolute_expression ();
3407 i
.log2_scale_factor
= 0;
3410 i
.log2_scale_factor
= 1;
3413 i
.log2_scale_factor
= 2;
3416 i
.log2_scale_factor
= 3;
3419 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3421 input_line_pointer
= save
;
3424 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3426 as_warn (_("scale factor of %d without an index register"),
3427 1 << i
.log2_scale_factor
);
3428 #if SCALE1_WHEN_NO_INDEX
3429 i
.log2_scale_factor
= 0;
3432 scale
= input_line_pointer
;
3433 input_line_pointer
= save
;
3437 static int i386_displacement
PARAMS ((char *, char *));
3440 i386_displacement (disp_start
, disp_end
)
3444 register expressionS
*exp
;
3446 char *save_input_line_pointer
;
3448 char *gotfree_input_line
;
3450 int bigdisp
= Disp32
;
3452 if (flag_code
== CODE_64BIT
)
3454 if (!i
.prefix
[ADDR_PREFIX
])
3457 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3459 i
.types
[this_operand
] |= bigdisp
;
3461 exp
= &disp_expressions
[i
.disp_operands
];
3462 i
.op
[this_operand
].disps
= exp
;
3464 save_input_line_pointer
= input_line_pointer
;
3465 input_line_pointer
= disp_start
;
3466 END_STRING_AND_SAVE (disp_end
);
3468 #ifndef GCC_ASM_O_HACK
3469 #define GCC_ASM_O_HACK 0
3472 END_STRING_AND_SAVE (disp_end
+ 1);
3473 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3474 && displacement_string_end
[-1] == '+')
3476 /* This hack is to avoid a warning when using the "o"
3477 constraint within gcc asm statements.
3480 #define _set_tssldt_desc(n,addr,limit,type) \
3481 __asm__ __volatile__ ( \
3483 "movw %w1,2+%0\n\t" \
3485 "movb %b1,4+%0\n\t" \
3486 "movb %4,5+%0\n\t" \
3487 "movb $0,6+%0\n\t" \
3488 "movb %h1,7+%0\n\t" \
3490 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3492 This works great except that the output assembler ends
3493 up looking a bit weird if it turns out that there is
3494 no offset. You end up producing code that looks like:
3507 So here we provide the missing zero. */
3509 *displacement_string_end
= '0';
3513 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3514 if (gotfree_input_line
)
3515 input_line_pointer
= gotfree_input_line
;
3518 exp_seg
= expression (exp
);
3521 if (*input_line_pointer
)
3522 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3524 RESTORE_END_STRING (disp_end
+ 1);
3526 RESTORE_END_STRING (disp_end
);
3527 input_line_pointer
= save_input_line_pointer
;
3529 if (gotfree_input_line
)
3530 free (gotfree_input_line
);
3533 #ifdef BFD_ASSEMBLER
3534 /* We do this to make sure that the section symbol is in
3535 the symbol table. We will ultimately change the relocation
3536 to be relative to the beginning of the section. */
3537 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3538 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3540 if (exp
->X_op
!= O_symbol
)
3542 as_bad (_("bad expression used with @%s"),
3543 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3549 if (S_IS_LOCAL (exp
->X_add_symbol
)
3550 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3551 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3552 exp
->X_op
= O_subtract
;
3553 exp
->X_op_symbol
= GOT_symbol
;
3554 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3555 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3557 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3561 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3563 /* Missing or bad expr becomes absolute 0. */
3564 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3566 exp
->X_op
= O_constant
;
3567 exp
->X_add_number
= 0;
3568 exp
->X_add_symbol
= (symbolS
*) 0;
3569 exp
->X_op_symbol
= (symbolS
*) 0;
3572 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3573 if (exp
->X_op
!= O_constant
3574 #ifdef BFD_ASSEMBLER
3575 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3577 && exp_seg
!= text_section
3578 && exp_seg
!= data_section
3579 && exp_seg
!= bss_section
3580 && exp_seg
!= undefined_section
)
3582 #ifdef BFD_ASSEMBLER
3583 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3585 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3590 else if (flag_code
== CODE_64BIT
)
3591 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3595 static int i386_index_check
PARAMS ((const char *));
3597 /* Make sure the memory operand we've been dealt is valid.
3598 Return 1 on success, 0 on a failure. */
3601 i386_index_check (operand_string
)
3602 const char *operand_string
;
3605 #if INFER_ADDR_PREFIX
3611 if (flag_code
== CODE_64BIT
)
3613 if (i
.prefix
[ADDR_PREFIX
] == 0)
3617 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3618 && (i
.base_reg
->reg_type
!= BaseIndex
3621 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3622 != (Reg64
|BaseIndex
))))
3629 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3631 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3632 != (Reg32
|BaseIndex
))))
3638 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3642 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3643 != (Reg16
|BaseIndex
)))
3645 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3646 != (Reg16
|BaseIndex
))
3648 && i
.base_reg
->reg_num
< 6
3649 && i
.index_reg
->reg_num
>= 6
3650 && i
.log2_scale_factor
== 0))))
3657 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3659 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3660 != (Reg32
|BaseIndex
))))
3666 #if INFER_ADDR_PREFIX
3667 if (flag_code
!= CODE_64BIT
3668 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3670 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3672 /* Change the size of any displacement too. At most one of
3673 Disp16 or Disp32 is set.
3674 FIXME. There doesn't seem to be any real need for separate
3675 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3676 Removing them would probably clean up the code quite a lot. */
3677 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3678 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3683 as_bad (_("`%s' is not a valid base/index expression"),
3687 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3689 flag_code_names
[flag_code
]);
3695 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3699 i386_operand (operand_string
)
3700 char *operand_string
;
3704 char *op_string
= operand_string
;
3706 if (is_space_char (*op_string
))
3709 /* We check for an absolute prefix (differentiating,
3710 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3711 if (*op_string
== ABSOLUTE_PREFIX
)
3714 if (is_space_char (*op_string
))
3716 i
.types
[this_operand
] |= JumpAbsolute
;
3719 /* Check if operand is a register. */
3720 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3721 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3723 /* Check for a segment override by searching for ':' after a
3724 segment register. */
3726 if (is_space_char (*op_string
))
3728 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3733 i
.seg
[i
.mem_operands
] = &es
;
3736 i
.seg
[i
.mem_operands
] = &cs
;
3739 i
.seg
[i
.mem_operands
] = &ss
;
3742 i
.seg
[i
.mem_operands
] = &ds
;
3745 i
.seg
[i
.mem_operands
] = &fs
;
3748 i
.seg
[i
.mem_operands
] = &gs
;
3752 /* Skip the ':' and whitespace. */
3754 if (is_space_char (*op_string
))
3757 if (!is_digit_char (*op_string
)
3758 && !is_identifier_char (*op_string
)
3759 && *op_string
!= '('
3760 && *op_string
!= ABSOLUTE_PREFIX
)
3762 as_bad (_("bad memory operand `%s'"), op_string
);
3765 /* Handle case of %es:*foo. */
3766 if (*op_string
== ABSOLUTE_PREFIX
)
3769 if (is_space_char (*op_string
))
3771 i
.types
[this_operand
] |= JumpAbsolute
;
3773 goto do_memory_reference
;
3777 as_bad (_("junk `%s' after register"), op_string
);
3780 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3781 i
.op
[this_operand
].regs
= r
;
3784 else if (*op_string
== REGISTER_PREFIX
)
3786 as_bad (_("bad register name `%s'"), op_string
);
3789 else if (*op_string
== IMMEDIATE_PREFIX
)
3792 if (i
.types
[this_operand
] & JumpAbsolute
)
3794 as_bad (_("immediate operand illegal with absolute jump"));
3797 if (!i386_immediate (op_string
))
3800 else if (is_digit_char (*op_string
)
3801 || is_identifier_char (*op_string
)
3802 || *op_string
== '(')
3804 /* This is a memory reference of some sort. */
3807 /* Start and end of displacement string expression (if found). */
3808 char *displacement_string_start
;
3809 char *displacement_string_end
;
3811 do_memory_reference
:
3812 if ((i
.mem_operands
== 1
3813 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3814 || i
.mem_operands
== 2)
3816 as_bad (_("too many memory references for `%s'"),
3817 current_templates
->start
->name
);
3821 /* Check for base index form. We detect the base index form by
3822 looking for an ')' at the end of the operand, searching
3823 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3825 base_string
= op_string
+ strlen (op_string
);
3828 if (is_space_char (*base_string
))
3831 /* If we only have a displacement, set-up for it to be parsed later. */
3832 displacement_string_start
= op_string
;
3833 displacement_string_end
= base_string
+ 1;
3835 if (*base_string
== ')')
3838 unsigned int parens_balanced
= 1;
3839 /* We've already checked that the number of left & right ()'s are
3840 equal, so this loop will not be infinite. */
3844 if (*base_string
== ')')
3846 if (*base_string
== '(')
3849 while (parens_balanced
);
3851 temp_string
= base_string
;
3853 /* Skip past '(' and whitespace. */
3855 if (is_space_char (*base_string
))
3858 if (*base_string
== ','
3859 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3860 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3862 displacement_string_end
= temp_string
;
3864 i
.types
[this_operand
] |= BaseIndex
;
3868 base_string
= end_op
;
3869 if (is_space_char (*base_string
))
3873 /* There may be an index reg or scale factor here. */
3874 if (*base_string
== ',')
3877 if (is_space_char (*base_string
))
3880 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3881 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3883 base_string
= end_op
;
3884 if (is_space_char (*base_string
))
3886 if (*base_string
== ',')
3889 if (is_space_char (*base_string
))
3892 else if (*base_string
!= ')')
3894 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3899 else if (*base_string
== REGISTER_PREFIX
)
3901 as_bad (_("bad register name `%s'"), base_string
);
3905 /* Check for scale factor. */
3906 if (*base_string
!= ')')
3908 char *end_scale
= i386_scale (base_string
);
3913 base_string
= end_scale
;
3914 if (is_space_char (*base_string
))
3916 if (*base_string
!= ')')
3918 as_bad (_("expecting `)' after scale factor in `%s'"),
3923 else if (!i
.index_reg
)
3925 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3930 else if (*base_string
!= ')')
3932 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3937 else if (*base_string
== REGISTER_PREFIX
)
3939 as_bad (_("bad register name `%s'"), base_string
);
3944 /* If there's an expression beginning the operand, parse it,
3945 assuming displacement_string_start and
3946 displacement_string_end are meaningful. */
3947 if (displacement_string_start
!= displacement_string_end
)
3949 if (!i386_displacement (displacement_string_start
,
3950 displacement_string_end
))
3954 /* Special case for (%dx) while doing input/output op. */
3956 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3958 && i
.log2_scale_factor
== 0
3959 && i
.seg
[i
.mem_operands
] == 0
3960 && (i
.types
[this_operand
] & Disp
) == 0)
3962 i
.types
[this_operand
] = InOutPortReg
;
3966 if (i386_index_check (operand_string
) == 0)
3972 /* It's not a memory operand; argh! */
3973 as_bad (_("invalid char %s beginning operand %d `%s'"),
3974 output_invalid (*op_string
),
3979 return 1; /* Normal return. */
3982 /* md_estimate_size_before_relax()
3984 Called just before relax() for rs_machine_dependent frags. The x86
3985 assembler uses these frags to handle variable size jump
3988 Any symbol that is now undefined will not become defined.
3989 Return the correct fr_subtype in the frag.
3990 Return the initial "guess for variable size of frag" to caller.
3991 The guess is actually the growth beyond the fixed part. Whatever
3992 we do to grow the fixed or variable part contributes to our
3996 md_estimate_size_before_relax (fragP
, segment
)
3997 register fragS
*fragP
;
3998 register segT segment
;
4000 /* We've already got fragP->fr_subtype right; all we have to do is
4001 check for un-relaxable symbols. On an ELF system, we can't relax
4002 an externally visible symbol, because it may be overridden by a
4004 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4006 || S_IS_EXTERNAL (fragP
->fr_symbol
)
4007 || S_IS_WEAK (fragP
->fr_symbol
)
4011 /* Symbol is undefined in this segment, or we need to keep a
4012 reloc so that weak symbols can be overridden. */
4013 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4014 RELOC_ENUM reloc_type
;
4015 unsigned char *opcode
;
4018 if (fragP
->fr_var
!= NO_RELOC
)
4019 reloc_type
= fragP
->fr_var
;
4021 reloc_type
= BFD_RELOC_16_PCREL
;
4023 reloc_type
= BFD_RELOC_32_PCREL
;
4025 old_fr_fix
= fragP
->fr_fix
;
4026 opcode
= (unsigned char *) fragP
->fr_opcode
;
4028 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4031 /* Make jmp (0xeb) a (d)word displacement jump. */
4033 fragP
->fr_fix
+= size
;
4034 fix_new (fragP
, old_fr_fix
, size
,
4036 fragP
->fr_offset
, 1,
4041 if (no_cond_jump_promotion
)
4046 /* Negate the condition, and branch past an
4047 unconditional jump. */
4050 /* Insert an unconditional jump. */
4052 /* We added two extra opcode bytes, and have a two byte
4054 fragP
->fr_fix
+= 2 + 2;
4055 fix_new (fragP
, old_fr_fix
+ 2, 2,
4057 fragP
->fr_offset
, 1,
4064 if (no_cond_jump_promotion
)
4067 /* This changes the byte-displacement jump 0x7N
4068 to the (d)word-displacement jump 0x0f,0x8N. */
4069 opcode
[1] = opcode
[0] + 0x10;
4070 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4071 /* We've added an opcode byte. */
4072 fragP
->fr_fix
+= 1 + size
;
4073 fix_new (fragP
, old_fr_fix
+ 1, size
,
4075 fragP
->fr_offset
, 1,
4080 BAD_CASE (fragP
->fr_subtype
);
4084 return fragP
->fr_fix
- old_fr_fix
;
4088 /* Guess size depending on current relax state. Initially the relax
4089 state will correspond to a short jump and we return 1, because
4090 the variable part of the frag (the branch offset) is one byte
4091 long. However, we can relax a section more than once and in that
4092 case we must either set fr_subtype back to the unrelaxed state,
4093 or return the value for the appropriate branch. */
4094 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4097 /* Called after relax() is finished.
4099 In: Address of frag.
4100 fr_type == rs_machine_dependent.
4101 fr_subtype is what the address relaxed to.
4103 Out: Any fixSs and constants are set up.
4104 Caller will turn frag into a ".space 0". */
4106 #ifndef BFD_ASSEMBLER
4108 md_convert_frag (headers
, sec
, fragP
)
4109 object_headers
*headers ATTRIBUTE_UNUSED
;
4110 segT sec ATTRIBUTE_UNUSED
;
4111 register fragS
*fragP
;
4114 md_convert_frag (abfd
, sec
, fragP
)
4115 bfd
*abfd ATTRIBUTE_UNUSED
;
4116 segT sec ATTRIBUTE_UNUSED
;
4117 register fragS
*fragP
;
4120 register unsigned char *opcode
;
4121 unsigned char *where_to_put_displacement
= NULL
;
4122 offsetT target_address
;
4123 offsetT opcode_address
;
4124 unsigned int extension
= 0;
4125 offsetT displacement_from_opcode_start
;
4127 opcode
= (unsigned char *) fragP
->fr_opcode
;
4129 /* Address we want to reach in file space. */
4130 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4132 /* Address opcode resides at in file space. */
4133 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4135 /* Displacement from opcode start to fill into instruction. */
4136 displacement_from_opcode_start
= target_address
- opcode_address
;
4138 if ((fragP
->fr_subtype
& BIG
) == 0)
4140 /* Don't have to change opcode. */
4141 extension
= 1; /* 1 opcode + 1 displacement */
4142 where_to_put_displacement
= &opcode
[1];
4146 if (no_cond_jump_promotion
4147 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4148 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4150 switch (fragP
->fr_subtype
)
4152 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4153 extension
= 4; /* 1 opcode + 4 displacement */
4155 where_to_put_displacement
= &opcode
[1];
4158 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4159 extension
= 2; /* 1 opcode + 2 displacement */
4161 where_to_put_displacement
= &opcode
[1];
4164 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4165 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4166 extension
= 5; /* 2 opcode + 4 displacement */
4167 opcode
[1] = opcode
[0] + 0x10;
4168 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4169 where_to_put_displacement
= &opcode
[2];
4172 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4173 extension
= 3; /* 2 opcode + 2 displacement */
4174 opcode
[1] = opcode
[0] + 0x10;
4175 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4176 where_to_put_displacement
= &opcode
[2];
4179 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4184 where_to_put_displacement
= &opcode
[3];
4188 BAD_CASE (fragP
->fr_subtype
);
4193 /* Now put displacement after opcode. */
4194 md_number_to_chars ((char *) where_to_put_displacement
,
4195 (valueT
) (displacement_from_opcode_start
- extension
),
4196 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4197 fragP
->fr_fix
+= extension
;
4200 /* Size of byte displacement jmp. */
4201 int md_short_jump_size
= 2;
4203 /* Size of dword displacement jmp. */
4204 int md_long_jump_size
= 5;
4206 /* Size of relocation record. */
4207 const int md_reloc_size
= 8;
4210 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4212 addressT from_addr
, to_addr
;
4213 fragS
*frag ATTRIBUTE_UNUSED
;
4214 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4218 offset
= to_addr
- (from_addr
+ 2);
4219 /* Opcode for byte-disp jump. */
4220 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4221 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4225 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4227 addressT from_addr
, to_addr
;
4228 fragS
*frag ATTRIBUTE_UNUSED
;
4229 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4233 offset
= to_addr
- (from_addr
+ 5);
4234 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4235 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4238 /* Apply a fixup (fixS) to segment data, once it has been determined
4239 by our caller that we have all the info we need to fix it up.
4241 On the 386, immediates, displacements, and data pointers are all in
4242 the same (little-endian) format, so we don't need to care about which
4246 md_apply_fix3 (fixP
, valP
, seg
)
4247 /* The fix we're to put in. */
4249 /* Pointer to the value of the bits. */
4251 /* Segment fix is from. */
4252 segT seg ATTRIBUTE_UNUSED
;
4254 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4255 valueT value
= * valP
;
4257 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4260 switch (fixP
->fx_r_type
)
4266 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4269 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4272 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4277 /* This is a hack. There should be a better way to handle this.
4278 This covers for the fact that bfd_install_relocation will
4279 subtract the current location (for partial_inplace, PC relative
4280 relocations); see more below. */
4281 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4282 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4283 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4284 && fixP
->fx_addsy
&& !use_rela_relocations
)
4287 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4289 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4292 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4295 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4297 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4300 || (symbol_section_p (fixP
->fx_addsy
)
4301 && fseg
!= absolute_section
))
4302 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4303 && ! S_IS_WEAK (fixP
->fx_addsy
)
4304 && S_IS_DEFINED (fixP
->fx_addsy
)
4305 && ! S_IS_COMMON (fixP
->fx_addsy
))
4307 /* Yes, we add the values in twice. This is because
4308 bfd_perform_relocation subtracts them out again. I think
4309 bfd_perform_relocation is broken, but I don't dare change
4311 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4315 #if defined (OBJ_COFF) && defined (TE_PE)
4316 /* For some reason, the PE format does not store a section
4317 address offset for a PC relative symbol. */
4318 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4319 value
+= md_pcrel_from (fixP
);
4323 /* Fix a few things - the dynamic linker expects certain values here,
4324 and we must not dissappoint it. */
4325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4326 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4328 switch (fixP
->fx_r_type
)
4330 case BFD_RELOC_386_PLT32
:
4331 case BFD_RELOC_X86_64_PLT32
:
4332 /* Make the jump instruction point to the address of the operand. At
4333 runtime we merely add the offset to the actual PLT entry. */
4336 case BFD_RELOC_386_GOTPC
:
4338 /* This is tough to explain. We end up with this one if we have
4339 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4340 * here is to obtain the absolute address of the GOT, and it is strongly
4341 * preferable from a performance point of view to avoid using a runtime
4342 * relocation for this. The actual sequence of instructions often look
4348 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4350 * The call and pop essentially return the absolute address of
4351 * the label .L66 and store it in %ebx. The linker itself will
4352 * ultimately change the first operand of the addl so that %ebx points to
4353 * the GOT, but to keep things simple, the .o file must have this operand
4354 * set so that it generates not the absolute address of .L66, but the
4355 * absolute address of itself. This allows the linker itself simply
4356 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4357 * added in, and the addend of the relocation is stored in the operand
4358 * field for the instruction itself.
4360 * Our job here is to fix the operand so that it would add the correct
4361 * offset so that %ebx would point to itself. The thing that is tricky is
4362 * that .-.L66 will point to the beginning of the instruction, so we need
4363 * to further modify the operand so that it will point to itself.
4364 * There are other cases where you have something like:
4366 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4368 * and here no correction would be required. Internally in the assembler
4369 * we treat operands of this form as not being pcrel since the '.' is
4370 * explicitly mentioned, and I wonder whether it would simplify matters
4371 * to do it this way. Who knows. In earlier versions of the PIC patches,
4372 * the pcrel_adjust field was used to store the correction, but since the
4373 * expression is not pcrel, I felt it would be confusing to do it this
4378 case BFD_RELOC_386_GOT32
:
4379 case BFD_RELOC_X86_64_GOT32
:
4380 value
= 0; /* Fully resolved at runtime. No addend. */
4382 case BFD_RELOC_386_GOTOFF
:
4383 case BFD_RELOC_X86_64_GOTPCREL
:
4386 case BFD_RELOC_VTABLE_INHERIT
:
4387 case BFD_RELOC_VTABLE_ENTRY
:
4394 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4396 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4398 /* Are we finished with this relocation now? */
4399 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4401 #ifdef BFD_ASSEMBLER
4402 else if (use_rela_relocations
)
4404 fixP
->fx_no_overflow
= 1;
4408 md_number_to_chars (p
, value
, fixP
->fx_size
);
4411 #define MAX_LITTLENUMS 6
4413 /* Turn the string pointed to by litP into a floating point constant
4414 of type TYPE, and emit the appropriate bytes. The number of
4415 LITTLENUMS emitted is stored in *SIZEP. An error message is
4416 returned, or NULL on OK. */
4419 md_atof (type
, litP
, sizeP
)
4425 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4426 LITTLENUM_TYPE
*wordP
;
4448 return _("Bad call to md_atof ()");
4450 t
= atof_ieee (input_line_pointer
, type
, words
);
4452 input_line_pointer
= t
;
4454 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4455 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4456 the bigendian 386. */
4457 for (wordP
= words
+ prec
- 1; prec
--;)
4459 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4460 litP
+= sizeof (LITTLENUM_TYPE
);
4465 char output_invalid_buf
[8];
4472 sprintf (output_invalid_buf
, "'%c'", c
);
4474 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4475 return output_invalid_buf
;
4478 /* REG_STRING starts *before* REGISTER_PREFIX. */
4480 static const reg_entry
*
4481 parse_register (reg_string
, end_op
)
4485 char *s
= reg_string
;
4487 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4490 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4491 if (*s
== REGISTER_PREFIX
)
4494 if (is_space_char (*s
))
4498 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4500 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4501 return (const reg_entry
*) NULL
;
4505 /* For naked regs, make sure that we are not dealing with an identifier.
4506 This prevents confusing an identifier like `eax_var' with register
4508 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4509 return (const reg_entry
*) NULL
;
4513 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4515 /* Handle floating point regs, allowing spaces in the (i) part. */
4516 if (r
== i386_regtab
/* %st is first entry of table */)
4518 if (is_space_char (*s
))
4523 if (is_space_char (*s
))
4525 if (*s
>= '0' && *s
<= '7')
4527 r
= &i386_float_regtab
[*s
- '0'];
4529 if (is_space_char (*s
))
4537 /* We have "%st(" then garbage. */
4538 return (const reg_entry
*) NULL
;
4543 && r
->reg_flags
& (RegRex64
|RegRex
)
4544 && flag_code
!= CODE_64BIT
)
4546 return (const reg_entry
*) NULL
;
4552 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4553 const char *md_shortopts
= "kVQ:sq";
4555 const char *md_shortopts
= "q";
4558 struct option md_longopts
[] = {
4559 #define OPTION_32 (OPTION_MD_BASE + 0)
4560 {"32", no_argument
, NULL
, OPTION_32
},
4561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4562 #define OPTION_64 (OPTION_MD_BASE + 1)
4563 {"64", no_argument
, NULL
, OPTION_64
},
4565 {NULL
, no_argument
, NULL
, 0}
4567 size_t md_longopts_size
= sizeof (md_longopts
);
4570 md_parse_option (c
, arg
)
4572 char *arg ATTRIBUTE_UNUSED
;
4580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4581 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4582 should be emitted or not. FIXME: Not implemented. */
4586 /* -V: SVR4 argument to print version ID. */
4588 print_version_id ();
4591 /* -k: Ignore for FreeBSD compatibility. */
4596 /* -s: On i386 Solaris, this tells the native assembler to use
4597 .stab instead of .stab.excl. We always use .stab anyhow. */
4602 const char **list
, **l
;
4604 list
= bfd_target_list ();
4605 for (l
= list
; *l
!= NULL
; l
++)
4606 if (strcmp (*l
, "elf64-x86-64") == 0)
4608 default_arch
= "x86_64";
4612 as_fatal (_("No compiled in support for x86_64"));
4619 default_arch
= "i386";
4629 md_show_usage (stream
)
4632 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4633 fprintf (stream
, _("\
4635 -V print assembler version number\n\
4637 -q quieten some warnings\n\
4640 fprintf (stream
, _("\
4641 -q quieten some warnings\n"));
4645 #ifdef BFD_ASSEMBLER
4646 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4647 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4649 /* Pick the target format to use. */
4652 i386_target_format ()
4654 if (!strcmp (default_arch
, "x86_64"))
4655 set_code_flag (CODE_64BIT
);
4656 else if (!strcmp (default_arch
, "i386"))
4657 set_code_flag (CODE_32BIT
);
4659 as_fatal (_("Unknown architecture"));
4660 switch (OUTPUT_FLAVOR
)
4662 #ifdef OBJ_MAYBE_AOUT
4663 case bfd_target_aout_flavour
:
4664 return AOUT_TARGET_FORMAT
;
4666 #ifdef OBJ_MAYBE_COFF
4667 case bfd_target_coff_flavour
:
4670 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4671 case bfd_target_elf_flavour
:
4673 if (flag_code
== CODE_64BIT
)
4674 use_rela_relocations
= 1;
4675 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4684 #endif /* OBJ_MAYBE_ more than one */
4686 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4687 void i386_elf_emit_arch_note ()
4689 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4690 && cpu_arch_name
!= NULL
)
4693 asection
*seg
= now_seg
;
4694 subsegT subseg
= now_subseg
;
4695 Elf_Internal_Note i_note
;
4696 Elf_External_Note e_note
;
4697 asection
*note_secp
;
4700 /* Create the .note section. */
4701 note_secp
= subseg_new (".note", 0);
4702 bfd_set_section_flags (stdoutput
,
4704 SEC_HAS_CONTENTS
| SEC_READONLY
);
4706 /* Process the arch string. */
4707 len
= strlen (cpu_arch_name
);
4709 i_note
.namesz
= len
+ 1;
4711 i_note
.type
= NT_ARCH
;
4712 p
= frag_more (sizeof (e_note
.namesz
));
4713 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4714 p
= frag_more (sizeof (e_note
.descsz
));
4715 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4716 p
= frag_more (sizeof (e_note
.type
));
4717 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4718 p
= frag_more (len
+ 1);
4719 strcpy (p
, cpu_arch_name
);
4721 frag_align (2, 0, 0);
4723 subseg_set (seg
, subseg
);
4727 #endif /* BFD_ASSEMBLER */
4730 md_undefined_symbol (name
)
4733 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4734 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4735 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4736 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4740 if (symbol_find (name
))
4741 as_bad (_("GOT already in symbol table"));
4742 GOT_symbol
= symbol_new (name
, undefined_section
,
4743 (valueT
) 0, &zero_address_frag
);
4750 /* Round up a section size to the appropriate boundary. */
4753 md_section_align (segment
, size
)
4754 segT segment ATTRIBUTE_UNUSED
;
4757 #ifdef BFD_ASSEMBLER
4758 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4759 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4761 /* For a.out, force the section size to be aligned. If we don't do
4762 this, BFD will align it for us, but it will not write out the
4763 final bytes of the section. This may be a bug in BFD, but it is
4764 easier to fix it here since that is how the other a.out targets
4768 align
= bfd_get_section_alignment (stdoutput
, segment
);
4769 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4777 /* On the i386, PC-relative offsets are relative to the start of the
4778 next instruction. That is, the address of the offset, plus its
4779 size, since the offset is always the last part of the insn. */
4782 md_pcrel_from (fixP
)
4785 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4792 int ignore ATTRIBUTE_UNUSED
;
4796 temp
= get_absolute_expression ();
4797 subseg_set (bss_section
, (subsegT
) temp
);
4798 demand_empty_rest_of_line ();
4803 #ifdef BFD_ASSEMBLER
4806 i386_validate_fix (fixp
)
4809 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4811 /* GOTOFF relocation are nonsense in 64bit mode. */
4812 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4814 if (flag_code
!= CODE_64BIT
)
4816 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4820 if (flag_code
== CODE_64BIT
)
4822 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4829 tc_gen_reloc (section
, fixp
)
4830 asection
*section ATTRIBUTE_UNUSED
;
4834 bfd_reloc_code_real_type code
;
4836 switch (fixp
->fx_r_type
)
4838 case BFD_RELOC_X86_64_PLT32
:
4839 case BFD_RELOC_X86_64_GOT32
:
4840 case BFD_RELOC_X86_64_GOTPCREL
:
4841 case BFD_RELOC_386_PLT32
:
4842 case BFD_RELOC_386_GOT32
:
4843 case BFD_RELOC_386_GOTOFF
:
4844 case BFD_RELOC_386_GOTPC
:
4845 case BFD_RELOC_X86_64_32S
:
4847 case BFD_RELOC_VTABLE_ENTRY
:
4848 case BFD_RELOC_VTABLE_INHERIT
:
4849 code
= fixp
->fx_r_type
;
4854 switch (fixp
->fx_size
)
4857 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4858 _("can not do %d byte pc-relative relocation"),
4860 code
= BFD_RELOC_32_PCREL
;
4862 case 1: code
= BFD_RELOC_8_PCREL
; break;
4863 case 2: code
= BFD_RELOC_16_PCREL
; break;
4864 case 4: code
= BFD_RELOC_32_PCREL
; break;
4869 switch (fixp
->fx_size
)
4872 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4873 _("can not do %d byte relocation"),
4875 code
= BFD_RELOC_32
;
4877 case 1: code
= BFD_RELOC_8
; break;
4878 case 2: code
= BFD_RELOC_16
; break;
4879 case 4: code
= BFD_RELOC_32
; break;
4880 case 8: code
= BFD_RELOC_64
; break;
4886 if (code
== BFD_RELOC_32
4888 && fixp
->fx_addsy
== GOT_symbol
)
4890 /* We don't support GOTPC on 64bit targets. */
4891 if (flag_code
== CODE_64BIT
)
4893 code
= BFD_RELOC_386_GOTPC
;
4896 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4897 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4898 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4900 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4901 if (!use_rela_relocations
)
4903 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4904 vtable entry to be used in the relocation's section offset. */
4905 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4906 rel
->address
= fixp
->fx_offset
;
4909 rel
->addend
= fixp
->fx_addnumber
;
4913 /* Use the rela in 64bit mode. */
4916 rel
->addend
= fixp
->fx_offset
;
4918 rel
->addend
-= fixp
->fx_size
;
4921 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4922 if (rel
->howto
== NULL
)
4924 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4925 _("cannot represent relocation type %s"),
4926 bfd_get_reloc_code_name (code
));
4927 /* Set howto to a garbage value so that we can keep going. */
4928 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4929 assert (rel
->howto
!= NULL
);
4935 #else /* ! BFD_ASSEMBLER */
4937 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4939 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4942 relax_addressT segment_address_in_file
;
4944 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4945 Out: GNU LD relocation length code: 0, 1, or 2. */
4947 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4950 know (fixP
->fx_addsy
!= NULL
);
4952 md_number_to_chars (where
,
4953 (valueT
) (fixP
->fx_frag
->fr_address
4954 + fixP
->fx_where
- segment_address_in_file
),
4957 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4958 ? S_GET_TYPE (fixP
->fx_addsy
)
4959 : fixP
->fx_addsy
->sy_number
);
4961 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4962 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4963 where
[4] = r_symbolnum
& 0x0ff;
4964 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4965 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4966 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4969 #endif /* OBJ_AOUT or OBJ_BOUT. */
4971 #if defined (I386COFF)
4974 tc_coff_fix2rtype (fixP
)
4977 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4980 return (fixP
->fx_pcrel
?
4981 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4982 fixP
->fx_size
== 2 ? R_PCRWORD
:
4984 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4985 fixP
->fx_size
== 2 ? R_RELWORD
:
4990 tc_coff_sizemachdep (frag
)
4994 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4999 #endif /* I386COFF */
5001 #endif /* ! BFD_ASSEMBLER */
5003 /* Parse operands using Intel syntax. This implements a recursive descent
5004 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5007 FIXME: We do not recognize the full operand grammar defined in the MASM
5008 documentation. In particular, all the structure/union and
5009 high-level macro operands are missing.
5011 Uppercase words are terminals, lower case words are non-terminals.
5012 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5013 bars '|' denote choices. Most grammar productions are implemented in
5014 functions called 'intel_<production>'.
5016 Initial production is 'expr'.
5022 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5024 constant digits [[ radixOverride ]]
5026 dataType BYTE | WORD | DWORD | QWORD | XWORD
5059 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5060 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5062 hexdigit a | b | c | d | e | f
5063 | A | B | C | D | E | F
5073 register specialRegister
5077 segmentRegister CS | DS | ES | FS | GS | SS
5079 specialRegister CR0 | CR2 | CR3
5080 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5081 | TR3 | TR4 | TR5 | TR6 | TR7
5083 We simplify the grammar in obvious places (e.g., register parsing is
5084 done by calling parse_register) and eliminate immediate left recursion
5085 to implement a recursive-descent parser.
5125 /* Parsing structure for the intel syntax parser. Used to implement the
5126 semantic actions for the operand grammar. */
5127 struct intel_parser_s
5129 char *op_string
; /* The string being parsed. */
5130 int got_a_float
; /* Whether the operand is a float. */
5131 int op_modifier
; /* Operand modifier. */
5132 int is_mem
; /* 1 if operand is memory reference. */
5133 const reg_entry
*reg
; /* Last register reference found. */
5134 char *disp
; /* Displacement string being built. */
5137 static struct intel_parser_s intel_parser
;
5139 /* Token structure for parsing intel syntax. */
5142 int code
; /* Token code. */
5143 const reg_entry
*reg
; /* Register entry for register tokens. */
5144 char *str
; /* String representation. */
5147 static struct intel_token cur_token
, prev_token
;
5149 /* Token codes for the intel parser. Since T_SHORT is already used
5150 by COFF, undefine it first to prevent a warning. */
5165 /* Prototypes for intel parser functions. */
5166 static int intel_match_token
PARAMS ((int code
));
5167 static void intel_get_token
PARAMS ((void));
5168 static void intel_putback_token
PARAMS ((void));
5169 static int intel_expr
PARAMS ((void));
5170 static int intel_e05
PARAMS ((void));
5171 static int intel_e05_1
PARAMS ((void));
5172 static int intel_e06
PARAMS ((void));
5173 static int intel_e06_1
PARAMS ((void));
5174 static int intel_e09
PARAMS ((void));
5175 static int intel_e09_1
PARAMS ((void));
5176 static int intel_e10
PARAMS ((void));
5177 static int intel_e10_1
PARAMS ((void));
5178 static int intel_e11
PARAMS ((void));
5181 i386_intel_operand (operand_string
, got_a_float
)
5182 char *operand_string
;
5188 /* Initialize token holders. */
5189 cur_token
.code
= prev_token
.code
= T_NIL
;
5190 cur_token
.reg
= prev_token
.reg
= NULL
;
5191 cur_token
.str
= prev_token
.str
= NULL
;
5193 /* Initialize parser structure. */
5194 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5197 strcpy (intel_parser
.op_string
, operand_string
);
5198 intel_parser
.got_a_float
= got_a_float
;
5199 intel_parser
.op_modifier
= -1;
5200 intel_parser
.is_mem
= 0;
5201 intel_parser
.reg
= NULL
;
5202 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5203 if (intel_parser
.disp
== NULL
)
5205 intel_parser
.disp
[0] = '\0';
5207 /* Read the first token and start the parser. */
5209 ret
= intel_expr ();
5213 /* If we found a memory reference, hand it over to i386_displacement
5214 to fill in the rest of the operand fields. */
5215 if (intel_parser
.is_mem
)
5217 if ((i
.mem_operands
== 1
5218 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5219 || i
.mem_operands
== 2)
5221 as_bad (_("too many memory references for '%s'"),
5222 current_templates
->start
->name
);
5227 char *s
= intel_parser
.disp
;
5230 /* Add the displacement expression. */
5232 ret
= i386_displacement (s
, s
+ strlen (s
))
5233 && i386_index_check (s
);
5237 /* Constant and OFFSET expressions are handled by i386_immediate. */
5238 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5239 || intel_parser
.reg
== NULL
)
5240 ret
= i386_immediate (intel_parser
.disp
);
5244 free (intel_parser
.disp
);
5254 /* expr SHORT e05 */
5255 if (cur_token
.code
== T_SHORT
)
5257 intel_parser
.op_modifier
= SHORT
;
5258 intel_match_token (T_SHORT
);
5260 return (intel_e05 ());
5265 return intel_e05 ();
5275 return (intel_e06 () && intel_e05_1 ());
5281 /* e05' addOp e06 e05' */
5282 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5284 strcat (intel_parser
.disp
, cur_token
.str
);
5285 intel_match_token (cur_token
.code
);
5287 return (intel_e06 () && intel_e05_1 ());
5302 return (intel_e09 () && intel_e06_1 ());
5308 /* e06' mulOp e09 e06' */
5309 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5311 strcat (intel_parser
.disp
, cur_token
.str
);
5312 intel_match_token (cur_token
.code
);
5314 return (intel_e09 () && intel_e06_1 ());
5322 /* e09 OFFSET e10 e09'
5331 /* e09 OFFSET e10 e09' */
5332 if (cur_token
.code
== T_OFFSET
)
5334 intel_parser
.is_mem
= 0;
5335 intel_parser
.op_modifier
= OFFSET_FLAT
;
5336 intel_match_token (T_OFFSET
);
5338 return (intel_e10 () && intel_e09_1 ());
5343 return (intel_e10 () && intel_e09_1 ());
5349 /* e09' PTR e10 e09' */
5350 if (cur_token
.code
== T_PTR
)
5352 if (prev_token
.code
== T_BYTE
)
5353 i
.suffix
= BYTE_MNEM_SUFFIX
;
5355 else if (prev_token
.code
== T_WORD
)
5357 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5358 i
.suffix
= SHORT_MNEM_SUFFIX
;
5360 i
.suffix
= WORD_MNEM_SUFFIX
;
5363 else if (prev_token
.code
== T_DWORD
)
5365 if (intel_parser
.got_a_float
== 1) /* "f..." */
5366 i
.suffix
= SHORT_MNEM_SUFFIX
;
5368 i
.suffix
= LONG_MNEM_SUFFIX
;
5371 else if (prev_token
.code
== T_QWORD
)
5373 if (intel_parser
.got_a_float
== 1) /* "f..." */
5374 i
.suffix
= LONG_MNEM_SUFFIX
;
5376 i
.suffix
= QWORD_MNEM_SUFFIX
;
5379 else if (prev_token
.code
== T_XWORD
)
5380 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5384 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5388 intel_match_token (T_PTR
);
5390 return (intel_e10 () && intel_e09_1 ());
5393 /* e09 : e10 e09' */
5394 else if (cur_token
.code
== ':')
5396 /* Mark as a memory operand only if it's not already known to be an
5397 offset expression. */
5398 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5399 intel_parser
.is_mem
= 1;
5401 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5416 return (intel_e11 () && intel_e10_1 ());
5422 /* e10' [ expr ] e10' */
5423 if (cur_token
.code
== '[')
5425 intel_match_token ('[');
5427 /* Mark as a memory operand only if it's not already known to be an
5428 offset expression. If it's an offset expression, we need to keep
5430 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5431 intel_parser
.is_mem
= 1;
5433 strcat (intel_parser
.disp
, "[");
5435 /* Add a '+' to the displacement string if necessary. */
5436 if (*intel_parser
.disp
!= '\0'
5437 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5438 strcat (intel_parser
.disp
, "+");
5440 if (intel_expr () && intel_match_token (']'))
5442 /* Preserve brackets when the operand is an offset expression. */
5443 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5444 strcat (intel_parser
.disp
, "]");
5446 return intel_e10_1 ();
5473 if (cur_token
.code
== '(')
5475 intel_match_token ('(');
5476 strcat (intel_parser
.disp
, "(");
5478 if (intel_expr () && intel_match_token (')'))
5480 strcat (intel_parser
.disp
, ")");
5488 else if (cur_token
.code
== '[')
5490 intel_match_token ('[');
5492 /* Mark as a memory operand only if it's not already known to be an
5493 offset expression. If it's an offset expression, we need to keep
5495 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5496 intel_parser
.is_mem
= 1;
5498 strcat (intel_parser
.disp
, "[");
5500 /* Operands for jump/call inside brackets denote absolute addresses. */
5501 if (current_templates
->start
->opcode_modifier
& Jump
5502 || current_templates
->start
->opcode_modifier
& JumpDword
5503 || current_templates
->start
->opcode_modifier
& JumpByte
5504 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5505 i
.types
[this_operand
] |= JumpAbsolute
;
5507 /* Add a '+' to the displacement string if necessary. */
5508 if (*intel_parser
.disp
!= '\0'
5509 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5510 strcat (intel_parser
.disp
, "+");
5512 if (intel_expr () && intel_match_token (']'))
5514 /* Preserve brackets when the operand is an offset expression. */
5515 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5516 strcat (intel_parser
.disp
, "]");
5529 else if (cur_token
.code
== T_BYTE
5530 || cur_token
.code
== T_WORD
5531 || cur_token
.code
== T_DWORD
5532 || cur_token
.code
== T_QWORD
5533 || cur_token
.code
== T_XWORD
)
5535 intel_match_token (cur_token
.code
);
5542 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5544 strcat (intel_parser
.disp
, cur_token
.str
);
5545 intel_match_token (cur_token
.code
);
5547 /* Mark as a memory operand only if it's not already known to be an
5548 offset expression. */
5549 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5550 intel_parser
.is_mem
= 1;
5556 else if (cur_token
.code
== T_REG
)
5558 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5560 intel_match_token (T_REG
);
5562 /* Check for segment change. */
5563 if (cur_token
.code
== ':')
5565 if (reg
->reg_type
& (SReg2
| SReg3
))
5567 switch (reg
->reg_num
)
5570 i
.seg
[i
.mem_operands
] = &es
;
5573 i
.seg
[i
.mem_operands
] = &cs
;
5576 i
.seg
[i
.mem_operands
] = &ss
;
5579 i
.seg
[i
.mem_operands
] = &ds
;
5582 i
.seg
[i
.mem_operands
] = &fs
;
5585 i
.seg
[i
.mem_operands
] = &gs
;
5591 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5596 /* Not a segment register. Check for register scaling. */
5597 else if (cur_token
.code
== '*')
5599 if (!intel_parser
.is_mem
)
5601 as_bad (_("Register scaling only allowed in memory operands."));
5605 /* What follows must be a valid scale. */
5606 if (intel_match_token ('*')
5607 && strchr ("01248", *cur_token
.str
))
5610 i
.types
[this_operand
] |= BaseIndex
;
5612 /* Set the scale after setting the register (otherwise,
5613 i386_scale will complain) */
5614 i386_scale (cur_token
.str
);
5615 intel_match_token (T_CONST
);
5619 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5625 /* No scaling. If this is a memory operand, the register is either a
5626 base register (first occurrence) or an index register (second
5628 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5630 if (i
.base_reg
&& i
.index_reg
)
5632 as_bad (_("Too many register references in memory operand.\n"));
5636 if (i
.base_reg
== NULL
)
5641 i
.types
[this_operand
] |= BaseIndex
;
5644 /* Offset modifier. Add the register to the displacement string to be
5645 parsed as an immediate expression after we're done. */
5646 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5647 strcat (intel_parser
.disp
, reg
->reg_name
);
5649 /* It's neither base nor index nor offset. */
5652 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5653 i
.op
[this_operand
].regs
= reg
;
5657 /* Since registers are not part of the displacement string (except
5658 when we're parsing offset operands), we may need to remove any
5659 preceding '+' from the displacement string. */
5660 if (*intel_parser
.disp
!= '\0'
5661 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5663 char *s
= intel_parser
.disp
;
5664 s
+= strlen (s
) - 1;
5673 else if (cur_token
.code
== T_ID
)
5675 /* Add the identifier to the displacement string. */
5676 strcat (intel_parser
.disp
, cur_token
.str
);
5677 intel_match_token (T_ID
);
5679 /* The identifier represents a memory reference only if it's not
5680 preceded by an offset modifier. */
5681 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5682 intel_parser
.is_mem
= 1;
5688 else if (cur_token
.code
== T_CONST
5689 || cur_token
.code
== '-'
5690 || cur_token
.code
== '+')
5694 /* Allow constants that start with `+' or `-'. */
5695 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5697 strcat (intel_parser
.disp
, cur_token
.str
);
5698 intel_match_token (cur_token
.code
);
5699 if (cur_token
.code
!= T_CONST
)
5701 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5707 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5708 if (save_str
== NULL
)
5710 strcpy (save_str
, cur_token
.str
);
5712 /* Get the next token to check for register scaling. */
5713 intel_match_token (cur_token
.code
);
5715 /* Check if this constant is a scaling factor for an index register. */
5716 if (cur_token
.code
== '*')
5718 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5720 if (!intel_parser
.is_mem
)
5722 as_bad (_("Register scaling only allowed in memory operands."));
5726 /* The constant is followed by `* reg', so it must be
5728 if (strchr ("01248", *save_str
))
5730 i
.index_reg
= cur_token
.reg
;
5731 i
.types
[this_operand
] |= BaseIndex
;
5733 /* Set the scale after setting the register (otherwise,
5734 i386_scale will complain) */
5735 i386_scale (save_str
);
5736 intel_match_token (T_REG
);
5738 /* Since registers are not part of the displacement
5739 string, we may need to remove any preceding '+' from
5740 the displacement string. */
5741 if (*intel_parser
.disp
!= '\0')
5743 char *s
= intel_parser
.disp
;
5744 s
+= strlen (s
) - 1;
5757 /* The constant was not used for register scaling. Since we have
5758 already consumed the token following `*' we now need to put it
5759 back in the stream. */
5761 intel_putback_token ();
5764 /* Add the constant to the displacement string. */
5765 strcat (intel_parser
.disp
, save_str
);
5771 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5775 /* Match the given token against cur_token. If they match, read the next
5776 token from the operand string. */
5778 intel_match_token (code
)
5781 if (cur_token
.code
== code
)
5788 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5793 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5798 const reg_entry
*reg
;
5799 struct intel_token new_token
;
5801 new_token
.code
= T_NIL
;
5802 new_token
.reg
= NULL
;
5803 new_token
.str
= NULL
;
5805 /* Free the memory allocated to the previous token and move
5806 cur_token to prev_token. */
5808 free (prev_token
.str
);
5810 prev_token
= cur_token
;
5812 /* Skip whitespace. */
5813 while (is_space_char (*intel_parser
.op_string
))
5814 intel_parser
.op_string
++;
5816 /* Return an empty token if we find nothing else on the line. */
5817 if (*intel_parser
.op_string
== '\0')
5819 cur_token
= new_token
;
5823 /* The new token cannot be larger than the remainder of the operand
5825 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5826 if (new_token
.str
== NULL
)
5828 new_token
.str
[0] = '\0';
5830 if (strchr ("0123456789", *intel_parser
.op_string
))
5832 char *p
= new_token
.str
;
5833 char *q
= intel_parser
.op_string
;
5834 new_token
.code
= T_CONST
;
5836 /* Allow any kind of identifier char to encompass floating point and
5837 hexadecimal numbers. */
5838 while (is_identifier_char (*q
))
5842 /* Recognize special symbol names [0-9][bf]. */
5843 if (strlen (intel_parser
.op_string
) == 2
5844 && (intel_parser
.op_string
[1] == 'b'
5845 || intel_parser
.op_string
[1] == 'f'))
5846 new_token
.code
= T_ID
;
5849 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5851 new_token
.code
= *intel_parser
.op_string
;
5852 new_token
.str
[0] = *intel_parser
.op_string
;
5853 new_token
.str
[1] = '\0';
5856 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5857 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5859 new_token
.code
= T_REG
;
5860 new_token
.reg
= reg
;
5862 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5864 new_token
.str
[0] = REGISTER_PREFIX
;
5865 new_token
.str
[1] = '\0';
5868 strcat (new_token
.str
, reg
->reg_name
);
5871 else if (is_identifier_char (*intel_parser
.op_string
))
5873 char *p
= new_token
.str
;
5874 char *q
= intel_parser
.op_string
;
5876 /* A '.' or '$' followed by an identifier char is an identifier.
5877 Otherwise, it's operator '.' followed by an expression. */
5878 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5880 new_token
.code
= *q
;
5881 new_token
.str
[0] = *q
;
5882 new_token
.str
[1] = '\0';
5886 while (is_identifier_char (*q
) || *q
== '@')
5890 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5891 new_token
.code
= T_BYTE
;
5893 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5894 new_token
.code
= T_WORD
;
5896 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5897 new_token
.code
= T_DWORD
;
5899 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5900 new_token
.code
= T_QWORD
;
5902 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5903 new_token
.code
= T_XWORD
;
5905 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5906 new_token
.code
= T_PTR
;
5908 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5909 new_token
.code
= T_SHORT
;
5911 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5913 new_token
.code
= T_OFFSET
;
5915 /* ??? This is not mentioned in the MASM grammar but gcc
5916 makes use of it with -mintel-syntax. OFFSET may be
5917 followed by FLAT: */
5918 if (strncasecmp (q
, " FLAT:", 6) == 0)
5919 strcat (new_token
.str
, " FLAT:");
5922 /* ??? This is not mentioned in the MASM grammar. */
5923 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5924 new_token
.code
= T_OFFSET
;
5927 new_token
.code
= T_ID
;
5932 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5934 intel_parser
.op_string
+= strlen (new_token
.str
);
5935 cur_token
= new_token
;
5938 /* Put cur_token back into the token stream and make cur_token point to
5941 intel_putback_token ()
5943 intel_parser
.op_string
-= strlen (cur_token
.str
);
5944 free (cur_token
.str
);
5945 cur_token
= prev_token
;
5947 /* Forget prev_token. */
5948 prev_token
.code
= T_NIL
;
5949 prev_token
.reg
= NULL
;
5950 prev_token
.str
= NULL
;