1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
962 CPU_PCOMMIT_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512IFMA_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512VBMI_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
968 CPU_CLZERO_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
970 CPU_MWAITX_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
972 CPU_OSPKE_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
974 CPU_RDPID_FLAGS
, 0 },
977 static const noarch_entry cpu_noarch
[] =
979 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
980 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
981 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
982 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
983 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
984 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
985 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
986 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
987 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
988 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
989 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
990 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
991 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
992 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
993 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
994 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
995 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
996 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1005 /* Like s_lcomm_internal in gas/read.c but the alignment string
1006 is allowed to be optional. */
1009 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1016 && *input_line_pointer
== ',')
1018 align
= parse_align (needs_align
- 1);
1020 if (align
== (addressT
) -1)
1035 bss_alloc (symbolP
, size
, align
);
1040 pe_lcomm (int needs_align
)
1042 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1046 const pseudo_typeS md_pseudo_table
[] =
1048 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1049 {"align", s_align_bytes
, 0},
1051 {"align", s_align_ptwo
, 0},
1053 {"arch", set_cpu_arch
, 0},
1057 {"lcomm", pe_lcomm
, 1},
1059 {"ffloat", float_cons
, 'f'},
1060 {"dfloat", float_cons
, 'd'},
1061 {"tfloat", float_cons
, 'x'},
1063 {"slong", signed_cons
, 4},
1064 {"noopt", s_ignore
, 0},
1065 {"optim", s_ignore
, 0},
1066 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1067 {"code16", set_code_flag
, CODE_16BIT
},
1068 {"code32", set_code_flag
, CODE_32BIT
},
1069 {"code64", set_code_flag
, CODE_64BIT
},
1070 {"intel_syntax", set_intel_syntax
, 1},
1071 {"att_syntax", set_intel_syntax
, 0},
1072 {"intel_mnemonic", set_intel_mnemonic
, 1},
1073 {"att_mnemonic", set_intel_mnemonic
, 0},
1074 {"allow_index_reg", set_allow_index_reg
, 1},
1075 {"disallow_index_reg", set_allow_index_reg
, 0},
1076 {"sse_check", set_check
, 0},
1077 {"operand_check", set_check
, 1},
1078 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1079 {"largecomm", handle_large_common
, 0},
1081 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1082 {"loc", dwarf2_directive_loc
, 0},
1083 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1086 {"secrel32", pe_directive_secrel
, 0},
1091 /* For interface with expression (). */
1092 extern char *input_line_pointer
;
1094 /* Hash table for instruction mnemonic lookup. */
1095 static struct hash_control
*op_hash
;
1097 /* Hash table for register lookup. */
1098 static struct hash_control
*reg_hash
;
1101 i386_align_code (fragS
*fragP
, int count
)
1103 /* Various efficient no-op patterns for aligning code labels.
1104 Note: Don't try to assemble the instructions in the comments.
1105 0L and 0w are not legal. */
1106 static const unsigned char f32_1
[] =
1108 static const unsigned char f32_2
[] =
1109 {0x66,0x90}; /* xchg %ax,%ax */
1110 static const unsigned char f32_3
[] =
1111 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1112 static const unsigned char f32_4
[] =
1113 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1114 static const unsigned char f32_5
[] =
1116 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1117 static const unsigned char f32_6
[] =
1118 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1119 static const unsigned char f32_7
[] =
1120 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1121 static const unsigned char f32_8
[] =
1123 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1124 static const unsigned char f32_9
[] =
1125 {0x89,0xf6, /* movl %esi,%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1127 static const unsigned char f32_10
[] =
1128 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1130 static const unsigned char f32_11
[] =
1131 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1132 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1133 static const unsigned char f32_12
[] =
1134 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1135 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1136 static const unsigned char f32_13
[] =
1137 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1139 static const unsigned char f32_14
[] =
1140 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1141 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1142 static const unsigned char f16_3
[] =
1143 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1144 static const unsigned char f16_4
[] =
1145 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1146 static const unsigned char f16_5
[] =
1148 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1149 static const unsigned char f16_6
[] =
1150 {0x89,0xf6, /* mov %si,%si */
1151 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1152 static const unsigned char f16_7
[] =
1153 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1154 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1155 static const unsigned char f16_8
[] =
1156 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1157 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1158 static const unsigned char jump_31
[] =
1159 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1160 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1161 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1163 static const unsigned char *const f32_patt
[] = {
1164 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1165 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1167 static const unsigned char *const f16_patt
[] = {
1168 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1170 /* nopl (%[re]ax) */
1171 static const unsigned char alt_3
[] =
1173 /* nopl 0(%[re]ax) */
1174 static const unsigned char alt_4
[] =
1175 {0x0f,0x1f,0x40,0x00};
1176 /* nopl 0(%[re]ax,%[re]ax,1) */
1177 static const unsigned char alt_5
[] =
1178 {0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1) */
1180 static const unsigned char alt_6
[] =
1181 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopl 0L(%[re]ax) */
1183 static const unsigned char alt_7
[] =
1184 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1185 /* nopl 0L(%[re]ax,%[re]ax,1) */
1186 static const unsigned char alt_8
[] =
1187 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1188 /* nopw 0L(%[re]ax,%[re]ax,1) */
1189 static const unsigned char alt_9
[] =
1190 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1192 static const unsigned char alt_10
[] =
1193 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const unsigned char *const alt_patt
[] = {
1195 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1199 /* Only align for at least a positive non-zero boundary. */
1200 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1203 /* We need to decide which NOP sequence to use for 32bit and
1204 64bit. When -mtune= is used:
1206 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1207 PROCESSOR_GENERIC32, f32_patt will be used.
1208 2. For the rest, alt_patt will be used.
1210 When -mtune= isn't used, alt_patt will be used if
1211 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1214 When -march= or .arch is used, we can't use anything beyond
1215 cpu_arch_isa_flags. */
1217 if (flag_code
== CODE_16BIT
)
1221 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1223 /* Adjust jump offset. */
1224 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1227 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1228 f16_patt
[count
- 1], count
);
1232 const unsigned char *const *patt
= NULL
;
1234 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1236 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1237 switch (cpu_arch_tune
)
1239 case PROCESSOR_UNKNOWN
:
1240 /* We use cpu_arch_isa_flags to check if we SHOULD
1241 optimize with nops. */
1242 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1247 case PROCESSOR_PENTIUM4
:
1248 case PROCESSOR_NOCONA
:
1249 case PROCESSOR_CORE
:
1250 case PROCESSOR_CORE2
:
1251 case PROCESSOR_COREI7
:
1252 case PROCESSOR_L1OM
:
1253 case PROCESSOR_K1OM
:
1254 case PROCESSOR_GENERIC64
:
1256 case PROCESSOR_ATHLON
:
1258 case PROCESSOR_AMDFAM10
:
1260 case PROCESSOR_ZNVER
:
1264 case PROCESSOR_I386
:
1265 case PROCESSOR_I486
:
1266 case PROCESSOR_PENTIUM
:
1267 case PROCESSOR_PENTIUMPRO
:
1268 case PROCESSOR_IAMCU
:
1269 case PROCESSOR_GENERIC32
:
1276 switch (fragP
->tc_frag_data
.tune
)
1278 case PROCESSOR_UNKNOWN
:
1279 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1280 PROCESSOR_UNKNOWN. */
1284 case PROCESSOR_I386
:
1285 case PROCESSOR_I486
:
1286 case PROCESSOR_PENTIUM
:
1287 case PROCESSOR_IAMCU
:
1289 case PROCESSOR_ATHLON
:
1291 case PROCESSOR_AMDFAM10
:
1293 case PROCESSOR_ZNVER
:
1295 case PROCESSOR_GENERIC32
:
1296 /* We use cpu_arch_isa_flags to check if we CAN optimize
1298 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1303 case PROCESSOR_PENTIUMPRO
:
1304 case PROCESSOR_PENTIUM4
:
1305 case PROCESSOR_NOCONA
:
1306 case PROCESSOR_CORE
:
1307 case PROCESSOR_CORE2
:
1308 case PROCESSOR_COREI7
:
1309 case PROCESSOR_L1OM
:
1310 case PROCESSOR_K1OM
:
1311 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1316 case PROCESSOR_GENERIC64
:
1322 if (patt
== f32_patt
)
1324 /* If the padding is less than 15 bytes, we use the normal
1325 ones. Otherwise, we use a jump instruction and adjust
1329 /* For 64bit, the limit is 3 bytes. */
1330 if (flag_code
== CODE_64BIT
1331 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1337 patt
[count
- 1], count
);
1340 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1342 /* Adjust jump offset. */
1343 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1348 /* Maximum length of an instruction is 10 byte. If the
1349 padding is greater than 10 bytes and we don't use jump,
1350 we have to break it into smaller pieces. */
1351 int padding
= count
;
1352 while (padding
> 10)
1355 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1360 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1361 patt
[padding
- 1], padding
);
1364 fragP
->fr_var
= count
;
1368 operand_type_all_zero (const union i386_operand_type
*x
)
1370 switch (ARRAY_SIZE(x
->array
))
1379 return !x
->array
[0];
1386 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1388 switch (ARRAY_SIZE(x
->array
))
1403 operand_type_equal (const union i386_operand_type
*x
,
1404 const union i386_operand_type
*y
)
1406 switch (ARRAY_SIZE(x
->array
))
1409 if (x
->array
[2] != y
->array
[2])
1412 if (x
->array
[1] != y
->array
[1])
1415 return x
->array
[0] == y
->array
[0];
1423 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1425 switch (ARRAY_SIZE(x
->array
))
1434 return !x
->array
[0];
1441 cpu_flags_equal (const union i386_cpu_flags
*x
,
1442 const union i386_cpu_flags
*y
)
1444 switch (ARRAY_SIZE(x
->array
))
1447 if (x
->array
[2] != y
->array
[2])
1450 if (x
->array
[1] != y
->array
[1])
1453 return x
->array
[0] == y
->array
[0];
1461 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1463 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1464 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1467 static INLINE i386_cpu_flags
1468 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1470 switch (ARRAY_SIZE (x
.array
))
1473 x
.array
[2] &= y
.array
[2];
1475 x
.array
[1] &= y
.array
[1];
1477 x
.array
[0] &= y
.array
[0];
1485 static INLINE i386_cpu_flags
1486 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1488 switch (ARRAY_SIZE (x
.array
))
1491 x
.array
[2] |= y
.array
[2];
1493 x
.array
[1] |= y
.array
[1];
1495 x
.array
[0] |= y
.array
[0];
1503 static INLINE i386_cpu_flags
1504 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1506 switch (ARRAY_SIZE (x
.array
))
1509 x
.array
[2] &= ~y
.array
[2];
1511 x
.array
[1] &= ~y
.array
[1];
1513 x
.array
[0] &= ~y
.array
[0];
1522 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1524 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1526 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1527 i386_cpu_flags compat_flags
;
1528 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1529 return cpu_flags_all_zero (&compat_flags
);
1535 #define CPU_FLAGS_ARCH_MATCH 0x1
1536 #define CPU_FLAGS_64BIT_MATCH 0x2
1537 #define CPU_FLAGS_AES_MATCH 0x4
1538 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1539 #define CPU_FLAGS_AVX_MATCH 0x10
1541 #define CPU_FLAGS_32BIT_MATCH \
1542 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1543 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1544 #define CPU_FLAGS_PERFECT_MATCH \
1545 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1547 /* Return CPU flags match bits. */
1550 cpu_flags_match (const insn_template
*t
)
1552 i386_cpu_flags x
= t
->cpu_flags
;
1553 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1555 x
.bitfield
.cpu64
= 0;
1556 x
.bitfield
.cpuno64
= 0;
1558 if (cpu_flags_all_zero (&x
))
1560 /* This instruction is available on all archs. */
1561 match
|= CPU_FLAGS_32BIT_MATCH
;
1565 /* This instruction is available only on some archs. */
1566 i386_cpu_flags cpu
= cpu_arch_flags
;
1568 cpu
= cpu_flags_and (x
, cpu
);
1569 if (!cpu_flags_all_zero (&cpu
))
1571 if (x
.bitfield
.cpuavx
)
1573 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1574 if (cpu
.bitfield
.cpuavx
)
1576 /* Check SSE2AVX. */
1577 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1579 match
|= (CPU_FLAGS_ARCH_MATCH
1580 | CPU_FLAGS_AVX_MATCH
);
1582 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1583 match
|= CPU_FLAGS_AES_MATCH
;
1585 if (!x
.bitfield
.cpupclmul
1586 || cpu
.bitfield
.cpupclmul
)
1587 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1591 match
|= CPU_FLAGS_ARCH_MATCH
;
1593 else if (x
.bitfield
.cpuavx512vl
)
1595 /* Match AVX512VL. */
1596 if (cpu
.bitfield
.cpuavx512vl
)
1598 /* Need another match. */
1599 cpu
.bitfield
.cpuavx512vl
= 0;
1600 if (!cpu_flags_all_zero (&cpu
))
1601 match
|= CPU_FLAGS_32BIT_MATCH
;
1603 match
|= CPU_FLAGS_ARCH_MATCH
;
1606 match
|= CPU_FLAGS_ARCH_MATCH
;
1609 match
|= CPU_FLAGS_32BIT_MATCH
;
1615 static INLINE i386_operand_type
1616 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1618 switch (ARRAY_SIZE (x
.array
))
1621 x
.array
[2] &= y
.array
[2];
1623 x
.array
[1] &= y
.array
[1];
1625 x
.array
[0] &= y
.array
[0];
1633 static INLINE i386_operand_type
1634 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1636 switch (ARRAY_SIZE (x
.array
))
1639 x
.array
[2] |= y
.array
[2];
1641 x
.array
[1] |= y
.array
[1];
1643 x
.array
[0] |= y
.array
[0];
1651 static INLINE i386_operand_type
1652 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1654 switch (ARRAY_SIZE (x
.array
))
1657 x
.array
[2] ^= y
.array
[2];
1659 x
.array
[1] ^= y
.array
[1];
1661 x
.array
[0] ^= y
.array
[0];
1669 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1670 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1671 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1672 static const i386_operand_type inoutportreg
1673 = OPERAND_TYPE_INOUTPORTREG
;
1674 static const i386_operand_type reg16_inoutportreg
1675 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1676 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1677 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1678 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1679 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1680 static const i386_operand_type anydisp
1681 = OPERAND_TYPE_ANYDISP
;
1682 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1683 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1684 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1685 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1686 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1687 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1688 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1689 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1690 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1691 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1692 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1693 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1694 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1695 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1706 operand_type_check (i386_operand_type t
, enum operand_type c
)
1711 return (t
.bitfield
.reg8
1714 || t
.bitfield
.reg64
);
1717 return (t
.bitfield
.imm8
1721 || t
.bitfield
.imm32s
1722 || t
.bitfield
.imm64
);
1725 return (t
.bitfield
.disp8
1726 || t
.bitfield
.disp16
1727 || t
.bitfield
.disp32
1728 || t
.bitfield
.disp32s
1729 || t
.bitfield
.disp64
);
1732 return (t
.bitfield
.disp8
1733 || t
.bitfield
.disp16
1734 || t
.bitfield
.disp32
1735 || t
.bitfield
.disp32s
1736 || t
.bitfield
.disp64
1737 || t
.bitfield
.baseindex
);
1746 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1747 operand J for instruction template T. */
1750 match_reg_size (const insn_template
*t
, unsigned int j
)
1752 return !((i
.types
[j
].bitfield
.byte
1753 && !t
->operand_types
[j
].bitfield
.byte
)
1754 || (i
.types
[j
].bitfield
.word
1755 && !t
->operand_types
[j
].bitfield
.word
)
1756 || (i
.types
[j
].bitfield
.dword
1757 && !t
->operand_types
[j
].bitfield
.dword
)
1758 || (i
.types
[j
].bitfield
.qword
1759 && !t
->operand_types
[j
].bitfield
.qword
));
1762 /* Return 1 if there is no conflict in any size on operand J for
1763 instruction template T. */
1766 match_mem_size (const insn_template
*t
, unsigned int j
)
1768 return (match_reg_size (t
, j
)
1769 && !((i
.types
[j
].bitfield
.unspecified
1771 && !t
->operand_types
[j
].bitfield
.unspecified
)
1772 || (i
.types
[j
].bitfield
.fword
1773 && !t
->operand_types
[j
].bitfield
.fword
)
1774 || (i
.types
[j
].bitfield
.tbyte
1775 && !t
->operand_types
[j
].bitfield
.tbyte
)
1776 || (i
.types
[j
].bitfield
.xmmword
1777 && !t
->operand_types
[j
].bitfield
.xmmword
)
1778 || (i
.types
[j
].bitfield
.ymmword
1779 && !t
->operand_types
[j
].bitfield
.ymmword
)
1780 || (i
.types
[j
].bitfield
.zmmword
1781 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1784 /* Return 1 if there is no size conflict on any operands for
1785 instruction template T. */
1788 operand_size_match (const insn_template
*t
)
1793 /* Don't check jump instructions. */
1794 if (t
->opcode_modifier
.jump
1795 || t
->opcode_modifier
.jumpbyte
1796 || t
->opcode_modifier
.jumpdword
1797 || t
->opcode_modifier
.jumpintersegment
)
1800 /* Check memory and accumulator operand size. */
1801 for (j
= 0; j
< i
.operands
; j
++)
1803 if (t
->operand_types
[j
].bitfield
.anysize
)
1806 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1812 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1821 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1824 i
.error
= operand_size_mismatch
;
1828 /* Check reverse. */
1829 gas_assert (i
.operands
== 2);
1832 for (j
= 0; j
< 2; j
++)
1834 if (t
->operand_types
[j
].bitfield
.acc
1835 && !match_reg_size (t
, j
? 0 : 1))
1838 if (i
.types
[j
].bitfield
.mem
1839 && !match_mem_size (t
, j
? 0 : 1))
1847 operand_type_match (i386_operand_type overlap
,
1848 i386_operand_type given
)
1850 i386_operand_type temp
= overlap
;
1852 temp
.bitfield
.jumpabsolute
= 0;
1853 temp
.bitfield
.unspecified
= 0;
1854 temp
.bitfield
.byte
= 0;
1855 temp
.bitfield
.word
= 0;
1856 temp
.bitfield
.dword
= 0;
1857 temp
.bitfield
.fword
= 0;
1858 temp
.bitfield
.qword
= 0;
1859 temp
.bitfield
.tbyte
= 0;
1860 temp
.bitfield
.xmmword
= 0;
1861 temp
.bitfield
.ymmword
= 0;
1862 temp
.bitfield
.zmmword
= 0;
1863 if (operand_type_all_zero (&temp
))
1866 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1867 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1871 i
.error
= operand_type_mismatch
;
1875 /* If given types g0 and g1 are registers they must be of the same type
1876 unless the expected operand type register overlap is null.
1877 Note that Acc in a template matches every size of reg. */
1880 operand_type_register_match (i386_operand_type m0
,
1881 i386_operand_type g0
,
1882 i386_operand_type t0
,
1883 i386_operand_type m1
,
1884 i386_operand_type g1
,
1885 i386_operand_type t1
)
1887 if (!operand_type_check (g0
, reg
))
1890 if (!operand_type_check (g1
, reg
))
1893 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1894 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1895 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1896 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1899 if (m0
.bitfield
.acc
)
1901 t0
.bitfield
.reg8
= 1;
1902 t0
.bitfield
.reg16
= 1;
1903 t0
.bitfield
.reg32
= 1;
1904 t0
.bitfield
.reg64
= 1;
1907 if (m1
.bitfield
.acc
)
1909 t1
.bitfield
.reg8
= 1;
1910 t1
.bitfield
.reg16
= 1;
1911 t1
.bitfield
.reg32
= 1;
1912 t1
.bitfield
.reg64
= 1;
1915 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1916 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1917 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1918 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1921 i
.error
= register_type_mismatch
;
1926 static INLINE
unsigned int
1927 register_number (const reg_entry
*r
)
1929 unsigned int nr
= r
->reg_num
;
1931 if (r
->reg_flags
& RegRex
)
1934 if (r
->reg_flags
& RegVRex
)
1940 static INLINE
unsigned int
1941 mode_from_disp_size (i386_operand_type t
)
1943 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1945 else if (t
.bitfield
.disp16
1946 || t
.bitfield
.disp32
1947 || t
.bitfield
.disp32s
)
1954 fits_in_signed_byte (addressT num
)
1956 return num
+ 0x80 <= 0xff;
1960 fits_in_unsigned_byte (addressT num
)
1966 fits_in_unsigned_word (addressT num
)
1968 return num
<= 0xffff;
1972 fits_in_signed_word (addressT num
)
1974 return num
+ 0x8000 <= 0xffff;
1978 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1983 return num
+ 0x80000000 <= 0xffffffff;
1985 } /* fits_in_signed_long() */
1988 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1993 return num
<= 0xffffffff;
1995 } /* fits_in_unsigned_long() */
1998 fits_in_vec_disp8 (offsetT num
)
2000 int shift
= i
.memshift
;
2006 mask
= (1 << shift
) - 1;
2008 /* Return 0 if NUM isn't properly aligned. */
2012 /* Check if NUM will fit in 8bit after shift. */
2013 return fits_in_signed_byte (num
>> shift
);
2017 fits_in_imm4 (offsetT num
)
2019 return (num
& 0xf) == num
;
2022 static i386_operand_type
2023 smallest_imm_type (offsetT num
)
2025 i386_operand_type t
;
2027 operand_type_set (&t
, 0);
2028 t
.bitfield
.imm64
= 1;
2030 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2032 /* This code is disabled on the 486 because all the Imm1 forms
2033 in the opcode table are slower on the i486. They're the
2034 versions with the implicitly specified single-position
2035 displacement, which has another syntax if you really want to
2037 t
.bitfield
.imm1
= 1;
2038 t
.bitfield
.imm8
= 1;
2039 t
.bitfield
.imm8s
= 1;
2040 t
.bitfield
.imm16
= 1;
2041 t
.bitfield
.imm32
= 1;
2042 t
.bitfield
.imm32s
= 1;
2044 else if (fits_in_signed_byte (num
))
2046 t
.bitfield
.imm8
= 1;
2047 t
.bitfield
.imm8s
= 1;
2048 t
.bitfield
.imm16
= 1;
2049 t
.bitfield
.imm32
= 1;
2050 t
.bitfield
.imm32s
= 1;
2052 else if (fits_in_unsigned_byte (num
))
2054 t
.bitfield
.imm8
= 1;
2055 t
.bitfield
.imm16
= 1;
2056 t
.bitfield
.imm32
= 1;
2057 t
.bitfield
.imm32s
= 1;
2059 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2061 t
.bitfield
.imm16
= 1;
2062 t
.bitfield
.imm32
= 1;
2063 t
.bitfield
.imm32s
= 1;
2065 else if (fits_in_signed_long (num
))
2067 t
.bitfield
.imm32
= 1;
2068 t
.bitfield
.imm32s
= 1;
2070 else if (fits_in_unsigned_long (num
))
2071 t
.bitfield
.imm32
= 1;
2077 offset_in_range (offsetT val
, int size
)
2083 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2084 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2085 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2087 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2093 /* If BFD64, sign extend val for 32bit address mode. */
2094 if (flag_code
!= CODE_64BIT
2095 || i
.prefix
[ADDR_PREFIX
])
2096 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2097 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2100 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2102 char buf1
[40], buf2
[40];
2104 sprint_value (buf1
, val
);
2105 sprint_value (buf2
, val
& mask
);
2106 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2120 a. PREFIX_EXIST if attempting to add a prefix where one from the
2121 same class already exists.
2122 b. PREFIX_LOCK if lock prefix is added.
2123 c. PREFIX_REP if rep/repne prefix is added.
2124 d. PREFIX_OTHER if other prefix is added.
2127 static enum PREFIX_GROUP
2128 add_prefix (unsigned int prefix
)
2130 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2133 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2134 && flag_code
== CODE_64BIT
)
2136 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2137 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2138 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2149 case CS_PREFIX_OPCODE
:
2150 case DS_PREFIX_OPCODE
:
2151 case ES_PREFIX_OPCODE
:
2152 case FS_PREFIX_OPCODE
:
2153 case GS_PREFIX_OPCODE
:
2154 case SS_PREFIX_OPCODE
:
2158 case REPNE_PREFIX_OPCODE
:
2159 case REPE_PREFIX_OPCODE
:
2164 case LOCK_PREFIX_OPCODE
:
2173 case ADDR_PREFIX_OPCODE
:
2177 case DATA_PREFIX_OPCODE
:
2181 if (i
.prefix
[q
] != 0)
2189 i
.prefix
[q
] |= prefix
;
2192 as_bad (_("same type of prefix used twice"));
2198 update_code_flag (int value
, int check
)
2200 PRINTF_LIKE ((*as_error
));
2202 flag_code
= (enum flag_code
) value
;
2203 if (flag_code
== CODE_64BIT
)
2205 cpu_arch_flags
.bitfield
.cpu64
= 1;
2206 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2210 cpu_arch_flags
.bitfield
.cpu64
= 0;
2211 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2213 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2216 as_error
= as_fatal
;
2219 (*as_error
) (_("64bit mode not supported on `%s'."),
2220 cpu_arch_name
? cpu_arch_name
: default_arch
);
2222 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2225 as_error
= as_fatal
;
2228 (*as_error
) (_("32bit mode not supported on `%s'."),
2229 cpu_arch_name
? cpu_arch_name
: default_arch
);
2231 stackop_size
= '\0';
2235 set_code_flag (int value
)
2237 update_code_flag (value
, 0);
2241 set_16bit_gcc_code_flag (int new_code_flag
)
2243 flag_code
= (enum flag_code
) new_code_flag
;
2244 if (flag_code
!= CODE_16BIT
)
2246 cpu_arch_flags
.bitfield
.cpu64
= 0;
2247 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2248 stackop_size
= LONG_MNEM_SUFFIX
;
2252 set_intel_syntax (int syntax_flag
)
2254 /* Find out if register prefixing is specified. */
2255 int ask_naked_reg
= 0;
2258 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2261 int e
= get_symbol_name (&string
);
2263 if (strcmp (string
, "prefix") == 0)
2265 else if (strcmp (string
, "noprefix") == 0)
2268 as_bad (_("bad argument to syntax directive."));
2269 (void) restore_line_pointer (e
);
2271 demand_empty_rest_of_line ();
2273 intel_syntax
= syntax_flag
;
2275 if (ask_naked_reg
== 0)
2276 allow_naked_reg
= (intel_syntax
2277 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2279 allow_naked_reg
= (ask_naked_reg
< 0);
2281 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2283 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2284 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2285 register_prefix
= allow_naked_reg
? "" : "%";
2289 set_intel_mnemonic (int mnemonic_flag
)
2291 intel_mnemonic
= mnemonic_flag
;
2295 set_allow_index_reg (int flag
)
2297 allow_index_reg
= flag
;
2301 set_check (int what
)
2303 enum check_kind
*kind
;
2308 kind
= &operand_check
;
2319 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2322 int e
= get_symbol_name (&string
);
2324 if (strcmp (string
, "none") == 0)
2326 else if (strcmp (string
, "warning") == 0)
2327 *kind
= check_warning
;
2328 else if (strcmp (string
, "error") == 0)
2329 *kind
= check_error
;
2331 as_bad (_("bad argument to %s_check directive."), str
);
2332 (void) restore_line_pointer (e
);
2335 as_bad (_("missing argument for %s_check directive"), str
);
2337 demand_empty_rest_of_line ();
2341 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2342 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2344 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2345 static const char *arch
;
2347 /* Intel LIOM is only supported on ELF. */
2353 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2354 use default_arch. */
2355 arch
= cpu_arch_name
;
2357 arch
= default_arch
;
2360 /* If we are targeting Intel MCU, we must enable it. */
2361 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2362 || new_flag
.bitfield
.cpuiamcu
)
2365 /* If we are targeting Intel L1OM, we must enable it. */
2366 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2367 || new_flag
.bitfield
.cpul1om
)
2370 /* If we are targeting Intel K1OM, we must enable it. */
2371 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2372 || new_flag
.bitfield
.cpuk1om
)
2375 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2380 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2384 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2387 int e
= get_symbol_name (&string
);
2389 i386_cpu_flags flags
;
2391 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2393 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2395 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2399 cpu_arch_name
= cpu_arch
[j
].name
;
2400 cpu_sub_arch_name
= NULL
;
2401 cpu_arch_flags
= cpu_arch
[j
].flags
;
2402 if (flag_code
== CODE_64BIT
)
2404 cpu_arch_flags
.bitfield
.cpu64
= 1;
2405 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2409 cpu_arch_flags
.bitfield
.cpu64
= 0;
2410 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2412 cpu_arch_isa
= cpu_arch
[j
].type
;
2413 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2414 if (!cpu_arch_tune_set
)
2416 cpu_arch_tune
= cpu_arch_isa
;
2417 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2422 flags
= cpu_flags_or (cpu_arch_flags
,
2425 if (!valid_iamcu_cpu_flags (&flags
))
2426 as_fatal (_("`%s' isn't valid for Intel MCU"),
2428 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2430 if (cpu_sub_arch_name
)
2432 char *name
= cpu_sub_arch_name
;
2433 cpu_sub_arch_name
= concat (name
,
2435 (const char *) NULL
);
2439 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2440 cpu_arch_flags
= flags
;
2441 cpu_arch_isa_flags
= flags
;
2443 (void) restore_line_pointer (e
);
2444 demand_empty_rest_of_line ();
2449 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2451 /* Disable an ISA entension. */
2452 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2453 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2455 flags
= cpu_flags_and_not (cpu_arch_flags
,
2456 cpu_noarch
[j
].flags
);
2457 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2459 if (cpu_sub_arch_name
)
2461 char *name
= cpu_sub_arch_name
;
2462 cpu_sub_arch_name
= concat (name
, string
,
2463 (const char *) NULL
);
2467 cpu_sub_arch_name
= xstrdup (string
);
2468 cpu_arch_flags
= flags
;
2469 cpu_arch_isa_flags
= flags
;
2471 (void) restore_line_pointer (e
);
2472 demand_empty_rest_of_line ();
2476 j
= ARRAY_SIZE (cpu_arch
);
2479 if (j
>= ARRAY_SIZE (cpu_arch
))
2480 as_bad (_("no such architecture: `%s'"), string
);
2482 *input_line_pointer
= e
;
2485 as_bad (_("missing cpu architecture"));
2487 no_cond_jump_promotion
= 0;
2488 if (*input_line_pointer
== ','
2489 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2494 ++input_line_pointer
;
2495 e
= get_symbol_name (&string
);
2497 if (strcmp (string
, "nojumps") == 0)
2498 no_cond_jump_promotion
= 1;
2499 else if (strcmp (string
, "jumps") == 0)
2502 as_bad (_("no such architecture modifier: `%s'"), string
);
2504 (void) restore_line_pointer (e
);
2507 demand_empty_rest_of_line ();
2510 enum bfd_architecture
2513 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2515 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2516 || flag_code
!= CODE_64BIT
)
2517 as_fatal (_("Intel L1OM is 64bit ELF only"));
2518 return bfd_arch_l1om
;
2520 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2522 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2523 || flag_code
!= CODE_64BIT
)
2524 as_fatal (_("Intel K1OM is 64bit ELF only"));
2525 return bfd_arch_k1om
;
2527 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2529 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2530 || flag_code
== CODE_64BIT
)
2531 as_fatal (_("Intel MCU is 32bit ELF only"));
2532 return bfd_arch_iamcu
;
2535 return bfd_arch_i386
;
2541 if (!strncmp (default_arch
, "x86_64", 6))
2543 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2545 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2546 || default_arch
[6] != '\0')
2547 as_fatal (_("Intel L1OM is 64bit ELF only"));
2548 return bfd_mach_l1om
;
2550 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2552 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2553 || default_arch
[6] != '\0')
2554 as_fatal (_("Intel K1OM is 64bit ELF only"));
2555 return bfd_mach_k1om
;
2557 else if (default_arch
[6] == '\0')
2558 return bfd_mach_x86_64
;
2560 return bfd_mach_x64_32
;
2562 else if (!strcmp (default_arch
, "i386")
2563 || !strcmp (default_arch
, "iamcu"))
2565 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2567 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2568 as_fatal (_("Intel MCU is 32bit ELF only"));
2569 return bfd_mach_i386_iamcu
;
2572 return bfd_mach_i386_i386
;
2575 as_fatal (_("unknown architecture"));
2581 const char *hash_err
;
2583 /* Initialize op_hash hash table. */
2584 op_hash
= hash_new ();
2587 const insn_template
*optab
;
2588 templates
*core_optab
;
2590 /* Setup for loop. */
2592 core_optab
= XNEW (templates
);
2593 core_optab
->start
= optab
;
2598 if (optab
->name
== NULL
2599 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2601 /* different name --> ship out current template list;
2602 add to hash table; & begin anew. */
2603 core_optab
->end
= optab
;
2604 hash_err
= hash_insert (op_hash
,
2606 (void *) core_optab
);
2609 as_fatal (_("can't hash %s: %s"),
2613 if (optab
->name
== NULL
)
2615 core_optab
= XNEW (templates
);
2616 core_optab
->start
= optab
;
2621 /* Initialize reg_hash hash table. */
2622 reg_hash
= hash_new ();
2624 const reg_entry
*regtab
;
2625 unsigned int regtab_size
= i386_regtab_size
;
2627 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2629 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2631 as_fatal (_("can't hash %s: %s"),
2637 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2642 for (c
= 0; c
< 256; c
++)
2647 mnemonic_chars
[c
] = c
;
2648 register_chars
[c
] = c
;
2649 operand_chars
[c
] = c
;
2651 else if (ISLOWER (c
))
2653 mnemonic_chars
[c
] = c
;
2654 register_chars
[c
] = c
;
2655 operand_chars
[c
] = c
;
2657 else if (ISUPPER (c
))
2659 mnemonic_chars
[c
] = TOLOWER (c
);
2660 register_chars
[c
] = mnemonic_chars
[c
];
2661 operand_chars
[c
] = c
;
2663 else if (c
== '{' || c
== '}')
2664 operand_chars
[c
] = c
;
2666 if (ISALPHA (c
) || ISDIGIT (c
))
2667 identifier_chars
[c
] = c
;
2670 identifier_chars
[c
] = c
;
2671 operand_chars
[c
] = c
;
2676 identifier_chars
['@'] = '@';
2679 identifier_chars
['?'] = '?';
2680 operand_chars
['?'] = '?';
2682 digit_chars
['-'] = '-';
2683 mnemonic_chars
['_'] = '_';
2684 mnemonic_chars
['-'] = '-';
2685 mnemonic_chars
['.'] = '.';
2686 identifier_chars
['_'] = '_';
2687 identifier_chars
['.'] = '.';
2689 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2690 operand_chars
[(unsigned char) *p
] = *p
;
2693 if (flag_code
== CODE_64BIT
)
2695 #if defined (OBJ_COFF) && defined (TE_PE)
2696 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2699 x86_dwarf2_return_column
= 16;
2701 x86_cie_data_alignment
= -8;
2705 x86_dwarf2_return_column
= 8;
2706 x86_cie_data_alignment
= -4;
2711 i386_print_statistics (FILE *file
)
2713 hash_print_statistics (file
, "i386 opcode", op_hash
);
2714 hash_print_statistics (file
, "i386 register", reg_hash
);
2719 /* Debugging routines for md_assemble. */
2720 static void pte (insn_template
*);
2721 static void pt (i386_operand_type
);
2722 static void pe (expressionS
*);
2723 static void ps (symbolS
*);
2726 pi (char *line
, i386_insn
*x
)
2730 fprintf (stdout
, "%s: template ", line
);
2732 fprintf (stdout
, " address: base %s index %s scale %x\n",
2733 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2734 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2735 x
->log2_scale_factor
);
2736 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2737 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2738 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2739 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2740 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2741 (x
->rex
& REX_W
) != 0,
2742 (x
->rex
& REX_R
) != 0,
2743 (x
->rex
& REX_X
) != 0,
2744 (x
->rex
& REX_B
) != 0);
2745 for (j
= 0; j
< x
->operands
; j
++)
2747 fprintf (stdout
, " #%d: ", j
+ 1);
2749 fprintf (stdout
, "\n");
2750 if (x
->types
[j
].bitfield
.reg8
2751 || x
->types
[j
].bitfield
.reg16
2752 || x
->types
[j
].bitfield
.reg32
2753 || x
->types
[j
].bitfield
.reg64
2754 || x
->types
[j
].bitfield
.regmmx
2755 || x
->types
[j
].bitfield
.regxmm
2756 || x
->types
[j
].bitfield
.regymm
2757 || x
->types
[j
].bitfield
.regzmm
2758 || x
->types
[j
].bitfield
.sreg2
2759 || x
->types
[j
].bitfield
.sreg3
2760 || x
->types
[j
].bitfield
.control
2761 || x
->types
[j
].bitfield
.debug
2762 || x
->types
[j
].bitfield
.test
)
2763 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2764 if (operand_type_check (x
->types
[j
], imm
))
2766 if (operand_type_check (x
->types
[j
], disp
))
2767 pe (x
->op
[j
].disps
);
2772 pte (insn_template
*t
)
2775 fprintf (stdout
, " %d operands ", t
->operands
);
2776 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2777 if (t
->extension_opcode
!= None
)
2778 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2779 if (t
->opcode_modifier
.d
)
2780 fprintf (stdout
, "D");
2781 if (t
->opcode_modifier
.w
)
2782 fprintf (stdout
, "W");
2783 fprintf (stdout
, "\n");
2784 for (j
= 0; j
< t
->operands
; j
++)
2786 fprintf (stdout
, " #%d type ", j
+ 1);
2787 pt (t
->operand_types
[j
]);
2788 fprintf (stdout
, "\n");
2795 fprintf (stdout
, " operation %d\n", e
->X_op
);
2796 fprintf (stdout
, " add_number %ld (%lx)\n",
2797 (long) e
->X_add_number
, (long) e
->X_add_number
);
2798 if (e
->X_add_symbol
)
2800 fprintf (stdout
, " add_symbol ");
2801 ps (e
->X_add_symbol
);
2802 fprintf (stdout
, "\n");
2806 fprintf (stdout
, " op_symbol ");
2807 ps (e
->X_op_symbol
);
2808 fprintf (stdout
, "\n");
2815 fprintf (stdout
, "%s type %s%s",
2817 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2818 segment_name (S_GET_SEGMENT (s
)));
2821 static struct type_name
2823 i386_operand_type mask
;
2826 const type_names
[] =
2828 { OPERAND_TYPE_REG8
, "r8" },
2829 { OPERAND_TYPE_REG16
, "r16" },
2830 { OPERAND_TYPE_REG32
, "r32" },
2831 { OPERAND_TYPE_REG64
, "r64" },
2832 { OPERAND_TYPE_IMM8
, "i8" },
2833 { OPERAND_TYPE_IMM8
, "i8s" },
2834 { OPERAND_TYPE_IMM16
, "i16" },
2835 { OPERAND_TYPE_IMM32
, "i32" },
2836 { OPERAND_TYPE_IMM32S
, "i32s" },
2837 { OPERAND_TYPE_IMM64
, "i64" },
2838 { OPERAND_TYPE_IMM1
, "i1" },
2839 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2840 { OPERAND_TYPE_DISP8
, "d8" },
2841 { OPERAND_TYPE_DISP16
, "d16" },
2842 { OPERAND_TYPE_DISP32
, "d32" },
2843 { OPERAND_TYPE_DISP32S
, "d32s" },
2844 { OPERAND_TYPE_DISP64
, "d64" },
2845 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2846 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2847 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2848 { OPERAND_TYPE_CONTROL
, "control reg" },
2849 { OPERAND_TYPE_TEST
, "test reg" },
2850 { OPERAND_TYPE_DEBUG
, "debug reg" },
2851 { OPERAND_TYPE_FLOATREG
, "FReg" },
2852 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2853 { OPERAND_TYPE_SREG2
, "SReg2" },
2854 { OPERAND_TYPE_SREG3
, "SReg3" },
2855 { OPERAND_TYPE_ACC
, "Acc" },
2856 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2857 { OPERAND_TYPE_REGMMX
, "rMMX" },
2858 { OPERAND_TYPE_REGXMM
, "rXMM" },
2859 { OPERAND_TYPE_REGYMM
, "rYMM" },
2860 { OPERAND_TYPE_REGZMM
, "rZMM" },
2861 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2862 { OPERAND_TYPE_ESSEG
, "es" },
2866 pt (i386_operand_type t
)
2869 i386_operand_type a
;
2871 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2873 a
= operand_type_and (t
, type_names
[j
].mask
);
2874 if (!operand_type_all_zero (&a
))
2875 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2880 #endif /* DEBUG386 */
2882 static bfd_reloc_code_real_type
2883 reloc (unsigned int size
,
2886 bfd_reloc_code_real_type other
)
2888 if (other
!= NO_RELOC
)
2890 reloc_howto_type
*rel
;
2895 case BFD_RELOC_X86_64_GOT32
:
2896 return BFD_RELOC_X86_64_GOT64
;
2898 case BFD_RELOC_X86_64_GOTPLT64
:
2899 return BFD_RELOC_X86_64_GOTPLT64
;
2901 case BFD_RELOC_X86_64_PLTOFF64
:
2902 return BFD_RELOC_X86_64_PLTOFF64
;
2904 case BFD_RELOC_X86_64_GOTPC32
:
2905 other
= BFD_RELOC_X86_64_GOTPC64
;
2907 case BFD_RELOC_X86_64_GOTPCREL
:
2908 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2910 case BFD_RELOC_X86_64_TPOFF32
:
2911 other
= BFD_RELOC_X86_64_TPOFF64
;
2913 case BFD_RELOC_X86_64_DTPOFF32
:
2914 other
= BFD_RELOC_X86_64_DTPOFF64
;
2920 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2921 if (other
== BFD_RELOC_SIZE32
)
2924 other
= BFD_RELOC_SIZE64
;
2927 as_bad (_("there are no pc-relative size relocations"));
2933 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2934 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2937 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2939 as_bad (_("unknown relocation (%u)"), other
);
2940 else if (size
!= bfd_get_reloc_size (rel
))
2941 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2942 bfd_get_reloc_size (rel
),
2944 else if (pcrel
&& !rel
->pc_relative
)
2945 as_bad (_("non-pc-relative relocation for pc-relative field"));
2946 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2948 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2950 as_bad (_("relocated field and relocation type differ in signedness"));
2959 as_bad (_("there are no unsigned pc-relative relocations"));
2962 case 1: return BFD_RELOC_8_PCREL
;
2963 case 2: return BFD_RELOC_16_PCREL
;
2964 case 4: return BFD_RELOC_32_PCREL
;
2965 case 8: return BFD_RELOC_64_PCREL
;
2967 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2974 case 4: return BFD_RELOC_X86_64_32S
;
2979 case 1: return BFD_RELOC_8
;
2980 case 2: return BFD_RELOC_16
;
2981 case 4: return BFD_RELOC_32
;
2982 case 8: return BFD_RELOC_64
;
2984 as_bad (_("cannot do %s %u byte relocation"),
2985 sign
> 0 ? "signed" : "unsigned", size
);
2991 /* Here we decide which fixups can be adjusted to make them relative to
2992 the beginning of the section instead of the symbol. Basically we need
2993 to make sure that the dynamic relocations are done correctly, so in
2994 some cases we force the original symbol to be used. */
2997 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3003 /* Don't adjust pc-relative references to merge sections in 64-bit
3005 if (use_rela_relocations
3006 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3010 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3011 and changed later by validate_fix. */
3012 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3013 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3016 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3017 for size relocations. */
3018 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3019 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3020 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3021 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3022 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3023 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3024 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3025 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3026 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3027 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3028 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3029 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3030 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3031 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3032 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3034 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3035 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3036 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3037 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3038 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3039 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3040 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3041 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3049 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3050 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3057 intel_float_operand (const char *mnemonic
)
3059 /* Note that the value returned is meaningful only for opcodes with (memory)
3060 operands, hence the code here is free to improperly handle opcodes that
3061 have no operands (for better performance and smaller code). */
3063 if (mnemonic
[0] != 'f')
3064 return 0; /* non-math */
3066 switch (mnemonic
[1])
3068 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3069 the fs segment override prefix not currently handled because no
3070 call path can make opcodes without operands get here */
3072 return 2 /* integer op */;
3074 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3075 return 3; /* fldcw/fldenv */
3078 if (mnemonic
[2] != 'o' /* fnop */)
3079 return 3; /* non-waiting control op */
3082 if (mnemonic
[2] == 's')
3083 return 3; /* frstor/frstpm */
3086 if (mnemonic
[2] == 'a')
3087 return 3; /* fsave */
3088 if (mnemonic
[2] == 't')
3090 switch (mnemonic
[3])
3092 case 'c': /* fstcw */
3093 case 'd': /* fstdw */
3094 case 'e': /* fstenv */
3095 case 's': /* fsts[gw] */
3101 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3102 return 0; /* fxsave/fxrstor are not really math ops */
3109 /* Build the VEX prefix. */
3112 build_vex_prefix (const insn_template
*t
)
3114 unsigned int register_specifier
;
3115 unsigned int implied_prefix
;
3116 unsigned int vector_length
;
3118 /* Check register specifier. */
3119 if (i
.vex
.register_specifier
)
3121 register_specifier
=
3122 ~register_number (i
.vex
.register_specifier
) & 0xf;
3123 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3126 register_specifier
= 0xf;
3128 /* Use 2-byte VEX prefix by swappping destination and source
3131 && i
.operands
== i
.reg_operands
3132 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3133 && i
.tm
.opcode_modifier
.s
3136 unsigned int xchg
= i
.operands
- 1;
3137 union i386_op temp_op
;
3138 i386_operand_type temp_type
;
3140 temp_type
= i
.types
[xchg
];
3141 i
.types
[xchg
] = i
.types
[0];
3142 i
.types
[0] = temp_type
;
3143 temp_op
= i
.op
[xchg
];
3144 i
.op
[xchg
] = i
.op
[0];
3147 gas_assert (i
.rm
.mode
== 3);
3151 i
.rm
.regmem
= i
.rm
.reg
;
3154 /* Use the next insn. */
3158 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3159 vector_length
= avxscalar
;
3161 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3163 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3168 case DATA_PREFIX_OPCODE
:
3171 case REPE_PREFIX_OPCODE
:
3174 case REPNE_PREFIX_OPCODE
:
3181 /* Use 2-byte VEX prefix if possible. */
3182 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3183 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3184 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3186 /* 2-byte VEX prefix. */
3190 i
.vex
.bytes
[0] = 0xc5;
3192 /* Check the REX.R bit. */
3193 r
= (i
.rex
& REX_R
) ? 0 : 1;
3194 i
.vex
.bytes
[1] = (r
<< 7
3195 | register_specifier
<< 3
3196 | vector_length
<< 2
3201 /* 3-byte VEX prefix. */
3206 switch (i
.tm
.opcode_modifier
.vexopcode
)
3210 i
.vex
.bytes
[0] = 0xc4;
3214 i
.vex
.bytes
[0] = 0xc4;
3218 i
.vex
.bytes
[0] = 0xc4;
3222 i
.vex
.bytes
[0] = 0x8f;
3226 i
.vex
.bytes
[0] = 0x8f;
3230 i
.vex
.bytes
[0] = 0x8f;
3236 /* The high 3 bits of the second VEX byte are 1's compliment
3237 of RXB bits from REX. */
3238 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3240 /* Check the REX.W bit. */
3241 w
= (i
.rex
& REX_W
) ? 1 : 0;
3242 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3245 i
.vex
.bytes
[2] = (w
<< 7
3246 | register_specifier
<< 3
3247 | vector_length
<< 2
3252 /* Build the EVEX prefix. */
3255 build_evex_prefix (void)
3257 unsigned int register_specifier
;
3258 unsigned int implied_prefix
;
3260 rex_byte vrex_used
= 0;
3262 /* Check register specifier. */
3263 if (i
.vex
.register_specifier
)
3265 gas_assert ((i
.vrex
& REX_X
) == 0);
3267 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3268 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3269 register_specifier
+= 8;
3270 /* The upper 16 registers are encoded in the fourth byte of the
3272 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3273 i
.vex
.bytes
[3] = 0x8;
3274 register_specifier
= ~register_specifier
& 0xf;
3278 register_specifier
= 0xf;
3280 /* Encode upper 16 vector index register in the fourth byte of
3282 if (!(i
.vrex
& REX_X
))
3283 i
.vex
.bytes
[3] = 0x8;
3288 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3293 case DATA_PREFIX_OPCODE
:
3296 case REPE_PREFIX_OPCODE
:
3299 case REPNE_PREFIX_OPCODE
:
3306 /* 4 byte EVEX prefix. */
3308 i
.vex
.bytes
[0] = 0x62;
3311 switch (i
.tm
.opcode_modifier
.vexopcode
)
3327 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3329 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3331 /* The fifth bit of the second EVEX byte is 1's compliment of the
3332 REX_R bit in VREX. */
3333 if (!(i
.vrex
& REX_R
))
3334 i
.vex
.bytes
[1] |= 0x10;
3338 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3340 /* When all operands are registers, the REX_X bit in REX is not
3341 used. We reuse it to encode the upper 16 registers, which is
3342 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3343 as 1's compliment. */
3344 if ((i
.vrex
& REX_B
))
3347 i
.vex
.bytes
[1] &= ~0x40;
3351 /* EVEX instructions shouldn't need the REX prefix. */
3352 i
.vrex
&= ~vrex_used
;
3353 gas_assert (i
.vrex
== 0);
3355 /* Check the REX.W bit. */
3356 w
= (i
.rex
& REX_W
) ? 1 : 0;
3357 if (i
.tm
.opcode_modifier
.vexw
)
3359 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3362 /* If w is not set it means we are dealing with WIG instruction. */
3365 if (evexwig
== evexw1
)
3369 /* Encode the U bit. */
3370 implied_prefix
|= 0x4;
3372 /* The third byte of the EVEX prefix. */
3373 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3375 /* The fourth byte of the EVEX prefix. */
3376 /* The zeroing-masking bit. */
3377 if (i
.mask
&& i
.mask
->zeroing
)
3378 i
.vex
.bytes
[3] |= 0x80;
3380 /* Don't always set the broadcast bit if there is no RC. */
3383 /* Encode the vector length. */
3384 unsigned int vec_length
;
3386 switch (i
.tm
.opcode_modifier
.evex
)
3388 case EVEXLIG
: /* LL' is ignored */
3389 vec_length
= evexlig
<< 5;
3392 vec_length
= 0 << 5;
3395 vec_length
= 1 << 5;
3398 vec_length
= 2 << 5;
3404 i
.vex
.bytes
[3] |= vec_length
;
3405 /* Encode the broadcast bit. */
3407 i
.vex
.bytes
[3] |= 0x10;
3411 if (i
.rounding
->type
!= saeonly
)
3412 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3414 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3417 if (i
.mask
&& i
.mask
->mask
)
3418 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3422 process_immext (void)
3426 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3429 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3430 with an opcode suffix which is coded in the same place as an
3431 8-bit immediate field would be.
3432 Here we check those operands and remove them afterwards. */
3435 for (x
= 0; x
< i
.operands
; x
++)
3436 if (register_number (i
.op
[x
].regs
) != x
)
3437 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3438 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3444 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3446 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3447 suffix which is coded in the same place as an 8-bit immediate
3449 Here we check those operands and remove them afterwards. */
3452 if (i
.operands
!= 3)
3455 for (x
= 0; x
< 2; x
++)
3456 if (register_number (i
.op
[x
].regs
) != x
)
3457 goto bad_register_operand
;
3459 /* Check for third operand for mwaitx/monitorx insn. */
3460 if (register_number (i
.op
[x
].regs
)
3461 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3463 bad_register_operand
:
3464 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3465 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3472 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3473 which is coded in the same place as an 8-bit immediate field
3474 would be. Here we fake an 8-bit immediate operand from the
3475 opcode suffix stored in tm.extension_opcode.
3477 AVX instructions also use this encoding, for some of
3478 3 argument instructions. */
3480 gas_assert (i
.imm_operands
<= 1
3482 || ((i
.tm
.opcode_modifier
.vex
3483 || i
.tm
.opcode_modifier
.evex
)
3484 && i
.operands
<= 4)));
3486 exp
= &im_expressions
[i
.imm_operands
++];
3487 i
.op
[i
.operands
].imms
= exp
;
3488 i
.types
[i
.operands
] = imm8
;
3490 exp
->X_op
= O_constant
;
3491 exp
->X_add_number
= i
.tm
.extension_opcode
;
3492 i
.tm
.extension_opcode
= None
;
3499 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3504 as_bad (_("invalid instruction `%s' after `%s'"),
3505 i
.tm
.name
, i
.hle_prefix
);
3508 if (i
.prefix
[LOCK_PREFIX
])
3510 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3514 case HLEPrefixRelease
:
3515 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3517 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3521 if (i
.mem_operands
== 0
3522 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3524 as_bad (_("memory destination needed for instruction `%s'"
3525 " after `xrelease'"), i
.tm
.name
);
3532 /* This is the guts of the machine-dependent assembler. LINE points to a
3533 machine dependent instruction. This function is supposed to emit
3534 the frags/bytes it assembles to. */
3537 md_assemble (char *line
)
3540 char mnemonic
[MAX_MNEM_SIZE
];
3541 const insn_template
*t
;
3543 /* Initialize globals. */
3544 memset (&i
, '\0', sizeof (i
));
3545 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3546 i
.reloc
[j
] = NO_RELOC
;
3547 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3548 memset (im_expressions
, '\0', sizeof (im_expressions
));
3549 save_stack_p
= save_stack
;
3551 /* First parse an instruction mnemonic & call i386_operand for the operands.
3552 We assume that the scrubber has arranged it so that line[0] is the valid
3553 start of a (possibly prefixed) mnemonic. */
3555 line
= parse_insn (line
, mnemonic
);
3559 line
= parse_operands (line
, mnemonic
);
3561 xfree (i
.memop1_string
);
3562 i
.memop1_string
= NULL
;
3566 /* Now we've parsed the mnemonic into a set of templates, and have the
3567 operands at hand. */
3569 /* All intel opcodes have reversed operands except for "bound" and
3570 "enter". We also don't reverse intersegment "jmp" and "call"
3571 instructions with 2 immediate operands so that the immediate segment
3572 precedes the offset, as it does when in AT&T mode. */
3575 && (strcmp (mnemonic
, "bound") != 0)
3576 && (strcmp (mnemonic
, "invlpga") != 0)
3577 && !(operand_type_check (i
.types
[0], imm
)
3578 && operand_type_check (i
.types
[1], imm
)))
3581 /* The order of the immediates should be reversed
3582 for 2 immediates extrq and insertq instructions */
3583 if (i
.imm_operands
== 2
3584 && (strcmp (mnemonic
, "extrq") == 0
3585 || strcmp (mnemonic
, "insertq") == 0))
3586 swap_2_operands (0, 1);
3591 /* Don't optimize displacement for movabs since it only takes 64bit
3594 && i
.disp_encoding
!= disp_encoding_32bit
3595 && (flag_code
!= CODE_64BIT
3596 || strcmp (mnemonic
, "movabs") != 0))
3599 /* Next, we find a template that matches the given insn,
3600 making sure the overlap of the given operands types is consistent
3601 with the template operand types. */
3603 if (!(t
= match_template ()))
3606 if (sse_check
!= check_none
3607 && !i
.tm
.opcode_modifier
.noavx
3608 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3609 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3610 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3611 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3612 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3613 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3615 (sse_check
== check_warning
3617 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3620 /* Zap movzx and movsx suffix. The suffix has been set from
3621 "word ptr" or "byte ptr" on the source operand in Intel syntax
3622 or extracted from mnemonic in AT&T syntax. But we'll use
3623 the destination register to choose the suffix for encoding. */
3624 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3626 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3627 there is no suffix, the default will be byte extension. */
3628 if (i
.reg_operands
!= 2
3631 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3636 if (i
.tm
.opcode_modifier
.fwait
)
3637 if (!add_prefix (FWAIT_OPCODE
))
3640 /* Check if REP prefix is OK. */
3641 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3643 as_bad (_("invalid instruction `%s' after `%s'"),
3644 i
.tm
.name
, i
.rep_prefix
);
3648 /* Check for lock without a lockable instruction. Destination operand
3649 must be memory unless it is xchg (0x86). */
3650 if (i
.prefix
[LOCK_PREFIX
]
3651 && (!i
.tm
.opcode_modifier
.islockable
3652 || i
.mem_operands
== 0
3653 || (i
.tm
.base_opcode
!= 0x86
3654 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3656 as_bad (_("expecting lockable instruction after `lock'"));
3660 /* Check if HLE prefix is OK. */
3661 if (i
.hle_prefix
&& !check_hle ())
3664 /* Check BND prefix. */
3665 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3666 as_bad (_("expecting valid branch instruction after `bnd'"));
3668 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3669 && flag_code
== CODE_64BIT
3670 && i
.prefix
[ADDR_PREFIX
])
3671 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3673 /* Insert BND prefix. */
3675 && i
.tm
.opcode_modifier
.bndprefixok
3676 && !i
.prefix
[BND_PREFIX
])
3677 add_prefix (BND_PREFIX_OPCODE
);
3679 /* Check string instruction segment overrides. */
3680 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3682 if (!check_string ())
3684 i
.disp_operands
= 0;
3687 if (!process_suffix ())
3690 /* Update operand types. */
3691 for (j
= 0; j
< i
.operands
; j
++)
3692 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3694 /* Make still unresolved immediate matches conform to size of immediate
3695 given in i.suffix. */
3696 if (!finalize_imm ())
3699 if (i
.types
[0].bitfield
.imm1
)
3700 i
.imm_operands
= 0; /* kludge for shift insns. */
3702 /* We only need to check those implicit registers for instructions
3703 with 3 operands or less. */
3704 if (i
.operands
<= 3)
3705 for (j
= 0; j
< i
.operands
; j
++)
3706 if (i
.types
[j
].bitfield
.inoutportreg
3707 || i
.types
[j
].bitfield
.shiftcount
3708 || i
.types
[j
].bitfield
.acc
3709 || i
.types
[j
].bitfield
.floatacc
)
3712 /* ImmExt should be processed after SSE2AVX. */
3713 if (!i
.tm
.opcode_modifier
.sse2avx
3714 && i
.tm
.opcode_modifier
.immext
)
3717 /* For insns with operands there are more diddles to do to the opcode. */
3720 if (!process_operands ())
3723 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3725 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3726 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3729 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3731 if (flag_code
== CODE_16BIT
)
3733 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3738 if (i
.tm
.opcode_modifier
.vex
)
3739 build_vex_prefix (t
);
3741 build_evex_prefix ();
3744 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3745 instructions may define INT_OPCODE as well, so avoid this corner
3746 case for those instructions that use MODRM. */
3747 if (i
.tm
.base_opcode
== INT_OPCODE
3748 && !i
.tm
.opcode_modifier
.modrm
3749 && i
.op
[0].imms
->X_add_number
== 3)
3751 i
.tm
.base_opcode
= INT3_OPCODE
;
3755 if ((i
.tm
.opcode_modifier
.jump
3756 || i
.tm
.opcode_modifier
.jumpbyte
3757 || i
.tm
.opcode_modifier
.jumpdword
)
3758 && i
.op
[0].disps
->X_op
== O_constant
)
3760 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3761 the absolute address given by the constant. Since ix86 jumps and
3762 calls are pc relative, we need to generate a reloc. */
3763 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3764 i
.op
[0].disps
->X_op
= O_symbol
;
3767 if (i
.tm
.opcode_modifier
.rex64
)
3770 /* For 8 bit registers we need an empty rex prefix. Also if the
3771 instruction already has a prefix, we need to convert old
3772 registers to new ones. */
3774 if ((i
.types
[0].bitfield
.reg8
3775 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3776 || (i
.types
[1].bitfield
.reg8
3777 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3778 || ((i
.types
[0].bitfield
.reg8
3779 || i
.types
[1].bitfield
.reg8
)
3784 i
.rex
|= REX_OPCODE
;
3785 for (x
= 0; x
< 2; x
++)
3787 /* Look for 8 bit operand that uses old registers. */
3788 if (i
.types
[x
].bitfield
.reg8
3789 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3791 /* In case it is "hi" register, give up. */
3792 if (i
.op
[x
].regs
->reg_num
> 3)
3793 as_bad (_("can't encode register '%s%s' in an "
3794 "instruction requiring REX prefix."),
3795 register_prefix
, i
.op
[x
].regs
->reg_name
);
3797 /* Otherwise it is equivalent to the extended register.
3798 Since the encoding doesn't change this is merely
3799 cosmetic cleanup for debug output. */
3801 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3807 add_prefix (REX_OPCODE
| i
.rex
);
3809 /* We are ready to output the insn. */
3814 parse_insn (char *line
, char *mnemonic
)
3817 char *token_start
= l
;
3820 const insn_template
*t
;
3826 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3831 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3833 as_bad (_("no such instruction: `%s'"), token_start
);
3838 if (!is_space_char (*l
)
3839 && *l
!= END_OF_INSN
3841 || (*l
!= PREFIX_SEPARATOR
3844 as_bad (_("invalid character %s in mnemonic"),
3845 output_invalid (*l
));
3848 if (token_start
== l
)
3850 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3851 as_bad (_("expecting prefix; got nothing"));
3853 as_bad (_("expecting mnemonic; got nothing"));
3857 /* Look up instruction (or prefix) via hash table. */
3858 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3860 if (*l
!= END_OF_INSN
3861 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3862 && current_templates
3863 && current_templates
->start
->opcode_modifier
.isprefix
)
3865 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3867 as_bad ((flag_code
!= CODE_64BIT
3868 ? _("`%s' is only supported in 64-bit mode")
3869 : _("`%s' is not supported in 64-bit mode")),
3870 current_templates
->start
->name
);
3873 /* If we are in 16-bit mode, do not allow addr16 or data16.
3874 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3875 if ((current_templates
->start
->opcode_modifier
.size16
3876 || current_templates
->start
->opcode_modifier
.size32
)
3877 && flag_code
!= CODE_64BIT
3878 && (current_templates
->start
->opcode_modifier
.size32
3879 ^ (flag_code
== CODE_16BIT
)))
3881 as_bad (_("redundant %s prefix"),
3882 current_templates
->start
->name
);
3885 /* Add prefix, checking for repeated prefixes. */
3886 switch (add_prefix (current_templates
->start
->base_opcode
))
3891 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3892 i
.hle_prefix
= current_templates
->start
->name
;
3893 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3894 i
.bnd_prefix
= current_templates
->start
->name
;
3896 i
.rep_prefix
= current_templates
->start
->name
;
3901 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3908 if (!current_templates
)
3910 /* Check if we should swap operand or force 32bit displacement in
3912 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3914 else if (mnem_p
- 3 == dot_p
3917 i
.disp_encoding
= disp_encoding_8bit
;
3918 else if (mnem_p
- 4 == dot_p
3922 i
.disp_encoding
= disp_encoding_32bit
;
3927 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3930 if (!current_templates
)
3933 /* See if we can get a match by trimming off a suffix. */
3936 case WORD_MNEM_SUFFIX
:
3937 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3938 i
.suffix
= SHORT_MNEM_SUFFIX
;
3940 case BYTE_MNEM_SUFFIX
:
3941 case QWORD_MNEM_SUFFIX
:
3942 i
.suffix
= mnem_p
[-1];
3944 current_templates
= (const templates
*) hash_find (op_hash
,
3947 case SHORT_MNEM_SUFFIX
:
3948 case LONG_MNEM_SUFFIX
:
3951 i
.suffix
= mnem_p
[-1];
3953 current_templates
= (const templates
*) hash_find (op_hash
,
3962 if (intel_float_operand (mnemonic
) == 1)
3963 i
.suffix
= SHORT_MNEM_SUFFIX
;
3965 i
.suffix
= LONG_MNEM_SUFFIX
;
3967 current_templates
= (const templates
*) hash_find (op_hash
,
3972 if (!current_templates
)
3974 as_bad (_("no such instruction: `%s'"), token_start
);
3979 if (current_templates
->start
->opcode_modifier
.jump
3980 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3982 /* Check for a branch hint. We allow ",pt" and ",pn" for
3983 predict taken and predict not taken respectively.
3984 I'm not sure that branch hints actually do anything on loop
3985 and jcxz insns (JumpByte) for current Pentium4 chips. They
3986 may work in the future and it doesn't hurt to accept them
3988 if (l
[0] == ',' && l
[1] == 'p')
3992 if (!add_prefix (DS_PREFIX_OPCODE
))
3996 else if (l
[2] == 'n')
3998 if (!add_prefix (CS_PREFIX_OPCODE
))
4004 /* Any other comma loses. */
4007 as_bad (_("invalid character %s in mnemonic"),
4008 output_invalid (*l
));
4012 /* Check if instruction is supported on specified architecture. */
4014 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4016 supported
|= cpu_flags_match (t
);
4017 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4021 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4023 as_bad (flag_code
== CODE_64BIT
4024 ? _("`%s' is not supported in 64-bit mode")
4025 : _("`%s' is only supported in 64-bit mode"),
4026 current_templates
->start
->name
);
4029 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4031 as_bad (_("`%s' is not supported on `%s%s'"),
4032 current_templates
->start
->name
,
4033 cpu_arch_name
? cpu_arch_name
: default_arch
,
4034 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4039 if (!cpu_arch_flags
.bitfield
.cpui386
4040 && (flag_code
!= CODE_16BIT
))
4042 as_warn (_("use .code16 to ensure correct addressing mode"));
4049 parse_operands (char *l
, const char *mnemonic
)
4053 /* 1 if operand is pending after ','. */
4054 unsigned int expecting_operand
= 0;
4056 /* Non-zero if operand parens not balanced. */
4057 unsigned int paren_not_balanced
;
4059 while (*l
!= END_OF_INSN
)
4061 /* Skip optional white space before operand. */
4062 if (is_space_char (*l
))
4064 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4066 as_bad (_("invalid character %s before operand %d"),
4067 output_invalid (*l
),
4071 token_start
= l
; /* After white space. */
4072 paren_not_balanced
= 0;
4073 while (paren_not_balanced
|| *l
!= ',')
4075 if (*l
== END_OF_INSN
)
4077 if (paren_not_balanced
)
4080 as_bad (_("unbalanced parenthesis in operand %d."),
4083 as_bad (_("unbalanced brackets in operand %d."),
4088 break; /* we are done */
4090 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4092 as_bad (_("invalid character %s in operand %d"),
4093 output_invalid (*l
),
4100 ++paren_not_balanced
;
4102 --paren_not_balanced
;
4107 ++paren_not_balanced
;
4109 --paren_not_balanced
;
4113 if (l
!= token_start
)
4114 { /* Yes, we've read in another operand. */
4115 unsigned int operand_ok
;
4116 this_operand
= i
.operands
++;
4117 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4118 if (i
.operands
> MAX_OPERANDS
)
4120 as_bad (_("spurious operands; (%d operands/instruction max)"),
4124 /* Now parse operand adding info to 'i' as we go along. */
4125 END_STRING_AND_SAVE (l
);
4129 i386_intel_operand (token_start
,
4130 intel_float_operand (mnemonic
));
4132 operand_ok
= i386_att_operand (token_start
);
4134 RESTORE_END_STRING (l
);
4140 if (expecting_operand
)
4142 expecting_operand_after_comma
:
4143 as_bad (_("expecting operand after ','; got nothing"));
4148 as_bad (_("expecting operand before ','; got nothing"));
4153 /* Now *l must be either ',' or END_OF_INSN. */
4156 if (*++l
== END_OF_INSN
)
4158 /* Just skip it, if it's \n complain. */
4159 goto expecting_operand_after_comma
;
4161 expecting_operand
= 1;
4168 swap_2_operands (int xchg1
, int xchg2
)
4170 union i386_op temp_op
;
4171 i386_operand_type temp_type
;
4172 enum bfd_reloc_code_real temp_reloc
;
4174 temp_type
= i
.types
[xchg2
];
4175 i
.types
[xchg2
] = i
.types
[xchg1
];
4176 i
.types
[xchg1
] = temp_type
;
4177 temp_op
= i
.op
[xchg2
];
4178 i
.op
[xchg2
] = i
.op
[xchg1
];
4179 i
.op
[xchg1
] = temp_op
;
4180 temp_reloc
= i
.reloc
[xchg2
];
4181 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4182 i
.reloc
[xchg1
] = temp_reloc
;
4186 if (i
.mask
->operand
== xchg1
)
4187 i
.mask
->operand
= xchg2
;
4188 else if (i
.mask
->operand
== xchg2
)
4189 i
.mask
->operand
= xchg1
;
4193 if (i
.broadcast
->operand
== xchg1
)
4194 i
.broadcast
->operand
= xchg2
;
4195 else if (i
.broadcast
->operand
== xchg2
)
4196 i
.broadcast
->operand
= xchg1
;
4200 if (i
.rounding
->operand
== xchg1
)
4201 i
.rounding
->operand
= xchg2
;
4202 else if (i
.rounding
->operand
== xchg2
)
4203 i
.rounding
->operand
= xchg1
;
4208 swap_operands (void)
4214 swap_2_operands (1, i
.operands
- 2);
4217 swap_2_operands (0, i
.operands
- 1);
4223 if (i
.mem_operands
== 2)
4225 const seg_entry
*temp_seg
;
4226 temp_seg
= i
.seg
[0];
4227 i
.seg
[0] = i
.seg
[1];
4228 i
.seg
[1] = temp_seg
;
4232 /* Try to ensure constant immediates are represented in the smallest
4237 char guess_suffix
= 0;
4241 guess_suffix
= i
.suffix
;
4242 else if (i
.reg_operands
)
4244 /* Figure out a suffix from the last register operand specified.
4245 We can't do this properly yet, ie. excluding InOutPortReg,
4246 but the following works for instructions with immediates.
4247 In any case, we can't set i.suffix yet. */
4248 for (op
= i
.operands
; --op
>= 0;)
4249 if (i
.types
[op
].bitfield
.reg8
)
4251 guess_suffix
= BYTE_MNEM_SUFFIX
;
4254 else if (i
.types
[op
].bitfield
.reg16
)
4256 guess_suffix
= WORD_MNEM_SUFFIX
;
4259 else if (i
.types
[op
].bitfield
.reg32
)
4261 guess_suffix
= LONG_MNEM_SUFFIX
;
4264 else if (i
.types
[op
].bitfield
.reg64
)
4266 guess_suffix
= QWORD_MNEM_SUFFIX
;
4270 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4271 guess_suffix
= WORD_MNEM_SUFFIX
;
4273 for (op
= i
.operands
; --op
>= 0;)
4274 if (operand_type_check (i
.types
[op
], imm
))
4276 switch (i
.op
[op
].imms
->X_op
)
4279 /* If a suffix is given, this operand may be shortened. */
4280 switch (guess_suffix
)
4282 case LONG_MNEM_SUFFIX
:
4283 i
.types
[op
].bitfield
.imm32
= 1;
4284 i
.types
[op
].bitfield
.imm64
= 1;
4286 case WORD_MNEM_SUFFIX
:
4287 i
.types
[op
].bitfield
.imm16
= 1;
4288 i
.types
[op
].bitfield
.imm32
= 1;
4289 i
.types
[op
].bitfield
.imm32s
= 1;
4290 i
.types
[op
].bitfield
.imm64
= 1;
4292 case BYTE_MNEM_SUFFIX
:
4293 i
.types
[op
].bitfield
.imm8
= 1;
4294 i
.types
[op
].bitfield
.imm8s
= 1;
4295 i
.types
[op
].bitfield
.imm16
= 1;
4296 i
.types
[op
].bitfield
.imm32
= 1;
4297 i
.types
[op
].bitfield
.imm32s
= 1;
4298 i
.types
[op
].bitfield
.imm64
= 1;
4302 /* If this operand is at most 16 bits, convert it
4303 to a signed 16 bit number before trying to see
4304 whether it will fit in an even smaller size.
4305 This allows a 16-bit operand such as $0xffe0 to
4306 be recognised as within Imm8S range. */
4307 if ((i
.types
[op
].bitfield
.imm16
)
4308 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4310 i
.op
[op
].imms
->X_add_number
=
4311 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4314 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4315 if ((i
.types
[op
].bitfield
.imm32
)
4316 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4319 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4320 ^ ((offsetT
) 1 << 31))
4321 - ((offsetT
) 1 << 31));
4325 = operand_type_or (i
.types
[op
],
4326 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4328 /* We must avoid matching of Imm32 templates when 64bit
4329 only immediate is available. */
4330 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4331 i
.types
[op
].bitfield
.imm32
= 0;
4338 /* Symbols and expressions. */
4340 /* Convert symbolic operand to proper sizes for matching, but don't
4341 prevent matching a set of insns that only supports sizes other
4342 than those matching the insn suffix. */
4344 i386_operand_type mask
, allowed
;
4345 const insn_template
*t
;
4347 operand_type_set (&mask
, 0);
4348 operand_type_set (&allowed
, 0);
4350 for (t
= current_templates
->start
;
4351 t
< current_templates
->end
;
4353 allowed
= operand_type_or (allowed
,
4354 t
->operand_types
[op
]);
4355 switch (guess_suffix
)
4357 case QWORD_MNEM_SUFFIX
:
4358 mask
.bitfield
.imm64
= 1;
4359 mask
.bitfield
.imm32s
= 1;
4361 case LONG_MNEM_SUFFIX
:
4362 mask
.bitfield
.imm32
= 1;
4364 case WORD_MNEM_SUFFIX
:
4365 mask
.bitfield
.imm16
= 1;
4367 case BYTE_MNEM_SUFFIX
:
4368 mask
.bitfield
.imm8
= 1;
4373 allowed
= operand_type_and (mask
, allowed
);
4374 if (!operand_type_all_zero (&allowed
))
4375 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4382 /* Try to use the smallest displacement type too. */
4384 optimize_disp (void)
4388 for (op
= i
.operands
; --op
>= 0;)
4389 if (operand_type_check (i
.types
[op
], disp
))
4391 if (i
.op
[op
].disps
->X_op
== O_constant
)
4393 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4395 if (i
.types
[op
].bitfield
.disp16
4396 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4398 /* If this operand is at most 16 bits, convert
4399 to a signed 16 bit number and don't use 64bit
4401 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4402 i
.types
[op
].bitfield
.disp64
= 0;
4405 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4406 if (i
.types
[op
].bitfield
.disp32
4407 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4409 /* If this operand is at most 32 bits, convert
4410 to a signed 32 bit number and don't use 64bit
4412 op_disp
&= (((offsetT
) 2 << 31) - 1);
4413 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4414 i
.types
[op
].bitfield
.disp64
= 0;
4417 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4419 i
.types
[op
].bitfield
.disp8
= 0;
4420 i
.types
[op
].bitfield
.disp16
= 0;
4421 i
.types
[op
].bitfield
.disp32
= 0;
4422 i
.types
[op
].bitfield
.disp32s
= 0;
4423 i
.types
[op
].bitfield
.disp64
= 0;
4427 else if (flag_code
== CODE_64BIT
)
4429 if (fits_in_signed_long (op_disp
))
4431 i
.types
[op
].bitfield
.disp64
= 0;
4432 i
.types
[op
].bitfield
.disp32s
= 1;
4434 if (i
.prefix
[ADDR_PREFIX
]
4435 && fits_in_unsigned_long (op_disp
))
4436 i
.types
[op
].bitfield
.disp32
= 1;
4438 if ((i
.types
[op
].bitfield
.disp32
4439 || i
.types
[op
].bitfield
.disp32s
4440 || i
.types
[op
].bitfield
.disp16
)
4441 && fits_in_signed_byte (op_disp
))
4442 i
.types
[op
].bitfield
.disp8
= 1;
4444 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4445 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4447 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4448 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4449 i
.types
[op
].bitfield
.disp8
= 0;
4450 i
.types
[op
].bitfield
.disp16
= 0;
4451 i
.types
[op
].bitfield
.disp32
= 0;
4452 i
.types
[op
].bitfield
.disp32s
= 0;
4453 i
.types
[op
].bitfield
.disp64
= 0;
4456 /* We only support 64bit displacement on constants. */
4457 i
.types
[op
].bitfield
.disp64
= 0;
4461 /* Check if operands are valid for the instruction. */
4464 check_VecOperands (const insn_template
*t
)
4468 /* Without VSIB byte, we can't have a vector register for index. */
4469 if (!t
->opcode_modifier
.vecsib
4471 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4472 || i
.index_reg
->reg_type
.bitfield
.regymm
4473 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4475 i
.error
= unsupported_vector_index_register
;
4479 /* Check if default mask is allowed. */
4480 if (t
->opcode_modifier
.nodefmask
4481 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4483 i
.error
= no_default_mask
;
4487 /* For VSIB byte, we need a vector register for index, and all vector
4488 registers must be distinct. */
4489 if (t
->opcode_modifier
.vecsib
)
4492 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4493 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4494 || (t
->opcode_modifier
.vecsib
== VecSIB256
4495 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4496 || (t
->opcode_modifier
.vecsib
== VecSIB512
4497 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4499 i
.error
= invalid_vsib_address
;
4503 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4504 if (i
.reg_operands
== 2 && !i
.mask
)
4506 gas_assert (i
.types
[0].bitfield
.regxmm
4507 || i
.types
[0].bitfield
.regymm
);
4508 gas_assert (i
.types
[2].bitfield
.regxmm
4509 || i
.types
[2].bitfield
.regymm
);
4510 if (operand_check
== check_none
)
4512 if (register_number (i
.op
[0].regs
)
4513 != register_number (i
.index_reg
)
4514 && register_number (i
.op
[2].regs
)
4515 != register_number (i
.index_reg
)
4516 && register_number (i
.op
[0].regs
)
4517 != register_number (i
.op
[2].regs
))
4519 if (operand_check
== check_error
)
4521 i
.error
= invalid_vector_register_set
;
4524 as_warn (_("mask, index, and destination registers should be distinct"));
4526 else if (i
.reg_operands
== 1 && i
.mask
)
4528 if ((i
.types
[1].bitfield
.regymm
4529 || i
.types
[1].bitfield
.regzmm
)
4530 && (register_number (i
.op
[1].regs
)
4531 == register_number (i
.index_reg
)))
4533 if (operand_check
== check_error
)
4535 i
.error
= invalid_vector_register_set
;
4538 if (operand_check
!= check_none
)
4539 as_warn (_("index and destination registers should be distinct"));
4544 /* Check if broadcast is supported by the instruction and is applied
4545 to the memory operand. */
4548 int broadcasted_opnd_size
;
4550 /* Check if specified broadcast is supported in this instruction,
4551 and it's applied to memory operand of DWORD or QWORD type,
4552 depending on VecESize. */
4553 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4554 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4555 || (t
->opcode_modifier
.vecesize
== 0
4556 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4557 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4558 || (t
->opcode_modifier
.vecesize
== 1
4559 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4560 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4563 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4564 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4565 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4566 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4567 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4568 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4569 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4570 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4571 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4575 if ((broadcasted_opnd_size
== 256
4576 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4577 || (broadcasted_opnd_size
== 512
4578 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4581 i
.error
= unsupported_broadcast
;
4585 /* If broadcast is supported in this instruction, we need to check if
4586 operand of one-element size isn't specified without broadcast. */
4587 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4589 /* Find memory operand. */
4590 for (op
= 0; op
< i
.operands
; op
++)
4591 if (operand_type_check (i
.types
[op
], anymem
))
4593 gas_assert (op
< i
.operands
);
4594 /* Check size of the memory operand. */
4595 if ((t
->opcode_modifier
.vecesize
== 0
4596 && i
.types
[op
].bitfield
.dword
)
4597 || (t
->opcode_modifier
.vecesize
== 1
4598 && i
.types
[op
].bitfield
.qword
))
4600 i
.error
= broadcast_needed
;
4605 /* Check if requested masking is supported. */
4607 && (!t
->opcode_modifier
.masking
4609 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4611 i
.error
= unsupported_masking
;
4615 /* Check if masking is applied to dest operand. */
4616 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4618 i
.error
= mask_not_on_destination
;
4625 if ((i
.rounding
->type
!= saeonly
4626 && !t
->opcode_modifier
.staticrounding
)
4627 || (i
.rounding
->type
== saeonly
4628 && (t
->opcode_modifier
.staticrounding
4629 || !t
->opcode_modifier
.sae
)))
4631 i
.error
= unsupported_rc_sae
;
4634 /* If the instruction has several immediate operands and one of
4635 them is rounding, the rounding operand should be the last
4636 immediate operand. */
4637 if (i
.imm_operands
> 1
4638 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4640 i
.error
= rc_sae_operand_not_last_imm
;
4645 /* Check vector Disp8 operand. */
4646 if (t
->opcode_modifier
.disp8memshift
)
4649 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4651 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4653 for (op
= 0; op
< i
.operands
; op
++)
4654 if (operand_type_check (i
.types
[op
], disp
)
4655 && i
.op
[op
].disps
->X_op
== O_constant
)
4657 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4659 = (i
.disp_encoding
!= disp_encoding_32bit
4660 && fits_in_vec_disp8 (value
));
4661 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4664 i
.types
[op
].bitfield
.vec_disp8
= 1;
4667 /* Vector insn can only have Vec_Disp8/Disp32 in
4668 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4670 i
.types
[op
].bitfield
.disp8
= 0;
4671 if (flag_code
!= CODE_16BIT
)
4672 i
.types
[op
].bitfield
.disp16
= 0;
4675 else if (flag_code
!= CODE_16BIT
)
4677 /* One form of this instruction supports vector Disp8.
4678 Try vector Disp8 if we need to use Disp32. */
4679 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4681 i
.error
= try_vector_disp8
;
4693 /* Check if operands are valid for the instruction. Update VEX
4697 VEX_check_operands (const insn_template
*t
)
4699 /* VREX is only valid with EVEX prefix. */
4700 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4702 i
.error
= invalid_register_operand
;
4706 if (!t
->opcode_modifier
.vex
)
4709 /* Only check VEX_Imm4, which must be the first operand. */
4710 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4712 if (i
.op
[0].imms
->X_op
!= O_constant
4713 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4719 /* Turn off Imm8 so that update_imm won't complain. */
4720 i
.types
[0] = vec_imm4
;
4726 static const insn_template
*
4727 match_template (void)
4729 /* Points to template once we've found it. */
4730 const insn_template
*t
;
4731 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4732 i386_operand_type overlap4
;
4733 unsigned int found_reverse_match
;
4734 i386_opcode_modifier suffix_check
;
4735 i386_operand_type operand_types
[MAX_OPERANDS
];
4736 int addr_prefix_disp
;
4738 unsigned int found_cpu_match
;
4739 unsigned int check_register
;
4740 enum i386_error specific_error
= 0;
4742 #if MAX_OPERANDS != 5
4743 # error "MAX_OPERANDS must be 5."
4746 found_reverse_match
= 0;
4747 addr_prefix_disp
= -1;
4749 memset (&suffix_check
, 0, sizeof (suffix_check
));
4750 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4751 suffix_check
.no_bsuf
= 1;
4752 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4753 suffix_check
.no_wsuf
= 1;
4754 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4755 suffix_check
.no_ssuf
= 1;
4756 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4757 suffix_check
.no_lsuf
= 1;
4758 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4759 suffix_check
.no_qsuf
= 1;
4760 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4761 suffix_check
.no_ldsuf
= 1;
4763 /* Must have right number of operands. */
4764 i
.error
= number_of_operands_mismatch
;
4766 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4768 addr_prefix_disp
= -1;
4770 if (i
.operands
!= t
->operands
)
4773 /* Check processor support. */
4774 i
.error
= unsupported
;
4775 found_cpu_match
= (cpu_flags_match (t
)
4776 == CPU_FLAGS_PERFECT_MATCH
);
4777 if (!found_cpu_match
)
4780 /* Check old gcc support. */
4781 i
.error
= old_gcc_only
;
4782 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4785 /* Check AT&T mnemonic. */
4786 i
.error
= unsupported_with_intel_mnemonic
;
4787 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4790 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4791 i
.error
= unsupported_syntax
;
4792 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4793 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4794 || (intel64
&& t
->opcode_modifier
.amd64
)
4795 || (!intel64
&& t
->opcode_modifier
.intel64
))
4798 /* Check the suffix, except for some instructions in intel mode. */
4799 i
.error
= invalid_instruction_suffix
;
4800 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4801 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4802 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4803 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4804 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4805 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4806 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4809 if (!operand_size_match (t
))
4812 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4813 operand_types
[j
] = t
->operand_types
[j
];
4815 /* In general, don't allow 64-bit operands in 32-bit mode. */
4816 if (i
.suffix
== QWORD_MNEM_SUFFIX
4817 && flag_code
!= CODE_64BIT
4819 ? (!t
->opcode_modifier
.ignoresize
4820 && !intel_float_operand (t
->name
))
4821 : intel_float_operand (t
->name
) != 2)
4822 && ((!operand_types
[0].bitfield
.regmmx
4823 && !operand_types
[0].bitfield
.regxmm
4824 && !operand_types
[0].bitfield
.regymm
4825 && !operand_types
[0].bitfield
.regzmm
)
4826 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4827 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4828 && operand_types
[t
->operands
> 1].bitfield
.regymm
4829 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4830 && (t
->base_opcode
!= 0x0fc7
4831 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4834 /* In general, don't allow 32-bit operands on pre-386. */
4835 else if (i
.suffix
== LONG_MNEM_SUFFIX
4836 && !cpu_arch_flags
.bitfield
.cpui386
4838 ? (!t
->opcode_modifier
.ignoresize
4839 && !intel_float_operand (t
->name
))
4840 : intel_float_operand (t
->name
) != 2)
4841 && ((!operand_types
[0].bitfield
.regmmx
4842 && !operand_types
[0].bitfield
.regxmm
)
4843 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4844 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4847 /* Do not verify operands when there are none. */
4851 /* We've found a match; break out of loop. */
4855 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4856 into Disp32/Disp16/Disp32 operand. */
4857 if (i
.prefix
[ADDR_PREFIX
] != 0)
4859 /* There should be only one Disp operand. */
4863 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4865 if (operand_types
[j
].bitfield
.disp16
)
4867 addr_prefix_disp
= j
;
4868 operand_types
[j
].bitfield
.disp32
= 1;
4869 operand_types
[j
].bitfield
.disp16
= 0;
4875 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4877 if (operand_types
[j
].bitfield
.disp32
)
4879 addr_prefix_disp
= j
;
4880 operand_types
[j
].bitfield
.disp32
= 0;
4881 operand_types
[j
].bitfield
.disp16
= 1;
4887 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4889 if (operand_types
[j
].bitfield
.disp64
)
4891 addr_prefix_disp
= j
;
4892 operand_types
[j
].bitfield
.disp64
= 0;
4893 operand_types
[j
].bitfield
.disp32
= 1;
4901 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4902 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4905 /* We check register size if needed. */
4906 check_register
= t
->opcode_modifier
.checkregsize
;
4907 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4908 switch (t
->operands
)
4911 if (!operand_type_match (overlap0
, i
.types
[0]))
4915 /* xchg %eax, %eax is a special case. It is an aliase for nop
4916 only in 32bit mode and we can use opcode 0x90. In 64bit
4917 mode, we can't use 0x90 for xchg %eax, %eax since it should
4918 zero-extend %eax to %rax. */
4919 if (flag_code
== CODE_64BIT
4920 && t
->base_opcode
== 0x90
4921 && operand_type_equal (&i
.types
[0], &acc32
)
4922 && operand_type_equal (&i
.types
[1], &acc32
))
4926 /* If we swap operand in encoding, we either match
4927 the next one or reverse direction of operands. */
4928 if (t
->opcode_modifier
.s
)
4930 else if (t
->opcode_modifier
.d
)
4935 /* If we swap operand in encoding, we match the next one. */
4936 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4940 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4941 if (!operand_type_match (overlap0
, i
.types
[0])
4942 || !operand_type_match (overlap1
, i
.types
[1])
4944 && !operand_type_register_match (overlap0
, i
.types
[0],
4946 overlap1
, i
.types
[1],
4949 /* Check if other direction is valid ... */
4950 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4954 /* Try reversing direction of operands. */
4955 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4956 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4957 if (!operand_type_match (overlap0
, i
.types
[0])
4958 || !operand_type_match (overlap1
, i
.types
[1])
4960 && !operand_type_register_match (overlap0
,
4967 /* Does not match either direction. */
4970 /* found_reverse_match holds which of D or FloatDR
4972 if (t
->opcode_modifier
.d
)
4973 found_reverse_match
= Opcode_D
;
4974 else if (t
->opcode_modifier
.floatd
)
4975 found_reverse_match
= Opcode_FloatD
;
4977 found_reverse_match
= 0;
4978 if (t
->opcode_modifier
.floatr
)
4979 found_reverse_match
|= Opcode_FloatR
;
4983 /* Found a forward 2 operand match here. */
4984 switch (t
->operands
)
4987 overlap4
= operand_type_and (i
.types
[4],
4990 overlap3
= operand_type_and (i
.types
[3],
4993 overlap2
= operand_type_and (i
.types
[2],
4998 switch (t
->operands
)
5001 if (!operand_type_match (overlap4
, i
.types
[4])
5002 || !operand_type_register_match (overlap3
,
5010 if (!operand_type_match (overlap3
, i
.types
[3])
5012 && !operand_type_register_match (overlap2
,
5020 /* Here we make use of the fact that there are no
5021 reverse match 3 operand instructions, and all 3
5022 operand instructions only need to be checked for
5023 register consistency between operands 2 and 3. */
5024 if (!operand_type_match (overlap2
, i
.types
[2])
5026 && !operand_type_register_match (overlap1
,
5036 /* Found either forward/reverse 2, 3 or 4 operand match here:
5037 slip through to break. */
5039 if (!found_cpu_match
)
5041 found_reverse_match
= 0;
5045 /* Check if vector and VEX operands are valid. */
5046 if (check_VecOperands (t
) || VEX_check_operands (t
))
5048 specific_error
= i
.error
;
5052 /* We've found a match; break out of loop. */
5056 if (t
== current_templates
->end
)
5058 /* We found no match. */
5059 const char *err_msg
;
5060 switch (specific_error
? specific_error
: i
.error
)
5064 case operand_size_mismatch
:
5065 err_msg
= _("operand size mismatch");
5067 case operand_type_mismatch
:
5068 err_msg
= _("operand type mismatch");
5070 case register_type_mismatch
:
5071 err_msg
= _("register type mismatch");
5073 case number_of_operands_mismatch
:
5074 err_msg
= _("number of operands mismatch");
5076 case invalid_instruction_suffix
:
5077 err_msg
= _("invalid instruction suffix");
5080 err_msg
= _("constant doesn't fit in 4 bits");
5083 err_msg
= _("only supported with old gcc");
5085 case unsupported_with_intel_mnemonic
:
5086 err_msg
= _("unsupported with Intel mnemonic");
5088 case unsupported_syntax
:
5089 err_msg
= _("unsupported syntax");
5092 as_bad (_("unsupported instruction `%s'"),
5093 current_templates
->start
->name
);
5095 case invalid_vsib_address
:
5096 err_msg
= _("invalid VSIB address");
5098 case invalid_vector_register_set
:
5099 err_msg
= _("mask, index, and destination registers must be distinct");
5101 case unsupported_vector_index_register
:
5102 err_msg
= _("unsupported vector index register");
5104 case unsupported_broadcast
:
5105 err_msg
= _("unsupported broadcast");
5107 case broadcast_not_on_src_operand
:
5108 err_msg
= _("broadcast not on source memory operand");
5110 case broadcast_needed
:
5111 err_msg
= _("broadcast is needed for operand of such type");
5113 case unsupported_masking
:
5114 err_msg
= _("unsupported masking");
5116 case mask_not_on_destination
:
5117 err_msg
= _("mask not on destination operand");
5119 case no_default_mask
:
5120 err_msg
= _("default mask isn't allowed");
5122 case unsupported_rc_sae
:
5123 err_msg
= _("unsupported static rounding/sae");
5125 case rc_sae_operand_not_last_imm
:
5127 err_msg
= _("RC/SAE operand must precede immediate operands");
5129 err_msg
= _("RC/SAE operand must follow immediate operands");
5131 case invalid_register_operand
:
5132 err_msg
= _("invalid register operand");
5135 as_bad (_("%s for `%s'"), err_msg
,
5136 current_templates
->start
->name
);
5140 if (!quiet_warnings
)
5143 && (i
.types
[0].bitfield
.jumpabsolute
5144 != operand_types
[0].bitfield
.jumpabsolute
))
5146 as_warn (_("indirect %s without `*'"), t
->name
);
5149 if (t
->opcode_modifier
.isprefix
5150 && t
->opcode_modifier
.ignoresize
)
5152 /* Warn them that a data or address size prefix doesn't
5153 affect assembly of the next line of code. */
5154 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5158 /* Copy the template we found. */
5161 if (addr_prefix_disp
!= -1)
5162 i
.tm
.operand_types
[addr_prefix_disp
]
5163 = operand_types
[addr_prefix_disp
];
5165 if (found_reverse_match
)
5167 /* If we found a reverse match we must alter the opcode
5168 direction bit. found_reverse_match holds bits to change
5169 (different for int & float insns). */
5171 i
.tm
.base_opcode
^= found_reverse_match
;
5173 i
.tm
.operand_types
[0] = operand_types
[1];
5174 i
.tm
.operand_types
[1] = operand_types
[0];
5183 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5184 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5186 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5188 as_bad (_("`%s' operand %d must use `%ses' segment"),
5194 /* There's only ever one segment override allowed per instruction.
5195 This instruction possibly has a legal segment override on the
5196 second operand, so copy the segment to where non-string
5197 instructions store it, allowing common code. */
5198 i
.seg
[0] = i
.seg
[1];
5200 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5202 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5204 as_bad (_("`%s' operand %d must use `%ses' segment"),
5215 process_suffix (void)
5217 /* If matched instruction specifies an explicit instruction mnemonic
5219 if (i
.tm
.opcode_modifier
.size16
)
5220 i
.suffix
= WORD_MNEM_SUFFIX
;
5221 else if (i
.tm
.opcode_modifier
.size32
)
5222 i
.suffix
= LONG_MNEM_SUFFIX
;
5223 else if (i
.tm
.opcode_modifier
.size64
)
5224 i
.suffix
= QWORD_MNEM_SUFFIX
;
5225 else if (i
.reg_operands
)
5227 /* If there's no instruction mnemonic suffix we try to invent one
5228 based on register operands. */
5231 /* We take i.suffix from the last register operand specified,
5232 Destination register type is more significant than source
5233 register type. crc32 in SSE4.2 prefers source register
5235 if (i
.tm
.base_opcode
== 0xf20f38f1)
5237 if (i
.types
[0].bitfield
.reg16
)
5238 i
.suffix
= WORD_MNEM_SUFFIX
;
5239 else if (i
.types
[0].bitfield
.reg32
)
5240 i
.suffix
= LONG_MNEM_SUFFIX
;
5241 else if (i
.types
[0].bitfield
.reg64
)
5242 i
.suffix
= QWORD_MNEM_SUFFIX
;
5244 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5246 if (i
.types
[0].bitfield
.reg8
)
5247 i
.suffix
= BYTE_MNEM_SUFFIX
;
5254 if (i
.tm
.base_opcode
== 0xf20f38f1
5255 || i
.tm
.base_opcode
== 0xf20f38f0)
5257 /* We have to know the operand size for crc32. */
5258 as_bad (_("ambiguous memory operand size for `%s`"),
5263 for (op
= i
.operands
; --op
>= 0;)
5264 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5266 if (i
.types
[op
].bitfield
.reg8
)
5268 i
.suffix
= BYTE_MNEM_SUFFIX
;
5271 else if (i
.types
[op
].bitfield
.reg16
)
5273 i
.suffix
= WORD_MNEM_SUFFIX
;
5276 else if (i
.types
[op
].bitfield
.reg32
)
5278 i
.suffix
= LONG_MNEM_SUFFIX
;
5281 else if (i
.types
[op
].bitfield
.reg64
)
5283 i
.suffix
= QWORD_MNEM_SUFFIX
;
5289 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5292 && i
.tm
.opcode_modifier
.ignoresize
5293 && i
.tm
.opcode_modifier
.no_bsuf
)
5295 else if (!check_byte_reg ())
5298 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5301 && i
.tm
.opcode_modifier
.ignoresize
5302 && i
.tm
.opcode_modifier
.no_lsuf
)
5304 else if (!check_long_reg ())
5307 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5310 && i
.tm
.opcode_modifier
.ignoresize
5311 && i
.tm
.opcode_modifier
.no_qsuf
)
5313 else if (!check_qword_reg ())
5316 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5319 && i
.tm
.opcode_modifier
.ignoresize
5320 && i
.tm
.opcode_modifier
.no_wsuf
)
5322 else if (!check_word_reg ())
5325 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5326 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5327 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5329 /* Skip if the instruction has x/y/z suffix. match_template
5330 should check if it is a valid suffix. */
5332 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5333 /* Do nothing if the instruction is going to ignore the prefix. */
5338 else if (i
.tm
.opcode_modifier
.defaultsize
5340 /* exclude fldenv/frstor/fsave/fstenv */
5341 && i
.tm
.opcode_modifier
.no_ssuf
)
5343 i
.suffix
= stackop_size
;
5345 else if (intel_syntax
5347 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5348 || i
.tm
.opcode_modifier
.jumpbyte
5349 || i
.tm
.opcode_modifier
.jumpintersegment
5350 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5351 && i
.tm
.extension_opcode
<= 3)))
5356 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5358 i
.suffix
= QWORD_MNEM_SUFFIX
;
5362 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5363 i
.suffix
= LONG_MNEM_SUFFIX
;
5366 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5367 i
.suffix
= WORD_MNEM_SUFFIX
;
5376 if (i
.tm
.opcode_modifier
.w
)
5378 as_bad (_("no instruction mnemonic suffix given and "
5379 "no register operands; can't size instruction"));
5385 unsigned int suffixes
;
5387 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5388 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5390 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5392 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5394 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5396 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5399 /* There are more than suffix matches. */
5400 if (i
.tm
.opcode_modifier
.w
5401 || ((suffixes
& (suffixes
- 1))
5402 && !i
.tm
.opcode_modifier
.defaultsize
5403 && !i
.tm
.opcode_modifier
.ignoresize
))
5405 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5411 /* Change the opcode based on the operand size given by i.suffix;
5412 We don't need to change things for byte insns. */
5415 && i
.suffix
!= BYTE_MNEM_SUFFIX
5416 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5417 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5418 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5420 /* It's not a byte, select word/dword operation. */
5421 if (i
.tm
.opcode_modifier
.w
)
5423 if (i
.tm
.opcode_modifier
.shortform
)
5424 i
.tm
.base_opcode
|= 8;
5426 i
.tm
.base_opcode
|= 1;
5429 /* Now select between word & dword operations via the operand
5430 size prefix, except for instructions that will ignore this
5432 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5434 /* The address size override prefix changes the size of the
5436 if ((flag_code
== CODE_32BIT
5437 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5438 || (flag_code
!= CODE_32BIT
5439 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5440 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5443 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5444 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5445 && !i
.tm
.opcode_modifier
.ignoresize
5446 && !i
.tm
.opcode_modifier
.floatmf
5447 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5448 || (flag_code
== CODE_64BIT
5449 && i
.tm
.opcode_modifier
.jumpbyte
)))
5451 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5453 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5454 prefix
= ADDR_PREFIX_OPCODE
;
5456 if (!add_prefix (prefix
))
5460 /* Set mode64 for an operand. */
5461 if (i
.suffix
== QWORD_MNEM_SUFFIX
5462 && flag_code
== CODE_64BIT
5463 && !i
.tm
.opcode_modifier
.norex64
)
5465 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5466 need rex64. cmpxchg8b is also a special case. */
5467 if (! (i
.operands
== 2
5468 && i
.tm
.base_opcode
== 0x90
5469 && i
.tm
.extension_opcode
== None
5470 && operand_type_equal (&i
.types
[0], &acc64
)
5471 && operand_type_equal (&i
.types
[1], &acc64
))
5472 && ! (i
.operands
== 1
5473 && i
.tm
.base_opcode
== 0xfc7
5474 && i
.tm
.extension_opcode
== 1
5475 && !operand_type_check (i
.types
[0], reg
)
5476 && operand_type_check (i
.types
[0], anymem
)))
5480 /* Size floating point instruction. */
5481 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5482 if (i
.tm
.opcode_modifier
.floatmf
)
5483 i
.tm
.base_opcode
^= 4;
5490 check_byte_reg (void)
5494 for (op
= i
.operands
; --op
>= 0;)
5496 /* If this is an eight bit register, it's OK. If it's the 16 or
5497 32 bit version of an eight bit register, we will just use the
5498 low portion, and that's OK too. */
5499 if (i
.types
[op
].bitfield
.reg8
)
5502 /* I/O port address operands are OK too. */
5503 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5506 /* crc32 doesn't generate this warning. */
5507 if (i
.tm
.base_opcode
== 0xf20f38f0)
5510 if ((i
.types
[op
].bitfield
.reg16
5511 || i
.types
[op
].bitfield
.reg32
5512 || i
.types
[op
].bitfield
.reg64
)
5513 && i
.op
[op
].regs
->reg_num
< 4
5514 /* Prohibit these changes in 64bit mode, since the lowering
5515 would be more complicated. */
5516 && flag_code
!= CODE_64BIT
)
5518 #if REGISTER_WARNINGS
5519 if (!quiet_warnings
)
5520 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5522 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5523 ? REGNAM_AL
- REGNAM_AX
5524 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5526 i
.op
[op
].regs
->reg_name
,
5531 /* Any other register is bad. */
5532 if (i
.types
[op
].bitfield
.reg16
5533 || i
.types
[op
].bitfield
.reg32
5534 || i
.types
[op
].bitfield
.reg64
5535 || i
.types
[op
].bitfield
.regmmx
5536 || i
.types
[op
].bitfield
.regxmm
5537 || i
.types
[op
].bitfield
.regymm
5538 || i
.types
[op
].bitfield
.regzmm
5539 || i
.types
[op
].bitfield
.sreg2
5540 || i
.types
[op
].bitfield
.sreg3
5541 || i
.types
[op
].bitfield
.control
5542 || i
.types
[op
].bitfield
.debug
5543 || i
.types
[op
].bitfield
.test
5544 || i
.types
[op
].bitfield
.floatreg
5545 || i
.types
[op
].bitfield
.floatacc
)
5547 as_bad (_("`%s%s' not allowed with `%s%c'"),
5549 i
.op
[op
].regs
->reg_name
,
5559 check_long_reg (void)
5563 for (op
= i
.operands
; --op
>= 0;)
5564 /* Reject eight bit registers, except where the template requires
5565 them. (eg. movzb) */
5566 if (i
.types
[op
].bitfield
.reg8
5567 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5568 || i
.tm
.operand_types
[op
].bitfield
.reg32
5569 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5571 as_bad (_("`%s%s' not allowed with `%s%c'"),
5573 i
.op
[op
].regs
->reg_name
,
5578 /* Warn if the e prefix on a general reg is missing. */
5579 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5580 && i
.types
[op
].bitfield
.reg16
5581 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5582 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5584 /* Prohibit these changes in the 64bit mode, since the
5585 lowering is more complicated. */
5586 if (flag_code
== CODE_64BIT
)
5588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5589 register_prefix
, i
.op
[op
].regs
->reg_name
,
5593 #if REGISTER_WARNINGS
5594 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5596 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5597 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5600 /* Warn if the r prefix on a general reg is present. */
5601 else if (i
.types
[op
].bitfield
.reg64
5602 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5603 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5606 && i
.tm
.opcode_modifier
.toqword
5607 && !i
.types
[0].bitfield
.regxmm
)
5609 /* Convert to QWORD. We want REX byte. */
5610 i
.suffix
= QWORD_MNEM_SUFFIX
;
5614 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5615 register_prefix
, i
.op
[op
].regs
->reg_name
,
5624 check_qword_reg (void)
5628 for (op
= i
.operands
; --op
>= 0; )
5629 /* Reject eight bit registers, except where the template requires
5630 them. (eg. movzb) */
5631 if (i
.types
[op
].bitfield
.reg8
5632 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5633 || i
.tm
.operand_types
[op
].bitfield
.reg32
5634 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5636 as_bad (_("`%s%s' not allowed with `%s%c'"),
5638 i
.op
[op
].regs
->reg_name
,
5643 /* Warn if the r prefix on a general reg is missing. */
5644 else if ((i
.types
[op
].bitfield
.reg16
5645 || i
.types
[op
].bitfield
.reg32
)
5646 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5647 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5649 /* Prohibit these changes in the 64bit mode, since the
5650 lowering is more complicated. */
5652 && i
.tm
.opcode_modifier
.todword
5653 && !i
.types
[0].bitfield
.regxmm
)
5655 /* Convert to DWORD. We don't want REX byte. */
5656 i
.suffix
= LONG_MNEM_SUFFIX
;
5660 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5661 register_prefix
, i
.op
[op
].regs
->reg_name
,
5670 check_word_reg (void)
5673 for (op
= i
.operands
; --op
>= 0;)
5674 /* Reject eight bit registers, except where the template requires
5675 them. (eg. movzb) */
5676 if (i
.types
[op
].bitfield
.reg8
5677 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5678 || i
.tm
.operand_types
[op
].bitfield
.reg32
5679 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5681 as_bad (_("`%s%s' not allowed with `%s%c'"),
5683 i
.op
[op
].regs
->reg_name
,
5688 /* Warn if the e or r prefix on a general reg is present. */
5689 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5690 && (i
.types
[op
].bitfield
.reg32
5691 || i
.types
[op
].bitfield
.reg64
)
5692 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5693 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5695 /* Prohibit these changes in the 64bit mode, since the
5696 lowering is more complicated. */
5697 if (flag_code
== CODE_64BIT
)
5699 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5700 register_prefix
, i
.op
[op
].regs
->reg_name
,
5704 #if REGISTER_WARNINGS
5705 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5707 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5708 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5715 update_imm (unsigned int j
)
5717 i386_operand_type overlap
= i
.types
[j
];
5718 if ((overlap
.bitfield
.imm8
5719 || overlap
.bitfield
.imm8s
5720 || overlap
.bitfield
.imm16
5721 || overlap
.bitfield
.imm32
5722 || overlap
.bitfield
.imm32s
5723 || overlap
.bitfield
.imm64
)
5724 && !operand_type_equal (&overlap
, &imm8
)
5725 && !operand_type_equal (&overlap
, &imm8s
)
5726 && !operand_type_equal (&overlap
, &imm16
)
5727 && !operand_type_equal (&overlap
, &imm32
)
5728 && !operand_type_equal (&overlap
, &imm32s
)
5729 && !operand_type_equal (&overlap
, &imm64
))
5733 i386_operand_type temp
;
5735 operand_type_set (&temp
, 0);
5736 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5738 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5739 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5741 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5742 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5743 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5745 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5746 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5749 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5752 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5753 || operand_type_equal (&overlap
, &imm16_32
)
5754 || operand_type_equal (&overlap
, &imm16_32s
))
5756 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5761 if (!operand_type_equal (&overlap
, &imm8
)
5762 && !operand_type_equal (&overlap
, &imm8s
)
5763 && !operand_type_equal (&overlap
, &imm16
)
5764 && !operand_type_equal (&overlap
, &imm32
)
5765 && !operand_type_equal (&overlap
, &imm32s
)
5766 && !operand_type_equal (&overlap
, &imm64
))
5768 as_bad (_("no instruction mnemonic suffix given; "
5769 "can't determine immediate size"));
5773 i
.types
[j
] = overlap
;
5783 /* Update the first 2 immediate operands. */
5784 n
= i
.operands
> 2 ? 2 : i
.operands
;
5787 for (j
= 0; j
< n
; j
++)
5788 if (update_imm (j
) == 0)
5791 /* The 3rd operand can't be immediate operand. */
5792 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5799 bad_implicit_operand (int xmm
)
5801 const char *ireg
= xmm
? "xmm0" : "ymm0";
5804 as_bad (_("the last operand of `%s' must be `%s%s'"),
5805 i
.tm
.name
, register_prefix
, ireg
);
5807 as_bad (_("the first operand of `%s' must be `%s%s'"),
5808 i
.tm
.name
, register_prefix
, ireg
);
5813 process_operands (void)
5815 /* Default segment register this instruction will use for memory
5816 accesses. 0 means unknown. This is only for optimizing out
5817 unnecessary segment overrides. */
5818 const seg_entry
*default_seg
= 0;
5820 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5822 unsigned int dupl
= i
.operands
;
5823 unsigned int dest
= dupl
- 1;
5826 /* The destination must be an xmm register. */
5827 gas_assert (i
.reg_operands
5828 && MAX_OPERANDS
> dupl
5829 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5831 if (i
.tm
.opcode_modifier
.firstxmm0
)
5833 /* The first operand is implicit and must be xmm0. */
5834 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5835 if (register_number (i
.op
[0].regs
) != 0)
5836 return bad_implicit_operand (1);
5838 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5840 /* Keep xmm0 for instructions with VEX prefix and 3
5846 /* We remove the first xmm0 and keep the number of
5847 operands unchanged, which in fact duplicates the
5849 for (j
= 1; j
< i
.operands
; j
++)
5851 i
.op
[j
- 1] = i
.op
[j
];
5852 i
.types
[j
- 1] = i
.types
[j
];
5853 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5857 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5859 gas_assert ((MAX_OPERANDS
- 1) > dupl
5860 && (i
.tm
.opcode_modifier
.vexsources
5863 /* Add the implicit xmm0 for instructions with VEX prefix
5865 for (j
= i
.operands
; j
> 0; j
--)
5867 i
.op
[j
] = i
.op
[j
- 1];
5868 i
.types
[j
] = i
.types
[j
- 1];
5869 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5872 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5873 i
.types
[0] = regxmm
;
5874 i
.tm
.operand_types
[0] = regxmm
;
5877 i
.reg_operands
+= 2;
5882 i
.op
[dupl
] = i
.op
[dest
];
5883 i
.types
[dupl
] = i
.types
[dest
];
5884 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5893 i
.op
[dupl
] = i
.op
[dest
];
5894 i
.types
[dupl
] = i
.types
[dest
];
5895 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5898 if (i
.tm
.opcode_modifier
.immext
)
5901 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5905 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5906 gas_assert (i
.reg_operands
5907 && (operand_type_equal (&i
.types
[0], ®xmm
)
5908 || operand_type_equal (&i
.types
[0], ®ymm
)
5909 || operand_type_equal (&i
.types
[0], ®zmm
)));
5910 if (register_number (i
.op
[0].regs
) != 0)
5911 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5913 for (j
= 1; j
< i
.operands
; j
++)
5915 i
.op
[j
- 1] = i
.op
[j
];
5916 i
.types
[j
- 1] = i
.types
[j
];
5918 /* We need to adjust fields in i.tm since they are used by
5919 build_modrm_byte. */
5920 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5927 else if (i
.tm
.opcode_modifier
.regkludge
)
5929 /* The imul $imm, %reg instruction is converted into
5930 imul $imm, %reg, %reg, and the clr %reg instruction
5931 is converted into xor %reg, %reg. */
5933 unsigned int first_reg_op
;
5935 if (operand_type_check (i
.types
[0], reg
))
5939 /* Pretend we saw the extra register operand. */
5940 gas_assert (i
.reg_operands
== 1
5941 && i
.op
[first_reg_op
+ 1].regs
== 0);
5942 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5943 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5948 if (i
.tm
.opcode_modifier
.shortform
)
5950 if (i
.types
[0].bitfield
.sreg2
5951 || i
.types
[0].bitfield
.sreg3
)
5953 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5954 && i
.op
[0].regs
->reg_num
== 1)
5956 as_bad (_("you can't `pop %scs'"), register_prefix
);
5959 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5960 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5965 /* The register or float register operand is in operand
5969 if (i
.types
[0].bitfield
.floatreg
5970 || operand_type_check (i
.types
[0], reg
))
5974 /* Register goes in low 3 bits of opcode. */
5975 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5976 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5978 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5980 /* Warn about some common errors, but press on regardless.
5981 The first case can be generated by gcc (<= 2.8.1). */
5982 if (i
.operands
== 2)
5984 /* Reversed arguments on faddp, fsubp, etc. */
5985 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5986 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5987 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5991 /* Extraneous `l' suffix on fp insn. */
5992 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5993 register_prefix
, i
.op
[0].regs
->reg_name
);
5998 else if (i
.tm
.opcode_modifier
.modrm
)
6000 /* The opcode is completed (modulo i.tm.extension_opcode which
6001 must be put into the modrm byte). Now, we make the modrm and
6002 index base bytes based on all the info we've collected. */
6004 default_seg
= build_modrm_byte ();
6006 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6010 else if (i
.tm
.opcode_modifier
.isstring
)
6012 /* For the string instructions that allow a segment override
6013 on one of their operands, the default segment is ds. */
6017 if (i
.tm
.base_opcode
== 0x8d /* lea */
6020 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6022 /* If a segment was explicitly specified, and the specified segment
6023 is not the default, use an opcode prefix to select it. If we
6024 never figured out what the default segment is, then default_seg
6025 will be zero at this point, and the specified segment prefix will
6027 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6029 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6035 static const seg_entry
*
6036 build_modrm_byte (void)
6038 const seg_entry
*default_seg
= 0;
6039 unsigned int source
, dest
;
6042 /* The first operand of instructions with VEX prefix and 3 sources
6043 must be VEX_Imm4. */
6044 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6047 unsigned int nds
, reg_slot
;
6050 if (i
.tm
.opcode_modifier
.veximmext
6051 && i
.tm
.opcode_modifier
.immext
)
6053 dest
= i
.operands
- 2;
6054 gas_assert (dest
== 3);
6057 dest
= i
.operands
- 1;
6060 /* There are 2 kinds of instructions:
6061 1. 5 operands: 4 register operands or 3 register operands
6062 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6063 VexW0 or VexW1. The destination must be either XMM, YMM or
6065 2. 4 operands: 4 register operands or 3 register operands
6066 plus 1 memory operand, VexXDS, and VexImmExt */
6067 gas_assert ((i
.reg_operands
== 4
6068 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6069 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6070 && (i
.tm
.opcode_modifier
.veximmext
6071 || (i
.imm_operands
== 1
6072 && i
.types
[0].bitfield
.vec_imm4
6073 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6074 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6075 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6076 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6077 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6079 if (i
.imm_operands
== 0)
6081 /* When there is no immediate operand, generate an 8bit
6082 immediate operand to encode the first operand. */
6083 exp
= &im_expressions
[i
.imm_operands
++];
6084 i
.op
[i
.operands
].imms
= exp
;
6085 i
.types
[i
.operands
] = imm8
;
6087 /* If VexW1 is set, the first operand is the source and
6088 the second operand is encoded in the immediate operand. */
6089 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6100 /* FMA swaps REG and NDS. */
6101 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6109 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6111 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6113 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6115 exp
->X_op
= O_constant
;
6116 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6117 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6121 unsigned int imm_slot
;
6123 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6125 /* If VexW0 is set, the third operand is the source and
6126 the second operand is encoded in the immediate
6133 /* VexW1 is set, the second operand is the source and
6134 the third operand is encoded in the immediate
6140 if (i
.tm
.opcode_modifier
.immext
)
6142 /* When ImmExt is set, the immdiate byte is the last
6144 imm_slot
= i
.operands
- 1;
6152 /* Turn on Imm8 so that output_imm will generate it. */
6153 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6156 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6158 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6160 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6162 i
.op
[imm_slot
].imms
->X_add_number
6163 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6164 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6167 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6168 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6170 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6172 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6177 /* i.reg_operands MUST be the number of real register operands;
6178 implicit registers do not count. If there are 3 register
6179 operands, it must be a instruction with VexNDS. For a
6180 instruction with VexNDD, the destination register is encoded
6181 in VEX prefix. If there are 4 register operands, it must be
6182 a instruction with VEX prefix and 3 sources. */
6183 if (i
.mem_operands
== 0
6184 && ((i
.reg_operands
== 2
6185 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6186 || (i
.reg_operands
== 3
6187 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6188 || (i
.reg_operands
== 4 && vex_3_sources
)))
6196 /* When there are 3 operands, one of them may be immediate,
6197 which may be the first or the last operand. Otherwise,
6198 the first operand must be shift count register (cl) or it
6199 is an instruction with VexNDS. */
6200 gas_assert (i
.imm_operands
== 1
6201 || (i
.imm_operands
== 0
6202 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6203 || i
.types
[0].bitfield
.shiftcount
)));
6204 if (operand_type_check (i
.types
[0], imm
)
6205 || i
.types
[0].bitfield
.shiftcount
)
6211 /* When there are 4 operands, the first two must be 8bit
6212 immediate operands. The source operand will be the 3rd
6215 For instructions with VexNDS, if the first operand
6216 an imm8, the source operand is the 2nd one. If the last
6217 operand is imm8, the source operand is the first one. */
6218 gas_assert ((i
.imm_operands
== 2
6219 && i
.types
[0].bitfield
.imm8
6220 && i
.types
[1].bitfield
.imm8
)
6221 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6222 && i
.imm_operands
== 1
6223 && (i
.types
[0].bitfield
.imm8
6224 || i
.types
[i
.operands
- 1].bitfield
.imm8
6226 if (i
.imm_operands
== 2)
6230 if (i
.types
[0].bitfield
.imm8
)
6237 if (i
.tm
.opcode_modifier
.evex
)
6239 /* For EVEX instructions, when there are 5 operands, the
6240 first one must be immediate operand. If the second one
6241 is immediate operand, the source operand is the 3th
6242 one. If the last one is immediate operand, the source
6243 operand is the 2nd one. */
6244 gas_assert (i
.imm_operands
== 2
6245 && i
.tm
.opcode_modifier
.sae
6246 && operand_type_check (i
.types
[0], imm
));
6247 if (operand_type_check (i
.types
[1], imm
))
6249 else if (operand_type_check (i
.types
[4], imm
))
6263 /* RC/SAE operand could be between DEST and SRC. That happens
6264 when one operand is GPR and the other one is XMM/YMM/ZMM
6266 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6269 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6271 /* For instructions with VexNDS, the register-only source
6272 operand must be 32/64bit integer, XMM, YMM or ZMM
6273 register. It is encoded in VEX prefix. We need to
6274 clear RegMem bit before calling operand_type_equal. */
6276 i386_operand_type op
;
6279 /* Check register-only source operand when two source
6280 operands are swapped. */
6281 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6282 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6290 op
= i
.tm
.operand_types
[vvvv
];
6291 op
.bitfield
.regmem
= 0;
6292 if ((dest
+ 1) >= i
.operands
6293 || (!op
.bitfield
.reg32
6294 && op
.bitfield
.reg64
6295 && !operand_type_equal (&op
, ®xmm
)
6296 && !operand_type_equal (&op
, ®ymm
)
6297 && !operand_type_equal (&op
, ®zmm
)
6298 && !operand_type_equal (&op
, ®mask
)))
6300 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6306 /* One of the register operands will be encoded in the i.tm.reg
6307 field, the other in the combined i.tm.mode and i.tm.regmem
6308 fields. If no form of this instruction supports a memory
6309 destination operand, then we assume the source operand may
6310 sometimes be a memory operand and so we need to store the
6311 destination in the i.rm.reg field. */
6312 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6313 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6315 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6316 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6317 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6319 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6321 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6323 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6328 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6329 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6330 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6332 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6334 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6336 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6339 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6341 if (!i
.types
[0].bitfield
.control
6342 && !i
.types
[1].bitfield
.control
)
6344 i
.rex
&= ~(REX_R
| REX_B
);
6345 add_prefix (LOCK_PREFIX_OPCODE
);
6349 { /* If it's not 2 reg operands... */
6354 unsigned int fake_zero_displacement
= 0;
6357 for (op
= 0; op
< i
.operands
; op
++)
6358 if (operand_type_check (i
.types
[op
], anymem
))
6360 gas_assert (op
< i
.operands
);
6362 if (i
.tm
.opcode_modifier
.vecsib
)
6364 if (i
.index_reg
->reg_num
== RegEiz
6365 || i
.index_reg
->reg_num
== RegRiz
)
6368 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6371 i
.sib
.base
= NO_BASE_REGISTER
;
6372 i
.sib
.scale
= i
.log2_scale_factor
;
6373 /* No Vec_Disp8 if there is no base. */
6374 i
.types
[op
].bitfield
.vec_disp8
= 0;
6375 i
.types
[op
].bitfield
.disp8
= 0;
6376 i
.types
[op
].bitfield
.disp16
= 0;
6377 i
.types
[op
].bitfield
.disp64
= 0;
6378 if (flag_code
!= CODE_64BIT
)
6380 /* Must be 32 bit */
6381 i
.types
[op
].bitfield
.disp32
= 1;
6382 i
.types
[op
].bitfield
.disp32s
= 0;
6386 i
.types
[op
].bitfield
.disp32
= 0;
6387 i
.types
[op
].bitfield
.disp32s
= 1;
6390 i
.sib
.index
= i
.index_reg
->reg_num
;
6391 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6393 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6399 if (i
.base_reg
== 0)
6402 if (!i
.disp_operands
)
6404 fake_zero_displacement
= 1;
6405 /* Instructions with VSIB byte need 32bit displacement
6406 if there is no base register. */
6407 if (i
.tm
.opcode_modifier
.vecsib
)
6408 i
.types
[op
].bitfield
.disp32
= 1;
6410 if (i
.index_reg
== 0)
6412 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6413 /* Operand is just <disp> */
6414 if (flag_code
== CODE_64BIT
)
6416 /* 64bit mode overwrites the 32bit absolute
6417 addressing by RIP relative addressing and
6418 absolute addressing is encoded by one of the
6419 redundant SIB forms. */
6420 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6421 i
.sib
.base
= NO_BASE_REGISTER
;
6422 i
.sib
.index
= NO_INDEX_REGISTER
;
6423 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6424 ? disp32s
: disp32
);
6426 else if ((flag_code
== CODE_16BIT
)
6427 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6429 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6430 i
.types
[op
] = disp16
;
6434 i
.rm
.regmem
= NO_BASE_REGISTER
;
6435 i
.types
[op
] = disp32
;
6438 else if (!i
.tm
.opcode_modifier
.vecsib
)
6440 /* !i.base_reg && i.index_reg */
6441 if (i
.index_reg
->reg_num
== RegEiz
6442 || i
.index_reg
->reg_num
== RegRiz
)
6443 i
.sib
.index
= NO_INDEX_REGISTER
;
6445 i
.sib
.index
= i
.index_reg
->reg_num
;
6446 i
.sib
.base
= NO_BASE_REGISTER
;
6447 i
.sib
.scale
= i
.log2_scale_factor
;
6448 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6449 /* No Vec_Disp8 if there is no base. */
6450 i
.types
[op
].bitfield
.vec_disp8
= 0;
6451 i
.types
[op
].bitfield
.disp8
= 0;
6452 i
.types
[op
].bitfield
.disp16
= 0;
6453 i
.types
[op
].bitfield
.disp64
= 0;
6454 if (flag_code
!= CODE_64BIT
)
6456 /* Must be 32 bit */
6457 i
.types
[op
].bitfield
.disp32
= 1;
6458 i
.types
[op
].bitfield
.disp32s
= 0;
6462 i
.types
[op
].bitfield
.disp32
= 0;
6463 i
.types
[op
].bitfield
.disp32s
= 1;
6465 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6469 /* RIP addressing for 64bit mode. */
6470 else if (i
.base_reg
->reg_num
== RegRip
||
6471 i
.base_reg
->reg_num
== RegEip
)
6473 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6474 i
.rm
.regmem
= NO_BASE_REGISTER
;
6475 i
.types
[op
].bitfield
.disp8
= 0;
6476 i
.types
[op
].bitfield
.disp16
= 0;
6477 i
.types
[op
].bitfield
.disp32
= 0;
6478 i
.types
[op
].bitfield
.disp32s
= 1;
6479 i
.types
[op
].bitfield
.disp64
= 0;
6480 i
.types
[op
].bitfield
.vec_disp8
= 0;
6481 i
.flags
[op
] |= Operand_PCrel
;
6482 if (! i
.disp_operands
)
6483 fake_zero_displacement
= 1;
6485 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6487 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6488 switch (i
.base_reg
->reg_num
)
6491 if (i
.index_reg
== 0)
6493 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6494 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6498 if (i
.index_reg
== 0)
6501 if (operand_type_check (i
.types
[op
], disp
) == 0)
6503 /* fake (%bp) into 0(%bp) */
6504 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6505 i
.types
[op
].bitfield
.vec_disp8
= 1;
6507 i
.types
[op
].bitfield
.disp8
= 1;
6508 fake_zero_displacement
= 1;
6511 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6512 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6514 default: /* (%si) -> 4 or (%di) -> 5 */
6515 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6517 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6519 else /* i.base_reg and 32/64 bit mode */
6521 if (flag_code
== CODE_64BIT
6522 && operand_type_check (i
.types
[op
], disp
))
6524 i386_operand_type temp
;
6525 operand_type_set (&temp
, 0);
6526 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6527 temp
.bitfield
.vec_disp8
6528 = i
.types
[op
].bitfield
.vec_disp8
;
6530 if (i
.prefix
[ADDR_PREFIX
] == 0)
6531 i
.types
[op
].bitfield
.disp32s
= 1;
6533 i
.types
[op
].bitfield
.disp32
= 1;
6536 if (!i
.tm
.opcode_modifier
.vecsib
)
6537 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6538 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6540 i
.sib
.base
= i
.base_reg
->reg_num
;
6541 /* x86-64 ignores REX prefix bit here to avoid decoder
6543 if (!(i
.base_reg
->reg_flags
& RegRex
)
6544 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6545 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6547 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6549 fake_zero_displacement
= 1;
6550 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6551 i
.types
[op
].bitfield
.vec_disp8
= 1;
6553 i
.types
[op
].bitfield
.disp8
= 1;
6555 i
.sib
.scale
= i
.log2_scale_factor
;
6556 if (i
.index_reg
== 0)
6558 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6559 /* <disp>(%esp) becomes two byte modrm with no index
6560 register. We've already stored the code for esp
6561 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6562 Any base register besides %esp will not use the
6563 extra modrm byte. */
6564 i
.sib
.index
= NO_INDEX_REGISTER
;
6566 else if (!i
.tm
.opcode_modifier
.vecsib
)
6568 if (i
.index_reg
->reg_num
== RegEiz
6569 || i
.index_reg
->reg_num
== RegRiz
)
6570 i
.sib
.index
= NO_INDEX_REGISTER
;
6572 i
.sib
.index
= i
.index_reg
->reg_num
;
6573 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6574 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6579 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6580 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6584 if (!fake_zero_displacement
6588 fake_zero_displacement
= 1;
6589 if (i
.disp_encoding
== disp_encoding_8bit
)
6590 i
.types
[op
].bitfield
.disp8
= 1;
6592 i
.types
[op
].bitfield
.disp32
= 1;
6594 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6598 if (fake_zero_displacement
)
6600 /* Fakes a zero displacement assuming that i.types[op]
6601 holds the correct displacement size. */
6604 gas_assert (i
.op
[op
].disps
== 0);
6605 exp
= &disp_expressions
[i
.disp_operands
++];
6606 i
.op
[op
].disps
= exp
;
6607 exp
->X_op
= O_constant
;
6608 exp
->X_add_number
= 0;
6609 exp
->X_add_symbol
= (symbolS
*) 0;
6610 exp
->X_op_symbol
= (symbolS
*) 0;
6618 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6620 if (operand_type_check (i
.types
[0], imm
))
6621 i
.vex
.register_specifier
= NULL
;
6624 /* VEX.vvvv encodes one of the sources when the first
6625 operand is not an immediate. */
6626 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6627 i
.vex
.register_specifier
= i
.op
[0].regs
;
6629 i
.vex
.register_specifier
= i
.op
[1].regs
;
6632 /* Destination is a XMM register encoded in the ModRM.reg
6634 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6635 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6638 /* ModRM.rm and VEX.B encodes the other source. */
6639 if (!i
.mem_operands
)
6643 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6644 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6646 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6648 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6652 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6654 i
.vex
.register_specifier
= i
.op
[2].regs
;
6655 if (!i
.mem_operands
)
6658 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6659 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6663 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6664 (if any) based on i.tm.extension_opcode. Again, we must be
6665 careful to make sure that segment/control/debug/test/MMX
6666 registers are coded into the i.rm.reg field. */
6667 else if (i
.reg_operands
)
6670 unsigned int vex_reg
= ~0;
6672 for (op
= 0; op
< i
.operands
; op
++)
6673 if (i
.types
[op
].bitfield
.reg8
6674 || i
.types
[op
].bitfield
.reg16
6675 || i
.types
[op
].bitfield
.reg32
6676 || i
.types
[op
].bitfield
.reg64
6677 || i
.types
[op
].bitfield
.regmmx
6678 || i
.types
[op
].bitfield
.regxmm
6679 || i
.types
[op
].bitfield
.regymm
6680 || i
.types
[op
].bitfield
.regbnd
6681 || i
.types
[op
].bitfield
.regzmm
6682 || i
.types
[op
].bitfield
.regmask
6683 || i
.types
[op
].bitfield
.sreg2
6684 || i
.types
[op
].bitfield
.sreg3
6685 || i
.types
[op
].bitfield
.control
6686 || i
.types
[op
].bitfield
.debug
6687 || i
.types
[op
].bitfield
.test
)
6692 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6694 /* For instructions with VexNDS, the register-only
6695 source operand is encoded in VEX prefix. */
6696 gas_assert (mem
!= (unsigned int) ~0);
6701 gas_assert (op
< i
.operands
);
6705 /* Check register-only source operand when two source
6706 operands are swapped. */
6707 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6708 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6712 gas_assert (mem
== (vex_reg
+ 1)
6713 && op
< i
.operands
);
6718 gas_assert (vex_reg
< i
.operands
);
6722 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6724 /* For instructions with VexNDD, the register destination
6725 is encoded in VEX prefix. */
6726 if (i
.mem_operands
== 0)
6728 /* There is no memory operand. */
6729 gas_assert ((op
+ 2) == i
.operands
);
6734 /* There are only 2 operands. */
6735 gas_assert (op
< 2 && i
.operands
== 2);
6740 gas_assert (op
< i
.operands
);
6742 if (vex_reg
!= (unsigned int) ~0)
6744 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6746 if (type
->bitfield
.reg32
!= 1
6747 && type
->bitfield
.reg64
!= 1
6748 && !operand_type_equal (type
, ®xmm
)
6749 && !operand_type_equal (type
, ®ymm
)
6750 && !operand_type_equal (type
, ®zmm
)
6751 && !operand_type_equal (type
, ®mask
))
6754 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6757 /* Don't set OP operand twice. */
6760 /* If there is an extension opcode to put here, the
6761 register number must be put into the regmem field. */
6762 if (i
.tm
.extension_opcode
!= None
)
6764 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6765 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6767 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6772 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6773 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6775 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6780 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6781 must set it to 3 to indicate this is a register operand
6782 in the regmem field. */
6783 if (!i
.mem_operands
)
6787 /* Fill in i.rm.reg field with extension opcode (if any). */
6788 if (i
.tm
.extension_opcode
!= None
)
6789 i
.rm
.reg
= i
.tm
.extension_opcode
;
6795 output_branch (void)
6801 relax_substateT subtype
;
6805 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6806 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6809 if (i
.prefix
[DATA_PREFIX
] != 0)
6815 /* Pentium4 branch hints. */
6816 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6817 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6822 if (i
.prefix
[REX_PREFIX
] != 0)
6828 /* BND prefixed jump. */
6829 if (i
.prefix
[BND_PREFIX
] != 0)
6831 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6835 if (i
.prefixes
!= 0 && !intel_syntax
)
6836 as_warn (_("skipping prefixes on this instruction"));
6838 /* It's always a symbol; End frag & setup for relax.
6839 Make sure there is enough room in this frag for the largest
6840 instruction we may generate in md_convert_frag. This is 2
6841 bytes for the opcode and room for the prefix and largest
6843 frag_grow (prefix
+ 2 + 4);
6844 /* Prefix and 1 opcode byte go in fr_fix. */
6845 p
= frag_more (prefix
+ 1);
6846 if (i
.prefix
[DATA_PREFIX
] != 0)
6847 *p
++ = DATA_PREFIX_OPCODE
;
6848 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6849 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6850 *p
++ = i
.prefix
[SEG_PREFIX
];
6851 if (i
.prefix
[REX_PREFIX
] != 0)
6852 *p
++ = i
.prefix
[REX_PREFIX
];
6853 *p
= i
.tm
.base_opcode
;
6855 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6856 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6857 else if (cpu_arch_flags
.bitfield
.cpui386
)
6858 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6860 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6863 sym
= i
.op
[0].disps
->X_add_symbol
;
6864 off
= i
.op
[0].disps
->X_add_number
;
6866 if (i
.op
[0].disps
->X_op
!= O_constant
6867 && i
.op
[0].disps
->X_op
!= O_symbol
)
6869 /* Handle complex expressions. */
6870 sym
= make_expr_symbol (i
.op
[0].disps
);
6874 /* 1 possible extra opcode + 4 byte displacement go in var part.
6875 Pass reloc in fr_var. */
6876 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6886 if (i
.tm
.opcode_modifier
.jumpbyte
)
6888 /* This is a loop or jecxz type instruction. */
6890 if (i
.prefix
[ADDR_PREFIX
] != 0)
6892 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6895 /* Pentium4 branch hints. */
6896 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6897 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6899 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6908 if (flag_code
== CODE_16BIT
)
6911 if (i
.prefix
[DATA_PREFIX
] != 0)
6913 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6923 if (i
.prefix
[REX_PREFIX
] != 0)
6925 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6929 /* BND prefixed jump. */
6930 if (i
.prefix
[BND_PREFIX
] != 0)
6932 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6936 if (i
.prefixes
!= 0 && !intel_syntax
)
6937 as_warn (_("skipping prefixes on this instruction"));
6939 p
= frag_more (i
.tm
.opcode_length
+ size
);
6940 switch (i
.tm
.opcode_length
)
6943 *p
++ = i
.tm
.base_opcode
>> 8;
6945 *p
++ = i
.tm
.base_opcode
;
6951 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6952 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6954 /* All jumps handled here are signed, but don't use a signed limit
6955 check for 32 and 16 bit jumps as we want to allow wrap around at
6956 4G and 64k respectively. */
6958 fixP
->fx_signed
= 1;
6962 output_interseg_jump (void)
6970 if (flag_code
== CODE_16BIT
)
6974 if (i
.prefix
[DATA_PREFIX
] != 0)
6980 if (i
.prefix
[REX_PREFIX
] != 0)
6990 if (i
.prefixes
!= 0 && !intel_syntax
)
6991 as_warn (_("skipping prefixes on this instruction"));
6993 /* 1 opcode; 2 segment; offset */
6994 p
= frag_more (prefix
+ 1 + 2 + size
);
6996 if (i
.prefix
[DATA_PREFIX
] != 0)
6997 *p
++ = DATA_PREFIX_OPCODE
;
6999 if (i
.prefix
[REX_PREFIX
] != 0)
7000 *p
++ = i
.prefix
[REX_PREFIX
];
7002 *p
++ = i
.tm
.base_opcode
;
7003 if (i
.op
[1].imms
->X_op
== O_constant
)
7005 offsetT n
= i
.op
[1].imms
->X_add_number
;
7008 && !fits_in_unsigned_word (n
)
7009 && !fits_in_signed_word (n
))
7011 as_bad (_("16-bit jump out of range"));
7014 md_number_to_chars (p
, n
, size
);
7017 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7018 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7019 if (i
.op
[0].imms
->X_op
!= O_constant
)
7020 as_bad (_("can't handle non absolute segment in `%s'"),
7022 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7028 fragS
*insn_start_frag
;
7029 offsetT insn_start_off
;
7031 /* Tie dwarf2 debug info to the address at the start of the insn.
7032 We can't do this after the insn has been output as the current
7033 frag may have been closed off. eg. by frag_var. */
7034 dwarf2_emit_insn (0);
7036 insn_start_frag
= frag_now
;
7037 insn_start_off
= frag_now_fix ();
7040 if (i
.tm
.opcode_modifier
.jump
)
7042 else if (i
.tm
.opcode_modifier
.jumpbyte
7043 || i
.tm
.opcode_modifier
.jumpdword
)
7045 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7046 output_interseg_jump ();
7049 /* Output normal instructions here. */
7053 unsigned int prefix
;
7056 && i
.tm
.base_opcode
== 0xfae
7058 && i
.imm_operands
== 1
7059 && (i
.op
[0].imms
->X_add_number
== 0xe8
7060 || i
.op
[0].imms
->X_add_number
== 0xf0
7061 || i
.op
[0].imms
->X_add_number
== 0xf8))
7063 /* Encode lfence, mfence, and sfence as
7064 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7065 offsetT val
= 0x240483f0ULL
;
7067 md_number_to_chars (p
, val
, 5);
7071 /* Some processors fail on LOCK prefix. This options makes
7072 assembler ignore LOCK prefix and serves as a workaround. */
7073 if (omit_lock_prefix
)
7075 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7077 i
.prefix
[LOCK_PREFIX
] = 0;
7080 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7081 don't need the explicit prefix. */
7082 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7084 switch (i
.tm
.opcode_length
)
7087 if (i
.tm
.base_opcode
& 0xff000000)
7089 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7094 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7096 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7097 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7100 if (prefix
!= REPE_PREFIX_OPCODE
7101 || (i
.prefix
[REP_PREFIX
]
7102 != REPE_PREFIX_OPCODE
))
7103 add_prefix (prefix
);
7106 add_prefix (prefix
);
7115 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7116 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7117 R_X86_64_GOTTPOFF relocation so that linker can safely
7118 perform IE->LE optimization. */
7119 if (x86_elf_abi
== X86_64_X32_ABI
7121 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7122 && i
.prefix
[REX_PREFIX
] == 0)
7123 add_prefix (REX_OPCODE
);
7126 /* The prefix bytes. */
7127 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7129 FRAG_APPEND_1_CHAR (*q
);
7133 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7138 /* REX byte is encoded in VEX prefix. */
7142 FRAG_APPEND_1_CHAR (*q
);
7145 /* There should be no other prefixes for instructions
7150 /* For EVEX instructions i.vrex should become 0 after
7151 build_evex_prefix. For VEX instructions upper 16 registers
7152 aren't available, so VREX should be 0. */
7155 /* Now the VEX prefix. */
7156 p
= frag_more (i
.vex
.length
);
7157 for (j
= 0; j
< i
.vex
.length
; j
++)
7158 p
[j
] = i
.vex
.bytes
[j
];
7161 /* Now the opcode; be careful about word order here! */
7162 if (i
.tm
.opcode_length
== 1)
7164 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7168 switch (i
.tm
.opcode_length
)
7172 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7173 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7177 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7187 /* Put out high byte first: can't use md_number_to_chars! */
7188 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7189 *p
= i
.tm
.base_opcode
& 0xff;
7192 /* Now the modrm byte and sib byte (if present). */
7193 if (i
.tm
.opcode_modifier
.modrm
)
7195 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7198 /* If i.rm.regmem == ESP (4)
7199 && i.rm.mode != (Register mode)
7201 ==> need second modrm byte. */
7202 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7204 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7205 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7207 | i
.sib
.scale
<< 6));
7210 if (i
.disp_operands
)
7211 output_disp (insn_start_frag
, insn_start_off
);
7214 output_imm (insn_start_frag
, insn_start_off
);
7220 pi ("" /*line*/, &i
);
7222 #endif /* DEBUG386 */
7225 /* Return the size of the displacement operand N. */
7228 disp_size (unsigned int n
)
7232 /* Vec_Disp8 has to be 8bit. */
7233 if (i
.types
[n
].bitfield
.vec_disp8
)
7235 else if (i
.types
[n
].bitfield
.disp64
)
7237 else if (i
.types
[n
].bitfield
.disp8
)
7239 else if (i
.types
[n
].bitfield
.disp16
)
7244 /* Return the size of the immediate operand N. */
7247 imm_size (unsigned int n
)
7250 if (i
.types
[n
].bitfield
.imm64
)
7252 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7254 else if (i
.types
[n
].bitfield
.imm16
)
7260 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7265 for (n
= 0; n
< i
.operands
; n
++)
7267 if (i
.types
[n
].bitfield
.vec_disp8
7268 || operand_type_check (i
.types
[n
], disp
))
7270 if (i
.op
[n
].disps
->X_op
== O_constant
)
7272 int size
= disp_size (n
);
7273 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7275 if (i
.types
[n
].bitfield
.vec_disp8
)
7277 val
= offset_in_range (val
, size
);
7278 p
= frag_more (size
);
7279 md_number_to_chars (p
, val
, size
);
7283 enum bfd_reloc_code_real reloc_type
;
7284 int size
= disp_size (n
);
7285 int sign
= i
.types
[n
].bitfield
.disp32s
;
7286 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7289 /* We can't have 8 bit displacement here. */
7290 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7292 /* The PC relative address is computed relative
7293 to the instruction boundary, so in case immediate
7294 fields follows, we need to adjust the value. */
7295 if (pcrel
&& i
.imm_operands
)
7300 for (n1
= 0; n1
< i
.operands
; n1
++)
7301 if (operand_type_check (i
.types
[n1
], imm
))
7303 /* Only one immediate is allowed for PC
7304 relative address. */
7305 gas_assert (sz
== 0);
7307 i
.op
[n
].disps
->X_add_number
-= sz
;
7309 /* We should find the immediate. */
7310 gas_assert (sz
!= 0);
7313 p
= frag_more (size
);
7314 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7316 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7317 && (((reloc_type
== BFD_RELOC_32
7318 || reloc_type
== BFD_RELOC_X86_64_32S
7319 || (reloc_type
== BFD_RELOC_64
7321 && (i
.op
[n
].disps
->X_op
== O_symbol
7322 || (i
.op
[n
].disps
->X_op
== O_add
7323 && ((symbol_get_value_expression
7324 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7326 || reloc_type
== BFD_RELOC_32_PCREL
))
7330 if (insn_start_frag
== frag_now
)
7331 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7336 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7337 for (fr
= insn_start_frag
->fr_next
;
7338 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7340 add
+= p
- frag_now
->fr_literal
;
7345 reloc_type
= BFD_RELOC_386_GOTPC
;
7346 i
.op
[n
].imms
->X_add_number
+= add
;
7348 else if (reloc_type
== BFD_RELOC_64
)
7349 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7351 /* Don't do the adjustment for x86-64, as there
7352 the pcrel addressing is relative to the _next_
7353 insn, and that is taken care of in other code. */
7354 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7356 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7357 size
, i
.op
[n
].disps
, pcrel
,
7359 /* Check for "call/jmp *mem", "mov mem, %reg",
7360 "test %reg, mem" and "binop mem, %reg" where binop
7361 is one of adc, add, and, cmp, or, sbb, sub, xor
7362 instructions. Always generate R_386_GOT32X for
7363 "sym*GOT" operand in 32-bit mode. */
7364 if ((generate_relax_relocations
7367 && i
.rm
.regmem
== 5))
7369 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7370 && ((i
.operands
== 1
7371 && i
.tm
.base_opcode
== 0xff
7372 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7374 && (i
.tm
.base_opcode
== 0x8b
7375 || i
.tm
.base_opcode
== 0x85
7376 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7380 fixP
->fx_tcbit
= i
.rex
!= 0;
7382 && (i
.base_reg
->reg_num
== RegRip
7383 || i
.base_reg
->reg_num
== RegEip
))
7384 fixP
->fx_tcbit2
= 1;
7387 fixP
->fx_tcbit2
= 1;
7395 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7400 for (n
= 0; n
< i
.operands
; n
++)
7402 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7403 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7406 if (operand_type_check (i
.types
[n
], imm
))
7408 if (i
.op
[n
].imms
->X_op
== O_constant
)
7410 int size
= imm_size (n
);
7413 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7415 p
= frag_more (size
);
7416 md_number_to_chars (p
, val
, size
);
7420 /* Not absolute_section.
7421 Need a 32-bit fixup (don't support 8bit
7422 non-absolute imms). Try to support other
7424 enum bfd_reloc_code_real reloc_type
;
7425 int size
= imm_size (n
);
7428 if (i
.types
[n
].bitfield
.imm32s
7429 && (i
.suffix
== QWORD_MNEM_SUFFIX
7430 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7435 p
= frag_more (size
);
7436 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7438 /* This is tough to explain. We end up with this one if we
7439 * have operands that look like
7440 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7441 * obtain the absolute address of the GOT, and it is strongly
7442 * preferable from a performance point of view to avoid using
7443 * a runtime relocation for this. The actual sequence of
7444 * instructions often look something like:
7449 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7451 * The call and pop essentially return the absolute address
7452 * of the label .L66 and store it in %ebx. The linker itself
7453 * will ultimately change the first operand of the addl so
7454 * that %ebx points to the GOT, but to keep things simple, the
7455 * .o file must have this operand set so that it generates not
7456 * the absolute address of .L66, but the absolute address of
7457 * itself. This allows the linker itself simply treat a GOTPC
7458 * relocation as asking for a pcrel offset to the GOT to be
7459 * added in, and the addend of the relocation is stored in the
7460 * operand field for the instruction itself.
7462 * Our job here is to fix the operand so that it would add
7463 * the correct offset so that %ebx would point to itself. The
7464 * thing that is tricky is that .-.L66 will point to the
7465 * beginning of the instruction, so we need to further modify
7466 * the operand so that it will point to itself. There are
7467 * other cases where you have something like:
7469 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7471 * and here no correction would be required. Internally in
7472 * the assembler we treat operands of this form as not being
7473 * pcrel since the '.' is explicitly mentioned, and I wonder
7474 * whether it would simplify matters to do it this way. Who
7475 * knows. In earlier versions of the PIC patches, the
7476 * pcrel_adjust field was used to store the correction, but
7477 * since the expression is not pcrel, I felt it would be
7478 * confusing to do it this way. */
7480 if ((reloc_type
== BFD_RELOC_32
7481 || reloc_type
== BFD_RELOC_X86_64_32S
7482 || reloc_type
== BFD_RELOC_64
)
7484 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7485 && (i
.op
[n
].imms
->X_op
== O_symbol
7486 || (i
.op
[n
].imms
->X_op
== O_add
7487 && ((symbol_get_value_expression
7488 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7493 if (insn_start_frag
== frag_now
)
7494 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7499 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7500 for (fr
= insn_start_frag
->fr_next
;
7501 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7503 add
+= p
- frag_now
->fr_literal
;
7507 reloc_type
= BFD_RELOC_386_GOTPC
;
7509 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7511 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7512 i
.op
[n
].imms
->X_add_number
+= add
;
7514 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7515 i
.op
[n
].imms
, 0, reloc_type
);
7521 /* x86_cons_fix_new is called via the expression parsing code when a
7522 reloc is needed. We use this hook to get the correct .got reloc. */
7523 static int cons_sign
= -1;
7526 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7527 expressionS
*exp
, bfd_reloc_code_real_type r
)
7529 r
= reloc (len
, 0, cons_sign
, r
);
7532 if (exp
->X_op
== O_secrel
)
7534 exp
->X_op
= O_symbol
;
7535 r
= BFD_RELOC_32_SECREL
;
7539 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7542 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7543 purpose of the `.dc.a' internal pseudo-op. */
7546 x86_address_bytes (void)
7548 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7550 return stdoutput
->arch_info
->bits_per_address
/ 8;
7553 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7555 # define lex_got(reloc, adjust, types) NULL
7557 /* Parse operands of the form
7558 <symbol>@GOTOFF+<nnn>
7559 and similar .plt or .got references.
7561 If we find one, set up the correct relocation in RELOC and copy the
7562 input string, minus the `@GOTOFF' into a malloc'd buffer for
7563 parsing by the calling routine. Return this buffer, and if ADJUST
7564 is non-null set it to the length of the string we removed from the
7565 input line. Otherwise return NULL. */
7567 lex_got (enum bfd_reloc_code_real
*rel
,
7569 i386_operand_type
*types
)
7571 /* Some of the relocations depend on the size of what field is to
7572 be relocated. But in our callers i386_immediate and i386_displacement
7573 we don't yet know the operand size (this will be set by insn
7574 matching). Hence we record the word32 relocation here,
7575 and adjust the reloc according to the real size in reloc(). */
7576 static const struct {
7579 const enum bfd_reloc_code_real rel
[2];
7580 const i386_operand_type types64
;
7582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7583 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7585 OPERAND_TYPE_IMM32_64
},
7587 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7588 BFD_RELOC_X86_64_PLTOFF64
},
7589 OPERAND_TYPE_IMM64
},
7590 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7591 BFD_RELOC_X86_64_PLT32
},
7592 OPERAND_TYPE_IMM32_32S_DISP32
},
7593 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7594 BFD_RELOC_X86_64_GOTPLT64
},
7595 OPERAND_TYPE_IMM64_DISP64
},
7596 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7597 BFD_RELOC_X86_64_GOTOFF64
},
7598 OPERAND_TYPE_IMM64_DISP64
},
7599 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7600 BFD_RELOC_X86_64_GOTPCREL
},
7601 OPERAND_TYPE_IMM32_32S_DISP32
},
7602 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7603 BFD_RELOC_X86_64_TLSGD
},
7604 OPERAND_TYPE_IMM32_32S_DISP32
},
7605 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7606 _dummy_first_bfd_reloc_code_real
},
7607 OPERAND_TYPE_NONE
},
7608 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7609 BFD_RELOC_X86_64_TLSLD
},
7610 OPERAND_TYPE_IMM32_32S_DISP32
},
7611 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7612 BFD_RELOC_X86_64_GOTTPOFF
},
7613 OPERAND_TYPE_IMM32_32S_DISP32
},
7614 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7615 BFD_RELOC_X86_64_TPOFF32
},
7616 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7617 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7618 _dummy_first_bfd_reloc_code_real
},
7619 OPERAND_TYPE_NONE
},
7620 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7621 BFD_RELOC_X86_64_DTPOFF32
},
7622 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7623 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7624 _dummy_first_bfd_reloc_code_real
},
7625 OPERAND_TYPE_NONE
},
7626 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7627 _dummy_first_bfd_reloc_code_real
},
7628 OPERAND_TYPE_NONE
},
7629 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7630 BFD_RELOC_X86_64_GOT32
},
7631 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7632 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7633 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7634 OPERAND_TYPE_IMM32_32S_DISP32
},
7635 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7636 BFD_RELOC_X86_64_TLSDESC_CALL
},
7637 OPERAND_TYPE_IMM32_32S_DISP32
},
7642 #if defined (OBJ_MAYBE_ELF)
7647 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7648 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7651 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7653 int len
= gotrel
[j
].len
;
7654 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7656 if (gotrel
[j
].rel
[object_64bit
] != 0)
7659 char *tmpbuf
, *past_reloc
;
7661 *rel
= gotrel
[j
].rel
[object_64bit
];
7665 if (flag_code
!= CODE_64BIT
)
7667 types
->bitfield
.imm32
= 1;
7668 types
->bitfield
.disp32
= 1;
7671 *types
= gotrel
[j
].types64
;
7674 if (j
!= 0 && GOT_symbol
== NULL
)
7675 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7677 /* The length of the first part of our input line. */
7678 first
= cp
- input_line_pointer
;
7680 /* The second part goes from after the reloc token until
7681 (and including) an end_of_line char or comma. */
7682 past_reloc
= cp
+ 1 + len
;
7684 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7686 second
= cp
+ 1 - past_reloc
;
7688 /* Allocate and copy string. The trailing NUL shouldn't
7689 be necessary, but be safe. */
7690 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7691 memcpy (tmpbuf
, input_line_pointer
, first
);
7692 if (second
!= 0 && *past_reloc
!= ' ')
7693 /* Replace the relocation token with ' ', so that
7694 errors like foo@GOTOFF1 will be detected. */
7695 tmpbuf
[first
++] = ' ';
7697 /* Increment length by 1 if the relocation token is
7702 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7703 tmpbuf
[first
+ second
] = '\0';
7707 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7708 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7713 /* Might be a symbol version string. Don't as_bad here. */
7722 /* Parse operands of the form
7723 <symbol>@SECREL32+<nnn>
7725 If we find one, set up the correct relocation in RELOC and copy the
7726 input string, minus the `@SECREL32' into a malloc'd buffer for
7727 parsing by the calling routine. Return this buffer, and if ADJUST
7728 is non-null set it to the length of the string we removed from the
7729 input line. Otherwise return NULL.
7731 This function is copied from the ELF version above adjusted for PE targets. */
7734 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7735 int *adjust ATTRIBUTE_UNUSED
,
7736 i386_operand_type
*types
)
7742 const enum bfd_reloc_code_real rel
[2];
7743 const i386_operand_type types64
;
7747 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7748 BFD_RELOC_32_SECREL
},
7749 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7755 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7756 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7759 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7761 int len
= gotrel
[j
].len
;
7763 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7765 if (gotrel
[j
].rel
[object_64bit
] != 0)
7768 char *tmpbuf
, *past_reloc
;
7770 *rel
= gotrel
[j
].rel
[object_64bit
];
7776 if (flag_code
!= CODE_64BIT
)
7778 types
->bitfield
.imm32
= 1;
7779 types
->bitfield
.disp32
= 1;
7782 *types
= gotrel
[j
].types64
;
7785 /* The length of the first part of our input line. */
7786 first
= cp
- input_line_pointer
;
7788 /* The second part goes from after the reloc token until
7789 (and including) an end_of_line char or comma. */
7790 past_reloc
= cp
+ 1 + len
;
7792 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7794 second
= cp
+ 1 - past_reloc
;
7796 /* Allocate and copy string. The trailing NUL shouldn't
7797 be necessary, but be safe. */
7798 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7799 memcpy (tmpbuf
, input_line_pointer
, first
);
7800 if (second
!= 0 && *past_reloc
!= ' ')
7801 /* Replace the relocation token with ' ', so that
7802 errors like foo@SECLREL321 will be detected. */
7803 tmpbuf
[first
++] = ' ';
7804 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7805 tmpbuf
[first
+ second
] = '\0';
7809 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7810 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7815 /* Might be a symbol version string. Don't as_bad here. */
7821 bfd_reloc_code_real_type
7822 x86_cons (expressionS
*exp
, int size
)
7824 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7826 intel_syntax
= -intel_syntax
;
7829 if (size
== 4 || (object_64bit
&& size
== 8))
7831 /* Handle @GOTOFF and the like in an expression. */
7833 char *gotfree_input_line
;
7836 save
= input_line_pointer
;
7837 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7838 if (gotfree_input_line
)
7839 input_line_pointer
= gotfree_input_line
;
7843 if (gotfree_input_line
)
7845 /* expression () has merrily parsed up to the end of line,
7846 or a comma - in the wrong buffer. Transfer how far
7847 input_line_pointer has moved to the right buffer. */
7848 input_line_pointer
= (save
7849 + (input_line_pointer
- gotfree_input_line
)
7851 free (gotfree_input_line
);
7852 if (exp
->X_op
== O_constant
7853 || exp
->X_op
== O_absent
7854 || exp
->X_op
== O_illegal
7855 || exp
->X_op
== O_register
7856 || exp
->X_op
== O_big
)
7858 char c
= *input_line_pointer
;
7859 *input_line_pointer
= 0;
7860 as_bad (_("missing or invalid expression `%s'"), save
);
7861 *input_line_pointer
= c
;
7868 intel_syntax
= -intel_syntax
;
7871 i386_intel_simplify (exp
);
7877 signed_cons (int size
)
7879 if (flag_code
== CODE_64BIT
)
7887 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7894 if (exp
.X_op
== O_symbol
)
7895 exp
.X_op
= O_secrel
;
7897 emit_expr (&exp
, 4);
7899 while (*input_line_pointer
++ == ',');
7901 input_line_pointer
--;
7902 demand_empty_rest_of_line ();
7906 /* Handle Vector operations. */
7909 check_VecOperations (char *op_string
, char *op_end
)
7911 const reg_entry
*mask
;
7916 && (op_end
== NULL
|| op_string
< op_end
))
7919 if (*op_string
== '{')
7923 /* Check broadcasts. */
7924 if (strncmp (op_string
, "1to", 3) == 0)
7929 goto duplicated_vec_op
;
7932 if (*op_string
== '8')
7933 bcst_type
= BROADCAST_1TO8
;
7934 else if (*op_string
== '4')
7935 bcst_type
= BROADCAST_1TO4
;
7936 else if (*op_string
== '2')
7937 bcst_type
= BROADCAST_1TO2
;
7938 else if (*op_string
== '1'
7939 && *(op_string
+1) == '6')
7941 bcst_type
= BROADCAST_1TO16
;
7946 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7951 broadcast_op
.type
= bcst_type
;
7952 broadcast_op
.operand
= this_operand
;
7953 i
.broadcast
= &broadcast_op
;
7955 /* Check masking operation. */
7956 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7958 /* k0 can't be used for write mask. */
7959 if (mask
->reg_num
== 0)
7961 as_bad (_("`%s' can't be used for write mask"),
7968 mask_op
.mask
= mask
;
7969 mask_op
.zeroing
= 0;
7970 mask_op
.operand
= this_operand
;
7976 goto duplicated_vec_op
;
7978 i
.mask
->mask
= mask
;
7980 /* Only "{z}" is allowed here. No need to check
7981 zeroing mask explicitly. */
7982 if (i
.mask
->operand
!= this_operand
)
7984 as_bad (_("invalid write mask `%s'"), saved
);
7991 /* Check zeroing-flag for masking operation. */
7992 else if (*op_string
== 'z')
7996 mask_op
.mask
= NULL
;
7997 mask_op
.zeroing
= 1;
7998 mask_op
.operand
= this_operand
;
8003 if (i
.mask
->zeroing
)
8006 as_bad (_("duplicated `%s'"), saved
);
8010 i
.mask
->zeroing
= 1;
8012 /* Only "{%k}" is allowed here. No need to check mask
8013 register explicitly. */
8014 if (i
.mask
->operand
!= this_operand
)
8016 as_bad (_("invalid zeroing-masking `%s'"),
8025 goto unknown_vec_op
;
8027 if (*op_string
!= '}')
8029 as_bad (_("missing `}' in `%s'"), saved
);
8036 /* We don't know this one. */
8037 as_bad (_("unknown vector operation: `%s'"), saved
);
8045 i386_immediate (char *imm_start
)
8047 char *save_input_line_pointer
;
8048 char *gotfree_input_line
;
8051 i386_operand_type types
;
8053 operand_type_set (&types
, ~0);
8055 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8057 as_bad (_("at most %d immediate operands are allowed"),
8058 MAX_IMMEDIATE_OPERANDS
);
8062 exp
= &im_expressions
[i
.imm_operands
++];
8063 i
.op
[this_operand
].imms
= exp
;
8065 if (is_space_char (*imm_start
))
8068 save_input_line_pointer
= input_line_pointer
;
8069 input_line_pointer
= imm_start
;
8071 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8072 if (gotfree_input_line
)
8073 input_line_pointer
= gotfree_input_line
;
8075 exp_seg
= expression (exp
);
8079 /* Handle vector operations. */
8080 if (*input_line_pointer
== '{')
8082 input_line_pointer
= check_VecOperations (input_line_pointer
,
8084 if (input_line_pointer
== NULL
)
8088 if (*input_line_pointer
)
8089 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8091 input_line_pointer
= save_input_line_pointer
;
8092 if (gotfree_input_line
)
8094 free (gotfree_input_line
);
8096 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8097 exp
->X_op
= O_illegal
;
8100 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8104 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8105 i386_operand_type types
, const char *imm_start
)
8107 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8110 as_bad (_("missing or invalid immediate expression `%s'"),
8114 else if (exp
->X_op
== O_constant
)
8116 /* Size it properly later. */
8117 i
.types
[this_operand
].bitfield
.imm64
= 1;
8118 /* If not 64bit, sign extend val. */
8119 if (flag_code
!= CODE_64BIT
8120 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8122 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8124 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8125 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8126 && exp_seg
!= absolute_section
8127 && exp_seg
!= text_section
8128 && exp_seg
!= data_section
8129 && exp_seg
!= bss_section
8130 && exp_seg
!= undefined_section
8131 && !bfd_is_com_section (exp_seg
))
8133 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8137 else if (!intel_syntax
&& exp_seg
== reg_section
)
8140 as_bad (_("illegal immediate register operand %s"), imm_start
);
8145 /* This is an address. The size of the address will be
8146 determined later, depending on destination register,
8147 suffix, or the default for the section. */
8148 i
.types
[this_operand
].bitfield
.imm8
= 1;
8149 i
.types
[this_operand
].bitfield
.imm16
= 1;
8150 i
.types
[this_operand
].bitfield
.imm32
= 1;
8151 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8152 i
.types
[this_operand
].bitfield
.imm64
= 1;
8153 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8161 i386_scale (char *scale
)
8164 char *save
= input_line_pointer
;
8166 input_line_pointer
= scale
;
8167 val
= get_absolute_expression ();
8172 i
.log2_scale_factor
= 0;
8175 i
.log2_scale_factor
= 1;
8178 i
.log2_scale_factor
= 2;
8181 i
.log2_scale_factor
= 3;
8185 char sep
= *input_line_pointer
;
8187 *input_line_pointer
= '\0';
8188 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8190 *input_line_pointer
= sep
;
8191 input_line_pointer
= save
;
8195 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8197 as_warn (_("scale factor of %d without an index register"),
8198 1 << i
.log2_scale_factor
);
8199 i
.log2_scale_factor
= 0;
8201 scale
= input_line_pointer
;
8202 input_line_pointer
= save
;
8207 i386_displacement (char *disp_start
, char *disp_end
)
8211 char *save_input_line_pointer
;
8212 char *gotfree_input_line
;
8214 i386_operand_type bigdisp
, types
= anydisp
;
8217 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8219 as_bad (_("at most %d displacement operands are allowed"),
8220 MAX_MEMORY_OPERANDS
);
8224 operand_type_set (&bigdisp
, 0);
8225 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8226 || (!current_templates
->start
->opcode_modifier
.jump
8227 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8229 bigdisp
.bitfield
.disp32
= 1;
8230 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8231 if (flag_code
== CODE_64BIT
)
8235 bigdisp
.bitfield
.disp32s
= 1;
8236 bigdisp
.bitfield
.disp64
= 1;
8239 else if ((flag_code
== CODE_16BIT
) ^ override
)
8241 bigdisp
.bitfield
.disp32
= 0;
8242 bigdisp
.bitfield
.disp16
= 1;
8247 /* For PC-relative branches, the width of the displacement
8248 is dependent upon data size, not address size. */
8249 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8250 if (flag_code
== CODE_64BIT
)
8252 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8253 bigdisp
.bitfield
.disp16
= 1;
8256 bigdisp
.bitfield
.disp32
= 1;
8257 bigdisp
.bitfield
.disp32s
= 1;
8263 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8265 : LONG_MNEM_SUFFIX
));
8266 bigdisp
.bitfield
.disp32
= 1;
8267 if ((flag_code
== CODE_16BIT
) ^ override
)
8269 bigdisp
.bitfield
.disp32
= 0;
8270 bigdisp
.bitfield
.disp16
= 1;
8274 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8277 exp
= &disp_expressions
[i
.disp_operands
];
8278 i
.op
[this_operand
].disps
= exp
;
8280 save_input_line_pointer
= input_line_pointer
;
8281 input_line_pointer
= disp_start
;
8282 END_STRING_AND_SAVE (disp_end
);
8284 #ifndef GCC_ASM_O_HACK
8285 #define GCC_ASM_O_HACK 0
8288 END_STRING_AND_SAVE (disp_end
+ 1);
8289 if (i
.types
[this_operand
].bitfield
.baseIndex
8290 && displacement_string_end
[-1] == '+')
8292 /* This hack is to avoid a warning when using the "o"
8293 constraint within gcc asm statements.
8296 #define _set_tssldt_desc(n,addr,limit,type) \
8297 __asm__ __volatile__ ( \
8299 "movw %w1,2+%0\n\t" \
8301 "movb %b1,4+%0\n\t" \
8302 "movb %4,5+%0\n\t" \
8303 "movb $0,6+%0\n\t" \
8304 "movb %h1,7+%0\n\t" \
8306 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8308 This works great except that the output assembler ends
8309 up looking a bit weird if it turns out that there is
8310 no offset. You end up producing code that looks like:
8323 So here we provide the missing zero. */
8325 *displacement_string_end
= '0';
8328 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8329 if (gotfree_input_line
)
8330 input_line_pointer
= gotfree_input_line
;
8332 exp_seg
= expression (exp
);
8335 if (*input_line_pointer
)
8336 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8338 RESTORE_END_STRING (disp_end
+ 1);
8340 input_line_pointer
= save_input_line_pointer
;
8341 if (gotfree_input_line
)
8343 free (gotfree_input_line
);
8345 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8346 exp
->X_op
= O_illegal
;
8349 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8351 RESTORE_END_STRING (disp_end
);
8357 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8358 i386_operand_type types
, const char *disp_start
)
8360 i386_operand_type bigdisp
;
8363 /* We do this to make sure that the section symbol is in
8364 the symbol table. We will ultimately change the relocation
8365 to be relative to the beginning of the section. */
8366 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8367 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8368 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8370 if (exp
->X_op
!= O_symbol
)
8373 if (S_IS_LOCAL (exp
->X_add_symbol
)
8374 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8375 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8376 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8377 exp
->X_op
= O_subtract
;
8378 exp
->X_op_symbol
= GOT_symbol
;
8379 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8380 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8381 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8382 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8384 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8387 else if (exp
->X_op
== O_absent
8388 || exp
->X_op
== O_illegal
8389 || exp
->X_op
== O_big
)
8392 as_bad (_("missing or invalid displacement expression `%s'"),
8397 else if (flag_code
== CODE_64BIT
8398 && !i
.prefix
[ADDR_PREFIX
]
8399 && exp
->X_op
== O_constant
)
8401 /* Since displacement is signed extended to 64bit, don't allow
8402 disp32 and turn off disp32s if they are out of range. */
8403 i
.types
[this_operand
].bitfield
.disp32
= 0;
8404 if (!fits_in_signed_long (exp
->X_add_number
))
8406 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8407 if (i
.types
[this_operand
].bitfield
.baseindex
)
8409 as_bad (_("0x%lx out range of signed 32bit displacement"),
8410 (long) exp
->X_add_number
);
8416 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8417 else if (exp
->X_op
!= O_constant
8418 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8419 && exp_seg
!= absolute_section
8420 && exp_seg
!= text_section
8421 && exp_seg
!= data_section
8422 && exp_seg
!= bss_section
8423 && exp_seg
!= undefined_section
8424 && !bfd_is_com_section (exp_seg
))
8426 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8431 /* Check if this is a displacement only operand. */
8432 bigdisp
= i
.types
[this_operand
];
8433 bigdisp
.bitfield
.disp8
= 0;
8434 bigdisp
.bitfield
.disp16
= 0;
8435 bigdisp
.bitfield
.disp32
= 0;
8436 bigdisp
.bitfield
.disp32s
= 0;
8437 bigdisp
.bitfield
.disp64
= 0;
8438 if (operand_type_all_zero (&bigdisp
))
8439 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8445 /* Make sure the memory operand we've been dealt is valid.
8446 Return 1 on success, 0 on a failure. */
8449 i386_index_check (const char *operand_string
)
8451 const char *kind
= "base/index";
8452 enum flag_code addr_mode
;
8454 if (i
.prefix
[ADDR_PREFIX
])
8455 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8458 addr_mode
= flag_code
;
8460 #if INFER_ADDR_PREFIX
8461 if (i
.mem_operands
== 0)
8463 /* Infer address prefix from the first memory operand. */
8464 const reg_entry
*addr_reg
= i
.base_reg
;
8466 if (addr_reg
== NULL
)
8467 addr_reg
= i
.index_reg
;
8471 if (addr_reg
->reg_num
== RegEip
8472 || addr_reg
->reg_num
== RegEiz
8473 || addr_reg
->reg_type
.bitfield
.reg32
)
8474 addr_mode
= CODE_32BIT
;
8475 else if (flag_code
!= CODE_64BIT
8476 && addr_reg
->reg_type
.bitfield
.reg16
)
8477 addr_mode
= CODE_16BIT
;
8479 if (addr_mode
!= flag_code
)
8481 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8483 /* Change the size of any displacement too. At most one
8484 of Disp16 or Disp32 is set.
8485 FIXME. There doesn't seem to be any real need for
8486 separate Disp16 and Disp32 flags. The same goes for
8487 Imm16 and Imm32. Removing them would probably clean
8488 up the code quite a lot. */
8489 if (flag_code
!= CODE_64BIT
8490 && (i
.types
[this_operand
].bitfield
.disp16
8491 || i
.types
[this_operand
].bitfield
.disp32
))
8492 i
.types
[this_operand
]
8493 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8500 if (current_templates
->start
->opcode_modifier
.isstring
8501 && !current_templates
->start
->opcode_modifier
.immext
8502 && (current_templates
->end
[-1].opcode_modifier
.isstring
8505 /* Memory operands of string insns are special in that they only allow
8506 a single register (rDI, rSI, or rBX) as their memory address. */
8507 const reg_entry
*expected_reg
;
8508 static const char *di_si
[][2] =
8514 static const char *bx
[] = { "ebx", "bx", "rbx" };
8516 kind
= "string address";
8518 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8520 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8522 if (!type
.bitfield
.baseindex
8523 || ((!i
.mem_operands
!= !intel_syntax
)
8524 && current_templates
->end
[-1].operand_types
[1]
8525 .bitfield
.baseindex
))
8526 type
= current_templates
->end
[-1].operand_types
[1];
8527 expected_reg
= hash_find (reg_hash
,
8528 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8532 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8534 if (i
.base_reg
!= expected_reg
8536 || operand_type_check (i
.types
[this_operand
], disp
))
8538 /* The second memory operand must have the same size as
8542 && !((addr_mode
== CODE_64BIT
8543 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8544 || (addr_mode
== CODE_32BIT
8545 ? i
.base_reg
->reg_type
.bitfield
.reg32
8546 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8549 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8551 intel_syntax
? '[' : '(',
8553 expected_reg
->reg_name
,
8554 intel_syntax
? ']' : ')');
8561 as_bad (_("`%s' is not a valid %s expression"),
8562 operand_string
, kind
);
8567 if (addr_mode
!= CODE_16BIT
)
8569 /* 32-bit/64-bit checks. */
8571 && (addr_mode
== CODE_64BIT
8572 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8573 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8575 || (i
.base_reg
->reg_num
8576 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8578 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8579 && !i
.index_reg
->reg_type
.bitfield
.regymm
8580 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8581 && ((addr_mode
== CODE_64BIT
8582 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8583 || i
.index_reg
->reg_num
== RegRiz
)
8584 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8585 || i
.index_reg
->reg_num
== RegEiz
))
8586 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8591 /* 16-bit checks. */
8593 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8594 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8596 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8597 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8599 && i
.base_reg
->reg_num
< 6
8600 && i
.index_reg
->reg_num
>= 6
8601 && i
.log2_scale_factor
== 0))))
8608 /* Handle vector immediates. */
8611 RC_SAE_immediate (const char *imm_start
)
8613 unsigned int match_found
, j
;
8614 const char *pstr
= imm_start
;
8622 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8624 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8628 rc_op
.type
= RC_NamesTable
[j
].type
;
8629 rc_op
.operand
= this_operand
;
8630 i
.rounding
= &rc_op
;
8634 as_bad (_("duplicated `%s'"), imm_start
);
8637 pstr
+= RC_NamesTable
[j
].len
;
8647 as_bad (_("Missing '}': '%s'"), imm_start
);
8650 /* RC/SAE immediate string should contain nothing more. */;
8653 as_bad (_("Junk after '}': '%s'"), imm_start
);
8657 exp
= &im_expressions
[i
.imm_operands
++];
8658 i
.op
[this_operand
].imms
= exp
;
8660 exp
->X_op
= O_constant
;
8661 exp
->X_add_number
= 0;
8662 exp
->X_add_symbol
= (symbolS
*) 0;
8663 exp
->X_op_symbol
= (symbolS
*) 0;
8665 i
.types
[this_operand
].bitfield
.imm8
= 1;
8669 /* Only string instructions can have a second memory operand, so
8670 reduce current_templates to just those if it contains any. */
8672 maybe_adjust_templates (void)
8674 const insn_template
*t
;
8676 gas_assert (i
.mem_operands
== 1);
8678 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8679 if (t
->opcode_modifier
.isstring
)
8682 if (t
< current_templates
->end
)
8684 static templates aux_templates
;
8685 bfd_boolean recheck
;
8687 aux_templates
.start
= t
;
8688 for (; t
< current_templates
->end
; ++t
)
8689 if (!t
->opcode_modifier
.isstring
)
8691 aux_templates
.end
= t
;
8693 /* Determine whether to re-check the first memory operand. */
8694 recheck
= (aux_templates
.start
!= current_templates
->start
8695 || t
!= current_templates
->end
);
8697 current_templates
= &aux_templates
;
8702 if (i
.memop1_string
!= NULL
8703 && i386_index_check (i
.memop1_string
) == 0)
8712 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8716 i386_att_operand (char *operand_string
)
8720 char *op_string
= operand_string
;
8722 if (is_space_char (*op_string
))
8725 /* We check for an absolute prefix (differentiating,
8726 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8727 if (*op_string
== ABSOLUTE_PREFIX
)
8730 if (is_space_char (*op_string
))
8732 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8735 /* Check if operand is a register. */
8736 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8738 i386_operand_type temp
;
8740 /* Check for a segment override by searching for ':' after a
8741 segment register. */
8743 if (is_space_char (*op_string
))
8745 if (*op_string
== ':'
8746 && (r
->reg_type
.bitfield
.sreg2
8747 || r
->reg_type
.bitfield
.sreg3
))
8752 i
.seg
[i
.mem_operands
] = &es
;
8755 i
.seg
[i
.mem_operands
] = &cs
;
8758 i
.seg
[i
.mem_operands
] = &ss
;
8761 i
.seg
[i
.mem_operands
] = &ds
;
8764 i
.seg
[i
.mem_operands
] = &fs
;
8767 i
.seg
[i
.mem_operands
] = &gs
;
8771 /* Skip the ':' and whitespace. */
8773 if (is_space_char (*op_string
))
8776 if (!is_digit_char (*op_string
)
8777 && !is_identifier_char (*op_string
)
8778 && *op_string
!= '('
8779 && *op_string
!= ABSOLUTE_PREFIX
)
8781 as_bad (_("bad memory operand `%s'"), op_string
);
8784 /* Handle case of %es:*foo. */
8785 if (*op_string
== ABSOLUTE_PREFIX
)
8788 if (is_space_char (*op_string
))
8790 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8792 goto do_memory_reference
;
8795 /* Handle vector operations. */
8796 if (*op_string
== '{')
8798 op_string
= check_VecOperations (op_string
, NULL
);
8799 if (op_string
== NULL
)
8805 as_bad (_("junk `%s' after register"), op_string
);
8809 temp
.bitfield
.baseindex
= 0;
8810 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8812 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8813 i
.op
[this_operand
].regs
= r
;
8816 else if (*op_string
== REGISTER_PREFIX
)
8818 as_bad (_("bad register name `%s'"), op_string
);
8821 else if (*op_string
== IMMEDIATE_PREFIX
)
8824 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8826 as_bad (_("immediate operand illegal with absolute jump"));
8829 if (!i386_immediate (op_string
))
8832 else if (RC_SAE_immediate (operand_string
))
8834 /* If it is a RC or SAE immediate, do nothing. */
8837 else if (is_digit_char (*op_string
)
8838 || is_identifier_char (*op_string
)
8839 || *op_string
== '"'
8840 || *op_string
== '(')
8842 /* This is a memory reference of some sort. */
8845 /* Start and end of displacement string expression (if found). */
8846 char *displacement_string_start
;
8847 char *displacement_string_end
;
8850 do_memory_reference
:
8851 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8853 if ((i
.mem_operands
== 1
8854 && !current_templates
->start
->opcode_modifier
.isstring
)
8855 || i
.mem_operands
== 2)
8857 as_bad (_("too many memory references for `%s'"),
8858 current_templates
->start
->name
);
8862 /* Check for base index form. We detect the base index form by
8863 looking for an ')' at the end of the operand, searching
8864 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8866 base_string
= op_string
+ strlen (op_string
);
8868 /* Handle vector operations. */
8869 vop_start
= strchr (op_string
, '{');
8870 if (vop_start
&& vop_start
< base_string
)
8872 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8874 base_string
= vop_start
;
8878 if (is_space_char (*base_string
))
8881 /* If we only have a displacement, set-up for it to be parsed later. */
8882 displacement_string_start
= op_string
;
8883 displacement_string_end
= base_string
+ 1;
8885 if (*base_string
== ')')
8888 unsigned int parens_balanced
= 1;
8889 /* We've already checked that the number of left & right ()'s are
8890 equal, so this loop will not be infinite. */
8894 if (*base_string
== ')')
8896 if (*base_string
== '(')
8899 while (parens_balanced
);
8901 temp_string
= base_string
;
8903 /* Skip past '(' and whitespace. */
8905 if (is_space_char (*base_string
))
8908 if (*base_string
== ','
8909 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8912 displacement_string_end
= temp_string
;
8914 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8918 base_string
= end_op
;
8919 if (is_space_char (*base_string
))
8923 /* There may be an index reg or scale factor here. */
8924 if (*base_string
== ',')
8927 if (is_space_char (*base_string
))
8930 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8933 base_string
= end_op
;
8934 if (is_space_char (*base_string
))
8936 if (*base_string
== ',')
8939 if (is_space_char (*base_string
))
8942 else if (*base_string
!= ')')
8944 as_bad (_("expecting `,' or `)' "
8945 "after index register in `%s'"),
8950 else if (*base_string
== REGISTER_PREFIX
)
8952 end_op
= strchr (base_string
, ',');
8955 as_bad (_("bad register name `%s'"), base_string
);
8959 /* Check for scale factor. */
8960 if (*base_string
!= ')')
8962 char *end_scale
= i386_scale (base_string
);
8967 base_string
= end_scale
;
8968 if (is_space_char (*base_string
))
8970 if (*base_string
!= ')')
8972 as_bad (_("expecting `)' "
8973 "after scale factor in `%s'"),
8978 else if (!i
.index_reg
)
8980 as_bad (_("expecting index register or scale factor "
8981 "after `,'; got '%c'"),
8986 else if (*base_string
!= ')')
8988 as_bad (_("expecting `,' or `)' "
8989 "after base register in `%s'"),
8994 else if (*base_string
== REGISTER_PREFIX
)
8996 end_op
= strchr (base_string
, ',');
8999 as_bad (_("bad register name `%s'"), base_string
);
9004 /* If there's an expression beginning the operand, parse it,
9005 assuming displacement_string_start and
9006 displacement_string_end are meaningful. */
9007 if (displacement_string_start
!= displacement_string_end
)
9009 if (!i386_displacement (displacement_string_start
,
9010 displacement_string_end
))
9014 /* Special case for (%dx) while doing input/output op. */
9016 && operand_type_equal (&i
.base_reg
->reg_type
,
9017 ®16_inoutportreg
)
9019 && i
.log2_scale_factor
== 0
9020 && i
.seg
[i
.mem_operands
] == 0
9021 && !operand_type_check (i
.types
[this_operand
], disp
))
9023 i
.types
[this_operand
] = inoutportreg
;
9027 if (i386_index_check (operand_string
) == 0)
9029 i
.types
[this_operand
].bitfield
.mem
= 1;
9030 if (i
.mem_operands
== 0)
9031 i
.memop1_string
= xstrdup (operand_string
);
9036 /* It's not a memory operand; argh! */
9037 as_bad (_("invalid char %s beginning operand %d `%s'"),
9038 output_invalid (*op_string
),
9043 return 1; /* Normal return. */
9046 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9047 that an rs_machine_dependent frag may reach. */
9050 i386_frag_max_var (fragS
*frag
)
9052 /* The only relaxable frags are for jumps.
9053 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9054 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9055 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9060 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9062 /* STT_GNU_IFUNC symbol must go through PLT. */
9063 if ((symbol_get_bfdsym (fr_symbol
)->flags
9064 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9067 if (!S_IS_EXTERNAL (fr_symbol
))
9068 /* Symbol may be weak or local. */
9069 return !S_IS_WEAK (fr_symbol
);
9071 /* Global symbols with non-default visibility can't be preempted. */
9072 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9075 if (fr_var
!= NO_RELOC
)
9076 switch ((enum bfd_reloc_code_real
) fr_var
)
9078 case BFD_RELOC_386_PLT32
:
9079 case BFD_RELOC_X86_64_PLT32
:
9080 /* Symbol with PLT relocatin may be preempted. */
9086 /* Global symbols with default visibility in a shared library may be
9087 preempted by another definition. */
9092 /* md_estimate_size_before_relax()
9094 Called just before relax() for rs_machine_dependent frags. The x86
9095 assembler uses these frags to handle variable size jump
9098 Any symbol that is now undefined will not become defined.
9099 Return the correct fr_subtype in the frag.
9100 Return the initial "guess for variable size of frag" to caller.
9101 The guess is actually the growth beyond the fixed part. Whatever
9102 we do to grow the fixed or variable part contributes to our
9106 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9108 /* We've already got fragP->fr_subtype right; all we have to do is
9109 check for un-relaxable symbols. On an ELF system, we can't relax
9110 an externally visible symbol, because it may be overridden by a
9112 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9115 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9118 #if defined (OBJ_COFF) && defined (TE_PE)
9119 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9120 && S_IS_WEAK (fragP
->fr_symbol
))
9124 /* Symbol is undefined in this segment, or we need to keep a
9125 reloc so that weak symbols can be overridden. */
9126 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9127 enum bfd_reloc_code_real reloc_type
;
9128 unsigned char *opcode
;
9131 if (fragP
->fr_var
!= NO_RELOC
)
9132 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9134 reloc_type
= BFD_RELOC_16_PCREL
;
9136 reloc_type
= BFD_RELOC_32_PCREL
;
9138 old_fr_fix
= fragP
->fr_fix
;
9139 opcode
= (unsigned char *) fragP
->fr_opcode
;
9141 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9144 /* Make jmp (0xeb) a (d)word displacement jump. */
9146 fragP
->fr_fix
+= size
;
9147 fix_new (fragP
, old_fr_fix
, size
,
9149 fragP
->fr_offset
, 1,
9155 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9157 /* Negate the condition, and branch past an
9158 unconditional jump. */
9161 /* Insert an unconditional jump. */
9163 /* We added two extra opcode bytes, and have a two byte
9165 fragP
->fr_fix
+= 2 + 2;
9166 fix_new (fragP
, old_fr_fix
+ 2, 2,
9168 fragP
->fr_offset
, 1,
9175 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9180 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9182 fragP
->fr_offset
, 1,
9184 fixP
->fx_signed
= 1;
9188 /* This changes the byte-displacement jump 0x7N
9189 to the (d)word-displacement jump 0x0f,0x8N. */
9190 opcode
[1] = opcode
[0] + 0x10;
9191 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9192 /* We've added an opcode byte. */
9193 fragP
->fr_fix
+= 1 + size
;
9194 fix_new (fragP
, old_fr_fix
+ 1, size
,
9196 fragP
->fr_offset
, 1,
9201 BAD_CASE (fragP
->fr_subtype
);
9205 return fragP
->fr_fix
- old_fr_fix
;
9208 /* Guess size depending on current relax state. Initially the relax
9209 state will correspond to a short jump and we return 1, because
9210 the variable part of the frag (the branch offset) is one byte
9211 long. However, we can relax a section more than once and in that
9212 case we must either set fr_subtype back to the unrelaxed state,
9213 or return the value for the appropriate branch. */
9214 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9217 /* Called after relax() is finished.
9219 In: Address of frag.
9220 fr_type == rs_machine_dependent.
9221 fr_subtype is what the address relaxed to.
9223 Out: Any fixSs and constants are set up.
9224 Caller will turn frag into a ".space 0". */
9227 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9230 unsigned char *opcode
;
9231 unsigned char *where_to_put_displacement
= NULL
;
9232 offsetT target_address
;
9233 offsetT opcode_address
;
9234 unsigned int extension
= 0;
9235 offsetT displacement_from_opcode_start
;
9237 opcode
= (unsigned char *) fragP
->fr_opcode
;
9239 /* Address we want to reach in file space. */
9240 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9242 /* Address opcode resides at in file space. */
9243 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9245 /* Displacement from opcode start to fill into instruction. */
9246 displacement_from_opcode_start
= target_address
- opcode_address
;
9248 if ((fragP
->fr_subtype
& BIG
) == 0)
9250 /* Don't have to change opcode. */
9251 extension
= 1; /* 1 opcode + 1 displacement */
9252 where_to_put_displacement
= &opcode
[1];
9256 if (no_cond_jump_promotion
9257 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9258 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9259 _("long jump required"));
9261 switch (fragP
->fr_subtype
)
9263 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9264 extension
= 4; /* 1 opcode + 4 displacement */
9266 where_to_put_displacement
= &opcode
[1];
9269 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9270 extension
= 2; /* 1 opcode + 2 displacement */
9272 where_to_put_displacement
= &opcode
[1];
9275 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9276 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9277 extension
= 5; /* 2 opcode + 4 displacement */
9278 opcode
[1] = opcode
[0] + 0x10;
9279 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9280 where_to_put_displacement
= &opcode
[2];
9283 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9284 extension
= 3; /* 2 opcode + 2 displacement */
9285 opcode
[1] = opcode
[0] + 0x10;
9286 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9287 where_to_put_displacement
= &opcode
[2];
9290 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9295 where_to_put_displacement
= &opcode
[3];
9299 BAD_CASE (fragP
->fr_subtype
);
9304 /* If size if less then four we are sure that the operand fits,
9305 but if it's 4, then it could be that the displacement is larger
9307 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9309 && ((addressT
) (displacement_from_opcode_start
- extension
9310 + ((addressT
) 1 << 31))
9311 > (((addressT
) 2 << 31) - 1)))
9313 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9314 _("jump target out of range"));
9315 /* Make us emit 0. */
9316 displacement_from_opcode_start
= extension
;
9318 /* Now put displacement after opcode. */
9319 md_number_to_chars ((char *) where_to_put_displacement
,
9320 (valueT
) (displacement_from_opcode_start
- extension
),
9321 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9322 fragP
->fr_fix
+= extension
;
9325 /* Apply a fixup (fixP) to segment data, once it has been determined
9326 by our caller that we have all the info we need to fix it up.
9328 Parameter valP is the pointer to the value of the bits.
9330 On the 386, immediates, displacements, and data pointers are all in
9331 the same (little-endian) format, so we don't need to care about which
9335 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9337 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9338 valueT value
= *valP
;
9340 #if !defined (TE_Mach)
9343 switch (fixP
->fx_r_type
)
9349 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9352 case BFD_RELOC_X86_64_32S
:
9353 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9356 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9359 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9364 if (fixP
->fx_addsy
!= NULL
9365 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9366 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9367 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9368 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9369 && !use_rela_relocations
)
9371 /* This is a hack. There should be a better way to handle this.
9372 This covers for the fact that bfd_install_relocation will
9373 subtract the current location (for partial_inplace, PC relative
9374 relocations); see more below. */
9378 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9381 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9386 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9389 || (symbol_section_p (fixP
->fx_addsy
)
9390 && sym_seg
!= absolute_section
))
9391 && !generic_force_reloc (fixP
))
9393 /* Yes, we add the values in twice. This is because
9394 bfd_install_relocation subtracts them out again. I think
9395 bfd_install_relocation is broken, but I don't dare change
9397 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9401 #if defined (OBJ_COFF) && defined (TE_PE)
9402 /* For some reason, the PE format does not store a
9403 section address offset for a PC relative symbol. */
9404 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9405 || S_IS_WEAK (fixP
->fx_addsy
))
9406 value
+= md_pcrel_from (fixP
);
9409 #if defined (OBJ_COFF) && defined (TE_PE)
9410 if (fixP
->fx_addsy
!= NULL
9411 && S_IS_WEAK (fixP
->fx_addsy
)
9412 /* PR 16858: Do not modify weak function references. */
9413 && ! fixP
->fx_pcrel
)
9415 #if !defined (TE_PEP)
9416 /* For x86 PE weak function symbols are neither PC-relative
9417 nor do they set S_IS_FUNCTION. So the only reliable way
9418 to detect them is to check the flags of their containing
9420 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9421 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9425 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9429 /* Fix a few things - the dynamic linker expects certain values here,
9430 and we must not disappoint it. */
9431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9432 if (IS_ELF
&& fixP
->fx_addsy
)
9433 switch (fixP
->fx_r_type
)
9435 case BFD_RELOC_386_PLT32
:
9436 case BFD_RELOC_X86_64_PLT32
:
9437 /* Make the jump instruction point to the address of the operand. At
9438 runtime we merely add the offset to the actual PLT entry. */
9442 case BFD_RELOC_386_TLS_GD
:
9443 case BFD_RELOC_386_TLS_LDM
:
9444 case BFD_RELOC_386_TLS_IE_32
:
9445 case BFD_RELOC_386_TLS_IE
:
9446 case BFD_RELOC_386_TLS_GOTIE
:
9447 case BFD_RELOC_386_TLS_GOTDESC
:
9448 case BFD_RELOC_X86_64_TLSGD
:
9449 case BFD_RELOC_X86_64_TLSLD
:
9450 case BFD_RELOC_X86_64_GOTTPOFF
:
9451 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9452 value
= 0; /* Fully resolved at runtime. No addend. */
9454 case BFD_RELOC_386_TLS_LE
:
9455 case BFD_RELOC_386_TLS_LDO_32
:
9456 case BFD_RELOC_386_TLS_LE_32
:
9457 case BFD_RELOC_X86_64_DTPOFF32
:
9458 case BFD_RELOC_X86_64_DTPOFF64
:
9459 case BFD_RELOC_X86_64_TPOFF32
:
9460 case BFD_RELOC_X86_64_TPOFF64
:
9461 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9464 case BFD_RELOC_386_TLS_DESC_CALL
:
9465 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9466 value
= 0; /* Fully resolved at runtime. No addend. */
9467 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9471 case BFD_RELOC_VTABLE_INHERIT
:
9472 case BFD_RELOC_VTABLE_ENTRY
:
9479 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9481 #endif /* !defined (TE_Mach) */
9483 /* Are we finished with this relocation now? */
9484 if (fixP
->fx_addsy
== NULL
)
9486 #if defined (OBJ_COFF) && defined (TE_PE)
9487 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9490 /* Remember value for tc_gen_reloc. */
9491 fixP
->fx_addnumber
= value
;
9492 /* Clear out the frag for now. */
9496 else if (use_rela_relocations
)
9498 fixP
->fx_no_overflow
= 1;
9499 /* Remember value for tc_gen_reloc. */
9500 fixP
->fx_addnumber
= value
;
9504 md_number_to_chars (p
, value
, fixP
->fx_size
);
9508 md_atof (int type
, char *litP
, int *sizeP
)
9510 /* This outputs the LITTLENUMs in REVERSE order;
9511 in accord with the bigendian 386. */
9512 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9515 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9518 output_invalid (int c
)
9521 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9524 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9525 "(0x%x)", (unsigned char) c
);
9526 return output_invalid_buf
;
9529 /* REG_STRING starts *before* REGISTER_PREFIX. */
9531 static const reg_entry
*
9532 parse_real_register (char *reg_string
, char **end_op
)
9534 char *s
= reg_string
;
9536 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9539 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9540 if (*s
== REGISTER_PREFIX
)
9543 if (is_space_char (*s
))
9547 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9549 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9550 return (const reg_entry
*) NULL
;
9554 /* For naked regs, make sure that we are not dealing with an identifier.
9555 This prevents confusing an identifier like `eax_var' with register
9557 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9558 return (const reg_entry
*) NULL
;
9562 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9564 /* Handle floating point regs, allowing spaces in the (i) part. */
9565 if (r
== i386_regtab
/* %st is first entry of table */)
9567 if (is_space_char (*s
))
9572 if (is_space_char (*s
))
9574 if (*s
>= '0' && *s
<= '7')
9578 if (is_space_char (*s
))
9583 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9588 /* We have "%st(" then garbage. */
9589 return (const reg_entry
*) NULL
;
9593 if (r
== NULL
|| allow_pseudo_reg
)
9596 if (operand_type_all_zero (&r
->reg_type
))
9597 return (const reg_entry
*) NULL
;
9599 if ((r
->reg_type
.bitfield
.reg32
9600 || r
->reg_type
.bitfield
.sreg3
9601 || r
->reg_type
.bitfield
.control
9602 || r
->reg_type
.bitfield
.debug
9603 || r
->reg_type
.bitfield
.test
)
9604 && !cpu_arch_flags
.bitfield
.cpui386
)
9605 return (const reg_entry
*) NULL
;
9607 if (r
->reg_type
.bitfield
.floatreg
9608 && !cpu_arch_flags
.bitfield
.cpu8087
9609 && !cpu_arch_flags
.bitfield
.cpu287
9610 && !cpu_arch_flags
.bitfield
.cpu387
)
9611 return (const reg_entry
*) NULL
;
9613 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9614 return (const reg_entry
*) NULL
;
9616 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9617 return (const reg_entry
*) NULL
;
9619 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9620 return (const reg_entry
*) NULL
;
9622 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9623 return (const reg_entry
*) NULL
;
9625 if (r
->reg_type
.bitfield
.regmask
9626 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9627 return (const reg_entry
*) NULL
;
9629 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9630 if (!allow_index_reg
9631 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9632 return (const reg_entry
*) NULL
;
9634 /* Upper 16 vector register is only available with VREX in 64bit
9636 if ((r
->reg_flags
& RegVRex
))
9638 if (!cpu_arch_flags
.bitfield
.cpuvrex
9639 || flag_code
!= CODE_64BIT
)
9640 return (const reg_entry
*) NULL
;
9645 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9646 || r
->reg_type
.bitfield
.reg64
)
9647 && (!cpu_arch_flags
.bitfield
.cpulm
9648 || !operand_type_equal (&r
->reg_type
, &control
))
9649 && flag_code
!= CODE_64BIT
)
9650 return (const reg_entry
*) NULL
;
9652 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9653 return (const reg_entry
*) NULL
;
9658 /* REG_STRING starts *before* REGISTER_PREFIX. */
9660 static const reg_entry
*
9661 parse_register (char *reg_string
, char **end_op
)
9665 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9666 r
= parse_real_register (reg_string
, end_op
);
9671 char *save
= input_line_pointer
;
9675 input_line_pointer
= reg_string
;
9676 c
= get_symbol_name (®_string
);
9677 symbolP
= symbol_find (reg_string
);
9678 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9680 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9682 know (e
->X_op
== O_register
);
9683 know (e
->X_add_number
>= 0
9684 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9685 r
= i386_regtab
+ e
->X_add_number
;
9686 if ((r
->reg_flags
& RegVRex
))
9688 *end_op
= input_line_pointer
;
9690 *input_line_pointer
= c
;
9691 input_line_pointer
= save
;
9697 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9700 char *end
= input_line_pointer
;
9703 r
= parse_register (name
, &input_line_pointer
);
9704 if (r
&& end
<= input_line_pointer
)
9706 *nextcharP
= *input_line_pointer
;
9707 *input_line_pointer
= 0;
9708 e
->X_op
= O_register
;
9709 e
->X_add_number
= r
- i386_regtab
;
9712 input_line_pointer
= end
;
9714 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9718 md_operand (expressionS
*e
)
9723 switch (*input_line_pointer
)
9725 case REGISTER_PREFIX
:
9726 r
= parse_real_register (input_line_pointer
, &end
);
9729 e
->X_op
= O_register
;
9730 e
->X_add_number
= r
- i386_regtab
;
9731 input_line_pointer
= end
;
9736 gas_assert (intel_syntax
);
9737 end
= input_line_pointer
++;
9739 if (*input_line_pointer
== ']')
9741 ++input_line_pointer
;
9742 e
->X_op_symbol
= make_expr_symbol (e
);
9743 e
->X_add_symbol
= NULL
;
9744 e
->X_add_number
= 0;
9750 input_line_pointer
= end
;
9757 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9758 const char *md_shortopts
= "kVQ:sqn";
9760 const char *md_shortopts
= "qn";
9763 #define OPTION_32 (OPTION_MD_BASE + 0)
9764 #define OPTION_64 (OPTION_MD_BASE + 1)
9765 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9766 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9767 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9768 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9769 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9770 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9771 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9772 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9773 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9774 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9775 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9776 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9777 #define OPTION_X32 (OPTION_MD_BASE + 14)
9778 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9779 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9780 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9781 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9782 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9783 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9784 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9785 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9786 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9787 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9788 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9790 struct option md_longopts
[] =
9792 {"32", no_argument
, NULL
, OPTION_32
},
9793 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9794 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9795 {"64", no_argument
, NULL
, OPTION_64
},
9797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9798 {"x32", no_argument
, NULL
, OPTION_X32
},
9799 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9801 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9802 {"march", required_argument
, NULL
, OPTION_MARCH
},
9803 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9804 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9805 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9806 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9807 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9808 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9809 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9810 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9811 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9812 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9813 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9814 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9815 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9816 # if defined (TE_PE) || defined (TE_PEP)
9817 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9819 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9820 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9821 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9822 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9823 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9824 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9825 {NULL
, no_argument
, NULL
, 0}
9827 size_t md_longopts_size
= sizeof (md_longopts
);
9830 md_parse_option (int c
, const char *arg
)
9833 char *arch
, *next
, *saved
;
9838 optimize_align_code
= 0;
9845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9846 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9847 should be emitted or not. FIXME: Not implemented. */
9851 /* -V: SVR4 argument to print version ID. */
9853 print_version_id ();
9856 /* -k: Ignore for FreeBSD compatibility. */
9861 /* -s: On i386 Solaris, this tells the native assembler to use
9862 .stab instead of .stab.excl. We always use .stab anyhow. */
9865 case OPTION_MSHARED
:
9869 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9870 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9873 const char **list
, **l
;
9875 list
= bfd_target_list ();
9876 for (l
= list
; *l
!= NULL
; l
++)
9877 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9878 || strcmp (*l
, "coff-x86-64") == 0
9879 || strcmp (*l
, "pe-x86-64") == 0
9880 || strcmp (*l
, "pei-x86-64") == 0
9881 || strcmp (*l
, "mach-o-x86-64") == 0)
9883 default_arch
= "x86_64";
9887 as_fatal (_("no compiled in support for x86_64"));
9893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9897 const char **list
, **l
;
9899 list
= bfd_target_list ();
9900 for (l
= list
; *l
!= NULL
; l
++)
9901 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9903 default_arch
= "x86_64:32";
9907 as_fatal (_("no compiled in support for 32bit x86_64"));
9911 as_fatal (_("32bit x86_64 is only supported for ELF"));
9916 default_arch
= "i386";
9920 #ifdef SVR4_COMMENT_CHARS
9925 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9927 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9931 i386_comment_chars
= n
;
9937 saved
= xstrdup (arg
);
9939 /* Allow -march=+nosse. */
9945 as_fatal (_("invalid -march= option: `%s'"), arg
);
9946 next
= strchr (arch
, '+');
9949 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9951 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9954 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9957 cpu_arch_name
= cpu_arch
[j
].name
;
9958 cpu_sub_arch_name
= NULL
;
9959 cpu_arch_flags
= cpu_arch
[j
].flags
;
9960 cpu_arch_isa
= cpu_arch
[j
].type
;
9961 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9962 if (!cpu_arch_tune_set
)
9964 cpu_arch_tune
= cpu_arch_isa
;
9965 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9969 else if (*cpu_arch
[j
].name
== '.'
9970 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9972 /* ISA entension. */
9973 i386_cpu_flags flags
;
9975 flags
= cpu_flags_or (cpu_arch_flags
,
9978 if (!valid_iamcu_cpu_flags (&flags
))
9979 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9980 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9982 if (cpu_sub_arch_name
)
9984 char *name
= cpu_sub_arch_name
;
9985 cpu_sub_arch_name
= concat (name
,
9987 (const char *) NULL
);
9991 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9992 cpu_arch_flags
= flags
;
9993 cpu_arch_isa_flags
= flags
;
9999 if (j
>= ARRAY_SIZE (cpu_arch
))
10001 /* Disable an ISA entension. */
10002 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10003 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10005 i386_cpu_flags flags
;
10007 flags
= cpu_flags_and_not (cpu_arch_flags
,
10008 cpu_noarch
[j
].flags
);
10009 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10011 if (cpu_sub_arch_name
)
10013 char *name
= cpu_sub_arch_name
;
10014 cpu_sub_arch_name
= concat (arch
,
10015 (const char *) NULL
);
10019 cpu_sub_arch_name
= xstrdup (arch
);
10020 cpu_arch_flags
= flags
;
10021 cpu_arch_isa_flags
= flags
;
10026 if (j
>= ARRAY_SIZE (cpu_noarch
))
10027 j
= ARRAY_SIZE (cpu_arch
);
10030 if (j
>= ARRAY_SIZE (cpu_arch
))
10031 as_fatal (_("invalid -march= option: `%s'"), arg
);
10035 while (next
!= NULL
);
10041 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10042 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10044 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10046 cpu_arch_tune_set
= 1;
10047 cpu_arch_tune
= cpu_arch
[j
].type
;
10048 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10052 if (j
>= ARRAY_SIZE (cpu_arch
))
10053 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10056 case OPTION_MMNEMONIC
:
10057 if (strcasecmp (arg
, "att") == 0)
10058 intel_mnemonic
= 0;
10059 else if (strcasecmp (arg
, "intel") == 0)
10060 intel_mnemonic
= 1;
10062 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10065 case OPTION_MSYNTAX
:
10066 if (strcasecmp (arg
, "att") == 0)
10068 else if (strcasecmp (arg
, "intel") == 0)
10071 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10074 case OPTION_MINDEX_REG
:
10075 allow_index_reg
= 1;
10078 case OPTION_MNAKED_REG
:
10079 allow_naked_reg
= 1;
10082 case OPTION_MOLD_GCC
:
10086 case OPTION_MSSE2AVX
:
10090 case OPTION_MSSE_CHECK
:
10091 if (strcasecmp (arg
, "error") == 0)
10092 sse_check
= check_error
;
10093 else if (strcasecmp (arg
, "warning") == 0)
10094 sse_check
= check_warning
;
10095 else if (strcasecmp (arg
, "none") == 0)
10096 sse_check
= check_none
;
10098 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10101 case OPTION_MOPERAND_CHECK
:
10102 if (strcasecmp (arg
, "error") == 0)
10103 operand_check
= check_error
;
10104 else if (strcasecmp (arg
, "warning") == 0)
10105 operand_check
= check_warning
;
10106 else if (strcasecmp (arg
, "none") == 0)
10107 operand_check
= check_none
;
10109 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10112 case OPTION_MAVXSCALAR
:
10113 if (strcasecmp (arg
, "128") == 0)
10114 avxscalar
= vex128
;
10115 else if (strcasecmp (arg
, "256") == 0)
10116 avxscalar
= vex256
;
10118 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10121 case OPTION_MADD_BND_PREFIX
:
10122 add_bnd_prefix
= 1;
10125 case OPTION_MEVEXLIG
:
10126 if (strcmp (arg
, "128") == 0)
10127 evexlig
= evexl128
;
10128 else if (strcmp (arg
, "256") == 0)
10129 evexlig
= evexl256
;
10130 else if (strcmp (arg
, "512") == 0)
10131 evexlig
= evexl512
;
10133 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10136 case OPTION_MEVEXRCIG
:
10137 if (strcmp (arg
, "rne") == 0)
10139 else if (strcmp (arg
, "rd") == 0)
10141 else if (strcmp (arg
, "ru") == 0)
10143 else if (strcmp (arg
, "rz") == 0)
10146 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10149 case OPTION_MEVEXWIG
:
10150 if (strcmp (arg
, "0") == 0)
10152 else if (strcmp (arg
, "1") == 0)
10155 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10158 # if defined (TE_PE) || defined (TE_PEP)
10159 case OPTION_MBIG_OBJ
:
10164 case OPTION_MOMIT_LOCK_PREFIX
:
10165 if (strcasecmp (arg
, "yes") == 0)
10166 omit_lock_prefix
= 1;
10167 else if (strcasecmp (arg
, "no") == 0)
10168 omit_lock_prefix
= 0;
10170 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10173 case OPTION_MFENCE_AS_LOCK_ADD
:
10174 if (strcasecmp (arg
, "yes") == 0)
10176 else if (strcasecmp (arg
, "no") == 0)
10179 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10182 case OPTION_MRELAX_RELOCATIONS
:
10183 if (strcasecmp (arg
, "yes") == 0)
10184 generate_relax_relocations
= 1;
10185 else if (strcasecmp (arg
, "no") == 0)
10186 generate_relax_relocations
= 0;
10188 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10191 case OPTION_MAMD64
:
10195 case OPTION_MINTEL64
:
10205 #define MESSAGE_TEMPLATE \
10209 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10210 int *left_p
, const char *name
, int len
)
10212 int size
= sizeof (MESSAGE_TEMPLATE
);
10213 int left
= *left_p
;
10215 /* Reserve 2 spaces for ", " or ",\0" */
10218 /* Check if there is any room. */
10226 p
= mempcpy (p
, name
, len
);
10230 /* Output the current message now and start a new one. */
10233 fprintf (stream
, "%s\n", message
);
10235 left
= size
- (start
- message
) - len
- 2;
10237 gas_assert (left
>= 0);
10239 p
= mempcpy (p
, name
, len
);
10247 show_arch (FILE *stream
, int ext
, int check
)
10249 static char message
[] = MESSAGE_TEMPLATE
;
10250 char *start
= message
+ 27;
10252 int size
= sizeof (MESSAGE_TEMPLATE
);
10259 left
= size
- (start
- message
);
10260 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10262 /* Should it be skipped? */
10263 if (cpu_arch
[j
].skip
)
10266 name
= cpu_arch
[j
].name
;
10267 len
= cpu_arch
[j
].len
;
10270 /* It is an extension. Skip if we aren't asked to show it. */
10281 /* It is an processor. Skip if we show only extension. */
10284 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10286 /* It is an impossible processor - skip. */
10290 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10293 /* Display disabled extensions. */
10295 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10297 name
= cpu_noarch
[j
].name
;
10298 len
= cpu_noarch
[j
].len
;
10299 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10304 fprintf (stream
, "%s\n", message
);
10308 md_show_usage (FILE *stream
)
10310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10311 fprintf (stream
, _("\
10313 -V print assembler version number\n\
10316 fprintf (stream
, _("\
10317 -n Do not optimize code alignment\n\
10318 -q quieten some warnings\n"));
10319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10320 fprintf (stream
, _("\
10323 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10324 || defined (TE_PE) || defined (TE_PEP))
10325 fprintf (stream
, _("\
10326 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10328 #ifdef SVR4_COMMENT_CHARS
10329 fprintf (stream
, _("\
10330 --divide do not treat `/' as a comment character\n"));
10332 fprintf (stream
, _("\
10333 --divide ignored\n"));
10335 fprintf (stream
, _("\
10336 -march=CPU[,+EXTENSION...]\n\
10337 generate code for CPU and EXTENSION, CPU is one of:\n"));
10338 show_arch (stream
, 0, 1);
10339 fprintf (stream
, _("\
10340 EXTENSION is combination of:\n"));
10341 show_arch (stream
, 1, 0);
10342 fprintf (stream
, _("\
10343 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10344 show_arch (stream
, 0, 0);
10345 fprintf (stream
, _("\
10346 -msse2avx encode SSE instructions with VEX prefix\n"));
10347 fprintf (stream
, _("\
10348 -msse-check=[none|error|warning]\n\
10349 check SSE instructions\n"));
10350 fprintf (stream
, _("\
10351 -moperand-check=[none|error|warning]\n\
10352 check operand combinations for validity\n"));
10353 fprintf (stream
, _("\
10354 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10356 fprintf (stream
, _("\
10357 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10359 fprintf (stream
, _("\
10360 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10361 for EVEX.W bit ignored instructions\n"));
10362 fprintf (stream
, _("\
10363 -mevexrcig=[rne|rd|ru|rz]\n\
10364 encode EVEX instructions with specific EVEX.RC value\n\
10365 for SAE-only ignored instructions\n"));
10366 fprintf (stream
, _("\
10367 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10368 fprintf (stream
, _("\
10369 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10370 fprintf (stream
, _("\
10371 -mindex-reg support pseudo index registers\n"));
10372 fprintf (stream
, _("\
10373 -mnaked-reg don't require `%%' prefix for registers\n"));
10374 fprintf (stream
, _("\
10375 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10376 fprintf (stream
, _("\
10377 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10378 fprintf (stream
, _("\
10379 -mshared disable branch optimization for shared code\n"));
10380 # if defined (TE_PE) || defined (TE_PEP)
10381 fprintf (stream
, _("\
10382 -mbig-obj generate big object files\n"));
10384 fprintf (stream
, _("\
10385 -momit-lock-prefix=[no|yes]\n\
10386 strip all lock prefixes\n"));
10387 fprintf (stream
, _("\
10388 -mfence-as-lock-add=[no|yes]\n\
10389 encode lfence, mfence and sfence as\n\
10390 lock addl $0x0, (%%{re}sp)\n"));
10391 fprintf (stream
, _("\
10392 -mrelax-relocations=[no|yes]\n\
10393 generate relax relocations\n"));
10394 fprintf (stream
, _("\
10395 -mamd64 accept only AMD64 ISA\n"));
10396 fprintf (stream
, _("\
10397 -mintel64 accept only Intel64 ISA\n"));
10400 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10401 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10402 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10404 /* Pick the target format to use. */
10407 i386_target_format (void)
10409 if (!strncmp (default_arch
, "x86_64", 6))
10411 update_code_flag (CODE_64BIT
, 1);
10412 if (default_arch
[6] == '\0')
10413 x86_elf_abi
= X86_64_ABI
;
10415 x86_elf_abi
= X86_64_X32_ABI
;
10417 else if (!strcmp (default_arch
, "i386"))
10418 update_code_flag (CODE_32BIT
, 1);
10419 else if (!strcmp (default_arch
, "iamcu"))
10421 update_code_flag (CODE_32BIT
, 1);
10422 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10424 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10425 cpu_arch_name
= "iamcu";
10426 cpu_sub_arch_name
= NULL
;
10427 cpu_arch_flags
= iamcu_flags
;
10428 cpu_arch_isa
= PROCESSOR_IAMCU
;
10429 cpu_arch_isa_flags
= iamcu_flags
;
10430 if (!cpu_arch_tune_set
)
10432 cpu_arch_tune
= cpu_arch_isa
;
10433 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10437 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10441 as_fatal (_("unknown architecture"));
10443 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10444 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10445 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10446 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10448 switch (OUTPUT_FLAVOR
)
10450 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10451 case bfd_target_aout_flavour
:
10452 return AOUT_TARGET_FORMAT
;
10454 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10455 # if defined (TE_PE) || defined (TE_PEP)
10456 case bfd_target_coff_flavour
:
10457 if (flag_code
== CODE_64BIT
)
10458 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10461 # elif defined (TE_GO32)
10462 case bfd_target_coff_flavour
:
10463 return "coff-go32";
10465 case bfd_target_coff_flavour
:
10466 return "coff-i386";
10469 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10470 case bfd_target_elf_flavour
:
10472 const char *format
;
10474 switch (x86_elf_abi
)
10477 format
= ELF_TARGET_FORMAT
;
10480 use_rela_relocations
= 1;
10482 format
= ELF_TARGET_FORMAT64
;
10484 case X86_64_X32_ABI
:
10485 use_rela_relocations
= 1;
10487 disallow_64bit_reloc
= 1;
10488 format
= ELF_TARGET_FORMAT32
;
10491 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10493 if (x86_elf_abi
!= X86_64_ABI
)
10494 as_fatal (_("Intel L1OM is 64bit only"));
10495 return ELF_TARGET_L1OM_FORMAT
;
10497 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10499 if (x86_elf_abi
!= X86_64_ABI
)
10500 as_fatal (_("Intel K1OM is 64bit only"));
10501 return ELF_TARGET_K1OM_FORMAT
;
10503 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10505 if (x86_elf_abi
!= I386_ABI
)
10506 as_fatal (_("Intel MCU is 32bit only"));
10507 return ELF_TARGET_IAMCU_FORMAT
;
10513 #if defined (OBJ_MACH_O)
10514 case bfd_target_mach_o_flavour
:
10515 if (flag_code
== CODE_64BIT
)
10517 use_rela_relocations
= 1;
10519 return "mach-o-x86-64";
10522 return "mach-o-i386";
10530 #endif /* OBJ_MAYBE_ more than one */
10533 md_undefined_symbol (char *name
)
10535 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10536 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10537 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10538 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10542 if (symbol_find (name
))
10543 as_bad (_("GOT already in symbol table"));
10544 GOT_symbol
= symbol_new (name
, undefined_section
,
10545 (valueT
) 0, &zero_address_frag
);
10552 /* Round up a section size to the appropriate boundary. */
10555 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10557 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10558 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10560 /* For a.out, force the section size to be aligned. If we don't do
10561 this, BFD will align it for us, but it will not write out the
10562 final bytes of the section. This may be a bug in BFD, but it is
10563 easier to fix it here since that is how the other a.out targets
10567 align
= bfd_get_section_alignment (stdoutput
, segment
);
10568 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10575 /* On the i386, PC-relative offsets are relative to the start of the
10576 next instruction. That is, the address of the offset, plus its
10577 size, since the offset is always the last part of the insn. */
10580 md_pcrel_from (fixS
*fixP
)
10582 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10588 s_bss (int ignore ATTRIBUTE_UNUSED
)
10592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10594 obj_elf_section_change_hook ();
10596 temp
= get_absolute_expression ();
10597 subseg_set (bss_section
, (subsegT
) temp
);
10598 demand_empty_rest_of_line ();
10604 i386_validate_fix (fixS
*fixp
)
10606 if (fixp
->fx_subsy
)
10608 if (fixp
->fx_subsy
== GOT_symbol
)
10610 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10614 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10615 if (fixp
->fx_tcbit2
)
10616 fixp
->fx_r_type
= (fixp
->fx_tcbit
10617 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10618 : BFD_RELOC_X86_64_GOTPCRELX
);
10621 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10626 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10628 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10630 fixp
->fx_subsy
= 0;
10633 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10634 else if (!object_64bit
)
10636 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10637 && fixp
->fx_tcbit2
)
10638 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10644 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10647 bfd_reloc_code_real_type code
;
10649 switch (fixp
->fx_r_type
)
10651 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10652 case BFD_RELOC_SIZE32
:
10653 case BFD_RELOC_SIZE64
:
10654 if (S_IS_DEFINED (fixp
->fx_addsy
)
10655 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10657 /* Resolve size relocation against local symbol to size of
10658 the symbol plus addend. */
10659 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10660 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10661 && !fits_in_unsigned_long (value
))
10662 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10663 _("symbol size computation overflow"));
10664 fixp
->fx_addsy
= NULL
;
10665 fixp
->fx_subsy
= NULL
;
10666 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10671 case BFD_RELOC_X86_64_PLT32
:
10672 case BFD_RELOC_X86_64_GOT32
:
10673 case BFD_RELOC_X86_64_GOTPCREL
:
10674 case BFD_RELOC_X86_64_GOTPCRELX
:
10675 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10676 case BFD_RELOC_386_PLT32
:
10677 case BFD_RELOC_386_GOT32
:
10678 case BFD_RELOC_386_GOT32X
:
10679 case BFD_RELOC_386_GOTOFF
:
10680 case BFD_RELOC_386_GOTPC
:
10681 case BFD_RELOC_386_TLS_GD
:
10682 case BFD_RELOC_386_TLS_LDM
:
10683 case BFD_RELOC_386_TLS_LDO_32
:
10684 case BFD_RELOC_386_TLS_IE_32
:
10685 case BFD_RELOC_386_TLS_IE
:
10686 case BFD_RELOC_386_TLS_GOTIE
:
10687 case BFD_RELOC_386_TLS_LE_32
:
10688 case BFD_RELOC_386_TLS_LE
:
10689 case BFD_RELOC_386_TLS_GOTDESC
:
10690 case BFD_RELOC_386_TLS_DESC_CALL
:
10691 case BFD_RELOC_X86_64_TLSGD
:
10692 case BFD_RELOC_X86_64_TLSLD
:
10693 case BFD_RELOC_X86_64_DTPOFF32
:
10694 case BFD_RELOC_X86_64_DTPOFF64
:
10695 case BFD_RELOC_X86_64_GOTTPOFF
:
10696 case BFD_RELOC_X86_64_TPOFF32
:
10697 case BFD_RELOC_X86_64_TPOFF64
:
10698 case BFD_RELOC_X86_64_GOTOFF64
:
10699 case BFD_RELOC_X86_64_GOTPC32
:
10700 case BFD_RELOC_X86_64_GOT64
:
10701 case BFD_RELOC_X86_64_GOTPCREL64
:
10702 case BFD_RELOC_X86_64_GOTPC64
:
10703 case BFD_RELOC_X86_64_GOTPLT64
:
10704 case BFD_RELOC_X86_64_PLTOFF64
:
10705 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10706 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10707 case BFD_RELOC_RVA
:
10708 case BFD_RELOC_VTABLE_ENTRY
:
10709 case BFD_RELOC_VTABLE_INHERIT
:
10711 case BFD_RELOC_32_SECREL
:
10713 code
= fixp
->fx_r_type
;
10715 case BFD_RELOC_X86_64_32S
:
10716 if (!fixp
->fx_pcrel
)
10718 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10719 code
= fixp
->fx_r_type
;
10723 if (fixp
->fx_pcrel
)
10725 switch (fixp
->fx_size
)
10728 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10729 _("can not do %d byte pc-relative relocation"),
10731 code
= BFD_RELOC_32_PCREL
;
10733 case 1: code
= BFD_RELOC_8_PCREL
; break;
10734 case 2: code
= BFD_RELOC_16_PCREL
; break;
10735 case 4: code
= BFD_RELOC_32_PCREL
; break;
10737 case 8: code
= BFD_RELOC_64_PCREL
; break;
10743 switch (fixp
->fx_size
)
10746 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10747 _("can not do %d byte relocation"),
10749 code
= BFD_RELOC_32
;
10751 case 1: code
= BFD_RELOC_8
; break;
10752 case 2: code
= BFD_RELOC_16
; break;
10753 case 4: code
= BFD_RELOC_32
; break;
10755 case 8: code
= BFD_RELOC_64
; break;
10762 if ((code
== BFD_RELOC_32
10763 || code
== BFD_RELOC_32_PCREL
10764 || code
== BFD_RELOC_X86_64_32S
)
10766 && fixp
->fx_addsy
== GOT_symbol
)
10769 code
= BFD_RELOC_386_GOTPC
;
10771 code
= BFD_RELOC_X86_64_GOTPC32
;
10773 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10775 && fixp
->fx_addsy
== GOT_symbol
)
10777 code
= BFD_RELOC_X86_64_GOTPC64
;
10780 rel
= XNEW (arelent
);
10781 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10782 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10784 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10786 if (!use_rela_relocations
)
10788 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10789 vtable entry to be used in the relocation's section offset. */
10790 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10791 rel
->address
= fixp
->fx_offset
;
10792 #if defined (OBJ_COFF) && defined (TE_PE)
10793 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10794 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10799 /* Use the rela in 64bit mode. */
10802 if (disallow_64bit_reloc
)
10805 case BFD_RELOC_X86_64_DTPOFF64
:
10806 case BFD_RELOC_X86_64_TPOFF64
:
10807 case BFD_RELOC_64_PCREL
:
10808 case BFD_RELOC_X86_64_GOTOFF64
:
10809 case BFD_RELOC_X86_64_GOT64
:
10810 case BFD_RELOC_X86_64_GOTPCREL64
:
10811 case BFD_RELOC_X86_64_GOTPC64
:
10812 case BFD_RELOC_X86_64_GOTPLT64
:
10813 case BFD_RELOC_X86_64_PLTOFF64
:
10814 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10815 _("cannot represent relocation type %s in x32 mode"),
10816 bfd_get_reloc_code_name (code
));
10822 if (!fixp
->fx_pcrel
)
10823 rel
->addend
= fixp
->fx_offset
;
10827 case BFD_RELOC_X86_64_PLT32
:
10828 case BFD_RELOC_X86_64_GOT32
:
10829 case BFD_RELOC_X86_64_GOTPCREL
:
10830 case BFD_RELOC_X86_64_GOTPCRELX
:
10831 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10832 case BFD_RELOC_X86_64_TLSGD
:
10833 case BFD_RELOC_X86_64_TLSLD
:
10834 case BFD_RELOC_X86_64_GOTTPOFF
:
10835 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10836 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10837 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10840 rel
->addend
= (section
->vma
10842 + fixp
->fx_addnumber
10843 + md_pcrel_from (fixp
));
10848 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10849 if (rel
->howto
== NULL
)
10851 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10852 _("cannot represent relocation type %s"),
10853 bfd_get_reloc_code_name (code
));
10854 /* Set howto to a garbage value so that we can keep going. */
10855 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10856 gas_assert (rel
->howto
!= NULL
);
10862 #include "tc-i386-intel.c"
10865 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10867 int saved_naked_reg
;
10868 char saved_register_dot
;
10870 saved_naked_reg
= allow_naked_reg
;
10871 allow_naked_reg
= 1;
10872 saved_register_dot
= register_chars
['.'];
10873 register_chars
['.'] = '.';
10874 allow_pseudo_reg
= 1;
10875 expression_and_evaluate (exp
);
10876 allow_pseudo_reg
= 0;
10877 register_chars
['.'] = saved_register_dot
;
10878 allow_naked_reg
= saved_naked_reg
;
10880 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10882 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10884 exp
->X_op
= O_constant
;
10885 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10886 .dw2_regnum
[flag_code
>> 1];
10889 exp
->X_op
= O_illegal
;
10894 tc_x86_frame_initial_instructions (void)
10896 static unsigned int sp_regno
[2];
10898 if (!sp_regno
[flag_code
>> 1])
10900 char *saved_input
= input_line_pointer
;
10901 char sp
[][4] = {"esp", "rsp"};
10904 input_line_pointer
= sp
[flag_code
>> 1];
10905 tc_x86_parse_to_dw2regnum (&exp
);
10906 gas_assert (exp
.X_op
== O_constant
);
10907 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10908 input_line_pointer
= saved_input
;
10911 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10912 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10916 x86_dwarf2_addr_size (void)
10918 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10919 if (x86_elf_abi
== X86_64_X32_ABI
)
10922 return bfd_arch_bits_per_address (stdoutput
) / 8;
10926 i386_elf_section_type (const char *str
, size_t len
)
10928 if (flag_code
== CODE_64BIT
10929 && len
== sizeof ("unwind") - 1
10930 && strncmp (str
, "unwind", 6) == 0)
10931 return SHT_X86_64_UNWIND
;
10938 i386_solaris_fix_up_eh_frame (segT sec
)
10940 if (flag_code
== CODE_64BIT
)
10941 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10947 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10951 exp
.X_op
= O_secrel
;
10952 exp
.X_add_symbol
= symbol
;
10953 exp
.X_add_number
= 0;
10954 emit_expr (&exp
, size
);
10958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10959 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10962 x86_64_section_letter (int letter
, const char **ptr_msg
)
10964 if (flag_code
== CODE_64BIT
)
10967 return SHF_X86_64_LARGE
;
10969 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10972 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10977 x86_64_section_word (char *str
, size_t len
)
10979 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10980 return SHF_X86_64_LARGE
;
10986 handle_large_common (int small ATTRIBUTE_UNUSED
)
10988 if (flag_code
!= CODE_64BIT
)
10990 s_comm_internal (0, elf_common_parse
);
10991 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10995 static segT lbss_section
;
10996 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10997 asection
*saved_bss_section
= bss_section
;
10999 if (lbss_section
== NULL
)
11001 flagword applicable
;
11002 segT seg
= now_seg
;
11003 subsegT subseg
= now_subseg
;
11005 /* The .lbss section is for local .largecomm symbols. */
11006 lbss_section
= subseg_new (".lbss", 0);
11007 applicable
= bfd_applicable_section_flags (stdoutput
);
11008 bfd_set_section_flags (stdoutput
, lbss_section
,
11009 applicable
& SEC_ALLOC
);
11010 seg_info (lbss_section
)->bss
= 1;
11012 subseg_set (seg
, subseg
);
11015 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11016 bss_section
= lbss_section
;
11018 s_comm_internal (0, elf_common_parse
);
11020 elf_com_section_ptr
= saved_com_section_ptr
;
11021 bss_section
= saved_bss_section
;
11024 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */