1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* If we have selected a cpu we are generating instructions for. */
808 static int cpu_arch_tune_set
= 0;
810 /* Cpu we are generating instructions for. */
811 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
813 /* CPU instruction set architecture used. */
814 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
816 /* CPU feature flags of instruction set architecture used. */
817 i386_cpu_flags cpu_arch_isa_flags
;
819 /* If set, conditional jumps are not automatically promoted to handle
820 larger than a byte offset. */
821 static bool no_cond_jump_promotion
= false;
823 /* This will be set from an expression parser hook if there's any
824 applicable operator involved in an expression. */
827 expr_operator_present
,
831 /* Encode SSE instructions with VEX prefix. */
832 static unsigned int sse2avx
;
834 /* Encode aligned vector move as unaligned vector move. */
835 static unsigned int use_unaligned_vector_move
;
837 /* Maximum permitted vector size. */
838 #define VSZ_DEFAULT VSZ512
839 static unsigned int vector_size
= VSZ_DEFAULT
;
841 /* Encode scalar AVX instructions with specific vector length. */
848 /* Encode VEX WIG instructions with specific vex.w. */
855 /* Encode scalar EVEX LIG instructions with specific vector length. */
863 /* Encode EVEX WIG instructions with specific evex.w. */
870 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
871 static enum rc_type evexrcig
= rne
;
873 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
874 static symbolS
*GOT_symbol
;
876 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
877 unsigned int x86_dwarf2_return_column
;
879 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
880 int x86_cie_data_alignment
;
882 /* Interface to relax_segment.
883 There are 3 major relax states for 386 jump insns because the
884 different types of jumps add different sizes to frags when we're
885 figuring out what sort of jump to choose to reach a given label.
887 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
888 branches which are handled by md_estimate_size_before_relax() and
889 i386_generic_table_relax_frag(). */
892 #define UNCOND_JUMP 0
894 #define COND_JUMP86 2
895 #define BRANCH_PADDING 3
896 #define BRANCH_PREFIX 4
897 #define FUSED_JCC_PADDING 5
902 #define SMALL16 (SMALL | CODE16)
904 #define BIG16 (BIG | CODE16)
908 #define INLINE __inline__
914 #define ENCODE_RELAX_STATE(type, size) \
915 ((relax_substateT) (((type) << 2) | (size)))
916 #define TYPE_FROM_RELAX_STATE(s) \
918 #define DISP_SIZE_FROM_RELAX_STATE(s) \
919 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
921 /* This table is used by relax_frag to promote short jumps to long
922 ones where necessary. SMALL (short) jumps may be promoted to BIG
923 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
924 don't allow a short jump in a 32 bit code segment to be promoted to
925 a 16 bit offset jump because it's slower (requires data size
926 prefix), and doesn't work, unless the destination is in the bottom
927 64k of the code segment (The top 16 bits of eip are zeroed). */
929 const relax_typeS md_relax_table
[] =
932 1) most positive reach of this state,
933 2) most negative reach of this state,
934 3) how many bytes this mode will have in the variable part of the frag
935 4) which index into the table to try if we can't fit into this one. */
937 /* UNCOND_JUMP states. */
938 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
939 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
940 /* dword jmp adds 4 bytes to frag:
941 0 extra opcode bytes, 4 displacement bytes. */
943 /* word jmp adds 2 byte2 to frag:
944 0 extra opcode bytes, 2 displacement bytes. */
947 /* COND_JUMP states. */
948 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
949 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
950 /* dword conditionals adds 5 bytes to frag:
951 1 extra opcode byte, 4 displacement bytes. */
953 /* word conditionals add 3 bytes to frag:
954 1 extra opcode byte, 2 displacement bytes. */
957 /* COND_JUMP86 states. */
958 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
959 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
960 /* dword conditionals adds 5 bytes to frag:
961 1 extra opcode byte, 4 displacement bytes. */
963 /* word conditionals add 4 bytes to frag:
964 1 displacement byte and a 3 byte long branch insn. */
968 #define ARCH(n, t, f, s) \
969 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
971 #define SUBARCH(n, e, d, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
973 CPU_ ## d ## _FLAGS }
974 #define VECARCH(n, e, d, v) \
975 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
976 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
978 static const arch_entry cpu_arch
[] =
980 /* Do not replace the first two entries - i386_target_format() and
981 set_cpu_arch() rely on them being there in this order. */
982 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
983 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
984 ARCH (i8086
, UNKNOWN
, NONE
, false),
985 ARCH (i186
, UNKNOWN
, 186, false),
986 ARCH (i286
, UNKNOWN
, 286, false),
987 ARCH (i386
, I386
, 386, false),
988 ARCH (i486
, I486
, 486, false),
989 ARCH (i586
, PENTIUM
, 586, false),
990 ARCH (i686
, PENTIUMPRO
, 686, false),
991 ARCH (pentium
, PENTIUM
, 586, false),
992 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
993 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
994 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
995 ARCH (pentium4
, PENTIUM4
, P4
, false),
996 ARCH (prescott
, NOCONA
, CORE
, false),
997 ARCH (nocona
, NOCONA
, NOCONA
, false),
998 ARCH (yonah
, CORE
, CORE
, true),
999 ARCH (core
, CORE
, CORE
, false),
1000 ARCH (merom
, CORE2
, CORE2
, true),
1001 ARCH (core2
, CORE2
, CORE2
, false),
1002 ARCH (corei7
, COREI7
, COREI7
, false),
1003 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1004 ARCH (k6
, K6
, K6
, false),
1005 ARCH (k6_2
, K6
, K6_2
, false),
1006 ARCH (athlon
, ATHLON
, ATHLON
, false),
1007 ARCH (sledgehammer
, K8
, K8
, true),
1008 ARCH (opteron
, K8
, K8
, false),
1009 ARCH (k8
, K8
, K8
, false),
1010 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1011 ARCH (bdver1
, BD
, BDVER1
, false),
1012 ARCH (bdver2
, BD
, BDVER2
, false),
1013 ARCH (bdver3
, BD
, BDVER3
, false),
1014 ARCH (bdver4
, BD
, BDVER4
, false),
1015 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1016 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1017 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1018 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1019 ARCH (btver1
, BT
, BTVER1
, false),
1020 ARCH (btver2
, BT
, BTVER2
, false),
1022 SUBARCH (8087, 8087, ANY_8087
, false),
1023 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1024 SUBARCH (287, 287, ANY_287
, false),
1025 SUBARCH (387, 387, ANY_387
, false),
1026 SUBARCH (687, 687, ANY_687
, false),
1027 SUBARCH (cmov
, CMOV
, CMOV
, false),
1028 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1029 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1030 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1031 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1032 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1033 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1034 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1035 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1036 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1037 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1038 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1039 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1040 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1041 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1042 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1043 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1044 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1045 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1046 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1047 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1048 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1049 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1050 SUBARCH (smx
, SMX
, SMX
, false),
1051 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1052 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1053 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1054 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1055 SUBARCH (aes
, AES
, ANY_AES
, false),
1056 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1057 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1058 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1059 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1060 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1061 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1062 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1063 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1064 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1065 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1066 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1067 SUBARCH (cx16
, CX16
, CX16
, false),
1068 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1069 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1070 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1071 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1072 SUBARCH (hle
, HLE
, HLE
, false),
1073 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1074 SUBARCH (tsx
, TSX
, TSX
, false),
1075 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1076 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1077 SUBARCH (nop
, NOP
, NOP
, false),
1078 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1079 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1080 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1081 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1082 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1083 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1084 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1085 SUBARCH (abm
, ABM
, ABM
, false),
1086 SUBARCH (bmi
, BMI
, BMI
, false),
1087 SUBARCH (tbm
, TBM
, TBM
, false),
1088 SUBARCH (adx
, ADX
, ADX
, false),
1089 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1090 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1091 SUBARCH (smap
, SMAP
, SMAP
, false),
1092 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1093 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1094 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1095 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1096 SUBARCH (se1
, SE1
, SE1
, false),
1097 SUBARCH (clwb
, CLWB
, CLWB
, false),
1098 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1099 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1100 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1101 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1102 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1103 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1104 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1105 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1106 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1107 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1108 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1109 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1110 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1111 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1112 SUBARCH (ibt
, IBT
, IBT
, false),
1113 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1114 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1115 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1116 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1117 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1118 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1119 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1120 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1121 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1122 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1123 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1124 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1125 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1126 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1127 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1128 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1129 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1130 ANY_AVX512_VP2INTERSECT
, reset
),
1131 SUBARCH (tdx
, TDX
, TDX
, false),
1132 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1133 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1134 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1135 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1136 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1137 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1138 SUBARCH (kl
, KL
, ANY_KL
, false),
1139 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1140 SUBARCH (uintr
, UINTR
, UINTR
, false),
1141 SUBARCH (hreset
, HRESET
, HRESET
, false),
1142 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1143 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1144 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1145 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1146 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1147 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1148 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1149 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1150 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1151 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1152 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1153 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1154 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1155 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1156 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1157 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1158 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1159 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1166 /* Like s_lcomm_internal in gas/read.c but the alignment string
1167 is allowed to be optional. */
1170 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1177 && *input_line_pointer
== ',')
1179 align
= parse_align (needs_align
- 1);
1181 if (align
== (addressT
) -1)
1196 bss_alloc (symbolP
, size
, align
);
1201 pe_lcomm (int needs_align
)
1203 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1207 const pseudo_typeS md_pseudo_table
[] =
1209 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1210 {"align", s_align_bytes
, 0},
1212 {"align", s_align_ptwo
, 0},
1214 {"arch", set_cpu_arch
, 0},
1218 {"lcomm", pe_lcomm
, 1},
1220 {"ffloat", float_cons
, 'f'},
1221 {"dfloat", float_cons
, 'd'},
1222 {"tfloat", float_cons
, 'x'},
1223 {"hfloat", float_cons
, 'h'},
1224 {"bfloat16", float_cons
, 'b'},
1226 {"slong", signed_cons
, 4},
1227 {"insn", s_insn
, 0},
1228 {"noopt", s_ignore
, 0},
1229 {"optim", s_ignore
, 0},
1230 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1231 {"code16", set_code_flag
, CODE_16BIT
},
1232 {"code32", set_code_flag
, CODE_32BIT
},
1234 {"code64", set_code_flag
, CODE_64BIT
},
1236 {"intel_syntax", set_intel_syntax
, 1},
1237 {"att_syntax", set_intel_syntax
, 0},
1238 {"intel_mnemonic", set_intel_mnemonic
, 1},
1239 {"att_mnemonic", set_intel_mnemonic
, 0},
1240 {"allow_index_reg", set_allow_index_reg
, 1},
1241 {"disallow_index_reg", set_allow_index_reg
, 0},
1242 {"sse_check", set_check
, 0},
1243 {"operand_check", set_check
, 1},
1244 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1245 {"largecomm", handle_large_common
, 0},
1247 {"file", dwarf2_directive_file
, 0},
1248 {"loc", dwarf2_directive_loc
, 0},
1249 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1252 {"secrel32", pe_directive_secrel
, 0},
1253 {"secidx", pe_directive_secidx
, 0},
1258 /* For interface with expression (). */
1259 extern char *input_line_pointer
;
1261 /* Hash table for instruction mnemonic lookup. */
1262 static htab_t op_hash
;
1264 /* Hash table for register lookup. */
1265 static htab_t reg_hash
;
1267 /* Various efficient no-op patterns for aligning code labels.
1268 Note: Don't try to assemble the instructions in the comments.
1269 0L and 0w are not legal. */
1270 static const unsigned char f32_1
[] =
1272 static const unsigned char f32_2
[] =
1273 {0x66,0x90}; /* xchg %ax,%ax */
1274 static const unsigned char f32_3
[] =
1275 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1276 static const unsigned char f32_4
[] =
1277 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1278 static const unsigned char f32_6
[] =
1279 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1280 static const unsigned char f32_7
[] =
1281 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1282 static const unsigned char f64_3
[] =
1283 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1284 static const unsigned char f64_4
[] =
1285 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1286 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1287 static const unsigned char f64_6
[] =
1288 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1289 static const unsigned char f64_7
[] =
1290 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1291 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1292 static const unsigned char f64_9
[] =
1293 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1294 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1295 static const unsigned char f16_3
[] =
1296 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1297 static const unsigned char f16_4
[] =
1298 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1299 static const unsigned char jump_disp8
[] =
1300 {0xeb}; /* jmp disp8 */
1301 static const unsigned char jump32_disp32
[] =
1302 {0xe9}; /* jmp disp32 */
1303 static const unsigned char jump16_disp32
[] =
1304 {0x66,0xe9}; /* jmp disp32 */
1305 /* 32-bit NOPs patterns. */
1306 static const unsigned char *const f32_patt
[] = {
1307 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1309 /* 64-bit NOPs patterns. */
1310 static const unsigned char *const f64_patt
[] = {
1311 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1313 /* 16-bit NOPs patterns. */
1314 static const unsigned char *const f16_patt
[] = {
1315 f32_1
, f16_2
, f16_3
, f16_4
1317 /* nopl (%[re]ax) */
1318 static const unsigned char alt_3
[] =
1320 /* nopl 0(%[re]ax) */
1321 static const unsigned char alt_4
[] =
1322 {0x0f,0x1f,0x40,0x00};
1323 /* nopl 0(%[re]ax,%[re]ax,1) */
1324 static const unsigned char alt_5
[] =
1325 {0x0f,0x1f,0x44,0x00,0x00};
1326 /* nopw 0(%[re]ax,%[re]ax,1) */
1327 static const unsigned char alt_6
[] =
1328 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1329 /* nopl 0L(%[re]ax) */
1330 static const unsigned char alt_7
[] =
1331 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1332 /* nopl 0L(%[re]ax,%[re]ax,1) */
1333 static const unsigned char alt_8
[] =
1334 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1335 /* nopw 0L(%[re]ax,%[re]ax,1) */
1336 static const unsigned char alt_9
[] =
1337 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1338 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1339 static const unsigned char alt_10
[] =
1340 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1341 /* data16 nopw %cs:0L(%eax,%eax,1) */
1342 static const unsigned char alt_11
[] =
1343 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1344 /* 32-bit and 64-bit NOPs patterns. */
1345 static const unsigned char *const alt_patt
[] = {
1346 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1347 alt_9
, alt_10
, alt_11
1350 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1351 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1354 i386_output_nops (char *where
, const unsigned char *const *patt
,
1355 int count
, int max_single_nop_size
)
1358 /* Place the longer NOP first. */
1361 const unsigned char *nops
;
1363 if (max_single_nop_size
< 1)
1365 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1366 max_single_nop_size
);
1370 nops
= patt
[max_single_nop_size
- 1];
1372 /* Use the smaller one if the requsted one isn't available. */
1375 max_single_nop_size
--;
1376 nops
= patt
[max_single_nop_size
- 1];
1379 last
= count
% max_single_nop_size
;
1382 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1383 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1387 nops
= patt
[last
- 1];
1390 /* Use the smaller one plus one-byte NOP if the needed one
1393 nops
= patt
[last
- 1];
1394 memcpy (where
+ offset
, nops
, last
);
1395 where
[offset
+ last
] = *patt
[0];
1398 memcpy (where
+ offset
, nops
, last
);
1403 fits_in_imm7 (offsetT num
)
1405 return (num
& 0x7f) == num
;
1409 fits_in_imm31 (offsetT num
)
1411 return (num
& 0x7fffffff) == num
;
1414 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1415 single NOP instruction LIMIT. */
1418 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1420 const unsigned char *const *patt
= NULL
;
1421 int max_single_nop_size
;
1422 /* Maximum number of NOPs before switching to jump over NOPs. */
1423 int max_number_of_nops
;
1425 switch (fragP
->fr_type
)
1430 case rs_machine_dependent
:
1431 /* Allow NOP padding for jumps and calls. */
1432 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1433 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1440 /* We need to decide which NOP sequence to use for 32bit and
1441 64bit. When -mtune= is used:
1443 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1444 PROCESSOR_GENERIC32, f32_patt will be used.
1445 2. For the rest, alt_patt will be used.
1447 When -mtune= isn't used, alt_patt will be used if
1448 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1451 When -march= or .arch is used, we can't use anything beyond
1452 cpu_arch_isa_flags. */
1454 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1457 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1458 /* Limit number of NOPs to 2 in 16-bit mode. */
1459 max_number_of_nops
= 2;
1463 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1464 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1466 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1467 explicitly disabled. */
1468 switch (fragP
->tc_frag_data
.tune
)
1470 case PROCESSOR_UNKNOWN
:
1471 /* We use cpu_arch_isa_flags to check if we SHOULD
1472 optimize with nops. */
1473 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1476 case PROCESSOR_PENTIUM4
:
1477 case PROCESSOR_NOCONA
:
1478 case PROCESSOR_CORE
:
1479 case PROCESSOR_CORE2
:
1480 case PROCESSOR_COREI7
:
1481 case PROCESSOR_GENERIC64
:
1483 case PROCESSOR_ATHLON
:
1485 case PROCESSOR_AMDFAM10
:
1487 case PROCESSOR_ZNVER
:
1489 if (fragP
->tc_frag_data
.cpunop
)
1493 case PROCESSOR_I386
:
1494 case PROCESSOR_I486
:
1495 case PROCESSOR_PENTIUM
:
1496 case PROCESSOR_PENTIUMPRO
:
1497 case PROCESSOR_IAMCU
:
1498 case PROCESSOR_GENERIC32
:
1500 case PROCESSOR_NONE
:
1506 switch (fragP
->tc_frag_data
.tune
)
1508 case PROCESSOR_UNKNOWN
:
1509 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1510 PROCESSOR_UNKNOWN. */
1515 /* We use cpu_arch_isa_flags to check if we CAN optimize
1517 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1521 case PROCESSOR_NONE
:
1526 if (patt
!= alt_patt
)
1528 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1529 : ARRAY_SIZE (f64_patt
);
1530 /* Limit number of NOPs to 2 for older processors. */
1531 max_number_of_nops
= 2;
1535 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1536 /* Limit number of NOPs to 7 for newer processors. */
1537 max_number_of_nops
= 7;
1542 limit
= max_single_nop_size
;
1544 if (fragP
->fr_type
== rs_fill_nop
)
1546 /* Output NOPs for .nop directive. */
1547 if (limit
> max_single_nop_size
)
1549 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1550 _("invalid single nop size: %d "
1551 "(expect within [0, %d])"),
1552 limit
, max_single_nop_size
);
1556 else if (fragP
->fr_type
!= rs_machine_dependent
)
1557 fragP
->fr_var
= count
;
1559 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1561 /* Generate jump over NOPs. */
1562 offsetT disp
= count
- 2;
1563 if (fits_in_imm7 (disp
))
1565 /* Use "jmp disp8" if possible. */
1567 where
[0] = jump_disp8
[0];
1573 unsigned int size_of_jump
;
1575 if (flag_code
== CODE_16BIT
)
1577 where
[0] = jump16_disp32
[0];
1578 where
[1] = jump16_disp32
[1];
1583 where
[0] = jump32_disp32
[0];
1587 count
-= size_of_jump
+ 4;
1588 if (!fits_in_imm31 (count
))
1590 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1591 _("jump over nop padding out of range"));
1595 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1596 where
+= size_of_jump
+ 4;
1600 /* Generate multiple NOPs. */
1601 i386_output_nops (where
, patt
, count
, limit
);
1605 operand_type_all_zero (const union i386_operand_type
*x
)
1607 switch (ARRAY_SIZE(x
->array
))
1618 return !x
->array
[0];
1625 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1627 switch (ARRAY_SIZE(x
->array
))
1643 x
->bitfield
.class = ClassNone
;
1644 x
->bitfield
.instance
= InstanceNone
;
1648 operand_type_equal (const union i386_operand_type
*x
,
1649 const union i386_operand_type
*y
)
1651 switch (ARRAY_SIZE(x
->array
))
1654 if (x
->array
[2] != y
->array
[2])
1658 if (x
->array
[1] != y
->array
[1])
1662 return x
->array
[0] == y
->array
[0];
1670 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1674 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1675 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1676 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1677 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1678 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1679 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1680 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1681 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1682 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1683 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1685 gas_assert (cpu
< CpuAttrEnums
);
1687 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1690 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1692 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1693 i386_cpu_flags f
= { .array
[0] = 0 };
1695 switch (ARRAY_SIZE(a
.array
))
1698 f
.array
[CpuAttrEnums
/ bps
]
1699 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1700 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1701 f
.array
[CpuAttrEnums
/ bps
+ 1]
1702 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1709 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1715 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1717 switch (ARRAY_SIZE(x
->array
))
1736 return !x
->array
[0];
1743 cpu_flags_equal (const union i386_cpu_flags
*x
,
1744 const union i386_cpu_flags
*y
)
1746 switch (ARRAY_SIZE(x
->array
))
1749 if (x
->array
[4] != y
->array
[4])
1753 if (x
->array
[3] != y
->array
[3])
1757 if (x
->array
[2] != y
->array
[2])
1761 if (x
->array
[1] != y
->array
[1])
1765 return x
->array
[0] == y
->array
[0];
1773 cpu_flags_check_cpu64 (const insn_template
*t
)
1775 return flag_code
== CODE_64BIT
1776 ? !t
->cpu
.bitfield
.cpuno64
1777 : !t
->cpu
.bitfield
.cpu64
;
1780 static INLINE i386_cpu_flags
1781 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1783 switch (ARRAY_SIZE (x
.array
))
1786 x
.array
[4] &= y
.array
[4];
1789 x
.array
[3] &= y
.array
[3];
1792 x
.array
[2] &= y
.array
[2];
1795 x
.array
[1] &= y
.array
[1];
1798 x
.array
[0] &= y
.array
[0];
1806 static INLINE i386_cpu_flags
1807 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1809 switch (ARRAY_SIZE (x
.array
))
1812 x
.array
[4] |= y
.array
[4];
1815 x
.array
[3] |= y
.array
[3];
1818 x
.array
[2] |= y
.array
[2];
1821 x
.array
[1] |= y
.array
[1];
1824 x
.array
[0] |= y
.array
[0];
1832 static INLINE i386_cpu_flags
1833 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1835 switch (ARRAY_SIZE (x
.array
))
1838 x
.array
[4] &= ~y
.array
[4];
1841 x
.array
[3] &= ~y
.array
[3];
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1860 static INLINE
bool need_evex_encoding (void)
1862 return i
.vec_encoding
== vex_encoding_evex
1863 || i
.vec_encoding
== vex_encoding_evex512
1867 #define CPU_FLAGS_ARCH_MATCH 0x1
1868 #define CPU_FLAGS_64BIT_MATCH 0x2
1870 #define CPU_FLAGS_PERFECT_MATCH \
1871 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1873 /* Return CPU flags match bits. */
1876 cpu_flags_match (const insn_template
*t
)
1878 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1879 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1881 x
.bitfield
.cpu64
= 0;
1882 x
.bitfield
.cpuno64
= 0;
1884 if (cpu_flags_all_zero (&x
))
1886 /* This instruction is available on all archs. */
1887 match
|= CPU_FLAGS_ARCH_MATCH
;
1891 /* This instruction is available only on some archs. */
1892 i386_cpu_flags cpu
= cpu_arch_flags
;
1894 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1895 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1897 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1898 know that EVEX encoding will be needed. */
1899 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1900 && x
.bitfield
.cpuavx512f
)
1902 if (need_evex_encoding ())
1904 x
.bitfield
.cpuavx
= 0;
1905 x
.bitfield
.cpuavx2
= 0;
1907 /* need_evex_encoding() isn't reliable before operands were
1909 else if (i
.operands
)
1911 x
.bitfield
.cpuavx512f
= 0;
1912 x
.bitfield
.cpuavx512vl
= 0;
1913 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1914 x
.bitfield
.cpuavx
= 0;
1919 /* AVX512VL is no standalone feature - match it and then strip it. */
1920 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1922 x
.bitfield
.cpuavx512vl
= 0;
1924 /* AVX and AVX2 present at the same time express an operand size
1925 dependency - strip AVX2 for the purposes here. The operand size
1926 dependent check occurs in check_vecOperands(). */
1927 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1928 x
.bitfield
.cpuavx2
= 0;
1930 cpu
= cpu_flags_and (x
, cpu
);
1931 if (!cpu_flags_all_zero (&cpu
))
1933 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1935 if ((need_evex_encoding ()
1936 ? cpu
.bitfield
.cpuavx512f
1937 : cpu
.bitfield
.cpuavx
)
1938 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1939 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1940 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1941 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1942 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1943 match
|= CPU_FLAGS_ARCH_MATCH
;
1945 else if (x
.bitfield
.cpuavx
)
1947 /* We need to check a few extra flags with AVX. */
1948 if (cpu
.bitfield
.cpuavx
1949 && (!t
->opcode_modifier
.sse2avx
1950 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1951 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1952 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1953 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1954 match
|= CPU_FLAGS_ARCH_MATCH
;
1956 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1957 match
|= CPU_FLAGS_ARCH_MATCH
;
1958 else if (x
.bitfield
.cpuavx512f
)
1960 /* We need to check a few extra flags with AVX512F. */
1961 if (cpu
.bitfield
.cpuavx512f
1962 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1966 match
|= CPU_FLAGS_ARCH_MATCH
;
1972 static INLINE i386_operand_type
1973 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1975 if (x
.bitfield
.class != y
.bitfield
.class)
1976 x
.bitfield
.class = ClassNone
;
1977 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1978 x
.bitfield
.instance
= InstanceNone
;
1980 switch (ARRAY_SIZE (x
.array
))
1983 x
.array
[2] &= y
.array
[2];
1986 x
.array
[1] &= y
.array
[1];
1989 x
.array
[0] &= y
.array
[0];
1997 static INLINE i386_operand_type
1998 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2000 gas_assert (y
.bitfield
.class == ClassNone
);
2001 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2003 switch (ARRAY_SIZE (x
.array
))
2006 x
.array
[2] &= ~y
.array
[2];
2009 x
.array
[1] &= ~y
.array
[1];
2012 x
.array
[0] &= ~y
.array
[0];
2020 static INLINE i386_operand_type
2021 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2023 gas_assert (x
.bitfield
.class == ClassNone
||
2024 y
.bitfield
.class == ClassNone
||
2025 x
.bitfield
.class == y
.bitfield
.class);
2026 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2027 y
.bitfield
.instance
== InstanceNone
||
2028 x
.bitfield
.instance
== y
.bitfield
.instance
);
2030 switch (ARRAY_SIZE (x
.array
))
2033 x
.array
[2] |= y
.array
[2];
2036 x
.array
[1] |= y
.array
[1];
2039 x
.array
[0] |= y
.array
[0];
2047 static INLINE i386_operand_type
2048 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2050 gas_assert (y
.bitfield
.class == ClassNone
);
2051 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2053 switch (ARRAY_SIZE (x
.array
))
2056 x
.array
[2] ^= y
.array
[2];
2059 x
.array
[1] ^= y
.array
[1];
2062 x
.array
[0] ^= y
.array
[0];
2070 static const i386_operand_type anydisp
= {
2071 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2083 operand_type_check (i386_operand_type t
, enum operand_type c
)
2088 return t
.bitfield
.class == Reg
;
2091 return (t
.bitfield
.imm8
2095 || t
.bitfield
.imm32s
2096 || t
.bitfield
.imm64
);
2099 return (t
.bitfield
.disp8
2100 || t
.bitfield
.disp16
2101 || t
.bitfield
.disp32
2102 || t
.bitfield
.disp64
);
2105 return (t
.bitfield
.disp8
2106 || t
.bitfield
.disp16
2107 || t
.bitfield
.disp32
2108 || t
.bitfield
.disp64
2109 || t
.bitfield
.baseindex
);
2118 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2119 between operand GIVEN and opeand WANTED for instruction template T. */
2122 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2125 return !((i
.types
[given
].bitfield
.byte
2126 && !t
->operand_types
[wanted
].bitfield
.byte
)
2127 || (i
.types
[given
].bitfield
.word
2128 && !t
->operand_types
[wanted
].bitfield
.word
)
2129 || (i
.types
[given
].bitfield
.dword
2130 && !t
->operand_types
[wanted
].bitfield
.dword
)
2131 || (i
.types
[given
].bitfield
.qword
2132 && (!t
->operand_types
[wanted
].bitfield
.qword
2133 /* Don't allow 64-bit (memory) operands outside of 64-bit
2134 mode, when they're used where a 64-bit GPR could also
2135 be used. Checking is needed for Intel Syntax only. */
2137 && flag_code
!= CODE_64BIT
2138 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2139 || t
->operand_types
[wanted
].bitfield
.class == Accum
2140 || t
->opcode_modifier
.isstring
))))
2141 || (i
.types
[given
].bitfield
.tbyte
2142 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2145 /* Return 1 if there is no conflict in SIMD register between operand
2146 GIVEN and opeand WANTED for instruction template T. */
2149 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2152 return !((i
.types
[given
].bitfield
.xmmword
2153 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2154 || (i
.types
[given
].bitfield
.ymmword
2155 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2156 || (i
.types
[given
].bitfield
.zmmword
2157 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2158 || (i
.types
[given
].bitfield
.tmmword
2159 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2162 /* Return 1 if there is no conflict in any size between operand GIVEN
2163 and opeand WANTED for instruction template T. */
2166 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2169 return (match_operand_size (t
, wanted
, given
)
2170 && !((i
.types
[given
].bitfield
.unspecified
2171 && !i
.broadcast
.type
2172 && !i
.broadcast
.bytes
2173 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2174 || (i
.types
[given
].bitfield
.fword
2175 && !t
->operand_types
[wanted
].bitfield
.fword
)
2176 /* For scalar opcode templates to allow register and memory
2177 operands at the same time, some special casing is needed
2178 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2179 down-conversion vpmov*. */
2180 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2181 && t
->operand_types
[wanted
].bitfield
.byte
2182 + t
->operand_types
[wanted
].bitfield
.word
2183 + t
->operand_types
[wanted
].bitfield
.dword
2184 + t
->operand_types
[wanted
].bitfield
.qword
2185 > !!t
->opcode_modifier
.broadcast
)
2186 ? (i
.types
[given
].bitfield
.xmmword
2187 || i
.types
[given
].bitfield
.ymmword
2188 || i
.types
[given
].bitfield
.zmmword
)
2189 : !match_simd_size(t
, wanted
, given
))));
2192 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2193 operands for instruction template T, and it has MATCH_REVERSE set if there
2194 is no size conflict on any operands for the template with operands reversed
2195 (and the template allows for reversing in the first place). */
2197 #define MATCH_STRAIGHT 1
2198 #define MATCH_REVERSE 2
2200 static INLINE
unsigned int
2201 operand_size_match (const insn_template
*t
)
2203 unsigned int j
, match
= MATCH_STRAIGHT
;
2205 /* Don't check non-absolute jump instructions. */
2206 if (t
->opcode_modifier
.jump
2207 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2210 /* Check memory and accumulator operand size. */
2211 for (j
= 0; j
< i
.operands
; j
++)
2213 if (i
.types
[j
].bitfield
.class != Reg
2214 && i
.types
[j
].bitfield
.class != RegSIMD
2215 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2218 if (t
->operand_types
[j
].bitfield
.class == Reg
2219 && !match_operand_size (t
, j
, j
))
2225 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2226 && !match_simd_size (t
, j
, j
))
2232 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2233 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2239 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2246 if (!t
->opcode_modifier
.d
)
2249 /* Check reverse. */
2250 gas_assert (i
.operands
>= 2);
2252 for (j
= 0; j
< i
.operands
; j
++)
2254 unsigned int given
= i
.operands
- j
- 1;
2256 /* For FMA4 and XOP insns VEX.W controls just the first two
2257 register operands. */
2258 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2259 given
= j
< 2 ? 1 - j
: j
;
2261 if (t
->operand_types
[j
].bitfield
.class == Reg
2262 && !match_operand_size (t
, j
, given
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, given
))
2269 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2270 && (!match_operand_size (t
, j
, given
)
2271 || !match_simd_size (t
, j
, given
)))
2274 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2278 return match
| MATCH_REVERSE
;
2282 operand_type_match (i386_operand_type overlap
,
2283 i386_operand_type given
)
2285 i386_operand_type temp
= overlap
;
2287 temp
.bitfield
.unspecified
= 0;
2288 temp
.bitfield
.byte
= 0;
2289 temp
.bitfield
.word
= 0;
2290 temp
.bitfield
.dword
= 0;
2291 temp
.bitfield
.fword
= 0;
2292 temp
.bitfield
.qword
= 0;
2293 temp
.bitfield
.tbyte
= 0;
2294 temp
.bitfield
.xmmword
= 0;
2295 temp
.bitfield
.ymmword
= 0;
2296 temp
.bitfield
.zmmword
= 0;
2297 temp
.bitfield
.tmmword
= 0;
2298 if (operand_type_all_zero (&temp
))
2301 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2305 i
.error
= operand_type_mismatch
;
2309 /* If given types g0 and g1 are registers they must be of the same type
2310 unless the expected operand type register overlap is null.
2311 Intel syntax sized memory operands are also checked here. */
2314 operand_type_register_match (i386_operand_type g0
,
2315 i386_operand_type t0
,
2316 i386_operand_type g1
,
2317 i386_operand_type t1
)
2319 if (g0
.bitfield
.class != Reg
2320 && g0
.bitfield
.class != RegSIMD
2321 && (g0
.bitfield
.unspecified
2322 || !operand_type_check (g0
, anymem
)))
2325 if (g1
.bitfield
.class != Reg
2326 && g1
.bitfield
.class != RegSIMD
2327 && (g1
.bitfield
.unspecified
2328 || !operand_type_check (g1
, anymem
)))
2331 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2332 && g0
.bitfield
.word
== g1
.bitfield
.word
2333 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2334 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2335 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2336 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2337 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2340 /* If expectations overlap in no more than a single size, all is fine. */
2341 g0
= operand_type_and (t0
, t1
);
2342 if (g0
.bitfield
.byte
2346 + g0
.bitfield
.xmmword
2347 + g0
.bitfield
.ymmword
2348 + g0
.bitfield
.zmmword
<= 1)
2351 i
.error
= register_type_mismatch
;
2356 static INLINE
unsigned int
2357 register_number (const reg_entry
*r
)
2359 unsigned int nr
= r
->reg_num
;
2361 if (r
->reg_flags
& RegRex
)
2364 if (r
->reg_flags
& RegVRex
)
2370 static INLINE
unsigned int
2371 mode_from_disp_size (i386_operand_type t
)
2373 if (t
.bitfield
.disp8
)
2375 else if (t
.bitfield
.disp16
2376 || t
.bitfield
.disp32
)
2383 fits_in_signed_byte (addressT num
)
2385 return num
+ 0x80 <= 0xff;
2389 fits_in_unsigned_byte (addressT num
)
2395 fits_in_unsigned_word (addressT num
)
2397 return num
<= 0xffff;
2401 fits_in_signed_word (addressT num
)
2403 return num
+ 0x8000 <= 0xffff;
2407 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2412 return num
+ 0x80000000 <= 0xffffffff;
2414 } /* fits_in_signed_long() */
2417 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2422 return num
<= 0xffffffff;
2424 } /* fits_in_unsigned_long() */
2426 static INLINE valueT
extend_to_32bit_address (addressT num
)
2429 if (fits_in_unsigned_long(num
))
2430 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2432 if (!fits_in_signed_long (num
))
2433 return num
& 0xffffffff;
2440 fits_in_disp8 (offsetT num
)
2442 int shift
= i
.memshift
;
2448 mask
= (1 << shift
) - 1;
2450 /* Return 0 if NUM isn't properly aligned. */
2454 /* Check if NUM will fit in 8bit after shift. */
2455 return fits_in_signed_byte (num
>> shift
);
2459 fits_in_imm4 (offsetT num
)
2461 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2462 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2465 static i386_operand_type
2466 smallest_imm_type (offsetT num
)
2468 i386_operand_type t
;
2470 operand_type_set (&t
, 0);
2471 t
.bitfield
.imm64
= 1;
2473 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2475 /* This code is disabled on the 486 because all the Imm1 forms
2476 in the opcode table are slower on the i486. They're the
2477 versions with the implicitly specified single-position
2478 displacement, which has another syntax if you really want to
2480 t
.bitfield
.imm1
= 1;
2481 t
.bitfield
.imm8
= 1;
2482 t
.bitfield
.imm8s
= 1;
2483 t
.bitfield
.imm16
= 1;
2484 t
.bitfield
.imm32
= 1;
2485 t
.bitfield
.imm32s
= 1;
2487 else if (fits_in_signed_byte (num
))
2489 if (fits_in_unsigned_byte (num
))
2490 t
.bitfield
.imm8
= 1;
2491 t
.bitfield
.imm8s
= 1;
2492 t
.bitfield
.imm16
= 1;
2493 t
.bitfield
.imm32
= 1;
2494 t
.bitfield
.imm32s
= 1;
2496 else if (fits_in_unsigned_byte (num
))
2498 t
.bitfield
.imm8
= 1;
2499 t
.bitfield
.imm16
= 1;
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2505 t
.bitfield
.imm16
= 1;
2506 t
.bitfield
.imm32
= 1;
2507 t
.bitfield
.imm32s
= 1;
2509 else if (fits_in_signed_long (num
))
2511 t
.bitfield
.imm32
= 1;
2512 t
.bitfield
.imm32s
= 1;
2514 else if (fits_in_unsigned_long (num
))
2515 t
.bitfield
.imm32
= 1;
2521 offset_in_range (offsetT val
, int size
)
2527 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2528 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2530 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2532 case sizeof (val
): return val
;
2536 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2537 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2538 (uint64_t) val
, (uint64_t) (val
& mask
));
2543 static INLINE
const char *insn_name (const insn_template
*t
)
2545 return &i386_mnemonics
[t
->mnem_off
];
2558 a. PREFIX_EXIST if attempting to add a prefix where one from the
2559 same class already exists.
2560 b. PREFIX_LOCK if lock prefix is added.
2561 c. PREFIX_REP if rep/repne prefix is added.
2562 d. PREFIX_DS if ds prefix is added.
2563 e. PREFIX_OTHER if other prefix is added.
2566 static enum PREFIX_GROUP
2567 add_prefix (unsigned int prefix
)
2569 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2572 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2573 && flag_code
== CODE_64BIT
)
2575 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2576 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2577 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2578 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2589 case DS_PREFIX_OPCODE
:
2592 case CS_PREFIX_OPCODE
:
2593 case ES_PREFIX_OPCODE
:
2594 case FS_PREFIX_OPCODE
:
2595 case GS_PREFIX_OPCODE
:
2596 case SS_PREFIX_OPCODE
:
2600 case REPNE_PREFIX_OPCODE
:
2601 case REPE_PREFIX_OPCODE
:
2606 case LOCK_PREFIX_OPCODE
:
2615 case ADDR_PREFIX_OPCODE
:
2619 case DATA_PREFIX_OPCODE
:
2623 if (i
.prefix
[q
] != 0)
2631 i
.prefix
[q
] |= prefix
;
2634 as_bad (_("same type of prefix used twice"));
2640 update_code_flag (int value
, int check
)
2642 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2644 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2646 as_error (_("64bit mode not supported on `%s'."),
2647 cpu_arch_name
? cpu_arch_name
: default_arch
);
2651 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2653 as_error (_("32bit mode not supported on `%s'."),
2654 cpu_arch_name
? cpu_arch_name
: default_arch
);
2658 flag_code
= (enum flag_code
) value
;
2660 stackop_size
= '\0';
2664 set_code_flag (int value
)
2666 update_code_flag (value
, 0);
2670 set_16bit_gcc_code_flag (int new_code_flag
)
2672 flag_code
= (enum flag_code
) new_code_flag
;
2673 if (flag_code
!= CODE_16BIT
)
2675 stackop_size
= LONG_MNEM_SUFFIX
;
2679 set_intel_syntax (int syntax_flag
)
2681 /* Find out if register prefixing is specified. */
2682 int ask_naked_reg
= 0;
2685 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2688 int e
= get_symbol_name (&string
);
2690 if (strcmp (string
, "prefix") == 0)
2692 else if (strcmp (string
, "noprefix") == 0)
2695 as_bad (_("bad argument to syntax directive."));
2696 (void) restore_line_pointer (e
);
2698 demand_empty_rest_of_line ();
2700 intel_syntax
= syntax_flag
;
2702 if (ask_naked_reg
== 0)
2703 allow_naked_reg
= (intel_syntax
2704 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2706 allow_naked_reg
= (ask_naked_reg
< 0);
2708 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2710 register_prefix
= allow_naked_reg
? "" : "%";
2714 set_intel_mnemonic (int mnemonic_flag
)
2716 intel_mnemonic
= mnemonic_flag
;
2720 set_allow_index_reg (int flag
)
2722 allow_index_reg
= flag
;
2726 set_check (int what
)
2728 enum check_kind
*kind
;
2733 kind
= &operand_check
;
2744 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2747 int e
= get_symbol_name (&string
);
2749 if (strcmp (string
, "none") == 0)
2751 else if (strcmp (string
, "warning") == 0)
2752 *kind
= check_warning
;
2753 else if (strcmp (string
, "error") == 0)
2754 *kind
= check_error
;
2756 as_bad (_("bad argument to %s_check directive."), str
);
2757 (void) restore_line_pointer (e
);
2760 as_bad (_("missing argument for %s_check directive"), str
);
2762 demand_empty_rest_of_line ();
2766 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2767 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2770 static const char *arch
;
2772 /* Intel MCU is only supported on ELF. */
2778 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2779 use default_arch. */
2780 arch
= cpu_arch_name
;
2782 arch
= default_arch
;
2785 /* If we are targeting Intel MCU, we must enable it. */
2786 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2787 == new_flag
.bitfield
.cpuiamcu
)
2790 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2795 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2797 if (cpu_sub_arch_name
)
2798 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2799 pfx
, name
, (const char *) NULL
);
2801 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2804 static void isa_enable (unsigned int idx
)
2806 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2808 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2810 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2811 cpu_arch_flags
= flags
;
2814 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2817 static void isa_disable (unsigned int idx
)
2819 i386_cpu_flags flags
2820 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2822 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2824 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2825 cpu_arch_flags
= flags
;
2829 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2833 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2835 typedef struct arch_stack_entry
2837 const struct arch_stack_entry
*prev
;
2840 i386_cpu_flags flags
;
2841 i386_cpu_flags isa_flags
;
2842 enum processor_type isa
;
2843 enum flag_code flag_code
;
2844 unsigned int vector_size
;
2846 bool no_cond_jump_promotion
;
2848 static const arch_stack_entry
*arch_stack_top
;
2856 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2858 as_bad (_("missing cpu architecture"));
2859 input_line_pointer
++;
2863 e
= get_symbol_name (&s
);
2866 if (strcmp (string
, "push") == 0)
2868 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2870 top
->name
= cpu_arch_name
;
2871 if (cpu_sub_arch_name
)
2872 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2874 top
->sub_name
= NULL
;
2875 top
->flags
= cpu_arch_flags
;
2876 top
->isa
= cpu_arch_isa
;
2877 top
->isa_flags
= cpu_arch_isa_flags
;
2878 top
->flag_code
= flag_code
;
2879 top
->vector_size
= vector_size
;
2880 top
->stackop_size
= stackop_size
;
2881 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2883 top
->prev
= arch_stack_top
;
2884 arch_stack_top
= top
;
2886 (void) restore_line_pointer (e
);
2887 demand_empty_rest_of_line ();
2891 if (strcmp (string
, "pop") == 0)
2893 const arch_stack_entry
*top
= arch_stack_top
;
2896 as_bad (_(".arch stack is empty"));
2897 else if (top
->flag_code
!= flag_code
2898 || top
->stackop_size
!= stackop_size
)
2900 static const unsigned int bits
[] = {
2906 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2907 bits
[top
->flag_code
],
2908 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2912 arch_stack_top
= top
->prev
;
2914 cpu_arch_name
= top
->name
;
2915 free (cpu_sub_arch_name
);
2916 cpu_sub_arch_name
= top
->sub_name
;
2917 cpu_arch_flags
= top
->flags
;
2918 cpu_arch_isa
= top
->isa
;
2919 cpu_arch_isa_flags
= top
->isa_flags
;
2920 vector_size
= top
->vector_size
;
2921 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2926 (void) restore_line_pointer (e
);
2927 demand_empty_rest_of_line ();
2931 if (strcmp (string
, "default") == 0)
2933 if (strcmp (default_arch
, "iamcu") == 0)
2934 string
= default_arch
;
2937 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2939 cpu_arch_name
= NULL
;
2940 free (cpu_sub_arch_name
);
2941 cpu_sub_arch_name
= NULL
;
2942 cpu_arch_flags
= cpu_unknown_flags
;
2943 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2944 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2945 if (!cpu_arch_tune_set
)
2946 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2948 vector_size
= VSZ_DEFAULT
;
2950 j
= ARRAY_SIZE (cpu_arch
) + 1;
2954 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2956 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2957 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2961 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2963 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2965 as_bad (_("64bit mode not supported on `%s'."),
2967 (void) restore_line_pointer (e
);
2968 ignore_rest_of_line ();
2972 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2974 as_bad (_("32bit mode not supported on `%s'."),
2976 (void) restore_line_pointer (e
);
2977 ignore_rest_of_line ();
2981 cpu_arch_name
= cpu_arch
[j
].name
;
2982 free (cpu_sub_arch_name
);
2983 cpu_sub_arch_name
= NULL
;
2984 cpu_arch_flags
= cpu_arch
[j
].enable
;
2985 cpu_arch_isa
= cpu_arch
[j
].type
;
2986 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2987 if (!cpu_arch_tune_set
)
2988 cpu_arch_tune
= cpu_arch_isa
;
2990 vector_size
= VSZ_DEFAULT
;
2992 pre_386_16bit_warned
= false;
2996 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
3001 (void) restore_line_pointer (e
);
3003 switch (cpu_arch
[j
].vsz
)
3009 #ifdef SVR4_COMMENT_CHARS
3010 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3012 if (*input_line_pointer
== '/')
3015 ++input_line_pointer
;
3016 switch (get_absolute_expression ())
3018 case 512: vector_size
= VSZ512
; break;
3019 case 256: vector_size
= VSZ256
; break;
3020 case 128: vector_size
= VSZ128
; break;
3022 as_bad (_("Unrecognized vector size specifier"));
3023 ignore_rest_of_line ();
3030 vector_size
= VSZ_DEFAULT
;
3034 demand_empty_rest_of_line ();
3039 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3041 /* Disable an ISA extension. */
3042 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3043 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3044 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3048 if (cpu_arch
[j
].vsz
== vsz_set
)
3049 vector_size
= VSZ_DEFAULT
;
3051 (void) restore_line_pointer (e
);
3052 demand_empty_rest_of_line ();
3057 if (j
== ARRAY_SIZE (cpu_arch
))
3058 as_bad (_("no such architecture: `%s'"), string
);
3060 *input_line_pointer
= e
;
3062 no_cond_jump_promotion
= 0;
3063 if (*input_line_pointer
== ','
3064 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3066 ++input_line_pointer
;
3067 e
= get_symbol_name (&s
);
3070 if (strcmp (string
, "nojumps") == 0)
3071 no_cond_jump_promotion
= 1;
3072 else if (strcmp (string
, "jumps") == 0)
3075 as_bad (_("no such architecture modifier: `%s'"), string
);
3077 (void) restore_line_pointer (e
);
3080 demand_empty_rest_of_line ();
3083 enum bfd_architecture
3086 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3088 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3089 || flag_code
== CODE_64BIT
)
3090 as_fatal (_("Intel MCU is 32bit ELF only"));
3091 return bfd_arch_iamcu
;
3094 return bfd_arch_i386
;
3100 if (startswith (default_arch
, "x86_64"))
3102 if (default_arch
[6] == '\0')
3103 return bfd_mach_x86_64
;
3105 return bfd_mach_x64_32
;
3107 else if (!strcmp (default_arch
, "i386")
3108 || !strcmp (default_arch
, "iamcu"))
3110 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3112 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3113 as_fatal (_("Intel MCU is 32bit ELF only"));
3114 return bfd_mach_i386_iamcu
;
3117 return bfd_mach_i386_i386
;
3120 as_fatal (_("unknown architecture"));
3123 #include "opcodes/i386-tbl.h"
3128 /* Support pseudo prefixes like {disp32}. */
3129 lex_type
['{'] = LEX_BEGIN_NAME
;
3131 /* Initialize op_hash hash table. */
3132 op_hash
= str_htab_create ();
3135 const insn_template
*const *sets
= i386_op_sets
;
3136 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3138 /* Type checks to compensate for the conversion through void * which
3139 occurs during hash table insertion / lookup. */
3140 (void) sizeof (sets
== ¤t_templates
->start
);
3141 (void) sizeof (end
== ¤t_templates
->end
);
3142 for (; sets
< end
; ++sets
)
3143 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3144 as_fatal (_("duplicate %s"), insn_name (*sets
));
3147 /* Initialize reg_hash hash table. */
3148 reg_hash
= str_htab_create ();
3150 const reg_entry
*regtab
;
3151 unsigned int regtab_size
= i386_regtab_size
;
3153 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3155 switch (regtab
->reg_type
.bitfield
.class)
3158 if (regtab
->reg_type
.bitfield
.dword
)
3160 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3163 else if (regtab
->reg_type
.bitfield
.tbyte
)
3165 /* There's no point inserting st(<N>) in the hash table, as
3166 parentheses aren't included in register_chars[] anyway. */
3167 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3174 switch (regtab
->reg_num
)
3176 case 0: reg_es
= regtab
; break;
3177 case 2: reg_ss
= regtab
; break;
3178 case 3: reg_ds
= regtab
; break;
3183 if (!regtab
->reg_num
)
3188 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3189 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3193 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3198 for (c
= 0; c
< 256; c
++)
3200 if (ISDIGIT (c
) || ISLOWER (c
))
3202 mnemonic_chars
[c
] = c
;
3203 register_chars
[c
] = c
;
3204 operand_chars
[c
] = c
;
3206 else if (ISUPPER (c
))
3208 mnemonic_chars
[c
] = TOLOWER (c
);
3209 register_chars
[c
] = mnemonic_chars
[c
];
3210 operand_chars
[c
] = c
;
3212 #ifdef SVR4_COMMENT_CHARS
3213 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3214 operand_chars
[c
] = c
;
3218 operand_chars
[c
] = c
;
3221 mnemonic_chars
['_'] = '_';
3222 mnemonic_chars
['-'] = '-';
3223 mnemonic_chars
['.'] = '.';
3225 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3226 operand_chars
[(unsigned char) *p
] = *p
;
3227 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3228 operand_chars
[(unsigned char) *p
] = *p
;
3231 if (flag_code
== CODE_64BIT
)
3233 #if defined (OBJ_COFF) && defined (TE_PE)
3234 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3237 x86_dwarf2_return_column
= 16;
3239 x86_cie_data_alignment
= -8;
3240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3241 x86_sframe_cfa_sp_reg
= 7;
3242 x86_sframe_cfa_fp_reg
= 6;
3247 x86_dwarf2_return_column
= 8;
3248 x86_cie_data_alignment
= -4;
3251 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3252 can be turned into BRANCH_PREFIX frag. */
3253 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3258 i386_print_statistics (FILE *file
)
3260 htab_print_statistics (file
, "i386 opcode", op_hash
);
3261 htab_print_statistics (file
, "i386 register", reg_hash
);
3267 htab_delete (op_hash
);
3268 htab_delete (reg_hash
);
3273 /* Debugging routines for md_assemble. */
3274 static void pte (insn_template
*);
3275 static void pt (i386_operand_type
);
3276 static void pe (expressionS
*);
3277 static void ps (symbolS
*);
3280 pi (const char *line
, i386_insn
*x
)
3284 fprintf (stdout
, "%s: template ", line
);
3286 fprintf (stdout
, " address: base %s index %s scale %x\n",
3287 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3288 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3289 x
->log2_scale_factor
);
3290 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3291 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3292 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3293 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3294 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3295 (x
->rex
& REX_W
) != 0,
3296 (x
->rex
& REX_R
) != 0,
3297 (x
->rex
& REX_X
) != 0,
3298 (x
->rex
& REX_B
) != 0);
3299 for (j
= 0; j
< x
->operands
; j
++)
3301 fprintf (stdout
, " #%d: ", j
+ 1);
3303 fprintf (stdout
, "\n");
3304 if (x
->types
[j
].bitfield
.class == Reg
3305 || x
->types
[j
].bitfield
.class == RegMMX
3306 || x
->types
[j
].bitfield
.class == RegSIMD
3307 || x
->types
[j
].bitfield
.class == RegMask
3308 || x
->types
[j
].bitfield
.class == SReg
3309 || x
->types
[j
].bitfield
.class == RegCR
3310 || x
->types
[j
].bitfield
.class == RegDR
3311 || x
->types
[j
].bitfield
.class == RegTR
3312 || x
->types
[j
].bitfield
.class == RegBND
)
3313 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3314 if (operand_type_check (x
->types
[j
], imm
))
3316 if (operand_type_check (x
->types
[j
], disp
))
3317 pe (x
->op
[j
].disps
);
3322 pte (insn_template
*t
)
3324 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3325 static const char *const opc_spc
[] = {
3326 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3327 "XOP08", "XOP09", "XOP0A",
3331 fprintf (stdout
, " %d operands ", t
->operands
);
3332 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3333 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3334 if (opc_spc
[t
->opcode_space
])
3335 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3336 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3337 if (t
->extension_opcode
!= None
)
3338 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3339 if (t
->opcode_modifier
.d
)
3340 fprintf (stdout
, "D");
3341 if (t
->opcode_modifier
.w
)
3342 fprintf (stdout
, "W");
3343 fprintf (stdout
, "\n");
3344 for (j
= 0; j
< t
->operands
; j
++)
3346 fprintf (stdout
, " #%d type ", j
+ 1);
3347 pt (t
->operand_types
[j
]);
3348 fprintf (stdout
, "\n");
3355 fprintf (stdout
, " operation %d\n", e
->X_op
);
3356 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3357 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3358 if (e
->X_add_symbol
)
3360 fprintf (stdout
, " add_symbol ");
3361 ps (e
->X_add_symbol
);
3362 fprintf (stdout
, "\n");
3366 fprintf (stdout
, " op_symbol ");
3367 ps (e
->X_op_symbol
);
3368 fprintf (stdout
, "\n");
3375 fprintf (stdout
, "%s type %s%s",
3377 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3378 segment_name (S_GET_SEGMENT (s
)));
3381 static struct type_name
3383 i386_operand_type mask
;
3386 const type_names
[] =
3388 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3389 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3390 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3391 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3392 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3393 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3394 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3395 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3396 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3397 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3398 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3399 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3400 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3401 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3402 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3403 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3404 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3405 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3406 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3407 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3408 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3409 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3410 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3411 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3412 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3413 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3414 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3415 { { .bitfield
= { .class = SReg
} }, "SReg" },
3416 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3417 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3418 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3419 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3420 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3421 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3425 pt (i386_operand_type t
)
3428 i386_operand_type a
;
3430 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3432 a
= operand_type_and (t
, type_names
[j
].mask
);
3433 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3434 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3439 #endif /* DEBUG386 */
3441 static bfd_reloc_code_real_type
3442 reloc (unsigned int size
,
3445 bfd_reloc_code_real_type other
)
3447 if (other
!= NO_RELOC
)
3449 reloc_howto_type
*rel
;
3454 case BFD_RELOC_X86_64_GOT32
:
3455 return BFD_RELOC_X86_64_GOT64
;
3457 case BFD_RELOC_X86_64_GOTPLT64
:
3458 return BFD_RELOC_X86_64_GOTPLT64
;
3460 case BFD_RELOC_X86_64_PLTOFF64
:
3461 return BFD_RELOC_X86_64_PLTOFF64
;
3463 case BFD_RELOC_X86_64_GOTPC32
:
3464 other
= BFD_RELOC_X86_64_GOTPC64
;
3466 case BFD_RELOC_X86_64_GOTPCREL
:
3467 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3469 case BFD_RELOC_X86_64_TPOFF32
:
3470 other
= BFD_RELOC_X86_64_TPOFF64
;
3472 case BFD_RELOC_X86_64_DTPOFF32
:
3473 other
= BFD_RELOC_X86_64_DTPOFF64
;
3479 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3480 if (other
== BFD_RELOC_SIZE32
)
3483 other
= BFD_RELOC_SIZE64
;
3486 as_bad (_("there are no pc-relative size relocations"));
3492 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3493 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3496 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3498 as_bad (_("unknown relocation (%u)"), other
);
3499 else if (size
!= bfd_get_reloc_size (rel
))
3500 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3501 bfd_get_reloc_size (rel
),
3503 else if (pcrel
&& !rel
->pc_relative
)
3504 as_bad (_("non-pc-relative relocation for pc-relative field"));
3505 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3507 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3509 as_bad (_("relocated field and relocation type differ in signedness"));
3518 as_bad (_("there are no unsigned pc-relative relocations"));
3521 case 1: return BFD_RELOC_8_PCREL
;
3522 case 2: return BFD_RELOC_16_PCREL
;
3523 case 4: return BFD_RELOC_32_PCREL
;
3524 case 8: return BFD_RELOC_64_PCREL
;
3526 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3533 case 4: return BFD_RELOC_X86_64_32S
;
3538 case 1: return BFD_RELOC_8
;
3539 case 2: return BFD_RELOC_16
;
3540 case 4: return BFD_RELOC_32
;
3541 case 8: return BFD_RELOC_64
;
3543 as_bad (_("cannot do %s %u byte relocation"),
3544 sign
> 0 ? "signed" : "unsigned", size
);
3550 /* Here we decide which fixups can be adjusted to make them relative to
3551 the beginning of the section instead of the symbol. Basically we need
3552 to make sure that the dynamic relocations are done correctly, so in
3553 some cases we force the original symbol to be used. */
3556 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3562 /* Don't adjust pc-relative references to merge sections in 64-bit
3564 if (use_rela_relocations
3565 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3569 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3570 and changed later by validate_fix. */
3571 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3572 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3575 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3576 for size relocations. */
3577 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3578 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3579 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3580 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3581 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3582 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3583 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3584 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3585 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3586 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3587 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3588 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3589 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3590 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3591 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3594 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3595 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3596 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3597 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3598 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3599 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3600 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3601 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3602 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3603 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3604 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3605 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3606 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3607 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3614 want_disp32 (const insn_template
*t
)
3616 return flag_code
!= CODE_64BIT
3617 || i
.prefix
[ADDR_PREFIX
]
3618 || (t
->mnem_off
== MN_lea
3619 && (!i
.types
[1].bitfield
.qword
3620 || t
->opcode_modifier
.size
== SIZE32
));
3624 intel_float_operand (const char *mnemonic
)
3626 /* Note that the value returned is meaningful only for opcodes with (memory)
3627 operands, hence the code here is free to improperly handle opcodes that
3628 have no operands (for better performance and smaller code). */
3630 if (mnemonic
[0] != 'f')
3631 return 0; /* non-math */
3633 switch (mnemonic
[1])
3635 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3636 the fs segment override prefix not currently handled because no
3637 call path can make opcodes without operands get here */
3639 return 2 /* integer op */;
3641 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3642 return 3; /* fldcw/fldenv */
3645 if (mnemonic
[2] != 'o' /* fnop */)
3646 return 3; /* non-waiting control op */
3649 if (mnemonic
[2] == 's')
3650 return 3; /* frstor/frstpm */
3653 if (mnemonic
[2] == 'a')
3654 return 3; /* fsave */
3655 if (mnemonic
[2] == 't')
3657 switch (mnemonic
[3])
3659 case 'c': /* fstcw */
3660 case 'd': /* fstdw */
3661 case 'e': /* fstenv */
3662 case 's': /* fsts[gw] */
3668 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3669 return 0; /* fxsave/fxrstor are not really math ops */
3677 install_template (const insn_template
*t
)
3683 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3684 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3686 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3687 && is_cpu (t
, CpuAVX512F
))
3689 if (need_evex_encoding ())
3691 i
.tm
.opcode_modifier
.vex
= 0;
3692 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3693 if (is_cpu (&i
.tm
, CpuAVX2
))
3694 i
.tm
.cpu
.bitfield
.isa
= 0;
3698 i
.tm
.opcode_modifier
.evex
= 0;
3699 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3704 /* Note that for pseudo prefixes this produces a length of 1. But for them
3705 the length isn't interesting at all. */
3706 for (l
= 1; l
< 4; ++l
)
3707 if (!(t
->base_opcode
>> (8 * l
)))
3710 i
.opcode_length
= l
;
3713 /* Build the VEX prefix. */
3716 build_vex_prefix (const insn_template
*t
)
3718 unsigned int register_specifier
;
3719 unsigned int vector_length
;
3722 /* Check register specifier. */
3723 if (i
.vex
.register_specifier
)
3725 register_specifier
=
3726 ~register_number (i
.vex
.register_specifier
) & 0xf;
3727 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3730 register_specifier
= 0xf;
3732 /* Use 2-byte VEX prefix by swapping destination and source operand
3733 if there are more than 1 register operand. */
3734 if (i
.reg_operands
> 1
3735 && i
.vec_encoding
!= vex_encoding_vex3
3736 && i
.dir_encoding
== dir_encoding_default
3737 && i
.operands
== i
.reg_operands
3738 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3739 && i
.tm
.opcode_space
== SPACE_0F
3740 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3745 swap_2_operands (0, i
.operands
- 1);
3747 gas_assert (i
.rm
.mode
== 3);
3751 i
.rm
.regmem
= i
.rm
.reg
;
3754 if (i
.tm
.opcode_modifier
.d
)
3755 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3756 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3757 else /* Use the next insn. */
3758 install_template (&t
[1]);
3761 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3762 are no memory operands and at least 3 register ones. */
3763 if (i
.reg_operands
>= 3
3764 && i
.vec_encoding
!= vex_encoding_vex3
3765 && i
.reg_operands
== i
.operands
- i
.imm_operands
3766 && i
.tm
.opcode_modifier
.vex
3767 && i
.tm
.opcode_modifier
.commutative
3768 && (i
.tm
.opcode_modifier
.sse2avx
3769 || (optimize
> 1 && !i
.no_optimize
))
3771 && i
.vex
.register_specifier
3772 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3774 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3776 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3777 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3778 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3779 &i
.types
[i
.operands
- 3]));
3780 gas_assert (i
.rm
.mode
== 3);
3782 swap_2_operands (xchg
, xchg
+ 1);
3785 xchg
= i
.rm
.regmem
| 8;
3786 i
.rm
.regmem
= ~register_specifier
& 0xf;
3787 gas_assert (!(i
.rm
.regmem
& 8));
3788 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3789 register_specifier
= ~xchg
& 0xf;
3792 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3793 vector_length
= avxscalar
;
3794 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3796 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3802 /* Determine vector length from the last multi-length vector
3805 for (op
= t
->operands
; op
--;)
3806 if (t
->operand_types
[op
].bitfield
.xmmword
3807 && t
->operand_types
[op
].bitfield
.ymmword
3808 && i
.types
[op
].bitfield
.ymmword
)
3815 /* Check the REX.W bit and VEXW. */
3816 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3817 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3818 else if (i
.tm
.opcode_modifier
.vexw
)
3819 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3821 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3823 /* Use 2-byte VEX prefix if possible. */
3825 && i
.vec_encoding
!= vex_encoding_vex3
3826 && i
.tm
.opcode_space
== SPACE_0F
3827 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3829 /* 2-byte VEX prefix. */
3833 i
.vex
.bytes
[0] = 0xc5;
3835 /* Check the REX.R bit. */
3836 r
= (i
.rex
& REX_R
) ? 0 : 1;
3837 i
.vex
.bytes
[1] = (r
<< 7
3838 | register_specifier
<< 3
3839 | vector_length
<< 2
3840 | i
.tm
.opcode_modifier
.opcodeprefix
);
3844 /* 3-byte VEX prefix. */
3847 switch (i
.tm
.opcode_space
)
3852 i
.vex
.bytes
[0] = 0xc4;
3857 i
.vex
.bytes
[0] = 0x8f;
3863 /* The high 3 bits of the second VEX byte are 1's compliment
3864 of RXB bits from REX. */
3865 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3866 | (!dot_insn () ? i
.tm
.opcode_space
3867 : i
.insn_opcode_space
);
3869 i
.vex
.bytes
[2] = (w
<< 7
3870 | register_specifier
<< 3
3871 | vector_length
<< 2
3872 | i
.tm
.opcode_modifier
.opcodeprefix
);
3877 is_evex_encoding (const insn_template
*t
)
3879 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3880 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3881 || t
->opcode_modifier
.sae
;
3885 is_any_vex_encoding (const insn_template
*t
)
3887 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3891 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3893 unsigned int op
, bytes
;
3894 const i386_operand_type
*types
;
3896 if (i
.broadcast
.type
)
3897 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3899 gas_assert (intel_syntax
);
3901 for (op
= 0; op
< t
->operands
; ++op
)
3902 if (t
->operand_types
[op
].bitfield
.baseindex
)
3905 gas_assert (op
< t
->operands
);
3907 if (t
->opcode_modifier
.evex
3908 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3909 switch (i
.broadcast
.bytes
)
3912 if (t
->operand_types
[op
].bitfield
.word
)
3916 if (t
->operand_types
[op
].bitfield
.dword
)
3920 if (t
->operand_types
[op
].bitfield
.qword
)
3924 if (t
->operand_types
[op
].bitfield
.xmmword
)
3926 if (t
->operand_types
[op
].bitfield
.ymmword
)
3928 if (t
->operand_types
[op
].bitfield
.zmmword
)
3935 gas_assert (op
+ 1 < t
->operands
);
3937 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3938 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3939 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3941 types
= &i
.types
[op
+ 1];
3944 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3945 types
= &t
->operand_types
[op
];
3947 if (types
->bitfield
.zmmword
)
3949 else if (types
->bitfield
.ymmword
)
3955 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3956 insn_name (t
), bytes
* 8);
3961 /* Build the EVEX prefix. */
3964 build_evex_prefix (void)
3966 unsigned int register_specifier
, w
;
3967 rex_byte vrex_used
= 0;
3969 /* Check register specifier. */
3970 if (i
.vex
.register_specifier
)
3972 gas_assert ((i
.vrex
& REX_X
) == 0);
3974 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3975 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3976 register_specifier
+= 8;
3977 /* The upper 16 registers are encoded in the fourth byte of the
3979 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3980 i
.vex
.bytes
[3] = 0x8;
3981 register_specifier
= ~register_specifier
& 0xf;
3985 register_specifier
= 0xf;
3987 /* Encode upper 16 vector index register in the fourth byte of
3989 if (!(i
.vrex
& REX_X
))
3990 i
.vex
.bytes
[3] = 0x8;
3995 /* 4 byte EVEX prefix. */
3997 i
.vex
.bytes
[0] = 0x62;
3999 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4001 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
4002 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
4003 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4004 | (!dot_insn () ? i
.tm
.opcode_space
4005 : i
.insn_opcode_space
);
4007 /* The fifth bit of the second EVEX byte is 1's compliment of the
4008 REX_R bit in VREX. */
4009 if (!(i
.vrex
& REX_R
))
4010 i
.vex
.bytes
[1] |= 0x10;
4014 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4016 /* When all operands are registers, the REX_X bit in REX is not
4017 used. We reuse it to encode the upper 16 registers, which is
4018 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4019 as 1's compliment. */
4020 if ((i
.vrex
& REX_B
))
4023 i
.vex
.bytes
[1] &= ~0x40;
4027 /* EVEX instructions shouldn't need the REX prefix. */
4028 i
.vrex
&= ~vrex_used
;
4029 gas_assert (i
.vrex
== 0);
4031 /* Check the REX.W bit and VEXW. */
4032 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4033 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4034 else if (i
.tm
.opcode_modifier
.vexw
)
4035 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4037 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4039 /* The third byte of the EVEX prefix. */
4040 i
.vex
.bytes
[2] = ((w
<< 7)
4041 | (register_specifier
<< 3)
4042 | 4 /* Encode the U bit. */
4043 | i
.tm
.opcode_modifier
.opcodeprefix
);
4045 /* The fourth byte of the EVEX prefix. */
4046 /* The zeroing-masking bit. */
4047 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4048 i
.vex
.bytes
[3] |= 0x80;
4050 /* Don't always set the broadcast bit if there is no RC. */
4051 if (i
.rounding
.type
== rc_none
)
4053 /* Encode the vector length. */
4054 unsigned int vec_length
;
4056 if (!i
.tm
.opcode_modifier
.evex
4057 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4061 /* Determine vector length from the last multi-length vector
4063 for (op
= i
.operands
; op
--;)
4064 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4065 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4066 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4068 if (i
.types
[op
].bitfield
.zmmword
)
4070 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4073 else if (i
.types
[op
].bitfield
.ymmword
)
4075 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4078 else if (i
.types
[op
].bitfield
.xmmword
)
4080 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4083 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4084 && op
== i
.broadcast
.operand
)
4086 switch (get_broadcast_bytes (&i
.tm
, true))
4089 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4092 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4095 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4104 if (op
>= MAX_OPERANDS
)
4108 switch (i
.tm
.opcode_modifier
.evex
)
4110 case EVEXLIG
: /* LL' is ignored */
4111 vec_length
= evexlig
<< 5;
4114 vec_length
= 0 << 5;
4117 vec_length
= 1 << 5;
4120 vec_length
= 2 << 5;
4125 vec_length
= 3 << 5;
4133 i
.vex
.bytes
[3] |= vec_length
;
4134 /* Encode the broadcast bit. */
4135 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4136 i
.vex
.bytes
[3] |= 0x10;
4138 else if (i
.rounding
.type
!= saeonly
)
4139 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4141 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4144 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4148 process_immext (void)
4152 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4153 which is coded in the same place as an 8-bit immediate field
4154 would be. Here we fake an 8-bit immediate operand from the
4155 opcode suffix stored in tm.extension_opcode.
4157 AVX instructions also use this encoding, for some of
4158 3 argument instructions. */
4160 gas_assert (i
.imm_operands
<= 1
4162 || (is_any_vex_encoding (&i
.tm
)
4163 && i
.operands
<= 4)));
4165 exp
= &im_expressions
[i
.imm_operands
++];
4166 i
.op
[i
.operands
].imms
= exp
;
4167 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4169 exp
->X_op
= O_constant
;
4170 exp
->X_add_number
= i
.tm
.extension_opcode
;
4171 i
.tm
.extension_opcode
= None
;
4178 switch (i
.tm
.opcode_modifier
.prefixok
)
4186 as_bad (_("invalid instruction `%s' after `%s'"),
4187 insn_name (&i
.tm
), i
.hle_prefix
);
4190 if (i
.prefix
[LOCK_PREFIX
])
4192 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4196 case PrefixHLERelease
:
4197 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4199 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4203 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4205 as_bad (_("memory destination needed for instruction `%s'"
4206 " after `xrelease'"), insn_name (&i
.tm
));
4213 /* Encode aligned vector move as unaligned vector move. */
4216 encode_with_unaligned_vector_move (void)
4218 switch (i
.tm
.base_opcode
)
4220 case 0x28: /* Load instructions. */
4221 case 0x29: /* Store instructions. */
4222 /* movaps/movapd/vmovaps/vmovapd. */
4223 if (i
.tm
.opcode_space
== SPACE_0F
4224 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4225 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4227 case 0x6f: /* Load instructions. */
4228 case 0x7f: /* Store instructions. */
4229 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4230 if (i
.tm
.opcode_space
== SPACE_0F
4231 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4232 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4239 /* Try the shortest encoding by shortening operand size. */
4242 optimize_encoding (void)
4246 if (i
.tm
.mnem_off
== MN_lea
)
4249 lea symbol, %rN -> mov $symbol, %rN
4250 lea (%rM), %rN -> mov %rM, %rN
4251 lea (,%rM,1), %rN -> mov %rM, %rN
4253 and in 32-bit mode for 16-bit addressing
4255 lea (%rM), %rN -> movzx %rM, %rN
4257 and in 64-bit mode zap 32-bit addressing in favor of using a
4258 32-bit (or less) destination.
4260 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4262 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4263 i
.tm
.opcode_modifier
.size
= SIZE32
;
4264 i
.prefix
[ADDR_PREFIX
] = 0;
4267 if (!i
.index_reg
&& !i
.base_reg
)
4270 lea symbol, %rN -> mov $symbol, %rN
4272 if (flag_code
== CODE_64BIT
)
4274 /* Don't transform a relocation to a 16-bit one. */
4276 && i
.op
[0].disps
->X_op
!= O_constant
4277 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4280 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4281 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4283 i
.tm
.base_opcode
= 0xb8;
4284 i
.tm
.opcode_modifier
.modrm
= 0;
4285 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4286 i
.types
[0].bitfield
.imm32
= 1;
4289 i
.tm
.opcode_modifier
.size
= SIZE16
;
4290 i
.types
[0].bitfield
.imm16
= 1;
4295 /* Subject to further optimization below. */
4296 i
.tm
.base_opcode
= 0xc7;
4297 i
.tm
.extension_opcode
= 0;
4298 i
.types
[0].bitfield
.imm32s
= 1;
4299 i
.types
[0].bitfield
.baseindex
= 0;
4302 /* Outside of 64-bit mode address and operand sizes have to match if
4303 a relocation is involved, as otherwise we wouldn't (currently) or
4304 even couldn't express the relocation correctly. */
4305 else if (i
.op
[0].disps
4306 && i
.op
[0].disps
->X_op
!= O_constant
4307 && ((!i
.prefix
[ADDR_PREFIX
])
4308 != (flag_code
== CODE_32BIT
4309 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4310 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4312 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4313 destination is going to grow encoding size. */
4314 else if (flag_code
== CODE_16BIT
4315 && (optimize
<= 1 || optimize_for_space
)
4316 && !i
.prefix
[ADDR_PREFIX
]
4317 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4321 i
.tm
.base_opcode
= 0xb8;
4322 i
.tm
.opcode_modifier
.modrm
= 0;
4323 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4324 i
.types
[0].bitfield
.imm32
= 1;
4326 i
.types
[0].bitfield
.imm16
= 1;
4329 && i
.op
[0].disps
->X_op
== O_constant
4330 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4331 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4333 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4334 i
.op
[0].disps
->X_add_number
&= 0xffff;
4337 i
.tm
.operand_types
[0] = i
.types
[0];
4341 i
.op
[0].imms
= &im_expressions
[0];
4342 i
.op
[0].imms
->X_op
= O_absent
;
4345 else if (i
.op
[0].disps
4346 && (i
.op
[0].disps
->X_op
!= O_constant
4347 || i
.op
[0].disps
->X_add_number
))
4352 lea (%rM), %rN -> mov %rM, %rN
4353 lea (,%rM,1), %rN -> mov %rM, %rN
4354 lea (%rM), %rN -> movzx %rM, %rN
4356 const reg_entry
*addr_reg
;
4358 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4359 addr_reg
= i
.base_reg
;
4360 else if (!i
.base_reg
4361 && i
.index_reg
->reg_num
!= RegIZ
4362 && !i
.log2_scale_factor
)
4363 addr_reg
= i
.index_reg
;
4367 if (addr_reg
->reg_type
.bitfield
.word
4368 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4370 if (flag_code
!= CODE_32BIT
)
4372 i
.tm
.opcode_space
= SPACE_0F
;
4373 i
.tm
.base_opcode
= 0xb7;
4376 i
.tm
.base_opcode
= 0x8b;
4378 if (addr_reg
->reg_type
.bitfield
.dword
4379 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4380 i
.tm
.opcode_modifier
.size
= SIZE32
;
4382 i
.op
[0].regs
= addr_reg
;
4387 i
.disp_operands
= 0;
4388 i
.prefix
[ADDR_PREFIX
] = 0;
4389 i
.prefix
[SEG_PREFIX
] = 0;
4393 if (optimize_for_space
4394 && i
.tm
.mnem_off
== MN_test
4395 && i
.reg_operands
== 1
4396 && i
.imm_operands
== 1
4397 && !i
.types
[1].bitfield
.byte
4398 && i
.op
[0].imms
->X_op
== O_constant
4399 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4402 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4404 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4405 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4407 i
.types
[1].bitfield
.byte
= 1;
4408 /* Ignore the suffix. */
4410 /* Convert to byte registers. */
4411 if (i
.types
[1].bitfield
.word
)
4413 else if (i
.types
[1].bitfield
.dword
)
4417 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4422 else if (flag_code
== CODE_64BIT
4423 && i
.tm
.opcode_space
== SPACE_BASE
4424 && ((i
.types
[1].bitfield
.qword
4425 && i
.reg_operands
== 1
4426 && i
.imm_operands
== 1
4427 && i
.op
[0].imms
->X_op
== O_constant
4428 && ((i
.tm
.base_opcode
== 0xb8
4429 && i
.tm
.extension_opcode
== None
4430 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4431 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4432 && (i
.tm
.base_opcode
== 0x24
4433 || (i
.tm
.base_opcode
== 0x80
4434 && i
.tm
.extension_opcode
== 0x4)
4435 || i
.tm
.mnem_off
== MN_test
4436 || ((i
.tm
.base_opcode
| 1) == 0xc7
4437 && i
.tm
.extension_opcode
== 0x0)))
4438 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4439 && i
.tm
.base_opcode
== 0x83
4440 && i
.tm
.extension_opcode
== 0x4)))
4441 || (i
.types
[0].bitfield
.qword
4442 && ((i
.reg_operands
== 2
4443 && i
.op
[0].regs
== i
.op
[1].regs
4444 && (i
.tm
.mnem_off
== MN_xor
4445 || i
.tm
.mnem_off
== MN_sub
))
4446 || i
.tm
.mnem_off
== MN_clr
))))
4449 andq $imm31, %r64 -> andl $imm31, %r32
4450 andq $imm7, %r64 -> andl $imm7, %r32
4451 testq $imm31, %r64 -> testl $imm31, %r32
4452 xorq %r64, %r64 -> xorl %r32, %r32
4453 subq %r64, %r64 -> subl %r32, %r32
4454 movq $imm31, %r64 -> movl $imm31, %r32
4455 movq $imm32, %r64 -> movl $imm32, %r32
4457 i
.tm
.opcode_modifier
.size
= SIZE32
;
4460 i
.types
[0].bitfield
.imm32
= 1;
4461 i
.types
[0].bitfield
.imm32s
= 0;
4462 i
.types
[0].bitfield
.imm64
= 0;
4466 i
.types
[0].bitfield
.dword
= 1;
4467 i
.types
[0].bitfield
.qword
= 0;
4469 i
.types
[1].bitfield
.dword
= 1;
4470 i
.types
[1].bitfield
.qword
= 0;
4471 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4474 movq $imm31, %r64 -> movl $imm31, %r32
4475 movq $imm32, %r64 -> movl $imm32, %r32
4477 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4478 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4479 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4480 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4483 movq $imm31, %r64 -> movl $imm31, %r32
4485 i
.tm
.base_opcode
= 0xb8;
4486 i
.tm
.extension_opcode
= None
;
4487 i
.tm
.opcode_modifier
.w
= 0;
4488 i
.tm
.opcode_modifier
.modrm
= 0;
4492 else if (optimize
> 1
4493 && !optimize_for_space
4494 && i
.reg_operands
== 2
4495 && i
.op
[0].regs
== i
.op
[1].regs
4496 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4497 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4500 andb %rN, %rN -> testb %rN, %rN
4501 andw %rN, %rN -> testw %rN, %rN
4502 andq %rN, %rN -> testq %rN, %rN
4503 orb %rN, %rN -> testb %rN, %rN
4504 orw %rN, %rN -> testw %rN, %rN
4505 orq %rN, %rN -> testq %rN, %rN
4507 and outside of 64-bit mode
4509 andl %rN, %rN -> testl %rN, %rN
4510 orl %rN, %rN -> testl %rN, %rN
4512 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4514 else if (i
.tm
.base_opcode
== 0xba
4515 && i
.tm
.opcode_space
== SPACE_0F
4516 && i
.reg_operands
== 1
4517 && i
.op
[0].imms
->X_op
== O_constant
4518 && i
.op
[0].imms
->X_add_number
>= 0)
4521 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4522 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4523 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4525 With <BT> one of bts, btr, and bts also:
4526 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4527 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4532 if (i
.tm
.extension_opcode
!= 4)
4534 if (i
.types
[1].bitfield
.qword
4535 && i
.op
[0].imms
->X_add_number
< 32
4536 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4537 i
.tm
.opcode_modifier
.size
= SIZE32
;
4540 if (i
.types
[1].bitfield
.word
4541 && i
.op
[0].imms
->X_add_number
< 16)
4542 i
.tm
.opcode_modifier
.size
= SIZE32
;
4545 if (i
.op
[0].imms
->X_add_number
< 16)
4546 i
.tm
.opcode_modifier
.size
= SIZE16
;
4550 else if (i
.reg_operands
== 3
4551 && i
.op
[0].regs
== i
.op
[1].regs
4552 && !i
.types
[2].bitfield
.xmmword
4553 && (i
.tm
.opcode_modifier
.vex
4554 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4555 && is_evex_encoding (&i
.tm
)
4556 && (i
.vec_encoding
!= vex_encoding_evex
4557 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4558 || is_cpu (&i
.tm
, CpuAVX512VL
)
4559 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4560 && i
.types
[2].bitfield
.ymmword
))))
4561 && i
.tm
.opcode_space
== SPACE_0F
4562 && ((i
.tm
.base_opcode
| 2) == 0x57
4563 || i
.tm
.base_opcode
== 0xdf
4564 || i
.tm
.base_opcode
== 0xef
4565 || (i
.tm
.base_opcode
| 3) == 0xfb
4566 || i
.tm
.base_opcode
== 0x42
4567 || i
.tm
.base_opcode
== 0x47))
4570 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4572 EVEX VOP %zmmM, %zmmM, %zmmN
4573 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4574 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4575 EVEX VOP %ymmM, %ymmM, %ymmN
4576 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4577 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4578 VEX VOP %ymmM, %ymmM, %ymmN
4579 -> VEX VOP %xmmM, %xmmM, %xmmN
4580 VOP, one of vpandn and vpxor:
4581 VEX VOP %ymmM, %ymmM, %ymmN
4582 -> VEX VOP %xmmM, %xmmM, %xmmN
4583 VOP, one of vpandnd and vpandnq:
4584 EVEX VOP %zmmM, %zmmM, %zmmN
4585 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4586 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4587 EVEX VOP %ymmM, %ymmM, %ymmN
4588 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4589 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4590 VOP, one of vpxord and vpxorq:
4591 EVEX VOP %zmmM, %zmmM, %zmmN
4592 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4593 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4594 EVEX VOP %ymmM, %ymmM, %ymmN
4595 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4596 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4597 VOP, one of kxord and kxorq:
4598 VEX VOP %kM, %kM, %kN
4599 -> VEX kxorw %kM, %kM, %kN
4600 VOP, one of kandnd and kandnq:
4601 VEX VOP %kM, %kM, %kN
4602 -> VEX kandnw %kM, %kM, %kN
4604 if (is_evex_encoding (&i
.tm
))
4606 if (i
.vec_encoding
!= vex_encoding_evex
)
4608 i
.tm
.opcode_modifier
.vex
= VEX128
;
4609 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4610 i
.tm
.opcode_modifier
.evex
= 0;
4611 i
.vec_encoding
= vex_encoding_vex
;
4614 else if (optimize
> 1)
4615 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4619 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4621 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4622 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4625 i
.tm
.opcode_modifier
.vex
= VEX128
;
4627 if (i
.tm
.opcode_modifier
.vex
)
4628 for (j
= 0; j
< 3; j
++)
4630 i
.types
[j
].bitfield
.xmmword
= 1;
4631 i
.types
[j
].bitfield
.ymmword
= 0;
4634 else if (i
.vec_encoding
!= vex_encoding_evex
4635 && !i
.types
[0].bitfield
.zmmword
4636 && !i
.types
[1].bitfield
.zmmword
4638 && !i
.broadcast
.type
4639 && !i
.broadcast
.bytes
4640 && is_evex_encoding (&i
.tm
)
4641 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4642 || (i
.tm
.base_opcode
& ~4) == 0xdb
4643 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4644 && i
.tm
.extension_opcode
== None
)
4647 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4648 vmovdqu32 and vmovdqu64:
4649 EVEX VOP %xmmM, %xmmN
4650 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4651 EVEX VOP %ymmM, %ymmN
4652 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4654 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4656 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4658 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4660 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4661 VOP, one of vpand, vpandn, vpor, vpxor:
4662 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4663 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4664 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4665 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4666 EVEX VOP{d,q} mem, %xmmM, %xmmN
4667 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4668 EVEX VOP{d,q} mem, %ymmM, %ymmN
4669 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4671 for (j
= 0; j
< i
.operands
; j
++)
4672 if (operand_type_check (i
.types
[j
], disp
)
4673 && i
.op
[j
].disps
->X_op
== O_constant
)
4675 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4676 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4677 bytes, we choose EVEX Disp8 over VEX Disp32. */
4678 int evex_disp8
, vex_disp8
;
4679 unsigned int memshift
= i
.memshift
;
4680 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4682 evex_disp8
= fits_in_disp8 (n
);
4684 vex_disp8
= fits_in_disp8 (n
);
4685 if (evex_disp8
!= vex_disp8
)
4687 i
.memshift
= memshift
;
4691 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4694 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4695 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4696 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4697 i
.tm
.opcode_modifier
.vex
4698 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4699 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4700 /* VPAND, VPOR, and VPXOR are commutative. */
4701 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4702 i
.tm
.opcode_modifier
.commutative
= 1;
4703 i
.tm
.opcode_modifier
.evex
= 0;
4704 i
.tm
.opcode_modifier
.masking
= 0;
4705 i
.tm
.opcode_modifier
.broadcast
= 0;
4706 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4709 i
.types
[j
].bitfield
.disp8
4710 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4712 else if (optimize_for_space
4713 && i
.tm
.base_opcode
== 0x29
4714 && i
.tm
.opcode_space
== SPACE_0F38
4715 && i
.operands
== i
.reg_operands
4716 && i
.op
[0].regs
== i
.op
[1].regs
4717 && (!i
.tm
.opcode_modifier
.vex
4718 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4719 && !is_evex_encoding (&i
.tm
))
4722 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4723 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4724 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4726 i
.tm
.opcode_space
= SPACE_0F
;
4727 i
.tm
.base_opcode
= 0x76;
4729 else if (((i
.tm
.base_opcode
>= 0x64
4730 && i
.tm
.base_opcode
<= 0x66
4731 && i
.tm
.opcode_space
== SPACE_0F
)
4732 || (i
.tm
.base_opcode
== 0x37
4733 && i
.tm
.opcode_space
== SPACE_0F38
))
4734 && i
.operands
== i
.reg_operands
4735 && i
.op
[0].regs
== i
.op
[1].regs
4736 && !is_evex_encoding (&i
.tm
))
4739 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4740 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4741 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4742 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4743 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4744 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4746 i
.tm
.opcode_space
= SPACE_0F
;
4747 i
.tm
.base_opcode
= 0xef;
4748 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4750 if (i
.operands
== 2)
4752 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4758 i
.op
[2].regs
= i
.op
[0].regs
;
4759 i
.types
[2] = i
.types
[0];
4760 i
.flags
[2] = i
.flags
[0];
4761 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4763 i
.tm
.opcode_modifier
.sse2avx
= 0;
4765 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4766 i
.op
[1].regs
= i
.op
[0].regs
;
4769 else if (optimize_for_space
4770 && i
.tm
.base_opcode
== 0x59
4771 && i
.tm
.opcode_space
== SPACE_0F38
4772 && i
.operands
== i
.reg_operands
4773 && i
.tm
.opcode_modifier
.vex
4774 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4775 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4776 && i
.vec_encoding
!= vex_encoding_vex3
)
4779 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4781 i
.tm
.opcode_space
= SPACE_0F
;
4782 i
.tm
.base_opcode
= 0x6c;
4783 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4789 i
.op
[2].regs
= i
.op
[0].regs
;
4790 i
.types
[2] = i
.types
[0];
4791 i
.flags
[2] = i
.flags
[0];
4792 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4794 swap_2_operands (1, 2);
4798 /* Return non-zero for load instruction. */
4804 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4805 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4809 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4810 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4811 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4815 if (i
.tm
.mnem_off
== MN_pop
)
4819 if (i
.tm
.opcode_space
== SPACE_BASE
)
4822 if (i
.tm
.base_opcode
== 0x9d
4823 || i
.tm
.base_opcode
== 0x61)
4826 /* movs, cmps, lods, scas. */
4827 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4831 if (base_opcode
== 0x6f
4832 || i
.tm
.base_opcode
== 0xd7)
4834 /* NB: For AMD-specific insns with implicit memory operands,
4835 they're intentionally not covered. */
4838 /* No memory operand. */
4839 if (!i
.mem_operands
)
4844 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4847 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4849 /* test, not, neg, mul, imul, div, idiv. */
4850 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4854 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4857 /* add, or, adc, sbb, and, sub, xor, cmp. */
4858 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4861 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4862 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4863 && i
.tm
.extension_opcode
!= 6)
4866 /* Check for x87 instructions. */
4867 if ((base_opcode
| 6) == 0xdf)
4869 /* Skip fst, fstp, fstenv, fstcw. */
4870 if (i
.tm
.base_opcode
== 0xd9
4871 && (i
.tm
.extension_opcode
== 2
4872 || i
.tm
.extension_opcode
== 3
4873 || i
.tm
.extension_opcode
== 6
4874 || i
.tm
.extension_opcode
== 7))
4877 /* Skip fisttp, fist, fistp, fstp. */
4878 if (i
.tm
.base_opcode
== 0xdb
4879 && (i
.tm
.extension_opcode
== 1
4880 || i
.tm
.extension_opcode
== 2
4881 || i
.tm
.extension_opcode
== 3
4882 || i
.tm
.extension_opcode
== 7))
4885 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4886 if (i
.tm
.base_opcode
== 0xdd
4887 && (i
.tm
.extension_opcode
== 1
4888 || i
.tm
.extension_opcode
== 2
4889 || i
.tm
.extension_opcode
== 3
4890 || i
.tm
.extension_opcode
== 6
4891 || i
.tm
.extension_opcode
== 7))
4894 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4895 if (i
.tm
.base_opcode
== 0xdf
4896 && (i
.tm
.extension_opcode
== 1
4897 || i
.tm
.extension_opcode
== 2
4898 || i
.tm
.extension_opcode
== 3
4899 || i
.tm
.extension_opcode
== 6
4900 || i
.tm
.extension_opcode
== 7))
4906 else if (i
.tm
.opcode_space
== SPACE_0F
)
4908 /* bt, bts, btr, btc. */
4909 if (i
.tm
.base_opcode
== 0xba
4910 && (i
.tm
.extension_opcode
| 3) == 7)
4913 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4914 if (i
.tm
.base_opcode
== 0xc7
4915 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4916 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4917 || i
.tm
.extension_opcode
== 6))
4920 /* fxrstor, ldmxcsr, xrstor. */
4921 if (i
.tm
.base_opcode
== 0xae
4922 && (i
.tm
.extension_opcode
== 1
4923 || i
.tm
.extension_opcode
== 2
4924 || i
.tm
.extension_opcode
== 5))
4927 /* lgdt, lidt, lmsw. */
4928 if (i
.tm
.base_opcode
== 0x01
4929 && (i
.tm
.extension_opcode
== 2
4930 || i
.tm
.extension_opcode
== 3
4931 || i
.tm
.extension_opcode
== 6))
4935 dest
= i
.operands
- 1;
4937 /* Check fake imm8 operand and 3 source operands. */
4938 if ((i
.tm
.opcode_modifier
.immext
4939 || i
.reg_operands
+ i
.mem_operands
== 4)
4940 && i
.types
[dest
].bitfield
.imm8
)
4943 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4944 if (i
.tm
.opcode_space
== SPACE_BASE
4945 && ((base_opcode
| 0x38) == 0x39
4946 || (base_opcode
| 2) == 0x87))
4949 if (i
.tm
.mnem_off
== MN_xadd
)
4952 /* Check for load instruction. */
4953 return (i
.types
[dest
].bitfield
.class != ClassNone
4954 || i
.types
[dest
].bitfield
.instance
== Accum
);
4957 /* Output lfence, 0xfaee8, after instruction. */
4960 insert_lfence_after (void)
4962 if (lfence_after_load
&& load_insn_p ())
4964 /* There are also two REP string instructions that require
4965 special treatment. Specifically, the compare string (CMPS)
4966 and scan string (SCAS) instructions set EFLAGS in a manner
4967 that depends on the data being compared/scanned. When used
4968 with a REP prefix, the number of iterations may therefore
4969 vary depending on this data. If the data is a program secret
4970 chosen by the adversary using an LVI method,
4971 then this data-dependent behavior may leak some aspect
4973 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4974 && i
.prefix
[REP_PREFIX
])
4976 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4979 char *p
= frag_more (3);
4986 /* Output lfence, 0xfaee8, before instruction. */
4989 insert_lfence_before (void)
4993 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4996 if (i
.tm
.base_opcode
== 0xff
4997 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4999 /* Insert lfence before indirect branch if needed. */
5001 if (lfence_before_indirect_branch
== lfence_branch_none
)
5004 if (i
.operands
!= 1)
5007 if (i
.reg_operands
== 1)
5009 /* Indirect branch via register. Don't insert lfence with
5010 -mlfence-after-load=yes. */
5011 if (lfence_after_load
5012 || lfence_before_indirect_branch
== lfence_branch_memory
)
5015 else if (i
.mem_operands
== 1
5016 && lfence_before_indirect_branch
!= lfence_branch_register
)
5018 as_warn (_("indirect `%s` with memory operand should be avoided"),
5025 if (last_insn
.kind
!= last_insn_other
5026 && last_insn
.seg
== now_seg
)
5028 as_warn_where (last_insn
.file
, last_insn
.line
,
5029 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5030 last_insn
.name
, insn_name (&i
.tm
));
5041 /* Output or/not/shl and lfence before near ret. */
5042 if (lfence_before_ret
!= lfence_before_ret_none
5043 && (i
.tm
.base_opcode
| 1) == 0xc3)
5045 if (last_insn
.kind
!= last_insn_other
5046 && last_insn
.seg
== now_seg
)
5048 as_warn_where (last_insn
.file
, last_insn
.line
,
5049 _("`%s` skips -mlfence-before-ret on `%s`"),
5050 last_insn
.name
, insn_name (&i
.tm
));
5054 /* Near ret ingore operand size override under CPU64. */
5055 char prefix
= flag_code
== CODE_64BIT
5057 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5059 if (lfence_before_ret
== lfence_before_ret_not
)
5061 /* not: 0xf71424, may add prefix
5062 for operand size override or 64-bit code. */
5063 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5077 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5080 if (lfence_before_ret
== lfence_before_ret_or
)
5082 /* or: 0x830c2400, may add prefix
5083 for operand size override or 64-bit code. */
5089 /* shl: 0xc1242400, may add prefix
5090 for operand size override or 64-bit code. */
5105 /* Shared helper for md_assemble() and s_insn(). */
5106 static void init_globals (void)
5110 memset (&i
, '\0', sizeof (i
));
5111 i
.rounding
.type
= rc_none
;
5112 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5113 i
.reloc
[j
] = NO_RELOC
;
5114 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5115 memset (im_expressions
, '\0', sizeof (im_expressions
));
5116 save_stack_p
= save_stack
;
5119 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5120 parsing pass. Instead of introducing a rarely use new insn attribute this
5121 utilizes a common pattern between affected templates. It is deemed
5122 acceptable that this will lead to unnecessary pass 2 preparations in a
5123 limited set of cases. */
5124 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5126 return t
->opcode_modifier
.sse2avx
5127 /* Note that all SSE2AVX templates have at least one operand. */
5128 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5129 : (t
->opcode_space
== SPACE_0F
5130 && (t
->base_opcode
| 1) == 0xbf)
5131 || (t
->opcode_space
== SPACE_BASE
5132 && t
->base_opcode
== 0x63);
5135 /* This is the guts of the machine-dependent assembler. LINE points to a
5136 machine dependent instruction. This function is supposed to emit
5137 the frags/bytes it assembles to. */
5140 md_assemble (char *line
)
5143 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5144 const char *end
, *pass1_mnem
= NULL
;
5145 enum i386_error pass1_err
= 0;
5146 const insn_template
*t
;
5148 /* Initialize globals. */
5149 current_templates
= NULL
;
5153 /* First parse an instruction mnemonic & call i386_operand for the operands.
5154 We assume that the scrubber has arranged it so that line[0] is the valid
5155 start of a (possibly prefixed) mnemonic. */
5157 end
= parse_insn (line
, mnemonic
, false);
5160 if (pass1_mnem
!= NULL
)
5162 if (i
.error
!= no_error
)
5164 gas_assert (current_templates
!= NULL
);
5165 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5167 /* No point in trying a 2nd pass - it'll only find the same suffix
5169 mnem_suffix
= i
.suffix
;
5174 t
= current_templates
->start
;
5175 if (may_need_pass2 (t
))
5177 /* Make a copy of the full line in case we need to retry. */
5178 copy
= xstrdup (line
);
5181 mnem_suffix
= i
.suffix
;
5183 line
= parse_operands (line
, mnemonic
);
5191 /* Now we've parsed the mnemonic into a set of templates, and have the
5192 operands at hand. */
5194 /* All Intel opcodes have reversed operands except for "bound", "enter",
5195 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5196 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5197 intersegment "jmp" and "call" instructions with 2 immediate operands so
5198 that the immediate segment precedes the offset consistently in Intel and
5202 && (t
->mnem_off
!= MN_bound
)
5203 && !startswith (mnemonic
, "invlpg")
5204 && !startswith (mnemonic
, "monitor")
5205 && !startswith (mnemonic
, "mwait")
5206 && (t
->mnem_off
!= MN_pvalidate
)
5207 && !startswith (mnemonic
, "rmp")
5208 && (t
->mnem_off
!= MN_tpause
)
5209 && (t
->mnem_off
!= MN_umwait
)
5210 && !(i
.operands
== 2
5211 && operand_type_check (i
.types
[0], imm
)
5212 && operand_type_check (i
.types
[1], imm
)))
5215 /* The order of the immediates should be reversed
5216 for 2 immediates extrq and insertq instructions */
5217 if (i
.imm_operands
== 2
5218 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5219 swap_2_operands (0, 1);
5224 if (i
.disp_operands
&& !optimize_disp (t
))
5227 /* Next, we find a template that matches the given insn,
5228 making sure the overlap of the given operands types is consistent
5229 with the template operand types. */
5231 if (!(t
= match_template (mnem_suffix
)))
5233 const char *err_msg
;
5235 if (copy
&& !mnem_suffix
)
5240 pass1_err
= i
.error
;
5241 pass1_mnem
= insn_name (current_templates
->start
);
5245 /* If a non-/only-64bit template (group) was found in pass 1, and if
5246 _some_ template (group) was found in pass 2, squash pass 1's
5248 if (pass1_err
== unsupported_64bit
)
5254 switch (pass1_mnem
? pass1_err
: i
.error
)
5258 case operand_size_mismatch
:
5259 err_msg
= _("operand size mismatch");
5261 case operand_type_mismatch
:
5262 err_msg
= _("operand type mismatch");
5264 case register_type_mismatch
:
5265 err_msg
= _("register type mismatch");
5267 case number_of_operands_mismatch
:
5268 err_msg
= _("number of operands mismatch");
5270 case invalid_instruction_suffix
:
5271 err_msg
= _("invalid instruction suffix");
5274 err_msg
= _("constant doesn't fit in 4 bits");
5276 case unsupported_with_intel_mnemonic
:
5277 err_msg
= _("unsupported with Intel mnemonic");
5279 case unsupported_syntax
:
5280 err_msg
= _("unsupported syntax");
5283 as_bad (_("unsupported instruction `%s'"),
5284 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5286 case unsupported_on_arch
:
5287 as_bad (_("`%s' is not supported on `%s%s'"),
5288 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5289 cpu_arch_name
? cpu_arch_name
: default_arch
,
5290 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5292 case unsupported_64bit
:
5293 if (ISLOWER (mnem_suffix
))
5295 if (flag_code
== CODE_64BIT
)
5296 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5297 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5300 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5301 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5306 if (flag_code
== CODE_64BIT
)
5307 as_bad (_("`%s' is not supported in 64-bit mode"),
5308 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5310 as_bad (_("`%s' is only supported in 64-bit mode"),
5311 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5314 case invalid_sib_address
:
5315 err_msg
= _("invalid SIB address");
5317 case invalid_vsib_address
:
5318 err_msg
= _("invalid VSIB address");
5320 case invalid_vector_register_set
:
5321 err_msg
= _("mask, index, and destination registers must be distinct");
5323 case invalid_tmm_register_set
:
5324 err_msg
= _("all tmm registers must be distinct");
5326 case invalid_dest_and_src_register_set
:
5327 err_msg
= _("destination and source registers must be distinct");
5329 case unsupported_vector_index_register
:
5330 err_msg
= _("unsupported vector index register");
5332 case unsupported_broadcast
:
5333 err_msg
= _("unsupported broadcast");
5335 case broadcast_needed
:
5336 err_msg
= _("broadcast is needed for operand of such type");
5338 case unsupported_masking
:
5339 err_msg
= _("unsupported masking");
5341 case mask_not_on_destination
:
5342 err_msg
= _("mask not on destination operand");
5344 case no_default_mask
:
5345 err_msg
= _("default mask isn't allowed");
5347 case unsupported_rc_sae
:
5348 err_msg
= _("unsupported static rounding/sae");
5350 case invalid_register_operand
:
5351 err_msg
= _("invalid register operand");
5353 case internal_error
:
5354 err_msg
= _("internal error");
5357 as_bad (_("%s for `%s'"), err_msg
,
5358 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5364 if (sse_check
!= check_none
5365 /* The opcode space check isn't strictly needed; it's there only to
5366 bypass the logic below when easily possible. */
5367 && t
->opcode_space
>= SPACE_0F
5368 && t
->opcode_space
<= SPACE_0F3A
5369 && !is_cpu (&i
.tm
, CpuSSE4a
)
5370 && !is_any_vex_encoding (t
))
5374 for (j
= 0; j
< t
->operands
; ++j
)
5376 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5378 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5382 if (j
>= t
->operands
&& simd
)
5383 (sse_check
== check_warning
5385 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5388 if (i
.tm
.opcode_modifier
.fwait
)
5389 if (!add_prefix (FWAIT_OPCODE
))
5392 /* Check if REP prefix is OK. */
5393 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5395 as_bad (_("invalid instruction `%s' after `%s'"),
5396 insn_name (&i
.tm
), i
.rep_prefix
);
5400 /* Check for lock without a lockable instruction. Destination operand
5401 must be memory unless it is xchg (0x86). */
5402 if (i
.prefix
[LOCK_PREFIX
])
5404 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5405 || i
.mem_operands
== 0
5406 || (i
.tm
.base_opcode
!= 0x86
5407 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5409 as_bad (_("expecting lockable instruction after `lock'"));
5413 /* Zap the redundant prefix from XCHG when optimizing. */
5414 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5415 i
.prefix
[LOCK_PREFIX
] = 0;
5418 if (is_any_vex_encoding (&i
.tm
)
5419 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5420 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5422 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5423 if (i
.prefix
[DATA_PREFIX
])
5425 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5429 /* Don't allow e.g. KMOV in TLS code sequences. */
5430 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5433 case BFD_RELOC_386_TLS_GOTIE
:
5434 case BFD_RELOC_386_TLS_LE_32
:
5435 case BFD_RELOC_X86_64_GOTTPOFF
:
5436 case BFD_RELOC_X86_64_TLSLD
:
5437 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5444 /* Check if HLE prefix is OK. */
5445 if (i
.hle_prefix
&& !check_hle ())
5448 /* Check BND prefix. */
5449 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5450 as_bad (_("expecting valid branch instruction after `bnd'"));
5452 /* Check NOTRACK prefix. */
5453 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5454 as_bad (_("expecting indirect branch instruction after `notrack'"));
5456 if (is_cpu (&i
.tm
, CpuMPX
))
5458 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5459 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5460 else if (flag_code
!= CODE_16BIT
5461 ? i
.prefix
[ADDR_PREFIX
]
5462 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5463 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5466 /* Insert BND prefix. */
5467 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5469 if (!i
.prefix
[BND_PREFIX
])
5470 add_prefix (BND_PREFIX_OPCODE
);
5471 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5473 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5474 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5478 /* Check string instruction segment overrides. */
5479 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5481 gas_assert (i
.mem_operands
);
5482 if (!check_string ())
5484 i
.disp_operands
= 0;
5487 /* The memory operand of (%dx) should be only used with input/output
5488 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5489 if (i
.input_output_operand
5490 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5491 || i
.tm
.opcode_space
!= SPACE_BASE
))
5493 as_bad (_("input/output port address isn't allowed with `%s'"),
5498 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5499 optimize_encoding ();
5501 /* Past optimization there's no need to distinguish vex_encoding_evex and
5502 vex_encoding_evex512 anymore. */
5503 if (i
.vec_encoding
== vex_encoding_evex512
)
5504 i
.vec_encoding
= vex_encoding_evex
;
5506 if (use_unaligned_vector_move
)
5507 encode_with_unaligned_vector_move ();
5509 if (!process_suffix ())
5512 /* Check if IP-relative addressing requirements can be satisfied. */
5513 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5514 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5515 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5517 /* Update operand types and check extended states. */
5518 for (j
= 0; j
< i
.operands
; j
++)
5520 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5521 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5526 i
.xstate
|= xstate_mmx
;
5529 i
.xstate
|= xstate_mask
;
5532 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5533 i
.xstate
|= xstate_tmm
;
5534 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5535 && !i
.tm
.opcode_modifier
.vex
5536 && vector_size
>= VSZ512
)
5537 i
.xstate
|= xstate_zmm
;
5538 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5539 && vector_size
>= VSZ256
)
5540 i
.xstate
|= xstate_ymm
;
5541 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5542 i
.xstate
|= xstate_xmm
;
5547 /* Make still unresolved immediate matches conform to size of immediate
5548 given in i.suffix. */
5549 if (!finalize_imm ())
5552 if (i
.types
[0].bitfield
.imm1
)
5553 i
.imm_operands
= 0; /* kludge for shift insns. */
5555 /* For insns with operands there are more diddles to do to the opcode. */
5558 if (!process_operands ())
5561 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5563 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5564 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5567 if (is_any_vex_encoding (&i
.tm
))
5569 if (!cpu_arch_flags
.bitfield
.cpui286
)
5571 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5576 /* Check for explicit REX prefix. */
5577 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5579 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5583 if (i
.tm
.opcode_modifier
.vex
)
5584 build_vex_prefix (t
);
5586 build_evex_prefix ();
5588 /* The individual REX.RXBW bits got consumed. */
5589 i
.rex
&= REX_OPCODE
;
5592 /* Handle conversion of 'int $3' --> special int3 insn. */
5593 if (i
.tm
.mnem_off
== MN_int
5594 && i
.op
[0].imms
->X_add_number
== 3)
5596 i
.tm
.base_opcode
= INT3_OPCODE
;
5600 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5601 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5602 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5603 && i
.op
[0].disps
->X_op
== O_constant
)
5605 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5606 the absolute address given by the constant. Since ix86 jumps and
5607 calls are pc relative, we need to generate a reloc. */
5608 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5609 i
.op
[0].disps
->X_op
= O_symbol
;
5612 /* For 8 bit registers we need an empty rex prefix. Also if the
5613 instruction already has a prefix, we need to convert old
5614 registers to new ones. */
5616 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5617 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5618 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5619 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5620 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5621 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5626 i
.rex
|= REX_OPCODE
;
5627 for (x
= 0; x
< 2; x
++)
5629 /* Look for 8 bit operand that uses old registers. */
5630 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5631 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5633 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5634 /* In case it is "hi" register, give up. */
5635 if (i
.op
[x
].regs
->reg_num
> 3)
5636 as_bad (_("can't encode register '%s%s' in an "
5637 "instruction requiring REX prefix."),
5638 register_prefix
, i
.op
[x
].regs
->reg_name
);
5640 /* Otherwise it is equivalent to the extended register.
5641 Since the encoding doesn't change this is merely
5642 cosmetic cleanup for debug output. */
5644 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5649 if (i
.rex
== 0 && i
.rex_encoding
)
5651 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5652 that uses legacy register. If it is "hi" register, don't add
5653 the REX_OPCODE byte. */
5655 for (x
= 0; x
< 2; x
++)
5656 if (i
.types
[x
].bitfield
.class == Reg
5657 && i
.types
[x
].bitfield
.byte
5658 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5659 && i
.op
[x
].regs
->reg_num
> 3)
5661 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5662 i
.rex_encoding
= false;
5671 add_prefix (REX_OPCODE
| i
.rex
);
5673 insert_lfence_before ();
5675 /* We are ready to output the insn. */
5678 insert_lfence_after ();
5680 last_insn
.seg
= now_seg
;
5682 if (i
.tm
.opcode_modifier
.isprefix
)
5684 last_insn
.kind
= last_insn_prefix
;
5685 last_insn
.name
= insn_name (&i
.tm
);
5686 last_insn
.file
= as_where (&last_insn
.line
);
5689 last_insn
.kind
= last_insn_other
;
5692 /* The Q suffix is generally valid only in 64-bit mode, with very few
5693 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5694 and fisttp only one of their two templates is matched below: That's
5695 sufficient since other relevant attributes are the same between both
5696 respective templates. */
5697 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5699 return flag_code
== CODE_64BIT
5700 || (t
->opcode_space
== SPACE_BASE
5701 && t
->base_opcode
== 0xdf
5702 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5703 || t
->mnem_off
== MN_cmpxchg8b
;
5707 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5709 const char *l
= line
, *token_start
= l
;
5711 bool pass1
= !current_templates
;
5713 const insn_template
*t
;
5719 /* Pseudo-prefixes start with an opening figure brace. */
5720 if ((*mnem_p
= *l
) == '{')
5725 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5730 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5733 as_bad (_("no such instruction: `%s'"), token_start
);
5738 /* Pseudo-prefixes end with a closing figure brace. */
5739 if (*mnemonic
== '{' && *l
== '}')
5742 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5746 /* Point l at the closing brace if there's no other separator. */
5747 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5748 && *l
!= PREFIX_SEPARATOR
)
5751 else if (!is_space_char (*l
)
5752 && *l
!= END_OF_INSN
5754 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5758 as_bad (_("invalid character %s in mnemonic"),
5759 output_invalid (*l
));
5762 if (token_start
== l
)
5764 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5765 as_bad (_("expecting prefix; got nothing"));
5767 as_bad (_("expecting mnemonic; got nothing"));
5771 /* Look up instruction (or prefix) via hash table. */
5772 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5774 if (*l
!= END_OF_INSN
5775 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5776 && current_templates
5777 && current_templates
->start
->opcode_modifier
.isprefix
)
5779 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5781 as_bad ((flag_code
!= CODE_64BIT
5782 ? _("`%s' is only supported in 64-bit mode")
5783 : _("`%s' is not supported in 64-bit mode")),
5784 insn_name (current_templates
->start
));
5787 /* If we are in 16-bit mode, do not allow addr16 or data16.
5788 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5789 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5790 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5791 && flag_code
!= CODE_64BIT
5792 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5793 ^ (flag_code
== CODE_16BIT
)))
5795 as_bad (_("redundant %s prefix"),
5796 insn_name (current_templates
->start
));
5800 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5802 /* Handle pseudo prefixes. */
5803 switch (current_templates
->start
->extension_opcode
)
5807 i
.disp_encoding
= disp_encoding_8bit
;
5811 i
.disp_encoding
= disp_encoding_16bit
;
5815 i
.disp_encoding
= disp_encoding_32bit
;
5819 i
.dir_encoding
= dir_encoding_load
;
5823 i
.dir_encoding
= dir_encoding_store
;
5827 i
.vec_encoding
= vex_encoding_vex
;
5831 i
.vec_encoding
= vex_encoding_vex3
;
5835 i
.vec_encoding
= vex_encoding_evex
;
5839 i
.rex_encoding
= true;
5841 case Prefix_NoOptimize
:
5843 i
.no_optimize
= true;
5851 /* Add prefix, checking for repeated prefixes. */
5852 switch (add_prefix (current_templates
->start
->base_opcode
))
5857 if (is_cpu (current_templates
->start
, CpuIBT
))
5858 i
.notrack_prefix
= insn_name (current_templates
->start
);
5861 if (is_cpu (current_templates
->start
, CpuHLE
))
5862 i
.hle_prefix
= insn_name (current_templates
->start
);
5863 else if (is_cpu (current_templates
->start
, CpuMPX
))
5864 i
.bnd_prefix
= insn_name (current_templates
->start
);
5866 i
.rep_prefix
= insn_name (current_templates
->start
);
5872 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5882 if (!current_templates
)
5884 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5885 Check if we should swap operand or force 32bit displacement in
5887 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5888 i
.dir_encoding
= dir_encoding_swap
;
5889 else if (mnem_p
- 3 == dot_p
5892 i
.disp_encoding
= disp_encoding_8bit
;
5893 else if (mnem_p
- 4 == dot_p
5897 i
.disp_encoding
= disp_encoding_32bit
;
5902 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5905 if (!current_templates
|| !pass1
)
5907 current_templates
= NULL
;
5910 if (mnem_p
> mnemonic
)
5912 /* See if we can get a match by trimming off a suffix. */
5915 case WORD_MNEM_SUFFIX
:
5916 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5917 i
.suffix
= SHORT_MNEM_SUFFIX
;
5920 case BYTE_MNEM_SUFFIX
:
5921 case QWORD_MNEM_SUFFIX
:
5922 i
.suffix
= mnem_p
[-1];
5925 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5927 case SHORT_MNEM_SUFFIX
:
5928 case LONG_MNEM_SUFFIX
:
5931 i
.suffix
= mnem_p
[-1];
5934 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5942 if (intel_float_operand (mnemonic
) == 1)
5943 i
.suffix
= SHORT_MNEM_SUFFIX
;
5945 i
.suffix
= LONG_MNEM_SUFFIX
;
5948 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5950 /* For compatibility reasons accept MOVSD and CMPSD without
5951 operands even in AT&T mode. */
5952 else if (*l
== END_OF_INSN
5953 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5957 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5958 if (current_templates
!= NULL
5960 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5961 && current_templates
->start
->opcode_space
5963 && mnem_p
[-2] == 's')
5965 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5966 mnemonic
, mnemonic
);
5967 i
.suffix
= LONG_MNEM_SUFFIX
;
5971 current_templates
= NULL
;
5979 if (!current_templates
)
5982 as_bad (_("no such instruction: `%s'"), token_start
);
5987 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5988 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5990 /* Check for a branch hint. We allow ",pt" and ",pn" for
5991 predict taken and predict not taken respectively.
5992 I'm not sure that branch hints actually do anything on loop
5993 and jcxz insns (JumpByte) for current Pentium4 chips. They
5994 may work in the future and it doesn't hurt to accept them
5996 if (l
[0] == ',' && l
[1] == 'p')
6000 if (!add_prefix (DS_PREFIX_OPCODE
))
6004 else if (l
[2] == 'n')
6006 if (!add_prefix (CS_PREFIX_OPCODE
))
6012 /* Any other comma loses. */
6015 as_bad (_("invalid character %s in mnemonic"),
6016 output_invalid (*l
));
6020 /* Check if instruction is supported on specified architecture. */
6022 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6024 supported
|= cpu_flags_match (t
);
6026 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6027 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6029 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6035 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6036 i
.error
= unsupported_on_arch
;
6038 i
.error
= unsupported_64bit
;
6045 parse_operands (char *l
, const char *mnemonic
)
6049 /* 1 if operand is pending after ','. */
6050 unsigned int expecting_operand
= 0;
6052 while (*l
!= END_OF_INSN
)
6054 /* Non-zero if operand parens not balanced. */
6055 unsigned int paren_not_balanced
= 0;
6056 /* True if inside double quotes. */
6057 bool in_quotes
= false;
6059 /* Skip optional white space before operand. */
6060 if (is_space_char (*l
))
6062 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6064 as_bad (_("invalid character %s before operand %d"),
6065 output_invalid (*l
),
6069 token_start
= l
; /* After white space. */
6070 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6072 if (*l
== END_OF_INSN
)
6076 as_bad (_("unbalanced double quotes in operand %d."),
6080 if (paren_not_balanced
)
6082 know (!intel_syntax
);
6083 as_bad (_("unbalanced parenthesis in operand %d."),
6088 break; /* we are done */
6090 else if (*l
== '\\' && l
[1] == '"')
6093 in_quotes
= !in_quotes
;
6094 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6096 as_bad (_("invalid character %s in operand %d"),
6097 output_invalid (*l
),
6101 if (!intel_syntax
&& !in_quotes
)
6104 ++paren_not_balanced
;
6106 --paren_not_balanced
;
6110 if (l
!= token_start
)
6111 { /* Yes, we've read in another operand. */
6112 unsigned int operand_ok
;
6113 this_operand
= i
.operands
++;
6114 if (i
.operands
> MAX_OPERANDS
)
6116 as_bad (_("spurious operands; (%d operands/instruction max)"),
6120 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6121 /* Now parse operand adding info to 'i' as we go along. */
6122 END_STRING_AND_SAVE (l
);
6124 if (i
.mem_operands
> 1)
6126 as_bad (_("too many memory references for `%s'"),
6133 i386_intel_operand (token_start
,
6134 intel_float_operand (mnemonic
));
6136 operand_ok
= i386_att_operand (token_start
);
6138 RESTORE_END_STRING (l
);
6144 if (expecting_operand
)
6146 expecting_operand_after_comma
:
6147 as_bad (_("expecting operand after ','; got nothing"));
6152 as_bad (_("expecting operand before ','; got nothing"));
6157 /* Now *l must be either ',' or END_OF_INSN. */
6160 if (*++l
== END_OF_INSN
)
6162 /* Just skip it, if it's \n complain. */
6163 goto expecting_operand_after_comma
;
6165 expecting_operand
= 1;
6172 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6174 union i386_op temp_op
;
6175 i386_operand_type temp_type
;
6176 unsigned int temp_flags
;
6177 enum bfd_reloc_code_real temp_reloc
;
6179 temp_type
= i
.types
[xchg2
];
6180 i
.types
[xchg2
] = i
.types
[xchg1
];
6181 i
.types
[xchg1
] = temp_type
;
6183 temp_flags
= i
.flags
[xchg2
];
6184 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6185 i
.flags
[xchg1
] = temp_flags
;
6187 temp_op
= i
.op
[xchg2
];
6188 i
.op
[xchg2
] = i
.op
[xchg1
];
6189 i
.op
[xchg1
] = temp_op
;
6191 temp_reloc
= i
.reloc
[xchg2
];
6192 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6193 i
.reloc
[xchg1
] = temp_reloc
;
6195 temp_flags
= i
.imm_bits
[xchg2
];
6196 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6197 i
.imm_bits
[xchg1
] = temp_flags
;
6201 if (i
.mask
.operand
== xchg1
)
6202 i
.mask
.operand
= xchg2
;
6203 else if (i
.mask
.operand
== xchg2
)
6204 i
.mask
.operand
= xchg1
;
6206 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6208 if (i
.broadcast
.operand
== xchg1
)
6209 i
.broadcast
.operand
= xchg2
;
6210 else if (i
.broadcast
.operand
== xchg2
)
6211 i
.broadcast
.operand
= xchg1
;
6216 swap_operands (void)
6222 swap_2_operands (1, i
.operands
- 2);
6226 swap_2_operands (0, i
.operands
- 1);
6232 if (i
.mem_operands
== 2)
6234 const reg_entry
*temp_seg
;
6235 temp_seg
= i
.seg
[0];
6236 i
.seg
[0] = i
.seg
[1];
6237 i
.seg
[1] = temp_seg
;
6241 /* Try to ensure constant immediates are represented in the smallest
6246 char guess_suffix
= 0;
6250 guess_suffix
= i
.suffix
;
6251 else if (i
.reg_operands
)
6253 /* Figure out a suffix from the last register operand specified.
6254 We can't do this properly yet, i.e. excluding special register
6255 instances, but the following works for instructions with
6256 immediates. In any case, we can't set i.suffix yet. */
6257 for (op
= i
.operands
; --op
>= 0;)
6258 if (i
.types
[op
].bitfield
.class != Reg
)
6260 else if (i
.types
[op
].bitfield
.byte
)
6262 guess_suffix
= BYTE_MNEM_SUFFIX
;
6265 else if (i
.types
[op
].bitfield
.word
)
6267 guess_suffix
= WORD_MNEM_SUFFIX
;
6270 else if (i
.types
[op
].bitfield
.dword
)
6272 guess_suffix
= LONG_MNEM_SUFFIX
;
6275 else if (i
.types
[op
].bitfield
.qword
)
6277 guess_suffix
= QWORD_MNEM_SUFFIX
;
6281 else if ((flag_code
== CODE_16BIT
)
6282 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6283 guess_suffix
= WORD_MNEM_SUFFIX
;
6284 else if (flag_code
!= CODE_64BIT
6285 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6286 /* A more generic (but also more involved) way of dealing
6287 with the special case(s) would be to go look for
6288 DefaultSize attributes on any of the templates. */
6289 && current_templates
->start
->mnem_off
!= MN_push
))
6290 guess_suffix
= LONG_MNEM_SUFFIX
;
6292 for (op
= i
.operands
; --op
>= 0;)
6293 if (operand_type_check (i
.types
[op
], imm
))
6295 switch (i
.op
[op
].imms
->X_op
)
6298 /* If a suffix is given, this operand may be shortened. */
6299 switch (guess_suffix
)
6301 case LONG_MNEM_SUFFIX
:
6302 i
.types
[op
].bitfield
.imm32
= 1;
6303 i
.types
[op
].bitfield
.imm64
= 1;
6305 case WORD_MNEM_SUFFIX
:
6306 i
.types
[op
].bitfield
.imm16
= 1;
6307 i
.types
[op
].bitfield
.imm32
= 1;
6308 i
.types
[op
].bitfield
.imm32s
= 1;
6309 i
.types
[op
].bitfield
.imm64
= 1;
6311 case BYTE_MNEM_SUFFIX
:
6312 i
.types
[op
].bitfield
.imm8
= 1;
6313 i
.types
[op
].bitfield
.imm8s
= 1;
6314 i
.types
[op
].bitfield
.imm16
= 1;
6315 i
.types
[op
].bitfield
.imm32
= 1;
6316 i
.types
[op
].bitfield
.imm32s
= 1;
6317 i
.types
[op
].bitfield
.imm64
= 1;
6321 /* If this operand is at most 16 bits, convert it
6322 to a signed 16 bit number before trying to see
6323 whether it will fit in an even smaller size.
6324 This allows a 16-bit operand such as $0xffe0 to
6325 be recognised as within Imm8S range. */
6326 if ((i
.types
[op
].bitfield
.imm16
)
6327 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6329 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6330 ^ 0x8000) - 0x8000);
6333 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6334 if ((i
.types
[op
].bitfield
.imm32
)
6335 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6337 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6338 ^ ((offsetT
) 1 << 31))
6339 - ((offsetT
) 1 << 31));
6343 = operand_type_or (i
.types
[op
],
6344 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6346 /* We must avoid matching of Imm32 templates when 64bit
6347 only immediate is available. */
6348 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6349 i
.types
[op
].bitfield
.imm32
= 0;
6356 /* Symbols and expressions. */
6358 /* Convert symbolic operand to proper sizes for matching, but don't
6359 prevent matching a set of insns that only supports sizes other
6360 than those matching the insn suffix. */
6362 i386_operand_type mask
, allowed
;
6363 const insn_template
*t
= current_templates
->start
;
6365 operand_type_set (&mask
, 0);
6366 switch (guess_suffix
)
6368 case QWORD_MNEM_SUFFIX
:
6369 mask
.bitfield
.imm64
= 1;
6370 mask
.bitfield
.imm32s
= 1;
6372 case LONG_MNEM_SUFFIX
:
6373 mask
.bitfield
.imm32
= 1;
6375 case WORD_MNEM_SUFFIX
:
6376 mask
.bitfield
.imm16
= 1;
6378 case BYTE_MNEM_SUFFIX
:
6379 mask
.bitfield
.imm8
= 1;
6385 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6386 while (++t
< current_templates
->end
)
6388 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6389 allowed
= operand_type_and (allowed
, mask
);
6392 if (!operand_type_all_zero (&allowed
))
6393 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6400 /* Try to use the smallest displacement type too. */
6402 optimize_disp (const insn_template
*t
)
6406 if (!want_disp32 (t
)
6407 && (!t
->opcode_modifier
.jump
6408 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6410 for (op
= 0; op
< i
.operands
; ++op
)
6412 const expressionS
*exp
= i
.op
[op
].disps
;
6414 if (!operand_type_check (i
.types
[op
], disp
))
6417 if (exp
->X_op
!= O_constant
)
6420 /* Since displacement is signed extended to 64bit, don't allow
6421 disp32 if it is out of range. */
6422 if (fits_in_signed_long (exp
->X_add_number
))
6425 i
.types
[op
].bitfield
.disp32
= 0;
6426 if (i
.types
[op
].bitfield
.baseindex
)
6428 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6429 (uint64_t) exp
->X_add_number
);
6435 /* Don't optimize displacement for movabs since it only takes 64bit
6437 if (i
.disp_encoding
> disp_encoding_8bit
6438 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6441 for (op
= i
.operands
; op
-- > 0;)
6442 if (operand_type_check (i
.types
[op
], disp
))
6444 if (i
.op
[op
].disps
->X_op
== O_constant
)
6446 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6448 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6450 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6451 i
.op
[op
].disps
= NULL
;
6456 if (i
.types
[op
].bitfield
.disp16
6457 && fits_in_unsigned_word (op_disp
))
6459 /* If this operand is at most 16 bits, convert
6460 to a signed 16 bit number and don't use 64bit
6462 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6463 i
.types
[op
].bitfield
.disp64
= 0;
6467 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6468 if ((flag_code
!= CODE_64BIT
6469 ? i
.types
[op
].bitfield
.disp32
6471 && (!t
->opcode_modifier
.jump
6472 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6473 && fits_in_unsigned_long (op_disp
))
6475 /* If this operand is at most 32 bits, convert
6476 to a signed 32 bit number and don't use 64bit
6478 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6479 i
.types
[op
].bitfield
.disp64
= 0;
6480 i
.types
[op
].bitfield
.disp32
= 1;
6483 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6485 i
.types
[op
].bitfield
.disp64
= 0;
6486 i
.types
[op
].bitfield
.disp32
= 1;
6489 if ((i
.types
[op
].bitfield
.disp32
6490 || i
.types
[op
].bitfield
.disp16
)
6491 && fits_in_disp8 (op_disp
))
6492 i
.types
[op
].bitfield
.disp8
= 1;
6494 i
.op
[op
].disps
->X_add_number
= op_disp
;
6496 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6497 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6499 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6500 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6501 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6504 /* We only support 64bit displacement on constants. */
6505 i
.types
[op
].bitfield
.disp64
= 0;
6511 /* Return 1 if there is a match in broadcast bytes between operand
6512 GIVEN and instruction template T. */
6515 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6517 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6518 && i
.types
[given
].bitfield
.byte
)
6519 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6520 && i
.types
[given
].bitfield
.word
)
6521 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6522 && i
.types
[given
].bitfield
.dword
)
6523 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6524 && i
.types
[given
].bitfield
.qword
));
6527 /* Check if operands are valid for the instruction. */
6530 check_VecOperands (const insn_template
*t
)
6535 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6536 any one operand are implicity requiring AVX512VL support if the actual
6537 operand size is YMMword or XMMword. Since this function runs after
6538 template matching, there's no need to check for YMMword/XMMword in
6540 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6541 if (!cpu_flags_all_zero (&cpu
)
6542 && !is_cpu (t
, CpuAVX512VL
)
6543 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6544 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6546 for (op
= 0; op
< t
->operands
; ++op
)
6548 if (t
->operand_types
[op
].bitfield
.zmmword
6549 && (i
.types
[op
].bitfield
.ymmword
6550 || i
.types
[op
].bitfield
.xmmword
))
6552 i
.error
= unsupported
;
6558 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6559 requiring AVX2 support if the actual operand size is YMMword. */
6560 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6561 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6563 for (op
= 0; op
< t
->operands
; ++op
)
6565 if (t
->operand_types
[op
].bitfield
.xmmword
6566 && i
.types
[op
].bitfield
.ymmword
)
6568 i
.error
= unsupported
;
6574 /* Without VSIB byte, we can't have a vector register for index. */
6575 if (!t
->opcode_modifier
.sib
6577 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6578 || i
.index_reg
->reg_type
.bitfield
.ymmword
6579 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6581 i
.error
= unsupported_vector_index_register
;
6585 /* Check if default mask is allowed. */
6586 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6587 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6589 i
.error
= no_default_mask
;
6593 /* For VSIB byte, we need a vector register for index, and all vector
6594 registers must be distinct. */
6595 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6598 || !((t
->opcode_modifier
.sib
== VECSIB128
6599 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6600 || (t
->opcode_modifier
.sib
== VECSIB256
6601 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6602 || (t
->opcode_modifier
.sib
== VECSIB512
6603 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6605 i
.error
= invalid_vsib_address
;
6609 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6610 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6612 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6613 gas_assert (i
.types
[0].bitfield
.xmmword
6614 || i
.types
[0].bitfield
.ymmword
);
6615 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6616 gas_assert (i
.types
[2].bitfield
.xmmword
6617 || i
.types
[2].bitfield
.ymmword
);
6618 if (operand_check
== check_none
)
6620 if (register_number (i
.op
[0].regs
)
6621 != register_number (i
.index_reg
)
6622 && register_number (i
.op
[2].regs
)
6623 != register_number (i
.index_reg
)
6624 && register_number (i
.op
[0].regs
)
6625 != register_number (i
.op
[2].regs
))
6627 if (operand_check
== check_error
)
6629 i
.error
= invalid_vector_register_set
;
6632 as_warn (_("mask, index, and destination registers should be distinct"));
6634 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6636 if (i
.types
[1].bitfield
.class == RegSIMD
6637 && (i
.types
[1].bitfield
.xmmword
6638 || i
.types
[1].bitfield
.ymmword
6639 || i
.types
[1].bitfield
.zmmword
)
6640 && (register_number (i
.op
[1].regs
)
6641 == register_number (i
.index_reg
)))
6643 if (operand_check
== check_error
)
6645 i
.error
= invalid_vector_register_set
;
6648 if (operand_check
!= check_none
)
6649 as_warn (_("index and destination registers should be distinct"));
6654 /* For AMX instructions with 3 TMM register operands, all operands
6655 must be distinct. */
6656 if (i
.reg_operands
== 3
6657 && t
->operand_types
[0].bitfield
.tmmword
6658 && (i
.op
[0].regs
== i
.op
[1].regs
6659 || i
.op
[0].regs
== i
.op
[2].regs
6660 || i
.op
[1].regs
== i
.op
[2].regs
))
6662 i
.error
= invalid_tmm_register_set
;
6666 /* For some special instructions require that destination must be distinct
6667 from source registers. */
6668 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6670 unsigned int dest_reg
= i
.operands
- 1;
6672 know (i
.operands
>= 3);
6674 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6675 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6676 || (i
.reg_operands
> 2
6677 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6679 i
.error
= invalid_dest_and_src_register_set
;
6684 /* Check if broadcast is supported by the instruction and is applied
6685 to the memory operand. */
6686 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6688 i386_operand_type type
, overlap
;
6690 /* Check if specified broadcast is supported in this instruction,
6691 and its broadcast bytes match the memory operand. */
6692 op
= i
.broadcast
.operand
;
6693 if (!t
->opcode_modifier
.broadcast
6694 || !(i
.flags
[op
] & Operand_Mem
)
6695 || (!i
.types
[op
].bitfield
.unspecified
6696 && !match_broadcast_size (t
, op
)))
6699 i
.error
= unsupported_broadcast
;
6703 operand_type_set (&type
, 0);
6704 switch (get_broadcast_bytes (t
, false))
6707 type
.bitfield
.word
= 1;
6710 type
.bitfield
.dword
= 1;
6713 type
.bitfield
.qword
= 1;
6716 type
.bitfield
.xmmword
= 1;
6719 if (vector_size
< VSZ256
)
6721 type
.bitfield
.ymmword
= 1;
6724 if (vector_size
< VSZ512
)
6726 type
.bitfield
.zmmword
= 1;
6732 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6733 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6734 && t
->operand_types
[op
].bitfield
.byte
6735 + t
->operand_types
[op
].bitfield
.word
6736 + t
->operand_types
[op
].bitfield
.dword
6737 + t
->operand_types
[op
].bitfield
.qword
> 1)
6739 overlap
.bitfield
.xmmword
= 0;
6740 overlap
.bitfield
.ymmword
= 0;
6741 overlap
.bitfield
.zmmword
= 0;
6743 if (operand_type_all_zero (&overlap
))
6746 if (t
->opcode_modifier
.checkoperandsize
)
6750 type
.bitfield
.baseindex
= 1;
6751 for (j
= 0; j
< i
.operands
; ++j
)
6754 && !operand_type_register_match(i
.types
[j
],
6755 t
->operand_types
[j
],
6757 t
->operand_types
[op
]))
6762 /* If broadcast is supported in this instruction, we need to check if
6763 operand of one-element size isn't specified without broadcast. */
6764 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6766 /* Find memory operand. */
6767 for (op
= 0; op
< i
.operands
; op
++)
6768 if (i
.flags
[op
] & Operand_Mem
)
6770 gas_assert (op
< i
.operands
);
6771 /* Check size of the memory operand. */
6772 if (match_broadcast_size (t
, op
))
6774 i
.error
= broadcast_needed
;
6779 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6781 /* Check if requested masking is supported. */
6784 if (!t
->opcode_modifier
.masking
)
6786 i
.error
= unsupported_masking
;
6790 /* Common rules for masking:
6791 - mask register destinations permit only zeroing-masking, without
6792 that actually being expressed by a {z} operand suffix or EVEX.z,
6793 - memory destinations allow only merging-masking,
6794 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6797 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6798 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6799 || t
->opcode_modifier
.sib
))
6801 i
.error
= unsupported_masking
;
6806 /* Check if masking is applied to dest operand. */
6807 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6809 i
.error
= mask_not_on_destination
;
6814 if (i
.rounding
.type
!= rc_none
)
6816 if (!t
->opcode_modifier
.sae
6817 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6820 i
.error
= unsupported_rc_sae
;
6824 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6826 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6828 for (op
= 0; op
< t
->operands
; ++op
)
6829 if (i
.types
[op
].bitfield
.zmmword
)
6831 if (op
>= t
->operands
)
6833 i
.error
= operand_size_mismatch
;
6839 /* Check the special Imm4 cases; must be the first operand. */
6840 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6842 if (i
.op
[0].imms
->X_op
!= O_constant
6843 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6849 /* Turn off Imm<N> so that update_imm won't complain. */
6850 operand_type_set (&i
.types
[0], 0);
6853 /* Check vector Disp8 operand. */
6854 if (t
->opcode_modifier
.disp8memshift
6855 && (!t
->opcode_modifier
.vex
6856 || need_evex_encoding ())
6857 && i
.disp_encoding
<= disp_encoding_8bit
)
6859 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6860 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6861 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6862 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6865 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6868 for (op
= 0; op
< i
.operands
; op
++)
6869 if (i
.flags
[op
] & Operand_Mem
)
6871 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6872 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6873 else if (t
->operand_types
[op
].bitfield
.xmmword
6874 + t
->operand_types
[op
].bitfield
.ymmword
6875 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6876 type
= &t
->operand_types
[op
];
6877 else if (!i
.types
[op
].bitfield
.unspecified
)
6878 type
= &i
.types
[op
];
6879 else /* Ambiguities get resolved elsewhere. */
6880 fallback
= &t
->operand_types
[op
];
6882 else if (i
.types
[op
].bitfield
.class == RegSIMD
6883 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6885 if (i
.types
[op
].bitfield
.zmmword
)
6887 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6889 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6893 if (!type
&& !i
.memshift
)
6897 if (type
->bitfield
.zmmword
)
6899 else if (type
->bitfield
.ymmword
)
6901 else if (type
->bitfield
.xmmword
)
6905 /* For the check in fits_in_disp8(). */
6906 if (i
.memshift
== 0)
6910 for (op
= 0; op
< i
.operands
; op
++)
6911 if (operand_type_check (i
.types
[op
], disp
)
6912 && i
.op
[op
].disps
->X_op
== O_constant
)
6914 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6916 i
.types
[op
].bitfield
.disp8
= 1;
6919 i
.types
[op
].bitfield
.disp8
= 0;
6928 /* Check if encoding requirements are met by the instruction. */
6931 VEX_check_encoding (const insn_template
*t
)
6933 if (i
.vec_encoding
== vex_encoding_error
)
6935 i
.error
= unsupported
;
6939 /* Vector size restrictions. */
6940 if ((vector_size
< VSZ512
6941 && (t
->opcode_modifier
.evex
== EVEX512
6942 || t
->opcode_modifier
.vsz
>= VSZ512
))
6943 || (vector_size
< VSZ256
6944 && (t
->opcode_modifier
.evex
== EVEX256
6945 || t
->opcode_modifier
.vex
== VEX256
6946 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6948 i
.error
= unsupported
;
6952 if (i
.vec_encoding
== vex_encoding_evex
6953 || i
.vec_encoding
== vex_encoding_evex512
)
6955 /* This instruction must be encoded with EVEX prefix. */
6956 if (!is_evex_encoding (t
))
6958 i
.error
= unsupported
;
6964 if (!t
->opcode_modifier
.vex
)
6966 /* This instruction template doesn't have VEX prefix. */
6967 if (i
.vec_encoding
!= vex_encoding_default
)
6969 i
.error
= unsupported
;
6978 /* Helper function for the progress() macro in match_template(). */
6979 static INLINE
enum i386_error
progress (enum i386_error
new,
6980 enum i386_error last
,
6981 unsigned int line
, unsigned int *line_p
)
6983 if (line
<= *line_p
)
6989 static const insn_template
*
6990 match_template (char mnem_suffix
)
6992 /* Points to template once we've found it. */
6993 const insn_template
*t
;
6994 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6995 i386_operand_type overlap4
;
6996 unsigned int found_reverse_match
;
6997 i386_operand_type operand_types
[MAX_OPERANDS
];
6998 int addr_prefix_disp
;
6999 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7000 enum i386_error specific_error
= number_of_operands_mismatch
;
7001 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7003 #if MAX_OPERANDS != 5
7004 # error "MAX_OPERANDS must be 5."
7007 found_reverse_match
= 0;
7008 addr_prefix_disp
= -1;
7010 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7012 addr_prefix_disp
= -1;
7013 found_reverse_match
= 0;
7015 /* Must have right number of operands. */
7016 if (i
.operands
!= t
->operands
)
7019 /* Check processor support. */
7020 specific_error
= progress (unsupported
);
7021 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7024 /* Check AT&T mnemonic. */
7025 specific_error
= progress (unsupported_with_intel_mnemonic
);
7026 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7029 /* Check AT&T/Intel syntax. */
7030 specific_error
= progress (unsupported_syntax
);
7031 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7032 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7035 /* Check Intel64/AMD64 ISA. */
7039 /* Default: Don't accept Intel64. */
7040 if (t
->opcode_modifier
.isa64
== INTEL64
)
7044 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7045 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7049 /* -mintel64: Don't accept AMD64. */
7050 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7055 /* Check the suffix. */
7056 specific_error
= progress (invalid_instruction_suffix
);
7057 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7058 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7059 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7060 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7061 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7064 specific_error
= progress (operand_size_mismatch
);
7065 size_match
= operand_size_match (t
);
7069 /* This is intentionally not
7071 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7073 as the case of a missing * on the operand is accepted (perhaps with
7074 a warning, issued further down). */
7075 specific_error
= progress (operand_type_mismatch
);
7076 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7079 /* In Intel syntax, normally we can check for memory operand size when
7080 there is no mnemonic suffix. But jmp and call have 2 different
7081 encodings with Dword memory operand size. Skip the "near" one
7082 (permitting a register operand) when "far" was requested. */
7084 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7085 && t
->operand_types
[0].bitfield
.class == Reg
)
7088 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7089 operand_types
[j
] = t
->operand_types
[j
];
7091 /* In general, don't allow 32-bit operands on pre-386. */
7092 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7093 : operand_size_mismatch
);
7094 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7095 if (i
.suffix
== LONG_MNEM_SUFFIX
7096 && !cpu_arch_flags
.bitfield
.cpui386
7098 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7099 && !intel_float_operand (insn_name (t
)))
7100 : intel_float_operand (insn_name (t
)) != 2)
7101 && (t
->operands
== i
.imm_operands
7102 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7103 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7104 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7105 || (operand_types
[j
].bitfield
.class != RegMMX
7106 && operand_types
[j
].bitfield
.class != RegSIMD
7107 && operand_types
[j
].bitfield
.class != RegMask
))
7108 && !t
->opcode_modifier
.sib
)
7111 /* Do not verify operands when there are none. */
7114 if (VEX_check_encoding (t
))
7116 specific_error
= progress (i
.error
);
7120 /* We've found a match; break out of loop. */
7124 if (!t
->opcode_modifier
.jump
7125 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7127 /* There should be only one Disp operand. */
7128 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7129 if (operand_type_check (operand_types
[j
], disp
))
7131 if (j
< MAX_OPERANDS
)
7133 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7135 addr_prefix_disp
= j
;
7137 /* Address size prefix will turn Disp64 operand into Disp32 and
7138 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7142 override
= !override
;
7145 if (operand_types
[j
].bitfield
.disp32
7146 && operand_types
[j
].bitfield
.disp16
)
7148 operand_types
[j
].bitfield
.disp16
= override
;
7149 operand_types
[j
].bitfield
.disp32
= !override
;
7151 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7155 if (operand_types
[j
].bitfield
.disp64
)
7157 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7158 operand_types
[j
].bitfield
.disp32
= override
;
7159 operand_types
[j
].bitfield
.disp64
= !override
;
7161 operand_types
[j
].bitfield
.disp16
= 0;
7167 /* We check register size if needed. */
7168 if (t
->opcode_modifier
.checkoperandsize
)
7170 check_register
= (1 << t
->operands
) - 1;
7171 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7172 check_register
&= ~(1 << i
.broadcast
.operand
);
7177 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7178 switch (t
->operands
)
7181 if (!operand_type_match (overlap0
, i
.types
[0]))
7184 /* Allow the ModR/M encoding to be requested by using the {load} or
7185 {store} pseudo prefix on an applicable insn. */
7186 if (!t
->opcode_modifier
.modrm
7187 && i
.reg_operands
== 1
7188 && ((i
.dir_encoding
== dir_encoding_load
7189 && t
->mnem_off
!= MN_pop
)
7190 || (i
.dir_encoding
== dir_encoding_store
7191 && t
->mnem_off
!= MN_push
))
7193 && t
->mnem_off
!= MN_bswap
)
7198 /* xchg %eax, %eax is a special case. It is an alias for nop
7199 only in 32bit mode and we can use opcode 0x90. In 64bit
7200 mode, we can't use 0x90 for xchg %eax, %eax since it should
7201 zero-extend %eax to %rax. */
7202 if (t
->base_opcode
== 0x90
7203 && t
->opcode_space
== SPACE_BASE
)
7205 if (flag_code
== CODE_64BIT
7206 && i
.types
[0].bitfield
.instance
== Accum
7207 && i
.types
[0].bitfield
.dword
7208 && i
.types
[1].bitfield
.instance
== Accum
)
7211 /* Allow the ModR/M encoding to be requested by using the
7212 {load} or {store} pseudo prefix. */
7213 if (i
.dir_encoding
== dir_encoding_load
7214 || i
.dir_encoding
== dir_encoding_store
)
7218 if (t
->base_opcode
== MOV_AX_DISP32
7219 && t
->opcode_space
== SPACE_BASE
7220 && t
->mnem_off
!= MN_movabs
)
7222 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7223 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7226 /* xrelease mov %eax, <disp> is another special case. It must not
7227 match the accumulator-only encoding of mov. */
7231 /* Allow the ModR/M encoding to be requested by using a suitable
7232 {load} or {store} pseudo prefix. */
7233 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7234 ? dir_encoding_store
7235 : dir_encoding_load
)
7236 && !i
.types
[0].bitfield
.disp64
7237 && !i
.types
[1].bitfield
.disp64
)
7241 /* Allow the ModR/M encoding to be requested by using the {load} or
7242 {store} pseudo prefix on an applicable insn. */
7243 if (!t
->opcode_modifier
.modrm
7244 && i
.reg_operands
== 1
7245 && i
.imm_operands
== 1
7246 && (i
.dir_encoding
== dir_encoding_load
7247 || i
.dir_encoding
== dir_encoding_store
)
7248 && t
->opcode_space
== SPACE_BASE
)
7250 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7251 && i
.dir_encoding
== dir_encoding_store
)
7254 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7255 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7256 || i
.dir_encoding
== dir_encoding_load
))
7259 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7260 && i
.dir_encoding
== dir_encoding_load
)
7266 if (!(size_match
& MATCH_STRAIGHT
))
7268 /* Reverse direction of operands if swapping is possible in the first
7269 place (operands need to be symmetric) and
7270 - the load form is requested, and the template is a store form,
7271 - the store form is requested, and the template is a load form,
7272 - the non-default (swapped) form is requested. */
7273 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7274 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7275 && !operand_type_all_zero (&overlap1
))
7276 switch (i
.dir_encoding
)
7278 case dir_encoding_load
:
7279 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7280 || t
->opcode_modifier
.regmem
)
7284 case dir_encoding_store
:
7285 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7286 && !t
->opcode_modifier
.regmem
)
7290 case dir_encoding_swap
:
7293 case dir_encoding_default
:
7296 /* If we want store form, we skip the current load. */
7297 if ((i
.dir_encoding
== dir_encoding_store
7298 || i
.dir_encoding
== dir_encoding_swap
)
7299 && i
.mem_operands
== 0
7300 && t
->opcode_modifier
.load
)
7305 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7306 if (!operand_type_match (overlap0
, i
.types
[0])
7307 || !operand_type_match (overlap1
, i
.types
[1])
7308 || ((check_register
& 3) == 3
7309 && !operand_type_register_match (i
.types
[0],
7314 specific_error
= progress (i
.error
);
7316 /* Check if other direction is valid ... */
7317 if (!t
->opcode_modifier
.d
)
7321 if (!(size_match
& MATCH_REVERSE
))
7323 /* Try reversing direction of operands. */
7324 j
= is_cpu (t
, CpuFMA4
)
7325 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7326 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7327 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7328 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7329 gas_assert (t
->operands
!= 3 || !check_register
);
7330 if (!operand_type_match (overlap0
, i
.types
[0])
7331 || !operand_type_match (overlap1
, i
.types
[j
])
7332 || (t
->operands
== 3
7333 && !operand_type_match (overlap2
, i
.types
[1]))
7335 && !operand_type_register_match (i
.types
[0],
7340 /* Does not match either direction. */
7341 specific_error
= progress (i
.error
);
7344 /* found_reverse_match holds which variant of D
7346 if (!t
->opcode_modifier
.d
)
7347 found_reverse_match
= 0;
7348 else if (operand_types
[0].bitfield
.tbyte
)
7350 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7351 found_reverse_match
= Opcode_FloatD
;
7353 found_reverse_match
= ~0;
7354 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7355 if ((t
->extension_opcode
& 4)
7356 && (intel_syntax
|| intel_mnemonic
))
7357 found_reverse_match
|= Opcode_FloatR
;
7359 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7361 found_reverse_match
= Opcode_VexW
;
7362 goto check_operands_345
;
7364 else if (t
->opcode_space
!= SPACE_BASE
7365 && (t
->opcode_space
!= SPACE_0F
7366 /* MOV to/from CR/DR/TR, as an exception, follow
7367 the base opcode space encoding model. */
7368 || (t
->base_opcode
| 7) != 0x27))
7369 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7370 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7371 else if (!t
->opcode_modifier
.commutative
)
7372 found_reverse_match
= Opcode_D
;
7374 found_reverse_match
= ~0;
7378 /* Found a forward 2 operand match here. */
7380 switch (t
->operands
)
7383 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7384 if (!operand_type_match (overlap4
, i
.types
[4])
7385 || !operand_type_register_match (i
.types
[3],
7390 specific_error
= progress (i
.error
);
7395 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7396 if (!operand_type_match (overlap3
, i
.types
[3])
7397 || ((check_register
& 0xa) == 0xa
7398 && !operand_type_register_match (i
.types
[1],
7402 || ((check_register
& 0xc) == 0xc
7403 && !operand_type_register_match (i
.types
[2],
7408 specific_error
= progress (i
.error
);
7413 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7414 if (!operand_type_match (overlap2
, i
.types
[2])
7415 || ((check_register
& 5) == 5
7416 && !operand_type_register_match (i
.types
[0],
7420 || ((check_register
& 6) == 6
7421 && !operand_type_register_match (i
.types
[1],
7426 specific_error
= progress (i
.error
);
7432 /* Found either forward/reverse 2, 3 or 4 operand match here:
7433 slip through to break. */
7436 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7437 if (VEX_check_encoding (t
))
7439 specific_error
= progress (i
.error
);
7443 /* Check if vector operands are valid. */
7444 if (check_VecOperands (t
))
7446 specific_error
= progress (i
.error
);
7450 /* Check whether to use the shorter VEX encoding for certain insns where
7451 the EVEX enconding comes first in the table. This requires the respective
7452 AVX-* feature to be explicitly enabled. */
7453 if (t
== current_templates
->start
7454 && t
->opcode_modifier
.disp8memshift
7455 && !t
->opcode_modifier
.vex
7456 && !need_evex_encoding ()
7457 && t
+ 1 < current_templates
->end
7458 && t
[1].opcode_modifier
.vex
)
7461 unsigned int memshift
= i
.memshift
;
7464 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7465 if (!cpu_flags_all_zero (&cpu
)
7466 && (!i
.types
[0].bitfield
.disp8
7467 || !operand_type_check (i
.types
[0], disp
)
7468 || i
.op
[0].disps
->X_op
!= O_constant
7469 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7471 specific_error
= progress (internal_error
);
7474 i
.memshift
= memshift
;
7477 /* We've found a match; break out of loop. */
7483 if (t
== current_templates
->end
)
7485 /* We found no match. */
7486 i
.error
= specific_error
;
7490 if (!quiet_warnings
)
7493 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7494 as_warn (_("indirect %s without `*'"), insn_name (t
));
7496 if (t
->opcode_modifier
.isprefix
7497 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7499 /* Warn them that a data or address size prefix doesn't
7500 affect assembly of the next line of code. */
7501 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7505 /* Copy the template we found. */
7506 install_template (t
);
7508 if (addr_prefix_disp
!= -1)
7509 i
.tm
.operand_types
[addr_prefix_disp
]
7510 = operand_types
[addr_prefix_disp
];
7512 switch (found_reverse_match
)
7518 case Opcode_FloatR
| Opcode_FloatD
:
7519 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7520 found_reverse_match
&= Opcode_FloatD
;
7524 /* If we found a reverse match we must alter the opcode direction
7525 bit and clear/flip the regmem modifier one. found_reverse_match
7526 holds bits to change (different for int & float insns). */
7528 i
.tm
.base_opcode
^= found_reverse_match
;
7530 /* Certain SIMD insns have their load forms specified in the opcode
7531 table, and hence we need to _set_ RegMem instead of clearing it.
7532 We need to avoid setting the bit though on insns like KMOVW. */
7533 i
.tm
.opcode_modifier
.regmem
7534 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7535 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7536 && !i
.tm
.opcode_modifier
.regmem
;
7540 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7541 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7545 /* Only the first two register operands need reversing, alongside
7547 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7549 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7550 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7551 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7561 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7562 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7564 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7566 as_bad (_("`%s' operand %u must use `%ses' segment"),
7568 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7573 /* There's only ever one segment override allowed per instruction.
7574 This instruction possibly has a legal segment override on the
7575 second operand, so copy the segment to where non-string
7576 instructions store it, allowing common code. */
7577 i
.seg
[op
] = i
.seg
[1];
7583 process_suffix (void)
7585 bool is_movx
= false;
7587 /* If matched instruction specifies an explicit instruction mnemonic
7589 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7590 i
.suffix
= WORD_MNEM_SUFFIX
;
7591 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7592 i
.suffix
= LONG_MNEM_SUFFIX
;
7593 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7594 i
.suffix
= QWORD_MNEM_SUFFIX
;
7595 else if (i
.reg_operands
7596 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7597 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7599 unsigned int numop
= i
.operands
;
7602 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7603 && (i
.tm
.base_opcode
| 8) == 0xbe)
7604 || (i
.tm
.opcode_space
== SPACE_BASE
7605 && i
.tm
.base_opcode
== 0x63
7606 && is_cpu (&i
.tm
, Cpu64
));
7608 /* movsx/movzx want only their source operand considered here, for the
7609 ambiguity checking below. The suffix will be replaced afterwards
7610 to represent the destination (register). */
7611 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7614 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7615 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7618 /* If there's no instruction mnemonic suffix we try to invent one
7619 based on GPR operands. */
7622 /* We take i.suffix from the last register operand specified,
7623 Destination register type is more significant than source
7624 register type. crc32 in SSE4.2 prefers source register
7626 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7629 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7630 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7632 if (i
.types
[op
].bitfield
.class != Reg
)
7634 if (i
.types
[op
].bitfield
.byte
)
7635 i
.suffix
= BYTE_MNEM_SUFFIX
;
7636 else if (i
.types
[op
].bitfield
.word
)
7637 i
.suffix
= WORD_MNEM_SUFFIX
;
7638 else if (i
.types
[op
].bitfield
.dword
)
7639 i
.suffix
= LONG_MNEM_SUFFIX
;
7640 else if (i
.types
[op
].bitfield
.qword
)
7641 i
.suffix
= QWORD_MNEM_SUFFIX
;
7647 /* As an exception, movsx/movzx silently default to a byte source
7649 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7650 i
.suffix
= BYTE_MNEM_SUFFIX
;
7652 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7654 if (!check_byte_reg ())
7657 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7659 if (!check_long_reg ())
7662 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7664 if (!check_qword_reg ())
7667 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7669 if (!check_word_reg ())
7672 else if (intel_syntax
7673 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7674 /* Do nothing if the instruction is going to ignore the prefix. */
7679 /* Undo the movsx/movzx change done above. */
7682 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7685 i
.suffix
= stackop_size
;
7686 if (stackop_size
== LONG_MNEM_SUFFIX
)
7688 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7689 .code16gcc directive to support 16-bit mode with
7690 32-bit address. For IRET without a suffix, generate
7691 16-bit IRET (opcode 0xcf) to return from an interrupt
7693 if (i
.tm
.base_opcode
== 0xcf)
7695 i
.suffix
= WORD_MNEM_SUFFIX
;
7696 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7698 /* Warn about changed behavior for segment register push/pop. */
7699 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7700 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7705 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7706 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7707 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7708 || (i
.tm
.opcode_space
== SPACE_0F
7709 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7710 && i
.tm
.extension_opcode
<= 3)))
7715 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7717 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7718 || i
.tm
.opcode_modifier
.no_lsuf
)
7719 i
.suffix
= QWORD_MNEM_SUFFIX
;
7724 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7725 i
.suffix
= LONG_MNEM_SUFFIX
;
7728 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7729 i
.suffix
= WORD_MNEM_SUFFIX
;
7735 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7736 /* Also cover lret/retf/iret in 64-bit mode. */
7737 || (flag_code
== CODE_64BIT
7738 && !i
.tm
.opcode_modifier
.no_lsuf
7739 && !i
.tm
.opcode_modifier
.no_qsuf
))
7740 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7741 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7742 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7743 /* Accept FLDENV et al without suffix. */
7744 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7746 unsigned int suffixes
, evex
= 0;
7748 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7749 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7751 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7753 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7755 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7758 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7759 also suitable for AT&T syntax mode, it was requested that this be
7760 restricted to just Intel syntax. */
7761 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7762 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7766 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7768 if (vector_size
< VSZ512
)
7770 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7771 if (vector_size
< VSZ256
)
7773 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7774 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7775 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7776 || (!i
.tm
.opcode_modifier
.evex
7777 && is_evex_encoding (&i
.tm
))))
7778 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7780 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7781 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7782 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7783 || (!i
.tm
.opcode_modifier
.evex
7784 && is_evex_encoding (&i
.tm
))))
7785 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7787 else if (is_evex_encoding (&i
.tm
)
7788 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7790 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7791 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7792 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7793 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7794 if (!i
.tm
.opcode_modifier
.evex
7795 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7796 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7799 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7800 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7801 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7804 /* Any properly sized operand disambiguates the insn. */
7805 if (i
.types
[op
].bitfield
.xmmword
7806 || i
.types
[op
].bitfield
.ymmword
7807 || i
.types
[op
].bitfield
.zmmword
)
7809 suffixes
&= ~(7 << 6);
7814 if ((i
.flags
[op
] & Operand_Mem
)
7815 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7817 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7819 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7821 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7823 if (is_evex_encoding (&i
.tm
))
7829 /* Are multiple suffixes / operand sizes allowed? */
7830 if (suffixes
& (suffixes
- 1))
7833 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7834 || operand_check
== check_error
))
7836 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7839 if (operand_check
== check_error
)
7841 as_bad (_("no instruction mnemonic suffix given and "
7842 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7845 if (operand_check
== check_warning
)
7846 as_warn (_("%s; using default for `%s'"),
7848 ? _("ambiguous operand size")
7849 : _("no instruction mnemonic suffix given and "
7850 "no register operands"),
7853 if (i
.tm
.opcode_modifier
.floatmf
)
7854 i
.suffix
= SHORT_MNEM_SUFFIX
;
7856 /* handled below */;
7858 i
.tm
.opcode_modifier
.evex
= evex
;
7859 else if (flag_code
== CODE_16BIT
)
7860 i
.suffix
= WORD_MNEM_SUFFIX
;
7861 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7862 i
.suffix
= LONG_MNEM_SUFFIX
;
7864 i
.suffix
= QWORD_MNEM_SUFFIX
;
7870 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7871 In AT&T syntax, if there is no suffix (warned about above), the default
7872 will be byte extension. */
7873 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7874 i
.tm
.base_opcode
|= 1;
7876 /* For further processing, the suffix should represent the destination
7877 (register). This is already the case when one was used with
7878 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7879 no suffix to begin with. */
7880 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7882 if (i
.types
[1].bitfield
.word
)
7883 i
.suffix
= WORD_MNEM_SUFFIX
;
7884 else if (i
.types
[1].bitfield
.qword
)
7885 i
.suffix
= QWORD_MNEM_SUFFIX
;
7887 i
.suffix
= LONG_MNEM_SUFFIX
;
7889 i
.tm
.opcode_modifier
.w
= 0;
7893 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7894 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7895 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7897 /* Change the opcode based on the operand size given by i.suffix. */
7900 /* Size floating point instruction. */
7901 case LONG_MNEM_SUFFIX
:
7902 if (i
.tm
.opcode_modifier
.floatmf
)
7904 i
.tm
.base_opcode
^= 4;
7908 case WORD_MNEM_SUFFIX
:
7909 case QWORD_MNEM_SUFFIX
:
7910 /* It's not a byte, select word/dword operation. */
7911 if (i
.tm
.opcode_modifier
.w
)
7914 i
.tm
.base_opcode
|= 8;
7916 i
.tm
.base_opcode
|= 1;
7919 case SHORT_MNEM_SUFFIX
:
7920 /* Now select between word & dword operations via the operand
7921 size prefix, except for instructions that will ignore this
7923 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7924 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7925 && !i
.tm
.opcode_modifier
.floatmf
7926 && !is_any_vex_encoding (&i
.tm
)
7927 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7928 || (flag_code
== CODE_64BIT
7929 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7931 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7933 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7934 prefix
= ADDR_PREFIX_OPCODE
;
7936 if (!add_prefix (prefix
))
7940 /* Set mode64 for an operand. */
7941 if (i
.suffix
== QWORD_MNEM_SUFFIX
7942 && flag_code
== CODE_64BIT
7943 && !i
.tm
.opcode_modifier
.norex64
7944 && !i
.tm
.opcode_modifier
.vexw
7945 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7947 && ! (i
.operands
== 2
7948 && i
.tm
.base_opcode
== 0x90
7949 && i
.tm
.opcode_space
== SPACE_BASE
7950 && i
.types
[0].bitfield
.instance
== Accum
7951 && i
.types
[0].bitfield
.qword
7952 && i
.types
[1].bitfield
.instance
== Accum
))
7958 /* Select word/dword/qword operation with explicit data sizing prefix
7959 when there are no suitable register operands. */
7960 if (i
.tm
.opcode_modifier
.w
7961 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7963 || (i
.reg_operands
== 1
7965 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7967 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7968 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7969 || i
.tm
.mnem_off
== MN_crc32
))))
7970 i
.tm
.base_opcode
|= 1;
7974 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7976 gas_assert (!i
.suffix
);
7977 gas_assert (i
.reg_operands
);
7979 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7982 /* The address size override prefix changes the size of the
7984 if (flag_code
== CODE_64BIT
7985 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7987 as_bad (_("16-bit addressing unavailable for `%s'"),
7992 if ((flag_code
== CODE_32BIT
7993 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7994 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7995 && !add_prefix (ADDR_PREFIX_OPCODE
))
8000 /* Check invalid register operand when the address size override
8001 prefix changes the size of register operands. */
8003 enum { need_word
, need_dword
, need_qword
} need
;
8005 /* Check the register operand for the address size prefix if
8006 the memory operand has no real registers, like symbol, DISP
8007 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8008 if (i
.mem_operands
== 1
8009 && i
.reg_operands
== 1
8011 && i
.types
[1].bitfield
.class == Reg
8012 && (flag_code
== CODE_32BIT
8013 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8014 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8015 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8016 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8017 || (x86_elf_abi
== X86_64_X32_ABI
8019 && i
.base_reg
->reg_num
== RegIP
8020 && i
.base_reg
->reg_type
.bitfield
.qword
))
8024 && !add_prefix (ADDR_PREFIX_OPCODE
))
8027 if (flag_code
== CODE_32BIT
)
8028 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8029 else if (i
.prefix
[ADDR_PREFIX
])
8032 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8034 for (op
= 0; op
< i
.operands
; op
++)
8036 if (i
.types
[op
].bitfield
.class != Reg
)
8042 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8046 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8050 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8055 as_bad (_("invalid register operand size for `%s'"),
8066 check_byte_reg (void)
8070 for (op
= i
.operands
; --op
>= 0;)
8072 /* Skip non-register operands. */
8073 if (i
.types
[op
].bitfield
.class != Reg
)
8076 /* If this is an eight bit register, it's OK. If it's the 16 or
8077 32 bit version of an eight bit register, we will just use the
8078 low portion, and that's OK too. */
8079 if (i
.types
[op
].bitfield
.byte
)
8082 /* I/O port address operands are OK too. */
8083 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8084 && i
.tm
.operand_types
[op
].bitfield
.word
)
8087 /* crc32 only wants its source operand checked here. */
8088 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8091 /* Any other register is bad. */
8092 as_bad (_("`%s%s' not allowed with `%s%c'"),
8093 register_prefix
, i
.op
[op
].regs
->reg_name
,
8094 insn_name (&i
.tm
), i
.suffix
);
8101 check_long_reg (void)
8105 for (op
= i
.operands
; --op
>= 0;)
8106 /* Skip non-register operands. */
8107 if (i
.types
[op
].bitfield
.class != Reg
)
8109 /* Reject eight bit registers, except where the template requires
8110 them. (eg. movzb) */
8111 else if (i
.types
[op
].bitfield
.byte
8112 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8113 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8114 && (i
.tm
.operand_types
[op
].bitfield
.word
8115 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8117 as_bad (_("`%s%s' not allowed with `%s%c'"),
8119 i
.op
[op
].regs
->reg_name
,
8124 /* Error if the e prefix on a general reg is missing. */
8125 else if (i
.types
[op
].bitfield
.word
8126 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8127 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8128 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8130 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8131 register_prefix
, i
.op
[op
].regs
->reg_name
,
8135 /* Warn if the r prefix on a general reg is present. */
8136 else if (i
.types
[op
].bitfield
.qword
8137 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8138 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8139 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8141 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8142 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8149 check_qword_reg (void)
8153 for (op
= i
.operands
; --op
>= 0; )
8154 /* Skip non-register operands. */
8155 if (i
.types
[op
].bitfield
.class != Reg
)
8157 /* Reject eight bit registers, except where the template requires
8158 them. (eg. movzb) */
8159 else if (i
.types
[op
].bitfield
.byte
8160 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8161 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8162 && (i
.tm
.operand_types
[op
].bitfield
.word
8163 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8165 as_bad (_("`%s%s' not allowed with `%s%c'"),
8167 i
.op
[op
].regs
->reg_name
,
8172 /* Warn if the r prefix on a general reg is missing. */
8173 else if ((i
.types
[op
].bitfield
.word
8174 || i
.types
[op
].bitfield
.dword
)
8175 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8176 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8177 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8179 /* Prohibit these changes in the 64bit mode, since the
8180 lowering is more complicated. */
8181 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8182 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8189 check_word_reg (void)
8192 for (op
= i
.operands
; --op
>= 0;)
8193 /* Skip non-register operands. */
8194 if (i
.types
[op
].bitfield
.class != Reg
)
8196 /* Reject eight bit registers, except where the template requires
8197 them. (eg. movzb) */
8198 else if (i
.types
[op
].bitfield
.byte
8199 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8200 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8201 && (i
.tm
.operand_types
[op
].bitfield
.word
8202 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8204 as_bad (_("`%s%s' not allowed with `%s%c'"),
8206 i
.op
[op
].regs
->reg_name
,
8211 /* Error if the e or r prefix on a general reg is present. */
8212 else if ((i
.types
[op
].bitfield
.dword
8213 || i
.types
[op
].bitfield
.qword
)
8214 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8215 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8216 && i
.tm
.operand_types
[op
].bitfield
.word
)
8218 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8219 register_prefix
, i
.op
[op
].regs
->reg_name
,
8227 update_imm (unsigned int j
)
8229 i386_operand_type overlap
= i
.types
[j
];
8231 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8232 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8233 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8235 /* This combination is used on 8-bit immediates where e.g. $~0 is
8236 desirable to permit. We're past operand type matching, so simply
8237 put things back in the shape they were before introducing the
8238 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8239 overlap
.bitfield
.imm8s
= 0;
8242 if (overlap
.bitfield
.imm8
8243 + overlap
.bitfield
.imm8s
8244 + overlap
.bitfield
.imm16
8245 + overlap
.bitfield
.imm32
8246 + overlap
.bitfield
.imm32s
8247 + overlap
.bitfield
.imm64
> 1)
8249 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8250 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8251 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8252 static const i386_operand_type imm16_32
= { .bitfield
=
8253 { .imm16
= 1, .imm32
= 1 }
8255 static const i386_operand_type imm16_32s
= { .bitfield
=
8256 { .imm16
= 1, .imm32s
= 1 }
8258 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8259 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8264 i386_operand_type temp
;
8266 operand_type_set (&temp
, 0);
8267 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8269 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8270 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8272 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8273 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8274 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8276 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8277 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8280 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8283 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8284 || operand_type_equal (&overlap
, &imm16_32
)
8285 || operand_type_equal (&overlap
, &imm16_32s
))
8287 if ((flag_code
== CODE_16BIT
)
8288 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8293 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8294 overlap
= operand_type_and (overlap
, imm32s
);
8295 else if (i
.prefix
[DATA_PREFIX
])
8296 overlap
= operand_type_and (overlap
,
8297 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8298 if (overlap
.bitfield
.imm8
8299 + overlap
.bitfield
.imm8s
8300 + overlap
.bitfield
.imm16
8301 + overlap
.bitfield
.imm32
8302 + overlap
.bitfield
.imm32s
8303 + overlap
.bitfield
.imm64
!= 1)
8305 as_bad (_("no instruction mnemonic suffix given; "
8306 "can't determine immediate size"));
8310 i
.types
[j
] = overlap
;
8320 /* Update the first 2 immediate operands. */
8321 n
= i
.operands
> 2 ? 2 : i
.operands
;
8324 for (j
= 0; j
< n
; j
++)
8325 if (update_imm (j
) == 0)
8328 /* The 3rd operand can't be immediate operand. */
8329 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8335 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8338 if (r
->reg_flags
& RegRex
)
8340 if (i
.rex
& rex_bit
)
8341 as_bad (_("same type of prefix used twice"));
8344 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8346 gas_assert (i
.vex
.register_specifier
== r
);
8347 i
.vex
.register_specifier
+= 8;
8350 if (r
->reg_flags
& RegVRex
)
8355 process_operands (void)
8357 /* Default segment register this instruction will use for memory
8358 accesses. 0 means unknown. This is only for optimizing out
8359 unnecessary segment overrides. */
8360 const reg_entry
*default_seg
= NULL
;
8362 /* We only need to check those implicit registers for instructions
8363 with 3 operands or less. */
8364 if (i
.operands
<= 3)
8365 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8366 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8369 if (i
.tm
.opcode_modifier
.sse2avx
)
8371 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8373 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8374 i
.prefix
[REX_PREFIX
] = 0;
8377 /* ImmExt should be processed after SSE2AVX. */
8378 else if (i
.tm
.opcode_modifier
.immext
)
8381 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8382 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8383 new destination operand here, while converting the source one to register
8385 if (i
.tm
.mnem_off
== MN_tilezero
)
8387 i
.op
[1].regs
= i
.op
[0].regs
;
8388 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8389 i
.types
[1] = i
.types
[0];
8390 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8391 i
.flags
[1] = i
.flags
[0];
8397 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8399 static const i386_operand_type regxmm
= {
8400 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8402 unsigned int dupl
= i
.operands
;
8403 unsigned int dest
= dupl
- 1;
8406 /* The destination must be an xmm register. */
8407 gas_assert (i
.reg_operands
8408 && MAX_OPERANDS
> dupl
8409 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8411 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8412 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8414 /* Keep xmm0 for instructions with VEX prefix and 3
8416 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8417 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8422 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8424 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8426 /* Add the implicit xmm0 for instructions with VEX prefix
8428 for (j
= i
.operands
; j
> 0; j
--)
8430 i
.op
[j
] = i
.op
[j
- 1];
8431 i
.types
[j
] = i
.types
[j
- 1];
8432 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8433 i
.flags
[j
] = i
.flags
[j
- 1];
8436 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8437 i
.types
[0] = regxmm
;
8438 i
.tm
.operand_types
[0] = regxmm
;
8441 i
.reg_operands
+= 2;
8446 i
.op
[dupl
] = i
.op
[dest
];
8447 i
.types
[dupl
] = i
.types
[dest
];
8448 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8449 i
.flags
[dupl
] = i
.flags
[dest
];
8458 i
.op
[dupl
] = i
.op
[dest
];
8459 i
.types
[dupl
] = i
.types
[dest
];
8460 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8461 i
.flags
[dupl
] = i
.flags
[dest
];
8464 if (i
.tm
.opcode_modifier
.immext
)
8467 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8468 && i
.tm
.opcode_modifier
.modrm
)
8472 for (j
= 1; j
< i
.operands
; j
++)
8474 i
.op
[j
- 1] = i
.op
[j
];
8475 i
.types
[j
- 1] = i
.types
[j
];
8477 /* We need to adjust fields in i.tm since they are used by
8478 build_modrm_byte. */
8479 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8481 i
.flags
[j
- 1] = i
.flags
[j
];
8484 /* No adjustment to i.reg_operands: This was already done at the top
8489 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8491 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8493 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8494 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8495 regnum
= register_number (i
.op
[1].regs
);
8496 first_reg_in_group
= regnum
& ~3;
8497 last_reg_in_group
= first_reg_in_group
+ 3;
8498 if (regnum
!= first_reg_in_group
)
8499 as_warn (_("source register `%s%s' implicitly denotes"
8500 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8501 register_prefix
, i
.op
[1].regs
->reg_name
,
8502 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8503 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8506 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8508 /* The imul $imm, %reg instruction is converted into
8509 imul $imm, %reg, %reg, and the clr %reg instruction
8510 is converted into xor %reg, %reg. */
8512 unsigned int first_reg_op
;
8514 if (operand_type_check (i
.types
[0], reg
))
8518 /* Pretend we saw the extra register operand. */
8519 gas_assert (i
.reg_operands
== 1
8520 && i
.op
[first_reg_op
+ 1].regs
== 0);
8521 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8522 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8527 if (i
.tm
.opcode_modifier
.modrm
)
8529 /* The opcode is completed (modulo i.tm.extension_opcode which
8530 must be put into the modrm byte). Now, we make the modrm and
8531 index base bytes based on all the info we've collected. */
8533 default_seg
= build_modrm_byte ();
8535 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8537 /* Warn about some common errors, but press on regardless. */
8538 if (i
.operands
== 2)
8540 /* Reversed arguments on faddp or fmulp. */
8541 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8542 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8543 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8545 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8547 /* Extraneous `l' suffix on fp insn. */
8548 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8549 register_prefix
, i
.op
[0].regs
->reg_name
);
8553 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8555 if (flag_code
!= CODE_64BIT
8556 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8557 && i
.op
[0].regs
->reg_num
== 1
8558 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8559 && i
.op
[0].regs
->reg_num
< 4)
8561 as_bad (_("you can't `%s %s%s'"),
8562 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8565 if (i
.op
[0].regs
->reg_num
> 3
8566 && i
.tm
.opcode_space
== SPACE_BASE
)
8568 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8569 i
.tm
.opcode_space
= SPACE_0F
;
8571 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8573 else if (i
.tm
.opcode_space
== SPACE_BASE
8574 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8576 default_seg
= reg_ds
;
8578 else if (i
.tm
.opcode_modifier
.isstring
)
8580 /* For the string instructions that allow a segment override
8581 on one of their operands, the default segment is ds. */
8582 default_seg
= reg_ds
;
8584 else if (i
.short_form
)
8586 /* The register operand is in the 1st or 2nd non-immediate operand. */
8587 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8590 && r
->reg_type
.bitfield
.instance
== Accum
8591 && i
.op
[i
.imm_operands
+ 1].regs
)
8592 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8593 /* Register goes in low 3 bits of opcode. */
8594 i
.tm
.base_opcode
|= r
->reg_num
;
8595 set_rex_vrex (r
, REX_B
, false);
8597 if (dot_insn () && i
.reg_operands
== 2)
8599 gas_assert (is_any_vex_encoding (&i
.tm
)
8600 || i
.vec_encoding
!= vex_encoding_default
);
8601 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8604 else if (i
.reg_operands
== 1
8605 && !i
.flags
[i
.operands
- 1]
8606 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8609 gas_assert (is_any_vex_encoding (&i
.tm
)
8610 || i
.vec_encoding
!= vex_encoding_default
);
8611 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8614 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8615 && i
.tm
.mnem_off
== MN_lea
)
8617 if (!quiet_warnings
)
8618 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8619 if (optimize
&& !i
.no_optimize
)
8622 i
.prefix
[SEG_PREFIX
] = 0;
8626 /* If a segment was explicitly specified, and the specified segment
8627 is neither the default nor the one already recorded from a prefix,
8628 use an opcode prefix to select it. If we never figured out what
8629 the default segment is, then default_seg will be zero at this
8630 point, and the specified segment prefix will always be used. */
8632 && i
.seg
[0] != default_seg
8633 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8635 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8641 static const reg_entry
*
8642 build_modrm_byte (void)
8644 const reg_entry
*default_seg
= NULL
;
8645 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8646 /* Compensate for kludge in md_assemble(). */
8647 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8648 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8649 unsigned int v
, op
, reg_slot
= ~0;
8651 /* Accumulator (in particular %st), shift count (%cl), and alike need
8652 to be skipped just like immediate operands do. */
8653 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8655 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8658 for (op
= source
; op
< i
.operands
; ++op
)
8659 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8662 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8666 /* There are 2 kinds of instructions:
8667 1. 5 operands: 4 register operands or 3 register operands
8668 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8669 VexW0 or VexW1. The destination must be either XMM, YMM or
8671 2. 4 operands: 4 register operands or 3 register operands
8672 plus 1 memory operand, with VexXDS.
8673 3. Other equivalent combinations when coming from s_insn(). */
8674 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8675 && i
.tm
.opcode_modifier
.vexw
);
8676 gas_assert (dot_insn ()
8677 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8679 /* Of the first two non-immediate operands the one with the template
8680 not allowing for a memory one is encoded in the immediate operand. */
8682 reg_slot
= source
+ 1;
8684 reg_slot
= source
++;
8688 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8689 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8692 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8694 if (i
.imm_operands
== 0)
8696 /* When there is no immediate operand, generate an 8bit
8697 immediate operand to encode the first operand. */
8698 exp
= &im_expressions
[i
.imm_operands
++];
8699 i
.op
[i
.operands
].imms
= exp
;
8700 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8703 exp
->X_op
= O_constant
;
8707 gas_assert (i
.imm_operands
== 1);
8708 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8709 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8711 /* Turn on Imm8 again so that output_imm will generate it. */
8712 i
.types
[0].bitfield
.imm8
= 1;
8716 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8717 << (3 + !(is_evex_encoding (&i
.tm
)
8718 || i
.vec_encoding
== vex_encoding_evex
));
8721 for (v
= source
+ 1; v
< dest
; ++v
)
8726 if (i
.tm
.extension_opcode
!= None
)
8732 gas_assert (source
< dest
);
8733 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8736 unsigned int tmp
= source
;
8742 if (v
< MAX_OPERANDS
)
8744 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8745 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8748 if (op
< i
.operands
)
8752 unsigned int fake_zero_displacement
= 0;
8754 gas_assert (i
.flags
[op
] & Operand_Mem
);
8756 if (i
.tm
.opcode_modifier
.sib
)
8758 /* The index register of VSIB shouldn't be RegIZ. */
8759 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8760 && i
.index_reg
->reg_num
== RegIZ
)
8763 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8766 i
.sib
.base
= NO_BASE_REGISTER
;
8767 i
.sib
.scale
= i
.log2_scale_factor
;
8768 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8769 i
.types
[op
].bitfield
.disp32
= 1;
8772 /* Since the mandatory SIB always has index register, so
8773 the code logic remains unchanged. The non-mandatory SIB
8774 without index register is allowed and will be handled
8778 if (i
.index_reg
->reg_num
== RegIZ
)
8779 i
.sib
.index
= NO_INDEX_REGISTER
;
8781 i
.sib
.index
= i
.index_reg
->reg_num
;
8782 set_rex_vrex (i
.index_reg
, REX_X
, false);
8786 default_seg
= reg_ds
;
8788 if (i
.base_reg
== 0)
8791 if (!i
.disp_operands
)
8792 fake_zero_displacement
= 1;
8793 if (i
.index_reg
== 0)
8795 /* Both check for VSIB and mandatory non-vector SIB. */
8796 gas_assert (!i
.tm
.opcode_modifier
.sib
8797 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8798 /* Operand is just <disp> */
8799 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8800 if (flag_code
== CODE_64BIT
)
8802 /* 64bit mode overwrites the 32bit absolute
8803 addressing by RIP relative addressing and
8804 absolute addressing is encoded by one of the
8805 redundant SIB forms. */
8806 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8807 i
.sib
.base
= NO_BASE_REGISTER
;
8808 i
.sib
.index
= NO_INDEX_REGISTER
;
8809 i
.types
[op
].bitfield
.disp32
= 1;
8811 else if ((flag_code
== CODE_16BIT
)
8812 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8814 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8815 i
.types
[op
].bitfield
.disp16
= 1;
8819 i
.rm
.regmem
= NO_BASE_REGISTER
;
8820 i
.types
[op
].bitfield
.disp32
= 1;
8823 else if (!i
.tm
.opcode_modifier
.sib
)
8825 /* !i.base_reg && i.index_reg */
8826 if (i
.index_reg
->reg_num
== RegIZ
)
8827 i
.sib
.index
= NO_INDEX_REGISTER
;
8829 i
.sib
.index
= i
.index_reg
->reg_num
;
8830 i
.sib
.base
= NO_BASE_REGISTER
;
8831 i
.sib
.scale
= i
.log2_scale_factor
;
8832 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8833 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8834 i
.types
[op
].bitfield
.disp32
= 1;
8835 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8839 /* RIP addressing for 64bit mode. */
8840 else if (i
.base_reg
->reg_num
== RegIP
)
8842 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8843 i
.rm
.regmem
= NO_BASE_REGISTER
;
8844 i
.types
[op
].bitfield
.disp8
= 0;
8845 i
.types
[op
].bitfield
.disp16
= 0;
8846 i
.types
[op
].bitfield
.disp32
= 1;
8847 i
.types
[op
].bitfield
.disp64
= 0;
8848 i
.flags
[op
] |= Operand_PCrel
;
8849 if (! i
.disp_operands
)
8850 fake_zero_displacement
= 1;
8852 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8854 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8855 switch (i
.base_reg
->reg_num
)
8858 if (i
.index_reg
== 0)
8860 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8861 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8864 default_seg
= reg_ss
;
8865 if (i
.index_reg
== 0)
8868 if (operand_type_check (i
.types
[op
], disp
) == 0)
8870 /* fake (%bp) into 0(%bp) */
8871 if (i
.disp_encoding
== disp_encoding_16bit
)
8872 i
.types
[op
].bitfield
.disp16
= 1;
8874 i
.types
[op
].bitfield
.disp8
= 1;
8875 fake_zero_displacement
= 1;
8878 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8879 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8881 default: /* (%si) -> 4 or (%di) -> 5 */
8882 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8884 if (!fake_zero_displacement
8888 fake_zero_displacement
= 1;
8889 if (i
.disp_encoding
== disp_encoding_8bit
)
8890 i
.types
[op
].bitfield
.disp8
= 1;
8892 i
.types
[op
].bitfield
.disp16
= 1;
8894 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8896 else /* i.base_reg and 32/64 bit mode */
8898 if (operand_type_check (i
.types
[op
], disp
))
8900 i
.types
[op
].bitfield
.disp16
= 0;
8901 i
.types
[op
].bitfield
.disp64
= 0;
8902 i
.types
[op
].bitfield
.disp32
= 1;
8905 if (!i
.tm
.opcode_modifier
.sib
)
8906 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8907 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8909 i
.sib
.base
= i
.base_reg
->reg_num
;
8910 /* x86-64 ignores REX prefix bit here to avoid decoder
8912 if (!(i
.base_reg
->reg_flags
& RegRex
)
8913 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8914 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8915 default_seg
= reg_ss
;
8916 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8918 fake_zero_displacement
= 1;
8919 if (i
.disp_encoding
== disp_encoding_32bit
)
8920 i
.types
[op
].bitfield
.disp32
= 1;
8922 i
.types
[op
].bitfield
.disp8
= 1;
8924 i
.sib
.scale
= i
.log2_scale_factor
;
8925 if (i
.index_reg
== 0)
8927 /* Only check for VSIB. */
8928 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8929 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8930 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8932 /* <disp>(%esp) becomes two byte modrm with no index
8933 register. We've already stored the code for esp
8934 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8935 Any base register besides %esp will not use the
8936 extra modrm byte. */
8937 i
.sib
.index
= NO_INDEX_REGISTER
;
8939 else if (!i
.tm
.opcode_modifier
.sib
)
8941 if (i
.index_reg
->reg_num
== RegIZ
)
8942 i
.sib
.index
= NO_INDEX_REGISTER
;
8944 i
.sib
.index
= i
.index_reg
->reg_num
;
8945 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8946 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8951 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8952 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8956 if (!fake_zero_displacement
8960 fake_zero_displacement
= 1;
8961 if (i
.disp_encoding
== disp_encoding_8bit
)
8962 i
.types
[op
].bitfield
.disp8
= 1;
8964 i
.types
[op
].bitfield
.disp32
= 1;
8966 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8970 if (fake_zero_displacement
)
8972 /* Fakes a zero displacement assuming that i.types[op]
8973 holds the correct displacement size. */
8976 gas_assert (i
.op
[op
].disps
== 0);
8977 exp
= &disp_expressions
[i
.disp_operands
++];
8978 i
.op
[op
].disps
= exp
;
8979 exp
->X_op
= O_constant
;
8980 exp
->X_add_number
= 0;
8981 exp
->X_add_symbol
= (symbolS
*) 0;
8982 exp
->X_op_symbol
= (symbolS
*) 0;
8988 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8989 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
9000 if (!i
.tm
.opcode_modifier
.regmem
)
9002 gas_assert (source
< MAX_OPERANDS
);
9003 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9004 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9005 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9010 gas_assert (dest
< MAX_OPERANDS
);
9011 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9012 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9017 /* Fill in i.rm.reg field with extension opcode (if any) or the
9018 appropriate register. */
9019 if (i
.tm
.extension_opcode
!= None
)
9020 i
.rm
.reg
= i
.tm
.extension_opcode
;
9021 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9023 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9024 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9028 gas_assert (source
< MAX_OPERANDS
);
9029 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9030 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9033 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9035 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9037 add_prefix (LOCK_PREFIX_OPCODE
);
9044 frag_opcode_byte (unsigned char byte
)
9046 if (now_seg
!= absolute_section
)
9047 FRAG_APPEND_1_CHAR (byte
);
9049 ++abs_section_offset
;
9053 flip_code16 (unsigned int code16
)
9055 gas_assert (i
.tm
.operands
== 1);
9057 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9058 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9059 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9064 output_branch (void)
9070 relax_substateT subtype
;
9074 if (now_seg
== absolute_section
)
9076 as_bad (_("relaxable branches not supported in absolute section"));
9080 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9081 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9084 if (i
.prefix
[DATA_PREFIX
] != 0)
9088 code16
^= flip_code16(code16
);
9090 /* Pentium4 branch hints. */
9091 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9092 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9097 if (i
.prefix
[REX_PREFIX
] != 0)
9103 /* BND prefixed jump. */
9104 if (i
.prefix
[BND_PREFIX
] != 0)
9110 if (i
.prefixes
!= 0)
9111 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9113 /* It's always a symbol; End frag & setup for relax.
9114 Make sure there is enough room in this frag for the largest
9115 instruction we may generate in md_convert_frag. This is 2
9116 bytes for the opcode and room for the prefix and largest
9118 frag_grow (prefix
+ 2 + 4);
9119 /* Prefix and 1 opcode byte go in fr_fix. */
9120 p
= frag_more (prefix
+ 1);
9121 if (i
.prefix
[DATA_PREFIX
] != 0)
9122 *p
++ = DATA_PREFIX_OPCODE
;
9123 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9124 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9125 *p
++ = i
.prefix
[SEG_PREFIX
];
9126 if (i
.prefix
[BND_PREFIX
] != 0)
9127 *p
++ = BND_PREFIX_OPCODE
;
9128 if (i
.prefix
[REX_PREFIX
] != 0)
9129 *p
++ = i
.prefix
[REX_PREFIX
];
9130 *p
= i
.tm
.base_opcode
;
9132 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9133 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9134 else if (cpu_arch_flags
.bitfield
.cpui386
)
9135 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9137 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9140 sym
= i
.op
[0].disps
->X_add_symbol
;
9141 off
= i
.op
[0].disps
->X_add_number
;
9143 if (i
.op
[0].disps
->X_op
!= O_constant
9144 && i
.op
[0].disps
->X_op
!= O_symbol
)
9146 /* Handle complex expressions. */
9147 sym
= make_expr_symbol (i
.op
[0].disps
);
9151 /* 1 possible extra opcode + 4 byte displacement go in var part.
9152 Pass reloc in fr_var. */
9153 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9157 /* Return TRUE iff PLT32 relocation should be used for branching to
9161 need_plt32_p (symbolS
*s
)
9163 /* PLT32 relocation is ELF only. */
9168 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9169 krtld support it. */
9173 /* Since there is no need to prepare for PLT branch on x86-64, we
9174 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9175 be used as a marker for 32-bit PC-relative branches. */
9182 /* Weak or undefined symbol need PLT32 relocation. */
9183 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9186 /* Non-global symbol doesn't need PLT32 relocation. */
9187 if (! S_IS_EXTERNAL (s
))
9190 /* Other global symbols need PLT32 relocation. NB: Symbol with
9191 non-default visibilities are treated as normal global symbol
9192 so that PLT32 relocation can be used as a marker for 32-bit
9193 PC-relative branches. It is useful for linker relaxation. */
9204 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9206 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9208 /* This is a loop or jecxz type instruction. */
9210 if (i
.prefix
[ADDR_PREFIX
] != 0)
9212 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9215 /* Pentium4 branch hints. */
9216 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9217 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9219 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9228 if (flag_code
== CODE_16BIT
)
9231 if (i
.prefix
[DATA_PREFIX
] != 0)
9233 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9235 code16
^= flip_code16(code16
);
9243 /* BND prefixed jump. */
9244 if (i
.prefix
[BND_PREFIX
] != 0)
9246 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9250 if (i
.prefix
[REX_PREFIX
] != 0)
9252 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9256 if (i
.prefixes
!= 0)
9257 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9259 if (now_seg
== absolute_section
)
9261 abs_section_offset
+= i
.opcode_length
+ size
;
9265 p
= frag_more (i
.opcode_length
+ size
);
9266 switch (i
.opcode_length
)
9269 *p
++ = i
.tm
.base_opcode
>> 8;
9272 *p
++ = i
.tm
.base_opcode
;
9278 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9279 if (flag_code
== CODE_64BIT
&& size
== 4
9280 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9281 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9282 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9285 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9287 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9288 i
.op
[0].disps
, 1, jump_reloc
);
9290 /* All jumps handled here are signed, but don't unconditionally use a
9291 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9292 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9297 fixP
->fx_signed
= 1;
9301 if (i
.tm
.mnem_off
== MN_xbegin
)
9302 fixP
->fx_signed
= 1;
9306 if (flag_code
== CODE_64BIT
)
9307 fixP
->fx_signed
= 1;
9313 output_interseg_jump (void)
9321 if (flag_code
== CODE_16BIT
)
9325 if (i
.prefix
[DATA_PREFIX
] != 0)
9332 gas_assert (!i
.prefix
[REX_PREFIX
]);
9338 if (i
.prefixes
!= 0)
9339 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9341 if (now_seg
== absolute_section
)
9343 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9347 /* 1 opcode; 2 segment; offset */
9348 p
= frag_more (prefix
+ 1 + 2 + size
);
9350 if (i
.prefix
[DATA_PREFIX
] != 0)
9351 *p
++ = DATA_PREFIX_OPCODE
;
9353 if (i
.prefix
[REX_PREFIX
] != 0)
9354 *p
++ = i
.prefix
[REX_PREFIX
];
9356 *p
++ = i
.tm
.base_opcode
;
9357 if (i
.op
[1].imms
->X_op
== O_constant
)
9359 offsetT n
= i
.op
[1].imms
->X_add_number
;
9362 && !fits_in_unsigned_word (n
)
9363 && !fits_in_signed_word (n
))
9365 as_bad (_("16-bit jump out of range"));
9368 md_number_to_chars (p
, n
, size
);
9371 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9372 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9375 if (i
.op
[0].imms
->X_op
== O_constant
)
9376 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9378 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9379 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9387 asection
*seg
= now_seg
;
9388 subsegT subseg
= now_subseg
;
9390 unsigned int alignment
, align_size_1
;
9391 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9392 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9393 unsigned int padding
;
9395 if (!IS_ELF
|| !x86_used_note
)
9398 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9400 /* The .note.gnu.property section layout:
9402 Field Length Contents
9405 n_descsz 4 The note descriptor size
9406 n_type 4 NT_GNU_PROPERTY_TYPE_0
9408 n_desc n_descsz The program property array
9412 /* Create the .note.gnu.property section. */
9413 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9414 bfd_set_section_flags (sec
,
9421 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9432 bfd_set_section_alignment (sec
, alignment
);
9433 elf_section_type (sec
) = SHT_NOTE
;
9435 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9437 isa_1_descsz_raw
= 4 + 4 + 4;
9438 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9439 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9441 feature_2_descsz_raw
= isa_1_descsz
;
9442 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9444 feature_2_descsz_raw
+= 4 + 4 + 4;
9445 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9446 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9449 descsz
= feature_2_descsz
;
9450 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9451 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9453 /* Write n_namsz. */
9454 md_number_to_chars (p
, (valueT
) 4, 4);
9456 /* Write n_descsz. */
9457 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9460 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9463 memcpy (p
+ 4 * 3, "GNU", 4);
9465 /* Write 4-byte type. */
9466 md_number_to_chars (p
+ 4 * 4,
9467 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9469 /* Write 4-byte data size. */
9470 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9472 /* Write 4-byte data. */
9473 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9475 /* Zero out paddings. */
9476 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9478 memset (p
+ 4 * 7, 0, padding
);
9480 /* Write 4-byte type. */
9481 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9482 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9484 /* Write 4-byte data size. */
9485 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9487 /* Write 4-byte data. */
9488 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9489 (valueT
) x86_feature_2_used
, 4);
9491 /* Zero out paddings. */
9492 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9494 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9496 /* We probably can't restore the current segment, for there likely
9499 subseg_set (seg
, subseg
);
9503 x86_support_sframe_p (void)
9505 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9506 return (x86_elf_abi
== X86_64_ABI
);
9510 x86_sframe_ra_tracking_p (void)
9512 /* In AMD64, return address is always stored on the stack at a fixed offset
9513 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9514 Do not track explicitly via an SFrame Frame Row Entry. */
9519 x86_sframe_cfa_ra_offset (void)
9521 gas_assert (x86_elf_abi
== X86_64_ABI
);
9522 return (offsetT
) -8;
9526 x86_sframe_get_abi_arch (void)
9528 unsigned char sframe_abi_arch
= 0;
9530 if (x86_support_sframe_p ())
9532 gas_assert (!target_big_endian
);
9533 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9536 return sframe_abi_arch
;
9542 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9543 const char *frag_now_ptr
)
9545 unsigned int len
= 0;
9547 if (start_frag
!= frag_now
)
9549 const fragS
*fr
= start_frag
;
9554 } while (fr
&& fr
!= frag_now
);
9557 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9560 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9561 be macro-fused with conditional jumps.
9562 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9563 or is one of the following format:
9576 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9578 /* No RIP address. */
9579 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9582 /* No opcodes outside of base encoding space. */
9583 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9586 /* add, sub without add/sub m, imm. */
9587 if (i
.tm
.base_opcode
<= 5
9588 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9589 || ((i
.tm
.base_opcode
| 3) == 0x83
9590 && (i
.tm
.extension_opcode
== 0x5
9591 || i
.tm
.extension_opcode
== 0x0)))
9593 *mf_cmp_p
= mf_cmp_alu_cmp
;
9594 return !(i
.mem_operands
&& i
.imm_operands
);
9597 /* and without and m, imm. */
9598 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9599 || ((i
.tm
.base_opcode
| 3) == 0x83
9600 && i
.tm
.extension_opcode
== 0x4))
9602 *mf_cmp_p
= mf_cmp_test_and
;
9603 return !(i
.mem_operands
&& i
.imm_operands
);
9606 /* test without test m imm. */
9607 if ((i
.tm
.base_opcode
| 1) == 0x85
9608 || (i
.tm
.base_opcode
| 1) == 0xa9
9609 || ((i
.tm
.base_opcode
| 1) == 0xf7
9610 && i
.tm
.extension_opcode
== 0))
9612 *mf_cmp_p
= mf_cmp_test_and
;
9613 return !(i
.mem_operands
&& i
.imm_operands
);
9616 /* cmp without cmp m, imm. */
9617 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9618 || ((i
.tm
.base_opcode
| 3) == 0x83
9619 && (i
.tm
.extension_opcode
== 0x7)))
9621 *mf_cmp_p
= mf_cmp_alu_cmp
;
9622 return !(i
.mem_operands
&& i
.imm_operands
);
9625 /* inc, dec without inc/dec m. */
9626 if ((is_cpu (&i
.tm
, CpuNo64
)
9627 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9628 || ((i
.tm
.base_opcode
| 1) == 0xff
9629 && i
.tm
.extension_opcode
<= 0x1))
9631 *mf_cmp_p
= mf_cmp_incdec
;
9632 return !i
.mem_operands
;
9638 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9641 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9643 /* NB: Don't work with COND_JUMP86 without i386. */
9644 if (!align_branch_power
9645 || now_seg
== absolute_section
9646 || !cpu_arch_flags
.bitfield
.cpui386
9647 || !(align_branch
& align_branch_fused_bit
))
9650 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9652 if (last_insn
.kind
== last_insn_other
9653 || last_insn
.seg
!= now_seg
)
9656 as_warn_where (last_insn
.file
, last_insn
.line
,
9657 _("`%s` skips -malign-branch-boundary on `%s`"),
9658 last_insn
.name
, insn_name (&i
.tm
));
9664 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9667 add_branch_prefix_frag_p (void)
9669 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9670 to PadLock instructions since they include prefixes in opcode. */
9671 if (!align_branch_power
9672 || !align_branch_prefix_size
9673 || now_seg
== absolute_section
9674 || is_cpu (&i
.tm
, CpuPadLock
)
9675 || !cpu_arch_flags
.bitfield
.cpui386
)
9678 /* Don't add prefix if it is a prefix or there is no operand in case
9679 that segment prefix is special. */
9680 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9683 if (last_insn
.kind
== last_insn_other
9684 || last_insn
.seg
!= now_seg
)
9688 as_warn_where (last_insn
.file
, last_insn
.line
,
9689 _("`%s` skips -malign-branch-boundary on `%s`"),
9690 last_insn
.name
, insn_name (&i
.tm
));
9695 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9698 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9699 enum mf_jcc_kind
*mf_jcc_p
)
9703 /* NB: Don't work with COND_JUMP86 without i386. */
9704 if (!align_branch_power
9705 || now_seg
== absolute_section
9706 || !cpu_arch_flags
.bitfield
.cpui386
9707 || i
.tm
.opcode_space
!= SPACE_BASE
)
9712 /* Check for jcc and direct jmp. */
9713 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9715 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9717 *branch_p
= align_branch_jmp
;
9718 add_padding
= align_branch
& align_branch_jmp_bit
;
9722 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9723 igore the lowest bit. */
9724 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9725 *branch_p
= align_branch_jcc
;
9726 if ((align_branch
& align_branch_jcc_bit
))
9730 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9733 *branch_p
= align_branch_ret
;
9734 if ((align_branch
& align_branch_ret_bit
))
9739 /* Check for indirect jmp, direct and indirect calls. */
9740 if (i
.tm
.base_opcode
== 0xe8)
9743 *branch_p
= align_branch_call
;
9744 if ((align_branch
& align_branch_call_bit
))
9747 else if (i
.tm
.base_opcode
== 0xff
9748 && (i
.tm
.extension_opcode
== 2
9749 || i
.tm
.extension_opcode
== 4))
9751 /* Indirect call and jmp. */
9752 *branch_p
= align_branch_indirect
;
9753 if ((align_branch
& align_branch_indirect_bit
))
9760 && (i
.op
[0].disps
->X_op
== O_symbol
9761 || (i
.op
[0].disps
->X_op
== O_subtract
9762 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9764 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9765 /* No padding to call to global or undefined tls_get_addr. */
9766 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9767 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9773 && last_insn
.kind
!= last_insn_other
9774 && last_insn
.seg
== now_seg
)
9777 as_warn_where (last_insn
.file
, last_insn
.line
,
9778 _("`%s` skips -malign-branch-boundary on `%s`"),
9779 last_insn
.name
, insn_name (&i
.tm
));
9789 fragS
*insn_start_frag
;
9790 offsetT insn_start_off
;
9791 fragS
*fragP
= NULL
;
9792 enum align_branch_kind branch
= align_branch_none
;
9793 /* The initializer is arbitrary just to avoid uninitialized error.
9794 it's actually either assigned in add_branch_padding_frag_p
9795 or never be used. */
9796 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9799 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9801 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9802 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9803 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9805 if (is_cpu (&i
.tm
, Cpu8087
)
9806 || is_cpu (&i
.tm
, Cpu287
)
9807 || is_cpu (&i
.tm
, Cpu387
)
9808 || is_cpu (&i
.tm
, Cpu687
)
9809 || is_cpu (&i
.tm
, CpuFISTTP
))
9810 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9812 if ((i
.xstate
& xstate_mmx
)
9813 || i
.tm
.mnem_off
== MN_emms
9814 || i
.tm
.mnem_off
== MN_femms
)
9815 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9819 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9820 i
.xstate
|= xstate_zmm
;
9821 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9822 i
.xstate
|= xstate_ymm
;
9823 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9824 i
.xstate
|= xstate_xmm
;
9827 /* vzeroall / vzeroupper */
9828 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9829 i
.xstate
|= xstate_ymm
;
9831 if ((i
.xstate
& xstate_xmm
)
9832 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9833 || (i
.tm
.base_opcode
== 0xae
9834 && (is_cpu (&i
.tm
, CpuSSE
)
9835 || is_cpu (&i
.tm
, CpuAVX
)))
9836 || is_cpu (&i
.tm
, CpuWideKL
)
9837 || is_cpu (&i
.tm
, CpuKL
))
9838 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9840 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9841 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9842 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9843 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9844 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9845 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9846 if (is_cpu (&i
.tm
, CpuFXSR
))
9847 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9848 if (is_cpu (&i
.tm
, CpuXsave
))
9849 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9850 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9851 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9852 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9853 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9855 if (x86_feature_2_used
9856 || is_cpu (&i
.tm
, CpuCMOV
)
9857 || is_cpu (&i
.tm
, CpuSYSCALL
)
9858 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9859 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9860 if (is_cpu (&i
.tm
, CpuSSE3
)
9861 || is_cpu (&i
.tm
, CpuSSSE3
)
9862 || is_cpu (&i
.tm
, CpuSSE4_1
)
9863 || is_cpu (&i
.tm
, CpuSSE4_2
)
9864 || is_cpu (&i
.tm
, CpuCX16
)
9865 || is_cpu (&i
.tm
, CpuPOPCNT
)
9866 /* LAHF-SAHF insns in 64-bit mode. */
9867 || (flag_code
== CODE_64BIT
9868 && (i
.tm
.base_opcode
| 1) == 0x9f
9869 && i
.tm
.opcode_space
== SPACE_BASE
))
9870 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9871 if (is_cpu (&i
.tm
, CpuAVX
)
9872 || is_cpu (&i
.tm
, CpuAVX2
)
9873 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9874 XOP, FMA4, LPW, TBM, and AMX. */
9875 || (i
.tm
.opcode_modifier
.vex
9876 && !is_cpu (&i
.tm
, CpuAVX512F
)
9877 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9878 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9879 && !is_cpu (&i
.tm
, CpuXOP
)
9880 && !is_cpu (&i
.tm
, CpuFMA4
)
9881 && !is_cpu (&i
.tm
, CpuLWP
)
9882 && !is_cpu (&i
.tm
, CpuTBM
)
9883 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9884 || is_cpu (&i
.tm
, CpuF16C
)
9885 || is_cpu (&i
.tm
, CpuFMA
)
9886 || is_cpu (&i
.tm
, CpuLZCNT
)
9887 || is_cpu (&i
.tm
, CpuMovbe
)
9888 || is_cpu (&i
.tm
, CpuXSAVES
)
9889 || (x86_feature_2_used
9890 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9891 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9892 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9893 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9894 if (is_cpu (&i
.tm
, CpuAVX512F
)
9895 || is_cpu (&i
.tm
, CpuAVX512BW
)
9896 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9897 || is_cpu (&i
.tm
, CpuAVX512VL
)
9898 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9899 AVX512-4FMAPS, and AVX512-4VNNIW. */
9900 || (i
.tm
.opcode_modifier
.evex
9901 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9902 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9903 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9904 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9905 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9909 /* Tie dwarf2 debug info to the address at the start of the insn.
9910 We can't do this after the insn has been output as the current
9911 frag may have been closed off. eg. by frag_var. */
9912 dwarf2_emit_insn (0);
9914 insn_start_frag
= frag_now
;
9915 insn_start_off
= frag_now_fix ();
9917 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9920 /* Branch can be 8 bytes. Leave some room for prefixes. */
9921 unsigned int max_branch_padding_size
= 14;
9923 /* Align section to boundary. */
9924 record_alignment (now_seg
, align_branch_power
);
9926 /* Make room for padding. */
9927 frag_grow (max_branch_padding_size
);
9929 /* Start of the padding. */
9934 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9935 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9938 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9939 fragP
->tc_frag_data
.branch_type
= branch
;
9940 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9943 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9944 && !pre_386_16bit_warned
)
9946 as_warn (_("use .code16 to ensure correct addressing mode"));
9947 pre_386_16bit_warned
= true;
9951 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9953 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9954 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9956 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9957 output_interseg_jump ();
9960 /* Output normal instructions here. */
9964 enum mf_cmp_kind mf_cmp
;
9967 && (i
.tm
.base_opcode
== 0xaee8
9968 || i
.tm
.base_opcode
== 0xaef0
9969 || i
.tm
.base_opcode
== 0xaef8))
9971 /* Encode lfence, mfence, and sfence as
9972 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9973 if (flag_code
== CODE_16BIT
)
9974 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9975 else if (omit_lock_prefix
)
9976 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9978 else if (now_seg
!= absolute_section
)
9980 offsetT val
= 0x240483f0ULL
;
9983 md_number_to_chars (p
, val
, 5);
9986 abs_section_offset
+= 5;
9990 /* Some processors fail on LOCK prefix. This options makes
9991 assembler ignore LOCK prefix and serves as a workaround. */
9992 if (omit_lock_prefix
)
9994 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9995 && i
.tm
.opcode_modifier
.isprefix
)
9997 i
.prefix
[LOCK_PREFIX
] = 0;
10001 /* Skip if this is a branch. */
10003 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10005 /* Make room for padding. */
10006 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10011 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10012 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10015 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10016 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10017 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10019 else if (add_branch_prefix_frag_p ())
10021 unsigned int max_prefix_size
= align_branch_prefix_size
;
10023 /* Make room for padding. */
10024 frag_grow (max_prefix_size
);
10029 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10030 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10033 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10036 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10037 don't need the explicit prefix. */
10038 if (!is_any_vex_encoding (&i
.tm
))
10040 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10049 if (!is_cpu (&i
.tm
, CpuPadLock
)
10050 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10054 switch (i
.opcode_length
)
10059 /* Check for pseudo prefixes. */
10060 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10062 as_bad_where (insn_start_frag
->fr_file
,
10063 insn_start_frag
->fr_line
,
10064 _("pseudo prefix without instruction"));
10074 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10075 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10076 R_X86_64_GOTTPOFF relocation so that linker can safely
10077 perform IE->LE optimization. A dummy REX_OPCODE prefix
10078 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10079 relocation for GDesc -> IE/LE optimization. */
10080 if (x86_elf_abi
== X86_64_X32_ABI
10082 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10083 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10084 && i
.prefix
[REX_PREFIX
] == 0)
10085 add_prefix (REX_OPCODE
);
10088 /* The prefix bytes. */
10089 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10091 frag_opcode_byte (*q
);
10095 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10101 frag_opcode_byte (*q
);
10104 /* There should be no other prefixes for instructions
10105 with VEX prefix. */
10109 /* For EVEX instructions i.vrex should become 0 after
10110 build_evex_prefix. For VEX instructions upper 16 registers
10111 aren't available, so VREX should be 0. */
10114 /* Now the VEX prefix. */
10115 if (now_seg
!= absolute_section
)
10117 p
= frag_more (i
.vex
.length
);
10118 for (j
= 0; j
< i
.vex
.length
; j
++)
10119 p
[j
] = i
.vex
.bytes
[j
];
10122 abs_section_offset
+= i
.vex
.length
;
10125 /* Now the opcode; be careful about word order here! */
10126 j
= i
.opcode_length
;
10128 switch (i
.tm
.opcode_space
)
10143 if (now_seg
== absolute_section
)
10144 abs_section_offset
+= j
;
10147 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10153 && i
.tm
.opcode_space
!= SPACE_BASE
)
10156 if (i
.tm
.opcode_space
!= SPACE_0F
)
10157 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10161 switch (i
.opcode_length
)
10164 /* Put out high byte first: can't use md_number_to_chars! */
10165 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10166 /* Fall through. */
10168 *p
= i
.tm
.base_opcode
& 0xff;
10177 /* Now the modrm byte and sib byte (if present). */
10178 if (i
.tm
.opcode_modifier
.modrm
)
10180 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10182 | (i
.rm
.mode
<< 6));
10183 /* If i.rm.regmem == ESP (4)
10184 && i.rm.mode != (Register mode)
10186 ==> need second modrm byte. */
10187 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10189 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10190 frag_opcode_byte ((i
.sib
.base
<< 0)
10191 | (i
.sib
.index
<< 3)
10192 | (i
.sib
.scale
<< 6));
10195 if (i
.disp_operands
)
10196 output_disp (insn_start_frag
, insn_start_off
);
10198 if (i
.imm_operands
)
10199 output_imm (insn_start_frag
, insn_start_off
);
10202 * frag_now_fix () returning plain abs_section_offset when we're in the
10203 * absolute section, and abs_section_offset not getting updated as data
10204 * gets added to the frag breaks the logic below.
10206 if (now_seg
!= absolute_section
)
10208 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10210 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10214 /* NB: Don't add prefix with GOTPC relocation since
10215 output_disp() above depends on the fixed encoding
10216 length. Can't add prefix with TLS relocation since
10217 it breaks TLS linker optimization. */
10218 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10219 /* Prefix count on the current instruction. */
10220 unsigned int count
= i
.vex
.length
;
10222 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10223 /* REX byte is encoded in VEX/EVEX prefix. */
10224 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10227 /* Count prefixes for extended opcode maps. */
10229 switch (i
.tm
.opcode_space
)
10244 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10247 /* Set the maximum prefix size in BRANCH_PREFIX
10249 if (fragP
->tc_frag_data
.max_bytes
> max
)
10250 fragP
->tc_frag_data
.max_bytes
= max
;
10251 if (fragP
->tc_frag_data
.max_bytes
> count
)
10252 fragP
->tc_frag_data
.max_bytes
-= count
;
10254 fragP
->tc_frag_data
.max_bytes
= 0;
10258 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10260 unsigned int max_prefix_size
;
10261 if (align_branch_prefix_size
> max
)
10262 max_prefix_size
= max
;
10264 max_prefix_size
= align_branch_prefix_size
;
10265 if (max_prefix_size
> count
)
10266 fragP
->tc_frag_data
.max_prefix_length
10267 = max_prefix_size
- count
;
10270 /* Use existing segment prefix if possible. Use CS
10271 segment prefix in 64-bit mode. In 32-bit mode, use SS
10272 segment prefix with ESP/EBP base register and use DS
10273 segment prefix without ESP/EBP base register. */
10274 if (i
.prefix
[SEG_PREFIX
])
10275 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10276 else if (flag_code
== CODE_64BIT
)
10277 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10278 else if (i
.base_reg
10279 && (i
.base_reg
->reg_num
== 4
10280 || i
.base_reg
->reg_num
== 5))
10281 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10283 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10288 /* NB: Don't work with COND_JUMP86 without i386. */
10289 if (align_branch_power
10290 && now_seg
!= absolute_section
10291 && cpu_arch_flags
.bitfield
.cpui386
)
10293 /* Terminate each frag so that we can add prefix and check for
10295 frag_wane (frag_now
);
10302 pi ("" /*line*/, &i
);
10304 #endif /* DEBUG386 */
10307 /* Return the size of the displacement operand N. */
10310 disp_size (unsigned int n
)
10314 if (i
.types
[n
].bitfield
.disp64
)
10316 else if (i
.types
[n
].bitfield
.disp8
)
10318 else if (i
.types
[n
].bitfield
.disp16
)
10323 /* Return the size of the immediate operand N. */
10326 imm_size (unsigned int n
)
10329 if (i
.types
[n
].bitfield
.imm64
)
10331 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10333 else if (i
.types
[n
].bitfield
.imm16
)
10339 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10344 for (n
= 0; n
< i
.operands
; n
++)
10346 if (operand_type_check (i
.types
[n
], disp
))
10348 int size
= disp_size (n
);
10350 if (now_seg
== absolute_section
)
10351 abs_section_offset
+= size
;
10352 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10354 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10356 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10358 p
= frag_more (size
);
10359 md_number_to_chars (p
, val
, size
);
10363 enum bfd_reloc_code_real reloc_type
;
10364 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10365 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10366 && (!want_disp32 (&i
.tm
)
10367 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10368 && !i
.types
[n
].bitfield
.baseindex
)))
10372 /* We can't have 8 bit displacement here. */
10373 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10375 /* The PC relative address is computed relative
10376 to the instruction boundary, so in case immediate
10377 fields follows, we need to adjust the value. */
10378 if (pcrel
&& i
.imm_operands
)
10383 for (n1
= 0; n1
< i
.operands
; n1
++)
10384 if (operand_type_check (i
.types
[n1
], imm
))
10386 /* Only one immediate is allowed for PC
10387 relative address, except with .insn. */
10388 gas_assert (sz
== 0 || dot_insn ());
10389 sz
+= imm_size (n1
);
10391 /* We should find at least one immediate. */
10392 gas_assert (sz
!= 0);
10393 i
.op
[n
].disps
->X_add_number
-= sz
;
10396 p
= frag_more (size
);
10397 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10399 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10400 && (((reloc_type
== BFD_RELOC_32
10401 || reloc_type
== BFD_RELOC_X86_64_32S
10402 || (reloc_type
== BFD_RELOC_64
10404 && (i
.op
[n
].disps
->X_op
== O_symbol
10405 || (i
.op
[n
].disps
->X_op
== O_add
10406 && ((symbol_get_value_expression
10407 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10409 || reloc_type
== BFD_RELOC_32_PCREL
))
10413 reloc_type
= BFD_RELOC_386_GOTPC
;
10414 i
.has_gotpc_tls_reloc
= true;
10415 i
.op
[n
].disps
->X_add_number
+=
10416 encoding_length (insn_start_frag
, insn_start_off
, p
);
10418 else if (reloc_type
== BFD_RELOC_64
)
10419 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10421 /* Don't do the adjustment for x86-64, as there
10422 the pcrel addressing is relative to the _next_
10423 insn, and that is taken care of in other code. */
10424 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10426 else if (align_branch_power
)
10428 switch (reloc_type
)
10430 case BFD_RELOC_386_TLS_GD
:
10431 case BFD_RELOC_386_TLS_LDM
:
10432 case BFD_RELOC_386_TLS_IE
:
10433 case BFD_RELOC_386_TLS_IE_32
:
10434 case BFD_RELOC_386_TLS_GOTIE
:
10435 case BFD_RELOC_386_TLS_GOTDESC
:
10436 case BFD_RELOC_386_TLS_DESC_CALL
:
10437 case BFD_RELOC_X86_64_TLSGD
:
10438 case BFD_RELOC_X86_64_TLSLD
:
10439 case BFD_RELOC_X86_64_GOTTPOFF
:
10440 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10441 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10442 i
.has_gotpc_tls_reloc
= true;
10447 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10448 size
, i
.op
[n
].disps
, pcrel
,
10451 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10452 && !i
.prefix
[ADDR_PREFIX
])
10453 fixP
->fx_signed
= 1;
10455 /* Check for "call/jmp *mem", "mov mem, %reg",
10456 "test %reg, mem" and "binop mem, %reg" where binop
10457 is one of adc, add, and, cmp, or, sbb, sub, xor
10458 instructions without data prefix. Always generate
10459 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10460 if (i
.prefix
[DATA_PREFIX
] == 0
10461 && (generate_relax_relocations
10464 && i
.rm
.regmem
== 5))
10466 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10467 && i
.tm
.opcode_space
== SPACE_BASE
10468 && ((i
.operands
== 1
10469 && i
.tm
.base_opcode
== 0xff
10470 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10471 || (i
.operands
== 2
10472 && (i
.tm
.base_opcode
== 0x8b
10473 || i
.tm
.base_opcode
== 0x85
10474 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10478 fixP
->fx_tcbit
= i
.rex
!= 0;
10480 && (i
.base_reg
->reg_num
== RegIP
))
10481 fixP
->fx_tcbit2
= 1;
10484 fixP
->fx_tcbit2
= 1;
10492 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10497 for (n
= 0; n
< i
.operands
; n
++)
10499 if (operand_type_check (i
.types
[n
], imm
))
10501 int size
= imm_size (n
);
10503 if (now_seg
== absolute_section
)
10504 abs_section_offset
+= size
;
10505 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10509 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10511 p
= frag_more (size
);
10512 md_number_to_chars (p
, val
, size
);
10516 /* Not absolute_section.
10517 Need a 32-bit fixup (don't support 8bit
10518 non-absolute imms). Try to support other
10520 enum bfd_reloc_code_real reloc_type
;
10523 if (i
.types
[n
].bitfield
.imm32s
10524 && (i
.suffix
== QWORD_MNEM_SUFFIX
10525 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10526 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10532 p
= frag_more (size
);
10533 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10535 /* This is tough to explain. We end up with this one if we
10536 * have operands that look like
10537 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10538 * obtain the absolute address of the GOT, and it is strongly
10539 * preferable from a performance point of view to avoid using
10540 * a runtime relocation for this. The actual sequence of
10541 * instructions often look something like:
10546 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10548 * The call and pop essentially return the absolute address
10549 * of the label .L66 and store it in %ebx. The linker itself
10550 * will ultimately change the first operand of the addl so
10551 * that %ebx points to the GOT, but to keep things simple, the
10552 * .o file must have this operand set so that it generates not
10553 * the absolute address of .L66, but the absolute address of
10554 * itself. This allows the linker itself simply treat a GOTPC
10555 * relocation as asking for a pcrel offset to the GOT to be
10556 * added in, and the addend of the relocation is stored in the
10557 * operand field for the instruction itself.
10559 * Our job here is to fix the operand so that it would add
10560 * the correct offset so that %ebx would point to itself. The
10561 * thing that is tricky is that .-.L66 will point to the
10562 * beginning of the instruction, so we need to further modify
10563 * the operand so that it will point to itself. There are
10564 * other cases where you have something like:
10566 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10568 * and here no correction would be required. Internally in
10569 * the assembler we treat operands of this form as not being
10570 * pcrel since the '.' is explicitly mentioned, and I wonder
10571 * whether it would simplify matters to do it this way. Who
10572 * knows. In earlier versions of the PIC patches, the
10573 * pcrel_adjust field was used to store the correction, but
10574 * since the expression is not pcrel, I felt it would be
10575 * confusing to do it this way. */
10577 if ((reloc_type
== BFD_RELOC_32
10578 || reloc_type
== BFD_RELOC_X86_64_32S
10579 || reloc_type
== BFD_RELOC_64
)
10581 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10582 && (i
.op
[n
].imms
->X_op
== O_symbol
10583 || (i
.op
[n
].imms
->X_op
== O_add
10584 && ((symbol_get_value_expression
10585 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10589 reloc_type
= BFD_RELOC_386_GOTPC
;
10590 else if (size
== 4)
10591 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10592 else if (size
== 8)
10593 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10594 i
.has_gotpc_tls_reloc
= true;
10595 i
.op
[n
].imms
->X_add_number
+=
10596 encoding_length (insn_start_frag
, insn_start_off
, p
);
10598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10599 i
.op
[n
].imms
, 0, reloc_type
);
10605 /* x86_cons_fix_new is called via the expression parsing code when a
10606 reloc is needed. We use this hook to get the correct .got reloc. */
10607 static int cons_sign
= -1;
10610 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10611 expressionS
*exp
, bfd_reloc_code_real_type r
)
10613 r
= reloc (len
, 0, cons_sign
, r
);
10616 if (exp
->X_op
== O_secrel
)
10618 exp
->X_op
= O_symbol
;
10619 r
= BFD_RELOC_32_SECREL
;
10621 else if (exp
->X_op
== O_secidx
)
10622 r
= BFD_RELOC_16_SECIDX
;
10625 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10628 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10629 purpose of the `.dc.a' internal pseudo-op. */
10632 x86_address_bytes (void)
10634 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10636 return stdoutput
->arch_info
->bits_per_address
/ 8;
10639 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10640 || defined (LEX_AT)) && !defined (TE_PE)
10641 # define lex_got(reloc, adjust, types) NULL
10643 /* Parse operands of the form
10644 <symbol>@GOTOFF+<nnn>
10645 and similar .plt or .got references.
10647 If we find one, set up the correct relocation in RELOC and copy the
10648 input string, minus the `@GOTOFF' into a malloc'd buffer for
10649 parsing by the calling routine. Return this buffer, and if ADJUST
10650 is non-null set it to the length of the string we removed from the
10651 input line. Otherwise return NULL. */
10653 lex_got (enum bfd_reloc_code_real
*rel
,
10655 i386_operand_type
*types
)
10657 /* Some of the relocations depend on the size of what field is to
10658 be relocated. But in our callers i386_immediate and i386_displacement
10659 we don't yet know the operand size (this will be set by insn
10660 matching). Hence we record the word32 relocation here,
10661 and adjust the reloc according to the real size in reloc(). */
10662 static const struct
10666 const enum bfd_reloc_code_real rel
[2];
10667 const i386_operand_type types64
;
10668 bool need_GOT_symbol
;
10673 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10674 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10675 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10676 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10677 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10678 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10679 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10680 { .imm64 = 1, .disp64 = 1 } }
10683 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10684 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10685 BFD_RELOC_SIZE32
},
10686 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10688 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10689 BFD_RELOC_X86_64_PLTOFF64
},
10690 { .bitfield
= { .imm64
= 1 } }, true },
10691 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10692 BFD_RELOC_X86_64_PLT32
},
10693 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10694 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10695 BFD_RELOC_X86_64_GOTPLT64
},
10696 OPERAND_TYPE_IMM64_DISP64
, true },
10697 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10698 BFD_RELOC_X86_64_GOTOFF64
},
10699 OPERAND_TYPE_IMM64_DISP64
, true },
10700 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10701 BFD_RELOC_X86_64_GOTPCREL
},
10702 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10703 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10704 BFD_RELOC_X86_64_TLSGD
},
10705 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10706 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10707 _dummy_first_bfd_reloc_code_real
},
10708 OPERAND_TYPE_NONE
, true },
10709 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10710 BFD_RELOC_X86_64_TLSLD
},
10711 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10712 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10713 BFD_RELOC_X86_64_GOTTPOFF
},
10714 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10715 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10716 BFD_RELOC_X86_64_TPOFF32
},
10717 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10718 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10719 _dummy_first_bfd_reloc_code_real
},
10720 OPERAND_TYPE_NONE
, true },
10721 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10722 BFD_RELOC_X86_64_DTPOFF32
},
10723 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10724 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10725 _dummy_first_bfd_reloc_code_real
},
10726 OPERAND_TYPE_NONE
, true },
10727 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10728 _dummy_first_bfd_reloc_code_real
},
10729 OPERAND_TYPE_NONE
, true },
10730 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10731 BFD_RELOC_X86_64_GOT32
},
10732 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10733 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10734 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10735 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10736 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10737 BFD_RELOC_X86_64_TLSDESC_CALL
},
10738 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10740 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10741 BFD_RELOC_32_SECREL
},
10742 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10745 #undef OPERAND_TYPE_IMM32_32S_DISP32
10746 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10747 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10748 #undef OPERAND_TYPE_IMM64_DISP64
10754 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10759 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10760 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10763 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10765 int len
= gotrel
[j
].len
;
10766 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10768 if (gotrel
[j
].rel
[object_64bit
] != 0)
10771 char *tmpbuf
, *past_reloc
;
10773 *rel
= gotrel
[j
].rel
[object_64bit
];
10777 if (flag_code
!= CODE_64BIT
)
10779 types
->bitfield
.imm32
= 1;
10780 types
->bitfield
.disp32
= 1;
10783 *types
= gotrel
[j
].types64
;
10786 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10787 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10789 /* The length of the first part of our input line. */
10790 first
= cp
- input_line_pointer
;
10792 /* The second part goes from after the reloc token until
10793 (and including) an end_of_line char or comma. */
10794 past_reloc
= cp
+ 1 + len
;
10796 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10798 second
= cp
+ 1 - past_reloc
;
10800 /* Allocate and copy string. The trailing NUL shouldn't
10801 be necessary, but be safe. */
10802 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10803 memcpy (tmpbuf
, input_line_pointer
, first
);
10804 if (second
!= 0 && *past_reloc
!= ' ')
10805 /* Replace the relocation token with ' ', so that
10806 errors like foo@GOTOFF1 will be detected. */
10807 tmpbuf
[first
++] = ' ';
10809 /* Increment length by 1 if the relocation token is
10814 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10815 tmpbuf
[first
+ second
] = '\0';
10819 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10820 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10825 /* Might be a symbol version string. Don't as_bad here. */
10830 bfd_reloc_code_real_type
10831 x86_cons (expressionS
*exp
, int size
)
10833 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10835 intel_syntax
= -intel_syntax
;
10837 expr_mode
= expr_operator_none
;
10839 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10840 && !defined (LEX_AT)) \
10842 if (size
== 4 || (object_64bit
&& size
== 8))
10844 /* Handle @GOTOFF and the like in an expression. */
10846 char *gotfree_input_line
;
10849 save
= input_line_pointer
;
10850 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10851 if (gotfree_input_line
)
10852 input_line_pointer
= gotfree_input_line
;
10856 if (gotfree_input_line
)
10858 /* expression () has merrily parsed up to the end of line,
10859 or a comma - in the wrong buffer. Transfer how far
10860 input_line_pointer has moved to the right buffer. */
10861 input_line_pointer
= (save
10862 + (input_line_pointer
- gotfree_input_line
)
10864 free (gotfree_input_line
);
10865 if (exp
->X_op
== O_constant
10866 || exp
->X_op
== O_absent
10867 || exp
->X_op
== O_illegal
10868 || exp
->X_op
== O_register
10869 || exp
->X_op
== O_big
)
10871 char c
= *input_line_pointer
;
10872 *input_line_pointer
= 0;
10873 as_bad (_("missing or invalid expression `%s'"), save
);
10874 *input_line_pointer
= c
;
10876 else if ((got_reloc
== BFD_RELOC_386_PLT32
10877 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10878 && exp
->X_op
!= O_symbol
)
10880 char c
= *input_line_pointer
;
10881 *input_line_pointer
= 0;
10882 as_bad (_("invalid PLT expression `%s'"), save
);
10883 *input_line_pointer
= c
;
10891 intel_syntax
= -intel_syntax
;
10894 i386_intel_simplify (exp
);
10896 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10897 if (size
<= 4 && expr_mode
== expr_operator_present
10898 && exp
->X_op
== O_constant
&& !object_64bit
)
10899 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10905 signed_cons (int size
)
10914 s_insn (int dummy ATTRIBUTE_UNUSED
)
10916 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10917 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10921 bool vex
= false, xop
= false, evex
= false;
10922 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10926 saved_char
= *saved_ilp
;
10929 end
= parse_insn (line
, mnemonic
, true);
10933 *saved_ilp
= saved_char
;
10934 ignore_rest_of_line ();
10938 line
+= end
- line
;
10940 current_templates
= &tt
;
10941 i
.tm
.mnem_off
= MN__insn
;
10942 i
.tm
.extension_opcode
= None
;
10944 if (startswith (line
, "VEX")
10945 && (line
[3] == '.' || is_space_char (line
[3])))
10950 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10953 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10955 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10956 && (*e
== '.' || is_space_char (*e
)))
10959 /* Arrange for build_vex_prefix() to emit 0x8f. */
10960 i
.tm
.opcode_space
= SPACE_XOP08
;
10961 i
.insn_opcode_space
= n
;
10965 else if (startswith (line
, "EVEX")
10966 && (line
[4] == '.' || is_space_char (line
[4])))
10973 ? i
.vec_encoding
== vex_encoding_evex
10975 ? i
.vec_encoding
== vex_encoding_vex
10976 || i
.vec_encoding
== vex_encoding_vex3
10977 : i
.vec_encoding
!= vex_encoding_default
)
10979 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10983 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10984 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10986 if (i
.vec_encoding
!= vex_encoding_default
)
10988 /* Only address size and segment override prefixes are permitted with
10989 VEX/XOP/EVEX encodings. */
10990 const unsigned char *p
= i
.prefix
;
10992 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11003 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11009 if (line
> end
&& *line
== '.')
11011 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11019 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11021 i
.tm
.opcode_modifier
.vex
= VEX128
;
11026 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11028 i
.tm
.opcode_modifier
.vex
= VEX256
;
11033 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11038 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11042 if (line
[3] == 'G')
11045 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11047 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11053 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11058 if (line
[2] == '2' && line
[3] == '8')
11061 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11063 i
.tm
.opcode_modifier
.vex
= VEX128
;
11069 if (line
[2] == '5' && line
[3] == '6')
11072 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11074 i
.tm
.opcode_modifier
.vex
= VEX256
;
11080 if (evex
&& line
[2] == '1' && line
[3] == '2')
11082 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11089 if (line
> end
&& *line
== '.')
11091 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11095 if (line
[2] == 'P')
11100 if (line
[2] == '6')
11102 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11107 case 'F': case 'f':
11108 if (line
[2] == '3')
11110 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11113 else if (line
[2] == '2')
11115 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11122 if (line
> end
&& !xop
&& *line
== '.')
11124 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11128 if (TOUPPER (line
[2]) != 'F')
11130 if (line
[3] == '.' || is_space_char (line
[3]))
11132 i
.insn_opcode_space
= SPACE_0F
;
11135 else if (line
[3] == '3'
11136 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11137 && (line
[5] == '.' || is_space_char (line
[5])))
11139 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11145 if (ISDIGIT (line
[2]) && line
[2] != '0')
11148 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11150 if (n
<= (evex
? 15 : 31)
11151 && (*e
== '.' || is_space_char (*e
)))
11153 i
.insn_opcode_space
= n
;
11161 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11163 /* VEX.W, XOP.W, EVEX.W */
11167 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11171 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11175 if (line
[3] == 'G')
11177 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11183 if (i
.tm
.opcode_modifier
.vexw
)
11187 if (line
> end
&& *line
&& !is_space_char (*line
))
11189 /* Improve diagnostic a little. */
11190 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11195 /* Before processing the opcode expression, find trailing "+r" or
11196 "/<digit>" specifiers. */
11197 for (ptr
= line
; ; ++ptr
)
11202 ptr
= strpbrk (ptr
, "+/,");
11203 if (ptr
== NULL
|| *ptr
== ',')
11206 if (*ptr
== '+' && ptr
[1] == 'r'
11207 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11211 i
.short_form
= true;
11215 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11216 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11218 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11222 i
.tm
.extension_opcode
= n
;
11223 i
.tm
.opcode_modifier
.modrm
= 1;
11228 input_line_pointer
= line
;
11229 val
= get_absolute_expression ();
11230 line
= input_line_pointer
;
11232 if (i
.short_form
&& (val
& 7))
11233 as_warn ("`+r' assumes low three opcode bits to be clear");
11235 for (j
= 1; j
< sizeof(val
); ++j
)
11236 if (!(val
>> (j
* 8)))
11239 /* Trim off a prefix if present. */
11240 if (j
> 1 && !vex
&& !xop
&& !evex
)
11242 uint8_t byte
= val
>> ((j
- 1) * 8);
11246 case DATA_PREFIX_OPCODE
:
11247 case REPE_PREFIX_OPCODE
:
11248 case REPNE_PREFIX_OPCODE
:
11249 if (!add_prefix (byte
))
11251 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11256 /* Trim off encoding space. */
11257 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11259 uint8_t byte
= val
>> ((--j
- 1) * 8);
11261 i
.insn_opcode_space
= SPACE_0F
;
11262 switch (byte
& -(j
> 1))
11265 i
.insn_opcode_space
= SPACE_0F38
;
11269 i
.insn_opcode_space
= SPACE_0F3A
;
11273 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11274 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11276 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11277 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11278 Also avoid hitting abort() there or in build_evex_prefix(). */
11279 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11284 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11287 i
.opcode_length
= j
;
11289 /* Handle operands, if any. */
11292 i386_operand_type combined
;
11293 expressionS
*disp_exp
= NULL
;
11298 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11306 as_bad (_("expecting operand after ','; got nothing"));
11310 if (i
.mem_operands
> 1)
11312 as_bad (_("too many memory references for `%s'"),
11313 &i386_mnemonics
[MN__insn
]);
11317 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11318 if (i
.vec_encoding
== vex_encoding_evex512
)
11319 i
.vec_encoding
= vex_encoding_evex
;
11321 /* Are we to emit ModR/M encoding? */
11324 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11325 || i
.tm
.extension_opcode
!= None
))
11326 i
.tm
.opcode_modifier
.modrm
= 1;
11328 if (!i
.tm
.opcode_modifier
.modrm
11330 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11331 || i
.mem_operands
))
11333 as_bad (_("too many register/memory operands"));
11337 /* Enforce certain constraints on operands. */
11338 switch (i
.reg_operands
+ i
.mem_operands
11339 + (i
.tm
.extension_opcode
!= None
))
11344 as_bad (_("too few register/memory operands"));
11347 /* Fall through. */
11349 if (i
.tm
.opcode_modifier
.modrm
)
11351 as_bad (_("too few register/memory operands"));
11361 && (i
.op
[0].imms
->X_op
!= O_constant
11362 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11364 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11367 /* Fall through. */
11369 if (i
.vec_encoding
!= vex_encoding_default
)
11371 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11374 /* Fall through. */
11376 as_bad (_("too many register/memory operands"));
11380 /* Bring operands into canonical order (imm, mem, reg). */
11385 for (j
= 1; j
< i
.operands
; ++j
)
11387 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11388 && operand_type_check (i
.types
[j
], imm
))
11389 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11390 && i
.types
[j
].bitfield
.class == ClassNone
))
11392 swap_2_operands (j
- 1, j
);
11399 /* For Intel syntax swap the order of register operands. */
11401 switch (i
.reg_operands
)
11408 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11409 /* Fall through. */
11412 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11419 /* Enforce constraints when using VSIB. */
11421 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11422 || i
.index_reg
->reg_type
.bitfield
.ymmword
11423 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11425 if (i
.vec_encoding
== vex_encoding_default
)
11427 as_bad (_("VSIB unavailable with legacy encoding"));
11431 if (i
.vec_encoding
== vex_encoding_evex
11432 && i
.reg_operands
> 1)
11434 /* We could allow two register operands, encoding the 2nd one in
11435 an 8-bit immediate like for 4-register-operand insns, but that
11436 would require ugly fiddling with process_operands() and/or
11437 build_modrm_byte(). */
11438 as_bad (_("too many register operands with VSIB"));
11442 i
.tm
.opcode_modifier
.sib
= 1;
11445 /* Establish operand size encoding. */
11446 operand_type_set (&combined
, 0);
11448 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11450 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11452 if (operand_type_check (i
.types
[j
], disp
))
11454 i
.types
[j
].bitfield
.baseindex
= 1;
11455 disp_exp
= i
.op
[j
].disps
;
11458 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11460 unsigned int n
= i
.memshift
;
11462 if (i
.types
[j
].bitfield
.byte
)
11464 else if (i
.types
[j
].bitfield
.word
)
11466 else if (i
.types
[j
].bitfield
.dword
)
11468 else if (i
.types
[j
].bitfield
.qword
)
11470 else if (i
.types
[j
].bitfield
.xmmword
)
11472 else if (i
.types
[j
].bitfield
.ymmword
)
11474 else if (i
.types
[j
].bitfield
.zmmword
)
11477 if (i
.memshift
< 32 && n
!= i
.memshift
)
11478 as_warn ("conflicting memory operand size specifiers");
11482 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11483 && j
== i
.broadcast
.operand
)
11486 combined
= operand_type_or (combined
, i
.types
[j
]);
11487 combined
.bitfield
.class = ClassNone
;
11490 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11491 << (i
.memshift
< 32 ? i
.memshift
: 0))
11493 case 64: combined
.bitfield
.zmmword
= 1; break;
11494 case 32: combined
.bitfield
.ymmword
= 1; break;
11495 case 16: combined
.bitfield
.xmmword
= 1; break;
11496 case 8: combined
.bitfield
.qword
= 1; break;
11497 case 4: combined
.bitfield
.dword
= 1; break;
11500 if (i
.vec_encoding
== vex_encoding_default
)
11502 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11504 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11505 : combined
.bitfield
.word
)
11506 && !add_prefix (DATA_PREFIX_OPCODE
))
11509 else if (!i
.tm
.opcode_modifier
.vexw
)
11511 if (flag_code
== CODE_64BIT
)
11513 if (combined
.bitfield
.qword
)
11514 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11515 else if (combined
.bitfield
.dword
)
11516 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11519 if (!i
.tm
.opcode_modifier
.vexw
)
11520 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11525 if (!i
.tm
.opcode_modifier
.vex
)
11527 if (combined
.bitfield
.ymmword
)
11528 i
.tm
.opcode_modifier
.vex
= VEX256
;
11529 else if (combined
.bitfield
.xmmword
)
11530 i
.tm
.opcode_modifier
.vex
= VEX128
;
11535 if (!i
.tm
.opcode_modifier
.evex
)
11537 /* Do _not_ consider AVX512VL here. */
11538 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11539 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11540 else if (combined
.bitfield
.ymmword
)
11541 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11542 else if (combined
.bitfield
.xmmword
)
11543 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11546 if (i
.memshift
>= 32)
11548 unsigned int n
= 0;
11550 switch (i
.tm
.opcode_modifier
.evex
)
11552 case EVEX512
: n
= 64; break;
11553 case EVEX256
: n
= 32; break;
11554 case EVEX128
: n
= 16; break;
11557 if (i
.broadcast
.type
)
11558 n
/= i
.broadcast
.type
;
11561 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11563 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11564 && disp_exp
->X_add_number
!= 0
11565 && i
.disp_encoding
!= disp_encoding_32bit
)
11567 if (!quiet_warnings
)
11568 as_warn ("cannot determine memory operand size");
11569 i
.disp_encoding
= disp_encoding_32bit
;
11574 if (i
.memshift
>= 32)
11577 i
.vec_encoding
= vex_encoding_error
;
11579 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11582 /* Establish size for immediate operands. */
11583 for (j
= 0; j
< i
.imm_operands
; ++j
)
11585 expressionS
*expP
= i
.op
[j
].imms
;
11587 gas_assert (operand_type_check (i
.types
[j
], imm
));
11588 operand_type_set (&i
.types
[j
], 0);
11590 if (i
.imm_bits
[j
] > 32)
11591 i
.types
[j
].bitfield
.imm64
= 1;
11592 else if (i
.imm_bits
[j
] > 16)
11594 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11595 i
.types
[j
].bitfield
.imm32s
= 1;
11597 i
.types
[j
].bitfield
.imm32
= 1;
11599 else if (i
.imm_bits
[j
] > 8)
11600 i
.types
[j
].bitfield
.imm16
= 1;
11601 else if (i
.imm_bits
[j
] > 0)
11603 if (i
.flags
[j
] & Operand_Signed
)
11604 i
.types
[j
].bitfield
.imm8s
= 1;
11606 i
.types
[j
].bitfield
.imm8
= 1;
11608 else if (expP
->X_op
== O_constant
)
11610 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11611 i
.types
[j
].bitfield
.imm1
= 0;
11612 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11613 zapping since smallest_imm_type() sets it unconditionally. */
11614 if (flag_code
!= CODE_64BIT
)
11616 i
.types
[j
].bitfield
.imm64
= 0;
11617 i
.types
[j
].bitfield
.imm32s
= 0;
11618 i
.types
[j
].bitfield
.imm32
= 1;
11620 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11621 i
.types
[j
].bitfield
.imm64
= 0;
11624 /* Non-constant expressions are sized heuristically. */
11627 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11628 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11629 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11633 for (j
= 0; j
< i
.operands
; ++j
)
11634 i
.tm
.operand_types
[j
] = i
.types
[j
];
11636 process_operands ();
11639 /* Don't set opcode until after processing operands, to avoid any
11640 potential special casing there. */
11641 i
.tm
.base_opcode
|= val
;
11643 if (i
.vec_encoding
== vex_encoding_error
11644 || (i
.vec_encoding
!= vex_encoding_evex
11645 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11646 || i
.rounding
.type
!= rc_none
11648 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11649 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11650 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11652 as_bad (_("conflicting .insn operands"));
11658 if (!i
.tm
.opcode_modifier
.vex
)
11659 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11661 build_vex_prefix (NULL
);
11662 i
.rex
&= REX_OPCODE
;
11666 if (!i
.tm
.opcode_modifier
.evex
)
11667 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11669 build_evex_prefix ();
11670 i
.rex
&= REX_OPCODE
;
11672 else if (i
.rex
!= 0)
11673 add_prefix (REX_OPCODE
| i
.rex
);
11678 *saved_ilp
= saved_char
;
11679 input_line_pointer
= line
;
11681 demand_empty_rest_of_line ();
11683 /* Make sure dot_insn() won't yield "true" anymore. */
11689 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11696 if (exp
.X_op
== O_symbol
)
11697 exp
.X_op
= O_secrel
;
11699 emit_expr (&exp
, 4);
11701 while (*input_line_pointer
++ == ',');
11703 input_line_pointer
--;
11704 demand_empty_rest_of_line ();
11708 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11715 if (exp
.X_op
== O_symbol
)
11716 exp
.X_op
= O_secidx
;
11718 emit_expr (&exp
, 2);
11720 while (*input_line_pointer
++ == ',');
11722 input_line_pointer
--;
11723 demand_empty_rest_of_line ();
11727 /* Handle Rounding Control / SAE specifiers. */
11730 RC_SAE_specifier (const char *pstr
)
11734 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11736 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11738 if (i
.rounding
.type
!= rc_none
)
11740 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11744 if (i
.vec_encoding
== vex_encoding_default
)
11745 i
.vec_encoding
= vex_encoding_evex512
;
11746 else if (i
.vec_encoding
!= vex_encoding_evex
11747 && i
.vec_encoding
!= vex_encoding_evex512
)
11750 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11752 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11759 /* Handle Vector operations. */
11762 check_VecOperations (char *op_string
)
11764 const reg_entry
*mask
;
11771 if (*op_string
== '{')
11775 /* Check broadcasts. */
11776 if (startswith (op_string
, "1to"))
11778 unsigned int bcst_type
;
11780 if (i
.broadcast
.type
)
11781 goto duplicated_vec_op
;
11784 if (*op_string
== '8')
11786 else if (*op_string
== '4')
11788 else if (*op_string
== '2')
11790 else if (*op_string
== '1'
11791 && *(op_string
+1) == '6')
11796 else if (*op_string
== '3'
11797 && *(op_string
+1) == '2')
11804 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11809 if (i
.vec_encoding
== vex_encoding_default
)
11810 i
.vec_encoding
= vex_encoding_evex
;
11811 else if (i
.vec_encoding
!= vex_encoding_evex
11812 && i
.vec_encoding
!= vex_encoding_evex512
)
11813 goto unknown_vec_op
;
11815 i
.broadcast
.type
= bcst_type
;
11816 i
.broadcast
.operand
= this_operand
;
11818 /* For .insn a data size specifier may be appended. */
11819 if (dot_insn () && *op_string
== ':')
11820 goto dot_insn_modifier
;
11822 /* Check .insn special cases. */
11823 else if (dot_insn () && *op_string
== ':')
11826 switch (op_string
[1])
11831 if (i
.memshift
< 32)
11832 goto duplicated_vec_op
;
11834 n
= strtoul (op_string
+ 2, &end_op
, 0);
11836 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11838 if (i
.memshift
< 32 && n
== 1)
11839 op_string
= end_op
;
11842 case 's': case 'u':
11843 /* This isn't really a "vector" operation, but a sign/size
11844 specifier for immediate operands of .insn. Note that AT&T
11845 syntax handles the same in i386_immediate(). */
11849 if (i
.imm_bits
[this_operand
])
11850 goto duplicated_vec_op
;
11852 n
= strtoul (op_string
+ 2, &end_op
, 0);
11853 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11855 i
.imm_bits
[this_operand
] = n
;
11856 if (op_string
[1] == 's')
11857 i
.flags
[this_operand
] |= Operand_Signed
;
11858 op_string
= end_op
;
11863 /* Check masking operation. */
11864 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11866 if (mask
== &bad_reg
)
11869 /* k0 can't be used for write mask. */
11870 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11872 as_bad (_("`%s%s' can't be used for write mask"),
11873 register_prefix
, mask
->reg_name
);
11880 i
.mask
.operand
= this_operand
;
11882 else if (i
.mask
.reg
->reg_num
)
11883 goto duplicated_vec_op
;
11888 /* Only "{z}" is allowed here. No need to check
11889 zeroing mask explicitly. */
11890 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11892 as_bad (_("invalid write mask `%s'"), saved
);
11897 op_string
= end_op
;
11899 /* Check zeroing-flag for masking operation. */
11900 else if (*op_string
== 'z')
11904 i
.mask
.reg
= reg_k0
;
11905 i
.mask
.zeroing
= 1;
11906 i
.mask
.operand
= this_operand
;
11910 if (i
.mask
.zeroing
)
11913 as_bad (_("duplicated `%s'"), saved
);
11917 i
.mask
.zeroing
= 1;
11919 /* Only "{%k}" is allowed here. No need to check mask
11920 register explicitly. */
11921 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11923 as_bad (_("invalid zeroing-masking `%s'"),
11931 else if (intel_syntax
11932 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11933 i
.rounding
.modifier
= true;
11935 goto unknown_vec_op
;
11937 if (*op_string
!= '}')
11939 as_bad (_("missing `}' in `%s'"), saved
);
11944 /* Strip whitespace since the addition of pseudo prefixes
11945 changed how the scrubber treats '{'. */
11946 if (is_space_char (*op_string
))
11952 /* We don't know this one. */
11953 as_bad (_("unknown vector operation: `%s'"), saved
);
11957 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11959 as_bad (_("zeroing-masking only allowed with write mask"));
11967 i386_immediate (char *imm_start
)
11969 char *save_input_line_pointer
;
11970 char *gotfree_input_line
;
11973 i386_operand_type types
;
11975 operand_type_set (&types
, ~0);
11977 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11979 as_bad (_("at most %d immediate operands are allowed"),
11980 MAX_IMMEDIATE_OPERANDS
);
11984 exp
= &im_expressions
[i
.imm_operands
++];
11985 i
.op
[this_operand
].imms
= exp
;
11987 if (is_space_char (*imm_start
))
11990 save_input_line_pointer
= input_line_pointer
;
11991 input_line_pointer
= imm_start
;
11993 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11994 if (gotfree_input_line
)
11995 input_line_pointer
= gotfree_input_line
;
11997 expr_mode
= expr_operator_none
;
11998 exp_seg
= expression (exp
);
12000 /* For .insn immediates there may be a size specifier. */
12001 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12002 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12005 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12007 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12009 i
.imm_bits
[this_operand
] = n
;
12010 if (input_line_pointer
[2] == 's')
12011 i
.flags
[this_operand
] |= Operand_Signed
;
12012 input_line_pointer
= e
+ 1;
12016 SKIP_WHITESPACE ();
12017 if (*input_line_pointer
)
12018 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12020 input_line_pointer
= save_input_line_pointer
;
12021 if (gotfree_input_line
)
12023 free (gotfree_input_line
);
12025 if (exp
->X_op
== O_constant
)
12026 exp
->X_op
= O_illegal
;
12029 if (exp_seg
== reg_section
)
12031 as_bad (_("illegal immediate register operand %s"), imm_start
);
12035 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12039 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12040 i386_operand_type types
, const char *imm_start
)
12042 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12045 as_bad (_("missing or invalid immediate expression `%s'"),
12049 else if (exp
->X_op
== O_constant
)
12051 /* Size it properly later. */
12052 i
.types
[this_operand
].bitfield
.imm64
= 1;
12054 /* If not 64bit, sign/zero extend val, to account for wraparound
12056 if (expr_mode
== expr_operator_present
12057 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12058 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12060 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12061 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12062 && exp_seg
!= absolute_section
12063 && exp_seg
!= text_section
12064 && exp_seg
!= data_section
12065 && exp_seg
!= bss_section
12066 && exp_seg
!= undefined_section
12067 && !bfd_is_com_section (exp_seg
))
12069 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12075 /* This is an address. The size of the address will be
12076 determined later, depending on destination register,
12077 suffix, or the default for the section. */
12078 i
.types
[this_operand
].bitfield
.imm8
= 1;
12079 i
.types
[this_operand
].bitfield
.imm16
= 1;
12080 i
.types
[this_operand
].bitfield
.imm32
= 1;
12081 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12082 i
.types
[this_operand
].bitfield
.imm64
= 1;
12083 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12091 i386_scale (char *scale
)
12094 char *save
= input_line_pointer
;
12096 input_line_pointer
= scale
;
12097 val
= get_absolute_expression ();
12102 i
.log2_scale_factor
= 0;
12105 i
.log2_scale_factor
= 1;
12108 i
.log2_scale_factor
= 2;
12111 i
.log2_scale_factor
= 3;
12115 char sep
= *input_line_pointer
;
12117 *input_line_pointer
= '\0';
12118 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12120 *input_line_pointer
= sep
;
12121 input_line_pointer
= save
;
12125 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12127 as_warn (_("scale factor of %d without an index register"),
12128 1 << i
.log2_scale_factor
);
12129 i
.log2_scale_factor
= 0;
12131 scale
= input_line_pointer
;
12132 input_line_pointer
= save
;
12137 i386_displacement (char *disp_start
, char *disp_end
)
12141 char *save_input_line_pointer
;
12142 char *gotfree_input_line
;
12144 i386_operand_type bigdisp
, types
= anydisp
;
12147 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12149 as_bad (_("at most %d displacement operands are allowed"),
12150 MAX_MEMORY_OPERANDS
);
12154 operand_type_set (&bigdisp
, 0);
12156 || i
.types
[this_operand
].bitfield
.baseindex
12157 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12158 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12160 i386_addressing_mode ();
12161 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12162 if (flag_code
== CODE_64BIT
)
12164 bigdisp
.bitfield
.disp32
= 1;
12166 bigdisp
.bitfield
.disp64
= 1;
12168 else if ((flag_code
== CODE_16BIT
) ^ override
)
12169 bigdisp
.bitfield
.disp16
= 1;
12171 bigdisp
.bitfield
.disp32
= 1;
12175 /* For PC-relative branches, the width of the displacement may be
12176 dependent upon data size, but is never dependent upon address size.
12177 Also make sure to not unintentionally match against a non-PC-relative
12178 branch template. */
12179 static templates aux_templates
;
12180 const insn_template
*t
= current_templates
->start
;
12181 bool has_intel64
= false;
12183 aux_templates
.start
= t
;
12184 while (++t
< current_templates
->end
)
12186 if (t
->opcode_modifier
.jump
12187 != current_templates
->start
->opcode_modifier
.jump
)
12189 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12190 has_intel64
= true;
12192 if (t
< current_templates
->end
)
12194 aux_templates
.end
= t
;
12195 current_templates
= &aux_templates
;
12198 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12199 if (flag_code
== CODE_64BIT
)
12201 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12202 && (!intel64
|| !has_intel64
))
12203 bigdisp
.bitfield
.disp16
= 1;
12205 bigdisp
.bitfield
.disp32
= 1;
12210 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12212 : LONG_MNEM_SUFFIX
));
12213 bigdisp
.bitfield
.disp32
= 1;
12214 if ((flag_code
== CODE_16BIT
) ^ override
)
12216 bigdisp
.bitfield
.disp32
= 0;
12217 bigdisp
.bitfield
.disp16
= 1;
12221 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12224 exp
= &disp_expressions
[i
.disp_operands
];
12225 i
.op
[this_operand
].disps
= exp
;
12227 save_input_line_pointer
= input_line_pointer
;
12228 input_line_pointer
= disp_start
;
12229 END_STRING_AND_SAVE (disp_end
);
12231 #ifndef GCC_ASM_O_HACK
12232 #define GCC_ASM_O_HACK 0
12235 END_STRING_AND_SAVE (disp_end
+ 1);
12236 if (i
.types
[this_operand
].bitfield
.baseIndex
12237 && displacement_string_end
[-1] == '+')
12239 /* This hack is to avoid a warning when using the "o"
12240 constraint within gcc asm statements.
12243 #define _set_tssldt_desc(n,addr,limit,type) \
12244 __asm__ __volatile__ ( \
12245 "movw %w2,%0\n\t" \
12246 "movw %w1,2+%0\n\t" \
12247 "rorl $16,%1\n\t" \
12248 "movb %b1,4+%0\n\t" \
12249 "movb %4,5+%0\n\t" \
12250 "movb $0,6+%0\n\t" \
12251 "movb %h1,7+%0\n\t" \
12253 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12255 This works great except that the output assembler ends
12256 up looking a bit weird if it turns out that there is
12257 no offset. You end up producing code that looks like:
12270 So here we provide the missing zero. */
12272 *displacement_string_end
= '0';
12275 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12276 if (gotfree_input_line
)
12277 input_line_pointer
= gotfree_input_line
;
12279 expr_mode
= expr_operator_none
;
12280 exp_seg
= expression (exp
);
12282 SKIP_WHITESPACE ();
12283 if (*input_line_pointer
)
12284 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12286 RESTORE_END_STRING (disp_end
+ 1);
12288 input_line_pointer
= save_input_line_pointer
;
12289 if (gotfree_input_line
)
12291 free (gotfree_input_line
);
12293 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12294 exp
->X_op
= O_illegal
;
12297 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12299 RESTORE_END_STRING (disp_end
);
12305 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12306 i386_operand_type types
, const char *disp_start
)
12310 /* We do this to make sure that the section symbol is in
12311 the symbol table. We will ultimately change the relocation
12312 to be relative to the beginning of the section. */
12313 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12314 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12315 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12317 if (exp
->X_op
!= O_symbol
)
12320 if (S_IS_LOCAL (exp
->X_add_symbol
)
12321 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12322 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12323 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12324 exp
->X_op
= O_subtract
;
12325 exp
->X_op_symbol
= GOT_symbol
;
12326 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12327 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12328 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12329 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12331 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12334 else if (exp
->X_op
== O_absent
12335 || exp
->X_op
== O_illegal
12336 || exp
->X_op
== O_big
)
12339 as_bad (_("missing or invalid displacement expression `%s'"),
12344 else if (exp
->X_op
== O_constant
)
12346 /* Sizing gets taken care of by optimize_disp().
12348 If not 64bit, sign/zero extend val, to account for wraparound
12350 if (expr_mode
== expr_operator_present
12351 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12352 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12355 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12356 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12357 && exp_seg
!= absolute_section
12358 && exp_seg
!= text_section
12359 && exp_seg
!= data_section
12360 && exp_seg
!= bss_section
12361 && exp_seg
!= undefined_section
12362 && !bfd_is_com_section (exp_seg
))
12364 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12369 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12370 i
.types
[this_operand
].bitfield
.disp8
= 1;
12372 /* Check if this is a displacement only operand. */
12373 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12374 i
.types
[this_operand
] =
12375 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12376 operand_type_and (i
.types
[this_operand
], types
));
12381 /* Return the active addressing mode, taking address override and
12382 registers forming the address into consideration. Update the
12383 address override prefix if necessary. */
12385 static enum flag_code
12386 i386_addressing_mode (void)
12388 enum flag_code addr_mode
;
12390 if (i
.prefix
[ADDR_PREFIX
])
12391 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12392 else if (flag_code
== CODE_16BIT
12393 && is_cpu (current_templates
->start
, CpuMPX
)
12394 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12395 from md_assemble() by "is not a valid base/index expression"
12396 when there is a base and/or index. */
12397 && !i
.types
[this_operand
].bitfield
.baseindex
)
12399 /* MPX insn memory operands with neither base nor index must be forced
12400 to use 32-bit addressing in 16-bit mode. */
12401 addr_mode
= CODE_32BIT
;
12402 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12404 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12405 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12409 addr_mode
= flag_code
;
12411 #if INFER_ADDR_PREFIX
12412 if (i
.mem_operands
== 0)
12414 /* Infer address prefix from the first memory operand. */
12415 const reg_entry
*addr_reg
= i
.base_reg
;
12417 if (addr_reg
== NULL
)
12418 addr_reg
= i
.index_reg
;
12422 if (addr_reg
->reg_type
.bitfield
.dword
)
12423 addr_mode
= CODE_32BIT
;
12424 else if (flag_code
!= CODE_64BIT
12425 && addr_reg
->reg_type
.bitfield
.word
)
12426 addr_mode
= CODE_16BIT
;
12428 if (addr_mode
!= flag_code
)
12430 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12432 /* Change the size of any displacement too. At most one
12433 of Disp16 or Disp32 is set.
12434 FIXME. There doesn't seem to be any real need for
12435 separate Disp16 and Disp32 flags. The same goes for
12436 Imm16 and Imm32. Removing them would probably clean
12437 up the code quite a lot. */
12438 if (flag_code
!= CODE_64BIT
12439 && (i
.types
[this_operand
].bitfield
.disp16
12440 || i
.types
[this_operand
].bitfield
.disp32
))
12442 static const i386_operand_type disp16_32
= {
12443 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12446 i
.types
[this_operand
]
12447 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12458 /* Make sure the memory operand we've been dealt is valid.
12459 Return 1 on success, 0 on a failure. */
12462 i386_index_check (const char *operand_string
)
12464 const char *kind
= "base/index";
12465 enum flag_code addr_mode
= i386_addressing_mode ();
12466 const insn_template
*t
= current_templates
->end
- 1;
12468 if (t
->opcode_modifier
.isstring
)
12470 /* Memory operands of string insns are special in that they only allow
12471 a single register (rDI, rSI, or rBX) as their memory address. */
12472 const reg_entry
*expected_reg
;
12473 static const char di_si
[][2][4] =
12479 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12481 kind
= "string address";
12483 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12485 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12488 if (!t
->operand_types
[0].bitfield
.baseindex
12489 || ((!i
.mem_operands
!= !intel_syntax
)
12490 && t
->operand_types
[1].bitfield
.baseindex
))
12493 = (const reg_entry
*) str_hash_find (reg_hash
,
12494 di_si
[addr_mode
][op
== es_op
]);
12498 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12500 if (i
.base_reg
!= expected_reg
12502 || operand_type_check (i
.types
[this_operand
], disp
))
12504 /* The second memory operand must have the same size as
12508 && !((addr_mode
== CODE_64BIT
12509 && i
.base_reg
->reg_type
.bitfield
.qword
)
12510 || (addr_mode
== CODE_32BIT
12511 ? i
.base_reg
->reg_type
.bitfield
.dword
12512 : i
.base_reg
->reg_type
.bitfield
.word
)))
12515 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12517 intel_syntax
? '[' : '(',
12519 expected_reg
->reg_name
,
12520 intel_syntax
? ']' : ')');
12527 as_bad (_("`%s' is not a valid %s expression"),
12528 operand_string
, kind
);
12533 t
= current_templates
->start
;
12535 if (addr_mode
!= CODE_16BIT
)
12537 /* 32-bit/64-bit checks. */
12538 if (i
.disp_encoding
== disp_encoding_16bit
)
12541 as_bad (_("invalid `%s' prefix"),
12542 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12547 && ((addr_mode
== CODE_64BIT
12548 ? !i
.base_reg
->reg_type
.bitfield
.qword
12549 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12550 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12551 || i
.base_reg
->reg_num
== RegIZ
))
12553 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12554 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12555 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12556 && ((addr_mode
== CODE_64BIT
12557 ? !i
.index_reg
->reg_type
.bitfield
.qword
12558 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12559 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12562 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12563 if (t
->mnem_off
== MN_bndmk
12564 || t
->mnem_off
== MN_bndldx
12565 || t
->mnem_off
== MN_bndstx
12566 || t
->opcode_modifier
.sib
== SIBMEM
)
12568 /* They cannot use RIP-relative addressing. */
12569 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12571 as_bad (_("`%s' cannot be used here"), operand_string
);
12575 /* bndldx and bndstx ignore their scale factor. */
12576 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12577 && i
.log2_scale_factor
)
12578 as_warn (_("register scaling is being ignored here"));
12583 /* 16-bit checks. */
12584 if (i
.disp_encoding
== disp_encoding_32bit
)
12588 && (!i
.base_reg
->reg_type
.bitfield
.word
12589 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12591 && (!i
.index_reg
->reg_type
.bitfield
.word
12592 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12594 && i
.base_reg
->reg_num
< 6
12595 && i
.index_reg
->reg_num
>= 6
12596 && i
.log2_scale_factor
== 0))))
12603 /* Handle vector immediates. */
12606 RC_SAE_immediate (const char *imm_start
)
12608 const char *pstr
= imm_start
;
12613 pstr
= RC_SAE_specifier (pstr
+ 1);
12617 if (*pstr
++ != '}')
12619 as_bad (_("Missing '}': '%s'"), imm_start
);
12622 /* RC/SAE immediate string should contain nothing more. */;
12625 as_bad (_("Junk after '}': '%s'"), imm_start
);
12629 /* Internally this doesn't count as an operand. */
12635 static INLINE
bool starts_memory_operand (char c
)
12638 || is_name_beginner (c
)
12639 || strchr ("([\"+-!~", c
);
12642 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12646 i386_att_operand (char *operand_string
)
12648 const reg_entry
*r
;
12650 char *op_string
= operand_string
;
12652 if (is_space_char (*op_string
))
12655 /* We check for an absolute prefix (differentiating,
12656 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12657 if (*op_string
== ABSOLUTE_PREFIX
12658 && current_templates
->start
->opcode_modifier
.jump
)
12661 if (is_space_char (*op_string
))
12663 i
.jumpabsolute
= true;
12666 /* Check if operand is a register. */
12667 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12669 i386_operand_type temp
;
12674 /* Check for a segment override by searching for ':' after a
12675 segment register. */
12676 op_string
= end_op
;
12677 if (is_space_char (*op_string
))
12679 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12681 i
.seg
[i
.mem_operands
] = r
;
12683 /* Skip the ':' and whitespace. */
12685 if (is_space_char (*op_string
))
12688 /* Handle case of %es:*foo. */
12689 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12690 && current_templates
->start
->opcode_modifier
.jump
)
12693 if (is_space_char (*op_string
))
12695 i
.jumpabsolute
= true;
12698 if (!starts_memory_operand (*op_string
))
12700 as_bad (_("bad memory operand `%s'"), op_string
);
12703 goto do_memory_reference
;
12706 /* Handle vector operations. */
12707 if (*op_string
== '{')
12709 op_string
= check_VecOperations (op_string
);
12710 if (op_string
== NULL
)
12716 as_bad (_("junk `%s' after register"), op_string
);
12720 /* Reject pseudo registers for .insn. */
12721 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12723 as_bad (_("`%s%s' cannot be used here"),
12724 register_prefix
, r
->reg_name
);
12728 temp
= r
->reg_type
;
12729 temp
.bitfield
.baseindex
= 0;
12730 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12732 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12733 i
.op
[this_operand
].regs
= r
;
12736 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12737 operand was also present earlier on. */
12738 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12739 && i
.reg_operands
== 1)
12743 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12744 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12746 as_bad (_("`%s': misplaced `{%s}'"),
12747 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12751 else if (*op_string
== REGISTER_PREFIX
)
12753 as_bad (_("bad register name `%s'"), op_string
);
12756 else if (*op_string
== IMMEDIATE_PREFIX
)
12759 if (i
.jumpabsolute
)
12761 as_bad (_("immediate operand illegal with absolute jump"));
12764 if (!i386_immediate (op_string
))
12766 if (i
.rounding
.type
!= rc_none
)
12768 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12769 insn_name (current_templates
->start
));
12773 else if (RC_SAE_immediate (operand_string
))
12775 /* If it is a RC or SAE immediate, do the necessary placement check:
12776 Only another immediate or a GPR may precede it. */
12777 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12778 || (i
.reg_operands
== 1
12779 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12781 as_bad (_("`%s': misplaced `%s'"),
12782 insn_name (current_templates
->start
), operand_string
);
12786 else if (starts_memory_operand (*op_string
))
12788 /* This is a memory reference of some sort. */
12791 /* Start and end of displacement string expression (if found). */
12792 char *displacement_string_start
;
12793 char *displacement_string_end
;
12795 do_memory_reference
:
12796 /* Check for base index form. We detect the base index form by
12797 looking for an ')' at the end of the operand, searching
12798 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12800 base_string
= op_string
+ strlen (op_string
);
12802 /* Handle vector operations. */
12804 if (is_space_char (*base_string
))
12807 if (*base_string
== '}')
12809 char *vop_start
= NULL
;
12811 while (base_string
-- > op_string
)
12813 if (*base_string
== '"')
12815 if (*base_string
!= '{')
12818 vop_start
= base_string
;
12821 if (is_space_char (*base_string
))
12824 if (*base_string
!= '}')
12832 as_bad (_("unbalanced figure braces"));
12836 if (check_VecOperations (vop_start
) == NULL
)
12840 /* If we only have a displacement, set-up for it to be parsed later. */
12841 displacement_string_start
= op_string
;
12842 displacement_string_end
= base_string
+ 1;
12844 if (*base_string
== ')')
12847 unsigned int parens_not_balanced
= 0;
12848 bool in_quotes
= false;
12850 /* We've already checked that the number of left & right ()'s are
12851 equal, and that there's a matching set of double quotes. */
12852 end_op
= base_string
;
12853 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12855 if (*temp_string
== '\\' && temp_string
[1] == '"')
12857 else if (*temp_string
== '"')
12858 in_quotes
= !in_quotes
;
12859 else if (!in_quotes
)
12861 if (*temp_string
== '(' && !parens_not_balanced
++)
12862 base_string
= temp_string
;
12863 if (*temp_string
== ')')
12864 --parens_not_balanced
;
12868 temp_string
= base_string
;
12870 /* Skip past '(' and whitespace. */
12871 gas_assert (*base_string
== '(');
12873 if (is_space_char (*base_string
))
12876 if (*base_string
== ','
12877 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12880 displacement_string_end
= temp_string
;
12882 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12886 if (i
.base_reg
== &bad_reg
)
12888 base_string
= end_op
;
12889 if (is_space_char (*base_string
))
12893 /* There may be an index reg or scale factor here. */
12894 if (*base_string
== ',')
12897 if (is_space_char (*base_string
))
12900 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12903 if (i
.index_reg
== &bad_reg
)
12905 base_string
= end_op
;
12906 if (is_space_char (*base_string
))
12908 if (*base_string
== ',')
12911 if (is_space_char (*base_string
))
12914 else if (*base_string
!= ')')
12916 as_bad (_("expecting `,' or `)' "
12917 "after index register in `%s'"),
12922 else if (*base_string
== REGISTER_PREFIX
)
12924 end_op
= strchr (base_string
, ',');
12927 as_bad (_("bad register name `%s'"), base_string
);
12931 /* Check for scale factor. */
12932 if (*base_string
!= ')')
12934 char *end_scale
= i386_scale (base_string
);
12939 base_string
= end_scale
;
12940 if (is_space_char (*base_string
))
12942 if (*base_string
!= ')')
12944 as_bad (_("expecting `)' "
12945 "after scale factor in `%s'"),
12950 else if (!i
.index_reg
)
12952 as_bad (_("expecting index register or scale factor "
12953 "after `,'; got '%c'"),
12958 else if (*base_string
!= ')')
12960 as_bad (_("expecting `,' or `)' "
12961 "after base register in `%s'"),
12966 else if (*base_string
== REGISTER_PREFIX
)
12968 end_op
= strchr (base_string
, ',');
12971 as_bad (_("bad register name `%s'"), base_string
);
12976 /* If there's an expression beginning the operand, parse it,
12977 assuming displacement_string_start and
12978 displacement_string_end are meaningful. */
12979 if (displacement_string_start
!= displacement_string_end
)
12981 if (!i386_displacement (displacement_string_start
,
12982 displacement_string_end
))
12986 /* Special case for (%dx) while doing input/output op. */
12988 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12989 && i
.base_reg
->reg_type
.bitfield
.word
12990 && i
.index_reg
== 0
12991 && i
.log2_scale_factor
== 0
12992 && i
.seg
[i
.mem_operands
] == 0
12993 && !operand_type_check (i
.types
[this_operand
], disp
))
12995 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12996 i
.input_output_operand
= true;
13000 if (i386_index_check (operand_string
) == 0)
13002 i
.flags
[this_operand
] |= Operand_Mem
;
13007 /* It's not a memory operand; argh! */
13008 as_bad (_("invalid char %s beginning operand %d `%s'"),
13009 output_invalid (*op_string
),
13014 return 1; /* Normal return. */
13017 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13018 that an rs_machine_dependent frag may reach. */
13021 i386_frag_max_var (fragS
*frag
)
13023 /* The only relaxable frags are for jumps.
13024 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13025 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13026 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13031 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13033 /* STT_GNU_IFUNC symbol must go through PLT. */
13034 if ((symbol_get_bfdsym (fr_symbol
)->flags
13035 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13038 if (!S_IS_EXTERNAL (fr_symbol
))
13039 /* Symbol may be weak or local. */
13040 return !S_IS_WEAK (fr_symbol
);
13042 /* Global symbols with non-default visibility can't be preempted. */
13043 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13046 if (fr_var
!= NO_RELOC
)
13047 switch ((enum bfd_reloc_code_real
) fr_var
)
13049 case BFD_RELOC_386_PLT32
:
13050 case BFD_RELOC_X86_64_PLT32
:
13051 /* Symbol with PLT relocation may be preempted. */
13057 /* Global symbols with default visibility in a shared library may be
13058 preempted by another definition. */
13063 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13064 Note also work for Skylake and Cascadelake.
13065 ---------------------------------------------------------------------
13066 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13067 | ------ | ----------- | ------- | -------- |
13069 | Jno | N | N | Y |
13070 | Jc/Jb | Y | N | Y |
13071 | Jae/Jnb | Y | N | Y |
13072 | Je/Jz | Y | Y | Y |
13073 | Jne/Jnz | Y | Y | Y |
13074 | Jna/Jbe | Y | N | Y |
13075 | Ja/Jnbe | Y | N | Y |
13077 | Jns | N | N | Y |
13078 | Jp/Jpe | N | N | Y |
13079 | Jnp/Jpo | N | N | Y |
13080 | Jl/Jnge | Y | Y | Y |
13081 | Jge/Jnl | Y | Y | Y |
13082 | Jle/Jng | Y | Y | Y |
13083 | Jg/Jnle | Y | Y | Y |
13084 --------------------------------------------------------------------- */
13086 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13088 if (mf_cmp
== mf_cmp_alu_cmp
)
13089 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13090 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13091 if (mf_cmp
== mf_cmp_incdec
)
13092 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13093 || mf_jcc
== mf_jcc_jle
);
13094 if (mf_cmp
== mf_cmp_test_and
)
13099 /* Return the next non-empty frag. */
13102 i386_next_non_empty_frag (fragS
*fragP
)
13104 /* There may be a frag with a ".fill 0" when there is no room in
13105 the current frag for frag_grow in output_insn. */
13106 for (fragP
= fragP
->fr_next
;
13108 && fragP
->fr_type
== rs_fill
13109 && fragP
->fr_fix
== 0);
13110 fragP
= fragP
->fr_next
)
13115 /* Return the next jcc frag after BRANCH_PADDING. */
13118 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13120 fragS
*branch_fragP
;
13124 if (pad_fragP
->fr_type
== rs_machine_dependent
13125 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13126 == BRANCH_PADDING
))
13128 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13129 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13131 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13132 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13133 pad_fragP
->tc_frag_data
.mf_type
))
13134 return branch_fragP
;
13140 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13143 i386_classify_machine_dependent_frag (fragS
*fragP
)
13147 fragS
*branch_fragP
;
13149 unsigned int max_prefix_length
;
13151 if (fragP
->tc_frag_data
.classified
)
13154 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13155 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13156 for (next_fragP
= fragP
;
13157 next_fragP
!= NULL
;
13158 next_fragP
= next_fragP
->fr_next
)
13160 next_fragP
->tc_frag_data
.classified
= 1;
13161 if (next_fragP
->fr_type
== rs_machine_dependent
)
13162 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13164 case BRANCH_PADDING
:
13165 /* The BRANCH_PADDING frag must be followed by a branch
13167 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13168 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13170 case FUSED_JCC_PADDING
:
13171 /* Check if this is a fused jcc:
13173 CMP like instruction
13177 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13178 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13179 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13182 /* The BRANCH_PADDING frag is merged with the
13183 FUSED_JCC_PADDING frag. */
13184 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13185 /* CMP like instruction size. */
13186 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13187 frag_wane (pad_fragP
);
13188 /* Skip to branch_fragP. */
13189 next_fragP
= branch_fragP
;
13191 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13193 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13195 next_fragP
->fr_subtype
13196 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13197 next_fragP
->tc_frag_data
.max_bytes
13198 = next_fragP
->tc_frag_data
.max_prefix_length
;
13199 /* This will be updated in the BRANCH_PREFIX scan. */
13200 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13203 frag_wane (next_fragP
);
13208 /* Stop if there is no BRANCH_PREFIX. */
13209 if (!align_branch_prefix_size
)
13212 /* Scan for BRANCH_PREFIX. */
13213 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13215 if (fragP
->fr_type
!= rs_machine_dependent
13216 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13220 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13221 COND_JUMP_PREFIX. */
13222 max_prefix_length
= 0;
13223 for (next_fragP
= fragP
;
13224 next_fragP
!= NULL
;
13225 next_fragP
= next_fragP
->fr_next
)
13227 if (next_fragP
->fr_type
== rs_fill
)
13228 /* Skip rs_fill frags. */
13230 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13231 /* Stop for all other frags. */
13234 /* rs_machine_dependent frags. */
13235 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13238 /* Count BRANCH_PREFIX frags. */
13239 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13241 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13242 frag_wane (next_fragP
);
13246 += next_fragP
->tc_frag_data
.max_bytes
;
13248 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13250 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13251 == FUSED_JCC_PADDING
))
13253 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13254 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13258 /* Stop for other rs_machine_dependent frags. */
13262 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13264 /* Skip to the next frag. */
13265 fragP
= next_fragP
;
13269 /* Compute padding size for
13272 CMP like instruction
13274 COND_JUMP/UNCOND_JUMP
13279 COND_JUMP/UNCOND_JUMP
13283 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13285 unsigned int offset
, size
, padding_size
;
13286 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13288 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13290 address
= fragP
->fr_address
;
13291 address
+= fragP
->fr_fix
;
13293 /* CMP like instrunction size. */
13294 size
= fragP
->tc_frag_data
.cmp_size
;
13296 /* The base size of the branch frag. */
13297 size
+= branch_fragP
->fr_fix
;
13299 /* Add opcode and displacement bytes for the rs_machine_dependent
13301 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13302 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13304 /* Check if branch is within boundary and doesn't end at the last
13306 offset
= address
& ((1U << align_branch_power
) - 1);
13307 if ((offset
+ size
) >= (1U << align_branch_power
))
13308 /* Padding needed to avoid crossing boundary. */
13309 padding_size
= (1U << align_branch_power
) - offset
;
13311 /* No padding needed. */
13314 /* The return value may be saved in tc_frag_data.length which is
13316 if (!fits_in_unsigned_byte (padding_size
))
13319 return padding_size
;
13322 /* i386_generic_table_relax_frag()
13324 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13325 grow/shrink padding to align branch frags. Hand others to
13329 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13331 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13332 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13334 long padding_size
= i386_branch_padding_size (fragP
, 0);
13335 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13337 /* When the BRANCH_PREFIX frag is used, the computed address
13338 must match the actual address and there should be no padding. */
13339 if (fragP
->tc_frag_data
.padding_address
13340 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13344 /* Update the padding size. */
13346 fragP
->tc_frag_data
.length
= padding_size
;
13350 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13352 fragS
*padding_fragP
, *next_fragP
;
13353 long padding_size
, left_size
, last_size
;
13355 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13356 if (!padding_fragP
)
13357 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13358 return (fragP
->tc_frag_data
.length
13359 - fragP
->tc_frag_data
.last_length
);
13361 /* Compute the relative address of the padding frag in the very
13362 first time where the BRANCH_PREFIX frag sizes are zero. */
13363 if (!fragP
->tc_frag_data
.padding_address
)
13364 fragP
->tc_frag_data
.padding_address
13365 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13367 /* First update the last length from the previous interation. */
13368 left_size
= fragP
->tc_frag_data
.prefix_length
;
13369 for (next_fragP
= fragP
;
13370 next_fragP
!= padding_fragP
;
13371 next_fragP
= next_fragP
->fr_next
)
13372 if (next_fragP
->fr_type
== rs_machine_dependent
13373 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13378 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13382 if (max
> left_size
)
13387 next_fragP
->tc_frag_data
.last_length
= size
;
13391 next_fragP
->tc_frag_data
.last_length
= 0;
13394 /* Check the padding size for the padding frag. */
13395 padding_size
= i386_branch_padding_size
13396 (padding_fragP
, (fragP
->fr_address
13397 + fragP
->tc_frag_data
.padding_address
));
13399 last_size
= fragP
->tc_frag_data
.prefix_length
;
13400 /* Check if there is change from the last interation. */
13401 if (padding_size
== last_size
)
13403 /* Update the expected address of the padding frag. */
13404 padding_fragP
->tc_frag_data
.padding_address
13405 = (fragP
->fr_address
+ padding_size
13406 + fragP
->tc_frag_data
.padding_address
);
13410 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13412 /* No padding if there is no sufficient room. Clear the
13413 expected address of the padding frag. */
13414 padding_fragP
->tc_frag_data
.padding_address
= 0;
13418 /* Store the expected address of the padding frag. */
13419 padding_fragP
->tc_frag_data
.padding_address
13420 = (fragP
->fr_address
+ padding_size
13421 + fragP
->tc_frag_data
.padding_address
);
13423 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13425 /* Update the length for the current interation. */
13426 left_size
= padding_size
;
13427 for (next_fragP
= fragP
;
13428 next_fragP
!= padding_fragP
;
13429 next_fragP
= next_fragP
->fr_next
)
13430 if (next_fragP
->fr_type
== rs_machine_dependent
13431 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13436 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13440 if (max
> left_size
)
13445 next_fragP
->tc_frag_data
.length
= size
;
13449 next_fragP
->tc_frag_data
.length
= 0;
13452 return (fragP
->tc_frag_data
.length
13453 - fragP
->tc_frag_data
.last_length
);
13455 return relax_frag (segment
, fragP
, stretch
);
13458 /* md_estimate_size_before_relax()
13460 Called just before relax() for rs_machine_dependent frags. The x86
13461 assembler uses these frags to handle variable size jump
13464 Any symbol that is now undefined will not become defined.
13465 Return the correct fr_subtype in the frag.
13466 Return the initial "guess for variable size of frag" to caller.
13467 The guess is actually the growth beyond the fixed part. Whatever
13468 we do to grow the fixed or variable part contributes to our
13472 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13474 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13475 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13476 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13478 i386_classify_machine_dependent_frag (fragP
);
13479 return fragP
->tc_frag_data
.length
;
13482 /* We've already got fragP->fr_subtype right; all we have to do is
13483 check for un-relaxable symbols. On an ELF system, we can't relax
13484 an externally visible symbol, because it may be overridden by a
13486 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13489 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13492 #if defined (OBJ_COFF) && defined (TE_PE)
13493 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13494 && S_IS_WEAK (fragP
->fr_symbol
))
13498 /* Symbol is undefined in this segment, or we need to keep a
13499 reloc so that weak symbols can be overridden. */
13500 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13501 enum bfd_reloc_code_real reloc_type
;
13502 unsigned char *opcode
;
13506 if (fragP
->fr_var
!= NO_RELOC
)
13507 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13508 else if (size
== 2)
13509 reloc_type
= BFD_RELOC_16_PCREL
;
13510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13511 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13512 && fragP
->fr_offset
== 0
13513 && need_plt32_p (fragP
->fr_symbol
))
13514 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13517 reloc_type
= BFD_RELOC_32_PCREL
;
13519 old_fr_fix
= fragP
->fr_fix
;
13520 opcode
= (unsigned char *) fragP
->fr_opcode
;
13522 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13525 /* Make jmp (0xeb) a (d)word displacement jump. */
13527 fragP
->fr_fix
+= size
;
13528 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13530 fragP
->fr_offset
, 1,
13536 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13538 /* Negate the condition, and branch past an
13539 unconditional jump. */
13542 /* Insert an unconditional jump. */
13544 /* We added two extra opcode bytes, and have a two byte
13546 fragP
->fr_fix
+= 2 + 2;
13547 fix_new (fragP
, old_fr_fix
+ 2, 2,
13549 fragP
->fr_offset
, 1,
13553 /* Fall through. */
13556 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13558 fragP
->fr_fix
+= 1;
13559 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13561 fragP
->fr_offset
, 1,
13562 BFD_RELOC_8_PCREL
);
13563 fixP
->fx_signed
= 1;
13567 /* This changes the byte-displacement jump 0x7N
13568 to the (d)word-displacement jump 0x0f,0x8N. */
13569 opcode
[1] = opcode
[0] + 0x10;
13570 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13571 /* We've added an opcode byte. */
13572 fragP
->fr_fix
+= 1 + size
;
13573 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13575 fragP
->fr_offset
, 1,
13580 BAD_CASE (fragP
->fr_subtype
);
13584 /* All jumps handled here are signed, but don't unconditionally use a
13585 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13586 around at 4G (outside of 64-bit mode) and 64k. */
13587 if (size
== 4 && flag_code
== CODE_64BIT
)
13588 fixP
->fx_signed
= 1;
13591 return fragP
->fr_fix
- old_fr_fix
;
13594 /* Guess size depending on current relax state. Initially the relax
13595 state will correspond to a short jump and we return 1, because
13596 the variable part of the frag (the branch offset) is one byte
13597 long. However, we can relax a section more than once and in that
13598 case we must either set fr_subtype back to the unrelaxed state,
13599 or return the value for the appropriate branch. */
13600 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13603 /* Called after relax() is finished.
13605 In: Address of frag.
13606 fr_type == rs_machine_dependent.
13607 fr_subtype is what the address relaxed to.
13609 Out: Any fixSs and constants are set up.
13610 Caller will turn frag into a ".space 0". */
13613 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13616 unsigned char *opcode
;
13617 unsigned char *where_to_put_displacement
= NULL
;
13618 offsetT target_address
;
13619 offsetT opcode_address
;
13620 unsigned int extension
= 0;
13621 offsetT displacement_from_opcode_start
;
13623 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13624 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13625 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13627 /* Generate nop padding. */
13628 unsigned int size
= fragP
->tc_frag_data
.length
;
13631 if (size
> fragP
->tc_frag_data
.max_bytes
)
13637 const char *branch
= "branch";
13638 const char *prefix
= "";
13639 fragS
*padding_fragP
;
13640 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13643 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13644 switch (fragP
->tc_frag_data
.default_prefix
)
13649 case CS_PREFIX_OPCODE
:
13652 case DS_PREFIX_OPCODE
:
13655 case ES_PREFIX_OPCODE
:
13658 case FS_PREFIX_OPCODE
:
13661 case GS_PREFIX_OPCODE
:
13664 case SS_PREFIX_OPCODE
:
13669 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13670 "%s within %d-byte boundary\n");
13672 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13673 "align %s within %d-byte boundary\n");
13677 padding_fragP
= fragP
;
13678 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13679 "%s within %d-byte boundary\n");
13683 switch (padding_fragP
->tc_frag_data
.branch_type
)
13685 case align_branch_jcc
:
13688 case align_branch_fused
:
13689 branch
= "fused jcc";
13691 case align_branch_jmp
:
13694 case align_branch_call
:
13697 case align_branch_indirect
:
13698 branch
= "indiret branch";
13700 case align_branch_ret
:
13707 fprintf (stdout
, msg
,
13708 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13709 (long long) fragP
->fr_address
, branch
,
13710 1 << align_branch_power
);
13712 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13713 memset (fragP
->fr_opcode
,
13714 fragP
->tc_frag_data
.default_prefix
, size
);
13716 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13718 fragP
->fr_fix
+= size
;
13723 opcode
= (unsigned char *) fragP
->fr_opcode
;
13725 /* Address we want to reach in file space. */
13726 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13728 /* Address opcode resides at in file space. */
13729 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13731 /* Displacement from opcode start to fill into instruction. */
13732 displacement_from_opcode_start
= target_address
- opcode_address
;
13734 if ((fragP
->fr_subtype
& BIG
) == 0)
13736 /* Don't have to change opcode. */
13737 extension
= 1; /* 1 opcode + 1 displacement */
13738 where_to_put_displacement
= &opcode
[1];
13742 if (no_cond_jump_promotion
13743 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13744 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13745 _("long jump required"));
13747 switch (fragP
->fr_subtype
)
13749 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13750 extension
= 4; /* 1 opcode + 4 displacement */
13752 where_to_put_displacement
= &opcode
[1];
13755 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13756 extension
= 2; /* 1 opcode + 2 displacement */
13758 where_to_put_displacement
= &opcode
[1];
13761 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13762 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13763 extension
= 5; /* 2 opcode + 4 displacement */
13764 opcode
[1] = opcode
[0] + 0x10;
13765 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13766 where_to_put_displacement
= &opcode
[2];
13769 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13770 extension
= 3; /* 2 opcode + 2 displacement */
13771 opcode
[1] = opcode
[0] + 0x10;
13772 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13773 where_to_put_displacement
= &opcode
[2];
13776 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13781 where_to_put_displacement
= &opcode
[3];
13785 BAD_CASE (fragP
->fr_subtype
);
13790 /* If size if less then four we are sure that the operand fits,
13791 but if it's 4, then it could be that the displacement is larger
13793 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13795 && ((addressT
) (displacement_from_opcode_start
- extension
13796 + ((addressT
) 1 << 31))
13797 > (((addressT
) 2 << 31) - 1)))
13799 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13800 _("jump target out of range"));
13801 /* Make us emit 0. */
13802 displacement_from_opcode_start
= extension
;
13804 /* Now put displacement after opcode. */
13805 md_number_to_chars ((char *) where_to_put_displacement
,
13806 (valueT
) (displacement_from_opcode_start
- extension
),
13807 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13808 fragP
->fr_fix
+= extension
;
13811 /* Apply a fixup (fixP) to segment data, once it has been determined
13812 by our caller that we have all the info we need to fix it up.
13814 Parameter valP is the pointer to the value of the bits.
13816 On the 386, immediates, displacements, and data pointers are all in
13817 the same (little-endian) format, so we don't need to care about which
13818 we are handling. */
13821 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13823 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13824 valueT value
= *valP
;
13826 #if !defined (TE_Mach)
13827 if (fixP
->fx_pcrel
)
13829 switch (fixP
->fx_r_type
)
13835 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13838 case BFD_RELOC_X86_64_32S
:
13839 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13842 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13845 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13850 if (fixP
->fx_addsy
!= NULL
13851 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13852 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13853 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13854 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13855 && !use_rela_relocations
)
13857 /* This is a hack. There should be a better way to handle this.
13858 This covers for the fact that bfd_install_relocation will
13859 subtract the current location (for partial_inplace, PC relative
13860 relocations); see more below. */
13864 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13867 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13872 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13874 if ((sym_seg
== seg
13875 || (symbol_section_p (fixP
->fx_addsy
)
13876 && sym_seg
!= absolute_section
))
13877 && !generic_force_reloc (fixP
))
13879 /* Yes, we add the values in twice. This is because
13880 bfd_install_relocation subtracts them out again. I think
13881 bfd_install_relocation is broken, but I don't dare change
13883 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13887 #if defined (OBJ_COFF) && defined (TE_PE)
13888 /* For some reason, the PE format does not store a
13889 section address offset for a PC relative symbol. */
13890 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13891 || S_IS_WEAK (fixP
->fx_addsy
))
13892 value
+= md_pcrel_from (fixP
);
13895 #if defined (OBJ_COFF) && defined (TE_PE)
13896 if (fixP
->fx_addsy
!= NULL
13897 && S_IS_WEAK (fixP
->fx_addsy
)
13898 /* PR 16858: Do not modify weak function references. */
13899 && ! fixP
->fx_pcrel
)
13901 #if !defined (TE_PEP)
13902 /* For x86 PE weak function symbols are neither PC-relative
13903 nor do they set S_IS_FUNCTION. So the only reliable way
13904 to detect them is to check the flags of their containing
13906 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13907 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13911 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13915 /* Fix a few things - the dynamic linker expects certain values here,
13916 and we must not disappoint it. */
13917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13918 if (IS_ELF
&& fixP
->fx_addsy
)
13919 switch (fixP
->fx_r_type
)
13921 case BFD_RELOC_386_PLT32
:
13922 case BFD_RELOC_X86_64_PLT32
:
13923 /* Make the jump instruction point to the address of the operand.
13924 At runtime we merely add the offset to the actual PLT entry.
13925 NB: Subtract the offset size only for jump instructions. */
13926 if (fixP
->fx_pcrel
)
13930 case BFD_RELOC_386_TLS_GD
:
13931 case BFD_RELOC_386_TLS_LDM
:
13932 case BFD_RELOC_386_TLS_IE_32
:
13933 case BFD_RELOC_386_TLS_IE
:
13934 case BFD_RELOC_386_TLS_GOTIE
:
13935 case BFD_RELOC_386_TLS_GOTDESC
:
13936 case BFD_RELOC_X86_64_TLSGD
:
13937 case BFD_RELOC_X86_64_TLSLD
:
13938 case BFD_RELOC_X86_64_GOTTPOFF
:
13939 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13940 value
= 0; /* Fully resolved at runtime. No addend. */
13942 case BFD_RELOC_386_TLS_LE
:
13943 case BFD_RELOC_386_TLS_LDO_32
:
13944 case BFD_RELOC_386_TLS_LE_32
:
13945 case BFD_RELOC_X86_64_DTPOFF32
:
13946 case BFD_RELOC_X86_64_DTPOFF64
:
13947 case BFD_RELOC_X86_64_TPOFF32
:
13948 case BFD_RELOC_X86_64_TPOFF64
:
13949 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13952 case BFD_RELOC_386_TLS_DESC_CALL
:
13953 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13954 value
= 0; /* Fully resolved at runtime. No addend. */
13955 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13959 case BFD_RELOC_VTABLE_INHERIT
:
13960 case BFD_RELOC_VTABLE_ENTRY
:
13967 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13969 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13971 value
= extend_to_32bit_address (value
);
13974 #endif /* !defined (TE_Mach) */
13976 /* Are we finished with this relocation now? */
13977 if (fixP
->fx_addsy
== NULL
)
13980 switch (fixP
->fx_r_type
)
13982 case BFD_RELOC_X86_64_32S
:
13983 fixP
->fx_signed
= 1;
13990 #if defined (OBJ_COFF) && defined (TE_PE)
13991 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13994 /* Remember value for tc_gen_reloc. */
13995 fixP
->fx_addnumber
= value
;
13996 /* Clear out the frag for now. */
14000 else if (use_rela_relocations
)
14002 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14003 fixP
->fx_no_overflow
= 1;
14004 /* Remember value for tc_gen_reloc. */
14005 fixP
->fx_addnumber
= value
;
14009 md_number_to_chars (p
, value
, fixP
->fx_size
);
14013 md_atof (int type
, char *litP
, int *sizeP
)
14015 /* This outputs the LITTLENUMs in REVERSE order;
14016 in accord with the bigendian 386. */
14017 return ieee_md_atof (type
, litP
, sizeP
, false);
14020 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14023 output_invalid (int c
)
14026 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14029 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14030 "(0x%x)", (unsigned char) c
);
14031 return output_invalid_buf
;
14034 /* Verify that @r can be used in the current context. */
14036 static bool check_register (const reg_entry
*r
)
14038 if (allow_pseudo_reg
)
14041 if (operand_type_all_zero (&r
->reg_type
))
14044 if ((r
->reg_type
.bitfield
.dword
14045 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14046 || r
->reg_type
.bitfield
.class == RegCR
14047 || r
->reg_type
.bitfield
.class == RegDR
)
14048 && !cpu_arch_flags
.bitfield
.cpui386
)
14051 if (r
->reg_type
.bitfield
.class == RegTR
14052 && (flag_code
== CODE_64BIT
14053 || !cpu_arch_flags
.bitfield
.cpui386
14054 || cpu_arch_isa_flags
.bitfield
.cpui586
14055 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14058 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14061 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14063 if (r
->reg_type
.bitfield
.zmmword
14064 || r
->reg_type
.bitfield
.class == RegMask
)
14067 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14069 if (r
->reg_type
.bitfield
.ymmword
)
14072 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14077 if (r
->reg_type
.bitfield
.zmmword
)
14079 if (vector_size
< VSZ512
)
14082 if (i
.vec_encoding
== vex_encoding_default
)
14083 i
.vec_encoding
= vex_encoding_evex512
;
14084 else if (i
.vec_encoding
!= vex_encoding_evex
14085 && i
.vec_encoding
!= vex_encoding_evex512
)
14086 i
.vec_encoding
= vex_encoding_error
;
14089 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14092 if (r
->reg_type
.bitfield
.tmmword
14093 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14094 || flag_code
!= CODE_64BIT
))
14097 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14100 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14101 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14104 /* Upper 16 vector registers are only available with VREX in 64bit
14105 mode, and require EVEX encoding. */
14106 if (r
->reg_flags
& RegVRex
)
14108 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14109 || flag_code
!= CODE_64BIT
)
14112 if (i
.vec_encoding
== vex_encoding_default
14113 || i
.vec_encoding
== vex_encoding_evex512
)
14114 i
.vec_encoding
= vex_encoding_evex
;
14115 else if (i
.vec_encoding
!= vex_encoding_evex
)
14116 i
.vec_encoding
= vex_encoding_error
;
14119 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14120 && (!cpu_arch_flags
.bitfield
.cpu64
14121 || r
->reg_type
.bitfield
.class != RegCR
14123 && flag_code
!= CODE_64BIT
)
14126 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14133 /* REG_STRING starts *before* REGISTER_PREFIX. */
14135 static const reg_entry
*
14136 parse_real_register (const char *reg_string
, char **end_op
)
14138 const char *s
= reg_string
;
14140 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14141 const reg_entry
*r
;
14143 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14144 if (*s
== REGISTER_PREFIX
)
14147 if (is_space_char (*s
))
14150 p
= reg_name_given
;
14151 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14153 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14154 return (const reg_entry
*) NULL
;
14158 if (is_part_of_name (*s
))
14159 return (const reg_entry
*) NULL
;
14161 *end_op
= (char *) s
;
14163 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14165 /* Handle floating point regs, allowing spaces in the (i) part. */
14168 if (!cpu_arch_flags
.bitfield
.cpu8087
14169 && !cpu_arch_flags
.bitfield
.cpu287
14170 && !cpu_arch_flags
.bitfield
.cpu387
14171 && !allow_pseudo_reg
)
14172 return (const reg_entry
*) NULL
;
14174 if (is_space_char (*s
))
14179 if (is_space_char (*s
))
14181 if (*s
>= '0' && *s
<= '7')
14183 int fpr
= *s
- '0';
14185 if (is_space_char (*s
))
14189 *end_op
= (char *) s
+ 1;
14190 know (r
[fpr
].reg_num
== fpr
);
14194 /* We have "%st(" then garbage. */
14195 return (const reg_entry
*) NULL
;
14199 return r
&& check_register (r
) ? r
: NULL
;
14202 /* REG_STRING starts *before* REGISTER_PREFIX. */
14204 static const reg_entry
*
14205 parse_register (const char *reg_string
, char **end_op
)
14207 const reg_entry
*r
;
14209 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14210 r
= parse_real_register (reg_string
, end_op
);
14215 char *save
= input_line_pointer
;
14216 char *buf
= xstrdup (reg_string
), *name
;
14219 input_line_pointer
= buf
;
14220 get_symbol_name (&name
);
14221 symbolP
= symbol_find (name
);
14222 while (symbolP
&& symbol_equated_p (symbolP
))
14224 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14226 if (e
->X_add_number
)
14228 symbolP
= e
->X_add_symbol
;
14230 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14232 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14234 if (e
->X_op
== O_register
)
14236 know (e
->X_add_number
>= 0
14237 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14238 r
= i386_regtab
+ e
->X_add_number
;
14239 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14241 if (r
&& !check_register (r
))
14243 as_bad (_("register '%s%s' cannot be used here"),
14244 register_prefix
, r
->reg_name
);
14248 input_line_pointer
= save
;
14255 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14257 const reg_entry
*r
= NULL
;
14258 char *end
= input_line_pointer
;
14260 /* We only know the terminating character here. It being double quote could
14261 be the closing one of a quoted symbol name, or an opening one from a
14262 following string (or another quoted symbol name). Since the latter can't
14263 be valid syntax for anything, bailing in either case is good enough. */
14264 if (*nextcharP
== '"')
14268 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14269 r
= parse_real_register (name
, &input_line_pointer
);
14270 if (r
&& end
<= input_line_pointer
)
14272 *nextcharP
= *input_line_pointer
;
14273 *input_line_pointer
= 0;
14274 e
->X_op
= O_register
;
14275 e
->X_add_number
= r
- i386_regtab
;
14278 input_line_pointer
= end
;
14280 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14284 md_operand (expressionS
*e
)
14287 const reg_entry
*r
;
14289 switch (*input_line_pointer
)
14291 case REGISTER_PREFIX
:
14292 r
= parse_real_register (input_line_pointer
, &end
);
14295 e
->X_op
= O_register
;
14296 e
->X_add_number
= r
- i386_regtab
;
14297 input_line_pointer
= end
;
14302 gas_assert (intel_syntax
);
14303 end
= input_line_pointer
++;
14305 if (*input_line_pointer
== ']')
14307 ++input_line_pointer
;
14308 e
->X_op_symbol
= make_expr_symbol (e
);
14309 e
->X_add_symbol
= NULL
;
14310 e
->X_add_number
= 0;
14315 e
->X_op
= O_absent
;
14316 input_line_pointer
= end
;
14323 /* To maintain consistency with !BFD64 builds of gas record, whether any
14324 (binary) operator was involved in an expression. As expressions are
14325 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14326 truncate results. */
14327 bool i386_record_operator (operatorT op
,
14328 const expressionS
*left
,
14329 const expressionS
*right
)
14331 if (op
== O_absent
)
14336 /* Since the expression parser applies unary operators fine to bignum
14337 operands, we don't need to be concerned of respective operands not
14338 fitting in 32 bits. */
14339 if (right
->X_op
== O_constant
&& right
->X_unsigned
14340 && !fits_in_unsigned_long (right
->X_add_number
))
14343 /* This isn't entirely right: The pattern can also result when constant
14344 expressions are folded (e.g. 0xffffffff + 1). */
14345 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14346 && !fits_in_unsigned_long (left
->X_add_number
))
14347 || (right
->X_op
== O_constant
&& right
->X_unsigned
14348 && !fits_in_unsigned_long (right
->X_add_number
)))
14349 expr_mode
= expr_large_value
;
14351 if (expr_mode
!= expr_large_value
)
14352 expr_mode
= expr_operator_present
;
14358 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14359 const char *md_shortopts
= "kVQ:sqnO::";
14361 const char *md_shortopts
= "qnO::";
14364 #define OPTION_32 (OPTION_MD_BASE + 0)
14365 #define OPTION_64 (OPTION_MD_BASE + 1)
14366 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14367 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14368 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14369 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14370 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14371 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14372 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14373 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14374 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14375 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14376 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14377 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14378 #define OPTION_X32 (OPTION_MD_BASE + 14)
14379 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14380 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14381 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14382 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14383 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14384 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14385 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14386 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14387 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14388 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14389 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14390 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14391 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14392 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14393 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14394 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14395 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14396 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14397 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14398 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14400 struct option md_longopts
[] =
14402 {"32", no_argument
, NULL
, OPTION_32
},
14403 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14404 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14405 {"64", no_argument
, NULL
, OPTION_64
},
14407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14408 {"x32", no_argument
, NULL
, OPTION_X32
},
14409 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14410 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14412 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14413 {"march", required_argument
, NULL
, OPTION_MARCH
},
14414 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14415 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14416 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14417 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14418 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14419 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14420 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14421 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14422 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14423 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14424 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14425 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14426 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14427 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14428 # if defined (TE_PE) || defined (TE_PEP)
14429 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14431 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14432 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14433 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14434 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14435 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14436 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14437 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14438 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14439 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14440 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14441 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14442 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14443 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14444 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14445 {NULL
, no_argument
, NULL
, 0}
14447 size_t md_longopts_size
= sizeof (md_longopts
);
14450 md_parse_option (int c
, const char *arg
)
14453 char *arch
, *next
, *saved
, *type
;
14458 optimize_align_code
= 0;
14462 quiet_warnings
= 1;
14465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14466 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14467 should be emitted or not. FIXME: Not implemented. */
14469 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14473 /* -V: SVR4 argument to print version ID. */
14475 print_version_id ();
14478 /* -k: Ignore for FreeBSD compatibility. */
14483 /* -s: On i386 Solaris, this tells the native assembler to use
14484 .stab instead of .stab.excl. We always use .stab anyhow. */
14487 case OPTION_MSHARED
:
14491 case OPTION_X86_USED_NOTE
:
14492 if (strcasecmp (arg
, "yes") == 0)
14494 else if (strcasecmp (arg
, "no") == 0)
14497 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14502 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14506 const char **list
, **l
;
14508 list
= bfd_target_list ();
14509 for (l
= list
; *l
!= NULL
; l
++)
14510 if (startswith (*l
, "elf64-x86-64")
14511 || strcmp (*l
, "coff-x86-64") == 0
14512 || strcmp (*l
, "pe-x86-64") == 0
14513 || strcmp (*l
, "pei-x86-64") == 0
14514 || strcmp (*l
, "mach-o-x86-64") == 0)
14516 default_arch
= "x86_64";
14520 as_fatal (_("no compiled in support for x86_64"));
14526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14530 const char **list
, **l
;
14532 list
= bfd_target_list ();
14533 for (l
= list
; *l
!= NULL
; l
++)
14534 if (startswith (*l
, "elf32-x86-64"))
14536 default_arch
= "x86_64:32";
14540 as_fatal (_("no compiled in support for 32bit x86_64"));
14544 as_fatal (_("32bit x86_64 is only supported for ELF"));
14550 const char **list
, **l
;
14552 list
= bfd_target_list ();
14553 for (l
= list
; *l
!= NULL
; l
++)
14554 if (strstr (*l
, "-i386")
14555 || strstr (*l
, "-go32"))
14557 default_arch
= "i386";
14561 as_fatal (_("no compiled in support for ix86"));
14566 case OPTION_DIVIDE
:
14567 #ifdef SVR4_COMMENT_CHARS
14572 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14574 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14578 i386_comment_chars
= n
;
14584 saved
= xstrdup (arg
);
14586 /* Allow -march=+nosse. */
14594 as_fatal (_("invalid -march= option: `%s'"), arg
);
14595 next
= strchr (arch
, '+');
14598 vsz
= strchr (arch
, '/');
14601 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14603 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14606 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14607 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14610 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14613 cpu_arch_name
= cpu_arch
[j
].name
;
14614 free (cpu_sub_arch_name
);
14615 cpu_sub_arch_name
= NULL
;
14616 cpu_arch_flags
= cpu_arch
[j
].enable
;
14617 cpu_arch_isa
= cpu_arch
[j
].type
;
14618 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14619 if (!cpu_arch_tune_set
)
14620 cpu_arch_tune
= cpu_arch_isa
;
14621 vector_size
= VSZ_DEFAULT
;
14624 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14625 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14626 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14628 /* ISA extension. */
14631 switch (cpu_arch
[j
].vsz
)
14640 unsigned long val
= strtoul (vsz
, &end
, 0);
14646 case 512: vector_size
= VSZ512
; break;
14647 case 256: vector_size
= VSZ256
; break;
14648 case 128: vector_size
= VSZ128
; break;
14650 as_warn (_("Unrecognized vector size specifier ignored"));
14655 /* Fall through. */
14657 vector_size
= VSZ_DEFAULT
;
14665 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14667 /* Disable an ISA extension. */
14668 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14669 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14670 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14673 if (cpu_arch
[j
].vsz
== vsz_set
)
14674 vector_size
= VSZ_DEFAULT
;
14679 if (j
>= ARRAY_SIZE (cpu_arch
))
14680 as_fatal (_("invalid -march= option: `%s'"), arg
);
14684 while (next
!= NULL
);
14690 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14691 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14693 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14694 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14696 cpu_arch_tune_set
= 1;
14697 cpu_arch_tune
= cpu_arch
[j
].type
;
14701 if (j
>= ARRAY_SIZE (cpu_arch
))
14702 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14705 case OPTION_MMNEMONIC
:
14706 if (strcasecmp (arg
, "att") == 0)
14707 intel_mnemonic
= 0;
14708 else if (strcasecmp (arg
, "intel") == 0)
14709 intel_mnemonic
= 1;
14711 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14714 case OPTION_MSYNTAX
:
14715 if (strcasecmp (arg
, "att") == 0)
14717 else if (strcasecmp (arg
, "intel") == 0)
14720 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14723 case OPTION_MINDEX_REG
:
14724 allow_index_reg
= 1;
14727 case OPTION_MNAKED_REG
:
14728 allow_naked_reg
= 1;
14731 case OPTION_MSSE2AVX
:
14735 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14736 use_unaligned_vector_move
= 1;
14739 case OPTION_MSSE_CHECK
:
14740 if (strcasecmp (arg
, "error") == 0)
14741 sse_check
= check_error
;
14742 else if (strcasecmp (arg
, "warning") == 0)
14743 sse_check
= check_warning
;
14744 else if (strcasecmp (arg
, "none") == 0)
14745 sse_check
= check_none
;
14747 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14750 case OPTION_MOPERAND_CHECK
:
14751 if (strcasecmp (arg
, "error") == 0)
14752 operand_check
= check_error
;
14753 else if (strcasecmp (arg
, "warning") == 0)
14754 operand_check
= check_warning
;
14755 else if (strcasecmp (arg
, "none") == 0)
14756 operand_check
= check_none
;
14758 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14761 case OPTION_MAVXSCALAR
:
14762 if (strcasecmp (arg
, "128") == 0)
14763 avxscalar
= vex128
;
14764 else if (strcasecmp (arg
, "256") == 0)
14765 avxscalar
= vex256
;
14767 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14770 case OPTION_MVEXWIG
:
14771 if (strcmp (arg
, "0") == 0)
14773 else if (strcmp (arg
, "1") == 0)
14776 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14779 case OPTION_MADD_BND_PREFIX
:
14780 add_bnd_prefix
= 1;
14783 case OPTION_MEVEXLIG
:
14784 if (strcmp (arg
, "128") == 0)
14785 evexlig
= evexl128
;
14786 else if (strcmp (arg
, "256") == 0)
14787 evexlig
= evexl256
;
14788 else if (strcmp (arg
, "512") == 0)
14789 evexlig
= evexl512
;
14791 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14794 case OPTION_MEVEXRCIG
:
14795 if (strcmp (arg
, "rne") == 0)
14797 else if (strcmp (arg
, "rd") == 0)
14799 else if (strcmp (arg
, "ru") == 0)
14801 else if (strcmp (arg
, "rz") == 0)
14804 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14807 case OPTION_MEVEXWIG
:
14808 if (strcmp (arg
, "0") == 0)
14810 else if (strcmp (arg
, "1") == 0)
14813 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14816 # if defined (TE_PE) || defined (TE_PEP)
14817 case OPTION_MBIG_OBJ
:
14822 case OPTION_MOMIT_LOCK_PREFIX
:
14823 if (strcasecmp (arg
, "yes") == 0)
14824 omit_lock_prefix
= 1;
14825 else if (strcasecmp (arg
, "no") == 0)
14826 omit_lock_prefix
= 0;
14828 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14831 case OPTION_MFENCE_AS_LOCK_ADD
:
14832 if (strcasecmp (arg
, "yes") == 0)
14834 else if (strcasecmp (arg
, "no") == 0)
14837 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14840 case OPTION_MLFENCE_AFTER_LOAD
:
14841 if (strcasecmp (arg
, "yes") == 0)
14842 lfence_after_load
= 1;
14843 else if (strcasecmp (arg
, "no") == 0)
14844 lfence_after_load
= 0;
14846 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14849 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14850 if (strcasecmp (arg
, "all") == 0)
14852 lfence_before_indirect_branch
= lfence_branch_all
;
14853 if (lfence_before_ret
== lfence_before_ret_none
)
14854 lfence_before_ret
= lfence_before_ret_shl
;
14856 else if (strcasecmp (arg
, "memory") == 0)
14857 lfence_before_indirect_branch
= lfence_branch_memory
;
14858 else if (strcasecmp (arg
, "register") == 0)
14859 lfence_before_indirect_branch
= lfence_branch_register
;
14860 else if (strcasecmp (arg
, "none") == 0)
14861 lfence_before_indirect_branch
= lfence_branch_none
;
14863 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14867 case OPTION_MLFENCE_BEFORE_RET
:
14868 if (strcasecmp (arg
, "or") == 0)
14869 lfence_before_ret
= lfence_before_ret_or
;
14870 else if (strcasecmp (arg
, "not") == 0)
14871 lfence_before_ret
= lfence_before_ret_not
;
14872 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14873 lfence_before_ret
= lfence_before_ret_shl
;
14874 else if (strcasecmp (arg
, "none") == 0)
14875 lfence_before_ret
= lfence_before_ret_none
;
14877 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14881 case OPTION_MRELAX_RELOCATIONS
:
14882 if (strcasecmp (arg
, "yes") == 0)
14883 generate_relax_relocations
= 1;
14884 else if (strcasecmp (arg
, "no") == 0)
14885 generate_relax_relocations
= 0;
14887 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14890 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14893 long int align
= strtoul (arg
, &end
, 0);
14898 align_branch_power
= 0;
14901 else if (align
>= 16)
14904 for (align_power
= 0;
14906 align
>>= 1, align_power
++)
14908 /* Limit alignment power to 31. */
14909 if (align
== 1 && align_power
< 32)
14911 align_branch_power
= align_power
;
14916 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14920 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14923 int align
= strtoul (arg
, &end
, 0);
14924 /* Some processors only support 5 prefixes. */
14925 if (*end
== '\0' && align
>= 0 && align
< 6)
14927 align_branch_prefix_size
= align
;
14930 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14935 case OPTION_MALIGN_BRANCH
:
14937 saved
= xstrdup (arg
);
14941 next
= strchr (type
, '+');
14944 if (strcasecmp (type
, "jcc") == 0)
14945 align_branch
|= align_branch_jcc_bit
;
14946 else if (strcasecmp (type
, "fused") == 0)
14947 align_branch
|= align_branch_fused_bit
;
14948 else if (strcasecmp (type
, "jmp") == 0)
14949 align_branch
|= align_branch_jmp_bit
;
14950 else if (strcasecmp (type
, "call") == 0)
14951 align_branch
|= align_branch_call_bit
;
14952 else if (strcasecmp (type
, "ret") == 0)
14953 align_branch
|= align_branch_ret_bit
;
14954 else if (strcasecmp (type
, "indirect") == 0)
14955 align_branch
|= align_branch_indirect_bit
;
14957 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14960 while (next
!= NULL
);
14964 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14965 align_branch_power
= 5;
14966 align_branch_prefix_size
= 5;
14967 align_branch
= (align_branch_jcc_bit
14968 | align_branch_fused_bit
14969 | align_branch_jmp_bit
);
14972 case OPTION_MAMD64
:
14976 case OPTION_MINTEL64
:
14984 /* Turn off -Os. */
14985 optimize_for_space
= 0;
14987 else if (*arg
== 's')
14989 optimize_for_space
= 1;
14990 /* Turn on all encoding optimizations. */
14991 optimize
= INT_MAX
;
14995 optimize
= atoi (arg
);
14996 /* Turn off -Os. */
14997 optimize_for_space
= 0;
15007 #define MESSAGE_TEMPLATE \
15011 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15012 int *left_p
, const char *name
, int len
)
15014 int size
= sizeof (MESSAGE_TEMPLATE
);
15015 int left
= *left_p
;
15017 /* Reserve 2 spaces for ", " or ",\0" */
15020 /* Check if there is any room. */
15028 p
= mempcpy (p
, name
, len
);
15032 /* Output the current message now and start a new one. */
15035 fprintf (stream
, "%s\n", message
);
15037 left
= size
- (start
- message
) - len
- 2;
15039 gas_assert (left
>= 0);
15041 p
= mempcpy (p
, name
, len
);
15049 show_arch (FILE *stream
, int ext
, int check
)
15051 static char message
[] = MESSAGE_TEMPLATE
;
15052 char *start
= message
+ 27;
15054 int size
= sizeof (MESSAGE_TEMPLATE
);
15061 left
= size
- (start
- message
);
15065 p
= output_message (stream
, p
, message
, start
, &left
,
15066 STRING_COMMA_LEN ("default"));
15067 p
= output_message (stream
, p
, message
, start
, &left
,
15068 STRING_COMMA_LEN ("push"));
15069 p
= output_message (stream
, p
, message
, start
, &left
,
15070 STRING_COMMA_LEN ("pop"));
15073 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15075 /* Should it be skipped? */
15076 if (cpu_arch
[j
].skip
)
15079 name
= cpu_arch
[j
].name
;
15080 len
= cpu_arch
[j
].len
;
15081 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15083 /* It is an extension. Skip if we aren't asked to show it. */
15084 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15089 /* It is an processor. Skip if we show only extension. */
15092 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15094 /* It is an impossible processor - skip. */
15098 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15101 /* Display disabled extensions. */
15103 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15107 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15108 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15110 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15111 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15117 fprintf (stream
, "%s\n", message
);
15121 md_show_usage (FILE *stream
)
15123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15124 fprintf (stream
, _("\
15125 -Qy, -Qn ignored\n\
15126 -V print assembler version number\n\
15129 fprintf (stream
, _("\
15130 -n do not optimize code alignment\n\
15131 -O{012s} attempt some code optimizations\n\
15132 -q quieten some warnings\n"));
15133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15134 fprintf (stream
, _("\
15138 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15139 fprintf (stream
, _("\
15140 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15141 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15142 fprintf (stream
, _("\
15143 --32/--64 generate 32bit/64bit object\n"));
15146 #ifdef SVR4_COMMENT_CHARS
15147 fprintf (stream
, _("\
15148 --divide do not treat `/' as a comment character\n"));
15150 fprintf (stream
, _("\
15151 --divide ignored\n"));
15153 fprintf (stream
, _("\
15154 -march=CPU[,+EXTENSION...]\n\
15155 generate code for CPU and EXTENSION, CPU is one of:\n"));
15156 show_arch (stream
, 0, 1);
15157 fprintf (stream
, _("\
15158 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15159 show_arch (stream
, 1, 0);
15160 fprintf (stream
, _("\
15161 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15162 show_arch (stream
, 0, 0);
15163 fprintf (stream
, _("\
15164 -msse2avx encode SSE instructions with VEX prefix\n"));
15165 fprintf (stream
, _("\
15166 -muse-unaligned-vector-move\n\
15167 encode aligned vector move as unaligned vector move\n"));
15168 fprintf (stream
, _("\
15169 -msse-check=[none|error|warning] (default: warning)\n\
15170 check SSE instructions\n"));
15171 fprintf (stream
, _("\
15172 -moperand-check=[none|error|warning] (default: warning)\n\
15173 check operand combinations for validity\n"));
15174 fprintf (stream
, _("\
15175 -mavxscalar=[128|256] (default: 128)\n\
15176 encode scalar AVX instructions with specific vector\n\
15178 fprintf (stream
, _("\
15179 -mvexwig=[0|1] (default: 0)\n\
15180 encode VEX instructions with specific VEX.W value\n\
15181 for VEX.W bit ignored instructions\n"));
15182 fprintf (stream
, _("\
15183 -mevexlig=[128|256|512] (default: 128)\n\
15184 encode scalar EVEX instructions with specific vector\n\
15186 fprintf (stream
, _("\
15187 -mevexwig=[0|1] (default: 0)\n\
15188 encode EVEX instructions with specific EVEX.W value\n\
15189 for EVEX.W bit ignored instructions\n"));
15190 fprintf (stream
, _("\
15191 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15192 encode EVEX instructions with specific EVEX.RC value\n\
15193 for SAE-only ignored instructions\n"));
15194 fprintf (stream
, _("\
15195 -mmnemonic=[att|intel] "));
15196 if (SYSV386_COMPAT
)
15197 fprintf (stream
, _("(default: att)\n"));
15199 fprintf (stream
, _("(default: intel)\n"));
15200 fprintf (stream
, _("\
15201 use AT&T/Intel mnemonic\n"));
15202 fprintf (stream
, _("\
15203 -msyntax=[att|intel] (default: att)\n\
15204 use AT&T/Intel syntax\n"));
15205 fprintf (stream
, _("\
15206 -mindex-reg support pseudo index registers\n"));
15207 fprintf (stream
, _("\
15208 -mnaked-reg don't require `%%' prefix for registers\n"));
15209 fprintf (stream
, _("\
15210 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15212 fprintf (stream
, _("\
15213 -mshared disable branch optimization for shared code\n"));
15214 fprintf (stream
, _("\
15215 -mx86-used-note=[no|yes] "));
15216 if (DEFAULT_X86_USED_NOTE
)
15217 fprintf (stream
, _("(default: yes)\n"));
15219 fprintf (stream
, _("(default: no)\n"));
15220 fprintf (stream
, _("\
15221 generate x86 used ISA and feature properties\n"));
15223 #if defined (TE_PE) || defined (TE_PEP)
15224 fprintf (stream
, _("\
15225 -mbig-obj generate big object files\n"));
15227 fprintf (stream
, _("\
15228 -momit-lock-prefix=[no|yes] (default: no)\n\
15229 strip all lock prefixes\n"));
15230 fprintf (stream
, _("\
15231 -mfence-as-lock-add=[no|yes] (default: no)\n\
15232 encode lfence, mfence and sfence as\n\
15233 lock addl $0x0, (%%{re}sp)\n"));
15234 fprintf (stream
, _("\
15235 -mrelax-relocations=[no|yes] "));
15236 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15237 fprintf (stream
, _("(default: yes)\n"));
15239 fprintf (stream
, _("(default: no)\n"));
15240 fprintf (stream
, _("\
15241 generate relax relocations\n"));
15242 fprintf (stream
, _("\
15243 -malign-branch-boundary=NUM (default: 0)\n\
15244 align branches within NUM byte boundary\n"));
15245 fprintf (stream
, _("\
15246 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15247 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15249 specify types of branches to align\n"));
15250 fprintf (stream
, _("\
15251 -malign-branch-prefix-size=NUM (default: 5)\n\
15252 align branches with NUM prefixes per instruction\n"));
15253 fprintf (stream
, _("\
15254 -mbranches-within-32B-boundaries\n\
15255 align branches within 32 byte boundary\n"));
15256 fprintf (stream
, _("\
15257 -mlfence-after-load=[no|yes] (default: no)\n\
15258 generate lfence after load\n"));
15259 fprintf (stream
, _("\
15260 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15261 generate lfence before indirect near branch\n"));
15262 fprintf (stream
, _("\
15263 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15264 generate lfence before ret\n"));
15265 fprintf (stream
, _("\
15266 -mamd64 accept only AMD64 ISA [default]\n"));
15267 fprintf (stream
, _("\
15268 -mintel64 accept only Intel64 ISA\n"));
15271 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15272 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15273 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15275 /* Pick the target format to use. */
15278 i386_target_format (void)
15280 if (startswith (default_arch
, "x86_64"))
15282 update_code_flag (CODE_64BIT
, 1);
15283 if (default_arch
[6] == '\0')
15284 x86_elf_abi
= X86_64_ABI
;
15286 x86_elf_abi
= X86_64_X32_ABI
;
15288 else if (!strcmp (default_arch
, "i386"))
15289 update_code_flag (CODE_32BIT
, 1);
15290 else if (!strcmp (default_arch
, "iamcu"))
15292 update_code_flag (CODE_32BIT
, 1);
15293 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15295 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15296 cpu_arch_name
= "iamcu";
15297 free (cpu_sub_arch_name
);
15298 cpu_sub_arch_name
= NULL
;
15299 cpu_arch_flags
= iamcu_flags
;
15300 cpu_arch_isa
= PROCESSOR_IAMCU
;
15301 cpu_arch_isa_flags
= iamcu_flags
;
15302 if (!cpu_arch_tune_set
)
15303 cpu_arch_tune
= PROCESSOR_IAMCU
;
15305 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15306 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15310 as_fatal (_("unknown architecture"));
15312 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15313 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15315 switch (OUTPUT_FLAVOR
)
15317 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15318 case bfd_target_aout_flavour
:
15319 return AOUT_TARGET_FORMAT
;
15321 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15322 # if defined (TE_PE) || defined (TE_PEP)
15323 case bfd_target_coff_flavour
:
15324 if (flag_code
== CODE_64BIT
)
15327 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15329 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15330 # elif defined (TE_GO32)
15331 case bfd_target_coff_flavour
:
15332 return "coff-go32";
15334 case bfd_target_coff_flavour
:
15335 return "coff-i386";
15338 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15339 case bfd_target_elf_flavour
:
15341 const char *format
;
15343 switch (x86_elf_abi
)
15346 format
= ELF_TARGET_FORMAT
;
15348 tls_get_addr
= "___tls_get_addr";
15352 use_rela_relocations
= 1;
15355 tls_get_addr
= "__tls_get_addr";
15357 format
= ELF_TARGET_FORMAT64
;
15359 case X86_64_X32_ABI
:
15360 use_rela_relocations
= 1;
15363 tls_get_addr
= "__tls_get_addr";
15365 disallow_64bit_reloc
= 1;
15366 format
= ELF_TARGET_FORMAT32
;
15369 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15371 if (x86_elf_abi
!= I386_ABI
)
15372 as_fatal (_("Intel MCU is 32bit only"));
15373 return ELF_TARGET_IAMCU_FORMAT
;
15379 #if defined (OBJ_MACH_O)
15380 case bfd_target_mach_o_flavour
:
15381 if (flag_code
== CODE_64BIT
)
15383 use_rela_relocations
= 1;
15385 return "mach-o-x86-64";
15388 return "mach-o-i386";
15396 #endif /* OBJ_MAYBE_ more than one */
15399 md_undefined_symbol (char *name
)
15401 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15402 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15403 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15404 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15408 if (symbol_find (name
))
15409 as_bad (_("GOT already in symbol table"));
15410 GOT_symbol
= symbol_new (name
, undefined_section
,
15411 &zero_address_frag
, 0);
15418 /* Round up a section size to the appropriate boundary. */
15421 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15423 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15424 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15426 /* For a.out, force the section size to be aligned. If we don't do
15427 this, BFD will align it for us, but it will not write out the
15428 final bytes of the section. This may be a bug in BFD, but it is
15429 easier to fix it here since that is how the other a.out targets
15433 align
= bfd_section_alignment (segment
);
15434 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15441 /* On the i386, PC-relative offsets are relative to the start of the
15442 next instruction. That is, the address of the offset, plus its
15443 size, since the offset is always the last part of the insn. */
15446 md_pcrel_from (fixS
*fixP
)
15448 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15454 s_bss (int ignore ATTRIBUTE_UNUSED
)
15458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15460 obj_elf_section_change_hook ();
15462 temp
= get_absolute_expression ();
15463 subseg_set (bss_section
, (subsegT
) temp
);
15464 demand_empty_rest_of_line ();
15469 /* Remember constant directive. */
15472 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15474 if (last_insn
.kind
!= last_insn_directive
15475 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15477 last_insn
.seg
= now_seg
;
15478 last_insn
.kind
= last_insn_directive
;
15479 last_insn
.name
= "constant directive";
15480 last_insn
.file
= as_where (&last_insn
.line
);
15481 if (lfence_before_ret
!= lfence_before_ret_none
)
15483 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15484 as_warn (_("constant directive skips -mlfence-before-ret "
15485 "and -mlfence-before-indirect-branch"));
15487 as_warn (_("constant directive skips -mlfence-before-ret"));
15489 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15490 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15495 i386_validate_fix (fixS
*fixp
)
15497 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15499 reloc_howto_type
*howto
;
15501 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15502 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15503 _("invalid %s relocation against register"),
15504 howto
? howto
->name
: "<unknown>");
15508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15509 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15510 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15511 return IS_ELF
&& fixp
->fx_addsy
15512 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15513 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15516 if (fixp
->fx_subsy
)
15518 if (fixp
->fx_subsy
== GOT_symbol
)
15520 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15525 if (fixp
->fx_tcbit2
)
15526 fixp
->fx_r_type
= (fixp
->fx_tcbit
15527 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15528 : BFD_RELOC_X86_64_GOTPCRELX
);
15531 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15536 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15538 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15540 fixp
->fx_subsy
= 0;
15543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15546 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15547 to section. Since PLT32 relocation must be against symbols,
15548 turn such PLT32 relocation into PC32 relocation. */
15550 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15551 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15552 && symbol_section_p (fixp
->fx_addsy
))
15553 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15556 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15557 && fixp
->fx_tcbit2
)
15558 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15567 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15570 bfd_reloc_code_real_type code
;
15572 switch (fixp
->fx_r_type
)
15574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15577 case BFD_RELOC_SIZE32
:
15578 case BFD_RELOC_SIZE64
:
15580 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15581 && (!fixp
->fx_subsy
15582 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15583 sym
= fixp
->fx_addsy
;
15584 else if (fixp
->fx_subsy
15585 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15586 && (!fixp
->fx_addsy
15587 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15588 sym
= fixp
->fx_subsy
;
15591 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15593 /* Resolve size relocation against local symbol to size of
15594 the symbol plus addend. */
15595 valueT value
= S_GET_SIZE (sym
);
15597 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15598 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15599 if (sym
== fixp
->fx_subsy
)
15602 if (fixp
->fx_addsy
)
15603 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15605 else if (fixp
->fx_subsy
)
15606 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15607 value
+= fixp
->fx_offset
;
15608 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15610 && !fits_in_unsigned_long (value
))
15611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15612 _("symbol size computation overflow"));
15613 fixp
->fx_addsy
= NULL
;
15614 fixp
->fx_subsy
= NULL
;
15615 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15618 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15620 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15621 "unsupported expression involving @size");
15625 /* Fall through. */
15627 case BFD_RELOC_X86_64_PLT32
:
15628 case BFD_RELOC_X86_64_GOT32
:
15629 case BFD_RELOC_X86_64_GOTPCREL
:
15630 case BFD_RELOC_X86_64_GOTPCRELX
:
15631 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15632 case BFD_RELOC_386_PLT32
:
15633 case BFD_RELOC_386_GOT32
:
15634 case BFD_RELOC_386_GOT32X
:
15635 case BFD_RELOC_386_GOTOFF
:
15636 case BFD_RELOC_386_GOTPC
:
15637 case BFD_RELOC_386_TLS_GD
:
15638 case BFD_RELOC_386_TLS_LDM
:
15639 case BFD_RELOC_386_TLS_LDO_32
:
15640 case BFD_RELOC_386_TLS_IE_32
:
15641 case BFD_RELOC_386_TLS_IE
:
15642 case BFD_RELOC_386_TLS_GOTIE
:
15643 case BFD_RELOC_386_TLS_LE_32
:
15644 case BFD_RELOC_386_TLS_LE
:
15645 case BFD_RELOC_386_TLS_GOTDESC
:
15646 case BFD_RELOC_386_TLS_DESC_CALL
:
15647 case BFD_RELOC_X86_64_TLSGD
:
15648 case BFD_RELOC_X86_64_TLSLD
:
15649 case BFD_RELOC_X86_64_DTPOFF32
:
15650 case BFD_RELOC_X86_64_DTPOFF64
:
15651 case BFD_RELOC_X86_64_GOTTPOFF
:
15652 case BFD_RELOC_X86_64_TPOFF32
:
15653 case BFD_RELOC_X86_64_TPOFF64
:
15654 case BFD_RELOC_X86_64_GOTOFF64
:
15655 case BFD_RELOC_X86_64_GOTPC32
:
15656 case BFD_RELOC_X86_64_GOT64
:
15657 case BFD_RELOC_X86_64_GOTPCREL64
:
15658 case BFD_RELOC_X86_64_GOTPC64
:
15659 case BFD_RELOC_X86_64_GOTPLT64
:
15660 case BFD_RELOC_X86_64_PLTOFF64
:
15661 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15662 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15663 case BFD_RELOC_RVA
:
15664 case BFD_RELOC_VTABLE_ENTRY
:
15665 case BFD_RELOC_VTABLE_INHERIT
:
15667 case BFD_RELOC_32_SECREL
:
15668 case BFD_RELOC_16_SECIDX
:
15670 code
= fixp
->fx_r_type
;
15672 case BFD_RELOC_X86_64_32S
:
15673 if (!fixp
->fx_pcrel
)
15675 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15676 code
= fixp
->fx_r_type
;
15679 /* Fall through. */
15681 if (fixp
->fx_pcrel
)
15683 switch (fixp
->fx_size
)
15686 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15687 _("can not do %d byte pc-relative relocation"),
15689 code
= BFD_RELOC_32_PCREL
;
15691 case 1: code
= BFD_RELOC_8_PCREL
; break;
15692 case 2: code
= BFD_RELOC_16_PCREL
; break;
15693 case 4: code
= BFD_RELOC_32_PCREL
; break;
15695 case 8: code
= BFD_RELOC_64_PCREL
; break;
15701 switch (fixp
->fx_size
)
15704 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15705 _("can not do %d byte relocation"),
15707 code
= BFD_RELOC_32
;
15709 case 1: code
= BFD_RELOC_8
; break;
15710 case 2: code
= BFD_RELOC_16
; break;
15711 case 4: code
= BFD_RELOC_32
; break;
15713 case 8: code
= BFD_RELOC_64
; break;
15720 if ((code
== BFD_RELOC_32
15721 || code
== BFD_RELOC_32_PCREL
15722 || code
== BFD_RELOC_X86_64_32S
)
15724 && fixp
->fx_addsy
== GOT_symbol
)
15727 code
= BFD_RELOC_386_GOTPC
;
15729 code
= BFD_RELOC_X86_64_GOTPC32
;
15731 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15733 && fixp
->fx_addsy
== GOT_symbol
)
15735 code
= BFD_RELOC_X86_64_GOTPC64
;
15738 rel
= XNEW (arelent
);
15739 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15740 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15742 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15744 if (!use_rela_relocations
)
15746 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15747 vtable entry to be used in the relocation's section offset. */
15748 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15749 rel
->address
= fixp
->fx_offset
;
15750 #if defined (OBJ_COFF) && defined (TE_PE)
15751 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15752 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15757 /* Use the rela in 64bit mode. */
15760 if (disallow_64bit_reloc
)
15763 case BFD_RELOC_X86_64_DTPOFF64
:
15764 case BFD_RELOC_X86_64_TPOFF64
:
15765 case BFD_RELOC_64_PCREL
:
15766 case BFD_RELOC_X86_64_GOTOFF64
:
15767 case BFD_RELOC_X86_64_GOT64
:
15768 case BFD_RELOC_X86_64_GOTPCREL64
:
15769 case BFD_RELOC_X86_64_GOTPC64
:
15770 case BFD_RELOC_X86_64_GOTPLT64
:
15771 case BFD_RELOC_X86_64_PLTOFF64
:
15772 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15773 _("cannot represent relocation type %s in x32 mode"),
15774 bfd_get_reloc_code_name (code
));
15780 if (!fixp
->fx_pcrel
)
15781 rel
->addend
= fixp
->fx_offset
;
15785 case BFD_RELOC_X86_64_PLT32
:
15786 case BFD_RELOC_X86_64_GOT32
:
15787 case BFD_RELOC_X86_64_GOTPCREL
:
15788 case BFD_RELOC_X86_64_GOTPCRELX
:
15789 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15790 case BFD_RELOC_X86_64_TLSGD
:
15791 case BFD_RELOC_X86_64_TLSLD
:
15792 case BFD_RELOC_X86_64_GOTTPOFF
:
15793 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15794 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15795 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15798 rel
->addend
= (section
->vma
15800 + fixp
->fx_addnumber
15801 + md_pcrel_from (fixp
));
15806 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15807 if (rel
->howto
== NULL
)
15809 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15810 _("cannot represent relocation type %s"),
15811 bfd_get_reloc_code_name (code
));
15812 /* Set howto to a garbage value so that we can keep going. */
15813 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15814 gas_assert (rel
->howto
!= NULL
);
15820 #include "tc-i386-intel.c"
15823 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15825 int saved_naked_reg
;
15826 char saved_register_dot
;
15828 saved_naked_reg
= allow_naked_reg
;
15829 allow_naked_reg
= 1;
15830 saved_register_dot
= register_chars
['.'];
15831 register_chars
['.'] = '.';
15832 allow_pseudo_reg
= 1;
15833 expression_and_evaluate (exp
);
15834 allow_pseudo_reg
= 0;
15835 register_chars
['.'] = saved_register_dot
;
15836 allow_naked_reg
= saved_naked_reg
;
15838 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15840 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15842 exp
->X_op
= O_constant
;
15843 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15844 .dw2_regnum
[flag_code
>> 1];
15847 exp
->X_op
= O_illegal
;
15852 tc_x86_frame_initial_instructions (void)
15854 static unsigned int sp_regno
[2];
15856 if (!sp_regno
[flag_code
>> 1])
15858 char *saved_input
= input_line_pointer
;
15859 char sp
[][4] = {"esp", "rsp"};
15862 input_line_pointer
= sp
[flag_code
>> 1];
15863 tc_x86_parse_to_dw2regnum (&exp
);
15864 gas_assert (exp
.X_op
== O_constant
);
15865 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15866 input_line_pointer
= saved_input
;
15869 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15870 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15874 x86_dwarf2_addr_size (void)
15876 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15877 if (x86_elf_abi
== X86_64_X32_ABI
)
15880 return bfd_arch_bits_per_address (stdoutput
) / 8;
15884 i386_elf_section_type (const char *str
, size_t len
)
15886 if (flag_code
== CODE_64BIT
15887 && len
== sizeof ("unwind") - 1
15888 && startswith (str
, "unwind"))
15889 return SHT_X86_64_UNWIND
;
15896 i386_solaris_fix_up_eh_frame (segT sec
)
15898 if (flag_code
== CODE_64BIT
)
15899 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15905 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15909 exp
.X_op
= O_secrel
;
15910 exp
.X_add_symbol
= symbol
;
15911 exp
.X_add_number
= 0;
15912 emit_expr (&exp
, size
);
15916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15917 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15920 x86_64_section_letter (int letter
, const char **ptr_msg
)
15922 if (flag_code
== CODE_64BIT
)
15925 return SHF_X86_64_LARGE
;
15927 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15930 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15935 handle_large_common (int small ATTRIBUTE_UNUSED
)
15937 if (flag_code
!= CODE_64BIT
)
15939 s_comm_internal (0, elf_common_parse
);
15940 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15944 static segT lbss_section
;
15945 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15946 asection
*saved_bss_section
= bss_section
;
15948 if (lbss_section
== NULL
)
15950 flagword applicable
;
15951 segT seg
= now_seg
;
15952 subsegT subseg
= now_subseg
;
15954 /* The .lbss section is for local .largecomm symbols. */
15955 lbss_section
= subseg_new (".lbss", 0);
15956 applicable
= bfd_applicable_section_flags (stdoutput
);
15957 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15958 seg_info (lbss_section
)->bss
= 1;
15960 subseg_set (seg
, subseg
);
15963 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15964 bss_section
= lbss_section
;
15966 s_comm_internal (0, elf_common_parse
);
15968 elf_com_section_ptr
= saved_com_section_ptr
;
15969 bss_section
= saved_bss_section
;
15972 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */