1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
66 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
67 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
69 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
71 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
72 static int smallest_imm_type
PARAMS ((offsetT
));
73 static offsetT offset_in_range
PARAMS ((offsetT
, int));
74 static int add_prefix
PARAMS ((unsigned int));
75 static void set_code_flag
PARAMS ((int));
76 static void set_16bit_gcc_code_flag
PARAMS ((int));
77 static void set_intel_syntax
PARAMS ((int));
78 static void set_cpu_arch
PARAMS ((int));
80 static void pe_directive_secrel
PARAMS ((int));
82 static char *output_invalid
PARAMS ((int c
));
83 static int i386_operand
PARAMS ((char *operand_string
));
84 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
85 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
87 static char *parse_insn
PARAMS ((char *, char *));
88 static char *parse_operands
PARAMS ((char *, const char *));
89 static void swap_operands
PARAMS ((void));
90 static void optimize_imm
PARAMS ((void));
91 static void optimize_disp
PARAMS ((void));
92 static int match_template
PARAMS ((void));
93 static int check_string
PARAMS ((void));
94 static int process_suffix
PARAMS ((void));
95 static int check_byte_reg
PARAMS ((void));
96 static int check_long_reg
PARAMS ((void));
97 static int check_qword_reg
PARAMS ((void));
98 static int check_word_reg
PARAMS ((void));
99 static int finalize_imm
PARAMS ((void));
100 static int process_operands
PARAMS ((void));
101 static const seg_entry
*build_modrm_byte
PARAMS ((void));
102 static void output_insn
PARAMS ((void));
103 static void output_branch
PARAMS ((void));
104 static void output_jump
PARAMS ((void));
105 static void output_interseg_jump
PARAMS ((void));
106 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
107 offsetT insn_start_off
));
108 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
111 static void s_bss
PARAMS ((int));
114 static const char *default_arch
= DEFAULT_ARCH
;
116 /* 'md_assemble ()' gathers together information and puts it into a
123 const reg_entry
*regs
;
128 /* TM holds the template for the insn were currently assembling. */
131 /* SUFFIX holds the instruction mnemonic suffix if given.
132 (e.g. 'l' for 'movl') */
135 /* OPERANDS gives the number of given operands. */
136 unsigned int operands
;
138 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
139 of given register, displacement, memory operands and immediate
141 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
143 /* TYPES [i] is the type (see above #defines) which tells us how to
144 use OP[i] for the corresponding operand. */
145 unsigned int types
[MAX_OPERANDS
];
147 /* Displacement expression, immediate expression, or register for each
149 union i386_op op
[MAX_OPERANDS
];
151 /* Flags for operands. */
152 unsigned int flags
[MAX_OPERANDS
];
153 #define Operand_PCrel 1
155 /* Relocation type for operand */
156 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
158 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
159 the base index byte below. */
160 const reg_entry
*base_reg
;
161 const reg_entry
*index_reg
;
162 unsigned int log2_scale_factor
;
164 /* SEG gives the seg_entries of this insn. They are zero unless
165 explicit segment overrides are given. */
166 const seg_entry
*seg
[2];
168 /* PREFIX holds all the given prefix opcodes (usually null).
169 PREFIXES is the number of prefix opcodes. */
170 unsigned int prefixes
;
171 unsigned char prefix
[MAX_PREFIXES
];
173 /* RM and SIB are the modrm byte and the sib byte where the
174 addressing modes of this insn are encoded. */
181 typedef struct _i386_insn i386_insn
;
183 /* List of chars besides those in app.c:symbol_chars that can start an
184 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars
[] = "*%-(["
194 #if (defined (TE_I386AIX) \
195 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
196 && !defined (TE_LINUX) \
197 && !defined (TE_NETWARE) \
198 && !defined (TE_FreeBSD) \
199 && !defined (TE_NetBSD)))
200 /* This array holds the chars that always start a comment. If the
201 pre-processor is disabled, these aren't very useful. */
202 const char comment_chars
[] = "#/";
203 #define PREFIX_SEPARATOR '\\'
205 /* This array holds the chars that only start a comment at the beginning of
206 a line. If the line seems to have the form '# 123 filename'
207 .line and .file directives will appear in the pre-processed output.
208 Note that input_file.c hand checks for '#' at the beginning of the
209 first line of the input file. This is because the compiler outputs
210 #NO_APP at the beginning of its output.
211 Also note that comments started like this one will always work if
212 '/' isn't otherwise defined. */
213 const char line_comment_chars
[] = "#";
216 /* Putting '/' here makes it impossible to use the divide operator.
217 However, we need it for compatibility with SVR4 systems. */
218 const char comment_chars
[] = "#";
219 #define PREFIX_SEPARATOR '/'
221 const char line_comment_chars
[] = "/#";
224 const char line_separator_chars
[] = ";";
226 /* Chars that can be used to separate mant from exp in floating point
228 const char EXP_CHARS
[] = "eE";
230 /* Chars that mean this number is a floating point constant
233 const char FLT_CHARS
[] = "fFdDxX";
235 /* Tables for lexical analysis. */
236 static char mnemonic_chars
[256];
237 static char register_chars
[256];
238 static char operand_chars
[256];
239 static char identifier_chars
[256];
240 static char digit_chars
[256];
242 /* Lexical macros. */
243 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
244 #define is_operand_char(x) (operand_chars[(unsigned char) x])
245 #define is_register_char(x) (register_chars[(unsigned char) x])
246 #define is_space_char(x) ((x) == ' ')
247 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
248 #define is_digit_char(x) (digit_chars[(unsigned char) x])
250 /* All non-digit non-letter characters that may occur in an operand. */
251 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
253 /* md_assemble() always leaves the strings it's passed unaltered. To
254 effect this we maintain a stack of saved characters that we've smashed
255 with '\0's (indicating end of strings for various sub-fields of the
256 assembler instruction). */
257 static char save_stack
[32];
258 static char *save_stack_p
;
259 #define END_STRING_AND_SAVE(s) \
260 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
261 #define RESTORE_END_STRING(s) \
262 do { *(s) = *--save_stack_p; } while (0)
264 /* The instruction we're assembling. */
267 /* Possible templates for current insn. */
268 static const templates
*current_templates
;
270 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
271 static expressionS disp_expressions
[2], im_expressions
[2];
273 /* Current operand we are working on. */
274 static int this_operand
;
276 /* We support four different modes. FLAG_CODE variable is used to distinguish
283 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
285 static enum flag_code flag_code
;
286 static int use_rela_relocations
= 0;
288 /* The names used to print error messages. */
289 static const char *flag_code_names
[] =
296 /* 1 for intel syntax,
298 static int intel_syntax
= 0;
300 /* 1 if register prefix % not required. */
301 static int allow_naked_reg
= 0;
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size
= '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code
= 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings
= 0;
315 static const char *cpu_arch_name
= NULL
;
317 /* CPU feature flags. */
318 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
320 /* If set, conditional jumps are not automatically promoted to handle
321 larger than a byte offset. */
322 static unsigned int no_cond_jump_promotion
= 0;
324 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
328 unsigned int x86_dwarf2_return_column
;
330 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
331 int x86_cie_data_alignment
;
333 /* Interface to relax_segment.
334 There are 3 major relax states for 386 jump insns because the
335 different types of jumps add different sizes to frags when we're
336 figuring out what sort of jump to choose to reach a given label. */
339 #define UNCOND_JUMP 0
341 #define COND_JUMP86 2
346 #define SMALL16 (SMALL | CODE16)
348 #define BIG16 (BIG | CODE16)
352 #define INLINE __inline__
358 #define ENCODE_RELAX_STATE(type, size) \
359 ((relax_substateT) (((type) << 2) | (size)))
360 #define TYPE_FROM_RELAX_STATE(s) \
362 #define DISP_SIZE_FROM_RELAX_STATE(s) \
363 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
365 /* This table is used by relax_frag to promote short jumps to long
366 ones where necessary. SMALL (short) jumps may be promoted to BIG
367 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
368 don't allow a short jump in a 32 bit code segment to be promoted to
369 a 16 bit offset jump because it's slower (requires data size
370 prefix), and doesn't work, unless the destination is in the bottom
371 64k of the code segment (The top 16 bits of eip are zeroed). */
373 const relax_typeS md_relax_table
[] =
376 1) most positive reach of this state,
377 2) most negative reach of this state,
378 3) how many bytes this mode will have in the variable part of the frag
379 4) which index into the table to try if we can't fit into this one. */
381 /* UNCOND_JUMP states. */
382 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
384 /* dword jmp adds 4 bytes to frag:
385 0 extra opcode bytes, 4 displacement bytes. */
387 /* word jmp adds 2 byte2 to frag:
388 0 extra opcode bytes, 2 displacement bytes. */
391 /* COND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
394 /* dword conditionals adds 5 bytes to frag:
395 1 extra opcode byte, 4 displacement bytes. */
397 /* word conditionals add 3 bytes to frag:
398 1 extra opcode byte, 2 displacement bytes. */
401 /* COND_JUMP86 states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 4 bytes to frag:
408 1 displacement byte and a 3 byte long branch insn. */
412 static const arch_entry cpu_arch
[] = {
414 {"i186", Cpu086
|Cpu186
},
415 {"i286", Cpu086
|Cpu186
|Cpu286
},
416 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
417 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
418 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
419 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
420 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
421 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
422 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
423 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
424 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
425 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
429 const pseudo_typeS md_pseudo_table
[] =
431 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
432 {"align", s_align_bytes
, 0},
434 {"align", s_align_ptwo
, 0},
436 {"arch", set_cpu_arch
, 0},
440 {"ffloat", float_cons
, 'f'},
441 {"dfloat", float_cons
, 'd'},
442 {"tfloat", float_cons
, 'x'},
444 {"noopt", s_ignore
, 0},
445 {"optim", s_ignore
, 0},
446 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
447 {"code16", set_code_flag
, CODE_16BIT
},
448 {"code32", set_code_flag
, CODE_32BIT
},
449 {"code64", set_code_flag
, CODE_64BIT
},
450 {"intel_syntax", set_intel_syntax
, 1},
451 {"att_syntax", set_intel_syntax
, 0},
452 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
453 {"loc", dwarf2_directive_loc
, 0},
455 {"secrel32", pe_directive_secrel
, 0},
460 /* For interface with expression (). */
461 extern char *input_line_pointer
;
463 /* Hash table for instruction mnemonic lookup. */
464 static struct hash_control
*op_hash
;
466 /* Hash table for register lookup. */
467 static struct hash_control
*reg_hash
;
470 i386_align_code (fragP
, count
)
474 /* Various efficient no-op patterns for aligning code labels.
475 Note: Don't try to assemble the instructions in the comments.
476 0L and 0w are not legal. */
477 static const char f32_1
[] =
479 static const char f32_2
[] =
480 {0x89,0xf6}; /* movl %esi,%esi */
481 static const char f32_3
[] =
482 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
483 static const char f32_4
[] =
484 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
485 static const char f32_5
[] =
487 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
488 static const char f32_6
[] =
489 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
490 static const char f32_7
[] =
491 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
492 static const char f32_8
[] =
494 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
495 static const char f32_9
[] =
496 {0x89,0xf6, /* movl %esi,%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_10
[] =
499 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
500 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
501 static const char f32_11
[] =
502 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
503 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
504 static const char f32_12
[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
506 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
507 static const char f32_13
[] =
508 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_14
[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_15
[] =
514 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
515 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
516 static const char f16_3
[] =
517 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
518 static const char f16_4
[] =
519 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
520 static const char f16_5
[] =
522 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
523 static const char f16_6
[] =
524 {0x89,0xf6, /* mov %si,%si */
525 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
526 static const char f16_7
[] =
527 {0x8d,0x74,0x00, /* lea 0(%si),%si */
528 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
529 static const char f16_8
[] =
530 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
531 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
532 static const char *const f32_patt
[] = {
533 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
534 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
536 static const char *const f16_patt
[] = {
537 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
538 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
541 if (count
<= 0 || count
> 15)
544 /* The recommended way to pad 64bit code is to use NOPs preceded by
545 maximally four 0x66 prefixes. Balance the size of nops. */
546 if (flag_code
== CODE_64BIT
)
549 int nnops
= (count
+ 3) / 4;
550 int len
= count
/ nnops
;
551 int remains
= count
- nnops
* len
;
554 for (i
= 0; i
< remains
; i
++)
556 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
557 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
560 for (; i
< nnops
; i
++)
562 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
563 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
568 if (flag_code
== CODE_16BIT
)
570 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
571 f16_patt
[count
- 1], count
);
573 /* Adjust jump offset. */
574 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
577 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
578 f32_patt
[count
- 1], count
);
579 fragP
->fr_var
= count
;
582 static INLINE
unsigned int
583 mode_from_disp_size (t
)
586 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
590 fits_in_signed_byte (num
)
593 return (num
>= -128) && (num
<= 127);
597 fits_in_unsigned_byte (num
)
600 return (num
& 0xff) == num
;
604 fits_in_unsigned_word (num
)
607 return (num
& 0xffff) == num
;
611 fits_in_signed_word (num
)
614 return (-32768 <= num
) && (num
<= 32767);
617 fits_in_signed_long (num
)
618 offsetT num ATTRIBUTE_UNUSED
;
623 return (!(((offsetT
) -1 << 31) & num
)
624 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
626 } /* fits_in_signed_long() */
628 fits_in_unsigned_long (num
)
629 offsetT num ATTRIBUTE_UNUSED
;
634 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
636 } /* fits_in_unsigned_long() */
639 smallest_imm_type (num
)
642 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
644 /* This code is disabled on the 486 because all the Imm1 forms
645 in the opcode table are slower on the i486. They're the
646 versions with the implicitly specified single-position
647 displacement, which has another syntax if you really want to
650 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
652 return (fits_in_signed_byte (num
)
653 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
654 : fits_in_unsigned_byte (num
)
655 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
656 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
657 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
658 : fits_in_signed_long (num
)
659 ? (Imm32
| Imm32S
| Imm64
)
660 : fits_in_unsigned_long (num
)
666 offset_in_range (val
, size
)
674 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
675 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
676 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
678 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
683 /* If BFD64, sign extend val. */
684 if (!use_rela_relocations
)
685 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
686 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
688 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
690 char buf1
[40], buf2
[40];
692 sprint_value (buf1
, val
);
693 sprint_value (buf2
, val
& mask
);
694 as_warn (_("%s shortened to %s"), buf1
, buf2
);
699 /* Returns 0 if attempting to add a prefix where one from the same
700 class already exists, 1 if non rep/repne added, 2 if rep/repne
709 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
710 && flag_code
== CODE_64BIT
)
718 case CS_PREFIX_OPCODE
:
719 case DS_PREFIX_OPCODE
:
720 case ES_PREFIX_OPCODE
:
721 case FS_PREFIX_OPCODE
:
722 case GS_PREFIX_OPCODE
:
723 case SS_PREFIX_OPCODE
:
727 case REPNE_PREFIX_OPCODE
:
728 case REPE_PREFIX_OPCODE
:
731 case LOCK_PREFIX_OPCODE
:
739 case ADDR_PREFIX_OPCODE
:
743 case DATA_PREFIX_OPCODE
:
748 if (i
.prefix
[q
] != 0)
750 as_bad (_("same type of prefix used twice"));
755 i
.prefix
[q
] = prefix
;
760 set_code_flag (value
)
764 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
765 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
766 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
768 as_bad (_("64bit mode not supported on this CPU."));
770 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
772 as_bad (_("32bit mode not supported on this CPU."));
778 set_16bit_gcc_code_flag (new_code_flag
)
781 flag_code
= new_code_flag
;
782 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
783 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
788 set_intel_syntax (syntax_flag
)
791 /* Find out if register prefixing is specified. */
792 int ask_naked_reg
= 0;
795 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
797 char *string
= input_line_pointer
;
798 int e
= get_symbol_end ();
800 if (strcmp (string
, "prefix") == 0)
802 else if (strcmp (string
, "noprefix") == 0)
805 as_bad (_("bad argument to syntax directive."));
806 *input_line_pointer
= e
;
808 demand_empty_rest_of_line ();
810 intel_syntax
= syntax_flag
;
812 if (ask_naked_reg
== 0)
813 allow_naked_reg
= (intel_syntax
814 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
816 allow_naked_reg
= (ask_naked_reg
< 0);
821 int dummy ATTRIBUTE_UNUSED
;
825 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
827 char *string
= input_line_pointer
;
828 int e
= get_symbol_end ();
831 for (i
= 0; cpu_arch
[i
].name
; i
++)
833 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
835 cpu_arch_name
= cpu_arch
[i
].name
;
836 cpu_arch_flags
= (cpu_arch
[i
].flags
837 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
841 if (!cpu_arch
[i
].name
)
842 as_bad (_("no such architecture: `%s'"), string
);
844 *input_line_pointer
= e
;
847 as_bad (_("missing cpu architecture"));
849 no_cond_jump_promotion
= 0;
850 if (*input_line_pointer
== ','
851 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
853 char *string
= ++input_line_pointer
;
854 int e
= get_symbol_end ();
856 if (strcmp (string
, "nojumps") == 0)
857 no_cond_jump_promotion
= 1;
858 else if (strcmp (string
, "jumps") == 0)
861 as_bad (_("no such architecture modifier: `%s'"), string
);
863 *input_line_pointer
= e
;
866 demand_empty_rest_of_line ();
872 if (!strcmp (default_arch
, "x86_64"))
873 return bfd_mach_x86_64
;
874 else if (!strcmp (default_arch
, "i386"))
875 return bfd_mach_i386_i386
;
877 as_fatal (_("Unknown architecture"));
883 const char *hash_err
;
885 /* Initialize op_hash hash table. */
886 op_hash
= hash_new ();
889 const template *optab
;
890 templates
*core_optab
;
892 /* Setup for loop. */
894 core_optab
= (templates
*) xmalloc (sizeof (templates
));
895 core_optab
->start
= optab
;
900 if (optab
->name
== NULL
901 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
903 /* different name --> ship out current template list;
904 add to hash table; & begin anew. */
905 core_optab
->end
= optab
;
906 hash_err
= hash_insert (op_hash
,
911 as_fatal (_("Internal Error: Can't hash %s: %s"),
915 if (optab
->name
== NULL
)
917 core_optab
= (templates
*) xmalloc (sizeof (templates
));
918 core_optab
->start
= optab
;
923 /* Initialize reg_hash hash table. */
924 reg_hash
= hash_new ();
926 const reg_entry
*regtab
;
928 for (regtab
= i386_regtab
;
929 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
932 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
934 as_fatal (_("Internal Error: Can't hash %s: %s"),
940 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
945 for (c
= 0; c
< 256; c
++)
950 mnemonic_chars
[c
] = c
;
951 register_chars
[c
] = c
;
952 operand_chars
[c
] = c
;
954 else if (ISLOWER (c
))
956 mnemonic_chars
[c
] = c
;
957 register_chars
[c
] = c
;
958 operand_chars
[c
] = c
;
960 else if (ISUPPER (c
))
962 mnemonic_chars
[c
] = TOLOWER (c
);
963 register_chars
[c
] = mnemonic_chars
[c
];
964 operand_chars
[c
] = c
;
967 if (ISALPHA (c
) || ISDIGIT (c
))
968 identifier_chars
[c
] = c
;
971 identifier_chars
[c
] = c
;
972 operand_chars
[c
] = c
;
977 identifier_chars
['@'] = '@';
980 identifier_chars
['?'] = '?';
981 operand_chars
['?'] = '?';
983 digit_chars
['-'] = '-';
984 identifier_chars
['_'] = '_';
985 identifier_chars
['.'] = '.';
987 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
988 operand_chars
[(unsigned char) *p
] = *p
;
991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
992 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
994 record_alignment (text_section
, 2);
995 record_alignment (data_section
, 2);
996 record_alignment (bss_section
, 2);
1000 if (flag_code
== CODE_64BIT
)
1002 x86_dwarf2_return_column
= 16;
1003 x86_cie_data_alignment
= -8;
1007 x86_dwarf2_return_column
= 8;
1008 x86_cie_data_alignment
= -4;
1013 i386_print_statistics (file
)
1016 hash_print_statistics (file
, "i386 opcode", op_hash
);
1017 hash_print_statistics (file
, "i386 register", reg_hash
);
1022 /* Debugging routines for md_assemble. */
1023 static void pi
PARAMS ((char *, i386_insn
*));
1024 static void pte
PARAMS ((template *));
1025 static void pt
PARAMS ((unsigned int));
1026 static void pe
PARAMS ((expressionS
*));
1027 static void ps
PARAMS ((symbolS
*));
1036 fprintf (stdout
, "%s: template ", line
);
1038 fprintf (stdout
, " address: base %s index %s scale %x\n",
1039 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1040 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1041 x
->log2_scale_factor
);
1042 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1043 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1044 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1045 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1046 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1047 (x
->rex
& REX_MODE64
) != 0,
1048 (x
->rex
& REX_EXTX
) != 0,
1049 (x
->rex
& REX_EXTY
) != 0,
1050 (x
->rex
& REX_EXTZ
) != 0);
1051 for (i
= 0; i
< x
->operands
; i
++)
1053 fprintf (stdout
, " #%d: ", i
+ 1);
1055 fprintf (stdout
, "\n");
1057 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1058 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1059 if (x
->types
[i
] & Imm
)
1061 if (x
->types
[i
] & Disp
)
1062 pe (x
->op
[i
].disps
);
1071 fprintf (stdout
, " %d operands ", t
->operands
);
1072 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1073 if (t
->extension_opcode
!= None
)
1074 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1075 if (t
->opcode_modifier
& D
)
1076 fprintf (stdout
, "D");
1077 if (t
->opcode_modifier
& W
)
1078 fprintf (stdout
, "W");
1079 fprintf (stdout
, "\n");
1080 for (i
= 0; i
< t
->operands
; i
++)
1082 fprintf (stdout
, " #%d type ", i
+ 1);
1083 pt (t
->operand_types
[i
]);
1084 fprintf (stdout
, "\n");
1092 fprintf (stdout
, " operation %d\n", e
->X_op
);
1093 fprintf (stdout
, " add_number %ld (%lx)\n",
1094 (long) e
->X_add_number
, (long) e
->X_add_number
);
1095 if (e
->X_add_symbol
)
1097 fprintf (stdout
, " add_symbol ");
1098 ps (e
->X_add_symbol
);
1099 fprintf (stdout
, "\n");
1103 fprintf (stdout
, " op_symbol ");
1104 ps (e
->X_op_symbol
);
1105 fprintf (stdout
, "\n");
1113 fprintf (stdout
, "%s type %s%s",
1115 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1116 segment_name (S_GET_SEGMENT (s
)));
1125 static const type_names
[] =
1138 { BaseIndex
, "BaseIndex" },
1142 { Disp32S
, "d32s" },
1144 { InOutPortReg
, "InOutPortReg" },
1145 { ShiftCount
, "ShiftCount" },
1146 { Control
, "control reg" },
1147 { Test
, "test reg" },
1148 { Debug
, "debug reg" },
1149 { FloatReg
, "FReg" },
1150 { FloatAcc
, "FAcc" },
1154 { JumpAbsolute
, "Jump Absolute" },
1165 const struct type_name
*ty
;
1167 for (ty
= type_names
; ty
->mask
; ty
++)
1169 fprintf (stdout
, "%s, ", ty
->tname
);
1173 #endif /* DEBUG386 */
1175 static bfd_reloc_code_real_type reloc
1176 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1178 static bfd_reloc_code_real_type
1179 reloc (size
, pcrel
, sign
, other
)
1183 bfd_reloc_code_real_type other
;
1185 if (other
!= NO_RELOC
)
1191 as_bad (_("There are no unsigned pc-relative relocations"));
1194 case 1: return BFD_RELOC_8_PCREL
;
1195 case 2: return BFD_RELOC_16_PCREL
;
1196 case 4: return BFD_RELOC_32_PCREL
;
1198 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1205 case 4: return BFD_RELOC_X86_64_32S
;
1210 case 1: return BFD_RELOC_8
;
1211 case 2: return BFD_RELOC_16
;
1212 case 4: return BFD_RELOC_32
;
1213 case 8: return BFD_RELOC_64
;
1215 as_bad (_("can not do %s %d byte relocation"),
1216 sign
? "signed" : "unsigned", size
);
1220 return BFD_RELOC_NONE
;
1223 /* Here we decide which fixups can be adjusted to make them relative to
1224 the beginning of the section instead of the symbol. Basically we need
1225 to make sure that the dynamic relocations are done correctly, so in
1226 some cases we force the original symbol to be used. */
1229 tc_i386_fix_adjustable (fixP
)
1230 fixS
*fixP ATTRIBUTE_UNUSED
;
1232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1233 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1236 /* Don't adjust pc-relative references to merge sections in 64-bit
1238 if (use_rela_relocations
1239 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1243 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1244 and changed later by validate_fix. */
1245 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1246 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1249 /* adjust_reloc_syms doesn't know about the GOT. */
1250 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1251 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1252 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1253 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1254 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1255 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1256 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1257 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1258 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1259 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1260 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1261 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1262 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1263 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1264 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1265 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1266 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1267 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1268 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1269 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1270 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1276 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1279 intel_float_operand (mnemonic
)
1280 const char *mnemonic
;
1282 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1285 if (mnemonic
[0] == 'f')
1291 /* This is the guts of the machine-dependent assembler. LINE points to a
1292 machine dependent instruction. This function is supposed to emit
1293 the frags/bytes it assembles to. */
1300 char mnemonic
[MAX_MNEM_SIZE
];
1302 /* Initialize globals. */
1303 memset (&i
, '\0', sizeof (i
));
1304 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1305 i
.reloc
[j
] = NO_RELOC
;
1306 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1307 memset (im_expressions
, '\0', sizeof (im_expressions
));
1308 save_stack_p
= save_stack
;
1310 /* First parse an instruction mnemonic & call i386_operand for the operands.
1311 We assume that the scrubber has arranged it so that line[0] is the valid
1312 start of a (possibly prefixed) mnemonic. */
1314 line
= parse_insn (line
, mnemonic
);
1318 line
= parse_operands (line
, mnemonic
);
1322 /* Now we've parsed the mnemonic into a set of templates, and have the
1323 operands at hand. */
1325 /* All intel opcodes have reversed operands except for "bound" and
1326 "enter". We also don't reverse intersegment "jmp" and "call"
1327 instructions with 2 immediate operands so that the immediate segment
1328 precedes the offset, as it does when in AT&T mode. "enter" and the
1329 intersegment "jmp" and "call" instructions are the only ones that
1330 have two immediate operands. */
1331 if (intel_syntax
&& i
.operands
> 1
1332 && (strcmp (mnemonic
, "bound") != 0)
1333 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1339 if (i
.disp_operands
)
1342 /* Next, we find a template that matches the given insn,
1343 making sure the overlap of the given operands types is consistent
1344 with the template operand types. */
1346 if (!match_template ())
1351 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1353 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1354 i
.tm
.base_opcode
^= FloatR
;
1356 /* Zap movzx and movsx suffix. The suffix may have been set from
1357 "word ptr" or "byte ptr" on the source operand, but we'll use
1358 the suffix later to choose the destination register. */
1359 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1363 if (i
.tm
.opcode_modifier
& FWait
)
1364 if (!add_prefix (FWAIT_OPCODE
))
1367 /* Check string instruction segment overrides. */
1368 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1370 if (!check_string ())
1374 if (!process_suffix ())
1377 /* Make still unresolved immediate matches conform to size of immediate
1378 given in i.suffix. */
1379 if (!finalize_imm ())
1382 if (i
.types
[0] & Imm1
)
1383 i
.imm_operands
= 0; /* kludge for shift insns. */
1384 if (i
.types
[0] & ImplicitRegister
)
1386 if (i
.types
[1] & ImplicitRegister
)
1388 if (i
.types
[2] & ImplicitRegister
)
1391 if (i
.tm
.opcode_modifier
& ImmExt
)
1395 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1397 /* These Intel Prescott New Instructions have the fixed
1398 operands with an opcode suffix which is coded in the same
1399 place as an 8-bit immediate field would be. Here we check
1400 those operands and remove them afterwards. */
1403 for (x
= 0; x
< i
.operands
; x
++)
1404 if (i
.op
[x
].regs
->reg_num
!= x
)
1405 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1406 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1410 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1411 opcode suffix which is coded in the same place as an 8-bit
1412 immediate field would be. Here we fake an 8-bit immediate
1413 operand from the opcode suffix stored in tm.extension_opcode. */
1415 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1417 exp
= &im_expressions
[i
.imm_operands
++];
1418 i
.op
[i
.operands
].imms
= exp
;
1419 i
.types
[i
.operands
++] = Imm8
;
1420 exp
->X_op
= O_constant
;
1421 exp
->X_add_number
= i
.tm
.extension_opcode
;
1422 i
.tm
.extension_opcode
= None
;
1425 /* For insns with operands there are more diddles to do to the opcode. */
1428 if (!process_operands ())
1431 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1433 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1434 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1437 /* Handle conversion of 'int $3' --> special int3 insn. */
1438 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1440 i
.tm
.base_opcode
= INT3_OPCODE
;
1444 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1445 && i
.op
[0].disps
->X_op
== O_constant
)
1447 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1448 the absolute address given by the constant. Since ix86 jumps and
1449 calls are pc relative, we need to generate a reloc. */
1450 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1451 i
.op
[0].disps
->X_op
= O_symbol
;
1454 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1455 i
.rex
|= REX_MODE64
;
1457 /* For 8 bit registers we need an empty rex prefix. Also if the
1458 instruction already has a prefix, we need to convert old
1459 registers to new ones. */
1461 if (((i
.types
[0] & Reg8
) != 0
1462 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1463 || ((i
.types
[1] & Reg8
) != 0
1464 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1465 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1470 i
.rex
|= REX_OPCODE
;
1471 for (x
= 0; x
< 2; x
++)
1473 /* Look for 8 bit operand that uses old registers. */
1474 if ((i
.types
[x
] & Reg8
) != 0
1475 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1477 /* In case it is "hi" register, give up. */
1478 if (i
.op
[x
].regs
->reg_num
> 3)
1479 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1480 i
.op
[x
].regs
->reg_name
);
1482 /* Otherwise it is equivalent to the extended register.
1483 Since the encoding doesn't change this is merely
1484 cosmetic cleanup for debug output. */
1486 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1492 add_prefix (REX_OPCODE
| i
.rex
);
1494 /* We are ready to output the insn. */
1499 parse_insn (line
, mnemonic
)
1504 char *token_start
= l
;
1507 /* Non-zero if we found a prefix only acceptable with string insns. */
1508 const char *expecting_string_instruction
= NULL
;
1513 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1516 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1518 as_bad (_("no such instruction: `%s'"), token_start
);
1523 if (!is_space_char (*l
)
1524 && *l
!= END_OF_INSN
1525 && *l
!= PREFIX_SEPARATOR
1528 as_bad (_("invalid character %s in mnemonic"),
1529 output_invalid (*l
));
1532 if (token_start
== l
)
1534 if (*l
== PREFIX_SEPARATOR
)
1535 as_bad (_("expecting prefix; got nothing"));
1537 as_bad (_("expecting mnemonic; got nothing"));
1541 /* Look up instruction (or prefix) via hash table. */
1542 current_templates
= hash_find (op_hash
, mnemonic
);
1544 if (*l
!= END_OF_INSN
1545 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1546 && current_templates
1547 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1549 /* If we are in 16-bit mode, do not allow addr16 or data16.
1550 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1551 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1552 && flag_code
!= CODE_64BIT
1553 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1554 ^ (flag_code
== CODE_16BIT
)))
1556 as_bad (_("redundant %s prefix"),
1557 current_templates
->start
->name
);
1560 /* Add prefix, checking for repeated prefixes. */
1561 switch (add_prefix (current_templates
->start
->base_opcode
))
1566 expecting_string_instruction
= current_templates
->start
->name
;
1569 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1576 if (!current_templates
)
1578 /* See if we can get a match by trimming off a suffix. */
1581 case WORD_MNEM_SUFFIX
:
1582 case BYTE_MNEM_SUFFIX
:
1583 case QWORD_MNEM_SUFFIX
:
1584 i
.suffix
= mnem_p
[-1];
1586 current_templates
= hash_find (op_hash
, mnemonic
);
1588 case SHORT_MNEM_SUFFIX
:
1589 case LONG_MNEM_SUFFIX
:
1592 i
.suffix
= mnem_p
[-1];
1594 current_templates
= hash_find (op_hash
, mnemonic
);
1602 if (intel_float_operand (mnemonic
))
1603 i
.suffix
= SHORT_MNEM_SUFFIX
;
1605 i
.suffix
= LONG_MNEM_SUFFIX
;
1607 current_templates
= hash_find (op_hash
, mnemonic
);
1611 if (!current_templates
)
1613 as_bad (_("no such instruction: `%s'"), token_start
);
1618 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1620 /* Check for a branch hint. We allow ",pt" and ",pn" for
1621 predict taken and predict not taken respectively.
1622 I'm not sure that branch hints actually do anything on loop
1623 and jcxz insns (JumpByte) for current Pentium4 chips. They
1624 may work in the future and it doesn't hurt to accept them
1626 if (l
[0] == ',' && l
[1] == 'p')
1630 if (!add_prefix (DS_PREFIX_OPCODE
))
1634 else if (l
[2] == 'n')
1636 if (!add_prefix (CS_PREFIX_OPCODE
))
1642 /* Any other comma loses. */
1645 as_bad (_("invalid character %s in mnemonic"),
1646 output_invalid (*l
));
1650 /* Check if instruction is supported on specified architecture. */
1651 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1652 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1654 as_warn (_("`%s' is not supported on `%s'"),
1655 current_templates
->start
->name
, cpu_arch_name
);
1657 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1659 as_warn (_("use .code16 to ensure correct addressing mode"));
1662 /* Check for rep/repne without a string instruction. */
1663 if (expecting_string_instruction
1664 && !(current_templates
->start
->opcode_modifier
& IsString
))
1666 as_bad (_("expecting string instruction after `%s'"),
1667 expecting_string_instruction
);
1675 parse_operands (l
, mnemonic
)
1677 const char *mnemonic
;
1681 /* 1 if operand is pending after ','. */
1682 unsigned int expecting_operand
= 0;
1684 /* Non-zero if operand parens not balanced. */
1685 unsigned int paren_not_balanced
;
1687 while (*l
!= END_OF_INSN
)
1689 /* Skip optional white space before operand. */
1690 if (is_space_char (*l
))
1692 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1694 as_bad (_("invalid character %s before operand %d"),
1695 output_invalid (*l
),
1699 token_start
= l
; /* after white space */
1700 paren_not_balanced
= 0;
1701 while (paren_not_balanced
|| *l
!= ',')
1703 if (*l
== END_OF_INSN
)
1705 if (paren_not_balanced
)
1708 as_bad (_("unbalanced parenthesis in operand %d."),
1711 as_bad (_("unbalanced brackets in operand %d."),
1716 break; /* we are done */
1718 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1720 as_bad (_("invalid character %s in operand %d"),
1721 output_invalid (*l
),
1728 ++paren_not_balanced
;
1730 --paren_not_balanced
;
1735 ++paren_not_balanced
;
1737 --paren_not_balanced
;
1741 if (l
!= token_start
)
1742 { /* Yes, we've read in another operand. */
1743 unsigned int operand_ok
;
1744 this_operand
= i
.operands
++;
1745 if (i
.operands
> MAX_OPERANDS
)
1747 as_bad (_("spurious operands; (%d operands/instruction max)"),
1751 /* Now parse operand adding info to 'i' as we go along. */
1752 END_STRING_AND_SAVE (l
);
1756 i386_intel_operand (token_start
,
1757 intel_float_operand (mnemonic
));
1759 operand_ok
= i386_operand (token_start
);
1761 RESTORE_END_STRING (l
);
1767 if (expecting_operand
)
1769 expecting_operand_after_comma
:
1770 as_bad (_("expecting operand after ','; got nothing"));
1775 as_bad (_("expecting operand before ','; got nothing"));
1780 /* Now *l must be either ',' or END_OF_INSN. */
1783 if (*++l
== END_OF_INSN
)
1785 /* Just skip it, if it's \n complain. */
1786 goto expecting_operand_after_comma
;
1788 expecting_operand
= 1;
1797 union i386_op temp_op
;
1798 unsigned int temp_type
;
1799 enum bfd_reloc_code_real temp_reloc
;
1803 if (i
.operands
== 2)
1808 else if (i
.operands
== 3)
1813 temp_type
= i
.types
[xchg2
];
1814 i
.types
[xchg2
] = i
.types
[xchg1
];
1815 i
.types
[xchg1
] = temp_type
;
1816 temp_op
= i
.op
[xchg2
];
1817 i
.op
[xchg2
] = i
.op
[xchg1
];
1818 i
.op
[xchg1
] = temp_op
;
1819 temp_reloc
= i
.reloc
[xchg2
];
1820 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1821 i
.reloc
[xchg1
] = temp_reloc
;
1823 if (i
.mem_operands
== 2)
1825 const seg_entry
*temp_seg
;
1826 temp_seg
= i
.seg
[0];
1827 i
.seg
[0] = i
.seg
[1];
1828 i
.seg
[1] = temp_seg
;
1832 /* Try to ensure constant immediates are represented in the smallest
1837 char guess_suffix
= 0;
1841 guess_suffix
= i
.suffix
;
1842 else if (i
.reg_operands
)
1844 /* Figure out a suffix from the last register operand specified.
1845 We can't do this properly yet, ie. excluding InOutPortReg,
1846 but the following works for instructions with immediates.
1847 In any case, we can't set i.suffix yet. */
1848 for (op
= i
.operands
; --op
>= 0;)
1849 if (i
.types
[op
] & Reg
)
1851 if (i
.types
[op
] & Reg8
)
1852 guess_suffix
= BYTE_MNEM_SUFFIX
;
1853 else if (i
.types
[op
] & Reg16
)
1854 guess_suffix
= WORD_MNEM_SUFFIX
;
1855 else if (i
.types
[op
] & Reg32
)
1856 guess_suffix
= LONG_MNEM_SUFFIX
;
1857 else if (i
.types
[op
] & Reg64
)
1858 guess_suffix
= QWORD_MNEM_SUFFIX
;
1862 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1863 guess_suffix
= WORD_MNEM_SUFFIX
;
1865 for (op
= i
.operands
; --op
>= 0;)
1866 if (i
.types
[op
] & Imm
)
1868 switch (i
.op
[op
].imms
->X_op
)
1871 /* If a suffix is given, this operand may be shortened. */
1872 switch (guess_suffix
)
1874 case LONG_MNEM_SUFFIX
:
1875 i
.types
[op
] |= Imm32
| Imm64
;
1877 case WORD_MNEM_SUFFIX
:
1878 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1880 case BYTE_MNEM_SUFFIX
:
1881 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1885 /* If this operand is at most 16 bits, convert it
1886 to a signed 16 bit number before trying to see
1887 whether it will fit in an even smaller size.
1888 This allows a 16-bit operand such as $0xffe0 to
1889 be recognised as within Imm8S range. */
1890 if ((i
.types
[op
] & Imm16
)
1891 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1893 i
.op
[op
].imms
->X_add_number
=
1894 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1896 if ((i
.types
[op
] & Imm32
)
1897 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1900 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1901 ^ ((offsetT
) 1 << 31))
1902 - ((offsetT
) 1 << 31));
1904 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1906 /* We must avoid matching of Imm32 templates when 64bit
1907 only immediate is available. */
1908 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1909 i
.types
[op
] &= ~Imm32
;
1916 /* Symbols and expressions. */
1918 /* Convert symbolic operand to proper sizes for matching. */
1919 switch (guess_suffix
)
1921 case QWORD_MNEM_SUFFIX
:
1922 i
.types
[op
] = Imm64
| Imm32S
;
1924 case LONG_MNEM_SUFFIX
:
1925 i
.types
[op
] = Imm32
;
1927 case WORD_MNEM_SUFFIX
:
1928 i
.types
[op
] = Imm16
;
1930 case BYTE_MNEM_SUFFIX
:
1931 i
.types
[op
] = Imm8
| Imm8S
;
1939 /* Try to use the smallest displacement type too. */
1945 for (op
= i
.operands
; --op
>= 0;)
1946 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1948 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1950 if (i
.types
[op
] & Disp16
)
1952 /* We know this operand is at most 16 bits, so
1953 convert to a signed 16 bit number before trying
1954 to see whether it will fit in an even smaller
1957 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1959 else if (i
.types
[op
] & Disp32
)
1961 /* We know this operand is at most 32 bits, so convert to a
1962 signed 32 bit number before trying to see whether it will
1963 fit in an even smaller size. */
1964 disp
&= (((offsetT
) 2 << 31) - 1);
1965 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1967 if (flag_code
== CODE_64BIT
)
1969 if (fits_in_signed_long (disp
))
1970 i
.types
[op
] |= Disp32S
;
1971 if (fits_in_unsigned_long (disp
))
1972 i
.types
[op
] |= Disp32
;
1974 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1975 && fits_in_signed_byte (disp
))
1976 i
.types
[op
] |= Disp8
;
1983 /* Points to template once we've found it. */
1985 unsigned int overlap0
, overlap1
, overlap2
;
1986 unsigned int found_reverse_match
;
1989 #define MATCH(overlap, given, template) \
1990 ((overlap & ~JumpAbsolute) \
1991 && (((given) & (BaseIndex | JumpAbsolute)) \
1992 == ((overlap) & (BaseIndex | JumpAbsolute))))
1994 /* If given types r0 and r1 are registers they must be of the same type
1995 unless the expected operand type register overlap is null.
1996 Note that Acc in a template matches every size of reg. */
1997 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1998 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1999 || ((g0) & Reg) == ((g1) & Reg) \
2000 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2005 found_reverse_match
= 0;
2006 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2008 : (i
.suffix
== WORD_MNEM_SUFFIX
2010 : (i
.suffix
== SHORT_MNEM_SUFFIX
2012 : (i
.suffix
== LONG_MNEM_SUFFIX
2014 : (i
.suffix
== QWORD_MNEM_SUFFIX
2016 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2017 ? No_xSuf
: 0))))));
2019 t
= current_templates
->start
;
2020 if (i
.suffix
== QWORD_MNEM_SUFFIX
2021 && flag_code
!= CODE_64BIT
2023 || (!(t
->opcode_modifier
& IgnoreSize
)
2024 && ! intel_float_operand (t
->name
)))
2025 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2026 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2027 && (t
->base_opcode
!= 0x0fc7
2028 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2029 t
= current_templates
->end
;
2030 for (; t
< current_templates
->end
; t
++)
2032 /* Must have right number of operands. */
2033 if (i
.operands
!= t
->operands
)
2036 /* Check the suffix, except for some instructions in intel mode. */
2037 if ((t
->opcode_modifier
& suffix_check
)
2039 && (t
->opcode_modifier
& IgnoreSize
))
2041 && t
->base_opcode
== 0xd9
2042 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2043 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2046 /* Do not verify operands when there are none. */
2047 else if (!t
->operands
)
2049 if (t
->cpu_flags
& ~cpu_arch_flags
)
2051 /* We've found a match; break out of loop. */
2055 overlap0
= i
.types
[0] & t
->operand_types
[0];
2056 switch (t
->operands
)
2059 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2064 overlap1
= i
.types
[1] & t
->operand_types
[1];
2065 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2066 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2067 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2068 t
->operand_types
[0],
2069 overlap1
, i
.types
[1],
2070 t
->operand_types
[1]))
2072 /* Check if other direction is valid ... */
2073 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2076 /* Try reversing direction of operands. */
2077 overlap0
= i
.types
[0] & t
->operand_types
[1];
2078 overlap1
= i
.types
[1] & t
->operand_types
[0];
2079 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2080 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2081 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2082 t
->operand_types
[1],
2083 overlap1
, i
.types
[1],
2084 t
->operand_types
[0]))
2086 /* Does not match either direction. */
2089 /* found_reverse_match holds which of D or FloatDR
2091 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2093 /* Found a forward 2 operand match here. */
2094 else if (t
->operands
== 3)
2096 /* Here we make use of the fact that there are no
2097 reverse match 3 operand instructions, and all 3
2098 operand instructions only need to be checked for
2099 register consistency between operands 2 and 3. */
2100 overlap2
= i
.types
[2] & t
->operand_types
[2];
2101 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2102 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2103 t
->operand_types
[1],
2104 overlap2
, i
.types
[2],
2105 t
->operand_types
[2]))
2109 /* Found either forward/reverse 2 or 3 operand match here:
2110 slip through to break. */
2112 if (t
->cpu_flags
& ~cpu_arch_flags
)
2114 found_reverse_match
= 0;
2117 /* We've found a match; break out of loop. */
2121 if (t
== current_templates
->end
)
2123 /* We found no match. */
2124 as_bad (_("suffix or operands invalid for `%s'"),
2125 current_templates
->start
->name
);
2129 if (!quiet_warnings
)
2132 && ((i
.types
[0] & JumpAbsolute
)
2133 != (t
->operand_types
[0] & JumpAbsolute
)))
2135 as_warn (_("indirect %s without `*'"), t
->name
);
2138 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2139 == (IsPrefix
| IgnoreSize
))
2141 /* Warn them that a data or address size prefix doesn't
2142 affect assembly of the next line of code. */
2143 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2147 /* Copy the template we found. */
2149 if (found_reverse_match
)
2151 /* If we found a reverse match we must alter the opcode
2152 direction bit. found_reverse_match holds bits to change
2153 (different for int & float insns). */
2155 i
.tm
.base_opcode
^= found_reverse_match
;
2157 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2158 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2167 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2168 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2170 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2172 as_bad (_("`%s' operand %d must use `%%es' segment"),
2177 /* There's only ever one segment override allowed per instruction.
2178 This instruction possibly has a legal segment override on the
2179 second operand, so copy the segment to where non-string
2180 instructions store it, allowing common code. */
2181 i
.seg
[0] = i
.seg
[1];
2183 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2185 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2187 as_bad (_("`%s' operand %d must use `%%es' segment"),
2197 process_suffix (void)
2199 /* If matched instruction specifies an explicit instruction mnemonic
2201 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2203 if (i
.tm
.opcode_modifier
& Size16
)
2204 i
.suffix
= WORD_MNEM_SUFFIX
;
2205 else if (i
.tm
.opcode_modifier
& Size64
)
2206 i
.suffix
= QWORD_MNEM_SUFFIX
;
2208 i
.suffix
= LONG_MNEM_SUFFIX
;
2210 else if (i
.reg_operands
)
2212 /* If there's no instruction mnemonic suffix we try to invent one
2213 based on register operands. */
2216 /* We take i.suffix from the last register operand specified,
2217 Destination register type is more significant than source
2221 for (op
= i
.operands
; --op
>= 0;)
2222 if ((i
.types
[op
] & Reg
)
2223 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2225 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2226 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2227 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2232 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2234 if (!check_byte_reg ())
2237 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2239 if (!check_long_reg ())
2242 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2244 if (!check_qword_reg ())
2247 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2249 if (!check_word_reg ())
2252 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2253 /* Do nothing if the instruction is going to ignore the prefix. */
2258 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2260 i
.suffix
= stackop_size
;
2261 if (i
.suffix
== QWORD_MNEM_SUFFIX
2262 && (i
.tm
.opcode_modifier
& No_qSuf
))
2263 i
.suffix
= LONG_MNEM_SUFFIX
;
2266 /* Change the opcode based on the operand size given by i.suffix;
2267 We need not change things for byte insns. */
2268 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2270 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2274 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2276 /* It's not a byte, select word/dword operation. */
2277 if (i
.tm
.opcode_modifier
& W
)
2279 if (i
.tm
.opcode_modifier
& ShortForm
)
2280 i
.tm
.base_opcode
|= 8;
2282 i
.tm
.base_opcode
|= 1;
2285 /* Now select between word & dword operations via the operand
2286 size prefix, except for instructions that will ignore this
2288 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2289 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2290 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2291 || (flag_code
== CODE_64BIT
2292 && (i
.tm
.opcode_modifier
& JumpByte
))))
2294 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2296 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2297 prefix
= ADDR_PREFIX_OPCODE
;
2299 if (!add_prefix (prefix
))
2303 /* Set mode64 for an operand. */
2304 if (i
.suffix
== QWORD_MNEM_SUFFIX
2305 && flag_code
== CODE_64BIT
2306 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2307 i
.rex
|= REX_MODE64
;
2309 /* Size floating point instruction. */
2310 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2311 if (i
.tm
.opcode_modifier
& FloatMF
)
2312 i
.tm
.base_opcode
^= 4;
2319 check_byte_reg (void)
2323 for (op
= i
.operands
; --op
>= 0;)
2325 /* If this is an eight bit register, it's OK. If it's the 16 or
2326 32 bit version of an eight bit register, we will just use the
2327 low portion, and that's OK too. */
2328 if (i
.types
[op
] & Reg8
)
2331 /* movzx and movsx should not generate this warning. */
2333 && (i
.tm
.base_opcode
== 0xfb7
2334 || i
.tm
.base_opcode
== 0xfb6
2335 || i
.tm
.base_opcode
== 0x63
2336 || i
.tm
.base_opcode
== 0xfbe
2337 || i
.tm
.base_opcode
== 0xfbf))
2340 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2342 /* Check that the template allows eight bit regs. This
2343 kills insns such as `orb $1,%edx', which maybe should be
2345 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2349 /* Prohibit these changes in the 64bit mode, since the
2350 lowering is more complicated. */
2351 if (flag_code
== CODE_64BIT
2352 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2354 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2355 i
.op
[op
].regs
->reg_name
,
2359 #if REGISTER_WARNINGS
2361 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2362 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2363 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2364 ? REGNAM_AL
- REGNAM_AX
2365 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2366 i
.op
[op
].regs
->reg_name
,
2371 /* Any other register is bad. */
2372 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2374 | Control
| Debug
| Test
2375 | FloatReg
| FloatAcc
))
2377 as_bad (_("`%%%s' not allowed with `%s%c'"),
2378 i
.op
[op
].regs
->reg_name
,
2392 for (op
= i
.operands
; --op
>= 0;)
2393 /* Reject eight bit registers, except where the template requires
2394 them. (eg. movzb) */
2395 if ((i
.types
[op
] & Reg8
) != 0
2396 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2398 as_bad (_("`%%%s' not allowed with `%s%c'"),
2399 i
.op
[op
].regs
->reg_name
,
2404 /* Warn if the e prefix on a general reg is missing. */
2405 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2406 && (i
.types
[op
] & Reg16
) != 0
2407 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2409 /* Prohibit these changes in the 64bit mode, since the
2410 lowering is more complicated. */
2411 if (flag_code
== CODE_64BIT
)
2413 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2414 i
.op
[op
].regs
->reg_name
,
2418 #if REGISTER_WARNINGS
2420 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2421 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2422 i
.op
[op
].regs
->reg_name
,
2426 /* Warn if the r prefix on a general reg is missing. */
2427 else if ((i
.types
[op
] & Reg64
) != 0
2428 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2430 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2431 i
.op
[op
].regs
->reg_name
,
2443 for (op
= i
.operands
; --op
>= 0; )
2444 /* Reject eight bit registers, except where the template requires
2445 them. (eg. movzb) */
2446 if ((i
.types
[op
] & Reg8
) != 0
2447 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2449 as_bad (_("`%%%s' not allowed with `%s%c'"),
2450 i
.op
[op
].regs
->reg_name
,
2455 /* Warn if the e prefix on a general reg is missing. */
2456 else if (((i
.types
[op
] & Reg16
) != 0
2457 || (i
.types
[op
] & Reg32
) != 0)
2458 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2460 /* Prohibit these changes in the 64bit mode, since the
2461 lowering is more complicated. */
2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2463 i
.op
[op
].regs
->reg_name
,
2474 for (op
= i
.operands
; --op
>= 0;)
2475 /* Reject eight bit registers, except where the template requires
2476 them. (eg. movzb) */
2477 if ((i
.types
[op
] & Reg8
) != 0
2478 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2480 as_bad (_("`%%%s' not allowed with `%s%c'"),
2481 i
.op
[op
].regs
->reg_name
,
2486 /* Warn if the e prefix on a general reg is present. */
2487 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2488 && (i
.types
[op
] & Reg32
) != 0
2489 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2491 /* Prohibit these changes in the 64bit mode, since the
2492 lowering is more complicated. */
2493 if (flag_code
== CODE_64BIT
)
2495 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2496 i
.op
[op
].regs
->reg_name
,
2501 #if REGISTER_WARNINGS
2502 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2503 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2504 i
.op
[op
].regs
->reg_name
,
2514 unsigned int overlap0
, overlap1
, overlap2
;
2516 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2517 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2518 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2519 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2520 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2524 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2526 : (i
.suffix
== WORD_MNEM_SUFFIX
2528 : (i
.suffix
== QWORD_MNEM_SUFFIX
2532 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2533 || overlap0
== (Imm16
| Imm32
)
2534 || overlap0
== (Imm16
| Imm32S
))
2536 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2539 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2540 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2541 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2547 i
.types
[0] = overlap0
;
2549 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2550 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2551 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2552 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2553 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2557 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2559 : (i
.suffix
== WORD_MNEM_SUFFIX
2561 : (i
.suffix
== QWORD_MNEM_SUFFIX
2565 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2566 || overlap1
== (Imm16
| Imm32
)
2567 || overlap1
== (Imm16
| Imm32S
))
2569 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2572 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2573 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2574 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2576 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2580 i
.types
[1] = overlap1
;
2582 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2583 assert ((overlap2
& Imm
) == 0);
2584 i
.types
[2] = overlap2
;
2592 /* Default segment register this instruction will use for memory
2593 accesses. 0 means unknown. This is only for optimizing out
2594 unnecessary segment overrides. */
2595 const seg_entry
*default_seg
= 0;
2597 /* The imul $imm, %reg instruction is converted into
2598 imul $imm, %reg, %reg, and the clr %reg instruction
2599 is converted into xor %reg, %reg. */
2600 if (i
.tm
.opcode_modifier
& regKludge
)
2602 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2603 /* Pretend we saw the extra register operand. */
2604 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2605 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2606 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2610 if (i
.tm
.opcode_modifier
& ShortForm
)
2612 /* The register or float register operand is in operand 0 or 1. */
2613 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2614 /* Register goes in low 3 bits of opcode. */
2615 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2616 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2618 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2620 /* Warn about some common errors, but press on regardless.
2621 The first case can be generated by gcc (<= 2.8.1). */
2622 if (i
.operands
== 2)
2624 /* Reversed arguments on faddp, fsubp, etc. */
2625 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2626 i
.op
[1].regs
->reg_name
,
2627 i
.op
[0].regs
->reg_name
);
2631 /* Extraneous `l' suffix on fp insn. */
2632 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2633 i
.op
[0].regs
->reg_name
);
2637 else if (i
.tm
.opcode_modifier
& Modrm
)
2639 /* The opcode is completed (modulo i.tm.extension_opcode which
2640 must be put into the modrm byte). Now, we make the modrm and
2641 index base bytes based on all the info we've collected. */
2643 default_seg
= build_modrm_byte ();
2645 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2647 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2648 && i
.op
[0].regs
->reg_num
== 1)
2650 as_bad (_("you can't `pop %%cs'"));
2653 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2654 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2657 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2661 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2663 /* For the string instructions that allow a segment override
2664 on one of their operands, the default segment is ds. */
2668 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2669 as_warn (_("segment override on `lea' is ineffectual"));
2671 /* If a segment was explicitly specified, and the specified segment
2672 is not the default, use an opcode prefix to select it. If we
2673 never figured out what the default segment is, then default_seg
2674 will be zero at this point, and the specified segment prefix will
2676 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2678 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2684 static const seg_entry
*
2687 const seg_entry
*default_seg
= 0;
2689 /* i.reg_operands MUST be the number of real register operands;
2690 implicit registers do not count. */
2691 if (i
.reg_operands
== 2)
2693 unsigned int source
, dest
;
2694 source
= ((i
.types
[0]
2695 & (Reg
| RegMMX
| RegXMM
2697 | Control
| Debug
| Test
))
2702 /* One of the register operands will be encoded in the i.tm.reg
2703 field, the other in the combined i.tm.mode and i.tm.regmem
2704 fields. If no form of this instruction supports a memory
2705 destination operand, then we assume the source operand may
2706 sometimes be a memory operand and so we need to store the
2707 destination in the i.rm.reg field. */
2708 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2710 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2711 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2712 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2714 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2719 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2720 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2721 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2723 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2728 { /* If it's not 2 reg operands... */
2731 unsigned int fake_zero_displacement
= 0;
2732 unsigned int op
= ((i
.types
[0] & AnyMem
)
2734 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2738 if (i
.base_reg
== 0)
2741 if (!i
.disp_operands
)
2742 fake_zero_displacement
= 1;
2743 if (i
.index_reg
== 0)
2745 /* Operand is just <disp> */
2746 if (flag_code
== CODE_64BIT
)
2748 /* 64bit mode overwrites the 32bit absolute
2749 addressing by RIP relative addressing and
2750 absolute addressing is encoded by one of the
2751 redundant SIB forms. */
2752 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2753 i
.sib
.base
= NO_BASE_REGISTER
;
2754 i
.sib
.index
= NO_INDEX_REGISTER
;
2755 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2757 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2759 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2760 i
.types
[op
] = Disp16
;
2764 i
.rm
.regmem
= NO_BASE_REGISTER
;
2765 i
.types
[op
] = Disp32
;
2768 else /* !i.base_reg && i.index_reg */
2770 i
.sib
.index
= i
.index_reg
->reg_num
;
2771 i
.sib
.base
= NO_BASE_REGISTER
;
2772 i
.sib
.scale
= i
.log2_scale_factor
;
2773 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2774 i
.types
[op
] &= ~Disp
;
2775 if (flag_code
!= CODE_64BIT
)
2776 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2778 i
.types
[op
] |= Disp32S
;
2779 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2783 /* RIP addressing for 64bit mode. */
2784 else if (i
.base_reg
->reg_type
== BaseIndex
)
2786 i
.rm
.regmem
= NO_BASE_REGISTER
;
2787 i
.types
[op
] &= ~ Disp
;
2788 i
.types
[op
] |= Disp32S
;
2789 i
.flags
[op
] = Operand_PCrel
;
2790 if (! i
.disp_operands
)
2791 fake_zero_displacement
= 1;
2793 else if (i
.base_reg
->reg_type
& Reg16
)
2795 switch (i
.base_reg
->reg_num
)
2798 if (i
.index_reg
== 0)
2800 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2801 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2805 if (i
.index_reg
== 0)
2808 if ((i
.types
[op
] & Disp
) == 0)
2810 /* fake (%bp) into 0(%bp) */
2811 i
.types
[op
] |= Disp8
;
2812 fake_zero_displacement
= 1;
2815 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2816 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2818 default: /* (%si) -> 4 or (%di) -> 5 */
2819 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2821 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2823 else /* i.base_reg and 32/64 bit mode */
2825 if (flag_code
== CODE_64BIT
2826 && (i
.types
[op
] & Disp
))
2827 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2829 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2830 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2832 i
.sib
.base
= i
.base_reg
->reg_num
;
2833 /* x86-64 ignores REX prefix bit here to avoid decoder
2835 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2838 if (i
.disp_operands
== 0)
2840 fake_zero_displacement
= 1;
2841 i
.types
[op
] |= Disp8
;
2844 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2848 i
.sib
.scale
= i
.log2_scale_factor
;
2849 if (i
.index_reg
== 0)
2851 /* <disp>(%esp) becomes two byte modrm with no index
2852 register. We've already stored the code for esp
2853 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2854 Any base register besides %esp will not use the
2855 extra modrm byte. */
2856 i
.sib
.index
= NO_INDEX_REGISTER
;
2857 #if !SCALE1_WHEN_NO_INDEX
2858 /* Another case where we force the second modrm byte. */
2859 if (i
.log2_scale_factor
)
2860 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2865 i
.sib
.index
= i
.index_reg
->reg_num
;
2866 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2867 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2870 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2873 if (fake_zero_displacement
)
2875 /* Fakes a zero displacement assuming that i.types[op]
2876 holds the correct displacement size. */
2879 assert (i
.op
[op
].disps
== 0);
2880 exp
= &disp_expressions
[i
.disp_operands
++];
2881 i
.op
[op
].disps
= exp
;
2882 exp
->X_op
= O_constant
;
2883 exp
->X_add_number
= 0;
2884 exp
->X_add_symbol
= (symbolS
*) 0;
2885 exp
->X_op_symbol
= (symbolS
*) 0;
2889 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2890 (if any) based on i.tm.extension_opcode. Again, we must be
2891 careful to make sure that segment/control/debug/test/MMX
2892 registers are coded into the i.rm.reg field. */
2897 & (Reg
| RegMMX
| RegXMM
2899 | Control
| Debug
| Test
))
2902 & (Reg
| RegMMX
| RegXMM
2904 | Control
| Debug
| Test
))
2907 /* If there is an extension opcode to put here, the register
2908 number must be put into the regmem field. */
2909 if (i
.tm
.extension_opcode
!= None
)
2911 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2912 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2917 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2918 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2922 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2923 must set it to 3 to indicate this is a register operand
2924 in the regmem field. */
2925 if (!i
.mem_operands
)
2929 /* Fill in i.rm.reg field with extension opcode (if any). */
2930 if (i
.tm
.extension_opcode
!= None
)
2931 i
.rm
.reg
= i
.tm
.extension_opcode
;
2942 relax_substateT subtype
;
2947 if (flag_code
== CODE_16BIT
)
2951 if (i
.prefix
[DATA_PREFIX
] != 0)
2957 /* Pentium4 branch hints. */
2958 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2959 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2964 if (i
.prefix
[REX_PREFIX
] != 0)
2970 if (i
.prefixes
!= 0 && !intel_syntax
)
2971 as_warn (_("skipping prefixes on this instruction"));
2973 /* It's always a symbol; End frag & setup for relax.
2974 Make sure there is enough room in this frag for the largest
2975 instruction we may generate in md_convert_frag. This is 2
2976 bytes for the opcode and room for the prefix and largest
2978 frag_grow (prefix
+ 2 + 4);
2979 /* Prefix and 1 opcode byte go in fr_fix. */
2980 p
= frag_more (prefix
+ 1);
2981 if (i
.prefix
[DATA_PREFIX
] != 0)
2982 *p
++ = DATA_PREFIX_OPCODE
;
2983 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2984 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2985 *p
++ = i
.prefix
[SEG_PREFIX
];
2986 if (i
.prefix
[REX_PREFIX
] != 0)
2987 *p
++ = i
.prefix
[REX_PREFIX
];
2988 *p
= i
.tm
.base_opcode
;
2990 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2991 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2992 else if ((cpu_arch_flags
& Cpu386
) != 0)
2993 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2995 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2998 sym
= i
.op
[0].disps
->X_add_symbol
;
2999 off
= i
.op
[0].disps
->X_add_number
;
3001 if (i
.op
[0].disps
->X_op
!= O_constant
3002 && i
.op
[0].disps
->X_op
!= O_symbol
)
3004 /* Handle complex expressions. */
3005 sym
= make_expr_symbol (i
.op
[0].disps
);
3009 /* 1 possible extra opcode + 4 byte displacement go in var part.
3010 Pass reloc in fr_var. */
3011 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3021 if (i
.tm
.opcode_modifier
& JumpByte
)
3023 /* This is a loop or jecxz type instruction. */
3025 if (i
.prefix
[ADDR_PREFIX
] != 0)
3027 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3030 /* Pentium4 branch hints. */
3031 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3032 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3034 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3043 if (flag_code
== CODE_16BIT
)
3046 if (i
.prefix
[DATA_PREFIX
] != 0)
3048 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3058 if (i
.prefix
[REX_PREFIX
] != 0)
3060 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3064 if (i
.prefixes
!= 0 && !intel_syntax
)
3065 as_warn (_("skipping prefixes on this instruction"));
3067 p
= frag_more (1 + size
);
3068 *p
++ = i
.tm
.base_opcode
;
3070 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3071 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3073 /* All jumps handled here are signed, but don't use a signed limit
3074 check for 32 and 16 bit jumps as we want to allow wrap around at
3075 4G and 64k respectively. */
3077 fixP
->fx_signed
= 1;
3081 output_interseg_jump ()
3089 if (flag_code
== CODE_16BIT
)
3093 if (i
.prefix
[DATA_PREFIX
] != 0)
3099 if (i
.prefix
[REX_PREFIX
] != 0)
3109 if (i
.prefixes
!= 0 && !intel_syntax
)
3110 as_warn (_("skipping prefixes on this instruction"));
3112 /* 1 opcode; 2 segment; offset */
3113 p
= frag_more (prefix
+ 1 + 2 + size
);
3115 if (i
.prefix
[DATA_PREFIX
] != 0)
3116 *p
++ = DATA_PREFIX_OPCODE
;
3118 if (i
.prefix
[REX_PREFIX
] != 0)
3119 *p
++ = i
.prefix
[REX_PREFIX
];
3121 *p
++ = i
.tm
.base_opcode
;
3122 if (i
.op
[1].imms
->X_op
== O_constant
)
3124 offsetT n
= i
.op
[1].imms
->X_add_number
;
3127 && !fits_in_unsigned_word (n
)
3128 && !fits_in_signed_word (n
))
3130 as_bad (_("16-bit jump out of range"));
3133 md_number_to_chars (p
, n
, size
);
3136 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3137 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3138 if (i
.op
[0].imms
->X_op
!= O_constant
)
3139 as_bad (_("can't handle non absolute segment in `%s'"),
3141 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3147 fragS
*insn_start_frag
;
3148 offsetT insn_start_off
;
3150 /* Tie dwarf2 debug info to the address at the start of the insn.
3151 We can't do this after the insn has been output as the current
3152 frag may have been closed off. eg. by frag_var. */
3153 dwarf2_emit_insn (0);
3155 insn_start_frag
= frag_now
;
3156 insn_start_off
= frag_now_fix ();
3159 if (i
.tm
.opcode_modifier
& Jump
)
3161 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3163 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3164 output_interseg_jump ();
3167 /* Output normal instructions here. */
3171 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3172 have 3 bytes. We may use one more higher byte to specify a prefix
3173 the instruction requires. */
3174 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0
3175 && (i
.tm
.base_opcode
& 0xff000000) != 0)
3177 unsigned int prefix
;
3178 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3180 if (prefix
!= REPE_PREFIX_OPCODE
3181 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3182 add_prefix (prefix
);
3185 if ((i
.tm
.cpu_flags
& CpuPadLock
) == 0
3186 && (i
.tm
.base_opcode
& 0xff0000) != 0)
3187 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3189 /* The prefix bytes. */
3191 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3197 md_number_to_chars (p
, (valueT
) *q
, 1);
3201 /* Now the opcode; be careful about word order here! */
3202 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3204 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3208 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3211 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3216 /* Put out high byte first: can't use md_number_to_chars! */
3217 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3218 *p
= i
.tm
.base_opcode
& 0xff;
3221 /* Now the modrm byte and sib byte (if present). */
3222 if (i
.tm
.opcode_modifier
& Modrm
)
3225 md_number_to_chars (p
,
3226 (valueT
) (i
.rm
.regmem
<< 0
3230 /* If i.rm.regmem == ESP (4)
3231 && i.rm.mode != (Register mode)
3233 ==> need second modrm byte. */
3234 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3236 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3239 md_number_to_chars (p
,
3240 (valueT
) (i
.sib
.base
<< 0
3242 | i
.sib
.scale
<< 6),
3247 if (i
.disp_operands
)
3248 output_disp (insn_start_frag
, insn_start_off
);
3251 output_imm (insn_start_frag
, insn_start_off
);
3259 #endif /* DEBUG386 */
3263 output_disp (insn_start_frag
, insn_start_off
)
3264 fragS
*insn_start_frag
;
3265 offsetT insn_start_off
;
3270 for (n
= 0; n
< i
.operands
; n
++)
3272 if (i
.types
[n
] & Disp
)
3274 if (i
.op
[n
].disps
->X_op
== O_constant
)
3280 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3283 if (i
.types
[n
] & Disp8
)
3285 if (i
.types
[n
] & Disp64
)
3288 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3290 p
= frag_more (size
);
3291 md_number_to_chars (p
, val
, size
);
3295 enum bfd_reloc_code_real reloc_type
;
3298 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3300 /* The PC relative address is computed relative
3301 to the instruction boundary, so in case immediate
3302 fields follows, we need to adjust the value. */
3303 if (pcrel
&& i
.imm_operands
)
3308 for (n1
= 0; n1
< i
.operands
; n1
++)
3309 if (i
.types
[n1
] & Imm
)
3311 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3314 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3316 if (i
.types
[n1
] & Imm64
)
3321 /* We should find the immediate. */
3322 if (n1
== i
.operands
)
3324 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3327 if (i
.types
[n
] & Disp32S
)
3330 if (i
.types
[n
] & (Disp16
| Disp64
))
3333 if (i
.types
[n
] & Disp64
)
3337 p
= frag_more (size
);
3338 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3339 if (reloc_type
== BFD_RELOC_32
3341 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3342 && (i
.op
[n
].disps
->X_op
== O_symbol
3343 || (i
.op
[n
].disps
->X_op
== O_add
3344 && ((symbol_get_value_expression
3345 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3350 if (insn_start_frag
== frag_now
)
3351 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3356 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3357 for (fr
= insn_start_frag
->fr_next
;
3358 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3360 add
+= p
- frag_now
->fr_literal
;
3363 /* We don't support dynamic linking on x86-64 yet. */
3364 if (flag_code
== CODE_64BIT
)
3366 reloc_type
= BFD_RELOC_386_GOTPC
;
3367 i
.op
[n
].disps
->X_add_number
+= add
;
3369 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3370 i
.op
[n
].disps
, pcrel
, reloc_type
);
3377 output_imm (insn_start_frag
, insn_start_off
)
3378 fragS
*insn_start_frag
;
3379 offsetT insn_start_off
;
3384 for (n
= 0; n
< i
.operands
; n
++)
3386 if (i
.types
[n
] & Imm
)
3388 if (i
.op
[n
].imms
->X_op
== O_constant
)
3394 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3397 if (i
.types
[n
] & (Imm8
| Imm8S
))
3399 else if (i
.types
[n
] & Imm64
)
3402 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3404 p
= frag_more (size
);
3405 md_number_to_chars (p
, val
, size
);
3409 /* Not absolute_section.
3410 Need a 32-bit fixup (don't support 8bit
3411 non-absolute imms). Try to support other
3413 enum bfd_reloc_code_real reloc_type
;
3417 if ((i
.types
[n
] & (Imm32S
))
3418 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3420 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3423 if (i
.types
[n
] & (Imm8
| Imm8S
))
3425 if (i
.types
[n
] & Imm64
)
3429 p
= frag_more (size
);
3430 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3432 /* This is tough to explain. We end up with this one if we
3433 * have operands that look like
3434 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3435 * obtain the absolute address of the GOT, and it is strongly
3436 * preferable from a performance point of view to avoid using
3437 * a runtime relocation for this. The actual sequence of
3438 * instructions often look something like:
3443 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3445 * The call and pop essentially return the absolute address
3446 * of the label .L66 and store it in %ebx. The linker itself
3447 * will ultimately change the first operand of the addl so
3448 * that %ebx points to the GOT, but to keep things simple, the
3449 * .o file must have this operand set so that it generates not
3450 * the absolute address of .L66, but the absolute address of
3451 * itself. This allows the linker itself simply treat a GOTPC
3452 * relocation as asking for a pcrel offset to the GOT to be
3453 * added in, and the addend of the relocation is stored in the
3454 * operand field for the instruction itself.
3456 * Our job here is to fix the operand so that it would add
3457 * the correct offset so that %ebx would point to itself. The
3458 * thing that is tricky is that .-.L66 will point to the
3459 * beginning of the instruction, so we need to further modify
3460 * the operand so that it will point to itself. There are
3461 * other cases where you have something like:
3463 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3465 * and here no correction would be required. Internally in
3466 * the assembler we treat operands of this form as not being
3467 * pcrel since the '.' is explicitly mentioned, and I wonder
3468 * whether it would simplify matters to do it this way. Who
3469 * knows. In earlier versions of the PIC patches, the
3470 * pcrel_adjust field was used to store the correction, but
3471 * since the expression is not pcrel, I felt it would be
3472 * confusing to do it this way. */
3474 if (reloc_type
== BFD_RELOC_32
3476 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3477 && (i
.op
[n
].imms
->X_op
== O_symbol
3478 || (i
.op
[n
].imms
->X_op
== O_add
3479 && ((symbol_get_value_expression
3480 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3485 if (insn_start_frag
== frag_now
)
3486 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3491 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3492 for (fr
= insn_start_frag
->fr_next
;
3493 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3495 add
+= p
- frag_now
->fr_literal
;
3498 /* We don't support dynamic linking on x86-64 yet. */
3499 if (flag_code
== CODE_64BIT
)
3501 reloc_type
= BFD_RELOC_386_GOTPC
;
3502 i
.op
[n
].imms
->X_add_number
+= add
;
3504 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3505 i
.op
[n
].imms
, 0, reloc_type
);
3512 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3514 /* Parse operands of the form
3515 <symbol>@GOTOFF+<nnn>
3516 and similar .plt or .got references.
3518 If we find one, set up the correct relocation in RELOC and copy the
3519 input string, minus the `@GOTOFF' into a malloc'd buffer for
3520 parsing by the calling routine. Return this buffer, and if ADJUST
3521 is non-null set it to the length of the string we removed from the
3522 input line. Otherwise return NULL. */
3524 lex_got (reloc
, adjust
)
3525 enum bfd_reloc_code_real
*reloc
;
3528 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3529 static const struct {
3531 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3533 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3534 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3535 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3536 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3537 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3538 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3539 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3540 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3541 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3542 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3543 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3544 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3545 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3550 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3551 if (is_end_of_line
[(unsigned char) *cp
])
3554 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3558 len
= strlen (gotrel
[j
].str
);
3559 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3561 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3564 char *tmpbuf
, *past_reloc
;
3566 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3570 if (GOT_symbol
== NULL
)
3571 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3573 /* Replace the relocation token with ' ', so that
3574 errors like foo@GOTOFF1 will be detected. */
3576 /* The length of the first part of our input line. */
3577 first
= cp
- input_line_pointer
;
3579 /* The second part goes from after the reloc token until
3580 (and including) an end_of_line char. Don't use strlen
3581 here as the end_of_line char may not be a NUL. */
3582 past_reloc
= cp
+ 1 + len
;
3583 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3585 second
= cp
- past_reloc
;
3587 /* Allocate and copy string. The trailing NUL shouldn't
3588 be necessary, but be safe. */
3589 tmpbuf
= xmalloc (first
+ second
+ 2);
3590 memcpy (tmpbuf
, input_line_pointer
, first
);
3591 tmpbuf
[first
] = ' ';
3592 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3593 tmpbuf
[first
+ second
+ 1] = '\0';
3597 as_bad (_("@%s reloc is not supported in %s bit mode"),
3598 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3603 /* Might be a symbol version string. Don't as_bad here. */
3607 /* x86_cons_fix_new is called via the expression parsing code when a
3608 reloc is needed. We use this hook to get the correct .got reloc. */
3609 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3612 x86_cons_fix_new (frag
, off
, len
, exp
)
3618 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3619 got_reloc
= NO_RELOC
;
3620 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3624 x86_cons (exp
, size
)
3630 /* Handle @GOTOFF and the like in an expression. */
3632 char *gotfree_input_line
;
3635 save
= input_line_pointer
;
3636 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3637 if (gotfree_input_line
)
3638 input_line_pointer
= gotfree_input_line
;
3642 if (gotfree_input_line
)
3644 /* expression () has merrily parsed up to the end of line,
3645 or a comma - in the wrong buffer. Transfer how far
3646 input_line_pointer has moved to the right buffer. */
3647 input_line_pointer
= (save
3648 + (input_line_pointer
- gotfree_input_line
)
3650 free (gotfree_input_line
);
3660 #define O_secrel (O_max + 1)
3663 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3669 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3671 if (exp
->X_op
== O_secrel
)
3673 exp
->X_op
= O_symbol
;
3674 r
= BFD_RELOC_32_SECREL
;
3677 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3681 pe_directive_secrel (dummy
)
3682 int dummy ATTRIBUTE_UNUSED
;
3689 if (exp
.X_op
== O_symbol
)
3690 exp
.X_op
= O_secrel
;
3692 emit_expr (&exp
, 4);
3694 while (*input_line_pointer
++ == ',');
3696 input_line_pointer
--;
3697 demand_empty_rest_of_line ();
3702 static int i386_immediate
PARAMS ((char *));
3705 i386_immediate (imm_start
)
3708 char *save_input_line_pointer
;
3710 char *gotfree_input_line
;
3715 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3717 as_bad (_("only 1 or 2 immediate operands are allowed"));
3721 exp
= &im_expressions
[i
.imm_operands
++];
3722 i
.op
[this_operand
].imms
= exp
;
3724 if (is_space_char (*imm_start
))
3727 save_input_line_pointer
= input_line_pointer
;
3728 input_line_pointer
= imm_start
;
3731 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3732 if (gotfree_input_line
)
3733 input_line_pointer
= gotfree_input_line
;
3736 exp_seg
= expression (exp
);
3739 if (*input_line_pointer
)
3740 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3742 input_line_pointer
= save_input_line_pointer
;
3744 if (gotfree_input_line
)
3745 free (gotfree_input_line
);
3748 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3750 /* Missing or bad expr becomes absolute 0. */
3751 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3753 exp
->X_op
= O_constant
;
3754 exp
->X_add_number
= 0;
3755 exp
->X_add_symbol
= (symbolS
*) 0;
3756 exp
->X_op_symbol
= (symbolS
*) 0;
3758 else if (exp
->X_op
== O_constant
)
3760 /* Size it properly later. */
3761 i
.types
[this_operand
] |= Imm64
;
3762 /* If BFD64, sign extend val. */
3763 if (!use_rela_relocations
)
3764 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3765 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3767 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3768 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3769 && exp_seg
!= absolute_section
3770 && exp_seg
!= text_section
3771 && exp_seg
!= data_section
3772 && exp_seg
!= bss_section
3773 && exp_seg
!= undefined_section
3774 && !bfd_is_com_section (exp_seg
))
3776 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3782 /* This is an address. The size of the address will be
3783 determined later, depending on destination register,
3784 suffix, or the default for the section. */
3785 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3791 static char *i386_scale
PARAMS ((char *));
3798 char *save
= input_line_pointer
;
3800 input_line_pointer
= scale
;
3801 val
= get_absolute_expression ();
3807 i
.log2_scale_factor
= 0;
3810 i
.log2_scale_factor
= 1;
3813 i
.log2_scale_factor
= 2;
3816 i
.log2_scale_factor
= 3;
3819 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3821 input_line_pointer
= save
;
3824 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3826 as_warn (_("scale factor of %d without an index register"),
3827 1 << i
.log2_scale_factor
);
3828 #if SCALE1_WHEN_NO_INDEX
3829 i
.log2_scale_factor
= 0;
3832 scale
= input_line_pointer
;
3833 input_line_pointer
= save
;
3837 static int i386_displacement
PARAMS ((char *, char *));
3840 i386_displacement (disp_start
, disp_end
)
3846 char *save_input_line_pointer
;
3848 char *gotfree_input_line
;
3850 int bigdisp
= Disp32
;
3852 if (flag_code
== CODE_64BIT
)
3854 if (i
.prefix
[ADDR_PREFIX
] == 0)
3857 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3859 i
.types
[this_operand
] |= bigdisp
;
3861 exp
= &disp_expressions
[i
.disp_operands
];
3862 i
.op
[this_operand
].disps
= exp
;
3864 save_input_line_pointer
= input_line_pointer
;
3865 input_line_pointer
= disp_start
;
3866 END_STRING_AND_SAVE (disp_end
);
3868 #ifndef GCC_ASM_O_HACK
3869 #define GCC_ASM_O_HACK 0
3872 END_STRING_AND_SAVE (disp_end
+ 1);
3873 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3874 && displacement_string_end
[-1] == '+')
3876 /* This hack is to avoid a warning when using the "o"
3877 constraint within gcc asm statements.
3880 #define _set_tssldt_desc(n,addr,limit,type) \
3881 __asm__ __volatile__ ( \
3883 "movw %w1,2+%0\n\t" \
3885 "movb %b1,4+%0\n\t" \
3886 "movb %4,5+%0\n\t" \
3887 "movb $0,6+%0\n\t" \
3888 "movb %h1,7+%0\n\t" \
3890 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3892 This works great except that the output assembler ends
3893 up looking a bit weird if it turns out that there is
3894 no offset. You end up producing code that looks like:
3907 So here we provide the missing zero. */
3909 *displacement_string_end
= '0';
3913 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3914 if (gotfree_input_line
)
3915 input_line_pointer
= gotfree_input_line
;
3918 exp_seg
= expression (exp
);
3921 if (*input_line_pointer
)
3922 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3924 RESTORE_END_STRING (disp_end
+ 1);
3926 RESTORE_END_STRING (disp_end
);
3927 input_line_pointer
= save_input_line_pointer
;
3929 if (gotfree_input_line
)
3930 free (gotfree_input_line
);
3933 /* We do this to make sure that the section symbol is in
3934 the symbol table. We will ultimately change the relocation
3935 to be relative to the beginning of the section. */
3936 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3937 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3939 if (exp
->X_op
!= O_symbol
)
3941 as_bad (_("bad expression used with @%s"),
3942 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3948 if (S_IS_LOCAL (exp
->X_add_symbol
)
3949 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3950 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3951 exp
->X_op
= O_subtract
;
3952 exp
->X_op_symbol
= GOT_symbol
;
3953 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3954 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3956 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3959 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3961 /* Missing or bad expr becomes absolute 0. */
3962 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3964 exp
->X_op
= O_constant
;
3965 exp
->X_add_number
= 0;
3966 exp
->X_add_symbol
= (symbolS
*) 0;
3967 exp
->X_op_symbol
= (symbolS
*) 0;
3970 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3971 if (exp
->X_op
!= O_constant
3972 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3973 && exp_seg
!= absolute_section
3974 && exp_seg
!= text_section
3975 && exp_seg
!= data_section
3976 && exp_seg
!= bss_section
3977 && exp_seg
!= undefined_section
3978 && !bfd_is_com_section (exp_seg
))
3980 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3984 else if (flag_code
== CODE_64BIT
)
3985 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3989 static int i386_index_check
PARAMS ((const char *));
3991 /* Make sure the memory operand we've been dealt is valid.
3992 Return 1 on success, 0 on a failure. */
3995 i386_index_check (operand_string
)
3996 const char *operand_string
;
3999 #if INFER_ADDR_PREFIX
4005 if (flag_code
== CODE_64BIT
)
4007 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4010 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4011 && (i
.base_reg
->reg_type
!= BaseIndex
4014 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4015 != (RegXX
| BaseIndex
))))
4020 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4024 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4025 != (Reg16
| BaseIndex
)))
4027 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4028 != (Reg16
| BaseIndex
))
4030 && i
.base_reg
->reg_num
< 6
4031 && i
.index_reg
->reg_num
>= 6
4032 && i
.log2_scale_factor
== 0))))
4039 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4041 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4042 != (Reg32
| BaseIndex
))))
4048 #if INFER_ADDR_PREFIX
4049 if (i
.prefix
[ADDR_PREFIX
] == 0)
4051 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4053 /* Change the size of any displacement too. At most one of
4054 Disp16 or Disp32 is set.
4055 FIXME. There doesn't seem to be any real need for separate
4056 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4057 Removing them would probably clean up the code quite a lot. */
4058 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4059 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4064 as_bad (_("`%s' is not a valid base/index expression"),
4068 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4070 flag_code_names
[flag_code
]);
4075 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4079 i386_operand (operand_string
)
4080 char *operand_string
;
4084 char *op_string
= operand_string
;
4086 if (is_space_char (*op_string
))
4089 /* We check for an absolute prefix (differentiating,
4090 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4091 if (*op_string
== ABSOLUTE_PREFIX
)
4094 if (is_space_char (*op_string
))
4096 i
.types
[this_operand
] |= JumpAbsolute
;
4099 /* Check if operand is a register. */
4100 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4101 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4103 /* Check for a segment override by searching for ':' after a
4104 segment register. */
4106 if (is_space_char (*op_string
))
4108 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4113 i
.seg
[i
.mem_operands
] = &es
;
4116 i
.seg
[i
.mem_operands
] = &cs
;
4119 i
.seg
[i
.mem_operands
] = &ss
;
4122 i
.seg
[i
.mem_operands
] = &ds
;
4125 i
.seg
[i
.mem_operands
] = &fs
;
4128 i
.seg
[i
.mem_operands
] = &gs
;
4132 /* Skip the ':' and whitespace. */
4134 if (is_space_char (*op_string
))
4137 if (!is_digit_char (*op_string
)
4138 && !is_identifier_char (*op_string
)
4139 && *op_string
!= '('
4140 && *op_string
!= ABSOLUTE_PREFIX
)
4142 as_bad (_("bad memory operand `%s'"), op_string
);
4145 /* Handle case of %es:*foo. */
4146 if (*op_string
== ABSOLUTE_PREFIX
)
4149 if (is_space_char (*op_string
))
4151 i
.types
[this_operand
] |= JumpAbsolute
;
4153 goto do_memory_reference
;
4157 as_bad (_("junk `%s' after register"), op_string
);
4160 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4161 i
.op
[this_operand
].regs
= r
;
4164 else if (*op_string
== REGISTER_PREFIX
)
4166 as_bad (_("bad register name `%s'"), op_string
);
4169 else if (*op_string
== IMMEDIATE_PREFIX
)
4172 if (i
.types
[this_operand
] & JumpAbsolute
)
4174 as_bad (_("immediate operand illegal with absolute jump"));
4177 if (!i386_immediate (op_string
))
4180 else if (is_digit_char (*op_string
)
4181 || is_identifier_char (*op_string
)
4182 || *op_string
== '(')
4184 /* This is a memory reference of some sort. */
4187 /* Start and end of displacement string expression (if found). */
4188 char *displacement_string_start
;
4189 char *displacement_string_end
;
4191 do_memory_reference
:
4192 if ((i
.mem_operands
== 1
4193 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4194 || i
.mem_operands
== 2)
4196 as_bad (_("too many memory references for `%s'"),
4197 current_templates
->start
->name
);
4201 /* Check for base index form. We detect the base index form by
4202 looking for an ')' at the end of the operand, searching
4203 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4205 base_string
= op_string
+ strlen (op_string
);
4208 if (is_space_char (*base_string
))
4211 /* If we only have a displacement, set-up for it to be parsed later. */
4212 displacement_string_start
= op_string
;
4213 displacement_string_end
= base_string
+ 1;
4215 if (*base_string
== ')')
4218 unsigned int parens_balanced
= 1;
4219 /* We've already checked that the number of left & right ()'s are
4220 equal, so this loop will not be infinite. */
4224 if (*base_string
== ')')
4226 if (*base_string
== '(')
4229 while (parens_balanced
);
4231 temp_string
= base_string
;
4233 /* Skip past '(' and whitespace. */
4235 if (is_space_char (*base_string
))
4238 if (*base_string
== ','
4239 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4240 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4242 displacement_string_end
= temp_string
;
4244 i
.types
[this_operand
] |= BaseIndex
;
4248 base_string
= end_op
;
4249 if (is_space_char (*base_string
))
4253 /* There may be an index reg or scale factor here. */
4254 if (*base_string
== ',')
4257 if (is_space_char (*base_string
))
4260 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4261 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4263 base_string
= end_op
;
4264 if (is_space_char (*base_string
))
4266 if (*base_string
== ',')
4269 if (is_space_char (*base_string
))
4272 else if (*base_string
!= ')')
4274 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4279 else if (*base_string
== REGISTER_PREFIX
)
4281 as_bad (_("bad register name `%s'"), base_string
);
4285 /* Check for scale factor. */
4286 if (*base_string
!= ')')
4288 char *end_scale
= i386_scale (base_string
);
4293 base_string
= end_scale
;
4294 if (is_space_char (*base_string
))
4296 if (*base_string
!= ')')
4298 as_bad (_("expecting `)' after scale factor in `%s'"),
4303 else if (!i
.index_reg
)
4305 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4310 else if (*base_string
!= ')')
4312 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4317 else if (*base_string
== REGISTER_PREFIX
)
4319 as_bad (_("bad register name `%s'"), base_string
);
4324 /* If there's an expression beginning the operand, parse it,
4325 assuming displacement_string_start and
4326 displacement_string_end are meaningful. */
4327 if (displacement_string_start
!= displacement_string_end
)
4329 if (!i386_displacement (displacement_string_start
,
4330 displacement_string_end
))
4334 /* Special case for (%dx) while doing input/output op. */
4336 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4338 && i
.log2_scale_factor
== 0
4339 && i
.seg
[i
.mem_operands
] == 0
4340 && (i
.types
[this_operand
] & Disp
) == 0)
4342 i
.types
[this_operand
] = InOutPortReg
;
4346 if (i386_index_check (operand_string
) == 0)
4352 /* It's not a memory operand; argh! */
4353 as_bad (_("invalid char %s beginning operand %d `%s'"),
4354 output_invalid (*op_string
),
4359 return 1; /* Normal return. */
4362 /* md_estimate_size_before_relax()
4364 Called just before relax() for rs_machine_dependent frags. The x86
4365 assembler uses these frags to handle variable size jump
4368 Any symbol that is now undefined will not become defined.
4369 Return the correct fr_subtype in the frag.
4370 Return the initial "guess for variable size of frag" to caller.
4371 The guess is actually the growth beyond the fixed part. Whatever
4372 we do to grow the fixed or variable part contributes to our
4376 md_estimate_size_before_relax (fragP
, segment
)
4380 /* We've already got fragP->fr_subtype right; all we have to do is
4381 check for un-relaxable symbols. On an ELF system, we can't relax
4382 an externally visible symbol, because it may be overridden by a
4384 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4386 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4387 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4388 || S_IS_WEAK (fragP
->fr_symbol
)))
4392 /* Symbol is undefined in this segment, or we need to keep a
4393 reloc so that weak symbols can be overridden. */
4394 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4395 enum bfd_reloc_code_real reloc_type
;
4396 unsigned char *opcode
;
4399 if (fragP
->fr_var
!= NO_RELOC
)
4400 reloc_type
= fragP
->fr_var
;
4402 reloc_type
= BFD_RELOC_16_PCREL
;
4404 reloc_type
= BFD_RELOC_32_PCREL
;
4406 old_fr_fix
= fragP
->fr_fix
;
4407 opcode
= (unsigned char *) fragP
->fr_opcode
;
4409 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4412 /* Make jmp (0xeb) a (d)word displacement jump. */
4414 fragP
->fr_fix
+= size
;
4415 fix_new (fragP
, old_fr_fix
, size
,
4417 fragP
->fr_offset
, 1,
4423 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4425 /* Negate the condition, and branch past an
4426 unconditional jump. */
4429 /* Insert an unconditional jump. */
4431 /* We added two extra opcode bytes, and have a two byte
4433 fragP
->fr_fix
+= 2 + 2;
4434 fix_new (fragP
, old_fr_fix
+ 2, 2,
4436 fragP
->fr_offset
, 1,
4443 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4448 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4450 fragP
->fr_offset
, 1,
4452 fixP
->fx_signed
= 1;
4456 /* This changes the byte-displacement jump 0x7N
4457 to the (d)word-displacement jump 0x0f,0x8N. */
4458 opcode
[1] = opcode
[0] + 0x10;
4459 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4460 /* We've added an opcode byte. */
4461 fragP
->fr_fix
+= 1 + size
;
4462 fix_new (fragP
, old_fr_fix
+ 1, size
,
4464 fragP
->fr_offset
, 1,
4469 BAD_CASE (fragP
->fr_subtype
);
4473 return fragP
->fr_fix
- old_fr_fix
;
4476 /* Guess size depending on current relax state. Initially the relax
4477 state will correspond to a short jump and we return 1, because
4478 the variable part of the frag (the branch offset) is one byte
4479 long. However, we can relax a section more than once and in that
4480 case we must either set fr_subtype back to the unrelaxed state,
4481 or return the value for the appropriate branch. */
4482 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4485 /* Called after relax() is finished.
4487 In: Address of frag.
4488 fr_type == rs_machine_dependent.
4489 fr_subtype is what the address relaxed to.
4491 Out: Any fixSs and constants are set up.
4492 Caller will turn frag into a ".space 0". */
4495 md_convert_frag (abfd
, sec
, fragP
)
4496 bfd
*abfd ATTRIBUTE_UNUSED
;
4497 segT sec ATTRIBUTE_UNUSED
;
4500 unsigned char *opcode
;
4501 unsigned char *where_to_put_displacement
= NULL
;
4502 offsetT target_address
;
4503 offsetT opcode_address
;
4504 unsigned int extension
= 0;
4505 offsetT displacement_from_opcode_start
;
4507 opcode
= (unsigned char *) fragP
->fr_opcode
;
4509 /* Address we want to reach in file space. */
4510 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4512 /* Address opcode resides at in file space. */
4513 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4515 /* Displacement from opcode start to fill into instruction. */
4516 displacement_from_opcode_start
= target_address
- opcode_address
;
4518 if ((fragP
->fr_subtype
& BIG
) == 0)
4520 /* Don't have to change opcode. */
4521 extension
= 1; /* 1 opcode + 1 displacement */
4522 where_to_put_displacement
= &opcode
[1];
4526 if (no_cond_jump_promotion
4527 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4528 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4530 switch (fragP
->fr_subtype
)
4532 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4533 extension
= 4; /* 1 opcode + 4 displacement */
4535 where_to_put_displacement
= &opcode
[1];
4538 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4539 extension
= 2; /* 1 opcode + 2 displacement */
4541 where_to_put_displacement
= &opcode
[1];
4544 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4545 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4546 extension
= 5; /* 2 opcode + 4 displacement */
4547 opcode
[1] = opcode
[0] + 0x10;
4548 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4549 where_to_put_displacement
= &opcode
[2];
4552 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4553 extension
= 3; /* 2 opcode + 2 displacement */
4554 opcode
[1] = opcode
[0] + 0x10;
4555 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4556 where_to_put_displacement
= &opcode
[2];
4559 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4564 where_to_put_displacement
= &opcode
[3];
4568 BAD_CASE (fragP
->fr_subtype
);
4573 /* Now put displacement after opcode. */
4574 md_number_to_chars ((char *) where_to_put_displacement
,
4575 (valueT
) (displacement_from_opcode_start
- extension
),
4576 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4577 fragP
->fr_fix
+= extension
;
4580 /* Size of byte displacement jmp. */
4581 int md_short_jump_size
= 2;
4583 /* Size of dword displacement jmp. */
4584 int md_long_jump_size
= 5;
4586 /* Size of relocation record. */
4587 const int md_reloc_size
= 8;
4590 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4592 addressT from_addr
, to_addr
;
4593 fragS
*frag ATTRIBUTE_UNUSED
;
4594 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4598 offset
= to_addr
- (from_addr
+ 2);
4599 /* Opcode for byte-disp jump. */
4600 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4601 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4605 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4607 addressT from_addr
, to_addr
;
4608 fragS
*frag ATTRIBUTE_UNUSED
;
4609 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4613 offset
= to_addr
- (from_addr
+ 5);
4614 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4615 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4618 /* Apply a fixup (fixS) to segment data, once it has been determined
4619 by our caller that we have all the info we need to fix it up.
4621 On the 386, immediates, displacements, and data pointers are all in
4622 the same (little-endian) format, so we don't need to care about which
4626 md_apply_fix3 (fixP
, valP
, seg
)
4627 /* The fix we're to put in. */
4629 /* Pointer to the value of the bits. */
4631 /* Segment fix is from. */
4632 segT seg ATTRIBUTE_UNUSED
;
4634 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4635 valueT value
= *valP
;
4637 #if !defined (TE_Mach)
4640 switch (fixP
->fx_r_type
)
4646 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4649 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4652 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4657 if (fixP
->fx_addsy
!= NULL
4658 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4659 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4660 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4661 && !use_rela_relocations
)
4663 /* This is a hack. There should be a better way to handle this.
4664 This covers for the fact that bfd_install_relocation will
4665 subtract the current location (for partial_inplace, PC relative
4666 relocations); see more below. */
4668 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4670 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4673 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4676 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4678 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4681 || (symbol_section_p (fixP
->fx_addsy
)
4682 && sym_seg
!= absolute_section
))
4683 && !generic_force_reloc (fixP
))
4685 /* Yes, we add the values in twice. This is because
4686 bfd_install_relocation subtracts them out again. I think
4687 bfd_install_relocation is broken, but I don't dare change
4689 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4693 #if defined (OBJ_COFF) && defined (TE_PE)
4694 /* For some reason, the PE format does not store a section
4695 address offset for a PC relative symbol. */
4696 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4697 value
+= md_pcrel_from (fixP
);
4701 /* Fix a few things - the dynamic linker expects certain values here,
4702 and we must not disappoint it. */
4703 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4704 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4706 switch (fixP
->fx_r_type
)
4708 case BFD_RELOC_386_PLT32
:
4709 case BFD_RELOC_X86_64_PLT32
:
4710 /* Make the jump instruction point to the address of the operand. At
4711 runtime we merely add the offset to the actual PLT entry. */
4715 case BFD_RELOC_386_TLS_GD
:
4716 case BFD_RELOC_386_TLS_LDM
:
4717 case BFD_RELOC_386_TLS_IE_32
:
4718 case BFD_RELOC_386_TLS_IE
:
4719 case BFD_RELOC_386_TLS_GOTIE
:
4720 case BFD_RELOC_X86_64_TLSGD
:
4721 case BFD_RELOC_X86_64_TLSLD
:
4722 case BFD_RELOC_X86_64_GOTTPOFF
:
4723 value
= 0; /* Fully resolved at runtime. No addend. */
4725 case BFD_RELOC_386_TLS_LE
:
4726 case BFD_RELOC_386_TLS_LDO_32
:
4727 case BFD_RELOC_386_TLS_LE_32
:
4728 case BFD_RELOC_X86_64_DTPOFF32
:
4729 case BFD_RELOC_X86_64_TPOFF32
:
4730 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4733 case BFD_RELOC_386_GOT32
:
4734 case BFD_RELOC_X86_64_GOT32
:
4735 value
= 0; /* Fully resolved at runtime. No addend. */
4738 case BFD_RELOC_VTABLE_INHERIT
:
4739 case BFD_RELOC_VTABLE_ENTRY
:
4746 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4748 #endif /* !defined (TE_Mach) */
4750 /* Are we finished with this relocation now? */
4751 if (fixP
->fx_addsy
== NULL
)
4753 else if (use_rela_relocations
)
4755 fixP
->fx_no_overflow
= 1;
4756 /* Remember value for tc_gen_reloc. */
4757 fixP
->fx_addnumber
= value
;
4761 md_number_to_chars (p
, value
, fixP
->fx_size
);
4764 #define MAX_LITTLENUMS 6
4766 /* Turn the string pointed to by litP into a floating point constant
4767 of type TYPE, and emit the appropriate bytes. The number of
4768 LITTLENUMS emitted is stored in *SIZEP. An error message is
4769 returned, or NULL on OK. */
4772 md_atof (type
, litP
, sizeP
)
4778 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4779 LITTLENUM_TYPE
*wordP
;
4801 return _("Bad call to md_atof ()");
4803 t
= atof_ieee (input_line_pointer
, type
, words
);
4805 input_line_pointer
= t
;
4807 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4808 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4809 the bigendian 386. */
4810 for (wordP
= words
+ prec
- 1; prec
--;)
4812 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4813 litP
+= sizeof (LITTLENUM_TYPE
);
4818 char output_invalid_buf
[8];
4825 sprintf (output_invalid_buf
, "'%c'", c
);
4827 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4828 return output_invalid_buf
;
4831 /* REG_STRING starts *before* REGISTER_PREFIX. */
4833 static const reg_entry
*
4834 parse_register (reg_string
, end_op
)
4838 char *s
= reg_string
;
4840 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4843 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4844 if (*s
== REGISTER_PREFIX
)
4847 if (is_space_char (*s
))
4851 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4853 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4854 return (const reg_entry
*) NULL
;
4858 /* For naked regs, make sure that we are not dealing with an identifier.
4859 This prevents confusing an identifier like `eax_var' with register
4861 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4862 return (const reg_entry
*) NULL
;
4866 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4868 /* Handle floating point regs, allowing spaces in the (i) part. */
4869 if (r
== i386_regtab
/* %st is first entry of table */)
4871 if (is_space_char (*s
))
4876 if (is_space_char (*s
))
4878 if (*s
>= '0' && *s
<= '7')
4880 r
= &i386_float_regtab
[*s
- '0'];
4882 if (is_space_char (*s
))
4890 /* We have "%st(" then garbage. */
4891 return (const reg_entry
*) NULL
;
4896 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
4897 && flag_code
!= CODE_64BIT
)
4898 return (const reg_entry
*) NULL
;
4903 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4904 const char *md_shortopts
= "kVQ:sqn";
4906 const char *md_shortopts
= "qn";
4909 struct option md_longopts
[] = {
4910 #define OPTION_32 (OPTION_MD_BASE + 0)
4911 {"32", no_argument
, NULL
, OPTION_32
},
4912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4913 #define OPTION_64 (OPTION_MD_BASE + 1)
4914 {"64", no_argument
, NULL
, OPTION_64
},
4916 {NULL
, no_argument
, NULL
, 0}
4918 size_t md_longopts_size
= sizeof (md_longopts
);
4921 md_parse_option (c
, arg
)
4923 char *arg ATTRIBUTE_UNUSED
;
4928 optimize_align_code
= 0;
4935 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4936 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4937 should be emitted or not. FIXME: Not implemented. */
4941 /* -V: SVR4 argument to print version ID. */
4943 print_version_id ();
4946 /* -k: Ignore for FreeBSD compatibility. */
4951 /* -s: On i386 Solaris, this tells the native assembler to use
4952 .stab instead of .stab.excl. We always use .stab anyhow. */
4957 const char **list
, **l
;
4959 list
= bfd_target_list ();
4960 for (l
= list
; *l
!= NULL
; l
++)
4961 if (strcmp (*l
, "elf64-x86-64") == 0)
4963 default_arch
= "x86_64";
4967 as_fatal (_("No compiled in support for x86_64"));
4974 default_arch
= "i386";
4984 md_show_usage (stream
)
4987 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4988 fprintf (stream
, _("\
4990 -V print assembler version number\n\
4992 -n Do not optimize code alignment\n\
4993 -q quieten some warnings\n\
4996 fprintf (stream
, _("\
4997 -n Do not optimize code alignment\n\
4998 -q quieten some warnings\n"));
5002 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5003 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5005 /* Pick the target format to use. */
5008 i386_target_format ()
5010 if (!strcmp (default_arch
, "x86_64"))
5011 set_code_flag (CODE_64BIT
);
5012 else if (!strcmp (default_arch
, "i386"))
5013 set_code_flag (CODE_32BIT
);
5015 as_fatal (_("Unknown architecture"));
5016 switch (OUTPUT_FLAVOR
)
5018 #ifdef OBJ_MAYBE_AOUT
5019 case bfd_target_aout_flavour
:
5020 return AOUT_TARGET_FORMAT
;
5022 #ifdef OBJ_MAYBE_COFF
5023 case bfd_target_coff_flavour
:
5026 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5027 case bfd_target_elf_flavour
:
5029 if (flag_code
== CODE_64BIT
)
5030 use_rela_relocations
= 1;
5031 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5040 #endif /* OBJ_MAYBE_ more than one */
5042 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5043 void i386_elf_emit_arch_note ()
5045 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5046 && cpu_arch_name
!= NULL
)
5049 asection
*seg
= now_seg
;
5050 subsegT subseg
= now_subseg
;
5051 Elf_Internal_Note i_note
;
5052 Elf_External_Note e_note
;
5053 asection
*note_secp
;
5056 /* Create the .note section. */
5057 note_secp
= subseg_new (".note", 0);
5058 bfd_set_section_flags (stdoutput
,
5060 SEC_HAS_CONTENTS
| SEC_READONLY
);
5062 /* Process the arch string. */
5063 len
= strlen (cpu_arch_name
);
5065 i_note
.namesz
= len
+ 1;
5067 i_note
.type
= NT_ARCH
;
5068 p
= frag_more (sizeof (e_note
.namesz
));
5069 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5070 p
= frag_more (sizeof (e_note
.descsz
));
5071 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5072 p
= frag_more (sizeof (e_note
.type
));
5073 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5074 p
= frag_more (len
+ 1);
5075 strcpy (p
, cpu_arch_name
);
5077 frag_align (2, 0, 0);
5079 subseg_set (seg
, subseg
);
5085 md_undefined_symbol (name
)
5088 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5089 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5090 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5091 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5095 if (symbol_find (name
))
5096 as_bad (_("GOT already in symbol table"));
5097 GOT_symbol
= symbol_new (name
, undefined_section
,
5098 (valueT
) 0, &zero_address_frag
);
5105 /* Round up a section size to the appropriate boundary. */
5108 md_section_align (segment
, size
)
5109 segT segment ATTRIBUTE_UNUSED
;
5112 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5113 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5115 /* For a.out, force the section size to be aligned. If we don't do
5116 this, BFD will align it for us, but it will not write out the
5117 final bytes of the section. This may be a bug in BFD, but it is
5118 easier to fix it here since that is how the other a.out targets
5122 align
= bfd_get_section_alignment (stdoutput
, segment
);
5123 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5130 /* On the i386, PC-relative offsets are relative to the start of the
5131 next instruction. That is, the address of the offset, plus its
5132 size, since the offset is always the last part of the insn. */
5135 md_pcrel_from (fixP
)
5138 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5145 int ignore ATTRIBUTE_UNUSED
;
5149 temp
= get_absolute_expression ();
5150 subseg_set (bss_section
, (subsegT
) temp
);
5151 demand_empty_rest_of_line ();
5157 i386_validate_fix (fixp
)
5160 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5162 /* GOTOFF relocation are nonsense in 64bit mode. */
5163 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5165 if (flag_code
!= CODE_64BIT
)
5167 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5171 if (flag_code
== CODE_64BIT
)
5173 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5180 tc_gen_reloc (section
, fixp
)
5181 asection
*section ATTRIBUTE_UNUSED
;
5185 bfd_reloc_code_real_type code
;
5187 switch (fixp
->fx_r_type
)
5189 case BFD_RELOC_X86_64_PLT32
:
5190 case BFD_RELOC_X86_64_GOT32
:
5191 case BFD_RELOC_X86_64_GOTPCREL
:
5192 case BFD_RELOC_386_PLT32
:
5193 case BFD_RELOC_386_GOT32
:
5194 case BFD_RELOC_386_GOTOFF
:
5195 case BFD_RELOC_386_GOTPC
:
5196 case BFD_RELOC_386_TLS_GD
:
5197 case BFD_RELOC_386_TLS_LDM
:
5198 case BFD_RELOC_386_TLS_LDO_32
:
5199 case BFD_RELOC_386_TLS_IE_32
:
5200 case BFD_RELOC_386_TLS_IE
:
5201 case BFD_RELOC_386_TLS_GOTIE
:
5202 case BFD_RELOC_386_TLS_LE_32
:
5203 case BFD_RELOC_386_TLS_LE
:
5204 case BFD_RELOC_X86_64_32S
:
5205 case BFD_RELOC_X86_64_TLSGD
:
5206 case BFD_RELOC_X86_64_TLSLD
:
5207 case BFD_RELOC_X86_64_DTPOFF32
:
5208 case BFD_RELOC_X86_64_GOTTPOFF
:
5209 case BFD_RELOC_X86_64_TPOFF32
:
5211 case BFD_RELOC_VTABLE_ENTRY
:
5212 case BFD_RELOC_VTABLE_INHERIT
:
5214 case BFD_RELOC_32_SECREL
:
5216 code
= fixp
->fx_r_type
;
5221 switch (fixp
->fx_size
)
5224 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5225 _("can not do %d byte pc-relative relocation"),
5227 code
= BFD_RELOC_32_PCREL
;
5229 case 1: code
= BFD_RELOC_8_PCREL
; break;
5230 case 2: code
= BFD_RELOC_16_PCREL
; break;
5231 case 4: code
= BFD_RELOC_32_PCREL
; break;
5236 switch (fixp
->fx_size
)
5239 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5240 _("can not do %d byte relocation"),
5242 code
= BFD_RELOC_32
;
5244 case 1: code
= BFD_RELOC_8
; break;
5245 case 2: code
= BFD_RELOC_16
; break;
5246 case 4: code
= BFD_RELOC_32
; break;
5248 case 8: code
= BFD_RELOC_64
; break;
5255 if (code
== BFD_RELOC_32
5257 && fixp
->fx_addsy
== GOT_symbol
)
5259 /* We don't support GOTPC on 64bit targets. */
5260 if (flag_code
== CODE_64BIT
)
5262 code
= BFD_RELOC_386_GOTPC
;
5265 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5266 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5267 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5269 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5272 if (S_IS_WEAK (fixp
->fx_addsy
))
5273 rel
->addend
= rel
->address
- (*rel
->sym_ptr_ptr
)->value
+ 4;
5276 if (!use_rela_relocations
)
5278 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5279 vtable entry to be used in the relocation's section offset. */
5280 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5281 rel
->address
= fixp
->fx_offset
;
5285 /* Use the rela in 64bit mode. */
5288 if (!fixp
->fx_pcrel
)
5289 rel
->addend
= fixp
->fx_offset
;
5293 case BFD_RELOC_X86_64_PLT32
:
5294 case BFD_RELOC_X86_64_GOT32
:
5295 case BFD_RELOC_X86_64_GOTPCREL
:
5296 case BFD_RELOC_X86_64_TLSGD
:
5297 case BFD_RELOC_X86_64_TLSLD
:
5298 case BFD_RELOC_X86_64_GOTTPOFF
:
5299 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5302 rel
->addend
= (section
->vma
5304 + fixp
->fx_addnumber
5305 + md_pcrel_from (fixp
));
5310 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5311 if (rel
->howto
== NULL
)
5313 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5314 _("cannot represent relocation type %s"),
5315 bfd_get_reloc_code_name (code
));
5316 /* Set howto to a garbage value so that we can keep going. */
5317 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5318 assert (rel
->howto
!= NULL
);
5325 /* Parse operands using Intel syntax. This implements a recursive descent
5326 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5329 FIXME: We do not recognize the full operand grammar defined in the MASM
5330 documentation. In particular, all the structure/union and
5331 high-level macro operands are missing.
5333 Uppercase words are terminals, lower case words are non-terminals.
5334 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5335 bars '|' denote choices. Most grammar productions are implemented in
5336 functions called 'intel_<production>'.
5338 Initial production is 'expr'.
5340 addOp + | - | & | \| | << | >>
5344 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5346 constant digits [[ radixOverride ]]
5348 dataType BYTE | WORD | DWORD | QWORD | XWORD
5382 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5383 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5385 hexdigit a | b | c | d | e | f
5386 | A | B | C | D | E | F
5396 register specialRegister
5400 segmentRegister CS | DS | ES | FS | GS | SS
5402 specialRegister CR0 | CR2 | CR3
5403 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5404 | TR3 | TR4 | TR5 | TR6 | TR7
5406 We simplify the grammar in obvious places (e.g., register parsing is
5407 done by calling parse_register) and eliminate immediate left recursion
5408 to implement a recursive-descent parser.
5449 /* Parsing structure for the intel syntax parser. Used to implement the
5450 semantic actions for the operand grammar. */
5451 struct intel_parser_s
5453 char *op_string
; /* The string being parsed. */
5454 int got_a_float
; /* Whether the operand is a float. */
5455 int op_modifier
; /* Operand modifier. */
5456 int is_mem
; /* 1 if operand is memory reference. */
5457 const reg_entry
*reg
; /* Last register reference found. */
5458 char *disp
; /* Displacement string being built. */
5461 static struct intel_parser_s intel_parser
;
5463 /* Token structure for parsing intel syntax. */
5466 int code
; /* Token code. */
5467 const reg_entry
*reg
; /* Register entry for register tokens. */
5468 char *str
; /* String representation. */
5471 static struct intel_token cur_token
, prev_token
;
5473 /* Token codes for the intel parser. Since T_SHORT is already used
5474 by COFF, undefine it first to prevent a warning. */
5488 #define T_SHIFTOP 12
5490 /* Prototypes for intel parser functions. */
5491 static int intel_match_token
PARAMS ((int code
));
5492 static void intel_get_token
PARAMS ((void));
5493 static void intel_putback_token
PARAMS ((void));
5494 static int intel_expr
PARAMS ((void));
5495 static int intel_e05
PARAMS ((void));
5496 static int intel_e05_1
PARAMS ((void));
5497 static int intel_e06
PARAMS ((void));
5498 static int intel_e06_1
PARAMS ((void));
5499 static int intel_e09
PARAMS ((void));
5500 static int intel_e09_1
PARAMS ((void));
5501 static int intel_e10
PARAMS ((void));
5502 static int intel_e10_1
PARAMS ((void));
5503 static int intel_e11
PARAMS ((void));
5506 i386_intel_operand (operand_string
, got_a_float
)
5507 char *operand_string
;
5513 /* Initialize token holders. */
5514 cur_token
.code
= prev_token
.code
= T_NIL
;
5515 cur_token
.reg
= prev_token
.reg
= NULL
;
5516 cur_token
.str
= prev_token
.str
= NULL
;
5518 /* Initialize parser structure. */
5519 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5522 strcpy (intel_parser
.op_string
, operand_string
);
5523 intel_parser
.got_a_float
= got_a_float
;
5524 intel_parser
.op_modifier
= -1;
5525 intel_parser
.is_mem
= 0;
5526 intel_parser
.reg
= NULL
;
5527 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5528 if (intel_parser
.disp
== NULL
)
5530 intel_parser
.disp
[0] = '\0';
5532 /* Read the first token and start the parser. */
5534 ret
= intel_expr ();
5538 /* If we found a memory reference, hand it over to i386_displacement
5539 to fill in the rest of the operand fields. */
5540 if (intel_parser
.is_mem
)
5542 if ((i
.mem_operands
== 1
5543 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5544 || i
.mem_operands
== 2)
5546 as_bad (_("too many memory references for '%s'"),
5547 current_templates
->start
->name
);
5552 char *s
= intel_parser
.disp
;
5555 /* Add the displacement expression. */
5557 ret
= i386_displacement (s
, s
+ strlen (s
));
5559 ret
= i386_index_check (operand_string
);
5563 /* Constant and OFFSET expressions are handled by i386_immediate. */
5564 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5565 || intel_parser
.reg
== NULL
)
5566 ret
= i386_immediate (intel_parser
.disp
);
5570 free (intel_parser
.disp
);
5580 /* expr SHORT e05 */
5581 if (cur_token
.code
== T_SHORT
)
5583 intel_parser
.op_modifier
= SHORT
;
5584 intel_match_token (T_SHORT
);
5586 return (intel_e05 ());
5591 return intel_e05 ();
5601 return (intel_e06 () && intel_e05_1 ());
5607 /* e05' addOp e06 e05' */
5608 if (cur_token
.code
== '+' || cur_token
.code
== '-'
5609 || cur_token
.code
== '&' || cur_token
.code
== '|'
5610 || cur_token
.code
== T_SHIFTOP
)
5612 strcat (intel_parser
.disp
, cur_token
.str
);
5613 intel_match_token (cur_token
.code
);
5615 return (intel_e06 () && intel_e05_1 ());
5630 return (intel_e09 () && intel_e06_1 ());
5636 /* e06' mulOp e09 e06' */
5637 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5639 strcat (intel_parser
.disp
, cur_token
.str
);
5640 intel_match_token (cur_token
.code
);
5642 return (intel_e09 () && intel_e06_1 ());
5650 /* e09 OFFSET e10 e09'
5659 /* e09 OFFSET e10 e09' */
5660 if (cur_token
.code
== T_OFFSET
)
5662 intel_parser
.is_mem
= 0;
5663 intel_parser
.op_modifier
= OFFSET_FLAT
;
5664 intel_match_token (T_OFFSET
);
5666 return (intel_e10 () && intel_e09_1 ());
5671 return (intel_e10 () && intel_e09_1 ());
5677 /* e09' PTR e10 e09' */
5678 if (cur_token
.code
== T_PTR
)
5680 if (prev_token
.code
== T_BYTE
)
5681 i
.suffix
= BYTE_MNEM_SUFFIX
;
5683 else if (prev_token
.code
== T_WORD
)
5685 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5686 i
.suffix
= SHORT_MNEM_SUFFIX
;
5688 i
.suffix
= WORD_MNEM_SUFFIX
;
5691 else if (prev_token
.code
== T_DWORD
)
5693 if (intel_parser
.got_a_float
== 1) /* "f..." */
5694 i
.suffix
= SHORT_MNEM_SUFFIX
;
5696 i
.suffix
= LONG_MNEM_SUFFIX
;
5699 else if (prev_token
.code
== T_QWORD
)
5701 if (intel_parser
.got_a_float
== 1) /* "f..." */
5702 i
.suffix
= LONG_MNEM_SUFFIX
;
5704 i
.suffix
= QWORD_MNEM_SUFFIX
;
5707 else if (prev_token
.code
== T_XWORD
)
5708 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5712 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
5716 intel_match_token (T_PTR
);
5718 return (intel_e10 () && intel_e09_1 ());
5721 /* e09 : e10 e09' */
5722 else if (cur_token
.code
== ':')
5724 /* Mark as a memory operand only if it's not already known to be an
5725 offset expression. */
5726 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5727 intel_parser
.is_mem
= 1;
5729 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5744 return (intel_e11 () && intel_e10_1 ());
5750 /* e10' [ expr ] e10' */
5751 if (cur_token
.code
== '[')
5753 intel_match_token ('[');
5755 /* Mark as a memory operand only if it's not already known to be an
5756 offset expression. If it's an offset expression, we need to keep
5758 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5759 intel_parser
.is_mem
= 1;
5761 strcat (intel_parser
.disp
, "[");
5763 /* Add a '+' to the displacement string if necessary. */
5764 if (*intel_parser
.disp
!= '\0'
5765 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5766 strcat (intel_parser
.disp
, "+");
5768 if (intel_expr () && intel_match_token (']'))
5770 /* Preserve brackets when the operand is an offset expression. */
5771 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5772 strcat (intel_parser
.disp
, "]");
5774 return intel_e10_1 ();
5802 if (cur_token
.code
== '(')
5804 intel_match_token ('(');
5805 strcat (intel_parser
.disp
, "(");
5807 if (intel_expr () && intel_match_token (')'))
5809 strcat (intel_parser
.disp
, ")");
5817 else if (cur_token
.code
== '~')
5819 strcat (intel_parser
.disp
, "~");
5820 intel_match_token ('~');
5822 return (intel_e11 ());
5826 else if (cur_token
.code
== '[')
5828 intel_match_token ('[');
5830 /* Mark as a memory operand only if it's not already known to be an
5831 offset expression. If it's an offset expression, we need to keep
5833 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5834 intel_parser
.is_mem
= 1;
5836 strcat (intel_parser
.disp
, "[");
5838 /* Operands for jump/call inside brackets denote absolute addresses. */
5839 if (current_templates
->start
->opcode_modifier
& Jump
5840 || current_templates
->start
->opcode_modifier
& JumpDword
5841 || current_templates
->start
->opcode_modifier
& JumpByte
5842 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5843 i
.types
[this_operand
] |= JumpAbsolute
;
5845 /* Add a '+' to the displacement string if necessary. */
5846 if (*intel_parser
.disp
!= '\0'
5847 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5848 strcat (intel_parser
.disp
, "+");
5850 if (intel_expr () && intel_match_token (']'))
5852 /* Preserve brackets when the operand is an offset expression. */
5853 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5854 strcat (intel_parser
.disp
, "]");
5867 else if (cur_token
.code
== T_BYTE
5868 || cur_token
.code
== T_WORD
5869 || cur_token
.code
== T_DWORD
5870 || cur_token
.code
== T_QWORD
5871 || cur_token
.code
== T_XWORD
)
5873 intel_match_token (cur_token
.code
);
5880 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5882 strcat (intel_parser
.disp
, cur_token
.str
);
5883 intel_match_token (cur_token
.code
);
5885 /* Mark as a memory operand only if it's not already known to be an
5886 offset expression. */
5887 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5888 intel_parser
.is_mem
= 1;
5894 else if (cur_token
.code
== T_REG
)
5896 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5898 intel_match_token (T_REG
);
5900 /* Check for segment change. */
5901 if (cur_token
.code
== ':')
5903 if (reg
->reg_type
& (SReg2
| SReg3
))
5905 switch (reg
->reg_num
)
5908 i
.seg
[i
.mem_operands
] = &es
;
5911 i
.seg
[i
.mem_operands
] = &cs
;
5914 i
.seg
[i
.mem_operands
] = &ss
;
5917 i
.seg
[i
.mem_operands
] = &ds
;
5920 i
.seg
[i
.mem_operands
] = &fs
;
5923 i
.seg
[i
.mem_operands
] = &gs
;
5929 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5934 /* Not a segment register. Check for register scaling. */
5935 else if (cur_token
.code
== '*')
5937 if (!intel_parser
.is_mem
)
5939 as_bad (_("Register scaling only allowed in memory operands."));
5943 /* What follows must be a valid scale. */
5944 if (intel_match_token ('*')
5945 && strchr ("01248", *cur_token
.str
))
5948 i
.types
[this_operand
] |= BaseIndex
;
5950 /* Set the scale after setting the register (otherwise,
5951 i386_scale will complain) */
5952 i386_scale (cur_token
.str
);
5953 intel_match_token (T_CONST
);
5957 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5963 /* No scaling. If this is a memory operand, the register is either a
5964 base register (first occurrence) or an index register (second
5966 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5968 if (i
.base_reg
&& i
.index_reg
)
5970 as_bad (_("Too many register references in memory operand."));
5974 if (i
.base_reg
== NULL
)
5979 i
.types
[this_operand
] |= BaseIndex
;
5982 /* Offset modifier. Add the register to the displacement string to be
5983 parsed as an immediate expression after we're done. */
5984 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5985 strcat (intel_parser
.disp
, reg
->reg_name
);
5987 /* It's neither base nor index nor offset. */
5990 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5991 i
.op
[this_operand
].regs
= reg
;
5995 /* Since registers are not part of the displacement string (except
5996 when we're parsing offset operands), we may need to remove any
5997 preceding '+' from the displacement string. */
5998 if (*intel_parser
.disp
!= '\0'
5999 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
6001 char *s
= intel_parser
.disp
;
6002 s
+= strlen (s
) - 1;
6011 else if (cur_token
.code
== T_ID
)
6013 /* Add the identifier to the displacement string. */
6014 strcat (intel_parser
.disp
, cur_token
.str
);
6015 intel_match_token (T_ID
);
6017 /* The identifier represents a memory reference only if it's not
6018 preceded by an offset modifier. */
6019 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6020 intel_parser
.is_mem
= 1;
6026 else if (cur_token
.code
== T_CONST
6027 || cur_token
.code
== '-'
6028 || cur_token
.code
== '+')
6032 /* Allow constants that start with `+' or `-'. */
6033 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6035 strcat (intel_parser
.disp
, cur_token
.str
);
6036 intel_match_token (cur_token
.code
);
6037 if (cur_token
.code
!= T_CONST
)
6039 as_bad (_("Syntax error. Expecting a constant. Got `%s'."),
6045 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6046 if (save_str
== NULL
)
6048 strcpy (save_str
, cur_token
.str
);
6050 /* Get the next token to check for register scaling. */
6051 intel_match_token (cur_token
.code
);
6053 /* Check if this constant is a scaling factor for an index register. */
6054 if (cur_token
.code
== '*')
6056 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6058 if (!intel_parser
.is_mem
)
6060 as_bad (_("Register scaling only allowed in memory operands."));
6064 /* The constant is followed by `* reg', so it must be
6066 if (strchr ("01248", *save_str
))
6068 i
.index_reg
= cur_token
.reg
;
6069 i
.types
[this_operand
] |= BaseIndex
;
6071 /* Set the scale after setting the register (otherwise,
6072 i386_scale will complain) */
6073 i386_scale (save_str
);
6074 intel_match_token (T_REG
);
6076 /* Since registers are not part of the displacement
6077 string, we may need to remove any preceding '+' from
6078 the displacement string. */
6079 if (*intel_parser
.disp
!= '\0')
6081 char *s
= intel_parser
.disp
;
6082 s
+= strlen (s
) - 1;
6095 /* The constant was not used for register scaling. Since we have
6096 already consumed the token following `*' we now need to put it
6097 back in the stream. */
6099 intel_putback_token ();
6102 /* Add the constant to the displacement string. */
6103 strcat (intel_parser
.disp
, save_str
);
6109 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6113 /* Match the given token against cur_token. If they match, read the next
6114 token from the operand string. */
6116 intel_match_token (code
)
6119 if (cur_token
.code
== code
)
6126 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6131 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6136 const reg_entry
*reg
;
6137 struct intel_token new_token
;
6139 new_token
.code
= T_NIL
;
6140 new_token
.reg
= NULL
;
6141 new_token
.str
= NULL
;
6143 /* Free the memory allocated to the previous token and move
6144 cur_token to prev_token. */
6146 free (prev_token
.str
);
6148 prev_token
= cur_token
;
6150 /* Skip whitespace. */
6151 while (is_space_char (*intel_parser
.op_string
))
6152 intel_parser
.op_string
++;
6154 /* Return an empty token if we find nothing else on the line. */
6155 if (*intel_parser
.op_string
== '\0')
6157 cur_token
= new_token
;
6161 /* The new token cannot be larger than the remainder of the operand
6163 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6164 if (new_token
.str
== NULL
)
6166 new_token
.str
[0] = '\0';
6168 if (strchr ("0123456789", *intel_parser
.op_string
))
6170 char *p
= new_token
.str
;
6171 char *q
= intel_parser
.op_string
;
6172 new_token
.code
= T_CONST
;
6174 /* Allow any kind of identifier char to encompass floating point and
6175 hexadecimal numbers. */
6176 while (is_identifier_char (*q
))
6180 /* Recognize special symbol names [0-9][bf]. */
6181 if (strlen (intel_parser
.op_string
) == 2
6182 && (intel_parser
.op_string
[1] == 'b'
6183 || intel_parser
.op_string
[1] == 'f'))
6184 new_token
.code
= T_ID
;
6187 else if (strchr ("<>", *intel_parser
.op_string
)
6188 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6190 new_token
.code
= T_SHIFTOP
;
6191 new_token
.str
[0] = *intel_parser
.op_string
;
6192 new_token
.str
[1] = *intel_parser
.op_string
;
6193 new_token
.str
[2] = '\0';
6196 else if (strchr ("+-/*&|:[]()~", *intel_parser
.op_string
))
6198 new_token
.code
= *intel_parser
.op_string
;
6199 new_token
.str
[0] = *intel_parser
.op_string
;
6200 new_token
.str
[1] = '\0';
6203 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6204 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6206 new_token
.code
= T_REG
;
6207 new_token
.reg
= reg
;
6209 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6211 new_token
.str
[0] = REGISTER_PREFIX
;
6212 new_token
.str
[1] = '\0';
6215 strcat (new_token
.str
, reg
->reg_name
);
6218 else if (is_identifier_char (*intel_parser
.op_string
))
6220 char *p
= new_token
.str
;
6221 char *q
= intel_parser
.op_string
;
6223 /* A '.' or '$' followed by an identifier char is an identifier.
6224 Otherwise, it's operator '.' followed by an expression. */
6225 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6227 new_token
.code
= *q
;
6228 new_token
.str
[0] = *q
;
6229 new_token
.str
[1] = '\0';
6233 while (is_identifier_char (*q
) || *q
== '@')
6237 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6238 new_token
.code
= T_BYTE
;
6240 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6241 new_token
.code
= T_WORD
;
6243 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6244 new_token
.code
= T_DWORD
;
6246 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6247 new_token
.code
= T_QWORD
;
6249 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6250 new_token
.code
= T_XWORD
;
6252 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6253 new_token
.code
= T_PTR
;
6255 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6256 new_token
.code
= T_SHORT
;
6258 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6260 new_token
.code
= T_OFFSET
;
6262 /* ??? This is not mentioned in the MASM grammar but gcc
6263 makes use of it with -mintel-syntax. OFFSET may be
6264 followed by FLAT: */
6265 if (strncasecmp (q
, " FLAT:", 6) == 0)
6266 strcat (new_token
.str
, " FLAT:");
6269 /* ??? This is not mentioned in the MASM grammar. */
6270 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6271 new_token
.code
= T_OFFSET
;
6274 new_token
.code
= T_ID
;
6279 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6281 intel_parser
.op_string
+= strlen (new_token
.str
);
6282 cur_token
= new_token
;
6285 /* Put cur_token back into the token stream and make cur_token point to
6288 intel_putback_token ()
6290 intel_parser
.op_string
-= strlen (cur_token
.str
);
6291 free (cur_token
.str
);
6292 cur_token
= prev_token
;
6294 /* Forget prev_token. */
6295 prev_token
.code
= T_NIL
;
6296 prev_token
.reg
= NULL
;
6297 prev_token
.str
= NULL
;
6301 tc_x86_regname_to_dw2regnum (const char *regname
)
6303 unsigned int regnum
;
6304 unsigned int regnames_count
;
6305 char *regnames_32
[] =
6307 "eax", "ecx", "edx", "ebx",
6308 "esp", "ebp", "esi", "edi",
6311 char *regnames_64
[] =
6313 "rax", "rbx", "rcx", "rdx",
6314 "rdi", "rsi", "rbp", "rsp",
6315 "r8", "r9", "r10", "r11",
6316 "r12", "r13", "r14", "r15",
6321 if (flag_code
== CODE_64BIT
)
6323 regnames
= regnames_64
;
6324 regnames_count
= ARRAY_SIZE (regnames_64
);
6328 regnames
= regnames_32
;
6329 regnames_count
= ARRAY_SIZE (regnames_32
);
6332 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6333 if (strcmp (regname
, regnames
[regnum
]) == 0)
6340 tc_x86_frame_initial_instructions (void)
6342 static unsigned int sp_regno
;
6345 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6348 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6349 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);