1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "corei7", PROCESSOR_COREI7
,
605 { "k6", PROCESSOR_K6
,
607 { "k6_2", PROCESSOR_K6
,
609 { "athlon", PROCESSOR_ATHLON
,
611 { "sledgehammer", PROCESSOR_K8
,
613 { "opteron", PROCESSOR_K8
,
615 { "k8", PROCESSOR_K8
,
617 { "amdfam10", PROCESSOR_AMDFAM10
,
618 CPU_AMDFAM10_FLAGS
},
619 { ".mmx", PROCESSOR_UNKNOWN
,
621 { ".sse", PROCESSOR_UNKNOWN
,
623 { ".sse2", PROCESSOR_UNKNOWN
,
625 { ".sse3", PROCESSOR_UNKNOWN
,
627 { ".ssse3", PROCESSOR_UNKNOWN
,
629 { ".sse4.1", PROCESSOR_UNKNOWN
,
631 { ".sse4.2", PROCESSOR_UNKNOWN
,
633 { ".sse4", PROCESSOR_UNKNOWN
,
635 { ".avx", PROCESSOR_UNKNOWN
,
637 { ".vmx", PROCESSOR_UNKNOWN
,
639 { ".smx", PROCESSOR_UNKNOWN
,
641 { ".xsave", PROCESSOR_UNKNOWN
,
643 { ".aes", PROCESSOR_UNKNOWN
,
645 { ".pclmul", PROCESSOR_UNKNOWN
,
647 { ".clmul", PROCESSOR_UNKNOWN
,
649 { ".fma", PROCESSOR_UNKNOWN
,
651 { ".movbe", PROCESSOR_UNKNOWN
,
653 { ".ept", PROCESSOR_UNKNOWN
,
655 { ".clflush", PROCESSOR_UNKNOWN
,
657 { ".syscall", PROCESSOR_UNKNOWN
,
659 { ".rdtscp", PROCESSOR_UNKNOWN
,
661 { ".3dnow", PROCESSOR_UNKNOWN
,
663 { ".3dnowa", PROCESSOR_UNKNOWN
,
665 { ".padlock", PROCESSOR_UNKNOWN
,
667 { ".pacifica", PROCESSOR_UNKNOWN
,
669 { ".svme", PROCESSOR_UNKNOWN
,
671 { ".sse4a", PROCESSOR_UNKNOWN
,
673 { ".abm", PROCESSOR_UNKNOWN
,
675 { ".sse5", PROCESSOR_UNKNOWN
,
680 /* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
684 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
691 && *input_line_pointer
== ',')
693 align
= parse_align (needs_align
- 1);
695 if (align
== (addressT
) -1)
710 bss_alloc (symbolP
, size
, align
);
715 pe_lcomm (int needs_align
)
717 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
721 const pseudo_typeS md_pseudo_table
[] =
723 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes
, 0},
726 {"align", s_align_ptwo
, 0},
728 {"arch", set_cpu_arch
, 0},
732 {"lcomm", pe_lcomm
, 1},
734 {"ffloat", float_cons
, 'f'},
735 {"dfloat", float_cons
, 'd'},
736 {"tfloat", float_cons
, 'x'},
738 {"slong", signed_cons
, 4},
739 {"noopt", s_ignore
, 0},
740 {"optim", s_ignore
, 0},
741 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
742 {"code16", set_code_flag
, CODE_16BIT
},
743 {"code32", set_code_flag
, CODE_32BIT
},
744 {"code64", set_code_flag
, CODE_64BIT
},
745 {"intel_syntax", set_intel_syntax
, 1},
746 {"att_syntax", set_intel_syntax
, 0},
747 {"intel_mnemonic", set_intel_mnemonic
, 1},
748 {"att_mnemonic", set_intel_mnemonic
, 0},
749 {"allow_index_reg", set_allow_index_reg
, 1},
750 {"disallow_index_reg", set_allow_index_reg
, 0},
751 {"sse_check", set_sse_check
, 0},
752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common
, 0},
755 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
756 {"loc", dwarf2_directive_loc
, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
760 {"secrel32", pe_directive_secrel
, 0},
765 /* For interface with expression (). */
766 extern char *input_line_pointer
;
768 /* Hash table for instruction mnemonic lookup. */
769 static struct hash_control
*op_hash
;
771 /* Hash table for register lookup. */
772 static struct hash_control
*reg_hash
;
775 i386_align_code (fragS
*fragP
, int count
)
777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
780 static const char f32_1
[] =
782 static const char f32_2
[] =
783 {0x66,0x90}; /* xchg %ax,%ax */
784 static const char f32_3
[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4
[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5
[] =
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6
[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7
[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8
[] =
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9
[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10
[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11
[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12
[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13
[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14
[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
816 static const char f16_3
[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
818 static const char f16_4
[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5
[] =
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6
[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7
[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8
[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char jump_31
[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
837 static const char *const f32_patt
[] = {
838 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
839 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
841 static const char *const f16_patt
[] = {
842 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
845 static const char alt_3
[] =
847 /* nopl 0(%[re]ax) */
848 static const char alt_4
[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5
[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6
[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7
[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8
[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9
[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10
[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15
[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11
[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
925 static const char alt_short_13
[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 static const char alt_short_14
[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15
[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt
[] = {
939 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
940 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
941 alt_short_14
, alt_short_15
943 static const char *const alt_long_patt
[] = {
944 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
945 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
946 alt_long_14
, alt_long_15
949 /* Only align for at least a positive non-zero boundary. */
950 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
971 if (flag_code
== CODE_16BIT
)
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
977 /* Adjust jump offset. */
978 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
981 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
982 f16_patt
[count
- 1], count
);
986 const char *const *patt
= NULL
;
988 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune
)
993 case PROCESSOR_UNKNOWN
:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
996 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
997 patt
= alt_long_patt
;
1001 case PROCESSOR_PENTIUMPRO
:
1002 case PROCESSOR_PENTIUM4
:
1003 case PROCESSOR_NOCONA
:
1004 case PROCESSOR_CORE
:
1005 case PROCESSOR_CORE2
:
1006 case PROCESSOR_COREI7
:
1007 case PROCESSOR_GENERIC64
:
1008 patt
= alt_long_patt
;
1011 case PROCESSOR_ATHLON
:
1013 case PROCESSOR_AMDFAM10
:
1014 patt
= alt_short_patt
;
1016 case PROCESSOR_I386
:
1017 case PROCESSOR_I486
:
1018 case PROCESSOR_PENTIUM
:
1019 case PROCESSOR_GENERIC32
:
1026 switch (fragP
->tc_frag_data
.tune
)
1028 case PROCESSOR_UNKNOWN
:
1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1030 PROCESSOR_UNKNOWN. */
1034 case PROCESSOR_I386
:
1035 case PROCESSOR_I486
:
1036 case PROCESSOR_PENTIUM
:
1038 case PROCESSOR_ATHLON
:
1040 case PROCESSOR_AMDFAM10
:
1041 case PROCESSOR_GENERIC32
:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1044 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1045 patt
= alt_short_patt
;
1049 case PROCESSOR_PENTIUMPRO
:
1050 case PROCESSOR_PENTIUM4
:
1051 case PROCESSOR_NOCONA
:
1052 case PROCESSOR_CORE
:
1053 case PROCESSOR_CORE2
:
1054 case PROCESSOR_COREI7
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1072 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1073 patt
[count
- 1], count
);
1076 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1078 /* Adjust jump offset. */
1079 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding
= count
;
1088 while (padding
> 15)
1091 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 patt
[padding
- 1], padding
);
1100 fragP
->fr_var
= count
;
1104 operand_type_all_zero (const union i386_operand_type
*x
)
1106 switch (ARRAY_SIZE(x
->array
))
1115 return !x
->array
[0];
1122 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1124 switch (ARRAY_SIZE(x
->array
))
1139 operand_type_equal (const union i386_operand_type
*x
,
1140 const union i386_operand_type
*y
)
1142 switch (ARRAY_SIZE(x
->array
))
1145 if (x
->array
[2] != y
->array
[2])
1148 if (x
->array
[1] != y
->array
[1])
1151 return x
->array
[0] == y
->array
[0];
1159 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1161 switch (ARRAY_SIZE(x
->array
))
1170 return !x
->array
[0];
1177 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1179 switch (ARRAY_SIZE(x
->array
))
1194 cpu_flags_equal (const union i386_cpu_flags
*x
,
1195 const union i386_cpu_flags
*y
)
1197 switch (ARRAY_SIZE(x
->array
))
1200 if (x
->array
[2] != y
->array
[2])
1203 if (x
->array
[1] != y
->array
[1])
1206 return x
->array
[0] == y
->array
[0];
1214 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1216 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1217 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1220 static INLINE i386_cpu_flags
1221 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1223 switch (ARRAY_SIZE (x
.array
))
1226 x
.array
[2] &= y
.array
[2];
1228 x
.array
[1] &= y
.array
[1];
1230 x
.array
[0] &= y
.array
[0];
1238 static INLINE i386_cpu_flags
1239 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1241 switch (ARRAY_SIZE (x
.array
))
1244 x
.array
[2] |= y
.array
[2];
1246 x
.array
[1] |= y
.array
[1];
1248 x
.array
[0] |= y
.array
[0];
1256 #define CPU_FLAGS_ARCH_MATCH 0x1
1257 #define CPU_FLAGS_64BIT_MATCH 0x2
1258 #define CPU_FLAGS_AES_MATCH 0x4
1259 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1260 #define CPU_FLAGS_AVX_MATCH 0x10
1262 #define CPU_FLAGS_32BIT_MATCH \
1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1265 #define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1268 /* Return CPU flags match bits. */
1271 cpu_flags_match (const template *t
)
1273 i386_cpu_flags x
= t
->cpu_flags
;
1274 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1276 x
.bitfield
.cpu64
= 0;
1277 x
.bitfield
.cpuno64
= 0;
1279 if (cpu_flags_all_zero (&x
))
1281 /* This instruction is available on all archs. */
1282 match
|= CPU_FLAGS_32BIT_MATCH
;
1286 /* This instruction is available only on some archs. */
1287 i386_cpu_flags cpu
= cpu_arch_flags
;
1289 cpu
.bitfield
.cpu64
= 0;
1290 cpu
.bitfield
.cpuno64
= 0;
1291 cpu
= cpu_flags_and (x
, cpu
);
1292 if (!cpu_flags_all_zero (&cpu
))
1294 if (x
.bitfield
.cpuavx
)
1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1297 if (cpu
.bitfield
.cpuavx
)
1299 /* Check SSE2AVX. */
1300 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1302 match
|= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH
);
1305 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1306 match
|= CPU_FLAGS_AES_MATCH
;
1308 if (!x
.bitfield
.cpupclmul
1309 || cpu
.bitfield
.cpupclmul
)
1310 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1314 match
|= CPU_FLAGS_ARCH_MATCH
;
1317 match
|= CPU_FLAGS_32BIT_MATCH
;
1323 static INLINE i386_operand_type
1324 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1326 switch (ARRAY_SIZE (x
.array
))
1329 x
.array
[2] &= y
.array
[2];
1331 x
.array
[1] &= y
.array
[1];
1333 x
.array
[0] &= y
.array
[0];
1341 static INLINE i386_operand_type
1342 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1344 switch (ARRAY_SIZE (x
.array
))
1347 x
.array
[2] |= y
.array
[2];
1349 x
.array
[1] |= y
.array
[1];
1351 x
.array
[0] |= y
.array
[0];
1359 static INLINE i386_operand_type
1360 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1362 switch (ARRAY_SIZE (x
.array
))
1365 x
.array
[2] ^= y
.array
[2];
1367 x
.array
[1] ^= y
.array
[1];
1369 x
.array
[0] ^= y
.array
[0];
1377 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1378 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1379 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1380 static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG
;
1382 static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1384 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1385 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1386 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1387 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1388 static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP
;
1390 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1391 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1392 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1393 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1394 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1395 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1396 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1397 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1398 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1399 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1400 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1411 operand_type_check (i386_operand_type t
, enum operand_type c
)
1416 return (t
.bitfield
.reg8
1419 || t
.bitfield
.reg64
);
1422 return (t
.bitfield
.imm8
1426 || t
.bitfield
.imm32s
1427 || t
.bitfield
.imm64
);
1430 return (t
.bitfield
.disp8
1431 || t
.bitfield
.disp16
1432 || t
.bitfield
.disp32
1433 || t
.bitfield
.disp32s
1434 || t
.bitfield
.disp64
);
1437 return (t
.bitfield
.disp8
1438 || t
.bitfield
.disp16
1439 || t
.bitfield
.disp32
1440 || t
.bitfield
.disp32s
1441 || t
.bitfield
.disp64
1442 || t
.bitfield
.baseindex
);
1451 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1455 match_reg_size (const template *t
, unsigned int j
)
1457 return !((i
.types
[j
].bitfield
.byte
1458 && !t
->operand_types
[j
].bitfield
.byte
)
1459 || (i
.types
[j
].bitfield
.word
1460 && !t
->operand_types
[j
].bitfield
.word
)
1461 || (i
.types
[j
].bitfield
.dword
1462 && !t
->operand_types
[j
].bitfield
.dword
)
1463 || (i
.types
[j
].bitfield
.qword
1464 && !t
->operand_types
[j
].bitfield
.qword
));
1467 /* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1471 match_mem_size (const template *t
, unsigned int j
)
1473 return (match_reg_size (t
, j
)
1474 && !((i
.types
[j
].bitfield
.unspecified
1475 && !t
->operand_types
[j
].bitfield
.unspecified
)
1476 || (i
.types
[j
].bitfield
.fword
1477 && !t
->operand_types
[j
].bitfield
.fword
)
1478 || (i
.types
[j
].bitfield
.tbyte
1479 && !t
->operand_types
[j
].bitfield
.tbyte
)
1480 || (i
.types
[j
].bitfield
.xmmword
1481 && !t
->operand_types
[j
].bitfield
.xmmword
)
1482 || (i
.types
[j
].bitfield
.ymmword
1483 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1486 /* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1490 operand_size_match (const template *t
)
1495 /* Don't check jump instructions. */
1496 if (t
->opcode_modifier
.jump
1497 || t
->opcode_modifier
.jumpbyte
1498 || t
->opcode_modifier
.jumpdword
1499 || t
->opcode_modifier
.jumpintersegment
)
1502 /* Check memory and accumulator operand size. */
1503 for (j
= 0; j
< i
.operands
; j
++)
1505 if (t
->operand_types
[j
].bitfield
.anysize
)
1508 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1514 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1522 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1525 /* Check reverse. */
1526 assert (i
.operands
== 2);
1529 for (j
= 0; j
< 2; j
++)
1531 if (t
->operand_types
[j
].bitfield
.acc
1532 && !match_reg_size (t
, j
? 0 : 1))
1538 if (i
.types
[j
].bitfield
.mem
1539 && !match_mem_size (t
, j
? 0 : 1))
1550 operand_type_match (i386_operand_type overlap
,
1551 i386_operand_type given
)
1553 i386_operand_type temp
= overlap
;
1555 temp
.bitfield
.jumpabsolute
= 0;
1556 temp
.bitfield
.unspecified
= 0;
1557 temp
.bitfield
.byte
= 0;
1558 temp
.bitfield
.word
= 0;
1559 temp
.bitfield
.dword
= 0;
1560 temp
.bitfield
.fword
= 0;
1561 temp
.bitfield
.qword
= 0;
1562 temp
.bitfield
.tbyte
= 0;
1563 temp
.bitfield
.xmmword
= 0;
1564 temp
.bitfield
.ymmword
= 0;
1565 if (operand_type_all_zero (&temp
))
1568 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1569 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1572 /* If given types g0 and g1 are registers they must be of the same type
1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1577 operand_type_register_match (i386_operand_type m0
,
1578 i386_operand_type g0
,
1579 i386_operand_type t0
,
1580 i386_operand_type m1
,
1581 i386_operand_type g1
,
1582 i386_operand_type t1
)
1584 if (!operand_type_check (g0
, reg
))
1587 if (!operand_type_check (g1
, reg
))
1590 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1591 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1592 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1593 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1596 if (m0
.bitfield
.acc
)
1598 t0
.bitfield
.reg8
= 1;
1599 t0
.bitfield
.reg16
= 1;
1600 t0
.bitfield
.reg32
= 1;
1601 t0
.bitfield
.reg64
= 1;
1604 if (m1
.bitfield
.acc
)
1606 t1
.bitfield
.reg8
= 1;
1607 t1
.bitfield
.reg16
= 1;
1608 t1
.bitfield
.reg32
= 1;
1609 t1
.bitfield
.reg64
= 1;
1612 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1613 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1614 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1615 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1618 static INLINE
unsigned int
1619 mode_from_disp_size (i386_operand_type t
)
1621 if (t
.bitfield
.disp8
)
1623 else if (t
.bitfield
.disp16
1624 || t
.bitfield
.disp32
1625 || t
.bitfield
.disp32s
)
1632 fits_in_signed_byte (offsetT num
)
1634 return (num
>= -128) && (num
<= 127);
1638 fits_in_unsigned_byte (offsetT num
)
1640 return (num
& 0xff) == num
;
1644 fits_in_unsigned_word (offsetT num
)
1646 return (num
& 0xffff) == num
;
1650 fits_in_signed_word (offsetT num
)
1652 return (-32768 <= num
) && (num
<= 32767);
1656 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1661 return (!(((offsetT
) -1 << 31) & num
)
1662 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1664 } /* fits_in_signed_long() */
1667 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1672 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1674 } /* fits_in_unsigned_long() */
1677 fits_in_imm4 (offsetT num
)
1679 return (num
& 0xf) == num
;
1682 static i386_operand_type
1683 smallest_imm_type (offsetT num
)
1685 i386_operand_type t
;
1687 operand_type_set (&t
, 0);
1688 t
.bitfield
.imm64
= 1;
1690 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1692 /* This code is disabled on the 486 because all the Imm1 forms
1693 in the opcode table are slower on the i486. They're the
1694 versions with the implicitly specified single-position
1695 displacement, which has another syntax if you really want to
1697 t
.bitfield
.imm1
= 1;
1698 t
.bitfield
.imm8
= 1;
1699 t
.bitfield
.imm8s
= 1;
1700 t
.bitfield
.imm16
= 1;
1701 t
.bitfield
.imm32
= 1;
1702 t
.bitfield
.imm32s
= 1;
1704 else if (fits_in_signed_byte (num
))
1706 t
.bitfield
.imm8
= 1;
1707 t
.bitfield
.imm8s
= 1;
1708 t
.bitfield
.imm16
= 1;
1709 t
.bitfield
.imm32
= 1;
1710 t
.bitfield
.imm32s
= 1;
1712 else if (fits_in_unsigned_byte (num
))
1714 t
.bitfield
.imm8
= 1;
1715 t
.bitfield
.imm16
= 1;
1716 t
.bitfield
.imm32
= 1;
1717 t
.bitfield
.imm32s
= 1;
1719 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_signed_long (num
))
1727 t
.bitfield
.imm32
= 1;
1728 t
.bitfield
.imm32s
= 1;
1730 else if (fits_in_unsigned_long (num
))
1731 t
.bitfield
.imm32
= 1;
1737 offset_in_range (offsetT val
, int size
)
1743 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1744 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1745 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1747 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1752 /* If BFD64, sign extend val. */
1753 if (!use_rela_relocations
)
1754 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1755 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1757 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1759 char buf1
[40], buf2
[40];
1761 sprint_value (buf1
, val
);
1762 sprint_value (buf2
, val
& mask
);
1763 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1768 /* Returns 0 if attempting to add a prefix where one from the same
1769 class already exists, 1 if non rep/repne added, 2 if rep/repne
1772 add_prefix (unsigned int prefix
)
1777 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1778 && flag_code
== CODE_64BIT
)
1780 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1781 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1782 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1793 case CS_PREFIX_OPCODE
:
1794 case DS_PREFIX_OPCODE
:
1795 case ES_PREFIX_OPCODE
:
1796 case FS_PREFIX_OPCODE
:
1797 case GS_PREFIX_OPCODE
:
1798 case SS_PREFIX_OPCODE
:
1802 case REPNE_PREFIX_OPCODE
:
1803 case REPE_PREFIX_OPCODE
:
1806 case LOCK_PREFIX_OPCODE
:
1814 case ADDR_PREFIX_OPCODE
:
1818 case DATA_PREFIX_OPCODE
:
1822 if (i
.prefix
[q
] != 0)
1830 i
.prefix
[q
] |= prefix
;
1833 as_bad (_("same type of prefix used twice"));
1839 set_code_flag (int value
)
1842 if (flag_code
== CODE_64BIT
)
1844 cpu_arch_flags
.bitfield
.cpu64
= 1;
1845 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1849 cpu_arch_flags
.bitfield
.cpu64
= 0;
1850 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1852 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1854 as_bad (_("64bit mode not supported on this CPU."));
1856 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1858 as_bad (_("32bit mode not supported on this CPU."));
1860 stackop_size
= '\0';
1864 set_16bit_gcc_code_flag (int new_code_flag
)
1866 flag_code
= new_code_flag
;
1867 if (flag_code
!= CODE_16BIT
)
1869 cpu_arch_flags
.bitfield
.cpu64
= 0;
1870 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1871 stackop_size
= LONG_MNEM_SUFFIX
;
1875 set_intel_syntax (int syntax_flag
)
1877 /* Find out if register prefixing is specified. */
1878 int ask_naked_reg
= 0;
1881 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1883 char *string
= input_line_pointer
;
1884 int e
= get_symbol_end ();
1886 if (strcmp (string
, "prefix") == 0)
1888 else if (strcmp (string
, "noprefix") == 0)
1891 as_bad (_("bad argument to syntax directive."));
1892 *input_line_pointer
= e
;
1894 demand_empty_rest_of_line ();
1896 intel_syntax
= syntax_flag
;
1898 if (ask_naked_reg
== 0)
1899 allow_naked_reg
= (intel_syntax
1900 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1902 allow_naked_reg
= (ask_naked_reg
< 0);
1904 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1905 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1906 register_prefix
= allow_naked_reg
? "" : "%";
1910 set_intel_mnemonic (int mnemonic_flag
)
1912 intel_mnemonic
= mnemonic_flag
;
1916 set_allow_index_reg (int flag
)
1918 allow_index_reg
= flag
;
1922 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1926 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1928 char *string
= input_line_pointer
;
1929 int e
= get_symbol_end ();
1931 if (strcmp (string
, "none") == 0)
1932 sse_check
= sse_check_none
;
1933 else if (strcmp (string
, "warning") == 0)
1934 sse_check
= sse_check_warning
;
1935 else if (strcmp (string
, "error") == 0)
1936 sse_check
= sse_check_error
;
1938 as_bad (_("bad argument to sse_check directive."));
1939 *input_line_pointer
= e
;
1942 as_bad (_("missing argument for sse_check directive"));
1944 demand_empty_rest_of_line ();
1948 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1952 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1954 char *string
= input_line_pointer
;
1955 int e
= get_symbol_end ();
1957 i386_cpu_flags flags
;
1959 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1961 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1965 cpu_arch_name
= cpu_arch
[i
].name
;
1966 cpu_sub_arch_name
= NULL
;
1967 cpu_arch_flags
= cpu_arch
[i
].flags
;
1968 if (flag_code
== CODE_64BIT
)
1970 cpu_arch_flags
.bitfield
.cpu64
= 1;
1971 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1975 cpu_arch_flags
.bitfield
.cpu64
= 0;
1976 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1978 cpu_arch_isa
= cpu_arch
[i
].type
;
1979 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1980 if (!cpu_arch_tune_set
)
1982 cpu_arch_tune
= cpu_arch_isa
;
1983 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1988 flags
= cpu_flags_or (cpu_arch_flags
,
1990 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1992 if (cpu_sub_arch_name
)
1994 char *name
= cpu_sub_arch_name
;
1995 cpu_sub_arch_name
= concat (name
,
1997 (const char *) NULL
);
2001 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2002 cpu_arch_flags
= flags
;
2004 *input_line_pointer
= e
;
2005 demand_empty_rest_of_line ();
2009 if (i
>= ARRAY_SIZE (cpu_arch
))
2010 as_bad (_("no such architecture: `%s'"), string
);
2012 *input_line_pointer
= e
;
2015 as_bad (_("missing cpu architecture"));
2017 no_cond_jump_promotion
= 0;
2018 if (*input_line_pointer
== ','
2019 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2021 char *string
= ++input_line_pointer
;
2022 int e
= get_symbol_end ();
2024 if (strcmp (string
, "nojumps") == 0)
2025 no_cond_jump_promotion
= 1;
2026 else if (strcmp (string
, "jumps") == 0)
2029 as_bad (_("no such architecture modifier: `%s'"), string
);
2031 *input_line_pointer
= e
;
2034 demand_empty_rest_of_line ();
2040 if (!strcmp (default_arch
, "x86_64"))
2041 return bfd_mach_x86_64
;
2042 else if (!strcmp (default_arch
, "i386"))
2043 return bfd_mach_i386_i386
;
2045 as_fatal (_("Unknown architecture"));
2051 const char *hash_err
;
2053 /* Initialize op_hash hash table. */
2054 op_hash
= hash_new ();
2057 const template *optab
;
2058 templates
*core_optab
;
2060 /* Setup for loop. */
2062 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2063 core_optab
->start
= optab
;
2068 if (optab
->name
== NULL
2069 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2071 /* different name --> ship out current template list;
2072 add to hash table; & begin anew. */
2073 core_optab
->end
= optab
;
2074 hash_err
= hash_insert (op_hash
,
2076 (void *) core_optab
);
2079 as_fatal (_("Internal Error: Can't hash %s: %s"),
2083 if (optab
->name
== NULL
)
2085 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2086 core_optab
->start
= optab
;
2091 /* Initialize reg_hash hash table. */
2092 reg_hash
= hash_new ();
2094 const reg_entry
*regtab
;
2095 unsigned int regtab_size
= i386_regtab_size
;
2097 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2099 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2101 as_fatal (_("Internal Error: Can't hash %s: %s"),
2107 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2112 for (c
= 0; c
< 256; c
++)
2117 mnemonic_chars
[c
] = c
;
2118 register_chars
[c
] = c
;
2119 operand_chars
[c
] = c
;
2121 else if (ISLOWER (c
))
2123 mnemonic_chars
[c
] = c
;
2124 register_chars
[c
] = c
;
2125 operand_chars
[c
] = c
;
2127 else if (ISUPPER (c
))
2129 mnemonic_chars
[c
] = TOLOWER (c
);
2130 register_chars
[c
] = mnemonic_chars
[c
];
2131 operand_chars
[c
] = c
;
2134 if (ISALPHA (c
) || ISDIGIT (c
))
2135 identifier_chars
[c
] = c
;
2138 identifier_chars
[c
] = c
;
2139 operand_chars
[c
] = c
;
2144 identifier_chars
['@'] = '@';
2147 identifier_chars
['?'] = '?';
2148 operand_chars
['?'] = '?';
2150 digit_chars
['-'] = '-';
2151 mnemonic_chars
['_'] = '_';
2152 mnemonic_chars
['-'] = '-';
2153 mnemonic_chars
['.'] = '.';
2154 identifier_chars
['_'] = '_';
2155 identifier_chars
['.'] = '.';
2157 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2158 operand_chars
[(unsigned char) *p
] = *p
;
2161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2164 record_alignment (text_section
, 2);
2165 record_alignment (data_section
, 2);
2166 record_alignment (bss_section
, 2);
2170 if (flag_code
== CODE_64BIT
)
2172 x86_dwarf2_return_column
= 16;
2173 x86_cie_data_alignment
= -8;
2177 x86_dwarf2_return_column
= 8;
2178 x86_cie_data_alignment
= -4;
2183 i386_print_statistics (FILE *file
)
2185 hash_print_statistics (file
, "i386 opcode", op_hash
);
2186 hash_print_statistics (file
, "i386 register", reg_hash
);
2191 /* Debugging routines for md_assemble. */
2192 static void pte (template *);
2193 static void pt (i386_operand_type
);
2194 static void pe (expressionS
*);
2195 static void ps (symbolS
*);
2198 pi (char *line
, i386_insn
*x
)
2202 fprintf (stdout
, "%s: template ", line
);
2204 fprintf (stdout
, " address: base %s index %s scale %x\n",
2205 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2206 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2207 x
->log2_scale_factor
);
2208 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2209 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2210 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2211 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2212 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2213 (x
->rex
& REX_W
) != 0,
2214 (x
->rex
& REX_R
) != 0,
2215 (x
->rex
& REX_X
) != 0,
2216 (x
->rex
& REX_B
) != 0);
2217 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2218 x
->drex
.reg
, x
->drex
.rex
);
2219 for (i
= 0; i
< x
->operands
; i
++)
2221 fprintf (stdout
, " #%d: ", i
+ 1);
2223 fprintf (stdout
, "\n");
2224 if (x
->types
[i
].bitfield
.reg8
2225 || x
->types
[i
].bitfield
.reg16
2226 || x
->types
[i
].bitfield
.reg32
2227 || x
->types
[i
].bitfield
.reg64
2228 || x
->types
[i
].bitfield
.regmmx
2229 || x
->types
[i
].bitfield
.regxmm
2230 || x
->types
[i
].bitfield
.regymm
2231 || x
->types
[i
].bitfield
.sreg2
2232 || x
->types
[i
].bitfield
.sreg3
2233 || x
->types
[i
].bitfield
.control
2234 || x
->types
[i
].bitfield
.debug
2235 || x
->types
[i
].bitfield
.test
)
2236 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2237 if (operand_type_check (x
->types
[i
], imm
))
2239 if (operand_type_check (x
->types
[i
], disp
))
2240 pe (x
->op
[i
].disps
);
2248 fprintf (stdout
, " %d operands ", t
->operands
);
2249 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2250 if (t
->extension_opcode
!= None
)
2251 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2252 if (t
->opcode_modifier
.d
)
2253 fprintf (stdout
, "D");
2254 if (t
->opcode_modifier
.w
)
2255 fprintf (stdout
, "W");
2256 fprintf (stdout
, "\n");
2257 for (i
= 0; i
< t
->operands
; i
++)
2259 fprintf (stdout
, " #%d type ", i
+ 1);
2260 pt (t
->operand_types
[i
]);
2261 fprintf (stdout
, "\n");
2268 fprintf (stdout
, " operation %d\n", e
->X_op
);
2269 fprintf (stdout
, " add_number %ld (%lx)\n",
2270 (long) e
->X_add_number
, (long) e
->X_add_number
);
2271 if (e
->X_add_symbol
)
2273 fprintf (stdout
, " add_symbol ");
2274 ps (e
->X_add_symbol
);
2275 fprintf (stdout
, "\n");
2279 fprintf (stdout
, " op_symbol ");
2280 ps (e
->X_op_symbol
);
2281 fprintf (stdout
, "\n");
2288 fprintf (stdout
, "%s type %s%s",
2290 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2291 segment_name (S_GET_SEGMENT (s
)));
2294 static struct type_name
2296 i386_operand_type mask
;
2299 const type_names
[] =
2301 { OPERAND_TYPE_REG8
, "r8" },
2302 { OPERAND_TYPE_REG16
, "r16" },
2303 { OPERAND_TYPE_REG32
, "r32" },
2304 { OPERAND_TYPE_REG64
, "r64" },
2305 { OPERAND_TYPE_IMM8
, "i8" },
2306 { OPERAND_TYPE_IMM8
, "i8s" },
2307 { OPERAND_TYPE_IMM16
, "i16" },
2308 { OPERAND_TYPE_IMM32
, "i32" },
2309 { OPERAND_TYPE_IMM32S
, "i32s" },
2310 { OPERAND_TYPE_IMM64
, "i64" },
2311 { OPERAND_TYPE_IMM1
, "i1" },
2312 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2313 { OPERAND_TYPE_DISP8
, "d8" },
2314 { OPERAND_TYPE_DISP16
, "d16" },
2315 { OPERAND_TYPE_DISP32
, "d32" },
2316 { OPERAND_TYPE_DISP32S
, "d32s" },
2317 { OPERAND_TYPE_DISP64
, "d64" },
2318 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2319 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2320 { OPERAND_TYPE_CONTROL
, "control reg" },
2321 { OPERAND_TYPE_TEST
, "test reg" },
2322 { OPERAND_TYPE_DEBUG
, "debug reg" },
2323 { OPERAND_TYPE_FLOATREG
, "FReg" },
2324 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2325 { OPERAND_TYPE_SREG2
, "SReg2" },
2326 { OPERAND_TYPE_SREG3
, "SReg3" },
2327 { OPERAND_TYPE_ACC
, "Acc" },
2328 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2329 { OPERAND_TYPE_REGMMX
, "rMMX" },
2330 { OPERAND_TYPE_REGXMM
, "rXMM" },
2331 { OPERAND_TYPE_REGYMM
, "rYMM" },
2332 { OPERAND_TYPE_ESSEG
, "es" },
2336 pt (i386_operand_type t
)
2339 i386_operand_type a
;
2341 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2343 a
= operand_type_and (t
, type_names
[j
].mask
);
2344 if (!operand_type_all_zero (&a
))
2345 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2350 #endif /* DEBUG386 */
2352 static bfd_reloc_code_real_type
2353 reloc (unsigned int size
,
2356 bfd_reloc_code_real_type other
)
2358 if (other
!= NO_RELOC
)
2360 reloc_howto_type
*reloc
;
2365 case BFD_RELOC_X86_64_GOT32
:
2366 return BFD_RELOC_X86_64_GOT64
;
2368 case BFD_RELOC_X86_64_PLTOFF64
:
2369 return BFD_RELOC_X86_64_PLTOFF64
;
2371 case BFD_RELOC_X86_64_GOTPC32
:
2372 other
= BFD_RELOC_X86_64_GOTPC64
;
2374 case BFD_RELOC_X86_64_GOTPCREL
:
2375 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2377 case BFD_RELOC_X86_64_TPOFF32
:
2378 other
= BFD_RELOC_X86_64_TPOFF64
;
2380 case BFD_RELOC_X86_64_DTPOFF32
:
2381 other
= BFD_RELOC_X86_64_DTPOFF64
;
2387 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2388 if (size
== 4 && flag_code
!= CODE_64BIT
)
2391 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2393 as_bad (_("unknown relocation (%u)"), other
);
2394 else if (size
!= bfd_get_reloc_size (reloc
))
2395 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2396 bfd_get_reloc_size (reloc
),
2398 else if (pcrel
&& !reloc
->pc_relative
)
2399 as_bad (_("non-pc-relative relocation for pc-relative field"));
2400 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2402 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2404 as_bad (_("relocated field and relocation type differ in signedness"));
2413 as_bad (_("there are no unsigned pc-relative relocations"));
2416 case 1: return BFD_RELOC_8_PCREL
;
2417 case 2: return BFD_RELOC_16_PCREL
;
2418 case 4: return BFD_RELOC_32_PCREL
;
2419 case 8: return BFD_RELOC_64_PCREL
;
2421 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2428 case 4: return BFD_RELOC_X86_64_32S
;
2433 case 1: return BFD_RELOC_8
;
2434 case 2: return BFD_RELOC_16
;
2435 case 4: return BFD_RELOC_32
;
2436 case 8: return BFD_RELOC_64
;
2438 as_bad (_("cannot do %s %u byte relocation"),
2439 sign
> 0 ? "signed" : "unsigned", size
);
2443 return BFD_RELOC_NONE
;
2446 /* Here we decide which fixups can be adjusted to make them relative to
2447 the beginning of the section instead of the symbol. Basically we need
2448 to make sure that the dynamic relocations are done correctly, so in
2449 some cases we force the original symbol to be used. */
2452 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2458 /* Don't adjust pc-relative references to merge sections in 64-bit
2460 if (use_rela_relocations
2461 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2465 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2466 and changed later by validate_fix. */
2467 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2468 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2471 /* adjust_reloc_syms doesn't know about the GOT. */
2472 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2473 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2474 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2479 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2480 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2481 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2498 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2499 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2506 intel_float_operand (const char *mnemonic
)
2508 /* Note that the value returned is meaningful only for opcodes with (memory)
2509 operands, hence the code here is free to improperly handle opcodes that
2510 have no operands (for better performance and smaller code). */
2512 if (mnemonic
[0] != 'f')
2513 return 0; /* non-math */
2515 switch (mnemonic
[1])
2517 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2518 the fs segment override prefix not currently handled because no
2519 call path can make opcodes without operands get here */
2521 return 2 /* integer op */;
2523 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2524 return 3; /* fldcw/fldenv */
2527 if (mnemonic
[2] != 'o' /* fnop */)
2528 return 3; /* non-waiting control op */
2531 if (mnemonic
[2] == 's')
2532 return 3; /* frstor/frstpm */
2535 if (mnemonic
[2] == 'a')
2536 return 3; /* fsave */
2537 if (mnemonic
[2] == 't')
2539 switch (mnemonic
[3])
2541 case 'c': /* fstcw */
2542 case 'd': /* fstdw */
2543 case 'e': /* fstenv */
2544 case 's': /* fsts[gw] */
2550 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2551 return 0; /* fxsave/fxrstor are not really math ops */
2558 /* Build the VEX prefix. */
2561 build_vex_prefix (const template *t
)
2563 unsigned int register_specifier
;
2564 unsigned int implied_prefix
;
2565 unsigned int vector_length
;
2567 /* Check register specifier. */
2568 if (i
.vex
.register_specifier
)
2570 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2571 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2572 register_specifier
+= 8;
2573 register_specifier
= ~register_specifier
& 0xf;
2576 register_specifier
= 0xf;
2578 /* Use 2-byte VEX prefix by swappping destination and source
2581 && i
.operands
== i
.reg_operands
2582 && i
.tm
.opcode_modifier
.vex0f
2583 && i
.tm
.opcode_modifier
.s
2586 unsigned int xchg
= i
.operands
- 1;
2587 union i386_op temp_op
;
2588 i386_operand_type temp_type
;
2590 temp_type
= i
.types
[xchg
];
2591 i
.types
[xchg
] = i
.types
[0];
2592 i
.types
[0] = temp_type
;
2593 temp_op
= i
.op
[xchg
];
2594 i
.op
[xchg
] = i
.op
[0];
2597 assert (i
.rm
.mode
== 3);
2601 i
.rm
.regmem
= i
.rm
.reg
;
2604 /* Use the next insn. */
2608 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2610 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2615 case DATA_PREFIX_OPCODE
:
2618 case REPE_PREFIX_OPCODE
:
2621 case REPNE_PREFIX_OPCODE
:
2628 /* Use 2-byte VEX prefix if possible. */
2629 if (i
.tm
.opcode_modifier
.vex0f
2630 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2632 /* 2-byte VEX prefix. */
2636 i
.vex
.bytes
[0] = 0xc5;
2638 /* Check the REX.R bit. */
2639 r
= (i
.rex
& REX_R
) ? 0 : 1;
2640 i
.vex
.bytes
[1] = (r
<< 7
2641 | register_specifier
<< 3
2642 | vector_length
<< 2
2647 /* 3-byte VEX prefix. */
2650 if (i
.tm
.opcode_modifier
.vex0f
)
2652 else if (i
.tm
.opcode_modifier
.vex0f38
)
2654 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2660 i
.vex
.bytes
[0] = 0xc4;
2662 /* The high 3 bits of the second VEX byte are 1's compliment
2663 of RXB bits from REX. */
2664 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2666 /* Check the REX.W bit. */
2667 w
= (i
.rex
& REX_W
) ? 1 : 0;
2668 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2673 if (i
.tm
.opcode_modifier
.vexw1
)
2677 i
.vex
.bytes
[2] = (w
<< 7
2678 | register_specifier
<< 3
2679 | vector_length
<< 2
2685 process_immext (void)
2689 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2691 /* SSE3 Instructions have the fixed operands with an opcode
2692 suffix which is coded in the same place as an 8-bit immediate
2693 field would be. Here we check those operands and remove them
2697 for (x
= 0; x
< i
.operands
; x
++)
2698 if (i
.op
[x
].regs
->reg_num
!= x
)
2699 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2700 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2706 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2707 which is coded in the same place as an 8-bit immediate field
2708 would be. Here we fake an 8-bit immediate operand from the
2709 opcode suffix stored in tm.extension_opcode.
2711 SSE5 and AVX instructions also use this encoding, for some of
2712 3 argument instructions. */
2714 assert (i
.imm_operands
== 0
2716 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2718 || (i
.tm
.opcode_modifier
.vex
2719 && i
.operands
<= 4)));
2721 exp
= &im_expressions
[i
.imm_operands
++];
2722 i
.op
[i
.operands
].imms
= exp
;
2723 i
.types
[i
.operands
] = imm8
;
2725 exp
->X_op
= O_constant
;
2726 exp
->X_add_number
= i
.tm
.extension_opcode
;
2727 i
.tm
.extension_opcode
= None
;
2730 /* This is the guts of the machine-dependent assembler. LINE points to a
2731 machine dependent instruction. This function is supposed to emit
2732 the frags/bytes it assembles to. */
2735 md_assemble (char *line
)
2738 char mnemonic
[MAX_MNEM_SIZE
];
2741 /* Initialize globals. */
2742 memset (&i
, '\0', sizeof (i
));
2743 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2744 i
.reloc
[j
] = NO_RELOC
;
2745 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2746 memset (im_expressions
, '\0', sizeof (im_expressions
));
2747 save_stack_p
= save_stack
;
2749 /* First parse an instruction mnemonic & call i386_operand for the operands.
2750 We assume that the scrubber has arranged it so that line[0] is the valid
2751 start of a (possibly prefixed) mnemonic. */
2753 line
= parse_insn (line
, mnemonic
);
2757 line
= parse_operands (line
, mnemonic
);
2761 /* Now we've parsed the mnemonic into a set of templates, and have the
2762 operands at hand. */
2764 /* All intel opcodes have reversed operands except for "bound" and
2765 "enter". We also don't reverse intersegment "jmp" and "call"
2766 instructions with 2 immediate operands so that the immediate segment
2767 precedes the offset, as it does when in AT&T mode. */
2770 && (strcmp (mnemonic
, "bound") != 0)
2771 && (strcmp (mnemonic
, "invlpga") != 0)
2772 && !(operand_type_check (i
.types
[0], imm
)
2773 && operand_type_check (i
.types
[1], imm
)))
2776 /* The order of the immediates should be reversed
2777 for 2 immediates extrq and insertq instructions */
2778 if (i
.imm_operands
== 2
2779 && (strcmp (mnemonic
, "extrq") == 0
2780 || strcmp (mnemonic
, "insertq") == 0))
2781 swap_2_operands (0, 1);
2786 /* Don't optimize displacement for movabs since it only takes 64bit
2789 && (flag_code
!= CODE_64BIT
2790 || strcmp (mnemonic
, "movabs") != 0))
2793 /* Next, we find a template that matches the given insn,
2794 making sure the overlap of the given operands types is consistent
2795 with the template operand types. */
2797 if (!(t
= match_template ()))
2800 if (sse_check
!= sse_check_none
2801 && !i
.tm
.opcode_modifier
.noavx
2802 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2803 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2804 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2805 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2806 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2807 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2809 (sse_check
== sse_check_warning
2811 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2814 /* Zap movzx and movsx suffix. The suffix has been set from
2815 "word ptr" or "byte ptr" on the source operand in Intel syntax
2816 or extracted from mnemonic in AT&T syntax. But we'll use
2817 the destination register to choose the suffix for encoding. */
2818 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2820 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2821 there is no suffix, the default will be byte extension. */
2822 if (i
.reg_operands
!= 2
2825 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2830 if (i
.tm
.opcode_modifier
.fwait
)
2831 if (!add_prefix (FWAIT_OPCODE
))
2834 /* Check string instruction segment overrides. */
2835 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2837 if (!check_string ())
2839 i
.disp_operands
= 0;
2842 if (!process_suffix ())
2845 /* Make still unresolved immediate matches conform to size of immediate
2846 given in i.suffix. */
2847 if (!finalize_imm ())
2850 if (i
.types
[0].bitfield
.imm1
)
2851 i
.imm_operands
= 0; /* kludge for shift insns. */
2853 for (j
= 0; j
< 3; j
++)
2854 if (i
.types
[j
].bitfield
.inoutportreg
2855 || i
.types
[j
].bitfield
.shiftcount
2856 || i
.types
[j
].bitfield
.acc
2857 || i
.types
[j
].bitfield
.floatacc
)
2860 /* ImmExt should be processed after SSE2AVX. */
2861 if (!i
.tm
.opcode_modifier
.sse2avx
2862 && i
.tm
.opcode_modifier
.immext
)
2865 /* For insns with operands there are more diddles to do to the opcode. */
2868 if (!process_operands ())
2871 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2873 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2874 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2877 if (i
.tm
.opcode_modifier
.vex
)
2878 build_vex_prefix (t
);
2880 /* Handle conversion of 'int $3' --> special int3 insn. */
2881 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2883 i
.tm
.base_opcode
= INT3_OPCODE
;
2887 if ((i
.tm
.opcode_modifier
.jump
2888 || i
.tm
.opcode_modifier
.jumpbyte
2889 || i
.tm
.opcode_modifier
.jumpdword
)
2890 && i
.op
[0].disps
->X_op
== O_constant
)
2892 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2893 the absolute address given by the constant. Since ix86 jumps and
2894 calls are pc relative, we need to generate a reloc. */
2895 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2896 i
.op
[0].disps
->X_op
= O_symbol
;
2899 if (i
.tm
.opcode_modifier
.rex64
)
2902 /* For 8 bit registers we need an empty rex prefix. Also if the
2903 instruction already has a prefix, we need to convert old
2904 registers to new ones. */
2906 if ((i
.types
[0].bitfield
.reg8
2907 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2908 || (i
.types
[1].bitfield
.reg8
2909 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2910 || ((i
.types
[0].bitfield
.reg8
2911 || i
.types
[1].bitfield
.reg8
)
2916 i
.rex
|= REX_OPCODE
;
2917 for (x
= 0; x
< 2; x
++)
2919 /* Look for 8 bit operand that uses old registers. */
2920 if (i
.types
[x
].bitfield
.reg8
2921 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2923 /* In case it is "hi" register, give up. */
2924 if (i
.op
[x
].regs
->reg_num
> 3)
2925 as_bad (_("can't encode register '%s%s' in an "
2926 "instruction requiring REX prefix."),
2927 register_prefix
, i
.op
[x
].regs
->reg_name
);
2929 /* Otherwise it is equivalent to the extended register.
2930 Since the encoding doesn't change this is merely
2931 cosmetic cleanup for debug output. */
2933 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2938 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2940 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2945 else if (i
.rex
!= 0)
2946 add_prefix (REX_OPCODE
| i
.rex
);
2948 /* We are ready to output the insn. */
2953 parse_insn (char *line
, char *mnemonic
)
2956 char *token_start
= l
;
2962 /* Non-zero if we found a prefix only acceptable with string insns. */
2963 const char *expecting_string_instruction
= NULL
;
2968 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2973 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2975 as_bad (_("no such instruction: `%s'"), token_start
);
2980 if (!is_space_char (*l
)
2981 && *l
!= END_OF_INSN
2983 || (*l
!= PREFIX_SEPARATOR
2986 as_bad (_("invalid character %s in mnemonic"),
2987 output_invalid (*l
));
2990 if (token_start
== l
)
2992 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2993 as_bad (_("expecting prefix; got nothing"));
2995 as_bad (_("expecting mnemonic; got nothing"));
2999 /* Look up instruction (or prefix) via hash table. */
3000 current_templates
= hash_find (op_hash
, mnemonic
);
3002 if (*l
!= END_OF_INSN
3003 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3004 && current_templates
3005 && current_templates
->start
->opcode_modifier
.isprefix
)
3007 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3009 as_bad ((flag_code
!= CODE_64BIT
3010 ? _("`%s' is only supported in 64-bit mode")
3011 : _("`%s' is not supported in 64-bit mode")),
3012 current_templates
->start
->name
);
3015 /* If we are in 16-bit mode, do not allow addr16 or data16.
3016 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3017 if ((current_templates
->start
->opcode_modifier
.size16
3018 || current_templates
->start
->opcode_modifier
.size32
)
3019 && flag_code
!= CODE_64BIT
3020 && (current_templates
->start
->opcode_modifier
.size32
3021 ^ (flag_code
== CODE_16BIT
)))
3023 as_bad (_("redundant %s prefix"),
3024 current_templates
->start
->name
);
3027 /* Add prefix, checking for repeated prefixes. */
3028 switch (add_prefix (current_templates
->start
->base_opcode
))
3033 expecting_string_instruction
= current_templates
->start
->name
;
3036 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3043 if (!current_templates
)
3045 /* Check if we should swap operand in encoding. */
3046 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3052 current_templates
= hash_find (op_hash
, mnemonic
);
3055 if (!current_templates
)
3058 /* See if we can get a match by trimming off a suffix. */
3061 case WORD_MNEM_SUFFIX
:
3062 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3063 i
.suffix
= SHORT_MNEM_SUFFIX
;
3065 case BYTE_MNEM_SUFFIX
:
3066 case QWORD_MNEM_SUFFIX
:
3067 i
.suffix
= mnem_p
[-1];
3069 current_templates
= hash_find (op_hash
, mnemonic
);
3071 case SHORT_MNEM_SUFFIX
:
3072 case LONG_MNEM_SUFFIX
:
3075 i
.suffix
= mnem_p
[-1];
3077 current_templates
= hash_find (op_hash
, mnemonic
);
3085 if (intel_float_operand (mnemonic
) == 1)
3086 i
.suffix
= SHORT_MNEM_SUFFIX
;
3088 i
.suffix
= LONG_MNEM_SUFFIX
;
3090 current_templates
= hash_find (op_hash
, mnemonic
);
3094 if (!current_templates
)
3096 as_bad (_("no such instruction: `%s'"), token_start
);
3101 if (current_templates
->start
->opcode_modifier
.jump
3102 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3104 /* Check for a branch hint. We allow ",pt" and ",pn" for
3105 predict taken and predict not taken respectively.
3106 I'm not sure that branch hints actually do anything on loop
3107 and jcxz insns (JumpByte) for current Pentium4 chips. They
3108 may work in the future and it doesn't hurt to accept them
3110 if (l
[0] == ',' && l
[1] == 'p')
3114 if (!add_prefix (DS_PREFIX_OPCODE
))
3118 else if (l
[2] == 'n')
3120 if (!add_prefix (CS_PREFIX_OPCODE
))
3126 /* Any other comma loses. */
3129 as_bad (_("invalid character %s in mnemonic"),
3130 output_invalid (*l
));
3134 /* Check if instruction is supported on specified architecture. */
3136 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3138 supported
|= cpu_flags_match (t
);
3139 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3143 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3145 as_bad (flag_code
== CODE_64BIT
3146 ? _("`%s' is not supported in 64-bit mode")
3147 : _("`%s' is only supported in 64-bit mode"),
3148 current_templates
->start
->name
);
3151 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3153 as_bad (_("`%s' is not supported on `%s%s'"),
3154 current_templates
->start
->name
, cpu_arch_name
,
3155 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3160 if (!cpu_arch_flags
.bitfield
.cpui386
3161 && (flag_code
!= CODE_16BIT
))
3163 as_warn (_("use .code16 to ensure correct addressing mode"));
3166 /* Check for rep/repne without a string instruction. */
3167 if (expecting_string_instruction
)
3169 static templates override
;
3171 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3172 if (t
->opcode_modifier
.isstring
)
3174 if (t
>= current_templates
->end
)
3176 as_bad (_("expecting string instruction after `%s'"),
3177 expecting_string_instruction
);
3180 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3181 if (!t
->opcode_modifier
.isstring
)
3184 current_templates
= &override
;
3191 parse_operands (char *l
, const char *mnemonic
)
3195 /* 1 if operand is pending after ','. */
3196 unsigned int expecting_operand
= 0;
3198 /* Non-zero if operand parens not balanced. */
3199 unsigned int paren_not_balanced
;
3201 while (*l
!= END_OF_INSN
)
3203 /* Skip optional white space before operand. */
3204 if (is_space_char (*l
))
3206 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3208 as_bad (_("invalid character %s before operand %d"),
3209 output_invalid (*l
),
3213 token_start
= l
; /* after white space */
3214 paren_not_balanced
= 0;
3215 while (paren_not_balanced
|| *l
!= ',')
3217 if (*l
== END_OF_INSN
)
3219 if (paren_not_balanced
)
3222 as_bad (_("unbalanced parenthesis in operand %d."),
3225 as_bad (_("unbalanced brackets in operand %d."),
3230 break; /* we are done */
3232 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3234 as_bad (_("invalid character %s in operand %d"),
3235 output_invalid (*l
),
3242 ++paren_not_balanced
;
3244 --paren_not_balanced
;
3249 ++paren_not_balanced
;
3251 --paren_not_balanced
;
3255 if (l
!= token_start
)
3256 { /* Yes, we've read in another operand. */
3257 unsigned int operand_ok
;
3258 this_operand
= i
.operands
++;
3259 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3260 if (i
.operands
> MAX_OPERANDS
)
3262 as_bad (_("spurious operands; (%d operands/instruction max)"),
3266 /* Now parse operand adding info to 'i' as we go along. */
3267 END_STRING_AND_SAVE (l
);
3271 i386_intel_operand (token_start
,
3272 intel_float_operand (mnemonic
));
3274 operand_ok
= i386_att_operand (token_start
);
3276 RESTORE_END_STRING (l
);
3282 if (expecting_operand
)
3284 expecting_operand_after_comma
:
3285 as_bad (_("expecting operand after ','; got nothing"));
3290 as_bad (_("expecting operand before ','; got nothing"));
3295 /* Now *l must be either ',' or END_OF_INSN. */
3298 if (*++l
== END_OF_INSN
)
3300 /* Just skip it, if it's \n complain. */
3301 goto expecting_operand_after_comma
;
3303 expecting_operand
= 1;
3310 swap_2_operands (int xchg1
, int xchg2
)
3312 union i386_op temp_op
;
3313 i386_operand_type temp_type
;
3314 enum bfd_reloc_code_real temp_reloc
;
3316 temp_type
= i
.types
[xchg2
];
3317 i
.types
[xchg2
] = i
.types
[xchg1
];
3318 i
.types
[xchg1
] = temp_type
;
3319 temp_op
= i
.op
[xchg2
];
3320 i
.op
[xchg2
] = i
.op
[xchg1
];
3321 i
.op
[xchg1
] = temp_op
;
3322 temp_reloc
= i
.reloc
[xchg2
];
3323 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3324 i
.reloc
[xchg1
] = temp_reloc
;
3328 swap_operands (void)
3334 swap_2_operands (1, i
.operands
- 2);
3337 swap_2_operands (0, i
.operands
- 1);
3343 if (i
.mem_operands
== 2)
3345 const seg_entry
*temp_seg
;
3346 temp_seg
= i
.seg
[0];
3347 i
.seg
[0] = i
.seg
[1];
3348 i
.seg
[1] = temp_seg
;
3352 /* Try to ensure constant immediates are represented in the smallest
3357 char guess_suffix
= 0;
3361 guess_suffix
= i
.suffix
;
3362 else if (i
.reg_operands
)
3364 /* Figure out a suffix from the last register operand specified.
3365 We can't do this properly yet, ie. excluding InOutPortReg,
3366 but the following works for instructions with immediates.
3367 In any case, we can't set i.suffix yet. */
3368 for (op
= i
.operands
; --op
>= 0;)
3369 if (i
.types
[op
].bitfield
.reg8
)
3371 guess_suffix
= BYTE_MNEM_SUFFIX
;
3374 else if (i
.types
[op
].bitfield
.reg16
)
3376 guess_suffix
= WORD_MNEM_SUFFIX
;
3379 else if (i
.types
[op
].bitfield
.reg32
)
3381 guess_suffix
= LONG_MNEM_SUFFIX
;
3384 else if (i
.types
[op
].bitfield
.reg64
)
3386 guess_suffix
= QWORD_MNEM_SUFFIX
;
3390 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3391 guess_suffix
= WORD_MNEM_SUFFIX
;
3393 for (op
= i
.operands
; --op
>= 0;)
3394 if (operand_type_check (i
.types
[op
], imm
))
3396 switch (i
.op
[op
].imms
->X_op
)
3399 /* If a suffix is given, this operand may be shortened. */
3400 switch (guess_suffix
)
3402 case LONG_MNEM_SUFFIX
:
3403 i
.types
[op
].bitfield
.imm32
= 1;
3404 i
.types
[op
].bitfield
.imm64
= 1;
3406 case WORD_MNEM_SUFFIX
:
3407 i
.types
[op
].bitfield
.imm16
= 1;
3408 i
.types
[op
].bitfield
.imm32
= 1;
3409 i
.types
[op
].bitfield
.imm32s
= 1;
3410 i
.types
[op
].bitfield
.imm64
= 1;
3412 case BYTE_MNEM_SUFFIX
:
3413 i
.types
[op
].bitfield
.imm8
= 1;
3414 i
.types
[op
].bitfield
.imm8s
= 1;
3415 i
.types
[op
].bitfield
.imm16
= 1;
3416 i
.types
[op
].bitfield
.imm32
= 1;
3417 i
.types
[op
].bitfield
.imm32s
= 1;
3418 i
.types
[op
].bitfield
.imm64
= 1;
3422 /* If this operand is at most 16 bits, convert it
3423 to a signed 16 bit number before trying to see
3424 whether it will fit in an even smaller size.
3425 This allows a 16-bit operand such as $0xffe0 to
3426 be recognised as within Imm8S range. */
3427 if ((i
.types
[op
].bitfield
.imm16
)
3428 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3430 i
.op
[op
].imms
->X_add_number
=
3431 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3433 if ((i
.types
[op
].bitfield
.imm32
)
3434 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3437 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3438 ^ ((offsetT
) 1 << 31))
3439 - ((offsetT
) 1 << 31));
3442 = operand_type_or (i
.types
[op
],
3443 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3445 /* We must avoid matching of Imm32 templates when 64bit
3446 only immediate is available. */
3447 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3448 i
.types
[op
].bitfield
.imm32
= 0;
3455 /* Symbols and expressions. */
3457 /* Convert symbolic operand to proper sizes for matching, but don't
3458 prevent matching a set of insns that only supports sizes other
3459 than those matching the insn suffix. */
3461 i386_operand_type mask
, allowed
;
3464 operand_type_set (&mask
, 0);
3465 operand_type_set (&allowed
, 0);
3467 for (t
= current_templates
->start
;
3468 t
< current_templates
->end
;
3470 allowed
= operand_type_or (allowed
,
3471 t
->operand_types
[op
]);
3472 switch (guess_suffix
)
3474 case QWORD_MNEM_SUFFIX
:
3475 mask
.bitfield
.imm64
= 1;
3476 mask
.bitfield
.imm32s
= 1;
3478 case LONG_MNEM_SUFFIX
:
3479 mask
.bitfield
.imm32
= 1;
3481 case WORD_MNEM_SUFFIX
:
3482 mask
.bitfield
.imm16
= 1;
3484 case BYTE_MNEM_SUFFIX
:
3485 mask
.bitfield
.imm8
= 1;
3490 allowed
= operand_type_and (mask
, allowed
);
3491 if (!operand_type_all_zero (&allowed
))
3492 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3499 /* Try to use the smallest displacement type too. */
3501 optimize_disp (void)
3505 for (op
= i
.operands
; --op
>= 0;)
3506 if (operand_type_check (i
.types
[op
], disp
))
3508 if (i
.op
[op
].disps
->X_op
== O_constant
)
3510 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3512 if (i
.types
[op
].bitfield
.disp16
3513 && (disp
& ~(offsetT
) 0xffff) == 0)
3515 /* If this operand is at most 16 bits, convert
3516 to a signed 16 bit number and don't use 64bit
3518 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3519 i
.types
[op
].bitfield
.disp64
= 0;
3521 if (i
.types
[op
].bitfield
.disp32
3522 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3524 /* If this operand is at most 32 bits, convert
3525 to a signed 32 bit number and don't use 64bit
3527 disp
&= (((offsetT
) 2 << 31) - 1);
3528 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3529 i
.types
[op
].bitfield
.disp64
= 0;
3531 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3533 i
.types
[op
].bitfield
.disp8
= 0;
3534 i
.types
[op
].bitfield
.disp16
= 0;
3535 i
.types
[op
].bitfield
.disp32
= 0;
3536 i
.types
[op
].bitfield
.disp32s
= 0;
3537 i
.types
[op
].bitfield
.disp64
= 0;
3541 else if (flag_code
== CODE_64BIT
)
3543 if (fits_in_signed_long (disp
))
3545 i
.types
[op
].bitfield
.disp64
= 0;
3546 i
.types
[op
].bitfield
.disp32s
= 1;
3548 if (fits_in_unsigned_long (disp
))
3549 i
.types
[op
].bitfield
.disp32
= 1;
3551 if ((i
.types
[op
].bitfield
.disp32
3552 || i
.types
[op
].bitfield
.disp32s
3553 || i
.types
[op
].bitfield
.disp16
)
3554 && fits_in_signed_byte (disp
))
3555 i
.types
[op
].bitfield
.disp8
= 1;
3557 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3558 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3560 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3561 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3562 i
.types
[op
].bitfield
.disp8
= 0;
3563 i
.types
[op
].bitfield
.disp16
= 0;
3564 i
.types
[op
].bitfield
.disp32
= 0;
3565 i
.types
[op
].bitfield
.disp32s
= 0;
3566 i
.types
[op
].bitfield
.disp64
= 0;
3569 /* We only support 64bit displacement on constants. */
3570 i
.types
[op
].bitfield
.disp64
= 0;
3574 static const template *
3575 match_template (void)
3577 /* Points to template once we've found it. */
3579 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3580 i386_operand_type overlap4
;
3581 unsigned int found_reverse_match
;
3582 i386_opcode_modifier suffix_check
;
3583 i386_operand_type operand_types
[MAX_OPERANDS
];
3584 int addr_prefix_disp
;
3586 unsigned int found_cpu_match
;
3587 unsigned int check_register
;
3589 #if MAX_OPERANDS != 5
3590 # error "MAX_OPERANDS must be 5."
3593 found_reverse_match
= 0;
3594 addr_prefix_disp
= -1;
3596 memset (&suffix_check
, 0, sizeof (suffix_check
));
3597 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3598 suffix_check
.no_bsuf
= 1;
3599 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3600 suffix_check
.no_wsuf
= 1;
3601 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3602 suffix_check
.no_ssuf
= 1;
3603 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3604 suffix_check
.no_lsuf
= 1;
3605 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3606 suffix_check
.no_qsuf
= 1;
3607 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3608 suffix_check
.no_ldsuf
= 1;
3610 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3612 addr_prefix_disp
= -1;
3614 /* Must have right number of operands. */
3615 if (i
.operands
!= t
->operands
)
3618 /* Check processor support. */
3619 found_cpu_match
= (cpu_flags_match (t
)
3620 == CPU_FLAGS_PERFECT_MATCH
);
3621 if (!found_cpu_match
)
3624 /* Check old gcc support. */
3625 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3628 /* Check AT&T mnemonic. */
3629 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3632 /* Check AT&T syntax Intel syntax. */
3633 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3634 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3637 /* Check the suffix, except for some instructions in intel mode. */
3638 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3639 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3640 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3641 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3642 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3643 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3644 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3647 if (!operand_size_match (t
))
3650 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3651 operand_types
[j
] = t
->operand_types
[j
];
3653 /* In general, don't allow 64-bit operands in 32-bit mode. */
3654 if (i
.suffix
== QWORD_MNEM_SUFFIX
3655 && flag_code
!= CODE_64BIT
3657 ? (!t
->opcode_modifier
.ignoresize
3658 && !intel_float_operand (t
->name
))
3659 : intel_float_operand (t
->name
) != 2)
3660 && ((!operand_types
[0].bitfield
.regmmx
3661 && !operand_types
[0].bitfield
.regxmm
3662 && !operand_types
[0].bitfield
.regymm
)
3663 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3664 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3665 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3666 && (t
->base_opcode
!= 0x0fc7
3667 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3670 /* In general, don't allow 32-bit operands on pre-386. */
3671 else if (i
.suffix
== LONG_MNEM_SUFFIX
3672 && !cpu_arch_flags
.bitfield
.cpui386
3674 ? (!t
->opcode_modifier
.ignoresize
3675 && !intel_float_operand (t
->name
))
3676 : intel_float_operand (t
->name
) != 2)
3677 && ((!operand_types
[0].bitfield
.regmmx
3678 && !operand_types
[0].bitfield
.regxmm
)
3679 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3680 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3683 /* Do not verify operands when there are none. */
3687 /* We've found a match; break out of loop. */
3691 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3692 into Disp32/Disp16/Disp32 operand. */
3693 if (i
.prefix
[ADDR_PREFIX
] != 0)
3695 /* There should be only one Disp operand. */
3699 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3701 if (operand_types
[j
].bitfield
.disp16
)
3703 addr_prefix_disp
= j
;
3704 operand_types
[j
].bitfield
.disp32
= 1;
3705 operand_types
[j
].bitfield
.disp16
= 0;
3711 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3713 if (operand_types
[j
].bitfield
.disp32
)
3715 addr_prefix_disp
= j
;
3716 operand_types
[j
].bitfield
.disp32
= 0;
3717 operand_types
[j
].bitfield
.disp16
= 1;
3723 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3725 if (operand_types
[j
].bitfield
.disp64
)
3727 addr_prefix_disp
= j
;
3728 operand_types
[j
].bitfield
.disp64
= 0;
3729 operand_types
[j
].bitfield
.disp32
= 1;
3737 /* We check register size only if size of operands can be
3738 encoded the canonical way. */
3739 check_register
= t
->opcode_modifier
.w
;
3740 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3741 switch (t
->operands
)
3744 if (!operand_type_match (overlap0
, i
.types
[0]))
3748 /* xchg %eax, %eax is a special case. It is an aliase for nop
3749 only in 32bit mode and we can use opcode 0x90. In 64bit
3750 mode, we can't use 0x90 for xchg %eax, %eax since it should
3751 zero-extend %eax to %rax. */
3752 if (flag_code
== CODE_64BIT
3753 && t
->base_opcode
== 0x90
3754 && operand_type_equal (&i
.types
[0], &acc32
)
3755 && operand_type_equal (&i
.types
[1], &acc32
))
3759 /* If we swap operand in encoding, we either match
3760 the next one or reverse direction of operands. */
3761 if (t
->opcode_modifier
.s
)
3763 else if (t
->opcode_modifier
.d
)
3768 /* If we swap operand in encoding, we match the next one. */
3769 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3773 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3774 if (!operand_type_match (overlap0
, i
.types
[0])
3775 || !operand_type_match (overlap1
, i
.types
[1])
3777 && !operand_type_register_match (overlap0
, i
.types
[0],
3779 overlap1
, i
.types
[1],
3782 /* Check if other direction is valid ... */
3783 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3787 /* Try reversing direction of operands. */
3788 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3789 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3790 if (!operand_type_match (overlap0
, i
.types
[0])
3791 || !operand_type_match (overlap1
, i
.types
[1])
3793 && !operand_type_register_match (overlap0
,
3800 /* Does not match either direction. */
3803 /* found_reverse_match holds which of D or FloatDR
3805 if (t
->opcode_modifier
.d
)
3806 found_reverse_match
= Opcode_D
;
3807 else if (t
->opcode_modifier
.floatd
)
3808 found_reverse_match
= Opcode_FloatD
;
3810 found_reverse_match
= 0;
3811 if (t
->opcode_modifier
.floatr
)
3812 found_reverse_match
|= Opcode_FloatR
;
3816 /* Found a forward 2 operand match here. */
3817 switch (t
->operands
)
3820 overlap4
= operand_type_and (i
.types
[4],
3823 overlap3
= operand_type_and (i
.types
[3],
3826 overlap2
= operand_type_and (i
.types
[2],
3831 switch (t
->operands
)
3834 if (!operand_type_match (overlap4
, i
.types
[4])
3835 || !operand_type_register_match (overlap3
,
3843 if (!operand_type_match (overlap3
, i
.types
[3])
3845 && !operand_type_register_match (overlap2
,
3853 /* Here we make use of the fact that there are no
3854 reverse match 3 operand instructions, and all 3
3855 operand instructions only need to be checked for
3856 register consistency between operands 2 and 3. */
3857 if (!operand_type_match (overlap2
, i
.types
[2])
3859 && !operand_type_register_match (overlap1
,
3869 /* Found either forward/reverse 2, 3 or 4 operand match here:
3870 slip through to break. */
3872 if (!found_cpu_match
)
3874 found_reverse_match
= 0;
3878 /* We've found a match; break out of loop. */
3882 if (t
== current_templates
->end
)
3884 /* We found no match. */
3886 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3887 current_templates
->start
->name
);
3889 as_bad (_("suffix or operands invalid for `%s'"),
3890 current_templates
->start
->name
);
3894 if (!quiet_warnings
)
3897 && (i
.types
[0].bitfield
.jumpabsolute
3898 != operand_types
[0].bitfield
.jumpabsolute
))
3900 as_warn (_("indirect %s without `*'"), t
->name
);
3903 if (t
->opcode_modifier
.isprefix
3904 && t
->opcode_modifier
.ignoresize
)
3906 /* Warn them that a data or address size prefix doesn't
3907 affect assembly of the next line of code. */
3908 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3912 /* Copy the template we found. */
3915 if (addr_prefix_disp
!= -1)
3916 i
.tm
.operand_types
[addr_prefix_disp
]
3917 = operand_types
[addr_prefix_disp
];
3919 if (found_reverse_match
)
3921 /* If we found a reverse match we must alter the opcode
3922 direction bit. found_reverse_match holds bits to change
3923 (different for int & float insns). */
3925 i
.tm
.base_opcode
^= found_reverse_match
;
3927 i
.tm
.operand_types
[0] = operand_types
[1];
3928 i
.tm
.operand_types
[1] = operand_types
[0];
3937 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3938 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3940 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3942 as_bad (_("`%s' operand %d must use `%ses' segment"),
3948 /* There's only ever one segment override allowed per instruction.
3949 This instruction possibly has a legal segment override on the
3950 second operand, so copy the segment to where non-string
3951 instructions store it, allowing common code. */
3952 i
.seg
[0] = i
.seg
[1];
3954 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3956 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3958 as_bad (_("`%s' operand %d must use `%ses' segment"),
3969 process_suffix (void)
3971 /* If matched instruction specifies an explicit instruction mnemonic
3973 if (i
.tm
.opcode_modifier
.size16
)
3974 i
.suffix
= WORD_MNEM_SUFFIX
;
3975 else if (i
.tm
.opcode_modifier
.size32
)
3976 i
.suffix
= LONG_MNEM_SUFFIX
;
3977 else if (i
.tm
.opcode_modifier
.size64
)
3978 i
.suffix
= QWORD_MNEM_SUFFIX
;
3979 else if (i
.reg_operands
)
3981 /* If there's no instruction mnemonic suffix we try to invent one
3982 based on register operands. */
3985 /* We take i.suffix from the last register operand specified,
3986 Destination register type is more significant than source
3987 register type. crc32 in SSE4.2 prefers source register
3989 if (i
.tm
.base_opcode
== 0xf20f38f1)
3991 if (i
.types
[0].bitfield
.reg16
)
3992 i
.suffix
= WORD_MNEM_SUFFIX
;
3993 else if (i
.types
[0].bitfield
.reg32
)
3994 i
.suffix
= LONG_MNEM_SUFFIX
;
3995 else if (i
.types
[0].bitfield
.reg64
)
3996 i
.suffix
= QWORD_MNEM_SUFFIX
;
3998 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4000 if (i
.types
[0].bitfield
.reg8
)
4001 i
.suffix
= BYTE_MNEM_SUFFIX
;
4008 if (i
.tm
.base_opcode
== 0xf20f38f1
4009 || i
.tm
.base_opcode
== 0xf20f38f0)
4011 /* We have to know the operand size for crc32. */
4012 as_bad (_("ambiguous memory operand size for `%s`"),
4017 for (op
= i
.operands
; --op
>= 0;)
4018 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4020 if (i
.types
[op
].bitfield
.reg8
)
4022 i
.suffix
= BYTE_MNEM_SUFFIX
;
4025 else if (i
.types
[op
].bitfield
.reg16
)
4027 i
.suffix
= WORD_MNEM_SUFFIX
;
4030 else if (i
.types
[op
].bitfield
.reg32
)
4032 i
.suffix
= LONG_MNEM_SUFFIX
;
4035 else if (i
.types
[op
].bitfield
.reg64
)
4037 i
.suffix
= QWORD_MNEM_SUFFIX
;
4043 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4045 if (!check_byte_reg ())
4048 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4050 if (!check_long_reg ())
4053 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4056 && i
.tm
.opcode_modifier
.ignoresize
4057 && i
.tm
.opcode_modifier
.no_qsuf
)
4059 else if (!check_qword_reg ())
4062 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4064 if (!check_word_reg ())
4067 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4068 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4070 /* Skip if the instruction has x/y suffix. match_template
4071 should check if it is a valid suffix. */
4073 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4074 /* Do nothing if the instruction is going to ignore the prefix. */
4079 else if (i
.tm
.opcode_modifier
.defaultsize
4081 /* exclude fldenv/frstor/fsave/fstenv */
4082 && i
.tm
.opcode_modifier
.no_ssuf
)
4084 i
.suffix
= stackop_size
;
4086 else if (intel_syntax
4088 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4089 || i
.tm
.opcode_modifier
.jumpbyte
4090 || i
.tm
.opcode_modifier
.jumpintersegment
4091 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4092 && i
.tm
.extension_opcode
<= 3)))
4097 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4099 i
.suffix
= QWORD_MNEM_SUFFIX
;
4103 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4104 i
.suffix
= LONG_MNEM_SUFFIX
;
4107 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4108 i
.suffix
= WORD_MNEM_SUFFIX
;
4117 if (i
.tm
.opcode_modifier
.w
)
4119 as_bad (_("no instruction mnemonic suffix given and "
4120 "no register operands; can't size instruction"));
4126 unsigned int suffixes
;
4128 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4129 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4131 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4133 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4135 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4137 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4140 /* There are more than suffix matches. */
4141 if (i
.tm
.opcode_modifier
.w
4142 || ((suffixes
& (suffixes
- 1))
4143 && !i
.tm
.opcode_modifier
.defaultsize
4144 && !i
.tm
.opcode_modifier
.ignoresize
))
4146 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4152 /* Change the opcode based on the operand size given by i.suffix;
4153 We don't need to change things for byte insns. */
4156 && i
.suffix
!= BYTE_MNEM_SUFFIX
4157 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4158 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4160 /* It's not a byte, select word/dword operation. */
4161 if (i
.tm
.opcode_modifier
.w
)
4163 if (i
.tm
.opcode_modifier
.shortform
)
4164 i
.tm
.base_opcode
|= 8;
4166 i
.tm
.base_opcode
|= 1;
4169 /* Now select between word & dword operations via the operand
4170 size prefix, except for instructions that will ignore this
4172 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4174 /* The address size override prefix changes the size of the
4176 if ((flag_code
== CODE_32BIT
4177 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4178 || (flag_code
!= CODE_32BIT
4179 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4180 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4183 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4184 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4185 && !i
.tm
.opcode_modifier
.ignoresize
4186 && !i
.tm
.opcode_modifier
.floatmf
4187 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4188 || (flag_code
== CODE_64BIT
4189 && i
.tm
.opcode_modifier
.jumpbyte
)))
4191 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4193 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4194 prefix
= ADDR_PREFIX_OPCODE
;
4196 if (!add_prefix (prefix
))
4200 /* Set mode64 for an operand. */
4201 if (i
.suffix
== QWORD_MNEM_SUFFIX
4202 && flag_code
== CODE_64BIT
4203 && !i
.tm
.opcode_modifier
.norex64
)
4205 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4206 need rex64. cmpxchg8b is also a special case. */
4207 if (! (i
.operands
== 2
4208 && i
.tm
.base_opcode
== 0x90
4209 && i
.tm
.extension_opcode
== None
4210 && operand_type_equal (&i
.types
[0], &acc64
)
4211 && operand_type_equal (&i
.types
[1], &acc64
))
4212 && ! (i
.operands
== 1
4213 && i
.tm
.base_opcode
== 0xfc7
4214 && i
.tm
.extension_opcode
== 1
4215 && !operand_type_check (i
.types
[0], reg
)
4216 && operand_type_check (i
.types
[0], anymem
)))
4220 /* Size floating point instruction. */
4221 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4222 if (i
.tm
.opcode_modifier
.floatmf
)
4223 i
.tm
.base_opcode
^= 4;
4230 check_byte_reg (void)
4234 for (op
= i
.operands
; --op
>= 0;)
4236 /* If this is an eight bit register, it's OK. If it's the 16 or
4237 32 bit version of an eight bit register, we will just use the
4238 low portion, and that's OK too. */
4239 if (i
.types
[op
].bitfield
.reg8
)
4242 /* Don't generate this warning if not needed. */
4243 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4246 /* crc32 doesn't generate this warning. */
4247 if (i
.tm
.base_opcode
== 0xf20f38f0)
4250 if ((i
.types
[op
].bitfield
.reg16
4251 || i
.types
[op
].bitfield
.reg32
4252 || i
.types
[op
].bitfield
.reg64
)
4253 && i
.op
[op
].regs
->reg_num
< 4)
4255 /* Prohibit these changes in the 64bit mode, since the
4256 lowering is more complicated. */
4257 if (flag_code
== CODE_64BIT
4258 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4260 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4261 register_prefix
, i
.op
[op
].regs
->reg_name
,
4265 #if REGISTER_WARNINGS
4267 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4268 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4270 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4271 ? REGNAM_AL
- REGNAM_AX
4272 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4274 i
.op
[op
].regs
->reg_name
,
4279 /* Any other register is bad. */
4280 if (i
.types
[op
].bitfield
.reg16
4281 || i
.types
[op
].bitfield
.reg32
4282 || i
.types
[op
].bitfield
.reg64
4283 || i
.types
[op
].bitfield
.regmmx
4284 || i
.types
[op
].bitfield
.regxmm
4285 || i
.types
[op
].bitfield
.regymm
4286 || i
.types
[op
].bitfield
.sreg2
4287 || i
.types
[op
].bitfield
.sreg3
4288 || i
.types
[op
].bitfield
.control
4289 || i
.types
[op
].bitfield
.debug
4290 || i
.types
[op
].bitfield
.test
4291 || i
.types
[op
].bitfield
.floatreg
4292 || i
.types
[op
].bitfield
.floatacc
)
4294 as_bad (_("`%s%s' not allowed with `%s%c'"),
4296 i
.op
[op
].regs
->reg_name
,
4306 check_long_reg (void)
4310 for (op
= i
.operands
; --op
>= 0;)
4311 /* Reject eight bit registers, except where the template requires
4312 them. (eg. movzb) */
4313 if (i
.types
[op
].bitfield
.reg8
4314 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4315 || i
.tm
.operand_types
[op
].bitfield
.reg32
4316 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4318 as_bad (_("`%s%s' not allowed with `%s%c'"),
4320 i
.op
[op
].regs
->reg_name
,
4325 /* Warn if the e prefix on a general reg is missing. */
4326 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4327 && i
.types
[op
].bitfield
.reg16
4328 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4329 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4331 /* Prohibit these changes in the 64bit mode, since the
4332 lowering is more complicated. */
4333 if (flag_code
== CODE_64BIT
)
4335 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4336 register_prefix
, i
.op
[op
].regs
->reg_name
,
4340 #if REGISTER_WARNINGS
4342 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4344 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4346 i
.op
[op
].regs
->reg_name
,
4350 /* Warn if the r prefix on a general reg is missing. */
4351 else if (i
.types
[op
].bitfield
.reg64
4352 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4353 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4356 && i
.tm
.opcode_modifier
.toqword
4357 && !i
.types
[0].bitfield
.regxmm
)
4359 /* Convert to QWORD. We want REX byte. */
4360 i
.suffix
= QWORD_MNEM_SUFFIX
;
4364 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4365 register_prefix
, i
.op
[op
].regs
->reg_name
,
4374 check_qword_reg (void)
4378 for (op
= i
.operands
; --op
>= 0; )
4379 /* Reject eight bit registers, except where the template requires
4380 them. (eg. movzb) */
4381 if (i
.types
[op
].bitfield
.reg8
4382 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4383 || i
.tm
.operand_types
[op
].bitfield
.reg32
4384 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4386 as_bad (_("`%s%s' not allowed with `%s%c'"),
4388 i
.op
[op
].regs
->reg_name
,
4393 /* Warn if the e prefix on a general reg is missing. */
4394 else if ((i
.types
[op
].bitfield
.reg16
4395 || i
.types
[op
].bitfield
.reg32
)
4396 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4397 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4399 /* Prohibit these changes in the 64bit mode, since the
4400 lowering is more complicated. */
4402 && i
.tm
.opcode_modifier
.todword
4403 && !i
.types
[0].bitfield
.regxmm
)
4405 /* Convert to DWORD. We don't want REX byte. */
4406 i
.suffix
= LONG_MNEM_SUFFIX
;
4410 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4411 register_prefix
, i
.op
[op
].regs
->reg_name
,
4420 check_word_reg (void)
4423 for (op
= i
.operands
; --op
>= 0;)
4424 /* Reject eight bit registers, except where the template requires
4425 them. (eg. movzb) */
4426 if (i
.types
[op
].bitfield
.reg8
4427 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4428 || i
.tm
.operand_types
[op
].bitfield
.reg32
4429 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4431 as_bad (_("`%s%s' not allowed with `%s%c'"),
4433 i
.op
[op
].regs
->reg_name
,
4438 /* Warn if the e prefix on a general reg is present. */
4439 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4440 && i
.types
[op
].bitfield
.reg32
4441 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4442 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4444 /* Prohibit these changes in the 64bit mode, since the
4445 lowering is more complicated. */
4446 if (flag_code
== CODE_64BIT
)
4448 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4449 register_prefix
, i
.op
[op
].regs
->reg_name
,
4454 #if REGISTER_WARNINGS
4455 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4457 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4459 i
.op
[op
].regs
->reg_name
,
4467 update_imm (unsigned int j
)
4469 i386_operand_type overlap
;
4471 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4472 if ((overlap
.bitfield
.imm8
4473 || overlap
.bitfield
.imm8s
4474 || overlap
.bitfield
.imm16
4475 || overlap
.bitfield
.imm32
4476 || overlap
.bitfield
.imm32s
4477 || overlap
.bitfield
.imm64
)
4478 && !operand_type_equal (&overlap
, &imm8
)
4479 && !operand_type_equal (&overlap
, &imm8s
)
4480 && !operand_type_equal (&overlap
, &imm16
)
4481 && !operand_type_equal (&overlap
, &imm32
)
4482 && !operand_type_equal (&overlap
, &imm32s
)
4483 && !operand_type_equal (&overlap
, &imm64
))
4487 i386_operand_type temp
;
4489 operand_type_set (&temp
, 0);
4490 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4492 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4493 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4495 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4496 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4497 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4499 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4500 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4503 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4506 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4507 || operand_type_equal (&overlap
, &imm16_32
)
4508 || operand_type_equal (&overlap
, &imm16_32s
))
4510 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4515 if (!operand_type_equal (&overlap
, &imm8
)
4516 && !operand_type_equal (&overlap
, &imm8s
)
4517 && !operand_type_equal (&overlap
, &imm16
)
4518 && !operand_type_equal (&overlap
, &imm32
)
4519 && !operand_type_equal (&overlap
, &imm32s
)
4520 && !operand_type_equal (&overlap
, &imm64
))
4522 as_bad (_("no instruction mnemonic suffix given; "
4523 "can't determine immediate size"));
4527 i
.types
[j
] = overlap
;
4537 for (j
= 0; j
< 2; j
++)
4538 if (update_imm (j
) == 0)
4541 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4542 assert (operand_type_check (i
.types
[2], imm
) == 0);
4550 i
.drex
.modrm_reg
= 0;
4551 i
.drex
.modrm_regmem
= 0;
4553 /* SSE5 4 operand instructions must have the destination the same as
4554 one of the inputs. Figure out the destination register and cache
4555 it away in the drex field, and remember which fields to use for
4557 if (i
.tm
.opcode_modifier
.drex
4558 && i
.tm
.opcode_modifier
.drexv
4561 i
.tm
.extension_opcode
= None
;
4563 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4564 if (i
.types
[0].bitfield
.regxmm
!= 0
4565 && i
.types
[1].bitfield
.regxmm
!= 0
4566 && i
.types
[2].bitfield
.regxmm
!= 0
4567 && i
.types
[3].bitfield
.regxmm
!= 0
4568 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4569 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4571 /* Clear the arguments that are stored in drex. */
4572 operand_type_set (&i
.types
[0], 0);
4573 operand_type_set (&i
.types
[3], 0);
4574 i
.reg_operands
-= 2;
4576 /* There are two different ways to encode a 4 operand
4577 instruction with all registers that uses OC1 set to
4578 0 or 1. Favor setting OC1 to 0 since this mimics the
4579 actions of other SSE5 assemblers. Use modrm encoding 2
4580 for register/register. Include the high order bit that
4581 is normally stored in the REX byte in the register
4583 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4584 i
.drex
.modrm_reg
= 2;
4585 i
.drex
.modrm_regmem
= 1;
4586 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4587 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4590 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4591 else if (i
.types
[0].bitfield
.regxmm
!= 0
4592 && i
.types
[1].bitfield
.regxmm
!= 0
4593 && (i
.types
[2].bitfield
.regxmm
4594 || operand_type_check (i
.types
[2], anymem
))
4595 && i
.types
[3].bitfield
.regxmm
!= 0
4596 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4597 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4599 /* clear the arguments that are stored in drex */
4600 operand_type_set (&i
.types
[0], 0);
4601 operand_type_set (&i
.types
[3], 0);
4602 i
.reg_operands
-= 2;
4604 /* Specify the modrm encoding for memory addressing. Include
4605 the high order bit that is normally stored in the REX byte
4606 in the register field. */
4607 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4608 i
.drex
.modrm_reg
= 1;
4609 i
.drex
.modrm_regmem
= 2;
4610 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4611 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4614 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4615 else if (i
.types
[0].bitfield
.regxmm
!= 0
4616 && operand_type_check (i
.types
[1], anymem
) != 0
4617 && i
.types
[2].bitfield
.regxmm
!= 0
4618 && i
.types
[3].bitfield
.regxmm
!= 0
4619 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4620 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4622 /* Clear the arguments that are stored in drex. */
4623 operand_type_set (&i
.types
[0], 0);
4624 operand_type_set (&i
.types
[3], 0);
4625 i
.reg_operands
-= 2;
4627 /* Specify the modrm encoding for memory addressing. Include
4628 the high order bit that is normally stored in the REX byte
4629 in the register field. */
4630 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4631 i
.drex
.modrm_reg
= 2;
4632 i
.drex
.modrm_regmem
= 1;
4633 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4634 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4637 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4638 else if (i
.types
[0].bitfield
.regxmm
!= 0
4639 && i
.types
[1].bitfield
.regxmm
!= 0
4640 && i
.types
[2].bitfield
.regxmm
!= 0
4641 && i
.types
[3].bitfield
.regxmm
!= 0
4642 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4643 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4645 /* clear the arguments that are stored in drex */
4646 operand_type_set (&i
.types
[2], 0);
4647 operand_type_set (&i
.types
[3], 0);
4648 i
.reg_operands
-= 2;
4650 /* There are two different ways to encode a 4 operand
4651 instruction with all registers that uses OC1 set to
4652 0 or 1. Favor setting OC1 to 0 since this mimics the
4653 actions of other SSE5 assemblers. Use modrm encoding
4654 2 for register/register. Include the high order bit that
4655 is normally stored in the REX byte in the register
4657 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4658 i
.drex
.modrm_reg
= 1;
4659 i
.drex
.modrm_regmem
= 0;
4661 /* Remember the register, including the upper bits */
4662 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4663 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4666 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4667 else if (i
.types
[0].bitfield
.regxmm
!= 0
4668 && (i
.types
[1].bitfield
.regxmm
4669 || operand_type_check (i
.types
[1], anymem
))
4670 && i
.types
[2].bitfield
.regxmm
!= 0
4671 && i
.types
[3].bitfield
.regxmm
!= 0
4672 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4673 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4675 /* Clear the arguments that are stored in drex. */
4676 operand_type_set (&i
.types
[2], 0);
4677 operand_type_set (&i
.types
[3], 0);
4678 i
.reg_operands
-= 2;
4680 /* Specify the modrm encoding and remember the register
4681 including the bits normally stored in the REX byte. */
4682 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4683 i
.drex
.modrm_reg
= 0;
4684 i
.drex
.modrm_regmem
= 1;
4685 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4686 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4689 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4690 else if (operand_type_check (i
.types
[0], anymem
) != 0
4691 && i
.types
[1].bitfield
.regxmm
!= 0
4692 && i
.types
[2].bitfield
.regxmm
!= 0
4693 && i
.types
[3].bitfield
.regxmm
!= 0
4694 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4695 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4697 /* clear the arguments that are stored in drex */
4698 operand_type_set (&i
.types
[2], 0);
4699 operand_type_set (&i
.types
[3], 0);
4700 i
.reg_operands
-= 2;
4702 /* Specify the modrm encoding and remember the register
4703 including the bits normally stored in the REX byte. */
4704 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4705 i
.drex
.modrm_reg
= 1;
4706 i
.drex
.modrm_regmem
= 0;
4707 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4708 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4712 as_bad (_("Incorrect operands for the '%s' instruction"),
4716 /* SSE5 instructions with the DREX byte where the only memory operand
4717 is in the 2nd argument, and the first and last xmm register must
4718 match, and is encoded in the DREX byte. */
4719 else if (i
.tm
.opcode_modifier
.drex
4720 && !i
.tm
.opcode_modifier
.drexv
4723 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4724 if (i
.types
[0].bitfield
.regxmm
!= 0
4725 && (i
.types
[1].bitfield
.regxmm
4726 || operand_type_check(i
.types
[1], anymem
))
4727 && i
.types
[2].bitfield
.regxmm
!= 0
4728 && i
.types
[3].bitfield
.regxmm
!= 0
4729 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4730 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4732 /* clear the arguments that are stored in drex */
4733 operand_type_set (&i
.types
[0], 0);
4734 operand_type_set (&i
.types
[3], 0);
4735 i
.reg_operands
-= 2;
4737 /* Specify the modrm encoding and remember the register
4738 including the high bit normally stored in the REX
4740 i
.drex
.modrm_reg
= 2;
4741 i
.drex
.modrm_regmem
= 1;
4742 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4743 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4747 as_bad (_("Incorrect operands for the '%s' instruction"),
4751 /* SSE5 3 operand instructions that the result is a register, being
4752 either operand can be a memory operand, using OC0 to note which
4753 one is the memory. */
4754 else if (i
.tm
.opcode_modifier
.drex
4755 && i
.tm
.opcode_modifier
.drexv
4758 i
.tm
.extension_opcode
= None
;
4760 /* Case 1: 3 operand insn, src1 = register. */
4761 if (i
.types
[0].bitfield
.regxmm
!= 0
4762 && i
.types
[1].bitfield
.regxmm
!= 0
4763 && i
.types
[2].bitfield
.regxmm
!= 0)
4765 /* Clear the arguments that are stored in drex. */
4766 operand_type_set (&i
.types
[2], 0);
4769 /* Specify the modrm encoding and remember the register
4770 including the high bit normally stored in the REX byte. */
4771 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4772 i
.drex
.modrm_reg
= 1;
4773 i
.drex
.modrm_regmem
= 0;
4774 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4775 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4778 /* Case 2: 3 operand insn, src1 = memory. */
4779 else if (operand_type_check (i
.types
[0], anymem
) != 0
4780 && i
.types
[1].bitfield
.regxmm
!= 0
4781 && i
.types
[2].bitfield
.regxmm
!= 0)
4783 /* Clear the arguments that are stored in drex. */
4784 operand_type_set (&i
.types
[2], 0);
4787 /* Specify the modrm encoding and remember the register
4788 including the high bit normally stored in the REX
4790 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4791 i
.drex
.modrm_reg
= 1;
4792 i
.drex
.modrm_regmem
= 0;
4793 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4794 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4797 /* Case 3: 3 operand insn, src2 = memory. */
4798 else if (i
.types
[0].bitfield
.regxmm
!= 0
4799 && operand_type_check (i
.types
[1], anymem
) != 0
4800 && i
.types
[2].bitfield
.regxmm
!= 0)
4802 /* Clear the arguments that are stored in drex. */
4803 operand_type_set (&i
.types
[2], 0);
4806 /* Specify the modrm encoding and remember the register
4807 including the high bit normally stored in the REX byte. */
4808 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4809 i
.drex
.modrm_reg
= 0;
4810 i
.drex
.modrm_regmem
= 1;
4811 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4812 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4816 as_bad (_("Incorrect operands for the '%s' instruction"),
4820 /* SSE5 4 operand instructions that are the comparison instructions
4821 where the first operand is the immediate value of the comparison
4823 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4825 /* Case 1: 4 operand insn, src1 = reg/memory. */
4826 if (operand_type_check (i
.types
[0], imm
) != 0
4827 && (i
.types
[1].bitfield
.regxmm
4828 || operand_type_check (i
.types
[1], anymem
))
4829 && i
.types
[2].bitfield
.regxmm
!= 0
4830 && i
.types
[3].bitfield
.regxmm
!= 0)
4832 /* clear the arguments that are stored in drex */
4833 operand_type_set (&i
.types
[3], 0);
4836 /* Specify the modrm encoding and remember the register
4837 including the high bit normally stored in the REX byte. */
4838 i
.drex
.modrm_reg
= 2;
4839 i
.drex
.modrm_regmem
= 1;
4840 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4841 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4844 /* Case 2: 3 operand insn with ImmExt that places the
4845 opcode_extension as an immediate argument. This is used for
4846 all of the varients of comparison that supplies the appropriate
4847 value as part of the instruction. */
4848 else if ((i
.types
[0].bitfield
.regxmm
4849 || operand_type_check (i
.types
[0], anymem
))
4850 && i
.types
[1].bitfield
.regxmm
!= 0
4851 && i
.types
[2].bitfield
.regxmm
!= 0
4852 && operand_type_check (i
.types
[3], imm
) != 0)
4854 /* clear the arguments that are stored in drex */
4855 operand_type_set (&i
.types
[2], 0);
4858 /* Specify the modrm encoding and remember the register
4859 including the high bit normally stored in the REX byte. */
4860 i
.drex
.modrm_reg
= 1;
4861 i
.drex
.modrm_regmem
= 0;
4862 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4863 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4867 as_bad (_("Incorrect operands for the '%s' instruction"),
4871 else if (i
.tm
.opcode_modifier
.drex
4872 || i
.tm
.opcode_modifier
.drexv
4873 || i
.tm
.opcode_modifier
.drexc
)
4874 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4878 bad_implicit_operand (int xmm
)
4880 const char *reg
= xmm
? "xmm0" : "ymm0";
4882 as_bad (_("the last operand of `%s' must be `%s%s'"),
4883 i
.tm
.name
, register_prefix
, reg
);
4885 as_bad (_("the first operand of `%s' must be `%s%s'"),
4886 i
.tm
.name
, register_prefix
, reg
);
4891 process_operands (void)
4893 /* Default segment register this instruction will use for memory
4894 accesses. 0 means unknown. This is only for optimizing out
4895 unnecessary segment overrides. */
4896 const seg_entry
*default_seg
= 0;
4898 /* Handle all of the DREX munging that SSE5 needs. */
4899 if (i
.tm
.opcode_modifier
.drex
4900 || i
.tm
.opcode_modifier
.drexv
4901 || i
.tm
.opcode_modifier
.drexc
)
4904 if (i
.tm
.opcode_modifier
.sse2avx
4905 && (i
.tm
.opcode_modifier
.vexnds
4906 || i
.tm
.opcode_modifier
.vexndd
))
4908 unsigned int dup
= i
.operands
;
4909 unsigned int dest
= dup
- 1;
4912 /* The destination must be an xmm register. */
4913 assert (i
.reg_operands
4914 && MAX_OPERANDS
> dup
4915 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4917 if (i
.tm
.opcode_modifier
.firstxmm0
)
4919 /* The first operand is implicit and must be xmm0. */
4920 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4921 if (i
.op
[0].regs
->reg_num
!= 0)
4922 return bad_implicit_operand (1);
4924 if (i
.tm
.opcode_modifier
.vex3sources
)
4926 /* Keep xmm0 for instructions with VEX prefix and 3
4932 /* We remove the first xmm0 and keep the number of
4933 operands unchanged, which in fact duplicates the
4935 for (j
= 1; j
< i
.operands
; j
++)
4937 i
.op
[j
- 1] = i
.op
[j
];
4938 i
.types
[j
- 1] = i
.types
[j
];
4939 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4943 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4945 assert ((MAX_OPERANDS
- 1) > dup
4946 && i
.tm
.opcode_modifier
.vex3sources
);
4948 /* Add the implicit xmm0 for instructions with VEX prefix
4950 for (j
= i
.operands
; j
> 0; j
--)
4952 i
.op
[j
] = i
.op
[j
- 1];
4953 i
.types
[j
] = i
.types
[j
- 1];
4954 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4957 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4958 i
.types
[0] = regxmm
;
4959 i
.tm
.operand_types
[0] = regxmm
;
4962 i
.reg_operands
+= 2;
4967 i
.op
[dup
] = i
.op
[dest
];
4968 i
.types
[dup
] = i
.types
[dest
];
4969 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4978 i
.op
[dup
] = i
.op
[dest
];
4979 i
.types
[dup
] = i
.types
[dest
];
4980 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4983 if (i
.tm
.opcode_modifier
.immext
)
4986 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4990 /* The first operand is implicit and must be xmm0/ymm0. */
4991 assert (i
.reg_operands
4992 && (operand_type_equal (&i
.types
[0], ®xmm
)
4993 || operand_type_equal (&i
.types
[0], ®ymm
)));
4994 if (i
.op
[0].regs
->reg_num
!= 0)
4995 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4997 for (j
= 1; j
< i
.operands
; j
++)
4999 i
.op
[j
- 1] = i
.op
[j
];
5000 i
.types
[j
- 1] = i
.types
[j
];
5002 /* We need to adjust fields in i.tm since they are used by
5003 build_modrm_byte. */
5004 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5011 else if (i
.tm
.opcode_modifier
.regkludge
)
5013 /* The imul $imm, %reg instruction is converted into
5014 imul $imm, %reg, %reg, and the clr %reg instruction
5015 is converted into xor %reg, %reg. */
5017 unsigned int first_reg_op
;
5019 if (operand_type_check (i
.types
[0], reg
))
5023 /* Pretend we saw the extra register operand. */
5024 assert (i
.reg_operands
== 1
5025 && i
.op
[first_reg_op
+ 1].regs
== 0);
5026 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5027 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5032 if (i
.tm
.opcode_modifier
.shortform
)
5034 if (i
.types
[0].bitfield
.sreg2
5035 || i
.types
[0].bitfield
.sreg3
)
5037 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5038 && i
.op
[0].regs
->reg_num
== 1)
5040 as_bad (_("you can't `pop %scs'"), register_prefix
);
5043 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5044 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5049 /* The register or float register operand is in operand
5053 if (i
.types
[0].bitfield
.floatreg
5054 || operand_type_check (i
.types
[0], reg
))
5058 /* Register goes in low 3 bits of opcode. */
5059 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5060 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5062 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5064 /* Warn about some common errors, but press on regardless.
5065 The first case can be generated by gcc (<= 2.8.1). */
5066 if (i
.operands
== 2)
5068 /* Reversed arguments on faddp, fsubp, etc. */
5069 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5070 register_prefix
, i
.op
[1].regs
->reg_name
,
5071 register_prefix
, i
.op
[0].regs
->reg_name
);
5075 /* Extraneous `l' suffix on fp insn. */
5076 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5077 register_prefix
, i
.op
[0].regs
->reg_name
);
5082 else if (i
.tm
.opcode_modifier
.modrm
)
5084 /* The opcode is completed (modulo i.tm.extension_opcode which
5085 must be put into the modrm byte). Now, we make the modrm and
5086 index base bytes based on all the info we've collected. */
5088 default_seg
= build_modrm_byte ();
5090 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5094 else if (i
.tm
.opcode_modifier
.isstring
)
5096 /* For the string instructions that allow a segment override
5097 on one of their operands, the default segment is ds. */
5101 if (i
.tm
.base_opcode
== 0x8d /* lea */
5104 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5106 /* If a segment was explicitly specified, and the specified segment
5107 is not the default, use an opcode prefix to select it. If we
5108 never figured out what the default segment is, then default_seg
5109 will be zero at this point, and the specified segment prefix will
5111 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5113 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5119 static const seg_entry
*
5120 build_modrm_byte (void)
5122 const seg_entry
*default_seg
= 0;
5123 unsigned int source
, dest
;
5126 /* The first operand of instructions with VEX prefix and 3 sources
5127 must be VEX_Imm4. */
5128 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5131 unsigned int nds
, reg
;
5133 dest
= i
.operands
- 1;
5138 /* This instruction must have 4 operands: 4 register operands
5139 or 3 register operands plus 1 memory operand. It must have
5140 VexNDS and VexImmExt. */
5141 assert (i
.operands
== 4
5142 && (i
.reg_operands
== 4
5143 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5144 && i
.tm
.opcode_modifier
.vexnds
5145 && i
.tm
.opcode_modifier
.veximmext
5146 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5148 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5150 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5152 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5154 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5156 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5159 /* Generate an 8bit immediate operand to encode the register
5161 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5162 i
.op
[i
.operands
].imms
= exp
;
5163 i
.types
[i
.operands
] = imm8
;
5165 exp
->X_op
= O_constant
;
5167 = ((i
.op
[0].regs
->reg_num
5168 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5170 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5175 /* SSE5 4 operand instructions are encoded in such a way that one of
5176 the inputs must match the destination register. Process_drex hides
5177 the 3rd argument in the drex field, so that by the time we get
5178 here, it looks to GAS as if this is a 2 operand instruction. */
5179 if ((i
.tm
.opcode_modifier
.drex
5180 || i
.tm
.opcode_modifier
.drexv
5181 || i
.tm
.opcode_modifier
.drexc
)
5182 && i
.reg_operands
== 2)
5184 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5185 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5187 i
.rm
.reg
= reg
->reg_num
;
5188 i
.rm
.regmem
= regmem
->reg_num
;
5190 if ((reg
->reg_flags
& RegRex
) != 0)
5192 if ((regmem
->reg_flags
& RegRex
) != 0)
5196 /* i.reg_operands MUST be the number of real register operands;
5197 implicit registers do not count. If there are 3 register
5198 operands, it must be a instruction with VexNDS. For a
5199 instruction with VexNDD, the destination register is encoded
5200 in VEX prefix. If there are 4 register operands, it must be
5201 a instruction with VEX prefix and 3 sources. */
5202 else if (i
.mem_operands
== 0
5203 && ((i
.reg_operands
== 2
5204 && !i
.tm
.opcode_modifier
.vexndd
)
5205 || (i
.reg_operands
== 3
5206 && i
.tm
.opcode_modifier
.vexnds
)
5207 || (i
.reg_operands
== 4 && vex_3_sources
)))
5215 /* When there are 3 operands, one of them may be immediate,
5216 which may be the first or the last operand. Otherwise,
5217 the first operand must be shift count register (cl) or it
5218 is an instruction with VexNDS. */
5219 assert (i
.imm_operands
== 1
5220 || (i
.imm_operands
== 0
5221 && (i
.tm
.opcode_modifier
.vexnds
5222 || i
.types
[0].bitfield
.shiftcount
)));
5223 if (operand_type_check (i
.types
[0], imm
)
5224 || i
.types
[0].bitfield
.shiftcount
)
5230 /* When there are 4 operands, the first two must be 8bit
5231 immediate operands. The source operand will be the 3rd
5234 For instructions with VexNDS, if the first operand
5235 an imm8, the source operand is the 2nd one. If the last
5236 operand is imm8, the source operand is the first one. */
5237 assert ((i
.imm_operands
== 2
5238 && i
.types
[0].bitfield
.imm8
5239 && i
.types
[1].bitfield
.imm8
)
5240 || (i
.tm
.opcode_modifier
.vexnds
5241 && i
.imm_operands
== 1
5242 && (i
.types
[0].bitfield
.imm8
5243 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5244 if (i
.tm
.opcode_modifier
.vexnds
)
5246 if (i
.types
[0].bitfield
.imm8
)
5264 if (i
.tm
.opcode_modifier
.vexnds
)
5266 /* For instructions with VexNDS, the register-only
5267 source operand must be XMM or YMM register. It is
5268 encoded in VEX prefix. We need to clear RegMem bit
5269 before calling operand_type_equal. */
5270 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5271 op
.bitfield
.regmem
= 0;
5272 if ((dest
+ 1) >= i
.operands
5273 || (!operand_type_equal (&op
, ®xmm
)
5274 && !operand_type_equal (&op
, ®ymm
)))
5276 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5282 /* One of the register operands will be encoded in the i.tm.reg
5283 field, the other in the combined i.tm.mode and i.tm.regmem
5284 fields. If no form of this instruction supports a memory
5285 destination operand, then we assume the source operand may
5286 sometimes be a memory operand and so we need to store the
5287 destination in the i.rm.reg field. */
5288 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5289 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5291 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5292 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5293 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5295 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5300 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5301 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5302 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5304 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5307 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5309 if (!i
.types
[0].bitfield
.control
5310 && !i
.types
[1].bitfield
.control
)
5312 i
.rex
&= ~(REX_R
| REX_B
);
5313 add_prefix (LOCK_PREFIX_OPCODE
);
5317 { /* If it's not 2 reg operands... */
5322 unsigned int fake_zero_displacement
= 0;
5325 /* This has been precalculated for SSE5 instructions
5326 that have a DREX field earlier in process_drex. */
5327 if (i
.tm
.opcode_modifier
.drex
5328 || i
.tm
.opcode_modifier
.drexv
5329 || i
.tm
.opcode_modifier
.drexc
)
5330 op
= i
.drex
.modrm_regmem
;
5333 for (op
= 0; op
< i
.operands
; op
++)
5334 if (operand_type_check (i
.types
[op
], anymem
))
5336 assert (op
< i
.operands
);
5341 if (i
.base_reg
== 0)
5344 if (!i
.disp_operands
)
5345 fake_zero_displacement
= 1;
5346 if (i
.index_reg
== 0)
5348 /* Operand is just <disp> */
5349 if (flag_code
== CODE_64BIT
)
5351 /* 64bit mode overwrites the 32bit absolute
5352 addressing by RIP relative addressing and
5353 absolute addressing is encoded by one of the
5354 redundant SIB forms. */
5355 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5356 i
.sib
.base
= NO_BASE_REGISTER
;
5357 i
.sib
.index
= NO_INDEX_REGISTER
;
5358 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5359 ? disp32s
: disp32
);
5361 else if ((flag_code
== CODE_16BIT
)
5362 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5364 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5365 i
.types
[op
] = disp16
;
5369 i
.rm
.regmem
= NO_BASE_REGISTER
;
5370 i
.types
[op
] = disp32
;
5373 else /* !i.base_reg && i.index_reg */
5375 if (i
.index_reg
->reg_num
== RegEiz
5376 || i
.index_reg
->reg_num
== RegRiz
)
5377 i
.sib
.index
= NO_INDEX_REGISTER
;
5379 i
.sib
.index
= i
.index_reg
->reg_num
;
5380 i
.sib
.base
= NO_BASE_REGISTER
;
5381 i
.sib
.scale
= i
.log2_scale_factor
;
5382 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5383 i
.types
[op
].bitfield
.disp8
= 0;
5384 i
.types
[op
].bitfield
.disp16
= 0;
5385 i
.types
[op
].bitfield
.disp64
= 0;
5386 if (flag_code
!= CODE_64BIT
)
5388 /* Must be 32 bit */
5389 i
.types
[op
].bitfield
.disp32
= 1;
5390 i
.types
[op
].bitfield
.disp32s
= 0;
5394 i
.types
[op
].bitfield
.disp32
= 0;
5395 i
.types
[op
].bitfield
.disp32s
= 1;
5397 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5401 /* RIP addressing for 64bit mode. */
5402 else if (i
.base_reg
->reg_num
== RegRip
||
5403 i
.base_reg
->reg_num
== RegEip
)
5405 i
.rm
.regmem
= NO_BASE_REGISTER
;
5406 i
.types
[op
].bitfield
.disp8
= 0;
5407 i
.types
[op
].bitfield
.disp16
= 0;
5408 i
.types
[op
].bitfield
.disp32
= 0;
5409 i
.types
[op
].bitfield
.disp32s
= 1;
5410 i
.types
[op
].bitfield
.disp64
= 0;
5411 i
.flags
[op
] |= Operand_PCrel
;
5412 if (! i
.disp_operands
)
5413 fake_zero_displacement
= 1;
5415 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5417 switch (i
.base_reg
->reg_num
)
5420 if (i
.index_reg
== 0)
5422 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5423 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5427 if (i
.index_reg
== 0)
5430 if (operand_type_check (i
.types
[op
], disp
) == 0)
5432 /* fake (%bp) into 0(%bp) */
5433 i
.types
[op
].bitfield
.disp8
= 1;
5434 fake_zero_displacement
= 1;
5437 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5438 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5440 default: /* (%si) -> 4 or (%di) -> 5 */
5441 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5443 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5445 else /* i.base_reg and 32/64 bit mode */
5447 if (flag_code
== CODE_64BIT
5448 && operand_type_check (i
.types
[op
], disp
))
5450 i386_operand_type temp
;
5451 operand_type_set (&temp
, 0);
5452 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5454 if (i
.prefix
[ADDR_PREFIX
] == 0)
5455 i
.types
[op
].bitfield
.disp32s
= 1;
5457 i
.types
[op
].bitfield
.disp32
= 1;
5460 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5461 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5463 i
.sib
.base
= i
.base_reg
->reg_num
;
5464 /* x86-64 ignores REX prefix bit here to avoid decoder
5466 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5469 if (i
.disp_operands
== 0)
5471 fake_zero_displacement
= 1;
5472 i
.types
[op
].bitfield
.disp8
= 1;
5475 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5479 i
.sib
.scale
= i
.log2_scale_factor
;
5480 if (i
.index_reg
== 0)
5482 /* <disp>(%esp) becomes two byte modrm with no index
5483 register. We've already stored the code for esp
5484 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5485 Any base register besides %esp will not use the
5486 extra modrm byte. */
5487 i
.sib
.index
= NO_INDEX_REGISTER
;
5491 if (i
.index_reg
->reg_num
== RegEiz
5492 || i
.index_reg
->reg_num
== RegRiz
)
5493 i
.sib
.index
= NO_INDEX_REGISTER
;
5495 i
.sib
.index
= i
.index_reg
->reg_num
;
5496 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5497 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5502 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5503 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5506 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5509 if (fake_zero_displacement
)
5511 /* Fakes a zero displacement assuming that i.types[op]
5512 holds the correct displacement size. */
5515 assert (i
.op
[op
].disps
== 0);
5516 exp
= &disp_expressions
[i
.disp_operands
++];
5517 i
.op
[op
].disps
= exp
;
5518 exp
->X_op
= O_constant
;
5519 exp
->X_add_number
= 0;
5520 exp
->X_add_symbol
= (symbolS
*) 0;
5521 exp
->X_op_symbol
= (symbolS
*) 0;
5529 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5530 (if any) based on i.tm.extension_opcode. Again, we must be
5531 careful to make sure that segment/control/debug/test/MMX
5532 registers are coded into the i.rm.reg field. */
5537 /* This has been precalculated for SSE5 instructions
5538 that have a DREX field earlier in process_drex. */
5539 if (i
.tm
.opcode_modifier
.drex
5540 || i
.tm
.opcode_modifier
.drexv
5541 || i
.tm
.opcode_modifier
.drexc
)
5543 op
= i
.drex
.modrm_reg
;
5544 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5545 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5550 unsigned int vex_reg
= ~0;
5552 for (op
= 0; op
< i
.operands
; op
++)
5553 if (i
.types
[op
].bitfield
.reg8
5554 || i
.types
[op
].bitfield
.reg16
5555 || i
.types
[op
].bitfield
.reg32
5556 || i
.types
[op
].bitfield
.reg64
5557 || i
.types
[op
].bitfield
.regmmx
5558 || i
.types
[op
].bitfield
.regxmm
5559 || i
.types
[op
].bitfield
.regymm
5560 || i
.types
[op
].bitfield
.sreg2
5561 || i
.types
[op
].bitfield
.sreg3
5562 || i
.types
[op
].bitfield
.control
5563 || i
.types
[op
].bitfield
.debug
5564 || i
.types
[op
].bitfield
.test
)
5569 else if (i
.tm
.opcode_modifier
.vexnds
)
5571 /* For instructions with VexNDS, the register-only
5572 source operand is encoded in VEX prefix. */
5573 assert (mem
!= (unsigned int) ~0);
5578 assert (op
< i
.operands
);
5583 assert (vex_reg
< i
.operands
);
5586 else if (i
.tm
.opcode_modifier
.vexndd
)
5588 /* For instructions with VexNDD, there should be
5589 no memory operand and the register destination
5590 is encoded in VEX prefix. */
5591 assert (i
.mem_operands
== 0
5592 && (op
+ 2) == i
.operands
);
5596 assert (op
< i
.operands
);
5598 if (vex_reg
!= (unsigned int) ~0)
5600 assert (i
.reg_operands
== 2);
5602 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5604 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5607 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5610 /* If there is an extension opcode to put here, the
5611 register number must be put into the regmem field. */
5612 if (i
.tm
.extension_opcode
!= None
)
5614 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5615 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5620 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5621 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5626 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5627 must set it to 3 to indicate this is a register operand
5628 in the regmem field. */
5629 if (!i
.mem_operands
)
5633 /* Fill in i.rm.reg field with extension opcode (if any). */
5634 if (i
.tm
.extension_opcode
!= None
5635 && !(i
.tm
.opcode_modifier
.drex
5636 || i
.tm
.opcode_modifier
.drexv
5637 || i
.tm
.opcode_modifier
.drexc
))
5638 i
.rm
.reg
= i
.tm
.extension_opcode
;
5644 output_branch (void)
5649 relax_substateT subtype
;
5654 if (flag_code
== CODE_16BIT
)
5658 if (i
.prefix
[DATA_PREFIX
] != 0)
5664 /* Pentium4 branch hints. */
5665 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5666 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5671 if (i
.prefix
[REX_PREFIX
] != 0)
5677 if (i
.prefixes
!= 0 && !intel_syntax
)
5678 as_warn (_("skipping prefixes on this instruction"));
5680 /* It's always a symbol; End frag & setup for relax.
5681 Make sure there is enough room in this frag for the largest
5682 instruction we may generate in md_convert_frag. This is 2
5683 bytes for the opcode and room for the prefix and largest
5685 frag_grow (prefix
+ 2 + 4);
5686 /* Prefix and 1 opcode byte go in fr_fix. */
5687 p
= frag_more (prefix
+ 1);
5688 if (i
.prefix
[DATA_PREFIX
] != 0)
5689 *p
++ = DATA_PREFIX_OPCODE
;
5690 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5691 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5692 *p
++ = i
.prefix
[SEG_PREFIX
];
5693 if (i
.prefix
[REX_PREFIX
] != 0)
5694 *p
++ = i
.prefix
[REX_PREFIX
];
5695 *p
= i
.tm
.base_opcode
;
5697 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5698 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5699 else if (cpu_arch_flags
.bitfield
.cpui386
)
5700 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5702 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5705 sym
= i
.op
[0].disps
->X_add_symbol
;
5706 off
= i
.op
[0].disps
->X_add_number
;
5708 if (i
.op
[0].disps
->X_op
!= O_constant
5709 && i
.op
[0].disps
->X_op
!= O_symbol
)
5711 /* Handle complex expressions. */
5712 sym
= make_expr_symbol (i
.op
[0].disps
);
5716 /* 1 possible extra opcode + 4 byte displacement go in var part.
5717 Pass reloc in fr_var. */
5718 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5728 if (i
.tm
.opcode_modifier
.jumpbyte
)
5730 /* This is a loop or jecxz type instruction. */
5732 if (i
.prefix
[ADDR_PREFIX
] != 0)
5734 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5737 /* Pentium4 branch hints. */
5738 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5739 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5741 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5750 if (flag_code
== CODE_16BIT
)
5753 if (i
.prefix
[DATA_PREFIX
] != 0)
5755 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5765 if (i
.prefix
[REX_PREFIX
] != 0)
5767 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5771 if (i
.prefixes
!= 0 && !intel_syntax
)
5772 as_warn (_("skipping prefixes on this instruction"));
5774 p
= frag_more (1 + size
);
5775 *p
++ = i
.tm
.base_opcode
;
5777 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5778 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5780 /* All jumps handled here are signed, but don't use a signed limit
5781 check for 32 and 16 bit jumps as we want to allow wrap around at
5782 4G and 64k respectively. */
5784 fixP
->fx_signed
= 1;
5788 output_interseg_jump (void)
5796 if (flag_code
== CODE_16BIT
)
5800 if (i
.prefix
[DATA_PREFIX
] != 0)
5806 if (i
.prefix
[REX_PREFIX
] != 0)
5816 if (i
.prefixes
!= 0 && !intel_syntax
)
5817 as_warn (_("skipping prefixes on this instruction"));
5819 /* 1 opcode; 2 segment; offset */
5820 p
= frag_more (prefix
+ 1 + 2 + size
);
5822 if (i
.prefix
[DATA_PREFIX
] != 0)
5823 *p
++ = DATA_PREFIX_OPCODE
;
5825 if (i
.prefix
[REX_PREFIX
] != 0)
5826 *p
++ = i
.prefix
[REX_PREFIX
];
5828 *p
++ = i
.tm
.base_opcode
;
5829 if (i
.op
[1].imms
->X_op
== O_constant
)
5831 offsetT n
= i
.op
[1].imms
->X_add_number
;
5834 && !fits_in_unsigned_word (n
)
5835 && !fits_in_signed_word (n
))
5837 as_bad (_("16-bit jump out of range"));
5840 md_number_to_chars (p
, n
, size
);
5843 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5844 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5845 if (i
.op
[0].imms
->X_op
!= O_constant
)
5846 as_bad (_("can't handle non absolute segment in `%s'"),
5848 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5854 fragS
*insn_start_frag
;
5855 offsetT insn_start_off
;
5857 /* Tie dwarf2 debug info to the address at the start of the insn.
5858 We can't do this after the insn has been output as the current
5859 frag may have been closed off. eg. by frag_var. */
5860 dwarf2_emit_insn (0);
5862 insn_start_frag
= frag_now
;
5863 insn_start_off
= frag_now_fix ();
5866 if (i
.tm
.opcode_modifier
.jump
)
5868 else if (i
.tm
.opcode_modifier
.jumpbyte
5869 || i
.tm
.opcode_modifier
.jumpdword
)
5871 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5872 output_interseg_jump ();
5875 /* Output normal instructions here. */
5879 unsigned int prefix
;
5881 /* Since the VEX prefix contains the implicit prefix, we don't
5882 need the explicit prefix. */
5883 if (!i
.tm
.opcode_modifier
.vex
)
5885 switch (i
.tm
.opcode_length
)
5888 if (i
.tm
.base_opcode
& 0xff000000)
5890 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5895 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5897 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5898 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5901 if (prefix
!= REPE_PREFIX_OPCODE
5902 || (i
.prefix
[LOCKREP_PREFIX
]
5903 != REPE_PREFIX_OPCODE
))
5904 add_prefix (prefix
);
5907 add_prefix (prefix
);
5916 /* The prefix bytes. */
5917 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5919 FRAG_APPEND_1_CHAR (*q
);
5922 if (i
.tm
.opcode_modifier
.vex
)
5924 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5929 /* REX byte is encoded in VEX prefix. */
5933 FRAG_APPEND_1_CHAR (*q
);
5936 /* There should be no other prefixes for instructions
5941 /* Now the VEX prefix. */
5942 p
= frag_more (i
.vex
.length
);
5943 for (j
= 0; j
< i
.vex
.length
; j
++)
5944 p
[j
] = i
.vex
.bytes
[j
];
5947 /* Now the opcode; be careful about word order here! */
5948 if (i
.tm
.opcode_length
== 1)
5950 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5954 switch (i
.tm
.opcode_length
)
5958 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5968 /* Put out high byte first: can't use md_number_to_chars! */
5969 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5970 *p
= i
.tm
.base_opcode
& 0xff;
5972 /* On SSE5, encode the OC1 bit in the DREX field if this
5973 encoding has multiple formats. */
5974 if (i
.tm
.opcode_modifier
.drex
5975 && i
.tm
.opcode_modifier
.drexv
5976 && DREX_OC1 (i
.tm
.extension_opcode
))
5977 *p
|= DREX_OC1_MASK
;
5980 /* Now the modrm byte and sib byte (if present). */
5981 if (i
.tm
.opcode_modifier
.modrm
)
5983 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5986 /* If i.rm.regmem == ESP (4)
5987 && i.rm.mode != (Register mode)
5989 ==> need second modrm byte. */
5990 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5992 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5993 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5995 | i
.sib
.scale
<< 6));
5998 /* Write the DREX byte if needed. */
5999 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6002 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6004 /* Encode the OC0 bit if this encoding has multiple
6006 if ((i
.tm
.opcode_modifier
.drex
6007 || i
.tm
.opcode_modifier
.drexv
)
6008 && DREX_OC0 (i
.tm
.extension_opcode
))
6009 *p
|= DREX_OC0_MASK
;
6012 if (i
.disp_operands
)
6013 output_disp (insn_start_frag
, insn_start_off
);
6016 output_imm (insn_start_frag
, insn_start_off
);
6022 pi ("" /*line*/, &i
);
6024 #endif /* DEBUG386 */
6027 /* Return the size of the displacement operand N. */
6030 disp_size (unsigned int n
)
6033 if (i
.types
[n
].bitfield
.disp64
)
6035 else if (i
.types
[n
].bitfield
.disp8
)
6037 else if (i
.types
[n
].bitfield
.disp16
)
6042 /* Return the size of the immediate operand N. */
6045 imm_size (unsigned int n
)
6048 if (i
.types
[n
].bitfield
.imm64
)
6050 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6052 else if (i
.types
[n
].bitfield
.imm16
)
6058 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6063 for (n
= 0; n
< i
.operands
; n
++)
6065 if (operand_type_check (i
.types
[n
], disp
))
6067 if (i
.op
[n
].disps
->X_op
== O_constant
)
6069 int size
= disp_size (n
);
6072 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6074 p
= frag_more (size
);
6075 md_number_to_chars (p
, val
, size
);
6079 enum bfd_reloc_code_real reloc_type
;
6080 int size
= disp_size (n
);
6081 int sign
= i
.types
[n
].bitfield
.disp32s
;
6082 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6084 /* We can't have 8 bit displacement here. */
6085 assert (!i
.types
[n
].bitfield
.disp8
);
6087 /* The PC relative address is computed relative
6088 to the instruction boundary, so in case immediate
6089 fields follows, we need to adjust the value. */
6090 if (pcrel
&& i
.imm_operands
)
6095 for (n1
= 0; n1
< i
.operands
; n1
++)
6096 if (operand_type_check (i
.types
[n1
], imm
))
6098 /* Only one immediate is allowed for PC
6099 relative address. */
6102 i
.op
[n
].disps
->X_add_number
-= sz
;
6104 /* We should find the immediate. */
6108 p
= frag_more (size
);
6109 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6111 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6112 && (((reloc_type
== BFD_RELOC_32
6113 || reloc_type
== BFD_RELOC_X86_64_32S
6114 || (reloc_type
== BFD_RELOC_64
6116 && (i
.op
[n
].disps
->X_op
== O_symbol
6117 || (i
.op
[n
].disps
->X_op
== O_add
6118 && ((symbol_get_value_expression
6119 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6121 || reloc_type
== BFD_RELOC_32_PCREL
))
6125 if (insn_start_frag
== frag_now
)
6126 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6131 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6132 for (fr
= insn_start_frag
->fr_next
;
6133 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6135 add
+= p
- frag_now
->fr_literal
;
6140 reloc_type
= BFD_RELOC_386_GOTPC
;
6141 i
.op
[n
].imms
->X_add_number
+= add
;
6143 else if (reloc_type
== BFD_RELOC_64
)
6144 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6146 /* Don't do the adjustment for x86-64, as there
6147 the pcrel addressing is relative to the _next_
6148 insn, and that is taken care of in other code. */
6149 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6151 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6152 i
.op
[n
].disps
, pcrel
, reloc_type
);
6159 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6164 for (n
= 0; n
< i
.operands
; n
++)
6166 if (operand_type_check (i
.types
[n
], imm
))
6168 if (i
.op
[n
].imms
->X_op
== O_constant
)
6170 int size
= imm_size (n
);
6173 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6175 p
= frag_more (size
);
6176 md_number_to_chars (p
, val
, size
);
6180 /* Not absolute_section.
6181 Need a 32-bit fixup (don't support 8bit
6182 non-absolute imms). Try to support other
6184 enum bfd_reloc_code_real reloc_type
;
6185 int size
= imm_size (n
);
6188 if (i
.types
[n
].bitfield
.imm32s
6189 && (i
.suffix
== QWORD_MNEM_SUFFIX
6190 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6195 p
= frag_more (size
);
6196 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6198 /* This is tough to explain. We end up with this one if we
6199 * have operands that look like
6200 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6201 * obtain the absolute address of the GOT, and it is strongly
6202 * preferable from a performance point of view to avoid using
6203 * a runtime relocation for this. The actual sequence of
6204 * instructions often look something like:
6209 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6211 * The call and pop essentially return the absolute address
6212 * of the label .L66 and store it in %ebx. The linker itself
6213 * will ultimately change the first operand of the addl so
6214 * that %ebx points to the GOT, but to keep things simple, the
6215 * .o file must have this operand set so that it generates not
6216 * the absolute address of .L66, but the absolute address of
6217 * itself. This allows the linker itself simply treat a GOTPC
6218 * relocation as asking for a pcrel offset to the GOT to be
6219 * added in, and the addend of the relocation is stored in the
6220 * operand field for the instruction itself.
6222 * Our job here is to fix the operand so that it would add
6223 * the correct offset so that %ebx would point to itself. The
6224 * thing that is tricky is that .-.L66 will point to the
6225 * beginning of the instruction, so we need to further modify
6226 * the operand so that it will point to itself. There are
6227 * other cases where you have something like:
6229 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6231 * and here no correction would be required. Internally in
6232 * the assembler we treat operands of this form as not being
6233 * pcrel since the '.' is explicitly mentioned, and I wonder
6234 * whether it would simplify matters to do it this way. Who
6235 * knows. In earlier versions of the PIC patches, the
6236 * pcrel_adjust field was used to store the correction, but
6237 * since the expression is not pcrel, I felt it would be
6238 * confusing to do it this way. */
6240 if ((reloc_type
== BFD_RELOC_32
6241 || reloc_type
== BFD_RELOC_X86_64_32S
6242 || reloc_type
== BFD_RELOC_64
)
6244 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6245 && (i
.op
[n
].imms
->X_op
== O_symbol
6246 || (i
.op
[n
].imms
->X_op
== O_add
6247 && ((symbol_get_value_expression
6248 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6253 if (insn_start_frag
== frag_now
)
6254 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6259 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6260 for (fr
= insn_start_frag
->fr_next
;
6261 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6263 add
+= p
- frag_now
->fr_literal
;
6267 reloc_type
= BFD_RELOC_386_GOTPC
;
6269 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6271 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6272 i
.op
[n
].imms
->X_add_number
+= add
;
6274 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6275 i
.op
[n
].imms
, 0, reloc_type
);
6281 /* x86_cons_fix_new is called via the expression parsing code when a
6282 reloc is needed. We use this hook to get the correct .got reloc. */
6283 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6284 static int cons_sign
= -1;
6287 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6290 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6292 got_reloc
= NO_RELOC
;
6295 if (exp
->X_op
== O_secrel
)
6297 exp
->X_op
= O_symbol
;
6298 r
= BFD_RELOC_32_SECREL
;
6302 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6305 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6306 # define lex_got(reloc, adjust, types) NULL
6308 /* Parse operands of the form
6309 <symbol>@GOTOFF+<nnn>
6310 and similar .plt or .got references.
6312 If we find one, set up the correct relocation in RELOC and copy the
6313 input string, minus the `@GOTOFF' into a malloc'd buffer for
6314 parsing by the calling routine. Return this buffer, and if ADJUST
6315 is non-null set it to the length of the string we removed from the
6316 input line. Otherwise return NULL. */
6318 lex_got (enum bfd_reloc_code_real
*reloc
,
6320 i386_operand_type
*types
)
6322 /* Some of the relocations depend on the size of what field is to
6323 be relocated. But in our callers i386_immediate and i386_displacement
6324 we don't yet know the operand size (this will be set by insn
6325 matching). Hence we record the word32 relocation here,
6326 and adjust the reloc according to the real size in reloc(). */
6327 static const struct {
6329 const enum bfd_reloc_code_real rel
[2];
6330 const i386_operand_type types64
;
6333 BFD_RELOC_X86_64_PLTOFF64
},
6334 OPERAND_TYPE_IMM64
},
6335 { "PLT", { BFD_RELOC_386_PLT32
,
6336 BFD_RELOC_X86_64_PLT32
},
6337 OPERAND_TYPE_IMM32_32S_DISP32
},
6339 BFD_RELOC_X86_64_GOTPLT64
},
6340 OPERAND_TYPE_IMM64_DISP64
},
6341 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6342 BFD_RELOC_X86_64_GOTOFF64
},
6343 OPERAND_TYPE_IMM64_DISP64
},
6345 BFD_RELOC_X86_64_GOTPCREL
},
6346 OPERAND_TYPE_IMM32_32S_DISP32
},
6347 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6348 BFD_RELOC_X86_64_TLSGD
},
6349 OPERAND_TYPE_IMM32_32S_DISP32
},
6350 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6352 OPERAND_TYPE_NONE
},
6354 BFD_RELOC_X86_64_TLSLD
},
6355 OPERAND_TYPE_IMM32_32S_DISP32
},
6356 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6357 BFD_RELOC_X86_64_GOTTPOFF
},
6358 OPERAND_TYPE_IMM32_32S_DISP32
},
6359 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6360 BFD_RELOC_X86_64_TPOFF32
},
6361 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6362 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6364 OPERAND_TYPE_NONE
},
6365 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6366 BFD_RELOC_X86_64_DTPOFF32
},
6368 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6369 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6371 OPERAND_TYPE_NONE
},
6372 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6374 OPERAND_TYPE_NONE
},
6375 { "GOT", { BFD_RELOC_386_GOT32
,
6376 BFD_RELOC_X86_64_GOT32
},
6377 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6378 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6379 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6380 OPERAND_TYPE_IMM32_32S_DISP32
},
6381 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6382 BFD_RELOC_X86_64_TLSDESC_CALL
},
6383 OPERAND_TYPE_IMM32_32S_DISP32
},
6391 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6392 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6395 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6399 len
= strlen (gotrel
[j
].str
);
6400 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6402 if (gotrel
[j
].rel
[object_64bit
] != 0)
6405 char *tmpbuf
, *past_reloc
;
6407 *reloc
= gotrel
[j
].rel
[object_64bit
];
6413 if (flag_code
!= CODE_64BIT
)
6415 types
->bitfield
.imm32
= 1;
6416 types
->bitfield
.disp32
= 1;
6419 *types
= gotrel
[j
].types64
;
6422 if (GOT_symbol
== NULL
)
6423 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6425 /* The length of the first part of our input line. */
6426 first
= cp
- input_line_pointer
;
6428 /* The second part goes from after the reloc token until
6429 (and including) an end_of_line char or comma. */
6430 past_reloc
= cp
+ 1 + len
;
6432 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6434 second
= cp
+ 1 - past_reloc
;
6436 /* Allocate and copy string. The trailing NUL shouldn't
6437 be necessary, but be safe. */
6438 tmpbuf
= xmalloc (first
+ second
+ 2);
6439 memcpy (tmpbuf
, input_line_pointer
, first
);
6440 if (second
!= 0 && *past_reloc
!= ' ')
6441 /* Replace the relocation token with ' ', so that
6442 errors like foo@GOTOFF1 will be detected. */
6443 tmpbuf
[first
++] = ' ';
6444 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6445 tmpbuf
[first
+ second
] = '\0';
6449 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6450 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6455 /* Might be a symbol version string. Don't as_bad here. */
6460 x86_cons (expressionS
*exp
, int size
)
6462 if (size
== 4 || (object_64bit
&& size
== 8))
6464 /* Handle @GOTOFF and the like in an expression. */
6466 char *gotfree_input_line
;
6469 save
= input_line_pointer
;
6470 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6471 if (gotfree_input_line
)
6472 input_line_pointer
= gotfree_input_line
;
6476 if (gotfree_input_line
)
6478 /* expression () has merrily parsed up to the end of line,
6479 or a comma - in the wrong buffer. Transfer how far
6480 input_line_pointer has moved to the right buffer. */
6481 input_line_pointer
= (save
6482 + (input_line_pointer
- gotfree_input_line
)
6484 free (gotfree_input_line
);
6485 if (exp
->X_op
== O_constant
6486 || exp
->X_op
== O_absent
6487 || exp
->X_op
== O_illegal
6488 || exp
->X_op
== O_register
6489 || exp
->X_op
== O_big
)
6491 char c
= *input_line_pointer
;
6492 *input_line_pointer
= 0;
6493 as_bad (_("missing or invalid expression `%s'"), save
);
6494 *input_line_pointer
= c
;
6503 static void signed_cons (int size
)
6505 if (flag_code
== CODE_64BIT
)
6513 pe_directive_secrel (dummy
)
6514 int dummy ATTRIBUTE_UNUSED
;
6521 if (exp
.X_op
== O_symbol
)
6522 exp
.X_op
= O_secrel
;
6524 emit_expr (&exp
, 4);
6526 while (*input_line_pointer
++ == ',');
6528 input_line_pointer
--;
6529 demand_empty_rest_of_line ();
6534 i386_immediate (char *imm_start
)
6536 char *save_input_line_pointer
;
6537 char *gotfree_input_line
;
6540 i386_operand_type types
;
6542 operand_type_set (&types
, ~0);
6544 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6546 as_bad (_("at most %d immediate operands are allowed"),
6547 MAX_IMMEDIATE_OPERANDS
);
6551 exp
= &im_expressions
[i
.imm_operands
++];
6552 i
.op
[this_operand
].imms
= exp
;
6554 if (is_space_char (*imm_start
))
6557 save_input_line_pointer
= input_line_pointer
;
6558 input_line_pointer
= imm_start
;
6560 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6561 if (gotfree_input_line
)
6562 input_line_pointer
= gotfree_input_line
;
6564 exp_seg
= expression (exp
);
6567 if (*input_line_pointer
)
6568 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6570 input_line_pointer
= save_input_line_pointer
;
6571 if (gotfree_input_line
)
6572 free (gotfree_input_line
);
6574 if (exp
->X_op
== O_absent
6575 || exp
->X_op
== O_illegal
6576 || exp
->X_op
== O_big
6577 || (gotfree_input_line
6578 && (exp
->X_op
== O_constant
6579 || exp
->X_op
== O_register
)))
6581 as_bad (_("missing or invalid immediate expression `%s'"),
6585 else if (exp
->X_op
== O_constant
)
6587 /* Size it properly later. */
6588 i
.types
[this_operand
].bitfield
.imm64
= 1;
6589 /* If BFD64, sign extend val. */
6590 if (!use_rela_relocations
6591 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6593 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6595 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6596 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6597 && exp_seg
!= absolute_section
6598 && exp_seg
!= text_section
6599 && exp_seg
!= data_section
6600 && exp_seg
!= bss_section
6601 && exp_seg
!= undefined_section
6602 && !bfd_is_com_section (exp_seg
))
6604 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6608 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6610 as_bad (_("illegal immediate register operand %s"), imm_start
);
6615 /* This is an address. The size of the address will be
6616 determined later, depending on destination register,
6617 suffix, or the default for the section. */
6618 i
.types
[this_operand
].bitfield
.imm8
= 1;
6619 i
.types
[this_operand
].bitfield
.imm16
= 1;
6620 i
.types
[this_operand
].bitfield
.imm32
= 1;
6621 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6622 i
.types
[this_operand
].bitfield
.imm64
= 1;
6623 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6631 i386_scale (char *scale
)
6634 char *save
= input_line_pointer
;
6636 input_line_pointer
= scale
;
6637 val
= get_absolute_expression ();
6642 i
.log2_scale_factor
= 0;
6645 i
.log2_scale_factor
= 1;
6648 i
.log2_scale_factor
= 2;
6651 i
.log2_scale_factor
= 3;
6655 char sep
= *input_line_pointer
;
6657 *input_line_pointer
= '\0';
6658 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6660 *input_line_pointer
= sep
;
6661 input_line_pointer
= save
;
6665 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6667 as_warn (_("scale factor of %d without an index register"),
6668 1 << i
.log2_scale_factor
);
6669 i
.log2_scale_factor
= 0;
6671 scale
= input_line_pointer
;
6672 input_line_pointer
= save
;
6677 i386_displacement (char *disp_start
, char *disp_end
)
6681 char *save_input_line_pointer
;
6682 char *gotfree_input_line
;
6684 i386_operand_type bigdisp
, types
= anydisp
;
6687 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6689 as_bad (_("at most %d displacement operands are allowed"),
6690 MAX_MEMORY_OPERANDS
);
6694 operand_type_set (&bigdisp
, 0);
6695 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6696 || (!current_templates
->start
->opcode_modifier
.jump
6697 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6699 bigdisp
.bitfield
.disp32
= 1;
6700 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6701 if (flag_code
== CODE_64BIT
)
6705 bigdisp
.bitfield
.disp32s
= 1;
6706 bigdisp
.bitfield
.disp64
= 1;
6709 else if ((flag_code
== CODE_16BIT
) ^ override
)
6711 bigdisp
.bitfield
.disp32
= 0;
6712 bigdisp
.bitfield
.disp16
= 1;
6717 /* For PC-relative branches, the width of the displacement
6718 is dependent upon data size, not address size. */
6719 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6720 if (flag_code
== CODE_64BIT
)
6722 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6723 bigdisp
.bitfield
.disp16
= 1;
6726 bigdisp
.bitfield
.disp32
= 1;
6727 bigdisp
.bitfield
.disp32s
= 1;
6733 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6735 : LONG_MNEM_SUFFIX
));
6736 bigdisp
.bitfield
.disp32
= 1;
6737 if ((flag_code
== CODE_16BIT
) ^ override
)
6739 bigdisp
.bitfield
.disp32
= 0;
6740 bigdisp
.bitfield
.disp16
= 1;
6744 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6747 exp
= &disp_expressions
[i
.disp_operands
];
6748 i
.op
[this_operand
].disps
= exp
;
6750 save_input_line_pointer
= input_line_pointer
;
6751 input_line_pointer
= disp_start
;
6752 END_STRING_AND_SAVE (disp_end
);
6754 #ifndef GCC_ASM_O_HACK
6755 #define GCC_ASM_O_HACK 0
6758 END_STRING_AND_SAVE (disp_end
+ 1);
6759 if (i
.types
[this_operand
].bitfield
.baseIndex
6760 && displacement_string_end
[-1] == '+')
6762 /* This hack is to avoid a warning when using the "o"
6763 constraint within gcc asm statements.
6766 #define _set_tssldt_desc(n,addr,limit,type) \
6767 __asm__ __volatile__ ( \
6769 "movw %w1,2+%0\n\t" \
6771 "movb %b1,4+%0\n\t" \
6772 "movb %4,5+%0\n\t" \
6773 "movb $0,6+%0\n\t" \
6774 "movb %h1,7+%0\n\t" \
6776 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6778 This works great except that the output assembler ends
6779 up looking a bit weird if it turns out that there is
6780 no offset. You end up producing code that looks like:
6793 So here we provide the missing zero. */
6795 *displacement_string_end
= '0';
6798 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6799 if (gotfree_input_line
)
6800 input_line_pointer
= gotfree_input_line
;
6802 exp_seg
= expression (exp
);
6805 if (*input_line_pointer
)
6806 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6808 RESTORE_END_STRING (disp_end
+ 1);
6810 input_line_pointer
= save_input_line_pointer
;
6811 if (gotfree_input_line
)
6812 free (gotfree_input_line
);
6815 /* We do this to make sure that the section symbol is in
6816 the symbol table. We will ultimately change the relocation
6817 to be relative to the beginning of the section. */
6818 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6819 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6820 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6822 if (exp
->X_op
!= O_symbol
)
6825 if (S_IS_LOCAL (exp
->X_add_symbol
)
6826 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6827 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6828 exp
->X_op
= O_subtract
;
6829 exp
->X_op_symbol
= GOT_symbol
;
6830 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6831 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6832 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6833 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6835 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6838 else if (exp
->X_op
== O_absent
6839 || exp
->X_op
== O_illegal
6840 || exp
->X_op
== O_big
6841 || (gotfree_input_line
6842 && (exp
->X_op
== O_constant
6843 || exp
->X_op
== O_register
)))
6846 as_bad (_("missing or invalid displacement expression `%s'"),
6851 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6852 else if (exp
->X_op
!= O_constant
6853 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6854 && exp_seg
!= absolute_section
6855 && exp_seg
!= text_section
6856 && exp_seg
!= data_section
6857 && exp_seg
!= bss_section
6858 && exp_seg
!= undefined_section
6859 && !bfd_is_com_section (exp_seg
))
6861 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6866 RESTORE_END_STRING (disp_end
);
6868 /* Check if this is a displacement only operand. */
6869 bigdisp
= i
.types
[this_operand
];
6870 bigdisp
.bitfield
.disp8
= 0;
6871 bigdisp
.bitfield
.disp16
= 0;
6872 bigdisp
.bitfield
.disp32
= 0;
6873 bigdisp
.bitfield
.disp32s
= 0;
6874 bigdisp
.bitfield
.disp64
= 0;
6875 if (operand_type_all_zero (&bigdisp
))
6876 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6882 /* Make sure the memory operand we've been dealt is valid.
6883 Return 1 on success, 0 on a failure. */
6886 i386_index_check (const char *operand_string
)
6889 const char *kind
= "base/index";
6890 #if INFER_ADDR_PREFIX
6896 if (current_templates
->start
->opcode_modifier
.isstring
6897 && !current_templates
->start
->opcode_modifier
.immext
6898 && (current_templates
->end
[-1].opcode_modifier
.isstring
6901 /* Memory operands of string insns are special in that they only allow
6902 a single register (rDI, rSI, or rBX) as their memory address. */
6903 unsigned int expected
;
6905 kind
= "string address";
6907 if (current_templates
->start
->opcode_modifier
.w
)
6909 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6911 if (!type
.bitfield
.baseindex
6912 || ((!i
.mem_operands
!= !intel_syntax
)
6913 && current_templates
->end
[-1].operand_types
[1]
6914 .bitfield
.baseindex
))
6915 type
= current_templates
->end
[-1].operand_types
[1];
6916 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6919 expected
= 3 /* rBX */;
6921 if (!i
.base_reg
|| i
.index_reg
6922 || operand_type_check (i
.types
[this_operand
], disp
))
6924 else if (!(flag_code
== CODE_64BIT
6925 ? i
.prefix
[ADDR_PREFIX
]
6926 ? i
.base_reg
->reg_type
.bitfield
.reg32
6927 : i
.base_reg
->reg_type
.bitfield
.reg64
6928 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6929 ? i
.base_reg
->reg_type
.bitfield
.reg32
6930 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6932 else if (i
.base_reg
->reg_num
!= expected
)
6939 for (j
= 0; j
< i386_regtab_size
; ++j
)
6940 if ((flag_code
== CODE_64BIT
6941 ? i
.prefix
[ADDR_PREFIX
]
6942 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6943 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6944 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6945 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6946 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6947 && i386_regtab
[j
].reg_num
== expected
)
6949 assert (j
< i386_regtab_size
);
6950 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6952 intel_syntax
? '[' : '(',
6954 i386_regtab
[j
].reg_name
,
6955 intel_syntax
? ']' : ')');
6959 else if (flag_code
== CODE_64BIT
)
6962 && ((i
.prefix
[ADDR_PREFIX
] == 0
6963 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6964 || (i
.prefix
[ADDR_PREFIX
]
6965 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6967 || i
.base_reg
->reg_num
!=
6968 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6970 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6971 || (i
.prefix
[ADDR_PREFIX
] == 0
6972 && i
.index_reg
->reg_num
!= RegRiz
6973 && !i
.index_reg
->reg_type
.bitfield
.reg64
6975 || (i
.prefix
[ADDR_PREFIX
]
6976 && i
.index_reg
->reg_num
!= RegEiz
6977 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6982 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6986 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6987 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6989 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6990 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6992 && i
.base_reg
->reg_num
< 6
6993 && i
.index_reg
->reg_num
>= 6
6994 && i
.log2_scale_factor
== 0))))
7001 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7003 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7004 && i
.index_reg
->reg_num
!= RegEiz
)
7005 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7011 #if INFER_ADDR_PREFIX
7012 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7014 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7016 /* Change the size of any displacement too. At most one of
7017 Disp16 or Disp32 is set.
7018 FIXME. There doesn't seem to be any real need for separate
7019 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7020 Removing them would probably clean up the code quite a lot. */
7021 if (flag_code
!= CODE_64BIT
7022 && (i
.types
[this_operand
].bitfield
.disp16
7023 || i
.types
[this_operand
].bitfield
.disp32
))
7024 i
.types
[this_operand
]
7025 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7030 as_bad (_("`%s' is not a valid %s expression"),
7035 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7037 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7038 ? flag_code
== CODE_32BIT
7047 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7051 i386_att_operand (char *operand_string
)
7055 char *op_string
= operand_string
;
7057 if (is_space_char (*op_string
))
7060 /* We check for an absolute prefix (differentiating,
7061 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7062 if (*op_string
== ABSOLUTE_PREFIX
)
7065 if (is_space_char (*op_string
))
7067 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7070 /* Check if operand is a register. */
7071 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7073 i386_operand_type temp
;
7075 /* Check for a segment override by searching for ':' after a
7076 segment register. */
7078 if (is_space_char (*op_string
))
7080 if (*op_string
== ':'
7081 && (r
->reg_type
.bitfield
.sreg2
7082 || r
->reg_type
.bitfield
.sreg3
))
7087 i
.seg
[i
.mem_operands
] = &es
;
7090 i
.seg
[i
.mem_operands
] = &cs
;
7093 i
.seg
[i
.mem_operands
] = &ss
;
7096 i
.seg
[i
.mem_operands
] = &ds
;
7099 i
.seg
[i
.mem_operands
] = &fs
;
7102 i
.seg
[i
.mem_operands
] = &gs
;
7106 /* Skip the ':' and whitespace. */
7108 if (is_space_char (*op_string
))
7111 if (!is_digit_char (*op_string
)
7112 && !is_identifier_char (*op_string
)
7113 && *op_string
!= '('
7114 && *op_string
!= ABSOLUTE_PREFIX
)
7116 as_bad (_("bad memory operand `%s'"), op_string
);
7119 /* Handle case of %es:*foo. */
7120 if (*op_string
== ABSOLUTE_PREFIX
)
7123 if (is_space_char (*op_string
))
7125 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7127 goto do_memory_reference
;
7131 as_bad (_("junk `%s' after register"), op_string
);
7135 temp
.bitfield
.baseindex
= 0;
7136 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7138 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7139 i
.op
[this_operand
].regs
= r
;
7142 else if (*op_string
== REGISTER_PREFIX
)
7144 as_bad (_("bad register name `%s'"), op_string
);
7147 else if (*op_string
== IMMEDIATE_PREFIX
)
7150 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7152 as_bad (_("immediate operand illegal with absolute jump"));
7155 if (!i386_immediate (op_string
))
7158 else if (is_digit_char (*op_string
)
7159 || is_identifier_char (*op_string
)
7160 || *op_string
== '(')
7162 /* This is a memory reference of some sort. */
7165 /* Start and end of displacement string expression (if found). */
7166 char *displacement_string_start
;
7167 char *displacement_string_end
;
7169 do_memory_reference
:
7170 if ((i
.mem_operands
== 1
7171 && !current_templates
->start
->opcode_modifier
.isstring
)
7172 || i
.mem_operands
== 2)
7174 as_bad (_("too many memory references for `%s'"),
7175 current_templates
->start
->name
);
7179 /* Check for base index form. We detect the base index form by
7180 looking for an ')' at the end of the operand, searching
7181 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7183 base_string
= op_string
+ strlen (op_string
);
7186 if (is_space_char (*base_string
))
7189 /* If we only have a displacement, set-up for it to be parsed later. */
7190 displacement_string_start
= op_string
;
7191 displacement_string_end
= base_string
+ 1;
7193 if (*base_string
== ')')
7196 unsigned int parens_balanced
= 1;
7197 /* We've already checked that the number of left & right ()'s are
7198 equal, so this loop will not be infinite. */
7202 if (*base_string
== ')')
7204 if (*base_string
== '(')
7207 while (parens_balanced
);
7209 temp_string
= base_string
;
7211 /* Skip past '(' and whitespace. */
7213 if (is_space_char (*base_string
))
7216 if (*base_string
== ','
7217 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7220 displacement_string_end
= temp_string
;
7222 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7226 base_string
= end_op
;
7227 if (is_space_char (*base_string
))
7231 /* There may be an index reg or scale factor here. */
7232 if (*base_string
== ',')
7235 if (is_space_char (*base_string
))
7238 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7241 base_string
= end_op
;
7242 if (is_space_char (*base_string
))
7244 if (*base_string
== ',')
7247 if (is_space_char (*base_string
))
7250 else if (*base_string
!= ')')
7252 as_bad (_("expecting `,' or `)' "
7253 "after index register in `%s'"),
7258 else if (*base_string
== REGISTER_PREFIX
)
7260 as_bad (_("bad register name `%s'"), base_string
);
7264 /* Check for scale factor. */
7265 if (*base_string
!= ')')
7267 char *end_scale
= i386_scale (base_string
);
7272 base_string
= end_scale
;
7273 if (is_space_char (*base_string
))
7275 if (*base_string
!= ')')
7277 as_bad (_("expecting `)' "
7278 "after scale factor in `%s'"),
7283 else if (!i
.index_reg
)
7285 as_bad (_("expecting index register or scale factor "
7286 "after `,'; got '%c'"),
7291 else if (*base_string
!= ')')
7293 as_bad (_("expecting `,' or `)' "
7294 "after base register in `%s'"),
7299 else if (*base_string
== REGISTER_PREFIX
)
7301 as_bad (_("bad register name `%s'"), base_string
);
7306 /* If there's an expression beginning the operand, parse it,
7307 assuming displacement_string_start and
7308 displacement_string_end are meaningful. */
7309 if (displacement_string_start
!= displacement_string_end
)
7311 if (!i386_displacement (displacement_string_start
,
7312 displacement_string_end
))
7316 /* Special case for (%dx) while doing input/output op. */
7318 && operand_type_equal (&i
.base_reg
->reg_type
,
7319 ®16_inoutportreg
)
7321 && i
.log2_scale_factor
== 0
7322 && i
.seg
[i
.mem_operands
] == 0
7323 && !operand_type_check (i
.types
[this_operand
], disp
))
7325 i
.types
[this_operand
] = inoutportreg
;
7329 if (i386_index_check (operand_string
) == 0)
7331 i
.types
[this_operand
].bitfield
.mem
= 1;
7336 /* It's not a memory operand; argh! */
7337 as_bad (_("invalid char %s beginning operand %d `%s'"),
7338 output_invalid (*op_string
),
7343 return 1; /* Normal return. */
7346 /* md_estimate_size_before_relax()
7348 Called just before relax() for rs_machine_dependent frags. The x86
7349 assembler uses these frags to handle variable size jump
7352 Any symbol that is now undefined will not become defined.
7353 Return the correct fr_subtype in the frag.
7354 Return the initial "guess for variable size of frag" to caller.
7355 The guess is actually the growth beyond the fixed part. Whatever
7356 we do to grow the fixed or variable part contributes to our
7360 md_estimate_size_before_relax (fragP
, segment
)
7364 /* We've already got fragP->fr_subtype right; all we have to do is
7365 check for un-relaxable symbols. On an ELF system, we can't relax
7366 an externally visible symbol, because it may be overridden by a
7368 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7371 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7372 || S_IS_WEAK (fragP
->fr_symbol
)))
7376 /* Symbol is undefined in this segment, or we need to keep a
7377 reloc so that weak symbols can be overridden. */
7378 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7379 enum bfd_reloc_code_real reloc_type
;
7380 unsigned char *opcode
;
7383 if (fragP
->fr_var
!= NO_RELOC
)
7384 reloc_type
= fragP
->fr_var
;
7386 reloc_type
= BFD_RELOC_16_PCREL
;
7388 reloc_type
= BFD_RELOC_32_PCREL
;
7390 old_fr_fix
= fragP
->fr_fix
;
7391 opcode
= (unsigned char *) fragP
->fr_opcode
;
7393 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7396 /* Make jmp (0xeb) a (d)word displacement jump. */
7398 fragP
->fr_fix
+= size
;
7399 fix_new (fragP
, old_fr_fix
, size
,
7401 fragP
->fr_offset
, 1,
7407 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7409 /* Negate the condition, and branch past an
7410 unconditional jump. */
7413 /* Insert an unconditional jump. */
7415 /* We added two extra opcode bytes, and have a two byte
7417 fragP
->fr_fix
+= 2 + 2;
7418 fix_new (fragP
, old_fr_fix
+ 2, 2,
7420 fragP
->fr_offset
, 1,
7427 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7432 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7434 fragP
->fr_offset
, 1,
7436 fixP
->fx_signed
= 1;
7440 /* This changes the byte-displacement jump 0x7N
7441 to the (d)word-displacement jump 0x0f,0x8N. */
7442 opcode
[1] = opcode
[0] + 0x10;
7443 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7444 /* We've added an opcode byte. */
7445 fragP
->fr_fix
+= 1 + size
;
7446 fix_new (fragP
, old_fr_fix
+ 1, size
,
7448 fragP
->fr_offset
, 1,
7453 BAD_CASE (fragP
->fr_subtype
);
7457 return fragP
->fr_fix
- old_fr_fix
;
7460 /* Guess size depending on current relax state. Initially the relax
7461 state will correspond to a short jump and we return 1, because
7462 the variable part of the frag (the branch offset) is one byte
7463 long. However, we can relax a section more than once and in that
7464 case we must either set fr_subtype back to the unrelaxed state,
7465 or return the value for the appropriate branch. */
7466 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7469 /* Called after relax() is finished.
7471 In: Address of frag.
7472 fr_type == rs_machine_dependent.
7473 fr_subtype is what the address relaxed to.
7475 Out: Any fixSs and constants are set up.
7476 Caller will turn frag into a ".space 0". */
7479 md_convert_frag (abfd
, sec
, fragP
)
7480 bfd
*abfd ATTRIBUTE_UNUSED
;
7481 segT sec ATTRIBUTE_UNUSED
;
7484 unsigned char *opcode
;
7485 unsigned char *where_to_put_displacement
= NULL
;
7486 offsetT target_address
;
7487 offsetT opcode_address
;
7488 unsigned int extension
= 0;
7489 offsetT displacement_from_opcode_start
;
7491 opcode
= (unsigned char *) fragP
->fr_opcode
;
7493 /* Address we want to reach in file space. */
7494 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7496 /* Address opcode resides at in file space. */
7497 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7499 /* Displacement from opcode start to fill into instruction. */
7500 displacement_from_opcode_start
= target_address
- opcode_address
;
7502 if ((fragP
->fr_subtype
& BIG
) == 0)
7504 /* Don't have to change opcode. */
7505 extension
= 1; /* 1 opcode + 1 displacement */
7506 where_to_put_displacement
= &opcode
[1];
7510 if (no_cond_jump_promotion
7511 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7512 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7513 _("long jump required"));
7515 switch (fragP
->fr_subtype
)
7517 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7518 extension
= 4; /* 1 opcode + 4 displacement */
7520 where_to_put_displacement
= &opcode
[1];
7523 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7524 extension
= 2; /* 1 opcode + 2 displacement */
7526 where_to_put_displacement
= &opcode
[1];
7529 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7530 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7531 extension
= 5; /* 2 opcode + 4 displacement */
7532 opcode
[1] = opcode
[0] + 0x10;
7533 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7534 where_to_put_displacement
= &opcode
[2];
7537 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7538 extension
= 3; /* 2 opcode + 2 displacement */
7539 opcode
[1] = opcode
[0] + 0x10;
7540 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7541 where_to_put_displacement
= &opcode
[2];
7544 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7549 where_to_put_displacement
= &opcode
[3];
7553 BAD_CASE (fragP
->fr_subtype
);
7558 /* If size if less then four we are sure that the operand fits,
7559 but if it's 4, then it could be that the displacement is larger
7561 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7563 && ((addressT
) (displacement_from_opcode_start
- extension
7564 + ((addressT
) 1 << 31))
7565 > (((addressT
) 2 << 31) - 1)))
7567 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7568 _("jump target out of range"));
7569 /* Make us emit 0. */
7570 displacement_from_opcode_start
= extension
;
7572 /* Now put displacement after opcode. */
7573 md_number_to_chars ((char *) where_to_put_displacement
,
7574 (valueT
) (displacement_from_opcode_start
- extension
),
7575 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7576 fragP
->fr_fix
+= extension
;
7579 /* Apply a fixup (fixS) to segment data, once it has been determined
7580 by our caller that we have all the info we need to fix it up.
7582 On the 386, immediates, displacements, and data pointers are all in
7583 the same (little-endian) format, so we don't need to care about which
7587 md_apply_fix (fixP
, valP
, seg
)
7588 /* The fix we're to put in. */
7590 /* Pointer to the value of the bits. */
7592 /* Segment fix is from. */
7593 segT seg ATTRIBUTE_UNUSED
;
7595 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7596 valueT value
= *valP
;
7598 #if !defined (TE_Mach)
7601 switch (fixP
->fx_r_type
)
7607 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7610 case BFD_RELOC_X86_64_32S
:
7611 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7614 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7617 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7622 if (fixP
->fx_addsy
!= NULL
7623 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7624 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7625 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7626 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7627 && !use_rela_relocations
)
7629 /* This is a hack. There should be a better way to handle this.
7630 This covers for the fact that bfd_install_relocation will
7631 subtract the current location (for partial_inplace, PC relative
7632 relocations); see more below. */
7636 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7639 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7644 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7647 || (symbol_section_p (fixP
->fx_addsy
)
7648 && sym_seg
!= absolute_section
))
7649 && !generic_force_reloc (fixP
))
7651 /* Yes, we add the values in twice. This is because
7652 bfd_install_relocation subtracts them out again. I think
7653 bfd_install_relocation is broken, but I don't dare change
7655 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7659 #if defined (OBJ_COFF) && defined (TE_PE)
7660 /* For some reason, the PE format does not store a
7661 section address offset for a PC relative symbol. */
7662 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7663 || S_IS_WEAK (fixP
->fx_addsy
))
7664 value
+= md_pcrel_from (fixP
);
7668 /* Fix a few things - the dynamic linker expects certain values here,
7669 and we must not disappoint it. */
7670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7671 if (IS_ELF
&& fixP
->fx_addsy
)
7672 switch (fixP
->fx_r_type
)
7674 case BFD_RELOC_386_PLT32
:
7675 case BFD_RELOC_X86_64_PLT32
:
7676 /* Make the jump instruction point to the address of the operand. At
7677 runtime we merely add the offset to the actual PLT entry. */
7681 case BFD_RELOC_386_TLS_GD
:
7682 case BFD_RELOC_386_TLS_LDM
:
7683 case BFD_RELOC_386_TLS_IE_32
:
7684 case BFD_RELOC_386_TLS_IE
:
7685 case BFD_RELOC_386_TLS_GOTIE
:
7686 case BFD_RELOC_386_TLS_GOTDESC
:
7687 case BFD_RELOC_X86_64_TLSGD
:
7688 case BFD_RELOC_X86_64_TLSLD
:
7689 case BFD_RELOC_X86_64_GOTTPOFF
:
7690 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7691 value
= 0; /* Fully resolved at runtime. No addend. */
7693 case BFD_RELOC_386_TLS_LE
:
7694 case BFD_RELOC_386_TLS_LDO_32
:
7695 case BFD_RELOC_386_TLS_LE_32
:
7696 case BFD_RELOC_X86_64_DTPOFF32
:
7697 case BFD_RELOC_X86_64_DTPOFF64
:
7698 case BFD_RELOC_X86_64_TPOFF32
:
7699 case BFD_RELOC_X86_64_TPOFF64
:
7700 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7703 case BFD_RELOC_386_TLS_DESC_CALL
:
7704 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7705 value
= 0; /* Fully resolved at runtime. No addend. */
7706 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7710 case BFD_RELOC_386_GOT32
:
7711 case BFD_RELOC_X86_64_GOT32
:
7712 value
= 0; /* Fully resolved at runtime. No addend. */
7715 case BFD_RELOC_VTABLE_INHERIT
:
7716 case BFD_RELOC_VTABLE_ENTRY
:
7723 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7725 #endif /* !defined (TE_Mach) */
7727 /* Are we finished with this relocation now? */
7728 if (fixP
->fx_addsy
== NULL
)
7730 else if (use_rela_relocations
)
7732 fixP
->fx_no_overflow
= 1;
7733 /* Remember value for tc_gen_reloc. */
7734 fixP
->fx_addnumber
= value
;
7738 md_number_to_chars (p
, value
, fixP
->fx_size
);
7742 md_atof (int type
, char *litP
, int *sizeP
)
7744 /* This outputs the LITTLENUMs in REVERSE order;
7745 in accord with the bigendian 386. */
7746 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7749 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7752 output_invalid (int c
)
7755 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7758 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7759 "(0x%x)", (unsigned char) c
);
7760 return output_invalid_buf
;
7763 /* REG_STRING starts *before* REGISTER_PREFIX. */
7765 static const reg_entry
*
7766 parse_real_register (char *reg_string
, char **end_op
)
7768 char *s
= reg_string
;
7770 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7773 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7774 if (*s
== REGISTER_PREFIX
)
7777 if (is_space_char (*s
))
7781 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7783 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7784 return (const reg_entry
*) NULL
;
7788 /* For naked regs, make sure that we are not dealing with an identifier.
7789 This prevents confusing an identifier like `eax_var' with register
7791 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7792 return (const reg_entry
*) NULL
;
7796 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7798 /* Handle floating point regs, allowing spaces in the (i) part. */
7799 if (r
== i386_regtab
/* %st is first entry of table */)
7801 if (is_space_char (*s
))
7806 if (is_space_char (*s
))
7808 if (*s
>= '0' && *s
<= '7')
7812 if (is_space_char (*s
))
7817 r
= hash_find (reg_hash
, "st(0)");
7822 /* We have "%st(" then garbage. */
7823 return (const reg_entry
*) NULL
;
7827 if (r
== NULL
|| allow_pseudo_reg
)
7830 if (operand_type_all_zero (&r
->reg_type
))
7831 return (const reg_entry
*) NULL
;
7833 if ((r
->reg_type
.bitfield
.reg32
7834 || r
->reg_type
.bitfield
.sreg3
7835 || r
->reg_type
.bitfield
.control
7836 || r
->reg_type
.bitfield
.debug
7837 || r
->reg_type
.bitfield
.test
)
7838 && !cpu_arch_flags
.bitfield
.cpui386
)
7839 return (const reg_entry
*) NULL
;
7841 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7842 return (const reg_entry
*) NULL
;
7844 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7845 return (const reg_entry
*) NULL
;
7847 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7848 return (const reg_entry
*) NULL
;
7850 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7851 if (!allow_index_reg
7852 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7853 return (const reg_entry
*) NULL
;
7855 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7856 || r
->reg_type
.bitfield
.reg64
)
7857 && (!cpu_arch_flags
.bitfield
.cpulm
7858 || !operand_type_equal (&r
->reg_type
, &control
))
7859 && flag_code
!= CODE_64BIT
)
7860 return (const reg_entry
*) NULL
;
7862 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7863 return (const reg_entry
*) NULL
;
7868 /* REG_STRING starts *before* REGISTER_PREFIX. */
7870 static const reg_entry
*
7871 parse_register (char *reg_string
, char **end_op
)
7875 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7876 r
= parse_real_register (reg_string
, end_op
);
7881 char *save
= input_line_pointer
;
7885 input_line_pointer
= reg_string
;
7886 c
= get_symbol_end ();
7887 symbolP
= symbol_find (reg_string
);
7888 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7890 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7892 know (e
->X_op
== O_register
);
7893 know (e
->X_add_number
>= 0
7894 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7895 r
= i386_regtab
+ e
->X_add_number
;
7896 *end_op
= input_line_pointer
;
7898 *input_line_pointer
= c
;
7899 input_line_pointer
= save
;
7905 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7908 char *end
= input_line_pointer
;
7911 r
= parse_register (name
, &input_line_pointer
);
7912 if (r
&& end
<= input_line_pointer
)
7914 *nextcharP
= *input_line_pointer
;
7915 *input_line_pointer
= 0;
7916 e
->X_op
= O_register
;
7917 e
->X_add_number
= r
- i386_regtab
;
7920 input_line_pointer
= end
;
7926 md_operand (expressionS
*e
)
7928 if (*input_line_pointer
== REGISTER_PREFIX
)
7931 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7935 e
->X_op
= O_register
;
7936 e
->X_add_number
= r
- i386_regtab
;
7937 input_line_pointer
= end
;
7943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7944 const char *md_shortopts
= "kVQ:sqn";
7946 const char *md_shortopts
= "qn";
7949 #define OPTION_32 (OPTION_MD_BASE + 0)
7950 #define OPTION_64 (OPTION_MD_BASE + 1)
7951 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7952 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7953 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7954 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7955 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7956 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7957 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7958 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7959 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7960 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7962 struct option md_longopts
[] =
7964 {"32", no_argument
, NULL
, OPTION_32
},
7965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7966 {"64", no_argument
, NULL
, OPTION_64
},
7968 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7969 {"march", required_argument
, NULL
, OPTION_MARCH
},
7970 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7971 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7972 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7973 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7974 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7975 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7976 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7977 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7978 {NULL
, no_argument
, NULL
, 0}
7980 size_t md_longopts_size
= sizeof (md_longopts
);
7983 md_parse_option (int c
, char *arg
)
7991 optimize_align_code
= 0;
7998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7999 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8000 should be emitted or not. FIXME: Not implemented. */
8004 /* -V: SVR4 argument to print version ID. */
8006 print_version_id ();
8009 /* -k: Ignore for FreeBSD compatibility. */
8014 /* -s: On i386 Solaris, this tells the native assembler to use
8015 .stab instead of .stab.excl. We always use .stab anyhow. */
8018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8021 const char **list
, **l
;
8023 list
= bfd_target_list ();
8024 for (l
= list
; *l
!= NULL
; l
++)
8025 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8026 || strcmp (*l
, "coff-x86-64") == 0
8027 || strcmp (*l
, "pe-x86-64") == 0
8028 || strcmp (*l
, "pei-x86-64") == 0)
8030 default_arch
= "x86_64";
8034 as_fatal (_("No compiled in support for x86_64"));
8041 default_arch
= "i386";
8045 #ifdef SVR4_COMMENT_CHARS
8050 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8052 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8056 i386_comment_chars
= n
;
8062 arch
= xstrdup (arg
);
8066 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8067 next
= strchr (arch
, '+');
8070 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8072 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8075 cpu_arch_name
= cpu_arch
[i
].name
;
8076 cpu_sub_arch_name
= NULL
;
8077 cpu_arch_flags
= cpu_arch
[i
].flags
;
8078 cpu_arch_isa
= cpu_arch
[i
].type
;
8079 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8080 if (!cpu_arch_tune_set
)
8082 cpu_arch_tune
= cpu_arch_isa
;
8083 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8087 else if (*cpu_arch
[i
].name
== '.'
8088 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8090 /* ISA entension. */
8091 i386_cpu_flags flags
;
8092 flags
= cpu_flags_or (cpu_arch_flags
,
8094 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8096 if (cpu_sub_arch_name
)
8098 char *name
= cpu_sub_arch_name
;
8099 cpu_sub_arch_name
= concat (name
,
8101 (const char *) NULL
);
8105 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8106 cpu_arch_flags
= flags
;
8112 if (i
>= ARRAY_SIZE (cpu_arch
))
8113 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8117 while (next
!= NULL
);
8122 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8123 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8125 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8127 cpu_arch_tune_set
= 1;
8128 cpu_arch_tune
= cpu_arch
[i
].type
;
8129 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8133 if (i
>= ARRAY_SIZE (cpu_arch
))
8134 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8137 case OPTION_MMNEMONIC
:
8138 if (strcasecmp (arg
, "att") == 0)
8140 else if (strcasecmp (arg
, "intel") == 0)
8143 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8146 case OPTION_MSYNTAX
:
8147 if (strcasecmp (arg
, "att") == 0)
8149 else if (strcasecmp (arg
, "intel") == 0)
8152 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8155 case OPTION_MINDEX_REG
:
8156 allow_index_reg
= 1;
8159 case OPTION_MNAKED_REG
:
8160 allow_naked_reg
= 1;
8163 case OPTION_MOLD_GCC
:
8167 case OPTION_MSSE2AVX
:
8171 case OPTION_MSSE_CHECK
:
8172 if (strcasecmp (arg
, "error") == 0)
8173 sse_check
= sse_check_error
;
8174 else if (strcasecmp (arg
, "warning") == 0)
8175 sse_check
= sse_check_warning
;
8176 else if (strcasecmp (arg
, "none") == 0)
8177 sse_check
= sse_check_none
;
8179 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8189 md_show_usage (stream
)
8192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8193 fprintf (stream
, _("\
8195 -V print assembler version number\n\
8198 fprintf (stream
, _("\
8199 -n Do not optimize code alignment\n\
8200 -q quieten some warnings\n"));
8201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8202 fprintf (stream
, _("\
8205 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8206 fprintf (stream
, _("\
8207 --32/--64 generate 32bit/64bit code\n"));
8209 #ifdef SVR4_COMMENT_CHARS
8210 fprintf (stream
, _("\
8211 --divide do not treat `/' as a comment character\n"));
8213 fprintf (stream
, _("\
8214 --divide ignored\n"));
8216 fprintf (stream
, _("\
8217 -march=CPU[,+EXTENSION...]\n\
8218 generate code for CPU and EXTENSION, CPU is one of:\n\
8219 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8220 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8221 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8222 generic32, generic64\n\
8223 EXTENSION is combination of:\n\
8224 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8225 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8226 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8227 sse5, svme, abm, padlock\n"));
8228 fprintf (stream
, _("\
8229 -mtune=CPU optimize for CPU, CPU is one of:\n\
8230 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8231 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8232 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8233 generic32, generic64\n"));
8234 fprintf (stream
, _("\
8235 -msse2avx encode SSE instructions with VEX prefix\n"));
8236 fprintf (stream
, _("\
8237 -msse-check=[none|error|warning]\n\
8238 check SSE instructions\n"));
8239 fprintf (stream
, _("\
8240 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8241 fprintf (stream
, _("\
8242 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8243 fprintf (stream
, _("\
8244 -mindex-reg support pseudo index registers\n"));
8245 fprintf (stream
, _("\
8246 -mnaked-reg don't require `%%' prefix for registers\n"));
8247 fprintf (stream
, _("\
8248 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8251 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8252 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8254 /* Pick the target format to use. */
8257 i386_target_format (void)
8259 if (!strcmp (default_arch
, "x86_64"))
8261 set_code_flag (CODE_64BIT
);
8262 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8264 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8265 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8266 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8267 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8268 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8269 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8270 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8271 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8272 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8273 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8275 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8277 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8278 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8279 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8280 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8281 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8282 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8283 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8284 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8285 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8286 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8289 else if (!strcmp (default_arch
, "i386"))
8291 set_code_flag (CODE_32BIT
);
8292 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8294 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8295 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8296 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8298 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8300 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8301 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8302 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8306 as_fatal (_("Unknown architecture"));
8307 switch (OUTPUT_FLAVOR
)
8310 case bfd_target_coff_flavour
:
8311 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8314 #ifdef OBJ_MAYBE_AOUT
8315 case bfd_target_aout_flavour
:
8316 return AOUT_TARGET_FORMAT
;
8318 #ifdef OBJ_MAYBE_COFF
8319 case bfd_target_coff_flavour
:
8322 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8323 case bfd_target_elf_flavour
:
8325 if (flag_code
== CODE_64BIT
)
8328 use_rela_relocations
= 1;
8330 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8339 #endif /* OBJ_MAYBE_ more than one */
8341 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8343 i386_elf_emit_arch_note (void)
8345 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8348 asection
*seg
= now_seg
;
8349 subsegT subseg
= now_subseg
;
8350 Elf_Internal_Note i_note
;
8351 Elf_External_Note e_note
;
8352 asection
*note_secp
;
8355 /* Create the .note section. */
8356 note_secp
= subseg_new (".note", 0);
8357 bfd_set_section_flags (stdoutput
,
8359 SEC_HAS_CONTENTS
| SEC_READONLY
);
8361 /* Process the arch string. */
8362 len
= strlen (cpu_arch_name
);
8364 i_note
.namesz
= len
+ 1;
8366 i_note
.type
= NT_ARCH
;
8367 p
= frag_more (sizeof (e_note
.namesz
));
8368 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8369 p
= frag_more (sizeof (e_note
.descsz
));
8370 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8371 p
= frag_more (sizeof (e_note
.type
));
8372 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8373 p
= frag_more (len
+ 1);
8374 strcpy (p
, cpu_arch_name
);
8376 frag_align (2, 0, 0);
8378 subseg_set (seg
, subseg
);
8384 md_undefined_symbol (name
)
8387 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8388 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8389 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8390 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8394 if (symbol_find (name
))
8395 as_bad (_("GOT already in symbol table"));
8396 GOT_symbol
= symbol_new (name
, undefined_section
,
8397 (valueT
) 0, &zero_address_frag
);
8404 /* Round up a section size to the appropriate boundary. */
8407 md_section_align (segment
, size
)
8408 segT segment ATTRIBUTE_UNUSED
;
8411 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8412 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8414 /* For a.out, force the section size to be aligned. If we don't do
8415 this, BFD will align it for us, but it will not write out the
8416 final bytes of the section. This may be a bug in BFD, but it is
8417 easier to fix it here since that is how the other a.out targets
8421 align
= bfd_get_section_alignment (stdoutput
, segment
);
8422 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8429 /* On the i386, PC-relative offsets are relative to the start of the
8430 next instruction. That is, the address of the offset, plus its
8431 size, since the offset is always the last part of the insn. */
8434 md_pcrel_from (fixS
*fixP
)
8436 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8442 s_bss (int ignore ATTRIBUTE_UNUSED
)
8446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8448 obj_elf_section_change_hook ();
8450 temp
= get_absolute_expression ();
8451 subseg_set (bss_section
, (subsegT
) temp
);
8452 demand_empty_rest_of_line ();
8458 i386_validate_fix (fixS
*fixp
)
8460 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8462 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8466 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8471 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8473 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8480 tc_gen_reloc (section
, fixp
)
8481 asection
*section ATTRIBUTE_UNUSED
;
8485 bfd_reloc_code_real_type code
;
8487 switch (fixp
->fx_r_type
)
8489 case BFD_RELOC_X86_64_PLT32
:
8490 case BFD_RELOC_X86_64_GOT32
:
8491 case BFD_RELOC_X86_64_GOTPCREL
:
8492 case BFD_RELOC_386_PLT32
:
8493 case BFD_RELOC_386_GOT32
:
8494 case BFD_RELOC_386_GOTOFF
:
8495 case BFD_RELOC_386_GOTPC
:
8496 case BFD_RELOC_386_TLS_GD
:
8497 case BFD_RELOC_386_TLS_LDM
:
8498 case BFD_RELOC_386_TLS_LDO_32
:
8499 case BFD_RELOC_386_TLS_IE_32
:
8500 case BFD_RELOC_386_TLS_IE
:
8501 case BFD_RELOC_386_TLS_GOTIE
:
8502 case BFD_RELOC_386_TLS_LE_32
:
8503 case BFD_RELOC_386_TLS_LE
:
8504 case BFD_RELOC_386_TLS_GOTDESC
:
8505 case BFD_RELOC_386_TLS_DESC_CALL
:
8506 case BFD_RELOC_X86_64_TLSGD
:
8507 case BFD_RELOC_X86_64_TLSLD
:
8508 case BFD_RELOC_X86_64_DTPOFF32
:
8509 case BFD_RELOC_X86_64_DTPOFF64
:
8510 case BFD_RELOC_X86_64_GOTTPOFF
:
8511 case BFD_RELOC_X86_64_TPOFF32
:
8512 case BFD_RELOC_X86_64_TPOFF64
:
8513 case BFD_RELOC_X86_64_GOTOFF64
:
8514 case BFD_RELOC_X86_64_GOTPC32
:
8515 case BFD_RELOC_X86_64_GOT64
:
8516 case BFD_RELOC_X86_64_GOTPCREL64
:
8517 case BFD_RELOC_X86_64_GOTPC64
:
8518 case BFD_RELOC_X86_64_GOTPLT64
:
8519 case BFD_RELOC_X86_64_PLTOFF64
:
8520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8521 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8523 case BFD_RELOC_VTABLE_ENTRY
:
8524 case BFD_RELOC_VTABLE_INHERIT
:
8526 case BFD_RELOC_32_SECREL
:
8528 code
= fixp
->fx_r_type
;
8530 case BFD_RELOC_X86_64_32S
:
8531 if (!fixp
->fx_pcrel
)
8533 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8534 code
= fixp
->fx_r_type
;
8540 switch (fixp
->fx_size
)
8543 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8544 _("can not do %d byte pc-relative relocation"),
8546 code
= BFD_RELOC_32_PCREL
;
8548 case 1: code
= BFD_RELOC_8_PCREL
; break;
8549 case 2: code
= BFD_RELOC_16_PCREL
; break;
8550 case 4: code
= BFD_RELOC_32_PCREL
; break;
8552 case 8: code
= BFD_RELOC_64_PCREL
; break;
8558 switch (fixp
->fx_size
)
8561 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8562 _("can not do %d byte relocation"),
8564 code
= BFD_RELOC_32
;
8566 case 1: code
= BFD_RELOC_8
; break;
8567 case 2: code
= BFD_RELOC_16
; break;
8568 case 4: code
= BFD_RELOC_32
; break;
8570 case 8: code
= BFD_RELOC_64
; break;
8577 if ((code
== BFD_RELOC_32
8578 || code
== BFD_RELOC_32_PCREL
8579 || code
== BFD_RELOC_X86_64_32S
)
8581 && fixp
->fx_addsy
== GOT_symbol
)
8584 code
= BFD_RELOC_386_GOTPC
;
8586 code
= BFD_RELOC_X86_64_GOTPC32
;
8588 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8590 && fixp
->fx_addsy
== GOT_symbol
)
8592 code
= BFD_RELOC_X86_64_GOTPC64
;
8595 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8596 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8597 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8599 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8601 if (!use_rela_relocations
)
8603 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8604 vtable entry to be used in the relocation's section offset. */
8605 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8606 rel
->address
= fixp
->fx_offset
;
8610 /* Use the rela in 64bit mode. */
8613 if (!fixp
->fx_pcrel
)
8614 rel
->addend
= fixp
->fx_offset
;
8618 case BFD_RELOC_X86_64_PLT32
:
8619 case BFD_RELOC_X86_64_GOT32
:
8620 case BFD_RELOC_X86_64_GOTPCREL
:
8621 case BFD_RELOC_X86_64_TLSGD
:
8622 case BFD_RELOC_X86_64_TLSLD
:
8623 case BFD_RELOC_X86_64_GOTTPOFF
:
8624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8625 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8626 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8629 rel
->addend
= (section
->vma
8631 + fixp
->fx_addnumber
8632 + md_pcrel_from (fixp
));
8637 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8638 if (rel
->howto
== NULL
)
8640 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8641 _("cannot represent relocation type %s"),
8642 bfd_get_reloc_code_name (code
));
8643 /* Set howto to a garbage value so that we can keep going. */
8644 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8645 assert (rel
->howto
!= NULL
);
8652 /* Parse operands using Intel syntax. This implements a recursive descent
8653 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8656 FIXME: We do not recognize the full operand grammar defined in the MASM
8657 documentation. In particular, all the structure/union and
8658 high-level macro operands are missing.
8660 Uppercase words are terminals, lower case words are non-terminals.
8661 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8662 bars '|' denote choices. Most grammar productions are implemented in
8663 functions called 'intel_<production>'.
8665 Initial production is 'expr'.
8671 binOp & | AND | \| | OR | ^ | XOR
8673 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8675 constant digits [[ radixOverride ]]
8677 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8715 => expr expr cmpOp e04
8718 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8719 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8721 hexdigit a | b | c | d | e | f
8722 | A | B | C | D | E | F
8728 mulOp * | / | % | MOD | << | SHL | >> | SHR
8732 register specialRegister
8736 segmentRegister CS | DS | ES | FS | GS | SS
8738 specialRegister CR0 | CR2 | CR3 | CR4
8739 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8740 | TR3 | TR4 | TR5 | TR6 | TR7
8742 We simplify the grammar in obvious places (e.g., register parsing is
8743 done by calling parse_register) and eliminate immediate left recursion
8744 to implement a recursive-descent parser.
8748 expr' cmpOp e04 expr'
8800 /* Parsing structure for the intel syntax parser. Used to implement the
8801 semantic actions for the operand grammar. */
8802 struct intel_parser_s
8804 char *op_string
; /* The string being parsed. */
8805 int got_a_float
; /* Whether the operand is a float. */
8806 int op_modifier
; /* Operand modifier. */
8807 int is_mem
; /* 1 if operand is memory reference. */
8808 int in_offset
; /* >=1 if parsing operand of offset. */
8809 int in_bracket
; /* >=1 if parsing operand in brackets. */
8810 const reg_entry
*reg
; /* Last register reference found. */
8811 char *disp
; /* Displacement string being built. */
8812 char *next_operand
; /* Resume point when splitting operands. */
8815 static struct intel_parser_s intel_parser
;
8817 /* Token structure for parsing intel syntax. */
8820 int code
; /* Token code. */
8821 const reg_entry
*reg
; /* Register entry for register tokens. */
8822 char *str
; /* String representation. */
8825 static struct intel_token cur_token
, prev_token
;
8827 /* Token codes for the intel parser. Since T_SHORT is already used
8828 by COFF, undefine it first to prevent a warning. */
8846 #define T_YMMWORD 16
8848 /* Prototypes for intel parser functions. */
8849 static int intel_match_token (int);
8850 static void intel_putback_token (void);
8851 static void intel_get_token (void);
8852 static int intel_expr (void);
8853 static int intel_e04 (void);
8854 static int intel_e05 (void);
8855 static int intel_e06 (void);
8856 static int intel_e09 (void);
8857 static int intel_e10 (void);
8858 static int intel_e11 (void);
8861 i386_intel_operand (char *operand_string
, int got_a_float
)
8865 const reg_entry
*final_base
= i
.base_reg
;
8866 const reg_entry
*final_index
= i
.index_reg
;
8868 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8869 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8873 /* Initialize token holders. */
8874 cur_token
.code
= prev_token
.code
= T_NIL
;
8875 cur_token
.reg
= prev_token
.reg
= NULL
;
8876 cur_token
.str
= prev_token
.str
= NULL
;
8878 /* Initialize parser structure. */
8879 intel_parser
.got_a_float
= got_a_float
;
8880 intel_parser
.op_modifier
= 0;
8881 intel_parser
.is_mem
= 0;
8882 intel_parser
.in_offset
= 0;
8883 intel_parser
.in_bracket
= 0;
8884 intel_parser
.reg
= NULL
;
8885 intel_parser
.disp
[0] = '\0';
8886 intel_parser
.next_operand
= NULL
;
8891 /* Read the first token and start the parser. */
8893 ret
= intel_expr ();
8898 if (cur_token
.code
!= T_NIL
)
8900 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8901 current_templates
->start
->name
, cur_token
.str
);
8904 /* If we found a memory reference, hand it over to i386_displacement
8905 to fill in the rest of the operand fields. */
8906 else if (intel_parser
.is_mem
)
8908 if ((i
.mem_operands
== 1
8909 && !current_templates
->start
->opcode_modifier
.isstring
)
8910 || i
.mem_operands
== 2)
8912 as_bad (_("too many memory references for '%s'"),
8913 current_templates
->start
->name
);
8918 char *s
= intel_parser
.disp
;
8920 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8921 /* See the comments in intel_bracket_expr. */
8922 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8924 /* Add the displacement expression. */
8926 ret
= i386_displacement (s
, s
+ strlen (s
));
8929 /* Swap base and index in 16-bit memory operands like
8930 [si+bx]. Since i386_index_check is also used in AT&T
8931 mode we have to do that here. */
8934 && i
.base_reg
->reg_type
.bitfield
.reg16
8935 && i
.index_reg
->reg_type
.bitfield
.reg16
8936 && i
.base_reg
->reg_num
>= 6
8937 && i
.index_reg
->reg_num
< 6)
8939 const reg_entry
*base
= i
.index_reg
;
8941 i
.index_reg
= i
.base_reg
;
8944 ret
= i386_index_check (operand_string
);
8948 i
.types
[this_operand
].bitfield
.mem
= 1;
8954 /* Constant and OFFSET expressions are handled by i386_immediate. */
8955 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8956 || intel_parser
.reg
== NULL
)
8958 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8960 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8961 as_warn (_("Segment override ignored"));
8962 i
.seg
[i
.mem_operands
] = NULL
;
8964 ret
= i386_immediate (intel_parser
.disp
);
8967 if (!final_base
&& !final_index
)
8969 final_base
= i
.base_reg
;
8970 final_index
= i
.index_reg
;
8973 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8975 if (!ret
|| !intel_parser
.next_operand
)
8977 intel_parser
.op_string
= intel_parser
.next_operand
;
8978 this_operand
= i
.operands
++;
8979 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8983 free (intel_parser
.disp
);
8985 if (final_base
|| final_index
)
8987 i
.base_reg
= final_base
;
8988 i
.index_reg
= final_index
;
8994 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8998 expr' cmpOp e04 expr'
9003 /* XXX Implement the comparison operators. */
9004 return intel_e04 ();
9021 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9022 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9024 if (cur_token
.code
== '+')
9026 else if (cur_token
.code
== '-')
9027 nregs
= NUM_ADDRESS_REGS
;
9031 strcat (intel_parser
.disp
, cur_token
.str
);
9032 intel_match_token (cur_token
.code
);
9043 int nregs
= ~NUM_ADDRESS_REGS
;
9050 if (cur_token
.code
== '&'
9051 || cur_token
.code
== '|'
9052 || cur_token
.code
== '^')
9056 str
[0] = cur_token
.code
;
9058 strcat (intel_parser
.disp
, str
);
9063 intel_match_token (cur_token
.code
);
9068 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9069 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9080 int nregs
= ~NUM_ADDRESS_REGS
;
9087 if (cur_token
.code
== '*'
9088 || cur_token
.code
== '/'
9089 || cur_token
.code
== '%')
9093 str
[0] = cur_token
.code
;
9095 strcat (intel_parser
.disp
, str
);
9097 else if (cur_token
.code
== T_SHL
)
9098 strcat (intel_parser
.disp
, "<<");
9099 else if (cur_token
.code
== T_SHR
)
9100 strcat (intel_parser
.disp
, ">>");
9104 intel_match_token (cur_token
.code
);
9109 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9110 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9128 int nregs
= ~NUM_ADDRESS_REGS
;
9133 /* Don't consume constants here. */
9134 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9136 /* Need to look one token ahead - if the next token
9137 is a constant, the current token is its sign. */
9140 intel_match_token (cur_token
.code
);
9141 next_code
= cur_token
.code
;
9142 intel_putback_token ();
9143 if (next_code
== T_CONST
)
9147 /* e09 OFFSET e09 */
9148 if (cur_token
.code
== T_OFFSET
)
9151 ++intel_parser
.in_offset
;
9155 else if (cur_token
.code
== T_SHORT
)
9156 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9159 else if (cur_token
.code
== '+')
9160 strcat (intel_parser
.disp
, "+");
9165 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9171 str
[0] = cur_token
.code
;
9173 strcat (intel_parser
.disp
, str
);
9180 intel_match_token (cur_token
.code
);
9188 /* e09' PTR e10 e09' */
9189 if (cur_token
.code
== T_PTR
)
9193 if (prev_token
.code
== T_BYTE
)
9195 suffix
= BYTE_MNEM_SUFFIX
;
9196 i
.types
[this_operand
].bitfield
.byte
= 1;
9199 else if (prev_token
.code
== T_WORD
)
9201 if ((current_templates
->start
->name
[0] == 'l'
9202 && current_templates
->start
->name
[2] == 's'
9203 && current_templates
->start
->name
[3] == 0)
9204 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9205 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9206 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9207 suffix
= SHORT_MNEM_SUFFIX
;
9209 suffix
= WORD_MNEM_SUFFIX
;
9210 i
.types
[this_operand
].bitfield
.word
= 1;
9213 else if (prev_token
.code
== T_DWORD
)
9215 if ((current_templates
->start
->name
[0] == 'l'
9216 && current_templates
->start
->name
[2] == 's'
9217 && current_templates
->start
->name
[3] == 0)
9218 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9219 suffix
= WORD_MNEM_SUFFIX
;
9220 else if (flag_code
== CODE_16BIT
9221 && (current_templates
->start
->opcode_modifier
.jump
9222 || current_templates
->start
->opcode_modifier
.jumpdword
))
9223 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9224 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9225 suffix
= SHORT_MNEM_SUFFIX
;
9227 suffix
= LONG_MNEM_SUFFIX
;
9228 i
.types
[this_operand
].bitfield
.dword
= 1;
9231 else if (prev_token
.code
== T_FWORD
)
9233 if (current_templates
->start
->name
[0] == 'l'
9234 && current_templates
->start
->name
[2] == 's'
9235 && current_templates
->start
->name
[3] == 0)
9236 suffix
= LONG_MNEM_SUFFIX
;
9237 else if (!intel_parser
.got_a_float
)
9239 if (flag_code
== CODE_16BIT
)
9240 add_prefix (DATA_PREFIX_OPCODE
);
9241 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9244 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9245 i
.types
[this_operand
].bitfield
.fword
= 1;
9248 else if (prev_token
.code
== T_QWORD
)
9250 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9251 || intel_parser
.got_a_float
== 1) /* "f..." */
9252 suffix
= LONG_MNEM_SUFFIX
;
9254 suffix
= QWORD_MNEM_SUFFIX
;
9255 i
.types
[this_operand
].bitfield
.qword
= 1;
9258 else if (prev_token
.code
== T_TBYTE
)
9260 if (intel_parser
.got_a_float
== 1)
9261 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9263 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9266 else if (prev_token
.code
== T_XMMWORD
)
9268 suffix
= XMMWORD_MNEM_SUFFIX
;
9269 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9272 else if (prev_token
.code
== T_YMMWORD
)
9274 suffix
= YMMWORD_MNEM_SUFFIX
;
9275 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9280 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9284 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9286 /* Operands for jump/call using 'ptr' notation denote absolute
9288 if (current_templates
->start
->opcode_modifier
.jump
9289 || current_templates
->start
->opcode_modifier
.jumpdword
)
9290 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9292 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9296 else if (i
.suffix
!= suffix
)
9298 as_bad (_("Conflicting operand modifiers"));
9304 /* e09' : e10 e09' */
9305 else if (cur_token
.code
== ':')
9307 if (prev_token
.code
!= T_REG
)
9309 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9310 segment/group identifier (which we don't have), using comma
9311 as the operand separator there is even less consistent, since
9312 there all branches only have a single operand. */
9313 if (this_operand
!= 0
9314 || intel_parser
.in_offset
9315 || intel_parser
.in_bracket
9316 || (!current_templates
->start
->opcode_modifier
.jump
9317 && !current_templates
->start
->opcode_modifier
.jumpdword
9318 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9319 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9320 return intel_match_token (T_NIL
);
9321 /* Remember the start of the 2nd operand and terminate 1st
9323 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9324 another expression), but it gets at least the simplest case
9325 (a plain number or symbol on the left side) right. */
9326 intel_parser
.next_operand
= intel_parser
.op_string
;
9327 *--intel_parser
.op_string
= '\0';
9328 return intel_match_token (':');
9336 intel_match_token (cur_token
.code
);
9342 --intel_parser
.in_offset
;
9345 if (NUM_ADDRESS_REGS
> nregs
)
9347 as_bad (_("Invalid operand to `OFFSET'"));
9350 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9353 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9354 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9359 intel_bracket_expr (void)
9361 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9362 const char *start
= intel_parser
.op_string
;
9365 if (i
.op
[this_operand
].regs
)
9366 return intel_match_token (T_NIL
);
9368 intel_match_token ('[');
9370 /* Mark as a memory operand only if it's not already known to be an
9371 offset expression. If it's an offset expression, we need to keep
9373 if (!intel_parser
.in_offset
)
9375 ++intel_parser
.in_bracket
;
9377 /* Operands for jump/call inside brackets denote absolute addresses. */
9378 if (current_templates
->start
->opcode_modifier
.jump
9379 || current_templates
->start
->opcode_modifier
.jumpdword
)
9380 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9382 /* Unfortunately gas always diverged from MASM in a respect that can't
9383 be easily fixed without risking to break code sequences likely to be
9384 encountered (the testsuite even check for this): MASM doesn't consider
9385 an expression inside brackets unconditionally as a memory reference.
9386 When that is e.g. a constant, an offset expression, or the sum of the
9387 two, this is still taken as a constant load. gas, however, always
9388 treated these as memory references. As a compromise, we'll try to make
9389 offset expressions inside brackets work the MASM way (since that's
9390 less likely to be found in real world code), but make constants alone
9391 continue to work the traditional gas way. In either case, issue a
9393 intel_parser
.op_modifier
&= ~was_offset
;
9396 strcat (intel_parser
.disp
, "[");
9398 /* Add a '+' to the displacement string if necessary. */
9399 if (*intel_parser
.disp
!= '\0'
9400 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9401 strcat (intel_parser
.disp
, "+");
9404 && (len
= intel_parser
.op_string
- start
- 1,
9405 intel_match_token (']')))
9407 /* Preserve brackets when the operand is an offset expression. */
9408 if (intel_parser
.in_offset
)
9409 strcat (intel_parser
.disp
, "]");
9412 --intel_parser
.in_bracket
;
9413 if (i
.base_reg
|| i
.index_reg
)
9414 intel_parser
.is_mem
= 1;
9415 if (!intel_parser
.is_mem
)
9417 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9418 /* Defer the warning until all of the operand was parsed. */
9419 intel_parser
.is_mem
= -1;
9420 else if (!quiet_warnings
)
9421 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9422 len
, start
, len
, start
);
9425 intel_parser
.op_modifier
|= was_offset
;
9442 while (cur_token
.code
== '[')
9444 if (!intel_bracket_expr ())
9470 switch (cur_token
.code
)
9474 intel_match_token ('(');
9475 strcat (intel_parser
.disp
, "(");
9477 if (intel_expr () && intel_match_token (')'))
9479 strcat (intel_parser
.disp
, ")");
9486 return intel_bracket_expr ();
9491 strcat (intel_parser
.disp
, cur_token
.str
);
9492 intel_match_token (cur_token
.code
);
9494 /* Mark as a memory operand only if it's not already known to be an
9495 offset expression. */
9496 if (!intel_parser
.in_offset
)
9497 intel_parser
.is_mem
= 1;
9504 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9506 intel_match_token (T_REG
);
9508 /* Check for segment change. */
9509 if (cur_token
.code
== ':')
9511 if (!reg
->reg_type
.bitfield
.sreg2
9512 && !reg
->reg_type
.bitfield
.sreg3
)
9514 as_bad (_("`%s' is not a valid segment register"),
9518 else if (i
.mem_operands
>= 2)
9519 as_warn (_("Segment override ignored"));
9520 else if (i
.seg
[i
.mem_operands
])
9521 as_warn (_("Extra segment override ignored"));
9524 if (!intel_parser
.in_offset
)
9525 intel_parser
.is_mem
= 1;
9526 switch (reg
->reg_num
)
9529 i
.seg
[i
.mem_operands
] = &es
;
9532 i
.seg
[i
.mem_operands
] = &cs
;
9535 i
.seg
[i
.mem_operands
] = &ss
;
9538 i
.seg
[i
.mem_operands
] = &ds
;
9541 i
.seg
[i
.mem_operands
] = &fs
;
9544 i
.seg
[i
.mem_operands
] = &gs
;
9550 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9552 as_bad (_("cannot use `FLAT' here"));
9556 /* Not a segment register. Check for register scaling. */
9557 else if (cur_token
.code
== '*')
9559 if (!intel_parser
.in_bracket
)
9561 as_bad (_("Register scaling only allowed in memory operands"));
9565 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9566 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9567 else if (i
.index_reg
)
9568 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9570 /* What follows must be a valid scale. */
9571 intel_match_token ('*');
9573 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9575 /* Set the scale after setting the register (otherwise,
9576 i386_scale will complain) */
9577 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9579 char *str
, sign
= cur_token
.code
;
9580 intel_match_token (cur_token
.code
);
9581 if (cur_token
.code
!= T_CONST
)
9583 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9587 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9588 strcpy (str
+ 1, cur_token
.str
);
9590 if (!i386_scale (str
))
9594 else if (!i386_scale (cur_token
.str
))
9596 intel_match_token (cur_token
.code
);
9599 /* No scaling. If this is a memory operand, the register is either a
9600 base register (first occurrence) or an index register (second
9602 else if (intel_parser
.in_bracket
)
9607 else if (!i
.index_reg
)
9611 as_bad (_("Too many register references in memory operand"));
9615 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9618 /* It's neither base nor index. */
9619 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9621 i386_operand_type temp
= reg
->reg_type
;
9622 temp
.bitfield
.baseindex
= 0;
9623 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9625 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9626 i
.op
[this_operand
].regs
= reg
;
9631 as_bad (_("Invalid use of register"));
9635 /* Since registers are not part of the displacement string (except
9636 when we're parsing offset operands), we may need to remove any
9637 preceding '+' from the displacement string. */
9638 if (*intel_parser
.disp
!= '\0'
9639 && !intel_parser
.in_offset
)
9641 char *s
= intel_parser
.disp
;
9642 s
+= strlen (s
) - 1;
9667 intel_match_token (cur_token
.code
);
9669 if (cur_token
.code
== T_PTR
)
9672 /* It must have been an identifier. */
9673 intel_putback_token ();
9674 cur_token
.code
= T_ID
;
9680 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9684 /* The identifier represents a memory reference only if it's not
9685 preceded by an offset modifier and if it's not an equate. */
9686 symbolP
= symbol_find(cur_token
.str
);
9687 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9688 intel_parser
.is_mem
= 1;
9696 char *save_str
, sign
= 0;
9698 /* Allow constants that start with `+' or `-'. */
9699 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9701 sign
= cur_token
.code
;
9702 intel_match_token (cur_token
.code
);
9703 if (cur_token
.code
!= T_CONST
)
9705 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9711 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9712 strcpy (save_str
+ !!sign
, cur_token
.str
);
9716 /* Get the next token to check for register scaling. */
9717 intel_match_token (cur_token
.code
);
9719 /* Check if this constant is a scaling factor for an
9721 if (cur_token
.code
== '*')
9723 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9725 const reg_entry
*reg
= cur_token
.reg
;
9727 if (!intel_parser
.in_bracket
)
9729 as_bad (_("Register scaling only allowed "
9730 "in memory operands"));
9734 /* Disallow things like [1*si].
9735 sp and esp are invalid as index. */
9736 if (reg
->reg_type
.bitfield
.reg16
)
9737 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9738 else if (i
.index_reg
)
9739 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9741 /* The constant is followed by `* reg', so it must be
9744 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9746 /* Set the scale after setting the register (otherwise,
9747 i386_scale will complain) */
9748 if (!i386_scale (save_str
))
9750 intel_match_token (T_REG
);
9752 /* Since registers are not part of the displacement
9753 string, we may need to remove any preceding '+' from
9754 the displacement string. */
9755 if (*intel_parser
.disp
!= '\0')
9757 char *s
= intel_parser
.disp
;
9758 s
+= strlen (s
) - 1;
9768 /* The constant was not used for register scaling. Since we have
9769 already consumed the token following `*' we now need to put it
9770 back in the stream. */
9771 intel_putback_token ();
9774 /* Add the constant to the displacement string. */
9775 strcat (intel_parser
.disp
, save_str
);
9782 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9786 /* Match the given token against cur_token. If they match, read the next
9787 token from the operand string. */
9789 intel_match_token (int code
)
9791 if (cur_token
.code
== code
)
9798 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9803 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9805 intel_get_token (void)
9808 const reg_entry
*reg
;
9809 struct intel_token new_token
;
9811 new_token
.code
= T_NIL
;
9812 new_token
.reg
= NULL
;
9813 new_token
.str
= NULL
;
9815 /* Free the memory allocated to the previous token and move
9816 cur_token to prev_token. */
9818 free (prev_token
.str
);
9820 prev_token
= cur_token
;
9822 /* Skip whitespace. */
9823 while (is_space_char (*intel_parser
.op_string
))
9824 intel_parser
.op_string
++;
9826 /* Return an empty token if we find nothing else on the line. */
9827 if (*intel_parser
.op_string
== '\0')
9829 cur_token
= new_token
;
9833 /* The new token cannot be larger than the remainder of the operand
9835 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9836 new_token
.str
[0] = '\0';
9838 if (strchr ("0123456789", *intel_parser
.op_string
))
9840 char *p
= new_token
.str
;
9841 char *q
= intel_parser
.op_string
;
9842 new_token
.code
= T_CONST
;
9844 /* Allow any kind of identifier char to encompass floating point and
9845 hexadecimal numbers. */
9846 while (is_identifier_char (*q
))
9850 /* Recognize special symbol names [0-9][bf]. */
9851 if (strlen (intel_parser
.op_string
) == 2
9852 && (intel_parser
.op_string
[1] == 'b'
9853 || intel_parser
.op_string
[1] == 'f'))
9854 new_token
.code
= T_ID
;
9857 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9859 size_t len
= end_op
- intel_parser
.op_string
;
9861 new_token
.code
= T_REG
;
9862 new_token
.reg
= reg
;
9864 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9865 new_token
.str
[len
] = '\0';
9868 else if (is_identifier_char (*intel_parser
.op_string
))
9870 char *p
= new_token
.str
;
9871 char *q
= intel_parser
.op_string
;
9873 /* A '.' or '$' followed by an identifier char is an identifier.
9874 Otherwise, it's operator '.' followed by an expression. */
9875 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9877 new_token
.code
= '.';
9878 new_token
.str
[0] = '.';
9879 new_token
.str
[1] = '\0';
9883 while (is_identifier_char (*q
) || *q
== '@')
9887 if (strcasecmp (new_token
.str
, "NOT") == 0)
9888 new_token
.code
= '~';
9890 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9891 new_token
.code
= '%';
9893 else if (strcasecmp (new_token
.str
, "AND") == 0)
9894 new_token
.code
= '&';
9896 else if (strcasecmp (new_token
.str
, "OR") == 0)
9897 new_token
.code
= '|';
9899 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9900 new_token
.code
= '^';
9902 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9903 new_token
.code
= T_SHL
;
9905 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9906 new_token
.code
= T_SHR
;
9908 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9909 new_token
.code
= T_BYTE
;
9911 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9912 new_token
.code
= T_WORD
;
9914 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9915 new_token
.code
= T_DWORD
;
9917 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9918 new_token
.code
= T_FWORD
;
9920 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9921 new_token
.code
= T_QWORD
;
9923 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9924 /* XXX remove (gcc still uses it) */
9925 || strcasecmp (new_token
.str
, "XWORD") == 0)
9926 new_token
.code
= T_TBYTE
;
9928 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9929 || strcasecmp (new_token
.str
, "OWORD") == 0)
9930 new_token
.code
= T_XMMWORD
;
9932 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9933 new_token
.code
= T_YMMWORD
;
9935 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9936 new_token
.code
= T_PTR
;
9938 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9939 new_token
.code
= T_SHORT
;
9941 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9943 new_token
.code
= T_OFFSET
;
9945 /* ??? This is not mentioned in the MASM grammar but gcc
9946 makes use of it with -mintel-syntax. OFFSET may be
9947 followed by FLAT: */
9948 if (strncasecmp (q
, " FLAT:", 6) == 0)
9949 strcat (new_token
.str
, " FLAT:");
9953 new_token
.code
= T_ID
;
9957 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9959 new_token
.code
= *intel_parser
.op_string
;
9960 new_token
.str
[0] = *intel_parser
.op_string
;
9961 new_token
.str
[1] = '\0';
9964 else if (strchr ("<>", *intel_parser
.op_string
)
9965 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9967 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9968 new_token
.str
[0] = *intel_parser
.op_string
;
9969 new_token
.str
[1] = *intel_parser
.op_string
;
9970 new_token
.str
[2] = '\0';
9974 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9976 intel_parser
.op_string
+= strlen (new_token
.str
);
9977 cur_token
= new_token
;
9980 /* Put cur_token back into the token stream and make cur_token point to
9983 intel_putback_token (void)
9985 if (cur_token
.code
!= T_NIL
)
9987 intel_parser
.op_string
-= strlen (cur_token
.str
);
9988 free (cur_token
.str
);
9990 cur_token
= prev_token
;
9992 /* Forget prev_token. */
9993 prev_token
.code
= T_NIL
;
9994 prev_token
.reg
= NULL
;
9995 prev_token
.str
= NULL
;
9999 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10001 int saved_naked_reg
;
10002 char saved_register_dot
;
10004 saved_naked_reg
= allow_naked_reg
;
10005 allow_naked_reg
= 1;
10006 saved_register_dot
= register_chars
['.'];
10007 register_chars
['.'] = '.';
10008 allow_pseudo_reg
= 1;
10009 expression_and_evaluate (exp
);
10010 allow_pseudo_reg
= 0;
10011 register_chars
['.'] = saved_register_dot
;
10012 allow_naked_reg
= saved_naked_reg
;
10014 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10016 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10018 exp
->X_op
= O_constant
;
10019 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10020 .dw2_regnum
[flag_code
>> 1];
10023 exp
->X_op
= O_illegal
;
10028 tc_x86_frame_initial_instructions (void)
10030 static unsigned int sp_regno
[2];
10032 if (!sp_regno
[flag_code
>> 1])
10034 char *saved_input
= input_line_pointer
;
10035 char sp
[][4] = {"esp", "rsp"};
10038 input_line_pointer
= sp
[flag_code
>> 1];
10039 tc_x86_parse_to_dw2regnum (&exp
);
10040 assert (exp
.X_op
== O_constant
);
10041 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10042 input_line_pointer
= saved_input
;
10045 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10046 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10050 i386_elf_section_type (const char *str
, size_t len
)
10052 if (flag_code
== CODE_64BIT
10053 && len
== sizeof ("unwind") - 1
10054 && strncmp (str
, "unwind", 6) == 0)
10055 return SHT_X86_64_UNWIND
;
10062 i386_solaris_fix_up_eh_frame (segT sec
)
10064 if (flag_code
== CODE_64BIT
)
10065 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10071 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10075 expr
.X_op
= O_secrel
;
10076 expr
.X_add_symbol
= symbol
;
10077 expr
.X_add_number
= 0;
10078 emit_expr (&expr
, size
);
10082 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10083 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10086 x86_64_section_letter (int letter
, char **ptr_msg
)
10088 if (flag_code
== CODE_64BIT
)
10091 return SHF_X86_64_LARGE
;
10093 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10096 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10101 x86_64_section_word (char *str
, size_t len
)
10103 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10104 return SHF_X86_64_LARGE
;
10110 handle_large_common (int small ATTRIBUTE_UNUSED
)
10112 if (flag_code
!= CODE_64BIT
)
10114 s_comm_internal (0, elf_common_parse
);
10115 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10119 static segT lbss_section
;
10120 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10121 asection
*saved_bss_section
= bss_section
;
10123 if (lbss_section
== NULL
)
10125 flagword applicable
;
10126 segT seg
= now_seg
;
10127 subsegT subseg
= now_subseg
;
10129 /* The .lbss section is for local .largecomm symbols. */
10130 lbss_section
= subseg_new (".lbss", 0);
10131 applicable
= bfd_applicable_section_flags (stdoutput
);
10132 bfd_set_section_flags (stdoutput
, lbss_section
,
10133 applicable
& SEC_ALLOC
);
10134 seg_info (lbss_section
)->bss
= 1;
10136 subseg_set (seg
, subseg
);
10139 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10140 bss_section
= lbss_section
;
10142 s_comm_internal (0, elf_common_parse
);
10144 elf_com_section_ptr
= saved_com_section_ptr
;
10145 bss_section
= saved_bss_section
;
10148 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */