1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "k6", PROCESSOR_K6
,
605 { "k6_2", PROCESSOR_K6
,
607 { "athlon", PROCESSOR_ATHLON
,
609 { "sledgehammer", PROCESSOR_K8
,
611 { "opteron", PROCESSOR_K8
,
613 { "k8", PROCESSOR_K8
,
615 { "amdfam10", PROCESSOR_AMDFAM10
,
616 CPU_AMDFAM10_FLAGS
},
617 { ".mmx", PROCESSOR_UNKNOWN
,
619 { ".sse", PROCESSOR_UNKNOWN
,
621 { ".sse2", PROCESSOR_UNKNOWN
,
623 { ".sse3", PROCESSOR_UNKNOWN
,
625 { ".ssse3", PROCESSOR_UNKNOWN
,
627 { ".sse4.1", PROCESSOR_UNKNOWN
,
629 { ".sse4.2", PROCESSOR_UNKNOWN
,
631 { ".sse4", PROCESSOR_UNKNOWN
,
633 { ".avx", PROCESSOR_UNKNOWN
,
635 { ".vmx", PROCESSOR_UNKNOWN
,
637 { ".smx", PROCESSOR_UNKNOWN
,
639 { ".xsave", PROCESSOR_UNKNOWN
,
641 { ".aes", PROCESSOR_UNKNOWN
,
643 { ".pclmul", PROCESSOR_UNKNOWN
,
645 { ".clmul", PROCESSOR_UNKNOWN
,
647 { ".fma", PROCESSOR_UNKNOWN
,
649 { ".movbe", PROCESSOR_UNKNOWN
,
651 { ".ept", PROCESSOR_UNKNOWN
,
653 { ".rdtscp", PROCESSOR_UNKNOWN
,
655 { ".3dnow", PROCESSOR_UNKNOWN
,
657 { ".3dnowa", PROCESSOR_UNKNOWN
,
659 { ".padlock", PROCESSOR_UNKNOWN
,
661 { ".pacifica", PROCESSOR_UNKNOWN
,
663 { ".svme", PROCESSOR_UNKNOWN
,
665 { ".sse4a", PROCESSOR_UNKNOWN
,
667 { ".abm", PROCESSOR_UNKNOWN
,
669 { ".sse5", PROCESSOR_UNKNOWN
,
674 /* Like s_lcomm_internal in gas/read.c but the alignment string
675 is allowed to be optional. */
678 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
685 && *input_line_pointer
== ',')
687 align
= parse_align (needs_align
- 1);
689 if (align
== (addressT
) -1)
704 bss_alloc (symbolP
, size
, align
);
709 pe_lcomm (int needs_align
)
711 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
715 const pseudo_typeS md_pseudo_table
[] =
717 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
718 {"align", s_align_bytes
, 0},
720 {"align", s_align_ptwo
, 0},
722 {"arch", set_cpu_arch
, 0},
726 {"lcomm", pe_lcomm
, 1},
728 {"ffloat", float_cons
, 'f'},
729 {"dfloat", float_cons
, 'd'},
730 {"tfloat", float_cons
, 'x'},
732 {"slong", signed_cons
, 4},
733 {"noopt", s_ignore
, 0},
734 {"optim", s_ignore
, 0},
735 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
736 {"code16", set_code_flag
, CODE_16BIT
},
737 {"code32", set_code_flag
, CODE_32BIT
},
738 {"code64", set_code_flag
, CODE_64BIT
},
739 {"intel_syntax", set_intel_syntax
, 1},
740 {"att_syntax", set_intel_syntax
, 0},
741 {"intel_mnemonic", set_intel_mnemonic
, 1},
742 {"att_mnemonic", set_intel_mnemonic
, 0},
743 {"allow_index_reg", set_allow_index_reg
, 1},
744 {"disallow_index_reg", set_allow_index_reg
, 0},
745 {"sse_check", set_sse_check
, 0},
746 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
747 {"largecomm", handle_large_common
, 0},
749 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
750 {"loc", dwarf2_directive_loc
, 0},
751 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
754 {"secrel32", pe_directive_secrel
, 0},
759 /* For interface with expression (). */
760 extern char *input_line_pointer
;
762 /* Hash table for instruction mnemonic lookup. */
763 static struct hash_control
*op_hash
;
765 /* Hash table for register lookup. */
766 static struct hash_control
*reg_hash
;
769 i386_align_code (fragS
*fragP
, int count
)
771 /* Various efficient no-op patterns for aligning code labels.
772 Note: Don't try to assemble the instructions in the comments.
773 0L and 0w are not legal. */
774 static const char f32_1
[] =
776 static const char f32_2
[] =
777 {0x66,0x90}; /* xchg %ax,%ax */
778 static const char f32_3
[] =
779 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
780 static const char f32_4
[] =
781 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_5
[] =
784 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
785 static const char f32_6
[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
787 static const char f32_7
[] =
788 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_8
[] =
791 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
792 static const char f32_9
[] =
793 {0x89,0xf6, /* movl %esi,%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_10
[] =
796 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_11
[] =
799 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_12
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
804 static const char f32_13
[] =
805 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_14
[] =
808 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
809 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
810 static const char f16_3
[] =
811 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
812 static const char f16_4
[] =
813 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_5
[] =
816 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
817 static const char f16_6
[] =
818 {0x89,0xf6, /* mov %si,%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_7
[] =
821 {0x8d,0x74,0x00, /* lea 0(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char f16_8
[] =
824 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char jump_31
[] =
827 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
829 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
830 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
831 static const char *const f32_patt
[] = {
832 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
833 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
835 static const char *const f16_patt
[] = {
836 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
839 static const char alt_3
[] =
841 /* nopl 0(%[re]ax) */
842 static const char alt_4
[] =
843 {0x0f,0x1f,0x40,0x00};
844 /* nopl 0(%[re]ax,%[re]ax,1) */
845 static const char alt_5
[] =
846 {0x0f,0x1f,0x44,0x00,0x00};
847 /* nopw 0(%[re]ax,%[re]ax,1) */
848 static const char alt_6
[] =
849 {0x66,0x0f,0x1f,0x44,0x00,0x00};
850 /* nopl 0L(%[re]ax) */
851 static const char alt_7
[] =
852 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_8
[] =
855 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw 0L(%[re]ax,%[re]ax,1) */
857 static const char alt_9
[] =
858 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
859 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
860 static const char alt_10
[] =
861 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_long_11
[] =
866 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_12
[] =
873 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 nopw %cs:0L(%[re]ax,%[re]ax,1) */
878 static const char alt_long_13
[] =
882 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 nopw %cs:0L(%[re]ax,%[re]ax,1) */
888 static const char alt_long_14
[] =
893 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_15
[] =
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 /* nopl 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_11
[] =
910 {0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
913 nopw 0(%[re]ax,%[re]ax,1) */
914 static const char alt_short_12
[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x66,0x0f,0x1f,0x44,0x00,0x00};
917 /* nopw 0(%[re]ax,%[re]ax,1)
919 static const char alt_short_13
[] =
920 {0x66,0x0f,0x1f,0x44,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
924 static const char alt_short_14
[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 nopl 0L(%[re]ax,%[re]ax,1) */
929 static const char alt_short_15
[] =
930 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
931 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
932 static const char *const alt_short_patt
[] = {
933 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
934 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
935 alt_short_14
, alt_short_15
937 static const char *const alt_long_patt
[] = {
938 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
939 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
940 alt_long_14
, alt_long_15
943 /* Only align for at least a positive non-zero boundary. */
944 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
947 /* We need to decide which NOP sequence to use for 32bit and
948 64bit. When -mtune= is used:
950 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
951 PROCESSOR_GENERIC32, f32_patt will be used.
952 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
953 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
954 alt_long_patt will be used.
955 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
956 PROCESSOR_AMDFAM10, alt_short_patt will be used.
958 When -mtune= isn't used, alt_long_patt will be used if
959 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
962 When -march= or .arch is used, we can't use anything beyond
963 cpu_arch_isa_flags. */
965 if (flag_code
== CODE_16BIT
)
969 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
971 /* Adjust jump offset. */
972 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
976 f16_patt
[count
- 1], count
);
980 const char *const *patt
= NULL
;
982 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
984 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
985 switch (cpu_arch_tune
)
987 case PROCESSOR_UNKNOWN
:
988 /* We use cpu_arch_isa_flags to check if we SHOULD
989 optimize for Cpu686. */
990 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
991 patt
= alt_long_patt
;
995 case PROCESSOR_PENTIUMPRO
:
996 case PROCESSOR_PENTIUM4
:
997 case PROCESSOR_NOCONA
:
999 case PROCESSOR_CORE2
:
1000 case PROCESSOR_GENERIC64
:
1001 patt
= alt_long_patt
;
1004 case PROCESSOR_ATHLON
:
1006 case PROCESSOR_AMDFAM10
:
1007 patt
= alt_short_patt
;
1009 case PROCESSOR_I386
:
1010 case PROCESSOR_I486
:
1011 case PROCESSOR_PENTIUM
:
1012 case PROCESSOR_GENERIC32
:
1019 switch (fragP
->tc_frag_data
.tune
)
1021 case PROCESSOR_UNKNOWN
:
1022 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1023 PROCESSOR_UNKNOWN. */
1027 case PROCESSOR_I386
:
1028 case PROCESSOR_I486
:
1029 case PROCESSOR_PENTIUM
:
1031 case PROCESSOR_ATHLON
:
1033 case PROCESSOR_AMDFAM10
:
1034 case PROCESSOR_GENERIC32
:
1035 /* We use cpu_arch_isa_flags to check if we CAN optimize
1037 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1038 patt
= alt_short_patt
;
1042 case PROCESSOR_PENTIUMPRO
:
1043 case PROCESSOR_PENTIUM4
:
1044 case PROCESSOR_NOCONA
:
1045 case PROCESSOR_CORE
:
1046 case PROCESSOR_CORE2
:
1047 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1048 patt
= alt_long_patt
;
1052 case PROCESSOR_GENERIC64
:
1053 patt
= alt_long_patt
;
1058 if (patt
== f32_patt
)
1060 /* If the padding is less than 15 bytes, we use the normal
1061 ones. Otherwise, we use a jump instruction and adjust
1064 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1065 patt
[count
- 1], count
);
1068 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1070 /* Adjust jump offset. */
1071 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1076 /* Maximum length of an instruction is 15 byte. If the
1077 padding is greater than 15 bytes and we don't use jump,
1078 we have to break it into smaller pieces. */
1079 int padding
= count
;
1080 while (padding
> 15)
1083 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1088 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1089 patt
[padding
- 1], padding
);
1092 fragP
->fr_var
= count
;
1096 operand_type_all_zero (const union i386_operand_type
*x
)
1098 switch (ARRAY_SIZE(x
->array
))
1107 return !x
->array
[0];
1114 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1116 switch (ARRAY_SIZE(x
->array
))
1131 operand_type_equal (const union i386_operand_type
*x
,
1132 const union i386_operand_type
*y
)
1134 switch (ARRAY_SIZE(x
->array
))
1137 if (x
->array
[2] != y
->array
[2])
1140 if (x
->array
[1] != y
->array
[1])
1143 return x
->array
[0] == y
->array
[0];
1151 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1153 switch (ARRAY_SIZE(x
->array
))
1162 return !x
->array
[0];
1169 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1171 switch (ARRAY_SIZE(x
->array
))
1186 cpu_flags_equal (const union i386_cpu_flags
*x
,
1187 const union i386_cpu_flags
*y
)
1189 switch (ARRAY_SIZE(x
->array
))
1192 if (x
->array
[2] != y
->array
[2])
1195 if (x
->array
[1] != y
->array
[1])
1198 return x
->array
[0] == y
->array
[0];
1206 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1208 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1209 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1212 static INLINE i386_cpu_flags
1213 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1215 switch (ARRAY_SIZE (x
.array
))
1218 x
.array
[2] &= y
.array
[2];
1220 x
.array
[1] &= y
.array
[1];
1222 x
.array
[0] &= y
.array
[0];
1230 static INLINE i386_cpu_flags
1231 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1233 switch (ARRAY_SIZE (x
.array
))
1236 x
.array
[2] |= y
.array
[2];
1238 x
.array
[1] |= y
.array
[1];
1240 x
.array
[0] |= y
.array
[0];
1248 #define CPU_FLAGS_ARCH_MATCH 0x1
1249 #define CPU_FLAGS_64BIT_MATCH 0x2
1250 #define CPU_FLAGS_AES_MATCH 0x4
1251 #define CPU_FLAGS_AVX_MATCH 0x8
1253 #define CPU_FLAGS_32BIT_MATCH \
1254 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1255 #define CPU_FLAGS_PERFECT_MATCH \
1256 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1258 /* Return CPU flags match bits. */
1261 cpu_flags_match (const template *t
)
1263 i386_cpu_flags x
= t
->cpu_flags
;
1264 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1266 x
.bitfield
.cpu64
= 0;
1267 x
.bitfield
.cpuno64
= 0;
1269 if (cpu_flags_all_zero (&x
))
1271 /* This instruction is available on all archs. */
1272 match
|= CPU_FLAGS_32BIT_MATCH
;
1276 /* This instruction is available only on some archs. */
1277 i386_cpu_flags cpu
= cpu_arch_flags
;
1279 cpu
.bitfield
.cpu64
= 0;
1280 cpu
.bitfield
.cpuno64
= 0;
1281 cpu
= cpu_flags_and (x
, cpu
);
1282 if (!cpu_flags_all_zero (&cpu
))
1284 if (x
.bitfield
.cpuavx
)
1286 /* We only need to check AES/SSE2AVX with AVX. */
1287 if (cpu
.bitfield
.cpuavx
)
1289 /* Check SSE2AVX. */
1290 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1292 match
|= (CPU_FLAGS_ARCH_MATCH
1293 | CPU_FLAGS_AVX_MATCH
);
1295 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1296 match
|= CPU_FLAGS_AES_MATCH
;
1300 match
|= CPU_FLAGS_ARCH_MATCH
;
1303 match
|= CPU_FLAGS_32BIT_MATCH
;
1309 static INLINE i386_operand_type
1310 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1312 switch (ARRAY_SIZE (x
.array
))
1315 x
.array
[2] &= y
.array
[2];
1317 x
.array
[1] &= y
.array
[1];
1319 x
.array
[0] &= y
.array
[0];
1327 static INLINE i386_operand_type
1328 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1330 switch (ARRAY_SIZE (x
.array
))
1333 x
.array
[2] |= y
.array
[2];
1335 x
.array
[1] |= y
.array
[1];
1337 x
.array
[0] |= y
.array
[0];
1345 static INLINE i386_operand_type
1346 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1348 switch (ARRAY_SIZE (x
.array
))
1351 x
.array
[2] ^= y
.array
[2];
1353 x
.array
[1] ^= y
.array
[1];
1355 x
.array
[0] ^= y
.array
[0];
1363 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1364 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1365 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1366 static const i386_operand_type inoutportreg
1367 = OPERAND_TYPE_INOUTPORTREG
;
1368 static const i386_operand_type reg16_inoutportreg
1369 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1370 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1371 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1372 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1373 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1374 static const i386_operand_type anydisp
1375 = OPERAND_TYPE_ANYDISP
;
1376 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1377 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1378 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1379 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1380 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1381 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1382 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1383 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1384 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1385 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1386 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1387 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1398 operand_type_check (i386_operand_type t
, enum operand_type c
)
1403 return (t
.bitfield
.reg8
1406 || t
.bitfield
.reg64
);
1409 return (t
.bitfield
.imm8
1413 || t
.bitfield
.imm32s
1414 || t
.bitfield
.imm64
);
1417 return (t
.bitfield
.disp8
1418 || t
.bitfield
.disp16
1419 || t
.bitfield
.disp32
1420 || t
.bitfield
.disp32s
1421 || t
.bitfield
.disp64
);
1424 return (t
.bitfield
.disp8
1425 || t
.bitfield
.disp16
1426 || t
.bitfield
.disp32
1427 || t
.bitfield
.disp32s
1428 || t
.bitfield
.disp64
1429 || t
.bitfield
.baseindex
);
1438 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1439 operand J for instruction template T. */
1442 match_reg_size (const template *t
, unsigned int j
)
1444 return !((i
.types
[j
].bitfield
.byte
1445 && !t
->operand_types
[j
].bitfield
.byte
)
1446 || (i
.types
[j
].bitfield
.word
1447 && !t
->operand_types
[j
].bitfield
.word
)
1448 || (i
.types
[j
].bitfield
.dword
1449 && !t
->operand_types
[j
].bitfield
.dword
)
1450 || (i
.types
[j
].bitfield
.qword
1451 && !t
->operand_types
[j
].bitfield
.qword
));
1454 /* Return 1 if there is no conflict in any size on operand J for
1455 instruction template T. */
1458 match_mem_size (const template *t
, unsigned int j
)
1460 return (match_reg_size (t
, j
)
1461 && !((i
.types
[j
].bitfield
.unspecified
1462 && !t
->operand_types
[j
].bitfield
.unspecified
)
1463 || (i
.types
[j
].bitfield
.fword
1464 && !t
->operand_types
[j
].bitfield
.fword
)
1465 || (i
.types
[j
].bitfield
.tbyte
1466 && !t
->operand_types
[j
].bitfield
.tbyte
)
1467 || (i
.types
[j
].bitfield
.xmmword
1468 && !t
->operand_types
[j
].bitfield
.xmmword
)
1469 || (i
.types
[j
].bitfield
.ymmword
1470 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1473 /* Return 1 if there is no size conflict on any operands for
1474 instruction template T. */
1477 operand_size_match (const template *t
)
1482 /* Don't check jump instructions. */
1483 if (t
->opcode_modifier
.jump
1484 || t
->opcode_modifier
.jumpbyte
1485 || t
->opcode_modifier
.jumpdword
1486 || t
->opcode_modifier
.jumpintersegment
)
1489 /* Check memory and accumulator operand size. */
1490 for (j
= 0; j
< i
.operands
; j
++)
1492 if (t
->operand_types
[j
].bitfield
.anysize
)
1495 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1501 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1509 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1512 /* Check reverse. */
1513 assert (i
.operands
== 2);
1516 for (j
= 0; j
< 2; j
++)
1518 if (t
->operand_types
[j
].bitfield
.acc
1519 && !match_reg_size (t
, j
? 0 : 1))
1525 if (i
.types
[j
].bitfield
.mem
1526 && !match_mem_size (t
, j
? 0 : 1))
1537 operand_type_match (i386_operand_type overlap
,
1538 i386_operand_type given
)
1540 i386_operand_type temp
= overlap
;
1542 temp
.bitfield
.jumpabsolute
= 0;
1543 temp
.bitfield
.unspecified
= 0;
1544 temp
.bitfield
.byte
= 0;
1545 temp
.bitfield
.word
= 0;
1546 temp
.bitfield
.dword
= 0;
1547 temp
.bitfield
.fword
= 0;
1548 temp
.bitfield
.qword
= 0;
1549 temp
.bitfield
.tbyte
= 0;
1550 temp
.bitfield
.xmmword
= 0;
1551 temp
.bitfield
.ymmword
= 0;
1552 if (operand_type_all_zero (&temp
))
1555 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1556 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1559 /* If given types g0 and g1 are registers they must be of the same type
1560 unless the expected operand type register overlap is null.
1561 Note that Acc in a template matches every size of reg. */
1564 operand_type_register_match (i386_operand_type m0
,
1565 i386_operand_type g0
,
1566 i386_operand_type t0
,
1567 i386_operand_type m1
,
1568 i386_operand_type g1
,
1569 i386_operand_type t1
)
1571 if (!operand_type_check (g0
, reg
))
1574 if (!operand_type_check (g1
, reg
))
1577 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1578 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1579 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1580 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1583 if (m0
.bitfield
.acc
)
1585 t0
.bitfield
.reg8
= 1;
1586 t0
.bitfield
.reg16
= 1;
1587 t0
.bitfield
.reg32
= 1;
1588 t0
.bitfield
.reg64
= 1;
1591 if (m1
.bitfield
.acc
)
1593 t1
.bitfield
.reg8
= 1;
1594 t1
.bitfield
.reg16
= 1;
1595 t1
.bitfield
.reg32
= 1;
1596 t1
.bitfield
.reg64
= 1;
1599 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1600 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1601 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1602 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1605 static INLINE
unsigned int
1606 mode_from_disp_size (i386_operand_type t
)
1608 if (t
.bitfield
.disp8
)
1610 else if (t
.bitfield
.disp16
1611 || t
.bitfield
.disp32
1612 || t
.bitfield
.disp32s
)
1619 fits_in_signed_byte (offsetT num
)
1621 return (num
>= -128) && (num
<= 127);
1625 fits_in_unsigned_byte (offsetT num
)
1627 return (num
& 0xff) == num
;
1631 fits_in_unsigned_word (offsetT num
)
1633 return (num
& 0xffff) == num
;
1637 fits_in_signed_word (offsetT num
)
1639 return (-32768 <= num
) && (num
<= 32767);
1643 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1648 return (!(((offsetT
) -1 << 31) & num
)
1649 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1651 } /* fits_in_signed_long() */
1654 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1659 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1661 } /* fits_in_unsigned_long() */
1664 fits_in_imm4 (offsetT num
)
1666 return (num
& 0xf) == num
;
1669 static i386_operand_type
1670 smallest_imm_type (offsetT num
)
1672 i386_operand_type t
;
1674 operand_type_set (&t
, 0);
1675 t
.bitfield
.imm64
= 1;
1677 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1679 /* This code is disabled on the 486 because all the Imm1 forms
1680 in the opcode table are slower on the i486. They're the
1681 versions with the implicitly specified single-position
1682 displacement, which has another syntax if you really want to
1684 t
.bitfield
.imm1
= 1;
1685 t
.bitfield
.imm8
= 1;
1686 t
.bitfield
.imm8s
= 1;
1687 t
.bitfield
.imm16
= 1;
1688 t
.bitfield
.imm32
= 1;
1689 t
.bitfield
.imm32s
= 1;
1691 else if (fits_in_signed_byte (num
))
1693 t
.bitfield
.imm8
= 1;
1694 t
.bitfield
.imm8s
= 1;
1695 t
.bitfield
.imm16
= 1;
1696 t
.bitfield
.imm32
= 1;
1697 t
.bitfield
.imm32s
= 1;
1699 else if (fits_in_unsigned_byte (num
))
1701 t
.bitfield
.imm8
= 1;
1702 t
.bitfield
.imm16
= 1;
1703 t
.bitfield
.imm32
= 1;
1704 t
.bitfield
.imm32s
= 1;
1706 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1708 t
.bitfield
.imm16
= 1;
1709 t
.bitfield
.imm32
= 1;
1710 t
.bitfield
.imm32s
= 1;
1712 else if (fits_in_signed_long (num
))
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_unsigned_long (num
))
1718 t
.bitfield
.imm32
= 1;
1724 offset_in_range (offsetT val
, int size
)
1730 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1731 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1732 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1734 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1739 /* If BFD64, sign extend val. */
1740 if (!use_rela_relocations
)
1741 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1742 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1744 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1746 char buf1
[40], buf2
[40];
1748 sprint_value (buf1
, val
);
1749 sprint_value (buf2
, val
& mask
);
1750 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1755 /* Returns 0 if attempting to add a prefix where one from the same
1756 class already exists, 1 if non rep/repne added, 2 if rep/repne
1759 add_prefix (unsigned int prefix
)
1764 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1765 && flag_code
== CODE_64BIT
)
1767 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1768 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1769 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1780 case CS_PREFIX_OPCODE
:
1781 case DS_PREFIX_OPCODE
:
1782 case ES_PREFIX_OPCODE
:
1783 case FS_PREFIX_OPCODE
:
1784 case GS_PREFIX_OPCODE
:
1785 case SS_PREFIX_OPCODE
:
1789 case REPNE_PREFIX_OPCODE
:
1790 case REPE_PREFIX_OPCODE
:
1793 case LOCK_PREFIX_OPCODE
:
1801 case ADDR_PREFIX_OPCODE
:
1805 case DATA_PREFIX_OPCODE
:
1809 if (i
.prefix
[q
] != 0)
1817 i
.prefix
[q
] |= prefix
;
1820 as_bad (_("same type of prefix used twice"));
1826 set_code_flag (int value
)
1829 if (flag_code
== CODE_64BIT
)
1831 cpu_arch_flags
.bitfield
.cpu64
= 1;
1832 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1836 cpu_arch_flags
.bitfield
.cpu64
= 0;
1837 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1839 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1841 as_bad (_("64bit mode not supported on this CPU."));
1843 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1845 as_bad (_("32bit mode not supported on this CPU."));
1847 stackop_size
= '\0';
1851 set_16bit_gcc_code_flag (int new_code_flag
)
1853 flag_code
= new_code_flag
;
1854 if (flag_code
!= CODE_16BIT
)
1856 cpu_arch_flags
.bitfield
.cpu64
= 0;
1857 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1858 stackop_size
= LONG_MNEM_SUFFIX
;
1862 set_intel_syntax (int syntax_flag
)
1864 /* Find out if register prefixing is specified. */
1865 int ask_naked_reg
= 0;
1868 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1870 char *string
= input_line_pointer
;
1871 int e
= get_symbol_end ();
1873 if (strcmp (string
, "prefix") == 0)
1875 else if (strcmp (string
, "noprefix") == 0)
1878 as_bad (_("bad argument to syntax directive."));
1879 *input_line_pointer
= e
;
1881 demand_empty_rest_of_line ();
1883 intel_syntax
= syntax_flag
;
1885 if (ask_naked_reg
== 0)
1886 allow_naked_reg
= (intel_syntax
1887 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1889 allow_naked_reg
= (ask_naked_reg
< 0);
1891 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1892 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1893 register_prefix
= allow_naked_reg
? "" : "%";
1897 set_intel_mnemonic (int mnemonic_flag
)
1899 intel_mnemonic
= mnemonic_flag
;
1903 set_allow_index_reg (int flag
)
1905 allow_index_reg
= flag
;
1909 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1913 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1915 char *string
= input_line_pointer
;
1916 int e
= get_symbol_end ();
1918 if (strcmp (string
, "none") == 0)
1919 sse_check
= sse_check_none
;
1920 else if (strcmp (string
, "warning") == 0)
1921 sse_check
= sse_check_warning
;
1922 else if (strcmp (string
, "error") == 0)
1923 sse_check
= sse_check_error
;
1925 as_bad (_("bad argument to sse_check directive."));
1926 *input_line_pointer
= e
;
1929 as_bad (_("missing argument for sse_check directive"));
1931 demand_empty_rest_of_line ();
1935 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1939 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1941 char *string
= input_line_pointer
;
1942 int e
= get_symbol_end ();
1944 i386_cpu_flags flags
;
1946 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1948 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1952 cpu_arch_name
= cpu_arch
[i
].name
;
1953 cpu_sub_arch_name
= NULL
;
1954 cpu_arch_flags
= cpu_arch
[i
].flags
;
1955 if (flag_code
== CODE_64BIT
)
1957 cpu_arch_flags
.bitfield
.cpu64
= 1;
1958 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1962 cpu_arch_flags
.bitfield
.cpu64
= 0;
1963 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1965 cpu_arch_isa
= cpu_arch
[i
].type
;
1966 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1967 if (!cpu_arch_tune_set
)
1969 cpu_arch_tune
= cpu_arch_isa
;
1970 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1975 flags
= cpu_flags_or (cpu_arch_flags
,
1977 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1979 if (cpu_sub_arch_name
)
1981 char *name
= cpu_sub_arch_name
;
1982 cpu_sub_arch_name
= concat (name
,
1984 (const char *) NULL
);
1988 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1989 cpu_arch_flags
= flags
;
1991 *input_line_pointer
= e
;
1992 demand_empty_rest_of_line ();
1996 if (i
>= ARRAY_SIZE (cpu_arch
))
1997 as_bad (_("no such architecture: `%s'"), string
);
1999 *input_line_pointer
= e
;
2002 as_bad (_("missing cpu architecture"));
2004 no_cond_jump_promotion
= 0;
2005 if (*input_line_pointer
== ','
2006 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2008 char *string
= ++input_line_pointer
;
2009 int e
= get_symbol_end ();
2011 if (strcmp (string
, "nojumps") == 0)
2012 no_cond_jump_promotion
= 1;
2013 else if (strcmp (string
, "jumps") == 0)
2016 as_bad (_("no such architecture modifier: `%s'"), string
);
2018 *input_line_pointer
= e
;
2021 demand_empty_rest_of_line ();
2027 if (!strcmp (default_arch
, "x86_64"))
2028 return bfd_mach_x86_64
;
2029 else if (!strcmp (default_arch
, "i386"))
2030 return bfd_mach_i386_i386
;
2032 as_fatal (_("Unknown architecture"));
2038 const char *hash_err
;
2040 /* Initialize op_hash hash table. */
2041 op_hash
= hash_new ();
2044 const template *optab
;
2045 templates
*core_optab
;
2047 /* Setup for loop. */
2049 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2050 core_optab
->start
= optab
;
2055 if (optab
->name
== NULL
2056 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2058 /* different name --> ship out current template list;
2059 add to hash table; & begin anew. */
2060 core_optab
->end
= optab
;
2061 hash_err
= hash_insert (op_hash
,
2063 (void *) core_optab
);
2066 as_fatal (_("Internal Error: Can't hash %s: %s"),
2070 if (optab
->name
== NULL
)
2072 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2073 core_optab
->start
= optab
;
2078 /* Initialize reg_hash hash table. */
2079 reg_hash
= hash_new ();
2081 const reg_entry
*regtab
;
2082 unsigned int regtab_size
= i386_regtab_size
;
2084 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2086 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2088 as_fatal (_("Internal Error: Can't hash %s: %s"),
2094 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2099 for (c
= 0; c
< 256; c
++)
2104 mnemonic_chars
[c
] = c
;
2105 register_chars
[c
] = c
;
2106 operand_chars
[c
] = c
;
2108 else if (ISLOWER (c
))
2110 mnemonic_chars
[c
] = c
;
2111 register_chars
[c
] = c
;
2112 operand_chars
[c
] = c
;
2114 else if (ISUPPER (c
))
2116 mnemonic_chars
[c
] = TOLOWER (c
);
2117 register_chars
[c
] = mnemonic_chars
[c
];
2118 operand_chars
[c
] = c
;
2121 if (ISALPHA (c
) || ISDIGIT (c
))
2122 identifier_chars
[c
] = c
;
2125 identifier_chars
[c
] = c
;
2126 operand_chars
[c
] = c
;
2131 identifier_chars
['@'] = '@';
2134 identifier_chars
['?'] = '?';
2135 operand_chars
['?'] = '?';
2137 digit_chars
['-'] = '-';
2138 mnemonic_chars
['_'] = '_';
2139 mnemonic_chars
['-'] = '-';
2140 mnemonic_chars
['.'] = '.';
2141 identifier_chars
['_'] = '_';
2142 identifier_chars
['.'] = '.';
2144 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2145 operand_chars
[(unsigned char) *p
] = *p
;
2148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2151 record_alignment (text_section
, 2);
2152 record_alignment (data_section
, 2);
2153 record_alignment (bss_section
, 2);
2157 if (flag_code
== CODE_64BIT
)
2159 x86_dwarf2_return_column
= 16;
2160 x86_cie_data_alignment
= -8;
2164 x86_dwarf2_return_column
= 8;
2165 x86_cie_data_alignment
= -4;
2170 i386_print_statistics (FILE *file
)
2172 hash_print_statistics (file
, "i386 opcode", op_hash
);
2173 hash_print_statistics (file
, "i386 register", reg_hash
);
2178 /* Debugging routines for md_assemble. */
2179 static void pte (template *);
2180 static void pt (i386_operand_type
);
2181 static void pe (expressionS
*);
2182 static void ps (symbolS
*);
2185 pi (char *line
, i386_insn
*x
)
2189 fprintf (stdout
, "%s: template ", line
);
2191 fprintf (stdout
, " address: base %s index %s scale %x\n",
2192 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2193 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2194 x
->log2_scale_factor
);
2195 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2196 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2197 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2198 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2199 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2200 (x
->rex
& REX_W
) != 0,
2201 (x
->rex
& REX_R
) != 0,
2202 (x
->rex
& REX_X
) != 0,
2203 (x
->rex
& REX_B
) != 0);
2204 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2205 x
->drex
.reg
, x
->drex
.rex
);
2206 for (i
= 0; i
< x
->operands
; i
++)
2208 fprintf (stdout
, " #%d: ", i
+ 1);
2210 fprintf (stdout
, "\n");
2211 if (x
->types
[i
].bitfield
.reg8
2212 || x
->types
[i
].bitfield
.reg16
2213 || x
->types
[i
].bitfield
.reg32
2214 || x
->types
[i
].bitfield
.reg64
2215 || x
->types
[i
].bitfield
.regmmx
2216 || x
->types
[i
].bitfield
.regxmm
2217 || x
->types
[i
].bitfield
.regymm
2218 || x
->types
[i
].bitfield
.sreg2
2219 || x
->types
[i
].bitfield
.sreg3
2220 || x
->types
[i
].bitfield
.control
2221 || x
->types
[i
].bitfield
.debug
2222 || x
->types
[i
].bitfield
.test
)
2223 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2224 if (operand_type_check (x
->types
[i
], imm
))
2226 if (operand_type_check (x
->types
[i
], disp
))
2227 pe (x
->op
[i
].disps
);
2235 fprintf (stdout
, " %d operands ", t
->operands
);
2236 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2237 if (t
->extension_opcode
!= None
)
2238 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2239 if (t
->opcode_modifier
.d
)
2240 fprintf (stdout
, "D");
2241 if (t
->opcode_modifier
.w
)
2242 fprintf (stdout
, "W");
2243 fprintf (stdout
, "\n");
2244 for (i
= 0; i
< t
->operands
; i
++)
2246 fprintf (stdout
, " #%d type ", i
+ 1);
2247 pt (t
->operand_types
[i
]);
2248 fprintf (stdout
, "\n");
2255 fprintf (stdout
, " operation %d\n", e
->X_op
);
2256 fprintf (stdout
, " add_number %ld (%lx)\n",
2257 (long) e
->X_add_number
, (long) e
->X_add_number
);
2258 if (e
->X_add_symbol
)
2260 fprintf (stdout
, " add_symbol ");
2261 ps (e
->X_add_symbol
);
2262 fprintf (stdout
, "\n");
2266 fprintf (stdout
, " op_symbol ");
2267 ps (e
->X_op_symbol
);
2268 fprintf (stdout
, "\n");
2275 fprintf (stdout
, "%s type %s%s",
2277 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2278 segment_name (S_GET_SEGMENT (s
)));
2281 static struct type_name
2283 i386_operand_type mask
;
2286 const type_names
[] =
2288 { OPERAND_TYPE_REG8
, "r8" },
2289 { OPERAND_TYPE_REG16
, "r16" },
2290 { OPERAND_TYPE_REG32
, "r32" },
2291 { OPERAND_TYPE_REG64
, "r64" },
2292 { OPERAND_TYPE_IMM8
, "i8" },
2293 { OPERAND_TYPE_IMM8
, "i8s" },
2294 { OPERAND_TYPE_IMM16
, "i16" },
2295 { OPERAND_TYPE_IMM32
, "i32" },
2296 { OPERAND_TYPE_IMM32S
, "i32s" },
2297 { OPERAND_TYPE_IMM64
, "i64" },
2298 { OPERAND_TYPE_IMM1
, "i1" },
2299 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2300 { OPERAND_TYPE_DISP8
, "d8" },
2301 { OPERAND_TYPE_DISP16
, "d16" },
2302 { OPERAND_TYPE_DISP32
, "d32" },
2303 { OPERAND_TYPE_DISP32S
, "d32s" },
2304 { OPERAND_TYPE_DISP64
, "d64" },
2305 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2306 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2307 { OPERAND_TYPE_CONTROL
, "control reg" },
2308 { OPERAND_TYPE_TEST
, "test reg" },
2309 { OPERAND_TYPE_DEBUG
, "debug reg" },
2310 { OPERAND_TYPE_FLOATREG
, "FReg" },
2311 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2312 { OPERAND_TYPE_SREG2
, "SReg2" },
2313 { OPERAND_TYPE_SREG3
, "SReg3" },
2314 { OPERAND_TYPE_ACC
, "Acc" },
2315 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2316 { OPERAND_TYPE_REGMMX
, "rMMX" },
2317 { OPERAND_TYPE_REGXMM
, "rXMM" },
2318 { OPERAND_TYPE_ESSEG
, "es" },
2319 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2323 pt (i386_operand_type t
)
2326 i386_operand_type a
;
2328 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2330 a
= operand_type_and (t
, type_names
[j
].mask
);
2331 if (!UINTS_ALL_ZERO (a
))
2332 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2337 #endif /* DEBUG386 */
2339 static bfd_reloc_code_real_type
2340 reloc (unsigned int size
,
2343 bfd_reloc_code_real_type other
)
2345 if (other
!= NO_RELOC
)
2347 reloc_howto_type
*reloc
;
2352 case BFD_RELOC_X86_64_GOT32
:
2353 return BFD_RELOC_X86_64_GOT64
;
2355 case BFD_RELOC_X86_64_PLTOFF64
:
2356 return BFD_RELOC_X86_64_PLTOFF64
;
2358 case BFD_RELOC_X86_64_GOTPC32
:
2359 other
= BFD_RELOC_X86_64_GOTPC64
;
2361 case BFD_RELOC_X86_64_GOTPCREL
:
2362 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2364 case BFD_RELOC_X86_64_TPOFF32
:
2365 other
= BFD_RELOC_X86_64_TPOFF64
;
2367 case BFD_RELOC_X86_64_DTPOFF32
:
2368 other
= BFD_RELOC_X86_64_DTPOFF64
;
2374 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2375 if (size
== 4 && flag_code
!= CODE_64BIT
)
2378 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2380 as_bad (_("unknown relocation (%u)"), other
);
2381 else if (size
!= bfd_get_reloc_size (reloc
))
2382 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2383 bfd_get_reloc_size (reloc
),
2385 else if (pcrel
&& !reloc
->pc_relative
)
2386 as_bad (_("non-pc-relative relocation for pc-relative field"));
2387 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2389 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2391 as_bad (_("relocated field and relocation type differ in signedness"));
2400 as_bad (_("there are no unsigned pc-relative relocations"));
2403 case 1: return BFD_RELOC_8_PCREL
;
2404 case 2: return BFD_RELOC_16_PCREL
;
2405 case 4: return BFD_RELOC_32_PCREL
;
2406 case 8: return BFD_RELOC_64_PCREL
;
2408 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2415 case 4: return BFD_RELOC_X86_64_32S
;
2420 case 1: return BFD_RELOC_8
;
2421 case 2: return BFD_RELOC_16
;
2422 case 4: return BFD_RELOC_32
;
2423 case 8: return BFD_RELOC_64
;
2425 as_bad (_("cannot do %s %u byte relocation"),
2426 sign
> 0 ? "signed" : "unsigned", size
);
2430 return BFD_RELOC_NONE
;
2433 /* Here we decide which fixups can be adjusted to make them relative to
2434 the beginning of the section instead of the symbol. Basically we need
2435 to make sure that the dynamic relocations are done correctly, so in
2436 some cases we force the original symbol to be used. */
2439 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2445 /* Don't adjust pc-relative references to merge sections in 64-bit
2447 if (use_rela_relocations
2448 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2452 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2453 and changed later by validate_fix. */
2454 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2455 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2458 /* adjust_reloc_syms doesn't know about the GOT. */
2459 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2460 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2461 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2485 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2486 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2493 intel_float_operand (const char *mnemonic
)
2495 /* Note that the value returned is meaningful only for opcodes with (memory)
2496 operands, hence the code here is free to improperly handle opcodes that
2497 have no operands (for better performance and smaller code). */
2499 if (mnemonic
[0] != 'f')
2500 return 0; /* non-math */
2502 switch (mnemonic
[1])
2504 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2505 the fs segment override prefix not currently handled because no
2506 call path can make opcodes without operands get here */
2508 return 2 /* integer op */;
2510 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2511 return 3; /* fldcw/fldenv */
2514 if (mnemonic
[2] != 'o' /* fnop */)
2515 return 3; /* non-waiting control op */
2518 if (mnemonic
[2] == 's')
2519 return 3; /* frstor/frstpm */
2522 if (mnemonic
[2] == 'a')
2523 return 3; /* fsave */
2524 if (mnemonic
[2] == 't')
2526 switch (mnemonic
[3])
2528 case 'c': /* fstcw */
2529 case 'd': /* fstdw */
2530 case 'e': /* fstenv */
2531 case 's': /* fsts[gw] */
2537 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2538 return 0; /* fxsave/fxrstor are not really math ops */
2545 /* Build the VEX prefix. */
2548 build_vex_prefix (const template *t
)
2550 unsigned int register_specifier
;
2551 unsigned int implied_prefix
;
2552 unsigned int vector_length
;
2554 /* Check register specifier. */
2555 if (i
.vex
.register_specifier
)
2557 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2558 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2559 register_specifier
+= 8;
2560 register_specifier
= ~register_specifier
& 0xf;
2563 register_specifier
= 0xf;
2565 /* Use 2-byte VEX prefix by swappping destination and source
2568 && i
.operands
== i
.reg_operands
2569 && i
.tm
.opcode_modifier
.vex0f
2570 && i
.tm
.opcode_modifier
.s
2573 unsigned int xchg
= i
.operands
- 1;
2574 union i386_op temp_op
;
2575 i386_operand_type temp_type
;
2577 temp_type
= i
.types
[xchg
];
2578 i
.types
[xchg
] = i
.types
[0];
2579 i
.types
[0] = temp_type
;
2580 temp_op
= i
.op
[xchg
];
2581 i
.op
[xchg
] = i
.op
[0];
2584 assert (i
.rm
.mode
== 3);
2588 i
.rm
.regmem
= i
.rm
.reg
;
2591 /* Use the next insn. */
2595 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2597 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2602 case DATA_PREFIX_OPCODE
:
2605 case REPE_PREFIX_OPCODE
:
2608 case REPNE_PREFIX_OPCODE
:
2615 /* Use 2-byte VEX prefix if possible. */
2616 if (i
.tm
.opcode_modifier
.vex0f
2617 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2619 /* 2-byte VEX prefix. */
2623 i
.vex
.bytes
[0] = 0xc5;
2625 /* Check the REX.R bit. */
2626 r
= (i
.rex
& REX_R
) ? 0 : 1;
2627 i
.vex
.bytes
[1] = (r
<< 7
2628 | register_specifier
<< 3
2629 | vector_length
<< 2
2634 /* 3-byte VEX prefix. */
2637 if (i
.tm
.opcode_modifier
.vex0f
)
2639 else if (i
.tm
.opcode_modifier
.vex0f38
)
2641 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2647 i
.vex
.bytes
[0] = 0xc4;
2649 /* The high 3 bits of the second VEX byte are 1's compliment
2650 of RXB bits from REX. */
2651 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2653 /* Check the REX.W bit. */
2654 w
= (i
.rex
& REX_W
) ? 1 : 0;
2655 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2660 if (i
.tm
.opcode_modifier
.vexw1
)
2664 i
.vex
.bytes
[2] = (w
<< 7
2665 | register_specifier
<< 3
2666 | vector_length
<< 2
2672 process_immext (void)
2676 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2678 /* SSE3 Instructions have the fixed operands with an opcode
2679 suffix which is coded in the same place as an 8-bit immediate
2680 field would be. Here we check those operands and remove them
2684 for (x
= 0; x
< i
.operands
; x
++)
2685 if (i
.op
[x
].regs
->reg_num
!= x
)
2686 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2687 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2693 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2694 which is coded in the same place as an 8-bit immediate field
2695 would be. Here we fake an 8-bit immediate operand from the
2696 opcode suffix stored in tm.extension_opcode.
2698 SSE5 and AVX instructions also use this encoding, for some of
2699 3 argument instructions. */
2701 assert (i
.imm_operands
== 0
2703 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2705 || (i
.tm
.opcode_modifier
.vex
2706 && i
.operands
<= 4)));
2708 exp
= &im_expressions
[i
.imm_operands
++];
2709 i
.op
[i
.operands
].imms
= exp
;
2710 i
.types
[i
.operands
] = imm8
;
2712 exp
->X_op
= O_constant
;
2713 exp
->X_add_number
= i
.tm
.extension_opcode
;
2714 i
.tm
.extension_opcode
= None
;
2717 /* This is the guts of the machine-dependent assembler. LINE points to a
2718 machine dependent instruction. This function is supposed to emit
2719 the frags/bytes it assembles to. */
2722 md_assemble (char *line
)
2725 char mnemonic
[MAX_MNEM_SIZE
];
2728 /* Initialize globals. */
2729 memset (&i
, '\0', sizeof (i
));
2730 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2731 i
.reloc
[j
] = NO_RELOC
;
2732 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2733 memset (im_expressions
, '\0', sizeof (im_expressions
));
2734 save_stack_p
= save_stack
;
2736 /* First parse an instruction mnemonic & call i386_operand for the operands.
2737 We assume that the scrubber has arranged it so that line[0] is the valid
2738 start of a (possibly prefixed) mnemonic. */
2740 line
= parse_insn (line
, mnemonic
);
2744 line
= parse_operands (line
, mnemonic
);
2748 /* Now we've parsed the mnemonic into a set of templates, and have the
2749 operands at hand. */
2751 /* All intel opcodes have reversed operands except for "bound" and
2752 "enter". We also don't reverse intersegment "jmp" and "call"
2753 instructions with 2 immediate operands so that the immediate segment
2754 precedes the offset, as it does when in AT&T mode. */
2757 && (strcmp (mnemonic
, "bound") != 0)
2758 && (strcmp (mnemonic
, "invlpga") != 0)
2759 && !(operand_type_check (i
.types
[0], imm
)
2760 && operand_type_check (i
.types
[1], imm
)))
2763 /* The order of the immediates should be reversed
2764 for 2 immediates extrq and insertq instructions */
2765 if (i
.imm_operands
== 2
2766 && (strcmp (mnemonic
, "extrq") == 0
2767 || strcmp (mnemonic
, "insertq") == 0))
2768 swap_2_operands (0, 1);
2773 /* Don't optimize displacement for movabs since it only takes 64bit
2776 && (flag_code
!= CODE_64BIT
2777 || strcmp (mnemonic
, "movabs") != 0))
2780 /* Next, we find a template that matches the given insn,
2781 making sure the overlap of the given operands types is consistent
2782 with the template operand types. */
2784 if (!(t
= match_template ()))
2787 if (sse_check
!= sse_check_none
2788 && !i
.tm
.opcode_modifier
.noavx
2789 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2790 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2791 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2792 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2793 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2794 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2796 (sse_check
== sse_check_warning
2798 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2801 /* Zap movzx and movsx suffix. The suffix has been set from
2802 "word ptr" or "byte ptr" on the source operand in Intel syntax
2803 or extracted from mnemonic in AT&T syntax. But we'll use
2804 the destination register to choose the suffix for encoding. */
2805 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2807 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2808 there is no suffix, the default will be byte extension. */
2809 if (i
.reg_operands
!= 2
2812 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2817 if (i
.tm
.opcode_modifier
.fwait
)
2818 if (!add_prefix (FWAIT_OPCODE
))
2821 /* Check string instruction segment overrides. */
2822 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2824 if (!check_string ())
2826 i
.disp_operands
= 0;
2829 if (!process_suffix ())
2832 /* Make still unresolved immediate matches conform to size of immediate
2833 given in i.suffix. */
2834 if (!finalize_imm ())
2837 if (i
.types
[0].bitfield
.imm1
)
2838 i
.imm_operands
= 0; /* kludge for shift insns. */
2840 for (j
= 0; j
< 3; j
++)
2841 if (i
.types
[j
].bitfield
.inoutportreg
2842 || i
.types
[j
].bitfield
.shiftcount
2843 || i
.types
[j
].bitfield
.acc
2844 || i
.types
[j
].bitfield
.floatacc
)
2847 /* ImmExt should be processed after SSE2AVX. */
2848 if (!i
.tm
.opcode_modifier
.sse2avx
2849 && i
.tm
.opcode_modifier
.immext
)
2852 /* For insns with operands there are more diddles to do to the opcode. */
2855 if (!process_operands ())
2858 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2860 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2861 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2864 if (i
.tm
.opcode_modifier
.vex
)
2865 build_vex_prefix (t
);
2867 /* Handle conversion of 'int $3' --> special int3 insn. */
2868 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2870 i
.tm
.base_opcode
= INT3_OPCODE
;
2874 if ((i
.tm
.opcode_modifier
.jump
2875 || i
.tm
.opcode_modifier
.jumpbyte
2876 || i
.tm
.opcode_modifier
.jumpdword
)
2877 && i
.op
[0].disps
->X_op
== O_constant
)
2879 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2880 the absolute address given by the constant. Since ix86 jumps and
2881 calls are pc relative, we need to generate a reloc. */
2882 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2883 i
.op
[0].disps
->X_op
= O_symbol
;
2886 if (i
.tm
.opcode_modifier
.rex64
)
2889 /* For 8 bit registers we need an empty rex prefix. Also if the
2890 instruction already has a prefix, we need to convert old
2891 registers to new ones. */
2893 if ((i
.types
[0].bitfield
.reg8
2894 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2895 || (i
.types
[1].bitfield
.reg8
2896 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2897 || ((i
.types
[0].bitfield
.reg8
2898 || i
.types
[1].bitfield
.reg8
)
2903 i
.rex
|= REX_OPCODE
;
2904 for (x
= 0; x
< 2; x
++)
2906 /* Look for 8 bit operand that uses old registers. */
2907 if (i
.types
[x
].bitfield
.reg8
2908 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2910 /* In case it is "hi" register, give up. */
2911 if (i
.op
[x
].regs
->reg_num
> 3)
2912 as_bad (_("can't encode register '%s%s' in an "
2913 "instruction requiring REX prefix."),
2914 register_prefix
, i
.op
[x
].regs
->reg_name
);
2916 /* Otherwise it is equivalent to the extended register.
2917 Since the encoding doesn't change this is merely
2918 cosmetic cleanup for debug output. */
2920 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2925 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2927 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2932 else if (i
.rex
!= 0)
2933 add_prefix (REX_OPCODE
| i
.rex
);
2935 /* We are ready to output the insn. */
2940 parse_insn (char *line
, char *mnemonic
)
2943 char *token_start
= l
;
2949 /* Non-zero if we found a prefix only acceptable with string insns. */
2950 const char *expecting_string_instruction
= NULL
;
2955 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2960 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2962 as_bad (_("no such instruction: `%s'"), token_start
);
2967 if (!is_space_char (*l
)
2968 && *l
!= END_OF_INSN
2970 || (*l
!= PREFIX_SEPARATOR
2973 as_bad (_("invalid character %s in mnemonic"),
2974 output_invalid (*l
));
2977 if (token_start
== l
)
2979 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2980 as_bad (_("expecting prefix; got nothing"));
2982 as_bad (_("expecting mnemonic; got nothing"));
2986 /* Look up instruction (or prefix) via hash table. */
2987 current_templates
= hash_find (op_hash
, mnemonic
);
2989 if (*l
!= END_OF_INSN
2990 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2991 && current_templates
2992 && current_templates
->start
->opcode_modifier
.isprefix
)
2994 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2996 as_bad ((flag_code
!= CODE_64BIT
2997 ? _("`%s' is only supported in 64-bit mode")
2998 : _("`%s' is not supported in 64-bit mode")),
2999 current_templates
->start
->name
);
3002 /* If we are in 16-bit mode, do not allow addr16 or data16.
3003 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3004 if ((current_templates
->start
->opcode_modifier
.size16
3005 || current_templates
->start
->opcode_modifier
.size32
)
3006 && flag_code
!= CODE_64BIT
3007 && (current_templates
->start
->opcode_modifier
.size32
3008 ^ (flag_code
== CODE_16BIT
)))
3010 as_bad (_("redundant %s prefix"),
3011 current_templates
->start
->name
);
3014 /* Add prefix, checking for repeated prefixes. */
3015 switch (add_prefix (current_templates
->start
->base_opcode
))
3020 expecting_string_instruction
= current_templates
->start
->name
;
3023 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3030 if (!current_templates
)
3032 /* Check if we should swap operand in encoding. */
3033 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3039 current_templates
= hash_find (op_hash
, mnemonic
);
3042 if (!current_templates
)
3045 /* See if we can get a match by trimming off a suffix. */
3048 case WORD_MNEM_SUFFIX
:
3049 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3050 i
.suffix
= SHORT_MNEM_SUFFIX
;
3052 case BYTE_MNEM_SUFFIX
:
3053 case QWORD_MNEM_SUFFIX
:
3054 i
.suffix
= mnem_p
[-1];
3056 current_templates
= hash_find (op_hash
, mnemonic
);
3058 case SHORT_MNEM_SUFFIX
:
3059 case LONG_MNEM_SUFFIX
:
3062 i
.suffix
= mnem_p
[-1];
3064 current_templates
= hash_find (op_hash
, mnemonic
);
3072 if (intel_float_operand (mnemonic
) == 1)
3073 i
.suffix
= SHORT_MNEM_SUFFIX
;
3075 i
.suffix
= LONG_MNEM_SUFFIX
;
3077 current_templates
= hash_find (op_hash
, mnemonic
);
3081 if (!current_templates
)
3083 as_bad (_("no such instruction: `%s'"), token_start
);
3088 if (current_templates
->start
->opcode_modifier
.jump
3089 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3091 /* Check for a branch hint. We allow ",pt" and ",pn" for
3092 predict taken and predict not taken respectively.
3093 I'm not sure that branch hints actually do anything on loop
3094 and jcxz insns (JumpByte) for current Pentium4 chips. They
3095 may work in the future and it doesn't hurt to accept them
3097 if (l
[0] == ',' && l
[1] == 'p')
3101 if (!add_prefix (DS_PREFIX_OPCODE
))
3105 else if (l
[2] == 'n')
3107 if (!add_prefix (CS_PREFIX_OPCODE
))
3113 /* Any other comma loses. */
3116 as_bad (_("invalid character %s in mnemonic"),
3117 output_invalid (*l
));
3121 /* Check if instruction is supported on specified architecture. */
3123 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3125 supported
|= cpu_flags_match (t
);
3126 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3130 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3132 as_bad (flag_code
== CODE_64BIT
3133 ? _("`%s' is not supported in 64-bit mode")
3134 : _("`%s' is only supported in 64-bit mode"),
3135 current_templates
->start
->name
);
3138 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3140 as_bad (_("`%s' is not supported on `%s%s'"),
3141 current_templates
->start
->name
, cpu_arch_name
,
3142 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3147 if (!cpu_arch_flags
.bitfield
.cpui386
3148 && (flag_code
!= CODE_16BIT
))
3150 as_warn (_("use .code16 to ensure correct addressing mode"));
3153 /* Check for rep/repne without a string instruction. */
3154 if (expecting_string_instruction
)
3156 static templates override
;
3158 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3159 if (t
->opcode_modifier
.isstring
)
3161 if (t
>= current_templates
->end
)
3163 as_bad (_("expecting string instruction after `%s'"),
3164 expecting_string_instruction
);
3167 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3168 if (!t
->opcode_modifier
.isstring
)
3171 current_templates
= &override
;
3178 parse_operands (char *l
, const char *mnemonic
)
3182 /* 1 if operand is pending after ','. */
3183 unsigned int expecting_operand
= 0;
3185 /* Non-zero if operand parens not balanced. */
3186 unsigned int paren_not_balanced
;
3188 while (*l
!= END_OF_INSN
)
3190 /* Skip optional white space before operand. */
3191 if (is_space_char (*l
))
3193 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3195 as_bad (_("invalid character %s before operand %d"),
3196 output_invalid (*l
),
3200 token_start
= l
; /* after white space */
3201 paren_not_balanced
= 0;
3202 while (paren_not_balanced
|| *l
!= ',')
3204 if (*l
== END_OF_INSN
)
3206 if (paren_not_balanced
)
3209 as_bad (_("unbalanced parenthesis in operand %d."),
3212 as_bad (_("unbalanced brackets in operand %d."),
3217 break; /* we are done */
3219 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3221 as_bad (_("invalid character %s in operand %d"),
3222 output_invalid (*l
),
3229 ++paren_not_balanced
;
3231 --paren_not_balanced
;
3236 ++paren_not_balanced
;
3238 --paren_not_balanced
;
3242 if (l
!= token_start
)
3243 { /* Yes, we've read in another operand. */
3244 unsigned int operand_ok
;
3245 this_operand
= i
.operands
++;
3246 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3247 if (i
.operands
> MAX_OPERANDS
)
3249 as_bad (_("spurious operands; (%d operands/instruction max)"),
3253 /* Now parse operand adding info to 'i' as we go along. */
3254 END_STRING_AND_SAVE (l
);
3258 i386_intel_operand (token_start
,
3259 intel_float_operand (mnemonic
));
3261 operand_ok
= i386_att_operand (token_start
);
3263 RESTORE_END_STRING (l
);
3269 if (expecting_operand
)
3271 expecting_operand_after_comma
:
3272 as_bad (_("expecting operand after ','; got nothing"));
3277 as_bad (_("expecting operand before ','; got nothing"));
3282 /* Now *l must be either ',' or END_OF_INSN. */
3285 if (*++l
== END_OF_INSN
)
3287 /* Just skip it, if it's \n complain. */
3288 goto expecting_operand_after_comma
;
3290 expecting_operand
= 1;
3297 swap_2_operands (int xchg1
, int xchg2
)
3299 union i386_op temp_op
;
3300 i386_operand_type temp_type
;
3301 enum bfd_reloc_code_real temp_reloc
;
3303 temp_type
= i
.types
[xchg2
];
3304 i
.types
[xchg2
] = i
.types
[xchg1
];
3305 i
.types
[xchg1
] = temp_type
;
3306 temp_op
= i
.op
[xchg2
];
3307 i
.op
[xchg2
] = i
.op
[xchg1
];
3308 i
.op
[xchg1
] = temp_op
;
3309 temp_reloc
= i
.reloc
[xchg2
];
3310 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3311 i
.reloc
[xchg1
] = temp_reloc
;
3315 swap_operands (void)
3321 swap_2_operands (1, i
.operands
- 2);
3324 swap_2_operands (0, i
.operands
- 1);
3330 if (i
.mem_operands
== 2)
3332 const seg_entry
*temp_seg
;
3333 temp_seg
= i
.seg
[0];
3334 i
.seg
[0] = i
.seg
[1];
3335 i
.seg
[1] = temp_seg
;
3339 /* Try to ensure constant immediates are represented in the smallest
3344 char guess_suffix
= 0;
3348 guess_suffix
= i
.suffix
;
3349 else if (i
.reg_operands
)
3351 /* Figure out a suffix from the last register operand specified.
3352 We can't do this properly yet, ie. excluding InOutPortReg,
3353 but the following works for instructions with immediates.
3354 In any case, we can't set i.suffix yet. */
3355 for (op
= i
.operands
; --op
>= 0;)
3356 if (i
.types
[op
].bitfield
.reg8
)
3358 guess_suffix
= BYTE_MNEM_SUFFIX
;
3361 else if (i
.types
[op
].bitfield
.reg16
)
3363 guess_suffix
= WORD_MNEM_SUFFIX
;
3366 else if (i
.types
[op
].bitfield
.reg32
)
3368 guess_suffix
= LONG_MNEM_SUFFIX
;
3371 else if (i
.types
[op
].bitfield
.reg64
)
3373 guess_suffix
= QWORD_MNEM_SUFFIX
;
3377 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3378 guess_suffix
= WORD_MNEM_SUFFIX
;
3380 for (op
= i
.operands
; --op
>= 0;)
3381 if (operand_type_check (i
.types
[op
], imm
))
3383 switch (i
.op
[op
].imms
->X_op
)
3386 /* If a suffix is given, this operand may be shortened. */
3387 switch (guess_suffix
)
3389 case LONG_MNEM_SUFFIX
:
3390 i
.types
[op
].bitfield
.imm32
= 1;
3391 i
.types
[op
].bitfield
.imm64
= 1;
3393 case WORD_MNEM_SUFFIX
:
3394 i
.types
[op
].bitfield
.imm16
= 1;
3395 i
.types
[op
].bitfield
.imm32
= 1;
3396 i
.types
[op
].bitfield
.imm32s
= 1;
3397 i
.types
[op
].bitfield
.imm64
= 1;
3399 case BYTE_MNEM_SUFFIX
:
3400 i
.types
[op
].bitfield
.imm8
= 1;
3401 i
.types
[op
].bitfield
.imm8s
= 1;
3402 i
.types
[op
].bitfield
.imm16
= 1;
3403 i
.types
[op
].bitfield
.imm32
= 1;
3404 i
.types
[op
].bitfield
.imm32s
= 1;
3405 i
.types
[op
].bitfield
.imm64
= 1;
3409 /* If this operand is at most 16 bits, convert it
3410 to a signed 16 bit number before trying to see
3411 whether it will fit in an even smaller size.
3412 This allows a 16-bit operand such as $0xffe0 to
3413 be recognised as within Imm8S range. */
3414 if ((i
.types
[op
].bitfield
.imm16
)
3415 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3417 i
.op
[op
].imms
->X_add_number
=
3418 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3420 if ((i
.types
[op
].bitfield
.imm32
)
3421 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3424 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3425 ^ ((offsetT
) 1 << 31))
3426 - ((offsetT
) 1 << 31));
3429 = operand_type_or (i
.types
[op
],
3430 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3432 /* We must avoid matching of Imm32 templates when 64bit
3433 only immediate is available. */
3434 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3435 i
.types
[op
].bitfield
.imm32
= 0;
3442 /* Symbols and expressions. */
3444 /* Convert symbolic operand to proper sizes for matching, but don't
3445 prevent matching a set of insns that only supports sizes other
3446 than those matching the insn suffix. */
3448 i386_operand_type mask
, allowed
;
3451 operand_type_set (&mask
, 0);
3452 operand_type_set (&allowed
, 0);
3454 for (t
= current_templates
->start
;
3455 t
< current_templates
->end
;
3457 allowed
= operand_type_or (allowed
,
3458 t
->operand_types
[op
]);
3459 switch (guess_suffix
)
3461 case QWORD_MNEM_SUFFIX
:
3462 mask
.bitfield
.imm64
= 1;
3463 mask
.bitfield
.imm32s
= 1;
3465 case LONG_MNEM_SUFFIX
:
3466 mask
.bitfield
.imm32
= 1;
3468 case WORD_MNEM_SUFFIX
:
3469 mask
.bitfield
.imm16
= 1;
3471 case BYTE_MNEM_SUFFIX
:
3472 mask
.bitfield
.imm8
= 1;
3477 allowed
= operand_type_and (mask
, allowed
);
3478 if (!operand_type_all_zero (&allowed
))
3479 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3486 /* Try to use the smallest displacement type too. */
3488 optimize_disp (void)
3492 for (op
= i
.operands
; --op
>= 0;)
3493 if (operand_type_check (i
.types
[op
], disp
))
3495 if (i
.op
[op
].disps
->X_op
== O_constant
)
3497 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3499 if (i
.types
[op
].bitfield
.disp16
3500 && (disp
& ~(offsetT
) 0xffff) == 0)
3502 /* If this operand is at most 16 bits, convert
3503 to a signed 16 bit number and don't use 64bit
3505 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3506 i
.types
[op
].bitfield
.disp64
= 0;
3508 if (i
.types
[op
].bitfield
.disp32
3509 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3511 /* If this operand is at most 32 bits, convert
3512 to a signed 32 bit number and don't use 64bit
3514 disp
&= (((offsetT
) 2 << 31) - 1);
3515 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3516 i
.types
[op
].bitfield
.disp64
= 0;
3518 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3520 i
.types
[op
].bitfield
.disp8
= 0;
3521 i
.types
[op
].bitfield
.disp16
= 0;
3522 i
.types
[op
].bitfield
.disp32
= 0;
3523 i
.types
[op
].bitfield
.disp32s
= 0;
3524 i
.types
[op
].bitfield
.disp64
= 0;
3528 else if (flag_code
== CODE_64BIT
)
3530 if (fits_in_signed_long (disp
))
3532 i
.types
[op
].bitfield
.disp64
= 0;
3533 i
.types
[op
].bitfield
.disp32s
= 1;
3535 if (fits_in_unsigned_long (disp
))
3536 i
.types
[op
].bitfield
.disp32
= 1;
3538 if ((i
.types
[op
].bitfield
.disp32
3539 || i
.types
[op
].bitfield
.disp32s
3540 || i
.types
[op
].bitfield
.disp16
)
3541 && fits_in_signed_byte (disp
))
3542 i
.types
[op
].bitfield
.disp8
= 1;
3544 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3545 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3547 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3548 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3549 i
.types
[op
].bitfield
.disp8
= 0;
3550 i
.types
[op
].bitfield
.disp16
= 0;
3551 i
.types
[op
].bitfield
.disp32
= 0;
3552 i
.types
[op
].bitfield
.disp32s
= 0;
3553 i
.types
[op
].bitfield
.disp64
= 0;
3556 /* We only support 64bit displacement on constants. */
3557 i
.types
[op
].bitfield
.disp64
= 0;
3561 /* Check if operands are valid for the instrucrtion. Update VEX
3565 VEX_check_operands (const template *t
)
3567 if (!t
->opcode_modifier
.vex
)
3570 /* Only check VEX_Imm4, which must be the first operand. */
3571 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3573 if (i
.op
[0].imms
->X_op
!= O_constant
3574 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3577 /* Turn off Imm8 so that update_imm won't complain. */
3578 i
.types
[0] = vex_imm4
;
3584 static const template *
3585 match_template (void)
3587 /* Points to template once we've found it. */
3589 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3590 i386_operand_type overlap4
;
3591 unsigned int found_reverse_match
;
3592 i386_opcode_modifier suffix_check
;
3593 i386_operand_type operand_types
[MAX_OPERANDS
];
3594 int addr_prefix_disp
;
3596 unsigned int found_cpu_match
;
3597 unsigned int check_register
;
3599 #if MAX_OPERANDS != 5
3600 # error "MAX_OPERANDS must be 5."
3603 found_reverse_match
= 0;
3604 addr_prefix_disp
= -1;
3606 memset (&suffix_check
, 0, sizeof (suffix_check
));
3607 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3608 suffix_check
.no_bsuf
= 1;
3609 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3610 suffix_check
.no_wsuf
= 1;
3611 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3612 suffix_check
.no_ssuf
= 1;
3613 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3614 suffix_check
.no_lsuf
= 1;
3615 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3616 suffix_check
.no_qsuf
= 1;
3617 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3618 suffix_check
.no_ldsuf
= 1;
3620 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3622 addr_prefix_disp
= -1;
3624 /* Must have right number of operands. */
3625 if (i
.operands
!= t
->operands
)
3628 /* Check processor support. */
3629 found_cpu_match
= (cpu_flags_match (t
)
3630 == CPU_FLAGS_PERFECT_MATCH
);
3631 if (!found_cpu_match
)
3634 /* Check old gcc support. */
3635 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3638 /* Check AT&T mnemonic. */
3639 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3642 /* Check AT&T syntax Intel syntax. */
3643 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3644 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3647 /* Check the suffix, except for some instructions in intel mode. */
3648 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3649 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3650 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3651 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3652 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3653 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3654 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3657 if (!operand_size_match (t
))
3660 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3661 operand_types
[j
] = t
->operand_types
[j
];
3663 /* In general, don't allow 64-bit operands in 32-bit mode. */
3664 if (i
.suffix
== QWORD_MNEM_SUFFIX
3665 && flag_code
!= CODE_64BIT
3667 ? (!t
->opcode_modifier
.ignoresize
3668 && !intel_float_operand (t
->name
))
3669 : intel_float_operand (t
->name
) != 2)
3670 && ((!operand_types
[0].bitfield
.regmmx
3671 && !operand_types
[0].bitfield
.regxmm
3672 && !operand_types
[0].bitfield
.regymm
)
3673 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3674 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3675 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3676 && (t
->base_opcode
!= 0x0fc7
3677 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3680 /* In general, don't allow 32-bit operands on pre-386. */
3681 else if (i
.suffix
== LONG_MNEM_SUFFIX
3682 && !cpu_arch_flags
.bitfield
.cpui386
3684 ? (!t
->opcode_modifier
.ignoresize
3685 && !intel_float_operand (t
->name
))
3686 : intel_float_operand (t
->name
) != 2)
3687 && ((!operand_types
[0].bitfield
.regmmx
3688 && !operand_types
[0].bitfield
.regxmm
)
3689 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3690 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3693 /* Do not verify operands when there are none. */
3697 /* We've found a match; break out of loop. */
3701 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3702 into Disp32/Disp16/Disp32 operand. */
3703 if (i
.prefix
[ADDR_PREFIX
] != 0)
3705 /* There should be only one Disp operand. */
3709 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3711 if (operand_types
[j
].bitfield
.disp16
)
3713 addr_prefix_disp
= j
;
3714 operand_types
[j
].bitfield
.disp32
= 1;
3715 operand_types
[j
].bitfield
.disp16
= 0;
3721 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3723 if (operand_types
[j
].bitfield
.disp32
)
3725 addr_prefix_disp
= j
;
3726 operand_types
[j
].bitfield
.disp32
= 0;
3727 operand_types
[j
].bitfield
.disp16
= 1;
3733 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3735 if (operand_types
[j
].bitfield
.disp64
)
3737 addr_prefix_disp
= j
;
3738 operand_types
[j
].bitfield
.disp64
= 0;
3739 operand_types
[j
].bitfield
.disp32
= 1;
3747 /* We check register size only if size of operands can be
3748 encoded the canonical way. */
3749 check_register
= t
->opcode_modifier
.w
;
3750 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3751 switch (t
->operands
)
3754 if (!operand_type_match (overlap0
, i
.types
[0]))
3758 /* xchg %eax, %eax is a special case. It is an aliase for nop
3759 only in 32bit mode and we can use opcode 0x90. In 64bit
3760 mode, we can't use 0x90 for xchg %eax, %eax since it should
3761 zero-extend %eax to %rax. */
3762 if (flag_code
== CODE_64BIT
3763 && t
->base_opcode
== 0x90
3764 && operand_type_equal (&i
.types
[0], &acc32
)
3765 && operand_type_equal (&i
.types
[1], &acc32
))
3769 /* If we swap operand in encoding, we either match
3770 the next one or reverse direction of operands. */
3771 if (t
->opcode_modifier
.s
)
3773 else if (t
->opcode_modifier
.d
)
3778 /* If we swap operand in encoding, we match the next one. */
3779 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3783 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3784 if (!operand_type_match (overlap0
, i
.types
[0])
3785 || !operand_type_match (overlap1
, i
.types
[1])
3787 && !operand_type_register_match (overlap0
, i
.types
[0],
3789 overlap1
, i
.types
[1],
3792 /* Check if other direction is valid ... */
3793 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3797 /* Try reversing direction of operands. */
3798 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3799 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3800 if (!operand_type_match (overlap0
, i
.types
[0])
3801 || !operand_type_match (overlap1
, i
.types
[1])
3803 && !operand_type_register_match (overlap0
,
3810 /* Does not match either direction. */
3813 /* found_reverse_match holds which of D or FloatDR
3815 if (t
->opcode_modifier
.d
)
3816 found_reverse_match
= Opcode_D
;
3817 else if (t
->opcode_modifier
.floatd
)
3818 found_reverse_match
= Opcode_FloatD
;
3820 found_reverse_match
= 0;
3821 if (t
->opcode_modifier
.floatr
)
3822 found_reverse_match
|= Opcode_FloatR
;
3826 /* Found a forward 2 operand match here. */
3827 switch (t
->operands
)
3830 overlap4
= operand_type_and (i
.types
[4],
3833 overlap3
= operand_type_and (i
.types
[3],
3836 overlap2
= operand_type_and (i
.types
[2],
3841 switch (t
->operands
)
3844 if (!operand_type_match (overlap4
, i
.types
[4])
3845 || !operand_type_register_match (overlap3
,
3853 if (!operand_type_match (overlap3
, i
.types
[3])
3855 && !operand_type_register_match (overlap2
,
3863 /* Here we make use of the fact that there are no
3864 reverse match 3 operand instructions, and all 3
3865 operand instructions only need to be checked for
3866 register consistency between operands 2 and 3. */
3867 if (!operand_type_match (overlap2
, i
.types
[2])
3869 && !operand_type_register_match (overlap1
,
3879 /* Found either forward/reverse 2, 3 or 4 operand match here:
3880 slip through to break. */
3882 if (!found_cpu_match
)
3884 found_reverse_match
= 0;
3888 /* Check if VEX operands are valid. */
3889 if (VEX_check_operands (t
))
3892 /* We've found a match; break out of loop. */
3896 if (t
== current_templates
->end
)
3898 /* We found no match. */
3900 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3901 current_templates
->start
->name
);
3903 as_bad (_("suffix or operands invalid for `%s'"),
3904 current_templates
->start
->name
);
3908 if (!quiet_warnings
)
3911 && (i
.types
[0].bitfield
.jumpabsolute
3912 != operand_types
[0].bitfield
.jumpabsolute
))
3914 as_warn (_("indirect %s without `*'"), t
->name
);
3917 if (t
->opcode_modifier
.isprefix
3918 && t
->opcode_modifier
.ignoresize
)
3920 /* Warn them that a data or address size prefix doesn't
3921 affect assembly of the next line of code. */
3922 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3926 /* Copy the template we found. */
3929 if (addr_prefix_disp
!= -1)
3930 i
.tm
.operand_types
[addr_prefix_disp
]
3931 = operand_types
[addr_prefix_disp
];
3933 if (found_reverse_match
)
3935 /* If we found a reverse match we must alter the opcode
3936 direction bit. found_reverse_match holds bits to change
3937 (different for int & float insns). */
3939 i
.tm
.base_opcode
^= found_reverse_match
;
3941 i
.tm
.operand_types
[0] = operand_types
[1];
3942 i
.tm
.operand_types
[1] = operand_types
[0];
3951 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3952 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3954 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3956 as_bad (_("`%s' operand %d must use `%ses' segment"),
3962 /* There's only ever one segment override allowed per instruction.
3963 This instruction possibly has a legal segment override on the
3964 second operand, so copy the segment to where non-string
3965 instructions store it, allowing common code. */
3966 i
.seg
[0] = i
.seg
[1];
3968 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3970 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3972 as_bad (_("`%s' operand %d must use `%ses' segment"),
3983 process_suffix (void)
3985 /* If matched instruction specifies an explicit instruction mnemonic
3987 if (i
.tm
.opcode_modifier
.size16
)
3988 i
.suffix
= WORD_MNEM_SUFFIX
;
3989 else if (i
.tm
.opcode_modifier
.size32
)
3990 i
.suffix
= LONG_MNEM_SUFFIX
;
3991 else if (i
.tm
.opcode_modifier
.size64
)
3992 i
.suffix
= QWORD_MNEM_SUFFIX
;
3993 else if (i
.reg_operands
)
3995 /* If there's no instruction mnemonic suffix we try to invent one
3996 based on register operands. */
3999 /* We take i.suffix from the last register operand specified,
4000 Destination register type is more significant than source
4001 register type. crc32 in SSE4.2 prefers source register
4003 if (i
.tm
.base_opcode
== 0xf20f38f1)
4005 if (i
.types
[0].bitfield
.reg16
)
4006 i
.suffix
= WORD_MNEM_SUFFIX
;
4007 else if (i
.types
[0].bitfield
.reg32
)
4008 i
.suffix
= LONG_MNEM_SUFFIX
;
4009 else if (i
.types
[0].bitfield
.reg64
)
4010 i
.suffix
= QWORD_MNEM_SUFFIX
;
4012 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4014 if (i
.types
[0].bitfield
.reg8
)
4015 i
.suffix
= BYTE_MNEM_SUFFIX
;
4022 if (i
.tm
.base_opcode
== 0xf20f38f1
4023 || i
.tm
.base_opcode
== 0xf20f38f0)
4025 /* We have to know the operand size for crc32. */
4026 as_bad (_("ambiguous memory operand size for `%s`"),
4031 for (op
= i
.operands
; --op
>= 0;)
4032 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4034 if (i
.types
[op
].bitfield
.reg8
)
4036 i
.suffix
= BYTE_MNEM_SUFFIX
;
4039 else if (i
.types
[op
].bitfield
.reg16
)
4041 i
.suffix
= WORD_MNEM_SUFFIX
;
4044 else if (i
.types
[op
].bitfield
.reg32
)
4046 i
.suffix
= LONG_MNEM_SUFFIX
;
4049 else if (i
.types
[op
].bitfield
.reg64
)
4051 i
.suffix
= QWORD_MNEM_SUFFIX
;
4057 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4059 if (!check_byte_reg ())
4062 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4064 if (!check_long_reg ())
4067 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4070 && i
.tm
.opcode_modifier
.ignoresize
4071 && i
.tm
.opcode_modifier
.no_qsuf
)
4073 else if (!check_qword_reg ())
4076 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4078 if (!check_word_reg ())
4081 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4082 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4084 /* Skip if the instruction has x/y suffix. match_template
4085 should check if it is a valid suffix. */
4087 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4088 /* Do nothing if the instruction is going to ignore the prefix. */
4093 else if (i
.tm
.opcode_modifier
.defaultsize
4095 /* exclude fldenv/frstor/fsave/fstenv */
4096 && i
.tm
.opcode_modifier
.no_ssuf
)
4098 i
.suffix
= stackop_size
;
4100 else if (intel_syntax
4102 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4103 || i
.tm
.opcode_modifier
.jumpbyte
4104 || i
.tm
.opcode_modifier
.jumpintersegment
4105 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4106 && i
.tm
.extension_opcode
<= 3)))
4111 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4113 i
.suffix
= QWORD_MNEM_SUFFIX
;
4117 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4118 i
.suffix
= LONG_MNEM_SUFFIX
;
4121 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4122 i
.suffix
= WORD_MNEM_SUFFIX
;
4131 if (i
.tm
.opcode_modifier
.w
)
4133 as_bad (_("no instruction mnemonic suffix given and "
4134 "no register operands; can't size instruction"));
4140 unsigned int suffixes
;
4142 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4143 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4145 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4147 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4149 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4151 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4154 /* There are more than suffix matches. */
4155 if (i
.tm
.opcode_modifier
.w
4156 || ((suffixes
& (suffixes
- 1))
4157 && !i
.tm
.opcode_modifier
.defaultsize
4158 && !i
.tm
.opcode_modifier
.ignoresize
))
4160 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4166 /* Change the opcode based on the operand size given by i.suffix;
4167 We don't need to change things for byte insns. */
4170 && i
.suffix
!= BYTE_MNEM_SUFFIX
4171 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4172 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4174 /* It's not a byte, select word/dword operation. */
4175 if (i
.tm
.opcode_modifier
.w
)
4177 if (i
.tm
.opcode_modifier
.shortform
)
4178 i
.tm
.base_opcode
|= 8;
4180 i
.tm
.base_opcode
|= 1;
4183 /* Now select between word & dword operations via the operand
4184 size prefix, except for instructions that will ignore this
4186 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4188 /* The address size override prefix changes the size of the
4190 if ((flag_code
== CODE_32BIT
4191 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4192 || (flag_code
!= CODE_32BIT
4193 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4194 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4197 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4198 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4199 && !i
.tm
.opcode_modifier
.ignoresize
4200 && !i
.tm
.opcode_modifier
.floatmf
4201 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4202 || (flag_code
== CODE_64BIT
4203 && i
.tm
.opcode_modifier
.jumpbyte
)))
4205 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4207 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4208 prefix
= ADDR_PREFIX_OPCODE
;
4210 if (!add_prefix (prefix
))
4214 /* Set mode64 for an operand. */
4215 if (i
.suffix
== QWORD_MNEM_SUFFIX
4216 && flag_code
== CODE_64BIT
4217 && !i
.tm
.opcode_modifier
.norex64
)
4219 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4220 need rex64. cmpxchg8b is also a special case. */
4221 if (! (i
.operands
== 2
4222 && i
.tm
.base_opcode
== 0x90
4223 && i
.tm
.extension_opcode
== None
4224 && operand_type_equal (&i
.types
[0], &acc64
)
4225 && operand_type_equal (&i
.types
[1], &acc64
))
4226 && ! (i
.operands
== 1
4227 && i
.tm
.base_opcode
== 0xfc7
4228 && i
.tm
.extension_opcode
== 1
4229 && !operand_type_check (i
.types
[0], reg
)
4230 && operand_type_check (i
.types
[0], anymem
)))
4234 /* Size floating point instruction. */
4235 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4236 if (i
.tm
.opcode_modifier
.floatmf
)
4237 i
.tm
.base_opcode
^= 4;
4244 check_byte_reg (void)
4248 for (op
= i
.operands
; --op
>= 0;)
4250 /* If this is an eight bit register, it's OK. If it's the 16 or
4251 32 bit version of an eight bit register, we will just use the
4252 low portion, and that's OK too. */
4253 if (i
.types
[op
].bitfield
.reg8
)
4256 /* Don't generate this warning if not needed. */
4257 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4260 /* crc32 doesn't generate this warning. */
4261 if (i
.tm
.base_opcode
== 0xf20f38f0)
4264 if ((i
.types
[op
].bitfield
.reg16
4265 || i
.types
[op
].bitfield
.reg32
4266 || i
.types
[op
].bitfield
.reg64
)
4267 && i
.op
[op
].regs
->reg_num
< 4)
4269 /* Prohibit these changes in the 64bit mode, since the
4270 lowering is more complicated. */
4271 if (flag_code
== CODE_64BIT
4272 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4274 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4275 register_prefix
, i
.op
[op
].regs
->reg_name
,
4279 #if REGISTER_WARNINGS
4281 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4282 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4284 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4285 ? REGNAM_AL
- REGNAM_AX
4286 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4288 i
.op
[op
].regs
->reg_name
,
4293 /* Any other register is bad. */
4294 if (i
.types
[op
].bitfield
.reg16
4295 || i
.types
[op
].bitfield
.reg32
4296 || i
.types
[op
].bitfield
.reg64
4297 || i
.types
[op
].bitfield
.regmmx
4298 || i
.types
[op
].bitfield
.regxmm
4299 || i
.types
[op
].bitfield
.regymm
4300 || i
.types
[op
].bitfield
.sreg2
4301 || i
.types
[op
].bitfield
.sreg3
4302 || i
.types
[op
].bitfield
.control
4303 || i
.types
[op
].bitfield
.debug
4304 || i
.types
[op
].bitfield
.test
4305 || i
.types
[op
].bitfield
.floatreg
4306 || i
.types
[op
].bitfield
.floatacc
)
4308 as_bad (_("`%s%s' not allowed with `%s%c'"),
4310 i
.op
[op
].regs
->reg_name
,
4320 check_long_reg (void)
4324 for (op
= i
.operands
; --op
>= 0;)
4325 /* Reject eight bit registers, except where the template requires
4326 them. (eg. movzb) */
4327 if (i
.types
[op
].bitfield
.reg8
4328 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4329 || i
.tm
.operand_types
[op
].bitfield
.reg32
4330 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4332 as_bad (_("`%s%s' not allowed with `%s%c'"),
4334 i
.op
[op
].regs
->reg_name
,
4339 /* Warn if the e prefix on a general reg is missing. */
4340 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4341 && i
.types
[op
].bitfield
.reg16
4342 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4343 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4345 /* Prohibit these changes in the 64bit mode, since the
4346 lowering is more complicated. */
4347 if (flag_code
== CODE_64BIT
)
4349 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4350 register_prefix
, i
.op
[op
].regs
->reg_name
,
4354 #if REGISTER_WARNINGS
4356 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4358 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4360 i
.op
[op
].regs
->reg_name
,
4364 /* Warn if the r prefix on a general reg is missing. */
4365 else if (i
.types
[op
].bitfield
.reg64
4366 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4367 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4370 && i
.tm
.opcode_modifier
.toqword
4371 && !i
.types
[0].bitfield
.regxmm
)
4373 /* Convert to QWORD. We want REX byte. */
4374 i
.suffix
= QWORD_MNEM_SUFFIX
;
4378 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4379 register_prefix
, i
.op
[op
].regs
->reg_name
,
4388 check_qword_reg (void)
4392 for (op
= i
.operands
; --op
>= 0; )
4393 /* Reject eight bit registers, except where the template requires
4394 them. (eg. movzb) */
4395 if (i
.types
[op
].bitfield
.reg8
4396 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4397 || i
.tm
.operand_types
[op
].bitfield
.reg32
4398 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4400 as_bad (_("`%s%s' not allowed with `%s%c'"),
4402 i
.op
[op
].regs
->reg_name
,
4407 /* Warn if the e prefix on a general reg is missing. */
4408 else if ((i
.types
[op
].bitfield
.reg16
4409 || i
.types
[op
].bitfield
.reg32
)
4410 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4411 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4413 /* Prohibit these changes in the 64bit mode, since the
4414 lowering is more complicated. */
4416 && i
.tm
.opcode_modifier
.todword
4417 && !i
.types
[0].bitfield
.regxmm
)
4419 /* Convert to DWORD. We don't want REX byte. */
4420 i
.suffix
= LONG_MNEM_SUFFIX
;
4424 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4425 register_prefix
, i
.op
[op
].regs
->reg_name
,
4434 check_word_reg (void)
4437 for (op
= i
.operands
; --op
>= 0;)
4438 /* Reject eight bit registers, except where the template requires
4439 them. (eg. movzb) */
4440 if (i
.types
[op
].bitfield
.reg8
4441 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4442 || i
.tm
.operand_types
[op
].bitfield
.reg32
4443 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4445 as_bad (_("`%s%s' not allowed with `%s%c'"),
4447 i
.op
[op
].regs
->reg_name
,
4452 /* Warn if the e prefix on a general reg is present. */
4453 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4454 && i
.types
[op
].bitfield
.reg32
4455 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4456 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4458 /* Prohibit these changes in the 64bit mode, since the
4459 lowering is more complicated. */
4460 if (flag_code
== CODE_64BIT
)
4462 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4463 register_prefix
, i
.op
[op
].regs
->reg_name
,
4468 #if REGISTER_WARNINGS
4469 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4471 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4473 i
.op
[op
].regs
->reg_name
,
4481 update_imm (unsigned int j
)
4483 i386_operand_type overlap
;
4485 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4486 if ((overlap
.bitfield
.imm8
4487 || overlap
.bitfield
.imm8s
4488 || overlap
.bitfield
.imm16
4489 || overlap
.bitfield
.imm32
4490 || overlap
.bitfield
.imm32s
4491 || overlap
.bitfield
.imm64
)
4492 && !operand_type_equal (&overlap
, &imm8
)
4493 && !operand_type_equal (&overlap
, &imm8s
)
4494 && !operand_type_equal (&overlap
, &imm16
)
4495 && !operand_type_equal (&overlap
, &imm32
)
4496 && !operand_type_equal (&overlap
, &imm32s
)
4497 && !operand_type_equal (&overlap
, &imm64
))
4501 i386_operand_type temp
;
4503 operand_type_set (&temp
, 0);
4504 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4506 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4507 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4509 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4510 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4511 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4513 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4514 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4517 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4520 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4521 || operand_type_equal (&overlap
, &imm16_32
)
4522 || operand_type_equal (&overlap
, &imm16_32s
))
4524 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4529 if (!operand_type_equal (&overlap
, &imm8
)
4530 && !operand_type_equal (&overlap
, &imm8s
)
4531 && !operand_type_equal (&overlap
, &imm16
)
4532 && !operand_type_equal (&overlap
, &imm32
)
4533 && !operand_type_equal (&overlap
, &imm32s
)
4534 && !operand_type_equal (&overlap
, &imm64
))
4536 as_bad (_("no instruction mnemonic suffix given; "
4537 "can't determine immediate size"));
4541 i
.types
[j
] = overlap
;
4551 for (j
= 0; j
< 2; j
++)
4552 if (update_imm (j
) == 0)
4555 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4556 assert (operand_type_check (i
.types
[2], imm
) == 0);
4564 i
.drex
.modrm_reg
= 0;
4565 i
.drex
.modrm_regmem
= 0;
4567 /* SSE5 4 operand instructions must have the destination the same as
4568 one of the inputs. Figure out the destination register and cache
4569 it away in the drex field, and remember which fields to use for
4571 if (i
.tm
.opcode_modifier
.drex
4572 && i
.tm
.opcode_modifier
.drexv
4575 i
.tm
.extension_opcode
= None
;
4577 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4578 if (i
.types
[0].bitfield
.regxmm
!= 0
4579 && i
.types
[1].bitfield
.regxmm
!= 0
4580 && i
.types
[2].bitfield
.regxmm
!= 0
4581 && i
.types
[3].bitfield
.regxmm
!= 0
4582 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4583 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4585 /* Clear the arguments that are stored in drex. */
4586 operand_type_set (&i
.types
[0], 0);
4587 operand_type_set (&i
.types
[3], 0);
4588 i
.reg_operands
-= 2;
4590 /* There are two different ways to encode a 4 operand
4591 instruction with all registers that uses OC1 set to
4592 0 or 1. Favor setting OC1 to 0 since this mimics the
4593 actions of other SSE5 assemblers. Use modrm encoding 2
4594 for register/register. Include the high order bit that
4595 is normally stored in the REX byte in the register
4597 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4598 i
.drex
.modrm_reg
= 2;
4599 i
.drex
.modrm_regmem
= 1;
4600 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4601 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4604 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4605 else if (i
.types
[0].bitfield
.regxmm
!= 0
4606 && i
.types
[1].bitfield
.regxmm
!= 0
4607 && (i
.types
[2].bitfield
.regxmm
4608 || operand_type_check (i
.types
[2], anymem
))
4609 && i
.types
[3].bitfield
.regxmm
!= 0
4610 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4611 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4613 /* clear the arguments that are stored in drex */
4614 operand_type_set (&i
.types
[0], 0);
4615 operand_type_set (&i
.types
[3], 0);
4616 i
.reg_operands
-= 2;
4618 /* Specify the modrm encoding for memory addressing. Include
4619 the high order bit that is normally stored in the REX byte
4620 in the register field. */
4621 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4622 i
.drex
.modrm_reg
= 1;
4623 i
.drex
.modrm_regmem
= 2;
4624 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4625 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4628 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4629 else if (i
.types
[0].bitfield
.regxmm
!= 0
4630 && operand_type_check (i
.types
[1], anymem
) != 0
4631 && i
.types
[2].bitfield
.regxmm
!= 0
4632 && i
.types
[3].bitfield
.regxmm
!= 0
4633 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4634 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4636 /* Clear the arguments that are stored in drex. */
4637 operand_type_set (&i
.types
[0], 0);
4638 operand_type_set (&i
.types
[3], 0);
4639 i
.reg_operands
-= 2;
4641 /* Specify the modrm encoding for memory addressing. Include
4642 the high order bit that is normally stored in the REX byte
4643 in the register field. */
4644 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4645 i
.drex
.modrm_reg
= 2;
4646 i
.drex
.modrm_regmem
= 1;
4647 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4648 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4651 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4652 else if (i
.types
[0].bitfield
.regxmm
!= 0
4653 && i
.types
[1].bitfield
.regxmm
!= 0
4654 && i
.types
[2].bitfield
.regxmm
!= 0
4655 && i
.types
[3].bitfield
.regxmm
!= 0
4656 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4657 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4659 /* clear the arguments that are stored in drex */
4660 operand_type_set (&i
.types
[2], 0);
4661 operand_type_set (&i
.types
[3], 0);
4662 i
.reg_operands
-= 2;
4664 /* There are two different ways to encode a 4 operand
4665 instruction with all registers that uses OC1 set to
4666 0 or 1. Favor setting OC1 to 0 since this mimics the
4667 actions of other SSE5 assemblers. Use modrm encoding
4668 2 for register/register. Include the high order bit that
4669 is normally stored in the REX byte in the register
4671 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4672 i
.drex
.modrm_reg
= 1;
4673 i
.drex
.modrm_regmem
= 0;
4675 /* Remember the register, including the upper bits */
4676 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4677 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4680 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4681 else if (i
.types
[0].bitfield
.regxmm
!= 0
4682 && (i
.types
[1].bitfield
.regxmm
4683 || operand_type_check (i
.types
[1], anymem
))
4684 && i
.types
[2].bitfield
.regxmm
!= 0
4685 && i
.types
[3].bitfield
.regxmm
!= 0
4686 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4687 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4689 /* Clear the arguments that are stored in drex. */
4690 operand_type_set (&i
.types
[2], 0);
4691 operand_type_set (&i
.types
[3], 0);
4692 i
.reg_operands
-= 2;
4694 /* Specify the modrm encoding and remember the register
4695 including the bits normally stored in the REX byte. */
4696 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4697 i
.drex
.modrm_reg
= 0;
4698 i
.drex
.modrm_regmem
= 1;
4699 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4700 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4703 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4704 else if (operand_type_check (i
.types
[0], anymem
) != 0
4705 && i
.types
[1].bitfield
.regxmm
!= 0
4706 && i
.types
[2].bitfield
.regxmm
!= 0
4707 && i
.types
[3].bitfield
.regxmm
!= 0
4708 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4709 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4711 /* clear the arguments that are stored in drex */
4712 operand_type_set (&i
.types
[2], 0);
4713 operand_type_set (&i
.types
[3], 0);
4714 i
.reg_operands
-= 2;
4716 /* Specify the modrm encoding and remember the register
4717 including the bits normally stored in the REX byte. */
4718 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4719 i
.drex
.modrm_reg
= 1;
4720 i
.drex
.modrm_regmem
= 0;
4721 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4722 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4726 as_bad (_("Incorrect operands for the '%s' instruction"),
4730 /* SSE5 instructions with the DREX byte where the only memory operand
4731 is in the 2nd argument, and the first and last xmm register must
4732 match, and is encoded in the DREX byte. */
4733 else if (i
.tm
.opcode_modifier
.drex
4734 && !i
.tm
.opcode_modifier
.drexv
4737 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4738 if (i
.types
[0].bitfield
.regxmm
!= 0
4739 && (i
.types
[1].bitfield
.regxmm
4740 || operand_type_check(i
.types
[1], anymem
))
4741 && i
.types
[2].bitfield
.regxmm
!= 0
4742 && i
.types
[3].bitfield
.regxmm
!= 0
4743 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4744 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4746 /* clear the arguments that are stored in drex */
4747 operand_type_set (&i
.types
[0], 0);
4748 operand_type_set (&i
.types
[3], 0);
4749 i
.reg_operands
-= 2;
4751 /* Specify the modrm encoding and remember the register
4752 including the high bit normally stored in the REX
4754 i
.drex
.modrm_reg
= 2;
4755 i
.drex
.modrm_regmem
= 1;
4756 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4757 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4761 as_bad (_("Incorrect operands for the '%s' instruction"),
4765 /* SSE5 3 operand instructions that the result is a register, being
4766 either operand can be a memory operand, using OC0 to note which
4767 one is the memory. */
4768 else if (i
.tm
.opcode_modifier
.drex
4769 && i
.tm
.opcode_modifier
.drexv
4772 i
.tm
.extension_opcode
= None
;
4774 /* Case 1: 3 operand insn, src1 = register. */
4775 if (i
.types
[0].bitfield
.regxmm
!= 0
4776 && i
.types
[1].bitfield
.regxmm
!= 0
4777 && i
.types
[2].bitfield
.regxmm
!= 0)
4779 /* Clear the arguments that are stored in drex. */
4780 operand_type_set (&i
.types
[2], 0);
4783 /* Specify the modrm encoding and remember the register
4784 including the high bit normally stored in the REX byte. */
4785 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4786 i
.drex
.modrm_reg
= 1;
4787 i
.drex
.modrm_regmem
= 0;
4788 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4789 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4792 /* Case 2: 3 operand insn, src1 = memory. */
4793 else if (operand_type_check (i
.types
[0], anymem
) != 0
4794 && i
.types
[1].bitfield
.regxmm
!= 0
4795 && i
.types
[2].bitfield
.regxmm
!= 0)
4797 /* Clear the arguments that are stored in drex. */
4798 operand_type_set (&i
.types
[2], 0);
4801 /* Specify the modrm encoding and remember the register
4802 including the high bit normally stored in the REX
4804 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4805 i
.drex
.modrm_reg
= 1;
4806 i
.drex
.modrm_regmem
= 0;
4807 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4808 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4811 /* Case 3: 3 operand insn, src2 = memory. */
4812 else if (i
.types
[0].bitfield
.regxmm
!= 0
4813 && operand_type_check (i
.types
[1], anymem
) != 0
4814 && i
.types
[2].bitfield
.regxmm
!= 0)
4816 /* Clear the arguments that are stored in drex. */
4817 operand_type_set (&i
.types
[2], 0);
4820 /* Specify the modrm encoding and remember the register
4821 including the high bit normally stored in the REX byte. */
4822 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4823 i
.drex
.modrm_reg
= 0;
4824 i
.drex
.modrm_regmem
= 1;
4825 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4826 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4830 as_bad (_("Incorrect operands for the '%s' instruction"),
4834 /* SSE5 4 operand instructions that are the comparison instructions
4835 where the first operand is the immediate value of the comparison
4837 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4839 /* Case 1: 4 operand insn, src1 = reg/memory. */
4840 if (operand_type_check (i
.types
[0], imm
) != 0
4841 && (i
.types
[1].bitfield
.regxmm
4842 || operand_type_check (i
.types
[1], anymem
))
4843 && i
.types
[2].bitfield
.regxmm
!= 0
4844 && i
.types
[3].bitfield
.regxmm
!= 0)
4846 /* clear the arguments that are stored in drex */
4847 operand_type_set (&i
.types
[3], 0);
4850 /* Specify the modrm encoding and remember the register
4851 including the high bit normally stored in the REX byte. */
4852 i
.drex
.modrm_reg
= 2;
4853 i
.drex
.modrm_regmem
= 1;
4854 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4855 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4858 /* Case 2: 3 operand insn with ImmExt that places the
4859 opcode_extension as an immediate argument. This is used for
4860 all of the varients of comparison that supplies the appropriate
4861 value as part of the instruction. */
4862 else if ((i
.types
[0].bitfield
.regxmm
4863 || operand_type_check (i
.types
[0], anymem
))
4864 && i
.types
[1].bitfield
.regxmm
!= 0
4865 && i
.types
[2].bitfield
.regxmm
!= 0
4866 && operand_type_check (i
.types
[3], imm
) != 0)
4868 /* clear the arguments that are stored in drex */
4869 operand_type_set (&i
.types
[2], 0);
4872 /* Specify the modrm encoding and remember the register
4873 including the high bit normally stored in the REX byte. */
4874 i
.drex
.modrm_reg
= 1;
4875 i
.drex
.modrm_regmem
= 0;
4876 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4877 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4881 as_bad (_("Incorrect operands for the '%s' instruction"),
4885 else if (i
.tm
.opcode_modifier
.drex
4886 || i
.tm
.opcode_modifier
.drexv
4887 || i
.tm
.opcode_modifier
.drexc
)
4888 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4892 bad_implicit_operand (int xmm
)
4894 const char *reg
= xmm
? "xmm0" : "ymm0";
4896 as_bad (_("the last operand of `%s' must be `%s%s'"),
4897 i
.tm
.name
, register_prefix
, reg
);
4899 as_bad (_("the first operand of `%s' must be `%s%s'"),
4900 i
.tm
.name
, register_prefix
, reg
);
4905 process_operands (void)
4907 /* Default segment register this instruction will use for memory
4908 accesses. 0 means unknown. This is only for optimizing out
4909 unnecessary segment overrides. */
4910 const seg_entry
*default_seg
= 0;
4912 /* Handle all of the DREX munging that SSE5 needs. */
4913 if (i
.tm
.opcode_modifier
.drex
4914 || i
.tm
.opcode_modifier
.drexv
4915 || i
.tm
.opcode_modifier
.drexc
)
4918 if (i
.tm
.opcode_modifier
.sse2avx
4919 && (i
.tm
.opcode_modifier
.vexnds
4920 || i
.tm
.opcode_modifier
.vexndd
))
4922 unsigned int dup
= i
.operands
;
4923 unsigned int dest
= dup
- 1;
4926 /* The destination must be an xmm register. */
4927 assert (i
.reg_operands
4928 && MAX_OPERANDS
> dup
4929 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4931 if (i
.tm
.opcode_modifier
.firstxmm0
)
4933 /* The first operand is implicit and must be xmm0. */
4934 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4935 if (i
.op
[0].regs
->reg_num
!= 0)
4936 return bad_implicit_operand (1);
4938 if (i
.tm
.opcode_modifier
.vex3sources
)
4940 /* Keep xmm0 for instructions with VEX prefix and 3
4946 /* We remove the first xmm0 and keep the number of
4947 operands unchanged, which in fact duplicates the
4949 for (j
= 1; j
< i
.operands
; j
++)
4951 i
.op
[j
- 1] = i
.op
[j
];
4952 i
.types
[j
- 1] = i
.types
[j
];
4953 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4957 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4959 assert ((MAX_OPERANDS
- 1) > dup
4960 && i
.tm
.opcode_modifier
.vex3sources
);
4962 /* Add the implicit xmm0 for instructions with VEX prefix
4964 for (j
= i
.operands
; j
> 0; j
--)
4966 i
.op
[j
] = i
.op
[j
- 1];
4967 i
.types
[j
] = i
.types
[j
- 1];
4968 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4971 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4972 i
.types
[0] = regxmm
;
4973 i
.tm
.operand_types
[0] = regxmm
;
4976 i
.reg_operands
+= 2;
4981 i
.op
[dup
] = i
.op
[dest
];
4982 i
.types
[dup
] = i
.types
[dest
];
4983 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4992 i
.op
[dup
] = i
.op
[dest
];
4993 i
.types
[dup
] = i
.types
[dest
];
4994 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4997 if (i
.tm
.opcode_modifier
.immext
)
5000 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5004 /* The first operand is implicit and must be xmm0/ymm0. */
5005 assert (i
.reg_operands
5006 && (operand_type_equal (&i
.types
[0], ®xmm
)
5007 || operand_type_equal (&i
.types
[0], ®ymm
)));
5008 if (i
.op
[0].regs
->reg_num
!= 0)
5009 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5011 for (j
= 1; j
< i
.operands
; j
++)
5013 i
.op
[j
- 1] = i
.op
[j
];
5014 i
.types
[j
- 1] = i
.types
[j
];
5016 /* We need to adjust fields in i.tm since they are used by
5017 build_modrm_byte. */
5018 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5025 else if (i
.tm
.opcode_modifier
.regkludge
)
5027 /* The imul $imm, %reg instruction is converted into
5028 imul $imm, %reg, %reg, and the clr %reg instruction
5029 is converted into xor %reg, %reg. */
5031 unsigned int first_reg_op
;
5033 if (operand_type_check (i
.types
[0], reg
))
5037 /* Pretend we saw the extra register operand. */
5038 assert (i
.reg_operands
== 1
5039 && i
.op
[first_reg_op
+ 1].regs
== 0);
5040 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5041 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5046 if (i
.tm
.opcode_modifier
.shortform
)
5048 if (i
.types
[0].bitfield
.sreg2
5049 || i
.types
[0].bitfield
.sreg3
)
5051 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5052 && i
.op
[0].regs
->reg_num
== 1)
5054 as_bad (_("you can't `pop %scs'"), register_prefix
);
5057 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5058 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5063 /* The register or float register operand is in operand
5067 if (i
.types
[0].bitfield
.floatreg
5068 || operand_type_check (i
.types
[0], reg
))
5072 /* Register goes in low 3 bits of opcode. */
5073 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5074 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5076 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5078 /* Warn about some common errors, but press on regardless.
5079 The first case can be generated by gcc (<= 2.8.1). */
5080 if (i
.operands
== 2)
5082 /* Reversed arguments on faddp, fsubp, etc. */
5083 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5084 register_prefix
, i
.op
[1].regs
->reg_name
,
5085 register_prefix
, i
.op
[0].regs
->reg_name
);
5089 /* Extraneous `l' suffix on fp insn. */
5090 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5091 register_prefix
, i
.op
[0].regs
->reg_name
);
5096 else if (i
.tm
.opcode_modifier
.modrm
)
5098 /* The opcode is completed (modulo i.tm.extension_opcode which
5099 must be put into the modrm byte). Now, we make the modrm and
5100 index base bytes based on all the info we've collected. */
5102 default_seg
= build_modrm_byte ();
5104 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5108 else if (i
.tm
.opcode_modifier
.isstring
)
5110 /* For the string instructions that allow a segment override
5111 on one of their operands, the default segment is ds. */
5115 if (i
.tm
.base_opcode
== 0x8d /* lea */
5118 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5120 /* If a segment was explicitly specified, and the specified segment
5121 is not the default, use an opcode prefix to select it. If we
5122 never figured out what the default segment is, then default_seg
5123 will be zero at this point, and the specified segment prefix will
5125 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5127 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5133 static const seg_entry
*
5134 build_modrm_byte (void)
5136 const seg_entry
*default_seg
= 0;
5137 unsigned int source
, dest
;
5140 /* The first operand of instructions with VEX prefix and 3 sources
5141 must be VEX_Imm4. */
5142 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5145 unsigned int nds
, reg
;
5147 dest
= i
.operands
- 1;
5152 /* This instruction must have 4 operands: 4 register operands
5153 or 3 register operands plus 1 memory operand. It must have
5154 VexNDS and VexImmExt. */
5155 assert (i
.operands
== 4
5156 && (i
.reg_operands
== 4
5157 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5158 && i
.tm
.opcode_modifier
.vexnds
5159 && i
.tm
.opcode_modifier
.veximmext
5160 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5162 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5164 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5166 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5168 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5170 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5173 /* Generate an 8bit immediate operand to encode the register
5175 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5176 i
.op
[i
.operands
].imms
= exp
;
5177 i
.types
[i
.operands
] = imm8
;
5179 exp
->X_op
= O_constant
;
5181 = ((i
.op
[0].regs
->reg_num
5182 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5184 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5189 /* SSE5 4 operand instructions are encoded in such a way that one of
5190 the inputs must match the destination register. Process_drex hides
5191 the 3rd argument in the drex field, so that by the time we get
5192 here, it looks to GAS as if this is a 2 operand instruction. */
5193 if ((i
.tm
.opcode_modifier
.drex
5194 || i
.tm
.opcode_modifier
.drexv
5195 || i
.tm
.opcode_modifier
.drexc
)
5196 && i
.reg_operands
== 2)
5198 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5199 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5201 i
.rm
.reg
= reg
->reg_num
;
5202 i
.rm
.regmem
= regmem
->reg_num
;
5204 if ((reg
->reg_flags
& RegRex
) != 0)
5206 if ((regmem
->reg_flags
& RegRex
) != 0)
5210 /* i.reg_operands MUST be the number of real register operands;
5211 implicit registers do not count. If there are 3 register
5212 operands, it must be a instruction with VexNDS. For a
5213 instruction with VexNDD, the destination register is encoded
5214 in VEX prefix. If there are 4 register operands, it must be
5215 a instruction with VEX prefix and 3 sources. */
5216 else if (i
.mem_operands
== 0
5217 && ((i
.reg_operands
== 2
5218 && !i
.tm
.opcode_modifier
.vexndd
)
5219 || (i
.reg_operands
== 3
5220 && i
.tm
.opcode_modifier
.vexnds
)
5221 || (i
.reg_operands
== 4 && vex_3_sources
)))
5229 /* When there are 3 operands, one of them may be immediate,
5230 which may be the first or the last operand. Otherwise,
5231 the first operand must be shift count register (cl) or it
5232 is an instruction with VexNDS. */
5233 assert (i
.imm_operands
== 1
5234 || (i
.imm_operands
== 0
5235 && (i
.tm
.opcode_modifier
.vexnds
5236 || i
.types
[0].bitfield
.shiftcount
)));
5237 if (operand_type_check (i
.types
[0], imm
)
5238 || i
.types
[0].bitfield
.shiftcount
)
5244 /* When there are 4 operands, the first two must be 8bit
5245 immediate operands. The source operand will be the 3rd
5248 For instructions with VexNDS, if the first operand
5249 an imm8, the source operand is the 2nd one. If the last
5250 operand is imm8, the source operand is the first one. */
5251 assert ((i
.imm_operands
== 2
5252 && i
.types
[0].bitfield
.imm8
5253 && i
.types
[1].bitfield
.imm8
)
5254 || (i
.tm
.opcode_modifier
.vexnds
5255 && i
.imm_operands
== 1
5256 && (i
.types
[0].bitfield
.imm8
5257 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5258 if (i
.tm
.opcode_modifier
.vexnds
)
5260 if (i
.types
[0].bitfield
.imm8
)
5278 if (i
.tm
.opcode_modifier
.vexnds
)
5280 /* For instructions with VexNDS, the register-only
5281 source operand must be XMM or YMM register. It is
5282 encoded in VEX prefix. We need to clear RegMem bit
5283 before calling operand_type_equal. */
5284 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5285 op
.bitfield
.regmem
= 0;
5286 if ((dest
+ 1) >= i
.operands
5287 || (!operand_type_equal (&op
, ®xmm
)
5288 && !operand_type_equal (&op
, ®ymm
)))
5290 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5296 /* One of the register operands will be encoded in the i.tm.reg
5297 field, the other in the combined i.tm.mode and i.tm.regmem
5298 fields. If no form of this instruction supports a memory
5299 destination operand, then we assume the source operand may
5300 sometimes be a memory operand and so we need to store the
5301 destination in the i.rm.reg field. */
5302 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5303 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5305 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5306 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5307 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5309 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5314 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5315 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5316 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5318 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5321 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5323 if (!i
.types
[0].bitfield
.control
5324 && !i
.types
[1].bitfield
.control
)
5326 i
.rex
&= ~(REX_R
| REX_B
);
5327 add_prefix (LOCK_PREFIX_OPCODE
);
5331 { /* If it's not 2 reg operands... */
5336 unsigned int fake_zero_displacement
= 0;
5339 /* This has been precalculated for SSE5 instructions
5340 that have a DREX field earlier in process_drex. */
5341 if (i
.tm
.opcode_modifier
.drex
5342 || i
.tm
.opcode_modifier
.drexv
5343 || i
.tm
.opcode_modifier
.drexc
)
5344 op
= i
.drex
.modrm_regmem
;
5347 for (op
= 0; op
< i
.operands
; op
++)
5348 if (operand_type_check (i
.types
[op
], anymem
))
5350 assert (op
< i
.operands
);
5355 if (i
.base_reg
== 0)
5358 if (!i
.disp_operands
)
5359 fake_zero_displacement
= 1;
5360 if (i
.index_reg
== 0)
5362 /* Operand is just <disp> */
5363 if (flag_code
== CODE_64BIT
)
5365 /* 64bit mode overwrites the 32bit absolute
5366 addressing by RIP relative addressing and
5367 absolute addressing is encoded by one of the
5368 redundant SIB forms. */
5369 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5370 i
.sib
.base
= NO_BASE_REGISTER
;
5371 i
.sib
.index
= NO_INDEX_REGISTER
;
5372 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5373 ? disp32s
: disp32
);
5375 else if ((flag_code
== CODE_16BIT
)
5376 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5378 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5379 i
.types
[op
] = disp16
;
5383 i
.rm
.regmem
= NO_BASE_REGISTER
;
5384 i
.types
[op
] = disp32
;
5387 else /* !i.base_reg && i.index_reg */
5389 if (i
.index_reg
->reg_num
== RegEiz
5390 || i
.index_reg
->reg_num
== RegRiz
)
5391 i
.sib
.index
= NO_INDEX_REGISTER
;
5393 i
.sib
.index
= i
.index_reg
->reg_num
;
5394 i
.sib
.base
= NO_BASE_REGISTER
;
5395 i
.sib
.scale
= i
.log2_scale_factor
;
5396 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5397 i
.types
[op
].bitfield
.disp8
= 0;
5398 i
.types
[op
].bitfield
.disp16
= 0;
5399 i
.types
[op
].bitfield
.disp64
= 0;
5400 if (flag_code
!= CODE_64BIT
)
5402 /* Must be 32 bit */
5403 i
.types
[op
].bitfield
.disp32
= 1;
5404 i
.types
[op
].bitfield
.disp32s
= 0;
5408 i
.types
[op
].bitfield
.disp32
= 0;
5409 i
.types
[op
].bitfield
.disp32s
= 1;
5411 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5415 /* RIP addressing for 64bit mode. */
5416 else if (i
.base_reg
->reg_num
== RegRip
||
5417 i
.base_reg
->reg_num
== RegEip
)
5419 i
.rm
.regmem
= NO_BASE_REGISTER
;
5420 i
.types
[op
].bitfield
.disp8
= 0;
5421 i
.types
[op
].bitfield
.disp16
= 0;
5422 i
.types
[op
].bitfield
.disp32
= 0;
5423 i
.types
[op
].bitfield
.disp32s
= 1;
5424 i
.types
[op
].bitfield
.disp64
= 0;
5425 i
.flags
[op
] |= Operand_PCrel
;
5426 if (! i
.disp_operands
)
5427 fake_zero_displacement
= 1;
5429 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5431 switch (i
.base_reg
->reg_num
)
5434 if (i
.index_reg
== 0)
5436 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5437 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5441 if (i
.index_reg
== 0)
5444 if (operand_type_check (i
.types
[op
], disp
) == 0)
5446 /* fake (%bp) into 0(%bp) */
5447 i
.types
[op
].bitfield
.disp8
= 1;
5448 fake_zero_displacement
= 1;
5451 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5452 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5454 default: /* (%si) -> 4 or (%di) -> 5 */
5455 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5457 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5459 else /* i.base_reg and 32/64 bit mode */
5461 if (flag_code
== CODE_64BIT
5462 && operand_type_check (i
.types
[op
], disp
))
5464 i386_operand_type temp
;
5465 operand_type_set (&temp
, 0);
5466 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5468 if (i
.prefix
[ADDR_PREFIX
] == 0)
5469 i
.types
[op
].bitfield
.disp32s
= 1;
5471 i
.types
[op
].bitfield
.disp32
= 1;
5474 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5475 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5477 i
.sib
.base
= i
.base_reg
->reg_num
;
5478 /* x86-64 ignores REX prefix bit here to avoid decoder
5480 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5483 if (i
.disp_operands
== 0)
5485 fake_zero_displacement
= 1;
5486 i
.types
[op
].bitfield
.disp8
= 1;
5489 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5493 i
.sib
.scale
= i
.log2_scale_factor
;
5494 if (i
.index_reg
== 0)
5496 /* <disp>(%esp) becomes two byte modrm with no index
5497 register. We've already stored the code for esp
5498 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5499 Any base register besides %esp will not use the
5500 extra modrm byte. */
5501 i
.sib
.index
= NO_INDEX_REGISTER
;
5505 if (i
.index_reg
->reg_num
== RegEiz
5506 || i
.index_reg
->reg_num
== RegRiz
)
5507 i
.sib
.index
= NO_INDEX_REGISTER
;
5509 i
.sib
.index
= i
.index_reg
->reg_num
;
5510 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5511 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5516 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5517 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5520 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5523 if (fake_zero_displacement
)
5525 /* Fakes a zero displacement assuming that i.types[op]
5526 holds the correct displacement size. */
5529 assert (i
.op
[op
].disps
== 0);
5530 exp
= &disp_expressions
[i
.disp_operands
++];
5531 i
.op
[op
].disps
= exp
;
5532 exp
->X_op
= O_constant
;
5533 exp
->X_add_number
= 0;
5534 exp
->X_add_symbol
= (symbolS
*) 0;
5535 exp
->X_op_symbol
= (symbolS
*) 0;
5543 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5544 (if any) based on i.tm.extension_opcode. Again, we must be
5545 careful to make sure that segment/control/debug/test/MMX
5546 registers are coded into the i.rm.reg field. */
5551 /* This has been precalculated for SSE5 instructions
5552 that have a DREX field earlier in process_drex. */
5553 if (i
.tm
.opcode_modifier
.drex
5554 || i
.tm
.opcode_modifier
.drexv
5555 || i
.tm
.opcode_modifier
.drexc
)
5557 op
= i
.drex
.modrm_reg
;
5558 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5559 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5564 unsigned int vex_reg
= ~0;
5566 for (op
= 0; op
< i
.operands
; op
++)
5567 if (i
.types
[op
].bitfield
.reg8
5568 || i
.types
[op
].bitfield
.reg16
5569 || i
.types
[op
].bitfield
.reg32
5570 || i
.types
[op
].bitfield
.reg64
5571 || i
.types
[op
].bitfield
.regmmx
5572 || i
.types
[op
].bitfield
.regxmm
5573 || i
.types
[op
].bitfield
.regymm
5574 || i
.types
[op
].bitfield
.sreg2
5575 || i
.types
[op
].bitfield
.sreg3
5576 || i
.types
[op
].bitfield
.control
5577 || i
.types
[op
].bitfield
.debug
5578 || i
.types
[op
].bitfield
.test
)
5583 else if (i
.tm
.opcode_modifier
.vexnds
)
5585 /* For instructions with VexNDS, the register-only
5586 source operand is encoded in VEX prefix. */
5587 assert (mem
!= (unsigned int) ~0);
5592 assert (op
< i
.operands
);
5597 assert (vex_reg
< i
.operands
);
5600 else if (i
.tm
.opcode_modifier
.vexndd
)
5602 /* For instructions with VexNDD, there should be
5603 no memory operand and the register destination
5604 is encoded in VEX prefix. */
5605 assert (i
.mem_operands
== 0
5606 && (op
+ 2) == i
.operands
);
5610 assert (op
< i
.operands
);
5612 if (vex_reg
!= (unsigned int) ~0)
5614 assert (i
.reg_operands
== 2);
5616 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5618 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5621 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5624 /* If there is an extension opcode to put here, the
5625 register number must be put into the regmem field. */
5626 if (i
.tm
.extension_opcode
!= None
)
5628 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5629 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5634 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5635 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5640 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5641 must set it to 3 to indicate this is a register operand
5642 in the regmem field. */
5643 if (!i
.mem_operands
)
5647 /* Fill in i.rm.reg field with extension opcode (if any). */
5648 if (i
.tm
.extension_opcode
!= None
5649 && !(i
.tm
.opcode_modifier
.drex
5650 || i
.tm
.opcode_modifier
.drexv
5651 || i
.tm
.opcode_modifier
.drexc
))
5652 i
.rm
.reg
= i
.tm
.extension_opcode
;
5658 output_branch (void)
5663 relax_substateT subtype
;
5668 if (flag_code
== CODE_16BIT
)
5672 if (i
.prefix
[DATA_PREFIX
] != 0)
5678 /* Pentium4 branch hints. */
5679 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5680 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5685 if (i
.prefix
[REX_PREFIX
] != 0)
5691 if (i
.prefixes
!= 0 && !intel_syntax
)
5692 as_warn (_("skipping prefixes on this instruction"));
5694 /* It's always a symbol; End frag & setup for relax.
5695 Make sure there is enough room in this frag for the largest
5696 instruction we may generate in md_convert_frag. This is 2
5697 bytes for the opcode and room for the prefix and largest
5699 frag_grow (prefix
+ 2 + 4);
5700 /* Prefix and 1 opcode byte go in fr_fix. */
5701 p
= frag_more (prefix
+ 1);
5702 if (i
.prefix
[DATA_PREFIX
] != 0)
5703 *p
++ = DATA_PREFIX_OPCODE
;
5704 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5705 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5706 *p
++ = i
.prefix
[SEG_PREFIX
];
5707 if (i
.prefix
[REX_PREFIX
] != 0)
5708 *p
++ = i
.prefix
[REX_PREFIX
];
5709 *p
= i
.tm
.base_opcode
;
5711 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5712 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5713 else if (cpu_arch_flags
.bitfield
.cpui386
)
5714 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5716 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5719 sym
= i
.op
[0].disps
->X_add_symbol
;
5720 off
= i
.op
[0].disps
->X_add_number
;
5722 if (i
.op
[0].disps
->X_op
!= O_constant
5723 && i
.op
[0].disps
->X_op
!= O_symbol
)
5725 /* Handle complex expressions. */
5726 sym
= make_expr_symbol (i
.op
[0].disps
);
5730 /* 1 possible extra opcode + 4 byte displacement go in var part.
5731 Pass reloc in fr_var. */
5732 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5742 if (i
.tm
.opcode_modifier
.jumpbyte
)
5744 /* This is a loop or jecxz type instruction. */
5746 if (i
.prefix
[ADDR_PREFIX
] != 0)
5748 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5751 /* Pentium4 branch hints. */
5752 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5753 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5755 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5764 if (flag_code
== CODE_16BIT
)
5767 if (i
.prefix
[DATA_PREFIX
] != 0)
5769 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5779 if (i
.prefix
[REX_PREFIX
] != 0)
5781 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5785 if (i
.prefixes
!= 0 && !intel_syntax
)
5786 as_warn (_("skipping prefixes on this instruction"));
5788 p
= frag_more (1 + size
);
5789 *p
++ = i
.tm
.base_opcode
;
5791 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5792 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5794 /* All jumps handled here are signed, but don't use a signed limit
5795 check for 32 and 16 bit jumps as we want to allow wrap around at
5796 4G and 64k respectively. */
5798 fixP
->fx_signed
= 1;
5802 output_interseg_jump (void)
5810 if (flag_code
== CODE_16BIT
)
5814 if (i
.prefix
[DATA_PREFIX
] != 0)
5820 if (i
.prefix
[REX_PREFIX
] != 0)
5830 if (i
.prefixes
!= 0 && !intel_syntax
)
5831 as_warn (_("skipping prefixes on this instruction"));
5833 /* 1 opcode; 2 segment; offset */
5834 p
= frag_more (prefix
+ 1 + 2 + size
);
5836 if (i
.prefix
[DATA_PREFIX
] != 0)
5837 *p
++ = DATA_PREFIX_OPCODE
;
5839 if (i
.prefix
[REX_PREFIX
] != 0)
5840 *p
++ = i
.prefix
[REX_PREFIX
];
5842 *p
++ = i
.tm
.base_opcode
;
5843 if (i
.op
[1].imms
->X_op
== O_constant
)
5845 offsetT n
= i
.op
[1].imms
->X_add_number
;
5848 && !fits_in_unsigned_word (n
)
5849 && !fits_in_signed_word (n
))
5851 as_bad (_("16-bit jump out of range"));
5854 md_number_to_chars (p
, n
, size
);
5857 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5858 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5859 if (i
.op
[0].imms
->X_op
!= O_constant
)
5860 as_bad (_("can't handle non absolute segment in `%s'"),
5862 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5868 fragS
*insn_start_frag
;
5869 offsetT insn_start_off
;
5871 /* Tie dwarf2 debug info to the address at the start of the insn.
5872 We can't do this after the insn has been output as the current
5873 frag may have been closed off. eg. by frag_var. */
5874 dwarf2_emit_insn (0);
5876 insn_start_frag
= frag_now
;
5877 insn_start_off
= frag_now_fix ();
5880 if (i
.tm
.opcode_modifier
.jump
)
5882 else if (i
.tm
.opcode_modifier
.jumpbyte
5883 || i
.tm
.opcode_modifier
.jumpdword
)
5885 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5886 output_interseg_jump ();
5889 /* Output normal instructions here. */
5893 unsigned int prefix
;
5895 /* Since the VEX prefix contains the implicit prefix, we don't
5896 need the explicit prefix. */
5897 if (!i
.tm
.opcode_modifier
.vex
)
5899 switch (i
.tm
.opcode_length
)
5902 if (i
.tm
.base_opcode
& 0xff000000)
5904 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5909 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5911 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5912 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5915 if (prefix
!= REPE_PREFIX_OPCODE
5916 || (i
.prefix
[LOCKREP_PREFIX
]
5917 != REPE_PREFIX_OPCODE
))
5918 add_prefix (prefix
);
5921 add_prefix (prefix
);
5930 /* The prefix bytes. */
5931 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5933 FRAG_APPEND_1_CHAR (*q
);
5936 if (i
.tm
.opcode_modifier
.vex
)
5938 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5943 /* REX byte is encoded in VEX prefix. */
5947 FRAG_APPEND_1_CHAR (*q
);
5950 /* There should be no other prefixes for instructions
5955 /* Now the VEX prefix. */
5956 p
= frag_more (i
.vex
.length
);
5957 for (j
= 0; j
< i
.vex
.length
; j
++)
5958 p
[j
] = i
.vex
.bytes
[j
];
5961 /* Now the opcode; be careful about word order here! */
5962 if (i
.tm
.opcode_length
== 1)
5964 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5968 switch (i
.tm
.opcode_length
)
5972 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5982 /* Put out high byte first: can't use md_number_to_chars! */
5983 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5984 *p
= i
.tm
.base_opcode
& 0xff;
5986 /* On SSE5, encode the OC1 bit in the DREX field if this
5987 encoding has multiple formats. */
5988 if (i
.tm
.opcode_modifier
.drex
5989 && i
.tm
.opcode_modifier
.drexv
5990 && DREX_OC1 (i
.tm
.extension_opcode
))
5991 *p
|= DREX_OC1_MASK
;
5994 /* Now the modrm byte and sib byte (if present). */
5995 if (i
.tm
.opcode_modifier
.modrm
)
5997 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6000 /* If i.rm.regmem == ESP (4)
6001 && i.rm.mode != (Register mode)
6003 ==> need second modrm byte. */
6004 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6006 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6007 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6009 | i
.sib
.scale
<< 6));
6012 /* Write the DREX byte if needed. */
6013 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6016 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6018 /* Encode the OC0 bit if this encoding has multiple
6020 if ((i
.tm
.opcode_modifier
.drex
6021 || i
.tm
.opcode_modifier
.drexv
)
6022 && DREX_OC0 (i
.tm
.extension_opcode
))
6023 *p
|= DREX_OC0_MASK
;
6026 if (i
.disp_operands
)
6027 output_disp (insn_start_frag
, insn_start_off
);
6030 output_imm (insn_start_frag
, insn_start_off
);
6036 pi ("" /*line*/, &i
);
6038 #endif /* DEBUG386 */
6041 /* Return the size of the displacement operand N. */
6044 disp_size (unsigned int n
)
6047 if (i
.types
[n
].bitfield
.disp64
)
6049 else if (i
.types
[n
].bitfield
.disp8
)
6051 else if (i
.types
[n
].bitfield
.disp16
)
6056 /* Return the size of the immediate operand N. */
6059 imm_size (unsigned int n
)
6062 if (i
.types
[n
].bitfield
.imm64
)
6064 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6066 else if (i
.types
[n
].bitfield
.imm16
)
6072 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6077 for (n
= 0; n
< i
.operands
; n
++)
6079 if (operand_type_check (i
.types
[n
], disp
))
6081 if (i
.op
[n
].disps
->X_op
== O_constant
)
6083 int size
= disp_size (n
);
6086 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6088 p
= frag_more (size
);
6089 md_number_to_chars (p
, val
, size
);
6093 enum bfd_reloc_code_real reloc_type
;
6094 int size
= disp_size (n
);
6095 int sign
= i
.types
[n
].bitfield
.disp32s
;
6096 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6098 /* We can't have 8 bit displacement here. */
6099 assert (!i
.types
[n
].bitfield
.disp8
);
6101 /* The PC relative address is computed relative
6102 to the instruction boundary, so in case immediate
6103 fields follows, we need to adjust the value. */
6104 if (pcrel
&& i
.imm_operands
)
6109 for (n1
= 0; n1
< i
.operands
; n1
++)
6110 if (operand_type_check (i
.types
[n1
], imm
))
6112 /* Only one immediate is allowed for PC
6113 relative address. */
6116 i
.op
[n
].disps
->X_add_number
-= sz
;
6118 /* We should find the immediate. */
6122 p
= frag_more (size
);
6123 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6125 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6126 && (((reloc_type
== BFD_RELOC_32
6127 || reloc_type
== BFD_RELOC_X86_64_32S
6128 || (reloc_type
== BFD_RELOC_64
6130 && (i
.op
[n
].disps
->X_op
== O_symbol
6131 || (i
.op
[n
].disps
->X_op
== O_add
6132 && ((symbol_get_value_expression
6133 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6135 || reloc_type
== BFD_RELOC_32_PCREL
))
6139 if (insn_start_frag
== frag_now
)
6140 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6145 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6146 for (fr
= insn_start_frag
->fr_next
;
6147 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6149 add
+= p
- frag_now
->fr_literal
;
6154 reloc_type
= BFD_RELOC_386_GOTPC
;
6155 i
.op
[n
].imms
->X_add_number
+= add
;
6157 else if (reloc_type
== BFD_RELOC_64
)
6158 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6160 /* Don't do the adjustment for x86-64, as there
6161 the pcrel addressing is relative to the _next_
6162 insn, and that is taken care of in other code. */
6163 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6165 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6166 i
.op
[n
].disps
, pcrel
, reloc_type
);
6173 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6178 for (n
= 0; n
< i
.operands
; n
++)
6180 if (operand_type_check (i
.types
[n
], imm
))
6182 if (i
.op
[n
].imms
->X_op
== O_constant
)
6184 int size
= imm_size (n
);
6187 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6189 p
= frag_more (size
);
6190 md_number_to_chars (p
, val
, size
);
6194 /* Not absolute_section.
6195 Need a 32-bit fixup (don't support 8bit
6196 non-absolute imms). Try to support other
6198 enum bfd_reloc_code_real reloc_type
;
6199 int size
= imm_size (n
);
6202 if (i
.types
[n
].bitfield
.imm32s
6203 && (i
.suffix
== QWORD_MNEM_SUFFIX
6204 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6209 p
= frag_more (size
);
6210 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6212 /* This is tough to explain. We end up with this one if we
6213 * have operands that look like
6214 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6215 * obtain the absolute address of the GOT, and it is strongly
6216 * preferable from a performance point of view to avoid using
6217 * a runtime relocation for this. The actual sequence of
6218 * instructions often look something like:
6223 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6225 * The call and pop essentially return the absolute address
6226 * of the label .L66 and store it in %ebx. The linker itself
6227 * will ultimately change the first operand of the addl so
6228 * that %ebx points to the GOT, but to keep things simple, the
6229 * .o file must have this operand set so that it generates not
6230 * the absolute address of .L66, but the absolute address of
6231 * itself. This allows the linker itself simply treat a GOTPC
6232 * relocation as asking for a pcrel offset to the GOT to be
6233 * added in, and the addend of the relocation is stored in the
6234 * operand field for the instruction itself.
6236 * Our job here is to fix the operand so that it would add
6237 * the correct offset so that %ebx would point to itself. The
6238 * thing that is tricky is that .-.L66 will point to the
6239 * beginning of the instruction, so we need to further modify
6240 * the operand so that it will point to itself. There are
6241 * other cases where you have something like:
6243 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6245 * and here no correction would be required. Internally in
6246 * the assembler we treat operands of this form as not being
6247 * pcrel since the '.' is explicitly mentioned, and I wonder
6248 * whether it would simplify matters to do it this way. Who
6249 * knows. In earlier versions of the PIC patches, the
6250 * pcrel_adjust field was used to store the correction, but
6251 * since the expression is not pcrel, I felt it would be
6252 * confusing to do it this way. */
6254 if ((reloc_type
== BFD_RELOC_32
6255 || reloc_type
== BFD_RELOC_X86_64_32S
6256 || reloc_type
== BFD_RELOC_64
)
6258 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6259 && (i
.op
[n
].imms
->X_op
== O_symbol
6260 || (i
.op
[n
].imms
->X_op
== O_add
6261 && ((symbol_get_value_expression
6262 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6267 if (insn_start_frag
== frag_now
)
6268 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6273 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6274 for (fr
= insn_start_frag
->fr_next
;
6275 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6277 add
+= p
- frag_now
->fr_literal
;
6281 reloc_type
= BFD_RELOC_386_GOTPC
;
6283 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6285 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6286 i
.op
[n
].imms
->X_add_number
+= add
;
6288 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6289 i
.op
[n
].imms
, 0, reloc_type
);
6295 /* x86_cons_fix_new is called via the expression parsing code when a
6296 reloc is needed. We use this hook to get the correct .got reloc. */
6297 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6298 static int cons_sign
= -1;
6301 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6304 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6306 got_reloc
= NO_RELOC
;
6309 if (exp
->X_op
== O_secrel
)
6311 exp
->X_op
= O_symbol
;
6312 r
= BFD_RELOC_32_SECREL
;
6316 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6319 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6320 # define lex_got(reloc, adjust, types) NULL
6322 /* Parse operands of the form
6323 <symbol>@GOTOFF+<nnn>
6324 and similar .plt or .got references.
6326 If we find one, set up the correct relocation in RELOC and copy the
6327 input string, minus the `@GOTOFF' into a malloc'd buffer for
6328 parsing by the calling routine. Return this buffer, and if ADJUST
6329 is non-null set it to the length of the string we removed from the
6330 input line. Otherwise return NULL. */
6332 lex_got (enum bfd_reloc_code_real
*reloc
,
6334 i386_operand_type
*types
)
6336 /* Some of the relocations depend on the size of what field is to
6337 be relocated. But in our callers i386_immediate and i386_displacement
6338 we don't yet know the operand size (this will be set by insn
6339 matching). Hence we record the word32 relocation here,
6340 and adjust the reloc according to the real size in reloc(). */
6341 static const struct {
6343 const enum bfd_reloc_code_real rel
[2];
6344 const i386_operand_type types64
;
6347 BFD_RELOC_X86_64_PLTOFF64
},
6348 OPERAND_TYPE_IMM64
},
6349 { "PLT", { BFD_RELOC_386_PLT32
,
6350 BFD_RELOC_X86_64_PLT32
},
6351 OPERAND_TYPE_IMM32_32S_DISP32
},
6353 BFD_RELOC_X86_64_GOTPLT64
},
6354 OPERAND_TYPE_IMM64_DISP64
},
6355 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6356 BFD_RELOC_X86_64_GOTOFF64
},
6357 OPERAND_TYPE_IMM64_DISP64
},
6359 BFD_RELOC_X86_64_GOTPCREL
},
6360 OPERAND_TYPE_IMM32_32S_DISP32
},
6361 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6362 BFD_RELOC_X86_64_TLSGD
},
6363 OPERAND_TYPE_IMM32_32S_DISP32
},
6364 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6366 OPERAND_TYPE_NONE
},
6368 BFD_RELOC_X86_64_TLSLD
},
6369 OPERAND_TYPE_IMM32_32S_DISP32
},
6370 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6371 BFD_RELOC_X86_64_GOTTPOFF
},
6372 OPERAND_TYPE_IMM32_32S_DISP32
},
6373 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6374 BFD_RELOC_X86_64_TPOFF32
},
6375 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6376 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6378 OPERAND_TYPE_NONE
},
6379 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6380 BFD_RELOC_X86_64_DTPOFF32
},
6382 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6383 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6385 OPERAND_TYPE_NONE
},
6386 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6388 OPERAND_TYPE_NONE
},
6389 { "GOT", { BFD_RELOC_386_GOT32
,
6390 BFD_RELOC_X86_64_GOT32
},
6391 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6392 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6393 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6394 OPERAND_TYPE_IMM32_32S_DISP32
},
6395 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6396 BFD_RELOC_X86_64_TLSDESC_CALL
},
6397 OPERAND_TYPE_IMM32_32S_DISP32
},
6405 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6406 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6409 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6413 len
= strlen (gotrel
[j
].str
);
6414 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6416 if (gotrel
[j
].rel
[object_64bit
] != 0)
6419 char *tmpbuf
, *past_reloc
;
6421 *reloc
= gotrel
[j
].rel
[object_64bit
];
6427 if (flag_code
!= CODE_64BIT
)
6429 types
->bitfield
.imm32
= 1;
6430 types
->bitfield
.disp32
= 1;
6433 *types
= gotrel
[j
].types64
;
6436 if (GOT_symbol
== NULL
)
6437 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6439 /* The length of the first part of our input line. */
6440 first
= cp
- input_line_pointer
;
6442 /* The second part goes from after the reloc token until
6443 (and including) an end_of_line char or comma. */
6444 past_reloc
= cp
+ 1 + len
;
6446 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6448 second
= cp
+ 1 - past_reloc
;
6450 /* Allocate and copy string. The trailing NUL shouldn't
6451 be necessary, but be safe. */
6452 tmpbuf
= xmalloc (first
+ second
+ 2);
6453 memcpy (tmpbuf
, input_line_pointer
, first
);
6454 if (second
!= 0 && *past_reloc
!= ' ')
6455 /* Replace the relocation token with ' ', so that
6456 errors like foo@GOTOFF1 will be detected. */
6457 tmpbuf
[first
++] = ' ';
6458 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6459 tmpbuf
[first
+ second
] = '\0';
6463 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6464 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6469 /* Might be a symbol version string. Don't as_bad here. */
6474 x86_cons (expressionS
*exp
, int size
)
6476 if (size
== 4 || (object_64bit
&& size
== 8))
6478 /* Handle @GOTOFF and the like in an expression. */
6480 char *gotfree_input_line
;
6483 save
= input_line_pointer
;
6484 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6485 if (gotfree_input_line
)
6486 input_line_pointer
= gotfree_input_line
;
6490 if (gotfree_input_line
)
6492 /* expression () has merrily parsed up to the end of line,
6493 or a comma - in the wrong buffer. Transfer how far
6494 input_line_pointer has moved to the right buffer. */
6495 input_line_pointer
= (save
6496 + (input_line_pointer
- gotfree_input_line
)
6498 free (gotfree_input_line
);
6499 if (exp
->X_op
== O_constant
6500 || exp
->X_op
== O_absent
6501 || exp
->X_op
== O_illegal
6502 || exp
->X_op
== O_register
6503 || exp
->X_op
== O_big
)
6505 char c
= *input_line_pointer
;
6506 *input_line_pointer
= 0;
6507 as_bad (_("missing or invalid expression `%s'"), save
);
6508 *input_line_pointer
= c
;
6517 static void signed_cons (int size
)
6519 if (flag_code
== CODE_64BIT
)
6527 pe_directive_secrel (dummy
)
6528 int dummy ATTRIBUTE_UNUSED
;
6535 if (exp
.X_op
== O_symbol
)
6536 exp
.X_op
= O_secrel
;
6538 emit_expr (&exp
, 4);
6540 while (*input_line_pointer
++ == ',');
6542 input_line_pointer
--;
6543 demand_empty_rest_of_line ();
6548 i386_immediate (char *imm_start
)
6550 char *save_input_line_pointer
;
6551 char *gotfree_input_line
;
6554 i386_operand_type types
;
6556 operand_type_set (&types
, ~0);
6558 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6560 as_bad (_("at most %d immediate operands are allowed"),
6561 MAX_IMMEDIATE_OPERANDS
);
6565 exp
= &im_expressions
[i
.imm_operands
++];
6566 i
.op
[this_operand
].imms
= exp
;
6568 if (is_space_char (*imm_start
))
6571 save_input_line_pointer
= input_line_pointer
;
6572 input_line_pointer
= imm_start
;
6574 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6575 if (gotfree_input_line
)
6576 input_line_pointer
= gotfree_input_line
;
6578 exp_seg
= expression (exp
);
6581 if (*input_line_pointer
)
6582 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6584 input_line_pointer
= save_input_line_pointer
;
6585 if (gotfree_input_line
)
6586 free (gotfree_input_line
);
6588 if (exp
->X_op
== O_absent
6589 || exp
->X_op
== O_illegal
6590 || exp
->X_op
== O_big
6591 || (gotfree_input_line
6592 && (exp
->X_op
== O_constant
6593 || exp
->X_op
== O_register
)))
6595 as_bad (_("missing or invalid immediate expression `%s'"),
6599 else if (exp
->X_op
== O_constant
)
6601 /* Size it properly later. */
6602 i
.types
[this_operand
].bitfield
.imm64
= 1;
6603 /* If BFD64, sign extend val. */
6604 if (!use_rela_relocations
6605 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6607 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6609 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6610 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6611 && exp_seg
!= absolute_section
6612 && exp_seg
!= text_section
6613 && exp_seg
!= data_section
6614 && exp_seg
!= bss_section
6615 && exp_seg
!= undefined_section
6616 && !bfd_is_com_section (exp_seg
))
6618 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6622 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6624 as_bad (_("illegal immediate register operand %s"), imm_start
);
6629 /* This is an address. The size of the address will be
6630 determined later, depending on destination register,
6631 suffix, or the default for the section. */
6632 i
.types
[this_operand
].bitfield
.imm8
= 1;
6633 i
.types
[this_operand
].bitfield
.imm16
= 1;
6634 i
.types
[this_operand
].bitfield
.imm32
= 1;
6635 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6636 i
.types
[this_operand
].bitfield
.imm64
= 1;
6637 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6645 i386_scale (char *scale
)
6648 char *save
= input_line_pointer
;
6650 input_line_pointer
= scale
;
6651 val
= get_absolute_expression ();
6656 i
.log2_scale_factor
= 0;
6659 i
.log2_scale_factor
= 1;
6662 i
.log2_scale_factor
= 2;
6665 i
.log2_scale_factor
= 3;
6669 char sep
= *input_line_pointer
;
6671 *input_line_pointer
= '\0';
6672 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6674 *input_line_pointer
= sep
;
6675 input_line_pointer
= save
;
6679 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6681 as_warn (_("scale factor of %d without an index register"),
6682 1 << i
.log2_scale_factor
);
6683 i
.log2_scale_factor
= 0;
6685 scale
= input_line_pointer
;
6686 input_line_pointer
= save
;
6691 i386_displacement (char *disp_start
, char *disp_end
)
6695 char *save_input_line_pointer
;
6696 char *gotfree_input_line
;
6698 i386_operand_type bigdisp
, types
= anydisp
;
6701 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6703 as_bad (_("at most %d displacement operands are allowed"),
6704 MAX_MEMORY_OPERANDS
);
6708 operand_type_set (&bigdisp
, 0);
6709 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6710 || (!current_templates
->start
->opcode_modifier
.jump
6711 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6713 bigdisp
.bitfield
.disp32
= 1;
6714 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6715 if (flag_code
== CODE_64BIT
)
6719 bigdisp
.bitfield
.disp32s
= 1;
6720 bigdisp
.bitfield
.disp64
= 1;
6723 else if ((flag_code
== CODE_16BIT
) ^ override
)
6725 bigdisp
.bitfield
.disp32
= 0;
6726 bigdisp
.bitfield
.disp16
= 1;
6731 /* For PC-relative branches, the width of the displacement
6732 is dependent upon data size, not address size. */
6733 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6734 if (flag_code
== CODE_64BIT
)
6736 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6737 bigdisp
.bitfield
.disp16
= 1;
6740 bigdisp
.bitfield
.disp32
= 1;
6741 bigdisp
.bitfield
.disp32s
= 1;
6747 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6749 : LONG_MNEM_SUFFIX
));
6750 bigdisp
.bitfield
.disp32
= 1;
6751 if ((flag_code
== CODE_16BIT
) ^ override
)
6753 bigdisp
.bitfield
.disp32
= 0;
6754 bigdisp
.bitfield
.disp16
= 1;
6758 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6761 exp
= &disp_expressions
[i
.disp_operands
];
6762 i
.op
[this_operand
].disps
= exp
;
6764 save_input_line_pointer
= input_line_pointer
;
6765 input_line_pointer
= disp_start
;
6766 END_STRING_AND_SAVE (disp_end
);
6768 #ifndef GCC_ASM_O_HACK
6769 #define GCC_ASM_O_HACK 0
6772 END_STRING_AND_SAVE (disp_end
+ 1);
6773 if (i
.types
[this_operand
].bitfield
.baseIndex
6774 && displacement_string_end
[-1] == '+')
6776 /* This hack is to avoid a warning when using the "o"
6777 constraint within gcc asm statements.
6780 #define _set_tssldt_desc(n,addr,limit,type) \
6781 __asm__ __volatile__ ( \
6783 "movw %w1,2+%0\n\t" \
6785 "movb %b1,4+%0\n\t" \
6786 "movb %4,5+%0\n\t" \
6787 "movb $0,6+%0\n\t" \
6788 "movb %h1,7+%0\n\t" \
6790 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6792 This works great except that the output assembler ends
6793 up looking a bit weird if it turns out that there is
6794 no offset. You end up producing code that looks like:
6807 So here we provide the missing zero. */
6809 *displacement_string_end
= '0';
6812 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6813 if (gotfree_input_line
)
6814 input_line_pointer
= gotfree_input_line
;
6816 exp_seg
= expression (exp
);
6819 if (*input_line_pointer
)
6820 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6822 RESTORE_END_STRING (disp_end
+ 1);
6824 input_line_pointer
= save_input_line_pointer
;
6825 if (gotfree_input_line
)
6826 free (gotfree_input_line
);
6829 /* We do this to make sure that the section symbol is in
6830 the symbol table. We will ultimately change the relocation
6831 to be relative to the beginning of the section. */
6832 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6833 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6834 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6836 if (exp
->X_op
!= O_symbol
)
6839 if (S_IS_LOCAL (exp
->X_add_symbol
)
6840 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6841 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6842 exp
->X_op
= O_subtract
;
6843 exp
->X_op_symbol
= GOT_symbol
;
6844 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6845 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6846 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6847 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6849 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6852 else if (exp
->X_op
== O_absent
6853 || exp
->X_op
== O_illegal
6854 || exp
->X_op
== O_big
6855 || (gotfree_input_line
6856 && (exp
->X_op
== O_constant
6857 || exp
->X_op
== O_register
)))
6860 as_bad (_("missing or invalid displacement expression `%s'"),
6865 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6866 else if (exp
->X_op
!= O_constant
6867 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6868 && exp_seg
!= absolute_section
6869 && exp_seg
!= text_section
6870 && exp_seg
!= data_section
6871 && exp_seg
!= bss_section
6872 && exp_seg
!= undefined_section
6873 && !bfd_is_com_section (exp_seg
))
6875 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6880 RESTORE_END_STRING (disp_end
);
6882 /* Check if this is a displacement only operand. */
6883 bigdisp
= i
.types
[this_operand
];
6884 bigdisp
.bitfield
.disp8
= 0;
6885 bigdisp
.bitfield
.disp16
= 0;
6886 bigdisp
.bitfield
.disp32
= 0;
6887 bigdisp
.bitfield
.disp32s
= 0;
6888 bigdisp
.bitfield
.disp64
= 0;
6889 if (operand_type_all_zero (&bigdisp
))
6890 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6896 /* Make sure the memory operand we've been dealt is valid.
6897 Return 1 on success, 0 on a failure. */
6900 i386_index_check (const char *operand_string
)
6903 const char *kind
= "base/index";
6904 #if INFER_ADDR_PREFIX
6910 if (current_templates
->start
->opcode_modifier
.isstring
6911 && !current_templates
->start
->opcode_modifier
.immext
6912 && (current_templates
->end
[-1].opcode_modifier
.isstring
6915 /* Memory operands of string insns are special in that they only allow
6916 a single register (rDI, rSI, or rBX) as their memory address. */
6917 unsigned int expected
;
6919 kind
= "string address";
6921 if (current_templates
->start
->opcode_modifier
.w
)
6923 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6925 if (!type
.bitfield
.baseindex
6926 || ((!i
.mem_operands
!= !intel_syntax
)
6927 && current_templates
->end
[-1].operand_types
[1]
6928 .bitfield
.baseindex
))
6929 type
= current_templates
->end
[-1].operand_types
[1];
6930 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6933 expected
= 3 /* rBX */;
6935 if (!i
.base_reg
|| i
.index_reg
6936 || operand_type_check (i
.types
[this_operand
], disp
))
6938 else if (!(flag_code
== CODE_64BIT
6939 ? i
.prefix
[ADDR_PREFIX
]
6940 ? i
.base_reg
->reg_type
.bitfield
.reg32
6941 : i
.base_reg
->reg_type
.bitfield
.reg64
6942 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6943 ? i
.base_reg
->reg_type
.bitfield
.reg32
6944 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6946 else if (i
.base_reg
->reg_num
!= expected
)
6953 for (j
= 0; j
< i386_regtab_size
; ++j
)
6954 if ((flag_code
== CODE_64BIT
6955 ? i
.prefix
[ADDR_PREFIX
]
6956 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6957 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6958 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6959 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6960 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6961 && i386_regtab
[j
].reg_num
== expected
)
6963 assert (j
< i386_regtab_size
);
6964 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6966 intel_syntax
? '[' : '(',
6968 i386_regtab
[j
].reg_name
,
6969 intel_syntax
? ']' : ')');
6973 else if (flag_code
== CODE_64BIT
)
6976 && ((i
.prefix
[ADDR_PREFIX
] == 0
6977 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6978 || (i
.prefix
[ADDR_PREFIX
]
6979 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6981 || i
.base_reg
->reg_num
!=
6982 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6984 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6985 || (i
.prefix
[ADDR_PREFIX
] == 0
6986 && i
.index_reg
->reg_num
!= RegRiz
6987 && !i
.index_reg
->reg_type
.bitfield
.reg64
6989 || (i
.prefix
[ADDR_PREFIX
]
6990 && i
.index_reg
->reg_num
!= RegEiz
6991 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6996 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7000 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7001 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7003 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7004 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7006 && i
.base_reg
->reg_num
< 6
7007 && i
.index_reg
->reg_num
>= 6
7008 && i
.log2_scale_factor
== 0))))
7015 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7017 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7018 && i
.index_reg
->reg_num
!= RegEiz
)
7019 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7025 #if INFER_ADDR_PREFIX
7026 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7028 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7030 /* Change the size of any displacement too. At most one of
7031 Disp16 or Disp32 is set.
7032 FIXME. There doesn't seem to be any real need for separate
7033 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7034 Removing them would probably clean up the code quite a lot. */
7035 if (flag_code
!= CODE_64BIT
7036 && (i
.types
[this_operand
].bitfield
.disp16
7037 || i
.types
[this_operand
].bitfield
.disp32
))
7038 i
.types
[this_operand
]
7039 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7044 as_bad (_("`%s' is not a valid %s expression"),
7049 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7051 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7052 ? flag_code
== CODE_32BIT
7061 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7065 i386_att_operand (char *operand_string
)
7069 char *op_string
= operand_string
;
7071 if (is_space_char (*op_string
))
7074 /* We check for an absolute prefix (differentiating,
7075 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7076 if (*op_string
== ABSOLUTE_PREFIX
)
7079 if (is_space_char (*op_string
))
7081 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7084 /* Check if operand is a register. */
7085 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7087 i386_operand_type temp
;
7089 /* Check for a segment override by searching for ':' after a
7090 segment register. */
7092 if (is_space_char (*op_string
))
7094 if (*op_string
== ':'
7095 && (r
->reg_type
.bitfield
.sreg2
7096 || r
->reg_type
.bitfield
.sreg3
))
7101 i
.seg
[i
.mem_operands
] = &es
;
7104 i
.seg
[i
.mem_operands
] = &cs
;
7107 i
.seg
[i
.mem_operands
] = &ss
;
7110 i
.seg
[i
.mem_operands
] = &ds
;
7113 i
.seg
[i
.mem_operands
] = &fs
;
7116 i
.seg
[i
.mem_operands
] = &gs
;
7120 /* Skip the ':' and whitespace. */
7122 if (is_space_char (*op_string
))
7125 if (!is_digit_char (*op_string
)
7126 && !is_identifier_char (*op_string
)
7127 && *op_string
!= '('
7128 && *op_string
!= ABSOLUTE_PREFIX
)
7130 as_bad (_("bad memory operand `%s'"), op_string
);
7133 /* Handle case of %es:*foo. */
7134 if (*op_string
== ABSOLUTE_PREFIX
)
7137 if (is_space_char (*op_string
))
7139 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7141 goto do_memory_reference
;
7145 as_bad (_("junk `%s' after register"), op_string
);
7149 temp
.bitfield
.baseindex
= 0;
7150 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7152 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7153 i
.op
[this_operand
].regs
= r
;
7156 else if (*op_string
== REGISTER_PREFIX
)
7158 as_bad (_("bad register name `%s'"), op_string
);
7161 else if (*op_string
== IMMEDIATE_PREFIX
)
7164 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7166 as_bad (_("immediate operand illegal with absolute jump"));
7169 if (!i386_immediate (op_string
))
7172 else if (is_digit_char (*op_string
)
7173 || is_identifier_char (*op_string
)
7174 || *op_string
== '(')
7176 /* This is a memory reference of some sort. */
7179 /* Start and end of displacement string expression (if found). */
7180 char *displacement_string_start
;
7181 char *displacement_string_end
;
7183 do_memory_reference
:
7184 if ((i
.mem_operands
== 1
7185 && !current_templates
->start
->opcode_modifier
.isstring
)
7186 || i
.mem_operands
== 2)
7188 as_bad (_("too many memory references for `%s'"),
7189 current_templates
->start
->name
);
7193 /* Check for base index form. We detect the base index form by
7194 looking for an ')' at the end of the operand, searching
7195 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7197 base_string
= op_string
+ strlen (op_string
);
7200 if (is_space_char (*base_string
))
7203 /* If we only have a displacement, set-up for it to be parsed later. */
7204 displacement_string_start
= op_string
;
7205 displacement_string_end
= base_string
+ 1;
7207 if (*base_string
== ')')
7210 unsigned int parens_balanced
= 1;
7211 /* We've already checked that the number of left & right ()'s are
7212 equal, so this loop will not be infinite. */
7216 if (*base_string
== ')')
7218 if (*base_string
== '(')
7221 while (parens_balanced
);
7223 temp_string
= base_string
;
7225 /* Skip past '(' and whitespace. */
7227 if (is_space_char (*base_string
))
7230 if (*base_string
== ','
7231 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7234 displacement_string_end
= temp_string
;
7236 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7240 base_string
= end_op
;
7241 if (is_space_char (*base_string
))
7245 /* There may be an index reg or scale factor here. */
7246 if (*base_string
== ',')
7249 if (is_space_char (*base_string
))
7252 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7255 base_string
= end_op
;
7256 if (is_space_char (*base_string
))
7258 if (*base_string
== ',')
7261 if (is_space_char (*base_string
))
7264 else if (*base_string
!= ')')
7266 as_bad (_("expecting `,' or `)' "
7267 "after index register in `%s'"),
7272 else if (*base_string
== REGISTER_PREFIX
)
7274 as_bad (_("bad register name `%s'"), base_string
);
7278 /* Check for scale factor. */
7279 if (*base_string
!= ')')
7281 char *end_scale
= i386_scale (base_string
);
7286 base_string
= end_scale
;
7287 if (is_space_char (*base_string
))
7289 if (*base_string
!= ')')
7291 as_bad (_("expecting `)' "
7292 "after scale factor in `%s'"),
7297 else if (!i
.index_reg
)
7299 as_bad (_("expecting index register or scale factor "
7300 "after `,'; got '%c'"),
7305 else if (*base_string
!= ')')
7307 as_bad (_("expecting `,' or `)' "
7308 "after base register in `%s'"),
7313 else if (*base_string
== REGISTER_PREFIX
)
7315 as_bad (_("bad register name `%s'"), base_string
);
7320 /* If there's an expression beginning the operand, parse it,
7321 assuming displacement_string_start and
7322 displacement_string_end are meaningful. */
7323 if (displacement_string_start
!= displacement_string_end
)
7325 if (!i386_displacement (displacement_string_start
,
7326 displacement_string_end
))
7330 /* Special case for (%dx) while doing input/output op. */
7332 && operand_type_equal (&i
.base_reg
->reg_type
,
7333 ®16_inoutportreg
)
7335 && i
.log2_scale_factor
== 0
7336 && i
.seg
[i
.mem_operands
] == 0
7337 && !operand_type_check (i
.types
[this_operand
], disp
))
7339 i
.types
[this_operand
] = inoutportreg
;
7343 if (i386_index_check (operand_string
) == 0)
7345 i
.types
[this_operand
].bitfield
.mem
= 1;
7350 /* It's not a memory operand; argh! */
7351 as_bad (_("invalid char %s beginning operand %d `%s'"),
7352 output_invalid (*op_string
),
7357 return 1; /* Normal return. */
7360 /* md_estimate_size_before_relax()
7362 Called just before relax() for rs_machine_dependent frags. The x86
7363 assembler uses these frags to handle variable size jump
7366 Any symbol that is now undefined will not become defined.
7367 Return the correct fr_subtype in the frag.
7368 Return the initial "guess for variable size of frag" to caller.
7369 The guess is actually the growth beyond the fixed part. Whatever
7370 we do to grow the fixed or variable part contributes to our
7374 md_estimate_size_before_relax (fragP
, segment
)
7378 /* We've already got fragP->fr_subtype right; all we have to do is
7379 check for un-relaxable symbols. On an ELF system, we can't relax
7380 an externally visible symbol, because it may be overridden by a
7382 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7385 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7386 || S_IS_WEAK (fragP
->fr_symbol
)))
7390 /* Symbol is undefined in this segment, or we need to keep a
7391 reloc so that weak symbols can be overridden. */
7392 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7393 enum bfd_reloc_code_real reloc_type
;
7394 unsigned char *opcode
;
7397 if (fragP
->fr_var
!= NO_RELOC
)
7398 reloc_type
= fragP
->fr_var
;
7400 reloc_type
= BFD_RELOC_16_PCREL
;
7402 reloc_type
= BFD_RELOC_32_PCREL
;
7404 old_fr_fix
= fragP
->fr_fix
;
7405 opcode
= (unsigned char *) fragP
->fr_opcode
;
7407 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7410 /* Make jmp (0xeb) a (d)word displacement jump. */
7412 fragP
->fr_fix
+= size
;
7413 fix_new (fragP
, old_fr_fix
, size
,
7415 fragP
->fr_offset
, 1,
7421 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7423 /* Negate the condition, and branch past an
7424 unconditional jump. */
7427 /* Insert an unconditional jump. */
7429 /* We added two extra opcode bytes, and have a two byte
7431 fragP
->fr_fix
+= 2 + 2;
7432 fix_new (fragP
, old_fr_fix
+ 2, 2,
7434 fragP
->fr_offset
, 1,
7441 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7446 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7448 fragP
->fr_offset
, 1,
7450 fixP
->fx_signed
= 1;
7454 /* This changes the byte-displacement jump 0x7N
7455 to the (d)word-displacement jump 0x0f,0x8N. */
7456 opcode
[1] = opcode
[0] + 0x10;
7457 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7458 /* We've added an opcode byte. */
7459 fragP
->fr_fix
+= 1 + size
;
7460 fix_new (fragP
, old_fr_fix
+ 1, size
,
7462 fragP
->fr_offset
, 1,
7467 BAD_CASE (fragP
->fr_subtype
);
7471 return fragP
->fr_fix
- old_fr_fix
;
7474 /* Guess size depending on current relax state. Initially the relax
7475 state will correspond to a short jump and we return 1, because
7476 the variable part of the frag (the branch offset) is one byte
7477 long. However, we can relax a section more than once and in that
7478 case we must either set fr_subtype back to the unrelaxed state,
7479 or return the value for the appropriate branch. */
7480 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7483 /* Called after relax() is finished.
7485 In: Address of frag.
7486 fr_type == rs_machine_dependent.
7487 fr_subtype is what the address relaxed to.
7489 Out: Any fixSs and constants are set up.
7490 Caller will turn frag into a ".space 0". */
7493 md_convert_frag (abfd
, sec
, fragP
)
7494 bfd
*abfd ATTRIBUTE_UNUSED
;
7495 segT sec ATTRIBUTE_UNUSED
;
7498 unsigned char *opcode
;
7499 unsigned char *where_to_put_displacement
= NULL
;
7500 offsetT target_address
;
7501 offsetT opcode_address
;
7502 unsigned int extension
= 0;
7503 offsetT displacement_from_opcode_start
;
7505 opcode
= (unsigned char *) fragP
->fr_opcode
;
7507 /* Address we want to reach in file space. */
7508 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7510 /* Address opcode resides at in file space. */
7511 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7513 /* Displacement from opcode start to fill into instruction. */
7514 displacement_from_opcode_start
= target_address
- opcode_address
;
7516 if ((fragP
->fr_subtype
& BIG
) == 0)
7518 /* Don't have to change opcode. */
7519 extension
= 1; /* 1 opcode + 1 displacement */
7520 where_to_put_displacement
= &opcode
[1];
7524 if (no_cond_jump_promotion
7525 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7526 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7527 _("long jump required"));
7529 switch (fragP
->fr_subtype
)
7531 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7532 extension
= 4; /* 1 opcode + 4 displacement */
7534 where_to_put_displacement
= &opcode
[1];
7537 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7538 extension
= 2; /* 1 opcode + 2 displacement */
7540 where_to_put_displacement
= &opcode
[1];
7543 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7544 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7545 extension
= 5; /* 2 opcode + 4 displacement */
7546 opcode
[1] = opcode
[0] + 0x10;
7547 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7548 where_to_put_displacement
= &opcode
[2];
7551 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7552 extension
= 3; /* 2 opcode + 2 displacement */
7553 opcode
[1] = opcode
[0] + 0x10;
7554 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7555 where_to_put_displacement
= &opcode
[2];
7558 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7563 where_to_put_displacement
= &opcode
[3];
7567 BAD_CASE (fragP
->fr_subtype
);
7572 /* If size if less then four we are sure that the operand fits,
7573 but if it's 4, then it could be that the displacement is larger
7575 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7577 && ((addressT
) (displacement_from_opcode_start
- extension
7578 + ((addressT
) 1 << 31))
7579 > (((addressT
) 2 << 31) - 1)))
7581 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7582 _("jump target out of range"));
7583 /* Make us emit 0. */
7584 displacement_from_opcode_start
= extension
;
7586 /* Now put displacement after opcode. */
7587 md_number_to_chars ((char *) where_to_put_displacement
,
7588 (valueT
) (displacement_from_opcode_start
- extension
),
7589 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7590 fragP
->fr_fix
+= extension
;
7593 /* Apply a fixup (fixS) to segment data, once it has been determined
7594 by our caller that we have all the info we need to fix it up.
7596 On the 386, immediates, displacements, and data pointers are all in
7597 the same (little-endian) format, so we don't need to care about which
7601 md_apply_fix (fixP
, valP
, seg
)
7602 /* The fix we're to put in. */
7604 /* Pointer to the value of the bits. */
7606 /* Segment fix is from. */
7607 segT seg ATTRIBUTE_UNUSED
;
7609 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7610 valueT value
= *valP
;
7612 #if !defined (TE_Mach)
7615 switch (fixP
->fx_r_type
)
7621 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7624 case BFD_RELOC_X86_64_32S
:
7625 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7628 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7631 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7636 if (fixP
->fx_addsy
!= NULL
7637 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7638 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7639 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7640 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7641 && !use_rela_relocations
)
7643 /* This is a hack. There should be a better way to handle this.
7644 This covers for the fact that bfd_install_relocation will
7645 subtract the current location (for partial_inplace, PC relative
7646 relocations); see more below. */
7650 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7653 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7658 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7661 || (symbol_section_p (fixP
->fx_addsy
)
7662 && sym_seg
!= absolute_section
))
7663 && !generic_force_reloc (fixP
))
7665 /* Yes, we add the values in twice. This is because
7666 bfd_install_relocation subtracts them out again. I think
7667 bfd_install_relocation is broken, but I don't dare change
7669 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7673 #if defined (OBJ_COFF) && defined (TE_PE)
7674 /* For some reason, the PE format does not store a
7675 section address offset for a PC relative symbol. */
7676 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7677 || S_IS_WEAK (fixP
->fx_addsy
))
7678 value
+= md_pcrel_from (fixP
);
7682 /* Fix a few things - the dynamic linker expects certain values here,
7683 and we must not disappoint it. */
7684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7685 if (IS_ELF
&& fixP
->fx_addsy
)
7686 switch (fixP
->fx_r_type
)
7688 case BFD_RELOC_386_PLT32
:
7689 case BFD_RELOC_X86_64_PLT32
:
7690 /* Make the jump instruction point to the address of the operand. At
7691 runtime we merely add the offset to the actual PLT entry. */
7695 case BFD_RELOC_386_TLS_GD
:
7696 case BFD_RELOC_386_TLS_LDM
:
7697 case BFD_RELOC_386_TLS_IE_32
:
7698 case BFD_RELOC_386_TLS_IE
:
7699 case BFD_RELOC_386_TLS_GOTIE
:
7700 case BFD_RELOC_386_TLS_GOTDESC
:
7701 case BFD_RELOC_X86_64_TLSGD
:
7702 case BFD_RELOC_X86_64_TLSLD
:
7703 case BFD_RELOC_X86_64_GOTTPOFF
:
7704 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7705 value
= 0; /* Fully resolved at runtime. No addend. */
7707 case BFD_RELOC_386_TLS_LE
:
7708 case BFD_RELOC_386_TLS_LDO_32
:
7709 case BFD_RELOC_386_TLS_LE_32
:
7710 case BFD_RELOC_X86_64_DTPOFF32
:
7711 case BFD_RELOC_X86_64_DTPOFF64
:
7712 case BFD_RELOC_X86_64_TPOFF32
:
7713 case BFD_RELOC_X86_64_TPOFF64
:
7714 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7717 case BFD_RELOC_386_TLS_DESC_CALL
:
7718 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7719 value
= 0; /* Fully resolved at runtime. No addend. */
7720 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7724 case BFD_RELOC_386_GOT32
:
7725 case BFD_RELOC_X86_64_GOT32
:
7726 value
= 0; /* Fully resolved at runtime. No addend. */
7729 case BFD_RELOC_VTABLE_INHERIT
:
7730 case BFD_RELOC_VTABLE_ENTRY
:
7737 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7739 #endif /* !defined (TE_Mach) */
7741 /* Are we finished with this relocation now? */
7742 if (fixP
->fx_addsy
== NULL
)
7744 else if (use_rela_relocations
)
7746 fixP
->fx_no_overflow
= 1;
7747 /* Remember value for tc_gen_reloc. */
7748 fixP
->fx_addnumber
= value
;
7752 md_number_to_chars (p
, value
, fixP
->fx_size
);
7756 md_atof (int type
, char *litP
, int *sizeP
)
7758 /* This outputs the LITTLENUMs in REVERSE order;
7759 in accord with the bigendian 386. */
7760 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7763 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7766 output_invalid (int c
)
7769 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7772 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7773 "(0x%x)", (unsigned char) c
);
7774 return output_invalid_buf
;
7777 /* REG_STRING starts *before* REGISTER_PREFIX. */
7779 static const reg_entry
*
7780 parse_real_register (char *reg_string
, char **end_op
)
7782 char *s
= reg_string
;
7784 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7787 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7788 if (*s
== REGISTER_PREFIX
)
7791 if (is_space_char (*s
))
7795 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7797 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7798 return (const reg_entry
*) NULL
;
7802 /* For naked regs, make sure that we are not dealing with an identifier.
7803 This prevents confusing an identifier like `eax_var' with register
7805 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7806 return (const reg_entry
*) NULL
;
7810 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7812 /* Handle floating point regs, allowing spaces in the (i) part. */
7813 if (r
== i386_regtab
/* %st is first entry of table */)
7815 if (is_space_char (*s
))
7820 if (is_space_char (*s
))
7822 if (*s
>= '0' && *s
<= '7')
7826 if (is_space_char (*s
))
7831 r
= hash_find (reg_hash
, "st(0)");
7836 /* We have "%st(" then garbage. */
7837 return (const reg_entry
*) NULL
;
7841 if (r
== NULL
|| allow_pseudo_reg
)
7844 if (operand_type_all_zero (&r
->reg_type
))
7845 return (const reg_entry
*) NULL
;
7847 if ((r
->reg_type
.bitfield
.reg32
7848 || r
->reg_type
.bitfield
.sreg3
7849 || r
->reg_type
.bitfield
.control
7850 || r
->reg_type
.bitfield
.debug
7851 || r
->reg_type
.bitfield
.test
)
7852 && !cpu_arch_flags
.bitfield
.cpui386
)
7853 return (const reg_entry
*) NULL
;
7855 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7856 return (const reg_entry
*) NULL
;
7858 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7859 return (const reg_entry
*) NULL
;
7861 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7862 return (const reg_entry
*) NULL
;
7864 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7865 if (!allow_index_reg
7866 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7867 return (const reg_entry
*) NULL
;
7869 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7870 || r
->reg_type
.bitfield
.reg64
)
7871 && (!cpu_arch_flags
.bitfield
.cpulm
7872 || !operand_type_equal (&r
->reg_type
, &control
))
7873 && flag_code
!= CODE_64BIT
)
7874 return (const reg_entry
*) NULL
;
7876 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7877 return (const reg_entry
*) NULL
;
7882 /* REG_STRING starts *before* REGISTER_PREFIX. */
7884 static const reg_entry
*
7885 parse_register (char *reg_string
, char **end_op
)
7889 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7890 r
= parse_real_register (reg_string
, end_op
);
7895 char *save
= input_line_pointer
;
7899 input_line_pointer
= reg_string
;
7900 c
= get_symbol_end ();
7901 symbolP
= symbol_find (reg_string
);
7902 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7904 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7906 know (e
->X_op
== O_register
);
7907 know (e
->X_add_number
>= 0
7908 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7909 r
= i386_regtab
+ e
->X_add_number
;
7910 *end_op
= input_line_pointer
;
7912 *input_line_pointer
= c
;
7913 input_line_pointer
= save
;
7919 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7922 char *end
= input_line_pointer
;
7925 r
= parse_register (name
, &input_line_pointer
);
7926 if (r
&& end
<= input_line_pointer
)
7928 *nextcharP
= *input_line_pointer
;
7929 *input_line_pointer
= 0;
7930 e
->X_op
= O_register
;
7931 e
->X_add_number
= r
- i386_regtab
;
7934 input_line_pointer
= end
;
7940 md_operand (expressionS
*e
)
7942 if (*input_line_pointer
== REGISTER_PREFIX
)
7945 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7949 e
->X_op
= O_register
;
7950 e
->X_add_number
= r
- i386_regtab
;
7951 input_line_pointer
= end
;
7957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7958 const char *md_shortopts
= "kVQ:sqn";
7960 const char *md_shortopts
= "qn";
7963 #define OPTION_32 (OPTION_MD_BASE + 0)
7964 #define OPTION_64 (OPTION_MD_BASE + 1)
7965 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7966 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7967 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7968 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7969 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7970 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7971 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7972 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7973 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7974 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7976 struct option md_longopts
[] =
7978 {"32", no_argument
, NULL
, OPTION_32
},
7979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7980 {"64", no_argument
, NULL
, OPTION_64
},
7982 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7983 {"march", required_argument
, NULL
, OPTION_MARCH
},
7984 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7985 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7986 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7987 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7988 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7989 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7990 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7991 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7992 {NULL
, no_argument
, NULL
, 0}
7994 size_t md_longopts_size
= sizeof (md_longopts
);
7997 md_parse_option (int c
, char *arg
)
8005 optimize_align_code
= 0;
8012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8013 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8014 should be emitted or not. FIXME: Not implemented. */
8018 /* -V: SVR4 argument to print version ID. */
8020 print_version_id ();
8023 /* -k: Ignore for FreeBSD compatibility. */
8028 /* -s: On i386 Solaris, this tells the native assembler to use
8029 .stab instead of .stab.excl. We always use .stab anyhow. */
8032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8035 const char **list
, **l
;
8037 list
= bfd_target_list ();
8038 for (l
= list
; *l
!= NULL
; l
++)
8039 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8040 || strcmp (*l
, "coff-x86-64") == 0
8041 || strcmp (*l
, "pe-x86-64") == 0
8042 || strcmp (*l
, "pei-x86-64") == 0)
8044 default_arch
= "x86_64";
8048 as_fatal (_("No compiled in support for x86_64"));
8055 default_arch
= "i386";
8059 #ifdef SVR4_COMMENT_CHARS
8064 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8066 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8070 i386_comment_chars
= n
;
8076 arch
= xstrdup (arg
);
8080 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8081 next
= strchr (arch
, '+');
8084 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8086 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8089 cpu_arch_name
= cpu_arch
[i
].name
;
8090 cpu_sub_arch_name
= NULL
;
8091 cpu_arch_flags
= cpu_arch
[i
].flags
;
8092 cpu_arch_isa
= cpu_arch
[i
].type
;
8093 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8094 if (!cpu_arch_tune_set
)
8096 cpu_arch_tune
= cpu_arch_isa
;
8097 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8101 else if (*cpu_arch
[i
].name
== '.'
8102 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8104 /* ISA entension. */
8105 i386_cpu_flags flags
;
8106 flags
= cpu_flags_or (cpu_arch_flags
,
8108 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8110 if (cpu_sub_arch_name
)
8112 char *name
= cpu_sub_arch_name
;
8113 cpu_sub_arch_name
= concat (name
,
8115 (const char *) NULL
);
8119 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8120 cpu_arch_flags
= flags
;
8126 if (i
>= ARRAY_SIZE (cpu_arch
))
8127 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8131 while (next
!= NULL
);
8136 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8137 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8139 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8141 cpu_arch_tune_set
= 1;
8142 cpu_arch_tune
= cpu_arch
[i
].type
;
8143 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8147 if (i
>= ARRAY_SIZE (cpu_arch
))
8148 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8151 case OPTION_MMNEMONIC
:
8152 if (strcasecmp (arg
, "att") == 0)
8154 else if (strcasecmp (arg
, "intel") == 0)
8157 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8160 case OPTION_MSYNTAX
:
8161 if (strcasecmp (arg
, "att") == 0)
8163 else if (strcasecmp (arg
, "intel") == 0)
8166 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8169 case OPTION_MINDEX_REG
:
8170 allow_index_reg
= 1;
8173 case OPTION_MNAKED_REG
:
8174 allow_naked_reg
= 1;
8177 case OPTION_MOLD_GCC
:
8181 case OPTION_MSSE2AVX
:
8185 case OPTION_MSSE_CHECK
:
8186 if (strcasecmp (arg
, "error") == 0)
8187 sse_check
= sse_check_error
;
8188 else if (strcasecmp (arg
, "warning") == 0)
8189 sse_check
= sse_check_warning
;
8190 else if (strcasecmp (arg
, "none") == 0)
8191 sse_check
= sse_check_none
;
8193 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8203 md_show_usage (stream
)
8206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8207 fprintf (stream
, _("\
8209 -V print assembler version number\n\
8212 fprintf (stream
, _("\
8213 -n Do not optimize code alignment\n\
8214 -q quieten some warnings\n"));
8215 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8216 fprintf (stream
, _("\
8219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8220 fprintf (stream
, _("\
8221 --32/--64 generate 32bit/64bit code\n"));
8223 #ifdef SVR4_COMMENT_CHARS
8224 fprintf (stream
, _("\
8225 --divide do not treat `/' as a comment character\n"));
8227 fprintf (stream
, _("\
8228 --divide ignored\n"));
8230 fprintf (stream
, _("\
8231 -march=CPU[,+EXTENSION...]\n\
8232 generate code for CPU and EXTENSION, CPU is one of:\n\
8233 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8234 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8235 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8236 generic32, generic64\n\
8237 EXTENSION is combination of:\n\
8238 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8239 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8240 rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\
8242 fprintf (stream
, _("\
8243 -mtune=CPU optimize for CPU, CPU is one of:\n\
8244 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8245 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8246 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8247 generic32, generic64\n"));
8248 fprintf (stream
, _("\
8249 -msse2avx encode SSE instructions with VEX prefix\n"));
8250 fprintf (stream
, _("\
8251 -msse-check=[none|error|warning]\n\
8252 check SSE instructions\n"));
8253 fprintf (stream
, _("\
8254 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8255 fprintf (stream
, _("\
8256 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8257 fprintf (stream
, _("\
8258 -mindex-reg support pseudo index registers\n"));
8259 fprintf (stream
, _("\
8260 -mnaked-reg don't require `%%' prefix for registers\n"));
8261 fprintf (stream
, _("\
8262 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8265 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8266 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8268 /* Pick the target format to use. */
8271 i386_target_format (void)
8273 if (!strcmp (default_arch
, "x86_64"))
8275 set_code_flag (CODE_64BIT
);
8276 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8278 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8279 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8280 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8281 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8282 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8283 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8284 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8285 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8286 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8287 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8289 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8291 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8292 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8293 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8294 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8295 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8296 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8297 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8298 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8299 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8300 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8303 else if (!strcmp (default_arch
, "i386"))
8305 set_code_flag (CODE_32BIT
);
8306 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8308 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8309 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8310 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8312 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8314 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8315 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8316 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8320 as_fatal (_("Unknown architecture"));
8321 switch (OUTPUT_FLAVOR
)
8324 case bfd_target_coff_flavour
:
8325 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8328 #ifdef OBJ_MAYBE_AOUT
8329 case bfd_target_aout_flavour
:
8330 return AOUT_TARGET_FORMAT
;
8332 #ifdef OBJ_MAYBE_COFF
8333 case bfd_target_coff_flavour
:
8336 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8337 case bfd_target_elf_flavour
:
8339 if (flag_code
== CODE_64BIT
)
8342 use_rela_relocations
= 1;
8344 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8353 #endif /* OBJ_MAYBE_ more than one */
8355 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8357 i386_elf_emit_arch_note (void)
8359 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8362 asection
*seg
= now_seg
;
8363 subsegT subseg
= now_subseg
;
8364 Elf_Internal_Note i_note
;
8365 Elf_External_Note e_note
;
8366 asection
*note_secp
;
8369 /* Create the .note section. */
8370 note_secp
= subseg_new (".note", 0);
8371 bfd_set_section_flags (stdoutput
,
8373 SEC_HAS_CONTENTS
| SEC_READONLY
);
8375 /* Process the arch string. */
8376 len
= strlen (cpu_arch_name
);
8378 i_note
.namesz
= len
+ 1;
8380 i_note
.type
= NT_ARCH
;
8381 p
= frag_more (sizeof (e_note
.namesz
));
8382 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8383 p
= frag_more (sizeof (e_note
.descsz
));
8384 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8385 p
= frag_more (sizeof (e_note
.type
));
8386 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8387 p
= frag_more (len
+ 1);
8388 strcpy (p
, cpu_arch_name
);
8390 frag_align (2, 0, 0);
8392 subseg_set (seg
, subseg
);
8398 md_undefined_symbol (name
)
8401 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8402 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8403 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8404 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8408 if (symbol_find (name
))
8409 as_bad (_("GOT already in symbol table"));
8410 GOT_symbol
= symbol_new (name
, undefined_section
,
8411 (valueT
) 0, &zero_address_frag
);
8418 /* Round up a section size to the appropriate boundary. */
8421 md_section_align (segment
, size
)
8422 segT segment ATTRIBUTE_UNUSED
;
8425 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8426 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8428 /* For a.out, force the section size to be aligned. If we don't do
8429 this, BFD will align it for us, but it will not write out the
8430 final bytes of the section. This may be a bug in BFD, but it is
8431 easier to fix it here since that is how the other a.out targets
8435 align
= bfd_get_section_alignment (stdoutput
, segment
);
8436 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8443 /* On the i386, PC-relative offsets are relative to the start of the
8444 next instruction. That is, the address of the offset, plus its
8445 size, since the offset is always the last part of the insn. */
8448 md_pcrel_from (fixS
*fixP
)
8450 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8456 s_bss (int ignore ATTRIBUTE_UNUSED
)
8460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8462 obj_elf_section_change_hook ();
8464 temp
= get_absolute_expression ();
8465 subseg_set (bss_section
, (subsegT
) temp
);
8466 demand_empty_rest_of_line ();
8472 i386_validate_fix (fixS
*fixp
)
8474 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8476 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8480 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8485 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8487 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8494 tc_gen_reloc (section
, fixp
)
8495 asection
*section ATTRIBUTE_UNUSED
;
8499 bfd_reloc_code_real_type code
;
8501 switch (fixp
->fx_r_type
)
8503 case BFD_RELOC_X86_64_PLT32
:
8504 case BFD_RELOC_X86_64_GOT32
:
8505 case BFD_RELOC_X86_64_GOTPCREL
:
8506 case BFD_RELOC_386_PLT32
:
8507 case BFD_RELOC_386_GOT32
:
8508 case BFD_RELOC_386_GOTOFF
:
8509 case BFD_RELOC_386_GOTPC
:
8510 case BFD_RELOC_386_TLS_GD
:
8511 case BFD_RELOC_386_TLS_LDM
:
8512 case BFD_RELOC_386_TLS_LDO_32
:
8513 case BFD_RELOC_386_TLS_IE_32
:
8514 case BFD_RELOC_386_TLS_IE
:
8515 case BFD_RELOC_386_TLS_GOTIE
:
8516 case BFD_RELOC_386_TLS_LE_32
:
8517 case BFD_RELOC_386_TLS_LE
:
8518 case BFD_RELOC_386_TLS_GOTDESC
:
8519 case BFD_RELOC_386_TLS_DESC_CALL
:
8520 case BFD_RELOC_X86_64_TLSGD
:
8521 case BFD_RELOC_X86_64_TLSLD
:
8522 case BFD_RELOC_X86_64_DTPOFF32
:
8523 case BFD_RELOC_X86_64_DTPOFF64
:
8524 case BFD_RELOC_X86_64_GOTTPOFF
:
8525 case BFD_RELOC_X86_64_TPOFF32
:
8526 case BFD_RELOC_X86_64_TPOFF64
:
8527 case BFD_RELOC_X86_64_GOTOFF64
:
8528 case BFD_RELOC_X86_64_GOTPC32
:
8529 case BFD_RELOC_X86_64_GOT64
:
8530 case BFD_RELOC_X86_64_GOTPCREL64
:
8531 case BFD_RELOC_X86_64_GOTPC64
:
8532 case BFD_RELOC_X86_64_GOTPLT64
:
8533 case BFD_RELOC_X86_64_PLTOFF64
:
8534 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8535 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8537 case BFD_RELOC_VTABLE_ENTRY
:
8538 case BFD_RELOC_VTABLE_INHERIT
:
8540 case BFD_RELOC_32_SECREL
:
8542 code
= fixp
->fx_r_type
;
8544 case BFD_RELOC_X86_64_32S
:
8545 if (!fixp
->fx_pcrel
)
8547 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8548 code
= fixp
->fx_r_type
;
8554 switch (fixp
->fx_size
)
8557 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8558 _("can not do %d byte pc-relative relocation"),
8560 code
= BFD_RELOC_32_PCREL
;
8562 case 1: code
= BFD_RELOC_8_PCREL
; break;
8563 case 2: code
= BFD_RELOC_16_PCREL
; break;
8564 case 4: code
= BFD_RELOC_32_PCREL
; break;
8566 case 8: code
= BFD_RELOC_64_PCREL
; break;
8572 switch (fixp
->fx_size
)
8575 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8576 _("can not do %d byte relocation"),
8578 code
= BFD_RELOC_32
;
8580 case 1: code
= BFD_RELOC_8
; break;
8581 case 2: code
= BFD_RELOC_16
; break;
8582 case 4: code
= BFD_RELOC_32
; break;
8584 case 8: code
= BFD_RELOC_64
; break;
8591 if ((code
== BFD_RELOC_32
8592 || code
== BFD_RELOC_32_PCREL
8593 || code
== BFD_RELOC_X86_64_32S
)
8595 && fixp
->fx_addsy
== GOT_symbol
)
8598 code
= BFD_RELOC_386_GOTPC
;
8600 code
= BFD_RELOC_X86_64_GOTPC32
;
8602 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8604 && fixp
->fx_addsy
== GOT_symbol
)
8606 code
= BFD_RELOC_X86_64_GOTPC64
;
8609 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8610 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8611 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8613 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8615 if (!use_rela_relocations
)
8617 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8618 vtable entry to be used in the relocation's section offset. */
8619 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8620 rel
->address
= fixp
->fx_offset
;
8624 /* Use the rela in 64bit mode. */
8627 if (!fixp
->fx_pcrel
)
8628 rel
->addend
= fixp
->fx_offset
;
8632 case BFD_RELOC_X86_64_PLT32
:
8633 case BFD_RELOC_X86_64_GOT32
:
8634 case BFD_RELOC_X86_64_GOTPCREL
:
8635 case BFD_RELOC_X86_64_TLSGD
:
8636 case BFD_RELOC_X86_64_TLSLD
:
8637 case BFD_RELOC_X86_64_GOTTPOFF
:
8638 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8639 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8640 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8643 rel
->addend
= (section
->vma
8645 + fixp
->fx_addnumber
8646 + md_pcrel_from (fixp
));
8651 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8652 if (rel
->howto
== NULL
)
8654 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8655 _("cannot represent relocation type %s"),
8656 bfd_get_reloc_code_name (code
));
8657 /* Set howto to a garbage value so that we can keep going. */
8658 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8659 assert (rel
->howto
!= NULL
);
8666 /* Parse operands using Intel syntax. This implements a recursive descent
8667 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8670 FIXME: We do not recognize the full operand grammar defined in the MASM
8671 documentation. In particular, all the structure/union and
8672 high-level macro operands are missing.
8674 Uppercase words are terminals, lower case words are non-terminals.
8675 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8676 bars '|' denote choices. Most grammar productions are implemented in
8677 functions called 'intel_<production>'.
8679 Initial production is 'expr'.
8685 binOp & | AND | \| | OR | ^ | XOR
8687 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8689 constant digits [[ radixOverride ]]
8691 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8729 => expr expr cmpOp e04
8732 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8733 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8735 hexdigit a | b | c | d | e | f
8736 | A | B | C | D | E | F
8742 mulOp * | / | % | MOD | << | SHL | >> | SHR
8746 register specialRegister
8750 segmentRegister CS | DS | ES | FS | GS | SS
8752 specialRegister CR0 | CR2 | CR3 | CR4
8753 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8754 | TR3 | TR4 | TR5 | TR6 | TR7
8756 We simplify the grammar in obvious places (e.g., register parsing is
8757 done by calling parse_register) and eliminate immediate left recursion
8758 to implement a recursive-descent parser.
8762 expr' cmpOp e04 expr'
8814 /* Parsing structure for the intel syntax parser. Used to implement the
8815 semantic actions for the operand grammar. */
8816 struct intel_parser_s
8818 char *op_string
; /* The string being parsed. */
8819 int got_a_float
; /* Whether the operand is a float. */
8820 int op_modifier
; /* Operand modifier. */
8821 int is_mem
; /* 1 if operand is memory reference. */
8822 int in_offset
; /* >=1 if parsing operand of offset. */
8823 int in_bracket
; /* >=1 if parsing operand in brackets. */
8824 const reg_entry
*reg
; /* Last register reference found. */
8825 char *disp
; /* Displacement string being built. */
8826 char *next_operand
; /* Resume point when splitting operands. */
8829 static struct intel_parser_s intel_parser
;
8831 /* Token structure for parsing intel syntax. */
8834 int code
; /* Token code. */
8835 const reg_entry
*reg
; /* Register entry for register tokens. */
8836 char *str
; /* String representation. */
8839 static struct intel_token cur_token
, prev_token
;
8841 /* Token codes for the intel parser. Since T_SHORT is already used
8842 by COFF, undefine it first to prevent a warning. */
8860 #define T_YMMWORD 16
8862 /* Prototypes for intel parser functions. */
8863 static int intel_match_token (int);
8864 static void intel_putback_token (void);
8865 static void intel_get_token (void);
8866 static int intel_expr (void);
8867 static int intel_e04 (void);
8868 static int intel_e05 (void);
8869 static int intel_e06 (void);
8870 static int intel_e09 (void);
8871 static int intel_e10 (void);
8872 static int intel_e11 (void);
8875 i386_intel_operand (char *operand_string
, int got_a_float
)
8879 const reg_entry
*final_base
= i
.base_reg
;
8880 const reg_entry
*final_index
= i
.index_reg
;
8882 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8883 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8887 /* Initialize token holders. */
8888 cur_token
.code
= prev_token
.code
= T_NIL
;
8889 cur_token
.reg
= prev_token
.reg
= NULL
;
8890 cur_token
.str
= prev_token
.str
= NULL
;
8892 /* Initialize parser structure. */
8893 intel_parser
.got_a_float
= got_a_float
;
8894 intel_parser
.op_modifier
= 0;
8895 intel_parser
.is_mem
= 0;
8896 intel_parser
.in_offset
= 0;
8897 intel_parser
.in_bracket
= 0;
8898 intel_parser
.reg
= NULL
;
8899 intel_parser
.disp
[0] = '\0';
8900 intel_parser
.next_operand
= NULL
;
8905 /* Read the first token and start the parser. */
8907 ret
= intel_expr ();
8912 if (cur_token
.code
!= T_NIL
)
8914 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8915 current_templates
->start
->name
, cur_token
.str
);
8918 /* If we found a memory reference, hand it over to i386_displacement
8919 to fill in the rest of the operand fields. */
8920 else if (intel_parser
.is_mem
)
8922 if ((i
.mem_operands
== 1
8923 && !current_templates
->start
->opcode_modifier
.isstring
)
8924 || i
.mem_operands
== 2)
8926 as_bad (_("too many memory references for '%s'"),
8927 current_templates
->start
->name
);
8932 char *s
= intel_parser
.disp
;
8934 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8935 /* See the comments in intel_bracket_expr. */
8936 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8938 /* Add the displacement expression. */
8940 ret
= i386_displacement (s
, s
+ strlen (s
));
8943 /* Swap base and index in 16-bit memory operands like
8944 [si+bx]. Since i386_index_check is also used in AT&T
8945 mode we have to do that here. */
8948 && i
.base_reg
->reg_type
.bitfield
.reg16
8949 && i
.index_reg
->reg_type
.bitfield
.reg16
8950 && i
.base_reg
->reg_num
>= 6
8951 && i
.index_reg
->reg_num
< 6)
8953 const reg_entry
*base
= i
.index_reg
;
8955 i
.index_reg
= i
.base_reg
;
8958 ret
= i386_index_check (operand_string
);
8962 i
.types
[this_operand
].bitfield
.mem
= 1;
8968 /* Constant and OFFSET expressions are handled by i386_immediate. */
8969 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8970 || intel_parser
.reg
== NULL
)
8972 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8974 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8975 as_warn (_("Segment override ignored"));
8976 i
.seg
[i
.mem_operands
] = NULL
;
8978 ret
= i386_immediate (intel_parser
.disp
);
8981 if (!final_base
&& !final_index
)
8983 final_base
= i
.base_reg
;
8984 final_index
= i
.index_reg
;
8987 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8989 if (!ret
|| !intel_parser
.next_operand
)
8991 intel_parser
.op_string
= intel_parser
.next_operand
;
8992 this_operand
= i
.operands
++;
8993 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8997 free (intel_parser
.disp
);
8999 if (final_base
|| final_index
)
9001 i
.base_reg
= final_base
;
9002 i
.index_reg
= final_index
;
9008 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9012 expr' cmpOp e04 expr'
9017 /* XXX Implement the comparison operators. */
9018 return intel_e04 ();
9035 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9036 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9038 if (cur_token
.code
== '+')
9040 else if (cur_token
.code
== '-')
9041 nregs
= NUM_ADDRESS_REGS
;
9045 strcat (intel_parser
.disp
, cur_token
.str
);
9046 intel_match_token (cur_token
.code
);
9057 int nregs
= ~NUM_ADDRESS_REGS
;
9064 if (cur_token
.code
== '&'
9065 || cur_token
.code
== '|'
9066 || cur_token
.code
== '^')
9070 str
[0] = cur_token
.code
;
9072 strcat (intel_parser
.disp
, str
);
9077 intel_match_token (cur_token
.code
);
9082 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9083 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9094 int nregs
= ~NUM_ADDRESS_REGS
;
9101 if (cur_token
.code
== '*'
9102 || cur_token
.code
== '/'
9103 || cur_token
.code
== '%')
9107 str
[0] = cur_token
.code
;
9109 strcat (intel_parser
.disp
, str
);
9111 else if (cur_token
.code
== T_SHL
)
9112 strcat (intel_parser
.disp
, "<<");
9113 else if (cur_token
.code
== T_SHR
)
9114 strcat (intel_parser
.disp
, ">>");
9118 intel_match_token (cur_token
.code
);
9123 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9124 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9142 int nregs
= ~NUM_ADDRESS_REGS
;
9147 /* Don't consume constants here. */
9148 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9150 /* Need to look one token ahead - if the next token
9151 is a constant, the current token is its sign. */
9154 intel_match_token (cur_token
.code
);
9155 next_code
= cur_token
.code
;
9156 intel_putback_token ();
9157 if (next_code
== T_CONST
)
9161 /* e09 OFFSET e09 */
9162 if (cur_token
.code
== T_OFFSET
)
9165 ++intel_parser
.in_offset
;
9169 else if (cur_token
.code
== T_SHORT
)
9170 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9173 else if (cur_token
.code
== '+')
9174 strcat (intel_parser
.disp
, "+");
9179 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9185 str
[0] = cur_token
.code
;
9187 strcat (intel_parser
.disp
, str
);
9194 intel_match_token (cur_token
.code
);
9202 /* e09' PTR e10 e09' */
9203 if (cur_token
.code
== T_PTR
)
9207 if (prev_token
.code
== T_BYTE
)
9209 suffix
= BYTE_MNEM_SUFFIX
;
9210 i
.types
[this_operand
].bitfield
.byte
= 1;
9213 else if (prev_token
.code
== T_WORD
)
9215 if ((current_templates
->start
->name
[0] == 'l'
9216 && current_templates
->start
->name
[2] == 's'
9217 && current_templates
->start
->name
[3] == 0)
9218 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9219 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9220 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9221 suffix
= SHORT_MNEM_SUFFIX
;
9223 suffix
= WORD_MNEM_SUFFIX
;
9224 i
.types
[this_operand
].bitfield
.word
= 1;
9227 else if (prev_token
.code
== T_DWORD
)
9229 if ((current_templates
->start
->name
[0] == 'l'
9230 && current_templates
->start
->name
[2] == 's'
9231 && current_templates
->start
->name
[3] == 0)
9232 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9233 suffix
= WORD_MNEM_SUFFIX
;
9234 else if (flag_code
== CODE_16BIT
9235 && (current_templates
->start
->opcode_modifier
.jump
9236 || current_templates
->start
->opcode_modifier
.jumpdword
))
9237 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9238 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9239 suffix
= SHORT_MNEM_SUFFIX
;
9241 suffix
= LONG_MNEM_SUFFIX
;
9242 i
.types
[this_operand
].bitfield
.dword
= 1;
9245 else if (prev_token
.code
== T_FWORD
)
9247 if (current_templates
->start
->name
[0] == 'l'
9248 && current_templates
->start
->name
[2] == 's'
9249 && current_templates
->start
->name
[3] == 0)
9250 suffix
= LONG_MNEM_SUFFIX
;
9251 else if (!intel_parser
.got_a_float
)
9253 if (flag_code
== CODE_16BIT
)
9254 add_prefix (DATA_PREFIX_OPCODE
);
9255 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9258 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9259 i
.types
[this_operand
].bitfield
.fword
= 1;
9262 else if (prev_token
.code
== T_QWORD
)
9264 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9265 || intel_parser
.got_a_float
== 1) /* "f..." */
9266 suffix
= LONG_MNEM_SUFFIX
;
9268 suffix
= QWORD_MNEM_SUFFIX
;
9269 i
.types
[this_operand
].bitfield
.qword
= 1;
9272 else if (prev_token
.code
== T_TBYTE
)
9274 if (intel_parser
.got_a_float
== 1)
9275 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9277 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9280 else if (prev_token
.code
== T_XMMWORD
)
9282 suffix
= XMMWORD_MNEM_SUFFIX
;
9283 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9286 else if (prev_token
.code
== T_YMMWORD
)
9288 suffix
= YMMWORD_MNEM_SUFFIX
;
9289 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9294 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9298 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9300 /* Operands for jump/call using 'ptr' notation denote absolute
9302 if (current_templates
->start
->opcode_modifier
.jump
9303 || current_templates
->start
->opcode_modifier
.jumpdword
)
9304 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9306 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9310 else if (i
.suffix
!= suffix
)
9312 as_bad (_("Conflicting operand modifiers"));
9318 /* e09' : e10 e09' */
9319 else if (cur_token
.code
== ':')
9321 if (prev_token
.code
!= T_REG
)
9323 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9324 segment/group identifier (which we don't have), using comma
9325 as the operand separator there is even less consistent, since
9326 there all branches only have a single operand. */
9327 if (this_operand
!= 0
9328 || intel_parser
.in_offset
9329 || intel_parser
.in_bracket
9330 || (!current_templates
->start
->opcode_modifier
.jump
9331 && !current_templates
->start
->opcode_modifier
.jumpdword
9332 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9333 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9334 return intel_match_token (T_NIL
);
9335 /* Remember the start of the 2nd operand and terminate 1st
9337 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9338 another expression), but it gets at least the simplest case
9339 (a plain number or symbol on the left side) right. */
9340 intel_parser
.next_operand
= intel_parser
.op_string
;
9341 *--intel_parser
.op_string
= '\0';
9342 return intel_match_token (':');
9350 intel_match_token (cur_token
.code
);
9356 --intel_parser
.in_offset
;
9359 if (NUM_ADDRESS_REGS
> nregs
)
9361 as_bad (_("Invalid operand to `OFFSET'"));
9364 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9367 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9368 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9373 intel_bracket_expr (void)
9375 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9376 const char *start
= intel_parser
.op_string
;
9379 if (i
.op
[this_operand
].regs
)
9380 return intel_match_token (T_NIL
);
9382 intel_match_token ('[');
9384 /* Mark as a memory operand only if it's not already known to be an
9385 offset expression. If it's an offset expression, we need to keep
9387 if (!intel_parser
.in_offset
)
9389 ++intel_parser
.in_bracket
;
9391 /* Operands for jump/call inside brackets denote absolute addresses. */
9392 if (current_templates
->start
->opcode_modifier
.jump
9393 || current_templates
->start
->opcode_modifier
.jumpdword
)
9394 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9396 /* Unfortunately gas always diverged from MASM in a respect that can't
9397 be easily fixed without risking to break code sequences likely to be
9398 encountered (the testsuite even check for this): MASM doesn't consider
9399 an expression inside brackets unconditionally as a memory reference.
9400 When that is e.g. a constant, an offset expression, or the sum of the
9401 two, this is still taken as a constant load. gas, however, always
9402 treated these as memory references. As a compromise, we'll try to make
9403 offset expressions inside brackets work the MASM way (since that's
9404 less likely to be found in real world code), but make constants alone
9405 continue to work the traditional gas way. In either case, issue a
9407 intel_parser
.op_modifier
&= ~was_offset
;
9410 strcat (intel_parser
.disp
, "[");
9412 /* Add a '+' to the displacement string if necessary. */
9413 if (*intel_parser
.disp
!= '\0'
9414 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9415 strcat (intel_parser
.disp
, "+");
9418 && (len
= intel_parser
.op_string
- start
- 1,
9419 intel_match_token (']')))
9421 /* Preserve brackets when the operand is an offset expression. */
9422 if (intel_parser
.in_offset
)
9423 strcat (intel_parser
.disp
, "]");
9426 --intel_parser
.in_bracket
;
9427 if (i
.base_reg
|| i
.index_reg
)
9428 intel_parser
.is_mem
= 1;
9429 if (!intel_parser
.is_mem
)
9431 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9432 /* Defer the warning until all of the operand was parsed. */
9433 intel_parser
.is_mem
= -1;
9434 else if (!quiet_warnings
)
9435 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9436 len
, start
, len
, start
);
9439 intel_parser
.op_modifier
|= was_offset
;
9456 while (cur_token
.code
== '[')
9458 if (!intel_bracket_expr ())
9484 switch (cur_token
.code
)
9488 intel_match_token ('(');
9489 strcat (intel_parser
.disp
, "(");
9491 if (intel_expr () && intel_match_token (')'))
9493 strcat (intel_parser
.disp
, ")");
9500 return intel_bracket_expr ();
9505 strcat (intel_parser
.disp
, cur_token
.str
);
9506 intel_match_token (cur_token
.code
);
9508 /* Mark as a memory operand only if it's not already known to be an
9509 offset expression. */
9510 if (!intel_parser
.in_offset
)
9511 intel_parser
.is_mem
= 1;
9518 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9520 intel_match_token (T_REG
);
9522 /* Check for segment change. */
9523 if (cur_token
.code
== ':')
9525 if (!reg
->reg_type
.bitfield
.sreg2
9526 && !reg
->reg_type
.bitfield
.sreg3
)
9528 as_bad (_("`%s' is not a valid segment register"),
9532 else if (i
.mem_operands
>= 2)
9533 as_warn (_("Segment override ignored"));
9534 else if (i
.seg
[i
.mem_operands
])
9535 as_warn (_("Extra segment override ignored"));
9538 if (!intel_parser
.in_offset
)
9539 intel_parser
.is_mem
= 1;
9540 switch (reg
->reg_num
)
9543 i
.seg
[i
.mem_operands
] = &es
;
9546 i
.seg
[i
.mem_operands
] = &cs
;
9549 i
.seg
[i
.mem_operands
] = &ss
;
9552 i
.seg
[i
.mem_operands
] = &ds
;
9555 i
.seg
[i
.mem_operands
] = &fs
;
9558 i
.seg
[i
.mem_operands
] = &gs
;
9564 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9566 as_bad (_("cannot use `FLAT' here"));
9570 /* Not a segment register. Check for register scaling. */
9571 else if (cur_token
.code
== '*')
9573 if (!intel_parser
.in_bracket
)
9575 as_bad (_("Register scaling only allowed in memory operands"));
9579 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9580 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9581 else if (i
.index_reg
)
9582 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9584 /* What follows must be a valid scale. */
9585 intel_match_token ('*');
9587 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9589 /* Set the scale after setting the register (otherwise,
9590 i386_scale will complain) */
9591 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9593 char *str
, sign
= cur_token
.code
;
9594 intel_match_token (cur_token
.code
);
9595 if (cur_token
.code
!= T_CONST
)
9597 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9601 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9602 strcpy (str
+ 1, cur_token
.str
);
9604 if (!i386_scale (str
))
9608 else if (!i386_scale (cur_token
.str
))
9610 intel_match_token (cur_token
.code
);
9613 /* No scaling. If this is a memory operand, the register is either a
9614 base register (first occurrence) or an index register (second
9616 else if (intel_parser
.in_bracket
)
9621 else if (!i
.index_reg
)
9625 as_bad (_("Too many register references in memory operand"));
9629 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9632 /* It's neither base nor index. */
9633 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9635 i386_operand_type temp
= reg
->reg_type
;
9636 temp
.bitfield
.baseindex
= 0;
9637 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9639 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9640 i
.op
[this_operand
].regs
= reg
;
9645 as_bad (_("Invalid use of register"));
9649 /* Since registers are not part of the displacement string (except
9650 when we're parsing offset operands), we may need to remove any
9651 preceding '+' from the displacement string. */
9652 if (*intel_parser
.disp
!= '\0'
9653 && !intel_parser
.in_offset
)
9655 char *s
= intel_parser
.disp
;
9656 s
+= strlen (s
) - 1;
9681 intel_match_token (cur_token
.code
);
9683 if (cur_token
.code
== T_PTR
)
9686 /* It must have been an identifier. */
9687 intel_putback_token ();
9688 cur_token
.code
= T_ID
;
9694 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9698 /* The identifier represents a memory reference only if it's not
9699 preceded by an offset modifier and if it's not an equate. */
9700 symbolP
= symbol_find(cur_token
.str
);
9701 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9702 intel_parser
.is_mem
= 1;
9710 char *save_str
, sign
= 0;
9712 /* Allow constants that start with `+' or `-'. */
9713 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9715 sign
= cur_token
.code
;
9716 intel_match_token (cur_token
.code
);
9717 if (cur_token
.code
!= T_CONST
)
9719 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9725 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9726 strcpy (save_str
+ !!sign
, cur_token
.str
);
9730 /* Get the next token to check for register scaling. */
9731 intel_match_token (cur_token
.code
);
9733 /* Check if this constant is a scaling factor for an
9735 if (cur_token
.code
== '*')
9737 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9739 const reg_entry
*reg
= cur_token
.reg
;
9741 if (!intel_parser
.in_bracket
)
9743 as_bad (_("Register scaling only allowed "
9744 "in memory operands"));
9748 /* Disallow things like [1*si].
9749 sp and esp are invalid as index. */
9750 if (reg
->reg_type
.bitfield
.reg16
)
9751 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9752 else if (i
.index_reg
)
9753 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9755 /* The constant is followed by `* reg', so it must be
9758 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9760 /* Set the scale after setting the register (otherwise,
9761 i386_scale will complain) */
9762 if (!i386_scale (save_str
))
9764 intel_match_token (T_REG
);
9766 /* Since registers are not part of the displacement
9767 string, we may need to remove any preceding '+' from
9768 the displacement string. */
9769 if (*intel_parser
.disp
!= '\0')
9771 char *s
= intel_parser
.disp
;
9772 s
+= strlen (s
) - 1;
9782 /* The constant was not used for register scaling. Since we have
9783 already consumed the token following `*' we now need to put it
9784 back in the stream. */
9785 intel_putback_token ();
9788 /* Add the constant to the displacement string. */
9789 strcat (intel_parser
.disp
, save_str
);
9796 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9800 /* Match the given token against cur_token. If they match, read the next
9801 token from the operand string. */
9803 intel_match_token (int code
)
9805 if (cur_token
.code
== code
)
9812 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9817 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9819 intel_get_token (void)
9822 const reg_entry
*reg
;
9823 struct intel_token new_token
;
9825 new_token
.code
= T_NIL
;
9826 new_token
.reg
= NULL
;
9827 new_token
.str
= NULL
;
9829 /* Free the memory allocated to the previous token and move
9830 cur_token to prev_token. */
9832 free (prev_token
.str
);
9834 prev_token
= cur_token
;
9836 /* Skip whitespace. */
9837 while (is_space_char (*intel_parser
.op_string
))
9838 intel_parser
.op_string
++;
9840 /* Return an empty token if we find nothing else on the line. */
9841 if (*intel_parser
.op_string
== '\0')
9843 cur_token
= new_token
;
9847 /* The new token cannot be larger than the remainder of the operand
9849 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9850 new_token
.str
[0] = '\0';
9852 if (strchr ("0123456789", *intel_parser
.op_string
))
9854 char *p
= new_token
.str
;
9855 char *q
= intel_parser
.op_string
;
9856 new_token
.code
= T_CONST
;
9858 /* Allow any kind of identifier char to encompass floating point and
9859 hexadecimal numbers. */
9860 while (is_identifier_char (*q
))
9864 /* Recognize special symbol names [0-9][bf]. */
9865 if (strlen (intel_parser
.op_string
) == 2
9866 && (intel_parser
.op_string
[1] == 'b'
9867 || intel_parser
.op_string
[1] == 'f'))
9868 new_token
.code
= T_ID
;
9871 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9873 size_t len
= end_op
- intel_parser
.op_string
;
9875 new_token
.code
= T_REG
;
9876 new_token
.reg
= reg
;
9878 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9879 new_token
.str
[len
] = '\0';
9882 else if (is_identifier_char (*intel_parser
.op_string
))
9884 char *p
= new_token
.str
;
9885 char *q
= intel_parser
.op_string
;
9887 /* A '.' or '$' followed by an identifier char is an identifier.
9888 Otherwise, it's operator '.' followed by an expression. */
9889 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9891 new_token
.code
= '.';
9892 new_token
.str
[0] = '.';
9893 new_token
.str
[1] = '\0';
9897 while (is_identifier_char (*q
) || *q
== '@')
9901 if (strcasecmp (new_token
.str
, "NOT") == 0)
9902 new_token
.code
= '~';
9904 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9905 new_token
.code
= '%';
9907 else if (strcasecmp (new_token
.str
, "AND") == 0)
9908 new_token
.code
= '&';
9910 else if (strcasecmp (new_token
.str
, "OR") == 0)
9911 new_token
.code
= '|';
9913 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9914 new_token
.code
= '^';
9916 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9917 new_token
.code
= T_SHL
;
9919 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9920 new_token
.code
= T_SHR
;
9922 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9923 new_token
.code
= T_BYTE
;
9925 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9926 new_token
.code
= T_WORD
;
9928 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9929 new_token
.code
= T_DWORD
;
9931 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9932 new_token
.code
= T_FWORD
;
9934 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9935 new_token
.code
= T_QWORD
;
9937 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9938 /* XXX remove (gcc still uses it) */
9939 || strcasecmp (new_token
.str
, "XWORD") == 0)
9940 new_token
.code
= T_TBYTE
;
9942 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9943 || strcasecmp (new_token
.str
, "OWORD") == 0)
9944 new_token
.code
= T_XMMWORD
;
9946 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9947 new_token
.code
= T_YMMWORD
;
9949 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9950 new_token
.code
= T_PTR
;
9952 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9953 new_token
.code
= T_SHORT
;
9955 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9957 new_token
.code
= T_OFFSET
;
9959 /* ??? This is not mentioned in the MASM grammar but gcc
9960 makes use of it with -mintel-syntax. OFFSET may be
9961 followed by FLAT: */
9962 if (strncasecmp (q
, " FLAT:", 6) == 0)
9963 strcat (new_token
.str
, " FLAT:");
9967 new_token
.code
= T_ID
;
9971 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9973 new_token
.code
= *intel_parser
.op_string
;
9974 new_token
.str
[0] = *intel_parser
.op_string
;
9975 new_token
.str
[1] = '\0';
9978 else if (strchr ("<>", *intel_parser
.op_string
)
9979 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9981 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9982 new_token
.str
[0] = *intel_parser
.op_string
;
9983 new_token
.str
[1] = *intel_parser
.op_string
;
9984 new_token
.str
[2] = '\0';
9988 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9990 intel_parser
.op_string
+= strlen (new_token
.str
);
9991 cur_token
= new_token
;
9994 /* Put cur_token back into the token stream and make cur_token point to
9997 intel_putback_token (void)
9999 if (cur_token
.code
!= T_NIL
)
10001 intel_parser
.op_string
-= strlen (cur_token
.str
);
10002 free (cur_token
.str
);
10004 cur_token
= prev_token
;
10006 /* Forget prev_token. */
10007 prev_token
.code
= T_NIL
;
10008 prev_token
.reg
= NULL
;
10009 prev_token
.str
= NULL
;
10013 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10015 int saved_naked_reg
;
10016 char saved_register_dot
;
10018 saved_naked_reg
= allow_naked_reg
;
10019 allow_naked_reg
= 1;
10020 saved_register_dot
= register_chars
['.'];
10021 register_chars
['.'] = '.';
10022 allow_pseudo_reg
= 1;
10023 expression_and_evaluate (exp
);
10024 allow_pseudo_reg
= 0;
10025 register_chars
['.'] = saved_register_dot
;
10026 allow_naked_reg
= saved_naked_reg
;
10028 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10030 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10032 exp
->X_op
= O_constant
;
10033 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10034 .dw2_regnum
[flag_code
>> 1];
10037 exp
->X_op
= O_illegal
;
10042 tc_x86_frame_initial_instructions (void)
10044 static unsigned int sp_regno
[2];
10046 if (!sp_regno
[flag_code
>> 1])
10048 char *saved_input
= input_line_pointer
;
10049 char sp
[][4] = {"esp", "rsp"};
10052 input_line_pointer
= sp
[flag_code
>> 1];
10053 tc_x86_parse_to_dw2regnum (&exp
);
10054 assert (exp
.X_op
== O_constant
);
10055 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10056 input_line_pointer
= saved_input
;
10059 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10060 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10064 i386_elf_section_type (const char *str
, size_t len
)
10066 if (flag_code
== CODE_64BIT
10067 && len
== sizeof ("unwind") - 1
10068 && strncmp (str
, "unwind", 6) == 0)
10069 return SHT_X86_64_UNWIND
;
10076 i386_solaris_fix_up_eh_frame (segT sec
)
10078 if (flag_code
== CODE_64BIT
)
10079 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10085 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10089 expr
.X_op
= O_secrel
;
10090 expr
.X_add_symbol
= symbol
;
10091 expr
.X_add_number
= 0;
10092 emit_expr (&expr
, size
);
10096 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10097 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10100 x86_64_section_letter (int letter
, char **ptr_msg
)
10102 if (flag_code
== CODE_64BIT
)
10105 return SHF_X86_64_LARGE
;
10107 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10110 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10115 x86_64_section_word (char *str
, size_t len
)
10117 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10118 return SHF_X86_64_LARGE
;
10124 handle_large_common (int small ATTRIBUTE_UNUSED
)
10126 if (flag_code
!= CODE_64BIT
)
10128 s_comm_internal (0, elf_common_parse
);
10129 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10133 static segT lbss_section
;
10134 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10135 asection
*saved_bss_section
= bss_section
;
10137 if (lbss_section
== NULL
)
10139 flagword applicable
;
10140 segT seg
= now_seg
;
10141 subsegT subseg
= now_subseg
;
10143 /* The .lbss section is for local .largecomm symbols. */
10144 lbss_section
= subseg_new (".lbss", 0);
10145 applicable
= bfd_applicable_section_flags (stdoutput
);
10146 bfd_set_section_flags (stdoutput
, lbss_section
,
10147 applicable
& SEC_ALLOC
);
10148 seg_info (lbss_section
)->bss
= 1;
10150 subseg_set (seg
, subseg
);
10153 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10154 bss_section
= lbss_section
;
10156 s_comm_internal (0, elf_common_parse
);
10158 elf_com_section_ptr
= saved_com_section_ptr
;
10159 bss_section
= saved_bss_section
;
10162 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */