1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 static enum check_kind
552 sse_check
, operand_check
= check_warning
;
554 /* Register prefix used for error message. */
555 static const char *register_prefix
= "%";
557 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560 static char stackop_size
= '\0';
562 /* Non-zero to optimize code alignment. */
563 int optimize_align_code
= 1;
565 /* Non-zero to quieten some warnings. */
566 static int quiet_warnings
= 0;
569 static const char *cpu_arch_name
= NULL
;
570 static char *cpu_sub_arch_name
= NULL
;
572 /* CPU feature flags. */
573 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
575 /* If we have selected a cpu we are generating instructions for. */
576 static int cpu_arch_tune_set
= 0;
578 /* Cpu we are generating instructions for. */
579 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
581 /* CPU feature flags of cpu we are generating instructions for. */
582 static i386_cpu_flags cpu_arch_tune_flags
;
584 /* CPU instruction set architecture used. */
585 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
587 /* CPU feature flags of instruction set architecture used. */
588 i386_cpu_flags cpu_arch_isa_flags
;
590 /* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592 static unsigned int no_cond_jump_promotion
= 0;
594 /* Encode SSE instructions with VEX prefix. */
595 static unsigned int sse2avx
;
597 /* Encode scalar AVX instructions with specific vector length. */
604 /* Encode scalar EVEX LIG instructions with specific vector length. */
612 /* Encode EVEX WIG instructions with specific evex.w. */
619 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
620 static symbolS
*GOT_symbol
;
622 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
623 unsigned int x86_dwarf2_return_column
;
625 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626 int x86_cie_data_alignment
;
628 /* Interface to relax_segment.
629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
634 #define UNCOND_JUMP 0
636 #define COND_JUMP86 2
641 #define SMALL16 (SMALL | CODE16)
643 #define BIG16 (BIG | CODE16)
647 #define INLINE __inline__
653 #define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655 #define TYPE_FROM_RELAX_STATE(s) \
657 #define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
660 /* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
668 const relax_typeS md_relax_table
[] =
671 1) most positive reach of this state,
672 2) most negative reach of this state,
673 3) how many bytes this mode will have in the variable part of the frag
674 4) which index into the table to try if we can't fit into this one. */
676 /* UNCOND_JUMP states. */
677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
692 /* word conditionals add 3 bytes to frag:
693 1 extra opcode byte, 2 displacement bytes. */
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
707 static const arch_entry cpu_arch
[] =
709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
712 CPU_GENERIC32_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
714 CPU_GENERIC64_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
716 CPU_NONE_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
718 CPU_I186_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
720 CPU_I286_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
722 CPU_I386_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
724 CPU_I486_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
726 CPU_I586_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
728 CPU_I686_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
730 CPU_I586_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
732 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
734 CPU_P2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
736 CPU_P3_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
738 CPU_P4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
740 CPU_CORE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
742 CPU_NOCONA_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 1, 0 },
745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
746 CPU_CORE_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 1, 0 },
749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
750 CPU_CORE2_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
752 CPU_COREI7_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
754 CPU_L1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
756 CPU_K1OM_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
758 CPU_K6_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
760 CPU_K6_2_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
762 CPU_ATHLON_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 1, 0 },
765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
768 CPU_K8_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
770 CPU_AMDFAM10_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
772 CPU_BDVER1_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
774 CPU_BDVER2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
776 CPU_BDVER3_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
778 CPU_BDVER4_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
780 CPU_BTVER1_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
782 CPU_BTVER2_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
784 CPU_8087_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
786 CPU_287_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
788 CPU_387_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
790 CPU_ANY87_FLAGS
, 0, 1 },
791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
792 CPU_MMX_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
794 CPU_3DNOWA_FLAGS
, 0, 1 },
795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
796 CPU_SSE_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
798 CPU_SSE2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
802 CPU_SSSE3_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_1_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
808 CPU_SSE4_2_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
810 CPU_ANY_SSE_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
812 CPU_AVX_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
814 CPU_AVX2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512F_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512CD_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512ER_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
822 CPU_AVX512PF_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
824 CPU_ANY_AVX_FLAGS
, 0, 1 },
825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
826 CPU_VMX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
828 CPU_VMFUNC_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
830 CPU_SMX_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVE_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
834 CPU_XSAVEOPT_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
836 CPU_AES_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
840 CPU_PCLMUL_FLAGS
, 1, 0 },
841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
842 CPU_FSGSBASE_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
844 CPU_RDRND_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
846 CPU_F16C_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
848 CPU_BMI2_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
850 CPU_FMA_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
852 CPU_FMA4_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
854 CPU_XOP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
856 CPU_LWP_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
858 CPU_MOVBE_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
860 CPU_CX16_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
862 CPU_EPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
864 CPU_LZCNT_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
866 CPU_HLE_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
868 CPU_RTM_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
870 CPU_INVPCID_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
872 CPU_CLFLUSH_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
874 CPU_NOP_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
876 CPU_SYSCALL_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
878 CPU_RDTSCP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOW_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
882 CPU_3DNOWA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
884 CPU_PADLOCK_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 1, 0 },
887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
888 CPU_SVME_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
890 CPU_SSE4A_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
892 CPU_ABM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
894 CPU_BMI_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
896 CPU_TBM_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
898 CPU_ADX_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
900 CPU_RDSEED_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
902 CPU_PRFCHW_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
904 CPU_SMAP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
906 CPU_MPX_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
908 CPU_SHA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
910 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVEC_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
914 CPU_XSAVES_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
916 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
918 CPU_SE1_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
920 CPU_AVX512BW_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
922 CPU_AVX512VL_FLAGS
, 0, 0 },
926 /* Like s_lcomm_internal in gas/read.c but the alignment string
927 is allowed to be optional. */
930 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
937 && *input_line_pointer
== ',')
939 align
= parse_align (needs_align
- 1);
941 if (align
== (addressT
) -1)
956 bss_alloc (symbolP
, size
, align
);
961 pe_lcomm (int needs_align
)
963 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
967 const pseudo_typeS md_pseudo_table
[] =
969 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
970 {"align", s_align_bytes
, 0},
972 {"align", s_align_ptwo
, 0},
974 {"arch", set_cpu_arch
, 0},
978 {"lcomm", pe_lcomm
, 1},
980 {"ffloat", float_cons
, 'f'},
981 {"dfloat", float_cons
, 'd'},
982 {"tfloat", float_cons
, 'x'},
984 {"slong", signed_cons
, 4},
985 {"noopt", s_ignore
, 0},
986 {"optim", s_ignore
, 0},
987 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
988 {"code16", set_code_flag
, CODE_16BIT
},
989 {"code32", set_code_flag
, CODE_32BIT
},
990 {"code64", set_code_flag
, CODE_64BIT
},
991 {"intel_syntax", set_intel_syntax
, 1},
992 {"att_syntax", set_intel_syntax
, 0},
993 {"intel_mnemonic", set_intel_mnemonic
, 1},
994 {"att_mnemonic", set_intel_mnemonic
, 0},
995 {"allow_index_reg", set_allow_index_reg
, 1},
996 {"disallow_index_reg", set_allow_index_reg
, 0},
997 {"sse_check", set_check
, 0},
998 {"operand_check", set_check
, 1},
999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1000 {"largecomm", handle_large_common
, 0},
1002 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1003 {"loc", dwarf2_directive_loc
, 0},
1004 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1007 {"secrel32", pe_directive_secrel
, 0},
1012 /* For interface with expression (). */
1013 extern char *input_line_pointer
;
1015 /* Hash table for instruction mnemonic lookup. */
1016 static struct hash_control
*op_hash
;
1018 /* Hash table for register lookup. */
1019 static struct hash_control
*reg_hash
;
1022 i386_align_code (fragS
*fragP
, int count
)
1024 /* Various efficient no-op patterns for aligning code labels.
1025 Note: Don't try to assemble the instructions in the comments.
1026 0L and 0w are not legal. */
1027 static const char f32_1
[] =
1029 static const char f32_2
[] =
1030 {0x66,0x90}; /* xchg %ax,%ax */
1031 static const char f32_3
[] =
1032 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1033 static const char f32_4
[] =
1034 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1035 static const char f32_5
[] =
1037 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1038 static const char f32_6
[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1040 static const char f32_7
[] =
1041 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1042 static const char f32_8
[] =
1044 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1045 static const char f32_9
[] =
1046 {0x89,0xf6, /* movl %esi,%esi */
1047 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1048 static const char f32_10
[] =
1049 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1050 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1051 static const char f32_11
[] =
1052 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1053 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1054 static const char f32_12
[] =
1055 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1056 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1057 static const char f32_13
[] =
1058 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_14
[] =
1061 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f16_3
[] =
1064 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1065 static const char f16_4
[] =
1066 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1067 static const char f16_5
[] =
1069 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1070 static const char f16_6
[] =
1071 {0x89,0xf6, /* mov %si,%si */
1072 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1073 static const char f16_7
[] =
1074 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1075 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1076 static const char f16_8
[] =
1077 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1078 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1079 static const char jump_31
[] =
1080 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1081 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1082 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1083 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1084 static const char *const f32_patt
[] = {
1085 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1086 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1088 static const char *const f16_patt
[] = {
1089 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1091 /* nopl (%[re]ax) */
1092 static const char alt_3
[] =
1094 /* nopl 0(%[re]ax) */
1095 static const char alt_4
[] =
1096 {0x0f,0x1f,0x40,0x00};
1097 /* nopl 0(%[re]ax,%[re]ax,1) */
1098 static const char alt_5
[] =
1099 {0x0f,0x1f,0x44,0x00,0x00};
1100 /* nopw 0(%[re]ax,%[re]ax,1) */
1101 static const char alt_6
[] =
1102 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1103 /* nopl 0L(%[re]ax) */
1104 static const char alt_7
[] =
1105 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1106 /* nopl 0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_8
[] =
1108 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1109 /* nopw 0L(%[re]ax,%[re]ax,1) */
1110 static const char alt_9
[] =
1111 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1112 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_10
[] =
1114 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1116 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1117 static const char alt_long_11
[] =
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1122 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_long_12
[] =
1126 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1130 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1131 static const char alt_long_13
[] =
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1140 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1141 static const char alt_long_14
[] =
1146 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1152 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1153 static const char alt_long_15
[] =
1159 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopl 0(%[re]ax,%[re]ax,1)
1161 nopw 0(%[re]ax,%[re]ax,1) */
1162 static const char alt_short_11
[] =
1163 {0x0f,0x1f,0x44,0x00,0x00,
1164 0x66,0x0f,0x1f,0x44,0x00,0x00};
1165 /* nopw 0(%[re]ax,%[re]ax,1)
1166 nopw 0(%[re]ax,%[re]ax,1) */
1167 static const char alt_short_12
[] =
1168 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1169 0x66,0x0f,0x1f,0x44,0x00,0x00};
1170 /* nopw 0(%[re]ax,%[re]ax,1)
1172 static const char alt_short_13
[] =
1173 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1174 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1177 static const char alt_short_14
[] =
1178 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1179 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1181 nopl 0L(%[re]ax,%[re]ax,1) */
1182 static const char alt_short_15
[] =
1183 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1184 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1185 static const char *const alt_short_patt
[] = {
1186 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1187 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1188 alt_short_14
, alt_short_15
1190 static const char *const alt_long_patt
[] = {
1191 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1192 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1193 alt_long_14
, alt_long_15
1196 /* Only align for at least a positive non-zero boundary. */
1197 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1200 /* We need to decide which NOP sequence to use for 32bit and
1201 64bit. When -mtune= is used:
1203 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1204 PROCESSOR_GENERIC32, f32_patt will be used.
1205 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1206 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1207 PROCESSOR_GENERIC64, alt_long_patt will be used.
1208 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1209 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1212 When -mtune= isn't used, alt_long_patt will be used if
1213 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1216 When -march= or .arch is used, we can't use anything beyond
1217 cpu_arch_isa_flags. */
1219 if (flag_code
== CODE_16BIT
)
1223 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1225 /* Adjust jump offset. */
1226 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1229 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1230 f16_patt
[count
- 1], count
);
1234 const char *const *patt
= NULL
;
1236 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1238 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1239 switch (cpu_arch_tune
)
1241 case PROCESSOR_UNKNOWN
:
1242 /* We use cpu_arch_isa_flags to check if we SHOULD
1243 optimize with nops. */
1244 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1245 patt
= alt_long_patt
;
1249 case PROCESSOR_PENTIUM4
:
1250 case PROCESSOR_NOCONA
:
1251 case PROCESSOR_CORE
:
1252 case PROCESSOR_CORE2
:
1253 case PROCESSOR_COREI7
:
1254 case PROCESSOR_L1OM
:
1255 case PROCESSOR_K1OM
:
1256 case PROCESSOR_GENERIC64
:
1257 patt
= alt_long_patt
;
1260 case PROCESSOR_ATHLON
:
1262 case PROCESSOR_AMDFAM10
:
1265 patt
= alt_short_patt
;
1267 case PROCESSOR_I386
:
1268 case PROCESSOR_I486
:
1269 case PROCESSOR_PENTIUM
:
1270 case PROCESSOR_PENTIUMPRO
:
1271 case PROCESSOR_GENERIC32
:
1278 switch (fragP
->tc_frag_data
.tune
)
1280 case PROCESSOR_UNKNOWN
:
1281 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1282 PROCESSOR_UNKNOWN. */
1286 case PROCESSOR_I386
:
1287 case PROCESSOR_I486
:
1288 case PROCESSOR_PENTIUM
:
1290 case PROCESSOR_ATHLON
:
1292 case PROCESSOR_AMDFAM10
:
1295 case PROCESSOR_GENERIC32
:
1296 /* We use cpu_arch_isa_flags to check if we CAN optimize
1298 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1299 patt
= alt_short_patt
;
1303 case PROCESSOR_PENTIUMPRO
:
1304 case PROCESSOR_PENTIUM4
:
1305 case PROCESSOR_NOCONA
:
1306 case PROCESSOR_CORE
:
1307 case PROCESSOR_CORE2
:
1308 case PROCESSOR_COREI7
:
1309 case PROCESSOR_L1OM
:
1310 case PROCESSOR_K1OM
:
1311 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1312 patt
= alt_long_patt
;
1316 case PROCESSOR_GENERIC64
:
1317 patt
= alt_long_patt
;
1322 if (patt
== f32_patt
)
1324 /* If the padding is less than 15 bytes, we use the normal
1325 ones. Otherwise, we use a jump instruction and adjust
1329 /* For 64bit, the limit is 3 bytes. */
1330 if (flag_code
== CODE_64BIT
1331 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1337 patt
[count
- 1], count
);
1340 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1342 /* Adjust jump offset. */
1343 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1348 /* Maximum length of an instruction is 15 byte. If the
1349 padding is greater than 15 bytes and we don't use jump,
1350 we have to break it into smaller pieces. */
1351 int padding
= count
;
1352 while (padding
> 15)
1355 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1360 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1361 patt
[padding
- 1], padding
);
1364 fragP
->fr_var
= count
;
1368 operand_type_all_zero (const union i386_operand_type
*x
)
1370 switch (ARRAY_SIZE(x
->array
))
1379 return !x
->array
[0];
1386 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1388 switch (ARRAY_SIZE(x
->array
))
1403 operand_type_equal (const union i386_operand_type
*x
,
1404 const union i386_operand_type
*y
)
1406 switch (ARRAY_SIZE(x
->array
))
1409 if (x
->array
[2] != y
->array
[2])
1412 if (x
->array
[1] != y
->array
[1])
1415 return x
->array
[0] == y
->array
[0];
1423 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1425 switch (ARRAY_SIZE(x
->array
))
1434 return !x
->array
[0];
1441 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1443 switch (ARRAY_SIZE(x
->array
))
1458 cpu_flags_equal (const union i386_cpu_flags
*x
,
1459 const union i386_cpu_flags
*y
)
1461 switch (ARRAY_SIZE(x
->array
))
1464 if (x
->array
[2] != y
->array
[2])
1467 if (x
->array
[1] != y
->array
[1])
1470 return x
->array
[0] == y
->array
[0];
1478 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1480 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1481 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1484 static INLINE i386_cpu_flags
1485 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1487 switch (ARRAY_SIZE (x
.array
))
1490 x
.array
[2] &= y
.array
[2];
1492 x
.array
[1] &= y
.array
[1];
1494 x
.array
[0] &= y
.array
[0];
1502 static INLINE i386_cpu_flags
1503 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1505 switch (ARRAY_SIZE (x
.array
))
1508 x
.array
[2] |= y
.array
[2];
1510 x
.array
[1] |= y
.array
[1];
1512 x
.array
[0] |= y
.array
[0];
1520 static INLINE i386_cpu_flags
1521 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1523 switch (ARRAY_SIZE (x
.array
))
1526 x
.array
[2] &= ~y
.array
[2];
1528 x
.array
[1] &= ~y
.array
[1];
1530 x
.array
[0] &= ~y
.array
[0];
1538 #define CPU_FLAGS_ARCH_MATCH 0x1
1539 #define CPU_FLAGS_64BIT_MATCH 0x2
1540 #define CPU_FLAGS_AES_MATCH 0x4
1541 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1542 #define CPU_FLAGS_AVX_MATCH 0x10
1544 #define CPU_FLAGS_32BIT_MATCH \
1545 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1546 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1547 #define CPU_FLAGS_PERFECT_MATCH \
1548 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1550 /* Return CPU flags match bits. */
1553 cpu_flags_match (const insn_template
*t
)
1555 i386_cpu_flags x
= t
->cpu_flags
;
1556 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1558 x
.bitfield
.cpu64
= 0;
1559 x
.bitfield
.cpuno64
= 0;
1561 if (cpu_flags_all_zero (&x
))
1563 /* This instruction is available on all archs. */
1564 match
|= CPU_FLAGS_32BIT_MATCH
;
1568 /* This instruction is available only on some archs. */
1569 i386_cpu_flags cpu
= cpu_arch_flags
;
1571 cpu
.bitfield
.cpu64
= 0;
1572 cpu
.bitfield
.cpuno64
= 0;
1573 cpu
= cpu_flags_and (x
, cpu
);
1574 if (!cpu_flags_all_zero (&cpu
))
1576 if (x
.bitfield
.cpuavx
)
1578 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1579 if (cpu
.bitfield
.cpuavx
)
1581 /* Check SSE2AVX. */
1582 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1584 match
|= (CPU_FLAGS_ARCH_MATCH
1585 | CPU_FLAGS_AVX_MATCH
);
1587 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1588 match
|= CPU_FLAGS_AES_MATCH
;
1590 if (!x
.bitfield
.cpupclmul
1591 || cpu
.bitfield
.cpupclmul
)
1592 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1596 match
|= CPU_FLAGS_ARCH_MATCH
;
1599 match
|= CPU_FLAGS_32BIT_MATCH
;
1605 static INLINE i386_operand_type
1606 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1608 switch (ARRAY_SIZE (x
.array
))
1611 x
.array
[2] &= y
.array
[2];
1613 x
.array
[1] &= y
.array
[1];
1615 x
.array
[0] &= y
.array
[0];
1623 static INLINE i386_operand_type
1624 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[2] |= y
.array
[2];
1631 x
.array
[1] |= y
.array
[1];
1633 x
.array
[0] |= y
.array
[0];
1641 static INLINE i386_operand_type
1642 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1644 switch (ARRAY_SIZE (x
.array
))
1647 x
.array
[2] ^= y
.array
[2];
1649 x
.array
[1] ^= y
.array
[1];
1651 x
.array
[0] ^= y
.array
[0];
1659 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1660 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1661 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1662 static const i386_operand_type inoutportreg
1663 = OPERAND_TYPE_INOUTPORTREG
;
1664 static const i386_operand_type reg16_inoutportreg
1665 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1666 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1667 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1668 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1669 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1670 static const i386_operand_type anydisp
1671 = OPERAND_TYPE_ANYDISP
;
1672 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1673 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1674 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1675 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1676 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1677 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1678 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1679 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1680 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1681 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1682 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1683 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1684 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1685 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1696 operand_type_check (i386_operand_type t
, enum operand_type c
)
1701 return (t
.bitfield
.reg8
1704 || t
.bitfield
.reg64
);
1707 return (t
.bitfield
.imm8
1711 || t
.bitfield
.imm32s
1712 || t
.bitfield
.imm64
);
1715 return (t
.bitfield
.disp8
1716 || t
.bitfield
.disp16
1717 || t
.bitfield
.disp32
1718 || t
.bitfield
.disp32s
1719 || t
.bitfield
.disp64
);
1722 return (t
.bitfield
.disp8
1723 || t
.bitfield
.disp16
1724 || t
.bitfield
.disp32
1725 || t
.bitfield
.disp32s
1726 || t
.bitfield
.disp64
1727 || t
.bitfield
.baseindex
);
1736 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1737 operand J for instruction template T. */
1740 match_reg_size (const insn_template
*t
, unsigned int j
)
1742 return !((i
.types
[j
].bitfield
.byte
1743 && !t
->operand_types
[j
].bitfield
.byte
)
1744 || (i
.types
[j
].bitfield
.word
1745 && !t
->operand_types
[j
].bitfield
.word
)
1746 || (i
.types
[j
].bitfield
.dword
1747 && !t
->operand_types
[j
].bitfield
.dword
)
1748 || (i
.types
[j
].bitfield
.qword
1749 && !t
->operand_types
[j
].bitfield
.qword
));
1752 /* Return 1 if there is no conflict in any size on operand J for
1753 instruction template T. */
1756 match_mem_size (const insn_template
*t
, unsigned int j
)
1758 return (match_reg_size (t
, j
)
1759 && !((i
.types
[j
].bitfield
.unspecified
1760 && !t
->operand_types
[j
].bitfield
.unspecified
)
1761 || (i
.types
[j
].bitfield
.fword
1762 && !t
->operand_types
[j
].bitfield
.fword
)
1763 || (i
.types
[j
].bitfield
.tbyte
1764 && !t
->operand_types
[j
].bitfield
.tbyte
)
1765 || (i
.types
[j
].bitfield
.xmmword
1766 && !t
->operand_types
[j
].bitfield
.xmmword
)
1767 || (i
.types
[j
].bitfield
.ymmword
1768 && !t
->operand_types
[j
].bitfield
.ymmword
)
1769 || (i
.types
[j
].bitfield
.zmmword
1770 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1773 /* Return 1 if there is no size conflict on any operands for
1774 instruction template T. */
1777 operand_size_match (const insn_template
*t
)
1782 /* Don't check jump instructions. */
1783 if (t
->opcode_modifier
.jump
1784 || t
->opcode_modifier
.jumpbyte
1785 || t
->opcode_modifier
.jumpdword
1786 || t
->opcode_modifier
.jumpintersegment
)
1789 /* Check memory and accumulator operand size. */
1790 for (j
= 0; j
< i
.operands
; j
++)
1792 if (t
->operand_types
[j
].bitfield
.anysize
)
1795 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1801 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1810 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1813 i
.error
= operand_size_mismatch
;
1817 /* Check reverse. */
1818 gas_assert (i
.operands
== 2);
1821 for (j
= 0; j
< 2; j
++)
1823 if (t
->operand_types
[j
].bitfield
.acc
1824 && !match_reg_size (t
, j
? 0 : 1))
1827 if (i
.types
[j
].bitfield
.mem
1828 && !match_mem_size (t
, j
? 0 : 1))
1836 operand_type_match (i386_operand_type overlap
,
1837 i386_operand_type given
)
1839 i386_operand_type temp
= overlap
;
1841 temp
.bitfield
.jumpabsolute
= 0;
1842 temp
.bitfield
.unspecified
= 0;
1843 temp
.bitfield
.byte
= 0;
1844 temp
.bitfield
.word
= 0;
1845 temp
.bitfield
.dword
= 0;
1846 temp
.bitfield
.fword
= 0;
1847 temp
.bitfield
.qword
= 0;
1848 temp
.bitfield
.tbyte
= 0;
1849 temp
.bitfield
.xmmword
= 0;
1850 temp
.bitfield
.ymmword
= 0;
1851 temp
.bitfield
.zmmword
= 0;
1852 if (operand_type_all_zero (&temp
))
1855 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1856 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1860 i
.error
= operand_type_mismatch
;
1864 /* If given types g0 and g1 are registers they must be of the same type
1865 unless the expected operand type register overlap is null.
1866 Note that Acc in a template matches every size of reg. */
1869 operand_type_register_match (i386_operand_type m0
,
1870 i386_operand_type g0
,
1871 i386_operand_type t0
,
1872 i386_operand_type m1
,
1873 i386_operand_type g1
,
1874 i386_operand_type t1
)
1876 if (!operand_type_check (g0
, reg
))
1879 if (!operand_type_check (g1
, reg
))
1882 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1883 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1884 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1885 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1888 if (m0
.bitfield
.acc
)
1890 t0
.bitfield
.reg8
= 1;
1891 t0
.bitfield
.reg16
= 1;
1892 t0
.bitfield
.reg32
= 1;
1893 t0
.bitfield
.reg64
= 1;
1896 if (m1
.bitfield
.acc
)
1898 t1
.bitfield
.reg8
= 1;
1899 t1
.bitfield
.reg16
= 1;
1900 t1
.bitfield
.reg32
= 1;
1901 t1
.bitfield
.reg64
= 1;
1904 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1905 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1906 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1907 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1910 i
.error
= register_type_mismatch
;
1915 static INLINE
unsigned int
1916 register_number (const reg_entry
*r
)
1918 unsigned int nr
= r
->reg_num
;
1920 if (r
->reg_flags
& RegRex
)
1926 static INLINE
unsigned int
1927 mode_from_disp_size (i386_operand_type t
)
1929 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1931 else if (t
.bitfield
.disp16
1932 || t
.bitfield
.disp32
1933 || t
.bitfield
.disp32s
)
1940 fits_in_signed_byte (offsetT num
)
1942 return (num
>= -128) && (num
<= 127);
1946 fits_in_unsigned_byte (offsetT num
)
1948 return (num
& 0xff) == num
;
1952 fits_in_unsigned_word (offsetT num
)
1954 return (num
& 0xffff) == num
;
1958 fits_in_signed_word (offsetT num
)
1960 return (-32768 <= num
) && (num
<= 32767);
1964 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1969 return (!(((offsetT
) -1 << 31) & num
)
1970 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1972 } /* fits_in_signed_long() */
1975 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1980 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1982 } /* fits_in_unsigned_long() */
1985 fits_in_vec_disp8 (offsetT num
)
1987 int shift
= i
.memshift
;
1993 mask
= (1 << shift
) - 1;
1995 /* Return 0 if NUM isn't properly aligned. */
1999 /* Check if NUM will fit in 8bit after shift. */
2000 return fits_in_signed_byte (num
>> shift
);
2004 fits_in_imm4 (offsetT num
)
2006 return (num
& 0xf) == num
;
2009 static i386_operand_type
2010 smallest_imm_type (offsetT num
)
2012 i386_operand_type t
;
2014 operand_type_set (&t
, 0);
2015 t
.bitfield
.imm64
= 1;
2017 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2019 /* This code is disabled on the 486 because all the Imm1 forms
2020 in the opcode table are slower on the i486. They're the
2021 versions with the implicitly specified single-position
2022 displacement, which has another syntax if you really want to
2024 t
.bitfield
.imm1
= 1;
2025 t
.bitfield
.imm8
= 1;
2026 t
.bitfield
.imm8s
= 1;
2027 t
.bitfield
.imm16
= 1;
2028 t
.bitfield
.imm32
= 1;
2029 t
.bitfield
.imm32s
= 1;
2031 else if (fits_in_signed_byte (num
))
2033 t
.bitfield
.imm8
= 1;
2034 t
.bitfield
.imm8s
= 1;
2035 t
.bitfield
.imm16
= 1;
2036 t
.bitfield
.imm32
= 1;
2037 t
.bitfield
.imm32s
= 1;
2039 else if (fits_in_unsigned_byte (num
))
2041 t
.bitfield
.imm8
= 1;
2042 t
.bitfield
.imm16
= 1;
2043 t
.bitfield
.imm32
= 1;
2044 t
.bitfield
.imm32s
= 1;
2046 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2048 t
.bitfield
.imm16
= 1;
2049 t
.bitfield
.imm32
= 1;
2050 t
.bitfield
.imm32s
= 1;
2052 else if (fits_in_signed_long (num
))
2054 t
.bitfield
.imm32
= 1;
2055 t
.bitfield
.imm32s
= 1;
2057 else if (fits_in_unsigned_long (num
))
2058 t
.bitfield
.imm32
= 1;
2064 offset_in_range (offsetT val
, int size
)
2070 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2071 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2072 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2074 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2080 /* If BFD64, sign extend val for 32bit address mode. */
2081 if (flag_code
!= CODE_64BIT
2082 || i
.prefix
[ADDR_PREFIX
])
2083 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2084 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2087 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2089 char buf1
[40], buf2
[40];
2091 sprint_value (buf1
, val
);
2092 sprint_value (buf2
, val
& mask
);
2093 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2107 a. PREFIX_EXIST if attempting to add a prefix where one from the
2108 same class already exists.
2109 b. PREFIX_LOCK if lock prefix is added.
2110 c. PREFIX_REP if rep/repne prefix is added.
2111 d. PREFIX_OTHER if other prefix is added.
2114 static enum PREFIX_GROUP
2115 add_prefix (unsigned int prefix
)
2117 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2120 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2121 && flag_code
== CODE_64BIT
)
2123 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2124 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2125 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2136 case CS_PREFIX_OPCODE
:
2137 case DS_PREFIX_OPCODE
:
2138 case ES_PREFIX_OPCODE
:
2139 case FS_PREFIX_OPCODE
:
2140 case GS_PREFIX_OPCODE
:
2141 case SS_PREFIX_OPCODE
:
2145 case REPNE_PREFIX_OPCODE
:
2146 case REPE_PREFIX_OPCODE
:
2151 case LOCK_PREFIX_OPCODE
:
2160 case ADDR_PREFIX_OPCODE
:
2164 case DATA_PREFIX_OPCODE
:
2168 if (i
.prefix
[q
] != 0)
2176 i
.prefix
[q
] |= prefix
;
2179 as_bad (_("same type of prefix used twice"));
2185 update_code_flag (int value
, int check
)
2187 PRINTF_LIKE ((*as_error
));
2189 flag_code
= (enum flag_code
) value
;
2190 if (flag_code
== CODE_64BIT
)
2192 cpu_arch_flags
.bitfield
.cpu64
= 1;
2193 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2197 cpu_arch_flags
.bitfield
.cpu64
= 0;
2198 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2200 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2203 as_error
= as_fatal
;
2206 (*as_error
) (_("64bit mode not supported on `%s'."),
2207 cpu_arch_name
? cpu_arch_name
: default_arch
);
2209 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2212 as_error
= as_fatal
;
2215 (*as_error
) (_("32bit mode not supported on `%s'."),
2216 cpu_arch_name
? cpu_arch_name
: default_arch
);
2218 stackop_size
= '\0';
2222 set_code_flag (int value
)
2224 update_code_flag (value
, 0);
2228 set_16bit_gcc_code_flag (int new_code_flag
)
2230 flag_code
= (enum flag_code
) new_code_flag
;
2231 if (flag_code
!= CODE_16BIT
)
2233 cpu_arch_flags
.bitfield
.cpu64
= 0;
2234 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2235 stackop_size
= LONG_MNEM_SUFFIX
;
2239 set_intel_syntax (int syntax_flag
)
2241 /* Find out if register prefixing is specified. */
2242 int ask_naked_reg
= 0;
2245 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2247 char *string
= input_line_pointer
;
2248 int e
= get_symbol_end ();
2250 if (strcmp (string
, "prefix") == 0)
2252 else if (strcmp (string
, "noprefix") == 0)
2255 as_bad (_("bad argument to syntax directive."));
2256 *input_line_pointer
= e
;
2258 demand_empty_rest_of_line ();
2260 intel_syntax
= syntax_flag
;
2262 if (ask_naked_reg
== 0)
2263 allow_naked_reg
= (intel_syntax
2264 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2266 allow_naked_reg
= (ask_naked_reg
< 0);
2268 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2270 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2271 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2272 register_prefix
= allow_naked_reg
? "" : "%";
2276 set_intel_mnemonic (int mnemonic_flag
)
2278 intel_mnemonic
= mnemonic_flag
;
2282 set_allow_index_reg (int flag
)
2284 allow_index_reg
= flag
;
2288 set_check (int what
)
2290 enum check_kind
*kind
;
2295 kind
= &operand_check
;
2306 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2308 char *string
= input_line_pointer
;
2309 int e
= get_symbol_end ();
2311 if (strcmp (string
, "none") == 0)
2313 else if (strcmp (string
, "warning") == 0)
2314 *kind
= check_warning
;
2315 else if (strcmp (string
, "error") == 0)
2316 *kind
= check_error
;
2318 as_bad (_("bad argument to %s_check directive."), str
);
2319 *input_line_pointer
= e
;
2322 as_bad (_("missing argument for %s_check directive"), str
);
2324 demand_empty_rest_of_line ();
2328 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2329 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2332 static const char *arch
;
2334 /* Intel LIOM is only supported on ELF. */
2340 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2341 use default_arch. */
2342 arch
= cpu_arch_name
;
2344 arch
= default_arch
;
2347 /* If we are targeting Intel L1OM, we must enable it. */
2348 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2349 || new_flag
.bitfield
.cpul1om
)
2352 /* If we are targeting Intel K1OM, we must enable it. */
2353 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2354 || new_flag
.bitfield
.cpuk1om
)
2357 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2362 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2366 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2368 char *string
= input_line_pointer
;
2369 int e
= get_symbol_end ();
2371 i386_cpu_flags flags
;
2373 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2375 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2377 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2381 cpu_arch_name
= cpu_arch
[j
].name
;
2382 cpu_sub_arch_name
= NULL
;
2383 cpu_arch_flags
= cpu_arch
[j
].flags
;
2384 if (flag_code
== CODE_64BIT
)
2386 cpu_arch_flags
.bitfield
.cpu64
= 1;
2387 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2391 cpu_arch_flags
.bitfield
.cpu64
= 0;
2392 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2394 cpu_arch_isa
= cpu_arch
[j
].type
;
2395 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2396 if (!cpu_arch_tune_set
)
2398 cpu_arch_tune
= cpu_arch_isa
;
2399 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2404 if (!cpu_arch
[j
].negated
)
2405 flags
= cpu_flags_or (cpu_arch_flags
,
2408 flags
= cpu_flags_and_not (cpu_arch_flags
,
2410 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2412 if (cpu_sub_arch_name
)
2414 char *name
= cpu_sub_arch_name
;
2415 cpu_sub_arch_name
= concat (name
,
2417 (const char *) NULL
);
2421 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2422 cpu_arch_flags
= flags
;
2423 cpu_arch_isa_flags
= flags
;
2425 *input_line_pointer
= e
;
2426 demand_empty_rest_of_line ();
2430 if (j
>= ARRAY_SIZE (cpu_arch
))
2431 as_bad (_("no such architecture: `%s'"), string
);
2433 *input_line_pointer
= e
;
2436 as_bad (_("missing cpu architecture"));
2438 no_cond_jump_promotion
= 0;
2439 if (*input_line_pointer
== ','
2440 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2442 char *string
= ++input_line_pointer
;
2443 int e
= get_symbol_end ();
2445 if (strcmp (string
, "nojumps") == 0)
2446 no_cond_jump_promotion
= 1;
2447 else if (strcmp (string
, "jumps") == 0)
2450 as_bad (_("no such architecture modifier: `%s'"), string
);
2452 *input_line_pointer
= e
;
2455 demand_empty_rest_of_line ();
2458 enum bfd_architecture
2461 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2463 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2464 || flag_code
!= CODE_64BIT
)
2465 as_fatal (_("Intel L1OM is 64bit ELF only"));
2466 return bfd_arch_l1om
;
2468 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2470 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2471 || flag_code
!= CODE_64BIT
)
2472 as_fatal (_("Intel K1OM is 64bit ELF only"));
2473 return bfd_arch_k1om
;
2476 return bfd_arch_i386
;
2482 if (!strncmp (default_arch
, "x86_64", 6))
2484 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2486 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2487 || default_arch
[6] != '\0')
2488 as_fatal (_("Intel L1OM is 64bit ELF only"));
2489 return bfd_mach_l1om
;
2491 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2493 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2494 || default_arch
[6] != '\0')
2495 as_fatal (_("Intel K1OM is 64bit ELF only"));
2496 return bfd_mach_k1om
;
2498 else if (default_arch
[6] == '\0')
2499 return bfd_mach_x86_64
;
2501 return bfd_mach_x64_32
;
2503 else if (!strcmp (default_arch
, "i386"))
2504 return bfd_mach_i386_i386
;
2506 as_fatal (_("unknown architecture"));
2512 const char *hash_err
;
2514 /* Initialize op_hash hash table. */
2515 op_hash
= hash_new ();
2518 const insn_template
*optab
;
2519 templates
*core_optab
;
2521 /* Setup for loop. */
2523 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2524 core_optab
->start
= optab
;
2529 if (optab
->name
== NULL
2530 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2532 /* different name --> ship out current template list;
2533 add to hash table; & begin anew. */
2534 core_optab
->end
= optab
;
2535 hash_err
= hash_insert (op_hash
,
2537 (void *) core_optab
);
2540 as_fatal (_("can't hash %s: %s"),
2544 if (optab
->name
== NULL
)
2546 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2547 core_optab
->start
= optab
;
2552 /* Initialize reg_hash hash table. */
2553 reg_hash
= hash_new ();
2555 const reg_entry
*regtab
;
2556 unsigned int regtab_size
= i386_regtab_size
;
2558 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2560 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2562 as_fatal (_("can't hash %s: %s"),
2568 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2573 for (c
= 0; c
< 256; c
++)
2578 mnemonic_chars
[c
] = c
;
2579 register_chars
[c
] = c
;
2580 operand_chars
[c
] = c
;
2582 else if (ISLOWER (c
))
2584 mnemonic_chars
[c
] = c
;
2585 register_chars
[c
] = c
;
2586 operand_chars
[c
] = c
;
2588 else if (ISUPPER (c
))
2590 mnemonic_chars
[c
] = TOLOWER (c
);
2591 register_chars
[c
] = mnemonic_chars
[c
];
2592 operand_chars
[c
] = c
;
2594 else if (c
== '{' || c
== '}')
2595 operand_chars
[c
] = c
;
2597 if (ISALPHA (c
) || ISDIGIT (c
))
2598 identifier_chars
[c
] = c
;
2601 identifier_chars
[c
] = c
;
2602 operand_chars
[c
] = c
;
2607 identifier_chars
['@'] = '@';
2610 identifier_chars
['?'] = '?';
2611 operand_chars
['?'] = '?';
2613 digit_chars
['-'] = '-';
2614 mnemonic_chars
['_'] = '_';
2615 mnemonic_chars
['-'] = '-';
2616 mnemonic_chars
['.'] = '.';
2617 identifier_chars
['_'] = '_';
2618 identifier_chars
['.'] = '.';
2620 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2621 operand_chars
[(unsigned char) *p
] = *p
;
2624 if (flag_code
== CODE_64BIT
)
2626 #if defined (OBJ_COFF) && defined (TE_PE)
2627 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2630 x86_dwarf2_return_column
= 16;
2632 x86_cie_data_alignment
= -8;
2636 x86_dwarf2_return_column
= 8;
2637 x86_cie_data_alignment
= -4;
2642 i386_print_statistics (FILE *file
)
2644 hash_print_statistics (file
, "i386 opcode", op_hash
);
2645 hash_print_statistics (file
, "i386 register", reg_hash
);
2650 /* Debugging routines for md_assemble. */
2651 static void pte (insn_template
*);
2652 static void pt (i386_operand_type
);
2653 static void pe (expressionS
*);
2654 static void ps (symbolS
*);
2657 pi (char *line
, i386_insn
*x
)
2661 fprintf (stdout
, "%s: template ", line
);
2663 fprintf (stdout
, " address: base %s index %s scale %x\n",
2664 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2665 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2666 x
->log2_scale_factor
);
2667 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2668 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2669 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2670 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2671 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2672 (x
->rex
& REX_W
) != 0,
2673 (x
->rex
& REX_R
) != 0,
2674 (x
->rex
& REX_X
) != 0,
2675 (x
->rex
& REX_B
) != 0);
2676 for (j
= 0; j
< x
->operands
; j
++)
2678 fprintf (stdout
, " #%d: ", j
+ 1);
2680 fprintf (stdout
, "\n");
2681 if (x
->types
[j
].bitfield
.reg8
2682 || x
->types
[j
].bitfield
.reg16
2683 || x
->types
[j
].bitfield
.reg32
2684 || x
->types
[j
].bitfield
.reg64
2685 || x
->types
[j
].bitfield
.regmmx
2686 || x
->types
[j
].bitfield
.regxmm
2687 || x
->types
[j
].bitfield
.regymm
2688 || x
->types
[j
].bitfield
.regzmm
2689 || x
->types
[j
].bitfield
.sreg2
2690 || x
->types
[j
].bitfield
.sreg3
2691 || x
->types
[j
].bitfield
.control
2692 || x
->types
[j
].bitfield
.debug
2693 || x
->types
[j
].bitfield
.test
)
2694 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2695 if (operand_type_check (x
->types
[j
], imm
))
2697 if (operand_type_check (x
->types
[j
], disp
))
2698 pe (x
->op
[j
].disps
);
2703 pte (insn_template
*t
)
2706 fprintf (stdout
, " %d operands ", t
->operands
);
2707 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2708 if (t
->extension_opcode
!= None
)
2709 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2710 if (t
->opcode_modifier
.d
)
2711 fprintf (stdout
, "D");
2712 if (t
->opcode_modifier
.w
)
2713 fprintf (stdout
, "W");
2714 fprintf (stdout
, "\n");
2715 for (j
= 0; j
< t
->operands
; j
++)
2717 fprintf (stdout
, " #%d type ", j
+ 1);
2718 pt (t
->operand_types
[j
]);
2719 fprintf (stdout
, "\n");
2726 fprintf (stdout
, " operation %d\n", e
->X_op
);
2727 fprintf (stdout
, " add_number %ld (%lx)\n",
2728 (long) e
->X_add_number
, (long) e
->X_add_number
);
2729 if (e
->X_add_symbol
)
2731 fprintf (stdout
, " add_symbol ");
2732 ps (e
->X_add_symbol
);
2733 fprintf (stdout
, "\n");
2737 fprintf (stdout
, " op_symbol ");
2738 ps (e
->X_op_symbol
);
2739 fprintf (stdout
, "\n");
2746 fprintf (stdout
, "%s type %s%s",
2748 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2749 segment_name (S_GET_SEGMENT (s
)));
2752 static struct type_name
2754 i386_operand_type mask
;
2757 const type_names
[] =
2759 { OPERAND_TYPE_REG8
, "r8" },
2760 { OPERAND_TYPE_REG16
, "r16" },
2761 { OPERAND_TYPE_REG32
, "r32" },
2762 { OPERAND_TYPE_REG64
, "r64" },
2763 { OPERAND_TYPE_IMM8
, "i8" },
2764 { OPERAND_TYPE_IMM8
, "i8s" },
2765 { OPERAND_TYPE_IMM16
, "i16" },
2766 { OPERAND_TYPE_IMM32
, "i32" },
2767 { OPERAND_TYPE_IMM32S
, "i32s" },
2768 { OPERAND_TYPE_IMM64
, "i64" },
2769 { OPERAND_TYPE_IMM1
, "i1" },
2770 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2771 { OPERAND_TYPE_DISP8
, "d8" },
2772 { OPERAND_TYPE_DISP16
, "d16" },
2773 { OPERAND_TYPE_DISP32
, "d32" },
2774 { OPERAND_TYPE_DISP32S
, "d32s" },
2775 { OPERAND_TYPE_DISP64
, "d64" },
2776 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2777 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2778 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2779 { OPERAND_TYPE_CONTROL
, "control reg" },
2780 { OPERAND_TYPE_TEST
, "test reg" },
2781 { OPERAND_TYPE_DEBUG
, "debug reg" },
2782 { OPERAND_TYPE_FLOATREG
, "FReg" },
2783 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2784 { OPERAND_TYPE_SREG2
, "SReg2" },
2785 { OPERAND_TYPE_SREG3
, "SReg3" },
2786 { OPERAND_TYPE_ACC
, "Acc" },
2787 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2788 { OPERAND_TYPE_REGMMX
, "rMMX" },
2789 { OPERAND_TYPE_REGXMM
, "rXMM" },
2790 { OPERAND_TYPE_REGYMM
, "rYMM" },
2791 { OPERAND_TYPE_REGZMM
, "rZMM" },
2792 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2793 { OPERAND_TYPE_ESSEG
, "es" },
2797 pt (i386_operand_type t
)
2800 i386_operand_type a
;
2802 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2804 a
= operand_type_and (t
, type_names
[j
].mask
);
2805 if (!operand_type_all_zero (&a
))
2806 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2811 #endif /* DEBUG386 */
2813 static bfd_reloc_code_real_type
2814 reloc (unsigned int size
,
2818 bfd_reloc_code_real_type other
)
2820 if (other
!= NO_RELOC
)
2822 reloc_howto_type
*rel
;
2827 case BFD_RELOC_X86_64_GOT32
:
2828 return BFD_RELOC_X86_64_GOT64
;
2830 case BFD_RELOC_X86_64_PLTOFF64
:
2831 return BFD_RELOC_X86_64_PLTOFF64
;
2833 case BFD_RELOC_X86_64_GOTPC32
:
2834 other
= BFD_RELOC_X86_64_GOTPC64
;
2836 case BFD_RELOC_X86_64_GOTPCREL
:
2837 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2839 case BFD_RELOC_X86_64_TPOFF32
:
2840 other
= BFD_RELOC_X86_64_TPOFF64
;
2842 case BFD_RELOC_X86_64_DTPOFF32
:
2843 other
= BFD_RELOC_X86_64_DTPOFF64
;
2849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2850 if (other
== BFD_RELOC_SIZE32
)
2853 other
= BFD_RELOC_SIZE64
;
2856 as_bad (_("there are no pc-relative size relocations"));
2862 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2863 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2866 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2868 as_bad (_("unknown relocation (%u)"), other
);
2869 else if (size
!= bfd_get_reloc_size (rel
))
2870 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2871 bfd_get_reloc_size (rel
),
2873 else if (pcrel
&& !rel
->pc_relative
)
2874 as_bad (_("non-pc-relative relocation for pc-relative field"));
2875 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2877 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2879 as_bad (_("relocated field and relocation type differ in signedness"));
2888 as_bad (_("there are no unsigned pc-relative relocations"));
2891 case 1: return BFD_RELOC_8_PCREL
;
2892 case 2: return BFD_RELOC_16_PCREL
;
2893 case 4: return (bnd_prefix
&& object_64bit
2894 ? BFD_RELOC_X86_64_PC32_BND
2895 : BFD_RELOC_32_PCREL
);
2896 case 8: return BFD_RELOC_64_PCREL
;
2898 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2905 case 4: return BFD_RELOC_X86_64_32S
;
2910 case 1: return BFD_RELOC_8
;
2911 case 2: return BFD_RELOC_16
;
2912 case 4: return BFD_RELOC_32
;
2913 case 8: return BFD_RELOC_64
;
2915 as_bad (_("cannot do %s %u byte relocation"),
2916 sign
> 0 ? "signed" : "unsigned", size
);
2922 /* Here we decide which fixups can be adjusted to make them relative to
2923 the beginning of the section instead of the symbol. Basically we need
2924 to make sure that the dynamic relocations are done correctly, so in
2925 some cases we force the original symbol to be used. */
2928 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2934 /* Don't adjust pc-relative references to merge sections in 64-bit
2936 if (use_rela_relocations
2937 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2941 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2942 and changed later by validate_fix. */
2943 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2944 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2947 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2948 for size relocations. */
2949 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2950 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2951 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2952 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2953 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2954 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2955 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2956 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2957 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2958 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2959 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2960 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2961 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2962 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2963 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2964 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2965 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2968 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2969 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2970 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2971 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2972 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2973 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2974 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2975 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2976 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2977 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2978 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2985 intel_float_operand (const char *mnemonic
)
2987 /* Note that the value returned is meaningful only for opcodes with (memory)
2988 operands, hence the code here is free to improperly handle opcodes that
2989 have no operands (for better performance and smaller code). */
2991 if (mnemonic
[0] != 'f')
2992 return 0; /* non-math */
2994 switch (mnemonic
[1])
2996 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2997 the fs segment override prefix not currently handled because no
2998 call path can make opcodes without operands get here */
3000 return 2 /* integer op */;
3002 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3003 return 3; /* fldcw/fldenv */
3006 if (mnemonic
[2] != 'o' /* fnop */)
3007 return 3; /* non-waiting control op */
3010 if (mnemonic
[2] == 's')
3011 return 3; /* frstor/frstpm */
3014 if (mnemonic
[2] == 'a')
3015 return 3; /* fsave */
3016 if (mnemonic
[2] == 't')
3018 switch (mnemonic
[3])
3020 case 'c': /* fstcw */
3021 case 'd': /* fstdw */
3022 case 'e': /* fstenv */
3023 case 's': /* fsts[gw] */
3029 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3030 return 0; /* fxsave/fxrstor are not really math ops */
3037 /* Build the VEX prefix. */
3040 build_vex_prefix (const insn_template
*t
)
3042 unsigned int register_specifier
;
3043 unsigned int implied_prefix
;
3044 unsigned int vector_length
;
3046 /* Check register specifier. */
3047 if (i
.vex
.register_specifier
)
3049 register_specifier
=
3050 ~register_number (i
.vex
.register_specifier
) & 0xf;
3051 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3054 register_specifier
= 0xf;
3056 /* Use 2-byte VEX prefix by swappping destination and source
3059 && i
.operands
== i
.reg_operands
3060 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3061 && i
.tm
.opcode_modifier
.s
3064 unsigned int xchg
= i
.operands
- 1;
3065 union i386_op temp_op
;
3066 i386_operand_type temp_type
;
3068 temp_type
= i
.types
[xchg
];
3069 i
.types
[xchg
] = i
.types
[0];
3070 i
.types
[0] = temp_type
;
3071 temp_op
= i
.op
[xchg
];
3072 i
.op
[xchg
] = i
.op
[0];
3075 gas_assert (i
.rm
.mode
== 3);
3079 i
.rm
.regmem
= i
.rm
.reg
;
3082 /* Use the next insn. */
3086 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3087 vector_length
= avxscalar
;
3089 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3091 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3096 case DATA_PREFIX_OPCODE
:
3099 case REPE_PREFIX_OPCODE
:
3102 case REPNE_PREFIX_OPCODE
:
3109 /* Use 2-byte VEX prefix if possible. */
3110 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3111 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3112 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3114 /* 2-byte VEX prefix. */
3118 i
.vex
.bytes
[0] = 0xc5;
3120 /* Check the REX.R bit. */
3121 r
= (i
.rex
& REX_R
) ? 0 : 1;
3122 i
.vex
.bytes
[1] = (r
<< 7
3123 | register_specifier
<< 3
3124 | vector_length
<< 2
3129 /* 3-byte VEX prefix. */
3134 switch (i
.tm
.opcode_modifier
.vexopcode
)
3138 i
.vex
.bytes
[0] = 0xc4;
3142 i
.vex
.bytes
[0] = 0xc4;
3146 i
.vex
.bytes
[0] = 0xc4;
3150 i
.vex
.bytes
[0] = 0x8f;
3154 i
.vex
.bytes
[0] = 0x8f;
3158 i
.vex
.bytes
[0] = 0x8f;
3164 /* The high 3 bits of the second VEX byte are 1's compliment
3165 of RXB bits from REX. */
3166 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3168 /* Check the REX.W bit. */
3169 w
= (i
.rex
& REX_W
) ? 1 : 0;
3170 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3173 i
.vex
.bytes
[2] = (w
<< 7
3174 | register_specifier
<< 3
3175 | vector_length
<< 2
3180 /* Build the EVEX prefix. */
3183 build_evex_prefix (void)
3185 unsigned int register_specifier
;
3186 unsigned int implied_prefix
;
3188 rex_byte vrex_used
= 0;
3190 /* Check register specifier. */
3191 if (i
.vex
.register_specifier
)
3193 gas_assert ((i
.vrex
& REX_X
) == 0);
3195 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3196 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3197 register_specifier
+= 8;
3198 /* The upper 16 registers are encoded in the fourth byte of the
3200 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3201 i
.vex
.bytes
[3] = 0x8;
3202 register_specifier
= ~register_specifier
& 0xf;
3206 register_specifier
= 0xf;
3208 /* Encode upper 16 vector index register in the fourth byte of
3210 if (!(i
.vrex
& REX_X
))
3211 i
.vex
.bytes
[3] = 0x8;
3216 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3221 case DATA_PREFIX_OPCODE
:
3224 case REPE_PREFIX_OPCODE
:
3227 case REPNE_PREFIX_OPCODE
:
3234 /* 4 byte EVEX prefix. */
3236 i
.vex
.bytes
[0] = 0x62;
3239 switch (i
.tm
.opcode_modifier
.vexopcode
)
3255 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3257 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3259 /* The fifth bit of the second EVEX byte is 1's compliment of the
3260 REX_R bit in VREX. */
3261 if (!(i
.vrex
& REX_R
))
3262 i
.vex
.bytes
[1] |= 0x10;
3266 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3268 /* When all operands are registers, the REX_X bit in REX is not
3269 used. We reuse it to encode the upper 16 registers, which is
3270 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3271 as 1's compliment. */
3272 if ((i
.vrex
& REX_B
))
3275 i
.vex
.bytes
[1] &= ~0x40;
3279 /* EVEX instructions shouldn't need the REX prefix. */
3280 i
.vrex
&= ~vrex_used
;
3281 gas_assert (i
.vrex
== 0);
3283 /* Check the REX.W bit. */
3284 w
= (i
.rex
& REX_W
) ? 1 : 0;
3285 if (i
.tm
.opcode_modifier
.vexw
)
3287 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3290 /* If w is not set it means we are dealing with WIG instruction. */
3293 if (evexwig
== evexw1
)
3297 /* Encode the U bit. */
3298 implied_prefix
|= 0x4;
3300 /* The third byte of the EVEX prefix. */
3301 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3303 /* The fourth byte of the EVEX prefix. */
3304 /* The zeroing-masking bit. */
3305 if (i
.mask
&& i
.mask
->zeroing
)
3306 i
.vex
.bytes
[3] |= 0x80;
3308 /* Don't always set the broadcast bit if there is no RC. */
3311 /* Encode the vector length. */
3312 unsigned int vec_length
;
3314 switch (i
.tm
.opcode_modifier
.evex
)
3316 case EVEXLIG
: /* LL' is ignored */
3317 vec_length
= evexlig
<< 5;
3320 vec_length
= 0 << 5;
3323 vec_length
= 1 << 5;
3326 vec_length
= 2 << 5;
3332 i
.vex
.bytes
[3] |= vec_length
;
3333 /* Encode the broadcast bit. */
3335 i
.vex
.bytes
[3] |= 0x10;
3339 if (i
.rounding
->type
!= saeonly
)
3340 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3342 i
.vex
.bytes
[3] |= 0x10;
3345 if (i
.mask
&& i
.mask
->mask
)
3346 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3350 process_immext (void)
3354 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3357 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3358 with an opcode suffix which is coded in the same place as an
3359 8-bit immediate field would be.
3360 Here we check those operands and remove them afterwards. */
3363 for (x
= 0; x
< i
.operands
; x
++)
3364 if (register_number (i
.op
[x
].regs
) != x
)
3365 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3366 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3372 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3373 which is coded in the same place as an 8-bit immediate field
3374 would be. Here we fake an 8-bit immediate operand from the
3375 opcode suffix stored in tm.extension_opcode.
3377 AVX instructions also use this encoding, for some of
3378 3 argument instructions. */
3380 gas_assert (i
.imm_operands
<= 1
3382 || ((i
.tm
.opcode_modifier
.vex
3383 || i
.tm
.opcode_modifier
.evex
)
3384 && i
.operands
<= 4)));
3386 exp
= &im_expressions
[i
.imm_operands
++];
3387 i
.op
[i
.operands
].imms
= exp
;
3388 i
.types
[i
.operands
] = imm8
;
3390 exp
->X_op
= O_constant
;
3391 exp
->X_add_number
= i
.tm
.extension_opcode
;
3392 i
.tm
.extension_opcode
= None
;
3399 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3404 as_bad (_("invalid instruction `%s' after `%s'"),
3405 i
.tm
.name
, i
.hle_prefix
);
3408 if (i
.prefix
[LOCK_PREFIX
])
3410 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3414 case HLEPrefixRelease
:
3415 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3417 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3421 if (i
.mem_operands
== 0
3422 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3424 as_bad (_("memory destination needed for instruction `%s'"
3425 " after `xrelease'"), i
.tm
.name
);
3432 /* This is the guts of the machine-dependent assembler. LINE points to a
3433 machine dependent instruction. This function is supposed to emit
3434 the frags/bytes it assembles to. */
3437 md_assemble (char *line
)
3440 char mnemonic
[MAX_MNEM_SIZE
];
3441 const insn_template
*t
;
3443 /* Initialize globals. */
3444 memset (&i
, '\0', sizeof (i
));
3445 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3446 i
.reloc
[j
] = NO_RELOC
;
3447 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3448 memset (im_expressions
, '\0', sizeof (im_expressions
));
3449 save_stack_p
= save_stack
;
3451 /* First parse an instruction mnemonic & call i386_operand for the operands.
3452 We assume that the scrubber has arranged it so that line[0] is the valid
3453 start of a (possibly prefixed) mnemonic. */
3455 line
= parse_insn (line
, mnemonic
);
3459 line
= parse_operands (line
, mnemonic
);
3464 /* Now we've parsed the mnemonic into a set of templates, and have the
3465 operands at hand. */
3467 /* All intel opcodes have reversed operands except for "bound" and
3468 "enter". We also don't reverse intersegment "jmp" and "call"
3469 instructions with 2 immediate operands so that the immediate segment
3470 precedes the offset, as it does when in AT&T mode. */
3473 && (strcmp (mnemonic
, "bound") != 0)
3474 && (strcmp (mnemonic
, "invlpga") != 0)
3475 && !(operand_type_check (i
.types
[0], imm
)
3476 && operand_type_check (i
.types
[1], imm
)))
3479 /* The order of the immediates should be reversed
3480 for 2 immediates extrq and insertq instructions */
3481 if (i
.imm_operands
== 2
3482 && (strcmp (mnemonic
, "extrq") == 0
3483 || strcmp (mnemonic
, "insertq") == 0))
3484 swap_2_operands (0, 1);
3489 /* Don't optimize displacement for movabs since it only takes 64bit
3492 && i
.disp_encoding
!= disp_encoding_32bit
3493 && (flag_code
!= CODE_64BIT
3494 || strcmp (mnemonic
, "movabs") != 0))
3497 /* Next, we find a template that matches the given insn,
3498 making sure the overlap of the given operands types is consistent
3499 with the template operand types. */
3501 if (!(t
= match_template ()))
3504 if (sse_check
!= check_none
3505 && !i
.tm
.opcode_modifier
.noavx
3506 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3507 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3508 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3509 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3510 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3511 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3513 (sse_check
== check_warning
3515 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3518 /* Zap movzx and movsx suffix. The suffix has been set from
3519 "word ptr" or "byte ptr" on the source operand in Intel syntax
3520 or extracted from mnemonic in AT&T syntax. But we'll use
3521 the destination register to choose the suffix for encoding. */
3522 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3524 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3525 there is no suffix, the default will be byte extension. */
3526 if (i
.reg_operands
!= 2
3529 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3534 if (i
.tm
.opcode_modifier
.fwait
)
3535 if (!add_prefix (FWAIT_OPCODE
))
3538 /* Check if REP prefix is OK. */
3539 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3541 as_bad (_("invalid instruction `%s' after `%s'"),
3542 i
.tm
.name
, i
.rep_prefix
);
3546 /* Check for lock without a lockable instruction. Destination operand
3547 must be memory unless it is xchg (0x86). */
3548 if (i
.prefix
[LOCK_PREFIX
]
3549 && (!i
.tm
.opcode_modifier
.islockable
3550 || i
.mem_operands
== 0
3551 || (i
.tm
.base_opcode
!= 0x86
3552 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3554 as_bad (_("expecting lockable instruction after `lock'"));
3558 /* Check if HLE prefix is OK. */
3559 if (i
.hle_prefix
&& !check_hle ())
3562 /* Check BND prefix. */
3563 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3564 as_bad (_("expecting valid branch instruction after `bnd'"));
3566 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3567 && flag_code
== CODE_64BIT
3568 && i
.prefix
[ADDR_PREFIX
])
3569 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3571 /* Insert BND prefix. */
3573 && i
.tm
.opcode_modifier
.bndprefixok
3574 && !i
.prefix
[BND_PREFIX
])
3575 add_prefix (BND_PREFIX_OPCODE
);
3577 /* Check string instruction segment overrides. */
3578 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3580 if (!check_string ())
3582 i
.disp_operands
= 0;
3585 if (!process_suffix ())
3588 /* Update operand types. */
3589 for (j
= 0; j
< i
.operands
; j
++)
3590 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3592 /* Make still unresolved immediate matches conform to size of immediate
3593 given in i.suffix. */
3594 if (!finalize_imm ())
3597 if (i
.types
[0].bitfield
.imm1
)
3598 i
.imm_operands
= 0; /* kludge for shift insns. */
3600 /* We only need to check those implicit registers for instructions
3601 with 3 operands or less. */
3602 if (i
.operands
<= 3)
3603 for (j
= 0; j
< i
.operands
; j
++)
3604 if (i
.types
[j
].bitfield
.inoutportreg
3605 || i
.types
[j
].bitfield
.shiftcount
3606 || i
.types
[j
].bitfield
.acc
3607 || i
.types
[j
].bitfield
.floatacc
)
3610 /* ImmExt should be processed after SSE2AVX. */
3611 if (!i
.tm
.opcode_modifier
.sse2avx
3612 && i
.tm
.opcode_modifier
.immext
)
3615 /* For insns with operands there are more diddles to do to the opcode. */
3618 if (!process_operands ())
3621 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3623 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3624 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3627 if (i
.tm
.opcode_modifier
.vex
)
3628 build_vex_prefix (t
);
3630 if (i
.tm
.opcode_modifier
.evex
)
3631 build_evex_prefix ();
3633 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3634 instructions may define INT_OPCODE as well, so avoid this corner
3635 case for those instructions that use MODRM. */
3636 if (i
.tm
.base_opcode
== INT_OPCODE
3637 && !i
.tm
.opcode_modifier
.modrm
3638 && i
.op
[0].imms
->X_add_number
== 3)
3640 i
.tm
.base_opcode
= INT3_OPCODE
;
3644 if ((i
.tm
.opcode_modifier
.jump
3645 || i
.tm
.opcode_modifier
.jumpbyte
3646 || i
.tm
.opcode_modifier
.jumpdword
)
3647 && i
.op
[0].disps
->X_op
== O_constant
)
3649 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3650 the absolute address given by the constant. Since ix86 jumps and
3651 calls are pc relative, we need to generate a reloc. */
3652 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3653 i
.op
[0].disps
->X_op
= O_symbol
;
3656 if (i
.tm
.opcode_modifier
.rex64
)
3659 /* For 8 bit registers we need an empty rex prefix. Also if the
3660 instruction already has a prefix, we need to convert old
3661 registers to new ones. */
3663 if ((i
.types
[0].bitfield
.reg8
3664 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3665 || (i
.types
[1].bitfield
.reg8
3666 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3667 || ((i
.types
[0].bitfield
.reg8
3668 || i
.types
[1].bitfield
.reg8
)
3673 i
.rex
|= REX_OPCODE
;
3674 for (x
= 0; x
< 2; x
++)
3676 /* Look for 8 bit operand that uses old registers. */
3677 if (i
.types
[x
].bitfield
.reg8
3678 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3680 /* In case it is "hi" register, give up. */
3681 if (i
.op
[x
].regs
->reg_num
> 3)
3682 as_bad (_("can't encode register '%s%s' in an "
3683 "instruction requiring REX prefix."),
3684 register_prefix
, i
.op
[x
].regs
->reg_name
);
3686 /* Otherwise it is equivalent to the extended register.
3687 Since the encoding doesn't change this is merely
3688 cosmetic cleanup for debug output. */
3690 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3696 add_prefix (REX_OPCODE
| i
.rex
);
3698 /* We are ready to output the insn. */
3703 parse_insn (char *line
, char *mnemonic
)
3706 char *token_start
= l
;
3709 const insn_template
*t
;
3715 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3720 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3722 as_bad (_("no such instruction: `%s'"), token_start
);
3727 if (!is_space_char (*l
)
3728 && *l
!= END_OF_INSN
3730 || (*l
!= PREFIX_SEPARATOR
3733 as_bad (_("invalid character %s in mnemonic"),
3734 output_invalid (*l
));
3737 if (token_start
== l
)
3739 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3740 as_bad (_("expecting prefix; got nothing"));
3742 as_bad (_("expecting mnemonic; got nothing"));
3746 /* Look up instruction (or prefix) via hash table. */
3747 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3749 if (*l
!= END_OF_INSN
3750 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3751 && current_templates
3752 && current_templates
->start
->opcode_modifier
.isprefix
)
3754 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3756 as_bad ((flag_code
!= CODE_64BIT
3757 ? _("`%s' is only supported in 64-bit mode")
3758 : _("`%s' is not supported in 64-bit mode")),
3759 current_templates
->start
->name
);
3762 /* If we are in 16-bit mode, do not allow addr16 or data16.
3763 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3764 if ((current_templates
->start
->opcode_modifier
.size16
3765 || current_templates
->start
->opcode_modifier
.size32
)
3766 && flag_code
!= CODE_64BIT
3767 && (current_templates
->start
->opcode_modifier
.size32
3768 ^ (flag_code
== CODE_16BIT
)))
3770 as_bad (_("redundant %s prefix"),
3771 current_templates
->start
->name
);
3774 /* Add prefix, checking for repeated prefixes. */
3775 switch (add_prefix (current_templates
->start
->base_opcode
))
3780 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3781 i
.hle_prefix
= current_templates
->start
->name
;
3782 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3783 i
.bnd_prefix
= current_templates
->start
->name
;
3785 i
.rep_prefix
= current_templates
->start
->name
;
3790 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3797 if (!current_templates
)
3799 /* Check if we should swap operand or force 32bit displacement in
3801 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3803 else if (mnem_p
- 3 == dot_p
3806 i
.disp_encoding
= disp_encoding_8bit
;
3807 else if (mnem_p
- 4 == dot_p
3811 i
.disp_encoding
= disp_encoding_32bit
;
3816 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3819 if (!current_templates
)
3822 /* See if we can get a match by trimming off a suffix. */
3825 case WORD_MNEM_SUFFIX
:
3826 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3827 i
.suffix
= SHORT_MNEM_SUFFIX
;
3829 case BYTE_MNEM_SUFFIX
:
3830 case QWORD_MNEM_SUFFIX
:
3831 i
.suffix
= mnem_p
[-1];
3833 current_templates
= (const templates
*) hash_find (op_hash
,
3836 case SHORT_MNEM_SUFFIX
:
3837 case LONG_MNEM_SUFFIX
:
3840 i
.suffix
= mnem_p
[-1];
3842 current_templates
= (const templates
*) hash_find (op_hash
,
3851 if (intel_float_operand (mnemonic
) == 1)
3852 i
.suffix
= SHORT_MNEM_SUFFIX
;
3854 i
.suffix
= LONG_MNEM_SUFFIX
;
3856 current_templates
= (const templates
*) hash_find (op_hash
,
3861 if (!current_templates
)
3863 as_bad (_("no such instruction: `%s'"), token_start
);
3868 if (current_templates
->start
->opcode_modifier
.jump
3869 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3871 /* Check for a branch hint. We allow ",pt" and ",pn" for
3872 predict taken and predict not taken respectively.
3873 I'm not sure that branch hints actually do anything on loop
3874 and jcxz insns (JumpByte) for current Pentium4 chips. They
3875 may work in the future and it doesn't hurt to accept them
3877 if (l
[0] == ',' && l
[1] == 'p')
3881 if (!add_prefix (DS_PREFIX_OPCODE
))
3885 else if (l
[2] == 'n')
3887 if (!add_prefix (CS_PREFIX_OPCODE
))
3893 /* Any other comma loses. */
3896 as_bad (_("invalid character %s in mnemonic"),
3897 output_invalid (*l
));
3901 /* Check if instruction is supported on specified architecture. */
3903 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3905 supported
|= cpu_flags_match (t
);
3906 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3910 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3912 as_bad (flag_code
== CODE_64BIT
3913 ? _("`%s' is not supported in 64-bit mode")
3914 : _("`%s' is only supported in 64-bit mode"),
3915 current_templates
->start
->name
);
3918 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3920 as_bad (_("`%s' is not supported on `%s%s'"),
3921 current_templates
->start
->name
,
3922 cpu_arch_name
? cpu_arch_name
: default_arch
,
3923 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3928 if (!cpu_arch_flags
.bitfield
.cpui386
3929 && (flag_code
!= CODE_16BIT
))
3931 as_warn (_("use .code16 to ensure correct addressing mode"));
3938 parse_operands (char *l
, const char *mnemonic
)
3942 /* 1 if operand is pending after ','. */
3943 unsigned int expecting_operand
= 0;
3945 /* Non-zero if operand parens not balanced. */
3946 unsigned int paren_not_balanced
;
3948 while (*l
!= END_OF_INSN
)
3950 /* Skip optional white space before operand. */
3951 if (is_space_char (*l
))
3953 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3955 as_bad (_("invalid character %s before operand %d"),
3956 output_invalid (*l
),
3960 token_start
= l
; /* after white space */
3961 paren_not_balanced
= 0;
3962 while (paren_not_balanced
|| *l
!= ',')
3964 if (*l
== END_OF_INSN
)
3966 if (paren_not_balanced
)
3969 as_bad (_("unbalanced parenthesis in operand %d."),
3972 as_bad (_("unbalanced brackets in operand %d."),
3977 break; /* we are done */
3979 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3981 as_bad (_("invalid character %s in operand %d"),
3982 output_invalid (*l
),
3989 ++paren_not_balanced
;
3991 --paren_not_balanced
;
3996 ++paren_not_balanced
;
3998 --paren_not_balanced
;
4002 if (l
!= token_start
)
4003 { /* Yes, we've read in another operand. */
4004 unsigned int operand_ok
;
4005 this_operand
= i
.operands
++;
4006 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4007 if (i
.operands
> MAX_OPERANDS
)
4009 as_bad (_("spurious operands; (%d operands/instruction max)"),
4013 /* Now parse operand adding info to 'i' as we go along. */
4014 END_STRING_AND_SAVE (l
);
4018 i386_intel_operand (token_start
,
4019 intel_float_operand (mnemonic
));
4021 operand_ok
= i386_att_operand (token_start
);
4023 RESTORE_END_STRING (l
);
4029 if (expecting_operand
)
4031 expecting_operand_after_comma
:
4032 as_bad (_("expecting operand after ','; got nothing"));
4037 as_bad (_("expecting operand before ','; got nothing"));
4042 /* Now *l must be either ',' or END_OF_INSN. */
4045 if (*++l
== END_OF_INSN
)
4047 /* Just skip it, if it's \n complain. */
4048 goto expecting_operand_after_comma
;
4050 expecting_operand
= 1;
4057 swap_2_operands (int xchg1
, int xchg2
)
4059 union i386_op temp_op
;
4060 i386_operand_type temp_type
;
4061 enum bfd_reloc_code_real temp_reloc
;
4063 temp_type
= i
.types
[xchg2
];
4064 i
.types
[xchg2
] = i
.types
[xchg1
];
4065 i
.types
[xchg1
] = temp_type
;
4066 temp_op
= i
.op
[xchg2
];
4067 i
.op
[xchg2
] = i
.op
[xchg1
];
4068 i
.op
[xchg1
] = temp_op
;
4069 temp_reloc
= i
.reloc
[xchg2
];
4070 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4071 i
.reloc
[xchg1
] = temp_reloc
;
4075 if (i
.mask
->operand
== xchg1
)
4076 i
.mask
->operand
= xchg2
;
4077 else if (i
.mask
->operand
== xchg2
)
4078 i
.mask
->operand
= xchg1
;
4082 if (i
.broadcast
->operand
== xchg1
)
4083 i
.broadcast
->operand
= xchg2
;
4084 else if (i
.broadcast
->operand
== xchg2
)
4085 i
.broadcast
->operand
= xchg1
;
4089 if (i
.rounding
->operand
== xchg1
)
4090 i
.rounding
->operand
= xchg2
;
4091 else if (i
.rounding
->operand
== xchg2
)
4092 i
.rounding
->operand
= xchg1
;
4097 swap_operands (void)
4103 swap_2_operands (1, i
.operands
- 2);
4106 swap_2_operands (0, i
.operands
- 1);
4112 if (i
.mem_operands
== 2)
4114 const seg_entry
*temp_seg
;
4115 temp_seg
= i
.seg
[0];
4116 i
.seg
[0] = i
.seg
[1];
4117 i
.seg
[1] = temp_seg
;
4121 /* Try to ensure constant immediates are represented in the smallest
4126 char guess_suffix
= 0;
4130 guess_suffix
= i
.suffix
;
4131 else if (i
.reg_operands
)
4133 /* Figure out a suffix from the last register operand specified.
4134 We can't do this properly yet, ie. excluding InOutPortReg,
4135 but the following works for instructions with immediates.
4136 In any case, we can't set i.suffix yet. */
4137 for (op
= i
.operands
; --op
>= 0;)
4138 if (i
.types
[op
].bitfield
.reg8
)
4140 guess_suffix
= BYTE_MNEM_SUFFIX
;
4143 else if (i
.types
[op
].bitfield
.reg16
)
4145 guess_suffix
= WORD_MNEM_SUFFIX
;
4148 else if (i
.types
[op
].bitfield
.reg32
)
4150 guess_suffix
= LONG_MNEM_SUFFIX
;
4153 else if (i
.types
[op
].bitfield
.reg64
)
4155 guess_suffix
= QWORD_MNEM_SUFFIX
;
4159 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4160 guess_suffix
= WORD_MNEM_SUFFIX
;
4162 for (op
= i
.operands
; --op
>= 0;)
4163 if (operand_type_check (i
.types
[op
], imm
))
4165 switch (i
.op
[op
].imms
->X_op
)
4168 /* If a suffix is given, this operand may be shortened. */
4169 switch (guess_suffix
)
4171 case LONG_MNEM_SUFFIX
:
4172 i
.types
[op
].bitfield
.imm32
= 1;
4173 i
.types
[op
].bitfield
.imm64
= 1;
4175 case WORD_MNEM_SUFFIX
:
4176 i
.types
[op
].bitfield
.imm16
= 1;
4177 i
.types
[op
].bitfield
.imm32
= 1;
4178 i
.types
[op
].bitfield
.imm32s
= 1;
4179 i
.types
[op
].bitfield
.imm64
= 1;
4181 case BYTE_MNEM_SUFFIX
:
4182 i
.types
[op
].bitfield
.imm8
= 1;
4183 i
.types
[op
].bitfield
.imm8s
= 1;
4184 i
.types
[op
].bitfield
.imm16
= 1;
4185 i
.types
[op
].bitfield
.imm32
= 1;
4186 i
.types
[op
].bitfield
.imm32s
= 1;
4187 i
.types
[op
].bitfield
.imm64
= 1;
4191 /* If this operand is at most 16 bits, convert it
4192 to a signed 16 bit number before trying to see
4193 whether it will fit in an even smaller size.
4194 This allows a 16-bit operand such as $0xffe0 to
4195 be recognised as within Imm8S range. */
4196 if ((i
.types
[op
].bitfield
.imm16
)
4197 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4199 i
.op
[op
].imms
->X_add_number
=
4200 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4202 if ((i
.types
[op
].bitfield
.imm32
)
4203 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4206 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4207 ^ ((offsetT
) 1 << 31))
4208 - ((offsetT
) 1 << 31));
4211 = operand_type_or (i
.types
[op
],
4212 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4214 /* We must avoid matching of Imm32 templates when 64bit
4215 only immediate is available. */
4216 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4217 i
.types
[op
].bitfield
.imm32
= 0;
4224 /* Symbols and expressions. */
4226 /* Convert symbolic operand to proper sizes for matching, but don't
4227 prevent matching a set of insns that only supports sizes other
4228 than those matching the insn suffix. */
4230 i386_operand_type mask
, allowed
;
4231 const insn_template
*t
;
4233 operand_type_set (&mask
, 0);
4234 operand_type_set (&allowed
, 0);
4236 for (t
= current_templates
->start
;
4237 t
< current_templates
->end
;
4239 allowed
= operand_type_or (allowed
,
4240 t
->operand_types
[op
]);
4241 switch (guess_suffix
)
4243 case QWORD_MNEM_SUFFIX
:
4244 mask
.bitfield
.imm64
= 1;
4245 mask
.bitfield
.imm32s
= 1;
4247 case LONG_MNEM_SUFFIX
:
4248 mask
.bitfield
.imm32
= 1;
4250 case WORD_MNEM_SUFFIX
:
4251 mask
.bitfield
.imm16
= 1;
4253 case BYTE_MNEM_SUFFIX
:
4254 mask
.bitfield
.imm8
= 1;
4259 allowed
= operand_type_and (mask
, allowed
);
4260 if (!operand_type_all_zero (&allowed
))
4261 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4268 /* Try to use the smallest displacement type too. */
4270 optimize_disp (void)
4274 for (op
= i
.operands
; --op
>= 0;)
4275 if (operand_type_check (i
.types
[op
], disp
))
4277 if (i
.op
[op
].disps
->X_op
== O_constant
)
4279 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4281 if (i
.types
[op
].bitfield
.disp16
4282 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4284 /* If this operand is at most 16 bits, convert
4285 to a signed 16 bit number and don't use 64bit
4287 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4288 i
.types
[op
].bitfield
.disp64
= 0;
4290 if (i
.types
[op
].bitfield
.disp32
4291 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4293 /* If this operand is at most 32 bits, convert
4294 to a signed 32 bit number and don't use 64bit
4296 op_disp
&= (((offsetT
) 2 << 31) - 1);
4297 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4298 i
.types
[op
].bitfield
.disp64
= 0;
4300 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4302 i
.types
[op
].bitfield
.disp8
= 0;
4303 i
.types
[op
].bitfield
.disp16
= 0;
4304 i
.types
[op
].bitfield
.disp32
= 0;
4305 i
.types
[op
].bitfield
.disp32s
= 0;
4306 i
.types
[op
].bitfield
.disp64
= 0;
4310 else if (flag_code
== CODE_64BIT
)
4312 if (fits_in_signed_long (op_disp
))
4314 i
.types
[op
].bitfield
.disp64
= 0;
4315 i
.types
[op
].bitfield
.disp32s
= 1;
4317 if (i
.prefix
[ADDR_PREFIX
]
4318 && fits_in_unsigned_long (op_disp
))
4319 i
.types
[op
].bitfield
.disp32
= 1;
4321 if ((i
.types
[op
].bitfield
.disp32
4322 || i
.types
[op
].bitfield
.disp32s
4323 || i
.types
[op
].bitfield
.disp16
)
4324 && fits_in_signed_byte (op_disp
))
4325 i
.types
[op
].bitfield
.disp8
= 1;
4327 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4328 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4330 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4331 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4332 i
.types
[op
].bitfield
.disp8
= 0;
4333 i
.types
[op
].bitfield
.disp16
= 0;
4334 i
.types
[op
].bitfield
.disp32
= 0;
4335 i
.types
[op
].bitfield
.disp32s
= 0;
4336 i
.types
[op
].bitfield
.disp64
= 0;
4339 /* We only support 64bit displacement on constants. */
4340 i
.types
[op
].bitfield
.disp64
= 0;
4344 /* Check if operands are valid for the instruction. */
4347 check_VecOperands (const insn_template
*t
)
4351 /* Without VSIB byte, we can't have a vector register for index. */
4352 if (!t
->opcode_modifier
.vecsib
4354 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4355 || i
.index_reg
->reg_type
.bitfield
.regymm
4356 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4358 i
.error
= unsupported_vector_index_register
;
4362 /* Check if default mask is allowed. */
4363 if (t
->opcode_modifier
.nodefmask
4364 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4366 i
.error
= no_default_mask
;
4370 /* For VSIB byte, we need a vector register for index, and all vector
4371 registers must be distinct. */
4372 if (t
->opcode_modifier
.vecsib
)
4375 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4376 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4377 || (t
->opcode_modifier
.vecsib
== VecSIB256
4378 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4379 || (t
->opcode_modifier
.vecsib
== VecSIB512
4380 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4382 i
.error
= invalid_vsib_address
;
4386 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4387 if (i
.reg_operands
== 2 && !i
.mask
)
4389 gas_assert (i
.types
[0].bitfield
.regxmm
4390 || i
.types
[0].bitfield
.regymm
);
4391 gas_assert (i
.types
[2].bitfield
.regxmm
4392 || i
.types
[2].bitfield
.regymm
);
4393 if (operand_check
== check_none
)
4395 if (register_number (i
.op
[0].regs
)
4396 != register_number (i
.index_reg
)
4397 && register_number (i
.op
[2].regs
)
4398 != register_number (i
.index_reg
)
4399 && register_number (i
.op
[0].regs
)
4400 != register_number (i
.op
[2].regs
))
4402 if (operand_check
== check_error
)
4404 i
.error
= invalid_vector_register_set
;
4407 as_warn (_("mask, index, and destination registers should be distinct"));
4409 else if (i
.reg_operands
== 1 && i
.mask
)
4411 if ((i
.types
[1].bitfield
.regymm
4412 || i
.types
[1].bitfield
.regzmm
)
4413 && (register_number (i
.op
[1].regs
)
4414 == register_number (i
.index_reg
)))
4416 if (operand_check
== check_error
)
4418 i
.error
= invalid_vector_register_set
;
4421 if (operand_check
!= check_none
)
4422 as_warn (_("index and destination registers should be distinct"));
4427 /* Check if broadcast is supported by the instruction and is applied
4428 to the memory operand. */
4431 int broadcasted_opnd_size
;
4433 /* Check if specified broadcast is supported in this instruction,
4434 and it's applied to memory operand of DWORD or QWORD type,
4435 depending on VecESize. */
4436 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4437 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4438 || (t
->opcode_modifier
.vecesize
== 0
4439 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4440 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4441 || (t
->opcode_modifier
.vecesize
== 1
4442 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4443 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4446 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4447 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4448 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4449 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4450 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4451 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4452 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4453 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4454 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4458 if ((broadcasted_opnd_size
== 256
4459 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4460 || (broadcasted_opnd_size
== 512
4461 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4464 i
.error
= unsupported_broadcast
;
4468 /* If broadcast is supported in this instruction, we need to check if
4469 operand of one-element size isn't specified without broadcast. */
4470 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4472 /* Find memory operand. */
4473 for (op
= 0; op
< i
.operands
; op
++)
4474 if (operand_type_check (i
.types
[op
], anymem
))
4476 gas_assert (op
< i
.operands
);
4477 /* Check size of the memory operand. */
4478 if ((t
->opcode_modifier
.vecesize
== 0
4479 && i
.types
[op
].bitfield
.dword
)
4480 || (t
->opcode_modifier
.vecesize
== 1
4481 && i
.types
[op
].bitfield
.qword
))
4483 i
.error
= broadcast_needed
;
4488 /* Check if requested masking is supported. */
4490 && (!t
->opcode_modifier
.masking
4492 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4494 i
.error
= unsupported_masking
;
4498 /* Check if masking is applied to dest operand. */
4499 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4501 i
.error
= mask_not_on_destination
;
4508 if ((i
.rounding
->type
!= saeonly
4509 && !t
->opcode_modifier
.staticrounding
)
4510 || (i
.rounding
->type
== saeonly
4511 && (t
->opcode_modifier
.staticrounding
4512 || !t
->opcode_modifier
.sae
)))
4514 i
.error
= unsupported_rc_sae
;
4517 /* If the instruction has several immediate operands and one of
4518 them is rounding, the rounding operand should be the last
4519 immediate operand. */
4520 if (i
.imm_operands
> 1
4521 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4523 i
.error
= rc_sae_operand_not_last_imm
;
4528 /* Check vector Disp8 operand. */
4529 if (t
->opcode_modifier
.disp8memshift
)
4532 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4534 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4536 for (op
= 0; op
< i
.operands
; op
++)
4537 if (operand_type_check (i
.types
[op
], disp
)
4538 && i
.op
[op
].disps
->X_op
== O_constant
)
4540 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4541 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4542 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4545 i
.types
[op
].bitfield
.vec_disp8
= 1;
4548 /* Vector insn can only have Vec_Disp8/Disp32 in
4549 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4551 i
.types
[op
].bitfield
.disp8
= 0;
4552 if (flag_code
!= CODE_16BIT
)
4553 i
.types
[op
].bitfield
.disp16
= 0;
4556 else if (flag_code
!= CODE_16BIT
)
4558 /* One form of this instruction supports vector Disp8.
4559 Try vector Disp8 if we need to use Disp32. */
4560 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4562 i
.error
= try_vector_disp8
;
4574 /* Check if operands are valid for the instruction. Update VEX
4578 VEX_check_operands (const insn_template
*t
)
4580 /* VREX is only valid with EVEX prefix. */
4581 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4583 i
.error
= invalid_register_operand
;
4587 if (!t
->opcode_modifier
.vex
)
4590 /* Only check VEX_Imm4, which must be the first operand. */
4591 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4593 if (i
.op
[0].imms
->X_op
!= O_constant
4594 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4600 /* Turn off Imm8 so that update_imm won't complain. */
4601 i
.types
[0] = vec_imm4
;
4607 static const insn_template
*
4608 match_template (void)
4610 /* Points to template once we've found it. */
4611 const insn_template
*t
;
4612 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4613 i386_operand_type overlap4
;
4614 unsigned int found_reverse_match
;
4615 i386_opcode_modifier suffix_check
;
4616 i386_operand_type operand_types
[MAX_OPERANDS
];
4617 int addr_prefix_disp
;
4619 unsigned int found_cpu_match
;
4620 unsigned int check_register
;
4621 enum i386_error specific_error
= 0;
4623 #if MAX_OPERANDS != 5
4624 # error "MAX_OPERANDS must be 5."
4627 found_reverse_match
= 0;
4628 addr_prefix_disp
= -1;
4630 memset (&suffix_check
, 0, sizeof (suffix_check
));
4631 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4632 suffix_check
.no_bsuf
= 1;
4633 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4634 suffix_check
.no_wsuf
= 1;
4635 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4636 suffix_check
.no_ssuf
= 1;
4637 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4638 suffix_check
.no_lsuf
= 1;
4639 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4640 suffix_check
.no_qsuf
= 1;
4641 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4642 suffix_check
.no_ldsuf
= 1;
4644 /* Must have right number of operands. */
4645 i
.error
= number_of_operands_mismatch
;
4647 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4649 addr_prefix_disp
= -1;
4651 if (i
.operands
!= t
->operands
)
4654 /* Check processor support. */
4655 i
.error
= unsupported
;
4656 found_cpu_match
= (cpu_flags_match (t
)
4657 == CPU_FLAGS_PERFECT_MATCH
);
4658 if (!found_cpu_match
)
4661 /* Check old gcc support. */
4662 i
.error
= old_gcc_only
;
4663 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4666 /* Check AT&T mnemonic. */
4667 i
.error
= unsupported_with_intel_mnemonic
;
4668 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4671 /* Check AT&T/Intel syntax. */
4672 i
.error
= unsupported_syntax
;
4673 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4674 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4677 /* Check the suffix, except for some instructions in intel mode. */
4678 i
.error
= invalid_instruction_suffix
;
4679 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4680 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4681 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4682 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4683 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4684 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4685 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4688 if (!operand_size_match (t
))
4691 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4692 operand_types
[j
] = t
->operand_types
[j
];
4694 /* In general, don't allow 64-bit operands in 32-bit mode. */
4695 if (i
.suffix
== QWORD_MNEM_SUFFIX
4696 && flag_code
!= CODE_64BIT
4698 ? (!t
->opcode_modifier
.ignoresize
4699 && !intel_float_operand (t
->name
))
4700 : intel_float_operand (t
->name
) != 2)
4701 && ((!operand_types
[0].bitfield
.regmmx
4702 && !operand_types
[0].bitfield
.regxmm
4703 && !operand_types
[0].bitfield
.regymm
4704 && !operand_types
[0].bitfield
.regzmm
)
4705 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4706 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4707 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4708 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4709 && (t
->base_opcode
!= 0x0fc7
4710 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4713 /* In general, don't allow 32-bit operands on pre-386. */
4714 else if (i
.suffix
== LONG_MNEM_SUFFIX
4715 && !cpu_arch_flags
.bitfield
.cpui386
4717 ? (!t
->opcode_modifier
.ignoresize
4718 && !intel_float_operand (t
->name
))
4719 : intel_float_operand (t
->name
) != 2)
4720 && ((!operand_types
[0].bitfield
.regmmx
4721 && !operand_types
[0].bitfield
.regxmm
)
4722 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4723 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4726 /* Do not verify operands when there are none. */
4730 /* We've found a match; break out of loop. */
4734 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4735 into Disp32/Disp16/Disp32 operand. */
4736 if (i
.prefix
[ADDR_PREFIX
] != 0)
4738 /* There should be only one Disp operand. */
4742 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4744 if (operand_types
[j
].bitfield
.disp16
)
4746 addr_prefix_disp
= j
;
4747 operand_types
[j
].bitfield
.disp32
= 1;
4748 operand_types
[j
].bitfield
.disp16
= 0;
4754 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4756 if (operand_types
[j
].bitfield
.disp32
)
4758 addr_prefix_disp
= j
;
4759 operand_types
[j
].bitfield
.disp32
= 0;
4760 operand_types
[j
].bitfield
.disp16
= 1;
4766 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4768 if (operand_types
[j
].bitfield
.disp64
)
4770 addr_prefix_disp
= j
;
4771 operand_types
[j
].bitfield
.disp64
= 0;
4772 operand_types
[j
].bitfield
.disp32
= 1;
4780 /* We check register size if needed. */
4781 check_register
= t
->opcode_modifier
.checkregsize
;
4782 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4783 switch (t
->operands
)
4786 if (!operand_type_match (overlap0
, i
.types
[0]))
4790 /* xchg %eax, %eax is a special case. It is an aliase for nop
4791 only in 32bit mode and we can use opcode 0x90. In 64bit
4792 mode, we can't use 0x90 for xchg %eax, %eax since it should
4793 zero-extend %eax to %rax. */
4794 if (flag_code
== CODE_64BIT
4795 && t
->base_opcode
== 0x90
4796 && operand_type_equal (&i
.types
[0], &acc32
)
4797 && operand_type_equal (&i
.types
[1], &acc32
))
4801 /* If we swap operand in encoding, we either match
4802 the next one or reverse direction of operands. */
4803 if (t
->opcode_modifier
.s
)
4805 else if (t
->opcode_modifier
.d
)
4810 /* If we swap operand in encoding, we match the next one. */
4811 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4815 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4816 if (!operand_type_match (overlap0
, i
.types
[0])
4817 || !operand_type_match (overlap1
, i
.types
[1])
4819 && !operand_type_register_match (overlap0
, i
.types
[0],
4821 overlap1
, i
.types
[1],
4824 /* Check if other direction is valid ... */
4825 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4829 /* Try reversing direction of operands. */
4830 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4831 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4832 if (!operand_type_match (overlap0
, i
.types
[0])
4833 || !operand_type_match (overlap1
, i
.types
[1])
4835 && !operand_type_register_match (overlap0
,
4842 /* Does not match either direction. */
4845 /* found_reverse_match holds which of D or FloatDR
4847 if (t
->opcode_modifier
.d
)
4848 found_reverse_match
= Opcode_D
;
4849 else if (t
->opcode_modifier
.floatd
)
4850 found_reverse_match
= Opcode_FloatD
;
4852 found_reverse_match
= 0;
4853 if (t
->opcode_modifier
.floatr
)
4854 found_reverse_match
|= Opcode_FloatR
;
4858 /* Found a forward 2 operand match here. */
4859 switch (t
->operands
)
4862 overlap4
= operand_type_and (i
.types
[4],
4865 overlap3
= operand_type_and (i
.types
[3],
4868 overlap2
= operand_type_and (i
.types
[2],
4873 switch (t
->operands
)
4876 if (!operand_type_match (overlap4
, i
.types
[4])
4877 || !operand_type_register_match (overlap3
,
4885 if (!operand_type_match (overlap3
, i
.types
[3])
4887 && !operand_type_register_match (overlap2
,
4895 /* Here we make use of the fact that there are no
4896 reverse match 3 operand instructions, and all 3
4897 operand instructions only need to be checked for
4898 register consistency between operands 2 and 3. */
4899 if (!operand_type_match (overlap2
, i
.types
[2])
4901 && !operand_type_register_match (overlap1
,
4911 /* Found either forward/reverse 2, 3 or 4 operand match here:
4912 slip through to break. */
4914 if (!found_cpu_match
)
4916 found_reverse_match
= 0;
4920 /* Check if vector and VEX operands are valid. */
4921 if (check_VecOperands (t
) || VEX_check_operands (t
))
4923 specific_error
= i
.error
;
4927 /* We've found a match; break out of loop. */
4931 if (t
== current_templates
->end
)
4933 /* We found no match. */
4934 const char *err_msg
;
4935 switch (specific_error
? specific_error
: i
.error
)
4939 case operand_size_mismatch
:
4940 err_msg
= _("operand size mismatch");
4942 case operand_type_mismatch
:
4943 err_msg
= _("operand type mismatch");
4945 case register_type_mismatch
:
4946 err_msg
= _("register type mismatch");
4948 case number_of_operands_mismatch
:
4949 err_msg
= _("number of operands mismatch");
4951 case invalid_instruction_suffix
:
4952 err_msg
= _("invalid instruction suffix");
4955 err_msg
= _("constant doesn't fit in 4 bits");
4958 err_msg
= _("only supported with old gcc");
4960 case unsupported_with_intel_mnemonic
:
4961 err_msg
= _("unsupported with Intel mnemonic");
4963 case unsupported_syntax
:
4964 err_msg
= _("unsupported syntax");
4967 as_bad (_("unsupported instruction `%s'"),
4968 current_templates
->start
->name
);
4970 case invalid_vsib_address
:
4971 err_msg
= _("invalid VSIB address");
4973 case invalid_vector_register_set
:
4974 err_msg
= _("mask, index, and destination registers must be distinct");
4976 case unsupported_vector_index_register
:
4977 err_msg
= _("unsupported vector index register");
4979 case unsupported_broadcast
:
4980 err_msg
= _("unsupported broadcast");
4982 case broadcast_not_on_src_operand
:
4983 err_msg
= _("broadcast not on source memory operand");
4985 case broadcast_needed
:
4986 err_msg
= _("broadcast is needed for operand of such type");
4988 case unsupported_masking
:
4989 err_msg
= _("unsupported masking");
4991 case mask_not_on_destination
:
4992 err_msg
= _("mask not on destination operand");
4994 case no_default_mask
:
4995 err_msg
= _("default mask isn't allowed");
4997 case unsupported_rc_sae
:
4998 err_msg
= _("unsupported static rounding/sae");
5000 case rc_sae_operand_not_last_imm
:
5002 err_msg
= _("RC/SAE operand must precede immediate operands");
5004 err_msg
= _("RC/SAE operand must follow immediate operands");
5006 case invalid_register_operand
:
5007 err_msg
= _("invalid register operand");
5010 as_bad (_("%s for `%s'"), err_msg
,
5011 current_templates
->start
->name
);
5015 if (!quiet_warnings
)
5018 && (i
.types
[0].bitfield
.jumpabsolute
5019 != operand_types
[0].bitfield
.jumpabsolute
))
5021 as_warn (_("indirect %s without `*'"), t
->name
);
5024 if (t
->opcode_modifier
.isprefix
5025 && t
->opcode_modifier
.ignoresize
)
5027 /* Warn them that a data or address size prefix doesn't
5028 affect assembly of the next line of code. */
5029 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5033 /* Copy the template we found. */
5036 if (addr_prefix_disp
!= -1)
5037 i
.tm
.operand_types
[addr_prefix_disp
]
5038 = operand_types
[addr_prefix_disp
];
5040 if (found_reverse_match
)
5042 /* If we found a reverse match we must alter the opcode
5043 direction bit. found_reverse_match holds bits to change
5044 (different for int & float insns). */
5046 i
.tm
.base_opcode
^= found_reverse_match
;
5048 i
.tm
.operand_types
[0] = operand_types
[1];
5049 i
.tm
.operand_types
[1] = operand_types
[0];
5058 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5059 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5061 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5063 as_bad (_("`%s' operand %d must use `%ses' segment"),
5069 /* There's only ever one segment override allowed per instruction.
5070 This instruction possibly has a legal segment override on the
5071 second operand, so copy the segment to where non-string
5072 instructions store it, allowing common code. */
5073 i
.seg
[0] = i
.seg
[1];
5075 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5077 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5079 as_bad (_("`%s' operand %d must use `%ses' segment"),
5090 process_suffix (void)
5092 /* If matched instruction specifies an explicit instruction mnemonic
5094 if (i
.tm
.opcode_modifier
.size16
)
5095 i
.suffix
= WORD_MNEM_SUFFIX
;
5096 else if (i
.tm
.opcode_modifier
.size32
)
5097 i
.suffix
= LONG_MNEM_SUFFIX
;
5098 else if (i
.tm
.opcode_modifier
.size64
)
5099 i
.suffix
= QWORD_MNEM_SUFFIX
;
5100 else if (i
.reg_operands
)
5102 /* If there's no instruction mnemonic suffix we try to invent one
5103 based on register operands. */
5106 /* We take i.suffix from the last register operand specified,
5107 Destination register type is more significant than source
5108 register type. crc32 in SSE4.2 prefers source register
5110 if (i
.tm
.base_opcode
== 0xf20f38f1)
5112 if (i
.types
[0].bitfield
.reg16
)
5113 i
.suffix
= WORD_MNEM_SUFFIX
;
5114 else if (i
.types
[0].bitfield
.reg32
)
5115 i
.suffix
= LONG_MNEM_SUFFIX
;
5116 else if (i
.types
[0].bitfield
.reg64
)
5117 i
.suffix
= QWORD_MNEM_SUFFIX
;
5119 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5121 if (i
.types
[0].bitfield
.reg8
)
5122 i
.suffix
= BYTE_MNEM_SUFFIX
;
5129 if (i
.tm
.base_opcode
== 0xf20f38f1
5130 || i
.tm
.base_opcode
== 0xf20f38f0)
5132 /* We have to know the operand size for crc32. */
5133 as_bad (_("ambiguous memory operand size for `%s`"),
5138 for (op
= i
.operands
; --op
>= 0;)
5139 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5141 if (i
.types
[op
].bitfield
.reg8
)
5143 i
.suffix
= BYTE_MNEM_SUFFIX
;
5146 else if (i
.types
[op
].bitfield
.reg16
)
5148 i
.suffix
= WORD_MNEM_SUFFIX
;
5151 else if (i
.types
[op
].bitfield
.reg32
)
5153 i
.suffix
= LONG_MNEM_SUFFIX
;
5156 else if (i
.types
[op
].bitfield
.reg64
)
5158 i
.suffix
= QWORD_MNEM_SUFFIX
;
5164 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5167 && i
.tm
.opcode_modifier
.ignoresize
5168 && i
.tm
.opcode_modifier
.no_bsuf
)
5170 else if (!check_byte_reg ())
5173 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5176 && i
.tm
.opcode_modifier
.ignoresize
5177 && i
.tm
.opcode_modifier
.no_lsuf
)
5179 else if (!check_long_reg ())
5182 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5185 && i
.tm
.opcode_modifier
.ignoresize
5186 && i
.tm
.opcode_modifier
.no_qsuf
)
5188 else if (!check_qword_reg ())
5191 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5194 && i
.tm
.opcode_modifier
.ignoresize
5195 && i
.tm
.opcode_modifier
.no_wsuf
)
5197 else if (!check_word_reg ())
5200 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5201 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5202 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5204 /* Skip if the instruction has x/y/z suffix. match_template
5205 should check if it is a valid suffix. */
5207 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5208 /* Do nothing if the instruction is going to ignore the prefix. */
5213 else if (i
.tm
.opcode_modifier
.defaultsize
5215 /* exclude fldenv/frstor/fsave/fstenv */
5216 && i
.tm
.opcode_modifier
.no_ssuf
)
5218 i
.suffix
= stackop_size
;
5220 else if (intel_syntax
5222 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5223 || i
.tm
.opcode_modifier
.jumpbyte
5224 || i
.tm
.opcode_modifier
.jumpintersegment
5225 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5226 && i
.tm
.extension_opcode
<= 3)))
5231 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5233 i
.suffix
= QWORD_MNEM_SUFFIX
;
5237 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5238 i
.suffix
= LONG_MNEM_SUFFIX
;
5241 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5242 i
.suffix
= WORD_MNEM_SUFFIX
;
5251 if (i
.tm
.opcode_modifier
.w
)
5253 as_bad (_("no instruction mnemonic suffix given and "
5254 "no register operands; can't size instruction"));
5260 unsigned int suffixes
;
5262 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5263 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5265 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5267 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5269 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5271 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5274 /* There are more than suffix matches. */
5275 if (i
.tm
.opcode_modifier
.w
5276 || ((suffixes
& (suffixes
- 1))
5277 && !i
.tm
.opcode_modifier
.defaultsize
5278 && !i
.tm
.opcode_modifier
.ignoresize
))
5280 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5286 /* Change the opcode based on the operand size given by i.suffix;
5287 We don't need to change things for byte insns. */
5290 && i
.suffix
!= BYTE_MNEM_SUFFIX
5291 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5292 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5293 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5295 /* It's not a byte, select word/dword operation. */
5296 if (i
.tm
.opcode_modifier
.w
)
5298 if (i
.tm
.opcode_modifier
.shortform
)
5299 i
.tm
.base_opcode
|= 8;
5301 i
.tm
.base_opcode
|= 1;
5304 /* Now select between word & dword operations via the operand
5305 size prefix, except for instructions that will ignore this
5307 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5309 /* The address size override prefix changes the size of the
5311 if ((flag_code
== CODE_32BIT
5312 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5313 || (flag_code
!= CODE_32BIT
5314 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5315 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5318 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5319 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5320 && !i
.tm
.opcode_modifier
.ignoresize
5321 && !i
.tm
.opcode_modifier
.floatmf
5322 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5323 || (flag_code
== CODE_64BIT
5324 && i
.tm
.opcode_modifier
.jumpbyte
)))
5326 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5328 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5329 prefix
= ADDR_PREFIX_OPCODE
;
5331 if (!add_prefix (prefix
))
5335 /* Set mode64 for an operand. */
5336 if (i
.suffix
== QWORD_MNEM_SUFFIX
5337 && flag_code
== CODE_64BIT
5338 && !i
.tm
.opcode_modifier
.norex64
)
5340 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5341 need rex64. cmpxchg8b is also a special case. */
5342 if (! (i
.operands
== 2
5343 && i
.tm
.base_opcode
== 0x90
5344 && i
.tm
.extension_opcode
== None
5345 && operand_type_equal (&i
.types
[0], &acc64
)
5346 && operand_type_equal (&i
.types
[1], &acc64
))
5347 && ! (i
.operands
== 1
5348 && i
.tm
.base_opcode
== 0xfc7
5349 && i
.tm
.extension_opcode
== 1
5350 && !operand_type_check (i
.types
[0], reg
)
5351 && operand_type_check (i
.types
[0], anymem
)))
5355 /* Size floating point instruction. */
5356 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5357 if (i
.tm
.opcode_modifier
.floatmf
)
5358 i
.tm
.base_opcode
^= 4;
5365 check_byte_reg (void)
5369 for (op
= i
.operands
; --op
>= 0;)
5371 /* If this is an eight bit register, it's OK. If it's the 16 or
5372 32 bit version of an eight bit register, we will just use the
5373 low portion, and that's OK too. */
5374 if (i
.types
[op
].bitfield
.reg8
)
5377 /* I/O port address operands are OK too. */
5378 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5381 /* crc32 doesn't generate this warning. */
5382 if (i
.tm
.base_opcode
== 0xf20f38f0)
5385 if ((i
.types
[op
].bitfield
.reg16
5386 || i
.types
[op
].bitfield
.reg32
5387 || i
.types
[op
].bitfield
.reg64
)
5388 && i
.op
[op
].regs
->reg_num
< 4
5389 /* Prohibit these changes in 64bit mode, since the lowering
5390 would be more complicated. */
5391 && flag_code
!= CODE_64BIT
)
5393 #if REGISTER_WARNINGS
5394 if (!quiet_warnings
)
5395 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5397 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5398 ? REGNAM_AL
- REGNAM_AX
5399 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5401 i
.op
[op
].regs
->reg_name
,
5406 /* Any other register is bad. */
5407 if (i
.types
[op
].bitfield
.reg16
5408 || i
.types
[op
].bitfield
.reg32
5409 || i
.types
[op
].bitfield
.reg64
5410 || i
.types
[op
].bitfield
.regmmx
5411 || i
.types
[op
].bitfield
.regxmm
5412 || i
.types
[op
].bitfield
.regymm
5413 || i
.types
[op
].bitfield
.regzmm
5414 || i
.types
[op
].bitfield
.sreg2
5415 || i
.types
[op
].bitfield
.sreg3
5416 || i
.types
[op
].bitfield
.control
5417 || i
.types
[op
].bitfield
.debug
5418 || i
.types
[op
].bitfield
.test
5419 || i
.types
[op
].bitfield
.floatreg
5420 || i
.types
[op
].bitfield
.floatacc
)
5422 as_bad (_("`%s%s' not allowed with `%s%c'"),
5424 i
.op
[op
].regs
->reg_name
,
5434 check_long_reg (void)
5438 for (op
= i
.operands
; --op
>= 0;)
5439 /* Reject eight bit registers, except where the template requires
5440 them. (eg. movzb) */
5441 if (i
.types
[op
].bitfield
.reg8
5442 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5443 || i
.tm
.operand_types
[op
].bitfield
.reg32
5444 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5446 as_bad (_("`%s%s' not allowed with `%s%c'"),
5448 i
.op
[op
].regs
->reg_name
,
5453 /* Warn if the e prefix on a general reg is missing. */
5454 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5455 && i
.types
[op
].bitfield
.reg16
5456 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5457 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5459 /* Prohibit these changes in the 64bit mode, since the
5460 lowering is more complicated. */
5461 if (flag_code
== CODE_64BIT
)
5463 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5464 register_prefix
, i
.op
[op
].regs
->reg_name
,
5468 #if REGISTER_WARNINGS
5469 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5471 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5472 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5475 /* Warn if the r prefix on a general reg is present. */
5476 else if (i
.types
[op
].bitfield
.reg64
5477 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5478 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5481 && i
.tm
.opcode_modifier
.toqword
5482 && !i
.types
[0].bitfield
.regxmm
)
5484 /* Convert to QWORD. We want REX byte. */
5485 i
.suffix
= QWORD_MNEM_SUFFIX
;
5489 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5490 register_prefix
, i
.op
[op
].regs
->reg_name
,
5499 check_qword_reg (void)
5503 for (op
= i
.operands
; --op
>= 0; )
5504 /* Reject eight bit registers, except where the template requires
5505 them. (eg. movzb) */
5506 if (i
.types
[op
].bitfield
.reg8
5507 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5508 || i
.tm
.operand_types
[op
].bitfield
.reg32
5509 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5511 as_bad (_("`%s%s' not allowed with `%s%c'"),
5513 i
.op
[op
].regs
->reg_name
,
5518 /* Warn if the r prefix on a general reg is missing. */
5519 else if ((i
.types
[op
].bitfield
.reg16
5520 || i
.types
[op
].bitfield
.reg32
)
5521 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5522 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5524 /* Prohibit these changes in the 64bit mode, since the
5525 lowering is more complicated. */
5527 && i
.tm
.opcode_modifier
.todword
5528 && !i
.types
[0].bitfield
.regxmm
)
5530 /* Convert to DWORD. We don't want REX byte. */
5531 i
.suffix
= LONG_MNEM_SUFFIX
;
5535 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5536 register_prefix
, i
.op
[op
].regs
->reg_name
,
5545 check_word_reg (void)
5548 for (op
= i
.operands
; --op
>= 0;)
5549 /* Reject eight bit registers, except where the template requires
5550 them. (eg. movzb) */
5551 if (i
.types
[op
].bitfield
.reg8
5552 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5553 || i
.tm
.operand_types
[op
].bitfield
.reg32
5554 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5556 as_bad (_("`%s%s' not allowed with `%s%c'"),
5558 i
.op
[op
].regs
->reg_name
,
5563 /* Warn if the e or r prefix on a general reg is present. */
5564 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5565 && (i
.types
[op
].bitfield
.reg32
5566 || i
.types
[op
].bitfield
.reg64
)
5567 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5568 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5570 /* Prohibit these changes in the 64bit mode, since the
5571 lowering is more complicated. */
5572 if (flag_code
== CODE_64BIT
)
5574 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5575 register_prefix
, i
.op
[op
].regs
->reg_name
,
5579 #if REGISTER_WARNINGS
5580 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5582 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5583 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5590 update_imm (unsigned int j
)
5592 i386_operand_type overlap
= i
.types
[j
];
5593 if ((overlap
.bitfield
.imm8
5594 || overlap
.bitfield
.imm8s
5595 || overlap
.bitfield
.imm16
5596 || overlap
.bitfield
.imm32
5597 || overlap
.bitfield
.imm32s
5598 || overlap
.bitfield
.imm64
)
5599 && !operand_type_equal (&overlap
, &imm8
)
5600 && !operand_type_equal (&overlap
, &imm8s
)
5601 && !operand_type_equal (&overlap
, &imm16
)
5602 && !operand_type_equal (&overlap
, &imm32
)
5603 && !operand_type_equal (&overlap
, &imm32s
)
5604 && !operand_type_equal (&overlap
, &imm64
))
5608 i386_operand_type temp
;
5610 operand_type_set (&temp
, 0);
5611 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5613 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5614 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5616 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5617 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5618 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5620 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5621 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5624 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5627 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5628 || operand_type_equal (&overlap
, &imm16_32
)
5629 || operand_type_equal (&overlap
, &imm16_32s
))
5631 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5636 if (!operand_type_equal (&overlap
, &imm8
)
5637 && !operand_type_equal (&overlap
, &imm8s
)
5638 && !operand_type_equal (&overlap
, &imm16
)
5639 && !operand_type_equal (&overlap
, &imm32
)
5640 && !operand_type_equal (&overlap
, &imm32s
)
5641 && !operand_type_equal (&overlap
, &imm64
))
5643 as_bad (_("no instruction mnemonic suffix given; "
5644 "can't determine immediate size"));
5648 i
.types
[j
] = overlap
;
5658 /* Update the first 2 immediate operands. */
5659 n
= i
.operands
> 2 ? 2 : i
.operands
;
5662 for (j
= 0; j
< n
; j
++)
5663 if (update_imm (j
) == 0)
5666 /* The 3rd operand can't be immediate operand. */
5667 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5674 bad_implicit_operand (int xmm
)
5676 const char *ireg
= xmm
? "xmm0" : "ymm0";
5679 as_bad (_("the last operand of `%s' must be `%s%s'"),
5680 i
.tm
.name
, register_prefix
, ireg
);
5682 as_bad (_("the first operand of `%s' must be `%s%s'"),
5683 i
.tm
.name
, register_prefix
, ireg
);
5688 process_operands (void)
5690 /* Default segment register this instruction will use for memory
5691 accesses. 0 means unknown. This is only for optimizing out
5692 unnecessary segment overrides. */
5693 const seg_entry
*default_seg
= 0;
5695 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5697 unsigned int dupl
= i
.operands
;
5698 unsigned int dest
= dupl
- 1;
5701 /* The destination must be an xmm register. */
5702 gas_assert (i
.reg_operands
5703 && MAX_OPERANDS
> dupl
5704 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5706 if (i
.tm
.opcode_modifier
.firstxmm0
)
5708 /* The first operand is implicit and must be xmm0. */
5709 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5710 if (register_number (i
.op
[0].regs
) != 0)
5711 return bad_implicit_operand (1);
5713 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5715 /* Keep xmm0 for instructions with VEX prefix and 3
5721 /* We remove the first xmm0 and keep the number of
5722 operands unchanged, which in fact duplicates the
5724 for (j
= 1; j
< i
.operands
; j
++)
5726 i
.op
[j
- 1] = i
.op
[j
];
5727 i
.types
[j
- 1] = i
.types
[j
];
5728 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5732 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5734 gas_assert ((MAX_OPERANDS
- 1) > dupl
5735 && (i
.tm
.opcode_modifier
.vexsources
5738 /* Add the implicit xmm0 for instructions with VEX prefix
5740 for (j
= i
.operands
; j
> 0; j
--)
5742 i
.op
[j
] = i
.op
[j
- 1];
5743 i
.types
[j
] = i
.types
[j
- 1];
5744 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5747 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5748 i
.types
[0] = regxmm
;
5749 i
.tm
.operand_types
[0] = regxmm
;
5752 i
.reg_operands
+= 2;
5757 i
.op
[dupl
] = i
.op
[dest
];
5758 i
.types
[dupl
] = i
.types
[dest
];
5759 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5768 i
.op
[dupl
] = i
.op
[dest
];
5769 i
.types
[dupl
] = i
.types
[dest
];
5770 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5773 if (i
.tm
.opcode_modifier
.immext
)
5776 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5780 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5781 gas_assert (i
.reg_operands
5782 && (operand_type_equal (&i
.types
[0], ®xmm
)
5783 || operand_type_equal (&i
.types
[0], ®ymm
)
5784 || operand_type_equal (&i
.types
[0], ®zmm
)));
5785 if (register_number (i
.op
[0].regs
) != 0)
5786 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5788 for (j
= 1; j
< i
.operands
; j
++)
5790 i
.op
[j
- 1] = i
.op
[j
];
5791 i
.types
[j
- 1] = i
.types
[j
];
5793 /* We need to adjust fields in i.tm since they are used by
5794 build_modrm_byte. */
5795 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5802 else if (i
.tm
.opcode_modifier
.regkludge
)
5804 /* The imul $imm, %reg instruction is converted into
5805 imul $imm, %reg, %reg, and the clr %reg instruction
5806 is converted into xor %reg, %reg. */
5808 unsigned int first_reg_op
;
5810 if (operand_type_check (i
.types
[0], reg
))
5814 /* Pretend we saw the extra register operand. */
5815 gas_assert (i
.reg_operands
== 1
5816 && i
.op
[first_reg_op
+ 1].regs
== 0);
5817 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5818 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5823 if (i
.tm
.opcode_modifier
.shortform
)
5825 if (i
.types
[0].bitfield
.sreg2
5826 || i
.types
[0].bitfield
.sreg3
)
5828 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5829 && i
.op
[0].regs
->reg_num
== 1)
5831 as_bad (_("you can't `pop %scs'"), register_prefix
);
5834 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5835 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5840 /* The register or float register operand is in operand
5844 if (i
.types
[0].bitfield
.floatreg
5845 || operand_type_check (i
.types
[0], reg
))
5849 /* Register goes in low 3 bits of opcode. */
5850 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5851 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5853 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5855 /* Warn about some common errors, but press on regardless.
5856 The first case can be generated by gcc (<= 2.8.1). */
5857 if (i
.operands
== 2)
5859 /* Reversed arguments on faddp, fsubp, etc. */
5860 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5861 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5862 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5866 /* Extraneous `l' suffix on fp insn. */
5867 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5868 register_prefix
, i
.op
[0].regs
->reg_name
);
5873 else if (i
.tm
.opcode_modifier
.modrm
)
5875 /* The opcode is completed (modulo i.tm.extension_opcode which
5876 must be put into the modrm byte). Now, we make the modrm and
5877 index base bytes based on all the info we've collected. */
5879 default_seg
= build_modrm_byte ();
5881 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5885 else if (i
.tm
.opcode_modifier
.isstring
)
5887 /* For the string instructions that allow a segment override
5888 on one of their operands, the default segment is ds. */
5892 if (i
.tm
.base_opcode
== 0x8d /* lea */
5895 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5897 /* If a segment was explicitly specified, and the specified segment
5898 is not the default, use an opcode prefix to select it. If we
5899 never figured out what the default segment is, then default_seg
5900 will be zero at this point, and the specified segment prefix will
5902 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5904 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5910 static const seg_entry
*
5911 build_modrm_byte (void)
5913 const seg_entry
*default_seg
= 0;
5914 unsigned int source
, dest
;
5917 /* The first operand of instructions with VEX prefix and 3 sources
5918 must be VEX_Imm4. */
5919 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5922 unsigned int nds
, reg_slot
;
5925 if (i
.tm
.opcode_modifier
.veximmext
5926 && i
.tm
.opcode_modifier
.immext
)
5928 dest
= i
.operands
- 2;
5929 gas_assert (dest
== 3);
5932 dest
= i
.operands
- 1;
5935 /* There are 2 kinds of instructions:
5936 1. 5 operands: 4 register operands or 3 register operands
5937 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5938 VexW0 or VexW1. The destination must be either XMM, YMM or
5940 2. 4 operands: 4 register operands or 3 register operands
5941 plus 1 memory operand, VexXDS, and VexImmExt */
5942 gas_assert ((i
.reg_operands
== 4
5943 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5944 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5945 && (i
.tm
.opcode_modifier
.veximmext
5946 || (i
.imm_operands
== 1
5947 && i
.types
[0].bitfield
.vec_imm4
5948 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5949 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5950 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5951 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5952 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5954 if (i
.imm_operands
== 0)
5956 /* When there is no immediate operand, generate an 8bit
5957 immediate operand to encode the first operand. */
5958 exp
= &im_expressions
[i
.imm_operands
++];
5959 i
.op
[i
.operands
].imms
= exp
;
5960 i
.types
[i
.operands
] = imm8
;
5962 /* If VexW1 is set, the first operand is the source and
5963 the second operand is encoded in the immediate operand. */
5964 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5975 /* FMA swaps REG and NDS. */
5976 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5984 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5986 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5988 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5990 exp
->X_op
= O_constant
;
5991 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5992 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5996 unsigned int imm_slot
;
5998 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6000 /* If VexW0 is set, the third operand is the source and
6001 the second operand is encoded in the immediate
6008 /* VexW1 is set, the second operand is the source and
6009 the third operand is encoded in the immediate
6015 if (i
.tm
.opcode_modifier
.immext
)
6017 /* When ImmExt is set, the immdiate byte is the last
6019 imm_slot
= i
.operands
- 1;
6027 /* Turn on Imm8 so that output_imm will generate it. */
6028 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6031 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6033 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6035 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6037 i
.op
[imm_slot
].imms
->X_add_number
6038 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6039 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6042 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6043 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6045 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6047 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6052 /* i.reg_operands MUST be the number of real register operands;
6053 implicit registers do not count. If there are 3 register
6054 operands, it must be a instruction with VexNDS. For a
6055 instruction with VexNDD, the destination register is encoded
6056 in VEX prefix. If there are 4 register operands, it must be
6057 a instruction with VEX prefix and 3 sources. */
6058 if (i
.mem_operands
== 0
6059 && ((i
.reg_operands
== 2
6060 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6061 || (i
.reg_operands
== 3
6062 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6063 || (i
.reg_operands
== 4 && vex_3_sources
)))
6071 /* When there are 3 operands, one of them may be immediate,
6072 which may be the first or the last operand. Otherwise,
6073 the first operand must be shift count register (cl) or it
6074 is an instruction with VexNDS. */
6075 gas_assert (i
.imm_operands
== 1
6076 || (i
.imm_operands
== 0
6077 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6078 || i
.types
[0].bitfield
.shiftcount
)));
6079 if (operand_type_check (i
.types
[0], imm
)
6080 || i
.types
[0].bitfield
.shiftcount
)
6086 /* When there are 4 operands, the first two must be 8bit
6087 immediate operands. The source operand will be the 3rd
6090 For instructions with VexNDS, if the first operand
6091 an imm8, the source operand is the 2nd one. If the last
6092 operand is imm8, the source operand is the first one. */
6093 gas_assert ((i
.imm_operands
== 2
6094 && i
.types
[0].bitfield
.imm8
6095 && i
.types
[1].bitfield
.imm8
)
6096 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6097 && i
.imm_operands
== 1
6098 && (i
.types
[0].bitfield
.imm8
6099 || i
.types
[i
.operands
- 1].bitfield
.imm8
6101 if (i
.imm_operands
== 2)
6105 if (i
.types
[0].bitfield
.imm8
)
6112 if (i
.tm
.opcode_modifier
.evex
)
6114 /* For EVEX instructions, when there are 5 operands, the
6115 first one must be immediate operand. If the second one
6116 is immediate operand, the source operand is the 3th
6117 one. If the last one is immediate operand, the source
6118 operand is the 2nd one. */
6119 gas_assert (i
.imm_operands
== 2
6120 && i
.tm
.opcode_modifier
.sae
6121 && operand_type_check (i
.types
[0], imm
));
6122 if (operand_type_check (i
.types
[1], imm
))
6124 else if (operand_type_check (i
.types
[4], imm
))
6138 /* RC/SAE operand could be between DEST and SRC. That happens
6139 when one operand is GPR and the other one is XMM/YMM/ZMM
6141 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6144 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6146 /* For instructions with VexNDS, the register-only source
6147 operand must be 32/64bit integer, XMM, YMM or ZMM
6148 register. It is encoded in VEX prefix. We need to
6149 clear RegMem bit before calling operand_type_equal. */
6151 i386_operand_type op
;
6154 /* Check register-only source operand when two source
6155 operands are swapped. */
6156 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6157 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6165 op
= i
.tm
.operand_types
[vvvv
];
6166 op
.bitfield
.regmem
= 0;
6167 if ((dest
+ 1) >= i
.operands
6168 || (op
.bitfield
.reg32
!= 1
6169 && !op
.bitfield
.reg64
!= 1
6170 && !operand_type_equal (&op
, ®xmm
)
6171 && !operand_type_equal (&op
, ®ymm
)
6172 && !operand_type_equal (&op
, ®zmm
)
6173 && !operand_type_equal (&op
, ®mask
)))
6175 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6181 /* One of the register operands will be encoded in the i.tm.reg
6182 field, the other in the combined i.tm.mode and i.tm.regmem
6183 fields. If no form of this instruction supports a memory
6184 destination operand, then we assume the source operand may
6185 sometimes be a memory operand and so we need to store the
6186 destination in the i.rm.reg field. */
6187 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6188 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6190 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6191 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6192 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6194 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6196 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6198 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6203 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6204 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6205 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6207 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6209 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6211 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6214 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6216 if (!i
.types
[0].bitfield
.control
6217 && !i
.types
[1].bitfield
.control
)
6219 i
.rex
&= ~(REX_R
| REX_B
);
6220 add_prefix (LOCK_PREFIX_OPCODE
);
6224 { /* If it's not 2 reg operands... */
6229 unsigned int fake_zero_displacement
= 0;
6232 for (op
= 0; op
< i
.operands
; op
++)
6233 if (operand_type_check (i
.types
[op
], anymem
))
6235 gas_assert (op
< i
.operands
);
6237 if (i
.tm
.opcode_modifier
.vecsib
)
6239 if (i
.index_reg
->reg_num
== RegEiz
6240 || i
.index_reg
->reg_num
== RegRiz
)
6243 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6246 i
.sib
.base
= NO_BASE_REGISTER
;
6247 i
.sib
.scale
= i
.log2_scale_factor
;
6248 /* No Vec_Disp8 if there is no base. */
6249 i
.types
[op
].bitfield
.vec_disp8
= 0;
6250 i
.types
[op
].bitfield
.disp8
= 0;
6251 i
.types
[op
].bitfield
.disp16
= 0;
6252 i
.types
[op
].bitfield
.disp64
= 0;
6253 if (flag_code
!= CODE_64BIT
)
6255 /* Must be 32 bit */
6256 i
.types
[op
].bitfield
.disp32
= 1;
6257 i
.types
[op
].bitfield
.disp32s
= 0;
6261 i
.types
[op
].bitfield
.disp32
= 0;
6262 i
.types
[op
].bitfield
.disp32s
= 1;
6265 i
.sib
.index
= i
.index_reg
->reg_num
;
6266 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6268 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6274 if (i
.base_reg
== 0)
6277 if (!i
.disp_operands
)
6279 fake_zero_displacement
= 1;
6280 /* Instructions with VSIB byte need 32bit displacement
6281 if there is no base register. */
6282 if (i
.tm
.opcode_modifier
.vecsib
)
6283 i
.types
[op
].bitfield
.disp32
= 1;
6285 if (i
.index_reg
== 0)
6287 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6288 /* Operand is just <disp> */
6289 if (flag_code
== CODE_64BIT
)
6291 /* 64bit mode overwrites the 32bit absolute
6292 addressing by RIP relative addressing and
6293 absolute addressing is encoded by one of the
6294 redundant SIB forms. */
6295 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6296 i
.sib
.base
= NO_BASE_REGISTER
;
6297 i
.sib
.index
= NO_INDEX_REGISTER
;
6298 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6299 ? disp32s
: disp32
);
6301 else if ((flag_code
== CODE_16BIT
)
6302 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6304 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6305 i
.types
[op
] = disp16
;
6309 i
.rm
.regmem
= NO_BASE_REGISTER
;
6310 i
.types
[op
] = disp32
;
6313 else if (!i
.tm
.opcode_modifier
.vecsib
)
6315 /* !i.base_reg && i.index_reg */
6316 if (i
.index_reg
->reg_num
== RegEiz
6317 || i
.index_reg
->reg_num
== RegRiz
)
6318 i
.sib
.index
= NO_INDEX_REGISTER
;
6320 i
.sib
.index
= i
.index_reg
->reg_num
;
6321 i
.sib
.base
= NO_BASE_REGISTER
;
6322 i
.sib
.scale
= i
.log2_scale_factor
;
6323 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6324 /* No Vec_Disp8 if there is no base. */
6325 i
.types
[op
].bitfield
.vec_disp8
= 0;
6326 i
.types
[op
].bitfield
.disp8
= 0;
6327 i
.types
[op
].bitfield
.disp16
= 0;
6328 i
.types
[op
].bitfield
.disp64
= 0;
6329 if (flag_code
!= CODE_64BIT
)
6331 /* Must be 32 bit */
6332 i
.types
[op
].bitfield
.disp32
= 1;
6333 i
.types
[op
].bitfield
.disp32s
= 0;
6337 i
.types
[op
].bitfield
.disp32
= 0;
6338 i
.types
[op
].bitfield
.disp32s
= 1;
6340 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6344 /* RIP addressing for 64bit mode. */
6345 else if (i
.base_reg
->reg_num
== RegRip
||
6346 i
.base_reg
->reg_num
== RegEip
)
6348 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6349 i
.rm
.regmem
= NO_BASE_REGISTER
;
6350 i
.types
[op
].bitfield
.disp8
= 0;
6351 i
.types
[op
].bitfield
.disp16
= 0;
6352 i
.types
[op
].bitfield
.disp32
= 0;
6353 i
.types
[op
].bitfield
.disp32s
= 1;
6354 i
.types
[op
].bitfield
.disp64
= 0;
6355 i
.types
[op
].bitfield
.vec_disp8
= 0;
6356 i
.flags
[op
] |= Operand_PCrel
;
6357 if (! i
.disp_operands
)
6358 fake_zero_displacement
= 1;
6360 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6362 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6363 switch (i
.base_reg
->reg_num
)
6366 if (i
.index_reg
== 0)
6368 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6369 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6373 if (i
.index_reg
== 0)
6376 if (operand_type_check (i
.types
[op
], disp
) == 0)
6378 /* fake (%bp) into 0(%bp) */
6379 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6380 i
.types
[op
].bitfield
.vec_disp8
= 1;
6382 i
.types
[op
].bitfield
.disp8
= 1;
6383 fake_zero_displacement
= 1;
6386 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6387 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6389 default: /* (%si) -> 4 or (%di) -> 5 */
6390 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6392 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6394 else /* i.base_reg and 32/64 bit mode */
6396 if (flag_code
== CODE_64BIT
6397 && operand_type_check (i
.types
[op
], disp
))
6399 i386_operand_type temp
;
6400 operand_type_set (&temp
, 0);
6401 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6402 temp
.bitfield
.vec_disp8
6403 = i
.types
[op
].bitfield
.vec_disp8
;
6405 if (i
.prefix
[ADDR_PREFIX
] == 0)
6406 i
.types
[op
].bitfield
.disp32s
= 1;
6408 i
.types
[op
].bitfield
.disp32
= 1;
6411 if (!i
.tm
.opcode_modifier
.vecsib
)
6412 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6413 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6415 i
.sib
.base
= i
.base_reg
->reg_num
;
6416 /* x86-64 ignores REX prefix bit here to avoid decoder
6418 if (!(i
.base_reg
->reg_flags
& RegRex
)
6419 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6420 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6422 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6424 fake_zero_displacement
= 1;
6425 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6426 i
.types
[op
].bitfield
.vec_disp8
= 1;
6428 i
.types
[op
].bitfield
.disp8
= 1;
6430 i
.sib
.scale
= i
.log2_scale_factor
;
6431 if (i
.index_reg
== 0)
6433 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6434 /* <disp>(%esp) becomes two byte modrm with no index
6435 register. We've already stored the code for esp
6436 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6437 Any base register besides %esp will not use the
6438 extra modrm byte. */
6439 i
.sib
.index
= NO_INDEX_REGISTER
;
6441 else if (!i
.tm
.opcode_modifier
.vecsib
)
6443 if (i
.index_reg
->reg_num
== RegEiz
6444 || i
.index_reg
->reg_num
== RegRiz
)
6445 i
.sib
.index
= NO_INDEX_REGISTER
;
6447 i
.sib
.index
= i
.index_reg
->reg_num
;
6448 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6449 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6454 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6455 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6459 if (!fake_zero_displacement
6463 fake_zero_displacement
= 1;
6464 if (i
.disp_encoding
== disp_encoding_8bit
)
6465 i
.types
[op
].bitfield
.disp8
= 1;
6467 i
.types
[op
].bitfield
.disp32
= 1;
6469 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6473 if (fake_zero_displacement
)
6475 /* Fakes a zero displacement assuming that i.types[op]
6476 holds the correct displacement size. */
6479 gas_assert (i
.op
[op
].disps
== 0);
6480 exp
= &disp_expressions
[i
.disp_operands
++];
6481 i
.op
[op
].disps
= exp
;
6482 exp
->X_op
= O_constant
;
6483 exp
->X_add_number
= 0;
6484 exp
->X_add_symbol
= (symbolS
*) 0;
6485 exp
->X_op_symbol
= (symbolS
*) 0;
6493 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6495 if (operand_type_check (i
.types
[0], imm
))
6496 i
.vex
.register_specifier
= NULL
;
6499 /* VEX.vvvv encodes one of the sources when the first
6500 operand is not an immediate. */
6501 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6502 i
.vex
.register_specifier
= i
.op
[0].regs
;
6504 i
.vex
.register_specifier
= i
.op
[1].regs
;
6507 /* Destination is a XMM register encoded in the ModRM.reg
6509 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6510 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6513 /* ModRM.rm and VEX.B encodes the other source. */
6514 if (!i
.mem_operands
)
6518 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6519 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6521 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6523 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6527 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6529 i
.vex
.register_specifier
= i
.op
[2].regs
;
6530 if (!i
.mem_operands
)
6533 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6534 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6538 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6539 (if any) based on i.tm.extension_opcode. Again, we must be
6540 careful to make sure that segment/control/debug/test/MMX
6541 registers are coded into the i.rm.reg field. */
6542 else if (i
.reg_operands
)
6545 unsigned int vex_reg
= ~0;
6547 for (op
= 0; op
< i
.operands
; op
++)
6548 if (i
.types
[op
].bitfield
.reg8
6549 || i
.types
[op
].bitfield
.reg16
6550 || i
.types
[op
].bitfield
.reg32
6551 || i
.types
[op
].bitfield
.reg64
6552 || i
.types
[op
].bitfield
.regmmx
6553 || i
.types
[op
].bitfield
.regxmm
6554 || i
.types
[op
].bitfield
.regymm
6555 || i
.types
[op
].bitfield
.regbnd
6556 || i
.types
[op
].bitfield
.regzmm
6557 || i
.types
[op
].bitfield
.regmask
6558 || i
.types
[op
].bitfield
.sreg2
6559 || i
.types
[op
].bitfield
.sreg3
6560 || i
.types
[op
].bitfield
.control
6561 || i
.types
[op
].bitfield
.debug
6562 || i
.types
[op
].bitfield
.test
)
6567 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6569 /* For instructions with VexNDS, the register-only
6570 source operand is encoded in VEX prefix. */
6571 gas_assert (mem
!= (unsigned int) ~0);
6576 gas_assert (op
< i
.operands
);
6580 /* Check register-only source operand when two source
6581 operands are swapped. */
6582 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6583 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6587 gas_assert (mem
== (vex_reg
+ 1)
6588 && op
< i
.operands
);
6593 gas_assert (vex_reg
< i
.operands
);
6597 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6599 /* For instructions with VexNDD, the register destination
6600 is encoded in VEX prefix. */
6601 if (i
.mem_operands
== 0)
6603 /* There is no memory operand. */
6604 gas_assert ((op
+ 2) == i
.operands
);
6609 /* There are only 2 operands. */
6610 gas_assert (op
< 2 && i
.operands
== 2);
6615 gas_assert (op
< i
.operands
);
6617 if (vex_reg
!= (unsigned int) ~0)
6619 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6621 if (type
->bitfield
.reg32
!= 1
6622 && type
->bitfield
.reg64
!= 1
6623 && !operand_type_equal (type
, ®xmm
)
6624 && !operand_type_equal (type
, ®ymm
)
6625 && !operand_type_equal (type
, ®zmm
)
6626 && !operand_type_equal (type
, ®mask
))
6629 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6632 /* Don't set OP operand twice. */
6635 /* If there is an extension opcode to put here, the
6636 register number must be put into the regmem field. */
6637 if (i
.tm
.extension_opcode
!= None
)
6639 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6640 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6642 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6647 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6648 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6650 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6655 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6656 must set it to 3 to indicate this is a register operand
6657 in the regmem field. */
6658 if (!i
.mem_operands
)
6662 /* Fill in i.rm.reg field with extension opcode (if any). */
6663 if (i
.tm
.extension_opcode
!= None
)
6664 i
.rm
.reg
= i
.tm
.extension_opcode
;
6670 output_branch (void)
6676 relax_substateT subtype
;
6680 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6681 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6684 if (i
.prefix
[DATA_PREFIX
] != 0)
6690 /* Pentium4 branch hints. */
6691 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6692 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6697 if (i
.prefix
[REX_PREFIX
] != 0)
6703 /* BND prefixed jump. */
6704 if (i
.prefix
[BND_PREFIX
] != 0)
6706 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6710 if (i
.prefixes
!= 0 && !intel_syntax
)
6711 as_warn (_("skipping prefixes on this instruction"));
6713 /* It's always a symbol; End frag & setup for relax.
6714 Make sure there is enough room in this frag for the largest
6715 instruction we may generate in md_convert_frag. This is 2
6716 bytes for the opcode and room for the prefix and largest
6718 frag_grow (prefix
+ 2 + 4);
6719 /* Prefix and 1 opcode byte go in fr_fix. */
6720 p
= frag_more (prefix
+ 1);
6721 if (i
.prefix
[DATA_PREFIX
] != 0)
6722 *p
++ = DATA_PREFIX_OPCODE
;
6723 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6724 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6725 *p
++ = i
.prefix
[SEG_PREFIX
];
6726 if (i
.prefix
[REX_PREFIX
] != 0)
6727 *p
++ = i
.prefix
[REX_PREFIX
];
6728 *p
= i
.tm
.base_opcode
;
6730 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6731 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6732 else if (cpu_arch_flags
.bitfield
.cpui386
)
6733 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6735 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6738 sym
= i
.op
[0].disps
->X_add_symbol
;
6739 off
= i
.op
[0].disps
->X_add_number
;
6741 if (i
.op
[0].disps
->X_op
!= O_constant
6742 && i
.op
[0].disps
->X_op
!= O_symbol
)
6744 /* Handle complex expressions. */
6745 sym
= make_expr_symbol (i
.op
[0].disps
);
6749 /* 1 possible extra opcode + 4 byte displacement go in var part.
6750 Pass reloc in fr_var. */
6751 frag_var (rs_machine_dependent
, 5,
6753 || i
.reloc
[0] != NO_RELOC
6754 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6756 : BFD_RELOC_X86_64_PC32_BND
),
6757 subtype
, sym
, off
, p
);
6767 if (i
.tm
.opcode_modifier
.jumpbyte
)
6769 /* This is a loop or jecxz type instruction. */
6771 if (i
.prefix
[ADDR_PREFIX
] != 0)
6773 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6776 /* Pentium4 branch hints. */
6777 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6778 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6780 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6789 if (flag_code
== CODE_16BIT
)
6792 if (i
.prefix
[DATA_PREFIX
] != 0)
6794 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6804 if (i
.prefix
[REX_PREFIX
] != 0)
6806 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6810 /* BND prefixed jump. */
6811 if (i
.prefix
[BND_PREFIX
] != 0)
6813 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6817 if (i
.prefixes
!= 0 && !intel_syntax
)
6818 as_warn (_("skipping prefixes on this instruction"));
6820 p
= frag_more (i
.tm
.opcode_length
+ size
);
6821 switch (i
.tm
.opcode_length
)
6824 *p
++ = i
.tm
.base_opcode
>> 8;
6826 *p
++ = i
.tm
.base_opcode
;
6832 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6833 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6834 (i
.bnd_prefix
!= NULL
6838 /* All jumps handled here are signed, but don't use a signed limit
6839 check for 32 and 16 bit jumps as we want to allow wrap around at
6840 4G and 64k respectively. */
6842 fixP
->fx_signed
= 1;
6846 output_interseg_jump (void)
6854 if (flag_code
== CODE_16BIT
)
6858 if (i
.prefix
[DATA_PREFIX
] != 0)
6864 if (i
.prefix
[REX_PREFIX
] != 0)
6874 if (i
.prefixes
!= 0 && !intel_syntax
)
6875 as_warn (_("skipping prefixes on this instruction"));
6877 /* 1 opcode; 2 segment; offset */
6878 p
= frag_more (prefix
+ 1 + 2 + size
);
6880 if (i
.prefix
[DATA_PREFIX
] != 0)
6881 *p
++ = DATA_PREFIX_OPCODE
;
6883 if (i
.prefix
[REX_PREFIX
] != 0)
6884 *p
++ = i
.prefix
[REX_PREFIX
];
6886 *p
++ = i
.tm
.base_opcode
;
6887 if (i
.op
[1].imms
->X_op
== O_constant
)
6889 offsetT n
= i
.op
[1].imms
->X_add_number
;
6892 && !fits_in_unsigned_word (n
)
6893 && !fits_in_signed_word (n
))
6895 as_bad (_("16-bit jump out of range"));
6898 md_number_to_chars (p
, n
, size
);
6901 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6902 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6903 if (i
.op
[0].imms
->X_op
!= O_constant
)
6904 as_bad (_("can't handle non absolute segment in `%s'"),
6906 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6912 fragS
*insn_start_frag
;
6913 offsetT insn_start_off
;
6915 /* Tie dwarf2 debug info to the address at the start of the insn.
6916 We can't do this after the insn has been output as the current
6917 frag may have been closed off. eg. by frag_var. */
6918 dwarf2_emit_insn (0);
6920 insn_start_frag
= frag_now
;
6921 insn_start_off
= frag_now_fix ();
6924 if (i
.tm
.opcode_modifier
.jump
)
6926 else if (i
.tm
.opcode_modifier
.jumpbyte
6927 || i
.tm
.opcode_modifier
.jumpdword
)
6929 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6930 output_interseg_jump ();
6933 /* Output normal instructions here. */
6937 unsigned int prefix
;
6939 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6940 don't need the explicit prefix. */
6941 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6943 switch (i
.tm
.opcode_length
)
6946 if (i
.tm
.base_opcode
& 0xff000000)
6948 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6953 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6955 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6956 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6959 if (prefix
!= REPE_PREFIX_OPCODE
6960 || (i
.prefix
[REP_PREFIX
]
6961 != REPE_PREFIX_OPCODE
))
6962 add_prefix (prefix
);
6965 add_prefix (prefix
);
6974 /* The prefix bytes. */
6975 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6977 FRAG_APPEND_1_CHAR (*q
);
6981 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6986 /* REX byte is encoded in VEX prefix. */
6990 FRAG_APPEND_1_CHAR (*q
);
6993 /* There should be no other prefixes for instructions
6998 /* For EVEX instructions i.vrex should become 0 after
6999 build_evex_prefix. For VEX instructions upper 16 registers
7000 aren't available, so VREX should be 0. */
7003 /* Now the VEX prefix. */
7004 p
= frag_more (i
.vex
.length
);
7005 for (j
= 0; j
< i
.vex
.length
; j
++)
7006 p
[j
] = i
.vex
.bytes
[j
];
7009 /* Now the opcode; be careful about word order here! */
7010 if (i
.tm
.opcode_length
== 1)
7012 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7016 switch (i
.tm
.opcode_length
)
7020 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7021 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7025 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7035 /* Put out high byte first: can't use md_number_to_chars! */
7036 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7037 *p
= i
.tm
.base_opcode
& 0xff;
7040 /* Now the modrm byte and sib byte (if present). */
7041 if (i
.tm
.opcode_modifier
.modrm
)
7043 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7046 /* If i.rm.regmem == ESP (4)
7047 && i.rm.mode != (Register mode)
7049 ==> need second modrm byte. */
7050 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7052 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7053 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7055 | i
.sib
.scale
<< 6));
7058 if (i
.disp_operands
)
7059 output_disp (insn_start_frag
, insn_start_off
);
7062 output_imm (insn_start_frag
, insn_start_off
);
7068 pi ("" /*line*/, &i
);
7070 #endif /* DEBUG386 */
7073 /* Return the size of the displacement operand N. */
7076 disp_size (unsigned int n
)
7080 /* Vec_Disp8 has to be 8bit. */
7081 if (i
.types
[n
].bitfield
.vec_disp8
)
7083 else if (i
.types
[n
].bitfield
.disp64
)
7085 else if (i
.types
[n
].bitfield
.disp8
)
7087 else if (i
.types
[n
].bitfield
.disp16
)
7092 /* Return the size of the immediate operand N. */
7095 imm_size (unsigned int n
)
7098 if (i
.types
[n
].bitfield
.imm64
)
7100 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7102 else if (i
.types
[n
].bitfield
.imm16
)
7108 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7113 for (n
= 0; n
< i
.operands
; n
++)
7115 if (i
.types
[n
].bitfield
.vec_disp8
7116 || operand_type_check (i
.types
[n
], disp
))
7118 if (i
.op
[n
].disps
->X_op
== O_constant
)
7120 int size
= disp_size (n
);
7121 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7123 if (i
.types
[n
].bitfield
.vec_disp8
)
7125 val
= offset_in_range (val
, size
);
7126 p
= frag_more (size
);
7127 md_number_to_chars (p
, val
, size
);
7131 enum bfd_reloc_code_real reloc_type
;
7132 int size
= disp_size (n
);
7133 int sign
= i
.types
[n
].bitfield
.disp32s
;
7134 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7136 /* We can't have 8 bit displacement here. */
7137 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7139 /* The PC relative address is computed relative
7140 to the instruction boundary, so in case immediate
7141 fields follows, we need to adjust the value. */
7142 if (pcrel
&& i
.imm_operands
)
7147 for (n1
= 0; n1
< i
.operands
; n1
++)
7148 if (operand_type_check (i
.types
[n1
], imm
))
7150 /* Only one immediate is allowed for PC
7151 relative address. */
7152 gas_assert (sz
== 0);
7154 i
.op
[n
].disps
->X_add_number
-= sz
;
7156 /* We should find the immediate. */
7157 gas_assert (sz
!= 0);
7160 p
= frag_more (size
);
7161 reloc_type
= reloc (size
, pcrel
, sign
,
7162 (i
.bnd_prefix
!= NULL
7166 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7167 && (((reloc_type
== BFD_RELOC_32
7168 || reloc_type
== BFD_RELOC_X86_64_32S
7169 || (reloc_type
== BFD_RELOC_64
7171 && (i
.op
[n
].disps
->X_op
== O_symbol
7172 || (i
.op
[n
].disps
->X_op
== O_add
7173 && ((symbol_get_value_expression
7174 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7176 || reloc_type
== BFD_RELOC_32_PCREL
))
7180 if (insn_start_frag
== frag_now
)
7181 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7186 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7187 for (fr
= insn_start_frag
->fr_next
;
7188 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7190 add
+= p
- frag_now
->fr_literal
;
7195 reloc_type
= BFD_RELOC_386_GOTPC
;
7196 i
.op
[n
].imms
->X_add_number
+= add
;
7198 else if (reloc_type
== BFD_RELOC_64
)
7199 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7201 /* Don't do the adjustment for x86-64, as there
7202 the pcrel addressing is relative to the _next_
7203 insn, and that is taken care of in other code. */
7204 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7206 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7207 i
.op
[n
].disps
, pcrel
, reloc_type
);
7214 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7219 for (n
= 0; n
< i
.operands
; n
++)
7221 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7222 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7225 if (operand_type_check (i
.types
[n
], imm
))
7227 if (i
.op
[n
].imms
->X_op
== O_constant
)
7229 int size
= imm_size (n
);
7232 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7234 p
= frag_more (size
);
7235 md_number_to_chars (p
, val
, size
);
7239 /* Not absolute_section.
7240 Need a 32-bit fixup (don't support 8bit
7241 non-absolute imms). Try to support other
7243 enum bfd_reloc_code_real reloc_type
;
7244 int size
= imm_size (n
);
7247 if (i
.types
[n
].bitfield
.imm32s
7248 && (i
.suffix
== QWORD_MNEM_SUFFIX
7249 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7254 p
= frag_more (size
);
7255 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7257 /* This is tough to explain. We end up with this one if we
7258 * have operands that look like
7259 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7260 * obtain the absolute address of the GOT, and it is strongly
7261 * preferable from a performance point of view to avoid using
7262 * a runtime relocation for this. The actual sequence of
7263 * instructions often look something like:
7268 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7270 * The call and pop essentially return the absolute address
7271 * of the label .L66 and store it in %ebx. The linker itself
7272 * will ultimately change the first operand of the addl so
7273 * that %ebx points to the GOT, but to keep things simple, the
7274 * .o file must have this operand set so that it generates not
7275 * the absolute address of .L66, but the absolute address of
7276 * itself. This allows the linker itself simply treat a GOTPC
7277 * relocation as asking for a pcrel offset to the GOT to be
7278 * added in, and the addend of the relocation is stored in the
7279 * operand field for the instruction itself.
7281 * Our job here is to fix the operand so that it would add
7282 * the correct offset so that %ebx would point to itself. The
7283 * thing that is tricky is that .-.L66 will point to the
7284 * beginning of the instruction, so we need to further modify
7285 * the operand so that it will point to itself. There are
7286 * other cases where you have something like:
7288 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7290 * and here no correction would be required. Internally in
7291 * the assembler we treat operands of this form as not being
7292 * pcrel since the '.' is explicitly mentioned, and I wonder
7293 * whether it would simplify matters to do it this way. Who
7294 * knows. In earlier versions of the PIC patches, the
7295 * pcrel_adjust field was used to store the correction, but
7296 * since the expression is not pcrel, I felt it would be
7297 * confusing to do it this way. */
7299 if ((reloc_type
== BFD_RELOC_32
7300 || reloc_type
== BFD_RELOC_X86_64_32S
7301 || reloc_type
== BFD_RELOC_64
)
7303 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7304 && (i
.op
[n
].imms
->X_op
== O_symbol
7305 || (i
.op
[n
].imms
->X_op
== O_add
7306 && ((symbol_get_value_expression
7307 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7312 if (insn_start_frag
== frag_now
)
7313 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7318 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7319 for (fr
= insn_start_frag
->fr_next
;
7320 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7322 add
+= p
- frag_now
->fr_literal
;
7326 reloc_type
= BFD_RELOC_386_GOTPC
;
7328 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7330 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7331 i
.op
[n
].imms
->X_add_number
+= add
;
7333 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7334 i
.op
[n
].imms
, 0, reloc_type
);
7340 /* x86_cons_fix_new is called via the expression parsing code when a
7341 reloc is needed. We use this hook to get the correct .got reloc. */
7342 static int cons_sign
= -1;
7345 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7346 expressionS
*exp
, bfd_reloc_code_real_type r
)
7348 r
= reloc (len
, 0, cons_sign
, 0, r
);
7351 if (exp
->X_op
== O_secrel
)
7353 exp
->X_op
= O_symbol
;
7354 r
= BFD_RELOC_32_SECREL
;
7358 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7361 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7362 purpose of the `.dc.a' internal pseudo-op. */
7365 x86_address_bytes (void)
7367 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7369 return stdoutput
->arch_info
->bits_per_address
/ 8;
7372 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7374 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7376 /* Parse operands of the form
7377 <symbol>@GOTOFF+<nnn>
7378 and similar .plt or .got references.
7380 If we find one, set up the correct relocation in RELOC and copy the
7381 input string, minus the `@GOTOFF' into a malloc'd buffer for
7382 parsing by the calling routine. Return this buffer, and if ADJUST
7383 is non-null set it to the length of the string we removed from the
7384 input line. Otherwise return NULL. */
7386 lex_got (enum bfd_reloc_code_real
*rel
,
7388 i386_operand_type
*types
,
7391 /* Some of the relocations depend on the size of what field is to
7392 be relocated. But in our callers i386_immediate and i386_displacement
7393 we don't yet know the operand size (this will be set by insn
7394 matching). Hence we record the word32 relocation here,
7395 and adjust the reloc according to the real size in reloc(). */
7396 static const struct {
7399 const enum bfd_reloc_code_real rel
[2];
7400 const i386_operand_type types64
;
7402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7403 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7405 OPERAND_TYPE_IMM32_64
},
7407 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7408 BFD_RELOC_X86_64_PLTOFF64
},
7409 OPERAND_TYPE_IMM64
},
7410 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7411 BFD_RELOC_X86_64_PLT32
},
7412 OPERAND_TYPE_IMM32_32S_DISP32
},
7413 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7414 BFD_RELOC_X86_64_GOTPLT64
},
7415 OPERAND_TYPE_IMM64_DISP64
},
7416 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7417 BFD_RELOC_X86_64_GOTOFF64
},
7418 OPERAND_TYPE_IMM64_DISP64
},
7419 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7420 BFD_RELOC_X86_64_GOTPCREL
},
7421 OPERAND_TYPE_IMM32_32S_DISP32
},
7422 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7423 BFD_RELOC_X86_64_TLSGD
},
7424 OPERAND_TYPE_IMM32_32S_DISP32
},
7425 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7426 _dummy_first_bfd_reloc_code_real
},
7427 OPERAND_TYPE_NONE
},
7428 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7429 BFD_RELOC_X86_64_TLSLD
},
7430 OPERAND_TYPE_IMM32_32S_DISP32
},
7431 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7432 BFD_RELOC_X86_64_GOTTPOFF
},
7433 OPERAND_TYPE_IMM32_32S_DISP32
},
7434 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7435 BFD_RELOC_X86_64_TPOFF32
},
7436 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7437 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7438 _dummy_first_bfd_reloc_code_real
},
7439 OPERAND_TYPE_NONE
},
7440 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7441 BFD_RELOC_X86_64_DTPOFF32
},
7442 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7443 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7444 _dummy_first_bfd_reloc_code_real
},
7445 OPERAND_TYPE_NONE
},
7446 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7447 _dummy_first_bfd_reloc_code_real
},
7448 OPERAND_TYPE_NONE
},
7449 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7450 BFD_RELOC_X86_64_GOT32
},
7451 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7452 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7453 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7454 OPERAND_TYPE_IMM32_32S_DISP32
},
7455 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7456 BFD_RELOC_X86_64_TLSDESC_CALL
},
7457 OPERAND_TYPE_IMM32_32S_DISP32
},
7462 #if defined (OBJ_MAYBE_ELF)
7467 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7468 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7471 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7473 int len
= gotrel
[j
].len
;
7474 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7476 if (gotrel
[j
].rel
[object_64bit
] != 0)
7479 char *tmpbuf
, *past_reloc
;
7481 *rel
= gotrel
[j
].rel
[object_64bit
];
7485 if (flag_code
!= CODE_64BIT
)
7487 types
->bitfield
.imm32
= 1;
7488 types
->bitfield
.disp32
= 1;
7491 *types
= gotrel
[j
].types64
;
7494 if (j
!= 0 && GOT_symbol
== NULL
)
7495 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7497 /* The length of the first part of our input line. */
7498 first
= cp
- input_line_pointer
;
7500 /* The second part goes from after the reloc token until
7501 (and including) an end_of_line char or comma. */
7502 past_reloc
= cp
+ 1 + len
;
7504 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7506 second
= cp
+ 1 - past_reloc
;
7508 /* Allocate and copy string. The trailing NUL shouldn't
7509 be necessary, but be safe. */
7510 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7511 memcpy (tmpbuf
, input_line_pointer
, first
);
7512 if (second
!= 0 && *past_reloc
!= ' ')
7513 /* Replace the relocation token with ' ', so that
7514 errors like foo@GOTOFF1 will be detected. */
7515 tmpbuf
[first
++] = ' ';
7517 /* Increment length by 1 if the relocation token is
7522 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7523 tmpbuf
[first
+ second
] = '\0';
7524 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7525 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7529 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7530 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7535 /* Might be a symbol version string. Don't as_bad here. */
7544 /* Parse operands of the form
7545 <symbol>@SECREL32+<nnn>
7547 If we find one, set up the correct relocation in RELOC and copy the
7548 input string, minus the `@SECREL32' into a malloc'd buffer for
7549 parsing by the calling routine. Return this buffer, and if ADJUST
7550 is non-null set it to the length of the string we removed from the
7551 input line. Otherwise return NULL.
7553 This function is copied from the ELF version above adjusted for PE targets. */
7556 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7557 int *adjust ATTRIBUTE_UNUSED
,
7558 i386_operand_type
*types
,
7559 int bnd_prefix ATTRIBUTE_UNUSED
)
7565 const enum bfd_reloc_code_real rel
[2];
7566 const i386_operand_type types64
;
7570 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7571 BFD_RELOC_32_SECREL
},
7572 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7578 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7579 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7582 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7584 int len
= gotrel
[j
].len
;
7586 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7588 if (gotrel
[j
].rel
[object_64bit
] != 0)
7591 char *tmpbuf
, *past_reloc
;
7593 *rel
= gotrel
[j
].rel
[object_64bit
];
7599 if (flag_code
!= CODE_64BIT
)
7601 types
->bitfield
.imm32
= 1;
7602 types
->bitfield
.disp32
= 1;
7605 *types
= gotrel
[j
].types64
;
7608 /* The length of the first part of our input line. */
7609 first
= cp
- input_line_pointer
;
7611 /* The second part goes from after the reloc token until
7612 (and including) an end_of_line char or comma. */
7613 past_reloc
= cp
+ 1 + len
;
7615 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7617 second
= cp
+ 1 - past_reloc
;
7619 /* Allocate and copy string. The trailing NUL shouldn't
7620 be necessary, but be safe. */
7621 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7622 memcpy (tmpbuf
, input_line_pointer
, first
);
7623 if (second
!= 0 && *past_reloc
!= ' ')
7624 /* Replace the relocation token with ' ', so that
7625 errors like foo@SECLREL321 will be detected. */
7626 tmpbuf
[first
++] = ' ';
7627 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7628 tmpbuf
[first
+ second
] = '\0';
7632 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7633 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7638 /* Might be a symbol version string. Don't as_bad here. */
7644 bfd_reloc_code_real_type
7645 x86_cons (expressionS
*exp
, int size
)
7647 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7649 intel_syntax
= -intel_syntax
;
7652 if (size
== 4 || (object_64bit
&& size
== 8))
7654 /* Handle @GOTOFF and the like in an expression. */
7656 char *gotfree_input_line
;
7659 save
= input_line_pointer
;
7660 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7661 if (gotfree_input_line
)
7662 input_line_pointer
= gotfree_input_line
;
7666 if (gotfree_input_line
)
7668 /* expression () has merrily parsed up to the end of line,
7669 or a comma - in the wrong buffer. Transfer how far
7670 input_line_pointer has moved to the right buffer. */
7671 input_line_pointer
= (save
7672 + (input_line_pointer
- gotfree_input_line
)
7674 free (gotfree_input_line
);
7675 if (exp
->X_op
== O_constant
7676 || exp
->X_op
== O_absent
7677 || exp
->X_op
== O_illegal
7678 || exp
->X_op
== O_register
7679 || exp
->X_op
== O_big
)
7681 char c
= *input_line_pointer
;
7682 *input_line_pointer
= 0;
7683 as_bad (_("missing or invalid expression `%s'"), save
);
7684 *input_line_pointer
= c
;
7691 intel_syntax
= -intel_syntax
;
7694 i386_intel_simplify (exp
);
7700 signed_cons (int size
)
7702 if (flag_code
== CODE_64BIT
)
7710 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7717 if (exp
.X_op
== O_symbol
)
7718 exp
.X_op
= O_secrel
;
7720 emit_expr (&exp
, 4);
7722 while (*input_line_pointer
++ == ',');
7724 input_line_pointer
--;
7725 demand_empty_rest_of_line ();
7729 /* Handle Vector operations. */
7732 check_VecOperations (char *op_string
, char *op_end
)
7734 const reg_entry
*mask
;
7739 && (op_end
== NULL
|| op_string
< op_end
))
7742 if (*op_string
== '{')
7746 /* Check broadcasts. */
7747 if (strncmp (op_string
, "1to", 3) == 0)
7752 goto duplicated_vec_op
;
7755 if (*op_string
== '8')
7756 bcst_type
= BROADCAST_1TO8
;
7757 else if (*op_string
== '4')
7758 bcst_type
= BROADCAST_1TO4
;
7759 else if (*op_string
== '2')
7760 bcst_type
= BROADCAST_1TO2
;
7761 else if (*op_string
== '1'
7762 && *(op_string
+1) == '6')
7764 bcst_type
= BROADCAST_1TO16
;
7769 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7774 broadcast_op
.type
= bcst_type
;
7775 broadcast_op
.operand
= this_operand
;
7776 i
.broadcast
= &broadcast_op
;
7778 /* Check masking operation. */
7779 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7781 /* k0 can't be used for write mask. */
7782 if (mask
->reg_num
== 0)
7784 as_bad (_("`%s' can't be used for write mask"),
7791 mask_op
.mask
= mask
;
7792 mask_op
.zeroing
= 0;
7793 mask_op
.operand
= this_operand
;
7799 goto duplicated_vec_op
;
7801 i
.mask
->mask
= mask
;
7803 /* Only "{z}" is allowed here. No need to check
7804 zeroing mask explicitly. */
7805 if (i
.mask
->operand
!= this_operand
)
7807 as_bad (_("invalid write mask `%s'"), saved
);
7814 /* Check zeroing-flag for masking operation. */
7815 else if (*op_string
== 'z')
7819 mask_op
.mask
= NULL
;
7820 mask_op
.zeroing
= 1;
7821 mask_op
.operand
= this_operand
;
7826 if (i
.mask
->zeroing
)
7829 as_bad (_("duplicated `%s'"), saved
);
7833 i
.mask
->zeroing
= 1;
7835 /* Only "{%k}" is allowed here. No need to check mask
7836 register explicitly. */
7837 if (i
.mask
->operand
!= this_operand
)
7839 as_bad (_("invalid zeroing-masking `%s'"),
7848 goto unknown_vec_op
;
7850 if (*op_string
!= '}')
7852 as_bad (_("missing `}' in `%s'"), saved
);
7859 /* We don't know this one. */
7860 as_bad (_("unknown vector operation: `%s'"), saved
);
7868 i386_immediate (char *imm_start
)
7870 char *save_input_line_pointer
;
7871 char *gotfree_input_line
;
7874 i386_operand_type types
;
7876 operand_type_set (&types
, ~0);
7878 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7880 as_bad (_("at most %d immediate operands are allowed"),
7881 MAX_IMMEDIATE_OPERANDS
);
7885 exp
= &im_expressions
[i
.imm_operands
++];
7886 i
.op
[this_operand
].imms
= exp
;
7888 if (is_space_char (*imm_start
))
7891 save_input_line_pointer
= input_line_pointer
;
7892 input_line_pointer
= imm_start
;
7894 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7895 (i
.bnd_prefix
!= NULL
7896 || add_bnd_prefix
));
7897 if (gotfree_input_line
)
7898 input_line_pointer
= gotfree_input_line
;
7900 exp_seg
= expression (exp
);
7904 /* Handle vector operations. */
7905 if (*input_line_pointer
== '{')
7907 input_line_pointer
= check_VecOperations (input_line_pointer
,
7909 if (input_line_pointer
== NULL
)
7913 if (*input_line_pointer
)
7914 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7916 input_line_pointer
= save_input_line_pointer
;
7917 if (gotfree_input_line
)
7919 free (gotfree_input_line
);
7921 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7922 exp
->X_op
= O_illegal
;
7925 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7929 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7930 i386_operand_type types
, const char *imm_start
)
7932 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7935 as_bad (_("missing or invalid immediate expression `%s'"),
7939 else if (exp
->X_op
== O_constant
)
7941 /* Size it properly later. */
7942 i
.types
[this_operand
].bitfield
.imm64
= 1;
7943 /* If not 64bit, sign extend val. */
7944 if (flag_code
!= CODE_64BIT
7945 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7947 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7949 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7950 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7951 && exp_seg
!= absolute_section
7952 && exp_seg
!= text_section
7953 && exp_seg
!= data_section
7954 && exp_seg
!= bss_section
7955 && exp_seg
!= undefined_section
7956 && !bfd_is_com_section (exp_seg
))
7958 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7962 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7965 as_bad (_("illegal immediate register operand %s"), imm_start
);
7970 /* This is an address. The size of the address will be
7971 determined later, depending on destination register,
7972 suffix, or the default for the section. */
7973 i
.types
[this_operand
].bitfield
.imm8
= 1;
7974 i
.types
[this_operand
].bitfield
.imm16
= 1;
7975 i
.types
[this_operand
].bitfield
.imm32
= 1;
7976 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7977 i
.types
[this_operand
].bitfield
.imm64
= 1;
7978 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7986 i386_scale (char *scale
)
7989 char *save
= input_line_pointer
;
7991 input_line_pointer
= scale
;
7992 val
= get_absolute_expression ();
7997 i
.log2_scale_factor
= 0;
8000 i
.log2_scale_factor
= 1;
8003 i
.log2_scale_factor
= 2;
8006 i
.log2_scale_factor
= 3;
8010 char sep
= *input_line_pointer
;
8012 *input_line_pointer
= '\0';
8013 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8015 *input_line_pointer
= sep
;
8016 input_line_pointer
= save
;
8020 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8022 as_warn (_("scale factor of %d without an index register"),
8023 1 << i
.log2_scale_factor
);
8024 i
.log2_scale_factor
= 0;
8026 scale
= input_line_pointer
;
8027 input_line_pointer
= save
;
8032 i386_displacement (char *disp_start
, char *disp_end
)
8036 char *save_input_line_pointer
;
8037 char *gotfree_input_line
;
8039 i386_operand_type bigdisp
, types
= anydisp
;
8042 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8044 as_bad (_("at most %d displacement operands are allowed"),
8045 MAX_MEMORY_OPERANDS
);
8049 operand_type_set (&bigdisp
, 0);
8050 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8051 || (!current_templates
->start
->opcode_modifier
.jump
8052 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8054 bigdisp
.bitfield
.disp32
= 1;
8055 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8056 if (flag_code
== CODE_64BIT
)
8060 bigdisp
.bitfield
.disp32s
= 1;
8061 bigdisp
.bitfield
.disp64
= 1;
8064 else if ((flag_code
== CODE_16BIT
) ^ override
)
8066 bigdisp
.bitfield
.disp32
= 0;
8067 bigdisp
.bitfield
.disp16
= 1;
8072 /* For PC-relative branches, the width of the displacement
8073 is dependent upon data size, not address size. */
8074 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8075 if (flag_code
== CODE_64BIT
)
8077 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8078 bigdisp
.bitfield
.disp16
= 1;
8081 bigdisp
.bitfield
.disp32
= 1;
8082 bigdisp
.bitfield
.disp32s
= 1;
8088 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8090 : LONG_MNEM_SUFFIX
));
8091 bigdisp
.bitfield
.disp32
= 1;
8092 if ((flag_code
== CODE_16BIT
) ^ override
)
8094 bigdisp
.bitfield
.disp32
= 0;
8095 bigdisp
.bitfield
.disp16
= 1;
8099 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8102 exp
= &disp_expressions
[i
.disp_operands
];
8103 i
.op
[this_operand
].disps
= exp
;
8105 save_input_line_pointer
= input_line_pointer
;
8106 input_line_pointer
= disp_start
;
8107 END_STRING_AND_SAVE (disp_end
);
8109 #ifndef GCC_ASM_O_HACK
8110 #define GCC_ASM_O_HACK 0
8113 END_STRING_AND_SAVE (disp_end
+ 1);
8114 if (i
.types
[this_operand
].bitfield
.baseIndex
8115 && displacement_string_end
[-1] == '+')
8117 /* This hack is to avoid a warning when using the "o"
8118 constraint within gcc asm statements.
8121 #define _set_tssldt_desc(n,addr,limit,type) \
8122 __asm__ __volatile__ ( \
8124 "movw %w1,2+%0\n\t" \
8126 "movb %b1,4+%0\n\t" \
8127 "movb %4,5+%0\n\t" \
8128 "movb $0,6+%0\n\t" \
8129 "movb %h1,7+%0\n\t" \
8131 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8133 This works great except that the output assembler ends
8134 up looking a bit weird if it turns out that there is
8135 no offset. You end up producing code that looks like:
8148 So here we provide the missing zero. */
8150 *displacement_string_end
= '0';
8153 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8154 (i
.bnd_prefix
!= NULL
8155 || add_bnd_prefix
));
8156 if (gotfree_input_line
)
8157 input_line_pointer
= gotfree_input_line
;
8159 exp_seg
= expression (exp
);
8162 if (*input_line_pointer
)
8163 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8165 RESTORE_END_STRING (disp_end
+ 1);
8167 input_line_pointer
= save_input_line_pointer
;
8168 if (gotfree_input_line
)
8170 free (gotfree_input_line
);
8172 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8173 exp
->X_op
= O_illegal
;
8176 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8178 RESTORE_END_STRING (disp_end
);
8184 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8185 i386_operand_type types
, const char *disp_start
)
8187 i386_operand_type bigdisp
;
8190 /* We do this to make sure that the section symbol is in
8191 the symbol table. We will ultimately change the relocation
8192 to be relative to the beginning of the section. */
8193 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8194 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8195 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8197 if (exp
->X_op
!= O_symbol
)
8200 if (S_IS_LOCAL (exp
->X_add_symbol
)
8201 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8202 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8203 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8204 exp
->X_op
= O_subtract
;
8205 exp
->X_op_symbol
= GOT_symbol
;
8206 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8207 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8208 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8209 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8211 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8214 else if (exp
->X_op
== O_absent
8215 || exp
->X_op
== O_illegal
8216 || exp
->X_op
== O_big
)
8219 as_bad (_("missing or invalid displacement expression `%s'"),
8224 else if (flag_code
== CODE_64BIT
8225 && !i
.prefix
[ADDR_PREFIX
]
8226 && exp
->X_op
== O_constant
)
8228 /* Since displacement is signed extended to 64bit, don't allow
8229 disp32 and turn off disp32s if they are out of range. */
8230 i
.types
[this_operand
].bitfield
.disp32
= 0;
8231 if (!fits_in_signed_long (exp
->X_add_number
))
8233 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8234 if (i
.types
[this_operand
].bitfield
.baseindex
)
8236 as_bad (_("0x%lx out range of signed 32bit displacement"),
8237 (long) exp
->X_add_number
);
8243 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8244 else if (exp
->X_op
!= O_constant
8245 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8246 && exp_seg
!= absolute_section
8247 && exp_seg
!= text_section
8248 && exp_seg
!= data_section
8249 && exp_seg
!= bss_section
8250 && exp_seg
!= undefined_section
8251 && !bfd_is_com_section (exp_seg
))
8253 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8258 /* Check if this is a displacement only operand. */
8259 bigdisp
= i
.types
[this_operand
];
8260 bigdisp
.bitfield
.disp8
= 0;
8261 bigdisp
.bitfield
.disp16
= 0;
8262 bigdisp
.bitfield
.disp32
= 0;
8263 bigdisp
.bitfield
.disp32s
= 0;
8264 bigdisp
.bitfield
.disp64
= 0;
8265 if (operand_type_all_zero (&bigdisp
))
8266 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8272 /* Make sure the memory operand we've been dealt is valid.
8273 Return 1 on success, 0 on a failure. */
8276 i386_index_check (const char *operand_string
)
8278 const char *kind
= "base/index";
8279 enum flag_code addr_mode
;
8281 if (i
.prefix
[ADDR_PREFIX
])
8282 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8285 addr_mode
= flag_code
;
8287 #if INFER_ADDR_PREFIX
8288 if (i
.mem_operands
== 0)
8290 /* Infer address prefix from the first memory operand. */
8291 const reg_entry
*addr_reg
= i
.base_reg
;
8293 if (addr_reg
== NULL
)
8294 addr_reg
= i
.index_reg
;
8298 if (addr_reg
->reg_num
== RegEip
8299 || addr_reg
->reg_num
== RegEiz
8300 || addr_reg
->reg_type
.bitfield
.reg32
)
8301 addr_mode
= CODE_32BIT
;
8302 else if (flag_code
!= CODE_64BIT
8303 && addr_reg
->reg_type
.bitfield
.reg16
)
8304 addr_mode
= CODE_16BIT
;
8306 if (addr_mode
!= flag_code
)
8308 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8310 /* Change the size of any displacement too. At most one
8311 of Disp16 or Disp32 is set.
8312 FIXME. There doesn't seem to be any real need for
8313 separate Disp16 and Disp32 flags. The same goes for
8314 Imm16 and Imm32. Removing them would probably clean
8315 up the code quite a lot. */
8316 if (flag_code
!= CODE_64BIT
8317 && (i
.types
[this_operand
].bitfield
.disp16
8318 || i
.types
[this_operand
].bitfield
.disp32
))
8319 i
.types
[this_operand
]
8320 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8327 if (current_templates
->start
->opcode_modifier
.isstring
8328 && !current_templates
->start
->opcode_modifier
.immext
8329 && (current_templates
->end
[-1].opcode_modifier
.isstring
8332 /* Memory operands of string insns are special in that they only allow
8333 a single register (rDI, rSI, or rBX) as their memory address. */
8334 const reg_entry
*expected_reg
;
8335 static const char *di_si
[][2] =
8341 static const char *bx
[] = { "ebx", "bx", "rbx" };
8343 kind
= "string address";
8345 if (current_templates
->start
->opcode_modifier
.w
)
8347 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8349 if (!type
.bitfield
.baseindex
8350 || ((!i
.mem_operands
!= !intel_syntax
)
8351 && current_templates
->end
[-1].operand_types
[1]
8352 .bitfield
.baseindex
))
8353 type
= current_templates
->end
[-1].operand_types
[1];
8354 expected_reg
= hash_find (reg_hash
,
8355 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8359 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8361 if (i
.base_reg
!= expected_reg
8363 || operand_type_check (i
.types
[this_operand
], disp
))
8365 /* The second memory operand must have the same size as
8369 && !((addr_mode
== CODE_64BIT
8370 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8371 || (addr_mode
== CODE_32BIT
8372 ? i
.base_reg
->reg_type
.bitfield
.reg32
8373 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8376 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8378 intel_syntax
? '[' : '(',
8380 expected_reg
->reg_name
,
8381 intel_syntax
? ']' : ')');
8388 as_bad (_("`%s' is not a valid %s expression"),
8389 operand_string
, kind
);
8394 if (addr_mode
!= CODE_16BIT
)
8396 /* 32-bit/64-bit checks. */
8398 && (addr_mode
== CODE_64BIT
8399 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8400 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8402 || (i
.base_reg
->reg_num
8403 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8405 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8406 && !i
.index_reg
->reg_type
.bitfield
.regymm
8407 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8408 && ((addr_mode
== CODE_64BIT
8409 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8410 || i
.index_reg
->reg_num
== RegRiz
)
8411 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8412 || i
.index_reg
->reg_num
== RegEiz
))
8413 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8418 /* 16-bit checks. */
8420 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8421 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8423 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8424 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8426 && i
.base_reg
->reg_num
< 6
8427 && i
.index_reg
->reg_num
>= 6
8428 && i
.log2_scale_factor
== 0))))
8435 /* Handle vector immediates. */
8438 RC_SAE_immediate (const char *imm_start
)
8440 unsigned int match_found
, j
;
8441 const char *pstr
= imm_start
;
8449 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8451 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8455 rc_op
.type
= RC_NamesTable
[j
].type
;
8456 rc_op
.operand
= this_operand
;
8457 i
.rounding
= &rc_op
;
8461 as_bad (_("duplicated `%s'"), imm_start
);
8464 pstr
+= RC_NamesTable
[j
].len
;
8474 as_bad (_("Missing '}': '%s'"), imm_start
);
8477 /* RC/SAE immediate string should contain nothing more. */;
8480 as_bad (_("Junk after '}': '%s'"), imm_start
);
8484 exp
= &im_expressions
[i
.imm_operands
++];
8485 i
.op
[this_operand
].imms
= exp
;
8487 exp
->X_op
= O_constant
;
8488 exp
->X_add_number
= 0;
8489 exp
->X_add_symbol
= (symbolS
*) 0;
8490 exp
->X_op_symbol
= (symbolS
*) 0;
8492 i
.types
[this_operand
].bitfield
.imm8
= 1;
8496 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8500 i386_att_operand (char *operand_string
)
8504 char *op_string
= operand_string
;
8506 if (is_space_char (*op_string
))
8509 /* We check for an absolute prefix (differentiating,
8510 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8511 if (*op_string
== ABSOLUTE_PREFIX
)
8514 if (is_space_char (*op_string
))
8516 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8519 /* Check if operand is a register. */
8520 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8522 i386_operand_type temp
;
8524 /* Check for a segment override by searching for ':' after a
8525 segment register. */
8527 if (is_space_char (*op_string
))
8529 if (*op_string
== ':'
8530 && (r
->reg_type
.bitfield
.sreg2
8531 || r
->reg_type
.bitfield
.sreg3
))
8536 i
.seg
[i
.mem_operands
] = &es
;
8539 i
.seg
[i
.mem_operands
] = &cs
;
8542 i
.seg
[i
.mem_operands
] = &ss
;
8545 i
.seg
[i
.mem_operands
] = &ds
;
8548 i
.seg
[i
.mem_operands
] = &fs
;
8551 i
.seg
[i
.mem_operands
] = &gs
;
8555 /* Skip the ':' and whitespace. */
8557 if (is_space_char (*op_string
))
8560 if (!is_digit_char (*op_string
)
8561 && !is_identifier_char (*op_string
)
8562 && *op_string
!= '('
8563 && *op_string
!= ABSOLUTE_PREFIX
)
8565 as_bad (_("bad memory operand `%s'"), op_string
);
8568 /* Handle case of %es:*foo. */
8569 if (*op_string
== ABSOLUTE_PREFIX
)
8572 if (is_space_char (*op_string
))
8574 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8576 goto do_memory_reference
;
8579 /* Handle vector operations. */
8580 if (*op_string
== '{')
8582 op_string
= check_VecOperations (op_string
, NULL
);
8583 if (op_string
== NULL
)
8589 as_bad (_("junk `%s' after register"), op_string
);
8593 temp
.bitfield
.baseindex
= 0;
8594 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8596 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8597 i
.op
[this_operand
].regs
= r
;
8600 else if (*op_string
== REGISTER_PREFIX
)
8602 as_bad (_("bad register name `%s'"), op_string
);
8605 else if (*op_string
== IMMEDIATE_PREFIX
)
8608 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8610 as_bad (_("immediate operand illegal with absolute jump"));
8613 if (!i386_immediate (op_string
))
8616 else if (RC_SAE_immediate (operand_string
))
8618 /* If it is a RC or SAE immediate, do nothing. */
8621 else if (is_digit_char (*op_string
)
8622 || is_identifier_char (*op_string
)
8623 || *op_string
== '(')
8625 /* This is a memory reference of some sort. */
8628 /* Start and end of displacement string expression (if found). */
8629 char *displacement_string_start
;
8630 char *displacement_string_end
;
8633 do_memory_reference
:
8634 if ((i
.mem_operands
== 1
8635 && !current_templates
->start
->opcode_modifier
.isstring
)
8636 || i
.mem_operands
== 2)
8638 as_bad (_("too many memory references for `%s'"),
8639 current_templates
->start
->name
);
8643 /* Check for base index form. We detect the base index form by
8644 looking for an ')' at the end of the operand, searching
8645 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8647 base_string
= op_string
+ strlen (op_string
);
8649 /* Handle vector operations. */
8650 vop_start
= strchr (op_string
, '{');
8651 if (vop_start
&& vop_start
< base_string
)
8653 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8655 base_string
= vop_start
;
8659 if (is_space_char (*base_string
))
8662 /* If we only have a displacement, set-up for it to be parsed later. */
8663 displacement_string_start
= op_string
;
8664 displacement_string_end
= base_string
+ 1;
8666 if (*base_string
== ')')
8669 unsigned int parens_balanced
= 1;
8670 /* We've already checked that the number of left & right ()'s are
8671 equal, so this loop will not be infinite. */
8675 if (*base_string
== ')')
8677 if (*base_string
== '(')
8680 while (parens_balanced
);
8682 temp_string
= base_string
;
8684 /* Skip past '(' and whitespace. */
8686 if (is_space_char (*base_string
))
8689 if (*base_string
== ','
8690 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8693 displacement_string_end
= temp_string
;
8695 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8699 base_string
= end_op
;
8700 if (is_space_char (*base_string
))
8704 /* There may be an index reg or scale factor here. */
8705 if (*base_string
== ',')
8708 if (is_space_char (*base_string
))
8711 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8714 base_string
= end_op
;
8715 if (is_space_char (*base_string
))
8717 if (*base_string
== ',')
8720 if (is_space_char (*base_string
))
8723 else if (*base_string
!= ')')
8725 as_bad (_("expecting `,' or `)' "
8726 "after index register in `%s'"),
8731 else if (*base_string
== REGISTER_PREFIX
)
8733 end_op
= strchr (base_string
, ',');
8736 as_bad (_("bad register name `%s'"), base_string
);
8740 /* Check for scale factor. */
8741 if (*base_string
!= ')')
8743 char *end_scale
= i386_scale (base_string
);
8748 base_string
= end_scale
;
8749 if (is_space_char (*base_string
))
8751 if (*base_string
!= ')')
8753 as_bad (_("expecting `)' "
8754 "after scale factor in `%s'"),
8759 else if (!i
.index_reg
)
8761 as_bad (_("expecting index register or scale factor "
8762 "after `,'; got '%c'"),
8767 else if (*base_string
!= ')')
8769 as_bad (_("expecting `,' or `)' "
8770 "after base register in `%s'"),
8775 else if (*base_string
== REGISTER_PREFIX
)
8777 end_op
= strchr (base_string
, ',');
8780 as_bad (_("bad register name `%s'"), base_string
);
8785 /* If there's an expression beginning the operand, parse it,
8786 assuming displacement_string_start and
8787 displacement_string_end are meaningful. */
8788 if (displacement_string_start
!= displacement_string_end
)
8790 if (!i386_displacement (displacement_string_start
,
8791 displacement_string_end
))
8795 /* Special case for (%dx) while doing input/output op. */
8797 && operand_type_equal (&i
.base_reg
->reg_type
,
8798 ®16_inoutportreg
)
8800 && i
.log2_scale_factor
== 0
8801 && i
.seg
[i
.mem_operands
] == 0
8802 && !operand_type_check (i
.types
[this_operand
], disp
))
8804 i
.types
[this_operand
] = inoutportreg
;
8808 if (i386_index_check (operand_string
) == 0)
8810 i
.types
[this_operand
].bitfield
.mem
= 1;
8815 /* It's not a memory operand; argh! */
8816 as_bad (_("invalid char %s beginning operand %d `%s'"),
8817 output_invalid (*op_string
),
8822 return 1; /* Normal return. */
8825 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8826 that an rs_machine_dependent frag may reach. */
8829 i386_frag_max_var (fragS
*frag
)
8831 /* The only relaxable frags are for jumps.
8832 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8833 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8834 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8837 /* md_estimate_size_before_relax()
8839 Called just before relax() for rs_machine_dependent frags. The x86
8840 assembler uses these frags to handle variable size jump
8843 Any symbol that is now undefined will not become defined.
8844 Return the correct fr_subtype in the frag.
8845 Return the initial "guess for variable size of frag" to caller.
8846 The guess is actually the growth beyond the fixed part. Whatever
8847 we do to grow the fixed or variable part contributes to our
8851 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8853 /* We've already got fragP->fr_subtype right; all we have to do is
8854 check for un-relaxable symbols. On an ELF system, we can't relax
8855 an externally visible symbol, because it may be overridden by a
8857 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8860 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8861 || S_IS_WEAK (fragP
->fr_symbol
)
8862 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8863 & BSF_GNU_INDIRECT_FUNCTION
))))
8865 #if defined (OBJ_COFF) && defined (TE_PE)
8866 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8867 && S_IS_WEAK (fragP
->fr_symbol
))
8871 /* Symbol is undefined in this segment, or we need to keep a
8872 reloc so that weak symbols can be overridden. */
8873 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8874 enum bfd_reloc_code_real reloc_type
;
8875 unsigned char *opcode
;
8878 if (fragP
->fr_var
!= NO_RELOC
)
8879 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8881 reloc_type
= BFD_RELOC_16_PCREL
;
8883 reloc_type
= BFD_RELOC_32_PCREL
;
8885 old_fr_fix
= fragP
->fr_fix
;
8886 opcode
= (unsigned char *) fragP
->fr_opcode
;
8888 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8891 /* Make jmp (0xeb) a (d)word displacement jump. */
8893 fragP
->fr_fix
+= size
;
8894 fix_new (fragP
, old_fr_fix
, size
,
8896 fragP
->fr_offset
, 1,
8902 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8904 /* Negate the condition, and branch past an
8905 unconditional jump. */
8908 /* Insert an unconditional jump. */
8910 /* We added two extra opcode bytes, and have a two byte
8912 fragP
->fr_fix
+= 2 + 2;
8913 fix_new (fragP
, old_fr_fix
+ 2, 2,
8915 fragP
->fr_offset
, 1,
8922 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8927 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8929 fragP
->fr_offset
, 1,
8931 fixP
->fx_signed
= 1;
8935 /* This changes the byte-displacement jump 0x7N
8936 to the (d)word-displacement jump 0x0f,0x8N. */
8937 opcode
[1] = opcode
[0] + 0x10;
8938 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8939 /* We've added an opcode byte. */
8940 fragP
->fr_fix
+= 1 + size
;
8941 fix_new (fragP
, old_fr_fix
+ 1, size
,
8943 fragP
->fr_offset
, 1,
8948 BAD_CASE (fragP
->fr_subtype
);
8952 return fragP
->fr_fix
- old_fr_fix
;
8955 /* Guess size depending on current relax state. Initially the relax
8956 state will correspond to a short jump and we return 1, because
8957 the variable part of the frag (the branch offset) is one byte
8958 long. However, we can relax a section more than once and in that
8959 case we must either set fr_subtype back to the unrelaxed state,
8960 or return the value for the appropriate branch. */
8961 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8964 /* Called after relax() is finished.
8966 In: Address of frag.
8967 fr_type == rs_machine_dependent.
8968 fr_subtype is what the address relaxed to.
8970 Out: Any fixSs and constants are set up.
8971 Caller will turn frag into a ".space 0". */
8974 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8977 unsigned char *opcode
;
8978 unsigned char *where_to_put_displacement
= NULL
;
8979 offsetT target_address
;
8980 offsetT opcode_address
;
8981 unsigned int extension
= 0;
8982 offsetT displacement_from_opcode_start
;
8984 opcode
= (unsigned char *) fragP
->fr_opcode
;
8986 /* Address we want to reach in file space. */
8987 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8989 /* Address opcode resides at in file space. */
8990 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8992 /* Displacement from opcode start to fill into instruction. */
8993 displacement_from_opcode_start
= target_address
- opcode_address
;
8995 if ((fragP
->fr_subtype
& BIG
) == 0)
8997 /* Don't have to change opcode. */
8998 extension
= 1; /* 1 opcode + 1 displacement */
8999 where_to_put_displacement
= &opcode
[1];
9003 if (no_cond_jump_promotion
9004 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9005 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9006 _("long jump required"));
9008 switch (fragP
->fr_subtype
)
9010 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9011 extension
= 4; /* 1 opcode + 4 displacement */
9013 where_to_put_displacement
= &opcode
[1];
9016 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9017 extension
= 2; /* 1 opcode + 2 displacement */
9019 where_to_put_displacement
= &opcode
[1];
9022 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9023 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9024 extension
= 5; /* 2 opcode + 4 displacement */
9025 opcode
[1] = opcode
[0] + 0x10;
9026 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9027 where_to_put_displacement
= &opcode
[2];
9030 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9031 extension
= 3; /* 2 opcode + 2 displacement */
9032 opcode
[1] = opcode
[0] + 0x10;
9033 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9034 where_to_put_displacement
= &opcode
[2];
9037 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9042 where_to_put_displacement
= &opcode
[3];
9046 BAD_CASE (fragP
->fr_subtype
);
9051 /* If size if less then four we are sure that the operand fits,
9052 but if it's 4, then it could be that the displacement is larger
9054 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9056 && ((addressT
) (displacement_from_opcode_start
- extension
9057 + ((addressT
) 1 << 31))
9058 > (((addressT
) 2 << 31) - 1)))
9060 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9061 _("jump target out of range"));
9062 /* Make us emit 0. */
9063 displacement_from_opcode_start
= extension
;
9065 /* Now put displacement after opcode. */
9066 md_number_to_chars ((char *) where_to_put_displacement
,
9067 (valueT
) (displacement_from_opcode_start
- extension
),
9068 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9069 fragP
->fr_fix
+= extension
;
9072 /* Apply a fixup (fixP) to segment data, once it has been determined
9073 by our caller that we have all the info we need to fix it up.
9075 Parameter valP is the pointer to the value of the bits.
9077 On the 386, immediates, displacements, and data pointers are all in
9078 the same (little-endian) format, so we don't need to care about which
9082 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9084 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9085 valueT value
= *valP
;
9087 #if !defined (TE_Mach)
9090 switch (fixP
->fx_r_type
)
9096 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9099 case BFD_RELOC_X86_64_32S
:
9100 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9103 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9106 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9111 if (fixP
->fx_addsy
!= NULL
9112 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9113 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9114 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9115 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9116 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9117 && !use_rela_relocations
)
9119 /* This is a hack. There should be a better way to handle this.
9120 This covers for the fact that bfd_install_relocation will
9121 subtract the current location (for partial_inplace, PC relative
9122 relocations); see more below. */
9126 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9129 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9131 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9134 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9137 || (symbol_section_p (fixP
->fx_addsy
)
9138 && sym_seg
!= absolute_section
))
9139 && !generic_force_reloc (fixP
))
9141 /* Yes, we add the values in twice. This is because
9142 bfd_install_relocation subtracts them out again. I think
9143 bfd_install_relocation is broken, but I don't dare change
9145 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9149 #if defined (OBJ_COFF) && defined (TE_PE)
9150 /* For some reason, the PE format does not store a
9151 section address offset for a PC relative symbol. */
9152 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9153 || S_IS_WEAK (fixP
->fx_addsy
))
9154 value
+= md_pcrel_from (fixP
);
9157 #if defined (OBJ_COFF) && defined (TE_PE)
9158 if (fixP
->fx_addsy
!= NULL
9159 && S_IS_WEAK (fixP
->fx_addsy
)
9160 /* PR 16858: Do not modify weak function references. */
9161 && ! fixP
->fx_pcrel
)
9163 #if !defined (TE_PEP)
9164 /* For x86 PE weak function symbols are neither PC-relative
9165 nor do they set S_IS_FUNCTION. So the only reliable way
9166 to detect them is to check the flags of their containing
9168 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9169 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9173 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9177 /* Fix a few things - the dynamic linker expects certain values here,
9178 and we must not disappoint it. */
9179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9180 if (IS_ELF
&& fixP
->fx_addsy
)
9181 switch (fixP
->fx_r_type
)
9183 case BFD_RELOC_386_PLT32
:
9184 case BFD_RELOC_X86_64_PLT32
:
9185 case BFD_RELOC_X86_64_PLT32_BND
:
9186 /* Make the jump instruction point to the address of the operand. At
9187 runtime we merely add the offset to the actual PLT entry. */
9191 case BFD_RELOC_386_TLS_GD
:
9192 case BFD_RELOC_386_TLS_LDM
:
9193 case BFD_RELOC_386_TLS_IE_32
:
9194 case BFD_RELOC_386_TLS_IE
:
9195 case BFD_RELOC_386_TLS_GOTIE
:
9196 case BFD_RELOC_386_TLS_GOTDESC
:
9197 case BFD_RELOC_X86_64_TLSGD
:
9198 case BFD_RELOC_X86_64_TLSLD
:
9199 case BFD_RELOC_X86_64_GOTTPOFF
:
9200 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9201 value
= 0; /* Fully resolved at runtime. No addend. */
9203 case BFD_RELOC_386_TLS_LE
:
9204 case BFD_RELOC_386_TLS_LDO_32
:
9205 case BFD_RELOC_386_TLS_LE_32
:
9206 case BFD_RELOC_X86_64_DTPOFF32
:
9207 case BFD_RELOC_X86_64_DTPOFF64
:
9208 case BFD_RELOC_X86_64_TPOFF32
:
9209 case BFD_RELOC_X86_64_TPOFF64
:
9210 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9213 case BFD_RELOC_386_TLS_DESC_CALL
:
9214 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9215 value
= 0; /* Fully resolved at runtime. No addend. */
9216 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9220 case BFD_RELOC_386_GOT32
:
9221 case BFD_RELOC_X86_64_GOT32
:
9222 value
= 0; /* Fully resolved at runtime. No addend. */
9225 case BFD_RELOC_VTABLE_INHERIT
:
9226 case BFD_RELOC_VTABLE_ENTRY
:
9233 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9235 #endif /* !defined (TE_Mach) */
9237 /* Are we finished with this relocation now? */
9238 if (fixP
->fx_addsy
== NULL
)
9240 #if defined (OBJ_COFF) && defined (TE_PE)
9241 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9244 /* Remember value for tc_gen_reloc. */
9245 fixP
->fx_addnumber
= value
;
9246 /* Clear out the frag for now. */
9250 else if (use_rela_relocations
)
9252 fixP
->fx_no_overflow
= 1;
9253 /* Remember value for tc_gen_reloc. */
9254 fixP
->fx_addnumber
= value
;
9258 md_number_to_chars (p
, value
, fixP
->fx_size
);
9262 md_atof (int type
, char *litP
, int *sizeP
)
9264 /* This outputs the LITTLENUMs in REVERSE order;
9265 in accord with the bigendian 386. */
9266 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9269 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9272 output_invalid (int c
)
9275 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9278 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9279 "(0x%x)", (unsigned char) c
);
9280 return output_invalid_buf
;
9283 /* REG_STRING starts *before* REGISTER_PREFIX. */
9285 static const reg_entry
*
9286 parse_real_register (char *reg_string
, char **end_op
)
9288 char *s
= reg_string
;
9290 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9293 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9294 if (*s
== REGISTER_PREFIX
)
9297 if (is_space_char (*s
))
9301 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9303 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9304 return (const reg_entry
*) NULL
;
9308 /* For naked regs, make sure that we are not dealing with an identifier.
9309 This prevents confusing an identifier like `eax_var' with register
9311 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9312 return (const reg_entry
*) NULL
;
9316 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9318 /* Handle floating point regs, allowing spaces in the (i) part. */
9319 if (r
== i386_regtab
/* %st is first entry of table */)
9321 if (is_space_char (*s
))
9326 if (is_space_char (*s
))
9328 if (*s
>= '0' && *s
<= '7')
9332 if (is_space_char (*s
))
9337 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9342 /* We have "%st(" then garbage. */
9343 return (const reg_entry
*) NULL
;
9347 if (r
== NULL
|| allow_pseudo_reg
)
9350 if (operand_type_all_zero (&r
->reg_type
))
9351 return (const reg_entry
*) NULL
;
9353 if ((r
->reg_type
.bitfield
.reg32
9354 || r
->reg_type
.bitfield
.sreg3
9355 || r
->reg_type
.bitfield
.control
9356 || r
->reg_type
.bitfield
.debug
9357 || r
->reg_type
.bitfield
.test
)
9358 && !cpu_arch_flags
.bitfield
.cpui386
)
9359 return (const reg_entry
*) NULL
;
9361 if (r
->reg_type
.bitfield
.floatreg
9362 && !cpu_arch_flags
.bitfield
.cpu8087
9363 && !cpu_arch_flags
.bitfield
.cpu287
9364 && !cpu_arch_flags
.bitfield
.cpu387
)
9365 return (const reg_entry
*) NULL
;
9367 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9368 return (const reg_entry
*) NULL
;
9370 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9371 return (const reg_entry
*) NULL
;
9373 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9374 return (const reg_entry
*) NULL
;
9376 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9377 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9378 return (const reg_entry
*) NULL
;
9380 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9381 if (!allow_index_reg
9382 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9383 return (const reg_entry
*) NULL
;
9385 /* Upper 16 vector register is only available with VREX in 64bit
9387 if ((r
->reg_flags
& RegVRex
))
9389 if (!cpu_arch_flags
.bitfield
.cpuvrex
9390 || flag_code
!= CODE_64BIT
)
9391 return (const reg_entry
*) NULL
;
9396 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9397 || r
->reg_type
.bitfield
.reg64
)
9398 && (!cpu_arch_flags
.bitfield
.cpulm
9399 || !operand_type_equal (&r
->reg_type
, &control
))
9400 && flag_code
!= CODE_64BIT
)
9401 return (const reg_entry
*) NULL
;
9403 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9404 return (const reg_entry
*) NULL
;
9409 /* REG_STRING starts *before* REGISTER_PREFIX. */
9411 static const reg_entry
*
9412 parse_register (char *reg_string
, char **end_op
)
9416 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9417 r
= parse_real_register (reg_string
, end_op
);
9422 char *save
= input_line_pointer
;
9426 input_line_pointer
= reg_string
;
9427 c
= get_symbol_end ();
9428 symbolP
= symbol_find (reg_string
);
9429 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9431 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9433 know (e
->X_op
== O_register
);
9434 know (e
->X_add_number
>= 0
9435 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9436 r
= i386_regtab
+ e
->X_add_number
;
9437 if ((r
->reg_flags
& RegVRex
))
9439 *end_op
= input_line_pointer
;
9441 *input_line_pointer
= c
;
9442 input_line_pointer
= save
;
9448 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9451 char *end
= input_line_pointer
;
9454 r
= parse_register (name
, &input_line_pointer
);
9455 if (r
&& end
<= input_line_pointer
)
9457 *nextcharP
= *input_line_pointer
;
9458 *input_line_pointer
= 0;
9459 e
->X_op
= O_register
;
9460 e
->X_add_number
= r
- i386_regtab
;
9463 input_line_pointer
= end
;
9465 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9469 md_operand (expressionS
*e
)
9474 switch (*input_line_pointer
)
9476 case REGISTER_PREFIX
:
9477 r
= parse_real_register (input_line_pointer
, &end
);
9480 e
->X_op
= O_register
;
9481 e
->X_add_number
= r
- i386_regtab
;
9482 input_line_pointer
= end
;
9487 gas_assert (intel_syntax
);
9488 end
= input_line_pointer
++;
9490 if (*input_line_pointer
== ']')
9492 ++input_line_pointer
;
9493 e
->X_op_symbol
= make_expr_symbol (e
);
9494 e
->X_add_symbol
= NULL
;
9495 e
->X_add_number
= 0;
9501 input_line_pointer
= end
;
9508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9509 const char *md_shortopts
= "kVQ:sqn";
9511 const char *md_shortopts
= "qn";
9514 #define OPTION_32 (OPTION_MD_BASE + 0)
9515 #define OPTION_64 (OPTION_MD_BASE + 1)
9516 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9517 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9518 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9519 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9520 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9521 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9522 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9523 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9524 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9525 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9526 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9527 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9528 #define OPTION_X32 (OPTION_MD_BASE + 14)
9529 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9530 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9531 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9532 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9534 struct option md_longopts
[] =
9536 {"32", no_argument
, NULL
, OPTION_32
},
9537 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9538 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9539 {"64", no_argument
, NULL
, OPTION_64
},
9541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9542 {"x32", no_argument
, NULL
, OPTION_X32
},
9544 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9545 {"march", required_argument
, NULL
, OPTION_MARCH
},
9546 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9547 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9548 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9549 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9550 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9551 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9552 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9553 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9554 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9555 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9556 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9557 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9558 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9559 # if defined (TE_PE) || defined (TE_PEP)
9560 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9562 {NULL
, no_argument
, NULL
, 0}
9564 size_t md_longopts_size
= sizeof (md_longopts
);
9567 md_parse_option (int c
, char *arg
)
9575 optimize_align_code
= 0;
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9583 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9584 should be emitted or not. FIXME: Not implemented. */
9588 /* -V: SVR4 argument to print version ID. */
9590 print_version_id ();
9593 /* -k: Ignore for FreeBSD compatibility. */
9598 /* -s: On i386 Solaris, this tells the native assembler to use
9599 .stab instead of .stab.excl. We always use .stab anyhow. */
9602 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9603 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9606 const char **list
, **l
;
9608 list
= bfd_target_list ();
9609 for (l
= list
; *l
!= NULL
; l
++)
9610 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9611 || strcmp (*l
, "coff-x86-64") == 0
9612 || strcmp (*l
, "pe-x86-64") == 0
9613 || strcmp (*l
, "pei-x86-64") == 0
9614 || strcmp (*l
, "mach-o-x86-64") == 0)
9616 default_arch
= "x86_64";
9620 as_fatal (_("no compiled in support for x86_64"));
9626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9630 const char **list
, **l
;
9632 list
= bfd_target_list ();
9633 for (l
= list
; *l
!= NULL
; l
++)
9634 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9636 default_arch
= "x86_64:32";
9640 as_fatal (_("no compiled in support for 32bit x86_64"));
9644 as_fatal (_("32bit x86_64 is only supported for ELF"));
9649 default_arch
= "i386";
9653 #ifdef SVR4_COMMENT_CHARS
9658 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9660 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9664 i386_comment_chars
= n
;
9670 arch
= xstrdup (arg
);
9674 as_fatal (_("invalid -march= option: `%s'"), arg
);
9675 next
= strchr (arch
, '+');
9678 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9680 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9683 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9686 cpu_arch_name
= cpu_arch
[j
].name
;
9687 cpu_sub_arch_name
= NULL
;
9688 cpu_arch_flags
= cpu_arch
[j
].flags
;
9689 cpu_arch_isa
= cpu_arch
[j
].type
;
9690 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9691 if (!cpu_arch_tune_set
)
9693 cpu_arch_tune
= cpu_arch_isa
;
9694 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9698 else if (*cpu_arch
[j
].name
== '.'
9699 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9701 /* ISA entension. */
9702 i386_cpu_flags flags
;
9704 if (!cpu_arch
[j
].negated
)
9705 flags
= cpu_flags_or (cpu_arch_flags
,
9708 flags
= cpu_flags_and_not (cpu_arch_flags
,
9710 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9712 if (cpu_sub_arch_name
)
9714 char *name
= cpu_sub_arch_name
;
9715 cpu_sub_arch_name
= concat (name
,
9717 (const char *) NULL
);
9721 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9722 cpu_arch_flags
= flags
;
9723 cpu_arch_isa_flags
= flags
;
9729 if (j
>= ARRAY_SIZE (cpu_arch
))
9730 as_fatal (_("invalid -march= option: `%s'"), arg
);
9734 while (next
!= NULL
);
9739 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9740 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9742 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9744 cpu_arch_tune_set
= 1;
9745 cpu_arch_tune
= cpu_arch
[j
].type
;
9746 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9750 if (j
>= ARRAY_SIZE (cpu_arch
))
9751 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9754 case OPTION_MMNEMONIC
:
9755 if (strcasecmp (arg
, "att") == 0)
9757 else if (strcasecmp (arg
, "intel") == 0)
9760 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9763 case OPTION_MSYNTAX
:
9764 if (strcasecmp (arg
, "att") == 0)
9766 else if (strcasecmp (arg
, "intel") == 0)
9769 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9772 case OPTION_MINDEX_REG
:
9773 allow_index_reg
= 1;
9776 case OPTION_MNAKED_REG
:
9777 allow_naked_reg
= 1;
9780 case OPTION_MOLD_GCC
:
9784 case OPTION_MSSE2AVX
:
9788 case OPTION_MSSE_CHECK
:
9789 if (strcasecmp (arg
, "error") == 0)
9790 sse_check
= check_error
;
9791 else if (strcasecmp (arg
, "warning") == 0)
9792 sse_check
= check_warning
;
9793 else if (strcasecmp (arg
, "none") == 0)
9794 sse_check
= check_none
;
9796 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9799 case OPTION_MOPERAND_CHECK
:
9800 if (strcasecmp (arg
, "error") == 0)
9801 operand_check
= check_error
;
9802 else if (strcasecmp (arg
, "warning") == 0)
9803 operand_check
= check_warning
;
9804 else if (strcasecmp (arg
, "none") == 0)
9805 operand_check
= check_none
;
9807 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9810 case OPTION_MAVXSCALAR
:
9811 if (strcasecmp (arg
, "128") == 0)
9813 else if (strcasecmp (arg
, "256") == 0)
9816 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9819 case OPTION_MADD_BND_PREFIX
:
9823 case OPTION_MEVEXLIG
:
9824 if (strcmp (arg
, "128") == 0)
9826 else if (strcmp (arg
, "256") == 0)
9828 else if (strcmp (arg
, "512") == 0)
9831 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9834 case OPTION_MEVEXWIG
:
9835 if (strcmp (arg
, "0") == 0)
9837 else if (strcmp (arg
, "1") == 0)
9840 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9843 # if defined (TE_PE) || defined (TE_PEP)
9844 case OPTION_MBIG_OBJ
:
9855 #define MESSAGE_TEMPLATE \
9859 show_arch (FILE *stream
, int ext
, int check
)
9861 static char message
[] = MESSAGE_TEMPLATE
;
9862 char *start
= message
+ 27;
9864 int size
= sizeof (MESSAGE_TEMPLATE
);
9871 left
= size
- (start
- message
);
9872 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9874 /* Should it be skipped? */
9875 if (cpu_arch
[j
].skip
)
9878 name
= cpu_arch
[j
].name
;
9879 len
= cpu_arch
[j
].len
;
9882 /* It is an extension. Skip if we aren't asked to show it. */
9893 /* It is an processor. Skip if we show only extension. */
9896 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9898 /* It is an impossible processor - skip. */
9902 /* Reserve 2 spaces for ", " or ",\0" */
9905 /* Check if there is any room. */
9913 p
= mempcpy (p
, name
, len
);
9917 /* Output the current message now and start a new one. */
9920 fprintf (stream
, "%s\n", message
);
9922 left
= size
- (start
- message
) - len
- 2;
9924 gas_assert (left
>= 0);
9926 p
= mempcpy (p
, name
, len
);
9931 fprintf (stream
, "%s\n", message
);
9935 md_show_usage (FILE *stream
)
9937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9938 fprintf (stream
, _("\
9940 -V print assembler version number\n\
9943 fprintf (stream
, _("\
9944 -n Do not optimize code alignment\n\
9945 -q quieten some warnings\n"));
9946 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9947 fprintf (stream
, _("\
9950 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9951 || defined (TE_PE) || defined (TE_PEP))
9952 fprintf (stream
, _("\
9953 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9955 #ifdef SVR4_COMMENT_CHARS
9956 fprintf (stream
, _("\
9957 --divide do not treat `/' as a comment character\n"));
9959 fprintf (stream
, _("\
9960 --divide ignored\n"));
9962 fprintf (stream
, _("\
9963 -march=CPU[,+EXTENSION...]\n\
9964 generate code for CPU and EXTENSION, CPU is one of:\n"));
9965 show_arch (stream
, 0, 1);
9966 fprintf (stream
, _("\
9967 EXTENSION is combination of:\n"));
9968 show_arch (stream
, 1, 0);
9969 fprintf (stream
, _("\
9970 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9971 show_arch (stream
, 0, 0);
9972 fprintf (stream
, _("\
9973 -msse2avx encode SSE instructions with VEX prefix\n"));
9974 fprintf (stream
, _("\
9975 -msse-check=[none|error|warning]\n\
9976 check SSE instructions\n"));
9977 fprintf (stream
, _("\
9978 -moperand-check=[none|error|warning]\n\
9979 check operand combinations for validity\n"));
9980 fprintf (stream
, _("\
9981 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9983 fprintf (stream
, _("\
9984 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9986 fprintf (stream
, _("\
9987 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9988 for EVEX.W bit ignored instructions\n"));
9989 fprintf (stream
, _("\
9990 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9991 fprintf (stream
, _("\
9992 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9993 fprintf (stream
, _("\
9994 -mindex-reg support pseudo index registers\n"));
9995 fprintf (stream
, _("\
9996 -mnaked-reg don't require `%%' prefix for registers\n"));
9997 fprintf (stream
, _("\
9998 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9999 fprintf (stream
, _("\
10000 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10001 # if defined (TE_PE) || defined (TE_PEP)
10002 fprintf (stream
, _("\
10003 -mbig-obj generate big object files\n"));
10007 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10009 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10011 /* Pick the target format to use. */
10014 i386_target_format (void)
10016 if (!strncmp (default_arch
, "x86_64", 6))
10018 update_code_flag (CODE_64BIT
, 1);
10019 if (default_arch
[6] == '\0')
10020 x86_elf_abi
= X86_64_ABI
;
10022 x86_elf_abi
= X86_64_X32_ABI
;
10024 else if (!strcmp (default_arch
, "i386"))
10025 update_code_flag (CODE_32BIT
, 1);
10027 as_fatal (_("unknown architecture"));
10029 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10030 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10031 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10032 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10034 switch (OUTPUT_FLAVOR
)
10036 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10037 case bfd_target_aout_flavour
:
10038 return AOUT_TARGET_FORMAT
;
10040 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10041 # if defined (TE_PE) || defined (TE_PEP)
10042 case bfd_target_coff_flavour
:
10043 if (flag_code
== CODE_64BIT
)
10044 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10047 # elif defined (TE_GO32)
10048 case bfd_target_coff_flavour
:
10049 return "coff-go32";
10051 case bfd_target_coff_flavour
:
10052 return "coff-i386";
10055 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10056 case bfd_target_elf_flavour
:
10058 const char *format
;
10060 switch (x86_elf_abi
)
10063 format
= ELF_TARGET_FORMAT
;
10066 use_rela_relocations
= 1;
10068 format
= ELF_TARGET_FORMAT64
;
10070 case X86_64_X32_ABI
:
10071 use_rela_relocations
= 1;
10073 disallow_64bit_reloc
= 1;
10074 format
= ELF_TARGET_FORMAT32
;
10077 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10079 if (x86_elf_abi
!= X86_64_ABI
)
10080 as_fatal (_("Intel L1OM is 64bit only"));
10081 return ELF_TARGET_L1OM_FORMAT
;
10083 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10085 if (x86_elf_abi
!= X86_64_ABI
)
10086 as_fatal (_("Intel K1OM is 64bit only"));
10087 return ELF_TARGET_K1OM_FORMAT
;
10093 #if defined (OBJ_MACH_O)
10094 case bfd_target_mach_o_flavour
:
10095 if (flag_code
== CODE_64BIT
)
10097 use_rela_relocations
= 1;
10099 return "mach-o-x86-64";
10102 return "mach-o-i386";
10110 #endif /* OBJ_MAYBE_ more than one */
10112 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10114 i386_elf_emit_arch_note (void)
10116 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10119 asection
*seg
= now_seg
;
10120 subsegT subseg
= now_subseg
;
10121 Elf_Internal_Note i_note
;
10122 Elf_External_Note e_note
;
10123 asection
*note_secp
;
10126 /* Create the .note section. */
10127 note_secp
= subseg_new (".note", 0);
10128 bfd_set_section_flags (stdoutput
,
10130 SEC_HAS_CONTENTS
| SEC_READONLY
);
10132 /* Process the arch string. */
10133 len
= strlen (cpu_arch_name
);
10135 i_note
.namesz
= len
+ 1;
10137 i_note
.type
= NT_ARCH
;
10138 p
= frag_more (sizeof (e_note
.namesz
));
10139 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10140 p
= frag_more (sizeof (e_note
.descsz
));
10141 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10142 p
= frag_more (sizeof (e_note
.type
));
10143 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10144 p
= frag_more (len
+ 1);
10145 strcpy (p
, cpu_arch_name
);
10147 frag_align (2, 0, 0);
10149 subseg_set (seg
, subseg
);
10155 md_undefined_symbol (char *name
)
10157 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10158 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10159 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10160 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10164 if (symbol_find (name
))
10165 as_bad (_("GOT already in symbol table"));
10166 GOT_symbol
= symbol_new (name
, undefined_section
,
10167 (valueT
) 0, &zero_address_frag
);
10174 /* Round up a section size to the appropriate boundary. */
10177 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10179 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10180 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10182 /* For a.out, force the section size to be aligned. If we don't do
10183 this, BFD will align it for us, but it will not write out the
10184 final bytes of the section. This may be a bug in BFD, but it is
10185 easier to fix it here since that is how the other a.out targets
10189 align
= bfd_get_section_alignment (stdoutput
, segment
);
10190 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10197 /* On the i386, PC-relative offsets are relative to the start of the
10198 next instruction. That is, the address of the offset, plus its
10199 size, since the offset is always the last part of the insn. */
10202 md_pcrel_from (fixS
*fixP
)
10204 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10210 s_bss (int ignore ATTRIBUTE_UNUSED
)
10214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10216 obj_elf_section_change_hook ();
10218 temp
= get_absolute_expression ();
10219 subseg_set (bss_section
, (subsegT
) temp
);
10220 demand_empty_rest_of_line ();
10226 i386_validate_fix (fixS
*fixp
)
10228 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10230 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10234 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10239 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10241 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10243 fixp
->fx_subsy
= 0;
10248 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10251 bfd_reloc_code_real_type code
;
10253 switch (fixp
->fx_r_type
)
10255 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10256 case BFD_RELOC_SIZE32
:
10257 case BFD_RELOC_SIZE64
:
10258 if (S_IS_DEFINED (fixp
->fx_addsy
)
10259 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10261 /* Resolve size relocation against local symbol to size of
10262 the symbol plus addend. */
10263 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10264 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10265 && !fits_in_unsigned_long (value
))
10266 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10267 _("symbol size computation overflow"));
10268 fixp
->fx_addsy
= NULL
;
10269 fixp
->fx_subsy
= NULL
;
10270 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10275 case BFD_RELOC_X86_64_PLT32
:
10276 case BFD_RELOC_X86_64_PLT32_BND
:
10277 case BFD_RELOC_X86_64_GOT32
:
10278 case BFD_RELOC_X86_64_GOTPCREL
:
10279 case BFD_RELOC_386_PLT32
:
10280 case BFD_RELOC_386_GOT32
:
10281 case BFD_RELOC_386_GOTOFF
:
10282 case BFD_RELOC_386_GOTPC
:
10283 case BFD_RELOC_386_TLS_GD
:
10284 case BFD_RELOC_386_TLS_LDM
:
10285 case BFD_RELOC_386_TLS_LDO_32
:
10286 case BFD_RELOC_386_TLS_IE_32
:
10287 case BFD_RELOC_386_TLS_IE
:
10288 case BFD_RELOC_386_TLS_GOTIE
:
10289 case BFD_RELOC_386_TLS_LE_32
:
10290 case BFD_RELOC_386_TLS_LE
:
10291 case BFD_RELOC_386_TLS_GOTDESC
:
10292 case BFD_RELOC_386_TLS_DESC_CALL
:
10293 case BFD_RELOC_X86_64_TLSGD
:
10294 case BFD_RELOC_X86_64_TLSLD
:
10295 case BFD_RELOC_X86_64_DTPOFF32
:
10296 case BFD_RELOC_X86_64_DTPOFF64
:
10297 case BFD_RELOC_X86_64_GOTTPOFF
:
10298 case BFD_RELOC_X86_64_TPOFF32
:
10299 case BFD_RELOC_X86_64_TPOFF64
:
10300 case BFD_RELOC_X86_64_GOTOFF64
:
10301 case BFD_RELOC_X86_64_GOTPC32
:
10302 case BFD_RELOC_X86_64_GOT64
:
10303 case BFD_RELOC_X86_64_GOTPCREL64
:
10304 case BFD_RELOC_X86_64_GOTPC64
:
10305 case BFD_RELOC_X86_64_GOTPLT64
:
10306 case BFD_RELOC_X86_64_PLTOFF64
:
10307 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10308 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10309 case BFD_RELOC_RVA
:
10310 case BFD_RELOC_VTABLE_ENTRY
:
10311 case BFD_RELOC_VTABLE_INHERIT
:
10313 case BFD_RELOC_32_SECREL
:
10315 code
= fixp
->fx_r_type
;
10317 case BFD_RELOC_X86_64_32S
:
10318 if (!fixp
->fx_pcrel
)
10320 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10321 code
= fixp
->fx_r_type
;
10325 if (fixp
->fx_pcrel
)
10327 switch (fixp
->fx_size
)
10330 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10331 _("can not do %d byte pc-relative relocation"),
10333 code
= BFD_RELOC_32_PCREL
;
10335 case 1: code
= BFD_RELOC_8_PCREL
; break;
10336 case 2: code
= BFD_RELOC_16_PCREL
; break;
10338 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10339 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10342 case 8: code
= BFD_RELOC_64_PCREL
; break;
10348 switch (fixp
->fx_size
)
10351 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10352 _("can not do %d byte relocation"),
10354 code
= BFD_RELOC_32
;
10356 case 1: code
= BFD_RELOC_8
; break;
10357 case 2: code
= BFD_RELOC_16
; break;
10358 case 4: code
= BFD_RELOC_32
; break;
10360 case 8: code
= BFD_RELOC_64
; break;
10367 if ((code
== BFD_RELOC_32
10368 || code
== BFD_RELOC_32_PCREL
10369 || code
== BFD_RELOC_X86_64_32S
)
10371 && fixp
->fx_addsy
== GOT_symbol
)
10374 code
= BFD_RELOC_386_GOTPC
;
10376 code
= BFD_RELOC_X86_64_GOTPC32
;
10378 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10380 && fixp
->fx_addsy
== GOT_symbol
)
10382 code
= BFD_RELOC_X86_64_GOTPC64
;
10385 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10386 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10387 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10389 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10391 if (!use_rela_relocations
)
10393 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10394 vtable entry to be used in the relocation's section offset. */
10395 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10396 rel
->address
= fixp
->fx_offset
;
10397 #if defined (OBJ_COFF) && defined (TE_PE)
10398 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10399 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10404 /* Use the rela in 64bit mode. */
10407 if (disallow_64bit_reloc
)
10410 case BFD_RELOC_X86_64_DTPOFF64
:
10411 case BFD_RELOC_X86_64_TPOFF64
:
10412 case BFD_RELOC_64_PCREL
:
10413 case BFD_RELOC_X86_64_GOTOFF64
:
10414 case BFD_RELOC_X86_64_GOT64
:
10415 case BFD_RELOC_X86_64_GOTPCREL64
:
10416 case BFD_RELOC_X86_64_GOTPC64
:
10417 case BFD_RELOC_X86_64_GOTPLT64
:
10418 case BFD_RELOC_X86_64_PLTOFF64
:
10419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10420 _("cannot represent relocation type %s in x32 mode"),
10421 bfd_get_reloc_code_name (code
));
10427 if (!fixp
->fx_pcrel
)
10428 rel
->addend
= fixp
->fx_offset
;
10432 case BFD_RELOC_X86_64_PLT32
:
10433 case BFD_RELOC_X86_64_PLT32_BND
:
10434 case BFD_RELOC_X86_64_GOT32
:
10435 case BFD_RELOC_X86_64_GOTPCREL
:
10436 case BFD_RELOC_X86_64_TLSGD
:
10437 case BFD_RELOC_X86_64_TLSLD
:
10438 case BFD_RELOC_X86_64_GOTTPOFF
:
10439 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10440 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10441 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10444 rel
->addend
= (section
->vma
10446 + fixp
->fx_addnumber
10447 + md_pcrel_from (fixp
));
10452 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10453 if (rel
->howto
== NULL
)
10455 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10456 _("cannot represent relocation type %s"),
10457 bfd_get_reloc_code_name (code
));
10458 /* Set howto to a garbage value so that we can keep going. */
10459 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10460 gas_assert (rel
->howto
!= NULL
);
10466 #include "tc-i386-intel.c"
10469 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10471 int saved_naked_reg
;
10472 char saved_register_dot
;
10474 saved_naked_reg
= allow_naked_reg
;
10475 allow_naked_reg
= 1;
10476 saved_register_dot
= register_chars
['.'];
10477 register_chars
['.'] = '.';
10478 allow_pseudo_reg
= 1;
10479 expression_and_evaluate (exp
);
10480 allow_pseudo_reg
= 0;
10481 register_chars
['.'] = saved_register_dot
;
10482 allow_naked_reg
= saved_naked_reg
;
10484 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10486 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10488 exp
->X_op
= O_constant
;
10489 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10490 .dw2_regnum
[flag_code
>> 1];
10493 exp
->X_op
= O_illegal
;
10498 tc_x86_frame_initial_instructions (void)
10500 static unsigned int sp_regno
[2];
10502 if (!sp_regno
[flag_code
>> 1])
10504 char *saved_input
= input_line_pointer
;
10505 char sp
[][4] = {"esp", "rsp"};
10508 input_line_pointer
= sp
[flag_code
>> 1];
10509 tc_x86_parse_to_dw2regnum (&exp
);
10510 gas_assert (exp
.X_op
== O_constant
);
10511 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10512 input_line_pointer
= saved_input
;
10515 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10516 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10520 x86_dwarf2_addr_size (void)
10522 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10523 if (x86_elf_abi
== X86_64_X32_ABI
)
10526 return bfd_arch_bits_per_address (stdoutput
) / 8;
10530 i386_elf_section_type (const char *str
, size_t len
)
10532 if (flag_code
== CODE_64BIT
10533 && len
== sizeof ("unwind") - 1
10534 && strncmp (str
, "unwind", 6) == 0)
10535 return SHT_X86_64_UNWIND
;
10542 i386_solaris_fix_up_eh_frame (segT sec
)
10544 if (flag_code
== CODE_64BIT
)
10545 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10551 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10555 exp
.X_op
= O_secrel
;
10556 exp
.X_add_symbol
= symbol
;
10557 exp
.X_add_number
= 0;
10558 emit_expr (&exp
, size
);
10562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10563 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10566 x86_64_section_letter (int letter
, char **ptr_msg
)
10568 if (flag_code
== CODE_64BIT
)
10571 return SHF_X86_64_LARGE
;
10573 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10576 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10581 x86_64_section_word (char *str
, size_t len
)
10583 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10584 return SHF_X86_64_LARGE
;
10590 handle_large_common (int small ATTRIBUTE_UNUSED
)
10592 if (flag_code
!= CODE_64BIT
)
10594 s_comm_internal (0, elf_common_parse
);
10595 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10599 static segT lbss_section
;
10600 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10601 asection
*saved_bss_section
= bss_section
;
10603 if (lbss_section
== NULL
)
10605 flagword applicable
;
10606 segT seg
= now_seg
;
10607 subsegT subseg
= now_subseg
;
10609 /* The .lbss section is for local .largecomm symbols. */
10610 lbss_section
= subseg_new (".lbss", 0);
10611 applicable
= bfd_applicable_section_flags (stdoutput
);
10612 bfd_set_section_flags (stdoutput
, lbss_section
,
10613 applicable
& SEC_ALLOC
);
10614 seg_info (lbss_section
)->bss
= 1;
10616 subseg_set (seg
, subseg
);
10619 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10620 bss_section
= lbss_section
;
10622 s_comm_internal (0, elf_common_parse
);
10624 elf_com_section_ptr
= saved_com_section_ptr
;
10625 bss_section
= saved_bss_section
;
10628 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */