1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
66 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
67 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
69 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
71 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
72 static int smallest_imm_type
PARAMS ((offsetT
));
73 static offsetT offset_in_range
PARAMS ((offsetT
, int));
74 static int add_prefix
PARAMS ((unsigned int));
75 static void set_code_flag
PARAMS ((int));
76 static void set_16bit_gcc_code_flag
PARAMS ((int));
77 static void set_intel_syntax
PARAMS ((int));
78 static void set_cpu_arch
PARAMS ((int));
80 static void pe_directive_secrel
PARAMS ((int));
82 static char *output_invalid
PARAMS ((int c
));
83 static int i386_operand
PARAMS ((char *operand_string
));
84 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
85 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
87 static char *parse_insn
PARAMS ((char *, char *));
88 static char *parse_operands
PARAMS ((char *, const char *));
89 static void swap_operands
PARAMS ((void));
90 static void optimize_imm
PARAMS ((void));
91 static void optimize_disp
PARAMS ((void));
92 static int match_template
PARAMS ((void));
93 static int check_string
PARAMS ((void));
94 static int process_suffix
PARAMS ((void));
95 static int check_byte_reg
PARAMS ((void));
96 static int check_long_reg
PARAMS ((void));
97 static int check_qword_reg
PARAMS ((void));
98 static int check_word_reg
PARAMS ((void));
99 static int finalize_imm
PARAMS ((void));
100 static int process_operands
PARAMS ((void));
101 static const seg_entry
*build_modrm_byte
PARAMS ((void));
102 static void output_insn
PARAMS ((void));
103 static void output_branch
PARAMS ((void));
104 static void output_jump
PARAMS ((void));
105 static void output_interseg_jump
PARAMS ((void));
106 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
107 offsetT insn_start_off
));
108 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
111 static void s_bss
PARAMS ((int));
114 static const char *default_arch
= DEFAULT_ARCH
;
116 /* 'md_assemble ()' gathers together information and puts it into a
123 const reg_entry
*regs
;
128 /* TM holds the template for the insn were currently assembling. */
131 /* SUFFIX holds the instruction mnemonic suffix if given.
132 (e.g. 'l' for 'movl') */
135 /* OPERANDS gives the number of given operands. */
136 unsigned int operands
;
138 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
139 of given register, displacement, memory operands and immediate
141 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
143 /* TYPES [i] is the type (see above #defines) which tells us how to
144 use OP[i] for the corresponding operand. */
145 unsigned int types
[MAX_OPERANDS
];
147 /* Displacement expression, immediate expression, or register for each
149 union i386_op op
[MAX_OPERANDS
];
151 /* Flags for operands. */
152 unsigned int flags
[MAX_OPERANDS
];
153 #define Operand_PCrel 1
155 /* Relocation type for operand */
156 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
158 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
159 the base index byte below. */
160 const reg_entry
*base_reg
;
161 const reg_entry
*index_reg
;
162 unsigned int log2_scale_factor
;
164 /* SEG gives the seg_entries of this insn. They are zero unless
165 explicit segment overrides are given. */
166 const seg_entry
*seg
[2];
168 /* PREFIX holds all the given prefix opcodes (usually null).
169 PREFIXES is the number of prefix opcodes. */
170 unsigned int prefixes
;
171 unsigned char prefix
[MAX_PREFIXES
];
173 /* RM and SIB are the modrm byte and the sib byte where the
174 addressing modes of this insn are encoded. */
181 typedef struct _i386_insn i386_insn
;
183 /* List of chars besides those in app.c:symbol_chars that can start an
184 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars
[] = "*%-(["
194 #if (defined (TE_I386AIX) \
195 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
196 && !defined (TE_LINUX) \
197 && !defined (TE_NETWARE) \
198 && !defined (TE_FreeBSD) \
199 && !defined (TE_NetBSD)))
200 /* This array holds the chars that always start a comment. If the
201 pre-processor is disabled, these aren't very useful. */
202 const char comment_chars
[] = "#/";
203 #define PREFIX_SEPARATOR '\\'
205 /* This array holds the chars that only start a comment at the beginning of
206 a line. If the line seems to have the form '# 123 filename'
207 .line and .file directives will appear in the pre-processed output.
208 Note that input_file.c hand checks for '#' at the beginning of the
209 first line of the input file. This is because the compiler outputs
210 #NO_APP at the beginning of its output.
211 Also note that comments started like this one will always work if
212 '/' isn't otherwise defined. */
213 const char line_comment_chars
[] = "#";
216 /* Putting '/' here makes it impossible to use the divide operator.
217 However, we need it for compatibility with SVR4 systems. */
218 const char comment_chars
[] = "#";
219 #define PREFIX_SEPARATOR '/'
221 const char line_comment_chars
[] = "/#";
224 const char line_separator_chars
[] = ";";
226 /* Chars that can be used to separate mant from exp in floating point
228 const char EXP_CHARS
[] = "eE";
230 /* Chars that mean this number is a floating point constant
233 const char FLT_CHARS
[] = "fFdDxX";
235 /* Tables for lexical analysis. */
236 static char mnemonic_chars
[256];
237 static char register_chars
[256];
238 static char operand_chars
[256];
239 static char identifier_chars
[256];
240 static char digit_chars
[256];
242 /* Lexical macros. */
243 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
244 #define is_operand_char(x) (operand_chars[(unsigned char) x])
245 #define is_register_char(x) (register_chars[(unsigned char) x])
246 #define is_space_char(x) ((x) == ' ')
247 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
248 #define is_digit_char(x) (digit_chars[(unsigned char) x])
250 /* All non-digit non-letter characters that may occur in an operand. */
251 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
253 /* md_assemble() always leaves the strings it's passed unaltered. To
254 effect this we maintain a stack of saved characters that we've smashed
255 with '\0's (indicating end of strings for various sub-fields of the
256 assembler instruction). */
257 static char save_stack
[32];
258 static char *save_stack_p
;
259 #define END_STRING_AND_SAVE(s) \
260 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
261 #define RESTORE_END_STRING(s) \
262 do { *(s) = *--save_stack_p; } while (0)
264 /* The instruction we're assembling. */
267 /* Possible templates for current insn. */
268 static const templates
*current_templates
;
270 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
271 static expressionS disp_expressions
[2], im_expressions
[2];
273 /* Current operand we are working on. */
274 static int this_operand
;
276 /* We support four different modes. FLAG_CODE variable is used to distinguish
283 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
285 static enum flag_code flag_code
;
286 static int use_rela_relocations
= 0;
288 /* The names used to print error messages. */
289 static const char *flag_code_names
[] =
296 /* 1 for intel syntax,
298 static int intel_syntax
= 0;
300 /* 1 if register prefix % not required. */
301 static int allow_naked_reg
= 0;
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size
= '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code
= 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings
= 0;
315 static const char *cpu_arch_name
= NULL
;
317 /* CPU feature flags. */
318 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
320 /* If set, conditional jumps are not automatically promoted to handle
321 larger than a byte offset. */
322 static unsigned int no_cond_jump_promotion
= 0;
324 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
328 unsigned int x86_dwarf2_return_column
;
330 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
331 int x86_cie_data_alignment
;
333 /* Interface to relax_segment.
334 There are 3 major relax states for 386 jump insns because the
335 different types of jumps add different sizes to frags when we're
336 figuring out what sort of jump to choose to reach a given label. */
339 #define UNCOND_JUMP 0
341 #define COND_JUMP86 2
346 #define SMALL16 (SMALL | CODE16)
348 #define BIG16 (BIG | CODE16)
352 #define INLINE __inline__
358 #define ENCODE_RELAX_STATE(type, size) \
359 ((relax_substateT) (((type) << 2) | (size)))
360 #define TYPE_FROM_RELAX_STATE(s) \
362 #define DISP_SIZE_FROM_RELAX_STATE(s) \
363 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
365 /* This table is used by relax_frag to promote short jumps to long
366 ones where necessary. SMALL (short) jumps may be promoted to BIG
367 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
368 don't allow a short jump in a 32 bit code segment to be promoted to
369 a 16 bit offset jump because it's slower (requires data size
370 prefix), and doesn't work, unless the destination is in the bottom
371 64k of the code segment (The top 16 bits of eip are zeroed). */
373 const relax_typeS md_relax_table
[] =
376 1) most positive reach of this state,
377 2) most negative reach of this state,
378 3) how many bytes this mode will have in the variable part of the frag
379 4) which index into the table to try if we can't fit into this one. */
381 /* UNCOND_JUMP states. */
382 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
384 /* dword jmp adds 4 bytes to frag:
385 0 extra opcode bytes, 4 displacement bytes. */
387 /* word jmp adds 2 byte2 to frag:
388 0 extra opcode bytes, 2 displacement bytes. */
391 /* COND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
394 /* dword conditionals adds 5 bytes to frag:
395 1 extra opcode byte, 4 displacement bytes. */
397 /* word conditionals add 3 bytes to frag:
398 1 extra opcode byte, 2 displacement bytes. */
401 /* COND_JUMP86 states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 4 bytes to frag:
408 1 displacement byte and a 3 byte long branch insn. */
412 static const arch_entry cpu_arch
[] = {
414 {"i186", Cpu086
|Cpu186
},
415 {"i286", Cpu086
|Cpu186
|Cpu286
},
416 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
417 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
418 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
419 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
420 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
421 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
422 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
423 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
424 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
425 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
429 const pseudo_typeS md_pseudo_table
[] =
431 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
432 {"align", s_align_bytes
, 0},
434 {"align", s_align_ptwo
, 0},
436 {"arch", set_cpu_arch
, 0},
440 {"ffloat", float_cons
, 'f'},
441 {"dfloat", float_cons
, 'd'},
442 {"tfloat", float_cons
, 'x'},
444 {"noopt", s_ignore
, 0},
445 {"optim", s_ignore
, 0},
446 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
447 {"code16", set_code_flag
, CODE_16BIT
},
448 {"code32", set_code_flag
, CODE_32BIT
},
449 {"code64", set_code_flag
, CODE_64BIT
},
450 {"intel_syntax", set_intel_syntax
, 1},
451 {"att_syntax", set_intel_syntax
, 0},
452 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
453 {"loc", dwarf2_directive_loc
, 0},
455 {"secrel32", pe_directive_secrel
, 0},
460 /* For interface with expression (). */
461 extern char *input_line_pointer
;
463 /* Hash table for instruction mnemonic lookup. */
464 static struct hash_control
*op_hash
;
466 /* Hash table for register lookup. */
467 static struct hash_control
*reg_hash
;
470 i386_align_code (fragP
, count
)
474 /* Various efficient no-op patterns for aligning code labels.
475 Note: Don't try to assemble the instructions in the comments.
476 0L and 0w are not legal. */
477 static const char f32_1
[] =
479 static const char f32_2
[] =
480 {0x89,0xf6}; /* movl %esi,%esi */
481 static const char f32_3
[] =
482 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
483 static const char f32_4
[] =
484 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
485 static const char f32_5
[] =
487 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
488 static const char f32_6
[] =
489 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
490 static const char f32_7
[] =
491 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
492 static const char f32_8
[] =
494 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
495 static const char f32_9
[] =
496 {0x89,0xf6, /* movl %esi,%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_10
[] =
499 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
500 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
501 static const char f32_11
[] =
502 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
503 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
504 static const char f32_12
[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
506 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
507 static const char f32_13
[] =
508 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_14
[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_15
[] =
514 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
515 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
516 static const char f16_3
[] =
517 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
518 static const char f16_4
[] =
519 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
520 static const char f16_5
[] =
522 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
523 static const char f16_6
[] =
524 {0x89,0xf6, /* mov %si,%si */
525 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
526 static const char f16_7
[] =
527 {0x8d,0x74,0x00, /* lea 0(%si),%si */
528 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
529 static const char f16_8
[] =
530 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
531 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
532 static const char *const f32_patt
[] = {
533 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
534 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
536 static const char *const f16_patt
[] = {
537 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
538 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
541 if (count
<= 0 || count
> 15)
544 /* The recommended way to pad 64bit code is to use NOPs preceded by
545 maximally four 0x66 prefixes. Balance the size of nops. */
546 if (flag_code
== CODE_64BIT
)
549 int nnops
= (count
+ 3) / 4;
550 int len
= count
/ nnops
;
551 int remains
= count
- nnops
* len
;
554 for (i
= 0; i
< remains
; i
++)
556 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
557 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
560 for (; i
< nnops
; i
++)
562 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
563 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
568 if (flag_code
== CODE_16BIT
)
570 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
571 f16_patt
[count
- 1], count
);
573 /* Adjust jump offset. */
574 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
577 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
578 f32_patt
[count
- 1], count
);
579 fragP
->fr_var
= count
;
582 static INLINE
unsigned int
583 mode_from_disp_size (t
)
586 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
590 fits_in_signed_byte (num
)
593 return (num
>= -128) && (num
<= 127);
597 fits_in_unsigned_byte (num
)
600 return (num
& 0xff) == num
;
604 fits_in_unsigned_word (num
)
607 return (num
& 0xffff) == num
;
611 fits_in_signed_word (num
)
614 return (-32768 <= num
) && (num
<= 32767);
617 fits_in_signed_long (num
)
618 offsetT num ATTRIBUTE_UNUSED
;
623 return (!(((offsetT
) -1 << 31) & num
)
624 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
626 } /* fits_in_signed_long() */
628 fits_in_unsigned_long (num
)
629 offsetT num ATTRIBUTE_UNUSED
;
634 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
636 } /* fits_in_unsigned_long() */
639 smallest_imm_type (num
)
642 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
644 /* This code is disabled on the 486 because all the Imm1 forms
645 in the opcode table are slower on the i486. They're the
646 versions with the implicitly specified single-position
647 displacement, which has another syntax if you really want to
650 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
652 return (fits_in_signed_byte (num
)
653 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
654 : fits_in_unsigned_byte (num
)
655 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
656 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
657 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
658 : fits_in_signed_long (num
)
659 ? (Imm32
| Imm32S
| Imm64
)
660 : fits_in_unsigned_long (num
)
666 offset_in_range (val
, size
)
674 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
675 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
676 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
678 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
683 /* If BFD64, sign extend val. */
684 if (!use_rela_relocations
)
685 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
686 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
688 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
690 char buf1
[40], buf2
[40];
692 sprint_value (buf1
, val
);
693 sprint_value (buf2
, val
& mask
);
694 as_warn (_("%s shortened to %s"), buf1
, buf2
);
699 /* Returns 0 if attempting to add a prefix where one from the same
700 class already exists, 1 if non rep/repne added, 2 if rep/repne
709 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
710 && flag_code
== CODE_64BIT
)
718 case CS_PREFIX_OPCODE
:
719 case DS_PREFIX_OPCODE
:
720 case ES_PREFIX_OPCODE
:
721 case FS_PREFIX_OPCODE
:
722 case GS_PREFIX_OPCODE
:
723 case SS_PREFIX_OPCODE
:
727 case REPNE_PREFIX_OPCODE
:
728 case REPE_PREFIX_OPCODE
:
731 case LOCK_PREFIX_OPCODE
:
739 case ADDR_PREFIX_OPCODE
:
743 case DATA_PREFIX_OPCODE
:
748 if (i
.prefix
[q
] != 0)
750 as_bad (_("same type of prefix used twice"));
755 i
.prefix
[q
] = prefix
;
760 set_code_flag (value
)
764 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
765 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
766 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
768 as_bad (_("64bit mode not supported on this CPU."));
770 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
772 as_bad (_("32bit mode not supported on this CPU."));
778 set_16bit_gcc_code_flag (new_code_flag
)
781 flag_code
= new_code_flag
;
782 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
783 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
788 set_intel_syntax (syntax_flag
)
791 /* Find out if register prefixing is specified. */
792 int ask_naked_reg
= 0;
795 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
797 char *string
= input_line_pointer
;
798 int e
= get_symbol_end ();
800 if (strcmp (string
, "prefix") == 0)
802 else if (strcmp (string
, "noprefix") == 0)
805 as_bad (_("bad argument to syntax directive."));
806 *input_line_pointer
= e
;
808 demand_empty_rest_of_line ();
810 intel_syntax
= syntax_flag
;
812 if (ask_naked_reg
== 0)
813 allow_naked_reg
= (intel_syntax
814 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
816 allow_naked_reg
= (ask_naked_reg
< 0);
821 int dummy ATTRIBUTE_UNUSED
;
825 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
827 char *string
= input_line_pointer
;
828 int e
= get_symbol_end ();
831 for (i
= 0; cpu_arch
[i
].name
; i
++)
833 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
835 cpu_arch_name
= cpu_arch
[i
].name
;
836 cpu_arch_flags
= (cpu_arch
[i
].flags
837 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
841 if (!cpu_arch
[i
].name
)
842 as_bad (_("no such architecture: `%s'"), string
);
844 *input_line_pointer
= e
;
847 as_bad (_("missing cpu architecture"));
849 no_cond_jump_promotion
= 0;
850 if (*input_line_pointer
== ','
851 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
853 char *string
= ++input_line_pointer
;
854 int e
= get_symbol_end ();
856 if (strcmp (string
, "nojumps") == 0)
857 no_cond_jump_promotion
= 1;
858 else if (strcmp (string
, "jumps") == 0)
861 as_bad (_("no such architecture modifier: `%s'"), string
);
863 *input_line_pointer
= e
;
866 demand_empty_rest_of_line ();
872 if (!strcmp (default_arch
, "x86_64"))
873 return bfd_mach_x86_64
;
874 else if (!strcmp (default_arch
, "i386"))
875 return bfd_mach_i386_i386
;
877 as_fatal (_("Unknown architecture"));
883 const char *hash_err
;
885 /* Initialize op_hash hash table. */
886 op_hash
= hash_new ();
889 const template *optab
;
890 templates
*core_optab
;
892 /* Setup for loop. */
894 core_optab
= (templates
*) xmalloc (sizeof (templates
));
895 core_optab
->start
= optab
;
900 if (optab
->name
== NULL
901 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
903 /* different name --> ship out current template list;
904 add to hash table; & begin anew. */
905 core_optab
->end
= optab
;
906 hash_err
= hash_insert (op_hash
,
911 as_fatal (_("Internal Error: Can't hash %s: %s"),
915 if (optab
->name
== NULL
)
917 core_optab
= (templates
*) xmalloc (sizeof (templates
));
918 core_optab
->start
= optab
;
923 /* Initialize reg_hash hash table. */
924 reg_hash
= hash_new ();
926 const reg_entry
*regtab
;
928 for (regtab
= i386_regtab
;
929 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
932 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
934 as_fatal (_("Internal Error: Can't hash %s: %s"),
940 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
945 for (c
= 0; c
< 256; c
++)
950 mnemonic_chars
[c
] = c
;
951 register_chars
[c
] = c
;
952 operand_chars
[c
] = c
;
954 else if (ISLOWER (c
))
956 mnemonic_chars
[c
] = c
;
957 register_chars
[c
] = c
;
958 operand_chars
[c
] = c
;
960 else if (ISUPPER (c
))
962 mnemonic_chars
[c
] = TOLOWER (c
);
963 register_chars
[c
] = mnemonic_chars
[c
];
964 operand_chars
[c
] = c
;
967 if (ISALPHA (c
) || ISDIGIT (c
))
968 identifier_chars
[c
] = c
;
971 identifier_chars
[c
] = c
;
972 operand_chars
[c
] = c
;
977 identifier_chars
['@'] = '@';
980 identifier_chars
['?'] = '?';
981 operand_chars
['?'] = '?';
983 digit_chars
['-'] = '-';
984 identifier_chars
['_'] = '_';
985 identifier_chars
['.'] = '.';
987 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
988 operand_chars
[(unsigned char) *p
] = *p
;
991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
992 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
994 record_alignment (text_section
, 2);
995 record_alignment (data_section
, 2);
996 record_alignment (bss_section
, 2);
1000 if (flag_code
== CODE_64BIT
)
1002 x86_dwarf2_return_column
= 16;
1003 x86_cie_data_alignment
= -8;
1007 x86_dwarf2_return_column
= 8;
1008 x86_cie_data_alignment
= -4;
1013 i386_print_statistics (file
)
1016 hash_print_statistics (file
, "i386 opcode", op_hash
);
1017 hash_print_statistics (file
, "i386 register", reg_hash
);
1022 /* Debugging routines for md_assemble. */
1023 static void pi
PARAMS ((char *, i386_insn
*));
1024 static void pte
PARAMS ((template *));
1025 static void pt
PARAMS ((unsigned int));
1026 static void pe
PARAMS ((expressionS
*));
1027 static void ps
PARAMS ((symbolS
*));
1036 fprintf (stdout
, "%s: template ", line
);
1038 fprintf (stdout
, " address: base %s index %s scale %x\n",
1039 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1040 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1041 x
->log2_scale_factor
);
1042 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1043 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1044 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1045 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1046 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1047 (x
->rex
& REX_MODE64
) != 0,
1048 (x
->rex
& REX_EXTX
) != 0,
1049 (x
->rex
& REX_EXTY
) != 0,
1050 (x
->rex
& REX_EXTZ
) != 0);
1051 for (i
= 0; i
< x
->operands
; i
++)
1053 fprintf (stdout
, " #%d: ", i
+ 1);
1055 fprintf (stdout
, "\n");
1057 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1058 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1059 if (x
->types
[i
] & Imm
)
1061 if (x
->types
[i
] & Disp
)
1062 pe (x
->op
[i
].disps
);
1071 fprintf (stdout
, " %d operands ", t
->operands
);
1072 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1073 if (t
->extension_opcode
!= None
)
1074 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1075 if (t
->opcode_modifier
& D
)
1076 fprintf (stdout
, "D");
1077 if (t
->opcode_modifier
& W
)
1078 fprintf (stdout
, "W");
1079 fprintf (stdout
, "\n");
1080 for (i
= 0; i
< t
->operands
; i
++)
1082 fprintf (stdout
, " #%d type ", i
+ 1);
1083 pt (t
->operand_types
[i
]);
1084 fprintf (stdout
, "\n");
1092 fprintf (stdout
, " operation %d\n", e
->X_op
);
1093 fprintf (stdout
, " add_number %ld (%lx)\n",
1094 (long) e
->X_add_number
, (long) e
->X_add_number
);
1095 if (e
->X_add_symbol
)
1097 fprintf (stdout
, " add_symbol ");
1098 ps (e
->X_add_symbol
);
1099 fprintf (stdout
, "\n");
1103 fprintf (stdout
, " op_symbol ");
1104 ps (e
->X_op_symbol
);
1105 fprintf (stdout
, "\n");
1113 fprintf (stdout
, "%s type %s%s",
1115 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1116 segment_name (S_GET_SEGMENT (s
)));
1125 static const type_names
[] =
1138 { BaseIndex
, "BaseIndex" },
1142 { Disp32S
, "d32s" },
1144 { InOutPortReg
, "InOutPortReg" },
1145 { ShiftCount
, "ShiftCount" },
1146 { Control
, "control reg" },
1147 { Test
, "test reg" },
1148 { Debug
, "debug reg" },
1149 { FloatReg
, "FReg" },
1150 { FloatAcc
, "FAcc" },
1154 { JumpAbsolute
, "Jump Absolute" },
1165 const struct type_name
*ty
;
1167 for (ty
= type_names
; ty
->mask
; ty
++)
1169 fprintf (stdout
, "%s, ", ty
->tname
);
1173 #endif /* DEBUG386 */
1175 static bfd_reloc_code_real_type reloc
1176 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1178 static bfd_reloc_code_real_type
1179 reloc (size
, pcrel
, sign
, other
)
1183 bfd_reloc_code_real_type other
;
1185 if (other
!= NO_RELOC
)
1191 as_bad (_("There are no unsigned pc-relative relocations"));
1194 case 1: return BFD_RELOC_8_PCREL
;
1195 case 2: return BFD_RELOC_16_PCREL
;
1196 case 4: return BFD_RELOC_32_PCREL
;
1198 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1205 case 4: return BFD_RELOC_X86_64_32S
;
1210 case 1: return BFD_RELOC_8
;
1211 case 2: return BFD_RELOC_16
;
1212 case 4: return BFD_RELOC_32
;
1213 case 8: return BFD_RELOC_64
;
1215 as_bad (_("can not do %s %d byte relocation"),
1216 sign
? "signed" : "unsigned", size
);
1220 return BFD_RELOC_NONE
;
1223 /* Here we decide which fixups can be adjusted to make them relative to
1224 the beginning of the section instead of the symbol. Basically we need
1225 to make sure that the dynamic relocations are done correctly, so in
1226 some cases we force the original symbol to be used. */
1229 tc_i386_fix_adjustable (fixP
)
1230 fixS
*fixP ATTRIBUTE_UNUSED
;
1232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1233 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1236 /* Don't adjust pc-relative references to merge sections in 64-bit
1238 if (use_rela_relocations
1239 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1243 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1244 and changed later by validate_fix. */
1245 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1246 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1249 /* adjust_reloc_syms doesn't know about the GOT. */
1250 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1251 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1252 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1253 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1254 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1255 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1256 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1257 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1258 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1259 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1260 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1261 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1262 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1263 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1264 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1265 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1266 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1267 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1268 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1269 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1270 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1276 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1279 intel_float_operand (mnemonic
)
1280 const char *mnemonic
;
1282 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1285 if (mnemonic
[0] == 'f')
1291 /* This is the guts of the machine-dependent assembler. LINE points to a
1292 machine dependent instruction. This function is supposed to emit
1293 the frags/bytes it assembles to. */
1300 char mnemonic
[MAX_MNEM_SIZE
];
1302 /* Initialize globals. */
1303 memset (&i
, '\0', sizeof (i
));
1304 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1305 i
.reloc
[j
] = NO_RELOC
;
1306 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1307 memset (im_expressions
, '\0', sizeof (im_expressions
));
1308 save_stack_p
= save_stack
;
1310 /* First parse an instruction mnemonic & call i386_operand for the operands.
1311 We assume that the scrubber has arranged it so that line[0] is the valid
1312 start of a (possibly prefixed) mnemonic. */
1314 line
= parse_insn (line
, mnemonic
);
1318 line
= parse_operands (line
, mnemonic
);
1322 /* Now we've parsed the mnemonic into a set of templates, and have the
1323 operands at hand. */
1325 /* All intel opcodes have reversed operands except for "bound" and
1326 "enter". We also don't reverse intersegment "jmp" and "call"
1327 instructions with 2 immediate operands so that the immediate segment
1328 precedes the offset, as it does when in AT&T mode. "enter" and the
1329 intersegment "jmp" and "call" instructions are the only ones that
1330 have two immediate operands. */
1331 if (intel_syntax
&& i
.operands
> 1
1332 && (strcmp (mnemonic
, "bound") != 0)
1333 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1339 if (i
.disp_operands
)
1342 /* Next, we find a template that matches the given insn,
1343 making sure the overlap of the given operands types is consistent
1344 with the template operand types. */
1346 if (!match_template ())
1351 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1353 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1354 i
.tm
.base_opcode
^= FloatR
;
1356 /* Zap movzx and movsx suffix. The suffix may have been set from
1357 "word ptr" or "byte ptr" on the source operand, but we'll use
1358 the suffix later to choose the destination register. */
1359 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1363 if (i
.tm
.opcode_modifier
& FWait
)
1364 if (!add_prefix (FWAIT_OPCODE
))
1367 /* Check string instruction segment overrides. */
1368 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1370 if (!check_string ())
1374 if (!process_suffix ())
1377 /* Make still unresolved immediate matches conform to size of immediate
1378 given in i.suffix. */
1379 if (!finalize_imm ())
1382 if (i
.types
[0] & Imm1
)
1383 i
.imm_operands
= 0; /* kludge for shift insns. */
1384 if (i
.types
[0] & ImplicitRegister
)
1386 if (i
.types
[1] & ImplicitRegister
)
1388 if (i
.types
[2] & ImplicitRegister
)
1391 if (i
.tm
.opcode_modifier
& ImmExt
)
1395 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1397 /* These Intel Prescott New Instructions have the fixed
1398 operands with an opcode suffix which is coded in the same
1399 place as an 8-bit immediate field would be. Here we check
1400 those operands and remove them afterwards. */
1403 for (x
= 0; x
< i
.operands
; x
++)
1404 if (i
.op
[x
].regs
->reg_num
!= x
)
1405 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1406 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1410 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1411 opcode suffix which is coded in the same place as an 8-bit
1412 immediate field would be. Here we fake an 8-bit immediate
1413 operand from the opcode suffix stored in tm.extension_opcode. */
1415 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1417 exp
= &im_expressions
[i
.imm_operands
++];
1418 i
.op
[i
.operands
].imms
= exp
;
1419 i
.types
[i
.operands
++] = Imm8
;
1420 exp
->X_op
= O_constant
;
1421 exp
->X_add_number
= i
.tm
.extension_opcode
;
1422 i
.tm
.extension_opcode
= None
;
1425 /* For insns with operands there are more diddles to do to the opcode. */
1428 if (!process_operands ())
1431 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1433 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1434 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1437 /* Handle conversion of 'int $3' --> special int3 insn. */
1438 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1440 i
.tm
.base_opcode
= INT3_OPCODE
;
1444 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1445 && i
.op
[0].disps
->X_op
== O_constant
)
1447 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1448 the absolute address given by the constant. Since ix86 jumps and
1449 calls are pc relative, we need to generate a reloc. */
1450 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1451 i
.op
[0].disps
->X_op
= O_symbol
;
1454 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1455 i
.rex
|= REX_MODE64
;
1457 /* For 8 bit registers we need an empty rex prefix. Also if the
1458 instruction already has a prefix, we need to convert old
1459 registers to new ones. */
1461 if (((i
.types
[0] & Reg8
) != 0
1462 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1463 || ((i
.types
[1] & Reg8
) != 0
1464 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1465 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1470 i
.rex
|= REX_OPCODE
;
1471 for (x
= 0; x
< 2; x
++)
1473 /* Look for 8 bit operand that uses old registers. */
1474 if ((i
.types
[x
] & Reg8
) != 0
1475 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1477 /* In case it is "hi" register, give up. */
1478 if (i
.op
[x
].regs
->reg_num
> 3)
1479 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1480 i
.op
[x
].regs
->reg_name
);
1482 /* Otherwise it is equivalent to the extended register.
1483 Since the encoding doesn't change this is merely
1484 cosmetic cleanup for debug output. */
1486 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1492 add_prefix (REX_OPCODE
| i
.rex
);
1494 /* We are ready to output the insn. */
1499 parse_insn (line
, mnemonic
)
1504 char *token_start
= l
;
1507 /* Non-zero if we found a prefix only acceptable with string insns. */
1508 const char *expecting_string_instruction
= NULL
;
1513 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1516 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1518 as_bad (_("no such instruction: `%s'"), token_start
);
1523 if (!is_space_char (*l
)
1524 && *l
!= END_OF_INSN
1525 && *l
!= PREFIX_SEPARATOR
1528 as_bad (_("invalid character %s in mnemonic"),
1529 output_invalid (*l
));
1532 if (token_start
== l
)
1534 if (*l
== PREFIX_SEPARATOR
)
1535 as_bad (_("expecting prefix; got nothing"));
1537 as_bad (_("expecting mnemonic; got nothing"));
1541 /* Look up instruction (or prefix) via hash table. */
1542 current_templates
= hash_find (op_hash
, mnemonic
);
1544 if (*l
!= END_OF_INSN
1545 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1546 && current_templates
1547 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1549 /* If we are in 16-bit mode, do not allow addr16 or data16.
1550 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1551 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1552 && flag_code
!= CODE_64BIT
1553 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1554 ^ (flag_code
== CODE_16BIT
)))
1556 as_bad (_("redundant %s prefix"),
1557 current_templates
->start
->name
);
1560 /* Add prefix, checking for repeated prefixes. */
1561 switch (add_prefix (current_templates
->start
->base_opcode
))
1566 expecting_string_instruction
= current_templates
->start
->name
;
1569 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1576 if (!current_templates
)
1578 /* See if we can get a match by trimming off a suffix. */
1581 case WORD_MNEM_SUFFIX
:
1582 case BYTE_MNEM_SUFFIX
:
1583 case QWORD_MNEM_SUFFIX
:
1584 i
.suffix
= mnem_p
[-1];
1586 current_templates
= hash_find (op_hash
, mnemonic
);
1588 case SHORT_MNEM_SUFFIX
:
1589 case LONG_MNEM_SUFFIX
:
1592 i
.suffix
= mnem_p
[-1];
1594 current_templates
= hash_find (op_hash
, mnemonic
);
1602 if (intel_float_operand (mnemonic
))
1603 i
.suffix
= SHORT_MNEM_SUFFIX
;
1605 i
.suffix
= LONG_MNEM_SUFFIX
;
1607 current_templates
= hash_find (op_hash
, mnemonic
);
1611 if (!current_templates
)
1613 as_bad (_("no such instruction: `%s'"), token_start
);
1618 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1620 /* Check for a branch hint. We allow ",pt" and ",pn" for
1621 predict taken and predict not taken respectively.
1622 I'm not sure that branch hints actually do anything on loop
1623 and jcxz insns (JumpByte) for current Pentium4 chips. They
1624 may work in the future and it doesn't hurt to accept them
1626 if (l
[0] == ',' && l
[1] == 'p')
1630 if (!add_prefix (DS_PREFIX_OPCODE
))
1634 else if (l
[2] == 'n')
1636 if (!add_prefix (CS_PREFIX_OPCODE
))
1642 /* Any other comma loses. */
1645 as_bad (_("invalid character %s in mnemonic"),
1646 output_invalid (*l
));
1650 /* Check if instruction is supported on specified architecture. */
1651 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1652 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1654 as_warn (_("`%s' is not supported on `%s'"),
1655 current_templates
->start
->name
, cpu_arch_name
);
1657 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1659 as_warn (_("use .code16 to ensure correct addressing mode"));
1662 /* Check for rep/repne without a string instruction. */
1663 if (expecting_string_instruction
1664 && !(current_templates
->start
->opcode_modifier
& IsString
))
1666 as_bad (_("expecting string instruction after `%s'"),
1667 expecting_string_instruction
);
1675 parse_operands (l
, mnemonic
)
1677 const char *mnemonic
;
1681 /* 1 if operand is pending after ','. */
1682 unsigned int expecting_operand
= 0;
1684 /* Non-zero if operand parens not balanced. */
1685 unsigned int paren_not_balanced
;
1687 while (*l
!= END_OF_INSN
)
1689 /* Skip optional white space before operand. */
1690 if (is_space_char (*l
))
1692 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1694 as_bad (_("invalid character %s before operand %d"),
1695 output_invalid (*l
),
1699 token_start
= l
; /* after white space */
1700 paren_not_balanced
= 0;
1701 while (paren_not_balanced
|| *l
!= ',')
1703 if (*l
== END_OF_INSN
)
1705 if (paren_not_balanced
)
1708 as_bad (_("unbalanced parenthesis in operand %d."),
1711 as_bad (_("unbalanced brackets in operand %d."),
1716 break; /* we are done */
1718 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1720 as_bad (_("invalid character %s in operand %d"),
1721 output_invalid (*l
),
1728 ++paren_not_balanced
;
1730 --paren_not_balanced
;
1735 ++paren_not_balanced
;
1737 --paren_not_balanced
;
1741 if (l
!= token_start
)
1742 { /* Yes, we've read in another operand. */
1743 unsigned int operand_ok
;
1744 this_operand
= i
.operands
++;
1745 if (i
.operands
> MAX_OPERANDS
)
1747 as_bad (_("spurious operands; (%d operands/instruction max)"),
1751 /* Now parse operand adding info to 'i' as we go along. */
1752 END_STRING_AND_SAVE (l
);
1756 i386_intel_operand (token_start
,
1757 intel_float_operand (mnemonic
));
1759 operand_ok
= i386_operand (token_start
);
1761 RESTORE_END_STRING (l
);
1767 if (expecting_operand
)
1769 expecting_operand_after_comma
:
1770 as_bad (_("expecting operand after ','; got nothing"));
1775 as_bad (_("expecting operand before ','; got nothing"));
1780 /* Now *l must be either ',' or END_OF_INSN. */
1783 if (*++l
== END_OF_INSN
)
1785 /* Just skip it, if it's \n complain. */
1786 goto expecting_operand_after_comma
;
1788 expecting_operand
= 1;
1797 union i386_op temp_op
;
1798 unsigned int temp_type
;
1799 enum bfd_reloc_code_real temp_reloc
;
1803 if (i
.operands
== 2)
1808 else if (i
.operands
== 3)
1813 temp_type
= i
.types
[xchg2
];
1814 i
.types
[xchg2
] = i
.types
[xchg1
];
1815 i
.types
[xchg1
] = temp_type
;
1816 temp_op
= i
.op
[xchg2
];
1817 i
.op
[xchg2
] = i
.op
[xchg1
];
1818 i
.op
[xchg1
] = temp_op
;
1819 temp_reloc
= i
.reloc
[xchg2
];
1820 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1821 i
.reloc
[xchg1
] = temp_reloc
;
1823 if (i
.mem_operands
== 2)
1825 const seg_entry
*temp_seg
;
1826 temp_seg
= i
.seg
[0];
1827 i
.seg
[0] = i
.seg
[1];
1828 i
.seg
[1] = temp_seg
;
1832 /* Try to ensure constant immediates are represented in the smallest
1837 char guess_suffix
= 0;
1841 guess_suffix
= i
.suffix
;
1842 else if (i
.reg_operands
)
1844 /* Figure out a suffix from the last register operand specified.
1845 We can't do this properly yet, ie. excluding InOutPortReg,
1846 but the following works for instructions with immediates.
1847 In any case, we can't set i.suffix yet. */
1848 for (op
= i
.operands
; --op
>= 0;)
1849 if (i
.types
[op
] & Reg
)
1851 if (i
.types
[op
] & Reg8
)
1852 guess_suffix
= BYTE_MNEM_SUFFIX
;
1853 else if (i
.types
[op
] & Reg16
)
1854 guess_suffix
= WORD_MNEM_SUFFIX
;
1855 else if (i
.types
[op
] & Reg32
)
1856 guess_suffix
= LONG_MNEM_SUFFIX
;
1857 else if (i
.types
[op
] & Reg64
)
1858 guess_suffix
= QWORD_MNEM_SUFFIX
;
1862 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1863 guess_suffix
= WORD_MNEM_SUFFIX
;
1865 for (op
= i
.operands
; --op
>= 0;)
1866 if (i
.types
[op
] & Imm
)
1868 switch (i
.op
[op
].imms
->X_op
)
1871 /* If a suffix is given, this operand may be shortened. */
1872 switch (guess_suffix
)
1874 case LONG_MNEM_SUFFIX
:
1875 i
.types
[op
] |= Imm32
| Imm64
;
1877 case WORD_MNEM_SUFFIX
:
1878 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1880 case BYTE_MNEM_SUFFIX
:
1881 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1885 /* If this operand is at most 16 bits, convert it
1886 to a signed 16 bit number before trying to see
1887 whether it will fit in an even smaller size.
1888 This allows a 16-bit operand such as $0xffe0 to
1889 be recognised as within Imm8S range. */
1890 if ((i
.types
[op
] & Imm16
)
1891 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1893 i
.op
[op
].imms
->X_add_number
=
1894 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1896 if ((i
.types
[op
] & Imm32
)
1897 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1900 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1901 ^ ((offsetT
) 1 << 31))
1902 - ((offsetT
) 1 << 31));
1904 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1906 /* We must avoid matching of Imm32 templates when 64bit
1907 only immediate is available. */
1908 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1909 i
.types
[op
] &= ~Imm32
;
1916 /* Symbols and expressions. */
1918 /* Convert symbolic operand to proper sizes for matching. */
1919 switch (guess_suffix
)
1921 case QWORD_MNEM_SUFFIX
:
1922 i
.types
[op
] = Imm64
| Imm32S
;
1924 case LONG_MNEM_SUFFIX
:
1925 i
.types
[op
] = Imm32
;
1927 case WORD_MNEM_SUFFIX
:
1928 i
.types
[op
] = Imm16
;
1930 case BYTE_MNEM_SUFFIX
:
1931 i
.types
[op
] = Imm8
| Imm8S
;
1939 /* Try to use the smallest displacement type too. */
1945 for (op
= i
.operands
; --op
>= 0;)
1946 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1948 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1950 if (i
.types
[op
] & Disp16
)
1952 /* We know this operand is at most 16 bits, so
1953 convert to a signed 16 bit number before trying
1954 to see whether it will fit in an even smaller
1957 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1959 else if (i
.types
[op
] & Disp32
)
1961 /* We know this operand is at most 32 bits, so convert to a
1962 signed 32 bit number before trying to see whether it will
1963 fit in an even smaller size. */
1964 disp
&= (((offsetT
) 2 << 31) - 1);
1965 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1967 if (flag_code
== CODE_64BIT
)
1969 if (fits_in_signed_long (disp
))
1970 i
.types
[op
] |= Disp32S
;
1971 if (fits_in_unsigned_long (disp
))
1972 i
.types
[op
] |= Disp32
;
1974 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1975 && fits_in_signed_byte (disp
))
1976 i
.types
[op
] |= Disp8
;
1983 /* Points to template once we've found it. */
1985 unsigned int overlap0
, overlap1
, overlap2
;
1986 unsigned int found_reverse_match
;
1989 #define MATCH(overlap, given, template) \
1990 ((overlap & ~JumpAbsolute) \
1991 && (((given) & (BaseIndex | JumpAbsolute)) \
1992 == ((overlap) & (BaseIndex | JumpAbsolute))))
1994 /* If given types r0 and r1 are registers they must be of the same type
1995 unless the expected operand type register overlap is null.
1996 Note that Acc in a template matches every size of reg. */
1997 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1998 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1999 || ((g0) & Reg) == ((g1) & Reg) \
2000 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2005 found_reverse_match
= 0;
2006 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2008 : (i
.suffix
== WORD_MNEM_SUFFIX
2010 : (i
.suffix
== SHORT_MNEM_SUFFIX
2012 : (i
.suffix
== LONG_MNEM_SUFFIX
2014 : (i
.suffix
== QWORD_MNEM_SUFFIX
2016 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2017 ? No_xSuf
: 0))))));
2019 t
= current_templates
->start
;
2020 if (i
.suffix
== QWORD_MNEM_SUFFIX
2021 && flag_code
!= CODE_64BIT
2023 || (!(t
->opcode_modifier
& IgnoreSize
)
2024 && ! intel_float_operand (t
->name
)))
2025 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2026 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2027 && (t
->base_opcode
!= 0x0fc7
2028 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2029 t
= current_templates
->end
;
2030 for (; t
< current_templates
->end
; t
++)
2032 /* Must have right number of operands. */
2033 if (i
.operands
!= t
->operands
)
2036 /* Check the suffix, except for some instructions in intel mode. */
2037 if ((t
->opcode_modifier
& suffix_check
)
2039 && (t
->opcode_modifier
& IgnoreSize
))
2041 && t
->base_opcode
== 0xd9
2042 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2043 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2046 /* Do not verify operands when there are none. */
2047 else if (!t
->operands
)
2049 if (t
->cpu_flags
& ~cpu_arch_flags
)
2051 /* We've found a match; break out of loop. */
2055 overlap0
= i
.types
[0] & t
->operand_types
[0];
2056 switch (t
->operands
)
2059 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2064 overlap1
= i
.types
[1] & t
->operand_types
[1];
2065 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2066 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2067 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2068 t
->operand_types
[0],
2069 overlap1
, i
.types
[1],
2070 t
->operand_types
[1]))
2072 /* Check if other direction is valid ... */
2073 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2076 /* Try reversing direction of operands. */
2077 overlap0
= i
.types
[0] & t
->operand_types
[1];
2078 overlap1
= i
.types
[1] & t
->operand_types
[0];
2079 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2080 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2081 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2082 t
->operand_types
[1],
2083 overlap1
, i
.types
[1],
2084 t
->operand_types
[0]))
2086 /* Does not match either direction. */
2089 /* found_reverse_match holds which of D or FloatDR
2091 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2093 /* Found a forward 2 operand match here. */
2094 else if (t
->operands
== 3)
2096 /* Here we make use of the fact that there are no
2097 reverse match 3 operand instructions, and all 3
2098 operand instructions only need to be checked for
2099 register consistency between operands 2 and 3. */
2100 overlap2
= i
.types
[2] & t
->operand_types
[2];
2101 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2102 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2103 t
->operand_types
[1],
2104 overlap2
, i
.types
[2],
2105 t
->operand_types
[2]))
2109 /* Found either forward/reverse 2 or 3 operand match here:
2110 slip through to break. */
2112 if (t
->cpu_flags
& ~cpu_arch_flags
)
2114 found_reverse_match
= 0;
2117 /* We've found a match; break out of loop. */
2121 if (t
== current_templates
->end
)
2123 /* We found no match. */
2124 as_bad (_("suffix or operands invalid for `%s'"),
2125 current_templates
->start
->name
);
2129 if (!quiet_warnings
)
2132 && ((i
.types
[0] & JumpAbsolute
)
2133 != (t
->operand_types
[0] & JumpAbsolute
)))
2135 as_warn (_("indirect %s without `*'"), t
->name
);
2138 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2139 == (IsPrefix
| IgnoreSize
))
2141 /* Warn them that a data or address size prefix doesn't
2142 affect assembly of the next line of code. */
2143 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2147 /* Copy the template we found. */
2149 if (found_reverse_match
)
2151 /* If we found a reverse match we must alter the opcode
2152 direction bit. found_reverse_match holds bits to change
2153 (different for int & float insns). */
2155 i
.tm
.base_opcode
^= found_reverse_match
;
2157 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2158 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2167 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2168 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2170 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2172 as_bad (_("`%s' operand %d must use `%%es' segment"),
2177 /* There's only ever one segment override allowed per instruction.
2178 This instruction possibly has a legal segment override on the
2179 second operand, so copy the segment to where non-string
2180 instructions store it, allowing common code. */
2181 i
.seg
[0] = i
.seg
[1];
2183 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2185 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2187 as_bad (_("`%s' operand %d must use `%%es' segment"),
2199 /* If matched instruction specifies an explicit instruction mnemonic
2201 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2203 if (i
.tm
.opcode_modifier
& Size16
)
2204 i
.suffix
= WORD_MNEM_SUFFIX
;
2205 else if (i
.tm
.opcode_modifier
& Size64
)
2206 i
.suffix
= QWORD_MNEM_SUFFIX
;
2208 i
.suffix
= LONG_MNEM_SUFFIX
;
2210 else if (i
.reg_operands
)
2212 /* If there's no instruction mnemonic suffix we try to invent one
2213 based on register operands. */
2216 /* We take i.suffix from the last register operand specified,
2217 Destination register type is more significant than source
2220 for (op
= i
.operands
; --op
>= 0;)
2221 if ((i
.types
[op
] & Reg
)
2222 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2224 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2225 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2226 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2231 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2233 if (!check_byte_reg ())
2236 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2238 if (!check_long_reg ())
2241 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2243 if (!check_qword_reg ())
2246 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2248 if (!check_word_reg ())
2251 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2252 /* Do nothing if the instruction is going to ignore the prefix. */
2257 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2259 i
.suffix
= stackop_size
;
2262 /* Change the opcode based on the operand size given by i.suffix;
2263 We need not change things for byte insns. */
2265 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2267 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2271 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2273 /* It's not a byte, select word/dword operation. */
2274 if (i
.tm
.opcode_modifier
& W
)
2276 if (i
.tm
.opcode_modifier
& ShortForm
)
2277 i
.tm
.base_opcode
|= 8;
2279 i
.tm
.base_opcode
|= 1;
2282 /* Now select between word & dword operations via the operand
2283 size prefix, except for instructions that will ignore this
2285 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2286 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2287 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2288 || (flag_code
== CODE_64BIT
2289 && (i
.tm
.opcode_modifier
& JumpByte
))))
2291 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2292 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2293 prefix
= ADDR_PREFIX_OPCODE
;
2295 if (!add_prefix (prefix
))
2299 /* Set mode64 for an operand. */
2300 if (i
.suffix
== QWORD_MNEM_SUFFIX
2301 && flag_code
== CODE_64BIT
2302 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2303 i
.rex
|= REX_MODE64
;
2305 /* Size floating point instruction. */
2306 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2308 if (i
.tm
.opcode_modifier
& FloatMF
)
2309 i
.tm
.base_opcode
^= 4;
2320 for (op
= i
.operands
; --op
>= 0;)
2322 /* If this is an eight bit register, it's OK. If it's the 16 or
2323 32 bit version of an eight bit register, we will just use the
2324 low portion, and that's OK too. */
2325 if (i
.types
[op
] & Reg8
)
2328 /* movzx and movsx should not generate this warning. */
2330 && (i
.tm
.base_opcode
== 0xfb7
2331 || i
.tm
.base_opcode
== 0xfb6
2332 || i
.tm
.base_opcode
== 0x63
2333 || i
.tm
.base_opcode
== 0xfbe
2334 || i
.tm
.base_opcode
== 0xfbf))
2337 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2339 /* Check that the template allows eight bit regs. This
2340 kills insns such as `orb $1,%edx', which maybe should be
2342 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2346 /* Prohibit these changes in the 64bit mode, since the
2347 lowering is more complicated. */
2348 if (flag_code
== CODE_64BIT
2349 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2351 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2352 i
.op
[op
].regs
->reg_name
,
2356 #if REGISTER_WARNINGS
2358 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2359 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2360 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2361 ? REGNAM_AL
- REGNAM_AX
2362 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2363 i
.op
[op
].regs
->reg_name
,
2368 /* Any other register is bad. */
2369 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2371 | Control
| Debug
| Test
2372 | FloatReg
| FloatAcc
))
2374 as_bad (_("`%%%s' not allowed with `%s%c'"),
2375 i
.op
[op
].regs
->reg_name
,
2389 for (op
= i
.operands
; --op
>= 0;)
2390 /* Reject eight bit registers, except where the template requires
2391 them. (eg. movzb) */
2392 if ((i
.types
[op
] & Reg8
) != 0
2393 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2395 as_bad (_("`%%%s' not allowed with `%s%c'"),
2396 i
.op
[op
].regs
->reg_name
,
2401 /* Warn if the e prefix on a general reg is missing. */
2402 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2403 && (i
.types
[op
] & Reg16
) != 0
2404 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2406 /* Prohibit these changes in the 64bit mode, since the
2407 lowering is more complicated. */
2408 if (flag_code
== CODE_64BIT
)
2410 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2411 i
.op
[op
].regs
->reg_name
,
2415 #if REGISTER_WARNINGS
2417 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2418 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2419 i
.op
[op
].regs
->reg_name
,
2423 /* Warn if the r prefix on a general reg is missing. */
2424 else if ((i
.types
[op
] & Reg64
) != 0
2425 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2427 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2428 i
.op
[op
].regs
->reg_name
,
2440 for (op
= i
.operands
; --op
>= 0; )
2441 /* Reject eight bit registers, except where the template requires
2442 them. (eg. movzb) */
2443 if ((i
.types
[op
] & Reg8
) != 0
2444 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2446 as_bad (_("`%%%s' not allowed with `%s%c'"),
2447 i
.op
[op
].regs
->reg_name
,
2452 /* Warn if the e prefix on a general reg is missing. */
2453 else if (((i
.types
[op
] & Reg16
) != 0
2454 || (i
.types
[op
] & Reg32
) != 0)
2455 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2457 /* Prohibit these changes in the 64bit mode, since the
2458 lowering is more complicated. */
2459 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2460 i
.op
[op
].regs
->reg_name
,
2471 for (op
= i
.operands
; --op
>= 0;)
2472 /* Reject eight bit registers, except where the template requires
2473 them. (eg. movzb) */
2474 if ((i
.types
[op
] & Reg8
) != 0
2475 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2477 as_bad (_("`%%%s' not allowed with `%s%c'"),
2478 i
.op
[op
].regs
->reg_name
,
2483 /* Warn if the e prefix on a general reg is present. */
2484 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2485 && (i
.types
[op
] & Reg32
) != 0
2486 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2488 /* Prohibit these changes in the 64bit mode, since the
2489 lowering is more complicated. */
2490 if (flag_code
== CODE_64BIT
)
2492 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2493 i
.op
[op
].regs
->reg_name
,
2498 #if REGISTER_WARNINGS
2499 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2500 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2501 i
.op
[op
].regs
->reg_name
,
2511 unsigned int overlap0
, overlap1
, overlap2
;
2513 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2514 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2515 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2516 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2517 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2521 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2523 : (i
.suffix
== WORD_MNEM_SUFFIX
2525 : (i
.suffix
== QWORD_MNEM_SUFFIX
2529 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2530 || overlap0
== (Imm16
| Imm32
)
2531 || overlap0
== (Imm16
| Imm32S
))
2533 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2536 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2537 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2538 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2540 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2544 i
.types
[0] = overlap0
;
2546 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2547 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2548 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2549 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2550 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2554 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2556 : (i
.suffix
== WORD_MNEM_SUFFIX
2558 : (i
.suffix
== QWORD_MNEM_SUFFIX
2562 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2563 || overlap1
== (Imm16
| Imm32
)
2564 || overlap1
== (Imm16
| Imm32S
))
2566 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2569 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2570 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2571 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2573 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2577 i
.types
[1] = overlap1
;
2579 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2580 assert ((overlap2
& Imm
) == 0);
2581 i
.types
[2] = overlap2
;
2589 /* Default segment register this instruction will use for memory
2590 accesses. 0 means unknown. This is only for optimizing out
2591 unnecessary segment overrides. */
2592 const seg_entry
*default_seg
= 0;
2594 /* The imul $imm, %reg instruction is converted into
2595 imul $imm, %reg, %reg, and the clr %reg instruction
2596 is converted into xor %reg, %reg. */
2597 if (i
.tm
.opcode_modifier
& regKludge
)
2599 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2600 /* Pretend we saw the extra register operand. */
2601 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2602 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2603 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2607 if (i
.tm
.opcode_modifier
& ShortForm
)
2609 /* The register or float register operand is in operand 0 or 1. */
2610 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2611 /* Register goes in low 3 bits of opcode. */
2612 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2613 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2615 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2617 /* Warn about some common errors, but press on regardless.
2618 The first case can be generated by gcc (<= 2.8.1). */
2619 if (i
.operands
== 2)
2621 /* Reversed arguments on faddp, fsubp, etc. */
2622 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2623 i
.op
[1].regs
->reg_name
,
2624 i
.op
[0].regs
->reg_name
);
2628 /* Extraneous `l' suffix on fp insn. */
2629 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2630 i
.op
[0].regs
->reg_name
);
2634 else if (i
.tm
.opcode_modifier
& Modrm
)
2636 /* The opcode is completed (modulo i.tm.extension_opcode which
2637 must be put into the modrm byte). Now, we make the modrm and
2638 index base bytes based on all the info we've collected. */
2640 default_seg
= build_modrm_byte ();
2642 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2644 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2645 && i
.op
[0].regs
->reg_num
== 1)
2647 as_bad (_("you can't `pop %%cs'"));
2650 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2651 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2654 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2658 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2660 /* For the string instructions that allow a segment override
2661 on one of their operands, the default segment is ds. */
2665 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2666 as_warn (_("segment override on `lea' is ineffectual"));
2668 /* If a segment was explicitly specified, and the specified segment
2669 is not the default, use an opcode prefix to select it. If we
2670 never figured out what the default segment is, then default_seg
2671 will be zero at this point, and the specified segment prefix will
2673 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2675 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2681 static const seg_entry
*
2684 const seg_entry
*default_seg
= 0;
2686 /* i.reg_operands MUST be the number of real register operands;
2687 implicit registers do not count. */
2688 if (i
.reg_operands
== 2)
2690 unsigned int source
, dest
;
2691 source
= ((i
.types
[0]
2692 & (Reg
| RegMMX
| RegXMM
2694 | Control
| Debug
| Test
))
2699 /* One of the register operands will be encoded in the i.tm.reg
2700 field, the other in the combined i.tm.mode and i.tm.regmem
2701 fields. If no form of this instruction supports a memory
2702 destination operand, then we assume the source operand may
2703 sometimes be a memory operand and so we need to store the
2704 destination in the i.rm.reg field. */
2705 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2707 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2708 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2709 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2711 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2716 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2717 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2718 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2720 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2725 { /* If it's not 2 reg operands... */
2728 unsigned int fake_zero_displacement
= 0;
2729 unsigned int op
= ((i
.types
[0] & AnyMem
)
2731 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2735 if (i
.base_reg
== 0)
2738 if (!i
.disp_operands
)
2739 fake_zero_displacement
= 1;
2740 if (i
.index_reg
== 0)
2742 /* Operand is just <disp> */
2743 if (flag_code
== CODE_64BIT
)
2745 /* 64bit mode overwrites the 32bit absolute
2746 addressing by RIP relative addressing and
2747 absolute addressing is encoded by one of the
2748 redundant SIB forms. */
2749 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2750 i
.sib
.base
= NO_BASE_REGISTER
;
2751 i
.sib
.index
= NO_INDEX_REGISTER
;
2752 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2754 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2756 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2757 i
.types
[op
] = Disp16
;
2761 i
.rm
.regmem
= NO_BASE_REGISTER
;
2762 i
.types
[op
] = Disp32
;
2765 else /* !i.base_reg && i.index_reg */
2767 i
.sib
.index
= i
.index_reg
->reg_num
;
2768 i
.sib
.base
= NO_BASE_REGISTER
;
2769 i
.sib
.scale
= i
.log2_scale_factor
;
2770 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2771 i
.types
[op
] &= ~Disp
;
2772 if (flag_code
!= CODE_64BIT
)
2773 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2775 i
.types
[op
] |= Disp32S
;
2776 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2780 /* RIP addressing for 64bit mode. */
2781 else if (i
.base_reg
->reg_type
== BaseIndex
)
2783 i
.rm
.regmem
= NO_BASE_REGISTER
;
2784 i
.types
[op
] &= ~ Disp
;
2785 i
.types
[op
] |= Disp32S
;
2786 i
.flags
[op
] = Operand_PCrel
;
2787 if (! i
.disp_operands
)
2788 fake_zero_displacement
= 1;
2790 else if (i
.base_reg
->reg_type
& Reg16
)
2792 switch (i
.base_reg
->reg_num
)
2795 if (i
.index_reg
== 0)
2797 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2798 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2802 if (i
.index_reg
== 0)
2805 if ((i
.types
[op
] & Disp
) == 0)
2807 /* fake (%bp) into 0(%bp) */
2808 i
.types
[op
] |= Disp8
;
2809 fake_zero_displacement
= 1;
2812 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2813 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2815 default: /* (%si) -> 4 or (%di) -> 5 */
2816 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2818 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2820 else /* i.base_reg and 32/64 bit mode */
2822 if (flag_code
== CODE_64BIT
2823 && (i
.types
[op
] & Disp
))
2824 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2826 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2827 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2829 i
.sib
.base
= i
.base_reg
->reg_num
;
2830 /* x86-64 ignores REX prefix bit here to avoid decoder
2832 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2835 if (i
.disp_operands
== 0)
2837 fake_zero_displacement
= 1;
2838 i
.types
[op
] |= Disp8
;
2841 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2845 i
.sib
.scale
= i
.log2_scale_factor
;
2846 if (i
.index_reg
== 0)
2848 /* <disp>(%esp) becomes two byte modrm with no index
2849 register. We've already stored the code for esp
2850 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2851 Any base register besides %esp will not use the
2852 extra modrm byte. */
2853 i
.sib
.index
= NO_INDEX_REGISTER
;
2854 #if !SCALE1_WHEN_NO_INDEX
2855 /* Another case where we force the second modrm byte. */
2856 if (i
.log2_scale_factor
)
2857 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2862 i
.sib
.index
= i
.index_reg
->reg_num
;
2863 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2864 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2867 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2870 if (fake_zero_displacement
)
2872 /* Fakes a zero displacement assuming that i.types[op]
2873 holds the correct displacement size. */
2876 assert (i
.op
[op
].disps
== 0);
2877 exp
= &disp_expressions
[i
.disp_operands
++];
2878 i
.op
[op
].disps
= exp
;
2879 exp
->X_op
= O_constant
;
2880 exp
->X_add_number
= 0;
2881 exp
->X_add_symbol
= (symbolS
*) 0;
2882 exp
->X_op_symbol
= (symbolS
*) 0;
2886 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2887 (if any) based on i.tm.extension_opcode. Again, we must be
2888 careful to make sure that segment/control/debug/test/MMX
2889 registers are coded into the i.rm.reg field. */
2894 & (Reg
| RegMMX
| RegXMM
2896 | Control
| Debug
| Test
))
2899 & (Reg
| RegMMX
| RegXMM
2901 | Control
| Debug
| Test
))
2904 /* If there is an extension opcode to put here, the register
2905 number must be put into the regmem field. */
2906 if (i
.tm
.extension_opcode
!= None
)
2908 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2909 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2914 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2915 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2919 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2920 must set it to 3 to indicate this is a register operand
2921 in the regmem field. */
2922 if (!i
.mem_operands
)
2926 /* Fill in i.rm.reg field with extension opcode (if any). */
2927 if (i
.tm
.extension_opcode
!= None
)
2928 i
.rm
.reg
= i
.tm
.extension_opcode
;
2939 relax_substateT subtype
;
2944 if (flag_code
== CODE_16BIT
)
2948 if (i
.prefix
[DATA_PREFIX
] != 0)
2954 /* Pentium4 branch hints. */
2955 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2956 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2961 if (i
.prefix
[REX_PREFIX
] != 0)
2967 if (i
.prefixes
!= 0 && !intel_syntax
)
2968 as_warn (_("skipping prefixes on this instruction"));
2970 /* It's always a symbol; End frag & setup for relax.
2971 Make sure there is enough room in this frag for the largest
2972 instruction we may generate in md_convert_frag. This is 2
2973 bytes for the opcode and room for the prefix and largest
2975 frag_grow (prefix
+ 2 + 4);
2976 /* Prefix and 1 opcode byte go in fr_fix. */
2977 p
= frag_more (prefix
+ 1);
2978 if (i
.prefix
[DATA_PREFIX
] != 0)
2979 *p
++ = DATA_PREFIX_OPCODE
;
2980 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2981 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2982 *p
++ = i
.prefix
[SEG_PREFIX
];
2983 if (i
.prefix
[REX_PREFIX
] != 0)
2984 *p
++ = i
.prefix
[REX_PREFIX
];
2985 *p
= i
.tm
.base_opcode
;
2987 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2988 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2989 else if ((cpu_arch_flags
& Cpu386
) != 0)
2990 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2992 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2995 sym
= i
.op
[0].disps
->X_add_symbol
;
2996 off
= i
.op
[0].disps
->X_add_number
;
2998 if (i
.op
[0].disps
->X_op
!= O_constant
2999 && i
.op
[0].disps
->X_op
!= O_symbol
)
3001 /* Handle complex expressions. */
3002 sym
= make_expr_symbol (i
.op
[0].disps
);
3006 /* 1 possible extra opcode + 4 byte displacement go in var part.
3007 Pass reloc in fr_var. */
3008 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3018 if (i
.tm
.opcode_modifier
& JumpByte
)
3020 /* This is a loop or jecxz type instruction. */
3022 if (i
.prefix
[ADDR_PREFIX
] != 0)
3024 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3027 /* Pentium4 branch hints. */
3028 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3029 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3031 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3040 if (flag_code
== CODE_16BIT
)
3043 if (i
.prefix
[DATA_PREFIX
] != 0)
3045 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3055 if (i
.prefix
[REX_PREFIX
] != 0)
3057 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3061 if (i
.prefixes
!= 0 && !intel_syntax
)
3062 as_warn (_("skipping prefixes on this instruction"));
3064 p
= frag_more (1 + size
);
3065 *p
++ = i
.tm
.base_opcode
;
3067 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3068 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3070 /* All jumps handled here are signed, but don't use a signed limit
3071 check for 32 and 16 bit jumps as we want to allow wrap around at
3072 4G and 64k respectively. */
3074 fixP
->fx_signed
= 1;
3078 output_interseg_jump ()
3086 if (flag_code
== CODE_16BIT
)
3090 if (i
.prefix
[DATA_PREFIX
] != 0)
3096 if (i
.prefix
[REX_PREFIX
] != 0)
3106 if (i
.prefixes
!= 0 && !intel_syntax
)
3107 as_warn (_("skipping prefixes on this instruction"));
3109 /* 1 opcode; 2 segment; offset */
3110 p
= frag_more (prefix
+ 1 + 2 + size
);
3112 if (i
.prefix
[DATA_PREFIX
] != 0)
3113 *p
++ = DATA_PREFIX_OPCODE
;
3115 if (i
.prefix
[REX_PREFIX
] != 0)
3116 *p
++ = i
.prefix
[REX_PREFIX
];
3118 *p
++ = i
.tm
.base_opcode
;
3119 if (i
.op
[1].imms
->X_op
== O_constant
)
3121 offsetT n
= i
.op
[1].imms
->X_add_number
;
3124 && !fits_in_unsigned_word (n
)
3125 && !fits_in_signed_word (n
))
3127 as_bad (_("16-bit jump out of range"));
3130 md_number_to_chars (p
, n
, size
);
3133 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3134 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3135 if (i
.op
[0].imms
->X_op
!= O_constant
)
3136 as_bad (_("can't handle non absolute segment in `%s'"),
3138 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3144 fragS
*insn_start_frag
;
3145 offsetT insn_start_off
;
3147 /* Tie dwarf2 debug info to the address at the start of the insn.
3148 We can't do this after the insn has been output as the current
3149 frag may have been closed off. eg. by frag_var. */
3150 dwarf2_emit_insn (0);
3152 insn_start_frag
= frag_now
;
3153 insn_start_off
= frag_now_fix ();
3156 if (i
.tm
.opcode_modifier
& Jump
)
3158 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3160 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3161 output_interseg_jump ();
3164 /* Output normal instructions here. */
3168 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3169 have 3 bytes. We may use one more higher byte to specify a prefix
3170 the instruction requires. */
3171 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0
3172 && (i
.tm
.base_opcode
& 0xff000000) != 0)
3174 unsigned int prefix
;
3175 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3177 if (prefix
!= REPE_PREFIX_OPCODE
3178 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3179 add_prefix (prefix
);
3182 if ((i
.tm
.cpu_flags
& CpuPadLock
) == 0
3183 && (i
.tm
.base_opcode
& 0xff0000) != 0)
3184 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3186 /* The prefix bytes. */
3188 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3194 md_number_to_chars (p
, (valueT
) *q
, 1);
3198 /* Now the opcode; be careful about word order here! */
3199 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3201 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3205 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3208 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3213 /* Put out high byte first: can't use md_number_to_chars! */
3214 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3215 *p
= i
.tm
.base_opcode
& 0xff;
3218 /* Now the modrm byte and sib byte (if present). */
3219 if (i
.tm
.opcode_modifier
& Modrm
)
3222 md_number_to_chars (p
,
3223 (valueT
) (i
.rm
.regmem
<< 0
3227 /* If i.rm.regmem == ESP (4)
3228 && i.rm.mode != (Register mode)
3230 ==> need second modrm byte. */
3231 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3233 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3236 md_number_to_chars (p
,
3237 (valueT
) (i
.sib
.base
<< 0
3239 | i
.sib
.scale
<< 6),
3244 if (i
.disp_operands
)
3245 output_disp (insn_start_frag
, insn_start_off
);
3248 output_imm (insn_start_frag
, insn_start_off
);
3256 #endif /* DEBUG386 */
3260 output_disp (insn_start_frag
, insn_start_off
)
3261 fragS
*insn_start_frag
;
3262 offsetT insn_start_off
;
3267 for (n
= 0; n
< i
.operands
; n
++)
3269 if (i
.types
[n
] & Disp
)
3271 if (i
.op
[n
].disps
->X_op
== O_constant
)
3277 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3280 if (i
.types
[n
] & Disp8
)
3282 if (i
.types
[n
] & Disp64
)
3285 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3287 p
= frag_more (size
);
3288 md_number_to_chars (p
, val
, size
);
3292 enum bfd_reloc_code_real reloc_type
;
3295 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3297 /* The PC relative address is computed relative
3298 to the instruction boundary, so in case immediate
3299 fields follows, we need to adjust the value. */
3300 if (pcrel
&& i
.imm_operands
)
3305 for (n1
= 0; n1
< i
.operands
; n1
++)
3306 if (i
.types
[n1
] & Imm
)
3308 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3311 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3313 if (i
.types
[n1
] & Imm64
)
3318 /* We should find the immediate. */
3319 if (n1
== i
.operands
)
3321 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3324 if (i
.types
[n
] & Disp32S
)
3327 if (i
.types
[n
] & (Disp16
| Disp64
))
3330 if (i
.types
[n
] & Disp64
)
3334 p
= frag_more (size
);
3335 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3336 if (reloc_type
== BFD_RELOC_32
3338 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3339 && (i
.op
[n
].disps
->X_op
== O_symbol
3340 || (i
.op
[n
].disps
->X_op
== O_add
3341 && ((symbol_get_value_expression
3342 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3347 if (insn_start_frag
== frag_now
)
3348 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3353 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3354 for (fr
= insn_start_frag
->fr_next
;
3355 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3357 add
+= p
- frag_now
->fr_literal
;
3360 /* We don't support dynamic linking on x86-64 yet. */
3361 if (flag_code
== CODE_64BIT
)
3363 reloc_type
= BFD_RELOC_386_GOTPC
;
3364 i
.op
[n
].disps
->X_add_number
+= add
;
3366 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3367 i
.op
[n
].disps
, pcrel
, reloc_type
);
3374 output_imm (insn_start_frag
, insn_start_off
)
3375 fragS
*insn_start_frag
;
3376 offsetT insn_start_off
;
3381 for (n
= 0; n
< i
.operands
; n
++)
3383 if (i
.types
[n
] & Imm
)
3385 if (i
.op
[n
].imms
->X_op
== O_constant
)
3391 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3394 if (i
.types
[n
] & (Imm8
| Imm8S
))
3396 else if (i
.types
[n
] & Imm64
)
3399 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3401 p
= frag_more (size
);
3402 md_number_to_chars (p
, val
, size
);
3406 /* Not absolute_section.
3407 Need a 32-bit fixup (don't support 8bit
3408 non-absolute imms). Try to support other
3410 enum bfd_reloc_code_real reloc_type
;
3414 if ((i
.types
[n
] & (Imm32S
))
3415 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3417 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3420 if (i
.types
[n
] & (Imm8
| Imm8S
))
3422 if (i
.types
[n
] & Imm64
)
3426 p
= frag_more (size
);
3427 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3429 /* This is tough to explain. We end up with this one if we
3430 * have operands that look like
3431 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3432 * obtain the absolute address of the GOT, and it is strongly
3433 * preferable from a performance point of view to avoid using
3434 * a runtime relocation for this. The actual sequence of
3435 * instructions often look something like:
3440 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3442 * The call and pop essentially return the absolute address
3443 * of the label .L66 and store it in %ebx. The linker itself
3444 * will ultimately change the first operand of the addl so
3445 * that %ebx points to the GOT, but to keep things simple, the
3446 * .o file must have this operand set so that it generates not
3447 * the absolute address of .L66, but the absolute address of
3448 * itself. This allows the linker itself simply treat a GOTPC
3449 * relocation as asking for a pcrel offset to the GOT to be
3450 * added in, and the addend of the relocation is stored in the
3451 * operand field for the instruction itself.
3453 * Our job here is to fix the operand so that it would add
3454 * the correct offset so that %ebx would point to itself. The
3455 * thing that is tricky is that .-.L66 will point to the
3456 * beginning of the instruction, so we need to further modify
3457 * the operand so that it will point to itself. There are
3458 * other cases where you have something like:
3460 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3462 * and here no correction would be required. Internally in
3463 * the assembler we treat operands of this form as not being
3464 * pcrel since the '.' is explicitly mentioned, and I wonder
3465 * whether it would simplify matters to do it this way. Who
3466 * knows. In earlier versions of the PIC patches, the
3467 * pcrel_adjust field was used to store the correction, but
3468 * since the expression is not pcrel, I felt it would be
3469 * confusing to do it this way. */
3471 if (reloc_type
== BFD_RELOC_32
3473 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3474 && (i
.op
[n
].imms
->X_op
== O_symbol
3475 || (i
.op
[n
].imms
->X_op
== O_add
3476 && ((symbol_get_value_expression
3477 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3482 if (insn_start_frag
== frag_now
)
3483 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3488 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3489 for (fr
= insn_start_frag
->fr_next
;
3490 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3492 add
+= p
- frag_now
->fr_literal
;
3495 /* We don't support dynamic linking on x86-64 yet. */
3496 if (flag_code
== CODE_64BIT
)
3498 reloc_type
= BFD_RELOC_386_GOTPC
;
3499 i
.op
[n
].imms
->X_add_number
+= add
;
3501 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3502 i
.op
[n
].imms
, 0, reloc_type
);
3509 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3511 /* Parse operands of the form
3512 <symbol>@GOTOFF+<nnn>
3513 and similar .plt or .got references.
3515 If we find one, set up the correct relocation in RELOC and copy the
3516 input string, minus the `@GOTOFF' into a malloc'd buffer for
3517 parsing by the calling routine. Return this buffer, and if ADJUST
3518 is non-null set it to the length of the string we removed from the
3519 input line. Otherwise return NULL. */
3521 lex_got (reloc
, adjust
)
3522 enum bfd_reloc_code_real
*reloc
;
3525 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3526 static const struct {
3528 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3530 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3531 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3532 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3533 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3534 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3535 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3536 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3537 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3538 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3539 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3540 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3541 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3542 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3547 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3548 if (is_end_of_line
[(unsigned char) *cp
])
3551 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3555 len
= strlen (gotrel
[j
].str
);
3556 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3558 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3561 char *tmpbuf
, *past_reloc
;
3563 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3567 if (GOT_symbol
== NULL
)
3568 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3570 /* Replace the relocation token with ' ', so that
3571 errors like foo@GOTOFF1 will be detected. */
3573 /* The length of the first part of our input line. */
3574 first
= cp
- input_line_pointer
;
3576 /* The second part goes from after the reloc token until
3577 (and including) an end_of_line char. Don't use strlen
3578 here as the end_of_line char may not be a NUL. */
3579 past_reloc
= cp
+ 1 + len
;
3580 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3582 second
= cp
- past_reloc
;
3584 /* Allocate and copy string. The trailing NUL shouldn't
3585 be necessary, but be safe. */
3586 tmpbuf
= xmalloc (first
+ second
+ 2);
3587 memcpy (tmpbuf
, input_line_pointer
, first
);
3588 tmpbuf
[first
] = ' ';
3589 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3590 tmpbuf
[first
+ second
+ 1] = '\0';
3594 as_bad (_("@%s reloc is not supported in %s bit mode"),
3595 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3600 /* Might be a symbol version string. Don't as_bad here. */
3604 /* x86_cons_fix_new is called via the expression parsing code when a
3605 reloc is needed. We use this hook to get the correct .got reloc. */
3606 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3609 x86_cons_fix_new (frag
, off
, len
, exp
)
3615 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3616 got_reloc
= NO_RELOC
;
3617 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3621 x86_cons (exp
, size
)
3627 /* Handle @GOTOFF and the like in an expression. */
3629 char *gotfree_input_line
;
3632 save
= input_line_pointer
;
3633 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3634 if (gotfree_input_line
)
3635 input_line_pointer
= gotfree_input_line
;
3639 if (gotfree_input_line
)
3641 /* expression () has merrily parsed up to the end of line,
3642 or a comma - in the wrong buffer. Transfer how far
3643 input_line_pointer has moved to the right buffer. */
3644 input_line_pointer
= (save
3645 + (input_line_pointer
- gotfree_input_line
)
3647 free (gotfree_input_line
);
3657 #define O_secrel (O_max + 1)
3660 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3666 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3668 if (exp
->X_op
== O_secrel
)
3670 exp
->X_op
= O_symbol
;
3671 r
= BFD_RELOC_32_SECREL
;
3674 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3678 pe_directive_secrel (dummy
)
3679 int dummy ATTRIBUTE_UNUSED
;
3686 if (exp
.X_op
== O_symbol
)
3687 exp
.X_op
= O_secrel
;
3689 emit_expr (&exp
, 4);
3691 while (*input_line_pointer
++ == ',');
3693 input_line_pointer
--;
3694 demand_empty_rest_of_line ();
3699 static int i386_immediate
PARAMS ((char *));
3702 i386_immediate (imm_start
)
3705 char *save_input_line_pointer
;
3707 char *gotfree_input_line
;
3712 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3714 as_bad (_("only 1 or 2 immediate operands are allowed"));
3718 exp
= &im_expressions
[i
.imm_operands
++];
3719 i
.op
[this_operand
].imms
= exp
;
3721 if (is_space_char (*imm_start
))
3724 save_input_line_pointer
= input_line_pointer
;
3725 input_line_pointer
= imm_start
;
3728 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3729 if (gotfree_input_line
)
3730 input_line_pointer
= gotfree_input_line
;
3733 exp_seg
= expression (exp
);
3736 if (*input_line_pointer
)
3737 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3739 input_line_pointer
= save_input_line_pointer
;
3741 if (gotfree_input_line
)
3742 free (gotfree_input_line
);
3745 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3747 /* Missing or bad expr becomes absolute 0. */
3748 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3750 exp
->X_op
= O_constant
;
3751 exp
->X_add_number
= 0;
3752 exp
->X_add_symbol
= (symbolS
*) 0;
3753 exp
->X_op_symbol
= (symbolS
*) 0;
3755 else if (exp
->X_op
== O_constant
)
3757 /* Size it properly later. */
3758 i
.types
[this_operand
] |= Imm64
;
3759 /* If BFD64, sign extend val. */
3760 if (!use_rela_relocations
)
3761 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3762 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3764 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3765 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3766 && exp_seg
!= absolute_section
3767 && exp_seg
!= text_section
3768 && exp_seg
!= data_section
3769 && exp_seg
!= bss_section
3770 && exp_seg
!= undefined_section
3771 && !bfd_is_com_section (exp_seg
))
3773 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3779 /* This is an address. The size of the address will be
3780 determined later, depending on destination register,
3781 suffix, or the default for the section. */
3782 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3788 static char *i386_scale
PARAMS ((char *));
3795 char *save
= input_line_pointer
;
3797 input_line_pointer
= scale
;
3798 val
= get_absolute_expression ();
3804 i
.log2_scale_factor
= 0;
3807 i
.log2_scale_factor
= 1;
3810 i
.log2_scale_factor
= 2;
3813 i
.log2_scale_factor
= 3;
3816 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3818 input_line_pointer
= save
;
3821 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3823 as_warn (_("scale factor of %d without an index register"),
3824 1 << i
.log2_scale_factor
);
3825 #if SCALE1_WHEN_NO_INDEX
3826 i
.log2_scale_factor
= 0;
3829 scale
= input_line_pointer
;
3830 input_line_pointer
= save
;
3834 static int i386_displacement
PARAMS ((char *, char *));
3837 i386_displacement (disp_start
, disp_end
)
3843 char *save_input_line_pointer
;
3845 char *gotfree_input_line
;
3847 int bigdisp
= Disp32
;
3849 if (flag_code
== CODE_64BIT
)
3851 if (i
.prefix
[ADDR_PREFIX
] == 0)
3854 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3856 i
.types
[this_operand
] |= bigdisp
;
3858 exp
= &disp_expressions
[i
.disp_operands
];
3859 i
.op
[this_operand
].disps
= exp
;
3861 save_input_line_pointer
= input_line_pointer
;
3862 input_line_pointer
= disp_start
;
3863 END_STRING_AND_SAVE (disp_end
);
3865 #ifndef GCC_ASM_O_HACK
3866 #define GCC_ASM_O_HACK 0
3869 END_STRING_AND_SAVE (disp_end
+ 1);
3870 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3871 && displacement_string_end
[-1] == '+')
3873 /* This hack is to avoid a warning when using the "o"
3874 constraint within gcc asm statements.
3877 #define _set_tssldt_desc(n,addr,limit,type) \
3878 __asm__ __volatile__ ( \
3880 "movw %w1,2+%0\n\t" \
3882 "movb %b1,4+%0\n\t" \
3883 "movb %4,5+%0\n\t" \
3884 "movb $0,6+%0\n\t" \
3885 "movb %h1,7+%0\n\t" \
3887 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3889 This works great except that the output assembler ends
3890 up looking a bit weird if it turns out that there is
3891 no offset. You end up producing code that looks like:
3904 So here we provide the missing zero. */
3906 *displacement_string_end
= '0';
3910 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3911 if (gotfree_input_line
)
3912 input_line_pointer
= gotfree_input_line
;
3915 exp_seg
= expression (exp
);
3918 if (*input_line_pointer
)
3919 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3921 RESTORE_END_STRING (disp_end
+ 1);
3923 RESTORE_END_STRING (disp_end
);
3924 input_line_pointer
= save_input_line_pointer
;
3926 if (gotfree_input_line
)
3927 free (gotfree_input_line
);
3930 /* We do this to make sure that the section symbol is in
3931 the symbol table. We will ultimately change the relocation
3932 to be relative to the beginning of the section. */
3933 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3934 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3936 if (exp
->X_op
!= O_symbol
)
3938 as_bad (_("bad expression used with @%s"),
3939 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3945 if (S_IS_LOCAL (exp
->X_add_symbol
)
3946 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3947 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3948 exp
->X_op
= O_subtract
;
3949 exp
->X_op_symbol
= GOT_symbol
;
3950 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3951 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3953 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3956 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3958 /* Missing or bad expr becomes absolute 0. */
3959 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3961 exp
->X_op
= O_constant
;
3962 exp
->X_add_number
= 0;
3963 exp
->X_add_symbol
= (symbolS
*) 0;
3964 exp
->X_op_symbol
= (symbolS
*) 0;
3967 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3968 if (exp
->X_op
!= O_constant
3969 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3970 && exp_seg
!= absolute_section
3971 && exp_seg
!= text_section
3972 && exp_seg
!= data_section
3973 && exp_seg
!= bss_section
3974 && exp_seg
!= undefined_section
3975 && !bfd_is_com_section (exp_seg
))
3977 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3981 else if (flag_code
== CODE_64BIT
)
3982 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3986 static int i386_index_check
PARAMS ((const char *));
3988 /* Make sure the memory operand we've been dealt is valid.
3989 Return 1 on success, 0 on a failure. */
3992 i386_index_check (operand_string
)
3993 const char *operand_string
;
3996 #if INFER_ADDR_PREFIX
4002 if (flag_code
== CODE_64BIT
)
4004 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4007 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4008 && (i
.base_reg
->reg_type
!= BaseIndex
4011 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4012 != (RegXX
| BaseIndex
))))
4017 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4021 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4022 != (Reg16
| BaseIndex
)))
4024 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4025 != (Reg16
| BaseIndex
))
4027 && i
.base_reg
->reg_num
< 6
4028 && i
.index_reg
->reg_num
>= 6
4029 && i
.log2_scale_factor
== 0))))
4036 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4038 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4039 != (Reg32
| BaseIndex
))))
4045 #if INFER_ADDR_PREFIX
4046 if (i
.prefix
[ADDR_PREFIX
] == 0)
4048 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4050 /* Change the size of any displacement too. At most one of
4051 Disp16 or Disp32 is set.
4052 FIXME. There doesn't seem to be any real need for separate
4053 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4054 Removing them would probably clean up the code quite a lot. */
4055 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4056 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4061 as_bad (_("`%s' is not a valid base/index expression"),
4065 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4067 flag_code_names
[flag_code
]);
4072 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4076 i386_operand (operand_string
)
4077 char *operand_string
;
4081 char *op_string
= operand_string
;
4083 if (is_space_char (*op_string
))
4086 /* We check for an absolute prefix (differentiating,
4087 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4088 if (*op_string
== ABSOLUTE_PREFIX
)
4091 if (is_space_char (*op_string
))
4093 i
.types
[this_operand
] |= JumpAbsolute
;
4096 /* Check if operand is a register. */
4097 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4098 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4100 /* Check for a segment override by searching for ':' after a
4101 segment register. */
4103 if (is_space_char (*op_string
))
4105 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4110 i
.seg
[i
.mem_operands
] = &es
;
4113 i
.seg
[i
.mem_operands
] = &cs
;
4116 i
.seg
[i
.mem_operands
] = &ss
;
4119 i
.seg
[i
.mem_operands
] = &ds
;
4122 i
.seg
[i
.mem_operands
] = &fs
;
4125 i
.seg
[i
.mem_operands
] = &gs
;
4129 /* Skip the ':' and whitespace. */
4131 if (is_space_char (*op_string
))
4134 if (!is_digit_char (*op_string
)
4135 && !is_identifier_char (*op_string
)
4136 && *op_string
!= '('
4137 && *op_string
!= ABSOLUTE_PREFIX
)
4139 as_bad (_("bad memory operand `%s'"), op_string
);
4142 /* Handle case of %es:*foo. */
4143 if (*op_string
== ABSOLUTE_PREFIX
)
4146 if (is_space_char (*op_string
))
4148 i
.types
[this_operand
] |= JumpAbsolute
;
4150 goto do_memory_reference
;
4154 as_bad (_("junk `%s' after register"), op_string
);
4157 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4158 i
.op
[this_operand
].regs
= r
;
4161 else if (*op_string
== REGISTER_PREFIX
)
4163 as_bad (_("bad register name `%s'"), op_string
);
4166 else if (*op_string
== IMMEDIATE_PREFIX
)
4169 if (i
.types
[this_operand
] & JumpAbsolute
)
4171 as_bad (_("immediate operand illegal with absolute jump"));
4174 if (!i386_immediate (op_string
))
4177 else if (is_digit_char (*op_string
)
4178 || is_identifier_char (*op_string
)
4179 || *op_string
== '(')
4181 /* This is a memory reference of some sort. */
4184 /* Start and end of displacement string expression (if found). */
4185 char *displacement_string_start
;
4186 char *displacement_string_end
;
4188 do_memory_reference
:
4189 if ((i
.mem_operands
== 1
4190 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4191 || i
.mem_operands
== 2)
4193 as_bad (_("too many memory references for `%s'"),
4194 current_templates
->start
->name
);
4198 /* Check for base index form. We detect the base index form by
4199 looking for an ')' at the end of the operand, searching
4200 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4202 base_string
= op_string
+ strlen (op_string
);
4205 if (is_space_char (*base_string
))
4208 /* If we only have a displacement, set-up for it to be parsed later. */
4209 displacement_string_start
= op_string
;
4210 displacement_string_end
= base_string
+ 1;
4212 if (*base_string
== ')')
4215 unsigned int parens_balanced
= 1;
4216 /* We've already checked that the number of left & right ()'s are
4217 equal, so this loop will not be infinite. */
4221 if (*base_string
== ')')
4223 if (*base_string
== '(')
4226 while (parens_balanced
);
4228 temp_string
= base_string
;
4230 /* Skip past '(' and whitespace. */
4232 if (is_space_char (*base_string
))
4235 if (*base_string
== ','
4236 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4237 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4239 displacement_string_end
= temp_string
;
4241 i
.types
[this_operand
] |= BaseIndex
;
4245 base_string
= end_op
;
4246 if (is_space_char (*base_string
))
4250 /* There may be an index reg or scale factor here. */
4251 if (*base_string
== ',')
4254 if (is_space_char (*base_string
))
4257 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4258 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4260 base_string
= end_op
;
4261 if (is_space_char (*base_string
))
4263 if (*base_string
== ',')
4266 if (is_space_char (*base_string
))
4269 else if (*base_string
!= ')')
4271 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4276 else if (*base_string
== REGISTER_PREFIX
)
4278 as_bad (_("bad register name `%s'"), base_string
);
4282 /* Check for scale factor. */
4283 if (*base_string
!= ')')
4285 char *end_scale
= i386_scale (base_string
);
4290 base_string
= end_scale
;
4291 if (is_space_char (*base_string
))
4293 if (*base_string
!= ')')
4295 as_bad (_("expecting `)' after scale factor in `%s'"),
4300 else if (!i
.index_reg
)
4302 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4307 else if (*base_string
!= ')')
4309 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4314 else if (*base_string
== REGISTER_PREFIX
)
4316 as_bad (_("bad register name `%s'"), base_string
);
4321 /* If there's an expression beginning the operand, parse it,
4322 assuming displacement_string_start and
4323 displacement_string_end are meaningful. */
4324 if (displacement_string_start
!= displacement_string_end
)
4326 if (!i386_displacement (displacement_string_start
,
4327 displacement_string_end
))
4331 /* Special case for (%dx) while doing input/output op. */
4333 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4335 && i
.log2_scale_factor
== 0
4336 && i
.seg
[i
.mem_operands
] == 0
4337 && (i
.types
[this_operand
] & Disp
) == 0)
4339 i
.types
[this_operand
] = InOutPortReg
;
4343 if (i386_index_check (operand_string
) == 0)
4349 /* It's not a memory operand; argh! */
4350 as_bad (_("invalid char %s beginning operand %d `%s'"),
4351 output_invalid (*op_string
),
4356 return 1; /* Normal return. */
4359 /* md_estimate_size_before_relax()
4361 Called just before relax() for rs_machine_dependent frags. The x86
4362 assembler uses these frags to handle variable size jump
4365 Any symbol that is now undefined will not become defined.
4366 Return the correct fr_subtype in the frag.
4367 Return the initial "guess for variable size of frag" to caller.
4368 The guess is actually the growth beyond the fixed part. Whatever
4369 we do to grow the fixed or variable part contributes to our
4373 md_estimate_size_before_relax (fragP
, segment
)
4377 /* We've already got fragP->fr_subtype right; all we have to do is
4378 check for un-relaxable symbols. On an ELF system, we can't relax
4379 an externally visible symbol, because it may be overridden by a
4381 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4383 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4384 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4385 || S_IS_WEAK (fragP
->fr_symbol
)))
4389 /* Symbol is undefined in this segment, or we need to keep a
4390 reloc so that weak symbols can be overridden. */
4391 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4392 enum bfd_reloc_code_real reloc_type
;
4393 unsigned char *opcode
;
4396 if (fragP
->fr_var
!= NO_RELOC
)
4397 reloc_type
= fragP
->fr_var
;
4399 reloc_type
= BFD_RELOC_16_PCREL
;
4401 reloc_type
= BFD_RELOC_32_PCREL
;
4403 old_fr_fix
= fragP
->fr_fix
;
4404 opcode
= (unsigned char *) fragP
->fr_opcode
;
4406 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4409 /* Make jmp (0xeb) a (d)word displacement jump. */
4411 fragP
->fr_fix
+= size
;
4412 fix_new (fragP
, old_fr_fix
, size
,
4414 fragP
->fr_offset
, 1,
4420 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4422 /* Negate the condition, and branch past an
4423 unconditional jump. */
4426 /* Insert an unconditional jump. */
4428 /* We added two extra opcode bytes, and have a two byte
4430 fragP
->fr_fix
+= 2 + 2;
4431 fix_new (fragP
, old_fr_fix
+ 2, 2,
4433 fragP
->fr_offset
, 1,
4440 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4445 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4447 fragP
->fr_offset
, 1,
4449 fixP
->fx_signed
= 1;
4453 /* This changes the byte-displacement jump 0x7N
4454 to the (d)word-displacement jump 0x0f,0x8N. */
4455 opcode
[1] = opcode
[0] + 0x10;
4456 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4457 /* We've added an opcode byte. */
4458 fragP
->fr_fix
+= 1 + size
;
4459 fix_new (fragP
, old_fr_fix
+ 1, size
,
4461 fragP
->fr_offset
, 1,
4466 BAD_CASE (fragP
->fr_subtype
);
4470 return fragP
->fr_fix
- old_fr_fix
;
4473 /* Guess size depending on current relax state. Initially the relax
4474 state will correspond to a short jump and we return 1, because
4475 the variable part of the frag (the branch offset) is one byte
4476 long. However, we can relax a section more than once and in that
4477 case we must either set fr_subtype back to the unrelaxed state,
4478 or return the value for the appropriate branch. */
4479 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4482 /* Called after relax() is finished.
4484 In: Address of frag.
4485 fr_type == rs_machine_dependent.
4486 fr_subtype is what the address relaxed to.
4488 Out: Any fixSs and constants are set up.
4489 Caller will turn frag into a ".space 0". */
4492 md_convert_frag (abfd
, sec
, fragP
)
4493 bfd
*abfd ATTRIBUTE_UNUSED
;
4494 segT sec ATTRIBUTE_UNUSED
;
4497 unsigned char *opcode
;
4498 unsigned char *where_to_put_displacement
= NULL
;
4499 offsetT target_address
;
4500 offsetT opcode_address
;
4501 unsigned int extension
= 0;
4502 offsetT displacement_from_opcode_start
;
4504 opcode
= (unsigned char *) fragP
->fr_opcode
;
4506 /* Address we want to reach in file space. */
4507 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4509 /* Address opcode resides at in file space. */
4510 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4512 /* Displacement from opcode start to fill into instruction. */
4513 displacement_from_opcode_start
= target_address
- opcode_address
;
4515 if ((fragP
->fr_subtype
& BIG
) == 0)
4517 /* Don't have to change opcode. */
4518 extension
= 1; /* 1 opcode + 1 displacement */
4519 where_to_put_displacement
= &opcode
[1];
4523 if (no_cond_jump_promotion
4524 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4525 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4527 switch (fragP
->fr_subtype
)
4529 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4530 extension
= 4; /* 1 opcode + 4 displacement */
4532 where_to_put_displacement
= &opcode
[1];
4535 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4536 extension
= 2; /* 1 opcode + 2 displacement */
4538 where_to_put_displacement
= &opcode
[1];
4541 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4542 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4543 extension
= 5; /* 2 opcode + 4 displacement */
4544 opcode
[1] = opcode
[0] + 0x10;
4545 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4546 where_to_put_displacement
= &opcode
[2];
4549 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4550 extension
= 3; /* 2 opcode + 2 displacement */
4551 opcode
[1] = opcode
[0] + 0x10;
4552 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4553 where_to_put_displacement
= &opcode
[2];
4556 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4561 where_to_put_displacement
= &opcode
[3];
4565 BAD_CASE (fragP
->fr_subtype
);
4570 /* Now put displacement after opcode. */
4571 md_number_to_chars ((char *) where_to_put_displacement
,
4572 (valueT
) (displacement_from_opcode_start
- extension
),
4573 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4574 fragP
->fr_fix
+= extension
;
4577 /* Size of byte displacement jmp. */
4578 int md_short_jump_size
= 2;
4580 /* Size of dword displacement jmp. */
4581 int md_long_jump_size
= 5;
4583 /* Size of relocation record. */
4584 const int md_reloc_size
= 8;
4587 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4589 addressT from_addr
, to_addr
;
4590 fragS
*frag ATTRIBUTE_UNUSED
;
4591 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4595 offset
= to_addr
- (from_addr
+ 2);
4596 /* Opcode for byte-disp jump. */
4597 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4598 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4602 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4604 addressT from_addr
, to_addr
;
4605 fragS
*frag ATTRIBUTE_UNUSED
;
4606 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4610 offset
= to_addr
- (from_addr
+ 5);
4611 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4612 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4615 /* Apply a fixup (fixS) to segment data, once it has been determined
4616 by our caller that we have all the info we need to fix it up.
4618 On the 386, immediates, displacements, and data pointers are all in
4619 the same (little-endian) format, so we don't need to care about which
4623 md_apply_fix3 (fixP
, valP
, seg
)
4624 /* The fix we're to put in. */
4626 /* Pointer to the value of the bits. */
4628 /* Segment fix is from. */
4629 segT seg ATTRIBUTE_UNUSED
;
4631 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4632 valueT value
= *valP
;
4634 #if !defined (TE_Mach)
4637 switch (fixP
->fx_r_type
)
4643 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4646 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4649 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4654 if (fixP
->fx_addsy
!= NULL
4655 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4656 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4657 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4658 && !use_rela_relocations
)
4660 /* This is a hack. There should be a better way to handle this.
4661 This covers for the fact that bfd_install_relocation will
4662 subtract the current location (for partial_inplace, PC relative
4663 relocations); see more below. */
4665 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4667 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4670 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4673 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4675 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4678 || (symbol_section_p (fixP
->fx_addsy
)
4679 && sym_seg
!= absolute_section
))
4680 && !generic_force_reloc (fixP
))
4682 /* Yes, we add the values in twice. This is because
4683 bfd_install_relocation subtracts them out again. I think
4684 bfd_install_relocation is broken, but I don't dare change
4686 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4690 #if defined (OBJ_COFF) && defined (TE_PE)
4691 /* For some reason, the PE format does not store a section
4692 address offset for a PC relative symbol. */
4693 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4694 value
+= md_pcrel_from (fixP
);
4698 /* Fix a few things - the dynamic linker expects certain values here,
4699 and we must not disappoint it. */
4700 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4701 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4703 switch (fixP
->fx_r_type
)
4705 case BFD_RELOC_386_PLT32
:
4706 case BFD_RELOC_X86_64_PLT32
:
4707 /* Make the jump instruction point to the address of the operand. At
4708 runtime we merely add the offset to the actual PLT entry. */
4712 case BFD_RELOC_386_TLS_GD
:
4713 case BFD_RELOC_386_TLS_LDM
:
4714 case BFD_RELOC_386_TLS_IE_32
:
4715 case BFD_RELOC_386_TLS_IE
:
4716 case BFD_RELOC_386_TLS_GOTIE
:
4717 case BFD_RELOC_X86_64_TLSGD
:
4718 case BFD_RELOC_X86_64_TLSLD
:
4719 case BFD_RELOC_X86_64_GOTTPOFF
:
4720 value
= 0; /* Fully resolved at runtime. No addend. */
4722 case BFD_RELOC_386_TLS_LE
:
4723 case BFD_RELOC_386_TLS_LDO_32
:
4724 case BFD_RELOC_386_TLS_LE_32
:
4725 case BFD_RELOC_X86_64_DTPOFF32
:
4726 case BFD_RELOC_X86_64_TPOFF32
:
4727 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4730 case BFD_RELOC_386_GOT32
:
4731 case BFD_RELOC_X86_64_GOT32
:
4732 value
= 0; /* Fully resolved at runtime. No addend. */
4735 case BFD_RELOC_VTABLE_INHERIT
:
4736 case BFD_RELOC_VTABLE_ENTRY
:
4743 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4745 #endif /* !defined (TE_Mach) */
4747 /* Are we finished with this relocation now? */
4748 if (fixP
->fx_addsy
== NULL
)
4750 else if (use_rela_relocations
)
4752 fixP
->fx_no_overflow
= 1;
4753 /* Remember value for tc_gen_reloc. */
4754 fixP
->fx_addnumber
= value
;
4758 md_number_to_chars (p
, value
, fixP
->fx_size
);
4761 #define MAX_LITTLENUMS 6
4763 /* Turn the string pointed to by litP into a floating point constant
4764 of type TYPE, and emit the appropriate bytes. The number of
4765 LITTLENUMS emitted is stored in *SIZEP. An error message is
4766 returned, or NULL on OK. */
4769 md_atof (type
, litP
, sizeP
)
4775 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4776 LITTLENUM_TYPE
*wordP
;
4798 return _("Bad call to md_atof ()");
4800 t
= atof_ieee (input_line_pointer
, type
, words
);
4802 input_line_pointer
= t
;
4804 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4805 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4806 the bigendian 386. */
4807 for (wordP
= words
+ prec
- 1; prec
--;)
4809 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4810 litP
+= sizeof (LITTLENUM_TYPE
);
4815 char output_invalid_buf
[8];
4822 sprintf (output_invalid_buf
, "'%c'", c
);
4824 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4825 return output_invalid_buf
;
4828 /* REG_STRING starts *before* REGISTER_PREFIX. */
4830 static const reg_entry
*
4831 parse_register (reg_string
, end_op
)
4835 char *s
= reg_string
;
4837 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4840 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4841 if (*s
== REGISTER_PREFIX
)
4844 if (is_space_char (*s
))
4848 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4850 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4851 return (const reg_entry
*) NULL
;
4855 /* For naked regs, make sure that we are not dealing with an identifier.
4856 This prevents confusing an identifier like `eax_var' with register
4858 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4859 return (const reg_entry
*) NULL
;
4863 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4865 /* Handle floating point regs, allowing spaces in the (i) part. */
4866 if (r
== i386_regtab
/* %st is first entry of table */)
4868 if (is_space_char (*s
))
4873 if (is_space_char (*s
))
4875 if (*s
>= '0' && *s
<= '7')
4877 r
= &i386_float_regtab
[*s
- '0'];
4879 if (is_space_char (*s
))
4887 /* We have "%st(" then garbage. */
4888 return (const reg_entry
*) NULL
;
4893 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
4894 && flag_code
!= CODE_64BIT
)
4895 return (const reg_entry
*) NULL
;
4900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4901 const char *md_shortopts
= "kVQ:sqn";
4903 const char *md_shortopts
= "qn";
4906 struct option md_longopts
[] = {
4907 #define OPTION_32 (OPTION_MD_BASE + 0)
4908 {"32", no_argument
, NULL
, OPTION_32
},
4909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4910 #define OPTION_64 (OPTION_MD_BASE + 1)
4911 {"64", no_argument
, NULL
, OPTION_64
},
4913 {NULL
, no_argument
, NULL
, 0}
4915 size_t md_longopts_size
= sizeof (md_longopts
);
4918 md_parse_option (c
, arg
)
4920 char *arg ATTRIBUTE_UNUSED
;
4925 optimize_align_code
= 0;
4932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4933 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4934 should be emitted or not. FIXME: Not implemented. */
4938 /* -V: SVR4 argument to print version ID. */
4940 print_version_id ();
4943 /* -k: Ignore for FreeBSD compatibility. */
4948 /* -s: On i386 Solaris, this tells the native assembler to use
4949 .stab instead of .stab.excl. We always use .stab anyhow. */
4954 const char **list
, **l
;
4956 list
= bfd_target_list ();
4957 for (l
= list
; *l
!= NULL
; l
++)
4958 if (strcmp (*l
, "elf64-x86-64") == 0)
4960 default_arch
= "x86_64";
4964 as_fatal (_("No compiled in support for x86_64"));
4971 default_arch
= "i386";
4981 md_show_usage (stream
)
4984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4985 fprintf (stream
, _("\
4987 -V print assembler version number\n\
4989 -n Do not optimize code alignment\n\
4990 -q quieten some warnings\n\
4993 fprintf (stream
, _("\
4994 -n Do not optimize code alignment\n\
4995 -q quieten some warnings\n"));
4999 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5000 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5002 /* Pick the target format to use. */
5005 i386_target_format ()
5007 if (!strcmp (default_arch
, "x86_64"))
5008 set_code_flag (CODE_64BIT
);
5009 else if (!strcmp (default_arch
, "i386"))
5010 set_code_flag (CODE_32BIT
);
5012 as_fatal (_("Unknown architecture"));
5013 switch (OUTPUT_FLAVOR
)
5015 #ifdef OBJ_MAYBE_AOUT
5016 case bfd_target_aout_flavour
:
5017 return AOUT_TARGET_FORMAT
;
5019 #ifdef OBJ_MAYBE_COFF
5020 case bfd_target_coff_flavour
:
5023 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5024 case bfd_target_elf_flavour
:
5026 if (flag_code
== CODE_64BIT
)
5027 use_rela_relocations
= 1;
5028 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5037 #endif /* OBJ_MAYBE_ more than one */
5039 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5040 void i386_elf_emit_arch_note ()
5042 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5043 && cpu_arch_name
!= NULL
)
5046 asection
*seg
= now_seg
;
5047 subsegT subseg
= now_subseg
;
5048 Elf_Internal_Note i_note
;
5049 Elf_External_Note e_note
;
5050 asection
*note_secp
;
5053 /* Create the .note section. */
5054 note_secp
= subseg_new (".note", 0);
5055 bfd_set_section_flags (stdoutput
,
5057 SEC_HAS_CONTENTS
| SEC_READONLY
);
5059 /* Process the arch string. */
5060 len
= strlen (cpu_arch_name
);
5062 i_note
.namesz
= len
+ 1;
5064 i_note
.type
= NT_ARCH
;
5065 p
= frag_more (sizeof (e_note
.namesz
));
5066 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5067 p
= frag_more (sizeof (e_note
.descsz
));
5068 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5069 p
= frag_more (sizeof (e_note
.type
));
5070 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5071 p
= frag_more (len
+ 1);
5072 strcpy (p
, cpu_arch_name
);
5074 frag_align (2, 0, 0);
5076 subseg_set (seg
, subseg
);
5082 md_undefined_symbol (name
)
5085 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5086 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5087 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5088 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5092 if (symbol_find (name
))
5093 as_bad (_("GOT already in symbol table"));
5094 GOT_symbol
= symbol_new (name
, undefined_section
,
5095 (valueT
) 0, &zero_address_frag
);
5102 /* Round up a section size to the appropriate boundary. */
5105 md_section_align (segment
, size
)
5106 segT segment ATTRIBUTE_UNUSED
;
5109 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5110 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5112 /* For a.out, force the section size to be aligned. If we don't do
5113 this, BFD will align it for us, but it will not write out the
5114 final bytes of the section. This may be a bug in BFD, but it is
5115 easier to fix it here since that is how the other a.out targets
5119 align
= bfd_get_section_alignment (stdoutput
, segment
);
5120 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5127 /* On the i386, PC-relative offsets are relative to the start of the
5128 next instruction. That is, the address of the offset, plus its
5129 size, since the offset is always the last part of the insn. */
5132 md_pcrel_from (fixP
)
5135 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5142 int ignore ATTRIBUTE_UNUSED
;
5146 temp
= get_absolute_expression ();
5147 subseg_set (bss_section
, (subsegT
) temp
);
5148 demand_empty_rest_of_line ();
5154 i386_validate_fix (fixp
)
5157 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5159 /* GOTOFF relocation are nonsense in 64bit mode. */
5160 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5162 if (flag_code
!= CODE_64BIT
)
5164 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5168 if (flag_code
== CODE_64BIT
)
5170 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5177 tc_gen_reloc (section
, fixp
)
5178 asection
*section ATTRIBUTE_UNUSED
;
5182 bfd_reloc_code_real_type code
;
5184 switch (fixp
->fx_r_type
)
5186 case BFD_RELOC_X86_64_PLT32
:
5187 case BFD_RELOC_X86_64_GOT32
:
5188 case BFD_RELOC_X86_64_GOTPCREL
:
5189 case BFD_RELOC_386_PLT32
:
5190 case BFD_RELOC_386_GOT32
:
5191 case BFD_RELOC_386_GOTOFF
:
5192 case BFD_RELOC_386_GOTPC
:
5193 case BFD_RELOC_386_TLS_GD
:
5194 case BFD_RELOC_386_TLS_LDM
:
5195 case BFD_RELOC_386_TLS_LDO_32
:
5196 case BFD_RELOC_386_TLS_IE_32
:
5197 case BFD_RELOC_386_TLS_IE
:
5198 case BFD_RELOC_386_TLS_GOTIE
:
5199 case BFD_RELOC_386_TLS_LE_32
:
5200 case BFD_RELOC_386_TLS_LE
:
5201 case BFD_RELOC_X86_64_32S
:
5202 case BFD_RELOC_X86_64_TLSGD
:
5203 case BFD_RELOC_X86_64_TLSLD
:
5204 case BFD_RELOC_X86_64_DTPOFF32
:
5205 case BFD_RELOC_X86_64_GOTTPOFF
:
5206 case BFD_RELOC_X86_64_TPOFF32
:
5208 case BFD_RELOC_VTABLE_ENTRY
:
5209 case BFD_RELOC_VTABLE_INHERIT
:
5211 case BFD_RELOC_32_SECREL
:
5213 code
= fixp
->fx_r_type
;
5218 switch (fixp
->fx_size
)
5221 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5222 _("can not do %d byte pc-relative relocation"),
5224 code
= BFD_RELOC_32_PCREL
;
5226 case 1: code
= BFD_RELOC_8_PCREL
; break;
5227 case 2: code
= BFD_RELOC_16_PCREL
; break;
5228 case 4: code
= BFD_RELOC_32_PCREL
; break;
5233 switch (fixp
->fx_size
)
5236 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5237 _("can not do %d byte relocation"),
5239 code
= BFD_RELOC_32
;
5241 case 1: code
= BFD_RELOC_8
; break;
5242 case 2: code
= BFD_RELOC_16
; break;
5243 case 4: code
= BFD_RELOC_32
; break;
5245 case 8: code
= BFD_RELOC_64
; break;
5252 if (code
== BFD_RELOC_32
5254 && fixp
->fx_addsy
== GOT_symbol
)
5256 /* We don't support GOTPC on 64bit targets. */
5257 if (flag_code
== CODE_64BIT
)
5259 code
= BFD_RELOC_386_GOTPC
;
5262 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5263 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5264 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5266 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5269 if (S_IS_WEAK (fixp
->fx_addsy
))
5270 rel
->addend
= rel
->address
- (*rel
->sym_ptr_ptr
)->value
+ 4;
5273 if (!use_rela_relocations
)
5275 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5276 vtable entry to be used in the relocation's section offset. */
5277 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5278 rel
->address
= fixp
->fx_offset
;
5282 /* Use the rela in 64bit mode. */
5285 if (!fixp
->fx_pcrel
)
5286 rel
->addend
= fixp
->fx_offset
;
5290 case BFD_RELOC_X86_64_PLT32
:
5291 case BFD_RELOC_X86_64_GOT32
:
5292 case BFD_RELOC_X86_64_GOTPCREL
:
5293 case BFD_RELOC_X86_64_TLSGD
:
5294 case BFD_RELOC_X86_64_TLSLD
:
5295 case BFD_RELOC_X86_64_GOTTPOFF
:
5296 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5299 rel
->addend
= (section
->vma
5301 + fixp
->fx_addnumber
5302 + md_pcrel_from (fixp
));
5307 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5308 if (rel
->howto
== NULL
)
5310 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5311 _("cannot represent relocation type %s"),
5312 bfd_get_reloc_code_name (code
));
5313 /* Set howto to a garbage value so that we can keep going. */
5314 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5315 assert (rel
->howto
!= NULL
);
5322 /* Parse operands using Intel syntax. This implements a recursive descent
5323 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5326 FIXME: We do not recognize the full operand grammar defined in the MASM
5327 documentation. In particular, all the structure/union and
5328 high-level macro operands are missing.
5330 Uppercase words are terminals, lower case words are non-terminals.
5331 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5332 bars '|' denote choices. Most grammar productions are implemented in
5333 functions called 'intel_<production>'.
5335 Initial production is 'expr'.
5337 addOp + | - | & | \| | << | >>
5341 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5343 constant digits [[ radixOverride ]]
5345 dataType BYTE | WORD | DWORD | QWORD | XWORD
5379 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5380 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5382 hexdigit a | b | c | d | e | f
5383 | A | B | C | D | E | F
5393 register specialRegister
5397 segmentRegister CS | DS | ES | FS | GS | SS
5399 specialRegister CR0 | CR2 | CR3
5400 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5401 | TR3 | TR4 | TR5 | TR6 | TR7
5403 We simplify the grammar in obvious places (e.g., register parsing is
5404 done by calling parse_register) and eliminate immediate left recursion
5405 to implement a recursive-descent parser.
5446 /* Parsing structure for the intel syntax parser. Used to implement the
5447 semantic actions for the operand grammar. */
5448 struct intel_parser_s
5450 char *op_string
; /* The string being parsed. */
5451 int got_a_float
; /* Whether the operand is a float. */
5452 int op_modifier
; /* Operand modifier. */
5453 int is_mem
; /* 1 if operand is memory reference. */
5454 const reg_entry
*reg
; /* Last register reference found. */
5455 char *disp
; /* Displacement string being built. */
5458 static struct intel_parser_s intel_parser
;
5460 /* Token structure for parsing intel syntax. */
5463 int code
; /* Token code. */
5464 const reg_entry
*reg
; /* Register entry for register tokens. */
5465 char *str
; /* String representation. */
5468 static struct intel_token cur_token
, prev_token
;
5470 /* Token codes for the intel parser. Since T_SHORT is already used
5471 by COFF, undefine it first to prevent a warning. */
5485 #define T_SHIFTOP 12
5487 /* Prototypes for intel parser functions. */
5488 static int intel_match_token
PARAMS ((int code
));
5489 static void intel_get_token
PARAMS ((void));
5490 static void intel_putback_token
PARAMS ((void));
5491 static int intel_expr
PARAMS ((void));
5492 static int intel_e05
PARAMS ((void));
5493 static int intel_e05_1
PARAMS ((void));
5494 static int intel_e06
PARAMS ((void));
5495 static int intel_e06_1
PARAMS ((void));
5496 static int intel_e09
PARAMS ((void));
5497 static int intel_e09_1
PARAMS ((void));
5498 static int intel_e10
PARAMS ((void));
5499 static int intel_e10_1
PARAMS ((void));
5500 static int intel_e11
PARAMS ((void));
5503 i386_intel_operand (operand_string
, got_a_float
)
5504 char *operand_string
;
5510 /* Initialize token holders. */
5511 cur_token
.code
= prev_token
.code
= T_NIL
;
5512 cur_token
.reg
= prev_token
.reg
= NULL
;
5513 cur_token
.str
= prev_token
.str
= NULL
;
5515 /* Initialize parser structure. */
5516 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5519 strcpy (intel_parser
.op_string
, operand_string
);
5520 intel_parser
.got_a_float
= got_a_float
;
5521 intel_parser
.op_modifier
= -1;
5522 intel_parser
.is_mem
= 0;
5523 intel_parser
.reg
= NULL
;
5524 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5525 if (intel_parser
.disp
== NULL
)
5527 intel_parser
.disp
[0] = '\0';
5529 /* Read the first token and start the parser. */
5531 ret
= intel_expr ();
5535 /* If we found a memory reference, hand it over to i386_displacement
5536 to fill in the rest of the operand fields. */
5537 if (intel_parser
.is_mem
)
5539 if ((i
.mem_operands
== 1
5540 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5541 || i
.mem_operands
== 2)
5543 as_bad (_("too many memory references for '%s'"),
5544 current_templates
->start
->name
);
5549 char *s
= intel_parser
.disp
;
5552 /* Add the displacement expression. */
5554 ret
= i386_displacement (s
, s
+ strlen (s
));
5556 ret
= i386_index_check (operand_string
);
5560 /* Constant and OFFSET expressions are handled by i386_immediate. */
5561 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5562 || intel_parser
.reg
== NULL
)
5563 ret
= i386_immediate (intel_parser
.disp
);
5567 free (intel_parser
.disp
);
5577 /* expr SHORT e05 */
5578 if (cur_token
.code
== T_SHORT
)
5580 intel_parser
.op_modifier
= SHORT
;
5581 intel_match_token (T_SHORT
);
5583 return (intel_e05 ());
5588 return intel_e05 ();
5598 return (intel_e06 () && intel_e05_1 ());
5604 /* e05' addOp e06 e05' */
5605 if (cur_token
.code
== '+' || cur_token
.code
== '-'
5606 || cur_token
.code
== '&' || cur_token
.code
== '|'
5607 || cur_token
.code
== T_SHIFTOP
)
5609 strcat (intel_parser
.disp
, cur_token
.str
);
5610 intel_match_token (cur_token
.code
);
5612 return (intel_e06 () && intel_e05_1 ());
5627 return (intel_e09 () && intel_e06_1 ());
5633 /* e06' mulOp e09 e06' */
5634 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5636 strcat (intel_parser
.disp
, cur_token
.str
);
5637 intel_match_token (cur_token
.code
);
5639 return (intel_e09 () && intel_e06_1 ());
5647 /* e09 OFFSET e10 e09'
5656 /* e09 OFFSET e10 e09' */
5657 if (cur_token
.code
== T_OFFSET
)
5659 intel_parser
.is_mem
= 0;
5660 intel_parser
.op_modifier
= OFFSET_FLAT
;
5661 intel_match_token (T_OFFSET
);
5663 return (intel_e10 () && intel_e09_1 ());
5668 return (intel_e10 () && intel_e09_1 ());
5674 /* e09' PTR e10 e09' */
5675 if (cur_token
.code
== T_PTR
)
5677 if (prev_token
.code
== T_BYTE
)
5678 i
.suffix
= BYTE_MNEM_SUFFIX
;
5680 else if (prev_token
.code
== T_WORD
)
5682 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5683 i
.suffix
= SHORT_MNEM_SUFFIX
;
5685 i
.suffix
= WORD_MNEM_SUFFIX
;
5688 else if (prev_token
.code
== T_DWORD
)
5690 if (intel_parser
.got_a_float
== 1) /* "f..." */
5691 i
.suffix
= SHORT_MNEM_SUFFIX
;
5693 i
.suffix
= LONG_MNEM_SUFFIX
;
5696 else if (prev_token
.code
== T_QWORD
)
5698 if (intel_parser
.got_a_float
== 1) /* "f..." */
5699 i
.suffix
= LONG_MNEM_SUFFIX
;
5701 i
.suffix
= QWORD_MNEM_SUFFIX
;
5704 else if (prev_token
.code
== T_XWORD
)
5705 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5709 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
5713 intel_match_token (T_PTR
);
5715 return (intel_e10 () && intel_e09_1 ());
5718 /* e09 : e10 e09' */
5719 else if (cur_token
.code
== ':')
5721 /* Mark as a memory operand only if it's not already known to be an
5722 offset expression. */
5723 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5724 intel_parser
.is_mem
= 1;
5726 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5741 return (intel_e11 () && intel_e10_1 ());
5747 /* e10' [ expr ] e10' */
5748 if (cur_token
.code
== '[')
5750 intel_match_token ('[');
5752 /* Mark as a memory operand only if it's not already known to be an
5753 offset expression. If it's an offset expression, we need to keep
5755 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5756 intel_parser
.is_mem
= 1;
5758 strcat (intel_parser
.disp
, "[");
5760 /* Add a '+' to the displacement string if necessary. */
5761 if (*intel_parser
.disp
!= '\0'
5762 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5763 strcat (intel_parser
.disp
, "+");
5765 if (intel_expr () && intel_match_token (']'))
5767 /* Preserve brackets when the operand is an offset expression. */
5768 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5769 strcat (intel_parser
.disp
, "]");
5771 return intel_e10_1 ();
5799 if (cur_token
.code
== '(')
5801 intel_match_token ('(');
5802 strcat (intel_parser
.disp
, "(");
5804 if (intel_expr () && intel_match_token (')'))
5806 strcat (intel_parser
.disp
, ")");
5814 else if (cur_token
.code
== '~')
5816 strcat (intel_parser
.disp
, "~");
5817 intel_match_token ('~');
5819 return (intel_e11 ());
5823 else if (cur_token
.code
== '[')
5825 intel_match_token ('[');
5827 /* Mark as a memory operand only if it's not already known to be an
5828 offset expression. If it's an offset expression, we need to keep
5830 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5831 intel_parser
.is_mem
= 1;
5833 strcat (intel_parser
.disp
, "[");
5835 /* Operands for jump/call inside brackets denote absolute addresses. */
5836 if (current_templates
->start
->opcode_modifier
& Jump
5837 || current_templates
->start
->opcode_modifier
& JumpDword
5838 || current_templates
->start
->opcode_modifier
& JumpByte
5839 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5840 i
.types
[this_operand
] |= JumpAbsolute
;
5842 /* Add a '+' to the displacement string if necessary. */
5843 if (*intel_parser
.disp
!= '\0'
5844 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5845 strcat (intel_parser
.disp
, "+");
5847 if (intel_expr () && intel_match_token (']'))
5849 /* Preserve brackets when the operand is an offset expression. */
5850 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5851 strcat (intel_parser
.disp
, "]");
5864 else if (cur_token
.code
== T_BYTE
5865 || cur_token
.code
== T_WORD
5866 || cur_token
.code
== T_DWORD
5867 || cur_token
.code
== T_QWORD
5868 || cur_token
.code
== T_XWORD
)
5870 intel_match_token (cur_token
.code
);
5877 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5879 strcat (intel_parser
.disp
, cur_token
.str
);
5880 intel_match_token (cur_token
.code
);
5882 /* Mark as a memory operand only if it's not already known to be an
5883 offset expression. */
5884 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5885 intel_parser
.is_mem
= 1;
5891 else if (cur_token
.code
== T_REG
)
5893 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5895 intel_match_token (T_REG
);
5897 /* Check for segment change. */
5898 if (cur_token
.code
== ':')
5900 if (reg
->reg_type
& (SReg2
| SReg3
))
5902 switch (reg
->reg_num
)
5905 i
.seg
[i
.mem_operands
] = &es
;
5908 i
.seg
[i
.mem_operands
] = &cs
;
5911 i
.seg
[i
.mem_operands
] = &ss
;
5914 i
.seg
[i
.mem_operands
] = &ds
;
5917 i
.seg
[i
.mem_operands
] = &fs
;
5920 i
.seg
[i
.mem_operands
] = &gs
;
5926 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5931 /* Not a segment register. Check for register scaling. */
5932 else if (cur_token
.code
== '*')
5934 if (!intel_parser
.is_mem
)
5936 as_bad (_("Register scaling only allowed in memory operands."));
5940 /* What follows must be a valid scale. */
5941 if (intel_match_token ('*')
5942 && strchr ("01248", *cur_token
.str
))
5945 i
.types
[this_operand
] |= BaseIndex
;
5947 /* Set the scale after setting the register (otherwise,
5948 i386_scale will complain) */
5949 i386_scale (cur_token
.str
);
5950 intel_match_token (T_CONST
);
5954 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5960 /* No scaling. If this is a memory operand, the register is either a
5961 base register (first occurrence) or an index register (second
5963 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5965 if (i
.base_reg
&& i
.index_reg
)
5967 as_bad (_("Too many register references in memory operand."));
5971 if (i
.base_reg
== NULL
)
5976 i
.types
[this_operand
] |= BaseIndex
;
5979 /* Offset modifier. Add the register to the displacement string to be
5980 parsed as an immediate expression after we're done. */
5981 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5982 strcat (intel_parser
.disp
, reg
->reg_name
);
5984 /* It's neither base nor index nor offset. */
5987 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5988 i
.op
[this_operand
].regs
= reg
;
5992 /* Since registers are not part of the displacement string (except
5993 when we're parsing offset operands), we may need to remove any
5994 preceding '+' from the displacement string. */
5995 if (*intel_parser
.disp
!= '\0'
5996 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5998 char *s
= intel_parser
.disp
;
5999 s
+= strlen (s
) - 1;
6008 else if (cur_token
.code
== T_ID
)
6010 /* Add the identifier to the displacement string. */
6011 strcat (intel_parser
.disp
, cur_token
.str
);
6012 intel_match_token (T_ID
);
6014 /* The identifier represents a memory reference only if it's not
6015 preceded by an offset modifier. */
6016 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6017 intel_parser
.is_mem
= 1;
6023 else if (cur_token
.code
== T_CONST
6024 || cur_token
.code
== '-'
6025 || cur_token
.code
== '+')
6029 /* Allow constants that start with `+' or `-'. */
6030 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6032 strcat (intel_parser
.disp
, cur_token
.str
);
6033 intel_match_token (cur_token
.code
);
6034 if (cur_token
.code
!= T_CONST
)
6036 as_bad (_("Syntax error. Expecting a constant. Got `%s'."),
6042 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6043 if (save_str
== NULL
)
6045 strcpy (save_str
, cur_token
.str
);
6047 /* Get the next token to check for register scaling. */
6048 intel_match_token (cur_token
.code
);
6050 /* Check if this constant is a scaling factor for an index register. */
6051 if (cur_token
.code
== '*')
6053 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6055 if (!intel_parser
.is_mem
)
6057 as_bad (_("Register scaling only allowed in memory operands."));
6061 /* The constant is followed by `* reg', so it must be
6063 if (strchr ("01248", *save_str
))
6065 i
.index_reg
= cur_token
.reg
;
6066 i
.types
[this_operand
] |= BaseIndex
;
6068 /* Set the scale after setting the register (otherwise,
6069 i386_scale will complain) */
6070 i386_scale (save_str
);
6071 intel_match_token (T_REG
);
6073 /* Since registers are not part of the displacement
6074 string, we may need to remove any preceding '+' from
6075 the displacement string. */
6076 if (*intel_parser
.disp
!= '\0')
6078 char *s
= intel_parser
.disp
;
6079 s
+= strlen (s
) - 1;
6092 /* The constant was not used for register scaling. Since we have
6093 already consumed the token following `*' we now need to put it
6094 back in the stream. */
6096 intel_putback_token ();
6099 /* Add the constant to the displacement string. */
6100 strcat (intel_parser
.disp
, save_str
);
6106 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6110 /* Match the given token against cur_token. If they match, read the next
6111 token from the operand string. */
6113 intel_match_token (code
)
6116 if (cur_token
.code
== code
)
6123 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6128 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6133 const reg_entry
*reg
;
6134 struct intel_token new_token
;
6136 new_token
.code
= T_NIL
;
6137 new_token
.reg
= NULL
;
6138 new_token
.str
= NULL
;
6140 /* Free the memory allocated to the previous token and move
6141 cur_token to prev_token. */
6143 free (prev_token
.str
);
6145 prev_token
= cur_token
;
6147 /* Skip whitespace. */
6148 while (is_space_char (*intel_parser
.op_string
))
6149 intel_parser
.op_string
++;
6151 /* Return an empty token if we find nothing else on the line. */
6152 if (*intel_parser
.op_string
== '\0')
6154 cur_token
= new_token
;
6158 /* The new token cannot be larger than the remainder of the operand
6160 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6161 if (new_token
.str
== NULL
)
6163 new_token
.str
[0] = '\0';
6165 if (strchr ("0123456789", *intel_parser
.op_string
))
6167 char *p
= new_token
.str
;
6168 char *q
= intel_parser
.op_string
;
6169 new_token
.code
= T_CONST
;
6171 /* Allow any kind of identifier char to encompass floating point and
6172 hexadecimal numbers. */
6173 while (is_identifier_char (*q
))
6177 /* Recognize special symbol names [0-9][bf]. */
6178 if (strlen (intel_parser
.op_string
) == 2
6179 && (intel_parser
.op_string
[1] == 'b'
6180 || intel_parser
.op_string
[1] == 'f'))
6181 new_token
.code
= T_ID
;
6184 else if (strchr ("<>", *intel_parser
.op_string
)
6185 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6187 new_token
.code
= T_SHIFTOP
;
6188 new_token
.str
[0] = *intel_parser
.op_string
;
6189 new_token
.str
[1] = *intel_parser
.op_string
;
6190 new_token
.str
[2] = '\0';
6193 else if (strchr ("+-/*&|:[]()~", *intel_parser
.op_string
))
6195 new_token
.code
= *intel_parser
.op_string
;
6196 new_token
.str
[0] = *intel_parser
.op_string
;
6197 new_token
.str
[1] = '\0';
6200 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6201 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6203 new_token
.code
= T_REG
;
6204 new_token
.reg
= reg
;
6206 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6208 new_token
.str
[0] = REGISTER_PREFIX
;
6209 new_token
.str
[1] = '\0';
6212 strcat (new_token
.str
, reg
->reg_name
);
6215 else if (is_identifier_char (*intel_parser
.op_string
))
6217 char *p
= new_token
.str
;
6218 char *q
= intel_parser
.op_string
;
6220 /* A '.' or '$' followed by an identifier char is an identifier.
6221 Otherwise, it's operator '.' followed by an expression. */
6222 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6224 new_token
.code
= *q
;
6225 new_token
.str
[0] = *q
;
6226 new_token
.str
[1] = '\0';
6230 while (is_identifier_char (*q
) || *q
== '@')
6234 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6235 new_token
.code
= T_BYTE
;
6237 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6238 new_token
.code
= T_WORD
;
6240 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6241 new_token
.code
= T_DWORD
;
6243 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6244 new_token
.code
= T_QWORD
;
6246 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6247 new_token
.code
= T_XWORD
;
6249 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6250 new_token
.code
= T_PTR
;
6252 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6253 new_token
.code
= T_SHORT
;
6255 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6257 new_token
.code
= T_OFFSET
;
6259 /* ??? This is not mentioned in the MASM grammar but gcc
6260 makes use of it with -mintel-syntax. OFFSET may be
6261 followed by FLAT: */
6262 if (strncasecmp (q
, " FLAT:", 6) == 0)
6263 strcat (new_token
.str
, " FLAT:");
6266 /* ??? This is not mentioned in the MASM grammar. */
6267 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6268 new_token
.code
= T_OFFSET
;
6271 new_token
.code
= T_ID
;
6276 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6278 intel_parser
.op_string
+= strlen (new_token
.str
);
6279 cur_token
= new_token
;
6282 /* Put cur_token back into the token stream and make cur_token point to
6285 intel_putback_token ()
6287 intel_parser
.op_string
-= strlen (cur_token
.str
);
6288 free (cur_token
.str
);
6289 cur_token
= prev_token
;
6291 /* Forget prev_token. */
6292 prev_token
.code
= T_NIL
;
6293 prev_token
.reg
= NULL
;
6294 prev_token
.str
= NULL
;
6298 tc_x86_regname_to_dw2regnum (const char *regname
)
6300 unsigned int regnum
;
6301 unsigned int regnames_count
;
6302 char *regnames_32
[] =
6304 "eax", "ecx", "edx", "ebx",
6305 "esp", "ebp", "esi", "edi",
6308 char *regnames_64
[] =
6310 "rax", "rbx", "rcx", "rdx",
6311 "rdi", "rsi", "rbp", "rsp",
6312 "r8", "r9", "r10", "r11",
6313 "r12", "r13", "r14", "r15",
6318 if (flag_code
== CODE_64BIT
)
6320 regnames
= regnames_64
;
6321 regnames_count
= ARRAY_SIZE (regnames_64
);
6325 regnames
= regnames_32
;
6326 regnames_count
= ARRAY_SIZE (regnames_32
);
6329 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6330 if (strcmp (regname
, regnames
[regnum
]) == 0)
6337 tc_x86_frame_initial_instructions (void)
6339 static unsigned int sp_regno
;
6342 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6345 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6346 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);