1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags enable
; /* cpu feature enable flags */
135 i386_cpu_flags disable
; /* cpu feature disable flags */
139 static void update_code_flag (int, int);
140 static void s_insn (int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
150 static void pe_directive_secidx (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (const char *, char **);
163 static const char *parse_insn (const char *, char *, bool);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (unsigned int, unsigned int);
167 static enum flag_code
i386_addressing_mode (void);
168 static void optimize_imm (void);
169 static bool optimize_disp (const insn_template
*t
);
170 static const insn_template
*match_template (char);
171 static int check_string (void);
172 static int process_suffix (void);
173 static int check_byte_reg (void);
174 static int check_long_reg (void);
175 static int check_qword_reg (void);
176 static int check_word_reg (void);
177 static int finalize_imm (void);
178 static int process_operands (void);
179 static const reg_entry
*build_modrm_byte (void);
180 static void output_insn (void);
181 static void output_imm (fragS
*, offsetT
);
182 static void output_disp (fragS
*, offsetT
);
184 static void s_bss (int);
186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
187 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 /* GNU_PROPERTY_X86_ISA_1_USED. */
190 static unsigned int x86_isa_1_used
;
191 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
192 static unsigned int x86_feature_2_used
;
193 /* Generate x86 used ISA and feature properties. */
194 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
197 static const char *default_arch
= DEFAULT_ARCH
;
199 /* parse_register() returns this when a register alias cannot be used. */
200 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
201 { Dw2Inval
, Dw2Inval
} };
203 static const reg_entry
*reg_eax
;
204 static const reg_entry
*reg_ds
;
205 static const reg_entry
*reg_es
;
206 static const reg_entry
*reg_ss
;
207 static const reg_entry
*reg_st0
;
208 static const reg_entry
*reg_k0
;
213 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
214 unsigned char bytes
[4];
216 /* Destination or source register specifier. */
217 const reg_entry
*register_specifier
;
220 /* 'md_assemble ()' gathers together information and puts it into a
227 const reg_entry
*regs
;
232 no_error
, /* Must be first. */
233 operand_size_mismatch
,
234 operand_type_mismatch
,
235 register_type_mismatch
,
236 number_of_operands_mismatch
,
237 invalid_instruction_suffix
,
239 unsupported_with_intel_mnemonic
,
245 invalid_vsib_address
,
246 invalid_vector_register_set
,
247 invalid_tmm_register_set
,
248 invalid_dest_and_src_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 invalid_register_operand
,
261 /* TM holds the template for the insn were currently assembling. */
264 /* SUFFIX holds the instruction size suffix for byte, word, dword
265 or qword, if given. */
268 /* OPCODE_LENGTH holds the number of base opcode bytes. */
269 unsigned char opcode_length
;
271 /* OPERANDS gives the number of given operands. */
272 unsigned int operands
;
274 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
275 of given register, displacement, memory operands and immediate
277 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
279 /* TYPES [i] is the type (see above #defines) which tells us how to
280 use OP[i] for the corresponding operand. */
281 i386_operand_type types
[MAX_OPERANDS
];
283 /* Displacement expression, immediate expression, or register for each
285 union i386_op op
[MAX_OPERANDS
];
287 /* Flags for operands. */
288 unsigned int flags
[MAX_OPERANDS
];
289 #define Operand_PCrel 1
290 #define Operand_Mem 2
291 #define Operand_Signed 4 /* .insn only */
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* PREFIX holds all the given prefix opcodes (usually null).
307 PREFIXES is the number of prefix opcodes. */
308 unsigned int prefixes
;
309 unsigned char prefix
[MAX_PREFIXES
];
311 /* .insn allows for reserved opcode spaces. */
312 unsigned char insn_opcode_space
;
314 /* .insn also allows (requires) specifying immediate size. */
315 unsigned char imm_bits
[MAX_OPERANDS
];
317 /* Register is in low 3 bits of opcode. */
320 /* The operand to a branch insn indicates an absolute branch. */
323 /* The operand to a branch insn indicates a far branch. */
326 /* There is a memory operand of (%dx) which should be only used
327 with input/output instructions. */
328 bool input_output_operand
;
330 /* Extended states. */
338 xstate_ymm
= 1 << 2 | xstate_xmm
,
340 xstate_zmm
= 1 << 3 | xstate_ymm
,
343 /* Use MASK state. */
347 /* Has GOTPC or TLS relocation. */
348 bool has_gotpc_tls_reloc
;
350 /* RM and SIB are the modrm byte and the sib byte where the
351 addressing modes of this insn are encoded. */
358 /* Masking attributes.
360 The struct describes masking, applied to OPERAND in the instruction.
361 REG is a pointer to the corresponding mask register. ZEROING tells
362 whether merging or zeroing mask is used. */
363 struct Mask_Operation
365 const reg_entry
*reg
;
366 unsigned int zeroing
;
367 /* The operand where this operation is associated. */
368 unsigned int operand
;
371 /* Rounding control and SAE attributes. */
383 /* In Intel syntax the operand modifier form is supposed to be used, but
384 we continue to accept the immediate forms as well. */
388 /* Broadcasting attributes.
390 The struct describes broadcasting, applied to OPERAND. TYPE is
391 expresses the broadcast factor. */
392 struct Broadcast_Operation
394 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
397 /* Index of broadcasted operand. */
398 unsigned int operand
;
400 /* Number of bytes to broadcast. */
404 /* Compressed disp8*N attribute. */
405 unsigned int memshift
;
407 /* Prefer load or store in encoding. */
410 dir_encoding_default
= 0,
416 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
419 disp_encoding_default
= 0,
425 /* Prefer the REX byte in encoding. */
428 /* Disable instruction size optimization. */
431 /* How to encode vector instructions. */
434 vex_encoding_default
= 0,
442 const char *rep_prefix
;
445 const char *hle_prefix
;
447 /* Have BND prefix. */
448 const char *bnd_prefix
;
450 /* Have NOTRACK prefix. */
451 const char *notrack_prefix
;
454 enum i386_error error
;
457 typedef struct _i386_insn i386_insn
;
459 /* Link RC type with corresponding string, that'll be looked for in
468 static const struct RC_name RC_NamesTable
[] =
470 { rne
, STRING_COMMA_LEN ("rn-sae") },
471 { rd
, STRING_COMMA_LEN ("rd-sae") },
472 { ru
, STRING_COMMA_LEN ("ru-sae") },
473 { rz
, STRING_COMMA_LEN ("rz-sae") },
474 { saeonly
, STRING_COMMA_LEN ("sae") },
477 /* To be indexed by segment register number. */
478 static const unsigned char i386_seg_prefixes
[] = {
487 /* List of chars besides those in app.c:symbol_chars that can start an
488 operand. Used to prevent the scrubber eating vital white-space. */
489 const char extra_symbol_chars
[] = "*%-([{}"
498 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
499 && !defined (TE_GNU) \
500 && !defined (TE_LINUX) \
501 && !defined (TE_Haiku) \
502 && !defined (TE_FreeBSD) \
503 && !defined (TE_DragonFly) \
504 && !defined (TE_NetBSD))
505 /* This array holds the chars that always start a comment. If the
506 pre-processor is disabled, these aren't very useful. The option
507 --divide will remove '/' from this list. */
508 const char *i386_comment_chars
= "#/";
509 #define SVR4_COMMENT_CHARS 1
510 #define PREFIX_SEPARATOR '\\'
513 const char *i386_comment_chars
= "#";
514 #define PREFIX_SEPARATOR '/'
517 /* This array holds the chars that only start a comment at the beginning of
518 a line. If the line seems to have the form '# 123 filename'
519 .line and .file directives will appear in the pre-processed output.
520 Note that input_file.c hand checks for '#' at the beginning of the
521 first line of the input file. This is because the compiler outputs
522 #NO_APP at the beginning of its output.
523 Also note that comments started like this one will always work if
524 '/' isn't otherwise defined. */
525 const char line_comment_chars
[] = "#/";
527 const char line_separator_chars
[] = ";";
529 /* Chars that can be used to separate mant from exp in floating point
531 const char EXP_CHARS
[] = "eE";
533 /* Chars that mean this number is a floating point constant
536 const char FLT_CHARS
[] = "fFdDxXhHbB";
538 /* Tables for lexical analysis. */
539 static char mnemonic_chars
[256];
540 static char register_chars
[256];
541 static char operand_chars
[256];
543 /* Lexical macros. */
544 #define is_operand_char(x) (operand_chars[(unsigned char) x])
545 #define is_register_char(x) (register_chars[(unsigned char) x])
546 #define is_space_char(x) ((x) == ' ')
548 /* All non-digit non-letter characters that may occur in an operand and
549 which aren't already in extra_symbol_chars[]. */
550 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
552 /* md_assemble() always leaves the strings it's passed unaltered. To
553 effect this we maintain a stack of saved characters that we've smashed
554 with '\0's (indicating end of strings for various sub-fields of the
555 assembler instruction). */
556 static char save_stack
[32];
557 static char *save_stack_p
;
558 #define END_STRING_AND_SAVE(s) \
559 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
560 #define RESTORE_END_STRING(s) \
561 do { *(s) = *--save_stack_p; } while (0)
563 /* The instruction we're assembling. */
566 /* Possible templates for current insn. */
567 static const templates
*current_templates
;
569 /* Per instruction expressionS buffers: max displacements & immediates. */
570 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
571 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
573 /* Current operand we are working on. */
574 static int this_operand
= -1;
576 /* Are we processing a .insn directive? */
577 #define dot_insn() (i.tm.mnem_off == MN__insn)
579 /* We support four different modes. FLAG_CODE variable is used to distinguish
587 static enum flag_code flag_code
;
588 static unsigned int object_64bit
;
589 static unsigned int disallow_64bit_reloc
;
590 static int use_rela_relocations
= 0;
591 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
592 static const char *tls_get_addr
;
594 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
595 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
596 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
598 /* The ELF ABI to use. */
606 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
609 #if defined (TE_PE) || defined (TE_PEP)
610 /* Use big object file format. */
611 static int use_big_obj
= 0;
614 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
615 /* 1 if generating code for a shared library. */
616 static int shared
= 0;
618 unsigned int x86_sframe_cfa_sp_reg
;
619 /* The other CFA base register for SFrame stack trace info. */
620 unsigned int x86_sframe_cfa_fp_reg
;
621 unsigned int x86_sframe_cfa_ra_reg
;
625 /* 1 for intel syntax,
627 static int intel_syntax
= 0;
629 static enum x86_64_isa
631 amd64
= 1, /* AMD64 ISA. */
632 intel64
/* Intel64 ISA. */
635 /* 1 for intel mnemonic,
636 0 if att mnemonic. */
637 static int intel_mnemonic
= !SYSV386_COMPAT
;
639 /* 1 if pseudo registers are permitted. */
640 static int allow_pseudo_reg
= 0;
642 /* 1 if register prefix % not required. */
643 static int allow_naked_reg
= 0;
645 /* 1 if the assembler should add BND prefix for all control-transferring
646 instructions supporting it, even if this prefix wasn't specified
648 static int add_bnd_prefix
= 0;
650 /* 1 if pseudo index register, eiz/riz, is allowed . */
651 static int allow_index_reg
= 0;
653 /* 1 if the assembler should ignore LOCK prefix, even if it was
654 specified explicitly. */
655 static int omit_lock_prefix
= 0;
657 /* 1 if the assembler should encode lfence, mfence, and sfence as
658 "lock addl $0, (%{re}sp)". */
659 static int avoid_fence
= 0;
661 /* 1 if lfence should be inserted after every load. */
662 static int lfence_after_load
= 0;
664 /* Non-zero if lfence should be inserted before indirect branch. */
665 static enum lfence_before_indirect_branch_kind
667 lfence_branch_none
= 0,
668 lfence_branch_register
,
669 lfence_branch_memory
,
672 lfence_before_indirect_branch
;
674 /* Non-zero if lfence should be inserted before ret. */
675 static enum lfence_before_ret_kind
677 lfence_before_ret_none
= 0,
678 lfence_before_ret_not
,
679 lfence_before_ret_or
,
680 lfence_before_ret_shl
684 /* Types of previous instruction is .byte or prefix. */
699 /* 1 if the assembler should generate relax relocations. */
701 static int generate_relax_relocations
702 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
704 static enum check_kind
710 sse_check
, operand_check
= check_warning
;
712 /* Non-zero if branches should be aligned within power of 2 boundary. */
713 static int align_branch_power
= 0;
715 /* Types of branches to align. */
716 enum align_branch_kind
718 align_branch_none
= 0,
719 align_branch_jcc
= 1,
720 align_branch_fused
= 2,
721 align_branch_jmp
= 3,
722 align_branch_call
= 4,
723 align_branch_indirect
= 5,
727 /* Type bits of branches to align. */
728 enum align_branch_bit
730 align_branch_jcc_bit
= 1 << align_branch_jcc
,
731 align_branch_fused_bit
= 1 << align_branch_fused
,
732 align_branch_jmp_bit
= 1 << align_branch_jmp
,
733 align_branch_call_bit
= 1 << align_branch_call
,
734 align_branch_indirect_bit
= 1 << align_branch_indirect
,
735 align_branch_ret_bit
= 1 << align_branch_ret
738 static unsigned int align_branch
= (align_branch_jcc_bit
739 | align_branch_fused_bit
740 | align_branch_jmp_bit
);
742 /* Types of condition jump used by macro-fusion. */
745 mf_jcc_jo
= 0, /* base opcode 0x70 */
746 mf_jcc_jc
, /* base opcode 0x72 */
747 mf_jcc_je
, /* base opcode 0x74 */
748 mf_jcc_jna
, /* base opcode 0x76 */
749 mf_jcc_js
, /* base opcode 0x78 */
750 mf_jcc_jp
, /* base opcode 0x7a */
751 mf_jcc_jl
, /* base opcode 0x7c */
752 mf_jcc_jle
, /* base opcode 0x7e */
755 /* Types of compare flag-modifying insntructions used by macro-fusion. */
758 mf_cmp_test_and
, /* test/cmp */
759 mf_cmp_alu_cmp
, /* add/sub/cmp */
760 mf_cmp_incdec
/* inc/dec */
763 /* The maximum padding size for fused jcc. CMP like instruction can
764 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
766 #define MAX_FUSED_JCC_PADDING_SIZE 20
768 /* The maximum number of prefixes added for an instruction. */
769 static unsigned int align_branch_prefix_size
= 5;
772 1. Clear the REX_W bit with register operand if possible.
773 2. Above plus use 128bit vector instruction to clear the full vector
776 static int optimize
= 0;
779 1. Clear the REX_W bit with register operand if possible.
780 2. Above plus use 128bit vector instruction to clear the full vector
782 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
785 static int optimize_for_space
= 0;
787 /* Register prefix used for error message. */
788 static const char *register_prefix
= "%";
790 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
791 leave, push, and pop instructions so that gcc has the same stack
792 frame as in 32 bit mode. */
793 static char stackop_size
= '\0';
795 /* Non-zero to optimize code alignment. */
796 int optimize_align_code
= 1;
798 /* Non-zero to quieten some warnings. */
799 static int quiet_warnings
= 0;
801 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
802 static bool pre_386_16bit_warned
;
805 static const char *cpu_arch_name
= NULL
;
806 static char *cpu_sub_arch_name
= NULL
;
808 /* CPU feature flags. */
809 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
811 /* If we have selected a cpu we are generating instructions for. */
812 static int cpu_arch_tune_set
= 0;
814 /* Cpu we are generating instructions for. */
815 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
817 /* CPU feature flags of cpu we are generating instructions for. */
818 static i386_cpu_flags cpu_arch_tune_flags
;
820 /* CPU instruction set architecture used. */
821 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
823 /* CPU feature flags of instruction set architecture used. */
824 i386_cpu_flags cpu_arch_isa_flags
;
826 /* If set, conditional jumps are not automatically promoted to handle
827 larger than a byte offset. */
828 static bool no_cond_jump_promotion
= false;
830 /* This will be set from an expression parser hook if there's any
831 applicable operator involved in an expression. */
834 expr_operator_present
,
838 /* Encode SSE instructions with VEX prefix. */
839 static unsigned int sse2avx
;
841 /* Encode aligned vector move as unaligned vector move. */
842 static unsigned int use_unaligned_vector_move
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
978 static const arch_entry cpu_arch
[] =
980 /* Do not replace the first two entries - i386_target_format() and
981 set_cpu_arch() rely on them being there in this order. */
982 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
983 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
984 ARCH (i8086
, UNKNOWN
, NONE
, false),
985 ARCH (i186
, UNKNOWN
, 186, false),
986 ARCH (i286
, UNKNOWN
, 286, false),
987 ARCH (i386
, I386
, 386, false),
988 ARCH (i486
, I486
, 486, false),
989 ARCH (i586
, PENTIUM
, 586, false),
990 ARCH (i686
, PENTIUMPRO
, 686, false),
991 ARCH (pentium
, PENTIUM
, 586, false),
992 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
993 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
994 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
995 ARCH (pentium4
, PENTIUM4
, P4
, false),
996 ARCH (prescott
, NOCONA
, CORE
, false),
997 ARCH (nocona
, NOCONA
, NOCONA
, false),
998 ARCH (yonah
, CORE
, CORE
, true),
999 ARCH (core
, CORE
, CORE
, false),
1000 ARCH (merom
, CORE2
, CORE2
, true),
1001 ARCH (core2
, CORE2
, CORE2
, false),
1002 ARCH (corei7
, COREI7
, COREI7
, false),
1003 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1004 ARCH (k6
, K6
, K6
, false),
1005 ARCH (k6_2
, K6
, K6_2
, false),
1006 ARCH (athlon
, ATHLON
, ATHLON
, false),
1007 ARCH (sledgehammer
, K8
, K8
, true),
1008 ARCH (opteron
, K8
, K8
, false),
1009 ARCH (k8
, K8
, K8
, false),
1010 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1011 ARCH (bdver1
, BD
, BDVER1
, false),
1012 ARCH (bdver2
, BD
, BDVER2
, false),
1013 ARCH (bdver3
, BD
, BDVER3
, false),
1014 ARCH (bdver4
, BD
, BDVER4
, false),
1015 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1016 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1017 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1018 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1019 ARCH (btver1
, BT
, BTVER1
, false),
1020 ARCH (btver2
, BT
, BTVER2
, false),
1022 SUBARCH (8087, 8087, ANY_8087
, false),
1023 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1024 SUBARCH (287, 287, ANY_287
, false),
1025 SUBARCH (387, 387, ANY_387
, false),
1026 SUBARCH (687, 687, ANY_687
, false),
1027 SUBARCH (cmov
, CMOV
, CMOV
, false),
1028 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1029 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1030 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1031 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1032 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1033 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1034 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1035 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1036 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1037 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1038 SUBARCH (avx
, AVX
, ANY_AVX
, false),
1039 SUBARCH (avx2
, AVX2
, ANY_AVX2
, false),
1040 SUBARCH (avx512f
, AVX512F
, ANY_AVX512F
, false),
1041 SUBARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, false),
1042 SUBARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, false),
1043 SUBARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, false),
1044 SUBARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, false),
1045 SUBARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, false),
1046 SUBARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, false),
1047 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1048 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1049 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1050 SUBARCH (smx
, SMX
, SMX
, false),
1051 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1052 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1053 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1054 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1055 SUBARCH (aes
, AES
, ANY_AES
, false),
1056 SUBARCH (pclmul
, PCLMUL
, ANY_PCLMUL
, false),
1057 SUBARCH (clmul
, PCLMUL
, ANY_PCLMUL
, true),
1058 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1059 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1060 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1061 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1062 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1063 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1064 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1065 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1066 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1067 SUBARCH (cx16
, CX16
, CX16
, false),
1068 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1069 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1070 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1071 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1072 SUBARCH (hle
, HLE
, HLE
, false),
1073 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1074 SUBARCH (tsx
, TSX
, TSX
, false),
1075 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1076 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1077 SUBARCH (nop
, NOP
, NOP
, false),
1078 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1079 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1080 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1081 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1082 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1083 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1084 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1085 SUBARCH (abm
, ABM
, ABM
, false),
1086 SUBARCH (bmi
, BMI
, BMI
, false),
1087 SUBARCH (tbm
, TBM
, TBM
, false),
1088 SUBARCH (adx
, ADX
, ADX
, false),
1089 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1090 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1091 SUBARCH (smap
, SMAP
, SMAP
, false),
1092 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1093 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1094 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1095 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1096 SUBARCH (se1
, SE1
, SE1
, false),
1097 SUBARCH (clwb
, CLWB
, CLWB
, false),
1098 SUBARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, false),
1099 SUBARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, false),
1100 SUBARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, false),
1101 SUBARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, false),
1102 SUBARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, false),
1103 SUBARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, false),
1104 SUBARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, false),
1105 SUBARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, false),
1106 SUBARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, false),
1107 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1108 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1109 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1110 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1111 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1112 SUBARCH (ibt
, IBT
, IBT
, false),
1113 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1114 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1115 SUBARCH (vaes
, VAES
, ANY_VAES
, false),
1116 SUBARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, false),
1117 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1118 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1119 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1120 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1121 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1122 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1123 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1124 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1125 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1126 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1127 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1128 SUBARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, false),
1129 SUBARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1130 ANY_AVX512_VP2INTERSECT
, false),
1131 SUBARCH (tdx
, TDX
, TDX
, false),
1132 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1133 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1134 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1135 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1136 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1137 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1138 SUBARCH (kl
, KL
, ANY_KL
, false),
1139 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1140 SUBARCH (uintr
, UINTR
, UINTR
, false),
1141 SUBARCH (hreset
, HRESET
, HRESET
, false),
1142 SUBARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, false),
1143 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1144 SUBARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, false),
1145 SUBARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, false),
1146 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1147 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1148 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1149 SUBARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, false),
1150 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1151 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1152 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1153 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1154 SUBARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, false),
1155 SUBARCH (sha512
, SHA512
, ANY_SHA512
, false),
1156 SUBARCH (sm3
, SM3
, ANY_SM3
, false),
1157 SUBARCH (sm4
, SM4
, ANY_SM4
, false),
1164 /* Like s_lcomm_internal in gas/read.c but the alignment string
1165 is allowed to be optional. */
1168 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1175 && *input_line_pointer
== ',')
1177 align
= parse_align (needs_align
- 1);
1179 if (align
== (addressT
) -1)
1194 bss_alloc (symbolP
, size
, align
);
1199 pe_lcomm (int needs_align
)
1201 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1205 const pseudo_typeS md_pseudo_table
[] =
1207 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1208 {"align", s_align_bytes
, 0},
1210 {"align", s_align_ptwo
, 0},
1212 {"arch", set_cpu_arch
, 0},
1216 {"lcomm", pe_lcomm
, 1},
1218 {"ffloat", float_cons
, 'f'},
1219 {"dfloat", float_cons
, 'd'},
1220 {"tfloat", float_cons
, 'x'},
1221 {"hfloat", float_cons
, 'h'},
1222 {"bfloat16", float_cons
, 'b'},
1224 {"slong", signed_cons
, 4},
1225 {"insn", s_insn
, 0},
1226 {"noopt", s_ignore
, 0},
1227 {"optim", s_ignore
, 0},
1228 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1229 {"code16", set_code_flag
, CODE_16BIT
},
1230 {"code32", set_code_flag
, CODE_32BIT
},
1232 {"code64", set_code_flag
, CODE_64BIT
},
1234 {"intel_syntax", set_intel_syntax
, 1},
1235 {"att_syntax", set_intel_syntax
, 0},
1236 {"intel_mnemonic", set_intel_mnemonic
, 1},
1237 {"att_mnemonic", set_intel_mnemonic
, 0},
1238 {"allow_index_reg", set_allow_index_reg
, 1},
1239 {"disallow_index_reg", set_allow_index_reg
, 0},
1240 {"sse_check", set_check
, 0},
1241 {"operand_check", set_check
, 1},
1242 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1243 {"largecomm", handle_large_common
, 0},
1245 {"file", dwarf2_directive_file
, 0},
1246 {"loc", dwarf2_directive_loc
, 0},
1247 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1250 {"secrel32", pe_directive_secrel
, 0},
1251 {"secidx", pe_directive_secidx
, 0},
1256 /* For interface with expression (). */
1257 extern char *input_line_pointer
;
1259 /* Hash table for instruction mnemonic lookup. */
1260 static htab_t op_hash
;
1262 /* Hash table for register lookup. */
1263 static htab_t reg_hash
;
1265 /* Various efficient no-op patterns for aligning code labels.
1266 Note: Don't try to assemble the instructions in the comments.
1267 0L and 0w are not legal. */
1268 static const unsigned char f32_1
[] =
1270 static const unsigned char f32_2
[] =
1271 {0x66,0x90}; /* xchg %ax,%ax */
1272 static const unsigned char f32_3
[] =
1273 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1274 static const unsigned char f32_4
[] =
1275 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1276 static const unsigned char f32_6
[] =
1277 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1278 static const unsigned char f32_7
[] =
1279 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1280 static const unsigned char f16_3
[] =
1281 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1282 static const unsigned char f16_4
[] =
1283 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1284 static const unsigned char jump_disp8
[] =
1285 {0xeb}; /* jmp disp8 */
1286 static const unsigned char jump32_disp32
[] =
1287 {0xe9}; /* jmp disp32 */
1288 static const unsigned char jump16_disp32
[] =
1289 {0x66,0xe9}; /* jmp disp32 */
1290 /* 32-bit NOPs patterns. */
1291 static const unsigned char *const f32_patt
[] = {
1292 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1294 /* 16-bit NOPs patterns. */
1295 static const unsigned char *const f16_patt
[] = {
1296 f32_1
, f32_2
, f16_3
, f16_4
1298 /* nopl (%[re]ax) */
1299 static const unsigned char alt_3
[] =
1301 /* nopl 0(%[re]ax) */
1302 static const unsigned char alt_4
[] =
1303 {0x0f,0x1f,0x40,0x00};
1304 /* nopl 0(%[re]ax,%[re]ax,1) */
1305 static const unsigned char alt_5
[] =
1306 {0x0f,0x1f,0x44,0x00,0x00};
1307 /* nopw 0(%[re]ax,%[re]ax,1) */
1308 static const unsigned char alt_6
[] =
1309 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1310 /* nopl 0L(%[re]ax) */
1311 static const unsigned char alt_7
[] =
1312 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1313 /* nopl 0L(%[re]ax,%[re]ax,1) */
1314 static const unsigned char alt_8
[] =
1315 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1316 /* nopw 0L(%[re]ax,%[re]ax,1) */
1317 static const unsigned char alt_9
[] =
1318 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1319 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1320 static const unsigned char alt_10
[] =
1321 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1322 /* data16 nopw %cs:0L(%eax,%eax,1) */
1323 static const unsigned char alt_11
[] =
1324 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1325 /* 32-bit and 64-bit NOPs patterns. */
1326 static const unsigned char *const alt_patt
[] = {
1327 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1328 alt_9
, alt_10
, alt_11
1331 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1332 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1335 i386_output_nops (char *where
, const unsigned char *const *patt
,
1336 int count
, int max_single_nop_size
)
1339 /* Place the longer NOP first. */
1342 const unsigned char *nops
;
1344 if (max_single_nop_size
< 1)
1346 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1347 max_single_nop_size
);
1351 nops
= patt
[max_single_nop_size
- 1];
1353 /* Use the smaller one if the requsted one isn't available. */
1356 max_single_nop_size
--;
1357 nops
= patt
[max_single_nop_size
- 1];
1360 last
= count
% max_single_nop_size
;
1363 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1364 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1368 nops
= patt
[last
- 1];
1371 /* Use the smaller one plus one-byte NOP if the needed one
1374 nops
= patt
[last
- 1];
1375 memcpy (where
+ offset
, nops
, last
);
1376 where
[offset
+ last
] = *patt
[0];
1379 memcpy (where
+ offset
, nops
, last
);
1384 fits_in_imm7 (offsetT num
)
1386 return (num
& 0x7f) == num
;
1390 fits_in_imm31 (offsetT num
)
1392 return (num
& 0x7fffffff) == num
;
1395 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1396 single NOP instruction LIMIT. */
1399 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1401 const unsigned char *const *patt
= NULL
;
1402 int max_single_nop_size
;
1403 /* Maximum number of NOPs before switching to jump over NOPs. */
1404 int max_number_of_nops
;
1406 switch (fragP
->fr_type
)
1411 case rs_machine_dependent
:
1412 /* Allow NOP padding for jumps and calls. */
1413 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1414 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1421 /* We need to decide which NOP sequence to use for 32bit and
1422 64bit. When -mtune= is used:
1424 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1425 PROCESSOR_GENERIC32, f32_patt will be used.
1426 2. For the rest, alt_patt will be used.
1428 When -mtune= isn't used, alt_patt will be used if
1429 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1432 When -march= or .arch is used, we can't use anything beyond
1433 cpu_arch_isa_flags. */
1435 if (flag_code
== CODE_16BIT
)
1438 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1439 /* Limit number of NOPs to 2 in 16-bit mode. */
1440 max_number_of_nops
= 2;
1444 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1446 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1447 switch (cpu_arch_tune
)
1449 case PROCESSOR_UNKNOWN
:
1450 /* We use cpu_arch_isa_flags to check if we SHOULD
1451 optimize with nops. */
1452 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1457 case PROCESSOR_PENTIUM4
:
1458 case PROCESSOR_NOCONA
:
1459 case PROCESSOR_CORE
:
1460 case PROCESSOR_CORE2
:
1461 case PROCESSOR_COREI7
:
1462 case PROCESSOR_GENERIC64
:
1464 case PROCESSOR_ATHLON
:
1466 case PROCESSOR_AMDFAM10
:
1468 case PROCESSOR_ZNVER
:
1472 case PROCESSOR_I386
:
1473 case PROCESSOR_I486
:
1474 case PROCESSOR_PENTIUM
:
1475 case PROCESSOR_PENTIUMPRO
:
1476 case PROCESSOR_IAMCU
:
1477 case PROCESSOR_GENERIC32
:
1480 case PROCESSOR_NONE
:
1486 switch (fragP
->tc_frag_data
.tune
)
1488 case PROCESSOR_UNKNOWN
:
1489 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1490 PROCESSOR_UNKNOWN. */
1494 case PROCESSOR_I386
:
1495 case PROCESSOR_I486
:
1496 case PROCESSOR_PENTIUM
:
1497 case PROCESSOR_IAMCU
:
1499 case PROCESSOR_ATHLON
:
1501 case PROCESSOR_AMDFAM10
:
1503 case PROCESSOR_ZNVER
:
1505 case PROCESSOR_GENERIC32
:
1506 /* We use cpu_arch_isa_flags to check if we CAN optimize
1508 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1513 case PROCESSOR_PENTIUMPRO
:
1514 case PROCESSOR_PENTIUM4
:
1515 case PROCESSOR_NOCONA
:
1516 case PROCESSOR_CORE
:
1517 case PROCESSOR_CORE2
:
1518 case PROCESSOR_COREI7
:
1519 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1524 case PROCESSOR_GENERIC64
:
1527 case PROCESSOR_NONE
:
1532 if (patt
== f32_patt
)
1534 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1535 /* Limit number of NOPs to 2 for older processors. */
1536 max_number_of_nops
= 2;
1540 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1541 /* Limit number of NOPs to 7 for newer processors. */
1542 max_number_of_nops
= 7;
1547 limit
= max_single_nop_size
;
1549 if (fragP
->fr_type
== rs_fill_nop
)
1551 /* Output NOPs for .nop directive. */
1552 if (limit
> max_single_nop_size
)
1554 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1555 _("invalid single nop size: %d "
1556 "(expect within [0, %d])"),
1557 limit
, max_single_nop_size
);
1561 else if (fragP
->fr_type
!= rs_machine_dependent
)
1562 fragP
->fr_var
= count
;
1564 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1566 /* Generate jump over NOPs. */
1567 offsetT disp
= count
- 2;
1568 if (fits_in_imm7 (disp
))
1570 /* Use "jmp disp8" if possible. */
1572 where
[0] = jump_disp8
[0];
1578 unsigned int size_of_jump
;
1580 if (flag_code
== CODE_16BIT
)
1582 where
[0] = jump16_disp32
[0];
1583 where
[1] = jump16_disp32
[1];
1588 where
[0] = jump32_disp32
[0];
1592 count
-= size_of_jump
+ 4;
1593 if (!fits_in_imm31 (count
))
1595 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1596 _("jump over nop padding out of range"));
1600 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1601 where
+= size_of_jump
+ 4;
1605 /* Generate multiple NOPs. */
1606 i386_output_nops (where
, patt
, count
, limit
);
1610 operand_type_all_zero (const union i386_operand_type
*x
)
1612 switch (ARRAY_SIZE(x
->array
))
1623 return !x
->array
[0];
1630 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1632 switch (ARRAY_SIZE(x
->array
))
1648 x
->bitfield
.class = ClassNone
;
1649 x
->bitfield
.instance
= InstanceNone
;
1653 operand_type_equal (const union i386_operand_type
*x
,
1654 const union i386_operand_type
*y
)
1656 switch (ARRAY_SIZE(x
->array
))
1659 if (x
->array
[2] != y
->array
[2])
1663 if (x
->array
[1] != y
->array
[1])
1667 return x
->array
[0] == y
->array
[0];
1675 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1677 switch (ARRAY_SIZE(x
->array
))
1696 return !x
->array
[0];
1703 cpu_flags_equal (const union i386_cpu_flags
*x
,
1704 const union i386_cpu_flags
*y
)
1706 switch (ARRAY_SIZE(x
->array
))
1709 if (x
->array
[4] != y
->array
[4])
1713 if (x
->array
[3] != y
->array
[3])
1717 if (x
->array
[2] != y
->array
[2])
1721 if (x
->array
[1] != y
->array
[1])
1725 return x
->array
[0] == y
->array
[0];
1733 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1735 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1736 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1739 static INLINE i386_cpu_flags
1740 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1742 switch (ARRAY_SIZE (x
.array
))
1745 x
.array
[4] &= y
.array
[4];
1748 x
.array
[3] &= y
.array
[3];
1751 x
.array
[2] &= y
.array
[2];
1754 x
.array
[1] &= y
.array
[1];
1757 x
.array
[0] &= y
.array
[0];
1765 static INLINE i386_cpu_flags
1766 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1768 switch (ARRAY_SIZE (x
.array
))
1771 x
.array
[4] |= y
.array
[4];
1774 x
.array
[3] |= y
.array
[3];
1777 x
.array
[2] |= y
.array
[2];
1780 x
.array
[1] |= y
.array
[1];
1783 x
.array
[0] |= y
.array
[0];
1791 static INLINE i386_cpu_flags
1792 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1794 switch (ARRAY_SIZE (x
.array
))
1797 x
.array
[4] &= ~y
.array
[4];
1800 x
.array
[3] &= ~y
.array
[3];
1803 x
.array
[2] &= ~y
.array
[2];
1806 x
.array
[1] &= ~y
.array
[1];
1809 x
.array
[0] &= ~y
.array
[0];
1817 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1819 #define CPU_FLAGS_ARCH_MATCH 0x1
1820 #define CPU_FLAGS_64BIT_MATCH 0x2
1822 #define CPU_FLAGS_PERFECT_MATCH \
1823 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1825 /* Return CPU flags match bits. */
1828 cpu_flags_match (const insn_template
*t
)
1830 i386_cpu_flags x
= t
->cpu_flags
;
1831 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1833 x
.bitfield
.cpu64
= 0;
1834 x
.bitfield
.cpuno64
= 0;
1836 if (cpu_flags_all_zero (&x
))
1838 /* This instruction is available on all archs. */
1839 match
|= CPU_FLAGS_ARCH_MATCH
;
1843 /* This instruction is available only on some archs. */
1844 i386_cpu_flags cpu
= cpu_arch_flags
;
1846 /* AVX512VL is no standalone feature - match it and then strip it. */
1847 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1849 x
.bitfield
.cpuavx512vl
= 0;
1851 /* AVX and AVX2 present at the same time express an operand size
1852 dependency - strip AVX2 for the purposes here. The operand size
1853 dependent check occurs in check_vecOperands(). */
1854 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1855 x
.bitfield
.cpuavx2
= 0;
1857 cpu
= cpu_flags_and (x
, cpu
);
1858 if (!cpu_flags_all_zero (&cpu
))
1860 if (x
.bitfield
.cpuavx
)
1862 /* We need to check a few extra flags with AVX. */
1863 if (cpu
.bitfield
.cpuavx
1864 && (!t
->opcode_modifier
.sse2avx
1865 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1866 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1867 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1868 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1869 match
|= CPU_FLAGS_ARCH_MATCH
;
1871 else if (x
.bitfield
.cpuavx512f
)
1873 /* We need to check a few extra flags with AVX512F. */
1874 if (cpu
.bitfield
.cpuavx512f
1875 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1876 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1877 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1878 match
|= CPU_FLAGS_ARCH_MATCH
;
1881 match
|= CPU_FLAGS_ARCH_MATCH
;
1887 static INLINE i386_operand_type
1888 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1890 if (x
.bitfield
.class != y
.bitfield
.class)
1891 x
.bitfield
.class = ClassNone
;
1892 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1893 x
.bitfield
.instance
= InstanceNone
;
1895 switch (ARRAY_SIZE (x
.array
))
1898 x
.array
[2] &= y
.array
[2];
1901 x
.array
[1] &= y
.array
[1];
1904 x
.array
[0] &= y
.array
[0];
1912 static INLINE i386_operand_type
1913 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1915 gas_assert (y
.bitfield
.class == ClassNone
);
1916 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1918 switch (ARRAY_SIZE (x
.array
))
1921 x
.array
[2] &= ~y
.array
[2];
1924 x
.array
[1] &= ~y
.array
[1];
1927 x
.array
[0] &= ~y
.array
[0];
1935 static INLINE i386_operand_type
1936 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1938 gas_assert (x
.bitfield
.class == ClassNone
||
1939 y
.bitfield
.class == ClassNone
||
1940 x
.bitfield
.class == y
.bitfield
.class);
1941 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1942 y
.bitfield
.instance
== InstanceNone
||
1943 x
.bitfield
.instance
== y
.bitfield
.instance
);
1945 switch (ARRAY_SIZE (x
.array
))
1948 x
.array
[2] |= y
.array
[2];
1951 x
.array
[1] |= y
.array
[1];
1954 x
.array
[0] |= y
.array
[0];
1962 static INLINE i386_operand_type
1963 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1965 gas_assert (y
.bitfield
.class == ClassNone
);
1966 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1968 switch (ARRAY_SIZE (x
.array
))
1971 x
.array
[2] ^= y
.array
[2];
1974 x
.array
[1] ^= y
.array
[1];
1977 x
.array
[0] ^= y
.array
[0];
1985 static const i386_operand_type anydisp
= {
1986 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
1998 operand_type_check (i386_operand_type t
, enum operand_type c
)
2003 return t
.bitfield
.class == Reg
;
2006 return (t
.bitfield
.imm8
2010 || t
.bitfield
.imm32s
2011 || t
.bitfield
.imm64
);
2014 return (t
.bitfield
.disp8
2015 || t
.bitfield
.disp16
2016 || t
.bitfield
.disp32
2017 || t
.bitfield
.disp64
);
2020 return (t
.bitfield
.disp8
2021 || t
.bitfield
.disp16
2022 || t
.bitfield
.disp32
2023 || t
.bitfield
.disp64
2024 || t
.bitfield
.baseindex
);
2033 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2034 between operand GIVEN and opeand WANTED for instruction template T. */
2037 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2040 return !((i
.types
[given
].bitfield
.byte
2041 && !t
->operand_types
[wanted
].bitfield
.byte
)
2042 || (i
.types
[given
].bitfield
.word
2043 && !t
->operand_types
[wanted
].bitfield
.word
)
2044 || (i
.types
[given
].bitfield
.dword
2045 && !t
->operand_types
[wanted
].bitfield
.dword
)
2046 || (i
.types
[given
].bitfield
.qword
2047 && (!t
->operand_types
[wanted
].bitfield
.qword
2048 /* Don't allow 64-bit (memory) operands outside of 64-bit
2049 mode, when they're used where a 64-bit GPR could also
2050 be used. Checking is needed for Intel Syntax only. */
2052 && flag_code
!= CODE_64BIT
2053 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2054 || t
->operand_types
[wanted
].bitfield
.class == Accum
2055 || t
->opcode_modifier
.isstring
))))
2056 || (i
.types
[given
].bitfield
.tbyte
2057 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2060 /* Return 1 if there is no conflict in SIMD register between operand
2061 GIVEN and opeand WANTED for instruction template T. */
2064 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2067 return !((i
.types
[given
].bitfield
.xmmword
2068 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2069 || (i
.types
[given
].bitfield
.ymmword
2070 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2071 || (i
.types
[given
].bitfield
.zmmword
2072 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2073 || (i
.types
[given
].bitfield
.tmmword
2074 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2077 /* Return 1 if there is no conflict in any size between operand GIVEN
2078 and opeand WANTED for instruction template T. */
2081 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2084 return (match_operand_size (t
, wanted
, given
)
2085 && !((i
.types
[given
].bitfield
.unspecified
2086 && !i
.broadcast
.type
2087 && !i
.broadcast
.bytes
2088 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2089 || (i
.types
[given
].bitfield
.fword
2090 && !t
->operand_types
[wanted
].bitfield
.fword
)
2091 /* For scalar opcode templates to allow register and memory
2092 operands at the same time, some special casing is needed
2093 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2094 down-conversion vpmov*. */
2095 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2096 && t
->operand_types
[wanted
].bitfield
.byte
2097 + t
->operand_types
[wanted
].bitfield
.word
2098 + t
->operand_types
[wanted
].bitfield
.dword
2099 + t
->operand_types
[wanted
].bitfield
.qword
2100 > !!t
->opcode_modifier
.broadcast
)
2101 ? (i
.types
[given
].bitfield
.xmmword
2102 || i
.types
[given
].bitfield
.ymmword
2103 || i
.types
[given
].bitfield
.zmmword
)
2104 : !match_simd_size(t
, wanted
, given
))));
2107 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2108 operands for instruction template T, and it has MATCH_REVERSE set if there
2109 is no size conflict on any operands for the template with operands reversed
2110 (and the template allows for reversing in the first place). */
2112 #define MATCH_STRAIGHT 1
2113 #define MATCH_REVERSE 2
2115 static INLINE
unsigned int
2116 operand_size_match (const insn_template
*t
)
2118 unsigned int j
, match
= MATCH_STRAIGHT
;
2120 /* Don't check non-absolute jump instructions. */
2121 if (t
->opcode_modifier
.jump
2122 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2125 /* Check memory and accumulator operand size. */
2126 for (j
= 0; j
< i
.operands
; j
++)
2128 if (i
.types
[j
].bitfield
.class != Reg
2129 && i
.types
[j
].bitfield
.class != RegSIMD
2130 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2133 if (t
->operand_types
[j
].bitfield
.class == Reg
2134 && !match_operand_size (t
, j
, j
))
2140 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2141 && !match_simd_size (t
, j
, j
))
2147 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2148 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2154 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2161 if (!t
->opcode_modifier
.d
)
2164 /* Check reverse. */
2165 gas_assert (i
.operands
>= 2);
2167 for (j
= 0; j
< i
.operands
; j
++)
2169 unsigned int given
= i
.operands
- j
- 1;
2171 /* For FMA4 and XOP insns VEX.W controls just the first two
2172 register operands. */
2173 if (t
->cpu_flags
.bitfield
.cpufma4
|| t
->cpu_flags
.bitfield
.cpuxop
)
2174 given
= j
< 2 ? 1 - j
: j
;
2176 if (t
->operand_types
[j
].bitfield
.class == Reg
2177 && !match_operand_size (t
, j
, given
))
2180 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2181 && !match_simd_size (t
, j
, given
))
2184 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2185 && (!match_operand_size (t
, j
, given
)
2186 || !match_simd_size (t
, j
, given
)))
2189 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2193 return match
| MATCH_REVERSE
;
2197 operand_type_match (i386_operand_type overlap
,
2198 i386_operand_type given
)
2200 i386_operand_type temp
= overlap
;
2202 temp
.bitfield
.unspecified
= 0;
2203 temp
.bitfield
.byte
= 0;
2204 temp
.bitfield
.word
= 0;
2205 temp
.bitfield
.dword
= 0;
2206 temp
.bitfield
.fword
= 0;
2207 temp
.bitfield
.qword
= 0;
2208 temp
.bitfield
.tbyte
= 0;
2209 temp
.bitfield
.xmmword
= 0;
2210 temp
.bitfield
.ymmword
= 0;
2211 temp
.bitfield
.zmmword
= 0;
2212 temp
.bitfield
.tmmword
= 0;
2213 if (operand_type_all_zero (&temp
))
2216 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2220 i
.error
= operand_type_mismatch
;
2224 /* If given types g0 and g1 are registers they must be of the same type
2225 unless the expected operand type register overlap is null.
2226 Intel syntax sized memory operands are also checked here. */
2229 operand_type_register_match (i386_operand_type g0
,
2230 i386_operand_type t0
,
2231 i386_operand_type g1
,
2232 i386_operand_type t1
)
2234 if (g0
.bitfield
.class != Reg
2235 && g0
.bitfield
.class != RegSIMD
2236 && (g0
.bitfield
.unspecified
2237 || !operand_type_check (g0
, anymem
)))
2240 if (g1
.bitfield
.class != Reg
2241 && g1
.bitfield
.class != RegSIMD
2242 && (g1
.bitfield
.unspecified
2243 || !operand_type_check (g1
, anymem
)))
2246 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2247 && g0
.bitfield
.word
== g1
.bitfield
.word
2248 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2249 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2250 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2251 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2252 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2255 /* If expectations overlap in no more than a single size, all is fine. */
2256 g0
= operand_type_and (t0
, t1
);
2257 if (g0
.bitfield
.byte
2261 + g0
.bitfield
.xmmword
2262 + g0
.bitfield
.ymmword
2263 + g0
.bitfield
.zmmword
<= 1)
2266 i
.error
= register_type_mismatch
;
2271 static INLINE
unsigned int
2272 register_number (const reg_entry
*r
)
2274 unsigned int nr
= r
->reg_num
;
2276 if (r
->reg_flags
& RegRex
)
2279 if (r
->reg_flags
& RegVRex
)
2285 static INLINE
unsigned int
2286 mode_from_disp_size (i386_operand_type t
)
2288 if (t
.bitfield
.disp8
)
2290 else if (t
.bitfield
.disp16
2291 || t
.bitfield
.disp32
)
2298 fits_in_signed_byte (addressT num
)
2300 return num
+ 0x80 <= 0xff;
2304 fits_in_unsigned_byte (addressT num
)
2310 fits_in_unsigned_word (addressT num
)
2312 return num
<= 0xffff;
2316 fits_in_signed_word (addressT num
)
2318 return num
+ 0x8000 <= 0xffff;
2322 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2327 return num
+ 0x80000000 <= 0xffffffff;
2329 } /* fits_in_signed_long() */
2332 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2337 return num
<= 0xffffffff;
2339 } /* fits_in_unsigned_long() */
2341 static INLINE valueT
extend_to_32bit_address (addressT num
)
2344 if (fits_in_unsigned_long(num
))
2345 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2347 if (!fits_in_signed_long (num
))
2348 return num
& 0xffffffff;
2355 fits_in_disp8 (offsetT num
)
2357 int shift
= i
.memshift
;
2363 mask
= (1 << shift
) - 1;
2365 /* Return 0 if NUM isn't properly aligned. */
2369 /* Check if NUM will fit in 8bit after shift. */
2370 return fits_in_signed_byte (num
>> shift
);
2374 fits_in_imm4 (offsetT num
)
2376 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2377 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2380 static i386_operand_type
2381 smallest_imm_type (offsetT num
)
2383 i386_operand_type t
;
2385 operand_type_set (&t
, 0);
2386 t
.bitfield
.imm64
= 1;
2388 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2390 /* This code is disabled on the 486 because all the Imm1 forms
2391 in the opcode table are slower on the i486. They're the
2392 versions with the implicitly specified single-position
2393 displacement, which has another syntax if you really want to
2395 t
.bitfield
.imm1
= 1;
2396 t
.bitfield
.imm8
= 1;
2397 t
.bitfield
.imm8s
= 1;
2398 t
.bitfield
.imm16
= 1;
2399 t
.bitfield
.imm32
= 1;
2400 t
.bitfield
.imm32s
= 1;
2402 else if (fits_in_signed_byte (num
))
2404 if (fits_in_unsigned_byte (num
))
2405 t
.bitfield
.imm8
= 1;
2406 t
.bitfield
.imm8s
= 1;
2407 t
.bitfield
.imm16
= 1;
2408 t
.bitfield
.imm32
= 1;
2409 t
.bitfield
.imm32s
= 1;
2411 else if (fits_in_unsigned_byte (num
))
2413 t
.bitfield
.imm8
= 1;
2414 t
.bitfield
.imm16
= 1;
2415 t
.bitfield
.imm32
= 1;
2416 t
.bitfield
.imm32s
= 1;
2418 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2420 t
.bitfield
.imm16
= 1;
2421 t
.bitfield
.imm32
= 1;
2422 t
.bitfield
.imm32s
= 1;
2424 else if (fits_in_signed_long (num
))
2426 t
.bitfield
.imm32
= 1;
2427 t
.bitfield
.imm32s
= 1;
2429 else if (fits_in_unsigned_long (num
))
2430 t
.bitfield
.imm32
= 1;
2436 offset_in_range (offsetT val
, int size
)
2442 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2443 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2445 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2447 case sizeof (val
): return val
;
2451 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2452 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2453 (uint64_t) val
, (uint64_t) (val
& mask
));
2458 static INLINE
const char *insn_name (const insn_template
*t
)
2460 return &i386_mnemonics
[t
->mnem_off
];
2473 a. PREFIX_EXIST if attempting to add a prefix where one from the
2474 same class already exists.
2475 b. PREFIX_LOCK if lock prefix is added.
2476 c. PREFIX_REP if rep/repne prefix is added.
2477 d. PREFIX_DS if ds prefix is added.
2478 e. PREFIX_OTHER if other prefix is added.
2481 static enum PREFIX_GROUP
2482 add_prefix (unsigned int prefix
)
2484 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2487 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2488 && flag_code
== CODE_64BIT
)
2490 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2491 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2492 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2493 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2504 case DS_PREFIX_OPCODE
:
2507 case CS_PREFIX_OPCODE
:
2508 case ES_PREFIX_OPCODE
:
2509 case FS_PREFIX_OPCODE
:
2510 case GS_PREFIX_OPCODE
:
2511 case SS_PREFIX_OPCODE
:
2515 case REPNE_PREFIX_OPCODE
:
2516 case REPE_PREFIX_OPCODE
:
2521 case LOCK_PREFIX_OPCODE
:
2530 case ADDR_PREFIX_OPCODE
:
2534 case DATA_PREFIX_OPCODE
:
2538 if (i
.prefix
[q
] != 0)
2546 i
.prefix
[q
] |= prefix
;
2549 as_bad (_("same type of prefix used twice"));
2555 update_code_flag (int value
, int check
)
2557 PRINTF_LIKE ((*as_error
));
2559 flag_code
= (enum flag_code
) value
;
2560 if (flag_code
== CODE_64BIT
)
2562 cpu_arch_flags
.bitfield
.cpu64
= 1;
2563 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2567 cpu_arch_flags
.bitfield
.cpu64
= 0;
2568 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2570 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2573 as_error
= as_fatal
;
2576 (*as_error
) (_("64bit mode not supported on `%s'."),
2577 cpu_arch_name
? cpu_arch_name
: default_arch
);
2579 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2582 as_error
= as_fatal
;
2585 (*as_error
) (_("32bit mode not supported on `%s'."),
2586 cpu_arch_name
? cpu_arch_name
: default_arch
);
2588 stackop_size
= '\0';
2592 set_code_flag (int value
)
2594 update_code_flag (value
, 0);
2598 set_16bit_gcc_code_flag (int new_code_flag
)
2600 flag_code
= (enum flag_code
) new_code_flag
;
2601 if (flag_code
!= CODE_16BIT
)
2603 cpu_arch_flags
.bitfield
.cpu64
= 0;
2604 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2605 stackop_size
= LONG_MNEM_SUFFIX
;
2609 set_intel_syntax (int syntax_flag
)
2611 /* Find out if register prefixing is specified. */
2612 int ask_naked_reg
= 0;
2615 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2618 int e
= get_symbol_name (&string
);
2620 if (strcmp (string
, "prefix") == 0)
2622 else if (strcmp (string
, "noprefix") == 0)
2625 as_bad (_("bad argument to syntax directive."));
2626 (void) restore_line_pointer (e
);
2628 demand_empty_rest_of_line ();
2630 intel_syntax
= syntax_flag
;
2632 if (ask_naked_reg
== 0)
2633 allow_naked_reg
= (intel_syntax
2634 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2636 allow_naked_reg
= (ask_naked_reg
< 0);
2638 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2640 register_prefix
= allow_naked_reg
? "" : "%";
2644 set_intel_mnemonic (int mnemonic_flag
)
2646 intel_mnemonic
= mnemonic_flag
;
2650 set_allow_index_reg (int flag
)
2652 allow_index_reg
= flag
;
2656 set_check (int what
)
2658 enum check_kind
*kind
;
2663 kind
= &operand_check
;
2674 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2677 int e
= get_symbol_name (&string
);
2679 if (strcmp (string
, "none") == 0)
2681 else if (strcmp (string
, "warning") == 0)
2682 *kind
= check_warning
;
2683 else if (strcmp (string
, "error") == 0)
2684 *kind
= check_error
;
2686 as_bad (_("bad argument to %s_check directive."), str
);
2687 (void) restore_line_pointer (e
);
2690 as_bad (_("missing argument for %s_check directive"), str
);
2692 demand_empty_rest_of_line ();
2696 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2697 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2700 static const char *arch
;
2702 /* Intel MCU is only supported on ELF. */
2708 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2709 use default_arch. */
2710 arch
= cpu_arch_name
;
2712 arch
= default_arch
;
2715 /* If we are targeting Intel MCU, we must enable it. */
2716 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2717 == new_flag
.bitfield
.cpuiamcu
)
2720 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2725 extend_cpu_sub_arch_name (const char *name
)
2727 if (cpu_sub_arch_name
)
2728 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2729 ".", name
, (const char *) NULL
);
2731 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2735 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2737 typedef struct arch_stack_entry
2739 const struct arch_stack_entry
*prev
;
2742 i386_cpu_flags flags
;
2743 i386_cpu_flags isa_flags
;
2744 enum processor_type isa
;
2745 enum flag_code flag_code
;
2747 bool no_cond_jump_promotion
;
2749 static const arch_stack_entry
*arch_stack_top
;
2753 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2756 int e
= get_symbol_name (&s
);
2757 const char *string
= s
;
2759 i386_cpu_flags flags
;
2761 if (strcmp (string
, "default") == 0)
2763 if (strcmp (default_arch
, "iamcu") == 0)
2764 string
= default_arch
;
2767 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2769 cpu_arch_name
= NULL
;
2770 free (cpu_sub_arch_name
);
2771 cpu_sub_arch_name
= NULL
;
2772 cpu_arch_flags
= cpu_unknown_flags
;
2773 if (flag_code
== CODE_64BIT
)
2775 cpu_arch_flags
.bitfield
.cpu64
= 1;
2776 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2780 cpu_arch_flags
.bitfield
.cpu64
= 0;
2781 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2783 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2784 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2785 if (!cpu_arch_tune_set
)
2787 cpu_arch_tune
= cpu_arch_isa
;
2788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2791 j
= ARRAY_SIZE (cpu_arch
) + 1;
2794 else if (strcmp (string
, "push") == 0)
2796 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2798 top
->name
= cpu_arch_name
;
2799 if (cpu_sub_arch_name
)
2800 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2802 top
->sub_name
= NULL
;
2803 top
->flags
= cpu_arch_flags
;
2804 top
->isa
= cpu_arch_isa
;
2805 top
->isa_flags
= cpu_arch_isa_flags
;
2806 top
->flag_code
= flag_code
;
2807 top
->stackop_size
= stackop_size
;
2808 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2810 top
->prev
= arch_stack_top
;
2811 arch_stack_top
= top
;
2813 (void) restore_line_pointer (e
);
2814 demand_empty_rest_of_line ();
2817 else if (strcmp (string
, "pop") == 0)
2819 const arch_stack_entry
*top
= arch_stack_top
;
2822 as_bad (_(".arch stack is empty"));
2823 else if (top
->flag_code
!= flag_code
2824 || top
->stackop_size
!= stackop_size
)
2826 static const unsigned int bits
[] = {
2832 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2833 bits
[top
->flag_code
],
2834 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2838 arch_stack_top
= top
->prev
;
2840 cpu_arch_name
= top
->name
;
2841 free (cpu_sub_arch_name
);
2842 cpu_sub_arch_name
= top
->sub_name
;
2843 cpu_arch_flags
= top
->flags
;
2844 cpu_arch_isa
= top
->isa
;
2845 cpu_arch_isa_flags
= top
->isa_flags
;
2846 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2851 (void) restore_line_pointer (e
);
2852 demand_empty_rest_of_line ();
2856 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2858 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2859 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2863 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2865 cpu_arch_name
= cpu_arch
[j
].name
;
2866 free (cpu_sub_arch_name
);
2867 cpu_sub_arch_name
= NULL
;
2868 cpu_arch_flags
= cpu_arch
[j
].enable
;
2869 if (flag_code
== CODE_64BIT
)
2871 cpu_arch_flags
.bitfield
.cpu64
= 1;
2872 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2876 cpu_arch_flags
.bitfield
.cpu64
= 0;
2877 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2879 cpu_arch_isa
= cpu_arch
[j
].type
;
2880 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2881 if (!cpu_arch_tune_set
)
2883 cpu_arch_tune
= cpu_arch_isa
;
2884 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2886 pre_386_16bit_warned
= false;
2890 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2893 flags
= cpu_flags_or (cpu_arch_flags
,
2894 cpu_arch
[j
].enable
);
2896 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2898 extend_cpu_sub_arch_name (string
+ 1);
2899 cpu_arch_flags
= flags
;
2900 cpu_arch_isa_flags
= flags
;
2904 = cpu_flags_or (cpu_arch_isa_flags
,
2905 cpu_arch
[j
].enable
);
2906 (void) restore_line_pointer (e
);
2907 demand_empty_rest_of_line ();
2912 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
2914 /* Disable an ISA extension. */
2915 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2916 if (cpu_arch
[j
].type
== PROCESSOR_NONE
2917 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
2919 flags
= cpu_flags_and_not (cpu_arch_flags
,
2920 cpu_arch
[j
].disable
);
2921 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2923 extend_cpu_sub_arch_name (string
+ 1);
2924 cpu_arch_flags
= flags
;
2925 cpu_arch_isa_flags
= flags
;
2927 (void) restore_line_pointer (e
);
2928 demand_empty_rest_of_line ();
2933 if (j
== ARRAY_SIZE (cpu_arch
))
2934 as_bad (_("no such architecture: `%s'"), string
);
2936 *input_line_pointer
= e
;
2939 as_bad (_("missing cpu architecture"));
2941 no_cond_jump_promotion
= 0;
2942 if (*input_line_pointer
== ','
2943 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2948 ++input_line_pointer
;
2949 e
= get_symbol_name (&string
);
2951 if (strcmp (string
, "nojumps") == 0)
2952 no_cond_jump_promotion
= 1;
2953 else if (strcmp (string
, "jumps") == 0)
2956 as_bad (_("no such architecture modifier: `%s'"), string
);
2958 (void) restore_line_pointer (e
);
2961 demand_empty_rest_of_line ();
2964 enum bfd_architecture
2967 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2969 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2970 || flag_code
== CODE_64BIT
)
2971 as_fatal (_("Intel MCU is 32bit ELF only"));
2972 return bfd_arch_iamcu
;
2975 return bfd_arch_i386
;
2981 if (startswith (default_arch
, "x86_64"))
2983 if (default_arch
[6] == '\0')
2984 return bfd_mach_x86_64
;
2986 return bfd_mach_x64_32
;
2988 else if (!strcmp (default_arch
, "i386")
2989 || !strcmp (default_arch
, "iamcu"))
2991 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2993 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2994 as_fatal (_("Intel MCU is 32bit ELF only"));
2995 return bfd_mach_i386_iamcu
;
2998 return bfd_mach_i386_i386
;
3001 as_fatal (_("unknown architecture"));
3004 #include "opcodes/i386-tbl.h"
3009 /* Support pseudo prefixes like {disp32}. */
3010 lex_type
['{'] = LEX_BEGIN_NAME
;
3012 /* Initialize op_hash hash table. */
3013 op_hash
= str_htab_create ();
3016 const insn_template
*const *sets
= i386_op_sets
;
3017 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3019 /* Type checks to compensate for the conversion through void * which
3020 occurs during hash table insertion / lookup. */
3021 (void) sizeof (sets
== ¤t_templates
->start
);
3022 (void) sizeof (end
== ¤t_templates
->end
);
3023 for (; sets
< end
; ++sets
)
3024 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3025 as_fatal (_("duplicate %s"), insn_name (*sets
));
3028 /* Initialize reg_hash hash table. */
3029 reg_hash
= str_htab_create ();
3031 const reg_entry
*regtab
;
3032 unsigned int regtab_size
= i386_regtab_size
;
3034 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3036 switch (regtab
->reg_type
.bitfield
.class)
3039 if (regtab
->reg_type
.bitfield
.dword
)
3041 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3044 else if (regtab
->reg_type
.bitfield
.tbyte
)
3046 /* There's no point inserting st(<N>) in the hash table, as
3047 parentheses aren't included in register_chars[] anyway. */
3048 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3055 switch (regtab
->reg_num
)
3057 case 0: reg_es
= regtab
; break;
3058 case 2: reg_ss
= regtab
; break;
3059 case 3: reg_ds
= regtab
; break;
3064 if (!regtab
->reg_num
)
3069 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3070 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3074 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3079 for (c
= 0; c
< 256; c
++)
3081 if (ISDIGIT (c
) || ISLOWER (c
))
3083 mnemonic_chars
[c
] = c
;
3084 register_chars
[c
] = c
;
3085 operand_chars
[c
] = c
;
3087 else if (ISUPPER (c
))
3089 mnemonic_chars
[c
] = TOLOWER (c
);
3090 register_chars
[c
] = mnemonic_chars
[c
];
3091 operand_chars
[c
] = c
;
3093 #ifdef SVR4_COMMENT_CHARS
3094 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3095 operand_chars
[c
] = c
;
3099 operand_chars
[c
] = c
;
3102 mnemonic_chars
['_'] = '_';
3103 mnemonic_chars
['-'] = '-';
3104 mnemonic_chars
['.'] = '.';
3106 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3107 operand_chars
[(unsigned char) *p
] = *p
;
3108 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3109 operand_chars
[(unsigned char) *p
] = *p
;
3112 if (flag_code
== CODE_64BIT
)
3114 #if defined (OBJ_COFF) && defined (TE_PE)
3115 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3118 x86_dwarf2_return_column
= 16;
3120 x86_cie_data_alignment
= -8;
3121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3122 x86_sframe_cfa_sp_reg
= 7;
3123 x86_sframe_cfa_fp_reg
= 6;
3128 x86_dwarf2_return_column
= 8;
3129 x86_cie_data_alignment
= -4;
3132 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3133 can be turned into BRANCH_PREFIX frag. */
3134 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3139 i386_print_statistics (FILE *file
)
3141 htab_print_statistics (file
, "i386 opcode", op_hash
);
3142 htab_print_statistics (file
, "i386 register", reg_hash
);
3148 htab_delete (op_hash
);
3149 htab_delete (reg_hash
);
3154 /* Debugging routines for md_assemble. */
3155 static void pte (insn_template
*);
3156 static void pt (i386_operand_type
);
3157 static void pe (expressionS
*);
3158 static void ps (symbolS
*);
3161 pi (const char *line
, i386_insn
*x
)
3165 fprintf (stdout
, "%s: template ", line
);
3167 fprintf (stdout
, " address: base %s index %s scale %x\n",
3168 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3169 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3170 x
->log2_scale_factor
);
3171 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3172 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3173 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3174 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3175 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3176 (x
->rex
& REX_W
) != 0,
3177 (x
->rex
& REX_R
) != 0,
3178 (x
->rex
& REX_X
) != 0,
3179 (x
->rex
& REX_B
) != 0);
3180 for (j
= 0; j
< x
->operands
; j
++)
3182 fprintf (stdout
, " #%d: ", j
+ 1);
3184 fprintf (stdout
, "\n");
3185 if (x
->types
[j
].bitfield
.class == Reg
3186 || x
->types
[j
].bitfield
.class == RegMMX
3187 || x
->types
[j
].bitfield
.class == RegSIMD
3188 || x
->types
[j
].bitfield
.class == RegMask
3189 || x
->types
[j
].bitfield
.class == SReg
3190 || x
->types
[j
].bitfield
.class == RegCR
3191 || x
->types
[j
].bitfield
.class == RegDR
3192 || x
->types
[j
].bitfield
.class == RegTR
3193 || x
->types
[j
].bitfield
.class == RegBND
)
3194 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3195 if (operand_type_check (x
->types
[j
], imm
))
3197 if (operand_type_check (x
->types
[j
], disp
))
3198 pe (x
->op
[j
].disps
);
3203 pte (insn_template
*t
)
3205 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3206 static const char *const opc_spc
[] = {
3207 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3208 "XOP08", "XOP09", "XOP0A",
3212 fprintf (stdout
, " %d operands ", t
->operands
);
3213 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3214 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3215 if (opc_spc
[t
->opcode_space
])
3216 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3217 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3218 if (t
->extension_opcode
!= None
)
3219 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3220 if (t
->opcode_modifier
.d
)
3221 fprintf (stdout
, "D");
3222 if (t
->opcode_modifier
.w
)
3223 fprintf (stdout
, "W");
3224 fprintf (stdout
, "\n");
3225 for (j
= 0; j
< t
->operands
; j
++)
3227 fprintf (stdout
, " #%d type ", j
+ 1);
3228 pt (t
->operand_types
[j
]);
3229 fprintf (stdout
, "\n");
3236 fprintf (stdout
, " operation %d\n", e
->X_op
);
3237 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3238 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3239 if (e
->X_add_symbol
)
3241 fprintf (stdout
, " add_symbol ");
3242 ps (e
->X_add_symbol
);
3243 fprintf (stdout
, "\n");
3247 fprintf (stdout
, " op_symbol ");
3248 ps (e
->X_op_symbol
);
3249 fprintf (stdout
, "\n");
3256 fprintf (stdout
, "%s type %s%s",
3258 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3259 segment_name (S_GET_SEGMENT (s
)));
3262 static struct type_name
3264 i386_operand_type mask
;
3267 const type_names
[] =
3269 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3270 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3271 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3272 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3273 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3274 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3275 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3276 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3277 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3278 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3279 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3280 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3281 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3282 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3283 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3284 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3285 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3286 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3287 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3288 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3289 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3290 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3291 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3292 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3293 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3294 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3295 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3296 { { .bitfield
= { .class = SReg
} }, "SReg" },
3297 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3298 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3299 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3300 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3301 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3302 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3306 pt (i386_operand_type t
)
3309 i386_operand_type a
;
3311 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3313 a
= operand_type_and (t
, type_names
[j
].mask
);
3314 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3315 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3320 #endif /* DEBUG386 */
3322 static bfd_reloc_code_real_type
3323 reloc (unsigned int size
,
3326 bfd_reloc_code_real_type other
)
3328 if (other
!= NO_RELOC
)
3330 reloc_howto_type
*rel
;
3335 case BFD_RELOC_X86_64_GOT32
:
3336 return BFD_RELOC_X86_64_GOT64
;
3338 case BFD_RELOC_X86_64_GOTPLT64
:
3339 return BFD_RELOC_X86_64_GOTPLT64
;
3341 case BFD_RELOC_X86_64_PLTOFF64
:
3342 return BFD_RELOC_X86_64_PLTOFF64
;
3344 case BFD_RELOC_X86_64_GOTPC32
:
3345 other
= BFD_RELOC_X86_64_GOTPC64
;
3347 case BFD_RELOC_X86_64_GOTPCREL
:
3348 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3350 case BFD_RELOC_X86_64_TPOFF32
:
3351 other
= BFD_RELOC_X86_64_TPOFF64
;
3353 case BFD_RELOC_X86_64_DTPOFF32
:
3354 other
= BFD_RELOC_X86_64_DTPOFF64
;
3360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3361 if (other
== BFD_RELOC_SIZE32
)
3364 other
= BFD_RELOC_SIZE64
;
3367 as_bad (_("there are no pc-relative size relocations"));
3373 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3374 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3377 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3379 as_bad (_("unknown relocation (%u)"), other
);
3380 else if (size
!= bfd_get_reloc_size (rel
))
3381 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3382 bfd_get_reloc_size (rel
),
3384 else if (pcrel
&& !rel
->pc_relative
)
3385 as_bad (_("non-pc-relative relocation for pc-relative field"));
3386 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3388 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3390 as_bad (_("relocated field and relocation type differ in signedness"));
3399 as_bad (_("there are no unsigned pc-relative relocations"));
3402 case 1: return BFD_RELOC_8_PCREL
;
3403 case 2: return BFD_RELOC_16_PCREL
;
3404 case 4: return BFD_RELOC_32_PCREL
;
3405 case 8: return BFD_RELOC_64_PCREL
;
3407 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3414 case 4: return BFD_RELOC_X86_64_32S
;
3419 case 1: return BFD_RELOC_8
;
3420 case 2: return BFD_RELOC_16
;
3421 case 4: return BFD_RELOC_32
;
3422 case 8: return BFD_RELOC_64
;
3424 as_bad (_("cannot do %s %u byte relocation"),
3425 sign
> 0 ? "signed" : "unsigned", size
);
3431 /* Here we decide which fixups can be adjusted to make them relative to
3432 the beginning of the section instead of the symbol. Basically we need
3433 to make sure that the dynamic relocations are done correctly, so in
3434 some cases we force the original symbol to be used. */
3437 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3443 /* Don't adjust pc-relative references to merge sections in 64-bit
3445 if (use_rela_relocations
3446 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3450 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3451 and changed later by validate_fix. */
3452 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3453 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3456 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3457 for size relocations. */
3458 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3459 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3460 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3461 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3462 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3487 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3488 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3495 want_disp32 (const insn_template
*t
)
3497 return flag_code
!= CODE_64BIT
3498 || i
.prefix
[ADDR_PREFIX
]
3499 || (t
->mnem_off
== MN_lea
3500 && (!i
.types
[1].bitfield
.qword
3501 || t
->opcode_modifier
.size
== SIZE32
));
3505 intel_float_operand (const char *mnemonic
)
3507 /* Note that the value returned is meaningful only for opcodes with (memory)
3508 operands, hence the code here is free to improperly handle opcodes that
3509 have no operands (for better performance and smaller code). */
3511 if (mnemonic
[0] != 'f')
3512 return 0; /* non-math */
3514 switch (mnemonic
[1])
3516 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3517 the fs segment override prefix not currently handled because no
3518 call path can make opcodes without operands get here */
3520 return 2 /* integer op */;
3522 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3523 return 3; /* fldcw/fldenv */
3526 if (mnemonic
[2] != 'o' /* fnop */)
3527 return 3; /* non-waiting control op */
3530 if (mnemonic
[2] == 's')
3531 return 3; /* frstor/frstpm */
3534 if (mnemonic
[2] == 'a')
3535 return 3; /* fsave */
3536 if (mnemonic
[2] == 't')
3538 switch (mnemonic
[3])
3540 case 'c': /* fstcw */
3541 case 'd': /* fstdw */
3542 case 'e': /* fstenv */
3543 case 's': /* fsts[gw] */
3549 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3550 return 0; /* fxsave/fxrstor are not really math ops */
3558 install_template (const insn_template
*t
)
3564 /* Note that for pseudo prefixes this produces a length of 1. But for them
3565 the length isn't interesting at all. */
3566 for (l
= 1; l
< 4; ++l
)
3567 if (!(t
->base_opcode
>> (8 * l
)))
3570 i
.opcode_length
= l
;
3573 /* Build the VEX prefix. */
3576 build_vex_prefix (const insn_template
*t
)
3578 unsigned int register_specifier
;
3579 unsigned int vector_length
;
3582 /* Check register specifier. */
3583 if (i
.vex
.register_specifier
)
3585 register_specifier
=
3586 ~register_number (i
.vex
.register_specifier
) & 0xf;
3587 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3590 register_specifier
= 0xf;
3592 /* Use 2-byte VEX prefix by swapping destination and source operand
3593 if there are more than 1 register operand. */
3594 if (i
.reg_operands
> 1
3595 && i
.vec_encoding
!= vex_encoding_vex3
3596 && i
.dir_encoding
== dir_encoding_default
3597 && i
.operands
== i
.reg_operands
3598 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3599 && i
.tm
.opcode_space
== SPACE_0F
3600 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3605 swap_2_operands (0, i
.operands
- 1);
3607 gas_assert (i
.rm
.mode
== 3);
3611 i
.rm
.regmem
= i
.rm
.reg
;
3614 if (i
.tm
.opcode_modifier
.d
)
3615 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3616 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3617 else /* Use the next insn. */
3618 install_template (&t
[1]);
3621 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3622 are no memory operands and at least 3 register ones. */
3623 if (i
.reg_operands
>= 3
3624 && i
.vec_encoding
!= vex_encoding_vex3
3625 && i
.reg_operands
== i
.operands
- i
.imm_operands
3626 && i
.tm
.opcode_modifier
.vex
3627 && i
.tm
.opcode_modifier
.commutative
3628 && (i
.tm
.opcode_modifier
.sse2avx
3629 || (optimize
> 1 && !i
.no_optimize
))
3631 && i
.vex
.register_specifier
3632 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3634 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3636 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3637 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3638 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3639 &i
.types
[i
.operands
- 3]));
3640 gas_assert (i
.rm
.mode
== 3);
3642 swap_2_operands (xchg
, xchg
+ 1);
3645 xchg
= i
.rm
.regmem
| 8;
3646 i
.rm
.regmem
= ~register_specifier
& 0xf;
3647 gas_assert (!(i
.rm
.regmem
& 8));
3648 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3649 register_specifier
= ~xchg
& 0xf;
3652 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3653 vector_length
= avxscalar
;
3654 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3656 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3662 /* Determine vector length from the last multi-length vector
3665 for (op
= t
->operands
; op
--;)
3666 if (t
->operand_types
[op
].bitfield
.xmmword
3667 && t
->operand_types
[op
].bitfield
.ymmword
3668 && i
.types
[op
].bitfield
.ymmword
)
3675 /* Check the REX.W bit and VEXW. */
3676 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3677 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3678 else if (i
.tm
.opcode_modifier
.vexw
)
3679 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3681 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3683 /* Use 2-byte VEX prefix if possible. */
3685 && i
.vec_encoding
!= vex_encoding_vex3
3686 && i
.tm
.opcode_space
== SPACE_0F
3687 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3689 /* 2-byte VEX prefix. */
3693 i
.vex
.bytes
[0] = 0xc5;
3695 /* Check the REX.R bit. */
3696 r
= (i
.rex
& REX_R
) ? 0 : 1;
3697 i
.vex
.bytes
[1] = (r
<< 7
3698 | register_specifier
<< 3
3699 | vector_length
<< 2
3700 | i
.tm
.opcode_modifier
.opcodeprefix
);
3704 /* 3-byte VEX prefix. */
3707 switch (i
.tm
.opcode_space
)
3712 i
.vex
.bytes
[0] = 0xc4;
3717 i
.vex
.bytes
[0] = 0x8f;
3723 /* The high 3 bits of the second VEX byte are 1's compliment
3724 of RXB bits from REX. */
3725 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3726 | (!dot_insn () ? i
.tm
.opcode_space
3727 : i
.insn_opcode_space
);
3729 i
.vex
.bytes
[2] = (w
<< 7
3730 | register_specifier
<< 3
3731 | vector_length
<< 2
3732 | i
.tm
.opcode_modifier
.opcodeprefix
);
3737 is_evex_encoding (const insn_template
*t
)
3739 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3740 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3741 || t
->opcode_modifier
.sae
;
3745 is_any_vex_encoding (const insn_template
*t
)
3747 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3751 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3753 unsigned int op
, bytes
;
3754 const i386_operand_type
*types
;
3756 if (i
.broadcast
.type
)
3757 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3759 gas_assert (intel_syntax
);
3761 for (op
= 0; op
< t
->operands
; ++op
)
3762 if (t
->operand_types
[op
].bitfield
.baseindex
)
3765 gas_assert (op
< t
->operands
);
3767 if (t
->opcode_modifier
.evex
3768 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3769 switch (i
.broadcast
.bytes
)
3772 if (t
->operand_types
[op
].bitfield
.word
)
3776 if (t
->operand_types
[op
].bitfield
.dword
)
3780 if (t
->operand_types
[op
].bitfield
.qword
)
3784 if (t
->operand_types
[op
].bitfield
.xmmword
)
3786 if (t
->operand_types
[op
].bitfield
.ymmword
)
3788 if (t
->operand_types
[op
].bitfield
.zmmword
)
3795 gas_assert (op
+ 1 < t
->operands
);
3797 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3798 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3799 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3801 types
= &i
.types
[op
+ 1];
3804 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3805 types
= &t
->operand_types
[op
];
3807 if (types
->bitfield
.zmmword
)
3809 else if (types
->bitfield
.ymmword
)
3815 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3816 insn_name (t
), bytes
* 8);
3821 /* Build the EVEX prefix. */
3824 build_evex_prefix (void)
3826 unsigned int register_specifier
, w
;
3827 rex_byte vrex_used
= 0;
3829 /* Check register specifier. */
3830 if (i
.vex
.register_specifier
)
3832 gas_assert ((i
.vrex
& REX_X
) == 0);
3834 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3835 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3836 register_specifier
+= 8;
3837 /* The upper 16 registers are encoded in the fourth byte of the
3839 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3840 i
.vex
.bytes
[3] = 0x8;
3841 register_specifier
= ~register_specifier
& 0xf;
3845 register_specifier
= 0xf;
3847 /* Encode upper 16 vector index register in the fourth byte of
3849 if (!(i
.vrex
& REX_X
))
3850 i
.vex
.bytes
[3] = 0x8;
3855 /* 4 byte EVEX prefix. */
3857 i
.vex
.bytes
[0] = 0x62;
3859 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3861 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3862 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3863 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3864 | (!dot_insn () ? i
.tm
.opcode_space
3865 : i
.insn_opcode_space
);
3867 /* The fifth bit of the second EVEX byte is 1's compliment of the
3868 REX_R bit in VREX. */
3869 if (!(i
.vrex
& REX_R
))
3870 i
.vex
.bytes
[1] |= 0x10;
3874 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3876 /* When all operands are registers, the REX_X bit in REX is not
3877 used. We reuse it to encode the upper 16 registers, which is
3878 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3879 as 1's compliment. */
3880 if ((i
.vrex
& REX_B
))
3883 i
.vex
.bytes
[1] &= ~0x40;
3887 /* EVEX instructions shouldn't need the REX prefix. */
3888 i
.vrex
&= ~vrex_used
;
3889 gas_assert (i
.vrex
== 0);
3891 /* Check the REX.W bit and VEXW. */
3892 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3893 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3894 else if (i
.tm
.opcode_modifier
.vexw
)
3895 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3897 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3899 /* The third byte of the EVEX prefix. */
3900 i
.vex
.bytes
[2] = ((w
<< 7)
3901 | (register_specifier
<< 3)
3902 | 4 /* Encode the U bit. */
3903 | i
.tm
.opcode_modifier
.opcodeprefix
);
3905 /* The fourth byte of the EVEX prefix. */
3906 /* The zeroing-masking bit. */
3907 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3908 i
.vex
.bytes
[3] |= 0x80;
3910 /* Don't always set the broadcast bit if there is no RC. */
3911 if (i
.rounding
.type
== rc_none
)
3913 /* Encode the vector length. */
3914 unsigned int vec_length
;
3916 if (!i
.tm
.opcode_modifier
.evex
3917 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3921 /* Determine vector length from the last multi-length vector
3923 for (op
= i
.operands
; op
--;)
3924 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3925 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3926 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3928 if (i
.types
[op
].bitfield
.zmmword
)
3930 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3933 else if (i
.types
[op
].bitfield
.ymmword
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3938 else if (i
.types
[op
].bitfield
.xmmword
)
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3943 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
3944 && op
== i
.broadcast
.operand
)
3946 switch (get_broadcast_bytes (&i
.tm
, true))
3949 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3952 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3955 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3964 if (op
>= MAX_OPERANDS
)
3968 switch (i
.tm
.opcode_modifier
.evex
)
3970 case EVEXLIG
: /* LL' is ignored */
3971 vec_length
= evexlig
<< 5;
3974 vec_length
= 0 << 5;
3977 vec_length
= 1 << 5;
3980 vec_length
= 2 << 5;
3985 vec_length
= 3 << 5;
3993 i
.vex
.bytes
[3] |= vec_length
;
3994 /* Encode the broadcast bit. */
3995 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
3996 i
.vex
.bytes
[3] |= 0x10;
3998 else if (i
.rounding
.type
!= saeonly
)
3999 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4001 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4004 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4008 process_immext (void)
4012 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4013 which is coded in the same place as an 8-bit immediate field
4014 would be. Here we fake an 8-bit immediate operand from the
4015 opcode suffix stored in tm.extension_opcode.
4017 AVX instructions also use this encoding, for some of
4018 3 argument instructions. */
4020 gas_assert (i
.imm_operands
<= 1
4022 || (is_any_vex_encoding (&i
.tm
)
4023 && i
.operands
<= 4)));
4025 exp
= &im_expressions
[i
.imm_operands
++];
4026 i
.op
[i
.operands
].imms
= exp
;
4027 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4029 exp
->X_op
= O_constant
;
4030 exp
->X_add_number
= i
.tm
.extension_opcode
;
4031 i
.tm
.extension_opcode
= None
;
4038 switch (i
.tm
.opcode_modifier
.prefixok
)
4046 as_bad (_("invalid instruction `%s' after `%s'"),
4047 insn_name (&i
.tm
), i
.hle_prefix
);
4050 if (i
.prefix
[LOCK_PREFIX
])
4052 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4056 case PrefixHLERelease
:
4057 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4059 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4063 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4065 as_bad (_("memory destination needed for instruction `%s'"
4066 " after `xrelease'"), insn_name (&i
.tm
));
4073 /* Encode aligned vector move as unaligned vector move. */
4076 encode_with_unaligned_vector_move (void)
4078 switch (i
.tm
.base_opcode
)
4080 case 0x28: /* Load instructions. */
4081 case 0x29: /* Store instructions. */
4082 /* movaps/movapd/vmovaps/vmovapd. */
4083 if (i
.tm
.opcode_space
== SPACE_0F
4084 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4085 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4087 case 0x6f: /* Load instructions. */
4088 case 0x7f: /* Store instructions. */
4089 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4090 if (i
.tm
.opcode_space
== SPACE_0F
4091 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4092 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4099 /* Try the shortest encoding by shortening operand size. */
4102 optimize_encoding (void)
4106 if (i
.tm
.mnem_off
== MN_lea
)
4109 lea symbol, %rN -> mov $symbol, %rN
4110 lea (%rM), %rN -> mov %rM, %rN
4111 lea (,%rM,1), %rN -> mov %rM, %rN
4113 and in 32-bit mode for 16-bit addressing
4115 lea (%rM), %rN -> movzx %rM, %rN
4117 and in 64-bit mode zap 32-bit addressing in favor of using a
4118 32-bit (or less) destination.
4120 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4122 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4123 i
.tm
.opcode_modifier
.size
= SIZE32
;
4124 i
.prefix
[ADDR_PREFIX
] = 0;
4127 if (!i
.index_reg
&& !i
.base_reg
)
4130 lea symbol, %rN -> mov $symbol, %rN
4132 if (flag_code
== CODE_64BIT
)
4134 /* Don't transform a relocation to a 16-bit one. */
4136 && i
.op
[0].disps
->X_op
!= O_constant
4137 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4140 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4141 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4143 i
.tm
.base_opcode
= 0xb8;
4144 i
.tm
.opcode_modifier
.modrm
= 0;
4145 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4146 i
.types
[0].bitfield
.imm32
= 1;
4149 i
.tm
.opcode_modifier
.size
= SIZE16
;
4150 i
.types
[0].bitfield
.imm16
= 1;
4155 /* Subject to further optimization below. */
4156 i
.tm
.base_opcode
= 0xc7;
4157 i
.tm
.extension_opcode
= 0;
4158 i
.types
[0].bitfield
.imm32s
= 1;
4159 i
.types
[0].bitfield
.baseindex
= 0;
4162 /* Outside of 64-bit mode address and operand sizes have to match if
4163 a relocation is involved, as otherwise we wouldn't (currently) or
4164 even couldn't express the relocation correctly. */
4165 else if (i
.op
[0].disps
4166 && i
.op
[0].disps
->X_op
!= O_constant
4167 && ((!i
.prefix
[ADDR_PREFIX
])
4168 != (flag_code
== CODE_32BIT
4169 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4170 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4172 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4173 destination is going to grow encoding size. */
4174 else if (flag_code
== CODE_16BIT
4175 && (optimize
<= 1 || optimize_for_space
)
4176 && !i
.prefix
[ADDR_PREFIX
]
4177 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4181 i
.tm
.base_opcode
= 0xb8;
4182 i
.tm
.opcode_modifier
.modrm
= 0;
4183 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4184 i
.types
[0].bitfield
.imm32
= 1;
4186 i
.types
[0].bitfield
.imm16
= 1;
4189 && i
.op
[0].disps
->X_op
== O_constant
4190 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4191 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4193 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4194 i
.op
[0].disps
->X_add_number
&= 0xffff;
4197 i
.tm
.operand_types
[0] = i
.types
[0];
4201 i
.op
[0].imms
= &im_expressions
[0];
4202 i
.op
[0].imms
->X_op
= O_absent
;
4205 else if (i
.op
[0].disps
4206 && (i
.op
[0].disps
->X_op
!= O_constant
4207 || i
.op
[0].disps
->X_add_number
))
4212 lea (%rM), %rN -> mov %rM, %rN
4213 lea (,%rM,1), %rN -> mov %rM, %rN
4214 lea (%rM), %rN -> movzx %rM, %rN
4216 const reg_entry
*addr_reg
;
4218 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4219 addr_reg
= i
.base_reg
;
4220 else if (!i
.base_reg
4221 && i
.index_reg
->reg_num
!= RegIZ
4222 && !i
.log2_scale_factor
)
4223 addr_reg
= i
.index_reg
;
4227 if (addr_reg
->reg_type
.bitfield
.word
4228 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4230 if (flag_code
!= CODE_32BIT
)
4232 i
.tm
.opcode_space
= SPACE_0F
;
4233 i
.tm
.base_opcode
= 0xb7;
4236 i
.tm
.base_opcode
= 0x8b;
4238 if (addr_reg
->reg_type
.bitfield
.dword
4239 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4240 i
.tm
.opcode_modifier
.size
= SIZE32
;
4242 i
.op
[0].regs
= addr_reg
;
4247 i
.disp_operands
= 0;
4248 i
.prefix
[ADDR_PREFIX
] = 0;
4249 i
.prefix
[SEG_PREFIX
] = 0;
4253 if (optimize_for_space
4254 && i
.tm
.mnem_off
== MN_test
4255 && i
.reg_operands
== 1
4256 && i
.imm_operands
== 1
4257 && !i
.types
[1].bitfield
.byte
4258 && i
.op
[0].imms
->X_op
== O_constant
4259 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4262 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4264 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4265 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4267 i
.types
[1].bitfield
.byte
= 1;
4268 /* Ignore the suffix. */
4270 /* Convert to byte registers. */
4271 if (i
.types
[1].bitfield
.word
)
4273 else if (i
.types
[1].bitfield
.dword
)
4277 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4282 else if (flag_code
== CODE_64BIT
4283 && i
.tm
.opcode_space
== SPACE_BASE
4284 && ((i
.types
[1].bitfield
.qword
4285 && i
.reg_operands
== 1
4286 && i
.imm_operands
== 1
4287 && i
.op
[0].imms
->X_op
== O_constant
4288 && ((i
.tm
.base_opcode
== 0xb8
4289 && i
.tm
.extension_opcode
== None
4290 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4291 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4292 && (i
.tm
.base_opcode
== 0x24
4293 || (i
.tm
.base_opcode
== 0x80
4294 && i
.tm
.extension_opcode
== 0x4)
4295 || i
.tm
.mnem_off
== MN_test
4296 || ((i
.tm
.base_opcode
| 1) == 0xc7
4297 && i
.tm
.extension_opcode
== 0x0)))
4298 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4299 && i
.tm
.base_opcode
== 0x83
4300 && i
.tm
.extension_opcode
== 0x4)))
4301 || (i
.types
[0].bitfield
.qword
4302 && ((i
.reg_operands
== 2
4303 && i
.op
[0].regs
== i
.op
[1].regs
4304 && (i
.tm
.mnem_off
== MN_xor
4305 || i
.tm
.mnem_off
== MN_sub
))
4306 || i
.tm
.mnem_off
== MN_clr
))))
4309 andq $imm31, %r64 -> andl $imm31, %r32
4310 andq $imm7, %r64 -> andl $imm7, %r32
4311 testq $imm31, %r64 -> testl $imm31, %r32
4312 xorq %r64, %r64 -> xorl %r32, %r32
4313 subq %r64, %r64 -> subl %r32, %r32
4314 movq $imm31, %r64 -> movl $imm31, %r32
4315 movq $imm32, %r64 -> movl $imm32, %r32
4317 i
.tm
.opcode_modifier
.size
= SIZE32
;
4320 i
.types
[0].bitfield
.imm32
= 1;
4321 i
.types
[0].bitfield
.imm32s
= 0;
4322 i
.types
[0].bitfield
.imm64
= 0;
4326 i
.types
[0].bitfield
.dword
= 1;
4327 i
.types
[0].bitfield
.qword
= 0;
4329 i
.types
[1].bitfield
.dword
= 1;
4330 i
.types
[1].bitfield
.qword
= 0;
4331 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4334 movq $imm31, %r64 -> movl $imm31, %r32
4335 movq $imm32, %r64 -> movl $imm32, %r32
4337 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4338 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4339 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4340 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4343 movq $imm31, %r64 -> movl $imm31, %r32
4345 i
.tm
.base_opcode
= 0xb8;
4346 i
.tm
.extension_opcode
= None
;
4347 i
.tm
.opcode_modifier
.w
= 0;
4348 i
.tm
.opcode_modifier
.modrm
= 0;
4352 else if (optimize
> 1
4353 && !optimize_for_space
4354 && i
.reg_operands
== 2
4355 && i
.op
[0].regs
== i
.op
[1].regs
4356 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4357 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4360 andb %rN, %rN -> testb %rN, %rN
4361 andw %rN, %rN -> testw %rN, %rN
4362 andq %rN, %rN -> testq %rN, %rN
4363 orb %rN, %rN -> testb %rN, %rN
4364 orw %rN, %rN -> testw %rN, %rN
4365 orq %rN, %rN -> testq %rN, %rN
4367 and outside of 64-bit mode
4369 andl %rN, %rN -> testl %rN, %rN
4370 orl %rN, %rN -> testl %rN, %rN
4372 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4374 else if (i
.tm
.base_opcode
== 0xba
4375 && i
.tm
.opcode_space
== SPACE_0F
4376 && i
.reg_operands
== 1
4377 && i
.op
[0].imms
->X_op
== O_constant
4378 && i
.op
[0].imms
->X_add_number
>= 0)
4381 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4382 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4383 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4385 With <BT> one of bts, btr, and bts also:
4386 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4387 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4392 if (i
.tm
.extension_opcode
!= 4)
4394 if (i
.types
[1].bitfield
.qword
4395 && i
.op
[0].imms
->X_add_number
< 32
4396 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4397 i
.tm
.opcode_modifier
.size
= SIZE32
;
4400 if (i
.types
[1].bitfield
.word
4401 && i
.op
[0].imms
->X_add_number
< 16)
4402 i
.tm
.opcode_modifier
.size
= SIZE32
;
4405 if (i
.op
[0].imms
->X_add_number
< 16)
4406 i
.tm
.opcode_modifier
.size
= SIZE16
;
4410 else if (i
.reg_operands
== 3
4411 && i
.op
[0].regs
== i
.op
[1].regs
4412 && !i
.types
[2].bitfield
.xmmword
4413 && (i
.tm
.opcode_modifier
.vex
4414 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4415 && is_evex_encoding (&i
.tm
)
4416 && (i
.vec_encoding
!= vex_encoding_evex
4417 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4418 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4419 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4420 && i
.types
[2].bitfield
.ymmword
))))
4421 && i
.tm
.opcode_space
== SPACE_0F
4422 && ((i
.tm
.base_opcode
| 2) == 0x57
4423 || i
.tm
.base_opcode
== 0xdf
4424 || i
.tm
.base_opcode
== 0xef
4425 || (i
.tm
.base_opcode
| 3) == 0xfb
4426 || i
.tm
.base_opcode
== 0x42
4427 || i
.tm
.base_opcode
== 0x47))
4430 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4432 EVEX VOP %zmmM, %zmmM, %zmmN
4433 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4434 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4435 EVEX VOP %ymmM, %ymmM, %ymmN
4436 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4437 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4438 VEX VOP %ymmM, %ymmM, %ymmN
4439 -> VEX VOP %xmmM, %xmmM, %xmmN
4440 VOP, one of vpandn and vpxor:
4441 VEX VOP %ymmM, %ymmM, %ymmN
4442 -> VEX VOP %xmmM, %xmmM, %xmmN
4443 VOP, one of vpandnd and vpandnq:
4444 EVEX VOP %zmmM, %zmmM, %zmmN
4445 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4446 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4447 EVEX VOP %ymmM, %ymmM, %ymmN
4448 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4449 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4450 VOP, one of vpxord and vpxorq:
4451 EVEX VOP %zmmM, %zmmM, %zmmN
4452 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4453 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4454 EVEX VOP %ymmM, %ymmM, %ymmN
4455 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4456 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4457 VOP, one of kxord and kxorq:
4458 VEX VOP %kM, %kM, %kN
4459 -> VEX kxorw %kM, %kM, %kN
4460 VOP, one of kandnd and kandnq:
4461 VEX VOP %kM, %kM, %kN
4462 -> VEX kandnw %kM, %kM, %kN
4464 if (is_evex_encoding (&i
.tm
))
4466 if (i
.vec_encoding
!= vex_encoding_evex
)
4468 i
.tm
.opcode_modifier
.vex
= VEX128
;
4469 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4470 i
.tm
.opcode_modifier
.evex
= 0;
4472 else if (optimize
> 1)
4473 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4477 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4479 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4480 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4483 i
.tm
.opcode_modifier
.vex
= VEX128
;
4485 if (i
.tm
.opcode_modifier
.vex
)
4486 for (j
= 0; j
< 3; j
++)
4488 i
.types
[j
].bitfield
.xmmword
= 1;
4489 i
.types
[j
].bitfield
.ymmword
= 0;
4492 else if (i
.vec_encoding
!= vex_encoding_evex
4493 && !i
.types
[0].bitfield
.zmmword
4494 && !i
.types
[1].bitfield
.zmmword
4496 && !i
.broadcast
.type
4497 && !i
.broadcast
.bytes
4498 && is_evex_encoding (&i
.tm
)
4499 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4500 || (i
.tm
.base_opcode
& ~4) == 0xdb
4501 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4502 && i
.tm
.extension_opcode
== None
)
4505 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4506 vmovdqu32 and vmovdqu64:
4507 EVEX VOP %xmmM, %xmmN
4508 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4509 EVEX VOP %ymmM, %ymmN
4510 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4512 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4514 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4516 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4518 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4519 VOP, one of vpand, vpandn, vpor, vpxor:
4520 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4521 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4522 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4523 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4524 EVEX VOP{d,q} mem, %xmmM, %xmmN
4525 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4526 EVEX VOP{d,q} mem, %ymmM, %ymmN
4527 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4529 for (j
= 0; j
< i
.operands
; j
++)
4530 if (operand_type_check (i
.types
[j
], disp
)
4531 && i
.op
[j
].disps
->X_op
== O_constant
)
4533 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4534 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4535 bytes, we choose EVEX Disp8 over VEX Disp32. */
4536 int evex_disp8
, vex_disp8
;
4537 unsigned int memshift
= i
.memshift
;
4538 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4540 evex_disp8
= fits_in_disp8 (n
);
4542 vex_disp8
= fits_in_disp8 (n
);
4543 if (evex_disp8
!= vex_disp8
)
4545 i
.memshift
= memshift
;
4549 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4552 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4553 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4554 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4555 i
.tm
.opcode_modifier
.vex
4556 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4557 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4558 /* VPAND, VPOR, and VPXOR are commutative. */
4559 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4560 i
.tm
.opcode_modifier
.commutative
= 1;
4561 i
.tm
.opcode_modifier
.evex
= 0;
4562 i
.tm
.opcode_modifier
.masking
= 0;
4563 i
.tm
.opcode_modifier
.broadcast
= 0;
4564 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4567 i
.types
[j
].bitfield
.disp8
4568 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4570 else if (optimize_for_space
4571 && i
.tm
.base_opcode
== 0x29
4572 && i
.tm
.opcode_space
== SPACE_0F38
4573 && i
.operands
== i
.reg_operands
4574 && i
.op
[0].regs
== i
.op
[1].regs
4575 && (!i
.tm
.opcode_modifier
.vex
4576 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4577 && !is_evex_encoding (&i
.tm
))
4580 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4581 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4582 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4584 i
.tm
.opcode_space
= SPACE_0F
;
4585 i
.tm
.base_opcode
= 0x76;
4587 else if (((i
.tm
.base_opcode
>= 0x64
4588 && i
.tm
.base_opcode
<= 0x66
4589 && i
.tm
.opcode_space
== SPACE_0F
)
4590 || (i
.tm
.base_opcode
== 0x37
4591 && i
.tm
.opcode_space
== SPACE_0F38
))
4592 && i
.operands
== i
.reg_operands
4593 && i
.op
[0].regs
== i
.op
[1].regs
4594 && !is_evex_encoding (&i
.tm
))
4597 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4598 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4599 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4600 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4601 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4602 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4604 i
.tm
.opcode_space
= SPACE_0F
;
4605 i
.tm
.base_opcode
= 0xef;
4606 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4608 if (i
.operands
== 2)
4610 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4616 i
.op
[2].regs
= i
.op
[0].regs
;
4617 i
.types
[2] = i
.types
[0];
4618 i
.flags
[2] = i
.flags
[0];
4619 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4621 i
.tm
.opcode_modifier
.sse2avx
= 0;
4623 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4624 i
.op
[1].regs
= i
.op
[0].regs
;
4627 else if (optimize_for_space
4628 && i
.tm
.base_opcode
== 0x59
4629 && i
.tm
.opcode_space
== SPACE_0F38
4630 && i
.operands
== i
.reg_operands
4631 && i
.tm
.opcode_modifier
.vex
4632 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4633 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4634 && i
.vec_encoding
!= vex_encoding_vex3
)
4637 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4639 i
.tm
.opcode_space
= SPACE_0F
;
4640 i
.tm
.base_opcode
= 0x6c;
4641 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4647 i
.op
[2].regs
= i
.op
[0].regs
;
4648 i
.types
[2] = i
.types
[0];
4649 i
.flags
[2] = i
.flags
[0];
4650 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4652 swap_2_operands (1, 2);
4656 /* Return non-zero for load instruction. */
4662 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4663 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4667 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4668 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4669 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4673 if (i
.tm
.mnem_off
== MN_pop
)
4677 if (i
.tm
.opcode_space
== SPACE_BASE
)
4680 if (i
.tm
.base_opcode
== 0x9d
4681 || i
.tm
.base_opcode
== 0x61)
4684 /* movs, cmps, lods, scas. */
4685 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4689 if (base_opcode
== 0x6f
4690 || i
.tm
.base_opcode
== 0xd7)
4692 /* NB: For AMD-specific insns with implicit memory operands,
4693 they're intentionally not covered. */
4696 /* No memory operand. */
4697 if (!i
.mem_operands
)
4702 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4705 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4707 /* test, not, neg, mul, imul, div, idiv. */
4708 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4712 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4715 /* add, or, adc, sbb, and, sub, xor, cmp. */
4716 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4719 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4720 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4721 && i
.tm
.extension_opcode
!= 6)
4724 /* Check for x87 instructions. */
4725 if ((base_opcode
| 6) == 0xdf)
4727 /* Skip fst, fstp, fstenv, fstcw. */
4728 if (i
.tm
.base_opcode
== 0xd9
4729 && (i
.tm
.extension_opcode
== 2
4730 || i
.tm
.extension_opcode
== 3
4731 || i
.tm
.extension_opcode
== 6
4732 || i
.tm
.extension_opcode
== 7))
4735 /* Skip fisttp, fist, fistp, fstp. */
4736 if (i
.tm
.base_opcode
== 0xdb
4737 && (i
.tm
.extension_opcode
== 1
4738 || i
.tm
.extension_opcode
== 2
4739 || i
.tm
.extension_opcode
== 3
4740 || i
.tm
.extension_opcode
== 7))
4743 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4744 if (i
.tm
.base_opcode
== 0xdd
4745 && (i
.tm
.extension_opcode
== 1
4746 || i
.tm
.extension_opcode
== 2
4747 || i
.tm
.extension_opcode
== 3
4748 || i
.tm
.extension_opcode
== 6
4749 || i
.tm
.extension_opcode
== 7))
4752 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4753 if (i
.tm
.base_opcode
== 0xdf
4754 && (i
.tm
.extension_opcode
== 1
4755 || i
.tm
.extension_opcode
== 2
4756 || i
.tm
.extension_opcode
== 3
4757 || i
.tm
.extension_opcode
== 6
4758 || i
.tm
.extension_opcode
== 7))
4764 else if (i
.tm
.opcode_space
== SPACE_0F
)
4766 /* bt, bts, btr, btc. */
4767 if (i
.tm
.base_opcode
== 0xba
4768 && (i
.tm
.extension_opcode
| 3) == 7)
4771 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4772 if (i
.tm
.base_opcode
== 0xc7
4773 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4774 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4775 || i
.tm
.extension_opcode
== 6))
4778 /* fxrstor, ldmxcsr, xrstor. */
4779 if (i
.tm
.base_opcode
== 0xae
4780 && (i
.tm
.extension_opcode
== 1
4781 || i
.tm
.extension_opcode
== 2
4782 || i
.tm
.extension_opcode
== 5))
4785 /* lgdt, lidt, lmsw. */
4786 if (i
.tm
.base_opcode
== 0x01
4787 && (i
.tm
.extension_opcode
== 2
4788 || i
.tm
.extension_opcode
== 3
4789 || i
.tm
.extension_opcode
== 6))
4793 dest
= i
.operands
- 1;
4795 /* Check fake imm8 operand and 3 source operands. */
4796 if ((i
.tm
.opcode_modifier
.immext
4797 || i
.reg_operands
+ i
.mem_operands
== 4)
4798 && i
.types
[dest
].bitfield
.imm8
)
4801 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4802 if (i
.tm
.opcode_space
== SPACE_BASE
4803 && ((base_opcode
| 0x38) == 0x39
4804 || (base_opcode
| 2) == 0x87))
4807 if (i
.tm
.mnem_off
== MN_xadd
)
4810 /* Check for load instruction. */
4811 return (i
.types
[dest
].bitfield
.class != ClassNone
4812 || i
.types
[dest
].bitfield
.instance
== Accum
);
4815 /* Output lfence, 0xfaee8, after instruction. */
4818 insert_lfence_after (void)
4820 if (lfence_after_load
&& load_insn_p ())
4822 /* There are also two REP string instructions that require
4823 special treatment. Specifically, the compare string (CMPS)
4824 and scan string (SCAS) instructions set EFLAGS in a manner
4825 that depends on the data being compared/scanned. When used
4826 with a REP prefix, the number of iterations may therefore
4827 vary depending on this data. If the data is a program secret
4828 chosen by the adversary using an LVI method,
4829 then this data-dependent behavior may leak some aspect
4831 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4832 && i
.prefix
[REP_PREFIX
])
4834 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4837 char *p
= frag_more (3);
4844 /* Output lfence, 0xfaee8, before instruction. */
4847 insert_lfence_before (void)
4851 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4854 if (i
.tm
.base_opcode
== 0xff
4855 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4857 /* Insert lfence before indirect branch if needed. */
4859 if (lfence_before_indirect_branch
== lfence_branch_none
)
4862 if (i
.operands
!= 1)
4865 if (i
.reg_operands
== 1)
4867 /* Indirect branch via register. Don't insert lfence with
4868 -mlfence-after-load=yes. */
4869 if (lfence_after_load
4870 || lfence_before_indirect_branch
== lfence_branch_memory
)
4873 else if (i
.mem_operands
== 1
4874 && lfence_before_indirect_branch
!= lfence_branch_register
)
4876 as_warn (_("indirect `%s` with memory operand should be avoided"),
4883 if (last_insn
.kind
!= last_insn_other
4884 && last_insn
.seg
== now_seg
)
4886 as_warn_where (last_insn
.file
, last_insn
.line
,
4887 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4888 last_insn
.name
, insn_name (&i
.tm
));
4899 /* Output or/not/shl and lfence before near ret. */
4900 if (lfence_before_ret
!= lfence_before_ret_none
4901 && (i
.tm
.base_opcode
| 1) == 0xc3)
4903 if (last_insn
.kind
!= last_insn_other
4904 && last_insn
.seg
== now_seg
)
4906 as_warn_where (last_insn
.file
, last_insn
.line
,
4907 _("`%s` skips -mlfence-before-ret on `%s`"),
4908 last_insn
.name
, insn_name (&i
.tm
));
4912 /* Near ret ingore operand size override under CPU64. */
4913 char prefix
= flag_code
== CODE_64BIT
4915 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4917 if (lfence_before_ret
== lfence_before_ret_not
)
4919 /* not: 0xf71424, may add prefix
4920 for operand size override or 64-bit code. */
4921 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4935 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4938 if (lfence_before_ret
== lfence_before_ret_or
)
4940 /* or: 0x830c2400, may add prefix
4941 for operand size override or 64-bit code. */
4947 /* shl: 0xc1242400, may add prefix
4948 for operand size override or 64-bit code. */
4963 /* Shared helper for md_assemble() and s_insn(). */
4964 static void init_globals (void)
4968 memset (&i
, '\0', sizeof (i
));
4969 i
.rounding
.type
= rc_none
;
4970 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4971 i
.reloc
[j
] = NO_RELOC
;
4972 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4973 memset (im_expressions
, '\0', sizeof (im_expressions
));
4974 save_stack_p
= save_stack
;
4977 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
4978 parsing pass. Instead of introducing a rarely use new insn attribute this
4979 utilizes a common pattern between affected templates. It is deemed
4980 acceptable that this will lead to unnecessary pass 2 preparations in a
4981 limited set of cases. */
4982 static INLINE
bool may_need_pass2 (const insn_template
*t
)
4984 return t
->opcode_modifier
.sse2avx
4985 /* Note that all SSE2AVX templates have at least one operand. */
4986 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
4987 : (t
->opcode_space
== SPACE_0F
4988 && (t
->base_opcode
| 1) == 0xbf)
4989 || (t
->opcode_space
== SPACE_BASE
4990 && t
->base_opcode
== 0x63);
4993 /* This is the guts of the machine-dependent assembler. LINE points to a
4994 machine dependent instruction. This function is supposed to emit
4995 the frags/bytes it assembles to. */
4998 md_assemble (char *line
)
5001 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5002 const char *end
, *pass1_mnem
= NULL
;
5003 enum i386_error pass1_err
= 0;
5004 const insn_template
*t
;
5006 /* Initialize globals. */
5007 current_templates
= NULL
;
5011 /* First parse an instruction mnemonic & call i386_operand for the operands.
5012 We assume that the scrubber has arranged it so that line[0] is the valid
5013 start of a (possibly prefixed) mnemonic. */
5015 end
= parse_insn (line
, mnemonic
, false);
5018 if (pass1_mnem
!= NULL
)
5020 if (i
.error
!= no_error
)
5022 gas_assert (current_templates
!= NULL
);
5023 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5025 /* No point in trying a 2nd pass - it'll only find the same suffix
5027 mnem_suffix
= i
.suffix
;
5032 t
= current_templates
->start
;
5033 if (may_need_pass2 (t
))
5035 /* Make a copy of the full line in case we need to retry. */
5036 copy
= xstrdup (line
);
5039 mnem_suffix
= i
.suffix
;
5041 line
= parse_operands (line
, mnemonic
);
5049 /* Now we've parsed the mnemonic into a set of templates, and have the
5050 operands at hand. */
5052 /* All Intel opcodes have reversed operands except for "bound", "enter",
5053 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5054 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5055 intersegment "jmp" and "call" instructions with 2 immediate operands so
5056 that the immediate segment precedes the offset consistently in Intel and
5060 && (t
->mnem_off
!= MN_bound
)
5061 && !startswith (mnemonic
, "invlpg")
5062 && !startswith (mnemonic
, "monitor")
5063 && !startswith (mnemonic
, "mwait")
5064 && (t
->mnem_off
!= MN_pvalidate
)
5065 && !startswith (mnemonic
, "rmp")
5066 && (t
->mnem_off
!= MN_tpause
)
5067 && (t
->mnem_off
!= MN_umwait
)
5068 && !(i
.operands
== 2
5069 && operand_type_check (i
.types
[0], imm
)
5070 && operand_type_check (i
.types
[1], imm
)))
5073 /* The order of the immediates should be reversed
5074 for 2 immediates extrq and insertq instructions */
5075 if (i
.imm_operands
== 2
5076 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5077 swap_2_operands (0, 1);
5082 if (i
.disp_operands
&& !optimize_disp (t
))
5085 /* Next, we find a template that matches the given insn,
5086 making sure the overlap of the given operands types is consistent
5087 with the template operand types. */
5089 if (!(t
= match_template (mnem_suffix
)))
5091 const char *err_msg
;
5093 if (copy
&& !mnem_suffix
)
5098 pass1_err
= i
.error
;
5099 pass1_mnem
= insn_name (current_templates
->start
);
5103 /* If a non-/only-64bit template (group) was found in pass 1, and if
5104 _some_ template (group) was found in pass 2, squash pass 1's
5106 if (pass1_err
== unsupported_64bit
)
5112 switch (pass1_mnem
? pass1_err
: i
.error
)
5116 case operand_size_mismatch
:
5117 err_msg
= _("operand size mismatch");
5119 case operand_type_mismatch
:
5120 err_msg
= _("operand type mismatch");
5122 case register_type_mismatch
:
5123 err_msg
= _("register type mismatch");
5125 case number_of_operands_mismatch
:
5126 err_msg
= _("number of operands mismatch");
5128 case invalid_instruction_suffix
:
5129 err_msg
= _("invalid instruction suffix");
5132 err_msg
= _("constant doesn't fit in 4 bits");
5134 case unsupported_with_intel_mnemonic
:
5135 err_msg
= _("unsupported with Intel mnemonic");
5137 case unsupported_syntax
:
5138 err_msg
= _("unsupported syntax");
5141 as_bad (_("unsupported instruction `%s'"),
5142 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5144 case unsupported_on_arch
:
5145 as_bad (_("`%s' is not supported on `%s%s'"),
5146 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5147 cpu_arch_name
? cpu_arch_name
: default_arch
,
5148 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5150 case unsupported_64bit
:
5151 if (ISLOWER (mnem_suffix
))
5153 if (flag_code
== CODE_64BIT
)
5154 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5155 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5158 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5159 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5164 if (flag_code
== CODE_64BIT
)
5165 as_bad (_("`%s' is not supported in 64-bit mode"),
5166 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5168 as_bad (_("`%s' is only supported in 64-bit mode"),
5169 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5172 case invalid_sib_address
:
5173 err_msg
= _("invalid SIB address");
5175 case invalid_vsib_address
:
5176 err_msg
= _("invalid VSIB address");
5178 case invalid_vector_register_set
:
5179 err_msg
= _("mask, index, and destination registers must be distinct");
5181 case invalid_tmm_register_set
:
5182 err_msg
= _("all tmm registers must be distinct");
5184 case invalid_dest_and_src_register_set
:
5185 err_msg
= _("destination and source registers must be distinct");
5187 case unsupported_vector_index_register
:
5188 err_msg
= _("unsupported vector index register");
5190 case unsupported_broadcast
:
5191 err_msg
= _("unsupported broadcast");
5193 case broadcast_needed
:
5194 err_msg
= _("broadcast is needed for operand of such type");
5196 case unsupported_masking
:
5197 err_msg
= _("unsupported masking");
5199 case mask_not_on_destination
:
5200 err_msg
= _("mask not on destination operand");
5202 case no_default_mask
:
5203 err_msg
= _("default mask isn't allowed");
5205 case unsupported_rc_sae
:
5206 err_msg
= _("unsupported static rounding/sae");
5208 case invalid_register_operand
:
5209 err_msg
= _("invalid register operand");
5212 as_bad (_("%s for `%s'"), err_msg
,
5213 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5219 if (sse_check
!= check_none
5220 /* The opcode space check isn't strictly needed; it's there only to
5221 bypass the logic below when easily possible. */
5222 && t
->opcode_space
>= SPACE_0F
5223 && t
->opcode_space
<= SPACE_0F3A
5224 && !i
.tm
.cpu_flags
.bitfield
.cpusse4a
5225 && !is_any_vex_encoding (t
))
5229 for (j
= 0; j
< t
->operands
; ++j
)
5231 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5233 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5237 if (j
>= t
->operands
&& simd
)
5238 (sse_check
== check_warning
5240 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5243 if (i
.tm
.opcode_modifier
.fwait
)
5244 if (!add_prefix (FWAIT_OPCODE
))
5247 /* Check if REP prefix is OK. */
5248 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5250 as_bad (_("invalid instruction `%s' after `%s'"),
5251 insn_name (&i
.tm
), i
.rep_prefix
);
5255 /* Check for lock without a lockable instruction. Destination operand
5256 must be memory unless it is xchg (0x86). */
5257 if (i
.prefix
[LOCK_PREFIX
])
5259 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5260 || i
.mem_operands
== 0
5261 || (i
.tm
.base_opcode
!= 0x86
5262 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5264 as_bad (_("expecting lockable instruction after `lock'"));
5268 /* Zap the redundant prefix from XCHG when optimizing. */
5269 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5270 i
.prefix
[LOCK_PREFIX
] = 0;
5273 if (is_any_vex_encoding (&i
.tm
)
5274 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5275 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5277 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5278 if (i
.prefix
[DATA_PREFIX
])
5280 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5284 /* Don't allow e.g. KMOV in TLS code sequences. */
5285 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5288 case BFD_RELOC_386_TLS_GOTIE
:
5289 case BFD_RELOC_386_TLS_LE_32
:
5290 case BFD_RELOC_X86_64_GOTTPOFF
:
5291 case BFD_RELOC_X86_64_TLSLD
:
5292 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5299 /* Check if HLE prefix is OK. */
5300 if (i
.hle_prefix
&& !check_hle ())
5303 /* Check BND prefix. */
5304 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5305 as_bad (_("expecting valid branch instruction after `bnd'"));
5307 /* Check NOTRACK prefix. */
5308 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5309 as_bad (_("expecting indirect branch instruction after `notrack'"));
5311 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5313 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5314 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5315 else if (flag_code
!= CODE_16BIT
5316 ? i
.prefix
[ADDR_PREFIX
]
5317 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5318 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5321 /* Insert BND prefix. */
5322 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5324 if (!i
.prefix
[BND_PREFIX
])
5325 add_prefix (BND_PREFIX_OPCODE
);
5326 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5328 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5329 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5333 /* Check string instruction segment overrides. */
5334 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5336 gas_assert (i
.mem_operands
);
5337 if (!check_string ())
5339 i
.disp_operands
= 0;
5342 /* The memory operand of (%dx) should be only used with input/output
5343 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5344 if (i
.input_output_operand
5345 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5346 || i
.tm
.opcode_space
!= SPACE_BASE
))
5348 as_bad (_("input/output port address isn't allowed with `%s'"),
5353 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5354 optimize_encoding ();
5356 if (use_unaligned_vector_move
)
5357 encode_with_unaligned_vector_move ();
5359 if (!process_suffix ())
5362 /* Check if IP-relative addressing requirements can be satisfied. */
5363 if (i
.tm
.cpu_flags
.bitfield
.cpuprefetchi
5364 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5365 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5367 /* Update operand types and check extended states. */
5368 for (j
= 0; j
< i
.operands
; j
++)
5370 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5371 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5376 i
.xstate
|= xstate_mmx
;
5379 i
.xstate
|= xstate_mask
;
5382 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5383 i
.xstate
|= xstate_tmm
;
5384 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5385 i
.xstate
|= xstate_zmm
;
5386 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5387 i
.xstate
|= xstate_ymm
;
5388 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5389 i
.xstate
|= xstate_xmm
;
5394 /* Make still unresolved immediate matches conform to size of immediate
5395 given in i.suffix. */
5396 if (!finalize_imm ())
5399 if (i
.types
[0].bitfield
.imm1
)
5400 i
.imm_operands
= 0; /* kludge for shift insns. */
5402 /* For insns with operands there are more diddles to do to the opcode. */
5405 if (!process_operands ())
5408 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5410 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5411 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5414 if (is_any_vex_encoding (&i
.tm
))
5416 if (!cpu_arch_flags
.bitfield
.cpui286
)
5418 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5423 /* Check for explicit REX prefix. */
5424 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5426 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5430 if (i
.tm
.opcode_modifier
.vex
)
5431 build_vex_prefix (t
);
5433 build_evex_prefix ();
5435 /* The individual REX.RXBW bits got consumed. */
5436 i
.rex
&= REX_OPCODE
;
5439 /* Handle conversion of 'int $3' --> special int3 insn. */
5440 if (i
.tm
.mnem_off
== MN_int
5441 && i
.op
[0].imms
->X_add_number
== 3)
5443 i
.tm
.base_opcode
= INT3_OPCODE
;
5447 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5448 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5449 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5450 && i
.op
[0].disps
->X_op
== O_constant
)
5452 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5453 the absolute address given by the constant. Since ix86 jumps and
5454 calls are pc relative, we need to generate a reloc. */
5455 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5456 i
.op
[0].disps
->X_op
= O_symbol
;
5459 /* For 8 bit registers we need an empty rex prefix. Also if the
5460 instruction already has a prefix, we need to convert old
5461 registers to new ones. */
5463 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5464 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5465 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5466 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5467 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5468 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5473 i
.rex
|= REX_OPCODE
;
5474 for (x
= 0; x
< 2; x
++)
5476 /* Look for 8 bit operand that uses old registers. */
5477 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5478 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5480 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5481 /* In case it is "hi" register, give up. */
5482 if (i
.op
[x
].regs
->reg_num
> 3)
5483 as_bad (_("can't encode register '%s%s' in an "
5484 "instruction requiring REX prefix."),
5485 register_prefix
, i
.op
[x
].regs
->reg_name
);
5487 /* Otherwise it is equivalent to the extended register.
5488 Since the encoding doesn't change this is merely
5489 cosmetic cleanup for debug output. */
5491 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5496 if (i
.rex
== 0 && i
.rex_encoding
)
5498 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5499 that uses legacy register. If it is "hi" register, don't add
5500 the REX_OPCODE byte. */
5502 for (x
= 0; x
< 2; x
++)
5503 if (i
.types
[x
].bitfield
.class == Reg
5504 && i
.types
[x
].bitfield
.byte
5505 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5506 && i
.op
[x
].regs
->reg_num
> 3)
5508 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5509 i
.rex_encoding
= false;
5518 add_prefix (REX_OPCODE
| i
.rex
);
5520 insert_lfence_before ();
5522 /* We are ready to output the insn. */
5525 insert_lfence_after ();
5527 last_insn
.seg
= now_seg
;
5529 if (i
.tm
.opcode_modifier
.isprefix
)
5531 last_insn
.kind
= last_insn_prefix
;
5532 last_insn
.name
= insn_name (&i
.tm
);
5533 last_insn
.file
= as_where (&last_insn
.line
);
5536 last_insn
.kind
= last_insn_other
;
5539 /* The Q suffix is generally valid only in 64-bit mode, with very few
5540 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5541 and fisttp only one of their two templates is matched below: That's
5542 sufficient since other relevant attributes are the same between both
5543 respective templates. */
5544 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5546 return flag_code
== CODE_64BIT
5547 || (t
->opcode_space
== SPACE_BASE
5548 && t
->base_opcode
== 0xdf
5549 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5550 || t
->mnem_off
== MN_cmpxchg8b
;
5554 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5556 const char *l
= line
, *token_start
= l
;
5558 bool pass1
= !current_templates
;
5560 const insn_template
*t
;
5566 /* Pseudo-prefixes start with an opening figure brace. */
5567 if ((*mnem_p
= *l
) == '{')
5572 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5577 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5580 as_bad (_("no such instruction: `%s'"), token_start
);
5585 /* Pseudo-prefixes end with a closing figure brace. */
5586 if (*mnemonic
== '{' && *l
== '}')
5589 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5593 /* Point l at the closing brace if there's no other separator. */
5594 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5595 && *l
!= PREFIX_SEPARATOR
)
5598 else if (!is_space_char (*l
)
5599 && *l
!= END_OF_INSN
5601 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5605 as_bad (_("invalid character %s in mnemonic"),
5606 output_invalid (*l
));
5609 if (token_start
== l
)
5611 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5612 as_bad (_("expecting prefix; got nothing"));
5614 as_bad (_("expecting mnemonic; got nothing"));
5618 /* Look up instruction (or prefix) via hash table. */
5619 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5621 if (*l
!= END_OF_INSN
5622 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5623 && current_templates
5624 && current_templates
->start
->opcode_modifier
.isprefix
)
5626 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5628 as_bad ((flag_code
!= CODE_64BIT
5629 ? _("`%s' is only supported in 64-bit mode")
5630 : _("`%s' is not supported in 64-bit mode")),
5631 insn_name (current_templates
->start
));
5634 /* If we are in 16-bit mode, do not allow addr16 or data16.
5635 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5636 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5637 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5638 && flag_code
!= CODE_64BIT
5639 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5640 ^ (flag_code
== CODE_16BIT
)))
5642 as_bad (_("redundant %s prefix"),
5643 insn_name (current_templates
->start
));
5647 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5649 /* Handle pseudo prefixes. */
5650 switch (current_templates
->start
->extension_opcode
)
5654 i
.disp_encoding
= disp_encoding_8bit
;
5658 i
.disp_encoding
= disp_encoding_16bit
;
5662 i
.disp_encoding
= disp_encoding_32bit
;
5666 i
.dir_encoding
= dir_encoding_load
;
5670 i
.dir_encoding
= dir_encoding_store
;
5674 i
.vec_encoding
= vex_encoding_vex
;
5678 i
.vec_encoding
= vex_encoding_vex3
;
5682 i
.vec_encoding
= vex_encoding_evex
;
5686 i
.rex_encoding
= true;
5688 case Prefix_NoOptimize
:
5690 i
.no_optimize
= true;
5698 /* Add prefix, checking for repeated prefixes. */
5699 switch (add_prefix (current_templates
->start
->base_opcode
))
5704 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5705 i
.notrack_prefix
= insn_name (current_templates
->start
);
5708 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5709 i
.hle_prefix
= insn_name (current_templates
->start
);
5710 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5711 i
.bnd_prefix
= insn_name (current_templates
->start
);
5713 i
.rep_prefix
= insn_name (current_templates
->start
);
5719 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5729 if (!current_templates
)
5731 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5732 Check if we should swap operand or force 32bit displacement in
5734 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5735 i
.dir_encoding
= dir_encoding_swap
;
5736 else if (mnem_p
- 3 == dot_p
5739 i
.disp_encoding
= disp_encoding_8bit
;
5740 else if (mnem_p
- 4 == dot_p
5744 i
.disp_encoding
= disp_encoding_32bit
;
5749 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5752 if (!current_templates
|| !pass1
)
5754 current_templates
= NULL
;
5757 if (mnem_p
> mnemonic
)
5759 /* See if we can get a match by trimming off a suffix. */
5762 case WORD_MNEM_SUFFIX
:
5763 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5764 i
.suffix
= SHORT_MNEM_SUFFIX
;
5767 case BYTE_MNEM_SUFFIX
:
5768 case QWORD_MNEM_SUFFIX
:
5769 i
.suffix
= mnem_p
[-1];
5772 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5774 case SHORT_MNEM_SUFFIX
:
5775 case LONG_MNEM_SUFFIX
:
5778 i
.suffix
= mnem_p
[-1];
5781 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5789 if (intel_float_operand (mnemonic
) == 1)
5790 i
.suffix
= SHORT_MNEM_SUFFIX
;
5792 i
.suffix
= LONG_MNEM_SUFFIX
;
5795 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5797 /* For compatibility reasons accept MOVSD and CMPSD without
5798 operands even in AT&T mode. */
5799 else if (*l
== END_OF_INSN
5800 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5804 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5805 if (current_templates
!= NULL
5807 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5808 && current_templates
->start
->opcode_space
5810 && mnem_p
[-2] == 's')
5812 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5813 mnemonic
, mnemonic
);
5814 i
.suffix
= LONG_MNEM_SUFFIX
;
5818 current_templates
= NULL
;
5826 if (!current_templates
)
5829 as_bad (_("no such instruction: `%s'"), token_start
);
5834 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5835 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5837 /* Check for a branch hint. We allow ",pt" and ",pn" for
5838 predict taken and predict not taken respectively.
5839 I'm not sure that branch hints actually do anything on loop
5840 and jcxz insns (JumpByte) for current Pentium4 chips. They
5841 may work in the future and it doesn't hurt to accept them
5843 if (l
[0] == ',' && l
[1] == 'p')
5847 if (!add_prefix (DS_PREFIX_OPCODE
))
5851 else if (l
[2] == 'n')
5853 if (!add_prefix (CS_PREFIX_OPCODE
))
5859 /* Any other comma loses. */
5862 as_bad (_("invalid character %s in mnemonic"),
5863 output_invalid (*l
));
5867 /* Check if instruction is supported on specified architecture. */
5869 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5871 supported
|= cpu_flags_match (t
);
5873 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5874 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5876 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5882 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5883 i
.error
= unsupported_on_arch
;
5885 i
.error
= unsupported_64bit
;
5892 parse_operands (char *l
, const char *mnemonic
)
5896 /* 1 if operand is pending after ','. */
5897 unsigned int expecting_operand
= 0;
5899 while (*l
!= END_OF_INSN
)
5901 /* Non-zero if operand parens not balanced. */
5902 unsigned int paren_not_balanced
= 0;
5903 /* True if inside double quotes. */
5904 bool in_quotes
= false;
5906 /* Skip optional white space before operand. */
5907 if (is_space_char (*l
))
5909 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5911 as_bad (_("invalid character %s before operand %d"),
5912 output_invalid (*l
),
5916 token_start
= l
; /* After white space. */
5917 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5919 if (*l
== END_OF_INSN
)
5923 as_bad (_("unbalanced double quotes in operand %d."),
5927 if (paren_not_balanced
)
5929 know (!intel_syntax
);
5930 as_bad (_("unbalanced parenthesis in operand %d."),
5935 break; /* we are done */
5937 else if (*l
== '\\' && l
[1] == '"')
5940 in_quotes
= !in_quotes
;
5941 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5943 as_bad (_("invalid character %s in operand %d"),
5944 output_invalid (*l
),
5948 if (!intel_syntax
&& !in_quotes
)
5951 ++paren_not_balanced
;
5953 --paren_not_balanced
;
5957 if (l
!= token_start
)
5958 { /* Yes, we've read in another operand. */
5959 unsigned int operand_ok
;
5960 this_operand
= i
.operands
++;
5961 if (i
.operands
> MAX_OPERANDS
)
5963 as_bad (_("spurious operands; (%d operands/instruction max)"),
5967 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5968 /* Now parse operand adding info to 'i' as we go along. */
5969 END_STRING_AND_SAVE (l
);
5971 if (i
.mem_operands
> 1)
5973 as_bad (_("too many memory references for `%s'"),
5980 i386_intel_operand (token_start
,
5981 intel_float_operand (mnemonic
));
5983 operand_ok
= i386_att_operand (token_start
);
5985 RESTORE_END_STRING (l
);
5991 if (expecting_operand
)
5993 expecting_operand_after_comma
:
5994 as_bad (_("expecting operand after ','; got nothing"));
5999 as_bad (_("expecting operand before ','; got nothing"));
6004 /* Now *l must be either ',' or END_OF_INSN. */
6007 if (*++l
== END_OF_INSN
)
6009 /* Just skip it, if it's \n complain. */
6010 goto expecting_operand_after_comma
;
6012 expecting_operand
= 1;
6019 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6021 union i386_op temp_op
;
6022 i386_operand_type temp_type
;
6023 unsigned int temp_flags
;
6024 enum bfd_reloc_code_real temp_reloc
;
6026 temp_type
= i
.types
[xchg2
];
6027 i
.types
[xchg2
] = i
.types
[xchg1
];
6028 i
.types
[xchg1
] = temp_type
;
6030 temp_flags
= i
.flags
[xchg2
];
6031 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6032 i
.flags
[xchg1
] = temp_flags
;
6034 temp_op
= i
.op
[xchg2
];
6035 i
.op
[xchg2
] = i
.op
[xchg1
];
6036 i
.op
[xchg1
] = temp_op
;
6038 temp_reloc
= i
.reloc
[xchg2
];
6039 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6040 i
.reloc
[xchg1
] = temp_reloc
;
6042 temp_flags
= i
.imm_bits
[xchg2
];
6043 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6044 i
.imm_bits
[xchg1
] = temp_flags
;
6048 if (i
.mask
.operand
== xchg1
)
6049 i
.mask
.operand
= xchg2
;
6050 else if (i
.mask
.operand
== xchg2
)
6051 i
.mask
.operand
= xchg1
;
6053 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6055 if (i
.broadcast
.operand
== xchg1
)
6056 i
.broadcast
.operand
= xchg2
;
6057 else if (i
.broadcast
.operand
== xchg2
)
6058 i
.broadcast
.operand
= xchg1
;
6063 swap_operands (void)
6069 swap_2_operands (1, i
.operands
- 2);
6073 swap_2_operands (0, i
.operands
- 1);
6079 if (i
.mem_operands
== 2)
6081 const reg_entry
*temp_seg
;
6082 temp_seg
= i
.seg
[0];
6083 i
.seg
[0] = i
.seg
[1];
6084 i
.seg
[1] = temp_seg
;
6088 /* Try to ensure constant immediates are represented in the smallest
6093 char guess_suffix
= 0;
6097 guess_suffix
= i
.suffix
;
6098 else if (i
.reg_operands
)
6100 /* Figure out a suffix from the last register operand specified.
6101 We can't do this properly yet, i.e. excluding special register
6102 instances, but the following works for instructions with
6103 immediates. In any case, we can't set i.suffix yet. */
6104 for (op
= i
.operands
; --op
>= 0;)
6105 if (i
.types
[op
].bitfield
.class != Reg
)
6107 else if (i
.types
[op
].bitfield
.byte
)
6109 guess_suffix
= BYTE_MNEM_SUFFIX
;
6112 else if (i
.types
[op
].bitfield
.word
)
6114 guess_suffix
= WORD_MNEM_SUFFIX
;
6117 else if (i
.types
[op
].bitfield
.dword
)
6119 guess_suffix
= LONG_MNEM_SUFFIX
;
6122 else if (i
.types
[op
].bitfield
.qword
)
6124 guess_suffix
= QWORD_MNEM_SUFFIX
;
6128 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6129 guess_suffix
= WORD_MNEM_SUFFIX
;
6130 else if (flag_code
!= CODE_64BIT
|| !(i
.prefix
[REX_PREFIX
] & REX_W
))
6131 guess_suffix
= LONG_MNEM_SUFFIX
;
6133 for (op
= i
.operands
; --op
>= 0;)
6134 if (operand_type_check (i
.types
[op
], imm
))
6136 switch (i
.op
[op
].imms
->X_op
)
6139 /* If a suffix is given, this operand may be shortened. */
6140 switch (guess_suffix
)
6142 case LONG_MNEM_SUFFIX
:
6143 i
.types
[op
].bitfield
.imm32
= 1;
6144 i
.types
[op
].bitfield
.imm64
= 1;
6146 case WORD_MNEM_SUFFIX
:
6147 i
.types
[op
].bitfield
.imm16
= 1;
6148 i
.types
[op
].bitfield
.imm32
= 1;
6149 i
.types
[op
].bitfield
.imm32s
= 1;
6150 i
.types
[op
].bitfield
.imm64
= 1;
6152 case BYTE_MNEM_SUFFIX
:
6153 i
.types
[op
].bitfield
.imm8
= 1;
6154 i
.types
[op
].bitfield
.imm8s
= 1;
6155 i
.types
[op
].bitfield
.imm16
= 1;
6156 i
.types
[op
].bitfield
.imm32
= 1;
6157 i
.types
[op
].bitfield
.imm32s
= 1;
6158 i
.types
[op
].bitfield
.imm64
= 1;
6162 /* If this operand is at most 16 bits, convert it
6163 to a signed 16 bit number before trying to see
6164 whether it will fit in an even smaller size.
6165 This allows a 16-bit operand such as $0xffe0 to
6166 be recognised as within Imm8S range. */
6167 if ((i
.types
[op
].bitfield
.imm16
)
6168 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6170 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6171 ^ 0x8000) - 0x8000);
6174 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6175 if ((i
.types
[op
].bitfield
.imm32
)
6176 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6178 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6179 ^ ((offsetT
) 1 << 31))
6180 - ((offsetT
) 1 << 31));
6184 = operand_type_or (i
.types
[op
],
6185 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6187 /* We must avoid matching of Imm32 templates when 64bit
6188 only immediate is available. */
6189 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6190 i
.types
[op
].bitfield
.imm32
= 0;
6197 /* Symbols and expressions. */
6199 /* Convert symbolic operand to proper sizes for matching, but don't
6200 prevent matching a set of insns that only supports sizes other
6201 than those matching the insn suffix. */
6203 i386_operand_type mask
, allowed
;
6204 const insn_template
*t
= current_templates
->start
;
6206 operand_type_set (&mask
, 0);
6207 switch (guess_suffix
)
6209 case QWORD_MNEM_SUFFIX
:
6210 mask
.bitfield
.imm64
= 1;
6211 mask
.bitfield
.imm32s
= 1;
6213 case LONG_MNEM_SUFFIX
:
6214 mask
.bitfield
.imm32
= 1;
6216 case WORD_MNEM_SUFFIX
:
6217 mask
.bitfield
.imm16
= 1;
6219 case BYTE_MNEM_SUFFIX
:
6220 mask
.bitfield
.imm8
= 1;
6226 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6227 while (++t
< current_templates
->end
)
6229 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6230 allowed
= operand_type_and (allowed
, mask
);
6233 if (!operand_type_all_zero (&allowed
))
6234 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6241 /* Try to use the smallest displacement type too. */
6243 optimize_disp (const insn_template
*t
)
6247 if (!want_disp32 (t
)
6248 && (!t
->opcode_modifier
.jump
6249 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6251 for (op
= 0; op
< i
.operands
; ++op
)
6253 const expressionS
*exp
= i
.op
[op
].disps
;
6255 if (!operand_type_check (i
.types
[op
], disp
))
6258 if (exp
->X_op
!= O_constant
)
6261 /* Since displacement is signed extended to 64bit, don't allow
6262 disp32 if it is out of range. */
6263 if (fits_in_signed_long (exp
->X_add_number
))
6266 i
.types
[op
].bitfield
.disp32
= 0;
6267 if (i
.types
[op
].bitfield
.baseindex
)
6269 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6270 (uint64_t) exp
->X_add_number
);
6276 /* Don't optimize displacement for movabs since it only takes 64bit
6278 if (i
.disp_encoding
> disp_encoding_8bit
6279 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6282 for (op
= i
.operands
; op
-- > 0;)
6283 if (operand_type_check (i
.types
[op
], disp
))
6285 if (i
.op
[op
].disps
->X_op
== O_constant
)
6287 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6289 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6291 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6292 i
.op
[op
].disps
= NULL
;
6297 if (i
.types
[op
].bitfield
.disp16
6298 && fits_in_unsigned_word (op_disp
))
6300 /* If this operand is at most 16 bits, convert
6301 to a signed 16 bit number and don't use 64bit
6303 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6304 i
.types
[op
].bitfield
.disp64
= 0;
6308 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6309 if ((flag_code
!= CODE_64BIT
6310 ? i
.types
[op
].bitfield
.disp32
6312 && (!t
->opcode_modifier
.jump
6313 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6314 && fits_in_unsigned_long (op_disp
))
6316 /* If this operand is at most 32 bits, convert
6317 to a signed 32 bit number and don't use 64bit
6319 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6320 i
.types
[op
].bitfield
.disp64
= 0;
6321 i
.types
[op
].bitfield
.disp32
= 1;
6324 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6326 i
.types
[op
].bitfield
.disp64
= 0;
6327 i
.types
[op
].bitfield
.disp32
= 1;
6330 if ((i
.types
[op
].bitfield
.disp32
6331 || i
.types
[op
].bitfield
.disp16
)
6332 && fits_in_disp8 (op_disp
))
6333 i
.types
[op
].bitfield
.disp8
= 1;
6335 i
.op
[op
].disps
->X_add_number
= op_disp
;
6337 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6338 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6340 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6341 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6342 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6345 /* We only support 64bit displacement on constants. */
6346 i
.types
[op
].bitfield
.disp64
= 0;
6352 /* Return 1 if there is a match in broadcast bytes between operand
6353 GIVEN and instruction template T. */
6356 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6358 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6359 && i
.types
[given
].bitfield
.byte
)
6360 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6361 && i
.types
[given
].bitfield
.word
)
6362 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6363 && i
.types
[given
].bitfield
.dword
)
6364 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6365 && i
.types
[given
].bitfield
.qword
));
6368 /* Check if operands are valid for the instruction. */
6371 check_VecOperands (const insn_template
*t
)
6376 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6377 any one operand are implicity requiring AVX512VL support if the actual
6378 operand size is YMMword or XMMword. Since this function runs after
6379 template matching, there's no need to check for YMMword/XMMword in
6381 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
6382 if (!cpu_flags_all_zero (&cpu
)
6383 && !t
->cpu_flags
.bitfield
.cpuavx512vl
6384 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6386 for (op
= 0; op
< t
->operands
; ++op
)
6388 if (t
->operand_types
[op
].bitfield
.zmmword
6389 && (i
.types
[op
].bitfield
.ymmword
6390 || i
.types
[op
].bitfield
.xmmword
))
6392 i
.error
= unsupported
;
6398 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6399 requiring AVX2 support if the actual operand size is YMMword. */
6400 if (t
->cpu_flags
.bitfield
.cpuavx
6401 && t
->cpu_flags
.bitfield
.cpuavx2
6402 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6404 for (op
= 0; op
< t
->operands
; ++op
)
6406 if (t
->operand_types
[op
].bitfield
.xmmword
6407 && i
.types
[op
].bitfield
.ymmword
)
6409 i
.error
= unsupported
;
6415 /* Without VSIB byte, we can't have a vector register for index. */
6416 if (!t
->opcode_modifier
.sib
6418 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6419 || i
.index_reg
->reg_type
.bitfield
.ymmword
6420 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6422 i
.error
= unsupported_vector_index_register
;
6426 /* Check if default mask is allowed. */
6427 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6428 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6430 i
.error
= no_default_mask
;
6434 /* For VSIB byte, we need a vector register for index, and all vector
6435 registers must be distinct. */
6436 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6439 || !((t
->opcode_modifier
.sib
== VECSIB128
6440 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6441 || (t
->opcode_modifier
.sib
== VECSIB256
6442 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6443 || (t
->opcode_modifier
.sib
== VECSIB512
6444 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6446 i
.error
= invalid_vsib_address
;
6450 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6451 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6453 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6454 gas_assert (i
.types
[0].bitfield
.xmmword
6455 || i
.types
[0].bitfield
.ymmword
);
6456 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6457 gas_assert (i
.types
[2].bitfield
.xmmword
6458 || i
.types
[2].bitfield
.ymmword
);
6459 if (operand_check
== check_none
)
6461 if (register_number (i
.op
[0].regs
)
6462 != register_number (i
.index_reg
)
6463 && register_number (i
.op
[2].regs
)
6464 != register_number (i
.index_reg
)
6465 && register_number (i
.op
[0].regs
)
6466 != register_number (i
.op
[2].regs
))
6468 if (operand_check
== check_error
)
6470 i
.error
= invalid_vector_register_set
;
6473 as_warn (_("mask, index, and destination registers should be distinct"));
6475 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6477 if (i
.types
[1].bitfield
.class == RegSIMD
6478 && (i
.types
[1].bitfield
.xmmword
6479 || i
.types
[1].bitfield
.ymmword
6480 || i
.types
[1].bitfield
.zmmword
)
6481 && (register_number (i
.op
[1].regs
)
6482 == register_number (i
.index_reg
)))
6484 if (operand_check
== check_error
)
6486 i
.error
= invalid_vector_register_set
;
6489 if (operand_check
!= check_none
)
6490 as_warn (_("index and destination registers should be distinct"));
6495 /* For AMX instructions with 3 TMM register operands, all operands
6496 must be distinct. */
6497 if (i
.reg_operands
== 3
6498 && t
->operand_types
[0].bitfield
.tmmword
6499 && (i
.op
[0].regs
== i
.op
[1].regs
6500 || i
.op
[0].regs
== i
.op
[2].regs
6501 || i
.op
[1].regs
== i
.op
[2].regs
))
6503 i
.error
= invalid_tmm_register_set
;
6507 /* For some special instructions require that destination must be distinct
6508 from source registers. */
6509 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6511 unsigned int dest_reg
= i
.operands
- 1;
6513 know (i
.operands
>= 3);
6515 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6516 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6517 || (i
.reg_operands
> 2
6518 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6520 i
.error
= invalid_dest_and_src_register_set
;
6525 /* Check if broadcast is supported by the instruction and is applied
6526 to the memory operand. */
6527 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6529 i386_operand_type type
, overlap
;
6531 /* Check if specified broadcast is supported in this instruction,
6532 and its broadcast bytes match the memory operand. */
6533 op
= i
.broadcast
.operand
;
6534 if (!t
->opcode_modifier
.broadcast
6535 || !(i
.flags
[op
] & Operand_Mem
)
6536 || (!i
.types
[op
].bitfield
.unspecified
6537 && !match_broadcast_size (t
, op
)))
6540 i
.error
= unsupported_broadcast
;
6544 operand_type_set (&type
, 0);
6545 switch (get_broadcast_bytes (t
, false))
6548 type
.bitfield
.word
= 1;
6551 type
.bitfield
.dword
= 1;
6554 type
.bitfield
.qword
= 1;
6557 type
.bitfield
.xmmword
= 1;
6560 type
.bitfield
.ymmword
= 1;
6563 type
.bitfield
.zmmword
= 1;
6569 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6570 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6571 && t
->operand_types
[op
].bitfield
.byte
6572 + t
->operand_types
[op
].bitfield
.word
6573 + t
->operand_types
[op
].bitfield
.dword
6574 + t
->operand_types
[op
].bitfield
.qword
> 1)
6576 overlap
.bitfield
.xmmword
= 0;
6577 overlap
.bitfield
.ymmword
= 0;
6578 overlap
.bitfield
.zmmword
= 0;
6580 if (operand_type_all_zero (&overlap
))
6583 if (t
->opcode_modifier
.checkoperandsize
)
6587 type
.bitfield
.baseindex
= 1;
6588 for (j
= 0; j
< i
.operands
; ++j
)
6591 && !operand_type_register_match(i
.types
[j
],
6592 t
->operand_types
[j
],
6594 t
->operand_types
[op
]))
6599 /* If broadcast is supported in this instruction, we need to check if
6600 operand of one-element size isn't specified without broadcast. */
6601 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6603 /* Find memory operand. */
6604 for (op
= 0; op
< i
.operands
; op
++)
6605 if (i
.flags
[op
] & Operand_Mem
)
6607 gas_assert (op
< i
.operands
);
6608 /* Check size of the memory operand. */
6609 if (match_broadcast_size (t
, op
))
6611 i
.error
= broadcast_needed
;
6616 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6618 /* Check if requested masking is supported. */
6621 if (!t
->opcode_modifier
.masking
)
6623 i
.error
= unsupported_masking
;
6627 /* Common rules for masking:
6628 - mask register destinations permit only zeroing-masking, without
6629 that actually being expressed by a {z} operand suffix or EVEX.z,
6630 - memory destinations allow only merging-masking,
6631 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6634 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6635 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6636 || t
->opcode_modifier
.sib
))
6638 i
.error
= unsupported_masking
;
6643 /* Check if masking is applied to dest operand. */
6644 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6646 i
.error
= mask_not_on_destination
;
6651 if (i
.rounding
.type
!= rc_none
)
6653 if (!t
->opcode_modifier
.sae
6654 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6657 i
.error
= unsupported_rc_sae
;
6661 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6663 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6665 for (op
= 0; op
< t
->operands
; ++op
)
6666 if (i
.types
[op
].bitfield
.zmmword
)
6668 if (op
>= t
->operands
)
6670 i
.error
= operand_size_mismatch
;
6676 /* Check the special Imm4 cases; must be the first operand. */
6677 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6679 if (i
.op
[0].imms
->X_op
!= O_constant
6680 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6686 /* Turn off Imm<N> so that update_imm won't complain. */
6687 operand_type_set (&i
.types
[0], 0);
6690 /* Check vector Disp8 operand. */
6691 if (t
->opcode_modifier
.disp8memshift
6692 && i
.disp_encoding
<= disp_encoding_8bit
)
6694 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6695 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6696 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6697 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6700 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6703 for (op
= 0; op
< i
.operands
; op
++)
6704 if (i
.flags
[op
] & Operand_Mem
)
6706 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6707 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6708 else if (t
->operand_types
[op
].bitfield
.xmmword
6709 + t
->operand_types
[op
].bitfield
.ymmword
6710 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6711 type
= &t
->operand_types
[op
];
6712 else if (!i
.types
[op
].bitfield
.unspecified
)
6713 type
= &i
.types
[op
];
6714 else /* Ambiguities get resolved elsewhere. */
6715 fallback
= &t
->operand_types
[op
];
6717 else if (i
.types
[op
].bitfield
.class == RegSIMD
6718 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6720 if (i
.types
[op
].bitfield
.zmmword
)
6722 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6724 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6728 if (!type
&& !i
.memshift
)
6732 if (type
->bitfield
.zmmword
)
6734 else if (type
->bitfield
.ymmword
)
6736 else if (type
->bitfield
.xmmword
)
6740 /* For the check in fits_in_disp8(). */
6741 if (i
.memshift
== 0)
6745 for (op
= 0; op
< i
.operands
; op
++)
6746 if (operand_type_check (i
.types
[op
], disp
)
6747 && i
.op
[op
].disps
->X_op
== O_constant
)
6749 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6751 i
.types
[op
].bitfield
.disp8
= 1;
6754 i
.types
[op
].bitfield
.disp8
= 0;
6763 /* Check if encoding requirements are met by the instruction. */
6766 VEX_check_encoding (const insn_template
*t
)
6768 if (i
.vec_encoding
== vex_encoding_error
)
6770 i
.error
= unsupported
;
6774 if (i
.vec_encoding
== vex_encoding_evex
)
6776 /* This instruction must be encoded with EVEX prefix. */
6777 if (!is_evex_encoding (t
))
6779 i
.error
= unsupported
;
6785 if (!t
->opcode_modifier
.vex
)
6787 /* This instruction template doesn't have VEX prefix. */
6788 if (i
.vec_encoding
!= vex_encoding_default
)
6790 i
.error
= unsupported
;
6799 /* Helper function for the progress() macro in match_template(). */
6800 static INLINE
enum i386_error
progress (enum i386_error
new,
6801 enum i386_error last
,
6802 unsigned int line
, unsigned int *line_p
)
6804 if (line
<= *line_p
)
6810 static const insn_template
*
6811 match_template (char mnem_suffix
)
6813 /* Points to template once we've found it. */
6814 const insn_template
*t
;
6815 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6816 i386_operand_type overlap4
;
6817 unsigned int found_reverse_match
;
6818 i386_operand_type operand_types
[MAX_OPERANDS
];
6819 int addr_prefix_disp
;
6820 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6821 enum i386_error specific_error
= number_of_operands_mismatch
;
6822 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6824 #if MAX_OPERANDS != 5
6825 # error "MAX_OPERANDS must be 5."
6828 found_reverse_match
= 0;
6829 addr_prefix_disp
= -1;
6831 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6833 addr_prefix_disp
= -1;
6834 found_reverse_match
= 0;
6836 /* Must have right number of operands. */
6837 if (i
.operands
!= t
->operands
)
6840 /* Check processor support. */
6841 specific_error
= progress (unsupported
);
6842 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6845 /* Check AT&T mnemonic. */
6846 specific_error
= progress (unsupported_with_intel_mnemonic
);
6847 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6850 /* Check AT&T/Intel syntax. */
6851 specific_error
= progress (unsupported_syntax
);
6852 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6853 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6856 /* Check Intel64/AMD64 ISA. */
6860 /* Default: Don't accept Intel64. */
6861 if (t
->opcode_modifier
.isa64
== INTEL64
)
6865 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6866 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6870 /* -mintel64: Don't accept AMD64. */
6871 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6876 /* Check the suffix. */
6877 specific_error
= progress (invalid_instruction_suffix
);
6878 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6879 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6880 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6881 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6882 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6885 specific_error
= progress (operand_size_mismatch
);
6886 size_match
= operand_size_match (t
);
6890 /* This is intentionally not
6892 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6894 as the case of a missing * on the operand is accepted (perhaps with
6895 a warning, issued further down). */
6896 specific_error
= progress (operand_type_mismatch
);
6897 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6900 /* In Intel syntax, normally we can check for memory operand size when
6901 there is no mnemonic suffix. But jmp and call have 2 different
6902 encodings with Dword memory operand size. Skip the "near" one
6903 (permitting a register operand) when "far" was requested. */
6905 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
6906 && t
->operand_types
[0].bitfield
.class == Reg
)
6909 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6910 operand_types
[j
] = t
->operand_types
[j
];
6912 /* In general, don't allow 32-bit operands on pre-386. */
6913 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
6914 : operand_size_mismatch
);
6915 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6916 if (i
.suffix
== LONG_MNEM_SUFFIX
6917 && !cpu_arch_flags
.bitfield
.cpui386
6919 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6920 && !intel_float_operand (insn_name (t
)))
6921 : intel_float_operand (insn_name (t
)) != 2)
6922 && (t
->operands
== i
.imm_operands
6923 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6924 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6925 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6926 || (operand_types
[j
].bitfield
.class != RegMMX
6927 && operand_types
[j
].bitfield
.class != RegSIMD
6928 && operand_types
[j
].bitfield
.class != RegMask
))
6929 && !t
->opcode_modifier
.sib
)
6932 /* Do not verify operands when there are none. */
6935 if (VEX_check_encoding (t
))
6937 specific_error
= progress (i
.error
);
6941 /* We've found a match; break out of loop. */
6945 if (!t
->opcode_modifier
.jump
6946 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6948 /* There should be only one Disp operand. */
6949 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6950 if (operand_type_check (operand_types
[j
], disp
))
6952 if (j
< MAX_OPERANDS
)
6954 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6956 addr_prefix_disp
= j
;
6958 /* Address size prefix will turn Disp64 operand into Disp32 and
6959 Disp32/Disp16 one into Disp16/Disp32 respectively. */
6963 override
= !override
;
6966 if (operand_types
[j
].bitfield
.disp32
6967 && operand_types
[j
].bitfield
.disp16
)
6969 operand_types
[j
].bitfield
.disp16
= override
;
6970 operand_types
[j
].bitfield
.disp32
= !override
;
6972 gas_assert (!operand_types
[j
].bitfield
.disp64
);
6976 if (operand_types
[j
].bitfield
.disp64
)
6978 gas_assert (!operand_types
[j
].bitfield
.disp32
);
6979 operand_types
[j
].bitfield
.disp32
= override
;
6980 operand_types
[j
].bitfield
.disp64
= !override
;
6982 operand_types
[j
].bitfield
.disp16
= 0;
6988 /* We check register size if needed. */
6989 if (t
->opcode_modifier
.checkoperandsize
)
6991 check_register
= (1 << t
->operands
) - 1;
6992 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6993 check_register
&= ~(1 << i
.broadcast
.operand
);
6998 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6999 switch (t
->operands
)
7002 if (!operand_type_match (overlap0
, i
.types
[0]))
7005 /* Allow the ModR/M encoding to be requested by using the {load} or
7006 {store} pseudo prefix on an applicable insn. */
7007 if (!t
->opcode_modifier
.modrm
7008 && i
.reg_operands
== 1
7009 && ((i
.dir_encoding
== dir_encoding_load
7010 && t
->mnem_off
!= MN_pop
)
7011 || (i
.dir_encoding
== dir_encoding_store
7012 && t
->mnem_off
!= MN_push
))
7014 && t
->mnem_off
!= MN_bswap
)
7019 /* xchg %eax, %eax is a special case. It is an alias for nop
7020 only in 32bit mode and we can use opcode 0x90. In 64bit
7021 mode, we can't use 0x90 for xchg %eax, %eax since it should
7022 zero-extend %eax to %rax. */
7023 if (t
->base_opcode
== 0x90
7024 && t
->opcode_space
== SPACE_BASE
)
7026 if (flag_code
== CODE_64BIT
7027 && i
.types
[0].bitfield
.instance
== Accum
7028 && i
.types
[0].bitfield
.dword
7029 && i
.types
[1].bitfield
.instance
== Accum
)
7032 /* Allow the ModR/M encoding to be requested by using the
7033 {load} or {store} pseudo prefix. */
7034 if (i
.dir_encoding
== dir_encoding_load
7035 || i
.dir_encoding
== dir_encoding_store
)
7039 if (t
->base_opcode
== MOV_AX_DISP32
7040 && t
->opcode_space
== SPACE_BASE
7041 && t
->mnem_off
!= MN_movabs
)
7043 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7044 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7047 /* xrelease mov %eax, <disp> is another special case. It must not
7048 match the accumulator-only encoding of mov. */
7052 /* Allow the ModR/M encoding to be requested by using a suitable
7053 {load} or {store} pseudo prefix. */
7054 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7055 ? dir_encoding_store
7056 : dir_encoding_load
)
7057 && !i
.types
[0].bitfield
.disp64
7058 && !i
.types
[1].bitfield
.disp64
)
7062 /* Allow the ModR/M encoding to be requested by using the {load} or
7063 {store} pseudo prefix on an applicable insn. */
7064 if (!t
->opcode_modifier
.modrm
7065 && i
.reg_operands
== 1
7066 && i
.imm_operands
== 1
7067 && (i
.dir_encoding
== dir_encoding_load
7068 || i
.dir_encoding
== dir_encoding_store
)
7069 && t
->opcode_space
== SPACE_BASE
)
7071 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7072 && i
.dir_encoding
== dir_encoding_store
)
7075 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7076 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7077 || i
.dir_encoding
== dir_encoding_load
))
7080 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7081 && i
.dir_encoding
== dir_encoding_load
)
7087 if (!(size_match
& MATCH_STRAIGHT
))
7089 /* Reverse direction of operands if swapping is possible in the first
7090 place (operands need to be symmetric) and
7091 - the load form is requested, and the template is a store form,
7092 - the store form is requested, and the template is a load form,
7093 - the non-default (swapped) form is requested. */
7094 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7095 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7096 && !operand_type_all_zero (&overlap1
))
7097 switch (i
.dir_encoding
)
7099 case dir_encoding_load
:
7100 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7101 || t
->opcode_modifier
.regmem
)
7105 case dir_encoding_store
:
7106 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7107 && !t
->opcode_modifier
.regmem
)
7111 case dir_encoding_swap
:
7114 case dir_encoding_default
:
7117 /* If we want store form, we skip the current load. */
7118 if ((i
.dir_encoding
== dir_encoding_store
7119 || i
.dir_encoding
== dir_encoding_swap
)
7120 && i
.mem_operands
== 0
7121 && t
->opcode_modifier
.load
)
7126 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7127 if (!operand_type_match (overlap0
, i
.types
[0])
7128 || !operand_type_match (overlap1
, i
.types
[1])
7129 || ((check_register
& 3) == 3
7130 && !operand_type_register_match (i
.types
[0],
7135 specific_error
= progress (i
.error
);
7137 /* Check if other direction is valid ... */
7138 if (!t
->opcode_modifier
.d
)
7142 if (!(size_match
& MATCH_REVERSE
))
7144 /* Try reversing direction of operands. */
7145 j
= t
->cpu_flags
.bitfield
.cpufma4
7146 || t
->cpu_flags
.bitfield
.cpuxop
? 1 : i
.operands
- 1;
7147 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7148 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7149 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7150 gas_assert (t
->operands
!= 3 || !check_register
);
7151 if (!operand_type_match (overlap0
, i
.types
[0])
7152 || !operand_type_match (overlap1
, i
.types
[j
])
7153 || (t
->operands
== 3
7154 && !operand_type_match (overlap2
, i
.types
[1]))
7156 && !operand_type_register_match (i
.types
[0],
7161 /* Does not match either direction. */
7162 specific_error
= progress (i
.error
);
7165 /* found_reverse_match holds which variant of D
7167 if (!t
->opcode_modifier
.d
)
7168 found_reverse_match
= 0;
7169 else if (operand_types
[0].bitfield
.tbyte
)
7171 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7172 found_reverse_match
= Opcode_FloatD
;
7174 found_reverse_match
= ~0;
7175 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7176 if ((t
->extension_opcode
& 4)
7177 && (intel_syntax
|| intel_mnemonic
))
7178 found_reverse_match
|= Opcode_FloatR
;
7180 else if (t
->cpu_flags
.bitfield
.cpufma4
7181 || t
->cpu_flags
.bitfield
.cpuxop
)
7183 found_reverse_match
= Opcode_VexW
;
7184 goto check_operands_345
;
7186 else if (t
->opcode_space
!= SPACE_BASE
7187 && (t
->opcode_space
!= SPACE_0F
7188 /* MOV to/from CR/DR/TR, as an exception, follow
7189 the base opcode space encoding model. */
7190 || (t
->base_opcode
| 7) != 0x27))
7191 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7192 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7193 else if (!t
->opcode_modifier
.commutative
)
7194 found_reverse_match
= Opcode_D
;
7196 found_reverse_match
= ~0;
7200 /* Found a forward 2 operand match here. */
7202 switch (t
->operands
)
7205 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7206 if (!operand_type_match (overlap4
, i
.types
[4])
7207 || !operand_type_register_match (i
.types
[3],
7212 specific_error
= progress (i
.error
);
7217 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7218 if (!operand_type_match (overlap3
, i
.types
[3])
7219 || ((check_register
& 0xa) == 0xa
7220 && !operand_type_register_match (i
.types
[1],
7224 || ((check_register
& 0xc) == 0xc
7225 && !operand_type_register_match (i
.types
[2],
7230 specific_error
= progress (i
.error
);
7235 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7236 if (!operand_type_match (overlap2
, i
.types
[2])
7237 || ((check_register
& 5) == 5
7238 && !operand_type_register_match (i
.types
[0],
7242 || ((check_register
& 6) == 6
7243 && !operand_type_register_match (i
.types
[1],
7248 specific_error
= progress (i
.error
);
7254 /* Found either forward/reverse 2, 3 or 4 operand match here:
7255 slip through to break. */
7258 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7259 if (VEX_check_encoding (t
))
7261 specific_error
= progress (i
.error
);
7265 /* Check if vector operands are valid. */
7266 if (check_VecOperands (t
))
7268 specific_error
= progress (i
.error
);
7272 /* We've found a match; break out of loop. */
7278 if (t
== current_templates
->end
)
7280 /* We found no match. */
7281 i
.error
= specific_error
;
7285 if (!quiet_warnings
)
7288 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7289 as_warn (_("indirect %s without `*'"), insn_name (t
));
7291 if (t
->opcode_modifier
.isprefix
7292 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7294 /* Warn them that a data or address size prefix doesn't
7295 affect assembly of the next line of code. */
7296 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7300 /* Copy the template we found. */
7301 install_template (t
);
7303 if (addr_prefix_disp
!= -1)
7304 i
.tm
.operand_types
[addr_prefix_disp
]
7305 = operand_types
[addr_prefix_disp
];
7307 switch (found_reverse_match
)
7313 case Opcode_FloatR
| Opcode_FloatD
:
7314 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7315 found_reverse_match
&= Opcode_FloatD
;
7319 /* If we found a reverse match we must alter the opcode direction
7320 bit and clear/flip the regmem modifier one. found_reverse_match
7321 holds bits to change (different for int & float insns). */
7323 i
.tm
.base_opcode
^= found_reverse_match
;
7325 /* Certain SIMD insns have their load forms specified in the opcode
7326 table, and hence we need to _set_ RegMem instead of clearing it.
7327 We need to avoid setting the bit though on insns like KMOVW. */
7328 i
.tm
.opcode_modifier
.regmem
7329 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7330 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7331 && !i
.tm
.opcode_modifier
.regmem
;
7335 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7336 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7340 /* Only the first two register operands need reversing, alongside
7342 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7344 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7345 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7346 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7356 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7357 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7359 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7361 as_bad (_("`%s' operand %u must use `%ses' segment"),
7363 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7368 /* There's only ever one segment override allowed per instruction.
7369 This instruction possibly has a legal segment override on the
7370 second operand, so copy the segment to where non-string
7371 instructions store it, allowing common code. */
7372 i
.seg
[op
] = i
.seg
[1];
7378 process_suffix (void)
7380 bool is_movx
= false;
7382 /* If matched instruction specifies an explicit instruction mnemonic
7384 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7385 i
.suffix
= WORD_MNEM_SUFFIX
;
7386 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7387 i
.suffix
= LONG_MNEM_SUFFIX
;
7388 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7389 i
.suffix
= QWORD_MNEM_SUFFIX
;
7390 else if (i
.reg_operands
7391 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7392 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7394 unsigned int numop
= i
.operands
;
7397 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7398 && (i
.tm
.base_opcode
| 8) == 0xbe)
7399 || (i
.tm
.opcode_space
== SPACE_BASE
7400 && i
.tm
.base_opcode
== 0x63
7401 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
7403 /* movsx/movzx want only their source operand considered here, for the
7404 ambiguity checking below. The suffix will be replaced afterwards
7405 to represent the destination (register). */
7406 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7409 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7410 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7413 /* If there's no instruction mnemonic suffix we try to invent one
7414 based on GPR operands. */
7417 /* We take i.suffix from the last register operand specified,
7418 Destination register type is more significant than source
7419 register type. crc32 in SSE4.2 prefers source register
7421 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7424 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7425 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7427 if (i
.types
[op
].bitfield
.class != Reg
)
7429 if (i
.types
[op
].bitfield
.byte
)
7430 i
.suffix
= BYTE_MNEM_SUFFIX
;
7431 else if (i
.types
[op
].bitfield
.word
)
7432 i
.suffix
= WORD_MNEM_SUFFIX
;
7433 else if (i
.types
[op
].bitfield
.dword
)
7434 i
.suffix
= LONG_MNEM_SUFFIX
;
7435 else if (i
.types
[op
].bitfield
.qword
)
7436 i
.suffix
= QWORD_MNEM_SUFFIX
;
7442 /* As an exception, movsx/movzx silently default to a byte source
7444 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7445 i
.suffix
= BYTE_MNEM_SUFFIX
;
7447 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7449 if (!check_byte_reg ())
7452 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7454 if (!check_long_reg ())
7457 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7459 if (!check_qword_reg ())
7462 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7464 if (!check_word_reg ())
7467 else if (intel_syntax
7468 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7469 /* Do nothing if the instruction is going to ignore the prefix. */
7474 /* Undo the movsx/movzx change done above. */
7477 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7480 i
.suffix
= stackop_size
;
7481 if (stackop_size
== LONG_MNEM_SUFFIX
)
7483 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7484 .code16gcc directive to support 16-bit mode with
7485 32-bit address. For IRET without a suffix, generate
7486 16-bit IRET (opcode 0xcf) to return from an interrupt
7488 if (i
.tm
.base_opcode
== 0xcf)
7490 i
.suffix
= WORD_MNEM_SUFFIX
;
7491 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7493 /* Warn about changed behavior for segment register push/pop. */
7494 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7495 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7500 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7501 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7502 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7503 || (i
.tm
.opcode_space
== SPACE_0F
7504 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7505 && i
.tm
.extension_opcode
<= 3)))
7510 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7512 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7513 || i
.tm
.opcode_modifier
.no_lsuf
)
7514 i
.suffix
= QWORD_MNEM_SUFFIX
;
7519 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7520 i
.suffix
= LONG_MNEM_SUFFIX
;
7523 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7524 i
.suffix
= WORD_MNEM_SUFFIX
;
7530 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7531 /* Also cover lret/retf/iret in 64-bit mode. */
7532 || (flag_code
== CODE_64BIT
7533 && !i
.tm
.opcode_modifier
.no_lsuf
7534 && !i
.tm
.opcode_modifier
.no_qsuf
))
7535 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7536 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7537 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7538 /* Accept FLDENV et al without suffix. */
7539 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7541 unsigned int suffixes
, evex
= 0;
7543 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7544 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7546 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7548 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7550 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7553 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7554 also suitable for AT&T syntax mode, it was requested that this be
7555 restricted to just Intel syntax. */
7556 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7557 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7561 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7563 if (is_evex_encoding (&i
.tm
)
7564 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7566 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7567 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7568 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7569 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7570 if (!i
.tm
.opcode_modifier
.evex
7571 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7572 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7575 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7576 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7577 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7580 /* Any properly sized operand disambiguates the insn. */
7581 if (i
.types
[op
].bitfield
.xmmword
7582 || i
.types
[op
].bitfield
.ymmword
7583 || i
.types
[op
].bitfield
.zmmword
)
7585 suffixes
&= ~(7 << 6);
7590 if ((i
.flags
[op
] & Operand_Mem
)
7591 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7593 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7595 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7597 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7599 if (is_evex_encoding (&i
.tm
))
7605 /* Are multiple suffixes / operand sizes allowed? */
7606 if (suffixes
& (suffixes
- 1))
7609 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7610 || operand_check
== check_error
))
7612 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7615 if (operand_check
== check_error
)
7617 as_bad (_("no instruction mnemonic suffix given and "
7618 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7621 if (operand_check
== check_warning
)
7622 as_warn (_("%s; using default for `%s'"),
7624 ? _("ambiguous operand size")
7625 : _("no instruction mnemonic suffix given and "
7626 "no register operands"),
7629 if (i
.tm
.opcode_modifier
.floatmf
)
7630 i
.suffix
= SHORT_MNEM_SUFFIX
;
7632 /* handled below */;
7634 i
.tm
.opcode_modifier
.evex
= evex
;
7635 else if (flag_code
== CODE_16BIT
)
7636 i
.suffix
= WORD_MNEM_SUFFIX
;
7637 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7638 i
.suffix
= LONG_MNEM_SUFFIX
;
7640 i
.suffix
= QWORD_MNEM_SUFFIX
;
7646 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7647 In AT&T syntax, if there is no suffix (warned about above), the default
7648 will be byte extension. */
7649 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7650 i
.tm
.base_opcode
|= 1;
7652 /* For further processing, the suffix should represent the destination
7653 (register). This is already the case when one was used with
7654 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7655 no suffix to begin with. */
7656 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7658 if (i
.types
[1].bitfield
.word
)
7659 i
.suffix
= WORD_MNEM_SUFFIX
;
7660 else if (i
.types
[1].bitfield
.qword
)
7661 i
.suffix
= QWORD_MNEM_SUFFIX
;
7663 i
.suffix
= LONG_MNEM_SUFFIX
;
7665 i
.tm
.opcode_modifier
.w
= 0;
7669 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7670 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7671 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7673 /* Change the opcode based on the operand size given by i.suffix. */
7676 /* Size floating point instruction. */
7677 case LONG_MNEM_SUFFIX
:
7678 if (i
.tm
.opcode_modifier
.floatmf
)
7680 i
.tm
.base_opcode
^= 4;
7684 case WORD_MNEM_SUFFIX
:
7685 case QWORD_MNEM_SUFFIX
:
7686 /* It's not a byte, select word/dword operation. */
7687 if (i
.tm
.opcode_modifier
.w
)
7690 i
.tm
.base_opcode
|= 8;
7692 i
.tm
.base_opcode
|= 1;
7695 case SHORT_MNEM_SUFFIX
:
7696 /* Now select between word & dword operations via the operand
7697 size prefix, except for instructions that will ignore this
7699 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7700 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7701 && !i
.tm
.opcode_modifier
.floatmf
7702 && !is_any_vex_encoding (&i
.tm
)
7703 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7704 || (flag_code
== CODE_64BIT
7705 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7707 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7709 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7710 prefix
= ADDR_PREFIX_OPCODE
;
7712 if (!add_prefix (prefix
))
7716 /* Set mode64 for an operand. */
7717 if (i
.suffix
== QWORD_MNEM_SUFFIX
7718 && flag_code
== CODE_64BIT
7719 && !i
.tm
.opcode_modifier
.norex64
7720 && !i
.tm
.opcode_modifier
.vexw
7721 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7723 && ! (i
.operands
== 2
7724 && i
.tm
.base_opcode
== 0x90
7725 && i
.tm
.opcode_space
== SPACE_BASE
7726 && i
.types
[0].bitfield
.instance
== Accum
7727 && i
.types
[0].bitfield
.qword
7728 && i
.types
[1].bitfield
.instance
== Accum
))
7734 /* Select word/dword/qword operation with explicit data sizing prefix
7735 when there are no suitable register operands. */
7736 if (i
.tm
.opcode_modifier
.w
7737 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7739 || (i
.reg_operands
== 1
7741 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7743 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7744 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7745 || i
.tm
.mnem_off
== MN_crc32
))))
7746 i
.tm
.base_opcode
|= 1;
7750 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7752 gas_assert (!i
.suffix
);
7753 gas_assert (i
.reg_operands
);
7755 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7758 /* The address size override prefix changes the size of the
7760 if (flag_code
== CODE_64BIT
7761 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7763 as_bad (_("16-bit addressing unavailable for `%s'"),
7768 if ((flag_code
== CODE_32BIT
7769 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7770 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7771 && !add_prefix (ADDR_PREFIX_OPCODE
))
7776 /* Check invalid register operand when the address size override
7777 prefix changes the size of register operands. */
7779 enum { need_word
, need_dword
, need_qword
} need
;
7781 /* Check the register operand for the address size prefix if
7782 the memory operand has no real registers, like symbol, DISP
7783 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7784 if (i
.mem_operands
== 1
7785 && i
.reg_operands
== 1
7787 && i
.types
[1].bitfield
.class == Reg
7788 && (flag_code
== CODE_32BIT
7789 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7790 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7791 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7792 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7793 || (x86_elf_abi
== X86_64_X32_ABI
7795 && i
.base_reg
->reg_num
== RegIP
7796 && i
.base_reg
->reg_type
.bitfield
.qword
))
7800 && !add_prefix (ADDR_PREFIX_OPCODE
))
7803 if (flag_code
== CODE_32BIT
)
7804 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7805 else if (i
.prefix
[ADDR_PREFIX
])
7808 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7810 for (op
= 0; op
< i
.operands
; op
++)
7812 if (i
.types
[op
].bitfield
.class != Reg
)
7818 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7822 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7826 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7831 as_bad (_("invalid register operand size for `%s'"),
7842 check_byte_reg (void)
7846 for (op
= i
.operands
; --op
>= 0;)
7848 /* Skip non-register operands. */
7849 if (i
.types
[op
].bitfield
.class != Reg
)
7852 /* If this is an eight bit register, it's OK. If it's the 16 or
7853 32 bit version of an eight bit register, we will just use the
7854 low portion, and that's OK too. */
7855 if (i
.types
[op
].bitfield
.byte
)
7858 /* I/O port address operands are OK too. */
7859 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7860 && i
.tm
.operand_types
[op
].bitfield
.word
)
7863 /* crc32 only wants its source operand checked here. */
7864 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
7867 /* Any other register is bad. */
7868 as_bad (_("`%s%s' not allowed with `%s%c'"),
7869 register_prefix
, i
.op
[op
].regs
->reg_name
,
7870 insn_name (&i
.tm
), i
.suffix
);
7877 check_long_reg (void)
7881 for (op
= i
.operands
; --op
>= 0;)
7882 /* Skip non-register operands. */
7883 if (i
.types
[op
].bitfield
.class != Reg
)
7885 /* Reject eight bit registers, except where the template requires
7886 them. (eg. movzb) */
7887 else if (i
.types
[op
].bitfield
.byte
7888 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7889 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7890 && (i
.tm
.operand_types
[op
].bitfield
.word
7891 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7893 as_bad (_("`%s%s' not allowed with `%s%c'"),
7895 i
.op
[op
].regs
->reg_name
,
7900 /* Error if the e prefix on a general reg is missing. */
7901 else if (i
.types
[op
].bitfield
.word
7902 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7903 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7904 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7906 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7907 register_prefix
, i
.op
[op
].regs
->reg_name
,
7911 /* Warn if the r prefix on a general reg is present. */
7912 else if (i
.types
[op
].bitfield
.qword
7913 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7914 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7915 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7917 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7918 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7925 check_qword_reg (void)
7929 for (op
= i
.operands
; --op
>= 0; )
7930 /* Skip non-register operands. */
7931 if (i
.types
[op
].bitfield
.class != Reg
)
7933 /* Reject eight bit registers, except where the template requires
7934 them. (eg. movzb) */
7935 else if (i
.types
[op
].bitfield
.byte
7936 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7937 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7938 && (i
.tm
.operand_types
[op
].bitfield
.word
7939 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7941 as_bad (_("`%s%s' not allowed with `%s%c'"),
7943 i
.op
[op
].regs
->reg_name
,
7948 /* Warn if the r prefix on a general reg is missing. */
7949 else if ((i
.types
[op
].bitfield
.word
7950 || i
.types
[op
].bitfield
.dword
)
7951 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7952 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7953 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7955 /* Prohibit these changes in the 64bit mode, since the
7956 lowering is more complicated. */
7957 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7958 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7965 check_word_reg (void)
7968 for (op
= i
.operands
; --op
>= 0;)
7969 /* Skip non-register operands. */
7970 if (i
.types
[op
].bitfield
.class != Reg
)
7972 /* Reject eight bit registers, except where the template requires
7973 them. (eg. movzb) */
7974 else if (i
.types
[op
].bitfield
.byte
7975 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7976 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7977 && (i
.tm
.operand_types
[op
].bitfield
.word
7978 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7980 as_bad (_("`%s%s' not allowed with `%s%c'"),
7982 i
.op
[op
].regs
->reg_name
,
7987 /* Error if the e or r prefix on a general reg is present. */
7988 else if ((i
.types
[op
].bitfield
.dword
7989 || i
.types
[op
].bitfield
.qword
)
7990 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7991 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7992 && i
.tm
.operand_types
[op
].bitfield
.word
)
7994 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7995 register_prefix
, i
.op
[op
].regs
->reg_name
,
8003 update_imm (unsigned int j
)
8005 i386_operand_type overlap
= i
.types
[j
];
8007 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8008 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8009 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8011 /* This combination is used on 8-bit immediates where e.g. $~0 is
8012 desirable to permit. We're past operand type matching, so simply
8013 put things back in the shape they were before introducing the
8014 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8015 overlap
.bitfield
.imm8s
= 0;
8018 if (overlap
.bitfield
.imm8
8019 + overlap
.bitfield
.imm8s
8020 + overlap
.bitfield
.imm16
8021 + overlap
.bitfield
.imm32
8022 + overlap
.bitfield
.imm32s
8023 + overlap
.bitfield
.imm64
> 1)
8025 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8026 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8027 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8028 static const i386_operand_type imm16_32
= { .bitfield
=
8029 { .imm16
= 1, .imm32
= 1 }
8031 static const i386_operand_type imm16_32s
= { .bitfield
=
8032 { .imm16
= 1, .imm32s
= 1 }
8034 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8035 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8040 i386_operand_type temp
;
8042 operand_type_set (&temp
, 0);
8043 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8045 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8046 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8048 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8049 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8050 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8052 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8053 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8056 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8059 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8060 || operand_type_equal (&overlap
, &imm16_32
)
8061 || operand_type_equal (&overlap
, &imm16_32s
))
8063 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
8068 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8069 overlap
= operand_type_and (overlap
, imm32s
);
8070 else if (i
.prefix
[DATA_PREFIX
])
8071 overlap
= operand_type_and (overlap
,
8072 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8073 if (overlap
.bitfield
.imm8
8074 + overlap
.bitfield
.imm8s
8075 + overlap
.bitfield
.imm16
8076 + overlap
.bitfield
.imm32
8077 + overlap
.bitfield
.imm32s
8078 + overlap
.bitfield
.imm64
!= 1)
8080 as_bad (_("no instruction mnemonic suffix given; "
8081 "can't determine immediate size"));
8085 i
.types
[j
] = overlap
;
8095 /* Update the first 2 immediate operands. */
8096 n
= i
.operands
> 2 ? 2 : i
.operands
;
8099 for (j
= 0; j
< n
; j
++)
8100 if (update_imm (j
) == 0)
8103 /* The 3rd operand can't be immediate operand. */
8104 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8110 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8113 if (r
->reg_flags
& RegRex
)
8115 if (i
.rex
& rex_bit
)
8116 as_bad (_("same type of prefix used twice"));
8119 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8121 gas_assert (i
.vex
.register_specifier
== r
);
8122 i
.vex
.register_specifier
+= 8;
8125 if (r
->reg_flags
& RegVRex
)
8130 process_operands (void)
8132 /* Default segment register this instruction will use for memory
8133 accesses. 0 means unknown. This is only for optimizing out
8134 unnecessary segment overrides. */
8135 const reg_entry
*default_seg
= NULL
;
8137 /* We only need to check those implicit registers for instructions
8138 with 3 operands or less. */
8139 if (i
.operands
<= 3)
8140 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8141 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8144 if (i
.tm
.opcode_modifier
.sse2avx
)
8146 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8148 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8149 i
.prefix
[REX_PREFIX
] = 0;
8152 /* ImmExt should be processed after SSE2AVX. */
8153 else if (i
.tm
.opcode_modifier
.immext
)
8156 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8157 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8158 new destination operand here, while converting the source one to register
8160 if (i
.tm
.mnem_off
== MN_tilezero
)
8162 i
.op
[1].regs
= i
.op
[0].regs
;
8163 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8164 i
.types
[1] = i
.types
[0];
8165 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8166 i
.flags
[1] = i
.flags
[0];
8172 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8174 static const i386_operand_type regxmm
= {
8175 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8177 unsigned int dupl
= i
.operands
;
8178 unsigned int dest
= dupl
- 1;
8181 /* The destination must be an xmm register. */
8182 gas_assert (i
.reg_operands
8183 && MAX_OPERANDS
> dupl
8184 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8186 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8187 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8189 /* Keep xmm0 for instructions with VEX prefix and 3
8191 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8192 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8197 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8199 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8201 /* Add the implicit xmm0 for instructions with VEX prefix
8203 for (j
= i
.operands
; j
> 0; j
--)
8205 i
.op
[j
] = i
.op
[j
- 1];
8206 i
.types
[j
] = i
.types
[j
- 1];
8207 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8208 i
.flags
[j
] = i
.flags
[j
- 1];
8211 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8212 i
.types
[0] = regxmm
;
8213 i
.tm
.operand_types
[0] = regxmm
;
8216 i
.reg_operands
+= 2;
8221 i
.op
[dupl
] = i
.op
[dest
];
8222 i
.types
[dupl
] = i
.types
[dest
];
8223 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8224 i
.flags
[dupl
] = i
.flags
[dest
];
8233 i
.op
[dupl
] = i
.op
[dest
];
8234 i
.types
[dupl
] = i
.types
[dest
];
8235 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8236 i
.flags
[dupl
] = i
.flags
[dest
];
8239 if (i
.tm
.opcode_modifier
.immext
)
8242 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8243 && i
.tm
.opcode_modifier
.modrm
)
8247 for (j
= 1; j
< i
.operands
; j
++)
8249 i
.op
[j
- 1] = i
.op
[j
];
8250 i
.types
[j
- 1] = i
.types
[j
];
8252 /* We need to adjust fields in i.tm since they are used by
8253 build_modrm_byte. */
8254 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8256 i
.flags
[j
- 1] = i
.flags
[j
];
8259 /* No adjustment to i.reg_operands: This was already done at the top
8264 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8266 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8268 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8269 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8270 regnum
= register_number (i
.op
[1].regs
);
8271 first_reg_in_group
= regnum
& ~3;
8272 last_reg_in_group
= first_reg_in_group
+ 3;
8273 if (regnum
!= first_reg_in_group
)
8274 as_warn (_("source register `%s%s' implicitly denotes"
8275 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8276 register_prefix
, i
.op
[1].regs
->reg_name
,
8277 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8278 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8281 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8283 /* The imul $imm, %reg instruction is converted into
8284 imul $imm, %reg, %reg, and the clr %reg instruction
8285 is converted into xor %reg, %reg. */
8287 unsigned int first_reg_op
;
8289 if (operand_type_check (i
.types
[0], reg
))
8293 /* Pretend we saw the extra register operand. */
8294 gas_assert (i
.reg_operands
== 1
8295 && i
.op
[first_reg_op
+ 1].regs
== 0);
8296 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8297 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8302 if (i
.tm
.opcode_modifier
.modrm
)
8304 /* The opcode is completed (modulo i.tm.extension_opcode which
8305 must be put into the modrm byte). Now, we make the modrm and
8306 index base bytes based on all the info we've collected. */
8308 default_seg
= build_modrm_byte ();
8310 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8312 /* Warn about some common errors, but press on regardless. */
8313 if (i
.operands
== 2)
8315 /* Reversed arguments on faddp or fmulp. */
8316 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8317 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8318 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8320 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8322 /* Extraneous `l' suffix on fp insn. */
8323 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8324 register_prefix
, i
.op
[0].regs
->reg_name
);
8328 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8330 if (flag_code
!= CODE_64BIT
8331 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8332 && i
.op
[0].regs
->reg_num
== 1
8333 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8334 && i
.op
[0].regs
->reg_num
< 4)
8336 as_bad (_("you can't `%s %s%s'"),
8337 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8340 if (i
.op
[0].regs
->reg_num
> 3
8341 && i
.tm
.opcode_space
== SPACE_BASE
)
8343 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8344 i
.tm
.opcode_space
= SPACE_0F
;
8346 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8348 else if (i
.tm
.opcode_space
== SPACE_BASE
8349 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8351 default_seg
= reg_ds
;
8353 else if (i
.tm
.opcode_modifier
.isstring
)
8355 /* For the string instructions that allow a segment override
8356 on one of their operands, the default segment is ds. */
8357 default_seg
= reg_ds
;
8359 else if (i
.short_form
)
8361 /* The register operand is in the 1st or 2nd non-immediate operand. */
8362 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8365 && r
->reg_type
.bitfield
.instance
== Accum
8366 && i
.op
[i
.imm_operands
+ 1].regs
)
8367 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8368 /* Register goes in low 3 bits of opcode. */
8369 i
.tm
.base_opcode
|= r
->reg_num
;
8370 set_rex_vrex (r
, REX_B
, false);
8372 if (dot_insn () && i
.reg_operands
== 2)
8374 gas_assert (is_any_vex_encoding (&i
.tm
)
8375 || i
.vec_encoding
!= vex_encoding_default
);
8376 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8379 else if (i
.reg_operands
== 1
8380 && !i
.flags
[i
.operands
- 1]
8381 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8384 gas_assert (is_any_vex_encoding (&i
.tm
)
8385 || i
.vec_encoding
!= vex_encoding_default
);
8386 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8389 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8390 && i
.tm
.mnem_off
== MN_lea
)
8392 if (!quiet_warnings
)
8393 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8394 if (optimize
&& !i
.no_optimize
)
8397 i
.prefix
[SEG_PREFIX
] = 0;
8401 /* If a segment was explicitly specified, and the specified segment
8402 is neither the default nor the one already recorded from a prefix,
8403 use an opcode prefix to select it. If we never figured out what
8404 the default segment is, then default_seg will be zero at this
8405 point, and the specified segment prefix will always be used. */
8407 && i
.seg
[0] != default_seg
8408 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8410 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8416 static const reg_entry
*
8417 build_modrm_byte (void)
8419 const reg_entry
*default_seg
= NULL
;
8420 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8421 /* Compensate for kludge in md_assemble(). */
8422 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8423 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8424 unsigned int v
, op
, reg_slot
= ~0;
8426 /* Accumulator (in particular %st), shift count (%cl), and alike need
8427 to be skipped just like immediate operands do. */
8428 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8430 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8433 for (op
= source
; op
< i
.operands
; ++op
)
8434 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8437 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8441 /* There are 2 kinds of instructions:
8442 1. 5 operands: 4 register operands or 3 register operands
8443 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8444 VexW0 or VexW1. The destination must be either XMM, YMM or
8446 2. 4 operands: 4 register operands or 3 register operands
8447 plus 1 memory operand, with VexXDS.
8448 3. Other equivalent combinations when coming from s_insn(). */
8449 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8450 && i
.tm
.opcode_modifier
.vexw
);
8451 gas_assert (dot_insn ()
8452 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8454 /* Of the first two non-immediate operands the one with the template
8455 not allowing for a memory one is encoded in the immediate operand. */
8457 reg_slot
= source
+ 1;
8459 reg_slot
= source
++;
8463 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8464 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8467 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8469 if (i
.imm_operands
== 0)
8471 /* When there is no immediate operand, generate an 8bit
8472 immediate operand to encode the first operand. */
8473 exp
= &im_expressions
[i
.imm_operands
++];
8474 i
.op
[i
.operands
].imms
= exp
;
8475 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8478 exp
->X_op
= O_constant
;
8482 gas_assert (i
.imm_operands
== 1);
8483 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8484 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8486 /* Turn on Imm8 again so that output_imm will generate it. */
8487 i
.types
[0].bitfield
.imm8
= 1;
8491 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8492 << (3 + !(is_evex_encoding (&i
.tm
)
8493 || i
.vec_encoding
== vex_encoding_evex
));
8496 for (v
= source
+ 1; v
< dest
; ++v
)
8501 if (i
.tm
.extension_opcode
!= None
)
8507 gas_assert (source
< dest
);
8508 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8511 unsigned int tmp
= source
;
8517 if (v
< MAX_OPERANDS
)
8519 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8520 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8523 if (op
< i
.operands
)
8527 unsigned int fake_zero_displacement
= 0;
8529 gas_assert (i
.flags
[op
] & Operand_Mem
);
8531 if (i
.tm
.opcode_modifier
.sib
)
8533 /* The index register of VSIB shouldn't be RegIZ. */
8534 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8535 && i
.index_reg
->reg_num
== RegIZ
)
8538 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8541 i
.sib
.base
= NO_BASE_REGISTER
;
8542 i
.sib
.scale
= i
.log2_scale_factor
;
8543 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8544 i
.types
[op
].bitfield
.disp32
= 1;
8547 /* Since the mandatory SIB always has index register, so
8548 the code logic remains unchanged. The non-mandatory SIB
8549 without index register is allowed and will be handled
8553 if (i
.index_reg
->reg_num
== RegIZ
)
8554 i
.sib
.index
= NO_INDEX_REGISTER
;
8556 i
.sib
.index
= i
.index_reg
->reg_num
;
8557 set_rex_vrex (i
.index_reg
, REX_X
, false);
8561 default_seg
= reg_ds
;
8563 if (i
.base_reg
== 0)
8566 if (!i
.disp_operands
)
8567 fake_zero_displacement
= 1;
8568 if (i
.index_reg
== 0)
8570 /* Both check for VSIB and mandatory non-vector SIB. */
8571 gas_assert (!i
.tm
.opcode_modifier
.sib
8572 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8573 /* Operand is just <disp> */
8574 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8575 if (flag_code
== CODE_64BIT
)
8577 /* 64bit mode overwrites the 32bit absolute
8578 addressing by RIP relative addressing and
8579 absolute addressing is encoded by one of the
8580 redundant SIB forms. */
8581 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8582 i
.sib
.base
= NO_BASE_REGISTER
;
8583 i
.sib
.index
= NO_INDEX_REGISTER
;
8584 i
.types
[op
].bitfield
.disp32
= 1;
8586 else if ((flag_code
== CODE_16BIT
)
8587 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8589 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8590 i
.types
[op
].bitfield
.disp16
= 1;
8594 i
.rm
.regmem
= NO_BASE_REGISTER
;
8595 i
.types
[op
].bitfield
.disp32
= 1;
8598 else if (!i
.tm
.opcode_modifier
.sib
)
8600 /* !i.base_reg && i.index_reg */
8601 if (i
.index_reg
->reg_num
== RegIZ
)
8602 i
.sib
.index
= NO_INDEX_REGISTER
;
8604 i
.sib
.index
= i
.index_reg
->reg_num
;
8605 i
.sib
.base
= NO_BASE_REGISTER
;
8606 i
.sib
.scale
= i
.log2_scale_factor
;
8607 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8608 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8609 i
.types
[op
].bitfield
.disp32
= 1;
8610 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8614 /* RIP addressing for 64bit mode. */
8615 else if (i
.base_reg
->reg_num
== RegIP
)
8617 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8618 i
.rm
.regmem
= NO_BASE_REGISTER
;
8619 i
.types
[op
].bitfield
.disp8
= 0;
8620 i
.types
[op
].bitfield
.disp16
= 0;
8621 i
.types
[op
].bitfield
.disp32
= 1;
8622 i
.types
[op
].bitfield
.disp64
= 0;
8623 i
.flags
[op
] |= Operand_PCrel
;
8624 if (! i
.disp_operands
)
8625 fake_zero_displacement
= 1;
8627 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8629 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8630 switch (i
.base_reg
->reg_num
)
8633 if (i
.index_reg
== 0)
8635 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8636 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8639 default_seg
= reg_ss
;
8640 if (i
.index_reg
== 0)
8643 if (operand_type_check (i
.types
[op
], disp
) == 0)
8645 /* fake (%bp) into 0(%bp) */
8646 if (i
.disp_encoding
== disp_encoding_16bit
)
8647 i
.types
[op
].bitfield
.disp16
= 1;
8649 i
.types
[op
].bitfield
.disp8
= 1;
8650 fake_zero_displacement
= 1;
8653 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8654 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8656 default: /* (%si) -> 4 or (%di) -> 5 */
8657 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8659 if (!fake_zero_displacement
8663 fake_zero_displacement
= 1;
8664 if (i
.disp_encoding
== disp_encoding_8bit
)
8665 i
.types
[op
].bitfield
.disp8
= 1;
8667 i
.types
[op
].bitfield
.disp16
= 1;
8669 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8671 else /* i.base_reg and 32/64 bit mode */
8673 if (operand_type_check (i
.types
[op
], disp
))
8675 i
.types
[op
].bitfield
.disp16
= 0;
8676 i
.types
[op
].bitfield
.disp64
= 0;
8677 i
.types
[op
].bitfield
.disp32
= 1;
8680 if (!i
.tm
.opcode_modifier
.sib
)
8681 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8682 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8684 i
.sib
.base
= i
.base_reg
->reg_num
;
8685 /* x86-64 ignores REX prefix bit here to avoid decoder
8687 if (!(i
.base_reg
->reg_flags
& RegRex
)
8688 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8689 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8690 default_seg
= reg_ss
;
8691 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8693 fake_zero_displacement
= 1;
8694 if (i
.disp_encoding
== disp_encoding_32bit
)
8695 i
.types
[op
].bitfield
.disp32
= 1;
8697 i
.types
[op
].bitfield
.disp8
= 1;
8699 i
.sib
.scale
= i
.log2_scale_factor
;
8700 if (i
.index_reg
== 0)
8702 /* Only check for VSIB. */
8703 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8704 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8705 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8707 /* <disp>(%esp) becomes two byte modrm with no index
8708 register. We've already stored the code for esp
8709 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8710 Any base register besides %esp will not use the
8711 extra modrm byte. */
8712 i
.sib
.index
= NO_INDEX_REGISTER
;
8714 else if (!i
.tm
.opcode_modifier
.sib
)
8716 if (i
.index_reg
->reg_num
== RegIZ
)
8717 i
.sib
.index
= NO_INDEX_REGISTER
;
8719 i
.sib
.index
= i
.index_reg
->reg_num
;
8720 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8721 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8726 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8727 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8731 if (!fake_zero_displacement
8735 fake_zero_displacement
= 1;
8736 if (i
.disp_encoding
== disp_encoding_8bit
)
8737 i
.types
[op
].bitfield
.disp8
= 1;
8739 i
.types
[op
].bitfield
.disp32
= 1;
8741 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8745 if (fake_zero_displacement
)
8747 /* Fakes a zero displacement assuming that i.types[op]
8748 holds the correct displacement size. */
8751 gas_assert (i
.op
[op
].disps
== 0);
8752 exp
= &disp_expressions
[i
.disp_operands
++];
8753 i
.op
[op
].disps
= exp
;
8754 exp
->X_op
= O_constant
;
8755 exp
->X_add_number
= 0;
8756 exp
->X_add_symbol
= (symbolS
*) 0;
8757 exp
->X_op_symbol
= (symbolS
*) 0;
8763 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8764 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8775 if (!i
.tm
.opcode_modifier
.regmem
)
8777 gas_assert (source
< MAX_OPERANDS
);
8778 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8779 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8780 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8785 gas_assert (dest
< MAX_OPERANDS
);
8786 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8787 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8792 /* Fill in i.rm.reg field with extension opcode (if any) or the
8793 appropriate register. */
8794 if (i
.tm
.extension_opcode
!= None
)
8795 i
.rm
.reg
= i
.tm
.extension_opcode
;
8796 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
8798 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8799 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8803 gas_assert (source
< MAX_OPERANDS
);
8804 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8805 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8808 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8810 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
8812 add_prefix (LOCK_PREFIX_OPCODE
);
8819 frag_opcode_byte (unsigned char byte
)
8821 if (now_seg
!= absolute_section
)
8822 FRAG_APPEND_1_CHAR (byte
);
8824 ++abs_section_offset
;
8828 flip_code16 (unsigned int code16
)
8830 gas_assert (i
.tm
.operands
== 1);
8832 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8833 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8834 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8839 output_branch (void)
8845 relax_substateT subtype
;
8849 if (now_seg
== absolute_section
)
8851 as_bad (_("relaxable branches not supported in absolute section"));
8855 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8856 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8859 if (i
.prefix
[DATA_PREFIX
] != 0)
8863 code16
^= flip_code16(code16
);
8865 /* Pentium4 branch hints. */
8866 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8867 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8872 if (i
.prefix
[REX_PREFIX
] != 0)
8878 /* BND prefixed jump. */
8879 if (i
.prefix
[BND_PREFIX
] != 0)
8885 if (i
.prefixes
!= 0)
8886 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8888 /* It's always a symbol; End frag & setup for relax.
8889 Make sure there is enough room in this frag for the largest
8890 instruction we may generate in md_convert_frag. This is 2
8891 bytes for the opcode and room for the prefix and largest
8893 frag_grow (prefix
+ 2 + 4);
8894 /* Prefix and 1 opcode byte go in fr_fix. */
8895 p
= frag_more (prefix
+ 1);
8896 if (i
.prefix
[DATA_PREFIX
] != 0)
8897 *p
++ = DATA_PREFIX_OPCODE
;
8898 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8899 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8900 *p
++ = i
.prefix
[SEG_PREFIX
];
8901 if (i
.prefix
[BND_PREFIX
] != 0)
8902 *p
++ = BND_PREFIX_OPCODE
;
8903 if (i
.prefix
[REX_PREFIX
] != 0)
8904 *p
++ = i
.prefix
[REX_PREFIX
];
8905 *p
= i
.tm
.base_opcode
;
8907 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8908 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8909 else if (cpu_arch_flags
.bitfield
.cpui386
)
8910 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8912 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8915 sym
= i
.op
[0].disps
->X_add_symbol
;
8916 off
= i
.op
[0].disps
->X_add_number
;
8918 if (i
.op
[0].disps
->X_op
!= O_constant
8919 && i
.op
[0].disps
->X_op
!= O_symbol
)
8921 /* Handle complex expressions. */
8922 sym
= make_expr_symbol (i
.op
[0].disps
);
8926 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
8928 /* 1 possible extra opcode + 4 byte displacement go in var part.
8929 Pass reloc in fr_var. */
8930 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8934 /* Return TRUE iff PLT32 relocation should be used for branching to
8938 need_plt32_p (symbolS
*s
)
8940 /* PLT32 relocation is ELF only. */
8945 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8946 krtld support it. */
8950 /* Since there is no need to prepare for PLT branch on x86-64, we
8951 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8952 be used as a marker for 32-bit PC-relative branches. */
8959 /* Weak or undefined symbol need PLT32 relocation. */
8960 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8963 /* Non-global symbol doesn't need PLT32 relocation. */
8964 if (! S_IS_EXTERNAL (s
))
8967 /* Other global symbols need PLT32 relocation. NB: Symbol with
8968 non-default visibilities are treated as normal global symbol
8969 so that PLT32 relocation can be used as a marker for 32-bit
8970 PC-relative branches. It is useful for linker relaxation. */
8981 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8983 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8985 /* This is a loop or jecxz type instruction. */
8987 if (i
.prefix
[ADDR_PREFIX
] != 0)
8989 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8992 /* Pentium4 branch hints. */
8993 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8994 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8996 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9005 if (flag_code
== CODE_16BIT
)
9008 if (i
.prefix
[DATA_PREFIX
] != 0)
9010 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9012 code16
^= flip_code16(code16
);
9020 /* BND prefixed jump. */
9021 if (i
.prefix
[BND_PREFIX
] != 0)
9023 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9027 if (i
.prefix
[REX_PREFIX
] != 0)
9029 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9033 if (i
.prefixes
!= 0)
9034 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9036 if (now_seg
== absolute_section
)
9038 abs_section_offset
+= i
.opcode_length
+ size
;
9042 p
= frag_more (i
.opcode_length
+ size
);
9043 switch (i
.opcode_length
)
9046 *p
++ = i
.tm
.base_opcode
>> 8;
9049 *p
++ = i
.tm
.base_opcode
;
9055 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9056 if (flag_code
== CODE_64BIT
&& size
== 4
9057 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9058 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9059 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9062 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9064 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9065 i
.op
[0].disps
, 1, jump_reloc
);
9067 /* All jumps handled here are signed, but don't unconditionally use a
9068 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9069 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9074 fixP
->fx_signed
= 1;
9078 if (i
.tm
.mnem_off
== MN_xbegin
)
9079 fixP
->fx_signed
= 1;
9083 if (flag_code
== CODE_64BIT
)
9084 fixP
->fx_signed
= 1;
9090 output_interseg_jump (void)
9098 if (flag_code
== CODE_16BIT
)
9102 if (i
.prefix
[DATA_PREFIX
] != 0)
9109 gas_assert (!i
.prefix
[REX_PREFIX
]);
9115 if (i
.prefixes
!= 0)
9116 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9118 if (now_seg
== absolute_section
)
9120 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9124 /* 1 opcode; 2 segment; offset */
9125 p
= frag_more (prefix
+ 1 + 2 + size
);
9127 if (i
.prefix
[DATA_PREFIX
] != 0)
9128 *p
++ = DATA_PREFIX_OPCODE
;
9130 if (i
.prefix
[REX_PREFIX
] != 0)
9131 *p
++ = i
.prefix
[REX_PREFIX
];
9133 *p
++ = i
.tm
.base_opcode
;
9134 if (i
.op
[1].imms
->X_op
== O_constant
)
9136 offsetT n
= i
.op
[1].imms
->X_add_number
;
9139 && !fits_in_unsigned_word (n
)
9140 && !fits_in_signed_word (n
))
9142 as_bad (_("16-bit jump out of range"));
9145 md_number_to_chars (p
, n
, size
);
9148 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9149 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9152 if (i
.op
[0].imms
->X_op
== O_constant
)
9153 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9155 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9156 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9164 asection
*seg
= now_seg
;
9165 subsegT subseg
= now_subseg
;
9167 unsigned int alignment
, align_size_1
;
9168 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9169 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9170 unsigned int padding
;
9172 if (!IS_ELF
|| !x86_used_note
)
9175 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9177 /* The .note.gnu.property section layout:
9179 Field Length Contents
9182 n_descsz 4 The note descriptor size
9183 n_type 4 NT_GNU_PROPERTY_TYPE_0
9185 n_desc n_descsz The program property array
9189 /* Create the .note.gnu.property section. */
9190 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9191 bfd_set_section_flags (sec
,
9198 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9209 bfd_set_section_alignment (sec
, alignment
);
9210 elf_section_type (sec
) = SHT_NOTE
;
9212 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9214 isa_1_descsz_raw
= 4 + 4 + 4;
9215 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9216 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9218 feature_2_descsz_raw
= isa_1_descsz
;
9219 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9221 feature_2_descsz_raw
+= 4 + 4 + 4;
9222 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9223 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9226 descsz
= feature_2_descsz
;
9227 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9228 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9230 /* Write n_namsz. */
9231 md_number_to_chars (p
, (valueT
) 4, 4);
9233 /* Write n_descsz. */
9234 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9237 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9240 memcpy (p
+ 4 * 3, "GNU", 4);
9242 /* Write 4-byte type. */
9243 md_number_to_chars (p
+ 4 * 4,
9244 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9246 /* Write 4-byte data size. */
9247 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9249 /* Write 4-byte data. */
9250 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9252 /* Zero out paddings. */
9253 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9255 memset (p
+ 4 * 7, 0, padding
);
9257 /* Write 4-byte type. */
9258 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9259 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9261 /* Write 4-byte data size. */
9262 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9264 /* Write 4-byte data. */
9265 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9266 (valueT
) x86_feature_2_used
, 4);
9268 /* Zero out paddings. */
9269 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9271 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9273 /* We probably can't restore the current segment, for there likely
9276 subseg_set (seg
, subseg
);
9280 x86_support_sframe_p (void)
9282 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9283 return (x86_elf_abi
== X86_64_ABI
);
9287 x86_sframe_ra_tracking_p (void)
9289 /* In AMD64, return address is always stored on the stack at a fixed offset
9290 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9291 Do not track explicitly via an SFrame Frame Row Entry. */
9296 x86_sframe_cfa_ra_offset (void)
9298 gas_assert (x86_elf_abi
== X86_64_ABI
);
9299 return (offsetT
) -8;
9303 x86_sframe_get_abi_arch (void)
9305 unsigned char sframe_abi_arch
= 0;
9307 if (x86_support_sframe_p ())
9309 gas_assert (!target_big_endian
);
9310 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9313 return sframe_abi_arch
;
9319 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9320 const char *frag_now_ptr
)
9322 unsigned int len
= 0;
9324 if (start_frag
!= frag_now
)
9326 const fragS
*fr
= start_frag
;
9331 } while (fr
&& fr
!= frag_now
);
9334 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9337 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9338 be macro-fused with conditional jumps.
9339 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9340 or is one of the following format:
9353 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9355 /* No RIP address. */
9356 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9359 /* No opcodes outside of base encoding space. */
9360 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9363 /* add, sub without add/sub m, imm. */
9364 if (i
.tm
.base_opcode
<= 5
9365 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9366 || ((i
.tm
.base_opcode
| 3) == 0x83
9367 && (i
.tm
.extension_opcode
== 0x5
9368 || i
.tm
.extension_opcode
== 0x0)))
9370 *mf_cmp_p
= mf_cmp_alu_cmp
;
9371 return !(i
.mem_operands
&& i
.imm_operands
);
9374 /* and without and m, imm. */
9375 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9376 || ((i
.tm
.base_opcode
| 3) == 0x83
9377 && i
.tm
.extension_opcode
== 0x4))
9379 *mf_cmp_p
= mf_cmp_test_and
;
9380 return !(i
.mem_operands
&& i
.imm_operands
);
9383 /* test without test m imm. */
9384 if ((i
.tm
.base_opcode
| 1) == 0x85
9385 || (i
.tm
.base_opcode
| 1) == 0xa9
9386 || ((i
.tm
.base_opcode
| 1) == 0xf7
9387 && i
.tm
.extension_opcode
== 0))
9389 *mf_cmp_p
= mf_cmp_test_and
;
9390 return !(i
.mem_operands
&& i
.imm_operands
);
9393 /* cmp without cmp m, imm. */
9394 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9395 || ((i
.tm
.base_opcode
| 3) == 0x83
9396 && (i
.tm
.extension_opcode
== 0x7)))
9398 *mf_cmp_p
= mf_cmp_alu_cmp
;
9399 return !(i
.mem_operands
&& i
.imm_operands
);
9402 /* inc, dec without inc/dec m. */
9403 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9404 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9405 || ((i
.tm
.base_opcode
| 1) == 0xff
9406 && i
.tm
.extension_opcode
<= 0x1))
9408 *mf_cmp_p
= mf_cmp_incdec
;
9409 return !i
.mem_operands
;
9415 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9418 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9420 /* NB: Don't work with COND_JUMP86 without i386. */
9421 if (!align_branch_power
9422 || now_seg
== absolute_section
9423 || !cpu_arch_flags
.bitfield
.cpui386
9424 || !(align_branch
& align_branch_fused_bit
))
9427 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9429 if (last_insn
.kind
== last_insn_other
9430 || last_insn
.seg
!= now_seg
)
9433 as_warn_where (last_insn
.file
, last_insn
.line
,
9434 _("`%s` skips -malign-branch-boundary on `%s`"),
9435 last_insn
.name
, insn_name (&i
.tm
));
9441 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9444 add_branch_prefix_frag_p (void)
9446 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9447 to PadLock instructions since they include prefixes in opcode. */
9448 if (!align_branch_power
9449 || !align_branch_prefix_size
9450 || now_seg
== absolute_section
9451 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9452 || !cpu_arch_flags
.bitfield
.cpui386
)
9455 /* Don't add prefix if it is a prefix or there is no operand in case
9456 that segment prefix is special. */
9457 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9460 if (last_insn
.kind
== last_insn_other
9461 || last_insn
.seg
!= now_seg
)
9465 as_warn_where (last_insn
.file
, last_insn
.line
,
9466 _("`%s` skips -malign-branch-boundary on `%s`"),
9467 last_insn
.name
, insn_name (&i
.tm
));
9472 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9475 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9476 enum mf_jcc_kind
*mf_jcc_p
)
9480 /* NB: Don't work with COND_JUMP86 without i386. */
9481 if (!align_branch_power
9482 || now_seg
== absolute_section
9483 || !cpu_arch_flags
.bitfield
.cpui386
9484 || i
.tm
.opcode_space
!= SPACE_BASE
)
9489 /* Check for jcc and direct jmp. */
9490 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9492 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9494 *branch_p
= align_branch_jmp
;
9495 add_padding
= align_branch
& align_branch_jmp_bit
;
9499 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9500 igore the lowest bit. */
9501 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9502 *branch_p
= align_branch_jcc
;
9503 if ((align_branch
& align_branch_jcc_bit
))
9507 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9510 *branch_p
= align_branch_ret
;
9511 if ((align_branch
& align_branch_ret_bit
))
9516 /* Check for indirect jmp, direct and indirect calls. */
9517 if (i
.tm
.base_opcode
== 0xe8)
9520 *branch_p
= align_branch_call
;
9521 if ((align_branch
& align_branch_call_bit
))
9524 else if (i
.tm
.base_opcode
== 0xff
9525 && (i
.tm
.extension_opcode
== 2
9526 || i
.tm
.extension_opcode
== 4))
9528 /* Indirect call and jmp. */
9529 *branch_p
= align_branch_indirect
;
9530 if ((align_branch
& align_branch_indirect_bit
))
9537 && (i
.op
[0].disps
->X_op
== O_symbol
9538 || (i
.op
[0].disps
->X_op
== O_subtract
9539 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9541 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9542 /* No padding to call to global or undefined tls_get_addr. */
9543 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9544 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9550 && last_insn
.kind
!= last_insn_other
9551 && last_insn
.seg
== now_seg
)
9554 as_warn_where (last_insn
.file
, last_insn
.line
,
9555 _("`%s` skips -malign-branch-boundary on `%s`"),
9556 last_insn
.name
, insn_name (&i
.tm
));
9566 fragS
*insn_start_frag
;
9567 offsetT insn_start_off
;
9568 fragS
*fragP
= NULL
;
9569 enum align_branch_kind branch
= align_branch_none
;
9570 /* The initializer is arbitrary just to avoid uninitialized error.
9571 it's actually either assigned in add_branch_padding_frag_p
9572 or never be used. */
9573 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9575 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9576 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9578 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9579 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9580 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9582 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9583 || i
.tm
.cpu_flags
.bitfield
.cpu287
9584 || i
.tm
.cpu_flags
.bitfield
.cpu387
9585 || i
.tm
.cpu_flags
.bitfield
.cpu687
9586 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9587 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9589 if ((i
.xstate
& xstate_mmx
)
9590 || i
.tm
.mnem_off
== MN_emms
9591 || i
.tm
.mnem_off
== MN_femms
)
9592 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9596 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9597 i
.xstate
|= xstate_zmm
;
9598 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9599 i
.xstate
|= xstate_ymm
;
9600 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9601 i
.xstate
|= xstate_xmm
;
9604 /* vzeroall / vzeroupper */
9605 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9606 i
.xstate
|= xstate_ymm
;
9608 if ((i
.xstate
& xstate_xmm
)
9609 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9610 || (i
.tm
.base_opcode
== 0xae
9611 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9612 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9613 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9614 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9615 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9617 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9618 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9619 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9620 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9621 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9622 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9623 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9624 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9625 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9626 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9627 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9628 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9629 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9630 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9632 if (x86_feature_2_used
9633 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9634 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9635 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9636 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9637 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9638 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9639 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9640 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9641 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9642 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9643 /* LAHF-SAHF insns in 64-bit mode. */
9644 || (flag_code
== CODE_64BIT
9645 && (i
.tm
.base_opcode
| 1) == 0x9f
9646 && i
.tm
.opcode_space
== SPACE_BASE
))
9647 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9648 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9649 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9650 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9651 XOP, FMA4, LPW, TBM, and AMX. */
9652 || (i
.tm
.opcode_modifier
.vex
9653 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9654 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9655 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9656 && !i
.tm
.cpu_flags
.bitfield
.cpuxop
9657 && !i
.tm
.cpu_flags
.bitfield
.cpufma4
9658 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9659 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9660 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9661 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9662 || i
.tm
.cpu_flags
.bitfield
.cpufma
9663 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9664 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9665 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9666 || (x86_feature_2_used
9667 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9668 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9669 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9670 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9671 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9672 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9673 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9674 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9675 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9676 AVX512-4FMAPS, and AVX512-4VNNIW. */
9677 || (i
.tm
.opcode_modifier
.evex
9678 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9679 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9680 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
9681 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9682 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9686 /* Tie dwarf2 debug info to the address at the start of the insn.
9687 We can't do this after the insn has been output as the current
9688 frag may have been closed off. eg. by frag_var. */
9689 dwarf2_emit_insn (0);
9691 insn_start_frag
= frag_now
;
9692 insn_start_off
= frag_now_fix ();
9694 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9697 /* Branch can be 8 bytes. Leave some room for prefixes. */
9698 unsigned int max_branch_padding_size
= 14;
9700 /* Align section to boundary. */
9701 record_alignment (now_seg
, align_branch_power
);
9703 /* Make room for padding. */
9704 frag_grow (max_branch_padding_size
);
9706 /* Start of the padding. */
9711 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9712 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9715 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9716 fragP
->tc_frag_data
.branch_type
= branch
;
9717 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9720 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9721 && !pre_386_16bit_warned
)
9723 as_warn (_("use .code16 to ensure correct addressing mode"));
9724 pre_386_16bit_warned
= true;
9728 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9730 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9731 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9733 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9734 output_interseg_jump ();
9737 /* Output normal instructions here. */
9741 enum mf_cmp_kind mf_cmp
;
9744 && (i
.tm
.base_opcode
== 0xaee8
9745 || i
.tm
.base_opcode
== 0xaef0
9746 || i
.tm
.base_opcode
== 0xaef8))
9748 /* Encode lfence, mfence, and sfence as
9749 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9750 if (flag_code
== CODE_16BIT
)
9751 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9752 else if (omit_lock_prefix
)
9753 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9755 else if (now_seg
!= absolute_section
)
9757 offsetT val
= 0x240483f0ULL
;
9760 md_number_to_chars (p
, val
, 5);
9763 abs_section_offset
+= 5;
9767 /* Some processors fail on LOCK prefix. This options makes
9768 assembler ignore LOCK prefix and serves as a workaround. */
9769 if (omit_lock_prefix
)
9771 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9772 && i
.tm
.opcode_modifier
.isprefix
)
9774 i
.prefix
[LOCK_PREFIX
] = 0;
9778 /* Skip if this is a branch. */
9780 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9782 /* Make room for padding. */
9783 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9788 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9789 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9792 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9793 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9794 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9796 else if (add_branch_prefix_frag_p ())
9798 unsigned int max_prefix_size
= align_branch_prefix_size
;
9800 /* Make room for padding. */
9801 frag_grow (max_prefix_size
);
9806 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9807 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9810 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9813 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9814 don't need the explicit prefix. */
9815 if (!is_any_vex_encoding (&i
.tm
))
9817 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9826 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9827 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9831 switch (i
.opcode_length
)
9836 /* Check for pseudo prefixes. */
9837 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9839 as_bad_where (insn_start_frag
->fr_file
,
9840 insn_start_frag
->fr_line
,
9841 _("pseudo prefix without instruction"));
9851 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9852 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9853 R_X86_64_GOTTPOFF relocation so that linker can safely
9854 perform IE->LE optimization. A dummy REX_OPCODE prefix
9855 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9856 relocation for GDesc -> IE/LE optimization. */
9857 if (x86_elf_abi
== X86_64_X32_ABI
9859 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9860 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9861 && i
.prefix
[REX_PREFIX
] == 0)
9862 add_prefix (REX_OPCODE
);
9865 /* The prefix bytes. */
9866 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9868 frag_opcode_byte (*q
);
9872 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9878 frag_opcode_byte (*q
);
9881 /* There should be no other prefixes for instructions
9886 /* For EVEX instructions i.vrex should become 0 after
9887 build_evex_prefix. For VEX instructions upper 16 registers
9888 aren't available, so VREX should be 0. */
9891 /* Now the VEX prefix. */
9892 if (now_seg
!= absolute_section
)
9894 p
= frag_more (i
.vex
.length
);
9895 for (j
= 0; j
< i
.vex
.length
; j
++)
9896 p
[j
] = i
.vex
.bytes
[j
];
9899 abs_section_offset
+= i
.vex
.length
;
9902 /* Now the opcode; be careful about word order here! */
9903 j
= i
.opcode_length
;
9905 switch (i
.tm
.opcode_space
)
9920 if (now_seg
== absolute_section
)
9921 abs_section_offset
+= j
;
9924 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9930 && i
.tm
.opcode_space
!= SPACE_BASE
)
9933 if (i
.tm
.opcode_space
!= SPACE_0F
)
9934 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
9938 switch (i
.opcode_length
)
9941 /* Put out high byte first: can't use md_number_to_chars! */
9942 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9945 *p
= i
.tm
.base_opcode
& 0xff;
9954 /* Now the modrm byte and sib byte (if present). */
9955 if (i
.tm
.opcode_modifier
.modrm
)
9957 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9959 | (i
.rm
.mode
<< 6));
9960 /* If i.rm.regmem == ESP (4)
9961 && i.rm.mode != (Register mode)
9963 ==> need second modrm byte. */
9964 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9966 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9967 frag_opcode_byte ((i
.sib
.base
<< 0)
9968 | (i
.sib
.index
<< 3)
9969 | (i
.sib
.scale
<< 6));
9972 if (i
.disp_operands
)
9973 output_disp (insn_start_frag
, insn_start_off
);
9976 output_imm (insn_start_frag
, insn_start_off
);
9979 * frag_now_fix () returning plain abs_section_offset when we're in the
9980 * absolute section, and abs_section_offset not getting updated as data
9981 * gets added to the frag breaks the logic below.
9983 if (now_seg
!= absolute_section
)
9985 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9987 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9991 /* NB: Don't add prefix with GOTPC relocation since
9992 output_disp() above depends on the fixed encoding
9993 length. Can't add prefix with TLS relocation since
9994 it breaks TLS linker optimization. */
9995 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9996 /* Prefix count on the current instruction. */
9997 unsigned int count
= i
.vex
.length
;
9999 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10000 /* REX byte is encoded in VEX/EVEX prefix. */
10001 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10004 /* Count prefixes for extended opcode maps. */
10006 switch (i
.tm
.opcode_space
)
10021 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10024 /* Set the maximum prefix size in BRANCH_PREFIX
10026 if (fragP
->tc_frag_data
.max_bytes
> max
)
10027 fragP
->tc_frag_data
.max_bytes
= max
;
10028 if (fragP
->tc_frag_data
.max_bytes
> count
)
10029 fragP
->tc_frag_data
.max_bytes
-= count
;
10031 fragP
->tc_frag_data
.max_bytes
= 0;
10035 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10037 unsigned int max_prefix_size
;
10038 if (align_branch_prefix_size
> max
)
10039 max_prefix_size
= max
;
10041 max_prefix_size
= align_branch_prefix_size
;
10042 if (max_prefix_size
> count
)
10043 fragP
->tc_frag_data
.max_prefix_length
10044 = max_prefix_size
- count
;
10047 /* Use existing segment prefix if possible. Use CS
10048 segment prefix in 64-bit mode. In 32-bit mode, use SS
10049 segment prefix with ESP/EBP base register and use DS
10050 segment prefix without ESP/EBP base register. */
10051 if (i
.prefix
[SEG_PREFIX
])
10052 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10053 else if (flag_code
== CODE_64BIT
)
10054 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10055 else if (i
.base_reg
10056 && (i
.base_reg
->reg_num
== 4
10057 || i
.base_reg
->reg_num
== 5))
10058 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10060 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10065 /* NB: Don't work with COND_JUMP86 without i386. */
10066 if (align_branch_power
10067 && now_seg
!= absolute_section
10068 && cpu_arch_flags
.bitfield
.cpui386
)
10070 /* Terminate each frag so that we can add prefix and check for
10072 frag_wane (frag_now
);
10079 pi ("" /*line*/, &i
);
10081 #endif /* DEBUG386 */
10084 /* Return the size of the displacement operand N. */
10087 disp_size (unsigned int n
)
10091 if (i
.types
[n
].bitfield
.disp64
)
10093 else if (i
.types
[n
].bitfield
.disp8
)
10095 else if (i
.types
[n
].bitfield
.disp16
)
10100 /* Return the size of the immediate operand N. */
10103 imm_size (unsigned int n
)
10106 if (i
.types
[n
].bitfield
.imm64
)
10108 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10110 else if (i
.types
[n
].bitfield
.imm16
)
10116 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10121 for (n
= 0; n
< i
.operands
; n
++)
10123 if (operand_type_check (i
.types
[n
], disp
))
10125 int size
= disp_size (n
);
10127 if (now_seg
== absolute_section
)
10128 abs_section_offset
+= size
;
10129 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10131 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10133 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10135 p
= frag_more (size
);
10136 md_number_to_chars (p
, val
, size
);
10140 enum bfd_reloc_code_real reloc_type
;
10141 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10142 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10143 && (!want_disp32 (&i
.tm
)
10144 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10145 && !i
.types
[n
].bitfield
.baseindex
)))
10149 /* We can't have 8 bit displacement here. */
10150 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10152 /* The PC relative address is computed relative
10153 to the instruction boundary, so in case immediate
10154 fields follows, we need to adjust the value. */
10155 if (pcrel
&& i
.imm_operands
)
10160 for (n1
= 0; n1
< i
.operands
; n1
++)
10161 if (operand_type_check (i
.types
[n1
], imm
))
10163 /* Only one immediate is allowed for PC
10164 relative address, except with .insn. */
10165 gas_assert (sz
== 0 || dot_insn ());
10166 sz
+= imm_size (n1
);
10168 /* We should find at least one immediate. */
10169 gas_assert (sz
!= 0);
10170 i
.op
[n
].disps
->X_add_number
-= sz
;
10173 p
= frag_more (size
);
10174 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10176 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10177 && (((reloc_type
== BFD_RELOC_32
10178 || reloc_type
== BFD_RELOC_X86_64_32S
10179 || (reloc_type
== BFD_RELOC_64
10181 && (i
.op
[n
].disps
->X_op
== O_symbol
10182 || (i
.op
[n
].disps
->X_op
== O_add
10183 && ((symbol_get_value_expression
10184 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10186 || reloc_type
== BFD_RELOC_32_PCREL
))
10190 reloc_type
= BFD_RELOC_386_GOTPC
;
10191 i
.has_gotpc_tls_reloc
= true;
10192 i
.op
[n
].disps
->X_add_number
+=
10193 encoding_length (insn_start_frag
, insn_start_off
, p
);
10195 else if (reloc_type
== BFD_RELOC_64
)
10196 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10198 /* Don't do the adjustment for x86-64, as there
10199 the pcrel addressing is relative to the _next_
10200 insn, and that is taken care of in other code. */
10201 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10203 else if (align_branch_power
)
10205 switch (reloc_type
)
10207 case BFD_RELOC_386_TLS_GD
:
10208 case BFD_RELOC_386_TLS_LDM
:
10209 case BFD_RELOC_386_TLS_IE
:
10210 case BFD_RELOC_386_TLS_IE_32
:
10211 case BFD_RELOC_386_TLS_GOTIE
:
10212 case BFD_RELOC_386_TLS_GOTDESC
:
10213 case BFD_RELOC_386_TLS_DESC_CALL
:
10214 case BFD_RELOC_X86_64_TLSGD
:
10215 case BFD_RELOC_X86_64_TLSLD
:
10216 case BFD_RELOC_X86_64_GOTTPOFF
:
10217 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10218 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10219 i
.has_gotpc_tls_reloc
= true;
10224 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10225 size
, i
.op
[n
].disps
, pcrel
,
10228 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10229 && !i
.prefix
[ADDR_PREFIX
])
10230 fixP
->fx_signed
= 1;
10232 /* Check for "call/jmp *mem", "mov mem, %reg",
10233 "test %reg, mem" and "binop mem, %reg" where binop
10234 is one of adc, add, and, cmp, or, sbb, sub, xor
10235 instructions without data prefix. Always generate
10236 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10237 if (i
.prefix
[DATA_PREFIX
] == 0
10238 && (generate_relax_relocations
10241 && i
.rm
.regmem
== 5))
10243 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10244 && i
.tm
.opcode_space
== SPACE_BASE
10245 && ((i
.operands
== 1
10246 && i
.tm
.base_opcode
== 0xff
10247 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10248 || (i
.operands
== 2
10249 && (i
.tm
.base_opcode
== 0x8b
10250 || i
.tm
.base_opcode
== 0x85
10251 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10255 fixP
->fx_tcbit
= i
.rex
!= 0;
10257 && (i
.base_reg
->reg_num
== RegIP
))
10258 fixP
->fx_tcbit2
= 1;
10261 fixP
->fx_tcbit2
= 1;
10269 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10274 for (n
= 0; n
< i
.operands
; n
++)
10276 if (operand_type_check (i
.types
[n
], imm
))
10278 int size
= imm_size (n
);
10280 if (now_seg
== absolute_section
)
10281 abs_section_offset
+= size
;
10282 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10286 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10288 p
= frag_more (size
);
10289 md_number_to_chars (p
, val
, size
);
10293 /* Not absolute_section.
10294 Need a 32-bit fixup (don't support 8bit
10295 non-absolute imms). Try to support other
10297 enum bfd_reloc_code_real reloc_type
;
10300 if (i
.types
[n
].bitfield
.imm32s
10301 && (i
.suffix
== QWORD_MNEM_SUFFIX
10302 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10308 p
= frag_more (size
);
10309 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10311 /* This is tough to explain. We end up with this one if we
10312 * have operands that look like
10313 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10314 * obtain the absolute address of the GOT, and it is strongly
10315 * preferable from a performance point of view to avoid using
10316 * a runtime relocation for this. The actual sequence of
10317 * instructions often look something like:
10322 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10324 * The call and pop essentially return the absolute address
10325 * of the label .L66 and store it in %ebx. The linker itself
10326 * will ultimately change the first operand of the addl so
10327 * that %ebx points to the GOT, but to keep things simple, the
10328 * .o file must have this operand set so that it generates not
10329 * the absolute address of .L66, but the absolute address of
10330 * itself. This allows the linker itself simply treat a GOTPC
10331 * relocation as asking for a pcrel offset to the GOT to be
10332 * added in, and the addend of the relocation is stored in the
10333 * operand field for the instruction itself.
10335 * Our job here is to fix the operand so that it would add
10336 * the correct offset so that %ebx would point to itself. The
10337 * thing that is tricky is that .-.L66 will point to the
10338 * beginning of the instruction, so we need to further modify
10339 * the operand so that it will point to itself. There are
10340 * other cases where you have something like:
10342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10344 * and here no correction would be required. Internally in
10345 * the assembler we treat operands of this form as not being
10346 * pcrel since the '.' is explicitly mentioned, and I wonder
10347 * whether it would simplify matters to do it this way. Who
10348 * knows. In earlier versions of the PIC patches, the
10349 * pcrel_adjust field was used to store the correction, but
10350 * since the expression is not pcrel, I felt it would be
10351 * confusing to do it this way. */
10353 if ((reloc_type
== BFD_RELOC_32
10354 || reloc_type
== BFD_RELOC_X86_64_32S
10355 || reloc_type
== BFD_RELOC_64
)
10357 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10358 && (i
.op
[n
].imms
->X_op
== O_symbol
10359 || (i
.op
[n
].imms
->X_op
== O_add
10360 && ((symbol_get_value_expression
10361 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10365 reloc_type
= BFD_RELOC_386_GOTPC
;
10366 else if (size
== 4)
10367 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10368 else if (size
== 8)
10369 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10370 i
.has_gotpc_tls_reloc
= true;
10371 i
.op
[n
].imms
->X_add_number
+=
10372 encoding_length (insn_start_frag
, insn_start_off
, p
);
10374 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10375 i
.op
[n
].imms
, 0, reloc_type
);
10381 /* x86_cons_fix_new is called via the expression parsing code when a
10382 reloc is needed. We use this hook to get the correct .got reloc. */
10383 static int cons_sign
= -1;
10386 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10387 expressionS
*exp
, bfd_reloc_code_real_type r
)
10389 r
= reloc (len
, 0, cons_sign
, r
);
10392 if (exp
->X_op
== O_secrel
)
10394 exp
->X_op
= O_symbol
;
10395 r
= BFD_RELOC_32_SECREL
;
10397 else if (exp
->X_op
== O_secidx
)
10398 r
= BFD_RELOC_16_SECIDX
;
10401 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10404 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10405 purpose of the `.dc.a' internal pseudo-op. */
10408 x86_address_bytes (void)
10410 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10412 return stdoutput
->arch_info
->bits_per_address
/ 8;
10415 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10416 || defined (LEX_AT)) && !defined (TE_PE)
10417 # define lex_got(reloc, adjust, types) NULL
10419 /* Parse operands of the form
10420 <symbol>@GOTOFF+<nnn>
10421 and similar .plt or .got references.
10423 If we find one, set up the correct relocation in RELOC and copy the
10424 input string, minus the `@GOTOFF' into a malloc'd buffer for
10425 parsing by the calling routine. Return this buffer, and if ADJUST
10426 is non-null set it to the length of the string we removed from the
10427 input line. Otherwise return NULL. */
10429 lex_got (enum bfd_reloc_code_real
*rel
,
10431 i386_operand_type
*types
)
10433 /* Some of the relocations depend on the size of what field is to
10434 be relocated. But in our callers i386_immediate and i386_displacement
10435 we don't yet know the operand size (this will be set by insn
10436 matching). Hence we record the word32 relocation here,
10437 and adjust the reloc according to the real size in reloc(). */
10438 static const struct
10442 const enum bfd_reloc_code_real rel
[2];
10443 const i386_operand_type types64
;
10444 bool need_GOT_symbol
;
10449 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10450 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10451 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10452 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10453 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10454 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10455 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10456 { .imm64 = 1, .disp64 = 1 } }
10459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10460 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10461 BFD_RELOC_SIZE32
},
10462 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10464 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10465 BFD_RELOC_X86_64_PLTOFF64
},
10466 { .bitfield
= { .imm64
= 1 } }, true },
10467 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10468 BFD_RELOC_X86_64_PLT32
},
10469 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10470 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10471 BFD_RELOC_X86_64_GOTPLT64
},
10472 OPERAND_TYPE_IMM64_DISP64
, true },
10473 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10474 BFD_RELOC_X86_64_GOTOFF64
},
10475 OPERAND_TYPE_IMM64_DISP64
, true },
10476 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10477 BFD_RELOC_X86_64_GOTPCREL
},
10478 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10479 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10480 BFD_RELOC_X86_64_TLSGD
},
10481 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10482 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10483 _dummy_first_bfd_reloc_code_real
},
10484 OPERAND_TYPE_NONE
, true },
10485 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10486 BFD_RELOC_X86_64_TLSLD
},
10487 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10488 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10489 BFD_RELOC_X86_64_GOTTPOFF
},
10490 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10491 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10492 BFD_RELOC_X86_64_TPOFF32
},
10493 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10494 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10495 _dummy_first_bfd_reloc_code_real
},
10496 OPERAND_TYPE_NONE
, true },
10497 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10498 BFD_RELOC_X86_64_DTPOFF32
},
10499 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10500 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10501 _dummy_first_bfd_reloc_code_real
},
10502 OPERAND_TYPE_NONE
, true },
10503 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10504 _dummy_first_bfd_reloc_code_real
},
10505 OPERAND_TYPE_NONE
, true },
10506 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10507 BFD_RELOC_X86_64_GOT32
},
10508 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10509 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10510 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10511 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10512 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10513 BFD_RELOC_X86_64_TLSDESC_CALL
},
10514 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10516 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10517 BFD_RELOC_32_SECREL
},
10518 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10521 #undef OPERAND_TYPE_IMM32_32S_DISP32
10522 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10523 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10524 #undef OPERAND_TYPE_IMM64_DISP64
10530 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10535 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10536 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10539 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10541 int len
= gotrel
[j
].len
;
10542 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10544 if (gotrel
[j
].rel
[object_64bit
] != 0)
10547 char *tmpbuf
, *past_reloc
;
10549 *rel
= gotrel
[j
].rel
[object_64bit
];
10553 if (flag_code
!= CODE_64BIT
)
10555 types
->bitfield
.imm32
= 1;
10556 types
->bitfield
.disp32
= 1;
10559 *types
= gotrel
[j
].types64
;
10562 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10563 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10565 /* The length of the first part of our input line. */
10566 first
= cp
- input_line_pointer
;
10568 /* The second part goes from after the reloc token until
10569 (and including) an end_of_line char or comma. */
10570 past_reloc
= cp
+ 1 + len
;
10572 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10574 second
= cp
+ 1 - past_reloc
;
10576 /* Allocate and copy string. The trailing NUL shouldn't
10577 be necessary, but be safe. */
10578 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10579 memcpy (tmpbuf
, input_line_pointer
, first
);
10580 if (second
!= 0 && *past_reloc
!= ' ')
10581 /* Replace the relocation token with ' ', so that
10582 errors like foo@GOTOFF1 will be detected. */
10583 tmpbuf
[first
++] = ' ';
10585 /* Increment length by 1 if the relocation token is
10590 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10591 tmpbuf
[first
+ second
] = '\0';
10595 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10596 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10601 /* Might be a symbol version string. Don't as_bad here. */
10606 bfd_reloc_code_real_type
10607 x86_cons (expressionS
*exp
, int size
)
10609 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10611 intel_syntax
= -intel_syntax
;
10613 expr_mode
= expr_operator_none
;
10615 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10616 && !defined (LEX_AT)) \
10618 if (size
== 4 || (object_64bit
&& size
== 8))
10620 /* Handle @GOTOFF and the like in an expression. */
10622 char *gotfree_input_line
;
10625 save
= input_line_pointer
;
10626 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10627 if (gotfree_input_line
)
10628 input_line_pointer
= gotfree_input_line
;
10632 if (gotfree_input_line
)
10634 /* expression () has merrily parsed up to the end of line,
10635 or a comma - in the wrong buffer. Transfer how far
10636 input_line_pointer has moved to the right buffer. */
10637 input_line_pointer
= (save
10638 + (input_line_pointer
- gotfree_input_line
)
10640 free (gotfree_input_line
);
10641 if (exp
->X_op
== O_constant
10642 || exp
->X_op
== O_absent
10643 || exp
->X_op
== O_illegal
10644 || exp
->X_op
== O_register
10645 || exp
->X_op
== O_big
)
10647 char c
= *input_line_pointer
;
10648 *input_line_pointer
= 0;
10649 as_bad (_("missing or invalid expression `%s'"), save
);
10650 *input_line_pointer
= c
;
10652 else if ((got_reloc
== BFD_RELOC_386_PLT32
10653 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10654 && exp
->X_op
!= O_symbol
)
10656 char c
= *input_line_pointer
;
10657 *input_line_pointer
= 0;
10658 as_bad (_("invalid PLT expression `%s'"), save
);
10659 *input_line_pointer
= c
;
10667 intel_syntax
= -intel_syntax
;
10670 i386_intel_simplify (exp
);
10672 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10673 if (size
<= 4 && expr_mode
== expr_operator_present
10674 && exp
->X_op
== O_constant
&& !object_64bit
)
10675 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10681 signed_cons (int size
)
10690 s_insn (int dummy ATTRIBUTE_UNUSED
)
10692 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10693 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10697 bool vex
= false, xop
= false, evex
= false;
10698 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10702 saved_char
= *saved_ilp
;
10705 end
= parse_insn (line
, mnemonic
, true);
10709 *saved_ilp
= saved_char
;
10710 ignore_rest_of_line ();
10714 line
+= end
- line
;
10716 current_templates
= &tt
;
10717 i
.tm
.mnem_off
= MN__insn
;
10718 i
.tm
.extension_opcode
= None
;
10720 if (startswith (line
, "VEX")
10721 && (line
[3] == '.' || is_space_char (line
[3])))
10726 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10729 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10731 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10732 && (*e
== '.' || is_space_char (*e
)))
10735 /* Arrange for build_vex_prefix() to emit 0x8f. */
10736 i
.tm
.opcode_space
= SPACE_XOP08
;
10737 i
.insn_opcode_space
= n
;
10741 else if (startswith (line
, "EVEX")
10742 && (line
[4] == '.' || is_space_char (line
[4])))
10749 ? i
.vec_encoding
== vex_encoding_evex
10751 ? i
.vec_encoding
== vex_encoding_vex
10752 || i
.vec_encoding
== vex_encoding_vex3
10753 : i
.vec_encoding
!= vex_encoding_default
)
10755 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10759 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10760 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10762 if (line
> end
&& *line
== '.')
10764 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
10772 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10774 i
.tm
.opcode_modifier
.vex
= VEX128
;
10779 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10781 i
.tm
.opcode_modifier
.vex
= VEX256
;
10786 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10791 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
10795 if (line
[3] == 'G')
10798 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10800 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10806 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
10811 if (line
[2] == '2' && line
[3] == '8')
10814 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10816 i
.tm
.opcode_modifier
.vex
= VEX128
;
10822 if (line
[2] == '5' && line
[3] == '6')
10825 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10827 i
.tm
.opcode_modifier
.vex
= VEX256
;
10833 if (evex
&& line
[2] == '1' && line
[3] == '2')
10835 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10842 if (line
> end
&& *line
== '.')
10844 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
10848 if (line
[2] == 'P')
10853 if (line
[2] == '6')
10855 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
10860 case 'F': case 'f':
10861 if (line
[2] == '3')
10863 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
10866 else if (line
[2] == '2')
10868 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
10875 if (line
> end
&& !xop
&& *line
== '.')
10877 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
10881 if (TOUPPER (line
[2]) != 'F')
10883 if (line
[3] == '.' || is_space_char (line
[3]))
10885 i
.insn_opcode_space
= SPACE_0F
;
10888 else if (line
[3] == '3'
10889 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
10890 && (line
[5] == '.' || is_space_char (line
[5])))
10892 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
10898 if (ISDIGIT (line
[2]) && line
[2] != '0')
10901 unsigned long n
= strtoul (line
+ 2, &e
, 10);
10903 if (n
<= (evex
? 15 : 31)
10904 && (*e
== '.' || is_space_char (*e
)))
10906 i
.insn_opcode_space
= n
;
10914 if (line
> end
&& *line
== '.' && line
[1] == 'W')
10916 /* VEX.W, XOP.W, EVEX.W */
10920 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
10924 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
10928 if (line
[3] == 'G')
10930 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
10936 if (i
.tm
.opcode_modifier
.vexw
)
10940 if (line
> end
&& *line
&& !is_space_char (*line
))
10942 /* Improve diagnostic a little. */
10943 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
10948 /* Before processing the opcode expression, find trailing "+r" or
10949 "/<digit>" specifiers. */
10950 for (ptr
= line
; ; ++ptr
)
10955 ptr
= strpbrk (ptr
, "+/,");
10956 if (ptr
== NULL
|| *ptr
== ',')
10959 if (*ptr
== '+' && ptr
[1] == 'r'
10960 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
10964 i
.short_form
= true;
10968 if (*ptr
== '/' && ISDIGIT (ptr
[1])
10969 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
10971 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
10975 i
.tm
.extension_opcode
= n
;
10976 i
.tm
.opcode_modifier
.modrm
= 1;
10981 input_line_pointer
= line
;
10982 val
= get_absolute_expression ();
10983 line
= input_line_pointer
;
10985 if (i
.short_form
&& (val
& 7))
10986 as_warn ("`+r' assumes low three opcode bits to be clear");
10988 for (j
= 1; j
< sizeof(val
); ++j
)
10989 if (!(val
>> (j
* 8)))
10992 /* Trim off a prefix if present. */
10993 if (j
> 1 && !vex
&& !xop
&& !evex
)
10995 uint8_t byte
= val
>> ((j
- 1) * 8);
10999 case DATA_PREFIX_OPCODE
:
11000 case REPE_PREFIX_OPCODE
:
11001 case REPNE_PREFIX_OPCODE
:
11002 if (!add_prefix (byte
))
11004 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11009 /* Trim off encoding space. */
11010 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11012 uint8_t byte
= val
>> ((--j
- 1) * 8);
11014 i
.insn_opcode_space
= SPACE_0F
;
11015 switch (byte
& -(j
> 1))
11018 i
.insn_opcode_space
= SPACE_0F38
;
11022 i
.insn_opcode_space
= SPACE_0F3A
;
11026 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11027 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11029 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11030 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11031 Also avoid hitting abort() there or in build_evex_prefix(). */
11032 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11037 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11040 i
.opcode_length
= j
;
11042 /* Handle operands, if any. */
11045 i386_operand_type combined
;
11046 expressionS
*disp_exp
= NULL
;
11051 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11059 as_bad (_("expecting operand after ','; got nothing"));
11063 if (i
.mem_operands
> 1)
11065 as_bad (_("too many memory references for `%s'"),
11066 &i386_mnemonics
[MN__insn
]);
11070 /* Are we to emit ModR/M encoding? */
11073 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11074 || i
.tm
.extension_opcode
!= None
))
11075 i
.tm
.opcode_modifier
.modrm
= 1;
11077 if (!i
.tm
.opcode_modifier
.modrm
11079 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11080 || i
.mem_operands
))
11082 as_bad (_("too many register/memory operands"));
11086 /* Enforce certain constraints on operands. */
11087 switch (i
.reg_operands
+ i
.mem_operands
11088 + (i
.tm
.extension_opcode
!= None
))
11093 as_bad (_("too few register/memory operands"));
11096 /* Fall through. */
11098 if (i
.tm
.opcode_modifier
.modrm
)
11100 as_bad (_("too few register/memory operands"));
11110 && (i
.op
[0].imms
->X_op
!= O_constant
11111 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11113 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11116 /* Fall through. */
11118 if (i
.vec_encoding
!= vex_encoding_default
)
11120 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11123 /* Fall through. */
11125 as_bad (_("too many register/memory operands"));
11129 /* Bring operands into canonical order (imm, mem, reg). */
11134 for (j
= 1; j
< i
.operands
; ++j
)
11136 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11137 && operand_type_check (i
.types
[j
], imm
))
11138 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11139 && i
.types
[j
].bitfield
.class == ClassNone
))
11141 swap_2_operands (j
- 1, j
);
11148 /* For Intel syntax swap the order of register operands. */
11150 switch (i
.reg_operands
)
11157 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11158 /* Fall through. */
11161 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11168 /* Enforce constraints when using VSIB. */
11170 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11171 || i
.index_reg
->reg_type
.bitfield
.ymmword
11172 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11174 if (i
.vec_encoding
== vex_encoding_default
)
11176 as_bad (_("VSIB unavailable with legacy encoding"));
11180 if (i
.vec_encoding
== vex_encoding_evex
11181 && i
.reg_operands
> 1)
11183 /* We could allow two register operands, encoding the 2nd one in
11184 an 8-bit immediate like for 4-register-operand insns, but that
11185 would require ugly fiddling with process_operands() and/or
11186 build_modrm_byte(). */
11187 as_bad (_("too many register operands with VSIB"));
11191 i
.tm
.opcode_modifier
.sib
= 1;
11194 /* Establish operand size encoding. */
11195 operand_type_set (&combined
, 0);
11197 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11199 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11201 if (operand_type_check (i
.types
[j
], disp
))
11203 i
.types
[j
].bitfield
.baseindex
= 1;
11204 disp_exp
= i
.op
[j
].disps
;
11207 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11209 unsigned int n
= i
.memshift
;
11211 if (i
.types
[j
].bitfield
.byte
)
11213 else if (i
.types
[j
].bitfield
.word
)
11215 else if (i
.types
[j
].bitfield
.dword
)
11217 else if (i
.types
[j
].bitfield
.qword
)
11219 else if (i
.types
[j
].bitfield
.xmmword
)
11221 else if (i
.types
[j
].bitfield
.ymmword
)
11223 else if (i
.types
[j
].bitfield
.zmmword
)
11226 if (i
.memshift
< 32 && n
!= i
.memshift
)
11227 as_warn ("conflicting memory operand size specifiers");
11231 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11232 && j
== i
.broadcast
.operand
)
11235 combined
= operand_type_or (combined
, i
.types
[j
]);
11236 combined
.bitfield
.class = ClassNone
;
11239 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11240 << (i
.memshift
< 32 ? i
.memshift
: 0))
11242 case 64: combined
.bitfield
.zmmword
= 1; break;
11243 case 32: combined
.bitfield
.ymmword
= 1; break;
11244 case 16: combined
.bitfield
.xmmword
= 1; break;
11245 case 8: combined
.bitfield
.qword
= 1; break;
11246 case 4: combined
.bitfield
.dword
= 1; break;
11249 if (i
.vec_encoding
== vex_encoding_default
)
11251 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11253 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11254 : combined
.bitfield
.word
)
11255 && !add_prefix (DATA_PREFIX_OPCODE
))
11258 else if (!i
.tm
.opcode_modifier
.vexw
)
11260 if (flag_code
== CODE_64BIT
)
11262 if (combined
.bitfield
.qword
)
11263 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11264 else if (combined
.bitfield
.dword
)
11265 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11268 if (!i
.tm
.opcode_modifier
.vexw
)
11269 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11274 if (!i
.tm
.opcode_modifier
.vex
)
11276 if (combined
.bitfield
.ymmword
)
11277 i
.tm
.opcode_modifier
.vex
= VEX256
;
11278 else if (combined
.bitfield
.xmmword
)
11279 i
.tm
.opcode_modifier
.vex
= VEX128
;
11284 if (!i
.tm
.opcode_modifier
.evex
)
11286 /* Do _not_ consider AVX512VL here. */
11287 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11288 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11289 else if (combined
.bitfield
.ymmword
)
11290 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11291 else if (combined
.bitfield
.xmmword
)
11292 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11295 if (i
.memshift
>= 32)
11297 unsigned int n
= 0;
11299 switch (i
.tm
.opcode_modifier
.evex
)
11301 case EVEX512
: n
= 64; break;
11302 case EVEX256
: n
= 32; break;
11303 case EVEX128
: n
= 16; break;
11306 if (i
.broadcast
.type
)
11307 n
/= i
.broadcast
.type
;
11310 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11312 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11313 && disp_exp
->X_add_number
!= 0
11314 && i
.disp_encoding
!= disp_encoding_32bit
)
11316 if (!quiet_warnings
)
11317 as_warn ("cannot determine memory operand size");
11318 i
.disp_encoding
= disp_encoding_32bit
;
11323 if (i
.memshift
>= 32)
11326 i
.vec_encoding
= vex_encoding_error
;
11328 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11331 /* Establish size for immediate operands. */
11332 for (j
= 0; j
< i
.imm_operands
; ++j
)
11334 expressionS
*expP
= i
.op
[j
].imms
;
11336 gas_assert (operand_type_check (i
.types
[j
], imm
));
11337 operand_type_set (&i
.types
[j
], 0);
11339 if (i
.imm_bits
[j
] > 32)
11340 i
.types
[j
].bitfield
.imm64
= 1;
11341 else if (i
.imm_bits
[j
] > 16)
11343 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11344 i
.types
[j
].bitfield
.imm32s
= 1;
11346 i
.types
[j
].bitfield
.imm32
= 1;
11348 else if (i
.imm_bits
[j
] > 8)
11349 i
.types
[j
].bitfield
.imm16
= 1;
11350 else if (i
.imm_bits
[j
] > 0)
11352 if (i
.flags
[j
] & Operand_Signed
)
11353 i
.types
[j
].bitfield
.imm8s
= 1;
11355 i
.types
[j
].bitfield
.imm8
= 1;
11357 else if (expP
->X_op
== O_constant
)
11359 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11360 i
.types
[j
].bitfield
.imm1
= 0;
11361 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11362 zapping since smallest_imm_type() sets it unconditionally. */
11363 if (flag_code
!= CODE_64BIT
)
11365 i
.types
[j
].bitfield
.imm64
= 0;
11366 i
.types
[j
].bitfield
.imm32s
= 0;
11367 i
.types
[j
].bitfield
.imm32
= 1;
11369 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11370 i
.types
[j
].bitfield
.imm64
= 0;
11373 /* Non-constant expressions are sized heuristically. */
11376 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11377 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11378 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11382 for (j
= 0; j
< i
.operands
; ++j
)
11383 i
.tm
.operand_types
[j
] = i
.types
[j
];
11385 process_operands ();
11388 /* Don't set opcode until after processing operands, to avoid any
11389 potential special casing there. */
11390 i
.tm
.base_opcode
|= val
;
11392 if (i
.vec_encoding
== vex_encoding_error
11393 || (i
.vec_encoding
!= vex_encoding_evex
11394 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11395 || i
.rounding
.type
!= rc_none
11397 : (i
.broadcast
.type
|| i
.broadcast
.bytes
)
11398 && i
.rounding
.type
!= rc_none
))
11400 as_bad (_("conflicting .insn operands"));
11406 if (!i
.tm
.opcode_modifier
.vex
)
11407 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11409 build_vex_prefix (NULL
);
11410 i
.rex
&= REX_OPCODE
;
11414 if (!i
.tm
.opcode_modifier
.evex
)
11415 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11417 build_evex_prefix ();
11418 i
.rex
&= REX_OPCODE
;
11420 else if (i
.rex
!= 0)
11421 add_prefix (REX_OPCODE
| i
.rex
);
11426 *saved_ilp
= saved_char
;
11427 input_line_pointer
= line
;
11429 demand_empty_rest_of_line ();
11431 /* Make sure dot_insn() won't yield "true" anymore. */
11437 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11444 if (exp
.X_op
== O_symbol
)
11445 exp
.X_op
= O_secrel
;
11447 emit_expr (&exp
, 4);
11449 while (*input_line_pointer
++ == ',');
11451 input_line_pointer
--;
11452 demand_empty_rest_of_line ();
11456 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11463 if (exp
.X_op
== O_symbol
)
11464 exp
.X_op
= O_secidx
;
11466 emit_expr (&exp
, 2);
11468 while (*input_line_pointer
++ == ',');
11470 input_line_pointer
--;
11471 demand_empty_rest_of_line ();
11475 /* Handle Rounding Control / SAE specifiers. */
11478 RC_SAE_specifier (const char *pstr
)
11482 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11484 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11486 if (i
.rounding
.type
!= rc_none
)
11488 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11492 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11494 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11501 /* Handle Vector operations. */
11504 check_VecOperations (char *op_string
)
11506 const reg_entry
*mask
;
11513 if (*op_string
== '{')
11517 /* Check broadcasts. */
11518 if (startswith (op_string
, "1to"))
11520 unsigned int bcst_type
;
11522 if (i
.broadcast
.type
)
11523 goto duplicated_vec_op
;
11526 if (*op_string
== '8')
11528 else if (*op_string
== '4')
11530 else if (*op_string
== '2')
11532 else if (*op_string
== '1'
11533 && *(op_string
+1) == '6')
11538 else if (*op_string
== '3'
11539 && *(op_string
+1) == '2')
11546 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11551 i
.broadcast
.type
= bcst_type
;
11552 i
.broadcast
.operand
= this_operand
;
11554 /* For .insn a data size specifier may be appended. */
11555 if (dot_insn () && *op_string
== ':')
11556 goto dot_insn_modifier
;
11558 /* Check .insn special cases. */
11559 else if (dot_insn () && *op_string
== ':')
11562 switch (op_string
[1])
11567 if (i
.memshift
< 32)
11568 goto duplicated_vec_op
;
11570 n
= strtoul (op_string
+ 2, &end_op
, 0);
11572 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11574 if (i
.memshift
< 32 && n
== 1)
11575 op_string
= end_op
;
11578 case 's': case 'u':
11579 /* This isn't really a "vector" operation, but a sign/size
11580 specifier for immediate operands of .insn. Note that AT&T
11581 syntax handles the same in i386_immediate(). */
11585 if (i
.imm_bits
[this_operand
])
11586 goto duplicated_vec_op
;
11588 n
= strtoul (op_string
+ 2, &end_op
, 0);
11589 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11591 i
.imm_bits
[this_operand
] = n
;
11592 if (op_string
[1] == 's')
11593 i
.flags
[this_operand
] |= Operand_Signed
;
11594 op_string
= end_op
;
11599 /* Check masking operation. */
11600 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11602 if (mask
== &bad_reg
)
11605 /* k0 can't be used for write mask. */
11606 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11608 as_bad (_("`%s%s' can't be used for write mask"),
11609 register_prefix
, mask
->reg_name
);
11616 i
.mask
.operand
= this_operand
;
11618 else if (i
.mask
.reg
->reg_num
)
11619 goto duplicated_vec_op
;
11624 /* Only "{z}" is allowed here. No need to check
11625 zeroing mask explicitly. */
11626 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11628 as_bad (_("invalid write mask `%s'"), saved
);
11633 op_string
= end_op
;
11635 /* Check zeroing-flag for masking operation. */
11636 else if (*op_string
== 'z')
11640 i
.mask
.reg
= reg_k0
;
11641 i
.mask
.zeroing
= 1;
11642 i
.mask
.operand
= this_operand
;
11646 if (i
.mask
.zeroing
)
11649 as_bad (_("duplicated `%s'"), saved
);
11653 i
.mask
.zeroing
= 1;
11655 /* Only "{%k}" is allowed here. No need to check mask
11656 register explicitly. */
11657 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11659 as_bad (_("invalid zeroing-masking `%s'"),
11667 else if (intel_syntax
11668 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11669 i
.rounding
.modifier
= true;
11671 goto unknown_vec_op
;
11673 if (*op_string
!= '}')
11675 as_bad (_("missing `}' in `%s'"), saved
);
11680 /* Strip whitespace since the addition of pseudo prefixes
11681 changed how the scrubber treats '{'. */
11682 if (is_space_char (*op_string
))
11688 /* We don't know this one. */
11689 as_bad (_("unknown vector operation: `%s'"), saved
);
11693 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11695 as_bad (_("zeroing-masking only allowed with write mask"));
11703 i386_immediate (char *imm_start
)
11705 char *save_input_line_pointer
;
11706 char *gotfree_input_line
;
11709 i386_operand_type types
;
11711 operand_type_set (&types
, ~0);
11713 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11715 as_bad (_("at most %d immediate operands are allowed"),
11716 MAX_IMMEDIATE_OPERANDS
);
11720 exp
= &im_expressions
[i
.imm_operands
++];
11721 i
.op
[this_operand
].imms
= exp
;
11723 if (is_space_char (*imm_start
))
11726 save_input_line_pointer
= input_line_pointer
;
11727 input_line_pointer
= imm_start
;
11729 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11730 if (gotfree_input_line
)
11731 input_line_pointer
= gotfree_input_line
;
11733 expr_mode
= expr_operator_none
;
11734 exp_seg
= expression (exp
);
11736 /* For .insn immediates there may be a size specifier. */
11737 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11738 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11741 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11743 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11745 i
.imm_bits
[this_operand
] = n
;
11746 if (input_line_pointer
[2] == 's')
11747 i
.flags
[this_operand
] |= Operand_Signed
;
11748 input_line_pointer
= e
+ 1;
11752 SKIP_WHITESPACE ();
11753 if (*input_line_pointer
)
11754 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11756 input_line_pointer
= save_input_line_pointer
;
11757 if (gotfree_input_line
)
11759 free (gotfree_input_line
);
11761 if (exp
->X_op
== O_constant
)
11762 exp
->X_op
= O_illegal
;
11765 if (exp_seg
== reg_section
)
11767 as_bad (_("illegal immediate register operand %s"), imm_start
);
11771 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
11775 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11776 i386_operand_type types
, const char *imm_start
)
11778 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
11781 as_bad (_("missing or invalid immediate expression `%s'"),
11785 else if (exp
->X_op
== O_constant
)
11787 /* Size it properly later. */
11788 i
.types
[this_operand
].bitfield
.imm64
= 1;
11790 /* If not 64bit, sign/zero extend val, to account for wraparound
11792 if (expr_mode
== expr_operator_present
11793 && flag_code
!= CODE_64BIT
&& !object_64bit
)
11794 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11796 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11797 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11798 && exp_seg
!= absolute_section
11799 && exp_seg
!= text_section
11800 && exp_seg
!= data_section
11801 && exp_seg
!= bss_section
11802 && exp_seg
!= undefined_section
11803 && !bfd_is_com_section (exp_seg
))
11805 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11811 /* This is an address. The size of the address will be
11812 determined later, depending on destination register,
11813 suffix, or the default for the section. */
11814 i
.types
[this_operand
].bitfield
.imm8
= 1;
11815 i
.types
[this_operand
].bitfield
.imm16
= 1;
11816 i
.types
[this_operand
].bitfield
.imm32
= 1;
11817 i
.types
[this_operand
].bitfield
.imm32s
= 1;
11818 i
.types
[this_operand
].bitfield
.imm64
= 1;
11819 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11827 i386_scale (char *scale
)
11830 char *save
= input_line_pointer
;
11832 input_line_pointer
= scale
;
11833 val
= get_absolute_expression ();
11838 i
.log2_scale_factor
= 0;
11841 i
.log2_scale_factor
= 1;
11844 i
.log2_scale_factor
= 2;
11847 i
.log2_scale_factor
= 3;
11851 char sep
= *input_line_pointer
;
11853 *input_line_pointer
= '\0';
11854 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
11856 *input_line_pointer
= sep
;
11857 input_line_pointer
= save
;
11861 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
11863 as_warn (_("scale factor of %d without an index register"),
11864 1 << i
.log2_scale_factor
);
11865 i
.log2_scale_factor
= 0;
11867 scale
= input_line_pointer
;
11868 input_line_pointer
= save
;
11873 i386_displacement (char *disp_start
, char *disp_end
)
11877 char *save_input_line_pointer
;
11878 char *gotfree_input_line
;
11880 i386_operand_type bigdisp
, types
= anydisp
;
11883 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
11885 as_bad (_("at most %d displacement operands are allowed"),
11886 MAX_MEMORY_OPERANDS
);
11890 operand_type_set (&bigdisp
, 0);
11892 || i
.types
[this_operand
].bitfield
.baseindex
11893 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
11894 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
11896 i386_addressing_mode ();
11897 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
11898 if (flag_code
== CODE_64BIT
)
11900 bigdisp
.bitfield
.disp32
= 1;
11902 bigdisp
.bitfield
.disp64
= 1;
11904 else if ((flag_code
== CODE_16BIT
) ^ override
)
11905 bigdisp
.bitfield
.disp16
= 1;
11907 bigdisp
.bitfield
.disp32
= 1;
11911 /* For PC-relative branches, the width of the displacement may be
11912 dependent upon data size, but is never dependent upon address size.
11913 Also make sure to not unintentionally match against a non-PC-relative
11914 branch template. */
11915 static templates aux_templates
;
11916 const insn_template
*t
= current_templates
->start
;
11917 bool has_intel64
= false;
11919 aux_templates
.start
= t
;
11920 while (++t
< current_templates
->end
)
11922 if (t
->opcode_modifier
.jump
11923 != current_templates
->start
->opcode_modifier
.jump
)
11925 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
11926 has_intel64
= true;
11928 if (t
< current_templates
->end
)
11930 aux_templates
.end
= t
;
11931 current_templates
= &aux_templates
;
11934 override
= (i
.prefix
[DATA_PREFIX
] != 0);
11935 if (flag_code
== CODE_64BIT
)
11937 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
11938 && (!intel64
|| !has_intel64
))
11939 bigdisp
.bitfield
.disp16
= 1;
11941 bigdisp
.bitfield
.disp32
= 1;
11946 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
11948 : LONG_MNEM_SUFFIX
));
11949 bigdisp
.bitfield
.disp32
= 1;
11950 if ((flag_code
== CODE_16BIT
) ^ override
)
11952 bigdisp
.bitfield
.disp32
= 0;
11953 bigdisp
.bitfield
.disp16
= 1;
11957 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11960 exp
= &disp_expressions
[i
.disp_operands
];
11961 i
.op
[this_operand
].disps
= exp
;
11963 save_input_line_pointer
= input_line_pointer
;
11964 input_line_pointer
= disp_start
;
11965 END_STRING_AND_SAVE (disp_end
);
11967 #ifndef GCC_ASM_O_HACK
11968 #define GCC_ASM_O_HACK 0
11971 END_STRING_AND_SAVE (disp_end
+ 1);
11972 if (i
.types
[this_operand
].bitfield
.baseIndex
11973 && displacement_string_end
[-1] == '+')
11975 /* This hack is to avoid a warning when using the "o"
11976 constraint within gcc asm statements.
11979 #define _set_tssldt_desc(n,addr,limit,type) \
11980 __asm__ __volatile__ ( \
11981 "movw %w2,%0\n\t" \
11982 "movw %w1,2+%0\n\t" \
11983 "rorl $16,%1\n\t" \
11984 "movb %b1,4+%0\n\t" \
11985 "movb %4,5+%0\n\t" \
11986 "movb $0,6+%0\n\t" \
11987 "movb %h1,7+%0\n\t" \
11989 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
11991 This works great except that the output assembler ends
11992 up looking a bit weird if it turns out that there is
11993 no offset. You end up producing code that looks like:
12006 So here we provide the missing zero. */
12008 *displacement_string_end
= '0';
12011 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12012 if (gotfree_input_line
)
12013 input_line_pointer
= gotfree_input_line
;
12015 expr_mode
= expr_operator_none
;
12016 exp_seg
= expression (exp
);
12018 SKIP_WHITESPACE ();
12019 if (*input_line_pointer
)
12020 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12022 RESTORE_END_STRING (disp_end
+ 1);
12024 input_line_pointer
= save_input_line_pointer
;
12025 if (gotfree_input_line
)
12027 free (gotfree_input_line
);
12029 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12030 exp
->X_op
= O_illegal
;
12033 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12035 RESTORE_END_STRING (disp_end
);
12041 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12042 i386_operand_type types
, const char *disp_start
)
12046 /* We do this to make sure that the section symbol is in
12047 the symbol table. We will ultimately change the relocation
12048 to be relative to the beginning of the section. */
12049 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12050 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12051 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12053 if (exp
->X_op
!= O_symbol
)
12056 if (S_IS_LOCAL (exp
->X_add_symbol
)
12057 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12058 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12059 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12060 exp
->X_op
= O_subtract
;
12061 exp
->X_op_symbol
= GOT_symbol
;
12062 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12063 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12064 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12065 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12067 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12070 else if (exp
->X_op
== O_absent
12071 || exp
->X_op
== O_illegal
12072 || exp
->X_op
== O_big
)
12075 as_bad (_("missing or invalid displacement expression `%s'"),
12080 else if (exp
->X_op
== O_constant
)
12082 /* Sizing gets taken care of by optimize_disp().
12084 If not 64bit, sign/zero extend val, to account for wraparound
12086 if (expr_mode
== expr_operator_present
12087 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12088 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12091 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12092 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12093 && exp_seg
!= absolute_section
12094 && exp_seg
!= text_section
12095 && exp_seg
!= data_section
12096 && exp_seg
!= bss_section
12097 && exp_seg
!= undefined_section
12098 && !bfd_is_com_section (exp_seg
))
12100 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12105 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12106 i
.types
[this_operand
].bitfield
.disp8
= 1;
12108 /* Check if this is a displacement only operand. */
12109 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12110 i
.types
[this_operand
] =
12111 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12112 operand_type_and (i
.types
[this_operand
], types
));
12117 /* Return the active addressing mode, taking address override and
12118 registers forming the address into consideration. Update the
12119 address override prefix if necessary. */
12121 static enum flag_code
12122 i386_addressing_mode (void)
12124 enum flag_code addr_mode
;
12126 if (i
.prefix
[ADDR_PREFIX
])
12127 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12128 else if (flag_code
== CODE_16BIT
12129 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
12130 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12131 from md_assemble() by "is not a valid base/index expression"
12132 when there is a base and/or index. */
12133 && !i
.types
[this_operand
].bitfield
.baseindex
)
12135 /* MPX insn memory operands with neither base nor index must be forced
12136 to use 32-bit addressing in 16-bit mode. */
12137 addr_mode
= CODE_32BIT
;
12138 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12140 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12141 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12145 addr_mode
= flag_code
;
12147 #if INFER_ADDR_PREFIX
12148 if (i
.mem_operands
== 0)
12150 /* Infer address prefix from the first memory operand. */
12151 const reg_entry
*addr_reg
= i
.base_reg
;
12153 if (addr_reg
== NULL
)
12154 addr_reg
= i
.index_reg
;
12158 if (addr_reg
->reg_type
.bitfield
.dword
)
12159 addr_mode
= CODE_32BIT
;
12160 else if (flag_code
!= CODE_64BIT
12161 && addr_reg
->reg_type
.bitfield
.word
)
12162 addr_mode
= CODE_16BIT
;
12164 if (addr_mode
!= flag_code
)
12166 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12168 /* Change the size of any displacement too. At most one
12169 of Disp16 or Disp32 is set.
12170 FIXME. There doesn't seem to be any real need for
12171 separate Disp16 and Disp32 flags. The same goes for
12172 Imm16 and Imm32. Removing them would probably clean
12173 up the code quite a lot. */
12174 if (flag_code
!= CODE_64BIT
12175 && (i
.types
[this_operand
].bitfield
.disp16
12176 || i
.types
[this_operand
].bitfield
.disp32
))
12178 static const i386_operand_type disp16_32
= {
12179 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12182 i
.types
[this_operand
]
12183 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12194 /* Make sure the memory operand we've been dealt is valid.
12195 Return 1 on success, 0 on a failure. */
12198 i386_index_check (const char *operand_string
)
12200 const char *kind
= "base/index";
12201 enum flag_code addr_mode
= i386_addressing_mode ();
12202 const insn_template
*t
= current_templates
->end
- 1;
12204 if (t
->opcode_modifier
.isstring
)
12206 /* Memory operands of string insns are special in that they only allow
12207 a single register (rDI, rSI, or rBX) as their memory address. */
12208 const reg_entry
*expected_reg
;
12209 static const char *di_si
[][2] =
12215 static const char *bx
[] = { "ebx", "bx", "rbx" };
12217 kind
= "string address";
12219 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12221 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12224 if (!t
->operand_types
[0].bitfield
.baseindex
12225 || ((!i
.mem_operands
!= !intel_syntax
)
12226 && t
->operand_types
[1].bitfield
.baseindex
))
12229 = (const reg_entry
*) str_hash_find (reg_hash
,
12230 di_si
[addr_mode
][op
== es_op
]);
12234 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12236 if (i
.base_reg
!= expected_reg
12238 || operand_type_check (i
.types
[this_operand
], disp
))
12240 /* The second memory operand must have the same size as
12244 && !((addr_mode
== CODE_64BIT
12245 && i
.base_reg
->reg_type
.bitfield
.qword
)
12246 || (addr_mode
== CODE_32BIT
12247 ? i
.base_reg
->reg_type
.bitfield
.dword
12248 : i
.base_reg
->reg_type
.bitfield
.word
)))
12251 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12253 intel_syntax
? '[' : '(',
12255 expected_reg
->reg_name
,
12256 intel_syntax
? ']' : ')');
12263 as_bad (_("`%s' is not a valid %s expression"),
12264 operand_string
, kind
);
12269 t
= current_templates
->start
;
12271 if (addr_mode
!= CODE_16BIT
)
12273 /* 32-bit/64-bit checks. */
12274 if (i
.disp_encoding
== disp_encoding_16bit
)
12277 as_bad (_("invalid `%s' prefix"),
12278 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12283 && ((addr_mode
== CODE_64BIT
12284 ? !i
.base_reg
->reg_type
.bitfield
.qword
12285 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12286 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12287 || i
.base_reg
->reg_num
== RegIZ
))
12289 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12290 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12291 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12292 && ((addr_mode
== CODE_64BIT
12293 ? !i
.index_reg
->reg_type
.bitfield
.qword
12294 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12295 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12298 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12299 if (t
->mnem_off
== MN_bndmk
12300 || t
->mnem_off
== MN_bndldx
12301 || t
->mnem_off
== MN_bndstx
12302 || t
->opcode_modifier
.sib
== SIBMEM
)
12304 /* They cannot use RIP-relative addressing. */
12305 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12307 as_bad (_("`%s' cannot be used here"), operand_string
);
12311 /* bndldx and bndstx ignore their scale factor. */
12312 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12313 && i
.log2_scale_factor
)
12314 as_warn (_("register scaling is being ignored here"));
12319 /* 16-bit checks. */
12320 if (i
.disp_encoding
== disp_encoding_32bit
)
12324 && (!i
.base_reg
->reg_type
.bitfield
.word
12325 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12327 && (!i
.index_reg
->reg_type
.bitfield
.word
12328 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12330 && i
.base_reg
->reg_num
< 6
12331 && i
.index_reg
->reg_num
>= 6
12332 && i
.log2_scale_factor
== 0))))
12339 /* Handle vector immediates. */
12342 RC_SAE_immediate (const char *imm_start
)
12344 const char *pstr
= imm_start
;
12349 pstr
= RC_SAE_specifier (pstr
+ 1);
12353 if (*pstr
++ != '}')
12355 as_bad (_("Missing '}': '%s'"), imm_start
);
12358 /* RC/SAE immediate string should contain nothing more. */;
12361 as_bad (_("Junk after '}': '%s'"), imm_start
);
12365 /* Internally this doesn't count as an operand. */
12371 static INLINE
bool starts_memory_operand (char c
)
12374 || is_name_beginner (c
)
12375 || strchr ("([\"+-!~", c
);
12378 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12382 i386_att_operand (char *operand_string
)
12384 const reg_entry
*r
;
12386 char *op_string
= operand_string
;
12388 if (is_space_char (*op_string
))
12391 /* We check for an absolute prefix (differentiating,
12392 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12393 if (*op_string
== ABSOLUTE_PREFIX
12394 && current_templates
->start
->opcode_modifier
.jump
)
12397 if (is_space_char (*op_string
))
12399 i
.jumpabsolute
= true;
12402 /* Check if operand is a register. */
12403 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12405 i386_operand_type temp
;
12410 /* Check for a segment override by searching for ':' after a
12411 segment register. */
12412 op_string
= end_op
;
12413 if (is_space_char (*op_string
))
12415 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12417 i
.seg
[i
.mem_operands
] = r
;
12419 /* Skip the ':' and whitespace. */
12421 if (is_space_char (*op_string
))
12424 /* Handle case of %es:*foo. */
12425 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12426 && current_templates
->start
->opcode_modifier
.jump
)
12429 if (is_space_char (*op_string
))
12431 i
.jumpabsolute
= true;
12434 if (!starts_memory_operand (*op_string
))
12436 as_bad (_("bad memory operand `%s'"), op_string
);
12439 goto do_memory_reference
;
12442 /* Handle vector operations. */
12443 if (*op_string
== '{')
12445 op_string
= check_VecOperations (op_string
);
12446 if (op_string
== NULL
)
12452 as_bad (_("junk `%s' after register"), op_string
);
12456 /* Reject pseudo registers for .insn. */
12457 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12459 as_bad (_("`%s%s' cannot be used here"),
12460 register_prefix
, r
->reg_name
);
12464 temp
= r
->reg_type
;
12465 temp
.bitfield
.baseindex
= 0;
12466 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12468 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12469 i
.op
[this_operand
].regs
= r
;
12472 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12473 operand was also present earlier on. */
12474 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12475 && i
.reg_operands
== 1)
12479 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12480 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12482 as_bad (_("`%s': misplaced `{%s}'"),
12483 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12487 else if (*op_string
== REGISTER_PREFIX
)
12489 as_bad (_("bad register name `%s'"), op_string
);
12492 else if (*op_string
== IMMEDIATE_PREFIX
)
12495 if (i
.jumpabsolute
)
12497 as_bad (_("immediate operand illegal with absolute jump"));
12500 if (!i386_immediate (op_string
))
12502 if (i
.rounding
.type
!= rc_none
)
12504 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12505 insn_name (current_templates
->start
));
12509 else if (RC_SAE_immediate (operand_string
))
12511 /* If it is a RC or SAE immediate, do the necessary placement check:
12512 Only another immediate or a GPR may precede it. */
12513 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12514 || (i
.reg_operands
== 1
12515 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12517 as_bad (_("`%s': misplaced `%s'"),
12518 insn_name (current_templates
->start
), operand_string
);
12522 else if (starts_memory_operand (*op_string
))
12524 /* This is a memory reference of some sort. */
12527 /* Start and end of displacement string expression (if found). */
12528 char *displacement_string_start
;
12529 char *displacement_string_end
;
12531 do_memory_reference
:
12532 /* Check for base index form. We detect the base index form by
12533 looking for an ')' at the end of the operand, searching
12534 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12536 base_string
= op_string
+ strlen (op_string
);
12538 /* Handle vector operations. */
12540 if (is_space_char (*base_string
))
12543 if (*base_string
== '}')
12545 char *vop_start
= NULL
;
12547 while (base_string
-- > op_string
)
12549 if (*base_string
== '"')
12551 if (*base_string
!= '{')
12554 vop_start
= base_string
;
12557 if (is_space_char (*base_string
))
12560 if (*base_string
!= '}')
12568 as_bad (_("unbalanced figure braces"));
12572 if (check_VecOperations (vop_start
) == NULL
)
12576 /* If we only have a displacement, set-up for it to be parsed later. */
12577 displacement_string_start
= op_string
;
12578 displacement_string_end
= base_string
+ 1;
12580 if (*base_string
== ')')
12583 unsigned int parens_not_balanced
= 0;
12584 bool in_quotes
= false;
12586 /* We've already checked that the number of left & right ()'s are
12587 equal, and that there's a matching set of double quotes. */
12588 end_op
= base_string
;
12589 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12591 if (*temp_string
== '\\' && temp_string
[1] == '"')
12593 else if (*temp_string
== '"')
12594 in_quotes
= !in_quotes
;
12595 else if (!in_quotes
)
12597 if (*temp_string
== '(' && !parens_not_balanced
++)
12598 base_string
= temp_string
;
12599 if (*temp_string
== ')')
12600 --parens_not_balanced
;
12604 temp_string
= base_string
;
12606 /* Skip past '(' and whitespace. */
12607 gas_assert (*base_string
== '(');
12609 if (is_space_char (*base_string
))
12612 if (*base_string
== ','
12613 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12616 displacement_string_end
= temp_string
;
12618 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12622 if (i
.base_reg
== &bad_reg
)
12624 base_string
= end_op
;
12625 if (is_space_char (*base_string
))
12629 /* There may be an index reg or scale factor here. */
12630 if (*base_string
== ',')
12633 if (is_space_char (*base_string
))
12636 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12639 if (i
.index_reg
== &bad_reg
)
12641 base_string
= end_op
;
12642 if (is_space_char (*base_string
))
12644 if (*base_string
== ',')
12647 if (is_space_char (*base_string
))
12650 else if (*base_string
!= ')')
12652 as_bad (_("expecting `,' or `)' "
12653 "after index register in `%s'"),
12658 else if (*base_string
== REGISTER_PREFIX
)
12660 end_op
= strchr (base_string
, ',');
12663 as_bad (_("bad register name `%s'"), base_string
);
12667 /* Check for scale factor. */
12668 if (*base_string
!= ')')
12670 char *end_scale
= i386_scale (base_string
);
12675 base_string
= end_scale
;
12676 if (is_space_char (*base_string
))
12678 if (*base_string
!= ')')
12680 as_bad (_("expecting `)' "
12681 "after scale factor in `%s'"),
12686 else if (!i
.index_reg
)
12688 as_bad (_("expecting index register or scale factor "
12689 "after `,'; got '%c'"),
12694 else if (*base_string
!= ')')
12696 as_bad (_("expecting `,' or `)' "
12697 "after base register in `%s'"),
12702 else if (*base_string
== REGISTER_PREFIX
)
12704 end_op
= strchr (base_string
, ',');
12707 as_bad (_("bad register name `%s'"), base_string
);
12712 /* If there's an expression beginning the operand, parse it,
12713 assuming displacement_string_start and
12714 displacement_string_end are meaningful. */
12715 if (displacement_string_start
!= displacement_string_end
)
12717 if (!i386_displacement (displacement_string_start
,
12718 displacement_string_end
))
12722 /* Special case for (%dx) while doing input/output op. */
12724 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12725 && i
.base_reg
->reg_type
.bitfield
.word
12726 && i
.index_reg
== 0
12727 && i
.log2_scale_factor
== 0
12728 && i
.seg
[i
.mem_operands
] == 0
12729 && !operand_type_check (i
.types
[this_operand
], disp
))
12731 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12732 i
.input_output_operand
= true;
12736 if (i386_index_check (operand_string
) == 0)
12738 i
.flags
[this_operand
] |= Operand_Mem
;
12743 /* It's not a memory operand; argh! */
12744 as_bad (_("invalid char %s beginning operand %d `%s'"),
12745 output_invalid (*op_string
),
12750 return 1; /* Normal return. */
12753 /* Calculate the maximum variable size (i.e., excluding fr_fix)
12754 that an rs_machine_dependent frag may reach. */
12757 i386_frag_max_var (fragS
*frag
)
12759 /* The only relaxable frags are for jumps.
12760 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
12761 gas_assert (frag
->fr_type
== rs_machine_dependent
);
12762 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
12765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12767 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
12769 /* STT_GNU_IFUNC symbol must go through PLT. */
12770 if ((symbol_get_bfdsym (fr_symbol
)->flags
12771 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
12774 if (!S_IS_EXTERNAL (fr_symbol
))
12775 /* Symbol may be weak or local. */
12776 return !S_IS_WEAK (fr_symbol
);
12778 /* Global symbols with non-default visibility can't be preempted. */
12779 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
12782 if (fr_var
!= NO_RELOC
)
12783 switch ((enum bfd_reloc_code_real
) fr_var
)
12785 case BFD_RELOC_386_PLT32
:
12786 case BFD_RELOC_X86_64_PLT32
:
12787 /* Symbol with PLT relocation may be preempted. */
12793 /* Global symbols with default visibility in a shared library may be
12794 preempted by another definition. */
12799 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
12800 Note also work for Skylake and Cascadelake.
12801 ---------------------------------------------------------------------
12802 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
12803 | ------ | ----------- | ------- | -------- |
12805 | Jno | N | N | Y |
12806 | Jc/Jb | Y | N | Y |
12807 | Jae/Jnb | Y | N | Y |
12808 | Je/Jz | Y | Y | Y |
12809 | Jne/Jnz | Y | Y | Y |
12810 | Jna/Jbe | Y | N | Y |
12811 | Ja/Jnbe | Y | N | Y |
12813 | Jns | N | N | Y |
12814 | Jp/Jpe | N | N | Y |
12815 | Jnp/Jpo | N | N | Y |
12816 | Jl/Jnge | Y | Y | Y |
12817 | Jge/Jnl | Y | Y | Y |
12818 | Jle/Jng | Y | Y | Y |
12819 | Jg/Jnle | Y | Y | Y |
12820 --------------------------------------------------------------------- */
12822 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
12824 if (mf_cmp
== mf_cmp_alu_cmp
)
12825 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
12826 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
12827 if (mf_cmp
== mf_cmp_incdec
)
12828 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
12829 || mf_jcc
== mf_jcc_jle
);
12830 if (mf_cmp
== mf_cmp_test_and
)
12835 /* Return the next non-empty frag. */
12838 i386_next_non_empty_frag (fragS
*fragP
)
12840 /* There may be a frag with a ".fill 0" when there is no room in
12841 the current frag for frag_grow in output_insn. */
12842 for (fragP
= fragP
->fr_next
;
12844 && fragP
->fr_type
== rs_fill
12845 && fragP
->fr_fix
== 0);
12846 fragP
= fragP
->fr_next
)
12851 /* Return the next jcc frag after BRANCH_PADDING. */
12854 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
12856 fragS
*branch_fragP
;
12860 if (pad_fragP
->fr_type
== rs_machine_dependent
12861 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
12862 == BRANCH_PADDING
))
12864 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
12865 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
12867 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
12868 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
12869 pad_fragP
->tc_frag_data
.mf_type
))
12870 return branch_fragP
;
12876 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
12879 i386_classify_machine_dependent_frag (fragS
*fragP
)
12883 fragS
*branch_fragP
;
12885 unsigned int max_prefix_length
;
12887 if (fragP
->tc_frag_data
.classified
)
12890 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
12891 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
12892 for (next_fragP
= fragP
;
12893 next_fragP
!= NULL
;
12894 next_fragP
= next_fragP
->fr_next
)
12896 next_fragP
->tc_frag_data
.classified
= 1;
12897 if (next_fragP
->fr_type
== rs_machine_dependent
)
12898 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
12900 case BRANCH_PADDING
:
12901 /* The BRANCH_PADDING frag must be followed by a branch
12903 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
12904 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12906 case FUSED_JCC_PADDING
:
12907 /* Check if this is a fused jcc:
12909 CMP like instruction
12913 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
12914 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
12915 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
12918 /* The BRANCH_PADDING frag is merged with the
12919 FUSED_JCC_PADDING frag. */
12920 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12921 /* CMP like instruction size. */
12922 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
12923 frag_wane (pad_fragP
);
12924 /* Skip to branch_fragP. */
12925 next_fragP
= branch_fragP
;
12927 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
12929 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
12931 next_fragP
->fr_subtype
12932 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
12933 next_fragP
->tc_frag_data
.max_bytes
12934 = next_fragP
->tc_frag_data
.max_prefix_length
;
12935 /* This will be updated in the BRANCH_PREFIX scan. */
12936 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
12939 frag_wane (next_fragP
);
12944 /* Stop if there is no BRANCH_PREFIX. */
12945 if (!align_branch_prefix_size
)
12948 /* Scan for BRANCH_PREFIX. */
12949 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
12951 if (fragP
->fr_type
!= rs_machine_dependent
12952 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12956 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
12957 COND_JUMP_PREFIX. */
12958 max_prefix_length
= 0;
12959 for (next_fragP
= fragP
;
12960 next_fragP
!= NULL
;
12961 next_fragP
= next_fragP
->fr_next
)
12963 if (next_fragP
->fr_type
== rs_fill
)
12964 /* Skip rs_fill frags. */
12966 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
12967 /* Stop for all other frags. */
12970 /* rs_machine_dependent frags. */
12971 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12974 /* Count BRANCH_PREFIX frags. */
12975 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
12977 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
12978 frag_wane (next_fragP
);
12982 += next_fragP
->tc_frag_data
.max_bytes
;
12984 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12986 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12987 == FUSED_JCC_PADDING
))
12989 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
12990 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
12994 /* Stop for other rs_machine_dependent frags. */
12998 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13000 /* Skip to the next frag. */
13001 fragP
= next_fragP
;
13005 /* Compute padding size for
13008 CMP like instruction
13010 COND_JUMP/UNCOND_JUMP
13015 COND_JUMP/UNCOND_JUMP
13019 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13021 unsigned int offset
, size
, padding_size
;
13022 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13024 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13026 address
= fragP
->fr_address
;
13027 address
+= fragP
->fr_fix
;
13029 /* CMP like instrunction size. */
13030 size
= fragP
->tc_frag_data
.cmp_size
;
13032 /* The base size of the branch frag. */
13033 size
+= branch_fragP
->fr_fix
;
13035 /* Add opcode and displacement bytes for the rs_machine_dependent
13037 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13038 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13040 /* Check if branch is within boundary and doesn't end at the last
13042 offset
= address
& ((1U << align_branch_power
) - 1);
13043 if ((offset
+ size
) >= (1U << align_branch_power
))
13044 /* Padding needed to avoid crossing boundary. */
13045 padding_size
= (1U << align_branch_power
) - offset
;
13047 /* No padding needed. */
13050 /* The return value may be saved in tc_frag_data.length which is
13052 if (!fits_in_unsigned_byte (padding_size
))
13055 return padding_size
;
13058 /* i386_generic_table_relax_frag()
13060 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13061 grow/shrink padding to align branch frags. Hand others to
13065 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13067 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13068 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13070 long padding_size
= i386_branch_padding_size (fragP
, 0);
13071 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13073 /* When the BRANCH_PREFIX frag is used, the computed address
13074 must match the actual address and there should be no padding. */
13075 if (fragP
->tc_frag_data
.padding_address
13076 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13080 /* Update the padding size. */
13082 fragP
->tc_frag_data
.length
= padding_size
;
13086 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13088 fragS
*padding_fragP
, *next_fragP
;
13089 long padding_size
, left_size
, last_size
;
13091 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13092 if (!padding_fragP
)
13093 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13094 return (fragP
->tc_frag_data
.length
13095 - fragP
->tc_frag_data
.last_length
);
13097 /* Compute the relative address of the padding frag in the very
13098 first time where the BRANCH_PREFIX frag sizes are zero. */
13099 if (!fragP
->tc_frag_data
.padding_address
)
13100 fragP
->tc_frag_data
.padding_address
13101 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13103 /* First update the last length from the previous interation. */
13104 left_size
= fragP
->tc_frag_data
.prefix_length
;
13105 for (next_fragP
= fragP
;
13106 next_fragP
!= padding_fragP
;
13107 next_fragP
= next_fragP
->fr_next
)
13108 if (next_fragP
->fr_type
== rs_machine_dependent
13109 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13114 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13118 if (max
> left_size
)
13123 next_fragP
->tc_frag_data
.last_length
= size
;
13127 next_fragP
->tc_frag_data
.last_length
= 0;
13130 /* Check the padding size for the padding frag. */
13131 padding_size
= i386_branch_padding_size
13132 (padding_fragP
, (fragP
->fr_address
13133 + fragP
->tc_frag_data
.padding_address
));
13135 last_size
= fragP
->tc_frag_data
.prefix_length
;
13136 /* Check if there is change from the last interation. */
13137 if (padding_size
== last_size
)
13139 /* Update the expected address of the padding frag. */
13140 padding_fragP
->tc_frag_data
.padding_address
13141 = (fragP
->fr_address
+ padding_size
13142 + fragP
->tc_frag_data
.padding_address
);
13146 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13148 /* No padding if there is no sufficient room. Clear the
13149 expected address of the padding frag. */
13150 padding_fragP
->tc_frag_data
.padding_address
= 0;
13154 /* Store the expected address of the padding frag. */
13155 padding_fragP
->tc_frag_data
.padding_address
13156 = (fragP
->fr_address
+ padding_size
13157 + fragP
->tc_frag_data
.padding_address
);
13159 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13161 /* Update the length for the current interation. */
13162 left_size
= padding_size
;
13163 for (next_fragP
= fragP
;
13164 next_fragP
!= padding_fragP
;
13165 next_fragP
= next_fragP
->fr_next
)
13166 if (next_fragP
->fr_type
== rs_machine_dependent
13167 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13172 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13176 if (max
> left_size
)
13181 next_fragP
->tc_frag_data
.length
= size
;
13185 next_fragP
->tc_frag_data
.length
= 0;
13188 return (fragP
->tc_frag_data
.length
13189 - fragP
->tc_frag_data
.last_length
);
13191 return relax_frag (segment
, fragP
, stretch
);
13194 /* md_estimate_size_before_relax()
13196 Called just before relax() for rs_machine_dependent frags. The x86
13197 assembler uses these frags to handle variable size jump
13200 Any symbol that is now undefined will not become defined.
13201 Return the correct fr_subtype in the frag.
13202 Return the initial "guess for variable size of frag" to caller.
13203 The guess is actually the growth beyond the fixed part. Whatever
13204 we do to grow the fixed or variable part contributes to our
13208 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13210 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13211 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13212 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13214 i386_classify_machine_dependent_frag (fragP
);
13215 return fragP
->tc_frag_data
.length
;
13218 /* We've already got fragP->fr_subtype right; all we have to do is
13219 check for un-relaxable symbols. On an ELF system, we can't relax
13220 an externally visible symbol, because it may be overridden by a
13222 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13225 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13228 #if defined (OBJ_COFF) && defined (TE_PE)
13229 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13230 && S_IS_WEAK (fragP
->fr_symbol
))
13234 /* Symbol is undefined in this segment, or we need to keep a
13235 reloc so that weak symbols can be overridden. */
13236 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13237 enum bfd_reloc_code_real reloc_type
;
13238 unsigned char *opcode
;
13242 if (fragP
->fr_var
!= NO_RELOC
)
13243 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13244 else if (size
== 2)
13245 reloc_type
= BFD_RELOC_16_PCREL
;
13246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13247 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13248 && need_plt32_p (fragP
->fr_symbol
))
13249 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13252 reloc_type
= BFD_RELOC_32_PCREL
;
13254 old_fr_fix
= fragP
->fr_fix
;
13255 opcode
= (unsigned char *) fragP
->fr_opcode
;
13257 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13260 /* Make jmp (0xeb) a (d)word displacement jump. */
13262 fragP
->fr_fix
+= size
;
13263 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13265 fragP
->fr_offset
, 1,
13271 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13273 /* Negate the condition, and branch past an
13274 unconditional jump. */
13277 /* Insert an unconditional jump. */
13279 /* We added two extra opcode bytes, and have a two byte
13281 fragP
->fr_fix
+= 2 + 2;
13282 fix_new (fragP
, old_fr_fix
+ 2, 2,
13284 fragP
->fr_offset
, 1,
13288 /* Fall through. */
13291 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13293 fragP
->fr_fix
+= 1;
13294 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13296 fragP
->fr_offset
, 1,
13297 BFD_RELOC_8_PCREL
);
13298 fixP
->fx_signed
= 1;
13302 /* This changes the byte-displacement jump 0x7N
13303 to the (d)word-displacement jump 0x0f,0x8N. */
13304 opcode
[1] = opcode
[0] + 0x10;
13305 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13306 /* We've added an opcode byte. */
13307 fragP
->fr_fix
+= 1 + size
;
13308 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13310 fragP
->fr_offset
, 1,
13315 BAD_CASE (fragP
->fr_subtype
);
13319 /* All jumps handled here are signed, but don't unconditionally use a
13320 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13321 around at 4G (outside of 64-bit mode) and 64k. */
13322 if (size
== 4 && flag_code
== CODE_64BIT
)
13323 fixP
->fx_signed
= 1;
13326 return fragP
->fr_fix
- old_fr_fix
;
13329 /* Guess size depending on current relax state. Initially the relax
13330 state will correspond to a short jump and we return 1, because
13331 the variable part of the frag (the branch offset) is one byte
13332 long. However, we can relax a section more than once and in that
13333 case we must either set fr_subtype back to the unrelaxed state,
13334 or return the value for the appropriate branch. */
13335 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13338 /* Called after relax() is finished.
13340 In: Address of frag.
13341 fr_type == rs_machine_dependent.
13342 fr_subtype is what the address relaxed to.
13344 Out: Any fixSs and constants are set up.
13345 Caller will turn frag into a ".space 0". */
13348 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13351 unsigned char *opcode
;
13352 unsigned char *where_to_put_displacement
= NULL
;
13353 offsetT target_address
;
13354 offsetT opcode_address
;
13355 unsigned int extension
= 0;
13356 offsetT displacement_from_opcode_start
;
13358 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13359 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13360 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13362 /* Generate nop padding. */
13363 unsigned int size
= fragP
->tc_frag_data
.length
;
13366 if (size
> fragP
->tc_frag_data
.max_bytes
)
13372 const char *branch
= "branch";
13373 const char *prefix
= "";
13374 fragS
*padding_fragP
;
13375 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13378 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13379 switch (fragP
->tc_frag_data
.default_prefix
)
13384 case CS_PREFIX_OPCODE
:
13387 case DS_PREFIX_OPCODE
:
13390 case ES_PREFIX_OPCODE
:
13393 case FS_PREFIX_OPCODE
:
13396 case GS_PREFIX_OPCODE
:
13399 case SS_PREFIX_OPCODE
:
13404 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13405 "%s within %d-byte boundary\n");
13407 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13408 "align %s within %d-byte boundary\n");
13412 padding_fragP
= fragP
;
13413 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13414 "%s within %d-byte boundary\n");
13418 switch (padding_fragP
->tc_frag_data
.branch_type
)
13420 case align_branch_jcc
:
13423 case align_branch_fused
:
13424 branch
= "fused jcc";
13426 case align_branch_jmp
:
13429 case align_branch_call
:
13432 case align_branch_indirect
:
13433 branch
= "indiret branch";
13435 case align_branch_ret
:
13442 fprintf (stdout
, msg
,
13443 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13444 (long long) fragP
->fr_address
, branch
,
13445 1 << align_branch_power
);
13447 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13448 memset (fragP
->fr_opcode
,
13449 fragP
->tc_frag_data
.default_prefix
, size
);
13451 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13453 fragP
->fr_fix
+= size
;
13458 opcode
= (unsigned char *) fragP
->fr_opcode
;
13460 /* Address we want to reach in file space. */
13461 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13463 /* Address opcode resides at in file space. */
13464 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13466 /* Displacement from opcode start to fill into instruction. */
13467 displacement_from_opcode_start
= target_address
- opcode_address
;
13469 if ((fragP
->fr_subtype
& BIG
) == 0)
13471 /* Don't have to change opcode. */
13472 extension
= 1; /* 1 opcode + 1 displacement */
13473 where_to_put_displacement
= &opcode
[1];
13477 if (no_cond_jump_promotion
13478 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13479 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13480 _("long jump required"));
13482 switch (fragP
->fr_subtype
)
13484 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13485 extension
= 4; /* 1 opcode + 4 displacement */
13487 where_to_put_displacement
= &opcode
[1];
13490 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13491 extension
= 2; /* 1 opcode + 2 displacement */
13493 where_to_put_displacement
= &opcode
[1];
13496 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13497 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13498 extension
= 5; /* 2 opcode + 4 displacement */
13499 opcode
[1] = opcode
[0] + 0x10;
13500 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13501 where_to_put_displacement
= &opcode
[2];
13504 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13505 extension
= 3; /* 2 opcode + 2 displacement */
13506 opcode
[1] = opcode
[0] + 0x10;
13507 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13508 where_to_put_displacement
= &opcode
[2];
13511 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13516 where_to_put_displacement
= &opcode
[3];
13520 BAD_CASE (fragP
->fr_subtype
);
13525 /* If size if less then four we are sure that the operand fits,
13526 but if it's 4, then it could be that the displacement is larger
13528 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13530 && ((addressT
) (displacement_from_opcode_start
- extension
13531 + ((addressT
) 1 << 31))
13532 > (((addressT
) 2 << 31) - 1)))
13534 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13535 _("jump target out of range"));
13536 /* Make us emit 0. */
13537 displacement_from_opcode_start
= extension
;
13539 /* Now put displacement after opcode. */
13540 md_number_to_chars ((char *) where_to_put_displacement
,
13541 (valueT
) (displacement_from_opcode_start
- extension
),
13542 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13543 fragP
->fr_fix
+= extension
;
13546 /* Apply a fixup (fixP) to segment data, once it has been determined
13547 by our caller that we have all the info we need to fix it up.
13549 Parameter valP is the pointer to the value of the bits.
13551 On the 386, immediates, displacements, and data pointers are all in
13552 the same (little-endian) format, so we don't need to care about which
13553 we are handling. */
13556 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13558 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13559 valueT value
= *valP
;
13561 #if !defined (TE_Mach)
13562 if (fixP
->fx_pcrel
)
13564 switch (fixP
->fx_r_type
)
13570 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13573 case BFD_RELOC_X86_64_32S
:
13574 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13577 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13580 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13585 if (fixP
->fx_addsy
!= NULL
13586 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13587 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13588 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13589 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13590 && !use_rela_relocations
)
13592 /* This is a hack. There should be a better way to handle this.
13593 This covers for the fact that bfd_install_relocation will
13594 subtract the current location (for partial_inplace, PC relative
13595 relocations); see more below. */
13599 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13602 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13607 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13609 if ((sym_seg
== seg
13610 || (symbol_section_p (fixP
->fx_addsy
)
13611 && sym_seg
!= absolute_section
))
13612 && !generic_force_reloc (fixP
))
13614 /* Yes, we add the values in twice. This is because
13615 bfd_install_relocation subtracts them out again. I think
13616 bfd_install_relocation is broken, but I don't dare change
13618 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13622 #if defined (OBJ_COFF) && defined (TE_PE)
13623 /* For some reason, the PE format does not store a
13624 section address offset for a PC relative symbol. */
13625 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13626 || S_IS_WEAK (fixP
->fx_addsy
))
13627 value
+= md_pcrel_from (fixP
);
13630 #if defined (OBJ_COFF) && defined (TE_PE)
13631 if (fixP
->fx_addsy
!= NULL
13632 && S_IS_WEAK (fixP
->fx_addsy
)
13633 /* PR 16858: Do not modify weak function references. */
13634 && ! fixP
->fx_pcrel
)
13636 #if !defined (TE_PEP)
13637 /* For x86 PE weak function symbols are neither PC-relative
13638 nor do they set S_IS_FUNCTION. So the only reliable way
13639 to detect them is to check the flags of their containing
13641 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13642 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13646 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13650 /* Fix a few things - the dynamic linker expects certain values here,
13651 and we must not disappoint it. */
13652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13653 if (IS_ELF
&& fixP
->fx_addsy
)
13654 switch (fixP
->fx_r_type
)
13656 case BFD_RELOC_386_PLT32
:
13657 case BFD_RELOC_X86_64_PLT32
:
13658 /* Make the jump instruction point to the address of the operand.
13659 At runtime we merely add the offset to the actual PLT entry.
13660 NB: Subtract the offset size only for jump instructions. */
13661 if (fixP
->fx_pcrel
)
13665 case BFD_RELOC_386_TLS_GD
:
13666 case BFD_RELOC_386_TLS_LDM
:
13667 case BFD_RELOC_386_TLS_IE_32
:
13668 case BFD_RELOC_386_TLS_IE
:
13669 case BFD_RELOC_386_TLS_GOTIE
:
13670 case BFD_RELOC_386_TLS_GOTDESC
:
13671 case BFD_RELOC_X86_64_TLSGD
:
13672 case BFD_RELOC_X86_64_TLSLD
:
13673 case BFD_RELOC_X86_64_GOTTPOFF
:
13674 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13675 value
= 0; /* Fully resolved at runtime. No addend. */
13677 case BFD_RELOC_386_TLS_LE
:
13678 case BFD_RELOC_386_TLS_LDO_32
:
13679 case BFD_RELOC_386_TLS_LE_32
:
13680 case BFD_RELOC_X86_64_DTPOFF32
:
13681 case BFD_RELOC_X86_64_DTPOFF64
:
13682 case BFD_RELOC_X86_64_TPOFF32
:
13683 case BFD_RELOC_X86_64_TPOFF64
:
13684 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13687 case BFD_RELOC_386_TLS_DESC_CALL
:
13688 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13689 value
= 0; /* Fully resolved at runtime. No addend. */
13690 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13694 case BFD_RELOC_VTABLE_INHERIT
:
13695 case BFD_RELOC_VTABLE_ENTRY
:
13702 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13704 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13706 value
= extend_to_32bit_address (value
);
13709 #endif /* !defined (TE_Mach) */
13711 /* Are we finished with this relocation now? */
13712 if (fixP
->fx_addsy
== NULL
)
13715 switch (fixP
->fx_r_type
)
13717 case BFD_RELOC_X86_64_32S
:
13718 fixP
->fx_signed
= 1;
13725 #if defined (OBJ_COFF) && defined (TE_PE)
13726 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13729 /* Remember value for tc_gen_reloc. */
13730 fixP
->fx_addnumber
= value
;
13731 /* Clear out the frag for now. */
13735 else if (use_rela_relocations
)
13737 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13738 fixP
->fx_no_overflow
= 1;
13739 /* Remember value for tc_gen_reloc. */
13740 fixP
->fx_addnumber
= value
;
13744 md_number_to_chars (p
, value
, fixP
->fx_size
);
13748 md_atof (int type
, char *litP
, int *sizeP
)
13750 /* This outputs the LITTLENUMs in REVERSE order;
13751 in accord with the bigendian 386. */
13752 return ieee_md_atof (type
, litP
, sizeP
, false);
13755 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
13758 output_invalid (int c
)
13761 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13764 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13765 "(0x%x)", (unsigned char) c
);
13766 return output_invalid_buf
;
13769 /* Verify that @r can be used in the current context. */
13771 static bool check_register (const reg_entry
*r
)
13773 if (allow_pseudo_reg
)
13776 if (operand_type_all_zero (&r
->reg_type
))
13779 if ((r
->reg_type
.bitfield
.dword
13780 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
13781 || r
->reg_type
.bitfield
.class == RegCR
13782 || r
->reg_type
.bitfield
.class == RegDR
)
13783 && !cpu_arch_flags
.bitfield
.cpui386
)
13786 if (r
->reg_type
.bitfield
.class == RegTR
13787 && (flag_code
== CODE_64BIT
13788 || !cpu_arch_flags
.bitfield
.cpui386
13789 || cpu_arch_isa_flags
.bitfield
.cpui586
13790 || cpu_arch_isa_flags
.bitfield
.cpui686
))
13793 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
13796 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
13798 if (r
->reg_type
.bitfield
.zmmword
13799 || r
->reg_type
.bitfield
.class == RegMask
)
13802 if (!cpu_arch_flags
.bitfield
.cpuavx
)
13804 if (r
->reg_type
.bitfield
.ymmword
)
13807 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
13812 if (r
->reg_type
.bitfield
.tmmword
13813 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
13814 || flag_code
!= CODE_64BIT
))
13817 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
13820 /* Don't allow fake index register unless allow_index_reg isn't 0. */
13821 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
13824 /* Upper 16 vector registers are only available with VREX in 64bit
13825 mode, and require EVEX encoding. */
13826 if (r
->reg_flags
& RegVRex
)
13828 if (!cpu_arch_flags
.bitfield
.cpuavx512f
13829 || flag_code
!= CODE_64BIT
)
13832 if (i
.vec_encoding
== vex_encoding_default
)
13833 i
.vec_encoding
= vex_encoding_evex
;
13834 else if (i
.vec_encoding
!= vex_encoding_evex
)
13835 i
.vec_encoding
= vex_encoding_error
;
13838 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
13839 && (!cpu_arch_flags
.bitfield
.cpulm
13840 || r
->reg_type
.bitfield
.class != RegCR
13842 && flag_code
!= CODE_64BIT
)
13845 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
13852 /* REG_STRING starts *before* REGISTER_PREFIX. */
13854 static const reg_entry
*
13855 parse_real_register (const char *reg_string
, char **end_op
)
13857 const char *s
= reg_string
;
13859 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
13860 const reg_entry
*r
;
13862 /* Skip possible REGISTER_PREFIX and possible whitespace. */
13863 if (*s
== REGISTER_PREFIX
)
13866 if (is_space_char (*s
))
13869 p
= reg_name_given
;
13870 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
13872 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
13873 return (const reg_entry
*) NULL
;
13877 if (is_part_of_name (*s
))
13878 return (const reg_entry
*) NULL
;
13880 *end_op
= (char *) s
;
13882 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
13884 /* Handle floating point regs, allowing spaces in the (i) part. */
13887 if (!cpu_arch_flags
.bitfield
.cpu8087
13888 && !cpu_arch_flags
.bitfield
.cpu287
13889 && !cpu_arch_flags
.bitfield
.cpu387
13890 && !allow_pseudo_reg
)
13891 return (const reg_entry
*) NULL
;
13893 if (is_space_char (*s
))
13898 if (is_space_char (*s
))
13900 if (*s
>= '0' && *s
<= '7')
13902 int fpr
= *s
- '0';
13904 if (is_space_char (*s
))
13908 *end_op
= (char *) s
+ 1;
13909 know (r
[fpr
].reg_num
== fpr
);
13913 /* We have "%st(" then garbage. */
13914 return (const reg_entry
*) NULL
;
13918 return r
&& check_register (r
) ? r
: NULL
;
13921 /* REG_STRING starts *before* REGISTER_PREFIX. */
13923 static const reg_entry
*
13924 parse_register (const char *reg_string
, char **end_op
)
13926 const reg_entry
*r
;
13928 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
13929 r
= parse_real_register (reg_string
, end_op
);
13934 char *save
= input_line_pointer
;
13935 char *buf
= xstrdup (reg_string
), *name
;
13938 input_line_pointer
= buf
;
13939 get_symbol_name (&name
);
13940 symbolP
= symbol_find (name
);
13941 while (symbolP
&& symbol_equated_p (symbolP
))
13943 const expressionS
*e
= symbol_get_value_expression(symbolP
);
13945 if (e
->X_add_number
)
13947 symbolP
= e
->X_add_symbol
;
13949 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
13951 const expressionS
*e
= symbol_get_value_expression (symbolP
);
13953 if (e
->X_op
== O_register
)
13955 know (e
->X_add_number
>= 0
13956 && (valueT
) e
->X_add_number
< i386_regtab_size
);
13957 r
= i386_regtab
+ e
->X_add_number
;
13958 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
13960 if (r
&& !check_register (r
))
13962 as_bad (_("register '%s%s' cannot be used here"),
13963 register_prefix
, r
->reg_name
);
13967 input_line_pointer
= save
;
13974 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
13976 const reg_entry
*r
= NULL
;
13977 char *end
= input_line_pointer
;
13979 /* We only know the terminating character here. It being double quote could
13980 be the closing one of a quoted symbol name, or an opening one from a
13981 following string (or another quoted symbol name). Since the latter can't
13982 be valid syntax for anything, bailing in either case is good enough. */
13983 if (*nextcharP
== '"')
13987 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
13988 r
= parse_real_register (name
, &input_line_pointer
);
13989 if (r
&& end
<= input_line_pointer
)
13991 *nextcharP
= *input_line_pointer
;
13992 *input_line_pointer
= 0;
13993 e
->X_op
= O_register
;
13994 e
->X_add_number
= r
- i386_regtab
;
13997 input_line_pointer
= end
;
13999 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14003 md_operand (expressionS
*e
)
14006 const reg_entry
*r
;
14008 switch (*input_line_pointer
)
14010 case REGISTER_PREFIX
:
14011 r
= parse_real_register (input_line_pointer
, &end
);
14014 e
->X_op
= O_register
;
14015 e
->X_add_number
= r
- i386_regtab
;
14016 input_line_pointer
= end
;
14021 gas_assert (intel_syntax
);
14022 end
= input_line_pointer
++;
14024 if (*input_line_pointer
== ']')
14026 ++input_line_pointer
;
14027 e
->X_op_symbol
= make_expr_symbol (e
);
14028 e
->X_add_symbol
= NULL
;
14029 e
->X_add_number
= 0;
14034 e
->X_op
= O_absent
;
14035 input_line_pointer
= end
;
14042 /* To maintain consistency with !BFD64 builds of gas record, whether any
14043 (binary) operator was involved in an expression. As expressions are
14044 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14045 truncate results. */
14046 bool i386_record_operator (operatorT op
,
14047 const expressionS
*left
,
14048 const expressionS
*right
)
14050 if (op
== O_absent
)
14055 /* Since the expression parser applies unary operators fine to bignum
14056 operands, we don't need to be concerned of respective operands not
14057 fitting in 32 bits. */
14058 if (right
->X_op
== O_constant
&& right
->X_unsigned
14059 && !fits_in_unsigned_long (right
->X_add_number
))
14062 /* This isn't entirely right: The pattern can also result when constant
14063 expressions are folded (e.g. 0xffffffff + 1). */
14064 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14065 && !fits_in_unsigned_long (left
->X_add_number
))
14066 || (right
->X_op
== O_constant
&& right
->X_unsigned
14067 && !fits_in_unsigned_long (right
->X_add_number
)))
14068 expr_mode
= expr_large_value
;
14070 if (expr_mode
!= expr_large_value
)
14071 expr_mode
= expr_operator_present
;
14077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14078 const char *md_shortopts
= "kVQ:sqnO::";
14080 const char *md_shortopts
= "qnO::";
14083 #define OPTION_32 (OPTION_MD_BASE + 0)
14084 #define OPTION_64 (OPTION_MD_BASE + 1)
14085 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14086 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14087 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14088 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14089 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14090 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14091 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14092 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14093 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14094 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14095 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14096 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14097 #define OPTION_X32 (OPTION_MD_BASE + 14)
14098 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14099 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14100 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14101 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14102 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14103 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14104 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14105 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14106 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14107 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14108 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14109 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14110 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14111 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14112 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14113 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14114 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14115 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14116 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14117 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14119 struct option md_longopts
[] =
14121 {"32", no_argument
, NULL
, OPTION_32
},
14122 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14123 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14124 {"64", no_argument
, NULL
, OPTION_64
},
14126 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14127 {"x32", no_argument
, NULL
, OPTION_X32
},
14128 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14129 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14131 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14132 {"march", required_argument
, NULL
, OPTION_MARCH
},
14133 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14134 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14135 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14136 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14137 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14138 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14139 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14140 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14141 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14142 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14143 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14144 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14145 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14146 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14147 # if defined (TE_PE) || defined (TE_PEP)
14148 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14150 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14151 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14152 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14153 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14154 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14155 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14156 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14157 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14158 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14159 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14160 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14161 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14162 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14163 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14164 {NULL
, no_argument
, NULL
, 0}
14166 size_t md_longopts_size
= sizeof (md_longopts
);
14169 md_parse_option (int c
, const char *arg
)
14172 char *arch
, *next
, *saved
, *type
;
14177 optimize_align_code
= 0;
14181 quiet_warnings
= 1;
14184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14185 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14186 should be emitted or not. FIXME: Not implemented. */
14188 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14192 /* -V: SVR4 argument to print version ID. */
14194 print_version_id ();
14197 /* -k: Ignore for FreeBSD compatibility. */
14202 /* -s: On i386 Solaris, this tells the native assembler to use
14203 .stab instead of .stab.excl. We always use .stab anyhow. */
14206 case OPTION_MSHARED
:
14210 case OPTION_X86_USED_NOTE
:
14211 if (strcasecmp (arg
, "yes") == 0)
14213 else if (strcasecmp (arg
, "no") == 0)
14216 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14221 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14222 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14225 const char **list
, **l
;
14227 list
= bfd_target_list ();
14228 for (l
= list
; *l
!= NULL
; l
++)
14229 if (startswith (*l
, "elf64-x86-64")
14230 || strcmp (*l
, "coff-x86-64") == 0
14231 || strcmp (*l
, "pe-x86-64") == 0
14232 || strcmp (*l
, "pei-x86-64") == 0
14233 || strcmp (*l
, "mach-o-x86-64") == 0)
14235 default_arch
= "x86_64";
14239 as_fatal (_("no compiled in support for x86_64"));
14245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14249 const char **list
, **l
;
14251 list
= bfd_target_list ();
14252 for (l
= list
; *l
!= NULL
; l
++)
14253 if (startswith (*l
, "elf32-x86-64"))
14255 default_arch
= "x86_64:32";
14259 as_fatal (_("no compiled in support for 32bit x86_64"));
14263 as_fatal (_("32bit x86_64 is only supported for ELF"));
14269 const char **list
, **l
;
14271 list
= bfd_target_list ();
14272 for (l
= list
; *l
!= NULL
; l
++)
14273 if (strstr (*l
, "-i386")
14274 || strstr (*l
, "-go32"))
14276 default_arch
= "i386";
14280 as_fatal (_("no compiled in support for ix86"));
14285 case OPTION_DIVIDE
:
14286 #ifdef SVR4_COMMENT_CHARS
14291 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14293 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14297 i386_comment_chars
= n
;
14303 saved
= xstrdup (arg
);
14305 /* Allow -march=+nosse. */
14311 as_fatal (_("invalid -march= option: `%s'"), arg
);
14312 next
= strchr (arch
, '+');
14315 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14317 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14318 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14321 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14324 cpu_arch_name
= cpu_arch
[j
].name
;
14325 free (cpu_sub_arch_name
);
14326 cpu_sub_arch_name
= NULL
;
14327 cpu_arch_flags
= cpu_arch
[j
].enable
;
14328 cpu_arch_isa
= cpu_arch
[j
].type
;
14329 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14330 if (!cpu_arch_tune_set
)
14332 cpu_arch_tune
= cpu_arch_isa
;
14333 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14337 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14338 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14339 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14341 /* ISA extension. */
14342 i386_cpu_flags flags
;
14344 flags
= cpu_flags_or (cpu_arch_flags
,
14345 cpu_arch
[j
].enable
);
14347 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14349 extend_cpu_sub_arch_name (arch
);
14350 cpu_arch_flags
= flags
;
14351 cpu_arch_isa_flags
= flags
;
14355 = cpu_flags_or (cpu_arch_isa_flags
,
14356 cpu_arch
[j
].enable
);
14361 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14363 /* Disable an ISA extension. */
14364 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14365 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14366 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14368 i386_cpu_flags flags
;
14370 flags
= cpu_flags_and_not (cpu_arch_flags
,
14371 cpu_arch
[j
].disable
);
14372 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14374 extend_cpu_sub_arch_name (arch
);
14375 cpu_arch_flags
= flags
;
14376 cpu_arch_isa_flags
= flags
;
14382 if (j
>= ARRAY_SIZE (cpu_arch
))
14383 as_fatal (_("invalid -march= option: `%s'"), arg
);
14387 while (next
!= NULL
);
14393 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14394 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14396 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14397 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14399 cpu_arch_tune_set
= 1;
14400 cpu_arch_tune
= cpu_arch
[j
].type
;
14401 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14405 if (j
>= ARRAY_SIZE (cpu_arch
))
14406 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14409 case OPTION_MMNEMONIC
:
14410 if (strcasecmp (arg
, "att") == 0)
14411 intel_mnemonic
= 0;
14412 else if (strcasecmp (arg
, "intel") == 0)
14413 intel_mnemonic
= 1;
14415 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14418 case OPTION_MSYNTAX
:
14419 if (strcasecmp (arg
, "att") == 0)
14421 else if (strcasecmp (arg
, "intel") == 0)
14424 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14427 case OPTION_MINDEX_REG
:
14428 allow_index_reg
= 1;
14431 case OPTION_MNAKED_REG
:
14432 allow_naked_reg
= 1;
14435 case OPTION_MSSE2AVX
:
14439 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14440 use_unaligned_vector_move
= 1;
14443 case OPTION_MSSE_CHECK
:
14444 if (strcasecmp (arg
, "error") == 0)
14445 sse_check
= check_error
;
14446 else if (strcasecmp (arg
, "warning") == 0)
14447 sse_check
= check_warning
;
14448 else if (strcasecmp (arg
, "none") == 0)
14449 sse_check
= check_none
;
14451 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14454 case OPTION_MOPERAND_CHECK
:
14455 if (strcasecmp (arg
, "error") == 0)
14456 operand_check
= check_error
;
14457 else if (strcasecmp (arg
, "warning") == 0)
14458 operand_check
= check_warning
;
14459 else if (strcasecmp (arg
, "none") == 0)
14460 operand_check
= check_none
;
14462 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14465 case OPTION_MAVXSCALAR
:
14466 if (strcasecmp (arg
, "128") == 0)
14467 avxscalar
= vex128
;
14468 else if (strcasecmp (arg
, "256") == 0)
14469 avxscalar
= vex256
;
14471 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14474 case OPTION_MVEXWIG
:
14475 if (strcmp (arg
, "0") == 0)
14477 else if (strcmp (arg
, "1") == 0)
14480 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14483 case OPTION_MADD_BND_PREFIX
:
14484 add_bnd_prefix
= 1;
14487 case OPTION_MEVEXLIG
:
14488 if (strcmp (arg
, "128") == 0)
14489 evexlig
= evexl128
;
14490 else if (strcmp (arg
, "256") == 0)
14491 evexlig
= evexl256
;
14492 else if (strcmp (arg
, "512") == 0)
14493 evexlig
= evexl512
;
14495 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14498 case OPTION_MEVEXRCIG
:
14499 if (strcmp (arg
, "rne") == 0)
14501 else if (strcmp (arg
, "rd") == 0)
14503 else if (strcmp (arg
, "ru") == 0)
14505 else if (strcmp (arg
, "rz") == 0)
14508 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14511 case OPTION_MEVEXWIG
:
14512 if (strcmp (arg
, "0") == 0)
14514 else if (strcmp (arg
, "1") == 0)
14517 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14520 # if defined (TE_PE) || defined (TE_PEP)
14521 case OPTION_MBIG_OBJ
:
14526 case OPTION_MOMIT_LOCK_PREFIX
:
14527 if (strcasecmp (arg
, "yes") == 0)
14528 omit_lock_prefix
= 1;
14529 else if (strcasecmp (arg
, "no") == 0)
14530 omit_lock_prefix
= 0;
14532 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14535 case OPTION_MFENCE_AS_LOCK_ADD
:
14536 if (strcasecmp (arg
, "yes") == 0)
14538 else if (strcasecmp (arg
, "no") == 0)
14541 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14544 case OPTION_MLFENCE_AFTER_LOAD
:
14545 if (strcasecmp (arg
, "yes") == 0)
14546 lfence_after_load
= 1;
14547 else if (strcasecmp (arg
, "no") == 0)
14548 lfence_after_load
= 0;
14550 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14553 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14554 if (strcasecmp (arg
, "all") == 0)
14556 lfence_before_indirect_branch
= lfence_branch_all
;
14557 if (lfence_before_ret
== lfence_before_ret_none
)
14558 lfence_before_ret
= lfence_before_ret_shl
;
14560 else if (strcasecmp (arg
, "memory") == 0)
14561 lfence_before_indirect_branch
= lfence_branch_memory
;
14562 else if (strcasecmp (arg
, "register") == 0)
14563 lfence_before_indirect_branch
= lfence_branch_register
;
14564 else if (strcasecmp (arg
, "none") == 0)
14565 lfence_before_indirect_branch
= lfence_branch_none
;
14567 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14571 case OPTION_MLFENCE_BEFORE_RET
:
14572 if (strcasecmp (arg
, "or") == 0)
14573 lfence_before_ret
= lfence_before_ret_or
;
14574 else if (strcasecmp (arg
, "not") == 0)
14575 lfence_before_ret
= lfence_before_ret_not
;
14576 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14577 lfence_before_ret
= lfence_before_ret_shl
;
14578 else if (strcasecmp (arg
, "none") == 0)
14579 lfence_before_ret
= lfence_before_ret_none
;
14581 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14585 case OPTION_MRELAX_RELOCATIONS
:
14586 if (strcasecmp (arg
, "yes") == 0)
14587 generate_relax_relocations
= 1;
14588 else if (strcasecmp (arg
, "no") == 0)
14589 generate_relax_relocations
= 0;
14591 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14594 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14597 long int align
= strtoul (arg
, &end
, 0);
14602 align_branch_power
= 0;
14605 else if (align
>= 16)
14608 for (align_power
= 0;
14610 align
>>= 1, align_power
++)
14612 /* Limit alignment power to 31. */
14613 if (align
== 1 && align_power
< 32)
14615 align_branch_power
= align_power
;
14620 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14624 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14627 int align
= strtoul (arg
, &end
, 0);
14628 /* Some processors only support 5 prefixes. */
14629 if (*end
== '\0' && align
>= 0 && align
< 6)
14631 align_branch_prefix_size
= align
;
14634 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14639 case OPTION_MALIGN_BRANCH
:
14641 saved
= xstrdup (arg
);
14645 next
= strchr (type
, '+');
14648 if (strcasecmp (type
, "jcc") == 0)
14649 align_branch
|= align_branch_jcc_bit
;
14650 else if (strcasecmp (type
, "fused") == 0)
14651 align_branch
|= align_branch_fused_bit
;
14652 else if (strcasecmp (type
, "jmp") == 0)
14653 align_branch
|= align_branch_jmp_bit
;
14654 else if (strcasecmp (type
, "call") == 0)
14655 align_branch
|= align_branch_call_bit
;
14656 else if (strcasecmp (type
, "ret") == 0)
14657 align_branch
|= align_branch_ret_bit
;
14658 else if (strcasecmp (type
, "indirect") == 0)
14659 align_branch
|= align_branch_indirect_bit
;
14661 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14664 while (next
!= NULL
);
14668 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14669 align_branch_power
= 5;
14670 align_branch_prefix_size
= 5;
14671 align_branch
= (align_branch_jcc_bit
14672 | align_branch_fused_bit
14673 | align_branch_jmp_bit
);
14676 case OPTION_MAMD64
:
14680 case OPTION_MINTEL64
:
14688 /* Turn off -Os. */
14689 optimize_for_space
= 0;
14691 else if (*arg
== 's')
14693 optimize_for_space
= 1;
14694 /* Turn on all encoding optimizations. */
14695 optimize
= INT_MAX
;
14699 optimize
= atoi (arg
);
14700 /* Turn off -Os. */
14701 optimize_for_space
= 0;
14711 #define MESSAGE_TEMPLATE \
14715 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14716 int *left_p
, const char *name
, int len
)
14718 int size
= sizeof (MESSAGE_TEMPLATE
);
14719 int left
= *left_p
;
14721 /* Reserve 2 spaces for ", " or ",\0" */
14724 /* Check if there is any room. */
14732 p
= mempcpy (p
, name
, len
);
14736 /* Output the current message now and start a new one. */
14739 fprintf (stream
, "%s\n", message
);
14741 left
= size
- (start
- message
) - len
- 2;
14743 gas_assert (left
>= 0);
14745 p
= mempcpy (p
, name
, len
);
14753 show_arch (FILE *stream
, int ext
, int check
)
14755 static char message
[] = MESSAGE_TEMPLATE
;
14756 char *start
= message
+ 27;
14758 int size
= sizeof (MESSAGE_TEMPLATE
);
14765 left
= size
- (start
- message
);
14769 p
= output_message (stream
, p
, message
, start
, &left
,
14770 STRING_COMMA_LEN ("default"));
14771 p
= output_message (stream
, p
, message
, start
, &left
,
14772 STRING_COMMA_LEN ("push"));
14773 p
= output_message (stream
, p
, message
, start
, &left
,
14774 STRING_COMMA_LEN ("pop"));
14777 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14779 /* Should it be skipped? */
14780 if (cpu_arch
[j
].skip
)
14783 name
= cpu_arch
[j
].name
;
14784 len
= cpu_arch
[j
].len
;
14785 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
14787 /* It is an extension. Skip if we aren't asked to show it. */
14788 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14793 /* It is an processor. Skip if we show only extension. */
14796 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14798 /* It is an impossible processor - skip. */
14802 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
14805 /* Display disabled extensions. */
14807 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14811 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14812 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14814 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
14815 p
= output_message (stream
, p
, message
, start
, &left
, str
,
14821 fprintf (stream
, "%s\n", message
);
14825 md_show_usage (FILE *stream
)
14827 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14828 fprintf (stream
, _("\
14829 -Qy, -Qn ignored\n\
14830 -V print assembler version number\n\
14833 fprintf (stream
, _("\
14834 -n do not optimize code alignment\n\
14835 -O{012s} attempt some code optimizations\n\
14836 -q quieten some warnings\n"));
14837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14838 fprintf (stream
, _("\
14842 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14843 fprintf (stream
, _("\
14844 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
14845 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
14846 fprintf (stream
, _("\
14847 --32/--64 generate 32bit/64bit object\n"));
14850 #ifdef SVR4_COMMENT_CHARS
14851 fprintf (stream
, _("\
14852 --divide do not treat `/' as a comment character\n"));
14854 fprintf (stream
, _("\
14855 --divide ignored\n"));
14857 fprintf (stream
, _("\
14858 -march=CPU[,+EXTENSION...]\n\
14859 generate code for CPU and EXTENSION, CPU is one of:\n"));
14860 show_arch (stream
, 0, 1);
14861 fprintf (stream
, _("\
14862 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
14863 show_arch (stream
, 1, 0);
14864 fprintf (stream
, _("\
14865 -mtune=CPU optimize for CPU, CPU is one of:\n"));
14866 show_arch (stream
, 0, 0);
14867 fprintf (stream
, _("\
14868 -msse2avx encode SSE instructions with VEX prefix\n"));
14869 fprintf (stream
, _("\
14870 -muse-unaligned-vector-move\n\
14871 encode aligned vector move as unaligned vector move\n"));
14872 fprintf (stream
, _("\
14873 -msse-check=[none|error|warning] (default: warning)\n\
14874 check SSE instructions\n"));
14875 fprintf (stream
, _("\
14876 -moperand-check=[none|error|warning] (default: warning)\n\
14877 check operand combinations for validity\n"));
14878 fprintf (stream
, _("\
14879 -mavxscalar=[128|256] (default: 128)\n\
14880 encode scalar AVX instructions with specific vector\n\
14882 fprintf (stream
, _("\
14883 -mvexwig=[0|1] (default: 0)\n\
14884 encode VEX instructions with specific VEX.W value\n\
14885 for VEX.W bit ignored instructions\n"));
14886 fprintf (stream
, _("\
14887 -mevexlig=[128|256|512] (default: 128)\n\
14888 encode scalar EVEX instructions with specific vector\n\
14890 fprintf (stream
, _("\
14891 -mevexwig=[0|1] (default: 0)\n\
14892 encode EVEX instructions with specific EVEX.W value\n\
14893 for EVEX.W bit ignored instructions\n"));
14894 fprintf (stream
, _("\
14895 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
14896 encode EVEX instructions with specific EVEX.RC value\n\
14897 for SAE-only ignored instructions\n"));
14898 fprintf (stream
, _("\
14899 -mmnemonic=[att|intel] "));
14900 if (SYSV386_COMPAT
)
14901 fprintf (stream
, _("(default: att)\n"));
14903 fprintf (stream
, _("(default: intel)\n"));
14904 fprintf (stream
, _("\
14905 use AT&T/Intel mnemonic\n"));
14906 fprintf (stream
, _("\
14907 -msyntax=[att|intel] (default: att)\n\
14908 use AT&T/Intel syntax\n"));
14909 fprintf (stream
, _("\
14910 -mindex-reg support pseudo index registers\n"));
14911 fprintf (stream
, _("\
14912 -mnaked-reg don't require `%%' prefix for registers\n"));
14913 fprintf (stream
, _("\
14914 -madd-bnd-prefix add BND prefix for all valid branches\n"));
14915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14916 fprintf (stream
, _("\
14917 -mshared disable branch optimization for shared code\n"));
14918 fprintf (stream
, _("\
14919 -mx86-used-note=[no|yes] "));
14920 if (DEFAULT_X86_USED_NOTE
)
14921 fprintf (stream
, _("(default: yes)\n"));
14923 fprintf (stream
, _("(default: no)\n"));
14924 fprintf (stream
, _("\
14925 generate x86 used ISA and feature properties\n"));
14927 #if defined (TE_PE) || defined (TE_PEP)
14928 fprintf (stream
, _("\
14929 -mbig-obj generate big object files\n"));
14931 fprintf (stream
, _("\
14932 -momit-lock-prefix=[no|yes] (default: no)\n\
14933 strip all lock prefixes\n"));
14934 fprintf (stream
, _("\
14935 -mfence-as-lock-add=[no|yes] (default: no)\n\
14936 encode lfence, mfence and sfence as\n\
14937 lock addl $0x0, (%%{re}sp)\n"));
14938 fprintf (stream
, _("\
14939 -mrelax-relocations=[no|yes] "));
14940 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
14941 fprintf (stream
, _("(default: yes)\n"));
14943 fprintf (stream
, _("(default: no)\n"));
14944 fprintf (stream
, _("\
14945 generate relax relocations\n"));
14946 fprintf (stream
, _("\
14947 -malign-branch-boundary=NUM (default: 0)\n\
14948 align branches within NUM byte boundary\n"));
14949 fprintf (stream
, _("\
14950 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
14951 TYPE is combination of jcc, fused, jmp, call, ret,\n\
14953 specify types of branches to align\n"));
14954 fprintf (stream
, _("\
14955 -malign-branch-prefix-size=NUM (default: 5)\n\
14956 align branches with NUM prefixes per instruction\n"));
14957 fprintf (stream
, _("\
14958 -mbranches-within-32B-boundaries\n\
14959 align branches within 32 byte boundary\n"));
14960 fprintf (stream
, _("\
14961 -mlfence-after-load=[no|yes] (default: no)\n\
14962 generate lfence after load\n"));
14963 fprintf (stream
, _("\
14964 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
14965 generate lfence before indirect near branch\n"));
14966 fprintf (stream
, _("\
14967 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
14968 generate lfence before ret\n"));
14969 fprintf (stream
, _("\
14970 -mamd64 accept only AMD64 ISA [default]\n"));
14971 fprintf (stream
, _("\
14972 -mintel64 accept only Intel64 ISA\n"));
14975 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
14976 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14977 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14979 /* Pick the target format to use. */
14982 i386_target_format (void)
14984 if (startswith (default_arch
, "x86_64"))
14986 update_code_flag (CODE_64BIT
, 1);
14987 if (default_arch
[6] == '\0')
14988 x86_elf_abi
= X86_64_ABI
;
14990 x86_elf_abi
= X86_64_X32_ABI
;
14992 else if (!strcmp (default_arch
, "i386"))
14993 update_code_flag (CODE_32BIT
, 1);
14994 else if (!strcmp (default_arch
, "iamcu"))
14996 update_code_flag (CODE_32BIT
, 1);
14997 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
14999 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15000 cpu_arch_name
= "iamcu";
15001 free (cpu_sub_arch_name
);
15002 cpu_sub_arch_name
= NULL
;
15003 cpu_arch_flags
= iamcu_flags
;
15004 cpu_arch_isa
= PROCESSOR_IAMCU
;
15005 cpu_arch_isa_flags
= iamcu_flags
;
15006 if (!cpu_arch_tune_set
)
15008 cpu_arch_tune
= cpu_arch_isa
;
15009 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
15012 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15013 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15017 as_fatal (_("unknown architecture"));
15019 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15020 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15021 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
15022 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15024 switch (OUTPUT_FLAVOR
)
15026 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15027 case bfd_target_aout_flavour
:
15028 return AOUT_TARGET_FORMAT
;
15030 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15031 # if defined (TE_PE) || defined (TE_PEP)
15032 case bfd_target_coff_flavour
:
15033 if (flag_code
== CODE_64BIT
)
15036 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15038 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15039 # elif defined (TE_GO32)
15040 case bfd_target_coff_flavour
:
15041 return "coff-go32";
15043 case bfd_target_coff_flavour
:
15044 return "coff-i386";
15047 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15048 case bfd_target_elf_flavour
:
15050 const char *format
;
15052 switch (x86_elf_abi
)
15055 format
= ELF_TARGET_FORMAT
;
15057 tls_get_addr
= "___tls_get_addr";
15061 use_rela_relocations
= 1;
15064 tls_get_addr
= "__tls_get_addr";
15066 format
= ELF_TARGET_FORMAT64
;
15068 case X86_64_X32_ABI
:
15069 use_rela_relocations
= 1;
15072 tls_get_addr
= "__tls_get_addr";
15074 disallow_64bit_reloc
= 1;
15075 format
= ELF_TARGET_FORMAT32
;
15078 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15080 if (x86_elf_abi
!= I386_ABI
)
15081 as_fatal (_("Intel MCU is 32bit only"));
15082 return ELF_TARGET_IAMCU_FORMAT
;
15088 #if defined (OBJ_MACH_O)
15089 case bfd_target_mach_o_flavour
:
15090 if (flag_code
== CODE_64BIT
)
15092 use_rela_relocations
= 1;
15094 return "mach-o-x86-64";
15097 return "mach-o-i386";
15105 #endif /* OBJ_MAYBE_ more than one */
15108 md_undefined_symbol (char *name
)
15110 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15111 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15112 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15113 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15117 if (symbol_find (name
))
15118 as_bad (_("GOT already in symbol table"));
15119 GOT_symbol
= symbol_new (name
, undefined_section
,
15120 &zero_address_frag
, 0);
15127 /* Round up a section size to the appropriate boundary. */
15130 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15132 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15133 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15135 /* For a.out, force the section size to be aligned. If we don't do
15136 this, BFD will align it for us, but it will not write out the
15137 final bytes of the section. This may be a bug in BFD, but it is
15138 easier to fix it here since that is how the other a.out targets
15142 align
= bfd_section_alignment (segment
);
15143 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15150 /* On the i386, PC-relative offsets are relative to the start of the
15151 next instruction. That is, the address of the offset, plus its
15152 size, since the offset is always the last part of the insn. */
15155 md_pcrel_from (fixS
*fixP
)
15157 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15163 s_bss (int ignore ATTRIBUTE_UNUSED
)
15167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15169 obj_elf_section_change_hook ();
15171 temp
= get_absolute_expression ();
15172 subseg_set (bss_section
, (subsegT
) temp
);
15173 demand_empty_rest_of_line ();
15178 /* Remember constant directive. */
15181 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15183 if (last_insn
.kind
!= last_insn_directive
15184 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15186 last_insn
.seg
= now_seg
;
15187 last_insn
.kind
= last_insn_directive
;
15188 last_insn
.name
= "constant directive";
15189 last_insn
.file
= as_where (&last_insn
.line
);
15190 if (lfence_before_ret
!= lfence_before_ret_none
)
15192 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15193 as_warn (_("constant directive skips -mlfence-before-ret "
15194 "and -mlfence-before-indirect-branch"));
15196 as_warn (_("constant directive skips -mlfence-before-ret"));
15198 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15199 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15204 i386_validate_fix (fixS
*fixp
)
15206 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15208 reloc_howto_type
*howto
;
15210 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15211 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15212 _("invalid %s relocation against register"),
15213 howto
? howto
->name
: "<unknown>");
15217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15218 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15219 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15220 return IS_ELF
&& fixp
->fx_addsy
15221 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15222 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15225 if (fixp
->fx_subsy
)
15227 if (fixp
->fx_subsy
== GOT_symbol
)
15229 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15234 if (fixp
->fx_tcbit2
)
15235 fixp
->fx_r_type
= (fixp
->fx_tcbit
15236 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15237 : BFD_RELOC_X86_64_GOTPCRELX
);
15240 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15245 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15247 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15249 fixp
->fx_subsy
= 0;
15252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15255 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15256 to section. Since PLT32 relocation must be against symbols,
15257 turn such PLT32 relocation into PC32 relocation. */
15259 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15260 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15261 && symbol_section_p (fixp
->fx_addsy
))
15262 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15265 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15266 && fixp
->fx_tcbit2
)
15267 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15276 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15279 bfd_reloc_code_real_type code
;
15281 switch (fixp
->fx_r_type
)
15283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15286 case BFD_RELOC_SIZE32
:
15287 case BFD_RELOC_SIZE64
:
15289 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15290 && (!fixp
->fx_subsy
15291 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15292 sym
= fixp
->fx_addsy
;
15293 else if (fixp
->fx_subsy
15294 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15295 && (!fixp
->fx_addsy
15296 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15297 sym
= fixp
->fx_subsy
;
15300 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15302 /* Resolve size relocation against local symbol to size of
15303 the symbol plus addend. */
15304 valueT value
= S_GET_SIZE (sym
);
15306 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15307 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15308 if (sym
== fixp
->fx_subsy
)
15311 if (fixp
->fx_addsy
)
15312 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15314 else if (fixp
->fx_subsy
)
15315 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15316 value
+= fixp
->fx_offset
;
15317 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15319 && !fits_in_unsigned_long (value
))
15320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15321 _("symbol size computation overflow"));
15322 fixp
->fx_addsy
= NULL
;
15323 fixp
->fx_subsy
= NULL
;
15324 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15327 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15329 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15330 "unsupported expression involving @size");
15334 /* Fall through. */
15336 case BFD_RELOC_X86_64_PLT32
:
15337 case BFD_RELOC_X86_64_GOT32
:
15338 case BFD_RELOC_X86_64_GOTPCREL
:
15339 case BFD_RELOC_X86_64_GOTPCRELX
:
15340 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15341 case BFD_RELOC_386_PLT32
:
15342 case BFD_RELOC_386_GOT32
:
15343 case BFD_RELOC_386_GOT32X
:
15344 case BFD_RELOC_386_GOTOFF
:
15345 case BFD_RELOC_386_GOTPC
:
15346 case BFD_RELOC_386_TLS_GD
:
15347 case BFD_RELOC_386_TLS_LDM
:
15348 case BFD_RELOC_386_TLS_LDO_32
:
15349 case BFD_RELOC_386_TLS_IE_32
:
15350 case BFD_RELOC_386_TLS_IE
:
15351 case BFD_RELOC_386_TLS_GOTIE
:
15352 case BFD_RELOC_386_TLS_LE_32
:
15353 case BFD_RELOC_386_TLS_LE
:
15354 case BFD_RELOC_386_TLS_GOTDESC
:
15355 case BFD_RELOC_386_TLS_DESC_CALL
:
15356 case BFD_RELOC_X86_64_TLSGD
:
15357 case BFD_RELOC_X86_64_TLSLD
:
15358 case BFD_RELOC_X86_64_DTPOFF32
:
15359 case BFD_RELOC_X86_64_DTPOFF64
:
15360 case BFD_RELOC_X86_64_GOTTPOFF
:
15361 case BFD_RELOC_X86_64_TPOFF32
:
15362 case BFD_RELOC_X86_64_TPOFF64
:
15363 case BFD_RELOC_X86_64_GOTOFF64
:
15364 case BFD_RELOC_X86_64_GOTPC32
:
15365 case BFD_RELOC_X86_64_GOT64
:
15366 case BFD_RELOC_X86_64_GOTPCREL64
:
15367 case BFD_RELOC_X86_64_GOTPC64
:
15368 case BFD_RELOC_X86_64_GOTPLT64
:
15369 case BFD_RELOC_X86_64_PLTOFF64
:
15370 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15371 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15372 case BFD_RELOC_RVA
:
15373 case BFD_RELOC_VTABLE_ENTRY
:
15374 case BFD_RELOC_VTABLE_INHERIT
:
15376 case BFD_RELOC_32_SECREL
:
15377 case BFD_RELOC_16_SECIDX
:
15379 code
= fixp
->fx_r_type
;
15381 case BFD_RELOC_X86_64_32S
:
15382 if (!fixp
->fx_pcrel
)
15384 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15385 code
= fixp
->fx_r_type
;
15388 /* Fall through. */
15390 if (fixp
->fx_pcrel
)
15392 switch (fixp
->fx_size
)
15395 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15396 _("can not do %d byte pc-relative relocation"),
15398 code
= BFD_RELOC_32_PCREL
;
15400 case 1: code
= BFD_RELOC_8_PCREL
; break;
15401 case 2: code
= BFD_RELOC_16_PCREL
; break;
15402 case 4: code
= BFD_RELOC_32_PCREL
; break;
15404 case 8: code
= BFD_RELOC_64_PCREL
; break;
15410 switch (fixp
->fx_size
)
15413 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15414 _("can not do %d byte relocation"),
15416 code
= BFD_RELOC_32
;
15418 case 1: code
= BFD_RELOC_8
; break;
15419 case 2: code
= BFD_RELOC_16
; break;
15420 case 4: code
= BFD_RELOC_32
; break;
15422 case 8: code
= BFD_RELOC_64
; break;
15429 if ((code
== BFD_RELOC_32
15430 || code
== BFD_RELOC_32_PCREL
15431 || code
== BFD_RELOC_X86_64_32S
)
15433 && fixp
->fx_addsy
== GOT_symbol
)
15436 code
= BFD_RELOC_386_GOTPC
;
15438 code
= BFD_RELOC_X86_64_GOTPC32
;
15440 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15442 && fixp
->fx_addsy
== GOT_symbol
)
15444 code
= BFD_RELOC_X86_64_GOTPC64
;
15447 rel
= XNEW (arelent
);
15448 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15449 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15451 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15453 if (!use_rela_relocations
)
15455 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15456 vtable entry to be used in the relocation's section offset. */
15457 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15458 rel
->address
= fixp
->fx_offset
;
15459 #if defined (OBJ_COFF) && defined (TE_PE)
15460 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15461 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15466 /* Use the rela in 64bit mode. */
15469 if (disallow_64bit_reloc
)
15472 case BFD_RELOC_X86_64_DTPOFF64
:
15473 case BFD_RELOC_X86_64_TPOFF64
:
15474 case BFD_RELOC_64_PCREL
:
15475 case BFD_RELOC_X86_64_GOTOFF64
:
15476 case BFD_RELOC_X86_64_GOT64
:
15477 case BFD_RELOC_X86_64_GOTPCREL64
:
15478 case BFD_RELOC_X86_64_GOTPC64
:
15479 case BFD_RELOC_X86_64_GOTPLT64
:
15480 case BFD_RELOC_X86_64_PLTOFF64
:
15481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15482 _("cannot represent relocation type %s in x32 mode"),
15483 bfd_get_reloc_code_name (code
));
15489 if (!fixp
->fx_pcrel
)
15490 rel
->addend
= fixp
->fx_offset
;
15494 case BFD_RELOC_X86_64_PLT32
:
15495 case BFD_RELOC_X86_64_GOT32
:
15496 case BFD_RELOC_X86_64_GOTPCREL
:
15497 case BFD_RELOC_X86_64_GOTPCRELX
:
15498 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15499 case BFD_RELOC_X86_64_TLSGD
:
15500 case BFD_RELOC_X86_64_TLSLD
:
15501 case BFD_RELOC_X86_64_GOTTPOFF
:
15502 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15503 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15504 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15507 rel
->addend
= (section
->vma
15509 + fixp
->fx_addnumber
15510 + md_pcrel_from (fixp
));
15515 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15516 if (rel
->howto
== NULL
)
15518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15519 _("cannot represent relocation type %s"),
15520 bfd_get_reloc_code_name (code
));
15521 /* Set howto to a garbage value so that we can keep going. */
15522 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15523 gas_assert (rel
->howto
!= NULL
);
15529 #include "tc-i386-intel.c"
15532 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15534 int saved_naked_reg
;
15535 char saved_register_dot
;
15537 saved_naked_reg
= allow_naked_reg
;
15538 allow_naked_reg
= 1;
15539 saved_register_dot
= register_chars
['.'];
15540 register_chars
['.'] = '.';
15541 allow_pseudo_reg
= 1;
15542 expression_and_evaluate (exp
);
15543 allow_pseudo_reg
= 0;
15544 register_chars
['.'] = saved_register_dot
;
15545 allow_naked_reg
= saved_naked_reg
;
15547 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15549 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15551 exp
->X_op
= O_constant
;
15552 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15553 .dw2_regnum
[flag_code
>> 1];
15556 exp
->X_op
= O_illegal
;
15561 tc_x86_frame_initial_instructions (void)
15563 static unsigned int sp_regno
[2];
15565 if (!sp_regno
[flag_code
>> 1])
15567 char *saved_input
= input_line_pointer
;
15568 char sp
[][4] = {"esp", "rsp"};
15571 input_line_pointer
= sp
[flag_code
>> 1];
15572 tc_x86_parse_to_dw2regnum (&exp
);
15573 gas_assert (exp
.X_op
== O_constant
);
15574 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15575 input_line_pointer
= saved_input
;
15578 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15579 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15583 x86_dwarf2_addr_size (void)
15585 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15586 if (x86_elf_abi
== X86_64_X32_ABI
)
15589 return bfd_arch_bits_per_address (stdoutput
) / 8;
15593 i386_elf_section_type (const char *str
, size_t len
)
15595 if (flag_code
== CODE_64BIT
15596 && len
== sizeof ("unwind") - 1
15597 && startswith (str
, "unwind"))
15598 return SHT_X86_64_UNWIND
;
15605 i386_solaris_fix_up_eh_frame (segT sec
)
15607 if (flag_code
== CODE_64BIT
)
15608 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15614 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15618 exp
.X_op
= O_secrel
;
15619 exp
.X_add_symbol
= symbol
;
15620 exp
.X_add_number
= 0;
15621 emit_expr (&exp
, size
);
15625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15626 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15629 x86_64_section_letter (int letter
, const char **ptr_msg
)
15631 if (flag_code
== CODE_64BIT
)
15634 return SHF_X86_64_LARGE
;
15636 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15639 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15644 x86_64_section_word (char *str
, size_t len
)
15646 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
15647 return SHF_X86_64_LARGE
;
15653 handle_large_common (int small ATTRIBUTE_UNUSED
)
15655 if (flag_code
!= CODE_64BIT
)
15657 s_comm_internal (0, elf_common_parse
);
15658 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15662 static segT lbss_section
;
15663 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15664 asection
*saved_bss_section
= bss_section
;
15666 if (lbss_section
== NULL
)
15668 flagword applicable
;
15669 segT seg
= now_seg
;
15670 subsegT subseg
= now_subseg
;
15672 /* The .lbss section is for local .largecomm symbols. */
15673 lbss_section
= subseg_new (".lbss", 0);
15674 applicable
= bfd_applicable_section_flags (stdoutput
);
15675 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15676 seg_info (lbss_section
)->bss
= 1;
15678 subseg_set (seg
, subseg
);
15681 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15682 bss_section
= lbss_section
;
15684 s_comm_internal (0, elf_common_parse
);
15686 elf_com_section_ptr
= saved_com_section_ptr
;
15687 bss_section
= saved_bss_section
;
15690 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */