1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
61 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
62 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
63 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
64 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
65 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
66 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
67 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
68 static int smallest_imm_type
PARAMS ((offsetT
));
69 static offsetT offset_in_range
PARAMS ((offsetT
, int));
70 static int add_prefix
PARAMS ((unsigned int));
71 static void set_code_flag
PARAMS ((int));
72 static void set_16bit_gcc_code_flag
PARAMS ((int));
73 static void set_intel_syntax
PARAMS ((int));
74 static void set_cpu_arch
PARAMS ((int));
75 static char *output_invalid
PARAMS ((int c
));
76 static int i386_operand
PARAMS ((char *operand_string
));
77 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
78 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
80 static char *parse_insn
PARAMS ((char *, char *));
81 static char *parse_operands
PARAMS ((char *, const char *));
82 static void swap_operands
PARAMS ((void));
83 static void optimize_imm
PARAMS ((void));
84 static void optimize_disp
PARAMS ((void));
85 static int match_template
PARAMS ((void));
86 static int check_string
PARAMS ((void));
87 static int process_suffix
PARAMS ((void));
88 static int check_byte_reg
PARAMS ((void));
89 static int check_long_reg
PARAMS ((void));
90 static int check_qword_reg
PARAMS ((void));
91 static int check_word_reg
PARAMS ((void));
92 static int finalize_imm
PARAMS ((void));
93 static int process_operands
PARAMS ((void));
94 static const seg_entry
*build_modrm_byte
PARAMS ((void));
95 static void output_insn
PARAMS ((void));
96 static void output_branch
PARAMS ((void));
97 static void output_jump
PARAMS ((void));
98 static void output_interseg_jump
PARAMS ((void));
99 static void output_imm
PARAMS ((void));
100 static void output_disp
PARAMS ((void));
102 static void s_bss
PARAMS ((int));
105 static const char *default_arch
= DEFAULT_ARCH
;
107 /* 'md_assemble ()' gathers together information and puts it into a
114 const reg_entry
*regs
;
119 /* TM holds the template for the insn were currently assembling. */
122 /* SUFFIX holds the instruction mnemonic suffix if given.
123 (e.g. 'l' for 'movl') */
126 /* OPERANDS gives the number of given operands. */
127 unsigned int operands
;
129 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
130 of given register, displacement, memory operands and immediate
132 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
134 /* TYPES [i] is the type (see above #defines) which tells us how to
135 use OP[i] for the corresponding operand. */
136 unsigned int types
[MAX_OPERANDS
];
138 /* Displacement expression, immediate expression, or register for each
140 union i386_op op
[MAX_OPERANDS
];
142 /* Flags for operands. */
143 unsigned int flags
[MAX_OPERANDS
];
144 #define Operand_PCrel 1
146 /* Relocation type for operand */
147 RELOC_ENUM reloc
[MAX_OPERANDS
];
149 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
150 the base index byte below. */
151 const reg_entry
*base_reg
;
152 const reg_entry
*index_reg
;
153 unsigned int log2_scale_factor
;
155 /* SEG gives the seg_entries of this insn. They are zero unless
156 explicit segment overrides are given. */
157 const seg_entry
*seg
[2];
159 /* PREFIX holds all the given prefix opcodes (usually null).
160 PREFIXES is the number of prefix opcodes. */
161 unsigned int prefixes
;
162 unsigned char prefix
[MAX_PREFIXES
];
164 /* RM and SIB are the modrm byte and the sib byte where the
165 addressing modes of this insn are encoded. */
172 typedef struct _i386_insn i386_insn
;
174 /* List of chars besides those in app.c:symbol_chars that can start an
175 operand. Used to prevent the scrubber eating vital white-space. */
177 const char extra_symbol_chars
[] = "*%-(@";
179 const char extra_symbol_chars
[] = "*%-(";
182 #if (defined (TE_I386AIX) \
183 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful. */
189 const char comment_chars
[] = "#/";
190 #define PREFIX_SEPARATOR '\\'
192 /* This array holds the chars that only start a comment at the beginning of
193 a line. If the line seems to have the form '# 123 filename'
194 .line and .file directives will appear in the pre-processed output.
195 Note that input_file.c hand checks for '#' at the beginning of the
196 first line of the input file. This is because the compiler outputs
197 #NO_APP at the beginning of its output.
198 Also note that comments started like this one will always work if
199 '/' isn't otherwise defined. */
200 const char line_comment_chars
[] = "";
203 /* Putting '/' here makes it impossible to use the divide operator.
204 However, we need it for compatibility with SVR4 systems. */
205 const char comment_chars
[] = "#";
206 #define PREFIX_SEPARATOR '/'
208 const char line_comment_chars
[] = "/";
211 const char line_separator_chars
[] = ";";
213 /* Chars that can be used to separate mant from exp in floating point
215 const char EXP_CHARS
[] = "eE";
217 /* Chars that mean this number is a floating point constant
220 const char FLT_CHARS
[] = "fFdDxX";
222 /* Tables for lexical analysis. */
223 static char mnemonic_chars
[256];
224 static char register_chars
[256];
225 static char operand_chars
[256];
226 static char identifier_chars
[256];
227 static char digit_chars
[256];
229 /* Lexical macros. */
230 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
231 #define is_operand_char(x) (operand_chars[(unsigned char) x])
232 #define is_register_char(x) (register_chars[(unsigned char) x])
233 #define is_space_char(x) ((x) == ' ')
234 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
235 #define is_digit_char(x) (digit_chars[(unsigned char) x])
237 /* All non-digit non-letter charcters that may occur in an operand. */
238 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
240 /* md_assemble() always leaves the strings it's passed unaltered. To
241 effect this we maintain a stack of saved characters that we've smashed
242 with '\0's (indicating end of strings for various sub-fields of the
243 assembler instruction). */
244 static char save_stack
[32];
245 static char *save_stack_p
;
246 #define END_STRING_AND_SAVE(s) \
247 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
248 #define RESTORE_END_STRING(s) \
249 do { *(s) = *--save_stack_p; } while (0)
251 /* The instruction we're assembling. */
254 /* Possible templates for current insn. */
255 static const templates
*current_templates
;
257 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
258 static expressionS disp_expressions
[2], im_expressions
[2];
260 /* Current operand we are working on. */
261 static int this_operand
;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
270 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
272 static enum flag_code flag_code
;
273 static int use_rela_relocations
= 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names
[] =
283 /* 1 for intel syntax,
285 static int intel_syntax
= 0;
287 /* 1 if register prefix % not required. */
288 static int allow_naked_reg
= 0;
290 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
291 leave, push, and pop instructions so that gcc has the same stack
292 frame as in 32 bit mode. */
293 static char stackop_size
= '\0';
295 /* Non-zero to quieten some warnings. */
296 static int quiet_warnings
= 0;
299 static const char *cpu_arch_name
= NULL
;
301 /* CPU feature flags. */
302 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
304 /* If set, conditional jumps are not automatically promoted to handle
305 larger than a byte offset. */
306 static unsigned int no_cond_jump_promotion
= 0;
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
311 /* Interface to relax_segment.
312 There are 3 major relax states for 386 jump insns because the
313 different types of jumps add different sizes to frags when we're
314 figuring out what sort of jump to choose to reach a given label. */
317 #define UNCOND_JUMP 0
319 #define COND_JUMP86 2
324 #define SMALL16 (SMALL | CODE16)
326 #define BIG16 (BIG | CODE16)
330 #define INLINE __inline__
336 #define ENCODE_RELAX_STATE(type, size) \
337 ((relax_substateT) (((type) << 2) | (size)))
338 #define TYPE_FROM_RELAX_STATE(s) \
340 #define DISP_SIZE_FROM_RELAX_STATE(s) \
341 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
343 /* This table is used by relax_frag to promote short jumps to long
344 ones where necessary. SMALL (short) jumps may be promoted to BIG
345 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
346 don't allow a short jump in a 32 bit code segment to be promoted to
347 a 16 bit offset jump because it's slower (requires data size
348 prefix), and doesn't work, unless the destination is in the bottom
349 64k of the code segment (The top 16 bits of eip are zeroed). */
351 const relax_typeS md_relax_table
[] =
354 1) most positive reach of this state,
355 2) most negative reach of this state,
356 3) how many bytes this mode will have in the variable part of the frag
357 4) which index into the table to try if we can't fit into this one. */
359 /* UNCOND_JUMP states. */
360 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
361 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
362 /* dword jmp adds 4 bytes to frag:
363 0 extra opcode bytes, 4 displacement bytes. */
365 /* word jmp adds 2 byte2 to frag:
366 0 extra opcode bytes, 2 displacement bytes. */
369 /* COND_JUMP states. */
370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
372 /* dword conditionals adds 5 bytes to frag:
373 1 extra opcode byte, 4 displacement bytes. */
375 /* word conditionals add 3 bytes to frag:
376 1 extra opcode byte, 2 displacement bytes. */
379 /* COND_JUMP86 states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
385 /* word conditionals add 4 bytes to frag:
386 1 displacement byte and a 3 byte long branch insn. */
390 static const arch_entry cpu_arch
[] = {
392 {"i186", Cpu086
|Cpu186
},
393 {"i286", Cpu086
|Cpu186
|Cpu286
},
394 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
395 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
396 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
397 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
398 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
399 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
400 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
401 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
402 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
403 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
407 const pseudo_typeS md_pseudo_table
[] =
409 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
410 {"align", s_align_bytes
, 0},
412 {"align", s_align_ptwo
, 0},
414 {"arch", set_cpu_arch
, 0},
418 {"ffloat", float_cons
, 'f'},
419 {"dfloat", float_cons
, 'd'},
420 {"tfloat", float_cons
, 'x'},
422 {"noopt", s_ignore
, 0},
423 {"optim", s_ignore
, 0},
424 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
425 {"code16", set_code_flag
, CODE_16BIT
},
426 {"code32", set_code_flag
, CODE_32BIT
},
427 {"code64", set_code_flag
, CODE_64BIT
},
428 {"intel_syntax", set_intel_syntax
, 1},
429 {"att_syntax", set_intel_syntax
, 0},
430 {"file", dwarf2_directive_file
, 0},
431 {"loc", dwarf2_directive_loc
, 0},
435 /* For interface with expression (). */
436 extern char *input_line_pointer
;
438 /* Hash table for instruction mnemonic lookup. */
439 static struct hash_control
*op_hash
;
441 /* Hash table for register lookup. */
442 static struct hash_control
*reg_hash
;
445 i386_align_code (fragP
, count
)
449 /* Various efficient no-op patterns for aligning code labels.
450 Note: Don't try to assemble the instructions in the comments.
451 0L and 0w are not legal. */
452 static const char f32_1
[] =
454 static const char f32_2
[] =
455 {0x89,0xf6}; /* movl %esi,%esi */
456 static const char f32_3
[] =
457 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
458 static const char f32_4
[] =
459 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
460 static const char f32_5
[] =
462 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
463 static const char f32_6
[] =
464 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
465 static const char f32_7
[] =
466 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
467 static const char f32_8
[] =
469 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
470 static const char f32_9
[] =
471 {0x89,0xf6, /* movl %esi,%esi */
472 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
473 static const char f32_10
[] =
474 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
475 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
476 static const char f32_11
[] =
477 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
478 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
479 static const char f32_12
[] =
480 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
481 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
482 static const char f32_13
[] =
483 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
484 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
485 static const char f32_14
[] =
486 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
487 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
488 static const char f32_15
[] =
489 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
490 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
491 static const char f16_3
[] =
492 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
493 static const char f16_4
[] =
494 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
495 static const char f16_5
[] =
497 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
498 static const char f16_6
[] =
499 {0x89,0xf6, /* mov %si,%si */
500 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
501 static const char f16_7
[] =
502 {0x8d,0x74,0x00, /* lea 0(%si),%si */
503 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
504 static const char f16_8
[] =
505 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
506 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
507 static const char *const f32_patt
[] = {
508 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
509 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
511 static const char *const f16_patt
[] = {
512 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
513 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
516 /* ??? We can't use these fillers for x86_64, since they often kills the
517 upper halves. Solve later. */
518 if (flag_code
== CODE_64BIT
)
521 if (count
> 0 && count
<= 15)
523 if (flag_code
== CODE_16BIT
)
525 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
526 f16_patt
[count
- 1], count
);
528 /* Adjust jump offset. */
529 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
532 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
533 f32_patt
[count
- 1], count
);
534 fragP
->fr_var
= count
;
538 static INLINE
unsigned int
539 mode_from_disp_size (t
)
542 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
546 fits_in_signed_byte (num
)
549 return (num
>= -128) && (num
<= 127);
553 fits_in_unsigned_byte (num
)
556 return (num
& 0xff) == num
;
560 fits_in_unsigned_word (num
)
563 return (num
& 0xffff) == num
;
567 fits_in_signed_word (num
)
570 return (-32768 <= num
) && (num
<= 32767);
573 fits_in_signed_long (num
)
574 offsetT num ATTRIBUTE_UNUSED
;
579 return (!(((offsetT
) -1 << 31) & num
)
580 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
582 } /* fits_in_signed_long() */
584 fits_in_unsigned_long (num
)
585 offsetT num ATTRIBUTE_UNUSED
;
590 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
592 } /* fits_in_unsigned_long() */
595 smallest_imm_type (num
)
598 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
600 /* This code is disabled on the 486 because all the Imm1 forms
601 in the opcode table are slower on the i486. They're the
602 versions with the implicitly specified single-position
603 displacement, which has another syntax if you really want to
606 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
608 return (fits_in_signed_byte (num
)
609 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
610 : fits_in_unsigned_byte (num
)
611 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
612 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
613 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
614 : fits_in_signed_long (num
)
615 ? (Imm32
| Imm32S
| Imm64
)
616 : fits_in_unsigned_long (num
)
622 offset_in_range (val
, size
)
630 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
631 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
632 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
634 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
639 /* If BFD64, sign extend val. */
640 if (!use_rela_relocations
)
641 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
642 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
644 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
646 char buf1
[40], buf2
[40];
648 sprint_value (buf1
, val
);
649 sprint_value (buf2
, val
& mask
);
650 as_warn (_("%s shortened to %s"), buf1
, buf2
);
655 /* Returns 0 if attempting to add a prefix where one from the same
656 class already exists, 1 if non rep/repne added, 2 if rep/repne
665 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
666 && flag_code
== CODE_64BIT
)
674 case CS_PREFIX_OPCODE
:
675 case DS_PREFIX_OPCODE
:
676 case ES_PREFIX_OPCODE
:
677 case FS_PREFIX_OPCODE
:
678 case GS_PREFIX_OPCODE
:
679 case SS_PREFIX_OPCODE
:
683 case REPNE_PREFIX_OPCODE
:
684 case REPE_PREFIX_OPCODE
:
687 case LOCK_PREFIX_OPCODE
:
695 case ADDR_PREFIX_OPCODE
:
699 case DATA_PREFIX_OPCODE
:
704 if (i
.prefix
[q
] != 0)
706 as_bad (_("same type of prefix used twice"));
711 i
.prefix
[q
] = prefix
;
716 set_code_flag (value
)
720 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
721 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
722 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
724 as_bad (_("64bit mode not supported on this CPU."));
726 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
728 as_bad (_("32bit mode not supported on this CPU."));
734 set_16bit_gcc_code_flag (new_code_flag
)
737 flag_code
= new_code_flag
;
738 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
739 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
744 set_intel_syntax (syntax_flag
)
747 /* Find out if register prefixing is specified. */
748 int ask_naked_reg
= 0;
751 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
753 char *string
= input_line_pointer
;
754 int e
= get_symbol_end ();
756 if (strcmp (string
, "prefix") == 0)
758 else if (strcmp (string
, "noprefix") == 0)
761 as_bad (_("bad argument to syntax directive."));
762 *input_line_pointer
= e
;
764 demand_empty_rest_of_line ();
766 intel_syntax
= syntax_flag
;
768 if (ask_naked_reg
== 0)
771 allow_naked_reg
= (intel_syntax
772 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
774 /* Conservative default. */
779 allow_naked_reg
= (ask_naked_reg
< 0);
784 int dummy ATTRIBUTE_UNUSED
;
788 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
790 char *string
= input_line_pointer
;
791 int e
= get_symbol_end ();
794 for (i
= 0; cpu_arch
[i
].name
; i
++)
796 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
798 cpu_arch_name
= cpu_arch
[i
].name
;
799 cpu_arch_flags
= (cpu_arch
[i
].flags
800 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
804 if (!cpu_arch
[i
].name
)
805 as_bad (_("no such architecture: `%s'"), string
);
807 *input_line_pointer
= e
;
810 as_bad (_("missing cpu architecture"));
812 no_cond_jump_promotion
= 0;
813 if (*input_line_pointer
== ','
814 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
816 char *string
= ++input_line_pointer
;
817 int e
= get_symbol_end ();
819 if (strcmp (string
, "nojumps") == 0)
820 no_cond_jump_promotion
= 1;
821 else if (strcmp (string
, "jumps") == 0)
824 as_bad (_("no such architecture modifier: `%s'"), string
);
826 *input_line_pointer
= e
;
829 demand_empty_rest_of_line ();
836 if (!strcmp (default_arch
, "x86_64"))
837 return bfd_mach_x86_64
;
838 else if (!strcmp (default_arch
, "i386"))
839 return bfd_mach_i386_i386
;
841 as_fatal (_("Unknown architecture"));
848 const char *hash_err
;
850 /* Initialize op_hash hash table. */
851 op_hash
= hash_new ();
854 const template *optab
;
855 templates
*core_optab
;
857 /* Setup for loop. */
859 core_optab
= (templates
*) xmalloc (sizeof (templates
));
860 core_optab
->start
= optab
;
865 if (optab
->name
== NULL
866 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
868 /* different name --> ship out current template list;
869 add to hash table; & begin anew. */
870 core_optab
->end
= optab
;
871 hash_err
= hash_insert (op_hash
,
876 as_fatal (_("Internal Error: Can't hash %s: %s"),
880 if (optab
->name
== NULL
)
882 core_optab
= (templates
*) xmalloc (sizeof (templates
));
883 core_optab
->start
= optab
;
888 /* Initialize reg_hash hash table. */
889 reg_hash
= hash_new ();
891 const reg_entry
*regtab
;
893 for (regtab
= i386_regtab
;
894 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
897 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
899 as_fatal (_("Internal Error: Can't hash %s: %s"),
905 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
910 for (c
= 0; c
< 256; c
++)
915 mnemonic_chars
[c
] = c
;
916 register_chars
[c
] = c
;
917 operand_chars
[c
] = c
;
919 else if (ISLOWER (c
))
921 mnemonic_chars
[c
] = c
;
922 register_chars
[c
] = c
;
923 operand_chars
[c
] = c
;
925 else if (ISUPPER (c
))
927 mnemonic_chars
[c
] = TOLOWER (c
);
928 register_chars
[c
] = mnemonic_chars
[c
];
929 operand_chars
[c
] = c
;
932 if (ISALPHA (c
) || ISDIGIT (c
))
933 identifier_chars
[c
] = c
;
936 identifier_chars
[c
] = c
;
937 operand_chars
[c
] = c
;
942 identifier_chars
['@'] = '@';
944 digit_chars
['-'] = '-';
945 identifier_chars
['_'] = '_';
946 identifier_chars
['.'] = '.';
948 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
949 operand_chars
[(unsigned char) *p
] = *p
;
952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
953 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
955 record_alignment (text_section
, 2);
956 record_alignment (data_section
, 2);
957 record_alignment (bss_section
, 2);
963 i386_print_statistics (file
)
966 hash_print_statistics (file
, "i386 opcode", op_hash
);
967 hash_print_statistics (file
, "i386 register", reg_hash
);
972 /* Debugging routines for md_assemble. */
973 static void pi
PARAMS ((char *, i386_insn
*));
974 static void pte
PARAMS ((template *));
975 static void pt
PARAMS ((unsigned int));
976 static void pe
PARAMS ((expressionS
*));
977 static void ps
PARAMS ((symbolS
*));
986 fprintf (stdout
, "%s: template ", line
);
988 fprintf (stdout
, " address: base %s index %s scale %x\n",
989 x
->base_reg
? x
->base_reg
->reg_name
: "none",
990 x
->index_reg
? x
->index_reg
->reg_name
: "none",
991 x
->log2_scale_factor
);
992 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
993 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
994 fprintf (stdout
, " sib: base %x index %x scale %x\n",
995 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
996 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
997 (x
->rex
& REX_MODE64
) != 0,
998 (x
->rex
& REX_EXTX
) != 0,
999 (x
->rex
& REX_EXTY
) != 0,
1000 (x
->rex
& REX_EXTZ
) != 0);
1001 for (i
= 0; i
< x
->operands
; i
++)
1003 fprintf (stdout
, " #%d: ", i
+ 1);
1005 fprintf (stdout
, "\n");
1007 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1008 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1009 if (x
->types
[i
] & Imm
)
1011 if (x
->types
[i
] & Disp
)
1012 pe (x
->op
[i
].disps
);
1021 fprintf (stdout
, " %d operands ", t
->operands
);
1022 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1023 if (t
->extension_opcode
!= None
)
1024 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1025 if (t
->opcode_modifier
& D
)
1026 fprintf (stdout
, "D");
1027 if (t
->opcode_modifier
& W
)
1028 fprintf (stdout
, "W");
1029 fprintf (stdout
, "\n");
1030 for (i
= 0; i
< t
->operands
; i
++)
1032 fprintf (stdout
, " #%d type ", i
+ 1);
1033 pt (t
->operand_types
[i
]);
1034 fprintf (stdout
, "\n");
1042 fprintf (stdout
, " operation %d\n", e
->X_op
);
1043 fprintf (stdout
, " add_number %ld (%lx)\n",
1044 (long) e
->X_add_number
, (long) e
->X_add_number
);
1045 if (e
->X_add_symbol
)
1047 fprintf (stdout
, " add_symbol ");
1048 ps (e
->X_add_symbol
);
1049 fprintf (stdout
, "\n");
1053 fprintf (stdout
, " op_symbol ");
1054 ps (e
->X_op_symbol
);
1055 fprintf (stdout
, "\n");
1063 fprintf (stdout
, "%s type %s%s",
1065 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1066 segment_name (S_GET_SEGMENT (s
)));
1075 static const type_names
[] =
1088 { BaseIndex
, "BaseIndex" },
1092 { Disp32S
, "d32s" },
1094 { InOutPortReg
, "InOutPortReg" },
1095 { ShiftCount
, "ShiftCount" },
1096 { Control
, "control reg" },
1097 { Test
, "test reg" },
1098 { Debug
, "debug reg" },
1099 { FloatReg
, "FReg" },
1100 { FloatAcc
, "FAcc" },
1104 { JumpAbsolute
, "Jump Absolute" },
1115 const struct type_name
*ty
;
1117 for (ty
= type_names
; ty
->mask
; ty
++)
1119 fprintf (stdout
, "%s, ", ty
->tname
);
1123 #endif /* DEBUG386 */
1126 tc_i386_force_relocation (fixp
)
1129 #ifdef BFD_ASSEMBLER
1130 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1131 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1136 return fixp
->fx_r_type
== 7;
1140 #ifdef BFD_ASSEMBLER
1141 static bfd_reloc_code_real_type reloc
1142 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1144 static bfd_reloc_code_real_type
1145 reloc (size
, pcrel
, sign
, other
)
1149 bfd_reloc_code_real_type other
;
1151 if (other
!= NO_RELOC
)
1157 as_bad (_("There are no unsigned pc-relative relocations"));
1160 case 1: return BFD_RELOC_8_PCREL
;
1161 case 2: return BFD_RELOC_16_PCREL
;
1162 case 4: return BFD_RELOC_32_PCREL
;
1164 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1171 case 4: return BFD_RELOC_X86_64_32S
;
1176 case 1: return BFD_RELOC_8
;
1177 case 2: return BFD_RELOC_16
;
1178 case 4: return BFD_RELOC_32
;
1179 case 8: return BFD_RELOC_64
;
1181 as_bad (_("can not do %s %d byte relocation"),
1182 sign
? "signed" : "unsigned", size
);
1186 return BFD_RELOC_NONE
;
1189 /* Here we decide which fixups can be adjusted to make them relative to
1190 the beginning of the section instead of the symbol. Basically we need
1191 to make sure that the dynamic relocations are done correctly, so in
1192 some cases we force the original symbol to be used. */
1195 tc_i386_fix_adjustable (fixP
)
1198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1199 /* Prevent all adjustments to global symbols, or else dynamic
1200 linking will not work correctly. */
1201 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1202 || S_IS_WEAK (fixP
->fx_addsy
)
1203 /* Don't adjust pc-relative references to merge sections in 64-bit
1205 || (use_rela_relocations
1206 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1210 /* adjust_reloc_syms doesn't know about the GOT. */
1211 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1212 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1213 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1214 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1215 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1216 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1217 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1218 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1223 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1224 #define BFD_RELOC_16 0
1225 #define BFD_RELOC_32 0
1226 #define BFD_RELOC_16_PCREL 0
1227 #define BFD_RELOC_32_PCREL 0
1228 #define BFD_RELOC_386_PLT32 0
1229 #define BFD_RELOC_386_GOT32 0
1230 #define BFD_RELOC_386_GOTOFF 0
1231 #define BFD_RELOC_X86_64_PLT32 0
1232 #define BFD_RELOC_X86_64_GOT32 0
1233 #define BFD_RELOC_X86_64_GOTPCREL 0
1236 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1239 intel_float_operand (mnemonic
)
1240 const char *mnemonic
;
1242 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1245 if (mnemonic
[0] == 'f')
1251 /* This is the guts of the machine-dependent assembler. LINE points to a
1252 machine dependent instruction. This function is supposed to emit
1253 the frags/bytes it assembles to. */
1260 char mnemonic
[MAX_MNEM_SIZE
];
1262 /* Initialize globals. */
1263 memset (&i
, '\0', sizeof (i
));
1264 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1265 i
.reloc
[j
] = NO_RELOC
;
1266 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1267 memset (im_expressions
, '\0', sizeof (im_expressions
));
1268 save_stack_p
= save_stack
;
1270 /* First parse an instruction mnemonic & call i386_operand for the operands.
1271 We assume that the scrubber has arranged it so that line[0] is the valid
1272 start of a (possibly prefixed) mnemonic. */
1274 line
= parse_insn (line
, mnemonic
);
1278 line
= parse_operands (line
, mnemonic
);
1282 /* Now we've parsed the mnemonic into a set of templates, and have the
1283 operands at hand. */
1285 /* All intel opcodes have reversed operands except for "bound" and
1286 "enter". We also don't reverse intersegment "jmp" and "call"
1287 instructions with 2 immediate operands so that the immediate segment
1288 precedes the offset, as it does when in AT&T mode. "enter" and the
1289 intersegment "jmp" and "call" instructions are the only ones that
1290 have two immediate operands. */
1291 if (intel_syntax
&& i
.operands
> 1
1292 && (strcmp (mnemonic
, "bound") != 0)
1293 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1299 if (i
.disp_operands
)
1302 /* Next, we find a template that matches the given insn,
1303 making sure the overlap of the given operands types is consistent
1304 with the template operand types. */
1306 if (!match_template ())
1309 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1312 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1313 i
.tm
.base_opcode
^= FloatR
;
1315 if (i
.tm
.opcode_modifier
& FWait
)
1316 if (!add_prefix (FWAIT_OPCODE
))
1319 /* Check string instruction segment overrides. */
1320 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1322 if (!check_string ())
1326 if (!process_suffix ())
1329 /* Make still unresolved immediate matches conform to size of immediate
1330 given in i.suffix. */
1331 if (!finalize_imm ())
1334 if (i
.types
[0] & Imm1
)
1335 i
.imm_operands
= 0; /* kludge for shift insns. */
1336 if (i
.types
[0] & ImplicitRegister
)
1338 if (i
.types
[1] & ImplicitRegister
)
1340 if (i
.types
[2] & ImplicitRegister
)
1343 if (i
.tm
.opcode_modifier
& ImmExt
)
1345 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1346 opcode suffix which is coded in the same place as an 8-bit
1347 immediate field would be. Here we fake an 8-bit immediate
1348 operand from the opcode suffix stored in tm.extension_opcode. */
1352 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1354 exp
= &im_expressions
[i
.imm_operands
++];
1355 i
.op
[i
.operands
].imms
= exp
;
1356 i
.types
[i
.operands
++] = Imm8
;
1357 exp
->X_op
= O_constant
;
1358 exp
->X_add_number
= i
.tm
.extension_opcode
;
1359 i
.tm
.extension_opcode
= None
;
1362 /* For insns with operands there are more diddles to do to the opcode. */
1365 if (!process_operands ())
1368 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1370 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1371 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1374 /* Handle conversion of 'int $3' --> special int3 insn. */
1375 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1377 i
.tm
.base_opcode
= INT3_OPCODE
;
1381 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1382 && i
.op
[0].disps
->X_op
== O_constant
)
1384 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1385 the absolute address given by the constant. Since ix86 jumps and
1386 calls are pc relative, we need to generate a reloc. */
1387 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1388 i
.op
[0].disps
->X_op
= O_symbol
;
1391 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1392 i
.rex
|= REX_MODE64
;
1394 /* For 8 bit registers we need an empty rex prefix. Also if the
1395 instruction already has a prefix, we need to convert old
1396 registers to new ones. */
1398 if (((i
.types
[0] & Reg8
) != 0
1399 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1400 || ((i
.types
[1] & Reg8
) != 0
1401 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1402 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1407 i
.rex
|= REX_OPCODE
;
1408 for (x
= 0; x
< 2; x
++)
1410 /* Look for 8 bit operand that uses old registers. */
1411 if ((i
.types
[x
] & Reg8
) != 0
1412 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1414 /* In case it is "hi" register, give up. */
1415 if (i
.op
[x
].regs
->reg_num
> 3)
1416 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1417 i
.op
[x
].regs
->reg_name
);
1419 /* Otherwise it is equivalent to the extended register.
1420 Since the encoding doesn't change this is merely
1421 cosmetic cleanup for debug output. */
1423 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1429 add_prefix (REX_OPCODE
| i
.rex
);
1431 /* We are ready to output the insn. */
1436 parse_insn (line
, mnemonic
)
1441 char *token_start
= l
;
1444 /* Non-zero if we found a prefix only acceptable with string insns. */
1445 const char *expecting_string_instruction
= NULL
;
1450 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1453 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1455 as_bad (_("no such instruction: `%s'"), token_start
);
1460 if (!is_space_char (*l
)
1461 && *l
!= END_OF_INSN
1462 && *l
!= PREFIX_SEPARATOR
1465 as_bad (_("invalid character %s in mnemonic"),
1466 output_invalid (*l
));
1469 if (token_start
== l
)
1471 if (*l
== PREFIX_SEPARATOR
)
1472 as_bad (_("expecting prefix; got nothing"));
1474 as_bad (_("expecting mnemonic; got nothing"));
1478 /* Look up instruction (or prefix) via hash table. */
1479 current_templates
= hash_find (op_hash
, mnemonic
);
1481 if (*l
!= END_OF_INSN
1482 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1483 && current_templates
1484 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1486 /* If we are in 16-bit mode, do not allow addr16 or data16.
1487 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1488 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1489 && flag_code
!= CODE_64BIT
1490 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1491 ^ (flag_code
== CODE_16BIT
)))
1493 as_bad (_("redundant %s prefix"),
1494 current_templates
->start
->name
);
1497 /* Add prefix, checking for repeated prefixes. */
1498 switch (add_prefix (current_templates
->start
->base_opcode
))
1503 expecting_string_instruction
= current_templates
->start
->name
;
1506 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1513 if (!current_templates
)
1515 /* See if we can get a match by trimming off a suffix. */
1518 case WORD_MNEM_SUFFIX
:
1519 case BYTE_MNEM_SUFFIX
:
1520 case QWORD_MNEM_SUFFIX
:
1521 i
.suffix
= mnem_p
[-1];
1523 current_templates
= hash_find (op_hash
, mnemonic
);
1525 case SHORT_MNEM_SUFFIX
:
1526 case LONG_MNEM_SUFFIX
:
1529 i
.suffix
= mnem_p
[-1];
1531 current_templates
= hash_find (op_hash
, mnemonic
);
1539 if (intel_float_operand (mnemonic
))
1540 i
.suffix
= SHORT_MNEM_SUFFIX
;
1542 i
.suffix
= LONG_MNEM_SUFFIX
;
1544 current_templates
= hash_find (op_hash
, mnemonic
);
1548 if (!current_templates
)
1550 as_bad (_("no such instruction: `%s'"), token_start
);
1555 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1557 /* Check for a branch hint. We allow ",pt" and ",pn" for
1558 predict taken and predict not taken respectively.
1559 I'm not sure that branch hints actually do anything on loop
1560 and jcxz insns (JumpByte) for current Pentium4 chips. They
1561 may work in the future and it doesn't hurt to accept them
1563 if (l
[0] == ',' && l
[1] == 'p')
1567 if (!add_prefix (DS_PREFIX_OPCODE
))
1571 else if (l
[2] == 'n')
1573 if (!add_prefix (CS_PREFIX_OPCODE
))
1579 /* Any other comma loses. */
1582 as_bad (_("invalid character %s in mnemonic"),
1583 output_invalid (*l
));
1587 /* Check if instruction is supported on specified architecture. */
1588 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1589 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1591 as_warn (_("`%s' is not supported on `%s'"),
1592 current_templates
->start
->name
, cpu_arch_name
);
1594 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1596 as_warn (_("use .code16 to ensure correct addressing mode"));
1599 /* Check for rep/repne without a string instruction. */
1600 if (expecting_string_instruction
1601 && !(current_templates
->start
->opcode_modifier
& IsString
))
1603 as_bad (_("expecting string instruction after `%s'"),
1604 expecting_string_instruction
);
1612 parse_operands (l
, mnemonic
)
1614 const char *mnemonic
;
1618 /* 1 if operand is pending after ','. */
1619 unsigned int expecting_operand
= 0;
1621 /* Non-zero if operand parens not balanced. */
1622 unsigned int paren_not_balanced
;
1624 while (*l
!= END_OF_INSN
)
1626 /* Skip optional white space before operand. */
1627 if (is_space_char (*l
))
1629 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1631 as_bad (_("invalid character %s before operand %d"),
1632 output_invalid (*l
),
1636 token_start
= l
; /* after white space */
1637 paren_not_balanced
= 0;
1638 while (paren_not_balanced
|| *l
!= ',')
1640 if (*l
== END_OF_INSN
)
1642 if (paren_not_balanced
)
1645 as_bad (_("unbalanced parenthesis in operand %d."),
1648 as_bad (_("unbalanced brackets in operand %d."),
1653 break; /* we are done */
1655 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1657 as_bad (_("invalid character %s in operand %d"),
1658 output_invalid (*l
),
1665 ++paren_not_balanced
;
1667 --paren_not_balanced
;
1672 ++paren_not_balanced
;
1674 --paren_not_balanced
;
1678 if (l
!= token_start
)
1679 { /* Yes, we've read in another operand. */
1680 unsigned int operand_ok
;
1681 this_operand
= i
.operands
++;
1682 if (i
.operands
> MAX_OPERANDS
)
1684 as_bad (_("spurious operands; (%d operands/instruction max)"),
1688 /* Now parse operand adding info to 'i' as we go along. */
1689 END_STRING_AND_SAVE (l
);
1693 i386_intel_operand (token_start
,
1694 intel_float_operand (mnemonic
));
1696 operand_ok
= i386_operand (token_start
);
1698 RESTORE_END_STRING (l
);
1704 if (expecting_operand
)
1706 expecting_operand_after_comma
:
1707 as_bad (_("expecting operand after ','; got nothing"));
1712 as_bad (_("expecting operand before ','; got nothing"));
1717 /* Now *l must be either ',' or END_OF_INSN. */
1720 if (*++l
== END_OF_INSN
)
1722 /* Just skip it, if it's \n complain. */
1723 goto expecting_operand_after_comma
;
1725 expecting_operand
= 1;
1734 union i386_op temp_op
;
1735 unsigned int temp_type
;
1736 RELOC_ENUM temp_reloc
;
1740 if (i
.operands
== 2)
1745 else if (i
.operands
== 3)
1750 temp_type
= i
.types
[xchg2
];
1751 i
.types
[xchg2
] = i
.types
[xchg1
];
1752 i
.types
[xchg1
] = temp_type
;
1753 temp_op
= i
.op
[xchg2
];
1754 i
.op
[xchg2
] = i
.op
[xchg1
];
1755 i
.op
[xchg1
] = temp_op
;
1756 temp_reloc
= i
.reloc
[xchg2
];
1757 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1758 i
.reloc
[xchg1
] = temp_reloc
;
1760 if (i
.mem_operands
== 2)
1762 const seg_entry
*temp_seg
;
1763 temp_seg
= i
.seg
[0];
1764 i
.seg
[0] = i
.seg
[1];
1765 i
.seg
[1] = temp_seg
;
1769 /* Try to ensure constant immediates are represented in the smallest
1774 char guess_suffix
= 0;
1778 guess_suffix
= i
.suffix
;
1779 else if (i
.reg_operands
)
1781 /* Figure out a suffix from the last register operand specified.
1782 We can't do this properly yet, ie. excluding InOutPortReg,
1783 but the following works for instructions with immediates.
1784 In any case, we can't set i.suffix yet. */
1785 for (op
= i
.operands
; --op
>= 0;)
1786 if (i
.types
[op
] & Reg
)
1788 if (i
.types
[op
] & Reg8
)
1789 guess_suffix
= BYTE_MNEM_SUFFIX
;
1790 else if (i
.types
[op
] & Reg16
)
1791 guess_suffix
= WORD_MNEM_SUFFIX
;
1792 else if (i
.types
[op
] & Reg32
)
1793 guess_suffix
= LONG_MNEM_SUFFIX
;
1794 else if (i
.types
[op
] & Reg64
)
1795 guess_suffix
= QWORD_MNEM_SUFFIX
;
1799 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1800 guess_suffix
= WORD_MNEM_SUFFIX
;
1802 for (op
= i
.operands
; --op
>= 0;)
1803 if (i
.types
[op
] & Imm
)
1805 switch (i
.op
[op
].imms
->X_op
)
1808 /* If a suffix is given, this operand may be shortened. */
1809 switch (guess_suffix
)
1811 case LONG_MNEM_SUFFIX
:
1812 i
.types
[op
] |= Imm32
| Imm64
;
1814 case WORD_MNEM_SUFFIX
:
1815 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1817 case BYTE_MNEM_SUFFIX
:
1818 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1822 /* If this operand is at most 16 bits, convert it
1823 to a signed 16 bit number before trying to see
1824 whether it will fit in an even smaller size.
1825 This allows a 16-bit operand such as $0xffe0 to
1826 be recognised as within Imm8S range. */
1827 if ((i
.types
[op
] & Imm16
)
1828 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1830 i
.op
[op
].imms
->X_add_number
=
1831 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1833 if ((i
.types
[op
] & Imm32
)
1834 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1837 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1838 ^ ((offsetT
) 1 << 31))
1839 - ((offsetT
) 1 << 31));
1841 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1843 /* We must avoid matching of Imm32 templates when 64bit
1844 only immediate is available. */
1845 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1846 i
.types
[op
] &= ~Imm32
;
1853 /* Symbols and expressions. */
1855 /* Convert symbolic operand to proper sizes for matching. */
1856 switch (guess_suffix
)
1858 case QWORD_MNEM_SUFFIX
:
1859 i
.types
[op
] = Imm64
| Imm32S
;
1861 case LONG_MNEM_SUFFIX
:
1862 i
.types
[op
] = Imm32
| Imm64
;
1864 case WORD_MNEM_SUFFIX
:
1865 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1868 case BYTE_MNEM_SUFFIX
:
1869 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1878 /* Try to use the smallest displacement type too. */
1884 for (op
= i
.operands
; --op
>= 0;)
1885 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1887 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1889 if (i
.types
[op
] & Disp16
)
1891 /* We know this operand is at most 16 bits, so
1892 convert to a signed 16 bit number before trying
1893 to see whether it will fit in an even smaller
1896 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1898 else if (i
.types
[op
] & Disp32
)
1900 /* We know this operand is at most 32 bits, so convert to a
1901 signed 32 bit number before trying to see whether it will
1902 fit in an even smaller size. */
1903 disp
&= (((offsetT
) 2 << 31) - 1);
1904 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1906 if (flag_code
== CODE_64BIT
)
1908 if (fits_in_signed_long (disp
))
1909 i
.types
[op
] |= Disp32S
;
1910 if (fits_in_unsigned_long (disp
))
1911 i
.types
[op
] |= Disp32
;
1913 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1914 && fits_in_signed_byte (disp
))
1915 i
.types
[op
] |= Disp8
;
1922 /* Points to template once we've found it. */
1924 unsigned int overlap0
, overlap1
, overlap2
;
1925 unsigned int found_reverse_match
;
1928 #define MATCH(overlap, given, template) \
1929 ((overlap & ~JumpAbsolute) \
1930 && (((given) & (BaseIndex | JumpAbsolute)) \
1931 == ((overlap) & (BaseIndex | JumpAbsolute))))
1933 /* If given types r0 and r1 are registers they must be of the same type
1934 unless the expected operand type register overlap is null.
1935 Note that Acc in a template matches every size of reg. */
1936 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1937 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1938 || ((g0) & Reg) == ((g1) & Reg) \
1939 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1944 found_reverse_match
= 0;
1945 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1947 : (i
.suffix
== WORD_MNEM_SUFFIX
1949 : (i
.suffix
== SHORT_MNEM_SUFFIX
1951 : (i
.suffix
== LONG_MNEM_SUFFIX
1953 : (i
.suffix
== QWORD_MNEM_SUFFIX
1955 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1956 ? No_xSuf
: 0))))));
1958 for (t
= current_templates
->start
;
1959 t
< current_templates
->end
;
1962 /* Must have right number of operands. */
1963 if (i
.operands
!= t
->operands
)
1966 /* Check the suffix, except for some instructions in intel mode. */
1967 if ((t
->opcode_modifier
& suffix_check
)
1969 && (t
->opcode_modifier
& IgnoreSize
))
1971 && t
->base_opcode
== 0xd9
1972 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1973 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1976 /* Do not verify operands when there are none. */
1977 else if (!t
->operands
)
1979 if (t
->cpu_flags
& ~cpu_arch_flags
)
1981 /* We've found a match; break out of loop. */
1985 overlap0
= i
.types
[0] & t
->operand_types
[0];
1986 switch (t
->operands
)
1989 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1994 overlap1
= i
.types
[1] & t
->operand_types
[1];
1995 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1996 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1997 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1998 t
->operand_types
[0],
1999 overlap1
, i
.types
[1],
2000 t
->operand_types
[1]))
2002 /* Check if other direction is valid ... */
2003 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2006 /* Try reversing direction of operands. */
2007 overlap0
= i
.types
[0] & t
->operand_types
[1];
2008 overlap1
= i
.types
[1] & t
->operand_types
[0];
2009 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2010 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2011 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2012 t
->operand_types
[1],
2013 overlap1
, i
.types
[1],
2014 t
->operand_types
[0]))
2016 /* Does not match either direction. */
2019 /* found_reverse_match holds which of D or FloatDR
2021 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2023 /* Found a forward 2 operand match here. */
2024 else if (t
->operands
== 3)
2026 /* Here we make use of the fact that there are no
2027 reverse match 3 operand instructions, and all 3
2028 operand instructions only need to be checked for
2029 register consistency between operands 2 and 3. */
2030 overlap2
= i
.types
[2] & t
->operand_types
[2];
2031 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2032 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2033 t
->operand_types
[1],
2034 overlap2
, i
.types
[2],
2035 t
->operand_types
[2]))
2039 /* Found either forward/reverse 2 or 3 operand match here:
2040 slip through to break. */
2042 if (t
->cpu_flags
& ~cpu_arch_flags
)
2044 found_reverse_match
= 0;
2047 /* We've found a match; break out of loop. */
2051 if (t
== current_templates
->end
)
2053 /* We found no match. */
2054 as_bad (_("suffix or operands invalid for `%s'"),
2055 current_templates
->start
->name
);
2059 if (!quiet_warnings
)
2062 && ((i
.types
[0] & JumpAbsolute
)
2063 != (t
->operand_types
[0] & JumpAbsolute
)))
2065 as_warn (_("indirect %s without `*'"), t
->name
);
2068 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2069 == (IsPrefix
| IgnoreSize
))
2071 /* Warn them that a data or address size prefix doesn't
2072 affect assembly of the next line of code. */
2073 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2077 /* Copy the template we found. */
2079 if (found_reverse_match
)
2081 /* If we found a reverse match we must alter the opcode
2082 direction bit. found_reverse_match holds bits to change
2083 (different for int & float insns). */
2085 i
.tm
.base_opcode
^= found_reverse_match
;
2087 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2088 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2097 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2098 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2100 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2102 as_bad (_("`%s' operand %d must use `%%es' segment"),
2107 /* There's only ever one segment override allowed per instruction.
2108 This instruction possibly has a legal segment override on the
2109 second operand, so copy the segment to where non-string
2110 instructions store it, allowing common code. */
2111 i
.seg
[0] = i
.seg
[1];
2113 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2115 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2117 as_bad (_("`%s' operand %d must use `%%es' segment"),
2129 /* If matched instruction specifies an explicit instruction mnemonic
2131 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2133 if (i
.tm
.opcode_modifier
& Size16
)
2134 i
.suffix
= WORD_MNEM_SUFFIX
;
2135 else if (i
.tm
.opcode_modifier
& Size64
)
2136 i
.suffix
= QWORD_MNEM_SUFFIX
;
2138 i
.suffix
= LONG_MNEM_SUFFIX
;
2140 else if (i
.reg_operands
)
2142 /* If there's no instruction mnemonic suffix we try to invent one
2143 based on register operands. */
2146 /* We take i.suffix from the last register operand specified,
2147 Destination register type is more significant than source
2150 for (op
= i
.operands
; --op
>= 0;)
2151 if ((i
.types
[op
] & Reg
)
2152 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2154 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2155 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2156 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2161 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2163 if (!check_byte_reg ())
2166 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2168 if (!check_long_reg ())
2171 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2173 if (!check_qword_reg ())
2176 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2178 if (!check_word_reg ())
2181 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2182 /* Do nothing if the instruction is going to ignore the prefix. */
2187 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2189 i
.suffix
= stackop_size
;
2192 /* Change the opcode based on the operand size given by i.suffix;
2193 We need not change things for byte insns. */
2195 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2197 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2201 /* For movzx and movsx, need to check the register type. */
2203 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2204 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2206 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2208 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2209 if (!add_prefix (prefix
))
2213 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2215 /* It's not a byte, select word/dword operation. */
2216 if (i
.tm
.opcode_modifier
& W
)
2218 if (i
.tm
.opcode_modifier
& ShortForm
)
2219 i
.tm
.base_opcode
|= 8;
2221 i
.tm
.base_opcode
|= 1;
2223 /* Now select between word & dword operations via the operand
2224 size prefix, except for instructions that will ignore this
2226 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2227 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2228 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2230 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2231 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2232 prefix
= ADDR_PREFIX_OPCODE
;
2234 if (!add_prefix (prefix
))
2238 if (i
.suffix
!= QWORD_MNEM_SUFFIX
&& (flag_code
== CODE_64BIT
)
2239 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2240 && (i
.tm
.opcode_modifier
& JumpByte
))
2242 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2246 /* Set mode64 for an operand. */
2247 if (i
.suffix
== QWORD_MNEM_SUFFIX
2248 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2250 i
.rex
|= REX_MODE64
;
2251 if (flag_code
< CODE_64BIT
)
2253 as_bad (_("64bit operations available only in 64bit modes."));
2258 /* Size floating point instruction. */
2259 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2261 if (i
.tm
.opcode_modifier
& FloatMF
)
2262 i
.tm
.base_opcode
^= 4;
2273 for (op
= i
.operands
; --op
>= 0;)
2275 /* If this is an eight bit register, it's OK. If it's the 16 or
2276 32 bit version of an eight bit register, we will just use the
2277 low portion, and that's OK too. */
2278 if (i
.types
[op
] & Reg8
)
2281 /* movzx and movsx should not generate this warning. */
2283 && (i
.tm
.base_opcode
== 0xfb7
2284 || i
.tm
.base_opcode
== 0xfb6
2285 || i
.tm
.base_opcode
== 0x63
2286 || i
.tm
.base_opcode
== 0xfbe
2287 || i
.tm
.base_opcode
== 0xfbf))
2290 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2292 /* Check that the template allows eight bit regs. This
2293 kills insns such as `orb $1,%edx', which maybe should be
2295 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2299 /* Prohibit these changes in the 64bit mode, since the
2300 lowering is more complicated. */
2301 if (flag_code
== CODE_64BIT
2302 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2304 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2305 i
.op
[op
].regs
->reg_name
,
2309 #if REGISTER_WARNINGS
2311 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2312 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2313 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2314 ? REGNAM_AL
- REGNAM_AX
2315 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2316 i
.op
[op
].regs
->reg_name
,
2321 /* Any other register is bad. */
2322 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2324 | Control
| Debug
| Test
2325 | FloatReg
| FloatAcc
))
2327 as_bad (_("`%%%s' not allowed with `%s%c'"),
2328 i
.op
[op
].regs
->reg_name
,
2342 for (op
= i
.operands
; --op
>= 0;)
2343 /* Reject eight bit registers, except where the template requires
2344 them. (eg. movzb) */
2345 if ((i
.types
[op
] & Reg8
) != 0
2346 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2348 as_bad (_("`%%%s' not allowed with `%s%c'"),
2349 i
.op
[op
].regs
->reg_name
,
2354 /* Warn if the e prefix on a general reg is missing. */
2355 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2356 && (i
.types
[op
] & Reg16
) != 0
2357 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2359 /* Prohibit these changes in the 64bit mode, since the
2360 lowering is more complicated. */
2361 if (flag_code
== CODE_64BIT
)
2363 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2364 i
.op
[op
].regs
->reg_name
,
2368 #if REGISTER_WARNINGS
2370 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2371 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2372 i
.op
[op
].regs
->reg_name
,
2376 /* Warn if the r prefix on a general reg is missing. */
2377 else if ((i
.types
[op
] & Reg64
) != 0
2378 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2380 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2381 i
.op
[op
].regs
->reg_name
,
2393 for (op
= i
.operands
; --op
>= 0; )
2394 /* Reject eight bit registers, except where the template requires
2395 them. (eg. movzb) */
2396 if ((i
.types
[op
] & Reg8
) != 0
2397 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2399 as_bad (_("`%%%s' not allowed with `%s%c'"),
2400 i
.op
[op
].regs
->reg_name
,
2405 /* Warn if the e prefix on a general reg is missing. */
2406 else if (((i
.types
[op
] & Reg16
) != 0
2407 || (i
.types
[op
] & Reg32
) != 0)
2408 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2410 /* Prohibit these changes in the 64bit mode, since the
2411 lowering is more complicated. */
2412 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2413 i
.op
[op
].regs
->reg_name
,
2424 for (op
= i
.operands
; --op
>= 0;)
2425 /* Reject eight bit registers, except where the template requires
2426 them. (eg. movzb) */
2427 if ((i
.types
[op
] & Reg8
) != 0
2428 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2430 as_bad (_("`%%%s' not allowed with `%s%c'"),
2431 i
.op
[op
].regs
->reg_name
,
2436 /* Warn if the e prefix on a general reg is present. */
2437 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2438 && (i
.types
[op
] & Reg32
) != 0
2439 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2441 /* Prohibit these changes in the 64bit mode, since the
2442 lowering is more complicated. */
2443 if (flag_code
== CODE_64BIT
)
2445 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2446 i
.op
[op
].regs
->reg_name
,
2451 #if REGISTER_WARNINGS
2452 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2453 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2454 i
.op
[op
].regs
->reg_name
,
2464 unsigned int overlap0
, overlap1
, overlap2
;
2466 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2467 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2468 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2469 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2470 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2474 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2476 : (i
.suffix
== WORD_MNEM_SUFFIX
2478 : (i
.suffix
== QWORD_MNEM_SUFFIX
2482 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2483 || overlap0
== (Imm16
| Imm32
)
2484 || overlap0
== (Imm16
| Imm32S
))
2486 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2489 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2490 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2491 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2493 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2497 i
.types
[0] = overlap0
;
2499 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2500 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2501 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2502 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2503 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2507 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2509 : (i
.suffix
== WORD_MNEM_SUFFIX
2511 : (i
.suffix
== QWORD_MNEM_SUFFIX
2515 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2516 || overlap1
== (Imm16
| Imm32
)
2517 || overlap1
== (Imm16
| Imm32S
))
2519 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2522 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2523 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2524 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2526 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2530 i
.types
[1] = overlap1
;
2532 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2533 assert ((overlap2
& Imm
) == 0);
2534 i
.types
[2] = overlap2
;
2542 /* Default segment register this instruction will use for memory
2543 accesses. 0 means unknown. This is only for optimizing out
2544 unnecessary segment overrides. */
2545 const seg_entry
*default_seg
= 0;
2547 /* The imul $imm, %reg instruction is converted into
2548 imul $imm, %reg, %reg, and the clr %reg instruction
2549 is converted into xor %reg, %reg. */
2550 if (i
.tm
.opcode_modifier
& regKludge
)
2552 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2553 /* Pretend we saw the extra register operand. */
2554 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2555 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2556 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2560 if (i
.tm
.opcode_modifier
& ShortForm
)
2562 /* The register or float register operand is in operand 0 or 1. */
2563 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2564 /* Register goes in low 3 bits of opcode. */
2565 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2566 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2568 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2570 /* Warn about some common errors, but press on regardless.
2571 The first case can be generated by gcc (<= 2.8.1). */
2572 if (i
.operands
== 2)
2574 /* Reversed arguments on faddp, fsubp, etc. */
2575 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2576 i
.op
[1].regs
->reg_name
,
2577 i
.op
[0].regs
->reg_name
);
2581 /* Extraneous `l' suffix on fp insn. */
2582 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2583 i
.op
[0].regs
->reg_name
);
2587 else if (i
.tm
.opcode_modifier
& Modrm
)
2589 /* The opcode is completed (modulo i.tm.extension_opcode which
2590 must be put into the modrm byte).
2591 Now, we make the modrm & index base bytes based on all the
2592 info we've collected. */
2594 default_seg
= build_modrm_byte ();
2596 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2598 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2599 && i
.op
[0].regs
->reg_num
== 1)
2601 as_bad (_("you can't `pop %%cs'"));
2604 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2605 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2608 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2612 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2614 /* For the string instructions that allow a segment override
2615 on one of their operands, the default segment is ds. */
2619 /* If a segment was explicitly specified,
2620 and the specified segment is not the default,
2621 use an opcode prefix to select it.
2622 If we never figured out what the default segment is,
2623 then default_seg will be zero at this point,
2624 and the specified segment prefix will always be used. */
2625 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2627 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2633 static const seg_entry
*
2636 const seg_entry
*default_seg
= 0;
2638 /* i.reg_operands MUST be the number of real register operands;
2639 implicit registers do not count. */
2640 if (i
.reg_operands
== 2)
2642 unsigned int source
, dest
;
2643 source
= ((i
.types
[0]
2644 & (Reg
| RegMMX
| RegXMM
2646 | Control
| Debug
| Test
))
2651 /* One of the register operands will be encoded in the i.tm.reg
2652 field, the other in the combined i.tm.mode and i.tm.regmem
2653 fields. If no form of this instruction supports a memory
2654 destination operand, then we assume the source operand may
2655 sometimes be a memory operand and so we need to store the
2656 destination in the i.rm.reg field. */
2657 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2659 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2660 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2661 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2663 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2668 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2669 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2670 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2672 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2677 { /* If it's not 2 reg operands... */
2680 unsigned int fake_zero_displacement
= 0;
2681 unsigned int op
= ((i
.types
[0] & AnyMem
)
2683 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2687 if (i
.base_reg
== 0)
2690 if (!i
.disp_operands
)
2691 fake_zero_displacement
= 1;
2692 if (i
.index_reg
== 0)
2694 /* Operand is just <disp> */
2695 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2696 && (flag_code
!= CODE_64BIT
))
2698 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2699 i
.types
[op
] &= ~Disp
;
2700 i
.types
[op
] |= Disp16
;
2702 else if (flag_code
!= CODE_64BIT
2703 || (i
.prefix
[ADDR_PREFIX
] != 0))
2705 i
.rm
.regmem
= NO_BASE_REGISTER
;
2706 i
.types
[op
] &= ~Disp
;
2707 i
.types
[op
] |= Disp32
;
2711 /* 64bit mode overwrites the 32bit absolute
2712 addressing by RIP relative addressing and
2713 absolute addressing is encoded by one of the
2714 redundant SIB forms. */
2715 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2716 i
.sib
.base
= NO_BASE_REGISTER
;
2717 i
.sib
.index
= NO_INDEX_REGISTER
;
2718 i
.types
[op
] &= ~Disp
;
2719 i
.types
[op
] |= Disp32S
;
2722 else /* !i.base_reg && i.index_reg */
2724 i
.sib
.index
= i
.index_reg
->reg_num
;
2725 i
.sib
.base
= NO_BASE_REGISTER
;
2726 i
.sib
.scale
= i
.log2_scale_factor
;
2727 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2728 i
.types
[op
] &= ~Disp
;
2729 if (flag_code
!= CODE_64BIT
)
2730 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2732 i
.types
[op
] |= Disp32S
;
2733 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2737 /* RIP addressing for 64bit mode. */
2738 else if (i
.base_reg
->reg_type
== BaseIndex
)
2740 i
.rm
.regmem
= NO_BASE_REGISTER
;
2741 i
.types
[op
] &= ~Disp
;
2742 i
.types
[op
] |= Disp32S
;
2743 i
.flags
[op
] = Operand_PCrel
;
2745 else if (i
.base_reg
->reg_type
& Reg16
)
2747 switch (i
.base_reg
->reg_num
)
2750 if (i
.index_reg
== 0)
2752 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2753 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2757 if (i
.index_reg
== 0)
2760 if ((i
.types
[op
] & Disp
) == 0)
2762 /* fake (%bp) into 0(%bp) */
2763 i
.types
[op
] |= Disp8
;
2764 fake_zero_displacement
= 1;
2767 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2768 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2770 default: /* (%si) -> 4 or (%di) -> 5 */
2771 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2773 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2775 else /* i.base_reg and 32/64 bit mode */
2777 if (flag_code
== CODE_64BIT
2778 && (i
.types
[op
] & Disp
))
2780 if (i
.types
[op
] & Disp8
)
2781 i
.types
[op
] = Disp8
| Disp32S
;
2783 i
.types
[op
] = Disp32S
;
2785 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2786 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2788 i
.sib
.base
= i
.base_reg
->reg_num
;
2789 /* x86-64 ignores REX prefix bit here to avoid decoder
2791 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2794 if (i
.disp_operands
== 0)
2796 fake_zero_displacement
= 1;
2797 i
.types
[op
] |= Disp8
;
2800 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2804 i
.sib
.scale
= i
.log2_scale_factor
;
2805 if (i
.index_reg
== 0)
2807 /* <disp>(%esp) becomes two byte modrm with no index
2808 register. We've already stored the code for esp
2809 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2810 Any base register besides %esp will not use the
2811 extra modrm byte. */
2812 i
.sib
.index
= NO_INDEX_REGISTER
;
2813 #if !SCALE1_WHEN_NO_INDEX
2814 /* Another case where we force the second modrm byte. */
2815 if (i
.log2_scale_factor
)
2816 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2821 i
.sib
.index
= i
.index_reg
->reg_num
;
2822 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2823 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2826 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2829 if (fake_zero_displacement
)
2831 /* Fakes a zero displacement assuming that i.types[op]
2832 holds the correct displacement size. */
2835 assert (i
.op
[op
].disps
== 0);
2836 exp
= &disp_expressions
[i
.disp_operands
++];
2837 i
.op
[op
].disps
= exp
;
2838 exp
->X_op
= O_constant
;
2839 exp
->X_add_number
= 0;
2840 exp
->X_add_symbol
= (symbolS
*) 0;
2841 exp
->X_op_symbol
= (symbolS
*) 0;
2845 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2846 (if any) based on i.tm.extension_opcode. Again, we must be
2847 careful to make sure that segment/control/debug/test/MMX
2848 registers are coded into the i.rm.reg field. */
2853 & (Reg
| RegMMX
| RegXMM
2855 | Control
| Debug
| Test
))
2858 & (Reg
| RegMMX
| RegXMM
2860 | Control
| Debug
| Test
))
2863 /* If there is an extension opcode to put here, the register
2864 number must be put into the regmem field. */
2865 if (i
.tm
.extension_opcode
!= None
)
2867 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2868 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2873 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2874 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2878 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2879 must set it to 3 to indicate this is a register operand
2880 in the regmem field. */
2881 if (!i
.mem_operands
)
2885 /* Fill in i.rm.reg field with extension opcode (if any). */
2886 if (i
.tm
.extension_opcode
!= None
)
2887 i
.rm
.reg
= i
.tm
.extension_opcode
;
2898 relax_substateT subtype
;
2903 if (flag_code
== CODE_16BIT
)
2907 if (i
.prefix
[DATA_PREFIX
] != 0)
2913 /* Pentium4 branch hints. */
2914 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2915 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2920 if (i
.prefix
[REX_PREFIX
] != 0)
2926 if (i
.prefixes
!= 0 && !intel_syntax
)
2927 as_warn (_("skipping prefixes on this instruction"));
2929 /* It's always a symbol; End frag & setup for relax.
2930 Make sure there is enough room in this frag for the largest
2931 instruction we may generate in md_convert_frag. This is 2
2932 bytes for the opcode and room for the prefix and largest
2934 frag_grow (prefix
+ 2 + 4);
2935 /* Prefix and 1 opcode byte go in fr_fix. */
2936 p
= frag_more (prefix
+ 1);
2937 if (i
.prefix
[DATA_PREFIX
] != 0)
2938 *p
++ = DATA_PREFIX_OPCODE
;
2939 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2940 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2941 *p
++ = i
.prefix
[SEG_PREFIX
];
2942 if (i
.prefix
[REX_PREFIX
] != 0)
2943 *p
++ = i
.prefix
[REX_PREFIX
];
2944 *p
= i
.tm
.base_opcode
;
2946 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2947 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2948 else if ((cpu_arch_flags
& Cpu386
) != 0)
2949 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2951 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2954 sym
= i
.op
[0].disps
->X_add_symbol
;
2955 off
= i
.op
[0].disps
->X_add_number
;
2957 if (i
.op
[0].disps
->X_op
!= O_constant
2958 && i
.op
[0].disps
->X_op
!= O_symbol
)
2960 /* Handle complex expressions. */
2961 sym
= make_expr_symbol (i
.op
[0].disps
);
2965 /* 1 possible extra opcode + 4 byte displacement go in var part.
2966 Pass reloc in fr_var. */
2967 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2977 if (i
.tm
.opcode_modifier
& JumpByte
)
2979 /* This is a loop or jecxz type instruction. */
2981 if (i
.prefix
[ADDR_PREFIX
] != 0)
2983 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2986 /* Pentium4 branch hints. */
2987 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2988 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2990 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2999 if (flag_code
== CODE_16BIT
)
3002 if (i
.prefix
[DATA_PREFIX
] != 0)
3004 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3014 if (i
.prefix
[REX_PREFIX
] != 0)
3016 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3020 if (i
.prefixes
!= 0 && !intel_syntax
)
3021 as_warn (_("skipping prefixes on this instruction"));
3023 p
= frag_more (1 + size
);
3024 *p
++ = i
.tm
.base_opcode
;
3026 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3027 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3028 fixP
->fx_pcrel_adjust
= size
;
3032 output_interseg_jump ()
3040 if (flag_code
== CODE_16BIT
)
3044 if (i
.prefix
[DATA_PREFIX
] != 0)
3050 if (i
.prefix
[REX_PREFIX
] != 0)
3060 if (i
.prefixes
!= 0 && !intel_syntax
)
3061 as_warn (_("skipping prefixes on this instruction"));
3063 /* 1 opcode; 2 segment; offset */
3064 p
= frag_more (prefix
+ 1 + 2 + size
);
3066 if (i
.prefix
[DATA_PREFIX
] != 0)
3067 *p
++ = DATA_PREFIX_OPCODE
;
3069 if (i
.prefix
[REX_PREFIX
] != 0)
3070 *p
++ = i
.prefix
[REX_PREFIX
];
3072 *p
++ = i
.tm
.base_opcode
;
3073 if (i
.op
[1].imms
->X_op
== O_constant
)
3075 offsetT n
= i
.op
[1].imms
->X_add_number
;
3078 && !fits_in_unsigned_word (n
)
3079 && !fits_in_signed_word (n
))
3081 as_bad (_("16-bit jump out of range"));
3084 md_number_to_chars (p
, n
, size
);
3087 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3088 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3089 if (i
.op
[0].imms
->X_op
!= O_constant
)
3090 as_bad (_("can't handle non absolute segment in `%s'"),
3092 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3098 /* Tie dwarf2 debug info to the address at the start of the insn.
3099 We can't do this after the insn has been output as the current
3100 frag may have been closed off. eg. by frag_var. */
3101 dwarf2_emit_insn (0);
3104 if (i
.tm
.opcode_modifier
& Jump
)
3106 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3108 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3109 output_interseg_jump ();
3112 /* Output normal instructions here. */
3116 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3117 byte for the SSE instructions to specify a prefix they require. */
3118 if (i
.tm
.base_opcode
& 0xff0000)
3119 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3121 /* The prefix bytes. */
3123 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3129 md_number_to_chars (p
, (valueT
) *q
, 1);
3133 /* Now the opcode; be careful about word order here! */
3134 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3136 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3141 /* Put out high byte first: can't use md_number_to_chars! */
3142 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3143 *p
= i
.tm
.base_opcode
& 0xff;
3146 /* Now the modrm byte and sib byte (if present). */
3147 if (i
.tm
.opcode_modifier
& Modrm
)
3150 md_number_to_chars (p
,
3151 (valueT
) (i
.rm
.regmem
<< 0
3155 /* If i.rm.regmem == ESP (4)
3156 && i.rm.mode != (Register mode)
3158 ==> need second modrm byte. */
3159 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3161 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3164 md_number_to_chars (p
,
3165 (valueT
) (i
.sib
.base
<< 0
3167 | i
.sib
.scale
<< 6),
3172 if (i
.disp_operands
)
3184 #endif /* DEBUG386 */
3193 for (n
= 0; n
< i
.operands
; n
++)
3195 if (i
.types
[n
] & Disp
)
3197 if (i
.op
[n
].disps
->X_op
== O_constant
)
3203 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3206 if (i
.types
[n
] & Disp8
)
3208 if (i
.types
[n
] & Disp64
)
3211 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3213 p
= frag_more (size
);
3214 md_number_to_chars (p
, val
, size
);
3220 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3223 /* The PC relative address is computed relative
3224 to the instruction boundary, so in case immediate
3225 fields follows, we need to adjust the value. */
3226 if (pcrel
&& i
.imm_operands
)
3231 for (n1
= 0; n1
< i
.operands
; n1
++)
3232 if (i
.types
[n1
] & Imm
)
3234 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3237 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3239 if (i
.types
[n1
] & Imm64
)
3244 /* We should find the immediate. */
3245 if (n1
== i
.operands
)
3247 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3250 if (i
.types
[n
] & Disp32S
)
3253 if (i
.types
[n
] & (Disp16
| Disp64
))
3256 if (i
.types
[n
] & Disp64
)
3260 p
= frag_more (size
);
3261 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3262 i
.op
[n
].disps
, pcrel
,
3263 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3265 fixP
->fx_pcrel_adjust
= size
;
3277 for (n
= 0; n
< i
.operands
; n
++)
3279 if (i
.types
[n
] & Imm
)
3281 if (i
.op
[n
].imms
->X_op
== O_constant
)
3287 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3290 if (i
.types
[n
] & (Imm8
| Imm8S
))
3292 else if (i
.types
[n
] & Imm64
)
3295 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3297 p
= frag_more (size
);
3298 md_number_to_chars (p
, val
, size
);
3302 /* Not absolute_section.
3303 Need a 32-bit fixup (don't support 8bit
3304 non-absolute imms). Try to support other
3306 RELOC_ENUM reloc_type
;
3310 if ((i
.types
[n
] & (Imm32S
))
3311 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3313 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3316 if (i
.types
[n
] & (Imm8
| Imm8S
))
3318 if (i
.types
[n
] & Imm64
)
3322 p
= frag_more (size
);
3323 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3324 #ifdef BFD_ASSEMBLER
3325 if (reloc_type
== BFD_RELOC_32
3327 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3328 && (i
.op
[n
].imms
->X_op
== O_symbol
3329 || (i
.op
[n
].imms
->X_op
== O_add
3330 && ((symbol_get_value_expression
3331 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3334 /* We don't support dynamic linking on x86-64 yet. */
3335 if (flag_code
== CODE_64BIT
)
3337 reloc_type
= BFD_RELOC_386_GOTPC
;
3338 i
.op
[n
].imms
->X_add_number
+= 3;
3341 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3342 i
.op
[n
].imms
, 0, reloc_type
);
3349 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3351 /* Parse operands of the form
3352 <symbol>@GOTOFF+<nnn>
3353 and similar .plt or .got references.
3355 If we find one, set up the correct relocation in RELOC and copy the
3356 input string, minus the `@GOTOFF' into a malloc'd buffer for
3357 parsing by the calling routine. Return this buffer, and if ADJUST
3358 is non-null set it to the length of the string we removed from the
3359 input line. Otherwise return NULL. */
3361 lex_got (reloc
, adjust
)
3365 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3366 static const struct {
3368 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3370 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3371 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3372 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3373 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3378 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3379 if (is_end_of_line
[(unsigned char) *cp
])
3382 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3386 len
= strlen (gotrel
[j
].str
);
3387 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3389 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3392 char *tmpbuf
, *past_reloc
;
3394 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3398 if (GOT_symbol
== NULL
)
3399 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3401 /* Replace the relocation token with ' ', so that
3402 errors like foo@GOTOFF1 will be detected. */
3404 /* The length of the first part of our input line. */
3405 first
= cp
- input_line_pointer
;
3407 /* The second part goes from after the reloc token until
3408 (and including) an end_of_line char. Don't use strlen
3409 here as the end_of_line char may not be a NUL. */
3410 past_reloc
= cp
+ 1 + len
;
3411 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3413 second
= cp
- past_reloc
;
3415 /* Allocate and copy string. The trailing NUL shouldn't
3416 be necessary, but be safe. */
3417 tmpbuf
= xmalloc (first
+ second
+ 2);
3418 memcpy (tmpbuf
, input_line_pointer
, first
);
3419 tmpbuf
[first
] = ' ';
3420 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3421 tmpbuf
[first
+ second
+ 1] = '\0';
3425 as_bad (_("@%s reloc is not supported in %s bit mode"),
3426 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3431 /* Might be a symbol version string. Don't as_bad here. */
3435 /* x86_cons_fix_new is called via the expression parsing code when a
3436 reloc is needed. We use this hook to get the correct .got reloc. */
3437 static RELOC_ENUM got_reloc
= NO_RELOC
;
3440 x86_cons_fix_new (frag
, off
, len
, exp
)
3446 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3447 got_reloc
= NO_RELOC
;
3448 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3452 x86_cons (exp
, size
)
3458 /* Handle @GOTOFF and the like in an expression. */
3460 char *gotfree_input_line
;
3463 save
= input_line_pointer
;
3464 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3465 if (gotfree_input_line
)
3466 input_line_pointer
= gotfree_input_line
;
3470 if (gotfree_input_line
)
3472 /* expression () has merrily parsed up to the end of line,
3473 or a comma - in the wrong buffer. Transfer how far
3474 input_line_pointer has moved to the right buffer. */
3475 input_line_pointer
= (save
3476 + (input_line_pointer
- gotfree_input_line
)
3478 free (gotfree_input_line
);
3486 static int i386_immediate
PARAMS ((char *));
3489 i386_immediate (imm_start
)
3492 char *save_input_line_pointer
;
3494 char *gotfree_input_line
;
3499 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3501 as_bad (_("only 1 or 2 immediate operands are allowed"));
3505 exp
= &im_expressions
[i
.imm_operands
++];
3506 i
.op
[this_operand
].imms
= exp
;
3508 if (is_space_char (*imm_start
))
3511 save_input_line_pointer
= input_line_pointer
;
3512 input_line_pointer
= imm_start
;
3515 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3516 if (gotfree_input_line
)
3517 input_line_pointer
= gotfree_input_line
;
3520 exp_seg
= expression (exp
);
3523 if (*input_line_pointer
)
3524 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3526 input_line_pointer
= save_input_line_pointer
;
3528 if (gotfree_input_line
)
3529 free (gotfree_input_line
);
3532 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3534 /* Missing or bad expr becomes absolute 0. */
3535 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3537 exp
->X_op
= O_constant
;
3538 exp
->X_add_number
= 0;
3539 exp
->X_add_symbol
= (symbolS
*) 0;
3540 exp
->X_op_symbol
= (symbolS
*) 0;
3542 else if (exp
->X_op
== O_constant
)
3544 /* Size it properly later. */
3545 i
.types
[this_operand
] |= Imm64
;
3546 /* If BFD64, sign extend val. */
3547 if (!use_rela_relocations
)
3548 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3549 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3551 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3553 #ifdef BFD_ASSEMBLER
3554 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3556 && exp_seg
!= text_section
3557 && exp_seg
!= data_section
3558 && exp_seg
!= bss_section
3559 && exp_seg
!= undefined_section
3560 #ifdef BFD_ASSEMBLER
3561 && !bfd_is_com_section (exp_seg
)
3565 #ifdef BFD_ASSEMBLER
3566 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3568 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3575 /* This is an address. The size of the address will be
3576 determined later, depending on destination register,
3577 suffix, or the default for the section. */
3578 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3584 static char *i386_scale
PARAMS ((char *));
3591 char *save
= input_line_pointer
;
3593 input_line_pointer
= scale
;
3594 val
= get_absolute_expression ();
3600 i
.log2_scale_factor
= 0;
3603 i
.log2_scale_factor
= 1;
3606 i
.log2_scale_factor
= 2;
3609 i
.log2_scale_factor
= 3;
3612 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3614 input_line_pointer
= save
;
3617 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3619 as_warn (_("scale factor of %d without an index register"),
3620 1 << i
.log2_scale_factor
);
3621 #if SCALE1_WHEN_NO_INDEX
3622 i
.log2_scale_factor
= 0;
3625 scale
= input_line_pointer
;
3626 input_line_pointer
= save
;
3630 static int i386_displacement
PARAMS ((char *, char *));
3633 i386_displacement (disp_start
, disp_end
)
3639 char *save_input_line_pointer
;
3641 char *gotfree_input_line
;
3643 int bigdisp
= Disp32
;
3645 if (flag_code
== CODE_64BIT
)
3647 if (i
.prefix
[ADDR_PREFIX
] == 0)
3650 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3652 i
.types
[this_operand
] |= bigdisp
;
3654 exp
= &disp_expressions
[i
.disp_operands
];
3655 i
.op
[this_operand
].disps
= exp
;
3657 save_input_line_pointer
= input_line_pointer
;
3658 input_line_pointer
= disp_start
;
3659 END_STRING_AND_SAVE (disp_end
);
3661 #ifndef GCC_ASM_O_HACK
3662 #define GCC_ASM_O_HACK 0
3665 END_STRING_AND_SAVE (disp_end
+ 1);
3666 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3667 && displacement_string_end
[-1] == '+')
3669 /* This hack is to avoid a warning when using the "o"
3670 constraint within gcc asm statements.
3673 #define _set_tssldt_desc(n,addr,limit,type) \
3674 __asm__ __volatile__ ( \
3676 "movw %w1,2+%0\n\t" \
3678 "movb %b1,4+%0\n\t" \
3679 "movb %4,5+%0\n\t" \
3680 "movb $0,6+%0\n\t" \
3681 "movb %h1,7+%0\n\t" \
3683 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3685 This works great except that the output assembler ends
3686 up looking a bit weird if it turns out that there is
3687 no offset. You end up producing code that looks like:
3700 So here we provide the missing zero. */
3702 *displacement_string_end
= '0';
3706 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3707 if (gotfree_input_line
)
3708 input_line_pointer
= gotfree_input_line
;
3711 exp_seg
= expression (exp
);
3714 if (*input_line_pointer
)
3715 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3717 RESTORE_END_STRING (disp_end
+ 1);
3719 RESTORE_END_STRING (disp_end
);
3720 input_line_pointer
= save_input_line_pointer
;
3722 if (gotfree_input_line
)
3723 free (gotfree_input_line
);
3726 #ifdef BFD_ASSEMBLER
3727 /* We do this to make sure that the section symbol is in
3728 the symbol table. We will ultimately change the relocation
3729 to be relative to the beginning of the section. */
3730 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3731 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3733 if (exp
->X_op
!= O_symbol
)
3735 as_bad (_("bad expression used with @%s"),
3736 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3742 if (S_IS_LOCAL (exp
->X_add_symbol
)
3743 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3744 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3745 exp
->X_op
= O_subtract
;
3746 exp
->X_op_symbol
= GOT_symbol
;
3747 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3748 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3750 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3754 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3756 /* Missing or bad expr becomes absolute 0. */
3757 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3759 exp
->X_op
= O_constant
;
3760 exp
->X_add_number
= 0;
3761 exp
->X_add_symbol
= (symbolS
*) 0;
3762 exp
->X_op_symbol
= (symbolS
*) 0;
3765 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3766 if (exp
->X_op
!= O_constant
3767 #ifdef BFD_ASSEMBLER
3768 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3770 && exp_seg
!= text_section
3771 && exp_seg
!= data_section
3772 && exp_seg
!= bss_section
3773 && exp_seg
!= undefined_section
)
3775 #ifdef BFD_ASSEMBLER
3776 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3778 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3783 else if (flag_code
== CODE_64BIT
)
3784 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3788 static int i386_index_check
PARAMS ((const char *));
3790 /* Make sure the memory operand we've been dealt is valid.
3791 Return 1 on success, 0 on a failure. */
3794 i386_index_check (operand_string
)
3795 const char *operand_string
;
3798 #if INFER_ADDR_PREFIX
3804 if (flag_code
== CODE_64BIT
)
3806 if (i
.prefix
[ADDR_PREFIX
] == 0)
3810 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3811 && (i
.base_reg
->reg_type
!= BaseIndex
3814 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3815 != (Reg64
| BaseIndex
))))
3822 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3824 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3825 != (Reg32
| BaseIndex
))))
3831 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3835 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3836 != (Reg16
| BaseIndex
)))
3838 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3839 != (Reg16
| BaseIndex
))
3841 && i
.base_reg
->reg_num
< 6
3842 && i
.index_reg
->reg_num
>= 6
3843 && i
.log2_scale_factor
== 0))))
3850 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3852 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3853 != (Reg32
| BaseIndex
))))
3859 #if INFER_ADDR_PREFIX
3860 if (flag_code
!= CODE_64BIT
3861 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3863 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3865 /* Change the size of any displacement too. At most one of
3866 Disp16 or Disp32 is set.
3867 FIXME. There doesn't seem to be any real need for separate
3868 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3869 Removing them would probably clean up the code quite a lot. */
3870 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3871 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3876 as_bad (_("`%s' is not a valid base/index expression"),
3880 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3882 flag_code_names
[flag_code
]);
3888 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3892 i386_operand (operand_string
)
3893 char *operand_string
;
3897 char *op_string
= operand_string
;
3899 if (is_space_char (*op_string
))
3902 /* We check for an absolute prefix (differentiating,
3903 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3904 if (*op_string
== ABSOLUTE_PREFIX
)
3907 if (is_space_char (*op_string
))
3909 i
.types
[this_operand
] |= JumpAbsolute
;
3912 /* Check if operand is a register. */
3913 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3914 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3916 /* Check for a segment override by searching for ':' after a
3917 segment register. */
3919 if (is_space_char (*op_string
))
3921 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3926 i
.seg
[i
.mem_operands
] = &es
;
3929 i
.seg
[i
.mem_operands
] = &cs
;
3932 i
.seg
[i
.mem_operands
] = &ss
;
3935 i
.seg
[i
.mem_operands
] = &ds
;
3938 i
.seg
[i
.mem_operands
] = &fs
;
3941 i
.seg
[i
.mem_operands
] = &gs
;
3945 /* Skip the ':' and whitespace. */
3947 if (is_space_char (*op_string
))
3950 if (!is_digit_char (*op_string
)
3951 && !is_identifier_char (*op_string
)
3952 && *op_string
!= '('
3953 && *op_string
!= ABSOLUTE_PREFIX
)
3955 as_bad (_("bad memory operand `%s'"), op_string
);
3958 /* Handle case of %es:*foo. */
3959 if (*op_string
== ABSOLUTE_PREFIX
)
3962 if (is_space_char (*op_string
))
3964 i
.types
[this_operand
] |= JumpAbsolute
;
3966 goto do_memory_reference
;
3970 as_bad (_("junk `%s' after register"), op_string
);
3973 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3974 i
.op
[this_operand
].regs
= r
;
3977 else if (*op_string
== REGISTER_PREFIX
)
3979 as_bad (_("bad register name `%s'"), op_string
);
3982 else if (*op_string
== IMMEDIATE_PREFIX
)
3985 if (i
.types
[this_operand
] & JumpAbsolute
)
3987 as_bad (_("immediate operand illegal with absolute jump"));
3990 if (!i386_immediate (op_string
))
3993 else if (is_digit_char (*op_string
)
3994 || is_identifier_char (*op_string
)
3995 || *op_string
== '(')
3997 /* This is a memory reference of some sort. */
4000 /* Start and end of displacement string expression (if found). */
4001 char *displacement_string_start
;
4002 char *displacement_string_end
;
4004 do_memory_reference
:
4005 if ((i
.mem_operands
== 1
4006 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4007 || i
.mem_operands
== 2)
4009 as_bad (_("too many memory references for `%s'"),
4010 current_templates
->start
->name
);
4014 /* Check for base index form. We detect the base index form by
4015 looking for an ')' at the end of the operand, searching
4016 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4018 base_string
= op_string
+ strlen (op_string
);
4021 if (is_space_char (*base_string
))
4024 /* If we only have a displacement, set-up for it to be parsed later. */
4025 displacement_string_start
= op_string
;
4026 displacement_string_end
= base_string
+ 1;
4028 if (*base_string
== ')')
4031 unsigned int parens_balanced
= 1;
4032 /* We've already checked that the number of left & right ()'s are
4033 equal, so this loop will not be infinite. */
4037 if (*base_string
== ')')
4039 if (*base_string
== '(')
4042 while (parens_balanced
);
4044 temp_string
= base_string
;
4046 /* Skip past '(' and whitespace. */
4048 if (is_space_char (*base_string
))
4051 if (*base_string
== ','
4052 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4053 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4055 displacement_string_end
= temp_string
;
4057 i
.types
[this_operand
] |= BaseIndex
;
4061 base_string
= end_op
;
4062 if (is_space_char (*base_string
))
4066 /* There may be an index reg or scale factor here. */
4067 if (*base_string
== ',')
4070 if (is_space_char (*base_string
))
4073 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4074 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4076 base_string
= end_op
;
4077 if (is_space_char (*base_string
))
4079 if (*base_string
== ',')
4082 if (is_space_char (*base_string
))
4085 else if (*base_string
!= ')')
4087 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4092 else if (*base_string
== REGISTER_PREFIX
)
4094 as_bad (_("bad register name `%s'"), base_string
);
4098 /* Check for scale factor. */
4099 if (*base_string
!= ')')
4101 char *end_scale
= i386_scale (base_string
);
4106 base_string
= end_scale
;
4107 if (is_space_char (*base_string
))
4109 if (*base_string
!= ')')
4111 as_bad (_("expecting `)' after scale factor in `%s'"),
4116 else if (!i
.index_reg
)
4118 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4123 else if (*base_string
!= ')')
4125 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4130 else if (*base_string
== REGISTER_PREFIX
)
4132 as_bad (_("bad register name `%s'"), base_string
);
4137 /* If there's an expression beginning the operand, parse it,
4138 assuming displacement_string_start and
4139 displacement_string_end are meaningful. */
4140 if (displacement_string_start
!= displacement_string_end
)
4142 if (!i386_displacement (displacement_string_start
,
4143 displacement_string_end
))
4147 /* Special case for (%dx) while doing input/output op. */
4149 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4151 && i
.log2_scale_factor
== 0
4152 && i
.seg
[i
.mem_operands
] == 0
4153 && (i
.types
[this_operand
] & Disp
) == 0)
4155 i
.types
[this_operand
] = InOutPortReg
;
4159 if (i386_index_check (operand_string
) == 0)
4165 /* It's not a memory operand; argh! */
4166 as_bad (_("invalid char %s beginning operand %d `%s'"),
4167 output_invalid (*op_string
),
4172 return 1; /* Normal return. */
4175 /* md_estimate_size_before_relax()
4177 Called just before relax() for rs_machine_dependent frags. The x86
4178 assembler uses these frags to handle variable size jump
4181 Any symbol that is now undefined will not become defined.
4182 Return the correct fr_subtype in the frag.
4183 Return the initial "guess for variable size of frag" to caller.
4184 The guess is actually the growth beyond the fixed part. Whatever
4185 we do to grow the fixed or variable part contributes to our
4189 md_estimate_size_before_relax (fragP
, segment
)
4193 /* We've already got fragP->fr_subtype right; all we have to do is
4194 check for un-relaxable symbols. On an ELF system, we can't relax
4195 an externally visible symbol, because it may be overridden by a
4197 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4199 || S_IS_EXTERNAL (fragP
->fr_symbol
)
4200 || S_IS_WEAK (fragP
->fr_symbol
)
4204 /* Symbol is undefined in this segment, or we need to keep a
4205 reloc so that weak symbols can be overridden. */
4206 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4207 RELOC_ENUM reloc_type
;
4208 unsigned char *opcode
;
4212 if (fragP
->fr_var
!= NO_RELOC
)
4213 reloc_type
= fragP
->fr_var
;
4215 reloc_type
= BFD_RELOC_16_PCREL
;
4217 reloc_type
= BFD_RELOC_32_PCREL
;
4219 old_fr_fix
= fragP
->fr_fix
;
4220 opcode
= (unsigned char *) fragP
->fr_opcode
;
4222 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4225 /* Make jmp (0xeb) a (d)word displacement jump. */
4227 fragP
->fr_fix
+= size
;
4228 fixP
= fix_new (fragP
, old_fr_fix
, size
,
4230 fragP
->fr_offset
, 1,
4232 fixP
->fx_pcrel_adjust
= size
;
4236 if (no_cond_jump_promotion
)
4241 /* Negate the condition, and branch past an
4242 unconditional jump. */
4245 /* Insert an unconditional jump. */
4247 /* We added two extra opcode bytes, and have a two byte
4249 fragP
->fr_fix
+= 2 + 2;
4250 fixP
= fix_new (fragP
, old_fr_fix
+ 2, 2,
4252 fragP
->fr_offset
, 1,
4254 fixP
->fx_pcrel_adjust
= size
;
4260 if (no_cond_jump_promotion
)
4263 /* This changes the byte-displacement jump 0x7N
4264 to the (d)word-displacement jump 0x0f,0x8N. */
4265 opcode
[1] = opcode
[0] + 0x10;
4266 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4267 /* We've added an opcode byte. */
4268 fragP
->fr_fix
+= 1 + size
;
4269 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
4271 fragP
->fr_offset
, 1,
4273 fixP
->fx_pcrel_adjust
= size
;
4277 BAD_CASE (fragP
->fr_subtype
);
4281 return fragP
->fr_fix
- old_fr_fix
;
4285 /* Guess size depending on current relax state. Initially the relax
4286 state will correspond to a short jump and we return 1, because
4287 the variable part of the frag (the branch offset) is one byte
4288 long. However, we can relax a section more than once and in that
4289 case we must either set fr_subtype back to the unrelaxed state,
4290 or return the value for the appropriate branch. */
4291 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4294 /* Called after relax() is finished.
4296 In: Address of frag.
4297 fr_type == rs_machine_dependent.
4298 fr_subtype is what the address relaxed to.
4300 Out: Any fixSs and constants are set up.
4301 Caller will turn frag into a ".space 0". */
4303 #ifndef BFD_ASSEMBLER
4305 md_convert_frag (headers
, sec
, fragP
)
4306 object_headers
*headers ATTRIBUTE_UNUSED
;
4307 segT sec ATTRIBUTE_UNUSED
;
4311 md_convert_frag (abfd
, sec
, fragP
)
4312 bfd
*abfd ATTRIBUTE_UNUSED
;
4313 segT sec ATTRIBUTE_UNUSED
;
4317 unsigned char *opcode
;
4318 unsigned char *where_to_put_displacement
= NULL
;
4319 offsetT target_address
;
4320 offsetT opcode_address
;
4321 unsigned int extension
= 0;
4322 offsetT displacement_from_opcode_start
;
4324 opcode
= (unsigned char *) fragP
->fr_opcode
;
4326 /* Address we want to reach in file space. */
4327 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4329 /* Address opcode resides at in file space. */
4330 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4332 /* Displacement from opcode start to fill into instruction. */
4333 displacement_from_opcode_start
= target_address
- opcode_address
;
4335 if ((fragP
->fr_subtype
& BIG
) == 0)
4337 /* Don't have to change opcode. */
4338 extension
= 1; /* 1 opcode + 1 displacement */
4339 where_to_put_displacement
= &opcode
[1];
4343 if (no_cond_jump_promotion
4344 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4345 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4347 switch (fragP
->fr_subtype
)
4349 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4350 extension
= 4; /* 1 opcode + 4 displacement */
4352 where_to_put_displacement
= &opcode
[1];
4355 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4356 extension
= 2; /* 1 opcode + 2 displacement */
4358 where_to_put_displacement
= &opcode
[1];
4361 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4362 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4363 extension
= 5; /* 2 opcode + 4 displacement */
4364 opcode
[1] = opcode
[0] + 0x10;
4365 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4366 where_to_put_displacement
= &opcode
[2];
4369 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4370 extension
= 3; /* 2 opcode + 2 displacement */
4371 opcode
[1] = opcode
[0] + 0x10;
4372 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4373 where_to_put_displacement
= &opcode
[2];
4376 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4381 where_to_put_displacement
= &opcode
[3];
4385 BAD_CASE (fragP
->fr_subtype
);
4390 /* Now put displacement after opcode. */
4391 md_number_to_chars ((char *) where_to_put_displacement
,
4392 (valueT
) (displacement_from_opcode_start
- extension
),
4393 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4394 fragP
->fr_fix
+= extension
;
4397 /* Size of byte displacement jmp. */
4398 int md_short_jump_size
= 2;
4400 /* Size of dword displacement jmp. */
4401 int md_long_jump_size
= 5;
4403 /* Size of relocation record. */
4404 const int md_reloc_size
= 8;
4407 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4409 addressT from_addr
, to_addr
;
4410 fragS
*frag ATTRIBUTE_UNUSED
;
4411 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4415 offset
= to_addr
- (from_addr
+ 2);
4416 /* Opcode for byte-disp jump. */
4417 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4418 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4422 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4424 addressT from_addr
, to_addr
;
4425 fragS
*frag ATTRIBUTE_UNUSED
;
4426 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4430 offset
= to_addr
- (from_addr
+ 5);
4431 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4432 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4435 /* Apply a fixup (fixS) to segment data, once it has been determined
4436 by our caller that we have all the info we need to fix it up.
4438 On the 386, immediates, displacements, and data pointers are all in
4439 the same (little-endian) format, so we don't need to care about which
4443 md_apply_fix3 (fixP
, valP
, seg
)
4444 /* The fix we're to put in. */
4446 /* Pointer to the value of the bits. */
4448 /* Segment fix is from. */
4449 segT seg ATTRIBUTE_UNUSED
;
4451 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4452 valueT value
= * valP
;
4454 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4457 switch (fixP
->fx_r_type
)
4463 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4466 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4469 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4474 /* This is a hack. There should be a better way to handle this.
4475 This covers for the fact that bfd_install_relocation will
4476 subtract the current location (for partial_inplace, PC relative
4477 relocations); see more below. */
4478 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4479 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4480 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4481 && fixP
->fx_addsy
&& !use_rela_relocations
)
4484 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4486 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4489 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4492 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4494 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4497 || (symbol_section_p (fixP
->fx_addsy
)
4498 && fseg
!= absolute_section
))
4499 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
4500 && !S_IS_WEAK (fixP
->fx_addsy
)
4501 && S_IS_DEFINED (fixP
->fx_addsy
)
4502 && !S_IS_COMMON (fixP
->fx_addsy
))
4504 /* Yes, we add the values in twice. This is because
4505 bfd_perform_relocation subtracts them out again. I think
4506 bfd_perform_relocation is broken, but I don't dare change
4508 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4512 #if defined (OBJ_COFF) && defined (TE_PE)
4513 /* For some reason, the PE format does not store a section
4514 address offset for a PC relative symbol. */
4515 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4516 value
+= md_pcrel_from (fixP
);
4520 /* Fix a few things - the dynamic linker expects certain values here,
4521 and we must not dissappoint it. */
4522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4523 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4525 switch (fixP
->fx_r_type
)
4527 case BFD_RELOC_386_PLT32
:
4528 case BFD_RELOC_X86_64_PLT32
:
4529 /* Make the jump instruction point to the address of the operand. At
4530 runtime we merely add the offset to the actual PLT entry. */
4533 case BFD_RELOC_386_GOTPC
:
4535 /* This is tough to explain. We end up with this one if we have
4536 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4537 * here is to obtain the absolute address of the GOT, and it is strongly
4538 * preferable from a performance point of view to avoid using a runtime
4539 * relocation for this. The actual sequence of instructions often look
4545 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4547 * The call and pop essentially return the absolute address of
4548 * the label .L66 and store it in %ebx. The linker itself will
4549 * ultimately change the first operand of the addl so that %ebx points to
4550 * the GOT, but to keep things simple, the .o file must have this operand
4551 * set so that it generates not the absolute address of .L66, but the
4552 * absolute address of itself. This allows the linker itself simply
4553 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4554 * added in, and the addend of the relocation is stored in the operand
4555 * field for the instruction itself.
4557 * Our job here is to fix the operand so that it would add the correct
4558 * offset so that %ebx would point to itself. The thing that is tricky is
4559 * that .-.L66 will point to the beginning of the instruction, so we need
4560 * to further modify the operand so that it will point to itself.
4561 * There are other cases where you have something like:
4563 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4565 * and here no correction would be required. Internally in the assembler
4566 * we treat operands of this form as not being pcrel since the '.' is
4567 * explicitly mentioned, and I wonder whether it would simplify matters
4568 * to do it this way. Who knows. In earlier versions of the PIC patches,
4569 * the pcrel_adjust field was used to store the correction, but since the
4570 * expression is not pcrel, I felt it would be confusing to do it this
4575 case BFD_RELOC_386_GOT32
:
4576 case BFD_RELOC_X86_64_GOT32
:
4577 value
= 0; /* Fully resolved at runtime. No addend. */
4579 case BFD_RELOC_386_GOTOFF
:
4580 case BFD_RELOC_X86_64_GOTPCREL
:
4583 case BFD_RELOC_VTABLE_INHERIT
:
4584 case BFD_RELOC_VTABLE_ENTRY
:
4591 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4593 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4595 /* Are we finished with this relocation now? */
4596 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4598 #ifdef BFD_ASSEMBLER
4599 else if (use_rela_relocations
)
4601 fixP
->fx_no_overflow
= 1;
4605 md_number_to_chars (p
, value
, fixP
->fx_size
);
4608 #define MAX_LITTLENUMS 6
4610 /* Turn the string pointed to by litP into a floating point constant
4611 of type TYPE, and emit the appropriate bytes. The number of
4612 LITTLENUMS emitted is stored in *SIZEP. An error message is
4613 returned, or NULL on OK. */
4616 md_atof (type
, litP
, sizeP
)
4622 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4623 LITTLENUM_TYPE
*wordP
;
4645 return _("Bad call to md_atof ()");
4647 t
= atof_ieee (input_line_pointer
, type
, words
);
4649 input_line_pointer
= t
;
4651 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4652 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4653 the bigendian 386. */
4654 for (wordP
= words
+ prec
- 1; prec
--;)
4656 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4657 litP
+= sizeof (LITTLENUM_TYPE
);
4662 char output_invalid_buf
[8];
4669 sprintf (output_invalid_buf
, "'%c'", c
);
4671 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4672 return output_invalid_buf
;
4675 /* REG_STRING starts *before* REGISTER_PREFIX. */
4677 static const reg_entry
*
4678 parse_register (reg_string
, end_op
)
4682 char *s
= reg_string
;
4684 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4687 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4688 if (*s
== REGISTER_PREFIX
)
4691 if (is_space_char (*s
))
4695 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4697 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4698 return (const reg_entry
*) NULL
;
4702 /* For naked regs, make sure that we are not dealing with an identifier.
4703 This prevents confusing an identifier like `eax_var' with register
4705 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4706 return (const reg_entry
*) NULL
;
4710 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4712 /* Handle floating point regs, allowing spaces in the (i) part. */
4713 if (r
== i386_regtab
/* %st is first entry of table */)
4715 if (is_space_char (*s
))
4720 if (is_space_char (*s
))
4722 if (*s
>= '0' && *s
<= '7')
4724 r
= &i386_float_regtab
[*s
- '0'];
4726 if (is_space_char (*s
))
4734 /* We have "%st(" then garbage. */
4735 return (const reg_entry
*) NULL
;
4740 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4741 && flag_code
!= CODE_64BIT
)
4743 return (const reg_entry
*) NULL
;
4749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4750 const char *md_shortopts
= "kVQ:sq";
4752 const char *md_shortopts
= "q";
4755 struct option md_longopts
[] = {
4756 #define OPTION_32 (OPTION_MD_BASE + 0)
4757 {"32", no_argument
, NULL
, OPTION_32
},
4758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4759 #define OPTION_64 (OPTION_MD_BASE + 1)
4760 {"64", no_argument
, NULL
, OPTION_64
},
4762 {NULL
, no_argument
, NULL
, 0}
4764 size_t md_longopts_size
= sizeof (md_longopts
);
4767 md_parse_option (c
, arg
)
4769 char *arg ATTRIBUTE_UNUSED
;
4777 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4778 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4779 should be emitted or not. FIXME: Not implemented. */
4783 /* -V: SVR4 argument to print version ID. */
4785 print_version_id ();
4788 /* -k: Ignore for FreeBSD compatibility. */
4793 /* -s: On i386 Solaris, this tells the native assembler to use
4794 .stab instead of .stab.excl. We always use .stab anyhow. */
4799 const char **list
, **l
;
4801 list
= bfd_target_list ();
4802 for (l
= list
; *l
!= NULL
; l
++)
4803 if (strcmp (*l
, "elf64-x86-64") == 0)
4805 default_arch
= "x86_64";
4809 as_fatal (_("No compiled in support for x86_64"));
4816 default_arch
= "i386";
4826 md_show_usage (stream
)
4829 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4830 fprintf (stream
, _("\
4832 -V print assembler version number\n\
4834 -q quieten some warnings\n\
4837 fprintf (stream
, _("\
4838 -q quieten some warnings\n"));
4842 #ifdef BFD_ASSEMBLER
4843 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4844 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4846 /* Pick the target format to use. */
4849 i386_target_format ()
4851 if (!strcmp (default_arch
, "x86_64"))
4852 set_code_flag (CODE_64BIT
);
4853 else if (!strcmp (default_arch
, "i386"))
4854 set_code_flag (CODE_32BIT
);
4856 as_fatal (_("Unknown architecture"));
4857 switch (OUTPUT_FLAVOR
)
4859 #ifdef OBJ_MAYBE_AOUT
4860 case bfd_target_aout_flavour
:
4861 return AOUT_TARGET_FORMAT
;
4863 #ifdef OBJ_MAYBE_COFF
4864 case bfd_target_coff_flavour
:
4867 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4868 case bfd_target_elf_flavour
:
4870 if (flag_code
== CODE_64BIT
)
4871 use_rela_relocations
= 1;
4872 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4881 #endif /* OBJ_MAYBE_ more than one */
4883 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4884 void i386_elf_emit_arch_note ()
4886 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4887 && cpu_arch_name
!= NULL
)
4890 asection
*seg
= now_seg
;
4891 subsegT subseg
= now_subseg
;
4892 Elf_Internal_Note i_note
;
4893 Elf_External_Note e_note
;
4894 asection
*note_secp
;
4897 /* Create the .note section. */
4898 note_secp
= subseg_new (".note", 0);
4899 bfd_set_section_flags (stdoutput
,
4901 SEC_HAS_CONTENTS
| SEC_READONLY
);
4903 /* Process the arch string. */
4904 len
= strlen (cpu_arch_name
);
4906 i_note
.namesz
= len
+ 1;
4908 i_note
.type
= NT_ARCH
;
4909 p
= frag_more (sizeof (e_note
.namesz
));
4910 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4911 p
= frag_more (sizeof (e_note
.descsz
));
4912 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4913 p
= frag_more (sizeof (e_note
.type
));
4914 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4915 p
= frag_more (len
+ 1);
4916 strcpy (p
, cpu_arch_name
);
4918 frag_align (2, 0, 0);
4920 subseg_set (seg
, subseg
);
4924 #endif /* BFD_ASSEMBLER */
4927 md_undefined_symbol (name
)
4930 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4931 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4932 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4933 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4937 if (symbol_find (name
))
4938 as_bad (_("GOT already in symbol table"));
4939 GOT_symbol
= symbol_new (name
, undefined_section
,
4940 (valueT
) 0, &zero_address_frag
);
4947 /* Round up a section size to the appropriate boundary. */
4950 md_section_align (segment
, size
)
4951 segT segment ATTRIBUTE_UNUSED
;
4954 #ifdef BFD_ASSEMBLER
4955 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4956 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4958 /* For a.out, force the section size to be aligned. If we don't do
4959 this, BFD will align it for us, but it will not write out the
4960 final bytes of the section. This may be a bug in BFD, but it is
4961 easier to fix it here since that is how the other a.out targets
4965 align
= bfd_get_section_alignment (stdoutput
, segment
);
4966 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4974 /* On the i386, PC-relative offsets are relative to the start of the
4975 next instruction. That is, the address of the offset, plus its
4976 size, since the offset is always the last part of the insn. */
4979 md_pcrel_from (fixP
)
4982 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4989 int ignore ATTRIBUTE_UNUSED
;
4993 temp
= get_absolute_expression ();
4994 subseg_set (bss_section
, (subsegT
) temp
);
4995 demand_empty_rest_of_line ();
5000 #ifdef BFD_ASSEMBLER
5003 i386_validate_fix (fixp
)
5006 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5008 /* GOTOFF relocation are nonsense in 64bit mode. */
5009 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5011 if (flag_code
!= CODE_64BIT
)
5013 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5017 if (flag_code
== CODE_64BIT
)
5019 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5026 tc_gen_reloc (section
, fixp
)
5027 asection
*section ATTRIBUTE_UNUSED
;
5031 bfd_reloc_code_real_type code
;
5033 switch (fixp
->fx_r_type
)
5035 case BFD_RELOC_X86_64_PLT32
:
5036 case BFD_RELOC_X86_64_GOT32
:
5037 case BFD_RELOC_X86_64_GOTPCREL
:
5038 case BFD_RELOC_386_PLT32
:
5039 case BFD_RELOC_386_GOT32
:
5040 case BFD_RELOC_386_GOTOFF
:
5041 case BFD_RELOC_386_GOTPC
:
5042 case BFD_RELOC_X86_64_32S
:
5044 case BFD_RELOC_VTABLE_ENTRY
:
5045 case BFD_RELOC_VTABLE_INHERIT
:
5046 code
= fixp
->fx_r_type
;
5051 switch (fixp
->fx_size
)
5054 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5055 _("can not do %d byte pc-relative relocation"),
5057 code
= BFD_RELOC_32_PCREL
;
5059 case 1: code
= BFD_RELOC_8_PCREL
; break;
5060 case 2: code
= BFD_RELOC_16_PCREL
; break;
5061 case 4: code
= BFD_RELOC_32_PCREL
; break;
5066 switch (fixp
->fx_size
)
5069 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5070 _("can not do %d byte relocation"),
5072 code
= BFD_RELOC_32
;
5074 case 1: code
= BFD_RELOC_8
; break;
5075 case 2: code
= BFD_RELOC_16
; break;
5076 case 4: code
= BFD_RELOC_32
; break;
5078 case 8: code
= BFD_RELOC_64
; break;
5085 if (code
== BFD_RELOC_32
5087 && fixp
->fx_addsy
== GOT_symbol
)
5089 /* We don't support GOTPC on 64bit targets. */
5090 if (flag_code
== CODE_64BIT
)
5092 code
= BFD_RELOC_386_GOTPC
;
5095 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5096 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5097 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5099 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5100 if (!use_rela_relocations
)
5102 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5103 vtable entry to be used in the relocation's section offset. */
5104 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5105 rel
->address
= fixp
->fx_offset
;
5108 rel
->addend
= fixp
->fx_addnumber
;
5112 /* Use the rela in 64bit mode. */
5115 rel
->addend
= fixp
->fx_offset
;
5117 rel
->addend
-= fixp
->fx_pcrel_adjust
;
5120 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5121 if (rel
->howto
== NULL
)
5123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5124 _("cannot represent relocation type %s"),
5125 bfd_get_reloc_code_name (code
));
5126 /* Set howto to a garbage value so that we can keep going. */
5127 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5128 assert (rel
->howto
!= NULL
);
5134 #else /* !BFD_ASSEMBLER */
5136 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5138 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5141 relax_addressT segment_address_in_file
;
5143 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5144 Out: GNU LD relocation length code: 0, 1, or 2. */
5146 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5149 know (fixP
->fx_addsy
!= NULL
);
5151 md_number_to_chars (where
,
5152 (valueT
) (fixP
->fx_frag
->fr_address
5153 + fixP
->fx_where
- segment_address_in_file
),
5156 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5157 ? S_GET_TYPE (fixP
->fx_addsy
)
5158 : fixP
->fx_addsy
->sy_number
);
5160 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5161 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5162 where
[4] = r_symbolnum
& 0x0ff;
5163 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5164 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5165 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5168 #endif /* OBJ_AOUT or OBJ_BOUT. */
5170 #if defined (I386COFF)
5173 tc_coff_fix2rtype (fixP
)
5176 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5179 return (fixP
->fx_pcrel
?
5180 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5181 fixP
->fx_size
== 2 ? R_PCRWORD
:
5183 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5184 fixP
->fx_size
== 2 ? R_RELWORD
:
5189 tc_coff_sizemachdep (frag
)
5193 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5198 #endif /* I386COFF */
5200 #endif /* !BFD_ASSEMBLER */
5202 /* Parse operands using Intel syntax. This implements a recursive descent
5203 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5206 FIXME: We do not recognize the full operand grammar defined in the MASM
5207 documentation. In particular, all the structure/union and
5208 high-level macro operands are missing.
5210 Uppercase words are terminals, lower case words are non-terminals.
5211 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5212 bars '|' denote choices. Most grammar productions are implemented in
5213 functions called 'intel_<production>'.
5215 Initial production is 'expr'.
5221 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5223 constant digits [[ radixOverride ]]
5225 dataType BYTE | WORD | DWORD | QWORD | XWORD
5258 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5259 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5261 hexdigit a | b | c | d | e | f
5262 | A | B | C | D | E | F
5272 register specialRegister
5276 segmentRegister CS | DS | ES | FS | GS | SS
5278 specialRegister CR0 | CR2 | CR3
5279 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5280 | TR3 | TR4 | TR5 | TR6 | TR7
5282 We simplify the grammar in obvious places (e.g., register parsing is
5283 done by calling parse_register) and eliminate immediate left recursion
5284 to implement a recursive-descent parser.
5324 /* Parsing structure for the intel syntax parser. Used to implement the
5325 semantic actions for the operand grammar. */
5326 struct intel_parser_s
5328 char *op_string
; /* The string being parsed. */
5329 int got_a_float
; /* Whether the operand is a float. */
5330 int op_modifier
; /* Operand modifier. */
5331 int is_mem
; /* 1 if operand is memory reference. */
5332 const reg_entry
*reg
; /* Last register reference found. */
5333 char *disp
; /* Displacement string being built. */
5336 static struct intel_parser_s intel_parser
;
5338 /* Token structure for parsing intel syntax. */
5341 int code
; /* Token code. */
5342 const reg_entry
*reg
; /* Register entry for register tokens. */
5343 char *str
; /* String representation. */
5346 static struct intel_token cur_token
, prev_token
;
5348 /* Token codes for the intel parser. Since T_SHORT is already used
5349 by COFF, undefine it first to prevent a warning. */
5364 /* Prototypes for intel parser functions. */
5365 static int intel_match_token
PARAMS ((int code
));
5366 static void intel_get_token
PARAMS ((void));
5367 static void intel_putback_token
PARAMS ((void));
5368 static int intel_expr
PARAMS ((void));
5369 static int intel_e05
PARAMS ((void));
5370 static int intel_e05_1
PARAMS ((void));
5371 static int intel_e06
PARAMS ((void));
5372 static int intel_e06_1
PARAMS ((void));
5373 static int intel_e09
PARAMS ((void));
5374 static int intel_e09_1
PARAMS ((void));
5375 static int intel_e10
PARAMS ((void));
5376 static int intel_e10_1
PARAMS ((void));
5377 static int intel_e11
PARAMS ((void));
5380 i386_intel_operand (operand_string
, got_a_float
)
5381 char *operand_string
;
5387 /* Initialize token holders. */
5388 cur_token
.code
= prev_token
.code
= T_NIL
;
5389 cur_token
.reg
= prev_token
.reg
= NULL
;
5390 cur_token
.str
= prev_token
.str
= NULL
;
5392 /* Initialize parser structure. */
5393 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5396 strcpy (intel_parser
.op_string
, operand_string
);
5397 intel_parser
.got_a_float
= got_a_float
;
5398 intel_parser
.op_modifier
= -1;
5399 intel_parser
.is_mem
= 0;
5400 intel_parser
.reg
= NULL
;
5401 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5402 if (intel_parser
.disp
== NULL
)
5404 intel_parser
.disp
[0] = '\0';
5406 /* Read the first token and start the parser. */
5408 ret
= intel_expr ();
5412 /* If we found a memory reference, hand it over to i386_displacement
5413 to fill in the rest of the operand fields. */
5414 if (intel_parser
.is_mem
)
5416 if ((i
.mem_operands
== 1
5417 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5418 || i
.mem_operands
== 2)
5420 as_bad (_("too many memory references for '%s'"),
5421 current_templates
->start
->name
);
5426 char *s
= intel_parser
.disp
;
5429 /* Add the displacement expression. */
5431 ret
= i386_displacement (s
, s
+ strlen (s
))
5432 && i386_index_check (s
);
5436 /* Constant and OFFSET expressions are handled by i386_immediate. */
5437 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5438 || intel_parser
.reg
== NULL
)
5439 ret
= i386_immediate (intel_parser
.disp
);
5443 free (intel_parser
.disp
);
5453 /* expr SHORT e05 */
5454 if (cur_token
.code
== T_SHORT
)
5456 intel_parser
.op_modifier
= SHORT
;
5457 intel_match_token (T_SHORT
);
5459 return (intel_e05 ());
5464 return intel_e05 ();
5474 return (intel_e06 () && intel_e05_1 ());
5480 /* e05' addOp e06 e05' */
5481 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5483 strcat (intel_parser
.disp
, cur_token
.str
);
5484 intel_match_token (cur_token
.code
);
5486 return (intel_e06 () && intel_e05_1 ());
5501 return (intel_e09 () && intel_e06_1 ());
5507 /* e06' mulOp e09 e06' */
5508 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5510 strcat (intel_parser
.disp
, cur_token
.str
);
5511 intel_match_token (cur_token
.code
);
5513 return (intel_e09 () && intel_e06_1 ());
5521 /* e09 OFFSET e10 e09'
5530 /* e09 OFFSET e10 e09' */
5531 if (cur_token
.code
== T_OFFSET
)
5533 intel_parser
.is_mem
= 0;
5534 intel_parser
.op_modifier
= OFFSET_FLAT
;
5535 intel_match_token (T_OFFSET
);
5537 return (intel_e10 () && intel_e09_1 ());
5542 return (intel_e10 () && intel_e09_1 ());
5548 /* e09' PTR e10 e09' */
5549 if (cur_token
.code
== T_PTR
)
5551 if (prev_token
.code
== T_BYTE
)
5552 i
.suffix
= BYTE_MNEM_SUFFIX
;
5554 else if (prev_token
.code
== T_WORD
)
5556 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5557 i
.suffix
= SHORT_MNEM_SUFFIX
;
5559 i
.suffix
= WORD_MNEM_SUFFIX
;
5562 else if (prev_token
.code
== T_DWORD
)
5564 if (intel_parser
.got_a_float
== 1) /* "f..." */
5565 i
.suffix
= SHORT_MNEM_SUFFIX
;
5567 i
.suffix
= LONG_MNEM_SUFFIX
;
5570 else if (prev_token
.code
== T_QWORD
)
5572 if (intel_parser
.got_a_float
== 1) /* "f..." */
5573 i
.suffix
= LONG_MNEM_SUFFIX
;
5575 i
.suffix
= QWORD_MNEM_SUFFIX
;
5578 else if (prev_token
.code
== T_XWORD
)
5579 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5583 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5587 intel_match_token (T_PTR
);
5589 return (intel_e10 () && intel_e09_1 ());
5592 /* e09 : e10 e09' */
5593 else if (cur_token
.code
== ':')
5595 /* Mark as a memory operand only if it's not already known to be an
5596 offset expression. */
5597 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5598 intel_parser
.is_mem
= 1;
5600 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5615 return (intel_e11 () && intel_e10_1 ());
5621 /* e10' [ expr ] e10' */
5622 if (cur_token
.code
== '[')
5624 intel_match_token ('[');
5626 /* Mark as a memory operand only if it's not already known to be an
5627 offset expression. If it's an offset expression, we need to keep
5629 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5630 intel_parser
.is_mem
= 1;
5632 strcat (intel_parser
.disp
, "[");
5634 /* Add a '+' to the displacement string if necessary. */
5635 if (*intel_parser
.disp
!= '\0'
5636 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5637 strcat (intel_parser
.disp
, "+");
5639 if (intel_expr () && intel_match_token (']'))
5641 /* Preserve brackets when the operand is an offset expression. */
5642 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5643 strcat (intel_parser
.disp
, "]");
5645 return intel_e10_1 ();
5672 if (cur_token
.code
== '(')
5674 intel_match_token ('(');
5675 strcat (intel_parser
.disp
, "(");
5677 if (intel_expr () && intel_match_token (')'))
5679 strcat (intel_parser
.disp
, ")");
5687 else if (cur_token
.code
== '[')
5689 intel_match_token ('[');
5691 /* Mark as a memory operand only if it's not already known to be an
5692 offset expression. If it's an offset expression, we need to keep
5694 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5695 intel_parser
.is_mem
= 1;
5697 strcat (intel_parser
.disp
, "[");
5699 /* Operands for jump/call inside brackets denote absolute addresses. */
5700 if (current_templates
->start
->opcode_modifier
& Jump
5701 || current_templates
->start
->opcode_modifier
& JumpDword
5702 || current_templates
->start
->opcode_modifier
& JumpByte
5703 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5704 i
.types
[this_operand
] |= JumpAbsolute
;
5706 /* Add a '+' to the displacement string if necessary. */
5707 if (*intel_parser
.disp
!= '\0'
5708 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5709 strcat (intel_parser
.disp
, "+");
5711 if (intel_expr () && intel_match_token (']'))
5713 /* Preserve brackets when the operand is an offset expression. */
5714 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5715 strcat (intel_parser
.disp
, "]");
5728 else if (cur_token
.code
== T_BYTE
5729 || cur_token
.code
== T_WORD
5730 || cur_token
.code
== T_DWORD
5731 || cur_token
.code
== T_QWORD
5732 || cur_token
.code
== T_XWORD
)
5734 intel_match_token (cur_token
.code
);
5741 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5743 strcat (intel_parser
.disp
, cur_token
.str
);
5744 intel_match_token (cur_token
.code
);
5746 /* Mark as a memory operand only if it's not already known to be an
5747 offset expression. */
5748 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5749 intel_parser
.is_mem
= 1;
5755 else if (cur_token
.code
== T_REG
)
5757 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5759 intel_match_token (T_REG
);
5761 /* Check for segment change. */
5762 if (cur_token
.code
== ':')
5764 if (reg
->reg_type
& (SReg2
| SReg3
))
5766 switch (reg
->reg_num
)
5769 i
.seg
[i
.mem_operands
] = &es
;
5772 i
.seg
[i
.mem_operands
] = &cs
;
5775 i
.seg
[i
.mem_operands
] = &ss
;
5778 i
.seg
[i
.mem_operands
] = &ds
;
5781 i
.seg
[i
.mem_operands
] = &fs
;
5784 i
.seg
[i
.mem_operands
] = &gs
;
5790 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5795 /* Not a segment register. Check for register scaling. */
5796 else if (cur_token
.code
== '*')
5798 if (!intel_parser
.is_mem
)
5800 as_bad (_("Register scaling only allowed in memory operands."));
5804 /* What follows must be a valid scale. */
5805 if (intel_match_token ('*')
5806 && strchr ("01248", *cur_token
.str
))
5809 i
.types
[this_operand
] |= BaseIndex
;
5811 /* Set the scale after setting the register (otherwise,
5812 i386_scale will complain) */
5813 i386_scale (cur_token
.str
);
5814 intel_match_token (T_CONST
);
5818 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5824 /* No scaling. If this is a memory operand, the register is either a
5825 base register (first occurrence) or an index register (second
5827 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5829 if (i
.base_reg
&& i
.index_reg
)
5831 as_bad (_("Too many register references in memory operand.\n"));
5835 if (i
.base_reg
== NULL
)
5840 i
.types
[this_operand
] |= BaseIndex
;
5843 /* Offset modifier. Add the register to the displacement string to be
5844 parsed as an immediate expression after we're done. */
5845 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5846 strcat (intel_parser
.disp
, reg
->reg_name
);
5848 /* It's neither base nor index nor offset. */
5851 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5852 i
.op
[this_operand
].regs
= reg
;
5856 /* Since registers are not part of the displacement string (except
5857 when we're parsing offset operands), we may need to remove any
5858 preceding '+' from the displacement string. */
5859 if (*intel_parser
.disp
!= '\0'
5860 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5862 char *s
= intel_parser
.disp
;
5863 s
+= strlen (s
) - 1;
5872 else if (cur_token
.code
== T_ID
)
5874 /* Add the identifier to the displacement string. */
5875 strcat (intel_parser
.disp
, cur_token
.str
);
5876 intel_match_token (T_ID
);
5878 /* The identifier represents a memory reference only if it's not
5879 preceded by an offset modifier. */
5880 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5881 intel_parser
.is_mem
= 1;
5887 else if (cur_token
.code
== T_CONST
5888 || cur_token
.code
== '-'
5889 || cur_token
.code
== '+')
5893 /* Allow constants that start with `+' or `-'. */
5894 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5896 strcat (intel_parser
.disp
, cur_token
.str
);
5897 intel_match_token (cur_token
.code
);
5898 if (cur_token
.code
!= T_CONST
)
5900 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5906 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5907 if (save_str
== NULL
)
5909 strcpy (save_str
, cur_token
.str
);
5911 /* Get the next token to check for register scaling. */
5912 intel_match_token (cur_token
.code
);
5914 /* Check if this constant is a scaling factor for an index register. */
5915 if (cur_token
.code
== '*')
5917 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5919 if (!intel_parser
.is_mem
)
5921 as_bad (_("Register scaling only allowed in memory operands."));
5925 /* The constant is followed by `* reg', so it must be
5927 if (strchr ("01248", *save_str
))
5929 i
.index_reg
= cur_token
.reg
;
5930 i
.types
[this_operand
] |= BaseIndex
;
5932 /* Set the scale after setting the register (otherwise,
5933 i386_scale will complain) */
5934 i386_scale (save_str
);
5935 intel_match_token (T_REG
);
5937 /* Since registers are not part of the displacement
5938 string, we may need to remove any preceding '+' from
5939 the displacement string. */
5940 if (*intel_parser
.disp
!= '\0')
5942 char *s
= intel_parser
.disp
;
5943 s
+= strlen (s
) - 1;
5956 /* The constant was not used for register scaling. Since we have
5957 already consumed the token following `*' we now need to put it
5958 back in the stream. */
5960 intel_putback_token ();
5963 /* Add the constant to the displacement string. */
5964 strcat (intel_parser
.disp
, save_str
);
5970 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5974 /* Match the given token against cur_token. If they match, read the next
5975 token from the operand string. */
5977 intel_match_token (code
)
5980 if (cur_token
.code
== code
)
5987 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5992 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5997 const reg_entry
*reg
;
5998 struct intel_token new_token
;
6000 new_token
.code
= T_NIL
;
6001 new_token
.reg
= NULL
;
6002 new_token
.str
= NULL
;
6004 /* Free the memory allocated to the previous token and move
6005 cur_token to prev_token. */
6007 free (prev_token
.str
);
6009 prev_token
= cur_token
;
6011 /* Skip whitespace. */
6012 while (is_space_char (*intel_parser
.op_string
))
6013 intel_parser
.op_string
++;
6015 /* Return an empty token if we find nothing else on the line. */
6016 if (*intel_parser
.op_string
== '\0')
6018 cur_token
= new_token
;
6022 /* The new token cannot be larger than the remainder of the operand
6024 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6025 if (new_token
.str
== NULL
)
6027 new_token
.str
[0] = '\0';
6029 if (strchr ("0123456789", *intel_parser
.op_string
))
6031 char *p
= new_token
.str
;
6032 char *q
= intel_parser
.op_string
;
6033 new_token
.code
= T_CONST
;
6035 /* Allow any kind of identifier char to encompass floating point and
6036 hexadecimal numbers. */
6037 while (is_identifier_char (*q
))
6041 /* Recognize special symbol names [0-9][bf]. */
6042 if (strlen (intel_parser
.op_string
) == 2
6043 && (intel_parser
.op_string
[1] == 'b'
6044 || intel_parser
.op_string
[1] == 'f'))
6045 new_token
.code
= T_ID
;
6048 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6050 new_token
.code
= *intel_parser
.op_string
;
6051 new_token
.str
[0] = *intel_parser
.op_string
;
6052 new_token
.str
[1] = '\0';
6055 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6056 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6058 new_token
.code
= T_REG
;
6059 new_token
.reg
= reg
;
6061 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6063 new_token
.str
[0] = REGISTER_PREFIX
;
6064 new_token
.str
[1] = '\0';
6067 strcat (new_token
.str
, reg
->reg_name
);
6070 else if (is_identifier_char (*intel_parser
.op_string
))
6072 char *p
= new_token
.str
;
6073 char *q
= intel_parser
.op_string
;
6075 /* A '.' or '$' followed by an identifier char is an identifier.
6076 Otherwise, it's operator '.' followed by an expression. */
6077 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6079 new_token
.code
= *q
;
6080 new_token
.str
[0] = *q
;
6081 new_token
.str
[1] = '\0';
6085 while (is_identifier_char (*q
) || *q
== '@')
6089 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6090 new_token
.code
= T_BYTE
;
6092 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6093 new_token
.code
= T_WORD
;
6095 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6096 new_token
.code
= T_DWORD
;
6098 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6099 new_token
.code
= T_QWORD
;
6101 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6102 new_token
.code
= T_XWORD
;
6104 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6105 new_token
.code
= T_PTR
;
6107 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6108 new_token
.code
= T_SHORT
;
6110 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6112 new_token
.code
= T_OFFSET
;
6114 /* ??? This is not mentioned in the MASM grammar but gcc
6115 makes use of it with -mintel-syntax. OFFSET may be
6116 followed by FLAT: */
6117 if (strncasecmp (q
, " FLAT:", 6) == 0)
6118 strcat (new_token
.str
, " FLAT:");
6121 /* ??? This is not mentioned in the MASM grammar. */
6122 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6123 new_token
.code
= T_OFFSET
;
6126 new_token
.code
= T_ID
;
6131 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6133 intel_parser
.op_string
+= strlen (new_token
.str
);
6134 cur_token
= new_token
;
6137 /* Put cur_token back into the token stream and make cur_token point to
6140 intel_putback_token ()
6142 intel_parser
.op_string
-= strlen (cur_token
.str
);
6143 free (cur_token
.str
);
6144 cur_token
= prev_token
;
6146 /* Forget prev_token. */
6147 prev_token
.code
= T_NIL
;
6148 prev_token
.reg
= NULL
;
6149 prev_token
.str
= NULL
;