1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489 const char *i386_comment_chars
= "#/";
490 #define SVR4_COMMENT_CHARS 1
491 #define PREFIX_SEPARATOR '\\'
494 const char *i386_comment_chars
= "#";
495 #define PREFIX_SEPARATOR '/'
498 /* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506 const char line_comment_chars
[] = "#/";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant from exp in floating point
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant
517 const char FLT_CHARS
[] = "fFdDxX";
519 /* Tables for lexical analysis. */
520 static char mnemonic_chars
[256];
521 static char register_chars
[256];
522 static char operand_chars
[256];
523 static char identifier_chars
[256];
524 static char digit_chars
[256];
526 /* Lexical macros. */
527 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528 #define is_operand_char(x) (operand_chars[(unsigned char) x])
529 #define is_register_char(x) (register_chars[(unsigned char) x])
530 #define is_space_char(x) ((x) == ' ')
531 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532 #define is_digit_char(x) (digit_chars[(unsigned char) x])
534 /* All non-digit non-letter characters that may occur in an operand. */
535 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
537 /* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541 static char save_stack
[32];
542 static char *save_stack_p
;
543 #define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545 #define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
548 /* The instruction we're assembling. */
551 /* Possible templates for current insn. */
552 static const templates
*current_templates
;
554 /* Per instruction expressionS buffers: max displacements & immediates. */
555 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
556 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
558 /* Current operand we are working on. */
559 static int this_operand
= -1;
561 /* We support four different modes. FLAG_CODE variable is used to distinguish
569 static enum flag_code flag_code
;
570 static unsigned int object_64bit
;
571 static unsigned int disallow_64bit_reloc
;
572 static int use_rela_relocations
= 0;
573 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
574 static const char *tls_get_addr
;
576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
580 /* The ELF ABI to use. */
588 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
591 #if defined (TE_PE) || defined (TE_PEP)
592 /* Use big object file format. */
593 static int use_big_obj
= 0;
596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597 /* 1 if generating code for a shared library. */
598 static int shared
= 0;
601 /* 1 for intel syntax,
603 static int intel_syntax
= 0;
605 static enum x86_64_isa
607 amd64
= 1, /* AMD64 ISA. */
608 intel64
/* Intel64 ISA. */
611 /* 1 for intel mnemonic,
612 0 if att mnemonic. */
613 static int intel_mnemonic
= !SYSV386_COMPAT
;
615 /* 1 if pseudo registers are permitted. */
616 static int allow_pseudo_reg
= 0;
618 /* 1 if register prefix % not required. */
619 static int allow_naked_reg
= 0;
621 /* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
624 static int add_bnd_prefix
= 0;
626 /* 1 if pseudo index register, eiz/riz, is allowed . */
627 static int allow_index_reg
= 0;
629 /* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631 static int omit_lock_prefix
= 0;
633 /* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635 static int avoid_fence
= 0;
637 /* 1 if lfence should be inserted after every load. */
638 static int lfence_after_load
= 0;
640 /* Non-zero if lfence should be inserted before indirect branch. */
641 static enum lfence_before_indirect_branch_kind
643 lfence_branch_none
= 0,
644 lfence_branch_register
,
645 lfence_branch_memory
,
648 lfence_before_indirect_branch
;
650 /* Non-zero if lfence should be inserted before ret. */
651 static enum lfence_before_ret_kind
653 lfence_before_ret_none
= 0,
654 lfence_before_ret_not
,
655 lfence_before_ret_or
,
656 lfence_before_ret_shl
660 /* Types of previous instruction is .byte or prefix. */
675 /* 1 if the assembler should generate relax relocations. */
677 static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
680 static enum check_kind
686 sse_check
, operand_check
= check_warning
;
688 /* Non-zero if branches should be aligned within power of 2 boundary. */
689 static int align_branch_power
= 0;
691 /* Types of branches to align. */
692 enum align_branch_kind
694 align_branch_none
= 0,
695 align_branch_jcc
= 1,
696 align_branch_fused
= 2,
697 align_branch_jmp
= 3,
698 align_branch_call
= 4,
699 align_branch_indirect
= 5,
703 /* Type bits of branches to align. */
704 enum align_branch_bit
706 align_branch_jcc_bit
= 1 << align_branch_jcc
,
707 align_branch_fused_bit
= 1 << align_branch_fused
,
708 align_branch_jmp_bit
= 1 << align_branch_jmp
,
709 align_branch_call_bit
= 1 << align_branch_call
,
710 align_branch_indirect_bit
= 1 << align_branch_indirect
,
711 align_branch_ret_bit
= 1 << align_branch_ret
714 static unsigned int align_branch
= (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit
);
718 /* Types of condition jump used by macro-fusion. */
721 mf_jcc_jo
= 0, /* base opcode 0x70 */
722 mf_jcc_jc
, /* base opcode 0x72 */
723 mf_jcc_je
, /* base opcode 0x74 */
724 mf_jcc_jna
, /* base opcode 0x76 */
725 mf_jcc_js
, /* base opcode 0x78 */
726 mf_jcc_jp
, /* base opcode 0x7a */
727 mf_jcc_jl
, /* base opcode 0x7c */
728 mf_jcc_jle
, /* base opcode 0x7e */
731 /* Types of compare flag-modifying insntructions used by macro-fusion. */
734 mf_cmp_test_and
, /* test/cmp */
735 mf_cmp_alu_cmp
, /* add/sub/cmp */
736 mf_cmp_incdec
/* inc/dec */
739 /* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
742 #define MAX_FUSED_JCC_PADDING_SIZE 20
744 /* The maximum number of prefixes added for an instruction. */
745 static unsigned int align_branch_prefix_size
= 5;
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
752 static int optimize
= 0;
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
761 static int optimize_for_space
= 0;
763 /* Register prefix used for error message. */
764 static const char *register_prefix
= "%";
766 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769 static char stackop_size
= '\0';
771 /* Non-zero to optimize code alignment. */
772 int optimize_align_code
= 1;
774 /* Non-zero to quieten some warnings. */
775 static int quiet_warnings
= 0;
778 static const char *cpu_arch_name
= NULL
;
779 static char *cpu_sub_arch_name
= NULL
;
781 /* CPU feature flags. */
782 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
784 /* If we have selected a cpu we are generating instructions for. */
785 static int cpu_arch_tune_set
= 0;
787 /* Cpu we are generating instructions for. */
788 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of cpu we are generating instructions for. */
791 static i386_cpu_flags cpu_arch_tune_flags
;
793 /* CPU instruction set architecture used. */
794 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of instruction set architecture used. */
797 i386_cpu_flags cpu_arch_isa_flags
;
799 /* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801 static unsigned int no_cond_jump_promotion
= 0;
803 /* Encode SSE instructions with VEX prefix. */
804 static unsigned int sse2avx
;
806 /* Encode scalar AVX instructions with specific vector length. */
813 /* Encode VEX WIG instructions with specific vex.w. */
820 /* Encode scalar EVEX LIG instructions with specific vector length. */
828 /* Encode EVEX WIG instructions with specific evex.w. */
835 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
836 static enum rc_type evexrcig
= rne
;
838 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839 static symbolS
*GOT_symbol
;
841 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
842 unsigned int x86_dwarf2_return_column
;
844 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845 int x86_cie_data_alignment
;
847 /* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
857 #define UNCOND_JUMP 0
859 #define COND_JUMP86 2
860 #define BRANCH_PADDING 3
861 #define BRANCH_PREFIX 4
862 #define FUSED_JCC_PADDING 5
867 #define SMALL16 (SMALL | CODE16)
869 #define BIG16 (BIG | CODE16)
873 #define INLINE __inline__
879 #define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881 #define TYPE_FROM_RELAX_STATE(s) \
883 #define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
886 /* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
894 const relax_typeS md_relax_table
[] =
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
933 static const arch_entry cpu_arch
[] =
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
938 CPU_GENERIC32_FLAGS
, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
940 CPU_GENERIC64_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
958 CPU_PENTIUMPRO_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
968 CPU_NOCONA_FLAGS
, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
974 CPU_CORE2_FLAGS
, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
976 CPU_CORE2_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
978 CPU_COREI7_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
984 CPU_IAMCU_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
990 CPU_ATHLON_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
998 CPU_AMDFAM10_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1000 CPU_BDVER1_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1002 CPU_BDVER2_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1004 CPU_BDVER3_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1006 CPU_BDVER4_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1008 CPU_ZNVER1_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1010 CPU_ZNVER2_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1012 CPU_BTVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1014 CPU_BTVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1016 CPU_8087_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1024 CPU_CMOV_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1026 CPU_FXSR_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1032 CPU_SSE2_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE3_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4A_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4_1_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4_2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_2_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512F_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512CD_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512ER_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512PF_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512DQ_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512BW_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512VL_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1066 CPU_VMFUNC_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVE_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1072 CPU_XSAVEOPT_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVEC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVES_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1080 CPU_PCLMUL_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1082 CPU_PCLMUL_FLAGS
, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1084 CPU_FSGSBASE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1086 CPU_RDRND_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1088 CPU_F16C_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1090 CPU_BMI2_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1094 CPU_FMA4_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1100 CPU_MOVBE_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1102 CPU_CX16_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1106 CPU_LZCNT_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1108 CPU_POPCNT_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1114 CPU_INVPCID_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1116 CPU_CLFLUSH_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1120 CPU_SYSCALL_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1122 CPU_RDTSCP_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1124 CPU_3DNOW_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1126 CPU_3DNOWA_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1128 CPU_PADLOCK_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1130 CPU_SVME_FLAGS
, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1132 CPU_SVME_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1134 CPU_SSE4A_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1144 CPU_RDSEED_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1146 CPU_PRFCHW_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1148 CPU_SMAP_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1154 CPU_CLFLUSHOPT_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1156 CPU_PREFETCHWT1_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1160 CPU_CLWB_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512IFMA_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512VBMI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_VBMI2_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VNNI_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_BITALG_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1178 CPU_CLZERO_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1180 CPU_MWAITX_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1182 CPU_OSPKE_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1184 CPU_RDPID_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1186 CPU_PTWRITE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1190 CPU_SHSTK_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1192 CPU_GFNI_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1194 CPU_VAES_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1196 CPU_VPCLMULQDQ_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1198 CPU_WBNOINVD_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1200 CPU_PCONFIG_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1202 CPU_WAITPKG_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1204 CPU_CLDEMOTE_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1206 CPU_MOVDIRI_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1208 CPU_MOVDIR64B_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1210 CPU_AVX512_BF16_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1212 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1214 CPU_ENQCMD_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1216 CPU_SERIALIZE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1218 CPU_RDPRU_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1220 CPU_MCOMMIT_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1222 CPU_SEV_ES_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1224 CPU_TSXLDTRK_FLAGS
, 0 },
1227 static const noarch_entry cpu_noarch
[] =
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1274 /* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1278 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1285 && *input_line_pointer
== ',')
1287 align
= parse_align (needs_align
- 1);
1289 if (align
== (addressT
) -1)
1304 bss_alloc (symbolP
, size
, align
);
1309 pe_lcomm (int needs_align
)
1311 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1315 const pseudo_typeS md_pseudo_table
[] =
1317 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes
, 0},
1320 {"align", s_align_ptwo
, 0},
1322 {"arch", set_cpu_arch
, 0},
1326 {"lcomm", pe_lcomm
, 1},
1328 {"ffloat", float_cons
, 'f'},
1329 {"dfloat", float_cons
, 'd'},
1330 {"tfloat", float_cons
, 'x'},
1332 {"slong", signed_cons
, 4},
1333 {"noopt", s_ignore
, 0},
1334 {"optim", s_ignore
, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1336 {"code16", set_code_flag
, CODE_16BIT
},
1337 {"code32", set_code_flag
, CODE_32BIT
},
1339 {"code64", set_code_flag
, CODE_64BIT
},
1341 {"intel_syntax", set_intel_syntax
, 1},
1342 {"att_syntax", set_intel_syntax
, 0},
1343 {"intel_mnemonic", set_intel_mnemonic
, 1},
1344 {"att_mnemonic", set_intel_mnemonic
, 0},
1345 {"allow_index_reg", set_allow_index_reg
, 1},
1346 {"disallow_index_reg", set_allow_index_reg
, 0},
1347 {"sse_check", set_check
, 0},
1348 {"operand_check", set_check
, 1},
1349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common
, 0},
1352 {"file", dwarf2_directive_file
, 0},
1353 {"loc", dwarf2_directive_loc
, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1357 {"secrel32", pe_directive_secrel
, 0},
1362 /* For interface with expression (). */
1363 extern char *input_line_pointer
;
1365 /* Hash table for instruction mnemonic lookup. */
1366 static struct hash_control
*op_hash
;
1368 /* Hash table for register lookup. */
1369 static struct hash_control
*reg_hash
;
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374 static const unsigned char f32_1
[] =
1376 static const unsigned char f32_2
[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378 static const unsigned char f32_3
[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380 static const unsigned char f32_4
[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382 static const unsigned char f32_6
[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384 static const unsigned char f32_7
[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386 static const unsigned char f16_3
[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388 static const unsigned char f16_4
[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390 static const unsigned char jump_disp8
[] =
1391 {0xeb}; /* jmp disp8 */
1392 static const unsigned char jump32_disp32
[] =
1393 {0xe9}; /* jmp disp32 */
1394 static const unsigned char jump16_disp32
[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396 /* 32-bit NOPs patterns. */
1397 static const unsigned char *const f32_patt
[] = {
1398 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1400 /* 16-bit NOPs patterns. */
1401 static const unsigned char *const f16_patt
[] = {
1402 f32_1
, f32_2
, f16_3
, f16_4
1404 /* nopl (%[re]ax) */
1405 static const unsigned char alt_3
[] =
1407 /* nopl 0(%[re]ax) */
1408 static const unsigned char alt_4
[] =
1409 {0x0f,0x1f,0x40,0x00};
1410 /* nopl 0(%[re]ax,%[re]ax,1) */
1411 static const unsigned char alt_5
[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413 /* nopw 0(%[re]ax,%[re]ax,1) */
1414 static const unsigned char alt_6
[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416 /* nopl 0L(%[re]ax) */
1417 static const unsigned char alt_7
[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419 /* nopl 0L(%[re]ax,%[re]ax,1) */
1420 static const unsigned char alt_8
[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422 /* nopw 0L(%[re]ax,%[re]ax,1) */
1423 static const unsigned char alt_9
[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426 static const unsigned char alt_10
[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428 /* data16 nopw %cs:0L(%eax,%eax,1) */
1429 static const unsigned char alt_11
[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431 /* 32-bit and 64-bit NOPs patterns. */
1432 static const unsigned char *const alt_patt
[] = {
1433 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1434 alt_9
, alt_10
, alt_11
1437 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1441 i386_output_nops (char *where
, const unsigned char *const *patt
,
1442 int count
, int max_single_nop_size
)
1445 /* Place the longer NOP first. */
1448 const unsigned char *nops
;
1450 if (max_single_nop_size
< 1)
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size
);
1457 nops
= patt
[max_single_nop_size
- 1];
1459 /* Use the smaller one if the requsted one isn't available. */
1462 max_single_nop_size
--;
1463 nops
= patt
[max_single_nop_size
- 1];
1466 last
= count
% max_single_nop_size
;
1469 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1470 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1474 nops
= patt
[last
- 1];
1477 /* Use the smaller one plus one-byte NOP if the needed one
1480 nops
= patt
[last
- 1];
1481 memcpy (where
+ offset
, nops
, last
);
1482 where
[offset
+ last
] = *patt
[0];
1485 memcpy (where
+ offset
, nops
, last
);
1490 fits_in_imm7 (offsetT num
)
1492 return (num
& 0x7f) == num
;
1496 fits_in_imm31 (offsetT num
)
1498 return (num
& 0x7fffffff) == num
;
1501 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1505 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1507 const unsigned char *const *patt
= NULL
;
1508 int max_single_nop_size
;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops
;
1512 switch (fragP
->fr_type
)
1517 case rs_machine_dependent
:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1541 if (flag_code
== CODE_16BIT
)
1544 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops
= 2;
1550 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune
)
1555 case PROCESSOR_UNKNOWN
:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1563 case PROCESSOR_PENTIUM4
:
1564 case PROCESSOR_NOCONA
:
1565 case PROCESSOR_CORE
:
1566 case PROCESSOR_CORE2
:
1567 case PROCESSOR_COREI7
:
1568 case PROCESSOR_L1OM
:
1569 case PROCESSOR_K1OM
:
1570 case PROCESSOR_GENERIC64
:
1572 case PROCESSOR_ATHLON
:
1574 case PROCESSOR_AMDFAM10
:
1576 case PROCESSOR_ZNVER
:
1580 case PROCESSOR_I386
:
1581 case PROCESSOR_I486
:
1582 case PROCESSOR_PENTIUM
:
1583 case PROCESSOR_PENTIUMPRO
:
1584 case PROCESSOR_IAMCU
:
1585 case PROCESSOR_GENERIC32
:
1592 switch (fragP
->tc_frag_data
.tune
)
1594 case PROCESSOR_UNKNOWN
:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1600 case PROCESSOR_I386
:
1601 case PROCESSOR_I486
:
1602 case PROCESSOR_PENTIUM
:
1603 case PROCESSOR_IAMCU
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1611 case PROCESSOR_GENERIC32
:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1614 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1619 case PROCESSOR_PENTIUMPRO
:
1620 case PROCESSOR_PENTIUM4
:
1621 case PROCESSOR_NOCONA
:
1622 case PROCESSOR_CORE
:
1623 case PROCESSOR_CORE2
:
1624 case PROCESSOR_COREI7
:
1625 case PROCESSOR_L1OM
:
1626 case PROCESSOR_K1OM
:
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_GENERIC64
:
1638 if (patt
== f32_patt
)
1640 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops
= 2;
1646 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops
= 7;
1653 limit
= max_single_nop_size
;
1655 if (fragP
->fr_type
== rs_fill_nop
)
1657 /* Output NOPs for .nop directive. */
1658 if (limit
> max_single_nop_size
)
1660 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit
, max_single_nop_size
);
1667 else if (fragP
->fr_type
!= rs_machine_dependent
)
1668 fragP
->fr_var
= count
;
1670 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1672 /* Generate jump over NOPs. */
1673 offsetT disp
= count
- 2;
1674 if (fits_in_imm7 (disp
))
1676 /* Use "jmp disp8" if possible. */
1678 where
[0] = jump_disp8
[0];
1684 unsigned int size_of_jump
;
1686 if (flag_code
== CODE_16BIT
)
1688 where
[0] = jump16_disp32
[0];
1689 where
[1] = jump16_disp32
[1];
1694 where
[0] = jump32_disp32
[0];
1698 count
-= size_of_jump
+ 4;
1699 if (!fits_in_imm31 (count
))
1701 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1702 _("jump over nop padding out of range"));
1706 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1707 where
+= size_of_jump
+ 4;
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where
, patt
, count
, limit
);
1716 operand_type_all_zero (const union i386_operand_type
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1729 return !x
->array
[0];
1736 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1738 switch (ARRAY_SIZE(x
->array
))
1754 x
->bitfield
.class = ClassNone
;
1755 x
->bitfield
.instance
= InstanceNone
;
1759 operand_type_equal (const union i386_operand_type
*x
,
1760 const union i386_operand_type
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[2] != y
->array
[2])
1769 if (x
->array
[1] != y
->array
[1])
1773 return x
->array
[0] == y
->array
[0];
1781 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1783 switch (ARRAY_SIZE(x
->array
))
1798 return !x
->array
[0];
1805 cpu_flags_equal (const union i386_cpu_flags
*x
,
1806 const union i386_cpu_flags
*y
)
1808 switch (ARRAY_SIZE(x
->array
))
1811 if (x
->array
[3] != y
->array
[3])
1815 if (x
->array
[2] != y
->array
[2])
1819 if (x
->array
[1] != y
->array
[1])
1823 return x
->array
[0] == y
->array
[0];
1831 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1833 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1834 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1837 static INLINE i386_cpu_flags
1838 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1840 switch (ARRAY_SIZE (x
.array
))
1843 x
.array
[3] &= y
.array
[3];
1846 x
.array
[2] &= y
.array
[2];
1849 x
.array
[1] &= y
.array
[1];
1852 x
.array
[0] &= y
.array
[0];
1860 static INLINE i386_cpu_flags
1861 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[3] |= y
.array
[3];
1869 x
.array
[2] |= y
.array
[2];
1872 x
.array
[1] |= y
.array
[1];
1875 x
.array
[0] |= y
.array
[0];
1883 static INLINE i386_cpu_flags
1884 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[3] &= ~y
.array
[3];
1892 x
.array
[2] &= ~y
.array
[2];
1895 x
.array
[1] &= ~y
.array
[1];
1898 x
.array
[0] &= ~y
.array
[0];
1906 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1908 #define CPU_FLAGS_ARCH_MATCH 0x1
1909 #define CPU_FLAGS_64BIT_MATCH 0x2
1911 #define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1914 /* Return CPU flags match bits. */
1917 cpu_flags_match (const insn_template
*t
)
1919 i386_cpu_flags x
= t
->cpu_flags
;
1920 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1922 x
.bitfield
.cpu64
= 0;
1923 x
.bitfield
.cpuno64
= 0;
1925 if (cpu_flags_all_zero (&x
))
1927 /* This instruction is available on all archs. */
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu
= cpu_arch_flags
;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 cpu
= cpu_flags_and (x
, cpu
);
1941 if (!cpu_flags_all_zero (&cpu
))
1943 if (x
.bitfield
.cpuavx
)
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu
.bitfield
.cpuavx
1947 && (!t
->opcode_modifier
.sse2avx
1948 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1949 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1950 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1951 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1954 else if (x
.bitfield
.cpuavx512f
)
1956 /* We need to check a few extra flags with AVX512F. */
1957 if (cpu
.bitfield
.cpuavx512f
1958 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1959 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1960 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1961 match
|= CPU_FLAGS_ARCH_MATCH
;
1964 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 static INLINE i386_operand_type
1971 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1973 if (x
.bitfield
.class != y
.bitfield
.class)
1974 x
.bitfield
.class = ClassNone
;
1975 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1976 x
.bitfield
.instance
= InstanceNone
;
1978 switch (ARRAY_SIZE (x
.array
))
1981 x
.array
[2] &= y
.array
[2];
1984 x
.array
[1] &= y
.array
[1];
1987 x
.array
[0] &= y
.array
[0];
1995 static INLINE i386_operand_type
1996 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1998 gas_assert (y
.bitfield
.class == ClassNone
);
1999 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2001 switch (ARRAY_SIZE (x
.array
))
2004 x
.array
[2] &= ~y
.array
[2];
2007 x
.array
[1] &= ~y
.array
[1];
2010 x
.array
[0] &= ~y
.array
[0];
2018 static INLINE i386_operand_type
2019 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2021 gas_assert (x
.bitfield
.class == ClassNone
||
2022 y
.bitfield
.class == ClassNone
||
2023 x
.bitfield
.class == y
.bitfield
.class);
2024 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2025 y
.bitfield
.instance
== InstanceNone
||
2026 x
.bitfield
.instance
== y
.bitfield
.instance
);
2028 switch (ARRAY_SIZE (x
.array
))
2031 x
.array
[2] |= y
.array
[2];
2034 x
.array
[1] |= y
.array
[1];
2037 x
.array
[0] |= y
.array
[0];
2045 static INLINE i386_operand_type
2046 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2048 gas_assert (y
.bitfield
.class == ClassNone
);
2049 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2051 switch (ARRAY_SIZE (x
.array
))
2054 x
.array
[2] ^= y
.array
[2];
2057 x
.array
[1] ^= y
.array
[1];
2060 x
.array
[0] ^= y
.array
[0];
2068 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2069 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2070 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2071 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2072 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2073 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2074 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2075 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2076 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2077 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2078 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2079 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2080 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2081 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2082 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2083 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2084 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2095 operand_type_check (i386_operand_type t
, enum operand_type c
)
2100 return t
.bitfield
.class == Reg
;
2103 return (t
.bitfield
.imm8
2107 || t
.bitfield
.imm32s
2108 || t
.bitfield
.imm64
);
2111 return (t
.bitfield
.disp8
2112 || t
.bitfield
.disp16
2113 || t
.bitfield
.disp32
2114 || t
.bitfield
.disp32s
2115 || t
.bitfield
.disp64
);
2118 return (t
.bitfield
.disp8
2119 || t
.bitfield
.disp16
2120 || t
.bitfield
.disp32
2121 || t
.bitfield
.disp32s
2122 || t
.bitfield
.disp64
2123 || t
.bitfield
.baseindex
);
2132 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2133 between operand GIVEN and opeand WANTED for instruction template T. */
2136 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2139 return !((i
.types
[given
].bitfield
.byte
2140 && !t
->operand_types
[wanted
].bitfield
.byte
)
2141 || (i
.types
[given
].bitfield
.word
2142 && !t
->operand_types
[wanted
].bitfield
.word
)
2143 || (i
.types
[given
].bitfield
.dword
2144 && !t
->operand_types
[wanted
].bitfield
.dword
)
2145 || (i
.types
[given
].bitfield
.qword
2146 && !t
->operand_types
[wanted
].bitfield
.qword
)
2147 || (i
.types
[given
].bitfield
.tbyte
2148 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2151 /* Return 1 if there is no conflict in SIMD register between operand
2152 GIVEN and opeand WANTED for instruction template T. */
2155 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2158 return !((i
.types
[given
].bitfield
.xmmword
2159 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2160 || (i
.types
[given
].bitfield
.ymmword
2161 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2162 || (i
.types
[given
].bitfield
.zmmword
2163 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2166 /* Return 1 if there is no conflict in any size between operand GIVEN
2167 and opeand WANTED for instruction template T. */
2170 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2173 return (match_operand_size (t
, wanted
, given
)
2174 && !((i
.types
[given
].bitfield
.unspecified
2176 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2177 || (i
.types
[given
].bitfield
.fword
2178 && !t
->operand_types
[wanted
].bitfield
.fword
)
2179 /* For scalar opcode templates to allow register and memory
2180 operands at the same time, some special casing is needed
2181 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2182 down-conversion vpmov*. */
2183 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2184 && t
->operand_types
[wanted
].bitfield
.byte
2185 + t
->operand_types
[wanted
].bitfield
.word
2186 + t
->operand_types
[wanted
].bitfield
.dword
2187 + t
->operand_types
[wanted
].bitfield
.qword
2188 > !!t
->opcode_modifier
.broadcast
)
2189 ? (i
.types
[given
].bitfield
.xmmword
2190 || i
.types
[given
].bitfield
.ymmword
2191 || i
.types
[given
].bitfield
.zmmword
)
2192 : !match_simd_size(t
, wanted
, given
))));
2195 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2196 operands for instruction template T, and it has MATCH_REVERSE set if there
2197 is no size conflict on any operands for the template with operands reversed
2198 (and the template allows for reversing in the first place). */
2200 #define MATCH_STRAIGHT 1
2201 #define MATCH_REVERSE 2
2203 static INLINE
unsigned int
2204 operand_size_match (const insn_template
*t
)
2206 unsigned int j
, match
= MATCH_STRAIGHT
;
2208 /* Don't check non-absolute jump instructions. */
2209 if (t
->opcode_modifier
.jump
2210 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2213 /* Check memory and accumulator operand size. */
2214 for (j
= 0; j
< i
.operands
; j
++)
2216 if (i
.types
[j
].bitfield
.class != Reg
2217 && i
.types
[j
].bitfield
.class != RegSIMD
2218 && t
->opcode_modifier
.anysize
)
2221 if (t
->operand_types
[j
].bitfield
.class == Reg
2222 && !match_operand_size (t
, j
, j
))
2228 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2229 && !match_simd_size (t
, j
, j
))
2235 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2236 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2242 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2249 if (!t
->opcode_modifier
.d
)
2253 i
.error
= operand_size_mismatch
;
2257 /* Check reverse. */
2258 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2260 for (j
= 0; j
< i
.operands
; j
++)
2262 unsigned int given
= i
.operands
- j
- 1;
2264 if (t
->operand_types
[j
].bitfield
.class == Reg
2265 && !match_operand_size (t
, j
, given
))
2268 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2269 && !match_simd_size (t
, j
, given
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, given
)
2274 || !match_simd_size (t
, j
, given
)))
2277 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2281 return match
| MATCH_REVERSE
;
2285 operand_type_match (i386_operand_type overlap
,
2286 i386_operand_type given
)
2288 i386_operand_type temp
= overlap
;
2290 temp
.bitfield
.unspecified
= 0;
2291 temp
.bitfield
.byte
= 0;
2292 temp
.bitfield
.word
= 0;
2293 temp
.bitfield
.dword
= 0;
2294 temp
.bitfield
.fword
= 0;
2295 temp
.bitfield
.qword
= 0;
2296 temp
.bitfield
.tbyte
= 0;
2297 temp
.bitfield
.xmmword
= 0;
2298 temp
.bitfield
.ymmword
= 0;
2299 temp
.bitfield
.zmmword
= 0;
2300 if (operand_type_all_zero (&temp
))
2303 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2307 i
.error
= operand_type_mismatch
;
2311 /* If given types g0 and g1 are registers they must be of the same type
2312 unless the expected operand type register overlap is null.
2313 Some Intel syntax memory operand size checking also happens here. */
2316 operand_type_register_match (i386_operand_type g0
,
2317 i386_operand_type t0
,
2318 i386_operand_type g1
,
2319 i386_operand_type t1
)
2321 if (g0
.bitfield
.class != Reg
2322 && g0
.bitfield
.class != RegSIMD
2323 && (!operand_type_check (g0
, anymem
)
2324 || g0
.bitfield
.unspecified
2325 || (t0
.bitfield
.class != Reg
2326 && t0
.bitfield
.class != RegSIMD
)))
2329 if (g1
.bitfield
.class != Reg
2330 && g1
.bitfield
.class != RegSIMD
2331 && (!operand_type_check (g1
, anymem
)
2332 || g1
.bitfield
.unspecified
2333 || (t1
.bitfield
.class != Reg
2334 && t1
.bitfield
.class != RegSIMD
)))
2337 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2338 && g0
.bitfield
.word
== g1
.bitfield
.word
2339 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2340 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2341 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2342 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2343 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2346 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2347 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2348 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2349 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2350 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2351 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2352 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2355 i
.error
= register_type_mismatch
;
2360 static INLINE
unsigned int
2361 register_number (const reg_entry
*r
)
2363 unsigned int nr
= r
->reg_num
;
2365 if (r
->reg_flags
& RegRex
)
2368 if (r
->reg_flags
& RegVRex
)
2374 static INLINE
unsigned int
2375 mode_from_disp_size (i386_operand_type t
)
2377 if (t
.bitfield
.disp8
)
2379 else if (t
.bitfield
.disp16
2380 || t
.bitfield
.disp32
2381 || t
.bitfield
.disp32s
)
2388 fits_in_signed_byte (addressT num
)
2390 return num
+ 0x80 <= 0xff;
2394 fits_in_unsigned_byte (addressT num
)
2400 fits_in_unsigned_word (addressT num
)
2402 return num
<= 0xffff;
2406 fits_in_signed_word (addressT num
)
2408 return num
+ 0x8000 <= 0xffff;
2412 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2417 return num
+ 0x80000000 <= 0xffffffff;
2419 } /* fits_in_signed_long() */
2422 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2427 return num
<= 0xffffffff;
2429 } /* fits_in_unsigned_long() */
2432 fits_in_disp8 (offsetT num
)
2434 int shift
= i
.memshift
;
2440 mask
= (1 << shift
) - 1;
2442 /* Return 0 if NUM isn't properly aligned. */
2446 /* Check if NUM will fit in 8bit after shift. */
2447 return fits_in_signed_byte (num
>> shift
);
2451 fits_in_imm4 (offsetT num
)
2453 return (num
& 0xf) == num
;
2456 static i386_operand_type
2457 smallest_imm_type (offsetT num
)
2459 i386_operand_type t
;
2461 operand_type_set (&t
, 0);
2462 t
.bitfield
.imm64
= 1;
2464 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2466 /* This code is disabled on the 486 because all the Imm1 forms
2467 in the opcode table are slower on the i486. They're the
2468 versions with the implicitly specified single-position
2469 displacement, which has another syntax if you really want to
2471 t
.bitfield
.imm1
= 1;
2472 t
.bitfield
.imm8
= 1;
2473 t
.bitfield
.imm8s
= 1;
2474 t
.bitfield
.imm16
= 1;
2475 t
.bitfield
.imm32
= 1;
2476 t
.bitfield
.imm32s
= 1;
2478 else if (fits_in_signed_byte (num
))
2480 t
.bitfield
.imm8
= 1;
2481 t
.bitfield
.imm8s
= 1;
2482 t
.bitfield
.imm16
= 1;
2483 t
.bitfield
.imm32
= 1;
2484 t
.bitfield
.imm32s
= 1;
2486 else if (fits_in_unsigned_byte (num
))
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm16
= 1;
2490 t
.bitfield
.imm32
= 1;
2491 t
.bitfield
.imm32s
= 1;
2493 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2495 t
.bitfield
.imm16
= 1;
2496 t
.bitfield
.imm32
= 1;
2497 t
.bitfield
.imm32s
= 1;
2499 else if (fits_in_signed_long (num
))
2501 t
.bitfield
.imm32
= 1;
2502 t
.bitfield
.imm32s
= 1;
2504 else if (fits_in_unsigned_long (num
))
2505 t
.bitfield
.imm32
= 1;
2511 offset_in_range (offsetT val
, int size
)
2517 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2518 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2519 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2521 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2527 /* If BFD64, sign extend val for 32bit address mode. */
2528 if (flag_code
!= CODE_64BIT
2529 || i
.prefix
[ADDR_PREFIX
])
2530 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2531 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2534 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2536 char buf1
[40], buf2
[40];
2538 sprint_value (buf1
, val
);
2539 sprint_value (buf2
, val
& mask
);
2540 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2555 a. PREFIX_EXIST if attempting to add a prefix where one from the
2556 same class already exists.
2557 b. PREFIX_LOCK if lock prefix is added.
2558 c. PREFIX_REP if rep/repne prefix is added.
2559 d. PREFIX_DS if ds prefix is added.
2560 e. PREFIX_OTHER if other prefix is added.
2563 static enum PREFIX_GROUP
2564 add_prefix (unsigned int prefix
)
2566 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2569 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2570 && flag_code
== CODE_64BIT
)
2572 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2575 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2586 case DS_PREFIX_OPCODE
:
2589 case CS_PREFIX_OPCODE
:
2590 case ES_PREFIX_OPCODE
:
2591 case FS_PREFIX_OPCODE
:
2592 case GS_PREFIX_OPCODE
:
2593 case SS_PREFIX_OPCODE
:
2597 case REPNE_PREFIX_OPCODE
:
2598 case REPE_PREFIX_OPCODE
:
2603 case LOCK_PREFIX_OPCODE
:
2612 case ADDR_PREFIX_OPCODE
:
2616 case DATA_PREFIX_OPCODE
:
2620 if (i
.prefix
[q
] != 0)
2628 i
.prefix
[q
] |= prefix
;
2631 as_bad (_("same type of prefix used twice"));
2637 update_code_flag (int value
, int check
)
2639 PRINTF_LIKE ((*as_error
));
2641 flag_code
= (enum flag_code
) value
;
2642 if (flag_code
== CODE_64BIT
)
2644 cpu_arch_flags
.bitfield
.cpu64
= 1;
2645 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2652 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2655 as_error
= as_fatal
;
2658 (*as_error
) (_("64bit mode not supported on `%s'."),
2659 cpu_arch_name
? cpu_arch_name
: default_arch
);
2661 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2664 as_error
= as_fatal
;
2667 (*as_error
) (_("32bit mode not supported on `%s'."),
2668 cpu_arch_name
? cpu_arch_name
: default_arch
);
2670 stackop_size
= '\0';
2674 set_code_flag (int value
)
2676 update_code_flag (value
, 0);
2680 set_16bit_gcc_code_flag (int new_code_flag
)
2682 flag_code
= (enum flag_code
) new_code_flag
;
2683 if (flag_code
!= CODE_16BIT
)
2685 cpu_arch_flags
.bitfield
.cpu64
= 0;
2686 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2687 stackop_size
= LONG_MNEM_SUFFIX
;
2691 set_intel_syntax (int syntax_flag
)
2693 /* Find out if register prefixing is specified. */
2694 int ask_naked_reg
= 0;
2697 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2700 int e
= get_symbol_name (&string
);
2702 if (strcmp (string
, "prefix") == 0)
2704 else if (strcmp (string
, "noprefix") == 0)
2707 as_bad (_("bad argument to syntax directive."));
2708 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2712 intel_syntax
= syntax_flag
;
2714 if (ask_naked_reg
== 0)
2715 allow_naked_reg
= (intel_syntax
2716 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2718 allow_naked_reg
= (ask_naked_reg
< 0);
2720 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2722 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2723 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2724 register_prefix
= allow_naked_reg
? "" : "%";
2728 set_intel_mnemonic (int mnemonic_flag
)
2730 intel_mnemonic
= mnemonic_flag
;
2734 set_allow_index_reg (int flag
)
2736 allow_index_reg
= flag
;
2740 set_check (int what
)
2742 enum check_kind
*kind
;
2747 kind
= &operand_check
;
2758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2761 int e
= get_symbol_name (&string
);
2763 if (strcmp (string
, "none") == 0)
2765 else if (strcmp (string
, "warning") == 0)
2766 *kind
= check_warning
;
2767 else if (strcmp (string
, "error") == 0)
2768 *kind
= check_error
;
2770 as_bad (_("bad argument to %s_check directive."), str
);
2771 (void) restore_line_pointer (e
);
2774 as_bad (_("missing argument for %s_check directive"), str
);
2776 demand_empty_rest_of_line ();
2780 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2781 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2784 static const char *arch
;
2786 /* Intel LIOM is only supported on ELF. */
2792 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2793 use default_arch. */
2794 arch
= cpu_arch_name
;
2796 arch
= default_arch
;
2799 /* If we are targeting Intel MCU, we must enable it. */
2800 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2801 || new_flag
.bitfield
.cpuiamcu
)
2804 /* If we are targeting Intel L1OM, we must enable it. */
2805 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2806 || new_flag
.bitfield
.cpul1om
)
2809 /* If we are targeting Intel K1OM, we must enable it. */
2810 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2811 || new_flag
.bitfield
.cpuk1om
)
2814 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2819 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2823 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2826 int e
= get_symbol_name (&string
);
2828 i386_cpu_flags flags
;
2830 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2832 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2834 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2838 cpu_arch_name
= cpu_arch
[j
].name
;
2839 cpu_sub_arch_name
= NULL
;
2840 cpu_arch_flags
= cpu_arch
[j
].flags
;
2841 if (flag_code
== CODE_64BIT
)
2843 cpu_arch_flags
.bitfield
.cpu64
= 1;
2844 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2848 cpu_arch_flags
.bitfield
.cpu64
= 0;
2849 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2851 cpu_arch_isa
= cpu_arch
[j
].type
;
2852 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2853 if (!cpu_arch_tune_set
)
2855 cpu_arch_tune
= cpu_arch_isa
;
2856 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2861 flags
= cpu_flags_or (cpu_arch_flags
,
2864 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2866 if (cpu_sub_arch_name
)
2868 char *name
= cpu_sub_arch_name
;
2869 cpu_sub_arch_name
= concat (name
,
2871 (const char *) NULL
);
2875 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2876 cpu_arch_flags
= flags
;
2877 cpu_arch_isa_flags
= flags
;
2881 = cpu_flags_or (cpu_arch_isa_flags
,
2883 (void) restore_line_pointer (e
);
2884 demand_empty_rest_of_line ();
2889 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2891 /* Disable an ISA extension. */
2892 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2893 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2895 flags
= cpu_flags_and_not (cpu_arch_flags
,
2896 cpu_noarch
[j
].flags
);
2897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2899 if (cpu_sub_arch_name
)
2901 char *name
= cpu_sub_arch_name
;
2902 cpu_sub_arch_name
= concat (name
, string
,
2903 (const char *) NULL
);
2907 cpu_sub_arch_name
= xstrdup (string
);
2908 cpu_arch_flags
= flags
;
2909 cpu_arch_isa_flags
= flags
;
2911 (void) restore_line_pointer (e
);
2912 demand_empty_rest_of_line ();
2916 j
= ARRAY_SIZE (cpu_arch
);
2919 if (j
>= ARRAY_SIZE (cpu_arch
))
2920 as_bad (_("no such architecture: `%s'"), string
);
2922 *input_line_pointer
= e
;
2925 as_bad (_("missing cpu architecture"));
2927 no_cond_jump_promotion
= 0;
2928 if (*input_line_pointer
== ','
2929 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2934 ++input_line_pointer
;
2935 e
= get_symbol_name (&string
);
2937 if (strcmp (string
, "nojumps") == 0)
2938 no_cond_jump_promotion
= 1;
2939 else if (strcmp (string
, "jumps") == 0)
2942 as_bad (_("no such architecture modifier: `%s'"), string
);
2944 (void) restore_line_pointer (e
);
2947 demand_empty_rest_of_line ();
2950 enum bfd_architecture
2953 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2955 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2956 || flag_code
!= CODE_64BIT
)
2957 as_fatal (_("Intel L1OM is 64bit ELF only"));
2958 return bfd_arch_l1om
;
2960 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2962 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2963 || flag_code
!= CODE_64BIT
)
2964 as_fatal (_("Intel K1OM is 64bit ELF only"));
2965 return bfd_arch_k1om
;
2967 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2969 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2970 || flag_code
== CODE_64BIT
)
2971 as_fatal (_("Intel MCU is 32bit ELF only"));
2972 return bfd_arch_iamcu
;
2975 return bfd_arch_i386
;
2981 if (!strncmp (default_arch
, "x86_64", 6))
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || default_arch
[6] != '\0')
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_mach_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || default_arch
[6] != '\0')
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_mach_k1om
;
2997 else if (default_arch
[6] == '\0')
2998 return bfd_mach_x86_64
;
3000 return bfd_mach_x64_32
;
3002 else if (!strcmp (default_arch
, "i386")
3003 || !strcmp (default_arch
, "iamcu"))
3005 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3007 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3008 as_fatal (_("Intel MCU is 32bit ELF only"));
3009 return bfd_mach_i386_iamcu
;
3012 return bfd_mach_i386_i386
;
3015 as_fatal (_("unknown architecture"));
3021 const char *hash_err
;
3023 /* Support pseudo prefixes like {disp32}. */
3024 lex_type
['{'] = LEX_BEGIN_NAME
;
3026 /* Initialize op_hash hash table. */
3027 op_hash
= hash_new ();
3030 const insn_template
*optab
;
3031 templates
*core_optab
;
3033 /* Setup for loop. */
3035 core_optab
= XNEW (templates
);
3036 core_optab
->start
= optab
;
3041 if (optab
->name
== NULL
3042 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3044 /* different name --> ship out current template list;
3045 add to hash table; & begin anew. */
3046 core_optab
->end
= optab
;
3047 hash_err
= hash_insert (op_hash
,
3049 (void *) core_optab
);
3052 as_fatal (_("can't hash %s: %s"),
3056 if (optab
->name
== NULL
)
3058 core_optab
= XNEW (templates
);
3059 core_optab
->start
= optab
;
3064 /* Initialize reg_hash hash table. */
3065 reg_hash
= hash_new ();
3067 const reg_entry
*regtab
;
3068 unsigned int regtab_size
= i386_regtab_size
;
3070 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3072 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3074 as_fatal (_("can't hash %s: %s"),
3080 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3085 for (c
= 0; c
< 256; c
++)
3090 mnemonic_chars
[c
] = c
;
3091 register_chars
[c
] = c
;
3092 operand_chars
[c
] = c
;
3094 else if (ISLOWER (c
))
3096 mnemonic_chars
[c
] = c
;
3097 register_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3100 else if (ISUPPER (c
))
3102 mnemonic_chars
[c
] = TOLOWER (c
);
3103 register_chars
[c
] = mnemonic_chars
[c
];
3104 operand_chars
[c
] = c
;
3106 else if (c
== '{' || c
== '}')
3108 mnemonic_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3112 if (ISALPHA (c
) || ISDIGIT (c
))
3113 identifier_chars
[c
] = c
;
3116 identifier_chars
[c
] = c
;
3117 operand_chars
[c
] = c
;
3122 identifier_chars
['@'] = '@';
3125 identifier_chars
['?'] = '?';
3126 operand_chars
['?'] = '?';
3128 digit_chars
['-'] = '-';
3129 mnemonic_chars
['_'] = '_';
3130 mnemonic_chars
['-'] = '-';
3131 mnemonic_chars
['.'] = '.';
3132 identifier_chars
['_'] = '_';
3133 identifier_chars
['.'] = '.';
3135 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3136 operand_chars
[(unsigned char) *p
] = *p
;
3139 if (flag_code
== CODE_64BIT
)
3141 #if defined (OBJ_COFF) && defined (TE_PE)
3142 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3145 x86_dwarf2_return_column
= 16;
3147 x86_cie_data_alignment
= -8;
3151 x86_dwarf2_return_column
= 8;
3152 x86_cie_data_alignment
= -4;
3155 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3156 can be turned into BRANCH_PREFIX frag. */
3157 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3162 i386_print_statistics (FILE *file
)
3164 hash_print_statistics (file
, "i386 opcode", op_hash
);
3165 hash_print_statistics (file
, "i386 register", reg_hash
);
3170 /* Debugging routines for md_assemble. */
3171 static void pte (insn_template
*);
3172 static void pt (i386_operand_type
);
3173 static void pe (expressionS
*);
3174 static void ps (symbolS
*);
3177 pi (const char *line
, i386_insn
*x
)
3181 fprintf (stdout
, "%s: template ", line
);
3183 fprintf (stdout
, " address: base %s index %s scale %x\n",
3184 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3185 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3186 x
->log2_scale_factor
);
3187 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3188 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3189 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3190 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3191 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3192 (x
->rex
& REX_W
) != 0,
3193 (x
->rex
& REX_R
) != 0,
3194 (x
->rex
& REX_X
) != 0,
3195 (x
->rex
& REX_B
) != 0);
3196 for (j
= 0; j
< x
->operands
; j
++)
3198 fprintf (stdout
, " #%d: ", j
+ 1);
3200 fprintf (stdout
, "\n");
3201 if (x
->types
[j
].bitfield
.class == Reg
3202 || x
->types
[j
].bitfield
.class == RegMMX
3203 || x
->types
[j
].bitfield
.class == RegSIMD
3204 || x
->types
[j
].bitfield
.class == RegMask
3205 || x
->types
[j
].bitfield
.class == SReg
3206 || x
->types
[j
].bitfield
.class == RegCR
3207 || x
->types
[j
].bitfield
.class == RegDR
3208 || x
->types
[j
].bitfield
.class == RegTR
3209 || x
->types
[j
].bitfield
.class == RegBND
)
3210 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3211 if (operand_type_check (x
->types
[j
], imm
))
3213 if (operand_type_check (x
->types
[j
], disp
))
3214 pe (x
->op
[j
].disps
);
3219 pte (insn_template
*t
)
3222 fprintf (stdout
, " %d operands ", t
->operands
);
3223 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3224 if (t
->extension_opcode
!= None
)
3225 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3226 if (t
->opcode_modifier
.d
)
3227 fprintf (stdout
, "D");
3228 if (t
->opcode_modifier
.w
)
3229 fprintf (stdout
, "W");
3230 fprintf (stdout
, "\n");
3231 for (j
= 0; j
< t
->operands
; j
++)
3233 fprintf (stdout
, " #%d type ", j
+ 1);
3234 pt (t
->operand_types
[j
]);
3235 fprintf (stdout
, "\n");
3242 fprintf (stdout
, " operation %d\n", e
->X_op
);
3243 fprintf (stdout
, " add_number %ld (%lx)\n",
3244 (long) e
->X_add_number
, (long) e
->X_add_number
);
3245 if (e
->X_add_symbol
)
3247 fprintf (stdout
, " add_symbol ");
3248 ps (e
->X_add_symbol
);
3249 fprintf (stdout
, "\n");
3253 fprintf (stdout
, " op_symbol ");
3254 ps (e
->X_op_symbol
);
3255 fprintf (stdout
, "\n");
3262 fprintf (stdout
, "%s type %s%s",
3264 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3265 segment_name (S_GET_SEGMENT (s
)));
3268 static struct type_name
3270 i386_operand_type mask
;
3273 const type_names
[] =
3275 { OPERAND_TYPE_REG8
, "r8" },
3276 { OPERAND_TYPE_REG16
, "r16" },
3277 { OPERAND_TYPE_REG32
, "r32" },
3278 { OPERAND_TYPE_REG64
, "r64" },
3279 { OPERAND_TYPE_ACC8
, "acc8" },
3280 { OPERAND_TYPE_ACC16
, "acc16" },
3281 { OPERAND_TYPE_ACC32
, "acc32" },
3282 { OPERAND_TYPE_ACC64
, "acc64" },
3283 { OPERAND_TYPE_IMM8
, "i8" },
3284 { OPERAND_TYPE_IMM8
, "i8s" },
3285 { OPERAND_TYPE_IMM16
, "i16" },
3286 { OPERAND_TYPE_IMM32
, "i32" },
3287 { OPERAND_TYPE_IMM32S
, "i32s" },
3288 { OPERAND_TYPE_IMM64
, "i64" },
3289 { OPERAND_TYPE_IMM1
, "i1" },
3290 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3291 { OPERAND_TYPE_DISP8
, "d8" },
3292 { OPERAND_TYPE_DISP16
, "d16" },
3293 { OPERAND_TYPE_DISP32
, "d32" },
3294 { OPERAND_TYPE_DISP32S
, "d32s" },
3295 { OPERAND_TYPE_DISP64
, "d64" },
3296 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3297 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3298 { OPERAND_TYPE_CONTROL
, "control reg" },
3299 { OPERAND_TYPE_TEST
, "test reg" },
3300 { OPERAND_TYPE_DEBUG
, "debug reg" },
3301 { OPERAND_TYPE_FLOATREG
, "FReg" },
3302 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3303 { OPERAND_TYPE_SREG
, "SReg" },
3304 { OPERAND_TYPE_REGMMX
, "rMMX" },
3305 { OPERAND_TYPE_REGXMM
, "rXMM" },
3306 { OPERAND_TYPE_REGYMM
, "rYMM" },
3307 { OPERAND_TYPE_REGZMM
, "rZMM" },
3308 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3312 pt (i386_operand_type t
)
3315 i386_operand_type a
;
3317 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3319 a
= operand_type_and (t
, type_names
[j
].mask
);
3320 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3321 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3326 #endif /* DEBUG386 */
3328 static bfd_reloc_code_real_type
3329 reloc (unsigned int size
,
3332 bfd_reloc_code_real_type other
)
3334 if (other
!= NO_RELOC
)
3336 reloc_howto_type
*rel
;
3341 case BFD_RELOC_X86_64_GOT32
:
3342 return BFD_RELOC_X86_64_GOT64
;
3344 case BFD_RELOC_X86_64_GOTPLT64
:
3345 return BFD_RELOC_X86_64_GOTPLT64
;
3347 case BFD_RELOC_X86_64_PLTOFF64
:
3348 return BFD_RELOC_X86_64_PLTOFF64
;
3350 case BFD_RELOC_X86_64_GOTPC32
:
3351 other
= BFD_RELOC_X86_64_GOTPC64
;
3353 case BFD_RELOC_X86_64_GOTPCREL
:
3354 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3356 case BFD_RELOC_X86_64_TPOFF32
:
3357 other
= BFD_RELOC_X86_64_TPOFF64
;
3359 case BFD_RELOC_X86_64_DTPOFF32
:
3360 other
= BFD_RELOC_X86_64_DTPOFF64
;
3366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3367 if (other
== BFD_RELOC_SIZE32
)
3370 other
= BFD_RELOC_SIZE64
;
3373 as_bad (_("there are no pc-relative size relocations"));
3379 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3380 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3383 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3385 as_bad (_("unknown relocation (%u)"), other
);
3386 else if (size
!= bfd_get_reloc_size (rel
))
3387 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3388 bfd_get_reloc_size (rel
),
3390 else if (pcrel
&& !rel
->pc_relative
)
3391 as_bad (_("non-pc-relative relocation for pc-relative field"));
3392 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3394 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3396 as_bad (_("relocated field and relocation type differ in signedness"));
3405 as_bad (_("there are no unsigned pc-relative relocations"));
3408 case 1: return BFD_RELOC_8_PCREL
;
3409 case 2: return BFD_RELOC_16_PCREL
;
3410 case 4: return BFD_RELOC_32_PCREL
;
3411 case 8: return BFD_RELOC_64_PCREL
;
3413 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3420 case 4: return BFD_RELOC_X86_64_32S
;
3425 case 1: return BFD_RELOC_8
;
3426 case 2: return BFD_RELOC_16
;
3427 case 4: return BFD_RELOC_32
;
3428 case 8: return BFD_RELOC_64
;
3430 as_bad (_("cannot do %s %u byte relocation"),
3431 sign
> 0 ? "signed" : "unsigned", size
);
3437 /* Here we decide which fixups can be adjusted to make them relative to
3438 the beginning of the section instead of the symbol. Basically we need
3439 to make sure that the dynamic relocations are done correctly, so in
3440 some cases we force the original symbol to be used. */
3443 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3449 /* Don't adjust pc-relative references to merge sections in 64-bit
3451 if (use_rela_relocations
3452 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3456 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3457 and changed later by validate_fix. */
3458 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3459 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3462 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3463 for size relocations. */
3464 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3465 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3468 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3501 intel_float_operand (const char *mnemonic
)
3503 /* Note that the value returned is meaningful only for opcodes with (memory)
3504 operands, hence the code here is free to improperly handle opcodes that
3505 have no operands (for better performance and smaller code). */
3507 if (mnemonic
[0] != 'f')
3508 return 0; /* non-math */
3510 switch (mnemonic
[1])
3512 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3513 the fs segment override prefix not currently handled because no
3514 call path can make opcodes without operands get here */
3516 return 2 /* integer op */;
3518 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3519 return 3; /* fldcw/fldenv */
3522 if (mnemonic
[2] != 'o' /* fnop */)
3523 return 3; /* non-waiting control op */
3526 if (mnemonic
[2] == 's')
3527 return 3; /* frstor/frstpm */
3530 if (mnemonic
[2] == 'a')
3531 return 3; /* fsave */
3532 if (mnemonic
[2] == 't')
3534 switch (mnemonic
[3])
3536 case 'c': /* fstcw */
3537 case 'd': /* fstdw */
3538 case 'e': /* fstenv */
3539 case 's': /* fsts[gw] */
3545 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3546 return 0; /* fxsave/fxrstor are not really math ops */
3553 /* Build the VEX prefix. */
3556 build_vex_prefix (const insn_template
*t
)
3558 unsigned int register_specifier
;
3559 unsigned int implied_prefix
;
3560 unsigned int vector_length
;
3563 /* Check register specifier. */
3564 if (i
.vex
.register_specifier
)
3566 register_specifier
=
3567 ~register_number (i
.vex
.register_specifier
) & 0xf;
3568 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3571 register_specifier
= 0xf;
3573 /* Use 2-byte VEX prefix by swapping destination and source operand
3574 if there are more than 1 register operand. */
3575 if (i
.reg_operands
> 1
3576 && i
.vec_encoding
!= vex_encoding_vex3
3577 && i
.dir_encoding
== dir_encoding_default
3578 && i
.operands
== i
.reg_operands
3579 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3580 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3581 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3584 unsigned int xchg
= i
.operands
- 1;
3585 union i386_op temp_op
;
3586 i386_operand_type temp_type
;
3588 temp_type
= i
.types
[xchg
];
3589 i
.types
[xchg
] = i
.types
[0];
3590 i
.types
[0] = temp_type
;
3591 temp_op
= i
.op
[xchg
];
3592 i
.op
[xchg
] = i
.op
[0];
3595 gas_assert (i
.rm
.mode
== 3);
3599 i
.rm
.regmem
= i
.rm
.reg
;
3602 if (i
.tm
.opcode_modifier
.d
)
3603 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3604 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3605 else /* Use the next insn. */
3609 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3610 are no memory operands and at least 3 register ones. */
3611 if (i
.reg_operands
>= 3
3612 && i
.vec_encoding
!= vex_encoding_vex3
3613 && i
.reg_operands
== i
.operands
- i
.imm_operands
3614 && i
.tm
.opcode_modifier
.vex
3615 && i
.tm
.opcode_modifier
.commutative
3616 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3618 && i
.vex
.register_specifier
3619 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3621 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3622 union i386_op temp_op
;
3623 i386_operand_type temp_type
;
3625 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3626 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3627 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3628 &i
.types
[i
.operands
- 3]));
3629 gas_assert (i
.rm
.mode
== 3);
3631 temp_type
= i
.types
[xchg
];
3632 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3633 i
.types
[xchg
+ 1] = temp_type
;
3634 temp_op
= i
.op
[xchg
];
3635 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3636 i
.op
[xchg
+ 1] = temp_op
;
3639 xchg
= i
.rm
.regmem
| 8;
3640 i
.rm
.regmem
= ~register_specifier
& 0xf;
3641 gas_assert (!(i
.rm
.regmem
& 8));
3642 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3643 register_specifier
= ~xchg
& 0xf;
3646 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3647 vector_length
= avxscalar
;
3648 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3654 /* Determine vector length from the last multi-length vector
3657 for (op
= t
->operands
; op
--;)
3658 if (t
->operand_types
[op
].bitfield
.xmmword
3659 && t
->operand_types
[op
].bitfield
.ymmword
3660 && i
.types
[op
].bitfield
.ymmword
)
3667 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3672 case DATA_PREFIX_OPCODE
:
3675 case REPE_PREFIX_OPCODE
:
3678 case REPNE_PREFIX_OPCODE
:
3685 /* Check the REX.W bit and VEXW. */
3686 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3687 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3688 else if (i
.tm
.opcode_modifier
.vexw
)
3689 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3691 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3693 /* Use 2-byte VEX prefix if possible. */
3695 && i
.vec_encoding
!= vex_encoding_vex3
3696 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3697 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3699 /* 2-byte VEX prefix. */
3703 i
.vex
.bytes
[0] = 0xc5;
3705 /* Check the REX.R bit. */
3706 r
= (i
.rex
& REX_R
) ? 0 : 1;
3707 i
.vex
.bytes
[1] = (r
<< 7
3708 | register_specifier
<< 3
3709 | vector_length
<< 2
3714 /* 3-byte VEX prefix. */
3719 switch (i
.tm
.opcode_modifier
.vexopcode
)
3723 i
.vex
.bytes
[0] = 0xc4;
3727 i
.vex
.bytes
[0] = 0xc4;
3731 i
.vex
.bytes
[0] = 0xc4;
3735 i
.vex
.bytes
[0] = 0x8f;
3739 i
.vex
.bytes
[0] = 0x8f;
3743 i
.vex
.bytes
[0] = 0x8f;
3749 /* The high 3 bits of the second VEX byte are 1's compliment
3750 of RXB bits from REX. */
3751 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3753 i
.vex
.bytes
[2] = (w
<< 7
3754 | register_specifier
<< 3
3755 | vector_length
<< 2
3760 static INLINE bfd_boolean
3761 is_evex_encoding (const insn_template
*t
)
3763 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3764 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3765 || t
->opcode_modifier
.sae
;
3768 static INLINE bfd_boolean
3769 is_any_vex_encoding (const insn_template
*t
)
3771 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3772 || is_evex_encoding (t
);
3775 /* Build the EVEX prefix. */
3778 build_evex_prefix (void)
3780 unsigned int register_specifier
;
3781 unsigned int implied_prefix
;
3783 rex_byte vrex_used
= 0;
3785 /* Check register specifier. */
3786 if (i
.vex
.register_specifier
)
3788 gas_assert ((i
.vrex
& REX_X
) == 0);
3790 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3791 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3792 register_specifier
+= 8;
3793 /* The upper 16 registers are encoded in the fourth byte of the
3795 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3796 i
.vex
.bytes
[3] = 0x8;
3797 register_specifier
= ~register_specifier
& 0xf;
3801 register_specifier
= 0xf;
3803 /* Encode upper 16 vector index register in the fourth byte of
3805 if (!(i
.vrex
& REX_X
))
3806 i
.vex
.bytes
[3] = 0x8;
3811 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3816 case DATA_PREFIX_OPCODE
:
3819 case REPE_PREFIX_OPCODE
:
3822 case REPNE_PREFIX_OPCODE
:
3829 /* 4 byte EVEX prefix. */
3831 i
.vex
.bytes
[0] = 0x62;
3834 switch (i
.tm
.opcode_modifier
.vexopcode
)
3850 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3852 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3854 /* The fifth bit of the second EVEX byte is 1's compliment of the
3855 REX_R bit in VREX. */
3856 if (!(i
.vrex
& REX_R
))
3857 i
.vex
.bytes
[1] |= 0x10;
3861 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3863 /* When all operands are registers, the REX_X bit in REX is not
3864 used. We reuse it to encode the upper 16 registers, which is
3865 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3866 as 1's compliment. */
3867 if ((i
.vrex
& REX_B
))
3870 i
.vex
.bytes
[1] &= ~0x40;
3874 /* EVEX instructions shouldn't need the REX prefix. */
3875 i
.vrex
&= ~vrex_used
;
3876 gas_assert (i
.vrex
== 0);
3878 /* Check the REX.W bit and VEXW. */
3879 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3880 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3881 else if (i
.tm
.opcode_modifier
.vexw
)
3882 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3884 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3886 /* Encode the U bit. */
3887 implied_prefix
|= 0x4;
3889 /* The third byte of the EVEX prefix. */
3890 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3892 /* The fourth byte of the EVEX prefix. */
3893 /* The zeroing-masking bit. */
3894 if (i
.mask
&& i
.mask
->zeroing
)
3895 i
.vex
.bytes
[3] |= 0x80;
3897 /* Don't always set the broadcast bit if there is no RC. */
3900 /* Encode the vector length. */
3901 unsigned int vec_length
;
3903 if (!i
.tm
.opcode_modifier
.evex
3904 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3908 /* Determine vector length from the last multi-length vector
3910 for (op
= i
.operands
; op
--;)
3911 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3912 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3913 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3915 if (i
.types
[op
].bitfield
.zmmword
)
3917 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3920 else if (i
.types
[op
].bitfield
.ymmword
)
3922 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3925 else if (i
.types
[op
].bitfield
.xmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3932 switch (i
.broadcast
->bytes
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3972 i
.vex
.bytes
[3] |= vec_length
;
3973 /* Encode the broadcast bit. */
3975 i
.vex
.bytes
[3] |= 0x10;
3979 if (i
.rounding
->type
!= saeonly
)
3980 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3982 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3985 if (i
.mask
&& i
.mask
->mask
)
3986 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3990 process_immext (void)
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4002 gas_assert (i
.imm_operands
<= 1
4004 || (is_any_vex_encoding (&i
.tm
)
4005 && i
.operands
<= 4)));
4007 exp
= &im_expressions
[i
.imm_operands
++];
4008 i
.op
[i
.operands
].imms
= exp
;
4009 i
.types
[i
.operands
] = imm8
;
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= i
.tm
.extension_opcode
;
4013 i
.tm
.extension_opcode
= None
;
4020 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i
.tm
.name
, i
.hle_prefix
);
4029 if (i
.prefix
[LOCK_PREFIX
])
4031 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4035 case HLEPrefixRelease
:
4036 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4042 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i
.tm
.name
);
4052 /* Try the shortest encoding by shortening operand size. */
4055 optimize_encoding (void)
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i
.tm
)
4061 && i
.reg_operands
== 1
4062 && i
.imm_operands
== 1
4063 && !i
.types
[1].bitfield
.byte
4064 && i
.op
[0].imms
->X_op
== O_constant
4065 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4066 && (i
.tm
.base_opcode
== 0xa8
4067 || (i
.tm
.base_opcode
== 0xf6
4068 && i
.tm
.extension_opcode
== 0x0)))
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4073 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4074 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4076 i
.types
[1].bitfield
.byte
= 1;
4077 /* Ignore the suffix. */
4079 /* Convert to byte registers. */
4080 if (i
.types
[1].bitfield
.word
)
4082 else if (i
.types
[1].bitfield
.dword
)
4086 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4091 else if (flag_code
== CODE_64BIT
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && ((i
.types
[1].bitfield
.qword
4094 && i
.reg_operands
== 1
4095 && i
.imm_operands
== 1
4096 && i
.op
[0].imms
->X_op
== O_constant
4097 && ((i
.tm
.base_opcode
== 0xb8
4098 && i
.tm
.extension_opcode
== None
4099 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4100 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4101 && ((i
.tm
.base_opcode
== 0x24
4102 || i
.tm
.base_opcode
== 0xa8)
4103 || (i
.tm
.base_opcode
== 0x80
4104 && i
.tm
.extension_opcode
== 0x4)
4105 || ((i
.tm
.base_opcode
== 0xf6
4106 || (i
.tm
.base_opcode
| 1) == 0xc7)
4107 && i
.tm
.extension_opcode
== 0x0)))
4108 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4109 && i
.tm
.base_opcode
== 0x83
4110 && i
.tm
.extension_opcode
== 0x4)))
4111 || (i
.types
[0].bitfield
.qword
4112 && ((i
.reg_operands
== 2
4113 && i
.op
[0].regs
== i
.op
[1].regs
4114 && (i
.tm
.base_opcode
== 0x30
4115 || i
.tm
.base_opcode
== 0x28))
4116 || (i
.reg_operands
== 1
4118 && i
.tm
.base_opcode
== 0x30)))))
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4129 i
.tm
.opcode_modifier
.norex64
= 1;
4130 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4136 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4137 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4138 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4139 i
.types
[0].bitfield
.imm32
= 1;
4140 i
.types
[0].bitfield
.imm32s
= 0;
4141 i
.types
[0].bitfield
.imm64
= 0;
4142 i
.types
[1].bitfield
.dword
= 1;
4143 i
.types
[1].bitfield
.qword
= 0;
4144 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4147 movq $imm31, %r64 -> movl $imm31, %r32
4149 i
.tm
.base_opcode
= 0xb8;
4150 i
.tm
.extension_opcode
= None
;
4151 i
.tm
.opcode_modifier
.w
= 0;
4152 i
.tm
.opcode_modifier
.modrm
= 0;
4156 else if (optimize
> 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i
.tm
)
4159 && i
.reg_operands
== 2
4160 && i
.op
[0].regs
== i
.op
[1].regs
4161 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4162 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4163 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4173 and outside of 64-bit mode
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4178 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4180 else if (i
.reg_operands
== 3
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && !i
.types
[2].bitfield
.xmmword
4183 && (i
.tm
.opcode_modifier
.vex
4184 || ((!i
.mask
|| i
.mask
->zeroing
)
4186 && is_evex_encoding (&i
.tm
)
4187 && (i
.vec_encoding
!= vex_encoding_evex
4188 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4189 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4190 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4191 && i
.types
[2].bitfield
.ymmword
))))
4192 && ((i
.tm
.base_opcode
== 0x55
4193 || i
.tm
.base_opcode
== 0x6655
4194 || i
.tm
.base_opcode
== 0x66df
4195 || i
.tm
.base_opcode
== 0x57
4196 || i
.tm
.base_opcode
== 0x6657
4197 || i
.tm
.base_opcode
== 0x66ef
4198 || i
.tm
.base_opcode
== 0x66f8
4199 || i
.tm
.base_opcode
== 0x66f9
4200 || i
.tm
.base_opcode
== 0x66fa
4201 || i
.tm
.base_opcode
== 0x66fb
4202 || i
.tm
.base_opcode
== 0x42
4203 || i
.tm
.base_opcode
== 0x6642
4204 || i
.tm
.base_opcode
== 0x47
4205 || i
.tm
.base_opcode
== 0x6647)
4206 && i
.tm
.extension_opcode
== None
))
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4243 if (is_evex_encoding (&i
.tm
))
4245 if (i
.vec_encoding
!= vex_encoding_evex
)
4247 i
.tm
.opcode_modifier
.vex
= VEX128
;
4248 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4249 i
.tm
.opcode_modifier
.evex
= 0;
4251 else if (optimize
> 1)
4252 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4256 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4258 i
.tm
.base_opcode
&= 0xff;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.vex
= VEX128
;
4264 if (i
.tm
.opcode_modifier
.vex
)
4265 for (j
= 0; j
< 3; j
++)
4267 i
.types
[j
].bitfield
.xmmword
= 1;
4268 i
.types
[j
].bitfield
.ymmword
= 0;
4271 else if (i
.vec_encoding
!= vex_encoding_evex
4272 && !i
.types
[0].bitfield
.zmmword
4273 && !i
.types
[1].bitfield
.zmmword
4276 && is_evex_encoding (&i
.tm
)
4277 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4279 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4280 || (i
.tm
.base_opcode
& ~4) == 0x66db
4281 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4282 && i
.tm
.extension_opcode
== None
)
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4309 for (j
= 0; j
< i
.operands
; j
++)
4310 if (operand_type_check (i
.types
[j
], disp
)
4311 && i
.op
[j
].disps
->X_op
== O_constant
)
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8
, vex_disp8
;
4317 unsigned int memshift
= i
.memshift
;
4318 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4320 evex_disp8
= fits_in_disp8 (n
);
4322 vex_disp8
= fits_in_disp8 (n
);
4323 if (evex_disp8
!= vex_disp8
)
4325 i
.memshift
= memshift
;
4329 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4332 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4333 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4334 i
.tm
.opcode_modifier
.vex
4335 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4336 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4339 i
.tm
.opcode_modifier
.commutative
= 1;
4340 i
.tm
.opcode_modifier
.evex
= 0;
4341 i
.tm
.opcode_modifier
.masking
= 0;
4342 i
.tm
.opcode_modifier
.broadcast
= 0;
4343 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4346 i
.types
[j
].bitfield
.disp8
4347 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4351 /* Return non-zero for load instruction. */
4357 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4358 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i
.tm
.opcode_modifier
.anysize
)
4368 /* pop, popf, popa. */
4369 if (strcmp (i
.tm
.name
, "pop") == 0
4370 || i
.tm
.base_opcode
== 0x9d
4371 || i
.tm
.base_opcode
== 0x61)
4374 /* movs, cmps, lods, scas. */
4375 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4379 if (base_opcode
== 0x6f
4380 || i
.tm
.base_opcode
== 0xd7)
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4386 /* No memory operand. */
4387 if (!i
.mem_operands
)
4393 if (i
.tm
.base_opcode
== 0xae
4394 && i
.tm
.opcode_modifier
.vex
4395 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4396 && i
.tm
.extension_opcode
== 2)
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4403 && i
.tm
.extension_opcode
!= 1)
4407 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4414 /* bt, bts, btr, btc. */
4415 if (i
.tm
.base_opcode
== 0xfba
4416 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode
== 0xc1
4421 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4422 && i
.tm
.extension_opcode
!= 6)
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i
.tm
.base_opcode
== 0xfc7
4427 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i
.tm
.base_opcode
== 0xfae
4432 && (i
.tm
.extension_opcode
== 1
4433 || i
.tm
.extension_opcode
== 2
4434 || i
.tm
.extension_opcode
== 5))
4437 /* lgdt, lidt, lmsw. */
4438 if (i
.tm
.base_opcode
== 0xf01
4439 && (i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 6))
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.extension_opcode
== 6)
4449 /* Check for x87 instructions. */
4450 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i
.tm
.base_opcode
== 0xd9
4454 && (i
.tm
.extension_opcode
== 2
4455 || i
.tm
.extension_opcode
== 3
4456 || i
.tm
.extension_opcode
== 6
4457 || i
.tm
.extension_opcode
== 7))
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i
.tm
.base_opcode
== 0xdb
4462 && (i
.tm
.extension_opcode
== 1
4463 || i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 7))
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i
.tm
.base_opcode
== 0xdd
4470 && (i
.tm
.extension_opcode
== 1
4471 || i
.tm
.extension_opcode
== 2
4472 || i
.tm
.extension_opcode
== 3
4473 || i
.tm
.extension_opcode
== 6
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i
.tm
.base_opcode
== 0xdf
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4490 dest
= i
.operands
- 1;
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i
.tm
.opcode_modifier
.immext
4494 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4495 && i
.types
[dest
].bitfield
.imm8
)
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4500 && (base_opcode
== 0x1
4501 || base_opcode
== 0x9
4502 || base_opcode
== 0x11
4503 || base_opcode
== 0x19
4504 || base_opcode
== 0x21
4505 || base_opcode
== 0x29
4506 || base_opcode
== 0x31
4507 || base_opcode
== 0x39
4508 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4509 || base_opcode
== 0xfc1))
4512 /* Check for load instruction. */
4513 return (i
.types
[dest
].bitfield
.class != ClassNone
4514 || i
.types
[dest
].bitfield
.instance
== Accum
);
4517 /* Output lfence, 0xfaee8, after instruction. */
4520 insert_lfence_after (void)
4522 if (lfence_after_load
&& load_insn_p ())
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4533 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4534 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4535 && i
.prefix
[REP_PREFIX
])
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4540 char *p
= frag_more (3);
4547 /* Output lfence, 0xfaee8, before instruction. */
4550 insert_lfence_before (void)
4554 if (is_any_vex_encoding (&i
.tm
))
4557 if (i
.tm
.base_opcode
== 0xff
4558 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4560 /* Insert lfence before indirect branch if needed. */
4562 if (lfence_before_indirect_branch
== lfence_branch_none
)
4565 if (i
.operands
!= 1)
4568 if (i
.reg_operands
== 1)
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch
== lfence_branch_memory
)
4576 else if (i
.mem_operands
== 1
4577 && lfence_before_indirect_branch
!= lfence_branch_register
)
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4586 if (last_insn
.kind
!= last_insn_other
4587 && last_insn
.seg
== now_seg
)
4589 as_warn_where (last_insn
.file
, last_insn
.line
,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn
.name
, i
.tm
.name
);
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret
!= lfence_before_ret_none
4604 && (i
.tm
.base_opcode
== 0xc2
4605 || i
.tm
.base_opcode
== 0xc3))
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix
= flag_code
== CODE_64BIT
4619 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4621 if (lfence_before_ret
== lfence_before_ret_not
)
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4639 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4642 if (lfence_before_ret
== lfence_before_ret_or
)
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4667 /* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4672 md_assemble (char *line
)
4675 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4676 const insn_template
*t
;
4678 /* Initialize globals. */
4679 memset (&i
, '\0', sizeof (i
));
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 i
.reloc
[j
] = NO_RELOC
;
4682 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4683 memset (im_expressions
, '\0', sizeof (im_expressions
));
4684 save_stack_p
= save_stack
;
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4690 line
= parse_insn (line
, mnemonic
);
4693 mnem_suffix
= i
.suffix
;
4695 line
= parse_operands (line
, mnemonic
);
4697 xfree (i
.memop1_string
);
4698 i
.memop1_string
= NULL
;
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4712 && (strcmp (mnemonic
, "bound") != 0)
4713 && (strcmp (mnemonic
, "invlpga") != 0)
4714 && (strncmp (mnemonic
, "monitor", 7) != 0)
4715 && (strncmp (mnemonic
, "mwait", 5) != 0)
4716 && (strcmp (mnemonic
, "tpause") != 0)
4717 && (strcmp (mnemonic
, "umwait") != 0)
4718 && !(operand_type_check (i
.types
[0], imm
)
4719 && operand_type_check (i
.types
[1], imm
)))
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i
.imm_operands
== 2
4725 && (strcmp (mnemonic
, "extrq") == 0
4726 || strcmp (mnemonic
, "insertq") == 0))
4727 swap_2_operands (0, 1);
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4735 && i
.disp_encoding
!= disp_encoding_32bit
4736 && (flag_code
!= CODE_64BIT
4737 || strcmp (mnemonic
, "movabs") != 0))
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4744 if (!(t
= match_template (mnem_suffix
)))
4747 if (sse_check
!= check_none
4748 && !i
.tm
.opcode_modifier
.noavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4750 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4751 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4756 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4757 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4758 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4759 || i
.tm
.cpu_flags
.bitfield
.cpusha
4760 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4762 (sse_check
== check_warning
4764 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4767 if (i
.tm
.opcode_modifier
.fwait
)
4768 if (!add_prefix (FWAIT_OPCODE
))
4771 /* Check if REP prefix is OK. */
4772 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i
.tm
.name
, i
.rep_prefix
);
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i
.prefix
[LOCK_PREFIX
]
4782 && (!i
.tm
.opcode_modifier
.islockable
4783 || i
.mem_operands
== 0
4784 || (i
.tm
.base_opcode
!= 0x86
4785 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4787 as_bad (_("expecting lockable instruction after `lock'"));
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4792 if (i
.prefix
[DATA_PREFIX
]
4793 && (is_any_vex_encoding (&i
.tm
)
4794 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4795 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4797 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4801 /* Check if HLE prefix is OK. */
4802 if (i
.hle_prefix
&& !check_hle ())
4805 /* Check BND prefix. */
4806 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4807 as_bad (_("expecting valid branch instruction after `bnd'"));
4809 /* Check NOTRACK prefix. */
4810 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4811 as_bad (_("expecting indirect branch instruction after `notrack'"));
4813 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4815 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4816 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4817 else if (flag_code
!= CODE_16BIT
4818 ? i
.prefix
[ADDR_PREFIX
]
4819 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4820 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4823 /* Insert BND prefix. */
4824 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4826 if (!i
.prefix
[BND_PREFIX
])
4827 add_prefix (BND_PREFIX_OPCODE
);
4828 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4830 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4831 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4835 /* Check string instruction segment overrides. */
4836 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4838 gas_assert (i
.mem_operands
);
4839 if (!check_string ())
4841 i
.disp_operands
= 0;
4844 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4845 optimize_encoding ();
4847 if (!process_suffix ())
4850 /* Update operand types. */
4851 for (j
= 0; j
< i
.operands
; j
++)
4852 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4854 /* Make still unresolved immediate matches conform to size of immediate
4855 given in i.suffix. */
4856 if (!finalize_imm ())
4859 if (i
.types
[0].bitfield
.imm1
)
4860 i
.imm_operands
= 0; /* kludge for shift insns. */
4862 /* We only need to check those implicit registers for instructions
4863 with 3 operands or less. */
4864 if (i
.operands
<= 3)
4865 for (j
= 0; j
< i
.operands
; j
++)
4866 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4867 && !i
.types
[j
].bitfield
.xmmword
)
4870 /* ImmExt should be processed after SSE2AVX. */
4871 if (!i
.tm
.opcode_modifier
.sse2avx
4872 && i
.tm
.opcode_modifier
.immext
)
4875 /* For insns with operands there are more diddles to do to the opcode. */
4878 if (!process_operands ())
4881 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4883 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4884 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4887 if (is_any_vex_encoding (&i
.tm
))
4889 if (!cpu_arch_flags
.bitfield
.cpui286
)
4891 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4896 if (i
.tm
.opcode_modifier
.vex
)
4897 build_vex_prefix (t
);
4899 build_evex_prefix ();
4902 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4903 instructions may define INT_OPCODE as well, so avoid this corner
4904 case for those instructions that use MODRM. */
4905 if (i
.tm
.base_opcode
== INT_OPCODE
4906 && !i
.tm
.opcode_modifier
.modrm
4907 && i
.op
[0].imms
->X_add_number
== 3)
4909 i
.tm
.base_opcode
= INT3_OPCODE
;
4913 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4914 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4915 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4916 && i
.op
[0].disps
->X_op
== O_constant
)
4918 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4919 the absolute address given by the constant. Since ix86 jumps and
4920 calls are pc relative, we need to generate a reloc. */
4921 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4922 i
.op
[0].disps
->X_op
= O_symbol
;
4925 /* For 8 bit registers we need an empty rex prefix. Also if the
4926 instruction already has a prefix, we need to convert old
4927 registers to new ones. */
4929 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4930 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4931 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4932 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4933 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4934 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4939 i
.rex
|= REX_OPCODE
;
4940 for (x
= 0; x
< 2; x
++)
4942 /* Look for 8 bit operand that uses old registers. */
4943 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4944 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4946 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4947 /* In case it is "hi" register, give up. */
4948 if (i
.op
[x
].regs
->reg_num
> 3)
4949 as_bad (_("can't encode register '%s%s' in an "
4950 "instruction requiring REX prefix."),
4951 register_prefix
, i
.op
[x
].regs
->reg_name
);
4953 /* Otherwise it is equivalent to the extended register.
4954 Since the encoding doesn't change this is merely
4955 cosmetic cleanup for debug output. */
4957 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4962 if (i
.rex
== 0 && i
.rex_encoding
)
4964 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4965 that uses legacy register. If it is "hi" register, don't add
4966 the REX_OPCODE byte. */
4968 for (x
= 0; x
< 2; x
++)
4969 if (i
.types
[x
].bitfield
.class == Reg
4970 && i
.types
[x
].bitfield
.byte
4971 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4972 && i
.op
[x
].regs
->reg_num
> 3)
4974 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4975 i
.rex_encoding
= FALSE
;
4984 add_prefix (REX_OPCODE
| i
.rex
);
4986 insert_lfence_before ();
4988 /* We are ready to output the insn. */
4991 insert_lfence_after ();
4993 last_insn
.seg
= now_seg
;
4995 if (i
.tm
.opcode_modifier
.isprefix
)
4997 last_insn
.kind
= last_insn_prefix
;
4998 last_insn
.name
= i
.tm
.name
;
4999 last_insn
.file
= as_where (&last_insn
.line
);
5002 last_insn
.kind
= last_insn_other
;
5006 parse_insn (char *line
, char *mnemonic
)
5009 char *token_start
= l
;
5012 const insn_template
*t
;
5018 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5023 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5025 as_bad (_("no such instruction: `%s'"), token_start
);
5030 if (!is_space_char (*l
)
5031 && *l
!= END_OF_INSN
5033 || (*l
!= PREFIX_SEPARATOR
5036 as_bad (_("invalid character %s in mnemonic"),
5037 output_invalid (*l
));
5040 if (token_start
== l
)
5042 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5043 as_bad (_("expecting prefix; got nothing"));
5045 as_bad (_("expecting mnemonic; got nothing"));
5049 /* Look up instruction (or prefix) via hash table. */
5050 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5052 if (*l
!= END_OF_INSN
5053 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5054 && current_templates
5055 && current_templates
->start
->opcode_modifier
.isprefix
)
5057 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5059 as_bad ((flag_code
!= CODE_64BIT
5060 ? _("`%s' is only supported in 64-bit mode")
5061 : _("`%s' is not supported in 64-bit mode")),
5062 current_templates
->start
->name
);
5065 /* If we are in 16-bit mode, do not allow addr16 or data16.
5066 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5067 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5068 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5069 && flag_code
!= CODE_64BIT
5070 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5071 ^ (flag_code
== CODE_16BIT
)))
5073 as_bad (_("redundant %s prefix"),
5074 current_templates
->start
->name
);
5077 if (current_templates
->start
->opcode_length
== 0)
5079 /* Handle pseudo prefixes. */
5080 switch (current_templates
->start
->base_opcode
)
5084 i
.disp_encoding
= disp_encoding_8bit
;
5088 i
.disp_encoding
= disp_encoding_32bit
;
5092 i
.dir_encoding
= dir_encoding_load
;
5096 i
.dir_encoding
= dir_encoding_store
;
5100 i
.vec_encoding
= vex_encoding_vex
;
5104 i
.vec_encoding
= vex_encoding_vex3
;
5108 i
.vec_encoding
= vex_encoding_evex
;
5112 i
.rex_encoding
= TRUE
;
5116 i
.no_optimize
= TRUE
;
5124 /* Add prefix, checking for repeated prefixes. */
5125 switch (add_prefix (current_templates
->start
->base_opcode
))
5130 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5131 i
.notrack_prefix
= current_templates
->start
->name
;
5134 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5135 i
.hle_prefix
= current_templates
->start
->name
;
5136 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5137 i
.bnd_prefix
= current_templates
->start
->name
;
5139 i
.rep_prefix
= current_templates
->start
->name
;
5145 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5152 if (!current_templates
)
5154 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5155 Check if we should swap operand or force 32bit displacement in
5157 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5158 i
.dir_encoding
= dir_encoding_swap
;
5159 else if (mnem_p
- 3 == dot_p
5162 i
.disp_encoding
= disp_encoding_8bit
;
5163 else if (mnem_p
- 4 == dot_p
5167 i
.disp_encoding
= disp_encoding_32bit
;
5172 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5175 if (!current_templates
)
5178 if (mnem_p
> mnemonic
)
5180 /* See if we can get a match by trimming off a suffix. */
5183 case WORD_MNEM_SUFFIX
:
5184 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5185 i
.suffix
= SHORT_MNEM_SUFFIX
;
5188 case BYTE_MNEM_SUFFIX
:
5189 case QWORD_MNEM_SUFFIX
:
5190 i
.suffix
= mnem_p
[-1];
5192 current_templates
= (const templates
*) hash_find (op_hash
,
5195 case SHORT_MNEM_SUFFIX
:
5196 case LONG_MNEM_SUFFIX
:
5199 i
.suffix
= mnem_p
[-1];
5201 current_templates
= (const templates
*) hash_find (op_hash
,
5210 if (intel_float_operand (mnemonic
) == 1)
5211 i
.suffix
= SHORT_MNEM_SUFFIX
;
5213 i
.suffix
= LONG_MNEM_SUFFIX
;
5215 current_templates
= (const templates
*) hash_find (op_hash
,
5222 if (!current_templates
)
5224 as_bad (_("no such instruction: `%s'"), token_start
);
5229 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5230 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5232 /* Check for a branch hint. We allow ",pt" and ",pn" for
5233 predict taken and predict not taken respectively.
5234 I'm not sure that branch hints actually do anything on loop
5235 and jcxz insns (JumpByte) for current Pentium4 chips. They
5236 may work in the future and it doesn't hurt to accept them
5238 if (l
[0] == ',' && l
[1] == 'p')
5242 if (!add_prefix (DS_PREFIX_OPCODE
))
5246 else if (l
[2] == 'n')
5248 if (!add_prefix (CS_PREFIX_OPCODE
))
5254 /* Any other comma loses. */
5257 as_bad (_("invalid character %s in mnemonic"),
5258 output_invalid (*l
));
5262 /* Check if instruction is supported on specified architecture. */
5264 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5266 supported
|= cpu_flags_match (t
);
5267 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5269 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5270 as_warn (_("use .code16 to ensure correct addressing mode"));
5276 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5277 as_bad (flag_code
== CODE_64BIT
5278 ? _("`%s' is not supported in 64-bit mode")
5279 : _("`%s' is only supported in 64-bit mode"),
5280 current_templates
->start
->name
);
5282 as_bad (_("`%s' is not supported on `%s%s'"),
5283 current_templates
->start
->name
,
5284 cpu_arch_name
? cpu_arch_name
: default_arch
,
5285 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5291 parse_operands (char *l
, const char *mnemonic
)
5295 /* 1 if operand is pending after ','. */
5296 unsigned int expecting_operand
= 0;
5298 /* Non-zero if operand parens not balanced. */
5299 unsigned int paren_not_balanced
;
5301 while (*l
!= END_OF_INSN
)
5303 /* Skip optional white space before operand. */
5304 if (is_space_char (*l
))
5306 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5308 as_bad (_("invalid character %s before operand %d"),
5309 output_invalid (*l
),
5313 token_start
= l
; /* After white space. */
5314 paren_not_balanced
= 0;
5315 while (paren_not_balanced
|| *l
!= ',')
5317 if (*l
== END_OF_INSN
)
5319 if (paren_not_balanced
)
5322 as_bad (_("unbalanced parenthesis in operand %d."),
5325 as_bad (_("unbalanced brackets in operand %d."),
5330 break; /* we are done */
5332 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5334 as_bad (_("invalid character %s in operand %d"),
5335 output_invalid (*l
),
5342 ++paren_not_balanced
;
5344 --paren_not_balanced
;
5349 ++paren_not_balanced
;
5351 --paren_not_balanced
;
5355 if (l
!= token_start
)
5356 { /* Yes, we've read in another operand. */
5357 unsigned int operand_ok
;
5358 this_operand
= i
.operands
++;
5359 if (i
.operands
> MAX_OPERANDS
)
5361 as_bad (_("spurious operands; (%d operands/instruction max)"),
5365 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5366 /* Now parse operand adding info to 'i' as we go along. */
5367 END_STRING_AND_SAVE (l
);
5369 if (i
.mem_operands
> 1)
5371 as_bad (_("too many memory references for `%s'"),
5378 i386_intel_operand (token_start
,
5379 intel_float_operand (mnemonic
));
5381 operand_ok
= i386_att_operand (token_start
);
5383 RESTORE_END_STRING (l
);
5389 if (expecting_operand
)
5391 expecting_operand_after_comma
:
5392 as_bad (_("expecting operand after ','; got nothing"));
5397 as_bad (_("expecting operand before ','; got nothing"));
5402 /* Now *l must be either ',' or END_OF_INSN. */
5405 if (*++l
== END_OF_INSN
)
5407 /* Just skip it, if it's \n complain. */
5408 goto expecting_operand_after_comma
;
5410 expecting_operand
= 1;
5417 swap_2_operands (int xchg1
, int xchg2
)
5419 union i386_op temp_op
;
5420 i386_operand_type temp_type
;
5421 unsigned int temp_flags
;
5422 enum bfd_reloc_code_real temp_reloc
;
5424 temp_type
= i
.types
[xchg2
];
5425 i
.types
[xchg2
] = i
.types
[xchg1
];
5426 i
.types
[xchg1
] = temp_type
;
5428 temp_flags
= i
.flags
[xchg2
];
5429 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5430 i
.flags
[xchg1
] = temp_flags
;
5432 temp_op
= i
.op
[xchg2
];
5433 i
.op
[xchg2
] = i
.op
[xchg1
];
5434 i
.op
[xchg1
] = temp_op
;
5436 temp_reloc
= i
.reloc
[xchg2
];
5437 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5438 i
.reloc
[xchg1
] = temp_reloc
;
5442 if (i
.mask
->operand
== xchg1
)
5443 i
.mask
->operand
= xchg2
;
5444 else if (i
.mask
->operand
== xchg2
)
5445 i
.mask
->operand
= xchg1
;
5449 if (i
.broadcast
->operand
== xchg1
)
5450 i
.broadcast
->operand
= xchg2
;
5451 else if (i
.broadcast
->operand
== xchg2
)
5452 i
.broadcast
->operand
= xchg1
;
5456 if (i
.rounding
->operand
== xchg1
)
5457 i
.rounding
->operand
= xchg2
;
5458 else if (i
.rounding
->operand
== xchg2
)
5459 i
.rounding
->operand
= xchg1
;
5464 swap_operands (void)
5470 swap_2_operands (1, i
.operands
- 2);
5474 swap_2_operands (0, i
.operands
- 1);
5480 if (i
.mem_operands
== 2)
5482 const seg_entry
*temp_seg
;
5483 temp_seg
= i
.seg
[0];
5484 i
.seg
[0] = i
.seg
[1];
5485 i
.seg
[1] = temp_seg
;
5489 /* Try to ensure constant immediates are represented in the smallest
5494 char guess_suffix
= 0;
5498 guess_suffix
= i
.suffix
;
5499 else if (i
.reg_operands
)
5501 /* Figure out a suffix from the last register operand specified.
5502 We can't do this properly yet, i.e. excluding special register
5503 instances, but the following works for instructions with
5504 immediates. In any case, we can't set i.suffix yet. */
5505 for (op
= i
.operands
; --op
>= 0;)
5506 if (i
.types
[op
].bitfield
.class != Reg
)
5508 else if (i
.types
[op
].bitfield
.byte
)
5510 guess_suffix
= BYTE_MNEM_SUFFIX
;
5513 else if (i
.types
[op
].bitfield
.word
)
5515 guess_suffix
= WORD_MNEM_SUFFIX
;
5518 else if (i
.types
[op
].bitfield
.dword
)
5520 guess_suffix
= LONG_MNEM_SUFFIX
;
5523 else if (i
.types
[op
].bitfield
.qword
)
5525 guess_suffix
= QWORD_MNEM_SUFFIX
;
5529 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5530 guess_suffix
= WORD_MNEM_SUFFIX
;
5532 for (op
= i
.operands
; --op
>= 0;)
5533 if (operand_type_check (i
.types
[op
], imm
))
5535 switch (i
.op
[op
].imms
->X_op
)
5538 /* If a suffix is given, this operand may be shortened. */
5539 switch (guess_suffix
)
5541 case LONG_MNEM_SUFFIX
:
5542 i
.types
[op
].bitfield
.imm32
= 1;
5543 i
.types
[op
].bitfield
.imm64
= 1;
5545 case WORD_MNEM_SUFFIX
:
5546 i
.types
[op
].bitfield
.imm16
= 1;
5547 i
.types
[op
].bitfield
.imm32
= 1;
5548 i
.types
[op
].bitfield
.imm32s
= 1;
5549 i
.types
[op
].bitfield
.imm64
= 1;
5551 case BYTE_MNEM_SUFFIX
:
5552 i
.types
[op
].bitfield
.imm8
= 1;
5553 i
.types
[op
].bitfield
.imm8s
= 1;
5554 i
.types
[op
].bitfield
.imm16
= 1;
5555 i
.types
[op
].bitfield
.imm32
= 1;
5556 i
.types
[op
].bitfield
.imm32s
= 1;
5557 i
.types
[op
].bitfield
.imm64
= 1;
5561 /* If this operand is at most 16 bits, convert it
5562 to a signed 16 bit number before trying to see
5563 whether it will fit in an even smaller size.
5564 This allows a 16-bit operand such as $0xffe0 to
5565 be recognised as within Imm8S range. */
5566 if ((i
.types
[op
].bitfield
.imm16
)
5567 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5569 i
.op
[op
].imms
->X_add_number
=
5570 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5573 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5574 if ((i
.types
[op
].bitfield
.imm32
)
5575 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5578 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5579 ^ ((offsetT
) 1 << 31))
5580 - ((offsetT
) 1 << 31));
5584 = operand_type_or (i
.types
[op
],
5585 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5587 /* We must avoid matching of Imm32 templates when 64bit
5588 only immediate is available. */
5589 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5590 i
.types
[op
].bitfield
.imm32
= 0;
5597 /* Symbols and expressions. */
5599 /* Convert symbolic operand to proper sizes for matching, but don't
5600 prevent matching a set of insns that only supports sizes other
5601 than those matching the insn suffix. */
5603 i386_operand_type mask
, allowed
;
5604 const insn_template
*t
;
5606 operand_type_set (&mask
, 0);
5607 operand_type_set (&allowed
, 0);
5609 for (t
= current_templates
->start
;
5610 t
< current_templates
->end
;
5613 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5614 allowed
= operand_type_and (allowed
, anyimm
);
5616 switch (guess_suffix
)
5618 case QWORD_MNEM_SUFFIX
:
5619 mask
.bitfield
.imm64
= 1;
5620 mask
.bitfield
.imm32s
= 1;
5622 case LONG_MNEM_SUFFIX
:
5623 mask
.bitfield
.imm32
= 1;
5625 case WORD_MNEM_SUFFIX
:
5626 mask
.bitfield
.imm16
= 1;
5628 case BYTE_MNEM_SUFFIX
:
5629 mask
.bitfield
.imm8
= 1;
5634 allowed
= operand_type_and (mask
, allowed
);
5635 if (!operand_type_all_zero (&allowed
))
5636 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5643 /* Try to use the smallest displacement type too. */
5645 optimize_disp (void)
5649 for (op
= i
.operands
; --op
>= 0;)
5650 if (operand_type_check (i
.types
[op
], disp
))
5652 if (i
.op
[op
].disps
->X_op
== O_constant
)
5654 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5656 if (i
.types
[op
].bitfield
.disp16
5657 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5659 /* If this operand is at most 16 bits, convert
5660 to a signed 16 bit number and don't use 64bit
5662 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5663 i
.types
[op
].bitfield
.disp64
= 0;
5666 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5667 if (i
.types
[op
].bitfield
.disp32
5668 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5670 /* If this operand is at most 32 bits, convert
5671 to a signed 32 bit number and don't use 64bit
5673 op_disp
&= (((offsetT
) 2 << 31) - 1);
5674 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5675 i
.types
[op
].bitfield
.disp64
= 0;
5678 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5680 i
.types
[op
].bitfield
.disp8
= 0;
5681 i
.types
[op
].bitfield
.disp16
= 0;
5682 i
.types
[op
].bitfield
.disp32
= 0;
5683 i
.types
[op
].bitfield
.disp32s
= 0;
5684 i
.types
[op
].bitfield
.disp64
= 0;
5688 else if (flag_code
== CODE_64BIT
)
5690 if (fits_in_signed_long (op_disp
))
5692 i
.types
[op
].bitfield
.disp64
= 0;
5693 i
.types
[op
].bitfield
.disp32s
= 1;
5695 if (i
.prefix
[ADDR_PREFIX
]
5696 && fits_in_unsigned_long (op_disp
))
5697 i
.types
[op
].bitfield
.disp32
= 1;
5699 if ((i
.types
[op
].bitfield
.disp32
5700 || i
.types
[op
].bitfield
.disp32s
5701 || i
.types
[op
].bitfield
.disp16
)
5702 && fits_in_disp8 (op_disp
))
5703 i
.types
[op
].bitfield
.disp8
= 1;
5705 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5706 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5708 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5709 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5710 i
.types
[op
].bitfield
.disp8
= 0;
5711 i
.types
[op
].bitfield
.disp16
= 0;
5712 i
.types
[op
].bitfield
.disp32
= 0;
5713 i
.types
[op
].bitfield
.disp32s
= 0;
5714 i
.types
[op
].bitfield
.disp64
= 0;
5717 /* We only support 64bit displacement on constants. */
5718 i
.types
[op
].bitfield
.disp64
= 0;
5722 /* Return 1 if there is a match in broadcast bytes between operand
5723 GIVEN and instruction template T. */
5726 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5728 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5729 && i
.types
[given
].bitfield
.byte
)
5730 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5731 && i
.types
[given
].bitfield
.word
)
5732 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5733 && i
.types
[given
].bitfield
.dword
)
5734 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5735 && i
.types
[given
].bitfield
.qword
));
5738 /* Check if operands are valid for the instruction. */
5741 check_VecOperands (const insn_template
*t
)
5746 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5747 any one operand are implicity requiring AVX512VL support if the actual
5748 operand size is YMMword or XMMword. Since this function runs after
5749 template matching, there's no need to check for YMMword/XMMword in
5751 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5752 if (!cpu_flags_all_zero (&cpu
)
5753 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5754 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5756 for (op
= 0; op
< t
->operands
; ++op
)
5758 if (t
->operand_types
[op
].bitfield
.zmmword
5759 && (i
.types
[op
].bitfield
.ymmword
5760 || i
.types
[op
].bitfield
.xmmword
))
5762 i
.error
= unsupported
;
5768 /* Without VSIB byte, we can't have a vector register for index. */
5769 if (!t
->opcode_modifier
.vecsib
5771 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5772 || i
.index_reg
->reg_type
.bitfield
.ymmword
5773 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5775 i
.error
= unsupported_vector_index_register
;
5779 /* Check if default mask is allowed. */
5780 if (t
->opcode_modifier
.nodefmask
5781 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5783 i
.error
= no_default_mask
;
5787 /* For VSIB byte, we need a vector register for index, and all vector
5788 registers must be distinct. */
5789 if (t
->opcode_modifier
.vecsib
)
5792 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5793 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5794 || (t
->opcode_modifier
.vecsib
== VecSIB256
5795 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5796 || (t
->opcode_modifier
.vecsib
== VecSIB512
5797 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5799 i
.error
= invalid_vsib_address
;
5803 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5804 if (i
.reg_operands
== 2 && !i
.mask
)
5806 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5807 gas_assert (i
.types
[0].bitfield
.xmmword
5808 || i
.types
[0].bitfield
.ymmword
);
5809 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5810 gas_assert (i
.types
[2].bitfield
.xmmword
5811 || i
.types
[2].bitfield
.ymmword
);
5812 if (operand_check
== check_none
)
5814 if (register_number (i
.op
[0].regs
)
5815 != register_number (i
.index_reg
)
5816 && register_number (i
.op
[2].regs
)
5817 != register_number (i
.index_reg
)
5818 && register_number (i
.op
[0].regs
)
5819 != register_number (i
.op
[2].regs
))
5821 if (operand_check
== check_error
)
5823 i
.error
= invalid_vector_register_set
;
5826 as_warn (_("mask, index, and destination registers should be distinct"));
5828 else if (i
.reg_operands
== 1 && i
.mask
)
5830 if (i
.types
[1].bitfield
.class == RegSIMD
5831 && (i
.types
[1].bitfield
.xmmword
5832 || i
.types
[1].bitfield
.ymmword
5833 || i
.types
[1].bitfield
.zmmword
)
5834 && (register_number (i
.op
[1].regs
)
5835 == register_number (i
.index_reg
)))
5837 if (operand_check
== check_error
)
5839 i
.error
= invalid_vector_register_set
;
5842 if (operand_check
!= check_none
)
5843 as_warn (_("index and destination registers should be distinct"));
5848 /* Check if broadcast is supported by the instruction and is applied
5849 to the memory operand. */
5852 i386_operand_type type
, overlap
;
5854 /* Check if specified broadcast is supported in this instruction,
5855 and its broadcast bytes match the memory operand. */
5856 op
= i
.broadcast
->operand
;
5857 if (!t
->opcode_modifier
.broadcast
5858 || !(i
.flags
[op
] & Operand_Mem
)
5859 || (!i
.types
[op
].bitfield
.unspecified
5860 && !match_broadcast_size (t
, op
)))
5863 i
.error
= unsupported_broadcast
;
5867 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5868 * i
.broadcast
->type
);
5869 operand_type_set (&type
, 0);
5870 switch (i
.broadcast
->bytes
)
5873 type
.bitfield
.word
= 1;
5876 type
.bitfield
.dword
= 1;
5879 type
.bitfield
.qword
= 1;
5882 type
.bitfield
.xmmword
= 1;
5885 type
.bitfield
.ymmword
= 1;
5888 type
.bitfield
.zmmword
= 1;
5894 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5895 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5896 && t
->operand_types
[op
].bitfield
.byte
5897 + t
->operand_types
[op
].bitfield
.word
5898 + t
->operand_types
[op
].bitfield
.dword
5899 + t
->operand_types
[op
].bitfield
.qword
> 1)
5901 overlap
.bitfield
.xmmword
= 0;
5902 overlap
.bitfield
.ymmword
= 0;
5903 overlap
.bitfield
.zmmword
= 0;
5905 if (operand_type_all_zero (&overlap
))
5908 if (t
->opcode_modifier
.checkregsize
)
5912 type
.bitfield
.baseindex
= 1;
5913 for (j
= 0; j
< i
.operands
; ++j
)
5916 && !operand_type_register_match(i
.types
[j
],
5917 t
->operand_types
[j
],
5919 t
->operand_types
[op
]))
5924 /* If broadcast is supported in this instruction, we need to check if
5925 operand of one-element size isn't specified without broadcast. */
5926 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5928 /* Find memory operand. */
5929 for (op
= 0; op
< i
.operands
; op
++)
5930 if (i
.flags
[op
] & Operand_Mem
)
5932 gas_assert (op
< i
.operands
);
5933 /* Check size of the memory operand. */
5934 if (match_broadcast_size (t
, op
))
5936 i
.error
= broadcast_needed
;
5941 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5943 /* Check if requested masking is supported. */
5946 switch (t
->opcode_modifier
.masking
)
5950 case MERGING_MASKING
:
5951 if (i
.mask
->zeroing
)
5954 i
.error
= unsupported_masking
;
5958 case DYNAMIC_MASKING
:
5959 /* Memory destinations allow only merging masking. */
5960 if (i
.mask
->zeroing
&& i
.mem_operands
)
5962 /* Find memory operand. */
5963 for (op
= 0; op
< i
.operands
; op
++)
5964 if (i
.flags
[op
] & Operand_Mem
)
5966 gas_assert (op
< i
.operands
);
5967 if (op
== i
.operands
- 1)
5969 i
.error
= unsupported_masking
;
5979 /* Check if masking is applied to dest operand. */
5980 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5982 i
.error
= mask_not_on_destination
;
5989 if (!t
->opcode_modifier
.sae
5990 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5992 i
.error
= unsupported_rc_sae
;
5995 /* If the instruction has several immediate operands and one of
5996 them is rounding, the rounding operand should be the last
5997 immediate operand. */
5998 if (i
.imm_operands
> 1
5999 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6001 i
.error
= rc_sae_operand_not_last_imm
;
6006 /* Check the special Imm4 cases; must be the first operand. */
6007 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6009 if (i
.op
[0].imms
->X_op
!= O_constant
6010 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6016 /* Turn off Imm<N> so that update_imm won't complain. */
6017 operand_type_set (&i
.types
[0], 0);
6020 /* Check vector Disp8 operand. */
6021 if (t
->opcode_modifier
.disp8memshift
6022 && i
.disp_encoding
!= disp_encoding_32bit
)
6025 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6026 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6027 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6030 const i386_operand_type
*type
= NULL
;
6033 for (op
= 0; op
< i
.operands
; op
++)
6034 if (i
.flags
[op
] & Operand_Mem
)
6036 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6037 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6038 else if (t
->operand_types
[op
].bitfield
.xmmword
6039 + t
->operand_types
[op
].bitfield
.ymmword
6040 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6041 type
= &t
->operand_types
[op
];
6042 else if (!i
.types
[op
].bitfield
.unspecified
)
6043 type
= &i
.types
[op
];
6045 else if (i
.types
[op
].bitfield
.class == RegSIMD
6046 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6048 if (i
.types
[op
].bitfield
.zmmword
)
6050 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6052 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6058 if (type
->bitfield
.zmmword
)
6060 else if (type
->bitfield
.ymmword
)
6062 else if (type
->bitfield
.xmmword
)
6066 /* For the check in fits_in_disp8(). */
6067 if (i
.memshift
== 0)
6071 for (op
= 0; op
< i
.operands
; op
++)
6072 if (operand_type_check (i
.types
[op
], disp
)
6073 && i
.op
[op
].disps
->X_op
== O_constant
)
6075 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6077 i
.types
[op
].bitfield
.disp8
= 1;
6080 i
.types
[op
].bitfield
.disp8
= 0;
6089 /* Check if encoding requirements are met by the instruction. */
6092 VEX_check_encoding (const insn_template
*t
)
6094 if (i
.vec_encoding
== vex_encoding_error
)
6096 i
.error
= unsupported
;
6100 if (i
.vec_encoding
== vex_encoding_evex
)
6102 /* This instruction must be encoded with EVEX prefix. */
6103 if (!is_evex_encoding (t
))
6105 i
.error
= unsupported
;
6111 if (!t
->opcode_modifier
.vex
)
6113 /* This instruction template doesn't have VEX prefix. */
6114 if (i
.vec_encoding
!= vex_encoding_default
)
6116 i
.error
= unsupported
;
6125 static const insn_template
*
6126 match_template (char mnem_suffix
)
6128 /* Points to template once we've found it. */
6129 const insn_template
*t
;
6130 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6131 i386_operand_type overlap4
;
6132 unsigned int found_reverse_match
;
6133 i386_opcode_modifier suffix_check
;
6134 i386_operand_type operand_types
[MAX_OPERANDS
];
6135 int addr_prefix_disp
;
6136 unsigned int j
, size_match
, check_register
;
6137 enum i386_error specific_error
= 0;
6139 #if MAX_OPERANDS != 5
6140 # error "MAX_OPERANDS must be 5."
6143 found_reverse_match
= 0;
6144 addr_prefix_disp
= -1;
6146 /* Prepare for mnemonic suffix check. */
6147 memset (&suffix_check
, 0, sizeof (suffix_check
));
6148 switch (mnem_suffix
)
6150 case BYTE_MNEM_SUFFIX
:
6151 suffix_check
.no_bsuf
= 1;
6153 case WORD_MNEM_SUFFIX
:
6154 suffix_check
.no_wsuf
= 1;
6156 case SHORT_MNEM_SUFFIX
:
6157 suffix_check
.no_ssuf
= 1;
6159 case LONG_MNEM_SUFFIX
:
6160 suffix_check
.no_lsuf
= 1;
6162 case QWORD_MNEM_SUFFIX
:
6163 suffix_check
.no_qsuf
= 1;
6166 /* NB: In Intel syntax, normally we can check for memory operand
6167 size when there is no mnemonic suffix. But jmp and call have
6168 2 different encodings with Dword memory operand size, one with
6169 No_ldSuf and the other without. i.suffix is set to
6170 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6171 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6172 suffix_check
.no_ldsuf
= 1;
6175 /* Must have right number of operands. */
6176 i
.error
= number_of_operands_mismatch
;
6178 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6180 addr_prefix_disp
= -1;
6181 found_reverse_match
= 0;
6183 if (i
.operands
!= t
->operands
)
6186 /* Check processor support. */
6187 i
.error
= unsupported
;
6188 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6191 /* Check AT&T mnemonic. */
6192 i
.error
= unsupported_with_intel_mnemonic
;
6193 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6196 /* Check AT&T/Intel syntax. */
6197 i
.error
= unsupported_syntax
;
6198 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6199 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6202 /* Check Intel64/AMD64 ISA. */
6206 /* Default: Don't accept Intel64. */
6207 if (t
->opcode_modifier
.isa64
== INTEL64
)
6211 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6212 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6216 /* -mintel64: Don't accept AMD64. */
6217 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6222 /* Check the suffix. */
6223 i
.error
= invalid_instruction_suffix
;
6224 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6225 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6226 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6227 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6228 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6229 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6232 size_match
= operand_size_match (t
);
6236 /* This is intentionally not
6238 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6240 as the case of a missing * on the operand is accepted (perhaps with
6241 a warning, issued further down). */
6242 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6244 i
.error
= operand_type_mismatch
;
6248 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6249 operand_types
[j
] = t
->operand_types
[j
];
6251 /* In general, don't allow
6252 - 64-bit operands outside of 64-bit mode,
6253 - 32-bit operands on pre-386. */
6254 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6255 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6256 && flag_code
!= CODE_64BIT
6257 && (t
->base_opcode
!= 0x0fc7
6258 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6259 || (i
.suffix
== LONG_MNEM_SUFFIX
6260 && !cpu_arch_flags
.bitfield
.cpui386
))
6262 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6263 && !intel_float_operand (t
->name
))
6264 : intel_float_operand (t
->name
) != 2)
6265 && (t
->operands
== i
.imm_operands
6266 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6267 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6268 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6269 || (operand_types
[j
].bitfield
.class != RegMMX
6270 && operand_types
[j
].bitfield
.class != RegSIMD
6271 && operand_types
[j
].bitfield
.class != RegMask
))
6272 && !t
->opcode_modifier
.vecsib
)
6275 /* Do not verify operands when there are none. */
6278 if (VEX_check_encoding (t
))
6280 specific_error
= i
.error
;
6284 /* We've found a match; break out of loop. */
6288 if (!t
->opcode_modifier
.jump
6289 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6291 /* There should be only one Disp operand. */
6292 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6293 if (operand_type_check (operand_types
[j
], disp
))
6295 if (j
< MAX_OPERANDS
)
6297 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6299 addr_prefix_disp
= j
;
6301 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6302 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6306 override
= !override
;
6309 if (operand_types
[j
].bitfield
.disp32
6310 && operand_types
[j
].bitfield
.disp16
)
6312 operand_types
[j
].bitfield
.disp16
= override
;
6313 operand_types
[j
].bitfield
.disp32
= !override
;
6315 operand_types
[j
].bitfield
.disp32s
= 0;
6316 operand_types
[j
].bitfield
.disp64
= 0;
6320 if (operand_types
[j
].bitfield
.disp32s
6321 || operand_types
[j
].bitfield
.disp64
)
6323 operand_types
[j
].bitfield
.disp64
&= !override
;
6324 operand_types
[j
].bitfield
.disp32s
&= !override
;
6325 operand_types
[j
].bitfield
.disp32
= override
;
6327 operand_types
[j
].bitfield
.disp16
= 0;
6333 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6334 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6337 /* We check register size if needed. */
6338 if (t
->opcode_modifier
.checkregsize
)
6340 check_register
= (1 << t
->operands
) - 1;
6342 check_register
&= ~(1 << i
.broadcast
->operand
);
6347 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6348 switch (t
->operands
)
6351 if (!operand_type_match (overlap0
, i
.types
[0]))
6355 /* xchg %eax, %eax is a special case. It is an alias for nop
6356 only in 32bit mode and we can use opcode 0x90. In 64bit
6357 mode, we can't use 0x90 for xchg %eax, %eax since it should
6358 zero-extend %eax to %rax. */
6359 if (flag_code
== CODE_64BIT
6360 && t
->base_opcode
== 0x90
6361 && i
.types
[0].bitfield
.instance
== Accum
6362 && i
.types
[0].bitfield
.dword
6363 && i
.types
[1].bitfield
.instance
== Accum
6364 && i
.types
[1].bitfield
.dword
)
6366 /* xrelease mov %eax, <disp> is another special case. It must not
6367 match the accumulator-only encoding of mov. */
6368 if (flag_code
!= CODE_64BIT
6370 && t
->base_opcode
== 0xa0
6371 && i
.types
[0].bitfield
.instance
== Accum
6372 && (i
.flags
[1] & Operand_Mem
))
6377 if (!(size_match
& MATCH_STRAIGHT
))
6379 /* Reverse direction of operands if swapping is possible in the first
6380 place (operands need to be symmetric) and
6381 - the load form is requested, and the template is a store form,
6382 - the store form is requested, and the template is a load form,
6383 - the non-default (swapped) form is requested. */
6384 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6385 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6386 && !operand_type_all_zero (&overlap1
))
6387 switch (i
.dir_encoding
)
6389 case dir_encoding_load
:
6390 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6391 || t
->opcode_modifier
.regmem
)
6395 case dir_encoding_store
:
6396 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6397 && !t
->opcode_modifier
.regmem
)
6401 case dir_encoding_swap
:
6404 case dir_encoding_default
:
6407 /* If we want store form, we skip the current load. */
6408 if ((i
.dir_encoding
== dir_encoding_store
6409 || i
.dir_encoding
== dir_encoding_swap
)
6410 && i
.mem_operands
== 0
6411 && t
->opcode_modifier
.load
)
6416 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6417 if (!operand_type_match (overlap0
, i
.types
[0])
6418 || !operand_type_match (overlap1
, i
.types
[1])
6419 || ((check_register
& 3) == 3
6420 && !operand_type_register_match (i
.types
[0],
6425 /* Check if other direction is valid ... */
6426 if (!t
->opcode_modifier
.d
)
6430 if (!(size_match
& MATCH_REVERSE
))
6432 /* Try reversing direction of operands. */
6433 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6434 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6435 if (!operand_type_match (overlap0
, i
.types
[0])
6436 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6438 && !operand_type_register_match (i
.types
[0],
6439 operand_types
[i
.operands
- 1],
6440 i
.types
[i
.operands
- 1],
6443 /* Does not match either direction. */
6446 /* found_reverse_match holds which of D or FloatR
6448 if (!t
->opcode_modifier
.d
)
6449 found_reverse_match
= 0;
6450 else if (operand_types
[0].bitfield
.tbyte
)
6451 found_reverse_match
= Opcode_FloatD
;
6452 else if (operand_types
[0].bitfield
.xmmword
6453 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6454 || operand_types
[0].bitfield
.class == RegMMX
6455 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6456 || is_any_vex_encoding(t
))
6457 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6458 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6460 found_reverse_match
= Opcode_D
;
6461 if (t
->opcode_modifier
.floatr
)
6462 found_reverse_match
|= Opcode_FloatR
;
6466 /* Found a forward 2 operand match here. */
6467 switch (t
->operands
)
6470 overlap4
= operand_type_and (i
.types
[4],
6474 overlap3
= operand_type_and (i
.types
[3],
6478 overlap2
= operand_type_and (i
.types
[2],
6483 switch (t
->operands
)
6486 if (!operand_type_match (overlap4
, i
.types
[4])
6487 || !operand_type_register_match (i
.types
[3],
6494 if (!operand_type_match (overlap3
, i
.types
[3])
6495 || ((check_register
& 0xa) == 0xa
6496 && !operand_type_register_match (i
.types
[1],
6500 || ((check_register
& 0xc) == 0xc
6501 && !operand_type_register_match (i
.types
[2],
6508 /* Here we make use of the fact that there are no
6509 reverse match 3 operand instructions. */
6510 if (!operand_type_match (overlap2
, i
.types
[2])
6511 || ((check_register
& 5) == 5
6512 && !operand_type_register_match (i
.types
[0],
6516 || ((check_register
& 6) == 6
6517 && !operand_type_register_match (i
.types
[1],
6525 /* Found either forward/reverse 2, 3 or 4 operand match here:
6526 slip through to break. */
6529 /* Check if vector operands are valid. */
6530 if (check_VecOperands (t
))
6532 specific_error
= i
.error
;
6536 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6537 if (VEX_check_encoding (t
))
6539 specific_error
= i
.error
;
6543 /* We've found a match; break out of loop. */
6547 if (t
== current_templates
->end
)
6549 /* We found no match. */
6550 const char *err_msg
;
6551 switch (specific_error
? specific_error
: i
.error
)
6555 case operand_size_mismatch
:
6556 err_msg
= _("operand size mismatch");
6558 case operand_type_mismatch
:
6559 err_msg
= _("operand type mismatch");
6561 case register_type_mismatch
:
6562 err_msg
= _("register type mismatch");
6564 case number_of_operands_mismatch
:
6565 err_msg
= _("number of operands mismatch");
6567 case invalid_instruction_suffix
:
6568 err_msg
= _("invalid instruction suffix");
6571 err_msg
= _("constant doesn't fit in 4 bits");
6573 case unsupported_with_intel_mnemonic
:
6574 err_msg
= _("unsupported with Intel mnemonic");
6576 case unsupported_syntax
:
6577 err_msg
= _("unsupported syntax");
6580 as_bad (_("unsupported instruction `%s'"),
6581 current_templates
->start
->name
);
6583 case invalid_vsib_address
:
6584 err_msg
= _("invalid VSIB address");
6586 case invalid_vector_register_set
:
6587 err_msg
= _("mask, index, and destination registers must be distinct");
6589 case unsupported_vector_index_register
:
6590 err_msg
= _("unsupported vector index register");
6592 case unsupported_broadcast
:
6593 err_msg
= _("unsupported broadcast");
6595 case broadcast_needed
:
6596 err_msg
= _("broadcast is needed for operand of such type");
6598 case unsupported_masking
:
6599 err_msg
= _("unsupported masking");
6601 case mask_not_on_destination
:
6602 err_msg
= _("mask not on destination operand");
6604 case no_default_mask
:
6605 err_msg
= _("default mask isn't allowed");
6607 case unsupported_rc_sae
:
6608 err_msg
= _("unsupported static rounding/sae");
6610 case rc_sae_operand_not_last_imm
:
6612 err_msg
= _("RC/SAE operand must precede immediate operands");
6614 err_msg
= _("RC/SAE operand must follow immediate operands");
6616 case invalid_register_operand
:
6617 err_msg
= _("invalid register operand");
6620 as_bad (_("%s for `%s'"), err_msg
,
6621 current_templates
->start
->name
);
6625 if (!quiet_warnings
)
6628 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6629 as_warn (_("indirect %s without `*'"), t
->name
);
6631 if (t
->opcode_modifier
.isprefix
6632 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6634 /* Warn them that a data or address size prefix doesn't
6635 affect assembly of the next line of code. */
6636 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6640 /* Copy the template we found. */
6643 if (addr_prefix_disp
!= -1)
6644 i
.tm
.operand_types
[addr_prefix_disp
]
6645 = operand_types
[addr_prefix_disp
];
6647 if (found_reverse_match
)
6649 /* If we found a reverse match we must alter the opcode direction
6650 bit and clear/flip the regmem modifier one. found_reverse_match
6651 holds bits to change (different for int & float insns). */
6653 i
.tm
.base_opcode
^= found_reverse_match
;
6655 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6656 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6658 /* Certain SIMD insns have their load forms specified in the opcode
6659 table, and hence we need to _set_ RegMem instead of clearing it.
6660 We need to avoid setting the bit though on insns like KMOVW. */
6661 i
.tm
.opcode_modifier
.regmem
6662 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6663 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6664 && !i
.tm
.opcode_modifier
.regmem
;
6673 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6674 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6676 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6678 as_bad (_("`%s' operand %u must use `%ses' segment"),
6680 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6685 /* There's only ever one segment override allowed per instruction.
6686 This instruction possibly has a legal segment override on the
6687 second operand, so copy the segment to where non-string
6688 instructions store it, allowing common code. */
6689 i
.seg
[op
] = i
.seg
[1];
6695 process_suffix (void)
6697 /* If matched instruction specifies an explicit instruction mnemonic
6699 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6700 i
.suffix
= WORD_MNEM_SUFFIX
;
6701 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6702 i
.suffix
= LONG_MNEM_SUFFIX
;
6703 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6704 i
.suffix
= QWORD_MNEM_SUFFIX
;
6705 else if (i
.reg_operands
6706 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6707 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6709 unsigned int numop
= i
.operands
;
6711 /* movsx/movzx want only their source operand considered here, for the
6712 ambiguity checking below. The suffix will be replaced afterwards
6713 to represent the destination (register). */
6714 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6715 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6718 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6719 if (i
.tm
.base_opcode
== 0xf20f38f0
6720 && i
.tm
.operand_types
[1].bitfield
.qword
)
6723 /* If there's no instruction mnemonic suffix we try to invent one
6724 based on GPR operands. */
6727 /* We take i.suffix from the last register operand specified,
6728 Destination register type is more significant than source
6729 register type. crc32 in SSE4.2 prefers source register
6731 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6734 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6735 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6737 if (i
.types
[op
].bitfield
.class != Reg
)
6739 if (i
.types
[op
].bitfield
.byte
)
6740 i
.suffix
= BYTE_MNEM_SUFFIX
;
6741 else if (i
.types
[op
].bitfield
.word
)
6742 i
.suffix
= WORD_MNEM_SUFFIX
;
6743 else if (i
.types
[op
].bitfield
.dword
)
6744 i
.suffix
= LONG_MNEM_SUFFIX
;
6745 else if (i
.types
[op
].bitfield
.qword
)
6746 i
.suffix
= QWORD_MNEM_SUFFIX
;
6752 /* As an exception, movsx/movzx silently default to a byte source
6754 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6755 && !i
.suffix
&& !intel_syntax
)
6756 i
.suffix
= BYTE_MNEM_SUFFIX
;
6758 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6761 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6762 && i
.tm
.opcode_modifier
.no_bsuf
)
6764 else if (!check_byte_reg ())
6767 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6770 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6771 && i
.tm
.opcode_modifier
.no_lsuf
6772 && !i
.tm
.opcode_modifier
.todword
6773 && !i
.tm
.opcode_modifier
.toqword
)
6775 else if (!check_long_reg ())
6778 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6781 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6782 && i
.tm
.opcode_modifier
.no_qsuf
6783 && !i
.tm
.opcode_modifier
.todword
6784 && !i
.tm
.opcode_modifier
.toqword
)
6786 else if (!check_qword_reg ())
6789 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6792 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6793 && i
.tm
.opcode_modifier
.no_wsuf
)
6795 else if (!check_word_reg ())
6798 else if (intel_syntax
6799 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6800 /* Do nothing if the instruction is going to ignore the prefix. */
6805 /* Undo the movsx/movzx change done above. */
6808 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6811 i
.suffix
= stackop_size
;
6812 if (stackop_size
== LONG_MNEM_SUFFIX
)
6814 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6815 .code16gcc directive to support 16-bit mode with
6816 32-bit address. For IRET without a suffix, generate
6817 16-bit IRET (opcode 0xcf) to return from an interrupt
6819 if (i
.tm
.base_opcode
== 0xcf)
6821 i
.suffix
= WORD_MNEM_SUFFIX
;
6822 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6824 /* Warn about changed behavior for segment register push/pop. */
6825 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6826 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6831 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6832 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6833 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6834 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6835 && i
.tm
.extension_opcode
<= 3)))
6840 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6842 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6843 || i
.tm
.opcode_modifier
.no_lsuf
)
6844 i
.suffix
= QWORD_MNEM_SUFFIX
;
6849 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6850 i
.suffix
= LONG_MNEM_SUFFIX
;
6853 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6854 i
.suffix
= WORD_MNEM_SUFFIX
;
6860 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6861 /* Also cover lret/retf/iret in 64-bit mode. */
6862 || (flag_code
== CODE_64BIT
6863 && !i
.tm
.opcode_modifier
.no_lsuf
6864 && !i
.tm
.opcode_modifier
.no_qsuf
))
6865 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6866 /* Accept FLDENV et al without suffix. */
6867 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6869 unsigned int suffixes
, evex
= 0;
6871 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6872 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6874 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6876 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6878 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6880 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6883 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6884 also suitable for AT&T syntax mode, it was requested that this be
6885 restricted to just Intel syntax. */
6886 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6890 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6892 if (is_evex_encoding (&i
.tm
)
6893 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6895 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6896 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6897 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6898 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6899 if (!i
.tm
.opcode_modifier
.evex
6900 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6901 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6904 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6905 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6906 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6909 /* Any properly sized operand disambiguates the insn. */
6910 if (i
.types
[op
].bitfield
.xmmword
6911 || i
.types
[op
].bitfield
.ymmword
6912 || i
.types
[op
].bitfield
.zmmword
)
6914 suffixes
&= ~(7 << 6);
6919 if ((i
.flags
[op
] & Operand_Mem
)
6920 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6922 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6924 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6926 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6928 if (is_evex_encoding (&i
.tm
))
6934 /* Are multiple suffixes / operand sizes allowed? */
6935 if (suffixes
& (suffixes
- 1))
6938 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6939 || operand_check
== check_error
))
6941 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6944 if (operand_check
== check_error
)
6946 as_bad (_("no instruction mnemonic suffix given and "
6947 "no register operands; can't size `%s'"), i
.tm
.name
);
6950 if (operand_check
== check_warning
)
6951 as_warn (_("%s; using default for `%s'"),
6953 ? _("ambiguous operand size")
6954 : _("no instruction mnemonic suffix given and "
6955 "no register operands"),
6958 if (i
.tm
.opcode_modifier
.floatmf
)
6959 i
.suffix
= SHORT_MNEM_SUFFIX
;
6960 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6961 || (i
.tm
.base_opcode
== 0x63
6962 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6963 /* handled below */;
6965 i
.tm
.opcode_modifier
.evex
= evex
;
6966 else if (flag_code
== CODE_16BIT
)
6967 i
.suffix
= WORD_MNEM_SUFFIX
;
6968 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6969 i
.suffix
= LONG_MNEM_SUFFIX
;
6971 i
.suffix
= QWORD_MNEM_SUFFIX
;
6975 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6976 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6978 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6979 In AT&T syntax, if there is no suffix (warned about above), the default
6980 will be byte extension. */
6981 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6982 i
.tm
.base_opcode
|= 1;
6984 /* For further processing, the suffix should represent the destination
6985 (register). This is already the case when one was used with
6986 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6987 no suffix to begin with. */
6988 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6990 if (i
.types
[1].bitfield
.word
)
6991 i
.suffix
= WORD_MNEM_SUFFIX
;
6992 else if (i
.types
[1].bitfield
.qword
)
6993 i
.suffix
= QWORD_MNEM_SUFFIX
;
6995 i
.suffix
= LONG_MNEM_SUFFIX
;
6997 i
.tm
.opcode_modifier
.w
= 0;
7001 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7002 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7003 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7005 /* Change the opcode based on the operand size given by i.suffix. */
7008 /* Size floating point instruction. */
7009 case LONG_MNEM_SUFFIX
:
7010 if (i
.tm
.opcode_modifier
.floatmf
)
7012 i
.tm
.base_opcode
^= 4;
7016 case WORD_MNEM_SUFFIX
:
7017 case QWORD_MNEM_SUFFIX
:
7018 /* It's not a byte, select word/dword operation. */
7019 if (i
.tm
.opcode_modifier
.w
)
7022 i
.tm
.base_opcode
|= 8;
7024 i
.tm
.base_opcode
|= 1;
7027 case SHORT_MNEM_SUFFIX
:
7028 /* Now select between word & dword operations via the operand
7029 size prefix, except for instructions that will ignore this
7031 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7032 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7033 && !i
.tm
.opcode_modifier
.floatmf
7034 && !is_any_vex_encoding (&i
.tm
)
7035 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7036 || (flag_code
== CODE_64BIT
7037 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7039 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7041 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7042 prefix
= ADDR_PREFIX_OPCODE
;
7044 if (!add_prefix (prefix
))
7048 /* Set mode64 for an operand. */
7049 if (i
.suffix
== QWORD_MNEM_SUFFIX
7050 && flag_code
== CODE_64BIT
7051 && !i
.tm
.opcode_modifier
.norex64
7052 && !i
.tm
.opcode_modifier
.vexw
7053 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7055 && ! (i
.operands
== 2
7056 && i
.tm
.base_opcode
== 0x90
7057 && i
.tm
.extension_opcode
== None
7058 && i
.types
[0].bitfield
.instance
== Accum
7059 && i
.types
[0].bitfield
.qword
7060 && i
.types
[1].bitfield
.instance
== Accum
7061 && i
.types
[1].bitfield
.qword
))
7067 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7069 gas_assert (!i
.suffix
);
7070 gas_assert (i
.reg_operands
);
7072 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7075 /* The address size override prefix changes the size of the
7077 if (flag_code
== CODE_64BIT
7078 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7080 as_bad (_("16-bit addressing unavailable for `%s'"),
7085 if ((flag_code
== CODE_32BIT
7086 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7087 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7088 && !add_prefix (ADDR_PREFIX_OPCODE
))
7093 /* Check invalid register operand when the address size override
7094 prefix changes the size of register operands. */
7096 enum { need_word
, need_dword
, need_qword
} need
;
7098 if (flag_code
== CODE_32BIT
)
7099 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7100 else if (i
.prefix
[ADDR_PREFIX
])
7103 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7105 for (op
= 0; op
< i
.operands
; op
++)
7107 if (i
.types
[op
].bitfield
.class != Reg
)
7113 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7117 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7121 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7126 as_bad (_("invalid register operand size for `%s'"),
7137 check_byte_reg (void)
7141 for (op
= i
.operands
; --op
>= 0;)
7143 /* Skip non-register operands. */
7144 if (i
.types
[op
].bitfield
.class != Reg
)
7147 /* If this is an eight bit register, it's OK. If it's the 16 or
7148 32 bit version of an eight bit register, we will just use the
7149 low portion, and that's OK too. */
7150 if (i
.types
[op
].bitfield
.byte
)
7153 /* I/O port address operands are OK too. */
7154 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7155 && i
.tm
.operand_types
[op
].bitfield
.word
)
7158 /* crc32 only wants its source operand checked here. */
7159 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7162 /* Any other register is bad. */
7163 as_bad (_("`%s%s' not allowed with `%s%c'"),
7164 register_prefix
, i
.op
[op
].regs
->reg_name
,
7165 i
.tm
.name
, i
.suffix
);
7172 check_long_reg (void)
7176 for (op
= i
.operands
; --op
>= 0;)
7177 /* Skip non-register operands. */
7178 if (i
.types
[op
].bitfield
.class != Reg
)
7180 /* Reject eight bit registers, except where the template requires
7181 them. (eg. movzb) */
7182 else if (i
.types
[op
].bitfield
.byte
7183 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7184 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7185 && (i
.tm
.operand_types
[op
].bitfield
.word
7186 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7188 as_bad (_("`%s%s' not allowed with `%s%c'"),
7190 i
.op
[op
].regs
->reg_name
,
7195 /* Error if the e prefix on a general reg is missing. */
7196 else if (i
.types
[op
].bitfield
.word
7197 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7198 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7199 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7201 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7202 register_prefix
, i
.op
[op
].regs
->reg_name
,
7206 /* Warn if the r prefix on a general reg is present. */
7207 else if (i
.types
[op
].bitfield
.qword
7208 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7209 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7210 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7213 && i
.tm
.opcode_modifier
.toqword
7214 && i
.types
[0].bitfield
.class != RegSIMD
)
7216 /* Convert to QWORD. We want REX byte. */
7217 i
.suffix
= QWORD_MNEM_SUFFIX
;
7221 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7222 register_prefix
, i
.op
[op
].regs
->reg_name
,
7231 check_qword_reg (void)
7235 for (op
= i
.operands
; --op
>= 0; )
7236 /* Skip non-register operands. */
7237 if (i
.types
[op
].bitfield
.class != Reg
)
7239 /* Reject eight bit registers, except where the template requires
7240 them. (eg. movzb) */
7241 else if (i
.types
[op
].bitfield
.byte
7242 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7243 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7244 && (i
.tm
.operand_types
[op
].bitfield
.word
7245 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7247 as_bad (_("`%s%s' not allowed with `%s%c'"),
7249 i
.op
[op
].regs
->reg_name
,
7254 /* Warn if the r prefix on a general reg is missing. */
7255 else if ((i
.types
[op
].bitfield
.word
7256 || i
.types
[op
].bitfield
.dword
)
7257 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7258 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7259 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7261 /* Prohibit these changes in the 64bit mode, since the
7262 lowering is more complicated. */
7264 && i
.tm
.opcode_modifier
.todword
7265 && i
.types
[0].bitfield
.class != RegSIMD
)
7267 /* Convert to DWORD. We don't want REX byte. */
7268 i
.suffix
= LONG_MNEM_SUFFIX
;
7272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7273 register_prefix
, i
.op
[op
].regs
->reg_name
,
7282 check_word_reg (void)
7285 for (op
= i
.operands
; --op
>= 0;)
7286 /* Skip non-register operands. */
7287 if (i
.types
[op
].bitfield
.class != Reg
)
7289 /* Reject eight bit registers, except where the template requires
7290 them. (eg. movzb) */
7291 else if (i
.types
[op
].bitfield
.byte
7292 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7293 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7294 && (i
.tm
.operand_types
[op
].bitfield
.word
7295 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7297 as_bad (_("`%s%s' not allowed with `%s%c'"),
7299 i
.op
[op
].regs
->reg_name
,
7304 /* Error if the e or r prefix on a general reg is present. */
7305 else if ((i
.types
[op
].bitfield
.dword
7306 || i
.types
[op
].bitfield
.qword
)
7307 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7308 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7309 && i
.tm
.operand_types
[op
].bitfield
.word
)
7311 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7312 register_prefix
, i
.op
[op
].regs
->reg_name
,
7320 update_imm (unsigned int j
)
7322 i386_operand_type overlap
= i
.types
[j
];
7323 if ((overlap
.bitfield
.imm8
7324 || overlap
.bitfield
.imm8s
7325 || overlap
.bitfield
.imm16
7326 || overlap
.bitfield
.imm32
7327 || overlap
.bitfield
.imm32s
7328 || overlap
.bitfield
.imm64
)
7329 && !operand_type_equal (&overlap
, &imm8
)
7330 && !operand_type_equal (&overlap
, &imm8s
)
7331 && !operand_type_equal (&overlap
, &imm16
)
7332 && !operand_type_equal (&overlap
, &imm32
)
7333 && !operand_type_equal (&overlap
, &imm32s
)
7334 && !operand_type_equal (&overlap
, &imm64
))
7338 i386_operand_type temp
;
7340 operand_type_set (&temp
, 0);
7341 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7343 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7344 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7346 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7347 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7348 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7350 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7351 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7354 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7357 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7358 || operand_type_equal (&overlap
, &imm16_32
)
7359 || operand_type_equal (&overlap
, &imm16_32s
))
7361 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7366 if (!operand_type_equal (&overlap
, &imm8
)
7367 && !operand_type_equal (&overlap
, &imm8s
)
7368 && !operand_type_equal (&overlap
, &imm16
)
7369 && !operand_type_equal (&overlap
, &imm32
)
7370 && !operand_type_equal (&overlap
, &imm32s
)
7371 && !operand_type_equal (&overlap
, &imm64
))
7373 as_bad (_("no instruction mnemonic suffix given; "
7374 "can't determine immediate size"));
7378 i
.types
[j
] = overlap
;
7388 /* Update the first 2 immediate operands. */
7389 n
= i
.operands
> 2 ? 2 : i
.operands
;
7392 for (j
= 0; j
< n
; j
++)
7393 if (update_imm (j
) == 0)
7396 /* The 3rd operand can't be immediate operand. */
7397 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7404 process_operands (void)
7406 /* Default segment register this instruction will use for memory
7407 accesses. 0 means unknown. This is only for optimizing out
7408 unnecessary segment overrides. */
7409 const seg_entry
*default_seg
= 0;
7411 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7413 unsigned int dupl
= i
.operands
;
7414 unsigned int dest
= dupl
- 1;
7417 /* The destination must be an xmm register. */
7418 gas_assert (i
.reg_operands
7419 && MAX_OPERANDS
> dupl
7420 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7422 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7423 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7425 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7427 /* Keep xmm0 for instructions with VEX prefix and 3
7429 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7430 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7435 /* We remove the first xmm0 and keep the number of
7436 operands unchanged, which in fact duplicates the
7438 for (j
= 1; j
< i
.operands
; j
++)
7440 i
.op
[j
- 1] = i
.op
[j
];
7441 i
.types
[j
- 1] = i
.types
[j
];
7442 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7443 i
.flags
[j
- 1] = i
.flags
[j
];
7447 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7449 gas_assert ((MAX_OPERANDS
- 1) > dupl
7450 && (i
.tm
.opcode_modifier
.vexsources
7453 /* Add the implicit xmm0 for instructions with VEX prefix
7455 for (j
= i
.operands
; j
> 0; j
--)
7457 i
.op
[j
] = i
.op
[j
- 1];
7458 i
.types
[j
] = i
.types
[j
- 1];
7459 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7460 i
.flags
[j
] = i
.flags
[j
- 1];
7463 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7464 i
.types
[0] = regxmm
;
7465 i
.tm
.operand_types
[0] = regxmm
;
7468 i
.reg_operands
+= 2;
7473 i
.op
[dupl
] = i
.op
[dest
];
7474 i
.types
[dupl
] = i
.types
[dest
];
7475 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7476 i
.flags
[dupl
] = i
.flags
[dest
];
7485 i
.op
[dupl
] = i
.op
[dest
];
7486 i
.types
[dupl
] = i
.types
[dest
];
7487 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7488 i
.flags
[dupl
] = i
.flags
[dest
];
7491 if (i
.tm
.opcode_modifier
.immext
)
7494 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7495 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7499 for (j
= 1; j
< i
.operands
; j
++)
7501 i
.op
[j
- 1] = i
.op
[j
];
7502 i
.types
[j
- 1] = i
.types
[j
];
7504 /* We need to adjust fields in i.tm since they are used by
7505 build_modrm_byte. */
7506 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7508 i
.flags
[j
- 1] = i
.flags
[j
];
7515 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7517 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7519 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7520 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7521 regnum
= register_number (i
.op
[1].regs
);
7522 first_reg_in_group
= regnum
& ~3;
7523 last_reg_in_group
= first_reg_in_group
+ 3;
7524 if (regnum
!= first_reg_in_group
)
7525 as_warn (_("source register `%s%s' implicitly denotes"
7526 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7527 register_prefix
, i
.op
[1].regs
->reg_name
,
7528 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7529 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7532 else if (i
.tm
.opcode_modifier
.regkludge
)
7534 /* The imul $imm, %reg instruction is converted into
7535 imul $imm, %reg, %reg, and the clr %reg instruction
7536 is converted into xor %reg, %reg. */
7538 unsigned int first_reg_op
;
7540 if (operand_type_check (i
.types
[0], reg
))
7544 /* Pretend we saw the extra register operand. */
7545 gas_assert (i
.reg_operands
== 1
7546 && i
.op
[first_reg_op
+ 1].regs
== 0);
7547 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7548 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7553 if (i
.tm
.opcode_modifier
.modrm
)
7555 /* The opcode is completed (modulo i.tm.extension_opcode which
7556 must be put into the modrm byte). Now, we make the modrm and
7557 index base bytes based on all the info we've collected. */
7559 default_seg
= build_modrm_byte ();
7561 else if (i
.types
[0].bitfield
.class == SReg
)
7563 if (flag_code
!= CODE_64BIT
7564 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7565 && i
.op
[0].regs
->reg_num
== 1
7566 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7567 && i
.op
[0].regs
->reg_num
< 4)
7569 as_bad (_("you can't `%s %s%s'"),
7570 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7573 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7575 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7576 i
.tm
.opcode_length
= 2;
7578 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7580 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7584 else if (i
.tm
.opcode_modifier
.isstring
)
7586 /* For the string instructions that allow a segment override
7587 on one of their operands, the default segment is ds. */
7590 else if (i
.short_form
)
7592 /* The register or float register operand is in operand
7594 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7596 /* Register goes in low 3 bits of opcode. */
7597 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7598 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7600 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7602 /* Warn about some common errors, but press on regardless.
7603 The first case can be generated by gcc (<= 2.8.1). */
7604 if (i
.operands
== 2)
7606 /* Reversed arguments on faddp, fsubp, etc. */
7607 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7608 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7609 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7613 /* Extraneous `l' suffix on fp insn. */
7614 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7615 register_prefix
, i
.op
[0].regs
->reg_name
);
7620 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7621 && i
.tm
.base_opcode
== 0x8d /* lea */
7622 && !is_any_vex_encoding(&i
.tm
))
7624 if (!quiet_warnings
)
7625 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7629 i
.prefix
[SEG_PREFIX
] = 0;
7633 /* If a segment was explicitly specified, and the specified segment
7634 is neither the default nor the one already recorded from a prefix,
7635 use an opcode prefix to select it. If we never figured out what
7636 the default segment is, then default_seg will be zero at this
7637 point, and the specified segment prefix will always be used. */
7639 && i
.seg
[0] != default_seg
7640 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7642 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7648 static const seg_entry
*
7649 build_modrm_byte (void)
7651 const seg_entry
*default_seg
= 0;
7652 unsigned int source
, dest
;
7655 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7658 unsigned int nds
, reg_slot
;
7661 dest
= i
.operands
- 1;
7664 /* There are 2 kinds of instructions:
7665 1. 5 operands: 4 register operands or 3 register operands
7666 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7667 VexW0 or VexW1. The destination must be either XMM, YMM or
7669 2. 4 operands: 4 register operands or 3 register operands
7670 plus 1 memory operand, with VexXDS. */
7671 gas_assert ((i
.reg_operands
== 4
7672 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7673 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7674 && i
.tm
.opcode_modifier
.vexw
7675 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7677 /* If VexW1 is set, the first non-immediate operand is the source and
7678 the second non-immediate one is encoded in the immediate operand. */
7679 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7681 source
= i
.imm_operands
;
7682 reg_slot
= i
.imm_operands
+ 1;
7686 source
= i
.imm_operands
+ 1;
7687 reg_slot
= i
.imm_operands
;
7690 if (i
.imm_operands
== 0)
7692 /* When there is no immediate operand, generate an 8bit
7693 immediate operand to encode the first operand. */
7694 exp
= &im_expressions
[i
.imm_operands
++];
7695 i
.op
[i
.operands
].imms
= exp
;
7696 i
.types
[i
.operands
] = imm8
;
7699 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7700 exp
->X_op
= O_constant
;
7701 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7702 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7706 gas_assert (i
.imm_operands
== 1);
7707 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7708 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7710 /* Turn on Imm8 again so that output_imm will generate it. */
7711 i
.types
[0].bitfield
.imm8
= 1;
7713 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7714 i
.op
[0].imms
->X_add_number
7715 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7716 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7719 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7720 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7725 /* i.reg_operands MUST be the number of real register operands;
7726 implicit registers do not count. If there are 3 register
7727 operands, it must be a instruction with VexNDS. For a
7728 instruction with VexNDD, the destination register is encoded
7729 in VEX prefix. If there are 4 register operands, it must be
7730 a instruction with VEX prefix and 3 sources. */
7731 if (i
.mem_operands
== 0
7732 && ((i
.reg_operands
== 2
7733 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7734 || (i
.reg_operands
== 3
7735 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7736 || (i
.reg_operands
== 4 && vex_3_sources
)))
7744 /* When there are 3 operands, one of them may be immediate,
7745 which may be the first or the last operand. Otherwise,
7746 the first operand must be shift count register (cl) or it
7747 is an instruction with VexNDS. */
7748 gas_assert (i
.imm_operands
== 1
7749 || (i
.imm_operands
== 0
7750 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7751 || (i
.types
[0].bitfield
.instance
== RegC
7752 && i
.types
[0].bitfield
.byte
))));
7753 if (operand_type_check (i
.types
[0], imm
)
7754 || (i
.types
[0].bitfield
.instance
== RegC
7755 && i
.types
[0].bitfield
.byte
))
7761 /* When there are 4 operands, the first two must be 8bit
7762 immediate operands. The source operand will be the 3rd
7765 For instructions with VexNDS, if the first operand
7766 an imm8, the source operand is the 2nd one. If the last
7767 operand is imm8, the source operand is the first one. */
7768 gas_assert ((i
.imm_operands
== 2
7769 && i
.types
[0].bitfield
.imm8
7770 && i
.types
[1].bitfield
.imm8
)
7771 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7772 && i
.imm_operands
== 1
7773 && (i
.types
[0].bitfield
.imm8
7774 || i
.types
[i
.operands
- 1].bitfield
.imm8
7776 if (i
.imm_operands
== 2)
7780 if (i
.types
[0].bitfield
.imm8
)
7787 if (is_evex_encoding (&i
.tm
))
7789 /* For EVEX instructions, when there are 5 operands, the
7790 first one must be immediate operand. If the second one
7791 is immediate operand, the source operand is the 3th
7792 one. If the last one is immediate operand, the source
7793 operand is the 2nd one. */
7794 gas_assert (i
.imm_operands
== 2
7795 && i
.tm
.opcode_modifier
.sae
7796 && operand_type_check (i
.types
[0], imm
));
7797 if (operand_type_check (i
.types
[1], imm
))
7799 else if (operand_type_check (i
.types
[4], imm
))
7813 /* RC/SAE operand could be between DEST and SRC. That happens
7814 when one operand is GPR and the other one is XMM/YMM/ZMM
7816 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7819 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7821 /* For instructions with VexNDS, the register-only source
7822 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7823 register. It is encoded in VEX prefix. */
7825 i386_operand_type op
;
7828 /* Check register-only source operand when two source
7829 operands are swapped. */
7830 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7831 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7839 op
= i
.tm
.operand_types
[vvvv
];
7840 if ((dest
+ 1) >= i
.operands
7841 || ((op
.bitfield
.class != Reg
7842 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7843 && op
.bitfield
.class != RegSIMD
7844 && !operand_type_equal (&op
, ®mask
)))
7846 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7852 /* One of the register operands will be encoded in the i.rm.reg
7853 field, the other in the combined i.rm.mode and i.rm.regmem
7854 fields. If no form of this instruction supports a memory
7855 destination operand, then we assume the source operand may
7856 sometimes be a memory operand and so we need to store the
7857 destination in the i.rm.reg field. */
7858 if (!i
.tm
.opcode_modifier
.regmem
7859 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7861 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7862 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7863 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7864 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7865 i
.has_regmmx
= TRUE
;
7866 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7867 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7869 if (i
.types
[dest
].bitfield
.zmmword
7870 || i
.types
[source
].bitfield
.zmmword
)
7871 i
.has_regzmm
= TRUE
;
7872 else if (i
.types
[dest
].bitfield
.ymmword
7873 || i
.types
[source
].bitfield
.ymmword
)
7874 i
.has_regymm
= TRUE
;
7876 i
.has_regxmm
= TRUE
;
7878 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7880 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7882 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7884 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7889 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7890 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7891 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7893 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7895 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7897 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7900 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7902 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7905 add_prefix (LOCK_PREFIX_OPCODE
);
7909 { /* If it's not 2 reg operands... */
7914 unsigned int fake_zero_displacement
= 0;
7917 for (op
= 0; op
< i
.operands
; op
++)
7918 if (i
.flags
[op
] & Operand_Mem
)
7920 gas_assert (op
< i
.operands
);
7922 if (i
.tm
.opcode_modifier
.vecsib
)
7924 if (i
.index_reg
->reg_num
== RegIZ
)
7927 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7930 i
.sib
.base
= NO_BASE_REGISTER
;
7931 i
.sib
.scale
= i
.log2_scale_factor
;
7932 i
.types
[op
].bitfield
.disp8
= 0;
7933 i
.types
[op
].bitfield
.disp16
= 0;
7934 i
.types
[op
].bitfield
.disp64
= 0;
7935 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7937 /* Must be 32 bit */
7938 i
.types
[op
].bitfield
.disp32
= 1;
7939 i
.types
[op
].bitfield
.disp32s
= 0;
7943 i
.types
[op
].bitfield
.disp32
= 0;
7944 i
.types
[op
].bitfield
.disp32s
= 1;
7947 i
.sib
.index
= i
.index_reg
->reg_num
;
7948 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7950 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7956 if (i
.base_reg
== 0)
7959 if (!i
.disp_operands
)
7960 fake_zero_displacement
= 1;
7961 if (i
.index_reg
== 0)
7963 i386_operand_type newdisp
;
7965 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7966 /* Operand is just <disp> */
7967 if (flag_code
== CODE_64BIT
)
7969 /* 64bit mode overwrites the 32bit absolute
7970 addressing by RIP relative addressing and
7971 absolute addressing is encoded by one of the
7972 redundant SIB forms. */
7973 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7974 i
.sib
.base
= NO_BASE_REGISTER
;
7975 i
.sib
.index
= NO_INDEX_REGISTER
;
7976 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7978 else if ((flag_code
== CODE_16BIT
)
7979 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7981 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7986 i
.rm
.regmem
= NO_BASE_REGISTER
;
7989 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7990 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7992 else if (!i
.tm
.opcode_modifier
.vecsib
)
7994 /* !i.base_reg && i.index_reg */
7995 if (i
.index_reg
->reg_num
== RegIZ
)
7996 i
.sib
.index
= NO_INDEX_REGISTER
;
7998 i
.sib
.index
= i
.index_reg
->reg_num
;
7999 i
.sib
.base
= NO_BASE_REGISTER
;
8000 i
.sib
.scale
= i
.log2_scale_factor
;
8001 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8002 i
.types
[op
].bitfield
.disp8
= 0;
8003 i
.types
[op
].bitfield
.disp16
= 0;
8004 i
.types
[op
].bitfield
.disp64
= 0;
8005 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8007 /* Must be 32 bit */
8008 i
.types
[op
].bitfield
.disp32
= 1;
8009 i
.types
[op
].bitfield
.disp32s
= 0;
8013 i
.types
[op
].bitfield
.disp32
= 0;
8014 i
.types
[op
].bitfield
.disp32s
= 1;
8016 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8020 /* RIP addressing for 64bit mode. */
8021 else if (i
.base_reg
->reg_num
== RegIP
)
8023 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8024 i
.rm
.regmem
= NO_BASE_REGISTER
;
8025 i
.types
[op
].bitfield
.disp8
= 0;
8026 i
.types
[op
].bitfield
.disp16
= 0;
8027 i
.types
[op
].bitfield
.disp32
= 0;
8028 i
.types
[op
].bitfield
.disp32s
= 1;
8029 i
.types
[op
].bitfield
.disp64
= 0;
8030 i
.flags
[op
] |= Operand_PCrel
;
8031 if (! i
.disp_operands
)
8032 fake_zero_displacement
= 1;
8034 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8036 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8037 switch (i
.base_reg
->reg_num
)
8040 if (i
.index_reg
== 0)
8042 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8043 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8047 if (i
.index_reg
== 0)
8050 if (operand_type_check (i
.types
[op
], disp
) == 0)
8052 /* fake (%bp) into 0(%bp) */
8053 i
.types
[op
].bitfield
.disp8
= 1;
8054 fake_zero_displacement
= 1;
8057 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8058 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8060 default: /* (%si) -> 4 or (%di) -> 5 */
8061 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8063 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8065 else /* i.base_reg and 32/64 bit mode */
8067 if (flag_code
== CODE_64BIT
8068 && operand_type_check (i
.types
[op
], disp
))
8070 i
.types
[op
].bitfield
.disp16
= 0;
8071 i
.types
[op
].bitfield
.disp64
= 0;
8072 if (i
.prefix
[ADDR_PREFIX
] == 0)
8074 i
.types
[op
].bitfield
.disp32
= 0;
8075 i
.types
[op
].bitfield
.disp32s
= 1;
8079 i
.types
[op
].bitfield
.disp32
= 1;
8080 i
.types
[op
].bitfield
.disp32s
= 0;
8084 if (!i
.tm
.opcode_modifier
.vecsib
)
8085 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8086 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8088 i
.sib
.base
= i
.base_reg
->reg_num
;
8089 /* x86-64 ignores REX prefix bit here to avoid decoder
8091 if (!(i
.base_reg
->reg_flags
& RegRex
)
8092 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8093 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8095 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8097 fake_zero_displacement
= 1;
8098 i
.types
[op
].bitfield
.disp8
= 1;
8100 i
.sib
.scale
= i
.log2_scale_factor
;
8101 if (i
.index_reg
== 0)
8103 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8104 /* <disp>(%esp) becomes two byte modrm with no index
8105 register. We've already stored the code for esp
8106 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8107 Any base register besides %esp will not use the
8108 extra modrm byte. */
8109 i
.sib
.index
= NO_INDEX_REGISTER
;
8111 else if (!i
.tm
.opcode_modifier
.vecsib
)
8113 if (i
.index_reg
->reg_num
== RegIZ
)
8114 i
.sib
.index
= NO_INDEX_REGISTER
;
8116 i
.sib
.index
= i
.index_reg
->reg_num
;
8117 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8118 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8123 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8124 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8128 if (!fake_zero_displacement
8132 fake_zero_displacement
= 1;
8133 if (i
.disp_encoding
== disp_encoding_8bit
)
8134 i
.types
[op
].bitfield
.disp8
= 1;
8136 i
.types
[op
].bitfield
.disp32
= 1;
8138 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8142 if (fake_zero_displacement
)
8144 /* Fakes a zero displacement assuming that i.types[op]
8145 holds the correct displacement size. */
8148 gas_assert (i
.op
[op
].disps
== 0);
8149 exp
= &disp_expressions
[i
.disp_operands
++];
8150 i
.op
[op
].disps
= exp
;
8151 exp
->X_op
= O_constant
;
8152 exp
->X_add_number
= 0;
8153 exp
->X_add_symbol
= (symbolS
*) 0;
8154 exp
->X_op_symbol
= (symbolS
*) 0;
8162 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8164 if (operand_type_check (i
.types
[0], imm
))
8165 i
.vex
.register_specifier
= NULL
;
8168 /* VEX.vvvv encodes one of the sources when the first
8169 operand is not an immediate. */
8170 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8171 i
.vex
.register_specifier
= i
.op
[0].regs
;
8173 i
.vex
.register_specifier
= i
.op
[1].regs
;
8176 /* Destination is a XMM register encoded in the ModRM.reg
8178 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8179 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8182 /* ModRM.rm and VEX.B encodes the other source. */
8183 if (!i
.mem_operands
)
8187 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8188 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8190 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8192 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8196 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8198 i
.vex
.register_specifier
= i
.op
[2].regs
;
8199 if (!i
.mem_operands
)
8202 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8203 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8207 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8208 (if any) based on i.tm.extension_opcode. Again, we must be
8209 careful to make sure that segment/control/debug/test/MMX
8210 registers are coded into the i.rm.reg field. */
8211 else if (i
.reg_operands
)
8214 unsigned int vex_reg
= ~0;
8216 for (op
= 0; op
< i
.operands
; op
++)
8218 if (i
.types
[op
].bitfield
.class == Reg
8219 || i
.types
[op
].bitfield
.class == RegBND
8220 || i
.types
[op
].bitfield
.class == RegMask
8221 || i
.types
[op
].bitfield
.class == SReg
8222 || i
.types
[op
].bitfield
.class == RegCR
8223 || i
.types
[op
].bitfield
.class == RegDR
8224 || i
.types
[op
].bitfield
.class == RegTR
)
8226 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8228 if (i
.types
[op
].bitfield
.zmmword
)
8229 i
.has_regzmm
= TRUE
;
8230 else if (i
.types
[op
].bitfield
.ymmword
)
8231 i
.has_regymm
= TRUE
;
8233 i
.has_regxmm
= TRUE
;
8236 if (i
.types
[op
].bitfield
.class == RegMMX
)
8238 i
.has_regmmx
= TRUE
;
8245 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8247 /* For instructions with VexNDS, the register-only
8248 source operand is encoded in VEX prefix. */
8249 gas_assert (mem
!= (unsigned int) ~0);
8254 gas_assert (op
< i
.operands
);
8258 /* Check register-only source operand when two source
8259 operands are swapped. */
8260 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8261 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8265 gas_assert (mem
== (vex_reg
+ 1)
8266 && op
< i
.operands
);
8271 gas_assert (vex_reg
< i
.operands
);
8275 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8277 /* For instructions with VexNDD, the register destination
8278 is encoded in VEX prefix. */
8279 if (i
.mem_operands
== 0)
8281 /* There is no memory operand. */
8282 gas_assert ((op
+ 2) == i
.operands
);
8287 /* There are only 2 non-immediate operands. */
8288 gas_assert (op
< i
.imm_operands
+ 2
8289 && i
.operands
== i
.imm_operands
+ 2);
8290 vex_reg
= i
.imm_operands
+ 1;
8294 gas_assert (op
< i
.operands
);
8296 if (vex_reg
!= (unsigned int) ~0)
8298 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8300 if ((type
->bitfield
.class != Reg
8301 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8302 && type
->bitfield
.class != RegSIMD
8303 && !operand_type_equal (type
, ®mask
))
8306 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8309 /* Don't set OP operand twice. */
8312 /* If there is an extension opcode to put here, the
8313 register number must be put into the regmem field. */
8314 if (i
.tm
.extension_opcode
!= None
)
8316 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8317 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8319 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8324 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8325 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8327 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8332 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8333 must set it to 3 to indicate this is a register operand
8334 in the regmem field. */
8335 if (!i
.mem_operands
)
8339 /* Fill in i.rm.reg field with extension opcode (if any). */
8340 if (i
.tm
.extension_opcode
!= None
)
8341 i
.rm
.reg
= i
.tm
.extension_opcode
;
8347 flip_code16 (unsigned int code16
)
8349 gas_assert (i
.tm
.operands
== 1);
8351 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8352 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8353 || i
.tm
.operand_types
[0].bitfield
.disp32s
8354 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8359 output_branch (void)
8365 relax_substateT subtype
;
8369 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8370 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8373 if (i
.prefix
[DATA_PREFIX
] != 0)
8377 code16
^= flip_code16(code16
);
8379 /* Pentium4 branch hints. */
8380 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8381 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8386 if (i
.prefix
[REX_PREFIX
] != 0)
8392 /* BND prefixed jump. */
8393 if (i
.prefix
[BND_PREFIX
] != 0)
8399 if (i
.prefixes
!= 0)
8400 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8402 /* It's always a symbol; End frag & setup for relax.
8403 Make sure there is enough room in this frag for the largest
8404 instruction we may generate in md_convert_frag. This is 2
8405 bytes for the opcode and room for the prefix and largest
8407 frag_grow (prefix
+ 2 + 4);
8408 /* Prefix and 1 opcode byte go in fr_fix. */
8409 p
= frag_more (prefix
+ 1);
8410 if (i
.prefix
[DATA_PREFIX
] != 0)
8411 *p
++ = DATA_PREFIX_OPCODE
;
8412 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8413 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8414 *p
++ = i
.prefix
[SEG_PREFIX
];
8415 if (i
.prefix
[BND_PREFIX
] != 0)
8416 *p
++ = BND_PREFIX_OPCODE
;
8417 if (i
.prefix
[REX_PREFIX
] != 0)
8418 *p
++ = i
.prefix
[REX_PREFIX
];
8419 *p
= i
.tm
.base_opcode
;
8421 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8422 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8423 else if (cpu_arch_flags
.bitfield
.cpui386
)
8424 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8426 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8429 sym
= i
.op
[0].disps
->X_add_symbol
;
8430 off
= i
.op
[0].disps
->X_add_number
;
8432 if (i
.op
[0].disps
->X_op
!= O_constant
8433 && i
.op
[0].disps
->X_op
!= O_symbol
)
8435 /* Handle complex expressions. */
8436 sym
= make_expr_symbol (i
.op
[0].disps
);
8440 /* 1 possible extra opcode + 4 byte displacement go in var part.
8441 Pass reloc in fr_var. */
8442 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8446 /* Return TRUE iff PLT32 relocation should be used for branching to
8450 need_plt32_p (symbolS
*s
)
8452 /* PLT32 relocation is ELF only. */
8457 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8458 krtld support it. */
8462 /* Since there is no need to prepare for PLT branch on x86-64, we
8463 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8464 be used as a marker for 32-bit PC-relative branches. */
8468 /* Weak or undefined symbol need PLT32 relocation. */
8469 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8472 /* Non-global symbol doesn't need PLT32 relocation. */
8473 if (! S_IS_EXTERNAL (s
))
8476 /* Other global symbols need PLT32 relocation. NB: Symbol with
8477 non-default visibilities are treated as normal global symbol
8478 so that PLT32 relocation can be used as a marker for 32-bit
8479 PC-relative branches. It is useful for linker relaxation. */
8490 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8492 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8494 /* This is a loop or jecxz type instruction. */
8496 if (i
.prefix
[ADDR_PREFIX
] != 0)
8498 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8501 /* Pentium4 branch hints. */
8502 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8503 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8505 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8514 if (flag_code
== CODE_16BIT
)
8517 if (i
.prefix
[DATA_PREFIX
] != 0)
8519 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8521 code16
^= flip_code16(code16
);
8529 /* BND prefixed jump. */
8530 if (i
.prefix
[BND_PREFIX
] != 0)
8532 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8536 if (i
.prefix
[REX_PREFIX
] != 0)
8538 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8542 if (i
.prefixes
!= 0)
8543 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8545 p
= frag_more (i
.tm
.opcode_length
+ size
);
8546 switch (i
.tm
.opcode_length
)
8549 *p
++ = i
.tm
.base_opcode
>> 8;
8552 *p
++ = i
.tm
.base_opcode
;
8558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8560 && jump_reloc
== NO_RELOC
8561 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8562 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8565 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8567 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8568 i
.op
[0].disps
, 1, jump_reloc
);
8570 /* All jumps handled here are signed, but don't use a signed limit
8571 check for 32 and 16 bit jumps as we want to allow wrap around at
8572 4G and 64k respectively. */
8574 fixP
->fx_signed
= 1;
8578 output_interseg_jump (void)
8586 if (flag_code
== CODE_16BIT
)
8590 if (i
.prefix
[DATA_PREFIX
] != 0)
8597 gas_assert (!i
.prefix
[REX_PREFIX
]);
8603 if (i
.prefixes
!= 0)
8604 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8606 /* 1 opcode; 2 segment; offset */
8607 p
= frag_more (prefix
+ 1 + 2 + size
);
8609 if (i
.prefix
[DATA_PREFIX
] != 0)
8610 *p
++ = DATA_PREFIX_OPCODE
;
8612 if (i
.prefix
[REX_PREFIX
] != 0)
8613 *p
++ = i
.prefix
[REX_PREFIX
];
8615 *p
++ = i
.tm
.base_opcode
;
8616 if (i
.op
[1].imms
->X_op
== O_constant
)
8618 offsetT n
= i
.op
[1].imms
->X_add_number
;
8621 && !fits_in_unsigned_word (n
)
8622 && !fits_in_signed_word (n
))
8624 as_bad (_("16-bit jump out of range"));
8627 md_number_to_chars (p
, n
, size
);
8630 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8631 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8632 if (i
.op
[0].imms
->X_op
!= O_constant
)
8633 as_bad (_("can't handle non absolute segment in `%s'"),
8635 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8643 asection
*seg
= now_seg
;
8644 subsegT subseg
= now_subseg
;
8646 unsigned int alignment
, align_size_1
;
8647 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8648 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8649 unsigned int padding
;
8651 if (!IS_ELF
|| !x86_used_note
)
8654 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8656 /* The .note.gnu.property section layout:
8658 Field Length Contents
8661 n_descsz 4 The note descriptor size
8662 n_type 4 NT_GNU_PROPERTY_TYPE_0
8664 n_desc n_descsz The program property array
8668 /* Create the .note.gnu.property section. */
8669 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8670 bfd_set_section_flags (sec
,
8677 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8688 bfd_set_section_alignment (sec
, alignment
);
8689 elf_section_type (sec
) = SHT_NOTE
;
8691 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8693 isa_1_descsz_raw
= 4 + 4 + 4;
8694 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8695 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8697 feature_2_descsz_raw
= isa_1_descsz
;
8698 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8700 feature_2_descsz_raw
+= 4 + 4 + 4;
8701 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8702 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8705 descsz
= feature_2_descsz
;
8706 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8707 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8709 /* Write n_namsz. */
8710 md_number_to_chars (p
, (valueT
) 4, 4);
8712 /* Write n_descsz. */
8713 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8716 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8719 memcpy (p
+ 4 * 3, "GNU", 4);
8721 /* Write 4-byte type. */
8722 md_number_to_chars (p
+ 4 * 4,
8723 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8725 /* Write 4-byte data size. */
8726 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8728 /* Write 4-byte data. */
8729 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8731 /* Zero out paddings. */
8732 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8734 memset (p
+ 4 * 7, 0, padding
);
8736 /* Write 4-byte type. */
8737 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8738 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8740 /* Write 4-byte data size. */
8741 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8743 /* Write 4-byte data. */
8744 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8745 (valueT
) x86_feature_2_used
, 4);
8747 /* Zero out paddings. */
8748 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8750 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8752 /* We probably can't restore the current segment, for there likely
8755 subseg_set (seg
, subseg
);
8760 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8761 const char *frag_now_ptr
)
8763 unsigned int len
= 0;
8765 if (start_frag
!= frag_now
)
8767 const fragS
*fr
= start_frag
;
8772 } while (fr
&& fr
!= frag_now
);
8775 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8778 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8779 be macro-fused with conditional jumps.
8780 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8781 or is one of the following format:
8794 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8796 /* No RIP address. */
8797 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8800 /* No VEX/EVEX encoding. */
8801 if (is_any_vex_encoding (&i
.tm
))
8804 /* add, sub without add/sub m, imm. */
8805 if (i
.tm
.base_opcode
<= 5
8806 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8807 || ((i
.tm
.base_opcode
| 3) == 0x83
8808 && (i
.tm
.extension_opcode
== 0x5
8809 || i
.tm
.extension_opcode
== 0x0)))
8811 *mf_cmp_p
= mf_cmp_alu_cmp
;
8812 return !(i
.mem_operands
&& i
.imm_operands
);
8815 /* and without and m, imm. */
8816 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8817 || ((i
.tm
.base_opcode
| 3) == 0x83
8818 && i
.tm
.extension_opcode
== 0x4))
8820 *mf_cmp_p
= mf_cmp_test_and
;
8821 return !(i
.mem_operands
&& i
.imm_operands
);
8824 /* test without test m imm. */
8825 if ((i
.tm
.base_opcode
| 1) == 0x85
8826 || (i
.tm
.base_opcode
| 1) == 0xa9
8827 || ((i
.tm
.base_opcode
| 1) == 0xf7
8828 && i
.tm
.extension_opcode
== 0))
8830 *mf_cmp_p
= mf_cmp_test_and
;
8831 return !(i
.mem_operands
&& i
.imm_operands
);
8834 /* cmp without cmp m, imm. */
8835 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8836 || ((i
.tm
.base_opcode
| 3) == 0x83
8837 && (i
.tm
.extension_opcode
== 0x7)))
8839 *mf_cmp_p
= mf_cmp_alu_cmp
;
8840 return !(i
.mem_operands
&& i
.imm_operands
);
8843 /* inc, dec without inc/dec m. */
8844 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8845 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8846 || ((i
.tm
.base_opcode
| 1) == 0xff
8847 && i
.tm
.extension_opcode
<= 0x1))
8849 *mf_cmp_p
= mf_cmp_incdec
;
8850 return !i
.mem_operands
;
8856 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8859 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8861 /* NB: Don't work with COND_JUMP86 without i386. */
8862 if (!align_branch_power
8863 || now_seg
== absolute_section
8864 || !cpu_arch_flags
.bitfield
.cpui386
8865 || !(align_branch
& align_branch_fused_bit
))
8868 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8870 if (last_insn
.kind
== last_insn_other
8871 || last_insn
.seg
!= now_seg
)
8874 as_warn_where (last_insn
.file
, last_insn
.line
,
8875 _("`%s` skips -malign-branch-boundary on `%s`"),
8876 last_insn
.name
, i
.tm
.name
);
8882 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8885 add_branch_prefix_frag_p (void)
8887 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8888 to PadLock instructions since they include prefixes in opcode. */
8889 if (!align_branch_power
8890 || !align_branch_prefix_size
8891 || now_seg
== absolute_section
8892 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8893 || !cpu_arch_flags
.bitfield
.cpui386
)
8896 /* Don't add prefix if it is a prefix or there is no operand in case
8897 that segment prefix is special. */
8898 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8901 if (last_insn
.kind
== last_insn_other
8902 || last_insn
.seg
!= now_seg
)
8906 as_warn_where (last_insn
.file
, last_insn
.line
,
8907 _("`%s` skips -malign-branch-boundary on `%s`"),
8908 last_insn
.name
, i
.tm
.name
);
8913 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8916 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8917 enum mf_jcc_kind
*mf_jcc_p
)
8921 /* NB: Don't work with COND_JUMP86 without i386. */
8922 if (!align_branch_power
8923 || now_seg
== absolute_section
8924 || !cpu_arch_flags
.bitfield
.cpui386
)
8929 /* Check for jcc and direct jmp. */
8930 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8932 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8934 *branch_p
= align_branch_jmp
;
8935 add_padding
= align_branch
& align_branch_jmp_bit
;
8939 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8940 igore the lowest bit. */
8941 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8942 *branch_p
= align_branch_jcc
;
8943 if ((align_branch
& align_branch_jcc_bit
))
8947 else if (is_any_vex_encoding (&i
.tm
))
8949 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8952 *branch_p
= align_branch_ret
;
8953 if ((align_branch
& align_branch_ret_bit
))
8958 /* Check for indirect jmp, direct and indirect calls. */
8959 if (i
.tm
.base_opcode
== 0xe8)
8962 *branch_p
= align_branch_call
;
8963 if ((align_branch
& align_branch_call_bit
))
8966 else if (i
.tm
.base_opcode
== 0xff
8967 && (i
.tm
.extension_opcode
== 2
8968 || i
.tm
.extension_opcode
== 4))
8970 /* Indirect call and jmp. */
8971 *branch_p
= align_branch_indirect
;
8972 if ((align_branch
& align_branch_indirect_bit
))
8979 && (i
.op
[0].disps
->X_op
== O_symbol
8980 || (i
.op
[0].disps
->X_op
== O_subtract
8981 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8983 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8984 /* No padding to call to global or undefined tls_get_addr. */
8985 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8986 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8992 && last_insn
.kind
!= last_insn_other
8993 && last_insn
.seg
== now_seg
)
8996 as_warn_where (last_insn
.file
, last_insn
.line
,
8997 _("`%s` skips -malign-branch-boundary on `%s`"),
8998 last_insn
.name
, i
.tm
.name
);
9008 fragS
*insn_start_frag
;
9009 offsetT insn_start_off
;
9010 fragS
*fragP
= NULL
;
9011 enum align_branch_kind branch
= align_branch_none
;
9012 /* The initializer is arbitrary just to avoid uninitialized error.
9013 it's actually either assigned in add_branch_padding_frag_p
9014 or never be used. */
9015 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9018 if (IS_ELF
&& x86_used_note
)
9020 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9021 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9022 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9023 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9024 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9025 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9026 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9027 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9028 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9029 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9030 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9031 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9032 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9033 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9034 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9035 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9036 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9038 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9040 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9042 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9044 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9046 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9048 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9054 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9055 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9056 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9057 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9058 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9059 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9060 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9061 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9062 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9063 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9064 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9065 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9066 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9067 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9068 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9069 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9071 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9072 || i
.tm
.cpu_flags
.bitfield
.cpu287
9073 || i
.tm
.cpu_flags
.bitfield
.cpu387
9074 || i
.tm
.cpu_flags
.bitfield
.cpu687
9075 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9076 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9078 || i
.tm
.base_opcode
== 0xf77 /* emms */
9079 || i
.tm
.base_opcode
== 0xf0e /* femms */
9080 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9081 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9082 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9084 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9086 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9088 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9089 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9090 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9091 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9092 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9093 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9094 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9095 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9096 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9100 /* Tie dwarf2 debug info to the address at the start of the insn.
9101 We can't do this after the insn has been output as the current
9102 frag may have been closed off. eg. by frag_var. */
9103 dwarf2_emit_insn (0);
9105 insn_start_frag
= frag_now
;
9106 insn_start_off
= frag_now_fix ();
9108 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9111 /* Branch can be 8 bytes. Leave some room for prefixes. */
9112 unsigned int max_branch_padding_size
= 14;
9114 /* Align section to boundary. */
9115 record_alignment (now_seg
, align_branch_power
);
9117 /* Make room for padding. */
9118 frag_grow (max_branch_padding_size
);
9120 /* Start of the padding. */
9125 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9126 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9129 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9130 fragP
->tc_frag_data
.branch_type
= branch
;
9131 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9135 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9137 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9138 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9140 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9141 output_interseg_jump ();
9144 /* Output normal instructions here. */
9148 unsigned int prefix
;
9149 enum mf_cmp_kind mf_cmp
;
9152 && (i
.tm
.base_opcode
== 0xfaee8
9153 || i
.tm
.base_opcode
== 0xfaef0
9154 || i
.tm
.base_opcode
== 0xfaef8))
9156 /* Encode lfence, mfence, and sfence as
9157 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9158 offsetT val
= 0x240483f0ULL
;
9160 md_number_to_chars (p
, val
, 5);
9164 /* Some processors fail on LOCK prefix. This options makes
9165 assembler ignore LOCK prefix and serves as a workaround. */
9166 if (omit_lock_prefix
)
9168 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9170 i
.prefix
[LOCK_PREFIX
] = 0;
9174 /* Skip if this is a branch. */
9176 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9178 /* Make room for padding. */
9179 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9184 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9185 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9188 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9189 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9190 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9192 else if (add_branch_prefix_frag_p ())
9194 unsigned int max_prefix_size
= align_branch_prefix_size
;
9196 /* Make room for padding. */
9197 frag_grow (max_prefix_size
);
9202 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9203 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9206 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9209 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9210 don't need the explicit prefix. */
9211 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9213 switch (i
.tm
.opcode_length
)
9216 if (i
.tm
.base_opcode
& 0xff000000)
9218 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9219 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9220 || prefix
!= REPE_PREFIX_OPCODE
9221 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9222 add_prefix (prefix
);
9226 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9228 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9229 add_prefix (prefix
);
9235 /* Check for pseudo prefixes. */
9236 as_bad_where (insn_start_frag
->fr_file
,
9237 insn_start_frag
->fr_line
,
9238 _("pseudo prefix without instruction"));
9244 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9245 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9246 R_X86_64_GOTTPOFF relocation so that linker can safely
9247 perform IE->LE optimization. A dummy REX_OPCODE prefix
9248 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9249 relocation for GDesc -> IE/LE optimization. */
9250 if (x86_elf_abi
== X86_64_X32_ABI
9252 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9253 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9254 && i
.prefix
[REX_PREFIX
] == 0)
9255 add_prefix (REX_OPCODE
);
9258 /* The prefix bytes. */
9259 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9261 FRAG_APPEND_1_CHAR (*q
);
9265 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9270 /* REX byte is encoded in VEX prefix. */
9274 FRAG_APPEND_1_CHAR (*q
);
9277 /* There should be no other prefixes for instructions
9282 /* For EVEX instructions i.vrex should become 0 after
9283 build_evex_prefix. For VEX instructions upper 16 registers
9284 aren't available, so VREX should be 0. */
9287 /* Now the VEX prefix. */
9288 p
= frag_more (i
.vex
.length
);
9289 for (j
= 0; j
< i
.vex
.length
; j
++)
9290 p
[j
] = i
.vex
.bytes
[j
];
9293 /* Now the opcode; be careful about word order here! */
9294 if (i
.tm
.opcode_length
== 1)
9296 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9300 switch (i
.tm
.opcode_length
)
9304 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9305 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9309 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9319 /* Put out high byte first: can't use md_number_to_chars! */
9320 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9321 *p
= i
.tm
.base_opcode
& 0xff;
9324 /* Now the modrm byte and sib byte (if present). */
9325 if (i
.tm
.opcode_modifier
.modrm
)
9327 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9330 /* If i.rm.regmem == ESP (4)
9331 && i.rm.mode != (Register mode)
9333 ==> need second modrm byte. */
9334 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9336 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9337 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9339 | i
.sib
.scale
<< 6));
9342 if (i
.disp_operands
)
9343 output_disp (insn_start_frag
, insn_start_off
);
9346 output_imm (insn_start_frag
, insn_start_off
);
9349 * frag_now_fix () returning plain abs_section_offset when we're in the
9350 * absolute section, and abs_section_offset not getting updated as data
9351 * gets added to the frag breaks the logic below.
9353 if (now_seg
!= absolute_section
)
9355 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9357 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9361 /* NB: Don't add prefix with GOTPC relocation since
9362 output_disp() above depends on the fixed encoding
9363 length. Can't add prefix with TLS relocation since
9364 it breaks TLS linker optimization. */
9365 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9366 /* Prefix count on the current instruction. */
9367 unsigned int count
= i
.vex
.length
;
9369 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9370 /* REX byte is encoded in VEX/EVEX prefix. */
9371 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9374 /* Count prefixes for extended opcode maps. */
9376 switch (i
.tm
.opcode_length
)
9379 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9382 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9394 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9403 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9406 /* Set the maximum prefix size in BRANCH_PREFIX
9408 if (fragP
->tc_frag_data
.max_bytes
> max
)
9409 fragP
->tc_frag_data
.max_bytes
= max
;
9410 if (fragP
->tc_frag_data
.max_bytes
> count
)
9411 fragP
->tc_frag_data
.max_bytes
-= count
;
9413 fragP
->tc_frag_data
.max_bytes
= 0;
9417 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9419 unsigned int max_prefix_size
;
9420 if (align_branch_prefix_size
> max
)
9421 max_prefix_size
= max
;
9423 max_prefix_size
= align_branch_prefix_size
;
9424 if (max_prefix_size
> count
)
9425 fragP
->tc_frag_data
.max_prefix_length
9426 = max_prefix_size
- count
;
9429 /* Use existing segment prefix if possible. Use CS
9430 segment prefix in 64-bit mode. In 32-bit mode, use SS
9431 segment prefix with ESP/EBP base register and use DS
9432 segment prefix without ESP/EBP base register. */
9433 if (i
.prefix
[SEG_PREFIX
])
9434 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9435 else if (flag_code
== CODE_64BIT
)
9436 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9438 && (i
.base_reg
->reg_num
== 4
9439 || i
.base_reg
->reg_num
== 5))
9440 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9442 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9447 /* NB: Don't work with COND_JUMP86 without i386. */
9448 if (align_branch_power
9449 && now_seg
!= absolute_section
9450 && cpu_arch_flags
.bitfield
.cpui386
)
9452 /* Terminate each frag so that we can add prefix and check for
9454 frag_wane (frag_now
);
9461 pi ("" /*line*/, &i
);
9463 #endif /* DEBUG386 */
9466 /* Return the size of the displacement operand N. */
9469 disp_size (unsigned int n
)
9473 if (i
.types
[n
].bitfield
.disp64
)
9475 else if (i
.types
[n
].bitfield
.disp8
)
9477 else if (i
.types
[n
].bitfield
.disp16
)
9482 /* Return the size of the immediate operand N. */
9485 imm_size (unsigned int n
)
9488 if (i
.types
[n
].bitfield
.imm64
)
9490 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9492 else if (i
.types
[n
].bitfield
.imm16
)
9498 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9503 for (n
= 0; n
< i
.operands
; n
++)
9505 if (operand_type_check (i
.types
[n
], disp
))
9507 if (i
.op
[n
].disps
->X_op
== O_constant
)
9509 int size
= disp_size (n
);
9510 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9512 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9514 p
= frag_more (size
);
9515 md_number_to_chars (p
, val
, size
);
9519 enum bfd_reloc_code_real reloc_type
;
9520 int size
= disp_size (n
);
9521 int sign
= i
.types
[n
].bitfield
.disp32s
;
9522 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9525 /* We can't have 8 bit displacement here. */
9526 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9528 /* The PC relative address is computed relative
9529 to the instruction boundary, so in case immediate
9530 fields follows, we need to adjust the value. */
9531 if (pcrel
&& i
.imm_operands
)
9536 for (n1
= 0; n1
< i
.operands
; n1
++)
9537 if (operand_type_check (i
.types
[n1
], imm
))
9539 /* Only one immediate is allowed for PC
9540 relative address. */
9541 gas_assert (sz
== 0);
9543 i
.op
[n
].disps
->X_add_number
-= sz
;
9545 /* We should find the immediate. */
9546 gas_assert (sz
!= 0);
9549 p
= frag_more (size
);
9550 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9552 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9553 && (((reloc_type
== BFD_RELOC_32
9554 || reloc_type
== BFD_RELOC_X86_64_32S
9555 || (reloc_type
== BFD_RELOC_64
9557 && (i
.op
[n
].disps
->X_op
== O_symbol
9558 || (i
.op
[n
].disps
->X_op
== O_add
9559 && ((symbol_get_value_expression
9560 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9562 || reloc_type
== BFD_RELOC_32_PCREL
))
9566 reloc_type
= BFD_RELOC_386_GOTPC
;
9567 i
.has_gotpc_tls_reloc
= TRUE
;
9568 i
.op
[n
].imms
->X_add_number
+=
9569 encoding_length (insn_start_frag
, insn_start_off
, p
);
9571 else if (reloc_type
== BFD_RELOC_64
)
9572 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9574 /* Don't do the adjustment for x86-64, as there
9575 the pcrel addressing is relative to the _next_
9576 insn, and that is taken care of in other code. */
9577 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9579 else if (align_branch_power
)
9583 case BFD_RELOC_386_TLS_GD
:
9584 case BFD_RELOC_386_TLS_LDM
:
9585 case BFD_RELOC_386_TLS_IE
:
9586 case BFD_RELOC_386_TLS_IE_32
:
9587 case BFD_RELOC_386_TLS_GOTIE
:
9588 case BFD_RELOC_386_TLS_GOTDESC
:
9589 case BFD_RELOC_386_TLS_DESC_CALL
:
9590 case BFD_RELOC_X86_64_TLSGD
:
9591 case BFD_RELOC_X86_64_TLSLD
:
9592 case BFD_RELOC_X86_64_GOTTPOFF
:
9593 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9594 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9595 i
.has_gotpc_tls_reloc
= TRUE
;
9600 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9601 size
, i
.op
[n
].disps
, pcrel
,
9603 /* Check for "call/jmp *mem", "mov mem, %reg",
9604 "test %reg, mem" and "binop mem, %reg" where binop
9605 is one of adc, add, and, cmp, or, sbb, sub, xor
9606 instructions without data prefix. Always generate
9607 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9608 if (i
.prefix
[DATA_PREFIX
] == 0
9609 && (generate_relax_relocations
9612 && i
.rm
.regmem
== 5))
9614 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9615 && !is_any_vex_encoding(&i
.tm
)
9616 && ((i
.operands
== 1
9617 && i
.tm
.base_opcode
== 0xff
9618 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9620 && (i
.tm
.base_opcode
== 0x8b
9621 || i
.tm
.base_opcode
== 0x85
9622 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9626 fixP
->fx_tcbit
= i
.rex
!= 0;
9628 && (i
.base_reg
->reg_num
== RegIP
))
9629 fixP
->fx_tcbit2
= 1;
9632 fixP
->fx_tcbit2
= 1;
9640 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9645 for (n
= 0; n
< i
.operands
; n
++)
9647 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9648 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9651 if (operand_type_check (i
.types
[n
], imm
))
9653 if (i
.op
[n
].imms
->X_op
== O_constant
)
9655 int size
= imm_size (n
);
9658 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9660 p
= frag_more (size
);
9661 md_number_to_chars (p
, val
, size
);
9665 /* Not absolute_section.
9666 Need a 32-bit fixup (don't support 8bit
9667 non-absolute imms). Try to support other
9669 enum bfd_reloc_code_real reloc_type
;
9670 int size
= imm_size (n
);
9673 if (i
.types
[n
].bitfield
.imm32s
9674 && (i
.suffix
== QWORD_MNEM_SUFFIX
9675 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9680 p
= frag_more (size
);
9681 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9683 /* This is tough to explain. We end up with this one if we
9684 * have operands that look like
9685 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9686 * obtain the absolute address of the GOT, and it is strongly
9687 * preferable from a performance point of view to avoid using
9688 * a runtime relocation for this. The actual sequence of
9689 * instructions often look something like:
9694 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9696 * The call and pop essentially return the absolute address
9697 * of the label .L66 and store it in %ebx. The linker itself
9698 * will ultimately change the first operand of the addl so
9699 * that %ebx points to the GOT, but to keep things simple, the
9700 * .o file must have this operand set so that it generates not
9701 * the absolute address of .L66, but the absolute address of
9702 * itself. This allows the linker itself simply treat a GOTPC
9703 * relocation as asking for a pcrel offset to the GOT to be
9704 * added in, and the addend of the relocation is stored in the
9705 * operand field for the instruction itself.
9707 * Our job here is to fix the operand so that it would add
9708 * the correct offset so that %ebx would point to itself. The
9709 * thing that is tricky is that .-.L66 will point to the
9710 * beginning of the instruction, so we need to further modify
9711 * the operand so that it will point to itself. There are
9712 * other cases where you have something like:
9714 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9716 * and here no correction would be required. Internally in
9717 * the assembler we treat operands of this form as not being
9718 * pcrel since the '.' is explicitly mentioned, and I wonder
9719 * whether it would simplify matters to do it this way. Who
9720 * knows. In earlier versions of the PIC patches, the
9721 * pcrel_adjust field was used to store the correction, but
9722 * since the expression is not pcrel, I felt it would be
9723 * confusing to do it this way. */
9725 if ((reloc_type
== BFD_RELOC_32
9726 || reloc_type
== BFD_RELOC_X86_64_32S
9727 || reloc_type
== BFD_RELOC_64
)
9729 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9730 && (i
.op
[n
].imms
->X_op
== O_symbol
9731 || (i
.op
[n
].imms
->X_op
== O_add
9732 && ((symbol_get_value_expression
9733 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9737 reloc_type
= BFD_RELOC_386_GOTPC
;
9739 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9741 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9742 i
.has_gotpc_tls_reloc
= TRUE
;
9743 i
.op
[n
].imms
->X_add_number
+=
9744 encoding_length (insn_start_frag
, insn_start_off
, p
);
9746 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9747 i
.op
[n
].imms
, 0, reloc_type
);
9753 /* x86_cons_fix_new is called via the expression parsing code when a
9754 reloc is needed. We use this hook to get the correct .got reloc. */
9755 static int cons_sign
= -1;
9758 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9759 expressionS
*exp
, bfd_reloc_code_real_type r
)
9761 r
= reloc (len
, 0, cons_sign
, r
);
9764 if (exp
->X_op
== O_secrel
)
9766 exp
->X_op
= O_symbol
;
9767 r
= BFD_RELOC_32_SECREL
;
9771 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9774 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9775 purpose of the `.dc.a' internal pseudo-op. */
9778 x86_address_bytes (void)
9780 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9782 return stdoutput
->arch_info
->bits_per_address
/ 8;
9785 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9787 # define lex_got(reloc, adjust, types) NULL
9789 /* Parse operands of the form
9790 <symbol>@GOTOFF+<nnn>
9791 and similar .plt or .got references.
9793 If we find one, set up the correct relocation in RELOC and copy the
9794 input string, minus the `@GOTOFF' into a malloc'd buffer for
9795 parsing by the calling routine. Return this buffer, and if ADJUST
9796 is non-null set it to the length of the string we removed from the
9797 input line. Otherwise return NULL. */
9799 lex_got (enum bfd_reloc_code_real
*rel
,
9801 i386_operand_type
*types
)
9803 /* Some of the relocations depend on the size of what field is to
9804 be relocated. But in our callers i386_immediate and i386_displacement
9805 we don't yet know the operand size (this will be set by insn
9806 matching). Hence we record the word32 relocation here,
9807 and adjust the reloc according to the real size in reloc(). */
9808 static const struct {
9811 const enum bfd_reloc_code_real rel
[2];
9812 const i386_operand_type types64
;
9814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9815 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9817 OPERAND_TYPE_IMM32_64
},
9819 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9820 BFD_RELOC_X86_64_PLTOFF64
},
9821 OPERAND_TYPE_IMM64
},
9822 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9823 BFD_RELOC_X86_64_PLT32
},
9824 OPERAND_TYPE_IMM32_32S_DISP32
},
9825 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9826 BFD_RELOC_X86_64_GOTPLT64
},
9827 OPERAND_TYPE_IMM64_DISP64
},
9828 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9829 BFD_RELOC_X86_64_GOTOFF64
},
9830 OPERAND_TYPE_IMM64_DISP64
},
9831 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9832 BFD_RELOC_X86_64_GOTPCREL
},
9833 OPERAND_TYPE_IMM32_32S_DISP32
},
9834 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9835 BFD_RELOC_X86_64_TLSGD
},
9836 OPERAND_TYPE_IMM32_32S_DISP32
},
9837 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9838 _dummy_first_bfd_reloc_code_real
},
9839 OPERAND_TYPE_NONE
},
9840 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9841 BFD_RELOC_X86_64_TLSLD
},
9842 OPERAND_TYPE_IMM32_32S_DISP32
},
9843 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9844 BFD_RELOC_X86_64_GOTTPOFF
},
9845 OPERAND_TYPE_IMM32_32S_DISP32
},
9846 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9847 BFD_RELOC_X86_64_TPOFF32
},
9848 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9849 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9850 _dummy_first_bfd_reloc_code_real
},
9851 OPERAND_TYPE_NONE
},
9852 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9853 BFD_RELOC_X86_64_DTPOFF32
},
9854 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9855 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9856 _dummy_first_bfd_reloc_code_real
},
9857 OPERAND_TYPE_NONE
},
9858 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9859 _dummy_first_bfd_reloc_code_real
},
9860 OPERAND_TYPE_NONE
},
9861 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9862 BFD_RELOC_X86_64_GOT32
},
9863 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9864 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9865 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9866 OPERAND_TYPE_IMM32_32S_DISP32
},
9867 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9868 BFD_RELOC_X86_64_TLSDESC_CALL
},
9869 OPERAND_TYPE_IMM32_32S_DISP32
},
9874 #if defined (OBJ_MAYBE_ELF)
9879 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9880 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9883 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9885 int len
= gotrel
[j
].len
;
9886 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9888 if (gotrel
[j
].rel
[object_64bit
] != 0)
9891 char *tmpbuf
, *past_reloc
;
9893 *rel
= gotrel
[j
].rel
[object_64bit
];
9897 if (flag_code
!= CODE_64BIT
)
9899 types
->bitfield
.imm32
= 1;
9900 types
->bitfield
.disp32
= 1;
9903 *types
= gotrel
[j
].types64
;
9906 if (j
!= 0 && GOT_symbol
== NULL
)
9907 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9909 /* The length of the first part of our input line. */
9910 first
= cp
- input_line_pointer
;
9912 /* The second part goes from after the reloc token until
9913 (and including) an end_of_line char or comma. */
9914 past_reloc
= cp
+ 1 + len
;
9916 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9918 second
= cp
+ 1 - past_reloc
;
9920 /* Allocate and copy string. The trailing NUL shouldn't
9921 be necessary, but be safe. */
9922 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9923 memcpy (tmpbuf
, input_line_pointer
, first
);
9924 if (second
!= 0 && *past_reloc
!= ' ')
9925 /* Replace the relocation token with ' ', so that
9926 errors like foo@GOTOFF1 will be detected. */
9927 tmpbuf
[first
++] = ' ';
9929 /* Increment length by 1 if the relocation token is
9934 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9935 tmpbuf
[first
+ second
] = '\0';
9939 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9940 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9945 /* Might be a symbol version string. Don't as_bad here. */
9954 /* Parse operands of the form
9955 <symbol>@SECREL32+<nnn>
9957 If we find one, set up the correct relocation in RELOC and copy the
9958 input string, minus the `@SECREL32' into a malloc'd buffer for
9959 parsing by the calling routine. Return this buffer, and if ADJUST
9960 is non-null set it to the length of the string we removed from the
9961 input line. Otherwise return NULL.
9963 This function is copied from the ELF version above adjusted for PE targets. */
9966 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9967 int *adjust ATTRIBUTE_UNUSED
,
9968 i386_operand_type
*types
)
9974 const enum bfd_reloc_code_real rel
[2];
9975 const i386_operand_type types64
;
9979 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9980 BFD_RELOC_32_SECREL
},
9981 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9987 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9988 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9991 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9993 int len
= gotrel
[j
].len
;
9995 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9997 if (gotrel
[j
].rel
[object_64bit
] != 0)
10000 char *tmpbuf
, *past_reloc
;
10002 *rel
= gotrel
[j
].rel
[object_64bit
];
10008 if (flag_code
!= CODE_64BIT
)
10010 types
->bitfield
.imm32
= 1;
10011 types
->bitfield
.disp32
= 1;
10014 *types
= gotrel
[j
].types64
;
10017 /* The length of the first part of our input line. */
10018 first
= cp
- input_line_pointer
;
10020 /* The second part goes from after the reloc token until
10021 (and including) an end_of_line char or comma. */
10022 past_reloc
= cp
+ 1 + len
;
10024 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10026 second
= cp
+ 1 - past_reloc
;
10028 /* Allocate and copy string. The trailing NUL shouldn't
10029 be necessary, but be safe. */
10030 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10031 memcpy (tmpbuf
, input_line_pointer
, first
);
10032 if (second
!= 0 && *past_reloc
!= ' ')
10033 /* Replace the relocation token with ' ', so that
10034 errors like foo@SECLREL321 will be detected. */
10035 tmpbuf
[first
++] = ' ';
10036 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10037 tmpbuf
[first
+ second
] = '\0';
10041 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10042 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10047 /* Might be a symbol version string. Don't as_bad here. */
10053 bfd_reloc_code_real_type
10054 x86_cons (expressionS
*exp
, int size
)
10056 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10058 intel_syntax
= -intel_syntax
;
10061 if (size
== 4 || (object_64bit
&& size
== 8))
10063 /* Handle @GOTOFF and the like in an expression. */
10065 char *gotfree_input_line
;
10068 save
= input_line_pointer
;
10069 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10070 if (gotfree_input_line
)
10071 input_line_pointer
= gotfree_input_line
;
10075 if (gotfree_input_line
)
10077 /* expression () has merrily parsed up to the end of line,
10078 or a comma - in the wrong buffer. Transfer how far
10079 input_line_pointer has moved to the right buffer. */
10080 input_line_pointer
= (save
10081 + (input_line_pointer
- gotfree_input_line
)
10083 free (gotfree_input_line
);
10084 if (exp
->X_op
== O_constant
10085 || exp
->X_op
== O_absent
10086 || exp
->X_op
== O_illegal
10087 || exp
->X_op
== O_register
10088 || exp
->X_op
== O_big
)
10090 char c
= *input_line_pointer
;
10091 *input_line_pointer
= 0;
10092 as_bad (_("missing or invalid expression `%s'"), save
);
10093 *input_line_pointer
= c
;
10095 else if ((got_reloc
== BFD_RELOC_386_PLT32
10096 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10097 && exp
->X_op
!= O_symbol
)
10099 char c
= *input_line_pointer
;
10100 *input_line_pointer
= 0;
10101 as_bad (_("invalid PLT expression `%s'"), save
);
10102 *input_line_pointer
= c
;
10109 intel_syntax
= -intel_syntax
;
10112 i386_intel_simplify (exp
);
10118 signed_cons (int size
)
10120 if (flag_code
== CODE_64BIT
)
10128 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10135 if (exp
.X_op
== O_symbol
)
10136 exp
.X_op
= O_secrel
;
10138 emit_expr (&exp
, 4);
10140 while (*input_line_pointer
++ == ',');
10142 input_line_pointer
--;
10143 demand_empty_rest_of_line ();
10147 /* Handle Vector operations. */
10150 check_VecOperations (char *op_string
, char *op_end
)
10152 const reg_entry
*mask
;
10157 && (op_end
== NULL
|| op_string
< op_end
))
10160 if (*op_string
== '{')
10164 /* Check broadcasts. */
10165 if (strncmp (op_string
, "1to", 3) == 0)
10170 goto duplicated_vec_op
;
10173 if (*op_string
== '8')
10175 else if (*op_string
== '4')
10177 else if (*op_string
== '2')
10179 else if (*op_string
== '1'
10180 && *(op_string
+1) == '6')
10187 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10192 broadcast_op
.type
= bcst_type
;
10193 broadcast_op
.operand
= this_operand
;
10194 broadcast_op
.bytes
= 0;
10195 i
.broadcast
= &broadcast_op
;
10197 /* Check masking operation. */
10198 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10200 if (mask
== &bad_reg
)
10203 /* k0 can't be used for write mask. */
10204 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10206 as_bad (_("`%s%s' can't be used for write mask"),
10207 register_prefix
, mask
->reg_name
);
10213 mask_op
.mask
= mask
;
10214 mask_op
.zeroing
= 0;
10215 mask_op
.operand
= this_operand
;
10221 goto duplicated_vec_op
;
10223 i
.mask
->mask
= mask
;
10225 /* Only "{z}" is allowed here. No need to check
10226 zeroing mask explicitly. */
10227 if (i
.mask
->operand
!= this_operand
)
10229 as_bad (_("invalid write mask `%s'"), saved
);
10234 op_string
= end_op
;
10236 /* Check zeroing-flag for masking operation. */
10237 else if (*op_string
== 'z')
10241 mask_op
.mask
= NULL
;
10242 mask_op
.zeroing
= 1;
10243 mask_op
.operand
= this_operand
;
10248 if (i
.mask
->zeroing
)
10251 as_bad (_("duplicated `%s'"), saved
);
10255 i
.mask
->zeroing
= 1;
10257 /* Only "{%k}" is allowed here. No need to check mask
10258 register explicitly. */
10259 if (i
.mask
->operand
!= this_operand
)
10261 as_bad (_("invalid zeroing-masking `%s'"),
10270 goto unknown_vec_op
;
10272 if (*op_string
!= '}')
10274 as_bad (_("missing `}' in `%s'"), saved
);
10279 /* Strip whitespace since the addition of pseudo prefixes
10280 changed how the scrubber treats '{'. */
10281 if (is_space_char (*op_string
))
10287 /* We don't know this one. */
10288 as_bad (_("unknown vector operation: `%s'"), saved
);
10292 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10294 as_bad (_("zeroing-masking only allowed with write mask"));
10302 i386_immediate (char *imm_start
)
10304 char *save_input_line_pointer
;
10305 char *gotfree_input_line
;
10308 i386_operand_type types
;
10310 operand_type_set (&types
, ~0);
10312 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10314 as_bad (_("at most %d immediate operands are allowed"),
10315 MAX_IMMEDIATE_OPERANDS
);
10319 exp
= &im_expressions
[i
.imm_operands
++];
10320 i
.op
[this_operand
].imms
= exp
;
10322 if (is_space_char (*imm_start
))
10325 save_input_line_pointer
= input_line_pointer
;
10326 input_line_pointer
= imm_start
;
10328 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10329 if (gotfree_input_line
)
10330 input_line_pointer
= gotfree_input_line
;
10332 exp_seg
= expression (exp
);
10334 SKIP_WHITESPACE ();
10336 /* Handle vector operations. */
10337 if (*input_line_pointer
== '{')
10339 input_line_pointer
= check_VecOperations (input_line_pointer
,
10341 if (input_line_pointer
== NULL
)
10345 if (*input_line_pointer
)
10346 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10348 input_line_pointer
= save_input_line_pointer
;
10349 if (gotfree_input_line
)
10351 free (gotfree_input_line
);
10353 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10354 exp
->X_op
= O_illegal
;
10357 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10361 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10362 i386_operand_type types
, const char *imm_start
)
10364 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10367 as_bad (_("missing or invalid immediate expression `%s'"),
10371 else if (exp
->X_op
== O_constant
)
10373 /* Size it properly later. */
10374 i
.types
[this_operand
].bitfield
.imm64
= 1;
10375 /* If not 64bit, sign extend val. */
10376 if (flag_code
!= CODE_64BIT
10377 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10379 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10381 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10382 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10383 && exp_seg
!= absolute_section
10384 && exp_seg
!= text_section
10385 && exp_seg
!= data_section
10386 && exp_seg
!= bss_section
10387 && exp_seg
!= undefined_section
10388 && !bfd_is_com_section (exp_seg
))
10390 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10394 else if (!intel_syntax
&& exp_seg
== reg_section
)
10397 as_bad (_("illegal immediate register operand %s"), imm_start
);
10402 /* This is an address. The size of the address will be
10403 determined later, depending on destination register,
10404 suffix, or the default for the section. */
10405 i
.types
[this_operand
].bitfield
.imm8
= 1;
10406 i
.types
[this_operand
].bitfield
.imm16
= 1;
10407 i
.types
[this_operand
].bitfield
.imm32
= 1;
10408 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10409 i
.types
[this_operand
].bitfield
.imm64
= 1;
10410 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10418 i386_scale (char *scale
)
10421 char *save
= input_line_pointer
;
10423 input_line_pointer
= scale
;
10424 val
= get_absolute_expression ();
10429 i
.log2_scale_factor
= 0;
10432 i
.log2_scale_factor
= 1;
10435 i
.log2_scale_factor
= 2;
10438 i
.log2_scale_factor
= 3;
10442 char sep
= *input_line_pointer
;
10444 *input_line_pointer
= '\0';
10445 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10447 *input_line_pointer
= sep
;
10448 input_line_pointer
= save
;
10452 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10454 as_warn (_("scale factor of %d without an index register"),
10455 1 << i
.log2_scale_factor
);
10456 i
.log2_scale_factor
= 0;
10458 scale
= input_line_pointer
;
10459 input_line_pointer
= save
;
10464 i386_displacement (char *disp_start
, char *disp_end
)
10468 char *save_input_line_pointer
;
10469 char *gotfree_input_line
;
10471 i386_operand_type bigdisp
, types
= anydisp
;
10474 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10476 as_bad (_("at most %d displacement operands are allowed"),
10477 MAX_MEMORY_OPERANDS
);
10481 operand_type_set (&bigdisp
, 0);
10483 || i
.types
[this_operand
].bitfield
.baseindex
10484 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10485 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10487 i386_addressing_mode ();
10488 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10489 if (flag_code
== CODE_64BIT
)
10493 bigdisp
.bitfield
.disp32s
= 1;
10494 bigdisp
.bitfield
.disp64
= 1;
10497 bigdisp
.bitfield
.disp32
= 1;
10499 else if ((flag_code
== CODE_16BIT
) ^ override
)
10500 bigdisp
.bitfield
.disp16
= 1;
10502 bigdisp
.bitfield
.disp32
= 1;
10506 /* For PC-relative branches, the width of the displacement may be
10507 dependent upon data size, but is never dependent upon address size.
10508 Also make sure to not unintentionally match against a non-PC-relative
10509 branch template. */
10510 static templates aux_templates
;
10511 const insn_template
*t
= current_templates
->start
;
10512 bfd_boolean has_intel64
= FALSE
;
10514 aux_templates
.start
= t
;
10515 while (++t
< current_templates
->end
)
10517 if (t
->opcode_modifier
.jump
10518 != current_templates
->start
->opcode_modifier
.jump
)
10520 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10521 has_intel64
= TRUE
;
10523 if (t
< current_templates
->end
)
10525 aux_templates
.end
= t
;
10526 current_templates
= &aux_templates
;
10529 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10530 if (flag_code
== CODE_64BIT
)
10532 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10533 && (!intel64
|| !has_intel64
))
10534 bigdisp
.bitfield
.disp16
= 1;
10536 bigdisp
.bitfield
.disp32s
= 1;
10541 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10543 : LONG_MNEM_SUFFIX
));
10544 bigdisp
.bitfield
.disp32
= 1;
10545 if ((flag_code
== CODE_16BIT
) ^ override
)
10547 bigdisp
.bitfield
.disp32
= 0;
10548 bigdisp
.bitfield
.disp16
= 1;
10552 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10555 exp
= &disp_expressions
[i
.disp_operands
];
10556 i
.op
[this_operand
].disps
= exp
;
10558 save_input_line_pointer
= input_line_pointer
;
10559 input_line_pointer
= disp_start
;
10560 END_STRING_AND_SAVE (disp_end
);
10562 #ifndef GCC_ASM_O_HACK
10563 #define GCC_ASM_O_HACK 0
10566 END_STRING_AND_SAVE (disp_end
+ 1);
10567 if (i
.types
[this_operand
].bitfield
.baseIndex
10568 && displacement_string_end
[-1] == '+')
10570 /* This hack is to avoid a warning when using the "o"
10571 constraint within gcc asm statements.
10574 #define _set_tssldt_desc(n,addr,limit,type) \
10575 __asm__ __volatile__ ( \
10576 "movw %w2,%0\n\t" \
10577 "movw %w1,2+%0\n\t" \
10578 "rorl $16,%1\n\t" \
10579 "movb %b1,4+%0\n\t" \
10580 "movb %4,5+%0\n\t" \
10581 "movb $0,6+%0\n\t" \
10582 "movb %h1,7+%0\n\t" \
10584 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10586 This works great except that the output assembler ends
10587 up looking a bit weird if it turns out that there is
10588 no offset. You end up producing code that looks like:
10601 So here we provide the missing zero. */
10603 *displacement_string_end
= '0';
10606 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10607 if (gotfree_input_line
)
10608 input_line_pointer
= gotfree_input_line
;
10610 exp_seg
= expression (exp
);
10612 SKIP_WHITESPACE ();
10613 if (*input_line_pointer
)
10614 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10616 RESTORE_END_STRING (disp_end
+ 1);
10618 input_line_pointer
= save_input_line_pointer
;
10619 if (gotfree_input_line
)
10621 free (gotfree_input_line
);
10623 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10624 exp
->X_op
= O_illegal
;
10627 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10629 RESTORE_END_STRING (disp_end
);
10635 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10636 i386_operand_type types
, const char *disp_start
)
10638 i386_operand_type bigdisp
;
10641 /* We do this to make sure that the section symbol is in
10642 the symbol table. We will ultimately change the relocation
10643 to be relative to the beginning of the section. */
10644 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10645 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10646 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10648 if (exp
->X_op
!= O_symbol
)
10651 if (S_IS_LOCAL (exp
->X_add_symbol
)
10652 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10653 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10654 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10655 exp
->X_op
= O_subtract
;
10656 exp
->X_op_symbol
= GOT_symbol
;
10657 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10658 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10659 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10660 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10662 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10665 else if (exp
->X_op
== O_absent
10666 || exp
->X_op
== O_illegal
10667 || exp
->X_op
== O_big
)
10670 as_bad (_("missing or invalid displacement expression `%s'"),
10675 else if (flag_code
== CODE_64BIT
10676 && !i
.prefix
[ADDR_PREFIX
]
10677 && exp
->X_op
== O_constant
)
10679 /* Since displacement is signed extended to 64bit, don't allow
10680 disp32 and turn off disp32s if they are out of range. */
10681 i
.types
[this_operand
].bitfield
.disp32
= 0;
10682 if (!fits_in_signed_long (exp
->X_add_number
))
10684 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10685 if (i
.types
[this_operand
].bitfield
.baseindex
)
10687 as_bad (_("0x%lx out range of signed 32bit displacement"),
10688 (long) exp
->X_add_number
);
10694 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10695 else if (exp
->X_op
!= O_constant
10696 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10697 && exp_seg
!= absolute_section
10698 && exp_seg
!= text_section
10699 && exp_seg
!= data_section
10700 && exp_seg
!= bss_section
10701 && exp_seg
!= undefined_section
10702 && !bfd_is_com_section (exp_seg
))
10704 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10709 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10710 /* Constants get taken care of by optimize_disp(). */
10711 && exp
->X_op
!= O_constant
)
10712 i
.types
[this_operand
].bitfield
.disp8
= 1;
10714 /* Check if this is a displacement only operand. */
10715 bigdisp
= i
.types
[this_operand
];
10716 bigdisp
.bitfield
.disp8
= 0;
10717 bigdisp
.bitfield
.disp16
= 0;
10718 bigdisp
.bitfield
.disp32
= 0;
10719 bigdisp
.bitfield
.disp32s
= 0;
10720 bigdisp
.bitfield
.disp64
= 0;
10721 if (operand_type_all_zero (&bigdisp
))
10722 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10728 /* Return the active addressing mode, taking address override and
10729 registers forming the address into consideration. Update the
10730 address override prefix if necessary. */
10732 static enum flag_code
10733 i386_addressing_mode (void)
10735 enum flag_code addr_mode
;
10737 if (i
.prefix
[ADDR_PREFIX
])
10738 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10739 else if (flag_code
== CODE_16BIT
10740 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10741 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10742 from md_assemble() by "is not a valid base/index expression"
10743 when there is a base and/or index. */
10744 && !i
.types
[this_operand
].bitfield
.baseindex
)
10746 /* MPX insn memory operands with neither base nor index must be forced
10747 to use 32-bit addressing in 16-bit mode. */
10748 addr_mode
= CODE_32BIT
;
10749 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10751 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10752 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10756 addr_mode
= flag_code
;
10758 #if INFER_ADDR_PREFIX
10759 if (i
.mem_operands
== 0)
10761 /* Infer address prefix from the first memory operand. */
10762 const reg_entry
*addr_reg
= i
.base_reg
;
10764 if (addr_reg
== NULL
)
10765 addr_reg
= i
.index_reg
;
10769 if (addr_reg
->reg_type
.bitfield
.dword
)
10770 addr_mode
= CODE_32BIT
;
10771 else if (flag_code
!= CODE_64BIT
10772 && addr_reg
->reg_type
.bitfield
.word
)
10773 addr_mode
= CODE_16BIT
;
10775 if (addr_mode
!= flag_code
)
10777 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10779 /* Change the size of any displacement too. At most one
10780 of Disp16 or Disp32 is set.
10781 FIXME. There doesn't seem to be any real need for
10782 separate Disp16 and Disp32 flags. The same goes for
10783 Imm16 and Imm32. Removing them would probably clean
10784 up the code quite a lot. */
10785 if (flag_code
!= CODE_64BIT
10786 && (i
.types
[this_operand
].bitfield
.disp16
10787 || i
.types
[this_operand
].bitfield
.disp32
))
10788 i
.types
[this_operand
]
10789 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10799 /* Make sure the memory operand we've been dealt is valid.
10800 Return 1 on success, 0 on a failure. */
10803 i386_index_check (const char *operand_string
)
10805 const char *kind
= "base/index";
10806 enum flag_code addr_mode
= i386_addressing_mode ();
10808 if (current_templates
->start
->opcode_modifier
.isstring
10809 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10810 && (current_templates
->end
[-1].opcode_modifier
.isstring
10811 || i
.mem_operands
))
10813 /* Memory operands of string insns are special in that they only allow
10814 a single register (rDI, rSI, or rBX) as their memory address. */
10815 const reg_entry
*expected_reg
;
10816 static const char *di_si
[][2] =
10822 static const char *bx
[] = { "ebx", "bx", "rbx" };
10824 kind
= "string address";
10826 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10828 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10829 - IS_STRING_ES_OP0
;
10832 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10833 || ((!i
.mem_operands
!= !intel_syntax
)
10834 && current_templates
->end
[-1].operand_types
[1]
10835 .bitfield
.baseindex
))
10837 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10840 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10842 if (i
.base_reg
!= expected_reg
10844 || operand_type_check (i
.types
[this_operand
], disp
))
10846 /* The second memory operand must have the same size as
10850 && !((addr_mode
== CODE_64BIT
10851 && i
.base_reg
->reg_type
.bitfield
.qword
)
10852 || (addr_mode
== CODE_32BIT
10853 ? i
.base_reg
->reg_type
.bitfield
.dword
10854 : i
.base_reg
->reg_type
.bitfield
.word
)))
10857 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10859 intel_syntax
? '[' : '(',
10861 expected_reg
->reg_name
,
10862 intel_syntax
? ']' : ')');
10869 as_bad (_("`%s' is not a valid %s expression"),
10870 operand_string
, kind
);
10875 if (addr_mode
!= CODE_16BIT
)
10877 /* 32-bit/64-bit checks. */
10879 && ((addr_mode
== CODE_64BIT
10880 ? !i
.base_reg
->reg_type
.bitfield
.qword
10881 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10882 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10883 || i
.base_reg
->reg_num
== RegIZ
))
10885 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10886 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10887 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10888 && ((addr_mode
== CODE_64BIT
10889 ? !i
.index_reg
->reg_type
.bitfield
.qword
10890 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10891 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10894 /* bndmk, bndldx, and bndstx have special restrictions. */
10895 if (current_templates
->start
->base_opcode
== 0xf30f1b
10896 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10898 /* They cannot use RIP-relative addressing. */
10899 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10901 as_bad (_("`%s' cannot be used here"), operand_string
);
10905 /* bndldx and bndstx ignore their scale factor. */
10906 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10907 && i
.log2_scale_factor
)
10908 as_warn (_("register scaling is being ignored here"));
10913 /* 16-bit checks. */
10915 && (!i
.base_reg
->reg_type
.bitfield
.word
10916 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10918 && (!i
.index_reg
->reg_type
.bitfield
.word
10919 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10921 && i
.base_reg
->reg_num
< 6
10922 && i
.index_reg
->reg_num
>= 6
10923 && i
.log2_scale_factor
== 0))))
10930 /* Handle vector immediates. */
10933 RC_SAE_immediate (const char *imm_start
)
10935 unsigned int match_found
, j
;
10936 const char *pstr
= imm_start
;
10944 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10946 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10950 rc_op
.type
= RC_NamesTable
[j
].type
;
10951 rc_op
.operand
= this_operand
;
10952 i
.rounding
= &rc_op
;
10956 as_bad (_("duplicated `%s'"), imm_start
);
10959 pstr
+= RC_NamesTable
[j
].len
;
10967 if (*pstr
++ != '}')
10969 as_bad (_("Missing '}': '%s'"), imm_start
);
10972 /* RC/SAE immediate string should contain nothing more. */;
10975 as_bad (_("Junk after '}': '%s'"), imm_start
);
10979 exp
= &im_expressions
[i
.imm_operands
++];
10980 i
.op
[this_operand
].imms
= exp
;
10982 exp
->X_op
= O_constant
;
10983 exp
->X_add_number
= 0;
10984 exp
->X_add_symbol
= (symbolS
*) 0;
10985 exp
->X_op_symbol
= (symbolS
*) 0;
10987 i
.types
[this_operand
].bitfield
.imm8
= 1;
10991 /* Only string instructions can have a second memory operand, so
10992 reduce current_templates to just those if it contains any. */
10994 maybe_adjust_templates (void)
10996 const insn_template
*t
;
10998 gas_assert (i
.mem_operands
== 1);
11000 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11001 if (t
->opcode_modifier
.isstring
)
11004 if (t
< current_templates
->end
)
11006 static templates aux_templates
;
11007 bfd_boolean recheck
;
11009 aux_templates
.start
= t
;
11010 for (; t
< current_templates
->end
; ++t
)
11011 if (!t
->opcode_modifier
.isstring
)
11013 aux_templates
.end
= t
;
11015 /* Determine whether to re-check the first memory operand. */
11016 recheck
= (aux_templates
.start
!= current_templates
->start
11017 || t
!= current_templates
->end
);
11019 current_templates
= &aux_templates
;
11023 i
.mem_operands
= 0;
11024 if (i
.memop1_string
!= NULL
11025 && i386_index_check (i
.memop1_string
) == 0)
11027 i
.mem_operands
= 1;
11034 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11038 i386_att_operand (char *operand_string
)
11040 const reg_entry
*r
;
11042 char *op_string
= operand_string
;
11044 if (is_space_char (*op_string
))
11047 /* We check for an absolute prefix (differentiating,
11048 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11049 if (*op_string
== ABSOLUTE_PREFIX
)
11052 if (is_space_char (*op_string
))
11054 i
.jumpabsolute
= TRUE
;
11057 /* Check if operand is a register. */
11058 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11060 i386_operand_type temp
;
11065 /* Check for a segment override by searching for ':' after a
11066 segment register. */
11067 op_string
= end_op
;
11068 if (is_space_char (*op_string
))
11070 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11072 switch (r
->reg_num
)
11075 i
.seg
[i
.mem_operands
] = &es
;
11078 i
.seg
[i
.mem_operands
] = &cs
;
11081 i
.seg
[i
.mem_operands
] = &ss
;
11084 i
.seg
[i
.mem_operands
] = &ds
;
11087 i
.seg
[i
.mem_operands
] = &fs
;
11090 i
.seg
[i
.mem_operands
] = &gs
;
11094 /* Skip the ':' and whitespace. */
11096 if (is_space_char (*op_string
))
11099 if (!is_digit_char (*op_string
)
11100 && !is_identifier_char (*op_string
)
11101 && *op_string
!= '('
11102 && *op_string
!= ABSOLUTE_PREFIX
)
11104 as_bad (_("bad memory operand `%s'"), op_string
);
11107 /* Handle case of %es:*foo. */
11108 if (*op_string
== ABSOLUTE_PREFIX
)
11111 if (is_space_char (*op_string
))
11113 i
.jumpabsolute
= TRUE
;
11115 goto do_memory_reference
;
11118 /* Handle vector operations. */
11119 if (*op_string
== '{')
11121 op_string
= check_VecOperations (op_string
, NULL
);
11122 if (op_string
== NULL
)
11128 as_bad (_("junk `%s' after register"), op_string
);
11131 temp
= r
->reg_type
;
11132 temp
.bitfield
.baseindex
= 0;
11133 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11135 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11136 i
.op
[this_operand
].regs
= r
;
11139 else if (*op_string
== REGISTER_PREFIX
)
11141 as_bad (_("bad register name `%s'"), op_string
);
11144 else if (*op_string
== IMMEDIATE_PREFIX
)
11147 if (i
.jumpabsolute
)
11149 as_bad (_("immediate operand illegal with absolute jump"));
11152 if (!i386_immediate (op_string
))
11155 else if (RC_SAE_immediate (operand_string
))
11157 /* If it is a RC or SAE immediate, do nothing. */
11160 else if (is_digit_char (*op_string
)
11161 || is_identifier_char (*op_string
)
11162 || *op_string
== '"'
11163 || *op_string
== '(')
11165 /* This is a memory reference of some sort. */
11168 /* Start and end of displacement string expression (if found). */
11169 char *displacement_string_start
;
11170 char *displacement_string_end
;
11173 do_memory_reference
:
11174 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11176 if ((i
.mem_operands
== 1
11177 && !current_templates
->start
->opcode_modifier
.isstring
)
11178 || i
.mem_operands
== 2)
11180 as_bad (_("too many memory references for `%s'"),
11181 current_templates
->start
->name
);
11185 /* Check for base index form. We detect the base index form by
11186 looking for an ')' at the end of the operand, searching
11187 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11189 base_string
= op_string
+ strlen (op_string
);
11191 /* Handle vector operations. */
11192 vop_start
= strchr (op_string
, '{');
11193 if (vop_start
&& vop_start
< base_string
)
11195 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11197 base_string
= vop_start
;
11201 if (is_space_char (*base_string
))
11204 /* If we only have a displacement, set-up for it to be parsed later. */
11205 displacement_string_start
= op_string
;
11206 displacement_string_end
= base_string
+ 1;
11208 if (*base_string
== ')')
11211 unsigned int parens_balanced
= 1;
11212 /* We've already checked that the number of left & right ()'s are
11213 equal, so this loop will not be infinite. */
11217 if (*base_string
== ')')
11219 if (*base_string
== '(')
11222 while (parens_balanced
);
11224 temp_string
= base_string
;
11226 /* Skip past '(' and whitespace. */
11228 if (is_space_char (*base_string
))
11231 if (*base_string
== ','
11232 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11235 displacement_string_end
= temp_string
;
11237 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11241 if (i
.base_reg
== &bad_reg
)
11243 base_string
= end_op
;
11244 if (is_space_char (*base_string
))
11248 /* There may be an index reg or scale factor here. */
11249 if (*base_string
== ',')
11252 if (is_space_char (*base_string
))
11255 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11258 if (i
.index_reg
== &bad_reg
)
11260 base_string
= end_op
;
11261 if (is_space_char (*base_string
))
11263 if (*base_string
== ',')
11266 if (is_space_char (*base_string
))
11269 else if (*base_string
!= ')')
11271 as_bad (_("expecting `,' or `)' "
11272 "after index register in `%s'"),
11277 else if (*base_string
== REGISTER_PREFIX
)
11279 end_op
= strchr (base_string
, ',');
11282 as_bad (_("bad register name `%s'"), base_string
);
11286 /* Check for scale factor. */
11287 if (*base_string
!= ')')
11289 char *end_scale
= i386_scale (base_string
);
11294 base_string
= end_scale
;
11295 if (is_space_char (*base_string
))
11297 if (*base_string
!= ')')
11299 as_bad (_("expecting `)' "
11300 "after scale factor in `%s'"),
11305 else if (!i
.index_reg
)
11307 as_bad (_("expecting index register or scale factor "
11308 "after `,'; got '%c'"),
11313 else if (*base_string
!= ')')
11315 as_bad (_("expecting `,' or `)' "
11316 "after base register in `%s'"),
11321 else if (*base_string
== REGISTER_PREFIX
)
11323 end_op
= strchr (base_string
, ',');
11326 as_bad (_("bad register name `%s'"), base_string
);
11331 /* If there's an expression beginning the operand, parse it,
11332 assuming displacement_string_start and
11333 displacement_string_end are meaningful. */
11334 if (displacement_string_start
!= displacement_string_end
)
11336 if (!i386_displacement (displacement_string_start
,
11337 displacement_string_end
))
11341 /* Special case for (%dx) while doing input/output op. */
11343 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11344 && i
.base_reg
->reg_type
.bitfield
.word
11345 && i
.index_reg
== 0
11346 && i
.log2_scale_factor
== 0
11347 && i
.seg
[i
.mem_operands
] == 0
11348 && !operand_type_check (i
.types
[this_operand
], disp
))
11350 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11354 if (i386_index_check (operand_string
) == 0)
11356 i
.flags
[this_operand
] |= Operand_Mem
;
11357 if (i
.mem_operands
== 0)
11358 i
.memop1_string
= xstrdup (operand_string
);
11363 /* It's not a memory operand; argh! */
11364 as_bad (_("invalid char %s beginning operand %d `%s'"),
11365 output_invalid (*op_string
),
11370 return 1; /* Normal return. */
11373 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11374 that an rs_machine_dependent frag may reach. */
11377 i386_frag_max_var (fragS
*frag
)
11379 /* The only relaxable frags are for jumps.
11380 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11381 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11382 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11387 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11389 /* STT_GNU_IFUNC symbol must go through PLT. */
11390 if ((symbol_get_bfdsym (fr_symbol
)->flags
11391 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11394 if (!S_IS_EXTERNAL (fr_symbol
))
11395 /* Symbol may be weak or local. */
11396 return !S_IS_WEAK (fr_symbol
);
11398 /* Global symbols with non-default visibility can't be preempted. */
11399 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11402 if (fr_var
!= NO_RELOC
)
11403 switch ((enum bfd_reloc_code_real
) fr_var
)
11405 case BFD_RELOC_386_PLT32
:
11406 case BFD_RELOC_X86_64_PLT32
:
11407 /* Symbol with PLT relocation may be preempted. */
11413 /* Global symbols with default visibility in a shared library may be
11414 preempted by another definition. */
11419 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11420 Note also work for Skylake and Cascadelake.
11421 ---------------------------------------------------------------------
11422 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11423 | ------ | ----------- | ------- | -------- |
11425 | Jno | N | N | Y |
11426 | Jc/Jb | Y | N | Y |
11427 | Jae/Jnb | Y | N | Y |
11428 | Je/Jz | Y | Y | Y |
11429 | Jne/Jnz | Y | Y | Y |
11430 | Jna/Jbe | Y | N | Y |
11431 | Ja/Jnbe | Y | N | Y |
11433 | Jns | N | N | Y |
11434 | Jp/Jpe | N | N | Y |
11435 | Jnp/Jpo | N | N | Y |
11436 | Jl/Jnge | Y | Y | Y |
11437 | Jge/Jnl | Y | Y | Y |
11438 | Jle/Jng | Y | Y | Y |
11439 | Jg/Jnle | Y | Y | Y |
11440 --------------------------------------------------------------------- */
11442 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11444 if (mf_cmp
== mf_cmp_alu_cmp
)
11445 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11446 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11447 if (mf_cmp
== mf_cmp_incdec
)
11448 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11449 || mf_jcc
== mf_jcc_jle
);
11450 if (mf_cmp
== mf_cmp_test_and
)
11455 /* Return the next non-empty frag. */
11458 i386_next_non_empty_frag (fragS
*fragP
)
11460 /* There may be a frag with a ".fill 0" when there is no room in
11461 the current frag for frag_grow in output_insn. */
11462 for (fragP
= fragP
->fr_next
;
11464 && fragP
->fr_type
== rs_fill
11465 && fragP
->fr_fix
== 0);
11466 fragP
= fragP
->fr_next
)
11471 /* Return the next jcc frag after BRANCH_PADDING. */
11474 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11476 fragS
*branch_fragP
;
11480 if (pad_fragP
->fr_type
== rs_machine_dependent
11481 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11482 == BRANCH_PADDING
))
11484 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11485 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11487 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11488 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11489 pad_fragP
->tc_frag_data
.mf_type
))
11490 return branch_fragP
;
11496 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11499 i386_classify_machine_dependent_frag (fragS
*fragP
)
11503 fragS
*branch_fragP
;
11505 unsigned int max_prefix_length
;
11507 if (fragP
->tc_frag_data
.classified
)
11510 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11511 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11512 for (next_fragP
= fragP
;
11513 next_fragP
!= NULL
;
11514 next_fragP
= next_fragP
->fr_next
)
11516 next_fragP
->tc_frag_data
.classified
= 1;
11517 if (next_fragP
->fr_type
== rs_machine_dependent
)
11518 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11520 case BRANCH_PADDING
:
11521 /* The BRANCH_PADDING frag must be followed by a branch
11523 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11524 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11526 case FUSED_JCC_PADDING
:
11527 /* Check if this is a fused jcc:
11529 CMP like instruction
11533 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11534 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11535 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11538 /* The BRANCH_PADDING frag is merged with the
11539 FUSED_JCC_PADDING frag. */
11540 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11541 /* CMP like instruction size. */
11542 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11543 frag_wane (pad_fragP
);
11544 /* Skip to branch_fragP. */
11545 next_fragP
= branch_fragP
;
11547 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11549 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11551 next_fragP
->fr_subtype
11552 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11553 next_fragP
->tc_frag_data
.max_bytes
11554 = next_fragP
->tc_frag_data
.max_prefix_length
;
11555 /* This will be updated in the BRANCH_PREFIX scan. */
11556 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11559 frag_wane (next_fragP
);
11564 /* Stop if there is no BRANCH_PREFIX. */
11565 if (!align_branch_prefix_size
)
11568 /* Scan for BRANCH_PREFIX. */
11569 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11571 if (fragP
->fr_type
!= rs_machine_dependent
11572 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11576 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11577 COND_JUMP_PREFIX. */
11578 max_prefix_length
= 0;
11579 for (next_fragP
= fragP
;
11580 next_fragP
!= NULL
;
11581 next_fragP
= next_fragP
->fr_next
)
11583 if (next_fragP
->fr_type
== rs_fill
)
11584 /* Skip rs_fill frags. */
11586 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11587 /* Stop for all other frags. */
11590 /* rs_machine_dependent frags. */
11591 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11594 /* Count BRANCH_PREFIX frags. */
11595 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11597 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11598 frag_wane (next_fragP
);
11602 += next_fragP
->tc_frag_data
.max_bytes
;
11604 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11606 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11607 == FUSED_JCC_PADDING
))
11609 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11610 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11614 /* Stop for other rs_machine_dependent frags. */
11618 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11620 /* Skip to the next frag. */
11621 fragP
= next_fragP
;
11625 /* Compute padding size for
11628 CMP like instruction
11630 COND_JUMP/UNCOND_JUMP
11635 COND_JUMP/UNCOND_JUMP
11639 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11641 unsigned int offset
, size
, padding_size
;
11642 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11644 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11646 address
= fragP
->fr_address
;
11647 address
+= fragP
->fr_fix
;
11649 /* CMP like instrunction size. */
11650 size
= fragP
->tc_frag_data
.cmp_size
;
11652 /* The base size of the branch frag. */
11653 size
+= branch_fragP
->fr_fix
;
11655 /* Add opcode and displacement bytes for the rs_machine_dependent
11657 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11658 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11660 /* Check if branch is within boundary and doesn't end at the last
11662 offset
= address
& ((1U << align_branch_power
) - 1);
11663 if ((offset
+ size
) >= (1U << align_branch_power
))
11664 /* Padding needed to avoid crossing boundary. */
11665 padding_size
= (1U << align_branch_power
) - offset
;
11667 /* No padding needed. */
11670 /* The return value may be saved in tc_frag_data.length which is
11672 if (!fits_in_unsigned_byte (padding_size
))
11675 return padding_size
;
11678 /* i386_generic_table_relax_frag()
11680 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11681 grow/shrink padding to align branch frags. Hand others to
11685 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11687 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11688 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11690 long padding_size
= i386_branch_padding_size (fragP
, 0);
11691 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11693 /* When the BRANCH_PREFIX frag is used, the computed address
11694 must match the actual address and there should be no padding. */
11695 if (fragP
->tc_frag_data
.padding_address
11696 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11700 /* Update the padding size. */
11702 fragP
->tc_frag_data
.length
= padding_size
;
11706 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11708 fragS
*padding_fragP
, *next_fragP
;
11709 long padding_size
, left_size
, last_size
;
11711 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11712 if (!padding_fragP
)
11713 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11714 return (fragP
->tc_frag_data
.length
11715 - fragP
->tc_frag_data
.last_length
);
11717 /* Compute the relative address of the padding frag in the very
11718 first time where the BRANCH_PREFIX frag sizes are zero. */
11719 if (!fragP
->tc_frag_data
.padding_address
)
11720 fragP
->tc_frag_data
.padding_address
11721 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11723 /* First update the last length from the previous interation. */
11724 left_size
= fragP
->tc_frag_data
.prefix_length
;
11725 for (next_fragP
= fragP
;
11726 next_fragP
!= padding_fragP
;
11727 next_fragP
= next_fragP
->fr_next
)
11728 if (next_fragP
->fr_type
== rs_machine_dependent
11729 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11734 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11738 if (max
> left_size
)
11743 next_fragP
->tc_frag_data
.last_length
= size
;
11747 next_fragP
->tc_frag_data
.last_length
= 0;
11750 /* Check the padding size for the padding frag. */
11751 padding_size
= i386_branch_padding_size
11752 (padding_fragP
, (fragP
->fr_address
11753 + fragP
->tc_frag_data
.padding_address
));
11755 last_size
= fragP
->tc_frag_data
.prefix_length
;
11756 /* Check if there is change from the last interation. */
11757 if (padding_size
== last_size
)
11759 /* Update the expected address of the padding frag. */
11760 padding_fragP
->tc_frag_data
.padding_address
11761 = (fragP
->fr_address
+ padding_size
11762 + fragP
->tc_frag_data
.padding_address
);
11766 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11768 /* No padding if there is no sufficient room. Clear the
11769 expected address of the padding frag. */
11770 padding_fragP
->tc_frag_data
.padding_address
= 0;
11774 /* Store the expected address of the padding frag. */
11775 padding_fragP
->tc_frag_data
.padding_address
11776 = (fragP
->fr_address
+ padding_size
11777 + fragP
->tc_frag_data
.padding_address
);
11779 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11781 /* Update the length for the current interation. */
11782 left_size
= padding_size
;
11783 for (next_fragP
= fragP
;
11784 next_fragP
!= padding_fragP
;
11785 next_fragP
= next_fragP
->fr_next
)
11786 if (next_fragP
->fr_type
== rs_machine_dependent
11787 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11792 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11796 if (max
> left_size
)
11801 next_fragP
->tc_frag_data
.length
= size
;
11805 next_fragP
->tc_frag_data
.length
= 0;
11808 return (fragP
->tc_frag_data
.length
11809 - fragP
->tc_frag_data
.last_length
);
11811 return relax_frag (segment
, fragP
, stretch
);
11814 /* md_estimate_size_before_relax()
11816 Called just before relax() for rs_machine_dependent frags. The x86
11817 assembler uses these frags to handle variable size jump
11820 Any symbol that is now undefined will not become defined.
11821 Return the correct fr_subtype in the frag.
11822 Return the initial "guess for variable size of frag" to caller.
11823 The guess is actually the growth beyond the fixed part. Whatever
11824 we do to grow the fixed or variable part contributes to our
11828 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11830 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11831 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11832 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11834 i386_classify_machine_dependent_frag (fragP
);
11835 return fragP
->tc_frag_data
.length
;
11838 /* We've already got fragP->fr_subtype right; all we have to do is
11839 check for un-relaxable symbols. On an ELF system, we can't relax
11840 an externally visible symbol, because it may be overridden by a
11842 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11843 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11845 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11848 #if defined (OBJ_COFF) && defined (TE_PE)
11849 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11850 && S_IS_WEAK (fragP
->fr_symbol
))
11854 /* Symbol is undefined in this segment, or we need to keep a
11855 reloc so that weak symbols can be overridden. */
11856 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11857 enum bfd_reloc_code_real reloc_type
;
11858 unsigned char *opcode
;
11861 if (fragP
->fr_var
!= NO_RELOC
)
11862 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11863 else if (size
== 2)
11864 reloc_type
= BFD_RELOC_16_PCREL
;
11865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11866 else if (need_plt32_p (fragP
->fr_symbol
))
11867 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11870 reloc_type
= BFD_RELOC_32_PCREL
;
11872 old_fr_fix
= fragP
->fr_fix
;
11873 opcode
= (unsigned char *) fragP
->fr_opcode
;
11875 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11878 /* Make jmp (0xeb) a (d)word displacement jump. */
11880 fragP
->fr_fix
+= size
;
11881 fix_new (fragP
, old_fr_fix
, size
,
11883 fragP
->fr_offset
, 1,
11889 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11891 /* Negate the condition, and branch past an
11892 unconditional jump. */
11895 /* Insert an unconditional jump. */
11897 /* We added two extra opcode bytes, and have a two byte
11899 fragP
->fr_fix
+= 2 + 2;
11900 fix_new (fragP
, old_fr_fix
+ 2, 2,
11902 fragP
->fr_offset
, 1,
11906 /* Fall through. */
11909 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11913 fragP
->fr_fix
+= 1;
11914 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11916 fragP
->fr_offset
, 1,
11917 BFD_RELOC_8_PCREL
);
11918 fixP
->fx_signed
= 1;
11922 /* This changes the byte-displacement jump 0x7N
11923 to the (d)word-displacement jump 0x0f,0x8N. */
11924 opcode
[1] = opcode
[0] + 0x10;
11925 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11926 /* We've added an opcode byte. */
11927 fragP
->fr_fix
+= 1 + size
;
11928 fix_new (fragP
, old_fr_fix
+ 1, size
,
11930 fragP
->fr_offset
, 1,
11935 BAD_CASE (fragP
->fr_subtype
);
11939 return fragP
->fr_fix
- old_fr_fix
;
11942 /* Guess size depending on current relax state. Initially the relax
11943 state will correspond to a short jump and we return 1, because
11944 the variable part of the frag (the branch offset) is one byte
11945 long. However, we can relax a section more than once and in that
11946 case we must either set fr_subtype back to the unrelaxed state,
11947 or return the value for the appropriate branch. */
11948 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11951 /* Called after relax() is finished.
11953 In: Address of frag.
11954 fr_type == rs_machine_dependent.
11955 fr_subtype is what the address relaxed to.
11957 Out: Any fixSs and constants are set up.
11958 Caller will turn frag into a ".space 0". */
11961 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11964 unsigned char *opcode
;
11965 unsigned char *where_to_put_displacement
= NULL
;
11966 offsetT target_address
;
11967 offsetT opcode_address
;
11968 unsigned int extension
= 0;
11969 offsetT displacement_from_opcode_start
;
11971 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11972 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11973 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11975 /* Generate nop padding. */
11976 unsigned int size
= fragP
->tc_frag_data
.length
;
11979 if (size
> fragP
->tc_frag_data
.max_bytes
)
11985 const char *branch
= "branch";
11986 const char *prefix
= "";
11987 fragS
*padding_fragP
;
11988 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11991 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11992 switch (fragP
->tc_frag_data
.default_prefix
)
11997 case CS_PREFIX_OPCODE
:
12000 case DS_PREFIX_OPCODE
:
12003 case ES_PREFIX_OPCODE
:
12006 case FS_PREFIX_OPCODE
:
12009 case GS_PREFIX_OPCODE
:
12012 case SS_PREFIX_OPCODE
:
12017 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12018 "%s within %d-byte boundary\n");
12020 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12021 "align %s within %d-byte boundary\n");
12025 padding_fragP
= fragP
;
12026 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12027 "%s within %d-byte boundary\n");
12031 switch (padding_fragP
->tc_frag_data
.branch_type
)
12033 case align_branch_jcc
:
12036 case align_branch_fused
:
12037 branch
= "fused jcc";
12039 case align_branch_jmp
:
12042 case align_branch_call
:
12045 case align_branch_indirect
:
12046 branch
= "indiret branch";
12048 case align_branch_ret
:
12055 fprintf (stdout
, msg
,
12056 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12057 (long long) fragP
->fr_address
, branch
,
12058 1 << align_branch_power
);
12060 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12061 memset (fragP
->fr_opcode
,
12062 fragP
->tc_frag_data
.default_prefix
, size
);
12064 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12066 fragP
->fr_fix
+= size
;
12071 opcode
= (unsigned char *) fragP
->fr_opcode
;
12073 /* Address we want to reach in file space. */
12074 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12076 /* Address opcode resides at in file space. */
12077 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12079 /* Displacement from opcode start to fill into instruction. */
12080 displacement_from_opcode_start
= target_address
- opcode_address
;
12082 if ((fragP
->fr_subtype
& BIG
) == 0)
12084 /* Don't have to change opcode. */
12085 extension
= 1; /* 1 opcode + 1 displacement */
12086 where_to_put_displacement
= &opcode
[1];
12090 if (no_cond_jump_promotion
12091 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12092 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12093 _("long jump required"));
12095 switch (fragP
->fr_subtype
)
12097 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12098 extension
= 4; /* 1 opcode + 4 displacement */
12100 where_to_put_displacement
= &opcode
[1];
12103 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12104 extension
= 2; /* 1 opcode + 2 displacement */
12106 where_to_put_displacement
= &opcode
[1];
12109 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12110 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12111 extension
= 5; /* 2 opcode + 4 displacement */
12112 opcode
[1] = opcode
[0] + 0x10;
12113 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12114 where_to_put_displacement
= &opcode
[2];
12117 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12118 extension
= 3; /* 2 opcode + 2 displacement */
12119 opcode
[1] = opcode
[0] + 0x10;
12120 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12121 where_to_put_displacement
= &opcode
[2];
12124 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12129 where_to_put_displacement
= &opcode
[3];
12133 BAD_CASE (fragP
->fr_subtype
);
12138 /* If size if less then four we are sure that the operand fits,
12139 but if it's 4, then it could be that the displacement is larger
12141 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12143 && ((addressT
) (displacement_from_opcode_start
- extension
12144 + ((addressT
) 1 << 31))
12145 > (((addressT
) 2 << 31) - 1)))
12147 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12148 _("jump target out of range"));
12149 /* Make us emit 0. */
12150 displacement_from_opcode_start
= extension
;
12152 /* Now put displacement after opcode. */
12153 md_number_to_chars ((char *) where_to_put_displacement
,
12154 (valueT
) (displacement_from_opcode_start
- extension
),
12155 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12156 fragP
->fr_fix
+= extension
;
12159 /* Apply a fixup (fixP) to segment data, once it has been determined
12160 by our caller that we have all the info we need to fix it up.
12162 Parameter valP is the pointer to the value of the bits.
12164 On the 386, immediates, displacements, and data pointers are all in
12165 the same (little-endian) format, so we don't need to care about which
12166 we are handling. */
12169 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12171 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12172 valueT value
= *valP
;
12174 #if !defined (TE_Mach)
12175 if (fixP
->fx_pcrel
)
12177 switch (fixP
->fx_r_type
)
12183 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12186 case BFD_RELOC_X86_64_32S
:
12187 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12190 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12193 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12198 if (fixP
->fx_addsy
!= NULL
12199 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12200 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12201 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12202 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12203 && !use_rela_relocations
)
12205 /* This is a hack. There should be a better way to handle this.
12206 This covers for the fact that bfd_install_relocation will
12207 subtract the current location (for partial_inplace, PC relative
12208 relocations); see more below. */
12212 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12215 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12220 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12222 if ((sym_seg
== seg
12223 || (symbol_section_p (fixP
->fx_addsy
)
12224 && sym_seg
!= absolute_section
))
12225 && !generic_force_reloc (fixP
))
12227 /* Yes, we add the values in twice. This is because
12228 bfd_install_relocation subtracts them out again. I think
12229 bfd_install_relocation is broken, but I don't dare change
12231 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12235 #if defined (OBJ_COFF) && defined (TE_PE)
12236 /* For some reason, the PE format does not store a
12237 section address offset for a PC relative symbol. */
12238 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12239 || S_IS_WEAK (fixP
->fx_addsy
))
12240 value
+= md_pcrel_from (fixP
);
12243 #if defined (OBJ_COFF) && defined (TE_PE)
12244 if (fixP
->fx_addsy
!= NULL
12245 && S_IS_WEAK (fixP
->fx_addsy
)
12246 /* PR 16858: Do not modify weak function references. */
12247 && ! fixP
->fx_pcrel
)
12249 #if !defined (TE_PEP)
12250 /* For x86 PE weak function symbols are neither PC-relative
12251 nor do they set S_IS_FUNCTION. So the only reliable way
12252 to detect them is to check the flags of their containing
12254 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12255 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12259 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12263 /* Fix a few things - the dynamic linker expects certain values here,
12264 and we must not disappoint it. */
12265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12266 if (IS_ELF
&& fixP
->fx_addsy
)
12267 switch (fixP
->fx_r_type
)
12269 case BFD_RELOC_386_PLT32
:
12270 case BFD_RELOC_X86_64_PLT32
:
12271 /* Make the jump instruction point to the address of the operand.
12272 At runtime we merely add the offset to the actual PLT entry.
12273 NB: Subtract the offset size only for jump instructions. */
12274 if (fixP
->fx_pcrel
)
12278 case BFD_RELOC_386_TLS_GD
:
12279 case BFD_RELOC_386_TLS_LDM
:
12280 case BFD_RELOC_386_TLS_IE_32
:
12281 case BFD_RELOC_386_TLS_IE
:
12282 case BFD_RELOC_386_TLS_GOTIE
:
12283 case BFD_RELOC_386_TLS_GOTDESC
:
12284 case BFD_RELOC_X86_64_TLSGD
:
12285 case BFD_RELOC_X86_64_TLSLD
:
12286 case BFD_RELOC_X86_64_GOTTPOFF
:
12287 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12288 value
= 0; /* Fully resolved at runtime. No addend. */
12290 case BFD_RELOC_386_TLS_LE
:
12291 case BFD_RELOC_386_TLS_LDO_32
:
12292 case BFD_RELOC_386_TLS_LE_32
:
12293 case BFD_RELOC_X86_64_DTPOFF32
:
12294 case BFD_RELOC_X86_64_DTPOFF64
:
12295 case BFD_RELOC_X86_64_TPOFF32
:
12296 case BFD_RELOC_X86_64_TPOFF64
:
12297 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12300 case BFD_RELOC_386_TLS_DESC_CALL
:
12301 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12302 value
= 0; /* Fully resolved at runtime. No addend. */
12303 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12307 case BFD_RELOC_VTABLE_INHERIT
:
12308 case BFD_RELOC_VTABLE_ENTRY
:
12315 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12317 #endif /* !defined (TE_Mach) */
12319 /* Are we finished with this relocation now? */
12320 if (fixP
->fx_addsy
== NULL
)
12322 #if defined (OBJ_COFF) && defined (TE_PE)
12323 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12326 /* Remember value for tc_gen_reloc. */
12327 fixP
->fx_addnumber
= value
;
12328 /* Clear out the frag for now. */
12332 else if (use_rela_relocations
)
12334 fixP
->fx_no_overflow
= 1;
12335 /* Remember value for tc_gen_reloc. */
12336 fixP
->fx_addnumber
= value
;
12340 md_number_to_chars (p
, value
, fixP
->fx_size
);
12344 md_atof (int type
, char *litP
, int *sizeP
)
12346 /* This outputs the LITTLENUMs in REVERSE order;
12347 in accord with the bigendian 386. */
12348 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12351 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12354 output_invalid (int c
)
12357 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12360 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12361 "(0x%x)", (unsigned char) c
);
12362 return output_invalid_buf
;
12365 /* Verify that @r can be used in the current context. */
12367 static bfd_boolean
check_register (const reg_entry
*r
)
12369 if (allow_pseudo_reg
)
12372 if (operand_type_all_zero (&r
->reg_type
))
12375 if ((r
->reg_type
.bitfield
.dword
12376 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12377 || r
->reg_type
.bitfield
.class == RegCR
12378 || r
->reg_type
.bitfield
.class == RegDR
)
12379 && !cpu_arch_flags
.bitfield
.cpui386
)
12382 if (r
->reg_type
.bitfield
.class == RegTR
12383 && (flag_code
== CODE_64BIT
12384 || !cpu_arch_flags
.bitfield
.cpui386
12385 || cpu_arch_isa_flags
.bitfield
.cpui586
12386 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12389 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12392 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12394 if (r
->reg_type
.bitfield
.zmmword
12395 || r
->reg_type
.bitfield
.class == RegMask
)
12398 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12400 if (r
->reg_type
.bitfield
.ymmword
)
12403 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12408 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12411 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12412 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12415 /* Upper 16 vector registers are only available with VREX in 64bit
12416 mode, and require EVEX encoding. */
12417 if (r
->reg_flags
& RegVRex
)
12419 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12420 || flag_code
!= CODE_64BIT
)
12423 if (i
.vec_encoding
== vex_encoding_default
)
12424 i
.vec_encoding
= vex_encoding_evex
;
12425 else if (i
.vec_encoding
!= vex_encoding_evex
)
12426 i
.vec_encoding
= vex_encoding_error
;
12429 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12430 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12431 && flag_code
!= CODE_64BIT
)
12434 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12441 /* REG_STRING starts *before* REGISTER_PREFIX. */
12443 static const reg_entry
*
12444 parse_real_register (char *reg_string
, char **end_op
)
12446 char *s
= reg_string
;
12448 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12449 const reg_entry
*r
;
12451 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12452 if (*s
== REGISTER_PREFIX
)
12455 if (is_space_char (*s
))
12458 p
= reg_name_given
;
12459 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12461 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12462 return (const reg_entry
*) NULL
;
12466 /* For naked regs, make sure that we are not dealing with an identifier.
12467 This prevents confusing an identifier like `eax_var' with register
12469 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12470 return (const reg_entry
*) NULL
;
12474 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12476 /* Handle floating point regs, allowing spaces in the (i) part. */
12477 if (r
== i386_regtab
/* %st is first entry of table */)
12479 if (!cpu_arch_flags
.bitfield
.cpu8087
12480 && !cpu_arch_flags
.bitfield
.cpu287
12481 && !cpu_arch_flags
.bitfield
.cpu387
12482 && !allow_pseudo_reg
)
12483 return (const reg_entry
*) NULL
;
12485 if (is_space_char (*s
))
12490 if (is_space_char (*s
))
12492 if (*s
>= '0' && *s
<= '7')
12494 int fpr
= *s
- '0';
12496 if (is_space_char (*s
))
12501 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12506 /* We have "%st(" then garbage. */
12507 return (const reg_entry
*) NULL
;
12511 return r
&& check_register (r
) ? r
: NULL
;
12514 /* REG_STRING starts *before* REGISTER_PREFIX. */
12516 static const reg_entry
*
12517 parse_register (char *reg_string
, char **end_op
)
12519 const reg_entry
*r
;
12521 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12522 r
= parse_real_register (reg_string
, end_op
);
12527 char *save
= input_line_pointer
;
12531 input_line_pointer
= reg_string
;
12532 c
= get_symbol_name (®_string
);
12533 symbolP
= symbol_find (reg_string
);
12534 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12536 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12538 know (e
->X_op
== O_register
);
12539 know (e
->X_add_number
>= 0
12540 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12541 r
= i386_regtab
+ e
->X_add_number
;
12542 if (!check_register (r
))
12544 as_bad (_("register '%s%s' cannot be used here"),
12545 register_prefix
, r
->reg_name
);
12548 *end_op
= input_line_pointer
;
12550 *input_line_pointer
= c
;
12551 input_line_pointer
= save
;
12557 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12559 const reg_entry
*r
;
12560 char *end
= input_line_pointer
;
12563 r
= parse_register (name
, &input_line_pointer
);
12564 if (r
&& end
<= input_line_pointer
)
12566 *nextcharP
= *input_line_pointer
;
12567 *input_line_pointer
= 0;
12570 e
->X_op
= O_register
;
12571 e
->X_add_number
= r
- i386_regtab
;
12574 e
->X_op
= O_illegal
;
12577 input_line_pointer
= end
;
12579 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12583 md_operand (expressionS
*e
)
12586 const reg_entry
*r
;
12588 switch (*input_line_pointer
)
12590 case REGISTER_PREFIX
:
12591 r
= parse_real_register (input_line_pointer
, &end
);
12594 e
->X_op
= O_register
;
12595 e
->X_add_number
= r
- i386_regtab
;
12596 input_line_pointer
= end
;
12601 gas_assert (intel_syntax
);
12602 end
= input_line_pointer
++;
12604 if (*input_line_pointer
== ']')
12606 ++input_line_pointer
;
12607 e
->X_op_symbol
= make_expr_symbol (e
);
12608 e
->X_add_symbol
= NULL
;
12609 e
->X_add_number
= 0;
12614 e
->X_op
= O_absent
;
12615 input_line_pointer
= end
;
12622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12623 const char *md_shortopts
= "kVQ:sqnO::";
12625 const char *md_shortopts
= "qnO::";
12628 #define OPTION_32 (OPTION_MD_BASE + 0)
12629 #define OPTION_64 (OPTION_MD_BASE + 1)
12630 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12631 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12632 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12633 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12634 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12635 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12636 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12637 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12638 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12639 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12640 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12641 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12642 #define OPTION_X32 (OPTION_MD_BASE + 14)
12643 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12644 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12645 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12646 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12647 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12648 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12649 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12650 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12651 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12652 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12653 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12654 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12655 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12656 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12657 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12658 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12659 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12660 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12661 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12663 struct option md_longopts
[] =
12665 {"32", no_argument
, NULL
, OPTION_32
},
12666 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12667 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12668 {"64", no_argument
, NULL
, OPTION_64
},
12670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12671 {"x32", no_argument
, NULL
, OPTION_X32
},
12672 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12673 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12675 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12676 {"march", required_argument
, NULL
, OPTION_MARCH
},
12677 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12678 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12679 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12680 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12681 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12682 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12683 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12684 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12685 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12686 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12687 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12688 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12689 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12690 # if defined (TE_PE) || defined (TE_PEP)
12691 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12693 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12694 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12695 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12696 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12697 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12698 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12699 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12700 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12701 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12702 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12703 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12704 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12705 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12706 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12707 {NULL
, no_argument
, NULL
, 0}
12709 size_t md_longopts_size
= sizeof (md_longopts
);
12712 md_parse_option (int c
, const char *arg
)
12715 char *arch
, *next
, *saved
, *type
;
12720 optimize_align_code
= 0;
12724 quiet_warnings
= 1;
12727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12728 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12729 should be emitted or not. FIXME: Not implemented. */
12731 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12735 /* -V: SVR4 argument to print version ID. */
12737 print_version_id ();
12740 /* -k: Ignore for FreeBSD compatibility. */
12745 /* -s: On i386 Solaris, this tells the native assembler to use
12746 .stab instead of .stab.excl. We always use .stab anyhow. */
12749 case OPTION_MSHARED
:
12753 case OPTION_X86_USED_NOTE
:
12754 if (strcasecmp (arg
, "yes") == 0)
12756 else if (strcasecmp (arg
, "no") == 0)
12759 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12764 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12765 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12768 const char **list
, **l
;
12770 list
= bfd_target_list ();
12771 for (l
= list
; *l
!= NULL
; l
++)
12772 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12773 || strcmp (*l
, "coff-x86-64") == 0
12774 || strcmp (*l
, "pe-x86-64") == 0
12775 || strcmp (*l
, "pei-x86-64") == 0
12776 || strcmp (*l
, "mach-o-x86-64") == 0)
12778 default_arch
= "x86_64";
12782 as_fatal (_("no compiled in support for x86_64"));
12788 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12792 const char **list
, **l
;
12794 list
= bfd_target_list ();
12795 for (l
= list
; *l
!= NULL
; l
++)
12796 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12798 default_arch
= "x86_64:32";
12802 as_fatal (_("no compiled in support for 32bit x86_64"));
12806 as_fatal (_("32bit x86_64 is only supported for ELF"));
12811 default_arch
= "i386";
12814 case OPTION_DIVIDE
:
12815 #ifdef SVR4_COMMENT_CHARS
12820 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12822 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12826 i386_comment_chars
= n
;
12832 saved
= xstrdup (arg
);
12834 /* Allow -march=+nosse. */
12840 as_fatal (_("invalid -march= option: `%s'"), arg
);
12841 next
= strchr (arch
, '+');
12844 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12846 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12849 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12852 cpu_arch_name
= cpu_arch
[j
].name
;
12853 cpu_sub_arch_name
= NULL
;
12854 cpu_arch_flags
= cpu_arch
[j
].flags
;
12855 cpu_arch_isa
= cpu_arch
[j
].type
;
12856 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12857 if (!cpu_arch_tune_set
)
12859 cpu_arch_tune
= cpu_arch_isa
;
12860 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12864 else if (*cpu_arch
[j
].name
== '.'
12865 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12867 /* ISA extension. */
12868 i386_cpu_flags flags
;
12870 flags
= cpu_flags_or (cpu_arch_flags
,
12871 cpu_arch
[j
].flags
);
12873 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12875 if (cpu_sub_arch_name
)
12877 char *name
= cpu_sub_arch_name
;
12878 cpu_sub_arch_name
= concat (name
,
12880 (const char *) NULL
);
12884 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12885 cpu_arch_flags
= flags
;
12886 cpu_arch_isa_flags
= flags
;
12890 = cpu_flags_or (cpu_arch_isa_flags
,
12891 cpu_arch
[j
].flags
);
12896 if (j
>= ARRAY_SIZE (cpu_arch
))
12898 /* Disable an ISA extension. */
12899 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12900 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12902 i386_cpu_flags flags
;
12904 flags
= cpu_flags_and_not (cpu_arch_flags
,
12905 cpu_noarch
[j
].flags
);
12906 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12908 if (cpu_sub_arch_name
)
12910 char *name
= cpu_sub_arch_name
;
12911 cpu_sub_arch_name
= concat (arch
,
12912 (const char *) NULL
);
12916 cpu_sub_arch_name
= xstrdup (arch
);
12917 cpu_arch_flags
= flags
;
12918 cpu_arch_isa_flags
= flags
;
12923 if (j
>= ARRAY_SIZE (cpu_noarch
))
12924 j
= ARRAY_SIZE (cpu_arch
);
12927 if (j
>= ARRAY_SIZE (cpu_arch
))
12928 as_fatal (_("invalid -march= option: `%s'"), arg
);
12932 while (next
!= NULL
);
12938 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12939 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12941 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12943 cpu_arch_tune_set
= 1;
12944 cpu_arch_tune
= cpu_arch
[j
].type
;
12945 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12949 if (j
>= ARRAY_SIZE (cpu_arch
))
12950 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12953 case OPTION_MMNEMONIC
:
12954 if (strcasecmp (arg
, "att") == 0)
12955 intel_mnemonic
= 0;
12956 else if (strcasecmp (arg
, "intel") == 0)
12957 intel_mnemonic
= 1;
12959 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12962 case OPTION_MSYNTAX
:
12963 if (strcasecmp (arg
, "att") == 0)
12965 else if (strcasecmp (arg
, "intel") == 0)
12968 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12971 case OPTION_MINDEX_REG
:
12972 allow_index_reg
= 1;
12975 case OPTION_MNAKED_REG
:
12976 allow_naked_reg
= 1;
12979 case OPTION_MSSE2AVX
:
12983 case OPTION_MSSE_CHECK
:
12984 if (strcasecmp (arg
, "error") == 0)
12985 sse_check
= check_error
;
12986 else if (strcasecmp (arg
, "warning") == 0)
12987 sse_check
= check_warning
;
12988 else if (strcasecmp (arg
, "none") == 0)
12989 sse_check
= check_none
;
12991 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12994 case OPTION_MOPERAND_CHECK
:
12995 if (strcasecmp (arg
, "error") == 0)
12996 operand_check
= check_error
;
12997 else if (strcasecmp (arg
, "warning") == 0)
12998 operand_check
= check_warning
;
12999 else if (strcasecmp (arg
, "none") == 0)
13000 operand_check
= check_none
;
13002 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13005 case OPTION_MAVXSCALAR
:
13006 if (strcasecmp (arg
, "128") == 0)
13007 avxscalar
= vex128
;
13008 else if (strcasecmp (arg
, "256") == 0)
13009 avxscalar
= vex256
;
13011 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13014 case OPTION_MVEXWIG
:
13015 if (strcmp (arg
, "0") == 0)
13017 else if (strcmp (arg
, "1") == 0)
13020 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13023 case OPTION_MADD_BND_PREFIX
:
13024 add_bnd_prefix
= 1;
13027 case OPTION_MEVEXLIG
:
13028 if (strcmp (arg
, "128") == 0)
13029 evexlig
= evexl128
;
13030 else if (strcmp (arg
, "256") == 0)
13031 evexlig
= evexl256
;
13032 else if (strcmp (arg
, "512") == 0)
13033 evexlig
= evexl512
;
13035 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13038 case OPTION_MEVEXRCIG
:
13039 if (strcmp (arg
, "rne") == 0)
13041 else if (strcmp (arg
, "rd") == 0)
13043 else if (strcmp (arg
, "ru") == 0)
13045 else if (strcmp (arg
, "rz") == 0)
13048 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13051 case OPTION_MEVEXWIG
:
13052 if (strcmp (arg
, "0") == 0)
13054 else if (strcmp (arg
, "1") == 0)
13057 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13060 # if defined (TE_PE) || defined (TE_PEP)
13061 case OPTION_MBIG_OBJ
:
13066 case OPTION_MOMIT_LOCK_PREFIX
:
13067 if (strcasecmp (arg
, "yes") == 0)
13068 omit_lock_prefix
= 1;
13069 else if (strcasecmp (arg
, "no") == 0)
13070 omit_lock_prefix
= 0;
13072 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13075 case OPTION_MFENCE_AS_LOCK_ADD
:
13076 if (strcasecmp (arg
, "yes") == 0)
13078 else if (strcasecmp (arg
, "no") == 0)
13081 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13084 case OPTION_MLFENCE_AFTER_LOAD
:
13085 if (strcasecmp (arg
, "yes") == 0)
13086 lfence_after_load
= 1;
13087 else if (strcasecmp (arg
, "no") == 0)
13088 lfence_after_load
= 0;
13090 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13093 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13094 if (strcasecmp (arg
, "all") == 0)
13096 lfence_before_indirect_branch
= lfence_branch_all
;
13097 if (lfence_before_ret
== lfence_before_ret_none
)
13098 lfence_before_ret
= lfence_before_ret_shl
;
13100 else if (strcasecmp (arg
, "memory") == 0)
13101 lfence_before_indirect_branch
= lfence_branch_memory
;
13102 else if (strcasecmp (arg
, "register") == 0)
13103 lfence_before_indirect_branch
= lfence_branch_register
;
13104 else if (strcasecmp (arg
, "none") == 0)
13105 lfence_before_indirect_branch
= lfence_branch_none
;
13107 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13111 case OPTION_MLFENCE_BEFORE_RET
:
13112 if (strcasecmp (arg
, "or") == 0)
13113 lfence_before_ret
= lfence_before_ret_or
;
13114 else if (strcasecmp (arg
, "not") == 0)
13115 lfence_before_ret
= lfence_before_ret_not
;
13116 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13117 lfence_before_ret
= lfence_before_ret_shl
;
13118 else if (strcasecmp (arg
, "none") == 0)
13119 lfence_before_ret
= lfence_before_ret_none
;
13121 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13125 case OPTION_MRELAX_RELOCATIONS
:
13126 if (strcasecmp (arg
, "yes") == 0)
13127 generate_relax_relocations
= 1;
13128 else if (strcasecmp (arg
, "no") == 0)
13129 generate_relax_relocations
= 0;
13131 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13134 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13137 long int align
= strtoul (arg
, &end
, 0);
13142 align_branch_power
= 0;
13145 else if (align
>= 16)
13148 for (align_power
= 0;
13150 align
>>= 1, align_power
++)
13152 /* Limit alignment power to 31. */
13153 if (align
== 1 && align_power
< 32)
13155 align_branch_power
= align_power
;
13160 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13164 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13167 int align
= strtoul (arg
, &end
, 0);
13168 /* Some processors only support 5 prefixes. */
13169 if (*end
== '\0' && align
>= 0 && align
< 6)
13171 align_branch_prefix_size
= align
;
13174 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13179 case OPTION_MALIGN_BRANCH
:
13181 saved
= xstrdup (arg
);
13185 next
= strchr (type
, '+');
13188 if (strcasecmp (type
, "jcc") == 0)
13189 align_branch
|= align_branch_jcc_bit
;
13190 else if (strcasecmp (type
, "fused") == 0)
13191 align_branch
|= align_branch_fused_bit
;
13192 else if (strcasecmp (type
, "jmp") == 0)
13193 align_branch
|= align_branch_jmp_bit
;
13194 else if (strcasecmp (type
, "call") == 0)
13195 align_branch
|= align_branch_call_bit
;
13196 else if (strcasecmp (type
, "ret") == 0)
13197 align_branch
|= align_branch_ret_bit
;
13198 else if (strcasecmp (type
, "indirect") == 0)
13199 align_branch
|= align_branch_indirect_bit
;
13201 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13204 while (next
!= NULL
);
13208 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13209 align_branch_power
= 5;
13210 align_branch_prefix_size
= 5;
13211 align_branch
= (align_branch_jcc_bit
13212 | align_branch_fused_bit
13213 | align_branch_jmp_bit
);
13216 case OPTION_MAMD64
:
13220 case OPTION_MINTEL64
:
13228 /* Turn off -Os. */
13229 optimize_for_space
= 0;
13231 else if (*arg
== 's')
13233 optimize_for_space
= 1;
13234 /* Turn on all encoding optimizations. */
13235 optimize
= INT_MAX
;
13239 optimize
= atoi (arg
);
13240 /* Turn off -Os. */
13241 optimize_for_space
= 0;
13251 #define MESSAGE_TEMPLATE \
13255 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13256 int *left_p
, const char *name
, int len
)
13258 int size
= sizeof (MESSAGE_TEMPLATE
);
13259 int left
= *left_p
;
13261 /* Reserve 2 spaces for ", " or ",\0" */
13264 /* Check if there is any room. */
13272 p
= mempcpy (p
, name
, len
);
13276 /* Output the current message now and start a new one. */
13279 fprintf (stream
, "%s\n", message
);
13281 left
= size
- (start
- message
) - len
- 2;
13283 gas_assert (left
>= 0);
13285 p
= mempcpy (p
, name
, len
);
13293 show_arch (FILE *stream
, int ext
, int check
)
13295 static char message
[] = MESSAGE_TEMPLATE
;
13296 char *start
= message
+ 27;
13298 int size
= sizeof (MESSAGE_TEMPLATE
);
13305 left
= size
- (start
- message
);
13306 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13308 /* Should it be skipped? */
13309 if (cpu_arch
[j
].skip
)
13312 name
= cpu_arch
[j
].name
;
13313 len
= cpu_arch
[j
].len
;
13316 /* It is an extension. Skip if we aren't asked to show it. */
13327 /* It is an processor. Skip if we show only extension. */
13330 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13332 /* It is an impossible processor - skip. */
13336 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13339 /* Display disabled extensions. */
13341 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13343 name
= cpu_noarch
[j
].name
;
13344 len
= cpu_noarch
[j
].len
;
13345 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13350 fprintf (stream
, "%s\n", message
);
13354 md_show_usage (FILE *stream
)
13356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13357 fprintf (stream
, _("\
13358 -Qy, -Qn ignored\n\
13359 -V print assembler version number\n\
13362 fprintf (stream
, _("\
13363 -n Do not optimize code alignment\n\
13364 -q quieten some warnings\n"));
13365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13366 fprintf (stream
, _("\
13369 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13370 || defined (TE_PE) || defined (TE_PEP))
13371 fprintf (stream
, _("\
13372 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13374 #ifdef SVR4_COMMENT_CHARS
13375 fprintf (stream
, _("\
13376 --divide do not treat `/' as a comment character\n"));
13378 fprintf (stream
, _("\
13379 --divide ignored\n"));
13381 fprintf (stream
, _("\
13382 -march=CPU[,+EXTENSION...]\n\
13383 generate code for CPU and EXTENSION, CPU is one of:\n"));
13384 show_arch (stream
, 0, 1);
13385 fprintf (stream
, _("\
13386 EXTENSION is combination of:\n"));
13387 show_arch (stream
, 1, 0);
13388 fprintf (stream
, _("\
13389 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13390 show_arch (stream
, 0, 0);
13391 fprintf (stream
, _("\
13392 -msse2avx encode SSE instructions with VEX prefix\n"));
13393 fprintf (stream
, _("\
13394 -msse-check=[none|error|warning] (default: warning)\n\
13395 check SSE instructions\n"));
13396 fprintf (stream
, _("\
13397 -moperand-check=[none|error|warning] (default: warning)\n\
13398 check operand combinations for validity\n"));
13399 fprintf (stream
, _("\
13400 -mavxscalar=[128|256] (default: 128)\n\
13401 encode scalar AVX instructions with specific vector\n\
13403 fprintf (stream
, _("\
13404 -mvexwig=[0|1] (default: 0)\n\
13405 encode VEX instructions with specific VEX.W value\n\
13406 for VEX.W bit ignored instructions\n"));
13407 fprintf (stream
, _("\
13408 -mevexlig=[128|256|512] (default: 128)\n\
13409 encode scalar EVEX instructions with specific vector\n\
13411 fprintf (stream
, _("\
13412 -mevexwig=[0|1] (default: 0)\n\
13413 encode EVEX instructions with specific EVEX.W value\n\
13414 for EVEX.W bit ignored instructions\n"));
13415 fprintf (stream
, _("\
13416 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13417 encode EVEX instructions with specific EVEX.RC value\n\
13418 for SAE-only ignored instructions\n"));
13419 fprintf (stream
, _("\
13420 -mmnemonic=[att|intel] "));
13421 if (SYSV386_COMPAT
)
13422 fprintf (stream
, _("(default: att)\n"));
13424 fprintf (stream
, _("(default: intel)\n"));
13425 fprintf (stream
, _("\
13426 use AT&T/Intel mnemonic\n"));
13427 fprintf (stream
, _("\
13428 -msyntax=[att|intel] (default: att)\n\
13429 use AT&T/Intel syntax\n"));
13430 fprintf (stream
, _("\
13431 -mindex-reg support pseudo index registers\n"));
13432 fprintf (stream
, _("\
13433 -mnaked-reg don't require `%%' prefix for registers\n"));
13434 fprintf (stream
, _("\
13435 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13437 fprintf (stream
, _("\
13438 -mshared disable branch optimization for shared code\n"));
13439 fprintf (stream
, _("\
13440 -mx86-used-note=[no|yes] "));
13441 if (DEFAULT_X86_USED_NOTE
)
13442 fprintf (stream
, _("(default: yes)\n"));
13444 fprintf (stream
, _("(default: no)\n"));
13445 fprintf (stream
, _("\
13446 generate x86 used ISA and feature properties\n"));
13448 #if defined (TE_PE) || defined (TE_PEP)
13449 fprintf (stream
, _("\
13450 -mbig-obj generate big object files\n"));
13452 fprintf (stream
, _("\
13453 -momit-lock-prefix=[no|yes] (default: no)\n\
13454 strip all lock prefixes\n"));
13455 fprintf (stream
, _("\
13456 -mfence-as-lock-add=[no|yes] (default: no)\n\
13457 encode lfence, mfence and sfence as\n\
13458 lock addl $0x0, (%%{re}sp)\n"));
13459 fprintf (stream
, _("\
13460 -mrelax-relocations=[no|yes] "));
13461 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13462 fprintf (stream
, _("(default: yes)\n"));
13464 fprintf (stream
, _("(default: no)\n"));
13465 fprintf (stream
, _("\
13466 generate relax relocations\n"));
13467 fprintf (stream
, _("\
13468 -malign-branch-boundary=NUM (default: 0)\n\
13469 align branches within NUM byte boundary\n"));
13470 fprintf (stream
, _("\
13471 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13472 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13474 specify types of branches to align\n"));
13475 fprintf (stream
, _("\
13476 -malign-branch-prefix-size=NUM (default: 5)\n\
13477 align branches with NUM prefixes per instruction\n"));
13478 fprintf (stream
, _("\
13479 -mbranches-within-32B-boundaries\n\
13480 align branches within 32 byte boundary\n"));
13481 fprintf (stream
, _("\
13482 -mlfence-after-load=[no|yes] (default: no)\n\
13483 generate lfence after load\n"));
13484 fprintf (stream
, _("\
13485 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13486 generate lfence before indirect near branch\n"));
13487 fprintf (stream
, _("\
13488 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13489 generate lfence before ret\n"));
13490 fprintf (stream
, _("\
13491 -mamd64 accept only AMD64 ISA [default]\n"));
13492 fprintf (stream
, _("\
13493 -mintel64 accept only Intel64 ISA\n"));
13496 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13497 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13498 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13500 /* Pick the target format to use. */
13503 i386_target_format (void)
13505 if (!strncmp (default_arch
, "x86_64", 6))
13507 update_code_flag (CODE_64BIT
, 1);
13508 if (default_arch
[6] == '\0')
13509 x86_elf_abi
= X86_64_ABI
;
13511 x86_elf_abi
= X86_64_X32_ABI
;
13513 else if (!strcmp (default_arch
, "i386"))
13514 update_code_flag (CODE_32BIT
, 1);
13515 else if (!strcmp (default_arch
, "iamcu"))
13517 update_code_flag (CODE_32BIT
, 1);
13518 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13520 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13521 cpu_arch_name
= "iamcu";
13522 cpu_sub_arch_name
= NULL
;
13523 cpu_arch_flags
= iamcu_flags
;
13524 cpu_arch_isa
= PROCESSOR_IAMCU
;
13525 cpu_arch_isa_flags
= iamcu_flags
;
13526 if (!cpu_arch_tune_set
)
13528 cpu_arch_tune
= cpu_arch_isa
;
13529 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13532 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13533 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13537 as_fatal (_("unknown architecture"));
13539 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13540 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13541 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13542 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13544 switch (OUTPUT_FLAVOR
)
13546 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13547 case bfd_target_aout_flavour
:
13548 return AOUT_TARGET_FORMAT
;
13550 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13551 # if defined (TE_PE) || defined (TE_PEP)
13552 case bfd_target_coff_flavour
:
13553 if (flag_code
== CODE_64BIT
)
13554 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13556 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13557 # elif defined (TE_GO32)
13558 case bfd_target_coff_flavour
:
13559 return "coff-go32";
13561 case bfd_target_coff_flavour
:
13562 return "coff-i386";
13565 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13566 case bfd_target_elf_flavour
:
13568 const char *format
;
13570 switch (x86_elf_abi
)
13573 format
= ELF_TARGET_FORMAT
;
13575 tls_get_addr
= "___tls_get_addr";
13579 use_rela_relocations
= 1;
13582 tls_get_addr
= "__tls_get_addr";
13584 format
= ELF_TARGET_FORMAT64
;
13586 case X86_64_X32_ABI
:
13587 use_rela_relocations
= 1;
13590 tls_get_addr
= "__tls_get_addr";
13592 disallow_64bit_reloc
= 1;
13593 format
= ELF_TARGET_FORMAT32
;
13596 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13598 if (x86_elf_abi
!= X86_64_ABI
)
13599 as_fatal (_("Intel L1OM is 64bit only"));
13600 return ELF_TARGET_L1OM_FORMAT
;
13602 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13604 if (x86_elf_abi
!= X86_64_ABI
)
13605 as_fatal (_("Intel K1OM is 64bit only"));
13606 return ELF_TARGET_K1OM_FORMAT
;
13608 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13610 if (x86_elf_abi
!= I386_ABI
)
13611 as_fatal (_("Intel MCU is 32bit only"));
13612 return ELF_TARGET_IAMCU_FORMAT
;
13618 #if defined (OBJ_MACH_O)
13619 case bfd_target_mach_o_flavour
:
13620 if (flag_code
== CODE_64BIT
)
13622 use_rela_relocations
= 1;
13624 return "mach-o-x86-64";
13627 return "mach-o-i386";
13635 #endif /* OBJ_MAYBE_ more than one */
13638 md_undefined_symbol (char *name
)
13640 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13641 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13642 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13643 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13647 if (symbol_find (name
))
13648 as_bad (_("GOT already in symbol table"));
13649 GOT_symbol
= symbol_new (name
, undefined_section
,
13650 (valueT
) 0, &zero_address_frag
);
13657 /* Round up a section size to the appropriate boundary. */
13660 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13662 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13663 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13665 /* For a.out, force the section size to be aligned. If we don't do
13666 this, BFD will align it for us, but it will not write out the
13667 final bytes of the section. This may be a bug in BFD, but it is
13668 easier to fix it here since that is how the other a.out targets
13672 align
= bfd_section_alignment (segment
);
13673 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13680 /* On the i386, PC-relative offsets are relative to the start of the
13681 next instruction. That is, the address of the offset, plus its
13682 size, since the offset is always the last part of the insn. */
13685 md_pcrel_from (fixS
*fixP
)
13687 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13693 s_bss (int ignore ATTRIBUTE_UNUSED
)
13697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13699 obj_elf_section_change_hook ();
13701 temp
= get_absolute_expression ();
13702 subseg_set (bss_section
, (subsegT
) temp
);
13703 demand_empty_rest_of_line ();
13708 /* Remember constant directive. */
13711 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13713 if (last_insn
.kind
!= last_insn_directive
13714 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13716 last_insn
.seg
= now_seg
;
13717 last_insn
.kind
= last_insn_directive
;
13718 last_insn
.name
= "constant directive";
13719 last_insn
.file
= as_where (&last_insn
.line
);
13720 if (lfence_before_ret
!= lfence_before_ret_none
)
13722 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13723 as_warn (_("constant directive skips -mlfence-before-ret "
13724 "and -mlfence-before-indirect-branch"));
13726 as_warn (_("constant directive skips -mlfence-before-ret"));
13728 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13729 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13734 i386_validate_fix (fixS
*fixp
)
13736 if (fixp
->fx_subsy
)
13738 if (fixp
->fx_subsy
== GOT_symbol
)
13740 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13744 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13745 if (fixp
->fx_tcbit2
)
13746 fixp
->fx_r_type
= (fixp
->fx_tcbit
13747 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13748 : BFD_RELOC_X86_64_GOTPCRELX
);
13751 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13756 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13758 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13760 fixp
->fx_subsy
= 0;
13763 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13764 else if (!object_64bit
)
13766 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13767 && fixp
->fx_tcbit2
)
13768 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13774 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13777 bfd_reloc_code_real_type code
;
13779 switch (fixp
->fx_r_type
)
13781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13782 case BFD_RELOC_SIZE32
:
13783 case BFD_RELOC_SIZE64
:
13784 if (S_IS_DEFINED (fixp
->fx_addsy
)
13785 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13787 /* Resolve size relocation against local symbol to size of
13788 the symbol plus addend. */
13789 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13790 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13791 && !fits_in_unsigned_long (value
))
13792 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13793 _("symbol size computation overflow"));
13794 fixp
->fx_addsy
= NULL
;
13795 fixp
->fx_subsy
= NULL
;
13796 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13800 /* Fall through. */
13802 case BFD_RELOC_X86_64_PLT32
:
13803 case BFD_RELOC_X86_64_GOT32
:
13804 case BFD_RELOC_X86_64_GOTPCREL
:
13805 case BFD_RELOC_X86_64_GOTPCRELX
:
13806 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13807 case BFD_RELOC_386_PLT32
:
13808 case BFD_RELOC_386_GOT32
:
13809 case BFD_RELOC_386_GOT32X
:
13810 case BFD_RELOC_386_GOTOFF
:
13811 case BFD_RELOC_386_GOTPC
:
13812 case BFD_RELOC_386_TLS_GD
:
13813 case BFD_RELOC_386_TLS_LDM
:
13814 case BFD_RELOC_386_TLS_LDO_32
:
13815 case BFD_RELOC_386_TLS_IE_32
:
13816 case BFD_RELOC_386_TLS_IE
:
13817 case BFD_RELOC_386_TLS_GOTIE
:
13818 case BFD_RELOC_386_TLS_LE_32
:
13819 case BFD_RELOC_386_TLS_LE
:
13820 case BFD_RELOC_386_TLS_GOTDESC
:
13821 case BFD_RELOC_386_TLS_DESC_CALL
:
13822 case BFD_RELOC_X86_64_TLSGD
:
13823 case BFD_RELOC_X86_64_TLSLD
:
13824 case BFD_RELOC_X86_64_DTPOFF32
:
13825 case BFD_RELOC_X86_64_DTPOFF64
:
13826 case BFD_RELOC_X86_64_GOTTPOFF
:
13827 case BFD_RELOC_X86_64_TPOFF32
:
13828 case BFD_RELOC_X86_64_TPOFF64
:
13829 case BFD_RELOC_X86_64_GOTOFF64
:
13830 case BFD_RELOC_X86_64_GOTPC32
:
13831 case BFD_RELOC_X86_64_GOT64
:
13832 case BFD_RELOC_X86_64_GOTPCREL64
:
13833 case BFD_RELOC_X86_64_GOTPC64
:
13834 case BFD_RELOC_X86_64_GOTPLT64
:
13835 case BFD_RELOC_X86_64_PLTOFF64
:
13836 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13837 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13838 case BFD_RELOC_RVA
:
13839 case BFD_RELOC_VTABLE_ENTRY
:
13840 case BFD_RELOC_VTABLE_INHERIT
:
13842 case BFD_RELOC_32_SECREL
:
13844 code
= fixp
->fx_r_type
;
13846 case BFD_RELOC_X86_64_32S
:
13847 if (!fixp
->fx_pcrel
)
13849 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13850 code
= fixp
->fx_r_type
;
13853 /* Fall through. */
13855 if (fixp
->fx_pcrel
)
13857 switch (fixp
->fx_size
)
13860 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13861 _("can not do %d byte pc-relative relocation"),
13863 code
= BFD_RELOC_32_PCREL
;
13865 case 1: code
= BFD_RELOC_8_PCREL
; break;
13866 case 2: code
= BFD_RELOC_16_PCREL
; break;
13867 case 4: code
= BFD_RELOC_32_PCREL
; break;
13869 case 8: code
= BFD_RELOC_64_PCREL
; break;
13875 switch (fixp
->fx_size
)
13878 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13879 _("can not do %d byte relocation"),
13881 code
= BFD_RELOC_32
;
13883 case 1: code
= BFD_RELOC_8
; break;
13884 case 2: code
= BFD_RELOC_16
; break;
13885 case 4: code
= BFD_RELOC_32
; break;
13887 case 8: code
= BFD_RELOC_64
; break;
13894 if ((code
== BFD_RELOC_32
13895 || code
== BFD_RELOC_32_PCREL
13896 || code
== BFD_RELOC_X86_64_32S
)
13898 && fixp
->fx_addsy
== GOT_symbol
)
13901 code
= BFD_RELOC_386_GOTPC
;
13903 code
= BFD_RELOC_X86_64_GOTPC32
;
13905 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13907 && fixp
->fx_addsy
== GOT_symbol
)
13909 code
= BFD_RELOC_X86_64_GOTPC64
;
13912 rel
= XNEW (arelent
);
13913 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13914 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13916 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13918 if (!use_rela_relocations
)
13920 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13921 vtable entry to be used in the relocation's section offset. */
13922 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13923 rel
->address
= fixp
->fx_offset
;
13924 #if defined (OBJ_COFF) && defined (TE_PE)
13925 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13926 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13931 /* Use the rela in 64bit mode. */
13934 if (disallow_64bit_reloc
)
13937 case BFD_RELOC_X86_64_DTPOFF64
:
13938 case BFD_RELOC_X86_64_TPOFF64
:
13939 case BFD_RELOC_64_PCREL
:
13940 case BFD_RELOC_X86_64_GOTOFF64
:
13941 case BFD_RELOC_X86_64_GOT64
:
13942 case BFD_RELOC_X86_64_GOTPCREL64
:
13943 case BFD_RELOC_X86_64_GOTPC64
:
13944 case BFD_RELOC_X86_64_GOTPLT64
:
13945 case BFD_RELOC_X86_64_PLTOFF64
:
13946 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13947 _("cannot represent relocation type %s in x32 mode"),
13948 bfd_get_reloc_code_name (code
));
13954 if (!fixp
->fx_pcrel
)
13955 rel
->addend
= fixp
->fx_offset
;
13959 case BFD_RELOC_X86_64_PLT32
:
13960 case BFD_RELOC_X86_64_GOT32
:
13961 case BFD_RELOC_X86_64_GOTPCREL
:
13962 case BFD_RELOC_X86_64_GOTPCRELX
:
13963 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13964 case BFD_RELOC_X86_64_TLSGD
:
13965 case BFD_RELOC_X86_64_TLSLD
:
13966 case BFD_RELOC_X86_64_GOTTPOFF
:
13967 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13968 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13969 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13972 rel
->addend
= (section
->vma
13974 + fixp
->fx_addnumber
13975 + md_pcrel_from (fixp
));
13980 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13981 if (rel
->howto
== NULL
)
13983 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13984 _("cannot represent relocation type %s"),
13985 bfd_get_reloc_code_name (code
));
13986 /* Set howto to a garbage value so that we can keep going. */
13987 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13988 gas_assert (rel
->howto
!= NULL
);
13994 #include "tc-i386-intel.c"
13997 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13999 int saved_naked_reg
;
14000 char saved_register_dot
;
14002 saved_naked_reg
= allow_naked_reg
;
14003 allow_naked_reg
= 1;
14004 saved_register_dot
= register_chars
['.'];
14005 register_chars
['.'] = '.';
14006 allow_pseudo_reg
= 1;
14007 expression_and_evaluate (exp
);
14008 allow_pseudo_reg
= 0;
14009 register_chars
['.'] = saved_register_dot
;
14010 allow_naked_reg
= saved_naked_reg
;
14012 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14014 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14016 exp
->X_op
= O_constant
;
14017 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14018 .dw2_regnum
[flag_code
>> 1];
14021 exp
->X_op
= O_illegal
;
14026 tc_x86_frame_initial_instructions (void)
14028 static unsigned int sp_regno
[2];
14030 if (!sp_regno
[flag_code
>> 1])
14032 char *saved_input
= input_line_pointer
;
14033 char sp
[][4] = {"esp", "rsp"};
14036 input_line_pointer
= sp
[flag_code
>> 1];
14037 tc_x86_parse_to_dw2regnum (&exp
);
14038 gas_assert (exp
.X_op
== O_constant
);
14039 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14040 input_line_pointer
= saved_input
;
14043 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14044 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14048 x86_dwarf2_addr_size (void)
14050 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14051 if (x86_elf_abi
== X86_64_X32_ABI
)
14054 return bfd_arch_bits_per_address (stdoutput
) / 8;
14058 i386_elf_section_type (const char *str
, size_t len
)
14060 if (flag_code
== CODE_64BIT
14061 && len
== sizeof ("unwind") - 1
14062 && strncmp (str
, "unwind", 6) == 0)
14063 return SHT_X86_64_UNWIND
;
14070 i386_solaris_fix_up_eh_frame (segT sec
)
14072 if (flag_code
== CODE_64BIT
)
14073 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14079 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14083 exp
.X_op
= O_secrel
;
14084 exp
.X_add_symbol
= symbol
;
14085 exp
.X_add_number
= 0;
14086 emit_expr (&exp
, size
);
14090 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14091 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14094 x86_64_section_letter (int letter
, const char **ptr_msg
)
14096 if (flag_code
== CODE_64BIT
)
14099 return SHF_X86_64_LARGE
;
14101 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14104 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14109 x86_64_section_word (char *str
, size_t len
)
14111 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14112 return SHF_X86_64_LARGE
;
14118 handle_large_common (int small ATTRIBUTE_UNUSED
)
14120 if (flag_code
!= CODE_64BIT
)
14122 s_comm_internal (0, elf_common_parse
);
14123 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14127 static segT lbss_section
;
14128 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14129 asection
*saved_bss_section
= bss_section
;
14131 if (lbss_section
== NULL
)
14133 flagword applicable
;
14134 segT seg
= now_seg
;
14135 subsegT subseg
= now_subseg
;
14137 /* The .lbss section is for local .largecomm symbols. */
14138 lbss_section
= subseg_new (".lbss", 0);
14139 applicable
= bfd_applicable_section_flags (stdoutput
);
14140 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14141 seg_info (lbss_section
)->bss
= 1;
14143 subseg_set (seg
, subseg
);
14146 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14147 bss_section
= lbss_section
;
14149 s_comm_internal (0, elf_common_parse
);
14151 elf_com_section_ptr
= saved_com_section_ptr
;
14152 bss_section
= saved_bss_section
;
14155 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */