1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
292 #define Operand_Signed 4 /* .insn only */
294 /* Relocation type for operand */
295 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
297 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
298 the base index byte below. */
299 const reg_entry
*base_reg
;
300 const reg_entry
*index_reg
;
301 unsigned int log2_scale_factor
;
303 /* SEG gives the seg_entries of this insn. They are zero unless
304 explicit segment overrides are given. */
305 const reg_entry
*seg
[2];
307 /* PREFIX holds all the given prefix opcodes (usually null).
308 PREFIXES is the number of prefix opcodes. */
309 unsigned int prefixes
;
310 unsigned char prefix
[MAX_PREFIXES
];
312 /* .insn allows for reserved opcode spaces. */
313 unsigned char insn_opcode_space
;
315 /* .insn also allows (requires) specifying immediate size. */
316 unsigned char imm_bits
[MAX_OPERANDS
];
318 /* Register is in low 3 bits of opcode. */
321 /* The operand to a branch insn indicates an absolute branch. */
324 /* The operand to a branch insn indicates a far branch. */
327 /* There is a memory operand of (%dx) which should be only used
328 with input/output instructions. */
329 bool input_output_operand
;
331 /* Extended states. */
339 xstate_ymm
= 1 << 2 | xstate_xmm
,
341 xstate_zmm
= 1 << 3 | xstate_ymm
,
344 /* Use MASK state. */
348 /* Has GOTPC or TLS relocation. */
349 bool has_gotpc_tls_reloc
;
351 /* RM and SIB are the modrm byte and the sib byte where the
352 addressing modes of this insn are encoded. */
359 /* Masking attributes.
361 The struct describes masking, applied to OPERAND in the instruction.
362 REG is a pointer to the corresponding mask register. ZEROING tells
363 whether merging or zeroing mask is used. */
364 struct Mask_Operation
366 const reg_entry
*reg
;
367 unsigned int zeroing
;
368 /* The operand where this operation is associated. */
369 unsigned int operand
;
372 /* Rounding control and SAE attributes. */
384 /* In Intel syntax the operand modifier form is supposed to be used, but
385 we continue to accept the immediate forms as well. */
389 /* Broadcasting attributes.
391 The struct describes broadcasting, applied to OPERAND. TYPE is
392 expresses the broadcast factor. */
393 struct Broadcast_Operation
395 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
398 /* Index of broadcasted operand. */
399 unsigned int operand
;
401 /* Number of bytes to broadcast. */
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
429 /* Disable instruction size optimization. */
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
443 const char *rep_prefix
;
446 const char *hle_prefix
;
448 /* Have BND prefix. */
449 const char *bnd_prefix
;
451 /* Have NOTRACK prefix. */
452 const char *notrack_prefix
;
455 enum i386_error error
;
458 typedef struct _i386_insn i386_insn
;
460 /* Link RC type with corresponding string, that'll be looked for in
469 static const struct RC_name RC_NamesTable
[] =
471 { rne
, STRING_COMMA_LEN ("rn-sae") },
472 { rd
, STRING_COMMA_LEN ("rd-sae") },
473 { ru
, STRING_COMMA_LEN ("ru-sae") },
474 { rz
, STRING_COMMA_LEN ("rz-sae") },
475 { saeonly
, STRING_COMMA_LEN ("sae") },
478 /* To be indexed by segment register number. */
479 static const unsigned char i386_seg_prefixes
[] = {
488 /* List of chars besides those in app.c:symbol_chars that can start an
489 operand. Used to prevent the scrubber eating vital white-space. */
490 const char extra_symbol_chars
[] = "*%-([{}"
499 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
500 && !defined (TE_GNU) \
501 && !defined (TE_LINUX) \
502 && !defined (TE_Haiku) \
503 && !defined (TE_FreeBSD) \
504 && !defined (TE_DragonFly) \
505 && !defined (TE_NetBSD))
506 /* This array holds the chars that always start a comment. If the
507 pre-processor is disabled, these aren't very useful. The option
508 --divide will remove '/' from this list. */
509 const char *i386_comment_chars
= "#/";
510 #define SVR4_COMMENT_CHARS 1
511 #define PREFIX_SEPARATOR '\\'
514 const char *i386_comment_chars
= "#";
515 #define PREFIX_SEPARATOR '/'
518 /* This array holds the chars that only start a comment at the beginning of
519 a line. If the line seems to have the form '# 123 filename'
520 .line and .file directives will appear in the pre-processed output.
521 Note that input_file.c hand checks for '#' at the beginning of the
522 first line of the input file. This is because the compiler outputs
523 #NO_APP at the beginning of its output.
524 Also note that comments started like this one will always work if
525 '/' isn't otherwise defined. */
526 const char line_comment_chars
[] = "#/";
528 const char line_separator_chars
[] = ";";
530 /* Chars that can be used to separate mant from exp in floating point
532 const char EXP_CHARS
[] = "eE";
534 /* Chars that mean this number is a floating point constant
537 const char FLT_CHARS
[] = "fFdDxXhHbB";
539 /* Tables for lexical analysis. */
540 static char mnemonic_chars
[256];
541 static char register_chars
[256];
542 static char operand_chars
[256];
544 /* Lexical macros. */
545 #define is_operand_char(x) (operand_chars[(unsigned char) x])
546 #define is_register_char(x) (register_chars[(unsigned char) x])
547 #define is_space_char(x) ((x) == ' ')
549 /* All non-digit non-letter characters that may occur in an operand and
550 which aren't already in extra_symbol_chars[]. */
551 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
553 /* md_assemble() always leaves the strings it's passed unaltered. To
554 effect this we maintain a stack of saved characters that we've smashed
555 with '\0's (indicating end of strings for various sub-fields of the
556 assembler instruction). */
557 static char save_stack
[32];
558 static char *save_stack_p
;
559 #define END_STRING_AND_SAVE(s) \
560 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
561 #define RESTORE_END_STRING(s) \
562 do { *(s) = *--save_stack_p; } while (0)
564 /* The instruction we're assembling. */
567 /* Possible templates for current insn. */
568 static const templates
*current_templates
;
570 /* Per instruction expressionS buffers: max displacements & immediates. */
571 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
572 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
574 /* Current operand we are working on. */
575 static int this_operand
= -1;
577 /* Are we processing a .insn directive? */
578 #define dot_insn() (i.tm.mnem_off == MN__insn)
580 /* We support four different modes. FLAG_CODE variable is used to distinguish
588 static enum flag_code flag_code
;
589 static unsigned int object_64bit
;
590 static unsigned int disallow_64bit_reloc
;
591 static int use_rela_relocations
= 0;
592 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
593 static const char *tls_get_addr
;
595 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
596 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
597 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
599 /* The ELF ABI to use. */
607 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
610 #if defined (TE_PE) || defined (TE_PEP)
611 /* Use big object file format. */
612 static int use_big_obj
= 0;
615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
616 /* 1 if generating code for a shared library. */
617 static int shared
= 0;
619 unsigned int x86_sframe_cfa_sp_reg
;
620 /* The other CFA base register for SFrame stack trace info. */
621 unsigned int x86_sframe_cfa_fp_reg
;
622 unsigned int x86_sframe_cfa_ra_reg
;
626 /* 1 for intel syntax,
628 static int intel_syntax
= 0;
630 static enum x86_64_isa
632 amd64
= 1, /* AMD64 ISA. */
633 intel64
/* Intel64 ISA. */
636 /* 1 for intel mnemonic,
637 0 if att mnemonic. */
638 static int intel_mnemonic
= !SYSV386_COMPAT
;
640 /* 1 if pseudo registers are permitted. */
641 static int allow_pseudo_reg
= 0;
643 /* 1 if register prefix % not required. */
644 static int allow_naked_reg
= 0;
646 /* 1 if the assembler should add BND prefix for all control-transferring
647 instructions supporting it, even if this prefix wasn't specified
649 static int add_bnd_prefix
= 0;
651 /* 1 if pseudo index register, eiz/riz, is allowed . */
652 static int allow_index_reg
= 0;
654 /* 1 if the assembler should ignore LOCK prefix, even if it was
655 specified explicitly. */
656 static int omit_lock_prefix
= 0;
658 /* 1 if the assembler should encode lfence, mfence, and sfence as
659 "lock addl $0, (%{re}sp)". */
660 static int avoid_fence
= 0;
662 /* 1 if lfence should be inserted after every load. */
663 static int lfence_after_load
= 0;
665 /* Non-zero if lfence should be inserted before indirect branch. */
666 static enum lfence_before_indirect_branch_kind
668 lfence_branch_none
= 0,
669 lfence_branch_register
,
670 lfence_branch_memory
,
673 lfence_before_indirect_branch
;
675 /* Non-zero if lfence should be inserted before ret. */
676 static enum lfence_before_ret_kind
678 lfence_before_ret_none
= 0,
679 lfence_before_ret_not
,
680 lfence_before_ret_or
,
681 lfence_before_ret_shl
685 /* Types of previous instruction is .byte or prefix. */
700 /* 1 if the assembler should generate relax relocations. */
702 static int generate_relax_relocations
703 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
705 static enum check_kind
711 sse_check
, operand_check
= check_warning
;
713 /* Non-zero if branches should be aligned within power of 2 boundary. */
714 static int align_branch_power
= 0;
716 /* Types of branches to align. */
717 enum align_branch_kind
719 align_branch_none
= 0,
720 align_branch_jcc
= 1,
721 align_branch_fused
= 2,
722 align_branch_jmp
= 3,
723 align_branch_call
= 4,
724 align_branch_indirect
= 5,
728 /* Type bits of branches to align. */
729 enum align_branch_bit
731 align_branch_jcc_bit
= 1 << align_branch_jcc
,
732 align_branch_fused_bit
= 1 << align_branch_fused
,
733 align_branch_jmp_bit
= 1 << align_branch_jmp
,
734 align_branch_call_bit
= 1 << align_branch_call
,
735 align_branch_indirect_bit
= 1 << align_branch_indirect
,
736 align_branch_ret_bit
= 1 << align_branch_ret
739 static unsigned int align_branch
= (align_branch_jcc_bit
740 | align_branch_fused_bit
741 | align_branch_jmp_bit
);
743 /* Types of condition jump used by macro-fusion. */
746 mf_jcc_jo
= 0, /* base opcode 0x70 */
747 mf_jcc_jc
, /* base opcode 0x72 */
748 mf_jcc_je
, /* base opcode 0x74 */
749 mf_jcc_jna
, /* base opcode 0x76 */
750 mf_jcc_js
, /* base opcode 0x78 */
751 mf_jcc_jp
, /* base opcode 0x7a */
752 mf_jcc_jl
, /* base opcode 0x7c */
753 mf_jcc_jle
, /* base opcode 0x7e */
756 /* Types of compare flag-modifying insntructions used by macro-fusion. */
759 mf_cmp_test_and
, /* test/cmp */
760 mf_cmp_alu_cmp
, /* add/sub/cmp */
761 mf_cmp_incdec
/* inc/dec */
764 /* The maximum padding size for fused jcc. CMP like instruction can
765 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
767 #define MAX_FUSED_JCC_PADDING_SIZE 20
769 /* The maximum number of prefixes added for an instruction. */
770 static unsigned int align_branch_prefix_size
= 5;
773 1. Clear the REX_W bit with register operand if possible.
774 2. Above plus use 128bit vector instruction to clear the full vector
777 static int optimize
= 0;
780 1. Clear the REX_W bit with register operand if possible.
781 2. Above plus use 128bit vector instruction to clear the full vector
783 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
786 static int optimize_for_space
= 0;
788 /* Register prefix used for error message. */
789 static const char *register_prefix
= "%";
791 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
792 leave, push, and pop instructions so that gcc has the same stack
793 frame as in 32 bit mode. */
794 static char stackop_size
= '\0';
796 /* Non-zero to optimize code alignment. */
797 int optimize_align_code
= 1;
799 /* Non-zero to quieten some warnings. */
800 static int quiet_warnings
= 0;
802 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
803 static bool pre_386_16bit_warned
;
806 static const char *cpu_arch_name
= NULL
;
807 static char *cpu_sub_arch_name
= NULL
;
809 /* CPU feature flags. */
810 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
812 /* If we have selected a cpu we are generating instructions for. */
813 static int cpu_arch_tune_set
= 0;
815 /* Cpu we are generating instructions for. */
816 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
818 /* CPU feature flags of cpu we are generating instructions for. */
819 static i386_cpu_flags cpu_arch_tune_flags
;
821 /* CPU instruction set architecture used. */
822 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
824 /* CPU feature flags of instruction set architecture used. */
825 i386_cpu_flags cpu_arch_isa_flags
;
827 /* If set, conditional jumps are not automatically promoted to handle
828 larger than a byte offset. */
829 static bool no_cond_jump_promotion
= false;
831 /* This will be set from an expression parser hook if there's any
832 applicable operator involved in an expression. */
835 expr_operator_present
,
839 /* Encode SSE instructions with VEX prefix. */
840 static unsigned int sse2avx
;
842 /* Encode aligned vector move as unaligned vector move. */
843 static unsigned int use_unaligned_vector_move
;
845 /* Maximum permitted vector size. */
846 #define VSZ_DEFAULT VSZ512
847 static unsigned int vector_size
= VSZ_DEFAULT
;
849 /* Encode scalar AVX instructions with specific vector length. */
856 /* Encode VEX WIG instructions with specific vex.w. */
863 /* Encode scalar EVEX LIG instructions with specific vector length. */
871 /* Encode EVEX WIG instructions with specific evex.w. */
878 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
879 static enum rc_type evexrcig
= rne
;
881 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
882 static symbolS
*GOT_symbol
;
884 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
885 unsigned int x86_dwarf2_return_column
;
887 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
888 int x86_cie_data_alignment
;
890 /* Interface to relax_segment.
891 There are 3 major relax states for 386 jump insns because the
892 different types of jumps add different sizes to frags when we're
893 figuring out what sort of jump to choose to reach a given label.
895 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
896 branches which are handled by md_estimate_size_before_relax() and
897 i386_generic_table_relax_frag(). */
900 #define UNCOND_JUMP 0
902 #define COND_JUMP86 2
903 #define BRANCH_PADDING 3
904 #define BRANCH_PREFIX 4
905 #define FUSED_JCC_PADDING 5
910 #define SMALL16 (SMALL | CODE16)
912 #define BIG16 (BIG | CODE16)
916 #define INLINE __inline__
922 #define ENCODE_RELAX_STATE(type, size) \
923 ((relax_substateT) (((type) << 2) | (size)))
924 #define TYPE_FROM_RELAX_STATE(s) \
926 #define DISP_SIZE_FROM_RELAX_STATE(s) \
927 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
929 /* This table is used by relax_frag to promote short jumps to long
930 ones where necessary. SMALL (short) jumps may be promoted to BIG
931 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
932 don't allow a short jump in a 32 bit code segment to be promoted to
933 a 16 bit offset jump because it's slower (requires data size
934 prefix), and doesn't work, unless the destination is in the bottom
935 64k of the code segment (The top 16 bits of eip are zeroed). */
937 const relax_typeS md_relax_table
[] =
940 1) most positive reach of this state,
941 2) most negative reach of this state,
942 3) how many bytes this mode will have in the variable part of the frag
943 4) which index into the table to try if we can't fit into this one. */
945 /* UNCOND_JUMP states. */
946 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
947 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
948 /* dword jmp adds 4 bytes to frag:
949 0 extra opcode bytes, 4 displacement bytes. */
951 /* word jmp adds 2 byte2 to frag:
952 0 extra opcode bytes, 2 displacement bytes. */
955 /* COND_JUMP states. */
956 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
957 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
958 /* dword conditionals adds 5 bytes to frag:
959 1 extra opcode byte, 4 displacement bytes. */
961 /* word conditionals add 3 bytes to frag:
962 1 extra opcode byte, 2 displacement bytes. */
965 /* COND_JUMP86 states. */
966 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
967 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
968 /* dword conditionals adds 5 bytes to frag:
969 1 extra opcode byte, 4 displacement bytes. */
971 /* word conditionals add 4 bytes to frag:
972 1 displacement byte and a 3 byte long branch insn. */
976 #define ARCH(n, t, f, s) \
977 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
979 #define SUBARCH(n, e, d, s) \
980 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
981 CPU_ ## d ## _FLAGS }
982 #define VECARCH(n, e, d, v) \
983 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
984 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
986 static const arch_entry cpu_arch
[] =
988 /* Do not replace the first two entries - i386_target_format() and
989 set_cpu_arch() rely on them being there in this order. */
990 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
991 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
992 ARCH (i8086
, UNKNOWN
, NONE
, false),
993 ARCH (i186
, UNKNOWN
, 186, false),
994 ARCH (i286
, UNKNOWN
, 286, false),
995 ARCH (i386
, I386
, 386, false),
996 ARCH (i486
, I486
, 486, false),
997 ARCH (i586
, PENTIUM
, 586, false),
998 ARCH (i686
, PENTIUMPRO
, 686, false),
999 ARCH (pentium
, PENTIUM
, 586, false),
1000 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
1001 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
1002 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
1003 ARCH (pentium4
, PENTIUM4
, P4
, false),
1004 ARCH (prescott
, NOCONA
, CORE
, false),
1005 ARCH (nocona
, NOCONA
, NOCONA
, false),
1006 ARCH (yonah
, CORE
, CORE
, true),
1007 ARCH (core
, CORE
, CORE
, false),
1008 ARCH (merom
, CORE2
, CORE2
, true),
1009 ARCH (core2
, CORE2
, CORE2
, false),
1010 ARCH (corei7
, COREI7
, COREI7
, false),
1011 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1012 ARCH (k6
, K6
, K6
, false),
1013 ARCH (k6_2
, K6
, K6_2
, false),
1014 ARCH (athlon
, ATHLON
, ATHLON
, false),
1015 ARCH (sledgehammer
, K8
, K8
, true),
1016 ARCH (opteron
, K8
, K8
, false),
1017 ARCH (k8
, K8
, K8
, false),
1018 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1019 ARCH (bdver1
, BD
, BDVER1
, false),
1020 ARCH (bdver2
, BD
, BDVER2
, false),
1021 ARCH (bdver3
, BD
, BDVER3
, false),
1022 ARCH (bdver4
, BD
, BDVER4
, false),
1023 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1024 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1025 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1026 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1027 ARCH (btver1
, BT
, BTVER1
, false),
1028 ARCH (btver2
, BT
, BTVER2
, false),
1030 SUBARCH (8087, 8087, ANY_8087
, false),
1031 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1032 SUBARCH (287, 287, ANY_287
, false),
1033 SUBARCH (387, 387, ANY_387
, false),
1034 SUBARCH (687, 687, ANY_687
, false),
1035 SUBARCH (cmov
, CMOV
, CMOV
, false),
1036 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1037 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1038 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1039 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1040 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1041 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1042 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1043 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1044 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1045 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1046 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1047 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1048 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1049 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1050 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1051 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1052 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1053 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1054 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1055 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1056 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1057 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1058 SUBARCH (smx
, SMX
, SMX
, false),
1059 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1060 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1061 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1062 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1063 SUBARCH (aes
, AES
, ANY_AES
, false),
1064 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1065 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1066 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1067 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1068 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1069 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1070 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1071 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1072 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1073 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1074 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1075 SUBARCH (cx16
, CX16
, CX16
, false),
1076 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1077 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1078 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1079 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1080 SUBARCH (hle
, HLE
, HLE
, false),
1081 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1082 SUBARCH (tsx
, TSX
, TSX
, false),
1083 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1084 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1085 SUBARCH (nop
, NOP
, NOP
, false),
1086 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1087 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1088 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1089 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1090 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1091 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1092 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1093 SUBARCH (abm
, ABM
, ABM
, false),
1094 SUBARCH (bmi
, BMI
, BMI
, false),
1095 SUBARCH (tbm
, TBM
, TBM
, false),
1096 SUBARCH (adx
, ADX
, ADX
, false),
1097 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1098 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1099 SUBARCH (smap
, SMAP
, SMAP
, false),
1100 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1101 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1102 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1103 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1104 SUBARCH (se1
, SE1
, SE1
, false),
1105 SUBARCH (clwb
, CLWB
, CLWB
, false),
1106 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1107 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1108 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1109 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1110 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1111 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1112 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1113 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1114 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1115 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1116 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1117 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1118 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1119 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1120 SUBARCH (ibt
, IBT
, IBT
, false),
1121 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1122 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1123 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1124 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1125 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1126 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1127 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1128 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1129 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1130 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1131 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1132 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1133 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1134 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1135 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1136 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1137 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1138 ANY_AVX512_VP2INTERSECT
, reset
),
1139 SUBARCH (tdx
, TDX
, TDX
, false),
1140 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1141 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1142 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1143 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1144 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1145 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1146 SUBARCH (kl
, KL
, ANY_KL
, false),
1147 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1148 SUBARCH (uintr
, UINTR
, UINTR
, false),
1149 SUBARCH (hreset
, HRESET
, HRESET
, false),
1150 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1151 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1152 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1153 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1154 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1155 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1156 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1157 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1158 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1159 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1160 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1161 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1162 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1163 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1164 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1165 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1166 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1167 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1174 /* Like s_lcomm_internal in gas/read.c but the alignment string
1175 is allowed to be optional. */
1178 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1185 && *input_line_pointer
== ',')
1187 align
= parse_align (needs_align
- 1);
1189 if (align
== (addressT
) -1)
1204 bss_alloc (symbolP
, size
, align
);
1209 pe_lcomm (int needs_align
)
1211 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1215 const pseudo_typeS md_pseudo_table
[] =
1217 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1218 {"align", s_align_bytes
, 0},
1220 {"align", s_align_ptwo
, 0},
1222 {"arch", set_cpu_arch
, 0},
1226 {"lcomm", pe_lcomm
, 1},
1228 {"ffloat", float_cons
, 'f'},
1229 {"dfloat", float_cons
, 'd'},
1230 {"tfloat", float_cons
, 'x'},
1231 {"hfloat", float_cons
, 'h'},
1232 {"bfloat16", float_cons
, 'b'},
1234 {"slong", signed_cons
, 4},
1235 {"insn", s_insn
, 0},
1236 {"noopt", s_ignore
, 0},
1237 {"optim", s_ignore
, 0},
1238 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1239 {"code16", set_code_flag
, CODE_16BIT
},
1240 {"code32", set_code_flag
, CODE_32BIT
},
1242 {"code64", set_code_flag
, CODE_64BIT
},
1244 {"intel_syntax", set_intel_syntax
, 1},
1245 {"att_syntax", set_intel_syntax
, 0},
1246 {"intel_mnemonic", set_intel_mnemonic
, 1},
1247 {"att_mnemonic", set_intel_mnemonic
, 0},
1248 {"allow_index_reg", set_allow_index_reg
, 1},
1249 {"disallow_index_reg", set_allow_index_reg
, 0},
1250 {"sse_check", set_check
, 0},
1251 {"operand_check", set_check
, 1},
1252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1253 {"largecomm", handle_large_common
, 0},
1255 {"file", dwarf2_directive_file
, 0},
1256 {"loc", dwarf2_directive_loc
, 0},
1257 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1260 {"secrel32", pe_directive_secrel
, 0},
1261 {"secidx", pe_directive_secidx
, 0},
1266 /* For interface with expression (). */
1267 extern char *input_line_pointer
;
1269 /* Hash table for instruction mnemonic lookup. */
1270 static htab_t op_hash
;
1272 /* Hash table for register lookup. */
1273 static htab_t reg_hash
;
1275 /* Various efficient no-op patterns for aligning code labels.
1276 Note: Don't try to assemble the instructions in the comments.
1277 0L and 0w are not legal. */
1278 static const unsigned char f32_1
[] =
1280 static const unsigned char f32_2
[] =
1281 {0x66,0x90}; /* xchg %ax,%ax */
1282 static const unsigned char f32_3
[] =
1283 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1284 static const unsigned char f32_4
[] =
1285 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1286 static const unsigned char f32_6
[] =
1287 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1288 static const unsigned char f32_7
[] =
1289 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1290 static const unsigned char f16_3
[] =
1291 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1292 static const unsigned char f16_4
[] =
1293 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1294 static const unsigned char jump_disp8
[] =
1295 {0xeb}; /* jmp disp8 */
1296 static const unsigned char jump32_disp32
[] =
1297 {0xe9}; /* jmp disp32 */
1298 static const unsigned char jump16_disp32
[] =
1299 {0x66,0xe9}; /* jmp disp32 */
1300 /* 32-bit NOPs patterns. */
1301 static const unsigned char *const f32_patt
[] = {
1302 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1304 /* 16-bit NOPs patterns. */
1305 static const unsigned char *const f16_patt
[] = {
1306 f32_1
, f32_2
, f16_3
, f16_4
1308 /* nopl (%[re]ax) */
1309 static const unsigned char alt_3
[] =
1311 /* nopl 0(%[re]ax) */
1312 static const unsigned char alt_4
[] =
1313 {0x0f,0x1f,0x40,0x00};
1314 /* nopl 0(%[re]ax,%[re]ax,1) */
1315 static const unsigned char alt_5
[] =
1316 {0x0f,0x1f,0x44,0x00,0x00};
1317 /* nopw 0(%[re]ax,%[re]ax,1) */
1318 static const unsigned char alt_6
[] =
1319 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1320 /* nopl 0L(%[re]ax) */
1321 static const unsigned char alt_7
[] =
1322 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1323 /* nopl 0L(%[re]ax,%[re]ax,1) */
1324 static const unsigned char alt_8
[] =
1325 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1326 /* nopw 0L(%[re]ax,%[re]ax,1) */
1327 static const unsigned char alt_9
[] =
1328 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1329 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1330 static const unsigned char alt_10
[] =
1331 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1332 /* data16 nopw %cs:0L(%eax,%eax,1) */
1333 static const unsigned char alt_11
[] =
1334 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1335 /* 32-bit and 64-bit NOPs patterns. */
1336 static const unsigned char *const alt_patt
[] = {
1337 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1338 alt_9
, alt_10
, alt_11
1341 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1342 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1345 i386_output_nops (char *where
, const unsigned char *const *patt
,
1346 int count
, int max_single_nop_size
)
1349 /* Place the longer NOP first. */
1352 const unsigned char *nops
;
1354 if (max_single_nop_size
< 1)
1356 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1357 max_single_nop_size
);
1361 nops
= patt
[max_single_nop_size
- 1];
1363 /* Use the smaller one if the requsted one isn't available. */
1366 max_single_nop_size
--;
1367 nops
= patt
[max_single_nop_size
- 1];
1370 last
= count
% max_single_nop_size
;
1373 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1374 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1378 nops
= patt
[last
- 1];
1381 /* Use the smaller one plus one-byte NOP if the needed one
1384 nops
= patt
[last
- 1];
1385 memcpy (where
+ offset
, nops
, last
);
1386 where
[offset
+ last
] = *patt
[0];
1389 memcpy (where
+ offset
, nops
, last
);
1394 fits_in_imm7 (offsetT num
)
1396 return (num
& 0x7f) == num
;
1400 fits_in_imm31 (offsetT num
)
1402 return (num
& 0x7fffffff) == num
;
1405 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1406 single NOP instruction LIMIT. */
1409 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1411 const unsigned char *const *patt
= NULL
;
1412 int max_single_nop_size
;
1413 /* Maximum number of NOPs before switching to jump over NOPs. */
1414 int max_number_of_nops
;
1416 switch (fragP
->fr_type
)
1421 case rs_machine_dependent
:
1422 /* Allow NOP padding for jumps and calls. */
1423 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1424 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1431 /* We need to decide which NOP sequence to use for 32bit and
1432 64bit. When -mtune= is used:
1434 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1435 PROCESSOR_GENERIC32, f32_patt will be used.
1436 2. For the rest, alt_patt will be used.
1438 When -mtune= isn't used, alt_patt will be used if
1439 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1442 When -march= or .arch is used, we can't use anything beyond
1443 cpu_arch_isa_flags. */
1445 if (flag_code
== CODE_16BIT
)
1448 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1449 /* Limit number of NOPs to 2 in 16-bit mode. */
1450 max_number_of_nops
= 2;
1454 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1456 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1457 switch (cpu_arch_tune
)
1459 case PROCESSOR_UNKNOWN
:
1460 /* We use cpu_arch_isa_flags to check if we SHOULD
1461 optimize with nops. */
1462 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1467 case PROCESSOR_PENTIUM4
:
1468 case PROCESSOR_NOCONA
:
1469 case PROCESSOR_CORE
:
1470 case PROCESSOR_CORE2
:
1471 case PROCESSOR_COREI7
:
1472 case PROCESSOR_GENERIC64
:
1474 case PROCESSOR_ATHLON
:
1476 case PROCESSOR_AMDFAM10
:
1478 case PROCESSOR_ZNVER
:
1482 case PROCESSOR_I386
:
1483 case PROCESSOR_I486
:
1484 case PROCESSOR_PENTIUM
:
1485 case PROCESSOR_PENTIUMPRO
:
1486 case PROCESSOR_IAMCU
:
1487 case PROCESSOR_GENERIC32
:
1490 case PROCESSOR_NONE
:
1496 switch (fragP
->tc_frag_data
.tune
)
1498 case PROCESSOR_UNKNOWN
:
1499 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1500 PROCESSOR_UNKNOWN. */
1504 case PROCESSOR_I386
:
1505 case PROCESSOR_I486
:
1506 case PROCESSOR_PENTIUM
:
1507 case PROCESSOR_IAMCU
:
1509 case PROCESSOR_ATHLON
:
1511 case PROCESSOR_AMDFAM10
:
1513 case PROCESSOR_ZNVER
:
1515 case PROCESSOR_GENERIC32
:
1516 /* We use cpu_arch_isa_flags to check if we CAN optimize
1518 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1523 case PROCESSOR_PENTIUMPRO
:
1524 case PROCESSOR_PENTIUM4
:
1525 case PROCESSOR_NOCONA
:
1526 case PROCESSOR_CORE
:
1527 case PROCESSOR_CORE2
:
1528 case PROCESSOR_COREI7
:
1529 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1534 case PROCESSOR_GENERIC64
:
1537 case PROCESSOR_NONE
:
1542 if (patt
== f32_patt
)
1544 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1545 /* Limit number of NOPs to 2 for older processors. */
1546 max_number_of_nops
= 2;
1550 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1551 /* Limit number of NOPs to 7 for newer processors. */
1552 max_number_of_nops
= 7;
1557 limit
= max_single_nop_size
;
1559 if (fragP
->fr_type
== rs_fill_nop
)
1561 /* Output NOPs for .nop directive. */
1562 if (limit
> max_single_nop_size
)
1564 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1565 _("invalid single nop size: %d "
1566 "(expect within [0, %d])"),
1567 limit
, max_single_nop_size
);
1571 else if (fragP
->fr_type
!= rs_machine_dependent
)
1572 fragP
->fr_var
= count
;
1574 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1576 /* Generate jump over NOPs. */
1577 offsetT disp
= count
- 2;
1578 if (fits_in_imm7 (disp
))
1580 /* Use "jmp disp8" if possible. */
1582 where
[0] = jump_disp8
[0];
1588 unsigned int size_of_jump
;
1590 if (flag_code
== CODE_16BIT
)
1592 where
[0] = jump16_disp32
[0];
1593 where
[1] = jump16_disp32
[1];
1598 where
[0] = jump32_disp32
[0];
1602 count
-= size_of_jump
+ 4;
1603 if (!fits_in_imm31 (count
))
1605 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1606 _("jump over nop padding out of range"));
1610 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1611 where
+= size_of_jump
+ 4;
1615 /* Generate multiple NOPs. */
1616 i386_output_nops (where
, patt
, count
, limit
);
1620 operand_type_all_zero (const union i386_operand_type
*x
)
1622 switch (ARRAY_SIZE(x
->array
))
1633 return !x
->array
[0];
1640 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1642 switch (ARRAY_SIZE(x
->array
))
1658 x
->bitfield
.class = ClassNone
;
1659 x
->bitfield
.instance
= InstanceNone
;
1663 operand_type_equal (const union i386_operand_type
*x
,
1664 const union i386_operand_type
*y
)
1666 switch (ARRAY_SIZE(x
->array
))
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1689 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1690 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1691 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1692 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1693 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1694 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1695 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1696 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1697 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1698 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1700 gas_assert (cpu
< CpuAttrEnums
);
1702 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1705 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1707 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1708 i386_cpu_flags f
= { .array
[0] = 0 };
1710 switch (ARRAY_SIZE(a
.array
))
1713 f
.array
[CpuAttrEnums
/ bps
]
1714 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1715 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1716 f
.array
[CpuAttrEnums
/ bps
+ 1]
1717 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1724 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1730 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1732 switch (ARRAY_SIZE(x
->array
))
1751 return !x
->array
[0];
1758 cpu_flags_equal (const union i386_cpu_flags
*x
,
1759 const union i386_cpu_flags
*y
)
1761 switch (ARRAY_SIZE(x
->array
))
1764 if (x
->array
[4] != y
->array
[4])
1768 if (x
->array
[3] != y
->array
[3])
1772 if (x
->array
[2] != y
->array
[2])
1776 if (x
->array
[1] != y
->array
[1])
1780 return x
->array
[0] == y
->array
[0];
1788 cpu_flags_check_cpu64 (i386_cpu_attr a
)
1790 return !((flag_code
== CODE_64BIT
&& a
.bitfield
.cpuno64
)
1791 || (flag_code
!= CODE_64BIT
&& a
.bitfield
.cpu64
));
1794 static INLINE i386_cpu_flags
1795 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1797 switch (ARRAY_SIZE (x
.array
))
1800 x
.array
[4] &= y
.array
[4];
1803 x
.array
[3] &= y
.array
[3];
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_cpu_flags
1821 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[4] |= y
.array
[4];
1829 x
.array
[3] |= y
.array
[3];
1832 x
.array
[2] |= y
.array
[2];
1835 x
.array
[1] |= y
.array
[1];
1838 x
.array
[0] |= y
.array
[0];
1846 static INLINE i386_cpu_flags
1847 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1849 switch (ARRAY_SIZE (x
.array
))
1852 x
.array
[4] &= ~y
.array
[4];
1855 x
.array
[3] &= ~y
.array
[3];
1858 x
.array
[2] &= ~y
.array
[2];
1861 x
.array
[1] &= ~y
.array
[1];
1864 x
.array
[0] &= ~y
.array
[0];
1872 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1874 #define CPU_FLAGS_ARCH_MATCH 0x1
1875 #define CPU_FLAGS_64BIT_MATCH 0x2
1877 #define CPU_FLAGS_PERFECT_MATCH \
1878 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1880 /* Return CPU flags match bits. */
1883 cpu_flags_match (const insn_template
*t
)
1885 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1886 int match
= cpu_flags_check_cpu64 (t
->cpu
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1888 x
.bitfield
.cpu64
= 0;
1889 x
.bitfield
.cpuno64
= 0;
1891 if (cpu_flags_all_zero (&x
))
1893 /* This instruction is available on all archs. */
1894 match
|= CPU_FLAGS_ARCH_MATCH
;
1898 /* This instruction is available only on some archs. */
1899 i386_cpu_flags cpu
= cpu_arch_flags
;
1901 /* AVX512VL is no standalone feature - match it and then strip it. */
1902 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1904 x
.bitfield
.cpuavx512vl
= 0;
1906 /* AVX and AVX2 present at the same time express an operand size
1907 dependency - strip AVX2 for the purposes here. The operand size
1908 dependent check occurs in check_vecOperands(). */
1909 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1910 x
.bitfield
.cpuavx2
= 0;
1912 cpu
= cpu_flags_and (x
, cpu
);
1913 if (!cpu_flags_all_zero (&cpu
))
1915 if (x
.bitfield
.cpuavx
)
1917 /* We need to check a few extra flags with AVX. */
1918 if (cpu
.bitfield
.cpuavx
1919 && (!t
->opcode_modifier
.sse2avx
1920 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1921 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1922 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1923 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1924 match
|= CPU_FLAGS_ARCH_MATCH
;
1926 else if (x
.bitfield
.cpuavx512f
)
1928 /* We need to check a few extra flags with AVX512F. */
1929 if (cpu
.bitfield
.cpuavx512f
1930 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1931 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1932 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1933 match
|= CPU_FLAGS_ARCH_MATCH
;
1936 match
|= CPU_FLAGS_ARCH_MATCH
;
1942 static INLINE i386_operand_type
1943 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1945 if (x
.bitfield
.class != y
.bitfield
.class)
1946 x
.bitfield
.class = ClassNone
;
1947 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1948 x
.bitfield
.instance
= InstanceNone
;
1950 switch (ARRAY_SIZE (x
.array
))
1953 x
.array
[2] &= y
.array
[2];
1956 x
.array
[1] &= y
.array
[1];
1959 x
.array
[0] &= y
.array
[0];
1967 static INLINE i386_operand_type
1968 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1970 gas_assert (y
.bitfield
.class == ClassNone
);
1971 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1973 switch (ARRAY_SIZE (x
.array
))
1976 x
.array
[2] &= ~y
.array
[2];
1979 x
.array
[1] &= ~y
.array
[1];
1982 x
.array
[0] &= ~y
.array
[0];
1990 static INLINE i386_operand_type
1991 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1993 gas_assert (x
.bitfield
.class == ClassNone
||
1994 y
.bitfield
.class == ClassNone
||
1995 x
.bitfield
.class == y
.bitfield
.class);
1996 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1997 y
.bitfield
.instance
== InstanceNone
||
1998 x
.bitfield
.instance
== y
.bitfield
.instance
);
2000 switch (ARRAY_SIZE (x
.array
))
2003 x
.array
[2] |= y
.array
[2];
2006 x
.array
[1] |= y
.array
[1];
2009 x
.array
[0] |= y
.array
[0];
2017 static INLINE i386_operand_type
2018 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2020 gas_assert (y
.bitfield
.class == ClassNone
);
2021 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2023 switch (ARRAY_SIZE (x
.array
))
2026 x
.array
[2] ^= y
.array
[2];
2029 x
.array
[1] ^= y
.array
[1];
2032 x
.array
[0] ^= y
.array
[0];
2040 static const i386_operand_type anydisp
= {
2041 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2053 operand_type_check (i386_operand_type t
, enum operand_type c
)
2058 return t
.bitfield
.class == Reg
;
2061 return (t
.bitfield
.imm8
2065 || t
.bitfield
.imm32s
2066 || t
.bitfield
.imm64
);
2069 return (t
.bitfield
.disp8
2070 || t
.bitfield
.disp16
2071 || t
.bitfield
.disp32
2072 || t
.bitfield
.disp64
);
2075 return (t
.bitfield
.disp8
2076 || t
.bitfield
.disp16
2077 || t
.bitfield
.disp32
2078 || t
.bitfield
.disp64
2079 || t
.bitfield
.baseindex
);
2088 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2089 between operand GIVEN and opeand WANTED for instruction template T. */
2092 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2095 return !((i
.types
[given
].bitfield
.byte
2096 && !t
->operand_types
[wanted
].bitfield
.byte
)
2097 || (i
.types
[given
].bitfield
.word
2098 && !t
->operand_types
[wanted
].bitfield
.word
)
2099 || (i
.types
[given
].bitfield
.dword
2100 && !t
->operand_types
[wanted
].bitfield
.dword
)
2101 || (i
.types
[given
].bitfield
.qword
2102 && (!t
->operand_types
[wanted
].bitfield
.qword
2103 /* Don't allow 64-bit (memory) operands outside of 64-bit
2104 mode, when they're used where a 64-bit GPR could also
2105 be used. Checking is needed for Intel Syntax only. */
2107 && flag_code
!= CODE_64BIT
2108 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2109 || t
->operand_types
[wanted
].bitfield
.class == Accum
2110 || t
->opcode_modifier
.isstring
))))
2111 || (i
.types
[given
].bitfield
.tbyte
2112 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2115 /* Return 1 if there is no conflict in SIMD register between operand
2116 GIVEN and opeand WANTED for instruction template T. */
2119 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2122 return !((i
.types
[given
].bitfield
.xmmword
2123 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2124 || (i
.types
[given
].bitfield
.ymmword
2125 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2126 || (i
.types
[given
].bitfield
.zmmword
2127 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2128 || (i
.types
[given
].bitfield
.tmmword
2129 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2132 /* Return 1 if there is no conflict in any size between operand GIVEN
2133 and opeand WANTED for instruction template T. */
2136 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2139 return (match_operand_size (t
, wanted
, given
)
2140 && !((i
.types
[given
].bitfield
.unspecified
2141 && !i
.broadcast
.type
2142 && !i
.broadcast
.bytes
2143 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2144 || (i
.types
[given
].bitfield
.fword
2145 && !t
->operand_types
[wanted
].bitfield
.fword
)
2146 /* For scalar opcode templates to allow register and memory
2147 operands at the same time, some special casing is needed
2148 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2149 down-conversion vpmov*. */
2150 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2151 && t
->operand_types
[wanted
].bitfield
.byte
2152 + t
->operand_types
[wanted
].bitfield
.word
2153 + t
->operand_types
[wanted
].bitfield
.dword
2154 + t
->operand_types
[wanted
].bitfield
.qword
2155 > !!t
->opcode_modifier
.broadcast
)
2156 ? (i
.types
[given
].bitfield
.xmmword
2157 || i
.types
[given
].bitfield
.ymmword
2158 || i
.types
[given
].bitfield
.zmmword
)
2159 : !match_simd_size(t
, wanted
, given
))));
2162 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2163 operands for instruction template T, and it has MATCH_REVERSE set if there
2164 is no size conflict on any operands for the template with operands reversed
2165 (and the template allows for reversing in the first place). */
2167 #define MATCH_STRAIGHT 1
2168 #define MATCH_REVERSE 2
2170 static INLINE
unsigned int
2171 operand_size_match (const insn_template
*t
)
2173 unsigned int j
, match
= MATCH_STRAIGHT
;
2175 /* Don't check non-absolute jump instructions. */
2176 if (t
->opcode_modifier
.jump
2177 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2180 /* Check memory and accumulator operand size. */
2181 for (j
= 0; j
< i
.operands
; j
++)
2183 if (i
.types
[j
].bitfield
.class != Reg
2184 && i
.types
[j
].bitfield
.class != RegSIMD
2185 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2188 if (t
->operand_types
[j
].bitfield
.class == Reg
2189 && !match_operand_size (t
, j
, j
))
2195 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2196 && !match_simd_size (t
, j
, j
))
2202 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2203 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2209 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2216 if (!t
->opcode_modifier
.d
)
2219 /* Check reverse. */
2220 gas_assert (i
.operands
>= 2);
2222 for (j
= 0; j
< i
.operands
; j
++)
2224 unsigned int given
= i
.operands
- j
- 1;
2226 /* For FMA4 and XOP insns VEX.W controls just the first two
2227 register operands. */
2228 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2229 given
= j
< 2 ? 1 - j
: j
;
2231 if (t
->operand_types
[j
].bitfield
.class == Reg
2232 && !match_operand_size (t
, j
, given
))
2235 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2236 && !match_simd_size (t
, j
, given
))
2239 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2240 && (!match_operand_size (t
, j
, given
)
2241 || !match_simd_size (t
, j
, given
)))
2244 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2248 return match
| MATCH_REVERSE
;
2252 operand_type_match (i386_operand_type overlap
,
2253 i386_operand_type given
)
2255 i386_operand_type temp
= overlap
;
2257 temp
.bitfield
.unspecified
= 0;
2258 temp
.bitfield
.byte
= 0;
2259 temp
.bitfield
.word
= 0;
2260 temp
.bitfield
.dword
= 0;
2261 temp
.bitfield
.fword
= 0;
2262 temp
.bitfield
.qword
= 0;
2263 temp
.bitfield
.tbyte
= 0;
2264 temp
.bitfield
.xmmword
= 0;
2265 temp
.bitfield
.ymmword
= 0;
2266 temp
.bitfield
.zmmword
= 0;
2267 temp
.bitfield
.tmmword
= 0;
2268 if (operand_type_all_zero (&temp
))
2271 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2275 i
.error
= operand_type_mismatch
;
2279 /* If given types g0 and g1 are registers they must be of the same type
2280 unless the expected operand type register overlap is null.
2281 Intel syntax sized memory operands are also checked here. */
2284 operand_type_register_match (i386_operand_type g0
,
2285 i386_operand_type t0
,
2286 i386_operand_type g1
,
2287 i386_operand_type t1
)
2289 if (g0
.bitfield
.class != Reg
2290 && g0
.bitfield
.class != RegSIMD
2291 && (g0
.bitfield
.unspecified
2292 || !operand_type_check (g0
, anymem
)))
2295 if (g1
.bitfield
.class != Reg
2296 && g1
.bitfield
.class != RegSIMD
2297 && (g1
.bitfield
.unspecified
2298 || !operand_type_check (g1
, anymem
)))
2301 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2302 && g0
.bitfield
.word
== g1
.bitfield
.word
2303 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2304 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2305 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2306 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2307 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2310 /* If expectations overlap in no more than a single size, all is fine. */
2311 g0
= operand_type_and (t0
, t1
);
2312 if (g0
.bitfield
.byte
2316 + g0
.bitfield
.xmmword
2317 + g0
.bitfield
.ymmword
2318 + g0
.bitfield
.zmmword
<= 1)
2321 i
.error
= register_type_mismatch
;
2326 static INLINE
unsigned int
2327 register_number (const reg_entry
*r
)
2329 unsigned int nr
= r
->reg_num
;
2331 if (r
->reg_flags
& RegRex
)
2334 if (r
->reg_flags
& RegVRex
)
2340 static INLINE
unsigned int
2341 mode_from_disp_size (i386_operand_type t
)
2343 if (t
.bitfield
.disp8
)
2345 else if (t
.bitfield
.disp16
2346 || t
.bitfield
.disp32
)
2353 fits_in_signed_byte (addressT num
)
2355 return num
+ 0x80 <= 0xff;
2359 fits_in_unsigned_byte (addressT num
)
2365 fits_in_unsigned_word (addressT num
)
2367 return num
<= 0xffff;
2371 fits_in_signed_word (addressT num
)
2373 return num
+ 0x8000 <= 0xffff;
2377 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2382 return num
+ 0x80000000 <= 0xffffffff;
2384 } /* fits_in_signed_long() */
2387 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2392 return num
<= 0xffffffff;
2394 } /* fits_in_unsigned_long() */
2396 static INLINE valueT
extend_to_32bit_address (addressT num
)
2399 if (fits_in_unsigned_long(num
))
2400 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2402 if (!fits_in_signed_long (num
))
2403 return num
& 0xffffffff;
2410 fits_in_disp8 (offsetT num
)
2412 int shift
= i
.memshift
;
2418 mask
= (1 << shift
) - 1;
2420 /* Return 0 if NUM isn't properly aligned. */
2424 /* Check if NUM will fit in 8bit after shift. */
2425 return fits_in_signed_byte (num
>> shift
);
2429 fits_in_imm4 (offsetT num
)
2431 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2432 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2435 static i386_operand_type
2436 smallest_imm_type (offsetT num
)
2438 i386_operand_type t
;
2440 operand_type_set (&t
, 0);
2441 t
.bitfield
.imm64
= 1;
2443 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2445 /* This code is disabled on the 486 because all the Imm1 forms
2446 in the opcode table are slower on the i486. They're the
2447 versions with the implicitly specified single-position
2448 displacement, which has another syntax if you really want to
2450 t
.bitfield
.imm1
= 1;
2451 t
.bitfield
.imm8
= 1;
2452 t
.bitfield
.imm8s
= 1;
2453 t
.bitfield
.imm16
= 1;
2454 t
.bitfield
.imm32
= 1;
2455 t
.bitfield
.imm32s
= 1;
2457 else if (fits_in_signed_byte (num
))
2459 if (fits_in_unsigned_byte (num
))
2460 t
.bitfield
.imm8
= 1;
2461 t
.bitfield
.imm8s
= 1;
2462 t
.bitfield
.imm16
= 1;
2463 t
.bitfield
.imm32
= 1;
2464 t
.bitfield
.imm32s
= 1;
2466 else if (fits_in_unsigned_byte (num
))
2468 t
.bitfield
.imm8
= 1;
2469 t
.bitfield
.imm16
= 1;
2470 t
.bitfield
.imm32
= 1;
2471 t
.bitfield
.imm32s
= 1;
2473 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2475 t
.bitfield
.imm16
= 1;
2476 t
.bitfield
.imm32
= 1;
2477 t
.bitfield
.imm32s
= 1;
2479 else if (fits_in_signed_long (num
))
2481 t
.bitfield
.imm32
= 1;
2482 t
.bitfield
.imm32s
= 1;
2484 else if (fits_in_unsigned_long (num
))
2485 t
.bitfield
.imm32
= 1;
2491 offset_in_range (offsetT val
, int size
)
2497 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2498 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2500 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2502 case sizeof (val
): return val
;
2506 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2507 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2508 (uint64_t) val
, (uint64_t) (val
& mask
));
2513 static INLINE
const char *insn_name (const insn_template
*t
)
2515 return &i386_mnemonics
[t
->mnem_off
];
2528 a. PREFIX_EXIST if attempting to add a prefix where one from the
2529 same class already exists.
2530 b. PREFIX_LOCK if lock prefix is added.
2531 c. PREFIX_REP if rep/repne prefix is added.
2532 d. PREFIX_DS if ds prefix is added.
2533 e. PREFIX_OTHER if other prefix is added.
2536 static enum PREFIX_GROUP
2537 add_prefix (unsigned int prefix
)
2539 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2542 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2543 && flag_code
== CODE_64BIT
)
2545 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2546 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2547 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2548 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2559 case DS_PREFIX_OPCODE
:
2562 case CS_PREFIX_OPCODE
:
2563 case ES_PREFIX_OPCODE
:
2564 case FS_PREFIX_OPCODE
:
2565 case GS_PREFIX_OPCODE
:
2566 case SS_PREFIX_OPCODE
:
2570 case REPNE_PREFIX_OPCODE
:
2571 case REPE_PREFIX_OPCODE
:
2576 case LOCK_PREFIX_OPCODE
:
2585 case ADDR_PREFIX_OPCODE
:
2589 case DATA_PREFIX_OPCODE
:
2593 if (i
.prefix
[q
] != 0)
2601 i
.prefix
[q
] |= prefix
;
2604 as_bad (_("same type of prefix used twice"));
2610 update_code_flag (int value
, int check
)
2612 PRINTF_LIKE ((*as_error
));
2614 flag_code
= (enum flag_code
) value
;
2615 if (flag_code
== CODE_64BIT
)
2617 cpu_arch_flags
.bitfield
.cpu64
= 1;
2618 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2622 cpu_arch_flags
.bitfield
.cpu64
= 0;
2623 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2625 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2628 as_error
= as_fatal
;
2631 (*as_error
) (_("64bit mode not supported on `%s'."),
2632 cpu_arch_name
? cpu_arch_name
: default_arch
);
2634 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2637 as_error
= as_fatal
;
2640 (*as_error
) (_("32bit mode not supported on `%s'."),
2641 cpu_arch_name
? cpu_arch_name
: default_arch
);
2643 stackop_size
= '\0';
2647 set_code_flag (int value
)
2649 update_code_flag (value
, 0);
2653 set_16bit_gcc_code_flag (int new_code_flag
)
2655 flag_code
= (enum flag_code
) new_code_flag
;
2656 if (flag_code
!= CODE_16BIT
)
2658 cpu_arch_flags
.bitfield
.cpu64
= 0;
2659 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2660 stackop_size
= LONG_MNEM_SUFFIX
;
2664 set_intel_syntax (int syntax_flag
)
2666 /* Find out if register prefixing is specified. */
2667 int ask_naked_reg
= 0;
2670 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2673 int e
= get_symbol_name (&string
);
2675 if (strcmp (string
, "prefix") == 0)
2677 else if (strcmp (string
, "noprefix") == 0)
2680 as_bad (_("bad argument to syntax directive."));
2681 (void) restore_line_pointer (e
);
2683 demand_empty_rest_of_line ();
2685 intel_syntax
= syntax_flag
;
2687 if (ask_naked_reg
== 0)
2688 allow_naked_reg
= (intel_syntax
2689 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2691 allow_naked_reg
= (ask_naked_reg
< 0);
2693 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2695 register_prefix
= allow_naked_reg
? "" : "%";
2699 set_intel_mnemonic (int mnemonic_flag
)
2701 intel_mnemonic
= mnemonic_flag
;
2705 set_allow_index_reg (int flag
)
2707 allow_index_reg
= flag
;
2711 set_check (int what
)
2713 enum check_kind
*kind
;
2718 kind
= &operand_check
;
2729 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2732 int e
= get_symbol_name (&string
);
2734 if (strcmp (string
, "none") == 0)
2736 else if (strcmp (string
, "warning") == 0)
2737 *kind
= check_warning
;
2738 else if (strcmp (string
, "error") == 0)
2739 *kind
= check_error
;
2741 as_bad (_("bad argument to %s_check directive."), str
);
2742 (void) restore_line_pointer (e
);
2745 as_bad (_("missing argument for %s_check directive"), str
);
2747 demand_empty_rest_of_line ();
2751 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2752 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2755 static const char *arch
;
2757 /* Intel MCU is only supported on ELF. */
2763 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2764 use default_arch. */
2765 arch
= cpu_arch_name
;
2767 arch
= default_arch
;
2770 /* If we are targeting Intel MCU, we must enable it. */
2771 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2772 == new_flag
.bitfield
.cpuiamcu
)
2775 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2780 extend_cpu_sub_arch_name (const char *name
)
2782 if (cpu_sub_arch_name
)
2783 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2784 ".", name
, (const char *) NULL
);
2786 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2790 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2792 typedef struct arch_stack_entry
2794 const struct arch_stack_entry
*prev
;
2797 i386_cpu_flags flags
;
2798 i386_cpu_flags isa_flags
;
2799 enum processor_type isa
;
2800 enum flag_code flag_code
;
2801 unsigned int vector_size
;
2803 bool no_cond_jump_promotion
;
2805 static const arch_stack_entry
*arch_stack_top
;
2810 i386_cpu_flags flags
;
2814 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2816 as_bad (_("missing cpu architecture"));
2817 input_line_pointer
++;
2821 e
= get_symbol_name (&s
);
2824 if (strcmp (string
, "push") == 0)
2826 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2828 top
->name
= cpu_arch_name
;
2829 if (cpu_sub_arch_name
)
2830 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2832 top
->sub_name
= NULL
;
2833 top
->flags
= cpu_arch_flags
;
2834 top
->isa
= cpu_arch_isa
;
2835 top
->isa_flags
= cpu_arch_isa_flags
;
2836 top
->flag_code
= flag_code
;
2837 top
->vector_size
= vector_size
;
2838 top
->stackop_size
= stackop_size
;
2839 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2841 top
->prev
= arch_stack_top
;
2842 arch_stack_top
= top
;
2844 (void) restore_line_pointer (e
);
2845 demand_empty_rest_of_line ();
2849 if (strcmp (string
, "pop") == 0)
2851 const arch_stack_entry
*top
= arch_stack_top
;
2854 as_bad (_(".arch stack is empty"));
2855 else if (top
->flag_code
!= flag_code
2856 || top
->stackop_size
!= stackop_size
)
2858 static const unsigned int bits
[] = {
2864 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2865 bits
[top
->flag_code
],
2866 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2870 arch_stack_top
= top
->prev
;
2872 cpu_arch_name
= top
->name
;
2873 free (cpu_sub_arch_name
);
2874 cpu_sub_arch_name
= top
->sub_name
;
2875 cpu_arch_flags
= top
->flags
;
2876 cpu_arch_isa
= top
->isa
;
2877 cpu_arch_isa_flags
= top
->isa_flags
;
2878 vector_size
= top
->vector_size
;
2879 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2884 (void) restore_line_pointer (e
);
2885 demand_empty_rest_of_line ();
2889 if (strcmp (string
, "default") == 0)
2891 if (strcmp (default_arch
, "iamcu") == 0)
2892 string
= default_arch
;
2895 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2897 cpu_arch_name
= NULL
;
2898 free (cpu_sub_arch_name
);
2899 cpu_sub_arch_name
= NULL
;
2900 cpu_arch_flags
= cpu_unknown_flags
;
2901 if (flag_code
== CODE_64BIT
)
2903 cpu_arch_flags
.bitfield
.cpu64
= 1;
2904 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2908 cpu_arch_flags
.bitfield
.cpu64
= 0;
2909 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2911 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2912 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2913 if (!cpu_arch_tune_set
)
2915 cpu_arch_tune
= cpu_arch_isa
;
2916 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2919 vector_size
= VSZ_DEFAULT
;
2921 j
= ARRAY_SIZE (cpu_arch
) + 1;
2925 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2927 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2928 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2932 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2934 cpu_arch_name
= cpu_arch
[j
].name
;
2935 free (cpu_sub_arch_name
);
2936 cpu_sub_arch_name
= NULL
;
2937 cpu_arch_flags
= cpu_arch
[j
].enable
;
2938 if (flag_code
== CODE_64BIT
)
2940 cpu_arch_flags
.bitfield
.cpu64
= 1;
2941 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2945 cpu_arch_flags
.bitfield
.cpu64
= 0;
2946 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2948 cpu_arch_isa
= cpu_arch
[j
].type
;
2949 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2950 if (!cpu_arch_tune_set
)
2952 cpu_arch_tune
= cpu_arch_isa
;
2953 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2956 vector_size
= VSZ_DEFAULT
;
2958 pre_386_16bit_warned
= false;
2962 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2965 flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[j
].enable
);
2967 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2969 extend_cpu_sub_arch_name (string
+ 1);
2970 cpu_arch_flags
= flags
;
2971 cpu_arch_isa_flags
= flags
;
2975 = cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[j
].enable
);
2977 (void) restore_line_pointer (e
);
2979 switch (cpu_arch
[j
].vsz
)
2985 #ifdef SVR4_COMMENT_CHARS
2986 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2988 if (*input_line_pointer
== '/')
2991 ++input_line_pointer
;
2992 switch (get_absolute_expression ())
2994 case 512: vector_size
= VSZ512
; break;
2995 case 256: vector_size
= VSZ256
; break;
2996 case 128: vector_size
= VSZ128
; break;
2998 as_bad (_("Unrecognized vector size specifier"));
2999 ignore_rest_of_line ();
3006 vector_size
= VSZ_DEFAULT
;
3010 demand_empty_rest_of_line ();
3015 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3017 /* Disable an ISA extension. */
3018 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3019 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3020 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3022 flags
= cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[j
].disable
);
3023 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
3025 extend_cpu_sub_arch_name (string
+ 1);
3026 cpu_arch_flags
= flags
;
3027 cpu_arch_isa_flags
= flags
;
3030 if (cpu_arch
[j
].vsz
== vsz_set
)
3031 vector_size
= VSZ_DEFAULT
;
3033 (void) restore_line_pointer (e
);
3034 demand_empty_rest_of_line ();
3039 if (j
== ARRAY_SIZE (cpu_arch
))
3040 as_bad (_("no such architecture: `%s'"), string
);
3042 *input_line_pointer
= e
;
3044 no_cond_jump_promotion
= 0;
3045 if (*input_line_pointer
== ','
3046 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3048 ++input_line_pointer
;
3049 e
= get_symbol_name (&s
);
3052 if (strcmp (string
, "nojumps") == 0)
3053 no_cond_jump_promotion
= 1;
3054 else if (strcmp (string
, "jumps") == 0)
3057 as_bad (_("no such architecture modifier: `%s'"), string
);
3059 (void) restore_line_pointer (e
);
3062 demand_empty_rest_of_line ();
3065 enum bfd_architecture
3068 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3070 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3071 || flag_code
== CODE_64BIT
)
3072 as_fatal (_("Intel MCU is 32bit ELF only"));
3073 return bfd_arch_iamcu
;
3076 return bfd_arch_i386
;
3082 if (startswith (default_arch
, "x86_64"))
3084 if (default_arch
[6] == '\0')
3085 return bfd_mach_x86_64
;
3087 return bfd_mach_x64_32
;
3089 else if (!strcmp (default_arch
, "i386")
3090 || !strcmp (default_arch
, "iamcu"))
3092 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3094 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3095 as_fatal (_("Intel MCU is 32bit ELF only"));
3096 return bfd_mach_i386_iamcu
;
3099 return bfd_mach_i386_i386
;
3102 as_fatal (_("unknown architecture"));
3105 #include "opcodes/i386-tbl.h"
3110 /* Support pseudo prefixes like {disp32}. */
3111 lex_type
['{'] = LEX_BEGIN_NAME
;
3113 /* Initialize op_hash hash table. */
3114 op_hash
= str_htab_create ();
3117 const insn_template
*const *sets
= i386_op_sets
;
3118 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3120 /* Type checks to compensate for the conversion through void * which
3121 occurs during hash table insertion / lookup. */
3122 (void) sizeof (sets
== ¤t_templates
->start
);
3123 (void) sizeof (end
== ¤t_templates
->end
);
3124 for (; sets
< end
; ++sets
)
3125 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3126 as_fatal (_("duplicate %s"), insn_name (*sets
));
3129 /* Initialize reg_hash hash table. */
3130 reg_hash
= str_htab_create ();
3132 const reg_entry
*regtab
;
3133 unsigned int regtab_size
= i386_regtab_size
;
3135 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3137 switch (regtab
->reg_type
.bitfield
.class)
3140 if (regtab
->reg_type
.bitfield
.dword
)
3142 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3145 else if (regtab
->reg_type
.bitfield
.tbyte
)
3147 /* There's no point inserting st(<N>) in the hash table, as
3148 parentheses aren't included in register_chars[] anyway. */
3149 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3156 switch (regtab
->reg_num
)
3158 case 0: reg_es
= regtab
; break;
3159 case 2: reg_ss
= regtab
; break;
3160 case 3: reg_ds
= regtab
; break;
3165 if (!regtab
->reg_num
)
3170 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3171 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3175 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3180 for (c
= 0; c
< 256; c
++)
3182 if (ISDIGIT (c
) || ISLOWER (c
))
3184 mnemonic_chars
[c
] = c
;
3185 register_chars
[c
] = c
;
3186 operand_chars
[c
] = c
;
3188 else if (ISUPPER (c
))
3190 mnemonic_chars
[c
] = TOLOWER (c
);
3191 register_chars
[c
] = mnemonic_chars
[c
];
3192 operand_chars
[c
] = c
;
3194 #ifdef SVR4_COMMENT_CHARS
3195 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3196 operand_chars
[c
] = c
;
3200 operand_chars
[c
] = c
;
3203 mnemonic_chars
['_'] = '_';
3204 mnemonic_chars
['-'] = '-';
3205 mnemonic_chars
['.'] = '.';
3207 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3208 operand_chars
[(unsigned char) *p
] = *p
;
3209 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3210 operand_chars
[(unsigned char) *p
] = *p
;
3213 if (flag_code
== CODE_64BIT
)
3215 #if defined (OBJ_COFF) && defined (TE_PE)
3216 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3219 x86_dwarf2_return_column
= 16;
3221 x86_cie_data_alignment
= -8;
3222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3223 x86_sframe_cfa_sp_reg
= 7;
3224 x86_sframe_cfa_fp_reg
= 6;
3229 x86_dwarf2_return_column
= 8;
3230 x86_cie_data_alignment
= -4;
3233 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3234 can be turned into BRANCH_PREFIX frag. */
3235 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3240 i386_print_statistics (FILE *file
)
3242 htab_print_statistics (file
, "i386 opcode", op_hash
);
3243 htab_print_statistics (file
, "i386 register", reg_hash
);
3249 htab_delete (op_hash
);
3250 htab_delete (reg_hash
);
3255 /* Debugging routines for md_assemble. */
3256 static void pte (insn_template
*);
3257 static void pt (i386_operand_type
);
3258 static void pe (expressionS
*);
3259 static void ps (symbolS
*);
3262 pi (const char *line
, i386_insn
*x
)
3266 fprintf (stdout
, "%s: template ", line
);
3268 fprintf (stdout
, " address: base %s index %s scale %x\n",
3269 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3270 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3271 x
->log2_scale_factor
);
3272 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3273 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3274 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3275 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3276 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3277 (x
->rex
& REX_W
) != 0,
3278 (x
->rex
& REX_R
) != 0,
3279 (x
->rex
& REX_X
) != 0,
3280 (x
->rex
& REX_B
) != 0);
3281 for (j
= 0; j
< x
->operands
; j
++)
3283 fprintf (stdout
, " #%d: ", j
+ 1);
3285 fprintf (stdout
, "\n");
3286 if (x
->types
[j
].bitfield
.class == Reg
3287 || x
->types
[j
].bitfield
.class == RegMMX
3288 || x
->types
[j
].bitfield
.class == RegSIMD
3289 || x
->types
[j
].bitfield
.class == RegMask
3290 || x
->types
[j
].bitfield
.class == SReg
3291 || x
->types
[j
].bitfield
.class == RegCR
3292 || x
->types
[j
].bitfield
.class == RegDR
3293 || x
->types
[j
].bitfield
.class == RegTR
3294 || x
->types
[j
].bitfield
.class == RegBND
)
3295 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3296 if (operand_type_check (x
->types
[j
], imm
))
3298 if (operand_type_check (x
->types
[j
], disp
))
3299 pe (x
->op
[j
].disps
);
3304 pte (insn_template
*t
)
3306 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3307 static const char *const opc_spc
[] = {
3308 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3309 "XOP08", "XOP09", "XOP0A",
3313 fprintf (stdout
, " %d operands ", t
->operands
);
3314 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3315 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3316 if (opc_spc
[t
->opcode_space
])
3317 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3318 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3319 if (t
->extension_opcode
!= None
)
3320 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3321 if (t
->opcode_modifier
.d
)
3322 fprintf (stdout
, "D");
3323 if (t
->opcode_modifier
.w
)
3324 fprintf (stdout
, "W");
3325 fprintf (stdout
, "\n");
3326 for (j
= 0; j
< t
->operands
; j
++)
3328 fprintf (stdout
, " #%d type ", j
+ 1);
3329 pt (t
->operand_types
[j
]);
3330 fprintf (stdout
, "\n");
3337 fprintf (stdout
, " operation %d\n", e
->X_op
);
3338 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3339 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3340 if (e
->X_add_symbol
)
3342 fprintf (stdout
, " add_symbol ");
3343 ps (e
->X_add_symbol
);
3344 fprintf (stdout
, "\n");
3348 fprintf (stdout
, " op_symbol ");
3349 ps (e
->X_op_symbol
);
3350 fprintf (stdout
, "\n");
3357 fprintf (stdout
, "%s type %s%s",
3359 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3360 segment_name (S_GET_SEGMENT (s
)));
3363 static struct type_name
3365 i386_operand_type mask
;
3368 const type_names
[] =
3370 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3371 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3372 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3373 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3374 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3375 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3376 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3377 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3378 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3379 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3380 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3381 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3382 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3383 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3384 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3385 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3386 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3387 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3388 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3389 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3390 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3391 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3392 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3393 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3394 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3395 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3396 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3397 { { .bitfield
= { .class = SReg
} }, "SReg" },
3398 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3399 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3400 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3401 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3402 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3403 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3407 pt (i386_operand_type t
)
3410 i386_operand_type a
;
3412 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3414 a
= operand_type_and (t
, type_names
[j
].mask
);
3415 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3416 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3421 #endif /* DEBUG386 */
3423 static bfd_reloc_code_real_type
3424 reloc (unsigned int size
,
3427 bfd_reloc_code_real_type other
)
3429 if (other
!= NO_RELOC
)
3431 reloc_howto_type
*rel
;
3436 case BFD_RELOC_X86_64_GOT32
:
3437 return BFD_RELOC_X86_64_GOT64
;
3439 case BFD_RELOC_X86_64_GOTPLT64
:
3440 return BFD_RELOC_X86_64_GOTPLT64
;
3442 case BFD_RELOC_X86_64_PLTOFF64
:
3443 return BFD_RELOC_X86_64_PLTOFF64
;
3445 case BFD_RELOC_X86_64_GOTPC32
:
3446 other
= BFD_RELOC_X86_64_GOTPC64
;
3448 case BFD_RELOC_X86_64_GOTPCREL
:
3449 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3451 case BFD_RELOC_X86_64_TPOFF32
:
3452 other
= BFD_RELOC_X86_64_TPOFF64
;
3454 case BFD_RELOC_X86_64_DTPOFF32
:
3455 other
= BFD_RELOC_X86_64_DTPOFF64
;
3461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3462 if (other
== BFD_RELOC_SIZE32
)
3465 other
= BFD_RELOC_SIZE64
;
3468 as_bad (_("there are no pc-relative size relocations"));
3474 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3475 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3478 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3480 as_bad (_("unknown relocation (%u)"), other
);
3481 else if (size
!= bfd_get_reloc_size (rel
))
3482 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3483 bfd_get_reloc_size (rel
),
3485 else if (pcrel
&& !rel
->pc_relative
)
3486 as_bad (_("non-pc-relative relocation for pc-relative field"));
3487 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3489 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3491 as_bad (_("relocated field and relocation type differ in signedness"));
3500 as_bad (_("there are no unsigned pc-relative relocations"));
3503 case 1: return BFD_RELOC_8_PCREL
;
3504 case 2: return BFD_RELOC_16_PCREL
;
3505 case 4: return BFD_RELOC_32_PCREL
;
3506 case 8: return BFD_RELOC_64_PCREL
;
3508 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3515 case 4: return BFD_RELOC_X86_64_32S
;
3520 case 1: return BFD_RELOC_8
;
3521 case 2: return BFD_RELOC_16
;
3522 case 4: return BFD_RELOC_32
;
3523 case 8: return BFD_RELOC_64
;
3525 as_bad (_("cannot do %s %u byte relocation"),
3526 sign
> 0 ? "signed" : "unsigned", size
);
3532 /* Here we decide which fixups can be adjusted to make them relative to
3533 the beginning of the section instead of the symbol. Basically we need
3534 to make sure that the dynamic relocations are done correctly, so in
3535 some cases we force the original symbol to be used. */
3538 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3544 /* Don't adjust pc-relative references to merge sections in 64-bit
3546 if (use_rela_relocations
3547 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3551 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3552 and changed later by validate_fix. */
3553 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3554 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3557 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3558 for size relocations. */
3559 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3560 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3561 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3562 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3563 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3564 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3565 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3566 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3574 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3575 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3576 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3588 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3589 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3596 want_disp32 (const insn_template
*t
)
3598 return flag_code
!= CODE_64BIT
3599 || i
.prefix
[ADDR_PREFIX
]
3600 || (t
->mnem_off
== MN_lea
3601 && (!i
.types
[1].bitfield
.qword
3602 || t
->opcode_modifier
.size
== SIZE32
));
3606 intel_float_operand (const char *mnemonic
)
3608 /* Note that the value returned is meaningful only for opcodes with (memory)
3609 operands, hence the code here is free to improperly handle opcodes that
3610 have no operands (for better performance and smaller code). */
3612 if (mnemonic
[0] != 'f')
3613 return 0; /* non-math */
3615 switch (mnemonic
[1])
3617 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3618 the fs segment override prefix not currently handled because no
3619 call path can make opcodes without operands get here */
3621 return 2 /* integer op */;
3623 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3624 return 3; /* fldcw/fldenv */
3627 if (mnemonic
[2] != 'o' /* fnop */)
3628 return 3; /* non-waiting control op */
3631 if (mnemonic
[2] == 's')
3632 return 3; /* frstor/frstpm */
3635 if (mnemonic
[2] == 'a')
3636 return 3; /* fsave */
3637 if (mnemonic
[2] == 't')
3639 switch (mnemonic
[3])
3641 case 'c': /* fstcw */
3642 case 'd': /* fstdw */
3643 case 'e': /* fstenv */
3644 case 's': /* fsts[gw] */
3650 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3651 return 0; /* fxsave/fxrstor are not really math ops */
3659 install_template (const insn_template
*t
)
3665 /* Note that for pseudo prefixes this produces a length of 1. But for them
3666 the length isn't interesting at all. */
3667 for (l
= 1; l
< 4; ++l
)
3668 if (!(t
->base_opcode
>> (8 * l
)))
3671 i
.opcode_length
= l
;
3674 /* Build the VEX prefix. */
3677 build_vex_prefix (const insn_template
*t
)
3679 unsigned int register_specifier
;
3680 unsigned int vector_length
;
3683 /* Check register specifier. */
3684 if (i
.vex
.register_specifier
)
3686 register_specifier
=
3687 ~register_number (i
.vex
.register_specifier
) & 0xf;
3688 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3691 register_specifier
= 0xf;
3693 /* Use 2-byte VEX prefix by swapping destination and source operand
3694 if there are more than 1 register operand. */
3695 if (i
.reg_operands
> 1
3696 && i
.vec_encoding
!= vex_encoding_vex3
3697 && i
.dir_encoding
== dir_encoding_default
3698 && i
.operands
== i
.reg_operands
3699 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3700 && i
.tm
.opcode_space
== SPACE_0F
3701 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3706 swap_2_operands (0, i
.operands
- 1);
3708 gas_assert (i
.rm
.mode
== 3);
3712 i
.rm
.regmem
= i
.rm
.reg
;
3715 if (i
.tm
.opcode_modifier
.d
)
3716 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3717 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3718 else /* Use the next insn. */
3719 install_template (&t
[1]);
3722 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3723 are no memory operands and at least 3 register ones. */
3724 if (i
.reg_operands
>= 3
3725 && i
.vec_encoding
!= vex_encoding_vex3
3726 && i
.reg_operands
== i
.operands
- i
.imm_operands
3727 && i
.tm
.opcode_modifier
.vex
3728 && i
.tm
.opcode_modifier
.commutative
3729 && (i
.tm
.opcode_modifier
.sse2avx
3730 || (optimize
> 1 && !i
.no_optimize
))
3732 && i
.vex
.register_specifier
3733 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3735 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3737 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3738 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3739 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3740 &i
.types
[i
.operands
- 3]));
3741 gas_assert (i
.rm
.mode
== 3);
3743 swap_2_operands (xchg
, xchg
+ 1);
3746 xchg
= i
.rm
.regmem
| 8;
3747 i
.rm
.regmem
= ~register_specifier
& 0xf;
3748 gas_assert (!(i
.rm
.regmem
& 8));
3749 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3750 register_specifier
= ~xchg
& 0xf;
3753 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3754 vector_length
= avxscalar
;
3755 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3757 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3763 /* Determine vector length from the last multi-length vector
3766 for (op
= t
->operands
; op
--;)
3767 if (t
->operand_types
[op
].bitfield
.xmmword
3768 && t
->operand_types
[op
].bitfield
.ymmword
3769 && i
.types
[op
].bitfield
.ymmword
)
3776 /* Check the REX.W bit and VEXW. */
3777 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3778 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3779 else if (i
.tm
.opcode_modifier
.vexw
)
3780 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3782 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3784 /* Use 2-byte VEX prefix if possible. */
3786 && i
.vec_encoding
!= vex_encoding_vex3
3787 && i
.tm
.opcode_space
== SPACE_0F
3788 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3790 /* 2-byte VEX prefix. */
3794 i
.vex
.bytes
[0] = 0xc5;
3796 /* Check the REX.R bit. */
3797 r
= (i
.rex
& REX_R
) ? 0 : 1;
3798 i
.vex
.bytes
[1] = (r
<< 7
3799 | register_specifier
<< 3
3800 | vector_length
<< 2
3801 | i
.tm
.opcode_modifier
.opcodeprefix
);
3805 /* 3-byte VEX prefix. */
3808 switch (i
.tm
.opcode_space
)
3813 i
.vex
.bytes
[0] = 0xc4;
3818 i
.vex
.bytes
[0] = 0x8f;
3824 /* The high 3 bits of the second VEX byte are 1's compliment
3825 of RXB bits from REX. */
3826 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3827 | (!dot_insn () ? i
.tm
.opcode_space
3828 : i
.insn_opcode_space
);
3830 i
.vex
.bytes
[2] = (w
<< 7
3831 | register_specifier
<< 3
3832 | vector_length
<< 2
3833 | i
.tm
.opcode_modifier
.opcodeprefix
);
3838 is_evex_encoding (const insn_template
*t
)
3840 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3841 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3842 || t
->opcode_modifier
.sae
;
3846 is_any_vex_encoding (const insn_template
*t
)
3848 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3852 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3854 unsigned int op
, bytes
;
3855 const i386_operand_type
*types
;
3857 if (i
.broadcast
.type
)
3858 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3860 gas_assert (intel_syntax
);
3862 for (op
= 0; op
< t
->operands
; ++op
)
3863 if (t
->operand_types
[op
].bitfield
.baseindex
)
3866 gas_assert (op
< t
->operands
);
3868 if (t
->opcode_modifier
.evex
3869 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3870 switch (i
.broadcast
.bytes
)
3873 if (t
->operand_types
[op
].bitfield
.word
)
3877 if (t
->operand_types
[op
].bitfield
.dword
)
3881 if (t
->operand_types
[op
].bitfield
.qword
)
3885 if (t
->operand_types
[op
].bitfield
.xmmword
)
3887 if (t
->operand_types
[op
].bitfield
.ymmword
)
3889 if (t
->operand_types
[op
].bitfield
.zmmword
)
3896 gas_assert (op
+ 1 < t
->operands
);
3898 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3899 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3900 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3902 types
= &i
.types
[op
+ 1];
3905 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3906 types
= &t
->operand_types
[op
];
3908 if (types
->bitfield
.zmmword
)
3910 else if (types
->bitfield
.ymmword
)
3916 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3917 insn_name (t
), bytes
* 8);
3922 /* Build the EVEX prefix. */
3925 build_evex_prefix (void)
3927 unsigned int register_specifier
, w
;
3928 rex_byte vrex_used
= 0;
3930 /* Check register specifier. */
3931 if (i
.vex
.register_specifier
)
3933 gas_assert ((i
.vrex
& REX_X
) == 0);
3935 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3936 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3937 register_specifier
+= 8;
3938 /* The upper 16 registers are encoded in the fourth byte of the
3940 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3941 i
.vex
.bytes
[3] = 0x8;
3942 register_specifier
= ~register_specifier
& 0xf;
3946 register_specifier
= 0xf;
3948 /* Encode upper 16 vector index register in the fourth byte of
3950 if (!(i
.vrex
& REX_X
))
3951 i
.vex
.bytes
[3] = 0x8;
3956 /* 4 byte EVEX prefix. */
3958 i
.vex
.bytes
[0] = 0x62;
3960 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3962 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3963 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3964 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3965 | (!dot_insn () ? i
.tm
.opcode_space
3966 : i
.insn_opcode_space
);
3968 /* The fifth bit of the second EVEX byte is 1's compliment of the
3969 REX_R bit in VREX. */
3970 if (!(i
.vrex
& REX_R
))
3971 i
.vex
.bytes
[1] |= 0x10;
3975 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3977 /* When all operands are registers, the REX_X bit in REX is not
3978 used. We reuse it to encode the upper 16 registers, which is
3979 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3980 as 1's compliment. */
3981 if ((i
.vrex
& REX_B
))
3984 i
.vex
.bytes
[1] &= ~0x40;
3988 /* EVEX instructions shouldn't need the REX prefix. */
3989 i
.vrex
&= ~vrex_used
;
3990 gas_assert (i
.vrex
== 0);
3992 /* Check the REX.W bit and VEXW. */
3993 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3994 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3995 else if (i
.tm
.opcode_modifier
.vexw
)
3996 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3998 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4000 /* The third byte of the EVEX prefix. */
4001 i
.vex
.bytes
[2] = ((w
<< 7)
4002 | (register_specifier
<< 3)
4003 | 4 /* Encode the U bit. */
4004 | i
.tm
.opcode_modifier
.opcodeprefix
);
4006 /* The fourth byte of the EVEX prefix. */
4007 /* The zeroing-masking bit. */
4008 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4009 i
.vex
.bytes
[3] |= 0x80;
4011 /* Don't always set the broadcast bit if there is no RC. */
4012 if (i
.rounding
.type
== rc_none
)
4014 /* Encode the vector length. */
4015 unsigned int vec_length
;
4017 if (!i
.tm
.opcode_modifier
.evex
4018 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4022 /* Determine vector length from the last multi-length vector
4024 for (op
= i
.operands
; op
--;)
4025 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4026 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4027 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4029 if (i
.types
[op
].bitfield
.zmmword
)
4031 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4034 else if (i
.types
[op
].bitfield
.ymmword
)
4036 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4039 else if (i
.types
[op
].bitfield
.xmmword
)
4041 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4044 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4045 && op
== i
.broadcast
.operand
)
4047 switch (get_broadcast_bytes (&i
.tm
, true))
4050 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4053 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4056 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4065 if (op
>= MAX_OPERANDS
)
4069 switch (i
.tm
.opcode_modifier
.evex
)
4071 case EVEXLIG
: /* LL' is ignored */
4072 vec_length
= evexlig
<< 5;
4075 vec_length
= 0 << 5;
4078 vec_length
= 1 << 5;
4081 vec_length
= 2 << 5;
4086 vec_length
= 3 << 5;
4094 i
.vex
.bytes
[3] |= vec_length
;
4095 /* Encode the broadcast bit. */
4096 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4097 i
.vex
.bytes
[3] |= 0x10;
4099 else if (i
.rounding
.type
!= saeonly
)
4100 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4102 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4105 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4109 process_immext (void)
4113 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4114 which is coded in the same place as an 8-bit immediate field
4115 would be. Here we fake an 8-bit immediate operand from the
4116 opcode suffix stored in tm.extension_opcode.
4118 AVX instructions also use this encoding, for some of
4119 3 argument instructions. */
4121 gas_assert (i
.imm_operands
<= 1
4123 || (is_any_vex_encoding (&i
.tm
)
4124 && i
.operands
<= 4)));
4126 exp
= &im_expressions
[i
.imm_operands
++];
4127 i
.op
[i
.operands
].imms
= exp
;
4128 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4130 exp
->X_op
= O_constant
;
4131 exp
->X_add_number
= i
.tm
.extension_opcode
;
4132 i
.tm
.extension_opcode
= None
;
4139 switch (i
.tm
.opcode_modifier
.prefixok
)
4147 as_bad (_("invalid instruction `%s' after `%s'"),
4148 insn_name (&i
.tm
), i
.hle_prefix
);
4151 if (i
.prefix
[LOCK_PREFIX
])
4153 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4157 case PrefixHLERelease
:
4158 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4160 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4164 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4166 as_bad (_("memory destination needed for instruction `%s'"
4167 " after `xrelease'"), insn_name (&i
.tm
));
4174 /* Encode aligned vector move as unaligned vector move. */
4177 encode_with_unaligned_vector_move (void)
4179 switch (i
.tm
.base_opcode
)
4181 case 0x28: /* Load instructions. */
4182 case 0x29: /* Store instructions. */
4183 /* movaps/movapd/vmovaps/vmovapd. */
4184 if (i
.tm
.opcode_space
== SPACE_0F
4185 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4186 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4188 case 0x6f: /* Load instructions. */
4189 case 0x7f: /* Store instructions. */
4190 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4191 if (i
.tm
.opcode_space
== SPACE_0F
4192 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4193 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4200 /* Try the shortest encoding by shortening operand size. */
4203 optimize_encoding (void)
4207 if (i
.tm
.mnem_off
== MN_lea
)
4210 lea symbol, %rN -> mov $symbol, %rN
4211 lea (%rM), %rN -> mov %rM, %rN
4212 lea (,%rM,1), %rN -> mov %rM, %rN
4214 and in 32-bit mode for 16-bit addressing
4216 lea (%rM), %rN -> movzx %rM, %rN
4218 and in 64-bit mode zap 32-bit addressing in favor of using a
4219 32-bit (or less) destination.
4221 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4223 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4224 i
.tm
.opcode_modifier
.size
= SIZE32
;
4225 i
.prefix
[ADDR_PREFIX
] = 0;
4228 if (!i
.index_reg
&& !i
.base_reg
)
4231 lea symbol, %rN -> mov $symbol, %rN
4233 if (flag_code
== CODE_64BIT
)
4235 /* Don't transform a relocation to a 16-bit one. */
4237 && i
.op
[0].disps
->X_op
!= O_constant
4238 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4241 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4242 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4244 i
.tm
.base_opcode
= 0xb8;
4245 i
.tm
.opcode_modifier
.modrm
= 0;
4246 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4247 i
.types
[0].bitfield
.imm32
= 1;
4250 i
.tm
.opcode_modifier
.size
= SIZE16
;
4251 i
.types
[0].bitfield
.imm16
= 1;
4256 /* Subject to further optimization below. */
4257 i
.tm
.base_opcode
= 0xc7;
4258 i
.tm
.extension_opcode
= 0;
4259 i
.types
[0].bitfield
.imm32s
= 1;
4260 i
.types
[0].bitfield
.baseindex
= 0;
4263 /* Outside of 64-bit mode address and operand sizes have to match if
4264 a relocation is involved, as otherwise we wouldn't (currently) or
4265 even couldn't express the relocation correctly. */
4266 else if (i
.op
[0].disps
4267 && i
.op
[0].disps
->X_op
!= O_constant
4268 && ((!i
.prefix
[ADDR_PREFIX
])
4269 != (flag_code
== CODE_32BIT
4270 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4271 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4273 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4274 destination is going to grow encoding size. */
4275 else if (flag_code
== CODE_16BIT
4276 && (optimize
<= 1 || optimize_for_space
)
4277 && !i
.prefix
[ADDR_PREFIX
]
4278 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4282 i
.tm
.base_opcode
= 0xb8;
4283 i
.tm
.opcode_modifier
.modrm
= 0;
4284 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4285 i
.types
[0].bitfield
.imm32
= 1;
4287 i
.types
[0].bitfield
.imm16
= 1;
4290 && i
.op
[0].disps
->X_op
== O_constant
4291 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4292 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4294 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4295 i
.op
[0].disps
->X_add_number
&= 0xffff;
4298 i
.tm
.operand_types
[0] = i
.types
[0];
4302 i
.op
[0].imms
= &im_expressions
[0];
4303 i
.op
[0].imms
->X_op
= O_absent
;
4306 else if (i
.op
[0].disps
4307 && (i
.op
[0].disps
->X_op
!= O_constant
4308 || i
.op
[0].disps
->X_add_number
))
4313 lea (%rM), %rN -> mov %rM, %rN
4314 lea (,%rM,1), %rN -> mov %rM, %rN
4315 lea (%rM), %rN -> movzx %rM, %rN
4317 const reg_entry
*addr_reg
;
4319 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4320 addr_reg
= i
.base_reg
;
4321 else if (!i
.base_reg
4322 && i
.index_reg
->reg_num
!= RegIZ
4323 && !i
.log2_scale_factor
)
4324 addr_reg
= i
.index_reg
;
4328 if (addr_reg
->reg_type
.bitfield
.word
4329 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4331 if (flag_code
!= CODE_32BIT
)
4333 i
.tm
.opcode_space
= SPACE_0F
;
4334 i
.tm
.base_opcode
= 0xb7;
4337 i
.tm
.base_opcode
= 0x8b;
4339 if (addr_reg
->reg_type
.bitfield
.dword
4340 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4341 i
.tm
.opcode_modifier
.size
= SIZE32
;
4343 i
.op
[0].regs
= addr_reg
;
4348 i
.disp_operands
= 0;
4349 i
.prefix
[ADDR_PREFIX
] = 0;
4350 i
.prefix
[SEG_PREFIX
] = 0;
4354 if (optimize_for_space
4355 && i
.tm
.mnem_off
== MN_test
4356 && i
.reg_operands
== 1
4357 && i
.imm_operands
== 1
4358 && !i
.types
[1].bitfield
.byte
4359 && i
.op
[0].imms
->X_op
== O_constant
4360 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4363 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4365 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4366 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4368 i
.types
[1].bitfield
.byte
= 1;
4369 /* Ignore the suffix. */
4371 /* Convert to byte registers. */
4372 if (i
.types
[1].bitfield
.word
)
4374 else if (i
.types
[1].bitfield
.dword
)
4378 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4383 else if (flag_code
== CODE_64BIT
4384 && i
.tm
.opcode_space
== SPACE_BASE
4385 && ((i
.types
[1].bitfield
.qword
4386 && i
.reg_operands
== 1
4387 && i
.imm_operands
== 1
4388 && i
.op
[0].imms
->X_op
== O_constant
4389 && ((i
.tm
.base_opcode
== 0xb8
4390 && i
.tm
.extension_opcode
== None
4391 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4392 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4393 && (i
.tm
.base_opcode
== 0x24
4394 || (i
.tm
.base_opcode
== 0x80
4395 && i
.tm
.extension_opcode
== 0x4)
4396 || i
.tm
.mnem_off
== MN_test
4397 || ((i
.tm
.base_opcode
| 1) == 0xc7
4398 && i
.tm
.extension_opcode
== 0x0)))
4399 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4400 && i
.tm
.base_opcode
== 0x83
4401 && i
.tm
.extension_opcode
== 0x4)))
4402 || (i
.types
[0].bitfield
.qword
4403 && ((i
.reg_operands
== 2
4404 && i
.op
[0].regs
== i
.op
[1].regs
4405 && (i
.tm
.mnem_off
== MN_xor
4406 || i
.tm
.mnem_off
== MN_sub
))
4407 || i
.tm
.mnem_off
== MN_clr
))))
4410 andq $imm31, %r64 -> andl $imm31, %r32
4411 andq $imm7, %r64 -> andl $imm7, %r32
4412 testq $imm31, %r64 -> testl $imm31, %r32
4413 xorq %r64, %r64 -> xorl %r32, %r32
4414 subq %r64, %r64 -> subl %r32, %r32
4415 movq $imm31, %r64 -> movl $imm31, %r32
4416 movq $imm32, %r64 -> movl $imm32, %r32
4418 i
.tm
.opcode_modifier
.size
= SIZE32
;
4421 i
.types
[0].bitfield
.imm32
= 1;
4422 i
.types
[0].bitfield
.imm32s
= 0;
4423 i
.types
[0].bitfield
.imm64
= 0;
4427 i
.types
[0].bitfield
.dword
= 1;
4428 i
.types
[0].bitfield
.qword
= 0;
4430 i
.types
[1].bitfield
.dword
= 1;
4431 i
.types
[1].bitfield
.qword
= 0;
4432 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4435 movq $imm31, %r64 -> movl $imm31, %r32
4436 movq $imm32, %r64 -> movl $imm32, %r32
4438 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4439 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4440 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4441 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4444 movq $imm31, %r64 -> movl $imm31, %r32
4446 i
.tm
.base_opcode
= 0xb8;
4447 i
.tm
.extension_opcode
= None
;
4448 i
.tm
.opcode_modifier
.w
= 0;
4449 i
.tm
.opcode_modifier
.modrm
= 0;
4453 else if (optimize
> 1
4454 && !optimize_for_space
4455 && i
.reg_operands
== 2
4456 && i
.op
[0].regs
== i
.op
[1].regs
4457 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4458 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4461 andb %rN, %rN -> testb %rN, %rN
4462 andw %rN, %rN -> testw %rN, %rN
4463 andq %rN, %rN -> testq %rN, %rN
4464 orb %rN, %rN -> testb %rN, %rN
4465 orw %rN, %rN -> testw %rN, %rN
4466 orq %rN, %rN -> testq %rN, %rN
4468 and outside of 64-bit mode
4470 andl %rN, %rN -> testl %rN, %rN
4471 orl %rN, %rN -> testl %rN, %rN
4473 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4475 else if (i
.tm
.base_opcode
== 0xba
4476 && i
.tm
.opcode_space
== SPACE_0F
4477 && i
.reg_operands
== 1
4478 && i
.op
[0].imms
->X_op
== O_constant
4479 && i
.op
[0].imms
->X_add_number
>= 0)
4482 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4483 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4484 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4486 With <BT> one of bts, btr, and bts also:
4487 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4488 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4493 if (i
.tm
.extension_opcode
!= 4)
4495 if (i
.types
[1].bitfield
.qword
4496 && i
.op
[0].imms
->X_add_number
< 32
4497 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4498 i
.tm
.opcode_modifier
.size
= SIZE32
;
4501 if (i
.types
[1].bitfield
.word
4502 && i
.op
[0].imms
->X_add_number
< 16)
4503 i
.tm
.opcode_modifier
.size
= SIZE32
;
4506 if (i
.op
[0].imms
->X_add_number
< 16)
4507 i
.tm
.opcode_modifier
.size
= SIZE16
;
4511 else if (i
.reg_operands
== 3
4512 && i
.op
[0].regs
== i
.op
[1].regs
4513 && !i
.types
[2].bitfield
.xmmword
4514 && (i
.tm
.opcode_modifier
.vex
4515 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4516 && is_evex_encoding (&i
.tm
)
4517 && (i
.vec_encoding
!= vex_encoding_evex
4518 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4519 || is_cpu (&i
.tm
, CpuAVX512VL
)
4520 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4521 && i
.types
[2].bitfield
.ymmword
))))
4522 && i
.tm
.opcode_space
== SPACE_0F
4523 && ((i
.tm
.base_opcode
| 2) == 0x57
4524 || i
.tm
.base_opcode
== 0xdf
4525 || i
.tm
.base_opcode
== 0xef
4526 || (i
.tm
.base_opcode
| 3) == 0xfb
4527 || i
.tm
.base_opcode
== 0x42
4528 || i
.tm
.base_opcode
== 0x47))
4531 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4533 EVEX VOP %zmmM, %zmmM, %zmmN
4534 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4535 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4536 EVEX VOP %ymmM, %ymmM, %ymmN
4537 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4538 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4539 VEX VOP %ymmM, %ymmM, %ymmN
4540 -> VEX VOP %xmmM, %xmmM, %xmmN
4541 VOP, one of vpandn and vpxor:
4542 VEX VOP %ymmM, %ymmM, %ymmN
4543 -> VEX VOP %xmmM, %xmmM, %xmmN
4544 VOP, one of vpandnd and vpandnq:
4545 EVEX VOP %zmmM, %zmmM, %zmmN
4546 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4547 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4548 EVEX VOP %ymmM, %ymmM, %ymmN
4549 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4550 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4551 VOP, one of vpxord and vpxorq:
4552 EVEX VOP %zmmM, %zmmM, %zmmN
4553 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4554 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4555 EVEX VOP %ymmM, %ymmM, %ymmN
4556 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4557 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4558 VOP, one of kxord and kxorq:
4559 VEX VOP %kM, %kM, %kN
4560 -> VEX kxorw %kM, %kM, %kN
4561 VOP, one of kandnd and kandnq:
4562 VEX VOP %kM, %kM, %kN
4563 -> VEX kandnw %kM, %kM, %kN
4565 if (is_evex_encoding (&i
.tm
))
4567 if (i
.vec_encoding
!= vex_encoding_evex
)
4569 i
.tm
.opcode_modifier
.vex
= VEX128
;
4570 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4571 i
.tm
.opcode_modifier
.evex
= 0;
4573 else if (optimize
> 1)
4574 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4578 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4580 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4581 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4584 i
.tm
.opcode_modifier
.vex
= VEX128
;
4586 if (i
.tm
.opcode_modifier
.vex
)
4587 for (j
= 0; j
< 3; j
++)
4589 i
.types
[j
].bitfield
.xmmword
= 1;
4590 i
.types
[j
].bitfield
.ymmword
= 0;
4593 else if (i
.vec_encoding
!= vex_encoding_evex
4594 && !i
.types
[0].bitfield
.zmmword
4595 && !i
.types
[1].bitfield
.zmmword
4597 && !i
.broadcast
.type
4598 && !i
.broadcast
.bytes
4599 && is_evex_encoding (&i
.tm
)
4600 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4601 || (i
.tm
.base_opcode
& ~4) == 0xdb
4602 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4603 && i
.tm
.extension_opcode
== None
)
4606 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4607 vmovdqu32 and vmovdqu64:
4608 EVEX VOP %xmmM, %xmmN
4609 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4610 EVEX VOP %ymmM, %ymmN
4611 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4613 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4615 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4617 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4619 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4620 VOP, one of vpand, vpandn, vpor, vpxor:
4621 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4622 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4623 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4624 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4625 EVEX VOP{d,q} mem, %xmmM, %xmmN
4626 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4627 EVEX VOP{d,q} mem, %ymmM, %ymmN
4628 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4630 for (j
= 0; j
< i
.operands
; j
++)
4631 if (operand_type_check (i
.types
[j
], disp
)
4632 && i
.op
[j
].disps
->X_op
== O_constant
)
4634 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4635 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4636 bytes, we choose EVEX Disp8 over VEX Disp32. */
4637 int evex_disp8
, vex_disp8
;
4638 unsigned int memshift
= i
.memshift
;
4639 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4641 evex_disp8
= fits_in_disp8 (n
);
4643 vex_disp8
= fits_in_disp8 (n
);
4644 if (evex_disp8
!= vex_disp8
)
4646 i
.memshift
= memshift
;
4650 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4653 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4654 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4655 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4656 i
.tm
.opcode_modifier
.vex
4657 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4658 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4659 /* VPAND, VPOR, and VPXOR are commutative. */
4660 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4661 i
.tm
.opcode_modifier
.commutative
= 1;
4662 i
.tm
.opcode_modifier
.evex
= 0;
4663 i
.tm
.opcode_modifier
.masking
= 0;
4664 i
.tm
.opcode_modifier
.broadcast
= 0;
4665 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4668 i
.types
[j
].bitfield
.disp8
4669 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4671 else if (optimize_for_space
4672 && i
.tm
.base_opcode
== 0x29
4673 && i
.tm
.opcode_space
== SPACE_0F38
4674 && i
.operands
== i
.reg_operands
4675 && i
.op
[0].regs
== i
.op
[1].regs
4676 && (!i
.tm
.opcode_modifier
.vex
4677 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4678 && !is_evex_encoding (&i
.tm
))
4681 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4682 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4683 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4685 i
.tm
.opcode_space
= SPACE_0F
;
4686 i
.tm
.base_opcode
= 0x76;
4688 else if (((i
.tm
.base_opcode
>= 0x64
4689 && i
.tm
.base_opcode
<= 0x66
4690 && i
.tm
.opcode_space
== SPACE_0F
)
4691 || (i
.tm
.base_opcode
== 0x37
4692 && i
.tm
.opcode_space
== SPACE_0F38
))
4693 && i
.operands
== i
.reg_operands
4694 && i
.op
[0].regs
== i
.op
[1].regs
4695 && !is_evex_encoding (&i
.tm
))
4698 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4699 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4700 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4701 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4702 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4703 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4705 i
.tm
.opcode_space
= SPACE_0F
;
4706 i
.tm
.base_opcode
= 0xef;
4707 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4709 if (i
.operands
== 2)
4711 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4717 i
.op
[2].regs
= i
.op
[0].regs
;
4718 i
.types
[2] = i
.types
[0];
4719 i
.flags
[2] = i
.flags
[0];
4720 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4722 i
.tm
.opcode_modifier
.sse2avx
= 0;
4724 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4725 i
.op
[1].regs
= i
.op
[0].regs
;
4728 else if (optimize_for_space
4729 && i
.tm
.base_opcode
== 0x59
4730 && i
.tm
.opcode_space
== SPACE_0F38
4731 && i
.operands
== i
.reg_operands
4732 && i
.tm
.opcode_modifier
.vex
4733 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4734 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4735 && i
.vec_encoding
!= vex_encoding_vex3
)
4738 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4740 i
.tm
.opcode_space
= SPACE_0F
;
4741 i
.tm
.base_opcode
= 0x6c;
4742 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4748 i
.op
[2].regs
= i
.op
[0].regs
;
4749 i
.types
[2] = i
.types
[0];
4750 i
.flags
[2] = i
.flags
[0];
4751 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4753 swap_2_operands (1, 2);
4757 /* Return non-zero for load instruction. */
4763 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4764 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4768 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4769 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4770 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4774 if (i
.tm
.mnem_off
== MN_pop
)
4778 if (i
.tm
.opcode_space
== SPACE_BASE
)
4781 if (i
.tm
.base_opcode
== 0x9d
4782 || i
.tm
.base_opcode
== 0x61)
4785 /* movs, cmps, lods, scas. */
4786 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4790 if (base_opcode
== 0x6f
4791 || i
.tm
.base_opcode
== 0xd7)
4793 /* NB: For AMD-specific insns with implicit memory operands,
4794 they're intentionally not covered. */
4797 /* No memory operand. */
4798 if (!i
.mem_operands
)
4803 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4806 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4808 /* test, not, neg, mul, imul, div, idiv. */
4809 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4813 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4816 /* add, or, adc, sbb, and, sub, xor, cmp. */
4817 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4820 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4821 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4822 && i
.tm
.extension_opcode
!= 6)
4825 /* Check for x87 instructions. */
4826 if ((base_opcode
| 6) == 0xdf)
4828 /* Skip fst, fstp, fstenv, fstcw. */
4829 if (i
.tm
.base_opcode
== 0xd9
4830 && (i
.tm
.extension_opcode
== 2
4831 || i
.tm
.extension_opcode
== 3
4832 || i
.tm
.extension_opcode
== 6
4833 || i
.tm
.extension_opcode
== 7))
4836 /* Skip fisttp, fist, fistp, fstp. */
4837 if (i
.tm
.base_opcode
== 0xdb
4838 && (i
.tm
.extension_opcode
== 1
4839 || i
.tm
.extension_opcode
== 2
4840 || i
.tm
.extension_opcode
== 3
4841 || i
.tm
.extension_opcode
== 7))
4844 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4845 if (i
.tm
.base_opcode
== 0xdd
4846 && (i
.tm
.extension_opcode
== 1
4847 || i
.tm
.extension_opcode
== 2
4848 || i
.tm
.extension_opcode
== 3
4849 || i
.tm
.extension_opcode
== 6
4850 || i
.tm
.extension_opcode
== 7))
4853 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4854 if (i
.tm
.base_opcode
== 0xdf
4855 && (i
.tm
.extension_opcode
== 1
4856 || i
.tm
.extension_opcode
== 2
4857 || i
.tm
.extension_opcode
== 3
4858 || i
.tm
.extension_opcode
== 6
4859 || i
.tm
.extension_opcode
== 7))
4865 else if (i
.tm
.opcode_space
== SPACE_0F
)
4867 /* bt, bts, btr, btc. */
4868 if (i
.tm
.base_opcode
== 0xba
4869 && (i
.tm
.extension_opcode
| 3) == 7)
4872 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4873 if (i
.tm
.base_opcode
== 0xc7
4874 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4875 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4876 || i
.tm
.extension_opcode
== 6))
4879 /* fxrstor, ldmxcsr, xrstor. */
4880 if (i
.tm
.base_opcode
== 0xae
4881 && (i
.tm
.extension_opcode
== 1
4882 || i
.tm
.extension_opcode
== 2
4883 || i
.tm
.extension_opcode
== 5))
4886 /* lgdt, lidt, lmsw. */
4887 if (i
.tm
.base_opcode
== 0x01
4888 && (i
.tm
.extension_opcode
== 2
4889 || i
.tm
.extension_opcode
== 3
4890 || i
.tm
.extension_opcode
== 6))
4894 dest
= i
.operands
- 1;
4896 /* Check fake imm8 operand and 3 source operands. */
4897 if ((i
.tm
.opcode_modifier
.immext
4898 || i
.reg_operands
+ i
.mem_operands
== 4)
4899 && i
.types
[dest
].bitfield
.imm8
)
4902 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4903 if (i
.tm
.opcode_space
== SPACE_BASE
4904 && ((base_opcode
| 0x38) == 0x39
4905 || (base_opcode
| 2) == 0x87))
4908 if (i
.tm
.mnem_off
== MN_xadd
)
4911 /* Check for load instruction. */
4912 return (i
.types
[dest
].bitfield
.class != ClassNone
4913 || i
.types
[dest
].bitfield
.instance
== Accum
);
4916 /* Output lfence, 0xfaee8, after instruction. */
4919 insert_lfence_after (void)
4921 if (lfence_after_load
&& load_insn_p ())
4923 /* There are also two REP string instructions that require
4924 special treatment. Specifically, the compare string (CMPS)
4925 and scan string (SCAS) instructions set EFLAGS in a manner
4926 that depends on the data being compared/scanned. When used
4927 with a REP prefix, the number of iterations may therefore
4928 vary depending on this data. If the data is a program secret
4929 chosen by the adversary using an LVI method,
4930 then this data-dependent behavior may leak some aspect
4932 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4933 && i
.prefix
[REP_PREFIX
])
4935 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4938 char *p
= frag_more (3);
4945 /* Output lfence, 0xfaee8, before instruction. */
4948 insert_lfence_before (void)
4952 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4955 if (i
.tm
.base_opcode
== 0xff
4956 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4958 /* Insert lfence before indirect branch if needed. */
4960 if (lfence_before_indirect_branch
== lfence_branch_none
)
4963 if (i
.operands
!= 1)
4966 if (i
.reg_operands
== 1)
4968 /* Indirect branch via register. Don't insert lfence with
4969 -mlfence-after-load=yes. */
4970 if (lfence_after_load
4971 || lfence_before_indirect_branch
== lfence_branch_memory
)
4974 else if (i
.mem_operands
== 1
4975 && lfence_before_indirect_branch
!= lfence_branch_register
)
4977 as_warn (_("indirect `%s` with memory operand should be avoided"),
4984 if (last_insn
.kind
!= last_insn_other
4985 && last_insn
.seg
== now_seg
)
4987 as_warn_where (last_insn
.file
, last_insn
.line
,
4988 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4989 last_insn
.name
, insn_name (&i
.tm
));
5000 /* Output or/not/shl and lfence before near ret. */
5001 if (lfence_before_ret
!= lfence_before_ret_none
5002 && (i
.tm
.base_opcode
| 1) == 0xc3)
5004 if (last_insn
.kind
!= last_insn_other
5005 && last_insn
.seg
== now_seg
)
5007 as_warn_where (last_insn
.file
, last_insn
.line
,
5008 _("`%s` skips -mlfence-before-ret on `%s`"),
5009 last_insn
.name
, insn_name (&i
.tm
));
5013 /* Near ret ingore operand size override under CPU64. */
5014 char prefix
= flag_code
== CODE_64BIT
5016 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5018 if (lfence_before_ret
== lfence_before_ret_not
)
5020 /* not: 0xf71424, may add prefix
5021 for operand size override or 64-bit code. */
5022 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5036 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5039 if (lfence_before_ret
== lfence_before_ret_or
)
5041 /* or: 0x830c2400, may add prefix
5042 for operand size override or 64-bit code. */
5048 /* shl: 0xc1242400, may add prefix
5049 for operand size override or 64-bit code. */
5064 /* Shared helper for md_assemble() and s_insn(). */
5065 static void init_globals (void)
5069 memset (&i
, '\0', sizeof (i
));
5070 i
.rounding
.type
= rc_none
;
5071 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5072 i
.reloc
[j
] = NO_RELOC
;
5073 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5074 memset (im_expressions
, '\0', sizeof (im_expressions
));
5075 save_stack_p
= save_stack
;
5078 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5079 parsing pass. Instead of introducing a rarely use new insn attribute this
5080 utilizes a common pattern between affected templates. It is deemed
5081 acceptable that this will lead to unnecessary pass 2 preparations in a
5082 limited set of cases. */
5083 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5085 return t
->opcode_modifier
.sse2avx
5086 /* Note that all SSE2AVX templates have at least one operand. */
5087 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5088 : (t
->opcode_space
== SPACE_0F
5089 && (t
->base_opcode
| 1) == 0xbf)
5090 || (t
->opcode_space
== SPACE_BASE
5091 && t
->base_opcode
== 0x63);
5094 /* This is the guts of the machine-dependent assembler. LINE points to a
5095 machine dependent instruction. This function is supposed to emit
5096 the frags/bytes it assembles to. */
5099 md_assemble (char *line
)
5102 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5103 const char *end
, *pass1_mnem
= NULL
;
5104 enum i386_error pass1_err
= 0;
5105 const insn_template
*t
;
5107 /* Initialize globals. */
5108 current_templates
= NULL
;
5112 /* First parse an instruction mnemonic & call i386_operand for the operands.
5113 We assume that the scrubber has arranged it so that line[0] is the valid
5114 start of a (possibly prefixed) mnemonic. */
5116 end
= parse_insn (line
, mnemonic
, false);
5119 if (pass1_mnem
!= NULL
)
5121 if (i
.error
!= no_error
)
5123 gas_assert (current_templates
!= NULL
);
5124 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5126 /* No point in trying a 2nd pass - it'll only find the same suffix
5128 mnem_suffix
= i
.suffix
;
5133 t
= current_templates
->start
;
5134 if (may_need_pass2 (t
))
5136 /* Make a copy of the full line in case we need to retry. */
5137 copy
= xstrdup (line
);
5140 mnem_suffix
= i
.suffix
;
5142 line
= parse_operands (line
, mnemonic
);
5150 /* Now we've parsed the mnemonic into a set of templates, and have the
5151 operands at hand. */
5153 /* All Intel opcodes have reversed operands except for "bound", "enter",
5154 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5155 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5156 intersegment "jmp" and "call" instructions with 2 immediate operands so
5157 that the immediate segment precedes the offset consistently in Intel and
5161 && (t
->mnem_off
!= MN_bound
)
5162 && !startswith (mnemonic
, "invlpg")
5163 && !startswith (mnemonic
, "monitor")
5164 && !startswith (mnemonic
, "mwait")
5165 && (t
->mnem_off
!= MN_pvalidate
)
5166 && !startswith (mnemonic
, "rmp")
5167 && (t
->mnem_off
!= MN_tpause
)
5168 && (t
->mnem_off
!= MN_umwait
)
5169 && !(i
.operands
== 2
5170 && operand_type_check (i
.types
[0], imm
)
5171 && operand_type_check (i
.types
[1], imm
)))
5174 /* The order of the immediates should be reversed
5175 for 2 immediates extrq and insertq instructions */
5176 if (i
.imm_operands
== 2
5177 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5178 swap_2_operands (0, 1);
5183 if (i
.disp_operands
&& !optimize_disp (t
))
5186 /* Next, we find a template that matches the given insn,
5187 making sure the overlap of the given operands types is consistent
5188 with the template operand types. */
5190 if (!(t
= match_template (mnem_suffix
)))
5192 const char *err_msg
;
5194 if (copy
&& !mnem_suffix
)
5199 pass1_err
= i
.error
;
5200 pass1_mnem
= insn_name (current_templates
->start
);
5204 /* If a non-/only-64bit template (group) was found in pass 1, and if
5205 _some_ template (group) was found in pass 2, squash pass 1's
5207 if (pass1_err
== unsupported_64bit
)
5213 switch (pass1_mnem
? pass1_err
: i
.error
)
5217 case operand_size_mismatch
:
5218 err_msg
= _("operand size mismatch");
5220 case operand_type_mismatch
:
5221 err_msg
= _("operand type mismatch");
5223 case register_type_mismatch
:
5224 err_msg
= _("register type mismatch");
5226 case number_of_operands_mismatch
:
5227 err_msg
= _("number of operands mismatch");
5229 case invalid_instruction_suffix
:
5230 err_msg
= _("invalid instruction suffix");
5233 err_msg
= _("constant doesn't fit in 4 bits");
5235 case unsupported_with_intel_mnemonic
:
5236 err_msg
= _("unsupported with Intel mnemonic");
5238 case unsupported_syntax
:
5239 err_msg
= _("unsupported syntax");
5242 as_bad (_("unsupported instruction `%s'"),
5243 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5245 case unsupported_on_arch
:
5246 as_bad (_("`%s' is not supported on `%s%s'"),
5247 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5248 cpu_arch_name
? cpu_arch_name
: default_arch
,
5249 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5251 case unsupported_64bit
:
5252 if (ISLOWER (mnem_suffix
))
5254 if (flag_code
== CODE_64BIT
)
5255 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5256 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5259 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5260 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5265 if (flag_code
== CODE_64BIT
)
5266 as_bad (_("`%s' is not supported in 64-bit mode"),
5267 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5269 as_bad (_("`%s' is only supported in 64-bit mode"),
5270 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5273 case invalid_sib_address
:
5274 err_msg
= _("invalid SIB address");
5276 case invalid_vsib_address
:
5277 err_msg
= _("invalid VSIB address");
5279 case invalid_vector_register_set
:
5280 err_msg
= _("mask, index, and destination registers must be distinct");
5282 case invalid_tmm_register_set
:
5283 err_msg
= _("all tmm registers must be distinct");
5285 case invalid_dest_and_src_register_set
:
5286 err_msg
= _("destination and source registers must be distinct");
5288 case unsupported_vector_index_register
:
5289 err_msg
= _("unsupported vector index register");
5291 case unsupported_broadcast
:
5292 err_msg
= _("unsupported broadcast");
5294 case broadcast_needed
:
5295 err_msg
= _("broadcast is needed for operand of such type");
5297 case unsupported_masking
:
5298 err_msg
= _("unsupported masking");
5300 case mask_not_on_destination
:
5301 err_msg
= _("mask not on destination operand");
5303 case no_default_mask
:
5304 err_msg
= _("default mask isn't allowed");
5306 case unsupported_rc_sae
:
5307 err_msg
= _("unsupported static rounding/sae");
5309 case invalid_register_operand
:
5310 err_msg
= _("invalid register operand");
5313 as_bad (_("%s for `%s'"), err_msg
,
5314 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5320 if (sse_check
!= check_none
5321 /* The opcode space check isn't strictly needed; it's there only to
5322 bypass the logic below when easily possible. */
5323 && t
->opcode_space
>= SPACE_0F
5324 && t
->opcode_space
<= SPACE_0F3A
5325 && !is_cpu (&i
.tm
, CpuSSE4a
)
5326 && !is_any_vex_encoding (t
))
5330 for (j
= 0; j
< t
->operands
; ++j
)
5332 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5334 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5338 if (j
>= t
->operands
&& simd
)
5339 (sse_check
== check_warning
5341 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5344 if (i
.tm
.opcode_modifier
.fwait
)
5345 if (!add_prefix (FWAIT_OPCODE
))
5348 /* Check if REP prefix is OK. */
5349 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5351 as_bad (_("invalid instruction `%s' after `%s'"),
5352 insn_name (&i
.tm
), i
.rep_prefix
);
5356 /* Check for lock without a lockable instruction. Destination operand
5357 must be memory unless it is xchg (0x86). */
5358 if (i
.prefix
[LOCK_PREFIX
])
5360 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5361 || i
.mem_operands
== 0
5362 || (i
.tm
.base_opcode
!= 0x86
5363 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5365 as_bad (_("expecting lockable instruction after `lock'"));
5369 /* Zap the redundant prefix from XCHG when optimizing. */
5370 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5371 i
.prefix
[LOCK_PREFIX
] = 0;
5374 if (is_any_vex_encoding (&i
.tm
)
5375 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5376 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5378 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5379 if (i
.prefix
[DATA_PREFIX
])
5381 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5385 /* Don't allow e.g. KMOV in TLS code sequences. */
5386 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5389 case BFD_RELOC_386_TLS_GOTIE
:
5390 case BFD_RELOC_386_TLS_LE_32
:
5391 case BFD_RELOC_X86_64_GOTTPOFF
:
5392 case BFD_RELOC_X86_64_TLSLD
:
5393 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5400 /* Check if HLE prefix is OK. */
5401 if (i
.hle_prefix
&& !check_hle ())
5404 /* Check BND prefix. */
5405 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5406 as_bad (_("expecting valid branch instruction after `bnd'"));
5408 /* Check NOTRACK prefix. */
5409 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5410 as_bad (_("expecting indirect branch instruction after `notrack'"));
5412 if (is_cpu (&i
.tm
, CpuMPX
))
5414 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5415 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5416 else if (flag_code
!= CODE_16BIT
5417 ? i
.prefix
[ADDR_PREFIX
]
5418 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5419 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5422 /* Insert BND prefix. */
5423 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5425 if (!i
.prefix
[BND_PREFIX
])
5426 add_prefix (BND_PREFIX_OPCODE
);
5427 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5429 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5430 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5434 /* Check string instruction segment overrides. */
5435 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5437 gas_assert (i
.mem_operands
);
5438 if (!check_string ())
5440 i
.disp_operands
= 0;
5443 /* The memory operand of (%dx) should be only used with input/output
5444 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5445 if (i
.input_output_operand
5446 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5447 || i
.tm
.opcode_space
!= SPACE_BASE
))
5449 as_bad (_("input/output port address isn't allowed with `%s'"),
5454 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5455 optimize_encoding ();
5457 if (use_unaligned_vector_move
)
5458 encode_with_unaligned_vector_move ();
5460 if (!process_suffix ())
5463 /* Check if IP-relative addressing requirements can be satisfied. */
5464 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5465 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5466 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5468 /* Update operand types and check extended states. */
5469 for (j
= 0; j
< i
.operands
; j
++)
5471 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5472 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5477 i
.xstate
|= xstate_mmx
;
5480 i
.xstate
|= xstate_mask
;
5483 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5484 i
.xstate
|= xstate_tmm
;
5485 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5486 && vector_size
>= VSZ512
)
5487 i
.xstate
|= xstate_zmm
;
5488 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5489 && vector_size
>= VSZ256
)
5490 i
.xstate
|= xstate_ymm
;
5491 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5492 i
.xstate
|= xstate_xmm
;
5497 /* Make still unresolved immediate matches conform to size of immediate
5498 given in i.suffix. */
5499 if (!finalize_imm ())
5502 if (i
.types
[0].bitfield
.imm1
)
5503 i
.imm_operands
= 0; /* kludge for shift insns. */
5505 /* For insns with operands there are more diddles to do to the opcode. */
5508 if (!process_operands ())
5511 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5513 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5514 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5517 if (is_any_vex_encoding (&i
.tm
))
5519 if (!cpu_arch_flags
.bitfield
.cpui286
)
5521 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5526 /* Check for explicit REX prefix. */
5527 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5529 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5533 if (i
.tm
.opcode_modifier
.vex
)
5534 build_vex_prefix (t
);
5536 build_evex_prefix ();
5538 /* The individual REX.RXBW bits got consumed. */
5539 i
.rex
&= REX_OPCODE
;
5542 /* Handle conversion of 'int $3' --> special int3 insn. */
5543 if (i
.tm
.mnem_off
== MN_int
5544 && i
.op
[0].imms
->X_add_number
== 3)
5546 i
.tm
.base_opcode
= INT3_OPCODE
;
5550 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5551 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5552 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5553 && i
.op
[0].disps
->X_op
== O_constant
)
5555 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5556 the absolute address given by the constant. Since ix86 jumps and
5557 calls are pc relative, we need to generate a reloc. */
5558 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5559 i
.op
[0].disps
->X_op
= O_symbol
;
5562 /* For 8 bit registers we need an empty rex prefix. Also if the
5563 instruction already has a prefix, we need to convert old
5564 registers to new ones. */
5566 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5567 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5568 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5569 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5570 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5571 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5576 i
.rex
|= REX_OPCODE
;
5577 for (x
= 0; x
< 2; x
++)
5579 /* Look for 8 bit operand that uses old registers. */
5580 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5581 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5583 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5584 /* In case it is "hi" register, give up. */
5585 if (i
.op
[x
].regs
->reg_num
> 3)
5586 as_bad (_("can't encode register '%s%s' in an "
5587 "instruction requiring REX prefix."),
5588 register_prefix
, i
.op
[x
].regs
->reg_name
);
5590 /* Otherwise it is equivalent to the extended register.
5591 Since the encoding doesn't change this is merely
5592 cosmetic cleanup for debug output. */
5594 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5599 if (i
.rex
== 0 && i
.rex_encoding
)
5601 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5602 that uses legacy register. If it is "hi" register, don't add
5603 the REX_OPCODE byte. */
5605 for (x
= 0; x
< 2; x
++)
5606 if (i
.types
[x
].bitfield
.class == Reg
5607 && i
.types
[x
].bitfield
.byte
5608 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5609 && i
.op
[x
].regs
->reg_num
> 3)
5611 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5612 i
.rex_encoding
= false;
5621 add_prefix (REX_OPCODE
| i
.rex
);
5623 insert_lfence_before ();
5625 /* We are ready to output the insn. */
5628 insert_lfence_after ();
5630 last_insn
.seg
= now_seg
;
5632 if (i
.tm
.opcode_modifier
.isprefix
)
5634 last_insn
.kind
= last_insn_prefix
;
5635 last_insn
.name
= insn_name (&i
.tm
);
5636 last_insn
.file
= as_where (&last_insn
.line
);
5639 last_insn
.kind
= last_insn_other
;
5642 /* The Q suffix is generally valid only in 64-bit mode, with very few
5643 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5644 and fisttp only one of their two templates is matched below: That's
5645 sufficient since other relevant attributes are the same between both
5646 respective templates. */
5647 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5649 return flag_code
== CODE_64BIT
5650 || (t
->opcode_space
== SPACE_BASE
5651 && t
->base_opcode
== 0xdf
5652 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5653 || t
->mnem_off
== MN_cmpxchg8b
;
5657 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5659 const char *l
= line
, *token_start
= l
;
5661 bool pass1
= !current_templates
;
5663 const insn_template
*t
;
5669 /* Pseudo-prefixes start with an opening figure brace. */
5670 if ((*mnem_p
= *l
) == '{')
5675 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5680 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5683 as_bad (_("no such instruction: `%s'"), token_start
);
5688 /* Pseudo-prefixes end with a closing figure brace. */
5689 if (*mnemonic
== '{' && *l
== '}')
5692 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5696 /* Point l at the closing brace if there's no other separator. */
5697 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5698 && *l
!= PREFIX_SEPARATOR
)
5701 else if (!is_space_char (*l
)
5702 && *l
!= END_OF_INSN
5704 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5708 as_bad (_("invalid character %s in mnemonic"),
5709 output_invalid (*l
));
5712 if (token_start
== l
)
5714 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5715 as_bad (_("expecting prefix; got nothing"));
5717 as_bad (_("expecting mnemonic; got nothing"));
5721 /* Look up instruction (or prefix) via hash table. */
5722 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5724 if (*l
!= END_OF_INSN
5725 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5726 && current_templates
5727 && current_templates
->start
->opcode_modifier
.isprefix
)
5729 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu
))
5731 as_bad ((flag_code
!= CODE_64BIT
5732 ? _("`%s' is only supported in 64-bit mode")
5733 : _("`%s' is not supported in 64-bit mode")),
5734 insn_name (current_templates
->start
));
5737 /* If we are in 16-bit mode, do not allow addr16 or data16.
5738 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5739 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5740 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5741 && flag_code
!= CODE_64BIT
5742 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5743 ^ (flag_code
== CODE_16BIT
)))
5745 as_bad (_("redundant %s prefix"),
5746 insn_name (current_templates
->start
));
5750 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5752 /* Handle pseudo prefixes. */
5753 switch (current_templates
->start
->extension_opcode
)
5757 i
.disp_encoding
= disp_encoding_8bit
;
5761 i
.disp_encoding
= disp_encoding_16bit
;
5765 i
.disp_encoding
= disp_encoding_32bit
;
5769 i
.dir_encoding
= dir_encoding_load
;
5773 i
.dir_encoding
= dir_encoding_store
;
5777 i
.vec_encoding
= vex_encoding_vex
;
5781 i
.vec_encoding
= vex_encoding_vex3
;
5785 i
.vec_encoding
= vex_encoding_evex
;
5789 i
.rex_encoding
= true;
5791 case Prefix_NoOptimize
:
5793 i
.no_optimize
= true;
5801 /* Add prefix, checking for repeated prefixes. */
5802 switch (add_prefix (current_templates
->start
->base_opcode
))
5807 if (is_cpu (current_templates
->start
, CpuIBT
))
5808 i
.notrack_prefix
= insn_name (current_templates
->start
);
5811 if (is_cpu (current_templates
->start
, CpuHLE
))
5812 i
.hle_prefix
= insn_name (current_templates
->start
);
5813 else if (is_cpu (current_templates
->start
, CpuMPX
))
5814 i
.bnd_prefix
= insn_name (current_templates
->start
);
5816 i
.rep_prefix
= insn_name (current_templates
->start
);
5822 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5832 if (!current_templates
)
5834 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5835 Check if we should swap operand or force 32bit displacement in
5837 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5838 i
.dir_encoding
= dir_encoding_swap
;
5839 else if (mnem_p
- 3 == dot_p
5842 i
.disp_encoding
= disp_encoding_8bit
;
5843 else if (mnem_p
- 4 == dot_p
5847 i
.disp_encoding
= disp_encoding_32bit
;
5852 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5855 if (!current_templates
|| !pass1
)
5857 current_templates
= NULL
;
5860 if (mnem_p
> mnemonic
)
5862 /* See if we can get a match by trimming off a suffix. */
5865 case WORD_MNEM_SUFFIX
:
5866 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5867 i
.suffix
= SHORT_MNEM_SUFFIX
;
5870 case BYTE_MNEM_SUFFIX
:
5871 case QWORD_MNEM_SUFFIX
:
5872 i
.suffix
= mnem_p
[-1];
5875 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5877 case SHORT_MNEM_SUFFIX
:
5878 case LONG_MNEM_SUFFIX
:
5881 i
.suffix
= mnem_p
[-1];
5884 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5892 if (intel_float_operand (mnemonic
) == 1)
5893 i
.suffix
= SHORT_MNEM_SUFFIX
;
5895 i
.suffix
= LONG_MNEM_SUFFIX
;
5898 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5900 /* For compatibility reasons accept MOVSD and CMPSD without
5901 operands even in AT&T mode. */
5902 else if (*l
== END_OF_INSN
5903 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5907 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5908 if (current_templates
!= NULL
5910 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5911 && current_templates
->start
->opcode_space
5913 && mnem_p
[-2] == 's')
5915 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5916 mnemonic
, mnemonic
);
5917 i
.suffix
= LONG_MNEM_SUFFIX
;
5921 current_templates
= NULL
;
5929 if (!current_templates
)
5932 as_bad (_("no such instruction: `%s'"), token_start
);
5937 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5938 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5940 /* Check for a branch hint. We allow ",pt" and ",pn" for
5941 predict taken and predict not taken respectively.
5942 I'm not sure that branch hints actually do anything on loop
5943 and jcxz insns (JumpByte) for current Pentium4 chips. They
5944 may work in the future and it doesn't hurt to accept them
5946 if (l
[0] == ',' && l
[1] == 'p')
5950 if (!add_prefix (DS_PREFIX_OPCODE
))
5954 else if (l
[2] == 'n')
5956 if (!add_prefix (CS_PREFIX_OPCODE
))
5962 /* Any other comma loses. */
5965 as_bad (_("invalid character %s in mnemonic"),
5966 output_invalid (*l
));
5970 /* Check if instruction is supported on specified architecture. */
5972 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5974 supported
|= cpu_flags_match (t
);
5976 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5977 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5979 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5985 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5986 i
.error
= unsupported_on_arch
;
5988 i
.error
= unsupported_64bit
;
5995 parse_operands (char *l
, const char *mnemonic
)
5999 /* 1 if operand is pending after ','. */
6000 unsigned int expecting_operand
= 0;
6002 while (*l
!= END_OF_INSN
)
6004 /* Non-zero if operand parens not balanced. */
6005 unsigned int paren_not_balanced
= 0;
6006 /* True if inside double quotes. */
6007 bool in_quotes
= false;
6009 /* Skip optional white space before operand. */
6010 if (is_space_char (*l
))
6012 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6014 as_bad (_("invalid character %s before operand %d"),
6015 output_invalid (*l
),
6019 token_start
= l
; /* After white space. */
6020 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6022 if (*l
== END_OF_INSN
)
6026 as_bad (_("unbalanced double quotes in operand %d."),
6030 if (paren_not_balanced
)
6032 know (!intel_syntax
);
6033 as_bad (_("unbalanced parenthesis in operand %d."),
6038 break; /* we are done */
6040 else if (*l
== '\\' && l
[1] == '"')
6043 in_quotes
= !in_quotes
;
6044 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6046 as_bad (_("invalid character %s in operand %d"),
6047 output_invalid (*l
),
6051 if (!intel_syntax
&& !in_quotes
)
6054 ++paren_not_balanced
;
6056 --paren_not_balanced
;
6060 if (l
!= token_start
)
6061 { /* Yes, we've read in another operand. */
6062 unsigned int operand_ok
;
6063 this_operand
= i
.operands
++;
6064 if (i
.operands
> MAX_OPERANDS
)
6066 as_bad (_("spurious operands; (%d operands/instruction max)"),
6070 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6071 /* Now parse operand adding info to 'i' as we go along. */
6072 END_STRING_AND_SAVE (l
);
6074 if (i
.mem_operands
> 1)
6076 as_bad (_("too many memory references for `%s'"),
6083 i386_intel_operand (token_start
,
6084 intel_float_operand (mnemonic
));
6086 operand_ok
= i386_att_operand (token_start
);
6088 RESTORE_END_STRING (l
);
6094 if (expecting_operand
)
6096 expecting_operand_after_comma
:
6097 as_bad (_("expecting operand after ','; got nothing"));
6102 as_bad (_("expecting operand before ','; got nothing"));
6107 /* Now *l must be either ',' or END_OF_INSN. */
6110 if (*++l
== END_OF_INSN
)
6112 /* Just skip it, if it's \n complain. */
6113 goto expecting_operand_after_comma
;
6115 expecting_operand
= 1;
6122 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6124 union i386_op temp_op
;
6125 i386_operand_type temp_type
;
6126 unsigned int temp_flags
;
6127 enum bfd_reloc_code_real temp_reloc
;
6129 temp_type
= i
.types
[xchg2
];
6130 i
.types
[xchg2
] = i
.types
[xchg1
];
6131 i
.types
[xchg1
] = temp_type
;
6133 temp_flags
= i
.flags
[xchg2
];
6134 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6135 i
.flags
[xchg1
] = temp_flags
;
6137 temp_op
= i
.op
[xchg2
];
6138 i
.op
[xchg2
] = i
.op
[xchg1
];
6139 i
.op
[xchg1
] = temp_op
;
6141 temp_reloc
= i
.reloc
[xchg2
];
6142 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6143 i
.reloc
[xchg1
] = temp_reloc
;
6145 temp_flags
= i
.imm_bits
[xchg2
];
6146 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6147 i
.imm_bits
[xchg1
] = temp_flags
;
6151 if (i
.mask
.operand
== xchg1
)
6152 i
.mask
.operand
= xchg2
;
6153 else if (i
.mask
.operand
== xchg2
)
6154 i
.mask
.operand
= xchg1
;
6156 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6158 if (i
.broadcast
.operand
== xchg1
)
6159 i
.broadcast
.operand
= xchg2
;
6160 else if (i
.broadcast
.operand
== xchg2
)
6161 i
.broadcast
.operand
= xchg1
;
6166 swap_operands (void)
6172 swap_2_operands (1, i
.operands
- 2);
6176 swap_2_operands (0, i
.operands
- 1);
6182 if (i
.mem_operands
== 2)
6184 const reg_entry
*temp_seg
;
6185 temp_seg
= i
.seg
[0];
6186 i
.seg
[0] = i
.seg
[1];
6187 i
.seg
[1] = temp_seg
;
6191 /* Try to ensure constant immediates are represented in the smallest
6196 char guess_suffix
= 0;
6200 guess_suffix
= i
.suffix
;
6201 else if (i
.reg_operands
)
6203 /* Figure out a suffix from the last register operand specified.
6204 We can't do this properly yet, i.e. excluding special register
6205 instances, but the following works for instructions with
6206 immediates. In any case, we can't set i.suffix yet. */
6207 for (op
= i
.operands
; --op
>= 0;)
6208 if (i
.types
[op
].bitfield
.class != Reg
)
6210 else if (i
.types
[op
].bitfield
.byte
)
6212 guess_suffix
= BYTE_MNEM_SUFFIX
;
6215 else if (i
.types
[op
].bitfield
.word
)
6217 guess_suffix
= WORD_MNEM_SUFFIX
;
6220 else if (i
.types
[op
].bitfield
.dword
)
6222 guess_suffix
= LONG_MNEM_SUFFIX
;
6225 else if (i
.types
[op
].bitfield
.qword
)
6227 guess_suffix
= QWORD_MNEM_SUFFIX
;
6231 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6232 guess_suffix
= WORD_MNEM_SUFFIX
;
6233 else if (flag_code
!= CODE_64BIT
|| !(i
.prefix
[REX_PREFIX
] & REX_W
))
6234 guess_suffix
= LONG_MNEM_SUFFIX
;
6236 for (op
= i
.operands
; --op
>= 0;)
6237 if (operand_type_check (i
.types
[op
], imm
))
6239 switch (i
.op
[op
].imms
->X_op
)
6242 /* If a suffix is given, this operand may be shortened. */
6243 switch (guess_suffix
)
6245 case LONG_MNEM_SUFFIX
:
6246 i
.types
[op
].bitfield
.imm32
= 1;
6247 i
.types
[op
].bitfield
.imm64
= 1;
6249 case WORD_MNEM_SUFFIX
:
6250 i
.types
[op
].bitfield
.imm16
= 1;
6251 i
.types
[op
].bitfield
.imm32
= 1;
6252 i
.types
[op
].bitfield
.imm32s
= 1;
6253 i
.types
[op
].bitfield
.imm64
= 1;
6255 case BYTE_MNEM_SUFFIX
:
6256 i
.types
[op
].bitfield
.imm8
= 1;
6257 i
.types
[op
].bitfield
.imm8s
= 1;
6258 i
.types
[op
].bitfield
.imm16
= 1;
6259 i
.types
[op
].bitfield
.imm32
= 1;
6260 i
.types
[op
].bitfield
.imm32s
= 1;
6261 i
.types
[op
].bitfield
.imm64
= 1;
6265 /* If this operand is at most 16 bits, convert it
6266 to a signed 16 bit number before trying to see
6267 whether it will fit in an even smaller size.
6268 This allows a 16-bit operand such as $0xffe0 to
6269 be recognised as within Imm8S range. */
6270 if ((i
.types
[op
].bitfield
.imm16
)
6271 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6273 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6274 ^ 0x8000) - 0x8000);
6277 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6278 if ((i
.types
[op
].bitfield
.imm32
)
6279 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6281 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6282 ^ ((offsetT
) 1 << 31))
6283 - ((offsetT
) 1 << 31));
6287 = operand_type_or (i
.types
[op
],
6288 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6290 /* We must avoid matching of Imm32 templates when 64bit
6291 only immediate is available. */
6292 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6293 i
.types
[op
].bitfield
.imm32
= 0;
6300 /* Symbols and expressions. */
6302 /* Convert symbolic operand to proper sizes for matching, but don't
6303 prevent matching a set of insns that only supports sizes other
6304 than those matching the insn suffix. */
6306 i386_operand_type mask
, allowed
;
6307 const insn_template
*t
= current_templates
->start
;
6309 operand_type_set (&mask
, 0);
6310 switch (guess_suffix
)
6312 case QWORD_MNEM_SUFFIX
:
6313 mask
.bitfield
.imm64
= 1;
6314 mask
.bitfield
.imm32s
= 1;
6316 case LONG_MNEM_SUFFIX
:
6317 mask
.bitfield
.imm32
= 1;
6319 case WORD_MNEM_SUFFIX
:
6320 mask
.bitfield
.imm16
= 1;
6322 case BYTE_MNEM_SUFFIX
:
6323 mask
.bitfield
.imm8
= 1;
6329 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6330 while (++t
< current_templates
->end
)
6332 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6333 allowed
= operand_type_and (allowed
, mask
);
6336 if (!operand_type_all_zero (&allowed
))
6337 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6344 /* Try to use the smallest displacement type too. */
6346 optimize_disp (const insn_template
*t
)
6350 if (!want_disp32 (t
)
6351 && (!t
->opcode_modifier
.jump
6352 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6354 for (op
= 0; op
< i
.operands
; ++op
)
6356 const expressionS
*exp
= i
.op
[op
].disps
;
6358 if (!operand_type_check (i
.types
[op
], disp
))
6361 if (exp
->X_op
!= O_constant
)
6364 /* Since displacement is signed extended to 64bit, don't allow
6365 disp32 if it is out of range. */
6366 if (fits_in_signed_long (exp
->X_add_number
))
6369 i
.types
[op
].bitfield
.disp32
= 0;
6370 if (i
.types
[op
].bitfield
.baseindex
)
6372 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6373 (uint64_t) exp
->X_add_number
);
6379 /* Don't optimize displacement for movabs since it only takes 64bit
6381 if (i
.disp_encoding
> disp_encoding_8bit
6382 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6385 for (op
= i
.operands
; op
-- > 0;)
6386 if (operand_type_check (i
.types
[op
], disp
))
6388 if (i
.op
[op
].disps
->X_op
== O_constant
)
6390 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6392 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6394 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6395 i
.op
[op
].disps
= NULL
;
6400 if (i
.types
[op
].bitfield
.disp16
6401 && fits_in_unsigned_word (op_disp
))
6403 /* If this operand is at most 16 bits, convert
6404 to a signed 16 bit number and don't use 64bit
6406 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6407 i
.types
[op
].bitfield
.disp64
= 0;
6411 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6412 if ((flag_code
!= CODE_64BIT
6413 ? i
.types
[op
].bitfield
.disp32
6415 && (!t
->opcode_modifier
.jump
6416 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6417 && fits_in_unsigned_long (op_disp
))
6419 /* If this operand is at most 32 bits, convert
6420 to a signed 32 bit number and don't use 64bit
6422 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6423 i
.types
[op
].bitfield
.disp64
= 0;
6424 i
.types
[op
].bitfield
.disp32
= 1;
6427 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6429 i
.types
[op
].bitfield
.disp64
= 0;
6430 i
.types
[op
].bitfield
.disp32
= 1;
6433 if ((i
.types
[op
].bitfield
.disp32
6434 || i
.types
[op
].bitfield
.disp16
)
6435 && fits_in_disp8 (op_disp
))
6436 i
.types
[op
].bitfield
.disp8
= 1;
6438 i
.op
[op
].disps
->X_add_number
= op_disp
;
6440 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6441 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6443 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6444 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6445 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6448 /* We only support 64bit displacement on constants. */
6449 i
.types
[op
].bitfield
.disp64
= 0;
6455 /* Return 1 if there is a match in broadcast bytes between operand
6456 GIVEN and instruction template T. */
6459 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6461 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6462 && i
.types
[given
].bitfield
.byte
)
6463 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6464 && i
.types
[given
].bitfield
.word
)
6465 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6466 && i
.types
[given
].bitfield
.dword
)
6467 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6468 && i
.types
[given
].bitfield
.qword
));
6471 /* Check if operands are valid for the instruction. */
6474 check_VecOperands (const insn_template
*t
)
6479 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6480 any one operand are implicity requiring AVX512VL support if the actual
6481 operand size is YMMword or XMMword. Since this function runs after
6482 template matching, there's no need to check for YMMword/XMMword in
6484 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6485 if (!cpu_flags_all_zero (&cpu
)
6486 && !is_cpu (t
, CpuAVX512VL
)
6487 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6489 for (op
= 0; op
< t
->operands
; ++op
)
6491 if (t
->operand_types
[op
].bitfield
.zmmword
6492 && (i
.types
[op
].bitfield
.ymmword
6493 || i
.types
[op
].bitfield
.xmmword
))
6495 i
.error
= unsupported
;
6501 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6502 requiring AVX2 support if the actual operand size is YMMword. */
6503 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6504 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6506 for (op
= 0; op
< t
->operands
; ++op
)
6508 if (t
->operand_types
[op
].bitfield
.xmmword
6509 && i
.types
[op
].bitfield
.ymmword
)
6511 i
.error
= unsupported
;
6517 /* Without VSIB byte, we can't have a vector register for index. */
6518 if (!t
->opcode_modifier
.sib
6520 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6521 || i
.index_reg
->reg_type
.bitfield
.ymmword
6522 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6524 i
.error
= unsupported_vector_index_register
;
6528 /* Check if default mask is allowed. */
6529 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6530 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6532 i
.error
= no_default_mask
;
6536 /* For VSIB byte, we need a vector register for index, and all vector
6537 registers must be distinct. */
6538 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6541 || !((t
->opcode_modifier
.sib
== VECSIB128
6542 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6543 || (t
->opcode_modifier
.sib
== VECSIB256
6544 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6545 || (t
->opcode_modifier
.sib
== VECSIB512
6546 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6548 i
.error
= invalid_vsib_address
;
6552 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6553 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6555 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6556 gas_assert (i
.types
[0].bitfield
.xmmword
6557 || i
.types
[0].bitfield
.ymmword
);
6558 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6559 gas_assert (i
.types
[2].bitfield
.xmmword
6560 || i
.types
[2].bitfield
.ymmword
);
6561 if (operand_check
== check_none
)
6563 if (register_number (i
.op
[0].regs
)
6564 != register_number (i
.index_reg
)
6565 && register_number (i
.op
[2].regs
)
6566 != register_number (i
.index_reg
)
6567 && register_number (i
.op
[0].regs
)
6568 != register_number (i
.op
[2].regs
))
6570 if (operand_check
== check_error
)
6572 i
.error
= invalid_vector_register_set
;
6575 as_warn (_("mask, index, and destination registers should be distinct"));
6577 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6579 if (i
.types
[1].bitfield
.class == RegSIMD
6580 && (i
.types
[1].bitfield
.xmmword
6581 || i
.types
[1].bitfield
.ymmword
6582 || i
.types
[1].bitfield
.zmmword
)
6583 && (register_number (i
.op
[1].regs
)
6584 == register_number (i
.index_reg
)))
6586 if (operand_check
== check_error
)
6588 i
.error
= invalid_vector_register_set
;
6591 if (operand_check
!= check_none
)
6592 as_warn (_("index and destination registers should be distinct"));
6597 /* For AMX instructions with 3 TMM register operands, all operands
6598 must be distinct. */
6599 if (i
.reg_operands
== 3
6600 && t
->operand_types
[0].bitfield
.tmmword
6601 && (i
.op
[0].regs
== i
.op
[1].regs
6602 || i
.op
[0].regs
== i
.op
[2].regs
6603 || i
.op
[1].regs
== i
.op
[2].regs
))
6605 i
.error
= invalid_tmm_register_set
;
6609 /* For some special instructions require that destination must be distinct
6610 from source registers. */
6611 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6613 unsigned int dest_reg
= i
.operands
- 1;
6615 know (i
.operands
>= 3);
6617 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6618 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6619 || (i
.reg_operands
> 2
6620 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6622 i
.error
= invalid_dest_and_src_register_set
;
6627 /* Check if broadcast is supported by the instruction and is applied
6628 to the memory operand. */
6629 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6631 i386_operand_type type
, overlap
;
6633 /* Check if specified broadcast is supported in this instruction,
6634 and its broadcast bytes match the memory operand. */
6635 op
= i
.broadcast
.operand
;
6636 if (!t
->opcode_modifier
.broadcast
6637 || !(i
.flags
[op
] & Operand_Mem
)
6638 || (!i
.types
[op
].bitfield
.unspecified
6639 && !match_broadcast_size (t
, op
)))
6642 i
.error
= unsupported_broadcast
;
6646 operand_type_set (&type
, 0);
6647 switch (get_broadcast_bytes (t
, false))
6650 type
.bitfield
.word
= 1;
6653 type
.bitfield
.dword
= 1;
6656 type
.bitfield
.qword
= 1;
6659 type
.bitfield
.xmmword
= 1;
6662 if (vector_size
< VSZ256
)
6664 type
.bitfield
.ymmword
= 1;
6667 if (vector_size
< VSZ512
)
6669 type
.bitfield
.zmmword
= 1;
6675 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6676 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6677 && t
->operand_types
[op
].bitfield
.byte
6678 + t
->operand_types
[op
].bitfield
.word
6679 + t
->operand_types
[op
].bitfield
.dword
6680 + t
->operand_types
[op
].bitfield
.qword
> 1)
6682 overlap
.bitfield
.xmmword
= 0;
6683 overlap
.bitfield
.ymmword
= 0;
6684 overlap
.bitfield
.zmmword
= 0;
6686 if (operand_type_all_zero (&overlap
))
6689 if (t
->opcode_modifier
.checkoperandsize
)
6693 type
.bitfield
.baseindex
= 1;
6694 for (j
= 0; j
< i
.operands
; ++j
)
6697 && !operand_type_register_match(i
.types
[j
],
6698 t
->operand_types
[j
],
6700 t
->operand_types
[op
]))
6705 /* If broadcast is supported in this instruction, we need to check if
6706 operand of one-element size isn't specified without broadcast. */
6707 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6709 /* Find memory operand. */
6710 for (op
= 0; op
< i
.operands
; op
++)
6711 if (i
.flags
[op
] & Operand_Mem
)
6713 gas_assert (op
< i
.operands
);
6714 /* Check size of the memory operand. */
6715 if (match_broadcast_size (t
, op
))
6717 i
.error
= broadcast_needed
;
6722 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6724 /* Check if requested masking is supported. */
6727 if (!t
->opcode_modifier
.masking
)
6729 i
.error
= unsupported_masking
;
6733 /* Common rules for masking:
6734 - mask register destinations permit only zeroing-masking, without
6735 that actually being expressed by a {z} operand suffix or EVEX.z,
6736 - memory destinations allow only merging-masking,
6737 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6740 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6741 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6742 || t
->opcode_modifier
.sib
))
6744 i
.error
= unsupported_masking
;
6749 /* Check if masking is applied to dest operand. */
6750 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6752 i
.error
= mask_not_on_destination
;
6757 if (i
.rounding
.type
!= rc_none
)
6759 if (!t
->opcode_modifier
.sae
6760 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6763 i
.error
= unsupported_rc_sae
;
6767 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6769 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6771 for (op
= 0; op
< t
->operands
; ++op
)
6772 if (i
.types
[op
].bitfield
.zmmword
)
6774 if (op
>= t
->operands
)
6776 i
.error
= operand_size_mismatch
;
6782 /* Check the special Imm4 cases; must be the first operand. */
6783 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6785 if (i
.op
[0].imms
->X_op
!= O_constant
6786 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6792 /* Turn off Imm<N> so that update_imm won't complain. */
6793 operand_type_set (&i
.types
[0], 0);
6796 /* Check vector Disp8 operand. */
6797 if (t
->opcode_modifier
.disp8memshift
6798 && i
.disp_encoding
<= disp_encoding_8bit
)
6800 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6801 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6802 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6803 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6806 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6809 for (op
= 0; op
< i
.operands
; op
++)
6810 if (i
.flags
[op
] & Operand_Mem
)
6812 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6813 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6814 else if (t
->operand_types
[op
].bitfield
.xmmword
6815 + t
->operand_types
[op
].bitfield
.ymmword
6816 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6817 type
= &t
->operand_types
[op
];
6818 else if (!i
.types
[op
].bitfield
.unspecified
)
6819 type
= &i
.types
[op
];
6820 else /* Ambiguities get resolved elsewhere. */
6821 fallback
= &t
->operand_types
[op
];
6823 else if (i
.types
[op
].bitfield
.class == RegSIMD
6824 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6826 if (i
.types
[op
].bitfield
.zmmword
)
6828 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6830 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6834 if (!type
&& !i
.memshift
)
6838 if (type
->bitfield
.zmmword
)
6840 else if (type
->bitfield
.ymmword
)
6842 else if (type
->bitfield
.xmmword
)
6846 /* For the check in fits_in_disp8(). */
6847 if (i
.memshift
== 0)
6851 for (op
= 0; op
< i
.operands
; op
++)
6852 if (operand_type_check (i
.types
[op
], disp
)
6853 && i
.op
[op
].disps
->X_op
== O_constant
)
6855 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6857 i
.types
[op
].bitfield
.disp8
= 1;
6860 i
.types
[op
].bitfield
.disp8
= 0;
6869 /* Check if encoding requirements are met by the instruction. */
6872 VEX_check_encoding (const insn_template
*t
)
6874 if (i
.vec_encoding
== vex_encoding_error
)
6876 i
.error
= unsupported
;
6880 /* Vector size restrictions. */
6881 if ((vector_size
< VSZ512
6882 && (t
->opcode_modifier
.evex
== EVEX512
6883 || t
->opcode_modifier
.vsz
>= VSZ512
))
6884 || (vector_size
< VSZ256
6885 && (t
->opcode_modifier
.evex
== EVEX256
6886 || t
->opcode_modifier
.vex
== VEX256
6887 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6889 i
.error
= unsupported
;
6893 if (i
.vec_encoding
== vex_encoding_evex
)
6895 /* This instruction must be encoded with EVEX prefix. */
6896 if (!is_evex_encoding (t
))
6898 i
.error
= unsupported
;
6904 if (!t
->opcode_modifier
.vex
)
6906 /* This instruction template doesn't have VEX prefix. */
6907 if (i
.vec_encoding
!= vex_encoding_default
)
6909 i
.error
= unsupported
;
6918 /* Helper function for the progress() macro in match_template(). */
6919 static INLINE
enum i386_error
progress (enum i386_error
new,
6920 enum i386_error last
,
6921 unsigned int line
, unsigned int *line_p
)
6923 if (line
<= *line_p
)
6929 static const insn_template
*
6930 match_template (char mnem_suffix
)
6932 /* Points to template once we've found it. */
6933 const insn_template
*t
;
6934 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6935 i386_operand_type overlap4
;
6936 unsigned int found_reverse_match
;
6937 i386_operand_type operand_types
[MAX_OPERANDS
];
6938 int addr_prefix_disp
;
6939 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6940 enum i386_error specific_error
= number_of_operands_mismatch
;
6941 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6943 #if MAX_OPERANDS != 5
6944 # error "MAX_OPERANDS must be 5."
6947 found_reverse_match
= 0;
6948 addr_prefix_disp
= -1;
6950 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6952 addr_prefix_disp
= -1;
6953 found_reverse_match
= 0;
6955 /* Must have right number of operands. */
6956 if (i
.operands
!= t
->operands
)
6959 /* Check processor support. */
6960 specific_error
= progress (unsupported
);
6961 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6964 /* Check AT&T mnemonic. */
6965 specific_error
= progress (unsupported_with_intel_mnemonic
);
6966 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6969 /* Check AT&T/Intel syntax. */
6970 specific_error
= progress (unsupported_syntax
);
6971 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6972 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6975 /* Check Intel64/AMD64 ISA. */
6979 /* Default: Don't accept Intel64. */
6980 if (t
->opcode_modifier
.isa64
== INTEL64
)
6984 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6985 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6989 /* -mintel64: Don't accept AMD64. */
6990 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6995 /* Check the suffix. */
6996 specific_error
= progress (invalid_instruction_suffix
);
6997 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6998 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6999 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7000 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7001 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7004 specific_error
= progress (operand_size_mismatch
);
7005 size_match
= operand_size_match (t
);
7009 /* This is intentionally not
7011 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7013 as the case of a missing * on the operand is accepted (perhaps with
7014 a warning, issued further down). */
7015 specific_error
= progress (operand_type_mismatch
);
7016 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7019 /* In Intel syntax, normally we can check for memory operand size when
7020 there is no mnemonic suffix. But jmp and call have 2 different
7021 encodings with Dword memory operand size. Skip the "near" one
7022 (permitting a register operand) when "far" was requested. */
7024 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7025 && t
->operand_types
[0].bitfield
.class == Reg
)
7028 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7029 operand_types
[j
] = t
->operand_types
[j
];
7031 /* In general, don't allow 32-bit operands on pre-386. */
7032 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7033 : operand_size_mismatch
);
7034 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7035 if (i
.suffix
== LONG_MNEM_SUFFIX
7036 && !cpu_arch_flags
.bitfield
.cpui386
7038 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7039 && !intel_float_operand (insn_name (t
)))
7040 : intel_float_operand (insn_name (t
)) != 2)
7041 && (t
->operands
== i
.imm_operands
7042 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7043 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7044 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7045 || (operand_types
[j
].bitfield
.class != RegMMX
7046 && operand_types
[j
].bitfield
.class != RegSIMD
7047 && operand_types
[j
].bitfield
.class != RegMask
))
7048 && !t
->opcode_modifier
.sib
)
7051 /* Do not verify operands when there are none. */
7054 if (VEX_check_encoding (t
))
7056 specific_error
= progress (i
.error
);
7060 /* We've found a match; break out of loop. */
7064 if (!t
->opcode_modifier
.jump
7065 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7067 /* There should be only one Disp operand. */
7068 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7069 if (operand_type_check (operand_types
[j
], disp
))
7071 if (j
< MAX_OPERANDS
)
7073 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7075 addr_prefix_disp
= j
;
7077 /* Address size prefix will turn Disp64 operand into Disp32 and
7078 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7082 override
= !override
;
7085 if (operand_types
[j
].bitfield
.disp32
7086 && operand_types
[j
].bitfield
.disp16
)
7088 operand_types
[j
].bitfield
.disp16
= override
;
7089 operand_types
[j
].bitfield
.disp32
= !override
;
7091 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7095 if (operand_types
[j
].bitfield
.disp64
)
7097 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7098 operand_types
[j
].bitfield
.disp32
= override
;
7099 operand_types
[j
].bitfield
.disp64
= !override
;
7101 operand_types
[j
].bitfield
.disp16
= 0;
7107 /* We check register size if needed. */
7108 if (t
->opcode_modifier
.checkoperandsize
)
7110 check_register
= (1 << t
->operands
) - 1;
7111 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7112 check_register
&= ~(1 << i
.broadcast
.operand
);
7117 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7118 switch (t
->operands
)
7121 if (!operand_type_match (overlap0
, i
.types
[0]))
7124 /* Allow the ModR/M encoding to be requested by using the {load} or
7125 {store} pseudo prefix on an applicable insn. */
7126 if (!t
->opcode_modifier
.modrm
7127 && i
.reg_operands
== 1
7128 && ((i
.dir_encoding
== dir_encoding_load
7129 && t
->mnem_off
!= MN_pop
)
7130 || (i
.dir_encoding
== dir_encoding_store
7131 && t
->mnem_off
!= MN_push
))
7133 && t
->mnem_off
!= MN_bswap
)
7138 /* xchg %eax, %eax is a special case. It is an alias for nop
7139 only in 32bit mode and we can use opcode 0x90. In 64bit
7140 mode, we can't use 0x90 for xchg %eax, %eax since it should
7141 zero-extend %eax to %rax. */
7142 if (t
->base_opcode
== 0x90
7143 && t
->opcode_space
== SPACE_BASE
)
7145 if (flag_code
== CODE_64BIT
7146 && i
.types
[0].bitfield
.instance
== Accum
7147 && i
.types
[0].bitfield
.dword
7148 && i
.types
[1].bitfield
.instance
== Accum
)
7151 /* Allow the ModR/M encoding to be requested by using the
7152 {load} or {store} pseudo prefix. */
7153 if (i
.dir_encoding
== dir_encoding_load
7154 || i
.dir_encoding
== dir_encoding_store
)
7158 if (t
->base_opcode
== MOV_AX_DISP32
7159 && t
->opcode_space
== SPACE_BASE
7160 && t
->mnem_off
!= MN_movabs
)
7162 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7163 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7166 /* xrelease mov %eax, <disp> is another special case. It must not
7167 match the accumulator-only encoding of mov. */
7171 /* Allow the ModR/M encoding to be requested by using a suitable
7172 {load} or {store} pseudo prefix. */
7173 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7174 ? dir_encoding_store
7175 : dir_encoding_load
)
7176 && !i
.types
[0].bitfield
.disp64
7177 && !i
.types
[1].bitfield
.disp64
)
7181 /* Allow the ModR/M encoding to be requested by using the {load} or
7182 {store} pseudo prefix on an applicable insn. */
7183 if (!t
->opcode_modifier
.modrm
7184 && i
.reg_operands
== 1
7185 && i
.imm_operands
== 1
7186 && (i
.dir_encoding
== dir_encoding_load
7187 || i
.dir_encoding
== dir_encoding_store
)
7188 && t
->opcode_space
== SPACE_BASE
)
7190 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7191 && i
.dir_encoding
== dir_encoding_store
)
7194 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7195 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7196 || i
.dir_encoding
== dir_encoding_load
))
7199 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7200 && i
.dir_encoding
== dir_encoding_load
)
7206 if (!(size_match
& MATCH_STRAIGHT
))
7208 /* Reverse direction of operands if swapping is possible in the first
7209 place (operands need to be symmetric) and
7210 - the load form is requested, and the template is a store form,
7211 - the store form is requested, and the template is a load form,
7212 - the non-default (swapped) form is requested. */
7213 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7214 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7215 && !operand_type_all_zero (&overlap1
))
7216 switch (i
.dir_encoding
)
7218 case dir_encoding_load
:
7219 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7220 || t
->opcode_modifier
.regmem
)
7224 case dir_encoding_store
:
7225 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7226 && !t
->opcode_modifier
.regmem
)
7230 case dir_encoding_swap
:
7233 case dir_encoding_default
:
7236 /* If we want store form, we skip the current load. */
7237 if ((i
.dir_encoding
== dir_encoding_store
7238 || i
.dir_encoding
== dir_encoding_swap
)
7239 && i
.mem_operands
== 0
7240 && t
->opcode_modifier
.load
)
7245 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7246 if (!operand_type_match (overlap0
, i
.types
[0])
7247 || !operand_type_match (overlap1
, i
.types
[1])
7248 || ((check_register
& 3) == 3
7249 && !operand_type_register_match (i
.types
[0],
7254 specific_error
= progress (i
.error
);
7256 /* Check if other direction is valid ... */
7257 if (!t
->opcode_modifier
.d
)
7261 if (!(size_match
& MATCH_REVERSE
))
7263 /* Try reversing direction of operands. */
7264 j
= is_cpu (t
, CpuFMA4
)
7265 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7266 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7267 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7268 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7269 gas_assert (t
->operands
!= 3 || !check_register
);
7270 if (!operand_type_match (overlap0
, i
.types
[0])
7271 || !operand_type_match (overlap1
, i
.types
[j
])
7272 || (t
->operands
== 3
7273 && !operand_type_match (overlap2
, i
.types
[1]))
7275 && !operand_type_register_match (i
.types
[0],
7280 /* Does not match either direction. */
7281 specific_error
= progress (i
.error
);
7284 /* found_reverse_match holds which variant of D
7286 if (!t
->opcode_modifier
.d
)
7287 found_reverse_match
= 0;
7288 else if (operand_types
[0].bitfield
.tbyte
)
7290 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7291 found_reverse_match
= Opcode_FloatD
;
7293 found_reverse_match
= ~0;
7294 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7295 if ((t
->extension_opcode
& 4)
7296 && (intel_syntax
|| intel_mnemonic
))
7297 found_reverse_match
|= Opcode_FloatR
;
7299 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7301 found_reverse_match
= Opcode_VexW
;
7302 goto check_operands_345
;
7304 else if (t
->opcode_space
!= SPACE_BASE
7305 && (t
->opcode_space
!= SPACE_0F
7306 /* MOV to/from CR/DR/TR, as an exception, follow
7307 the base opcode space encoding model. */
7308 || (t
->base_opcode
| 7) != 0x27))
7309 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7310 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7311 else if (!t
->opcode_modifier
.commutative
)
7312 found_reverse_match
= Opcode_D
;
7314 found_reverse_match
= ~0;
7318 /* Found a forward 2 operand match here. */
7320 switch (t
->operands
)
7323 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7324 if (!operand_type_match (overlap4
, i
.types
[4])
7325 || !operand_type_register_match (i
.types
[3],
7330 specific_error
= progress (i
.error
);
7335 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7336 if (!operand_type_match (overlap3
, i
.types
[3])
7337 || ((check_register
& 0xa) == 0xa
7338 && !operand_type_register_match (i
.types
[1],
7342 || ((check_register
& 0xc) == 0xc
7343 && !operand_type_register_match (i
.types
[2],
7348 specific_error
= progress (i
.error
);
7353 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7354 if (!operand_type_match (overlap2
, i
.types
[2])
7355 || ((check_register
& 5) == 5
7356 && !operand_type_register_match (i
.types
[0],
7360 || ((check_register
& 6) == 6
7361 && !operand_type_register_match (i
.types
[1],
7366 specific_error
= progress (i
.error
);
7372 /* Found either forward/reverse 2, 3 or 4 operand match here:
7373 slip through to break. */
7376 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7377 if (VEX_check_encoding (t
))
7379 specific_error
= progress (i
.error
);
7383 /* Check if vector operands are valid. */
7384 if (check_VecOperands (t
))
7386 specific_error
= progress (i
.error
);
7390 /* We've found a match; break out of loop. */
7396 if (t
== current_templates
->end
)
7398 /* We found no match. */
7399 i
.error
= specific_error
;
7403 if (!quiet_warnings
)
7406 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7407 as_warn (_("indirect %s without `*'"), insn_name (t
));
7409 if (t
->opcode_modifier
.isprefix
7410 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7412 /* Warn them that a data or address size prefix doesn't
7413 affect assembly of the next line of code. */
7414 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7418 /* Copy the template we found. */
7419 install_template (t
);
7421 if (addr_prefix_disp
!= -1)
7422 i
.tm
.operand_types
[addr_prefix_disp
]
7423 = operand_types
[addr_prefix_disp
];
7425 switch (found_reverse_match
)
7431 case Opcode_FloatR
| Opcode_FloatD
:
7432 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7433 found_reverse_match
&= Opcode_FloatD
;
7437 /* If we found a reverse match we must alter the opcode direction
7438 bit and clear/flip the regmem modifier one. found_reverse_match
7439 holds bits to change (different for int & float insns). */
7441 i
.tm
.base_opcode
^= found_reverse_match
;
7443 /* Certain SIMD insns have their load forms specified in the opcode
7444 table, and hence we need to _set_ RegMem instead of clearing it.
7445 We need to avoid setting the bit though on insns like KMOVW. */
7446 i
.tm
.opcode_modifier
.regmem
7447 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7448 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7449 && !i
.tm
.opcode_modifier
.regmem
;
7453 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7454 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7458 /* Only the first two register operands need reversing, alongside
7460 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7462 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7463 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7464 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7474 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7475 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7477 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7479 as_bad (_("`%s' operand %u must use `%ses' segment"),
7481 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7486 /* There's only ever one segment override allowed per instruction.
7487 This instruction possibly has a legal segment override on the
7488 second operand, so copy the segment to where non-string
7489 instructions store it, allowing common code. */
7490 i
.seg
[op
] = i
.seg
[1];
7496 process_suffix (void)
7498 bool is_movx
= false;
7500 /* If matched instruction specifies an explicit instruction mnemonic
7502 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7503 i
.suffix
= WORD_MNEM_SUFFIX
;
7504 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7505 i
.suffix
= LONG_MNEM_SUFFIX
;
7506 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7507 i
.suffix
= QWORD_MNEM_SUFFIX
;
7508 else if (i
.reg_operands
7509 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7510 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7512 unsigned int numop
= i
.operands
;
7515 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7516 && (i
.tm
.base_opcode
| 8) == 0xbe)
7517 || (i
.tm
.opcode_space
== SPACE_BASE
7518 && i
.tm
.base_opcode
== 0x63
7519 && is_cpu (&i
.tm
, Cpu64
));
7521 /* movsx/movzx want only their source operand considered here, for the
7522 ambiguity checking below. The suffix will be replaced afterwards
7523 to represent the destination (register). */
7524 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7527 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7528 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7531 /* If there's no instruction mnemonic suffix we try to invent one
7532 based on GPR operands. */
7535 /* We take i.suffix from the last register operand specified,
7536 Destination register type is more significant than source
7537 register type. crc32 in SSE4.2 prefers source register
7539 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7542 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7543 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7545 if (i
.types
[op
].bitfield
.class != Reg
)
7547 if (i
.types
[op
].bitfield
.byte
)
7548 i
.suffix
= BYTE_MNEM_SUFFIX
;
7549 else if (i
.types
[op
].bitfield
.word
)
7550 i
.suffix
= WORD_MNEM_SUFFIX
;
7551 else if (i
.types
[op
].bitfield
.dword
)
7552 i
.suffix
= LONG_MNEM_SUFFIX
;
7553 else if (i
.types
[op
].bitfield
.qword
)
7554 i
.suffix
= QWORD_MNEM_SUFFIX
;
7560 /* As an exception, movsx/movzx silently default to a byte source
7562 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7563 i
.suffix
= BYTE_MNEM_SUFFIX
;
7565 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7567 if (!check_byte_reg ())
7570 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7572 if (!check_long_reg ())
7575 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7577 if (!check_qword_reg ())
7580 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7582 if (!check_word_reg ())
7585 else if (intel_syntax
7586 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7587 /* Do nothing if the instruction is going to ignore the prefix. */
7592 /* Undo the movsx/movzx change done above. */
7595 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7598 i
.suffix
= stackop_size
;
7599 if (stackop_size
== LONG_MNEM_SUFFIX
)
7601 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7602 .code16gcc directive to support 16-bit mode with
7603 32-bit address. For IRET without a suffix, generate
7604 16-bit IRET (opcode 0xcf) to return from an interrupt
7606 if (i
.tm
.base_opcode
== 0xcf)
7608 i
.suffix
= WORD_MNEM_SUFFIX
;
7609 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7611 /* Warn about changed behavior for segment register push/pop. */
7612 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7613 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7618 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7619 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7620 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7621 || (i
.tm
.opcode_space
== SPACE_0F
7622 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7623 && i
.tm
.extension_opcode
<= 3)))
7628 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7630 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7631 || i
.tm
.opcode_modifier
.no_lsuf
)
7632 i
.suffix
= QWORD_MNEM_SUFFIX
;
7637 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7638 i
.suffix
= LONG_MNEM_SUFFIX
;
7641 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7642 i
.suffix
= WORD_MNEM_SUFFIX
;
7648 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7649 /* Also cover lret/retf/iret in 64-bit mode. */
7650 || (flag_code
== CODE_64BIT
7651 && !i
.tm
.opcode_modifier
.no_lsuf
7652 && !i
.tm
.opcode_modifier
.no_qsuf
))
7653 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7654 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7655 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7656 /* Accept FLDENV et al without suffix. */
7657 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7659 unsigned int suffixes
, evex
= 0;
7661 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7662 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7664 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7666 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7668 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7671 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7672 also suitable for AT&T syntax mode, it was requested that this be
7673 restricted to just Intel syntax. */
7674 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7675 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7679 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7681 if (vector_size
< VSZ512
)
7683 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7684 if (vector_size
< VSZ256
)
7686 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7687 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7688 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7689 || (!i
.tm
.opcode_modifier
.evex
7690 && is_evex_encoding (&i
.tm
))))
7691 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7693 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7694 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7695 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7696 || (!i
.tm
.opcode_modifier
.evex
7697 && is_evex_encoding (&i
.tm
))))
7698 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7700 else if (is_evex_encoding (&i
.tm
)
7701 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7703 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7704 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7705 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7706 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7707 if (!i
.tm
.opcode_modifier
.evex
7708 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7709 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7712 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7713 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7714 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7717 /* Any properly sized operand disambiguates the insn. */
7718 if (i
.types
[op
].bitfield
.xmmword
7719 || i
.types
[op
].bitfield
.ymmword
7720 || i
.types
[op
].bitfield
.zmmword
)
7722 suffixes
&= ~(7 << 6);
7727 if ((i
.flags
[op
] & Operand_Mem
)
7728 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7730 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7732 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7734 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7736 if (is_evex_encoding (&i
.tm
))
7742 /* Are multiple suffixes / operand sizes allowed? */
7743 if (suffixes
& (suffixes
- 1))
7746 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7747 || operand_check
== check_error
))
7749 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7752 if (operand_check
== check_error
)
7754 as_bad (_("no instruction mnemonic suffix given and "
7755 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7758 if (operand_check
== check_warning
)
7759 as_warn (_("%s; using default for `%s'"),
7761 ? _("ambiguous operand size")
7762 : _("no instruction mnemonic suffix given and "
7763 "no register operands"),
7766 if (i
.tm
.opcode_modifier
.floatmf
)
7767 i
.suffix
= SHORT_MNEM_SUFFIX
;
7769 /* handled below */;
7771 i
.tm
.opcode_modifier
.evex
= evex
;
7772 else if (flag_code
== CODE_16BIT
)
7773 i
.suffix
= WORD_MNEM_SUFFIX
;
7774 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7775 i
.suffix
= LONG_MNEM_SUFFIX
;
7777 i
.suffix
= QWORD_MNEM_SUFFIX
;
7783 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7784 In AT&T syntax, if there is no suffix (warned about above), the default
7785 will be byte extension. */
7786 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7787 i
.tm
.base_opcode
|= 1;
7789 /* For further processing, the suffix should represent the destination
7790 (register). This is already the case when one was used with
7791 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7792 no suffix to begin with. */
7793 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7795 if (i
.types
[1].bitfield
.word
)
7796 i
.suffix
= WORD_MNEM_SUFFIX
;
7797 else if (i
.types
[1].bitfield
.qword
)
7798 i
.suffix
= QWORD_MNEM_SUFFIX
;
7800 i
.suffix
= LONG_MNEM_SUFFIX
;
7802 i
.tm
.opcode_modifier
.w
= 0;
7806 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7807 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7808 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7810 /* Change the opcode based on the operand size given by i.suffix. */
7813 /* Size floating point instruction. */
7814 case LONG_MNEM_SUFFIX
:
7815 if (i
.tm
.opcode_modifier
.floatmf
)
7817 i
.tm
.base_opcode
^= 4;
7821 case WORD_MNEM_SUFFIX
:
7822 case QWORD_MNEM_SUFFIX
:
7823 /* It's not a byte, select word/dword operation. */
7824 if (i
.tm
.opcode_modifier
.w
)
7827 i
.tm
.base_opcode
|= 8;
7829 i
.tm
.base_opcode
|= 1;
7832 case SHORT_MNEM_SUFFIX
:
7833 /* Now select between word & dword operations via the operand
7834 size prefix, except for instructions that will ignore this
7836 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7837 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7838 && !i
.tm
.opcode_modifier
.floatmf
7839 && !is_any_vex_encoding (&i
.tm
)
7840 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7841 || (flag_code
== CODE_64BIT
7842 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7844 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7846 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7847 prefix
= ADDR_PREFIX_OPCODE
;
7849 if (!add_prefix (prefix
))
7853 /* Set mode64 for an operand. */
7854 if (i
.suffix
== QWORD_MNEM_SUFFIX
7855 && flag_code
== CODE_64BIT
7856 && !i
.tm
.opcode_modifier
.norex64
7857 && !i
.tm
.opcode_modifier
.vexw
7858 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7860 && ! (i
.operands
== 2
7861 && i
.tm
.base_opcode
== 0x90
7862 && i
.tm
.opcode_space
== SPACE_BASE
7863 && i
.types
[0].bitfield
.instance
== Accum
7864 && i
.types
[0].bitfield
.qword
7865 && i
.types
[1].bitfield
.instance
== Accum
))
7871 /* Select word/dword/qword operation with explicit data sizing prefix
7872 when there are no suitable register operands. */
7873 if (i
.tm
.opcode_modifier
.w
7874 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7876 || (i
.reg_operands
== 1
7878 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7880 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7881 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7882 || i
.tm
.mnem_off
== MN_crc32
))))
7883 i
.tm
.base_opcode
|= 1;
7887 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7889 gas_assert (!i
.suffix
);
7890 gas_assert (i
.reg_operands
);
7892 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7895 /* The address size override prefix changes the size of the
7897 if (flag_code
== CODE_64BIT
7898 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7900 as_bad (_("16-bit addressing unavailable for `%s'"),
7905 if ((flag_code
== CODE_32BIT
7906 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7907 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7908 && !add_prefix (ADDR_PREFIX_OPCODE
))
7913 /* Check invalid register operand when the address size override
7914 prefix changes the size of register operands. */
7916 enum { need_word
, need_dword
, need_qword
} need
;
7918 /* Check the register operand for the address size prefix if
7919 the memory operand has no real registers, like symbol, DISP
7920 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7921 if (i
.mem_operands
== 1
7922 && i
.reg_operands
== 1
7924 && i
.types
[1].bitfield
.class == Reg
7925 && (flag_code
== CODE_32BIT
7926 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7927 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7928 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7929 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7930 || (x86_elf_abi
== X86_64_X32_ABI
7932 && i
.base_reg
->reg_num
== RegIP
7933 && i
.base_reg
->reg_type
.bitfield
.qword
))
7937 && !add_prefix (ADDR_PREFIX_OPCODE
))
7940 if (flag_code
== CODE_32BIT
)
7941 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7942 else if (i
.prefix
[ADDR_PREFIX
])
7945 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7947 for (op
= 0; op
< i
.operands
; op
++)
7949 if (i
.types
[op
].bitfield
.class != Reg
)
7955 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7959 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7963 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7968 as_bad (_("invalid register operand size for `%s'"),
7979 check_byte_reg (void)
7983 for (op
= i
.operands
; --op
>= 0;)
7985 /* Skip non-register operands. */
7986 if (i
.types
[op
].bitfield
.class != Reg
)
7989 /* If this is an eight bit register, it's OK. If it's the 16 or
7990 32 bit version of an eight bit register, we will just use the
7991 low portion, and that's OK too. */
7992 if (i
.types
[op
].bitfield
.byte
)
7995 /* I/O port address operands are OK too. */
7996 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7997 && i
.tm
.operand_types
[op
].bitfield
.word
)
8000 /* crc32 only wants its source operand checked here. */
8001 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8004 /* Any other register is bad. */
8005 as_bad (_("`%s%s' not allowed with `%s%c'"),
8006 register_prefix
, i
.op
[op
].regs
->reg_name
,
8007 insn_name (&i
.tm
), i
.suffix
);
8014 check_long_reg (void)
8018 for (op
= i
.operands
; --op
>= 0;)
8019 /* Skip non-register operands. */
8020 if (i
.types
[op
].bitfield
.class != Reg
)
8022 /* Reject eight bit registers, except where the template requires
8023 them. (eg. movzb) */
8024 else if (i
.types
[op
].bitfield
.byte
8025 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8026 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8027 && (i
.tm
.operand_types
[op
].bitfield
.word
8028 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8030 as_bad (_("`%s%s' not allowed with `%s%c'"),
8032 i
.op
[op
].regs
->reg_name
,
8037 /* Error if the e prefix on a general reg is missing. */
8038 else if (i
.types
[op
].bitfield
.word
8039 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8040 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8041 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8043 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8044 register_prefix
, i
.op
[op
].regs
->reg_name
,
8048 /* Warn if the r prefix on a general reg is present. */
8049 else if (i
.types
[op
].bitfield
.qword
8050 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8051 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8052 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8054 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8055 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8062 check_qword_reg (void)
8066 for (op
= i
.operands
; --op
>= 0; )
8067 /* Skip non-register operands. */
8068 if (i
.types
[op
].bitfield
.class != Reg
)
8070 /* Reject eight bit registers, except where the template requires
8071 them. (eg. movzb) */
8072 else if (i
.types
[op
].bitfield
.byte
8073 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8074 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8075 && (i
.tm
.operand_types
[op
].bitfield
.word
8076 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8078 as_bad (_("`%s%s' not allowed with `%s%c'"),
8080 i
.op
[op
].regs
->reg_name
,
8085 /* Warn if the r prefix on a general reg is missing. */
8086 else if ((i
.types
[op
].bitfield
.word
8087 || i
.types
[op
].bitfield
.dword
)
8088 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8089 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8090 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8092 /* Prohibit these changes in the 64bit mode, since the
8093 lowering is more complicated. */
8094 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8095 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8102 check_word_reg (void)
8105 for (op
= i
.operands
; --op
>= 0;)
8106 /* Skip non-register operands. */
8107 if (i
.types
[op
].bitfield
.class != Reg
)
8109 /* Reject eight bit registers, except where the template requires
8110 them. (eg. movzb) */
8111 else if (i
.types
[op
].bitfield
.byte
8112 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8113 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8114 && (i
.tm
.operand_types
[op
].bitfield
.word
8115 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8117 as_bad (_("`%s%s' not allowed with `%s%c'"),
8119 i
.op
[op
].regs
->reg_name
,
8124 /* Error if the e or r prefix on a general reg is present. */
8125 else if ((i
.types
[op
].bitfield
.dword
8126 || i
.types
[op
].bitfield
.qword
)
8127 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8128 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8129 && i
.tm
.operand_types
[op
].bitfield
.word
)
8131 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8132 register_prefix
, i
.op
[op
].regs
->reg_name
,
8140 update_imm (unsigned int j
)
8142 i386_operand_type overlap
= i
.types
[j
];
8144 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8145 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8146 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8148 /* This combination is used on 8-bit immediates where e.g. $~0 is
8149 desirable to permit. We're past operand type matching, so simply
8150 put things back in the shape they were before introducing the
8151 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8152 overlap
.bitfield
.imm8s
= 0;
8155 if (overlap
.bitfield
.imm8
8156 + overlap
.bitfield
.imm8s
8157 + overlap
.bitfield
.imm16
8158 + overlap
.bitfield
.imm32
8159 + overlap
.bitfield
.imm32s
8160 + overlap
.bitfield
.imm64
> 1)
8162 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8163 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8164 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8165 static const i386_operand_type imm16_32
= { .bitfield
=
8166 { .imm16
= 1, .imm32
= 1 }
8168 static const i386_operand_type imm16_32s
= { .bitfield
=
8169 { .imm16
= 1, .imm32s
= 1 }
8171 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8172 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8177 i386_operand_type temp
;
8179 operand_type_set (&temp
, 0);
8180 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8182 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8183 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8185 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8186 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8187 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8189 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8190 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8193 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8196 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8197 || operand_type_equal (&overlap
, &imm16_32
)
8198 || operand_type_equal (&overlap
, &imm16_32s
))
8200 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
8205 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8206 overlap
= operand_type_and (overlap
, imm32s
);
8207 else if (i
.prefix
[DATA_PREFIX
])
8208 overlap
= operand_type_and (overlap
,
8209 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8210 if (overlap
.bitfield
.imm8
8211 + overlap
.bitfield
.imm8s
8212 + overlap
.bitfield
.imm16
8213 + overlap
.bitfield
.imm32
8214 + overlap
.bitfield
.imm32s
8215 + overlap
.bitfield
.imm64
!= 1)
8217 as_bad (_("no instruction mnemonic suffix given; "
8218 "can't determine immediate size"));
8222 i
.types
[j
] = overlap
;
8232 /* Update the first 2 immediate operands. */
8233 n
= i
.operands
> 2 ? 2 : i
.operands
;
8236 for (j
= 0; j
< n
; j
++)
8237 if (update_imm (j
) == 0)
8240 /* The 3rd operand can't be immediate operand. */
8241 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8247 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8250 if (r
->reg_flags
& RegRex
)
8252 if (i
.rex
& rex_bit
)
8253 as_bad (_("same type of prefix used twice"));
8256 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8258 gas_assert (i
.vex
.register_specifier
== r
);
8259 i
.vex
.register_specifier
+= 8;
8262 if (r
->reg_flags
& RegVRex
)
8267 process_operands (void)
8269 /* Default segment register this instruction will use for memory
8270 accesses. 0 means unknown. This is only for optimizing out
8271 unnecessary segment overrides. */
8272 const reg_entry
*default_seg
= NULL
;
8274 /* We only need to check those implicit registers for instructions
8275 with 3 operands or less. */
8276 if (i
.operands
<= 3)
8277 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8278 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8281 if (i
.tm
.opcode_modifier
.sse2avx
)
8283 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8285 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8286 i
.prefix
[REX_PREFIX
] = 0;
8289 /* ImmExt should be processed after SSE2AVX. */
8290 else if (i
.tm
.opcode_modifier
.immext
)
8293 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8294 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8295 new destination operand here, while converting the source one to register
8297 if (i
.tm
.mnem_off
== MN_tilezero
)
8299 i
.op
[1].regs
= i
.op
[0].regs
;
8300 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8301 i
.types
[1] = i
.types
[0];
8302 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8303 i
.flags
[1] = i
.flags
[0];
8309 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8311 static const i386_operand_type regxmm
= {
8312 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8314 unsigned int dupl
= i
.operands
;
8315 unsigned int dest
= dupl
- 1;
8318 /* The destination must be an xmm register. */
8319 gas_assert (i
.reg_operands
8320 && MAX_OPERANDS
> dupl
8321 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8323 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8324 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8326 /* Keep xmm0 for instructions with VEX prefix and 3
8328 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8329 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8334 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8336 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8338 /* Add the implicit xmm0 for instructions with VEX prefix
8340 for (j
= i
.operands
; j
> 0; j
--)
8342 i
.op
[j
] = i
.op
[j
- 1];
8343 i
.types
[j
] = i
.types
[j
- 1];
8344 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8345 i
.flags
[j
] = i
.flags
[j
- 1];
8348 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8349 i
.types
[0] = regxmm
;
8350 i
.tm
.operand_types
[0] = regxmm
;
8353 i
.reg_operands
+= 2;
8358 i
.op
[dupl
] = i
.op
[dest
];
8359 i
.types
[dupl
] = i
.types
[dest
];
8360 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8361 i
.flags
[dupl
] = i
.flags
[dest
];
8370 i
.op
[dupl
] = i
.op
[dest
];
8371 i
.types
[dupl
] = i
.types
[dest
];
8372 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8373 i
.flags
[dupl
] = i
.flags
[dest
];
8376 if (i
.tm
.opcode_modifier
.immext
)
8379 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8380 && i
.tm
.opcode_modifier
.modrm
)
8384 for (j
= 1; j
< i
.operands
; j
++)
8386 i
.op
[j
- 1] = i
.op
[j
];
8387 i
.types
[j
- 1] = i
.types
[j
];
8389 /* We need to adjust fields in i.tm since they are used by
8390 build_modrm_byte. */
8391 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8393 i
.flags
[j
- 1] = i
.flags
[j
];
8396 /* No adjustment to i.reg_operands: This was already done at the top
8401 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8403 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8405 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8406 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8407 regnum
= register_number (i
.op
[1].regs
);
8408 first_reg_in_group
= regnum
& ~3;
8409 last_reg_in_group
= first_reg_in_group
+ 3;
8410 if (regnum
!= first_reg_in_group
)
8411 as_warn (_("source register `%s%s' implicitly denotes"
8412 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8413 register_prefix
, i
.op
[1].regs
->reg_name
,
8414 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8415 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8418 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8420 /* The imul $imm, %reg instruction is converted into
8421 imul $imm, %reg, %reg, and the clr %reg instruction
8422 is converted into xor %reg, %reg. */
8424 unsigned int first_reg_op
;
8426 if (operand_type_check (i
.types
[0], reg
))
8430 /* Pretend we saw the extra register operand. */
8431 gas_assert (i
.reg_operands
== 1
8432 && i
.op
[first_reg_op
+ 1].regs
== 0);
8433 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8434 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8439 if (i
.tm
.opcode_modifier
.modrm
)
8441 /* The opcode is completed (modulo i.tm.extension_opcode which
8442 must be put into the modrm byte). Now, we make the modrm and
8443 index base bytes based on all the info we've collected. */
8445 default_seg
= build_modrm_byte ();
8447 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8449 /* Warn about some common errors, but press on regardless. */
8450 if (i
.operands
== 2)
8452 /* Reversed arguments on faddp or fmulp. */
8453 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8454 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8455 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8457 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8459 /* Extraneous `l' suffix on fp insn. */
8460 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8461 register_prefix
, i
.op
[0].regs
->reg_name
);
8465 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8467 if (flag_code
!= CODE_64BIT
8468 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8469 && i
.op
[0].regs
->reg_num
== 1
8470 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8471 && i
.op
[0].regs
->reg_num
< 4)
8473 as_bad (_("you can't `%s %s%s'"),
8474 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8477 if (i
.op
[0].regs
->reg_num
> 3
8478 && i
.tm
.opcode_space
== SPACE_BASE
)
8480 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8481 i
.tm
.opcode_space
= SPACE_0F
;
8483 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8485 else if (i
.tm
.opcode_space
== SPACE_BASE
8486 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8488 default_seg
= reg_ds
;
8490 else if (i
.tm
.opcode_modifier
.isstring
)
8492 /* For the string instructions that allow a segment override
8493 on one of their operands, the default segment is ds. */
8494 default_seg
= reg_ds
;
8496 else if (i
.short_form
)
8498 /* The register operand is in the 1st or 2nd non-immediate operand. */
8499 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8502 && r
->reg_type
.bitfield
.instance
== Accum
8503 && i
.op
[i
.imm_operands
+ 1].regs
)
8504 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8505 /* Register goes in low 3 bits of opcode. */
8506 i
.tm
.base_opcode
|= r
->reg_num
;
8507 set_rex_vrex (r
, REX_B
, false);
8509 if (dot_insn () && i
.reg_operands
== 2)
8511 gas_assert (is_any_vex_encoding (&i
.tm
)
8512 || i
.vec_encoding
!= vex_encoding_default
);
8513 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8516 else if (i
.reg_operands
== 1
8517 && !i
.flags
[i
.operands
- 1]
8518 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8521 gas_assert (is_any_vex_encoding (&i
.tm
)
8522 || i
.vec_encoding
!= vex_encoding_default
);
8523 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8526 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8527 && i
.tm
.mnem_off
== MN_lea
)
8529 if (!quiet_warnings
)
8530 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8531 if (optimize
&& !i
.no_optimize
)
8534 i
.prefix
[SEG_PREFIX
] = 0;
8538 /* If a segment was explicitly specified, and the specified segment
8539 is neither the default nor the one already recorded from a prefix,
8540 use an opcode prefix to select it. If we never figured out what
8541 the default segment is, then default_seg will be zero at this
8542 point, and the specified segment prefix will always be used. */
8544 && i
.seg
[0] != default_seg
8545 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8547 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8553 static const reg_entry
*
8554 build_modrm_byte (void)
8556 const reg_entry
*default_seg
= NULL
;
8557 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8558 /* Compensate for kludge in md_assemble(). */
8559 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8560 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8561 unsigned int v
, op
, reg_slot
= ~0;
8563 /* Accumulator (in particular %st), shift count (%cl), and alike need
8564 to be skipped just like immediate operands do. */
8565 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8567 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8570 for (op
= source
; op
< i
.operands
; ++op
)
8571 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8574 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8578 /* There are 2 kinds of instructions:
8579 1. 5 operands: 4 register operands or 3 register operands
8580 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8581 VexW0 or VexW1. The destination must be either XMM, YMM or
8583 2. 4 operands: 4 register operands or 3 register operands
8584 plus 1 memory operand, with VexXDS.
8585 3. Other equivalent combinations when coming from s_insn(). */
8586 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8587 && i
.tm
.opcode_modifier
.vexw
);
8588 gas_assert (dot_insn ()
8589 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8591 /* Of the first two non-immediate operands the one with the template
8592 not allowing for a memory one is encoded in the immediate operand. */
8594 reg_slot
= source
+ 1;
8596 reg_slot
= source
++;
8600 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8601 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8604 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8606 if (i
.imm_operands
== 0)
8608 /* When there is no immediate operand, generate an 8bit
8609 immediate operand to encode the first operand. */
8610 exp
= &im_expressions
[i
.imm_operands
++];
8611 i
.op
[i
.operands
].imms
= exp
;
8612 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8615 exp
->X_op
= O_constant
;
8619 gas_assert (i
.imm_operands
== 1);
8620 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8621 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8623 /* Turn on Imm8 again so that output_imm will generate it. */
8624 i
.types
[0].bitfield
.imm8
= 1;
8628 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8629 << (3 + !(is_evex_encoding (&i
.tm
)
8630 || i
.vec_encoding
== vex_encoding_evex
));
8633 for (v
= source
+ 1; v
< dest
; ++v
)
8638 if (i
.tm
.extension_opcode
!= None
)
8644 gas_assert (source
< dest
);
8645 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8648 unsigned int tmp
= source
;
8654 if (v
< MAX_OPERANDS
)
8656 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8657 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8660 if (op
< i
.operands
)
8664 unsigned int fake_zero_displacement
= 0;
8666 gas_assert (i
.flags
[op
] & Operand_Mem
);
8668 if (i
.tm
.opcode_modifier
.sib
)
8670 /* The index register of VSIB shouldn't be RegIZ. */
8671 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8672 && i
.index_reg
->reg_num
== RegIZ
)
8675 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8678 i
.sib
.base
= NO_BASE_REGISTER
;
8679 i
.sib
.scale
= i
.log2_scale_factor
;
8680 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8681 i
.types
[op
].bitfield
.disp32
= 1;
8684 /* Since the mandatory SIB always has index register, so
8685 the code logic remains unchanged. The non-mandatory SIB
8686 without index register is allowed and will be handled
8690 if (i
.index_reg
->reg_num
== RegIZ
)
8691 i
.sib
.index
= NO_INDEX_REGISTER
;
8693 i
.sib
.index
= i
.index_reg
->reg_num
;
8694 set_rex_vrex (i
.index_reg
, REX_X
, false);
8698 default_seg
= reg_ds
;
8700 if (i
.base_reg
== 0)
8703 if (!i
.disp_operands
)
8704 fake_zero_displacement
= 1;
8705 if (i
.index_reg
== 0)
8707 /* Both check for VSIB and mandatory non-vector SIB. */
8708 gas_assert (!i
.tm
.opcode_modifier
.sib
8709 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8710 /* Operand is just <disp> */
8711 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8712 if (flag_code
== CODE_64BIT
)
8714 /* 64bit mode overwrites the 32bit absolute
8715 addressing by RIP relative addressing and
8716 absolute addressing is encoded by one of the
8717 redundant SIB forms. */
8718 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8719 i
.sib
.base
= NO_BASE_REGISTER
;
8720 i
.sib
.index
= NO_INDEX_REGISTER
;
8721 i
.types
[op
].bitfield
.disp32
= 1;
8723 else if ((flag_code
== CODE_16BIT
)
8724 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8726 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8727 i
.types
[op
].bitfield
.disp16
= 1;
8731 i
.rm
.regmem
= NO_BASE_REGISTER
;
8732 i
.types
[op
].bitfield
.disp32
= 1;
8735 else if (!i
.tm
.opcode_modifier
.sib
)
8737 /* !i.base_reg && i.index_reg */
8738 if (i
.index_reg
->reg_num
== RegIZ
)
8739 i
.sib
.index
= NO_INDEX_REGISTER
;
8741 i
.sib
.index
= i
.index_reg
->reg_num
;
8742 i
.sib
.base
= NO_BASE_REGISTER
;
8743 i
.sib
.scale
= i
.log2_scale_factor
;
8744 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8745 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8746 i
.types
[op
].bitfield
.disp32
= 1;
8747 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8751 /* RIP addressing for 64bit mode. */
8752 else if (i
.base_reg
->reg_num
== RegIP
)
8754 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8755 i
.rm
.regmem
= NO_BASE_REGISTER
;
8756 i
.types
[op
].bitfield
.disp8
= 0;
8757 i
.types
[op
].bitfield
.disp16
= 0;
8758 i
.types
[op
].bitfield
.disp32
= 1;
8759 i
.types
[op
].bitfield
.disp64
= 0;
8760 i
.flags
[op
] |= Operand_PCrel
;
8761 if (! i
.disp_operands
)
8762 fake_zero_displacement
= 1;
8764 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8766 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8767 switch (i
.base_reg
->reg_num
)
8770 if (i
.index_reg
== 0)
8772 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8773 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8776 default_seg
= reg_ss
;
8777 if (i
.index_reg
== 0)
8780 if (operand_type_check (i
.types
[op
], disp
) == 0)
8782 /* fake (%bp) into 0(%bp) */
8783 if (i
.disp_encoding
== disp_encoding_16bit
)
8784 i
.types
[op
].bitfield
.disp16
= 1;
8786 i
.types
[op
].bitfield
.disp8
= 1;
8787 fake_zero_displacement
= 1;
8790 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8791 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8793 default: /* (%si) -> 4 or (%di) -> 5 */
8794 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8796 if (!fake_zero_displacement
8800 fake_zero_displacement
= 1;
8801 if (i
.disp_encoding
== disp_encoding_8bit
)
8802 i
.types
[op
].bitfield
.disp8
= 1;
8804 i
.types
[op
].bitfield
.disp16
= 1;
8806 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8808 else /* i.base_reg and 32/64 bit mode */
8810 if (operand_type_check (i
.types
[op
], disp
))
8812 i
.types
[op
].bitfield
.disp16
= 0;
8813 i
.types
[op
].bitfield
.disp64
= 0;
8814 i
.types
[op
].bitfield
.disp32
= 1;
8817 if (!i
.tm
.opcode_modifier
.sib
)
8818 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8819 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8821 i
.sib
.base
= i
.base_reg
->reg_num
;
8822 /* x86-64 ignores REX prefix bit here to avoid decoder
8824 if (!(i
.base_reg
->reg_flags
& RegRex
)
8825 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8826 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8827 default_seg
= reg_ss
;
8828 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8830 fake_zero_displacement
= 1;
8831 if (i
.disp_encoding
== disp_encoding_32bit
)
8832 i
.types
[op
].bitfield
.disp32
= 1;
8834 i
.types
[op
].bitfield
.disp8
= 1;
8836 i
.sib
.scale
= i
.log2_scale_factor
;
8837 if (i
.index_reg
== 0)
8839 /* Only check for VSIB. */
8840 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8841 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8842 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8844 /* <disp>(%esp) becomes two byte modrm with no index
8845 register. We've already stored the code for esp
8846 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8847 Any base register besides %esp will not use the
8848 extra modrm byte. */
8849 i
.sib
.index
= NO_INDEX_REGISTER
;
8851 else if (!i
.tm
.opcode_modifier
.sib
)
8853 if (i
.index_reg
->reg_num
== RegIZ
)
8854 i
.sib
.index
= NO_INDEX_REGISTER
;
8856 i
.sib
.index
= i
.index_reg
->reg_num
;
8857 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8858 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8863 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8864 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8868 if (!fake_zero_displacement
8872 fake_zero_displacement
= 1;
8873 if (i
.disp_encoding
== disp_encoding_8bit
)
8874 i
.types
[op
].bitfield
.disp8
= 1;
8876 i
.types
[op
].bitfield
.disp32
= 1;
8878 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8882 if (fake_zero_displacement
)
8884 /* Fakes a zero displacement assuming that i.types[op]
8885 holds the correct displacement size. */
8888 gas_assert (i
.op
[op
].disps
== 0);
8889 exp
= &disp_expressions
[i
.disp_operands
++];
8890 i
.op
[op
].disps
= exp
;
8891 exp
->X_op
= O_constant
;
8892 exp
->X_add_number
= 0;
8893 exp
->X_add_symbol
= (symbolS
*) 0;
8894 exp
->X_op_symbol
= (symbolS
*) 0;
8900 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8901 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8912 if (!i
.tm
.opcode_modifier
.regmem
)
8914 gas_assert (source
< MAX_OPERANDS
);
8915 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8916 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8917 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8922 gas_assert (dest
< MAX_OPERANDS
);
8923 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8924 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8929 /* Fill in i.rm.reg field with extension opcode (if any) or the
8930 appropriate register. */
8931 if (i
.tm
.extension_opcode
!= None
)
8932 i
.rm
.reg
= i
.tm
.extension_opcode
;
8933 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
8935 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8936 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8940 gas_assert (source
< MAX_OPERANDS
);
8941 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8942 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8945 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8947 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
8949 add_prefix (LOCK_PREFIX_OPCODE
);
8956 frag_opcode_byte (unsigned char byte
)
8958 if (now_seg
!= absolute_section
)
8959 FRAG_APPEND_1_CHAR (byte
);
8961 ++abs_section_offset
;
8965 flip_code16 (unsigned int code16
)
8967 gas_assert (i
.tm
.operands
== 1);
8969 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8970 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8971 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8976 output_branch (void)
8982 relax_substateT subtype
;
8986 if (now_seg
== absolute_section
)
8988 as_bad (_("relaxable branches not supported in absolute section"));
8992 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8993 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8996 if (i
.prefix
[DATA_PREFIX
] != 0)
9000 code16
^= flip_code16(code16
);
9002 /* Pentium4 branch hints. */
9003 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9004 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9009 if (i
.prefix
[REX_PREFIX
] != 0)
9015 /* BND prefixed jump. */
9016 if (i
.prefix
[BND_PREFIX
] != 0)
9022 if (i
.prefixes
!= 0)
9023 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9025 /* It's always a symbol; End frag & setup for relax.
9026 Make sure there is enough room in this frag for the largest
9027 instruction we may generate in md_convert_frag. This is 2
9028 bytes for the opcode and room for the prefix and largest
9030 frag_grow (prefix
+ 2 + 4);
9031 /* Prefix and 1 opcode byte go in fr_fix. */
9032 p
= frag_more (prefix
+ 1);
9033 if (i
.prefix
[DATA_PREFIX
] != 0)
9034 *p
++ = DATA_PREFIX_OPCODE
;
9035 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9036 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9037 *p
++ = i
.prefix
[SEG_PREFIX
];
9038 if (i
.prefix
[BND_PREFIX
] != 0)
9039 *p
++ = BND_PREFIX_OPCODE
;
9040 if (i
.prefix
[REX_PREFIX
] != 0)
9041 *p
++ = i
.prefix
[REX_PREFIX
];
9042 *p
= i
.tm
.base_opcode
;
9044 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9045 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9046 else if (cpu_arch_flags
.bitfield
.cpui386
)
9047 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9049 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9052 sym
= i
.op
[0].disps
->X_add_symbol
;
9053 off
= i
.op
[0].disps
->X_add_number
;
9055 if (i
.op
[0].disps
->X_op
!= O_constant
9056 && i
.op
[0].disps
->X_op
!= O_symbol
)
9058 /* Handle complex expressions. */
9059 sym
= make_expr_symbol (i
.op
[0].disps
);
9063 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
9065 /* 1 possible extra opcode + 4 byte displacement go in var part.
9066 Pass reloc in fr_var. */
9067 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9070 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9071 /* Return TRUE iff PLT32 relocation should be used for branching to
9075 need_plt32_p (symbolS
*s
)
9077 /* PLT32 relocation is ELF only. */
9082 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9083 krtld support it. */
9087 /* Since there is no need to prepare for PLT branch on x86-64, we
9088 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9089 be used as a marker for 32-bit PC-relative branches. */
9096 /* Weak or undefined symbol need PLT32 relocation. */
9097 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9100 /* Non-global symbol doesn't need PLT32 relocation. */
9101 if (! S_IS_EXTERNAL (s
))
9104 /* Other global symbols need PLT32 relocation. NB: Symbol with
9105 non-default visibilities are treated as normal global symbol
9106 so that PLT32 relocation can be used as a marker for 32-bit
9107 PC-relative branches. It is useful for linker relaxation. */
9118 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9120 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9122 /* This is a loop or jecxz type instruction. */
9124 if (i
.prefix
[ADDR_PREFIX
] != 0)
9126 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9129 /* Pentium4 branch hints. */
9130 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9131 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9133 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9142 if (flag_code
== CODE_16BIT
)
9145 if (i
.prefix
[DATA_PREFIX
] != 0)
9147 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9149 code16
^= flip_code16(code16
);
9157 /* BND prefixed jump. */
9158 if (i
.prefix
[BND_PREFIX
] != 0)
9160 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9164 if (i
.prefix
[REX_PREFIX
] != 0)
9166 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9170 if (i
.prefixes
!= 0)
9171 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9173 if (now_seg
== absolute_section
)
9175 abs_section_offset
+= i
.opcode_length
+ size
;
9179 p
= frag_more (i
.opcode_length
+ size
);
9180 switch (i
.opcode_length
)
9183 *p
++ = i
.tm
.base_opcode
>> 8;
9186 *p
++ = i
.tm
.base_opcode
;
9192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9193 if (flag_code
== CODE_64BIT
&& size
== 4
9194 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9195 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9196 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9199 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9201 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9202 i
.op
[0].disps
, 1, jump_reloc
);
9204 /* All jumps handled here are signed, but don't unconditionally use a
9205 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9206 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9211 fixP
->fx_signed
= 1;
9215 if (i
.tm
.mnem_off
== MN_xbegin
)
9216 fixP
->fx_signed
= 1;
9220 if (flag_code
== CODE_64BIT
)
9221 fixP
->fx_signed
= 1;
9227 output_interseg_jump (void)
9235 if (flag_code
== CODE_16BIT
)
9239 if (i
.prefix
[DATA_PREFIX
] != 0)
9246 gas_assert (!i
.prefix
[REX_PREFIX
]);
9252 if (i
.prefixes
!= 0)
9253 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9255 if (now_seg
== absolute_section
)
9257 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9261 /* 1 opcode; 2 segment; offset */
9262 p
= frag_more (prefix
+ 1 + 2 + size
);
9264 if (i
.prefix
[DATA_PREFIX
] != 0)
9265 *p
++ = DATA_PREFIX_OPCODE
;
9267 if (i
.prefix
[REX_PREFIX
] != 0)
9268 *p
++ = i
.prefix
[REX_PREFIX
];
9270 *p
++ = i
.tm
.base_opcode
;
9271 if (i
.op
[1].imms
->X_op
== O_constant
)
9273 offsetT n
= i
.op
[1].imms
->X_add_number
;
9276 && !fits_in_unsigned_word (n
)
9277 && !fits_in_signed_word (n
))
9279 as_bad (_("16-bit jump out of range"));
9282 md_number_to_chars (p
, n
, size
);
9285 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9286 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9289 if (i
.op
[0].imms
->X_op
== O_constant
)
9290 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9292 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9293 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9296 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9301 asection
*seg
= now_seg
;
9302 subsegT subseg
= now_subseg
;
9304 unsigned int alignment
, align_size_1
;
9305 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9306 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9307 unsigned int padding
;
9309 if (!IS_ELF
|| !x86_used_note
)
9312 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9314 /* The .note.gnu.property section layout:
9316 Field Length Contents
9319 n_descsz 4 The note descriptor size
9320 n_type 4 NT_GNU_PROPERTY_TYPE_0
9322 n_desc n_descsz The program property array
9326 /* Create the .note.gnu.property section. */
9327 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9328 bfd_set_section_flags (sec
,
9335 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9346 bfd_set_section_alignment (sec
, alignment
);
9347 elf_section_type (sec
) = SHT_NOTE
;
9349 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9351 isa_1_descsz_raw
= 4 + 4 + 4;
9352 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9353 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9355 feature_2_descsz_raw
= isa_1_descsz
;
9356 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9358 feature_2_descsz_raw
+= 4 + 4 + 4;
9359 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9360 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9363 descsz
= feature_2_descsz
;
9364 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9365 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9367 /* Write n_namsz. */
9368 md_number_to_chars (p
, (valueT
) 4, 4);
9370 /* Write n_descsz. */
9371 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9374 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9377 memcpy (p
+ 4 * 3, "GNU", 4);
9379 /* Write 4-byte type. */
9380 md_number_to_chars (p
+ 4 * 4,
9381 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9383 /* Write 4-byte data size. */
9384 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9386 /* Write 4-byte data. */
9387 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9389 /* Zero out paddings. */
9390 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9392 memset (p
+ 4 * 7, 0, padding
);
9394 /* Write 4-byte type. */
9395 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9396 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9398 /* Write 4-byte data size. */
9399 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9401 /* Write 4-byte data. */
9402 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9403 (valueT
) x86_feature_2_used
, 4);
9405 /* Zero out paddings. */
9406 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9408 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9410 /* We probably can't restore the current segment, for there likely
9413 subseg_set (seg
, subseg
);
9417 x86_support_sframe_p (void)
9419 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9420 return (x86_elf_abi
== X86_64_ABI
);
9424 x86_sframe_ra_tracking_p (void)
9426 /* In AMD64, return address is always stored on the stack at a fixed offset
9427 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9428 Do not track explicitly via an SFrame Frame Row Entry. */
9433 x86_sframe_cfa_ra_offset (void)
9435 gas_assert (x86_elf_abi
== X86_64_ABI
);
9436 return (offsetT
) -8;
9440 x86_sframe_get_abi_arch (void)
9442 unsigned char sframe_abi_arch
= 0;
9444 if (x86_support_sframe_p ())
9446 gas_assert (!target_big_endian
);
9447 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9450 return sframe_abi_arch
;
9456 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9457 const char *frag_now_ptr
)
9459 unsigned int len
= 0;
9461 if (start_frag
!= frag_now
)
9463 const fragS
*fr
= start_frag
;
9468 } while (fr
&& fr
!= frag_now
);
9471 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9474 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9475 be macro-fused with conditional jumps.
9476 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9477 or is one of the following format:
9490 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9492 /* No RIP address. */
9493 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9496 /* No opcodes outside of base encoding space. */
9497 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9500 /* add, sub without add/sub m, imm. */
9501 if (i
.tm
.base_opcode
<= 5
9502 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9503 || ((i
.tm
.base_opcode
| 3) == 0x83
9504 && (i
.tm
.extension_opcode
== 0x5
9505 || i
.tm
.extension_opcode
== 0x0)))
9507 *mf_cmp_p
= mf_cmp_alu_cmp
;
9508 return !(i
.mem_operands
&& i
.imm_operands
);
9511 /* and without and m, imm. */
9512 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9513 || ((i
.tm
.base_opcode
| 3) == 0x83
9514 && i
.tm
.extension_opcode
== 0x4))
9516 *mf_cmp_p
= mf_cmp_test_and
;
9517 return !(i
.mem_operands
&& i
.imm_operands
);
9520 /* test without test m imm. */
9521 if ((i
.tm
.base_opcode
| 1) == 0x85
9522 || (i
.tm
.base_opcode
| 1) == 0xa9
9523 || ((i
.tm
.base_opcode
| 1) == 0xf7
9524 && i
.tm
.extension_opcode
== 0))
9526 *mf_cmp_p
= mf_cmp_test_and
;
9527 return !(i
.mem_operands
&& i
.imm_operands
);
9530 /* cmp without cmp m, imm. */
9531 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9532 || ((i
.tm
.base_opcode
| 3) == 0x83
9533 && (i
.tm
.extension_opcode
== 0x7)))
9535 *mf_cmp_p
= mf_cmp_alu_cmp
;
9536 return !(i
.mem_operands
&& i
.imm_operands
);
9539 /* inc, dec without inc/dec m. */
9540 if ((is_cpu (&i
.tm
, CpuNo64
)
9541 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9542 || ((i
.tm
.base_opcode
| 1) == 0xff
9543 && i
.tm
.extension_opcode
<= 0x1))
9545 *mf_cmp_p
= mf_cmp_incdec
;
9546 return !i
.mem_operands
;
9552 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9555 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9557 /* NB: Don't work with COND_JUMP86 without i386. */
9558 if (!align_branch_power
9559 || now_seg
== absolute_section
9560 || !cpu_arch_flags
.bitfield
.cpui386
9561 || !(align_branch
& align_branch_fused_bit
))
9564 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9566 if (last_insn
.kind
== last_insn_other
9567 || last_insn
.seg
!= now_seg
)
9570 as_warn_where (last_insn
.file
, last_insn
.line
,
9571 _("`%s` skips -malign-branch-boundary on `%s`"),
9572 last_insn
.name
, insn_name (&i
.tm
));
9578 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9581 add_branch_prefix_frag_p (void)
9583 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9584 to PadLock instructions since they include prefixes in opcode. */
9585 if (!align_branch_power
9586 || !align_branch_prefix_size
9587 || now_seg
== absolute_section
9588 || is_cpu (&i
.tm
, CpuPadLock
)
9589 || !cpu_arch_flags
.bitfield
.cpui386
)
9592 /* Don't add prefix if it is a prefix or there is no operand in case
9593 that segment prefix is special. */
9594 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9597 if (last_insn
.kind
== last_insn_other
9598 || last_insn
.seg
!= now_seg
)
9602 as_warn_where (last_insn
.file
, last_insn
.line
,
9603 _("`%s` skips -malign-branch-boundary on `%s`"),
9604 last_insn
.name
, insn_name (&i
.tm
));
9609 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9612 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9613 enum mf_jcc_kind
*mf_jcc_p
)
9617 /* NB: Don't work with COND_JUMP86 without i386. */
9618 if (!align_branch_power
9619 || now_seg
== absolute_section
9620 || !cpu_arch_flags
.bitfield
.cpui386
9621 || i
.tm
.opcode_space
!= SPACE_BASE
)
9626 /* Check for jcc and direct jmp. */
9627 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9629 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9631 *branch_p
= align_branch_jmp
;
9632 add_padding
= align_branch
& align_branch_jmp_bit
;
9636 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9637 igore the lowest bit. */
9638 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9639 *branch_p
= align_branch_jcc
;
9640 if ((align_branch
& align_branch_jcc_bit
))
9644 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9647 *branch_p
= align_branch_ret
;
9648 if ((align_branch
& align_branch_ret_bit
))
9653 /* Check for indirect jmp, direct and indirect calls. */
9654 if (i
.tm
.base_opcode
== 0xe8)
9657 *branch_p
= align_branch_call
;
9658 if ((align_branch
& align_branch_call_bit
))
9661 else if (i
.tm
.base_opcode
== 0xff
9662 && (i
.tm
.extension_opcode
== 2
9663 || i
.tm
.extension_opcode
== 4))
9665 /* Indirect call and jmp. */
9666 *branch_p
= align_branch_indirect
;
9667 if ((align_branch
& align_branch_indirect_bit
))
9674 && (i
.op
[0].disps
->X_op
== O_symbol
9675 || (i
.op
[0].disps
->X_op
== O_subtract
9676 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9678 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9679 /* No padding to call to global or undefined tls_get_addr. */
9680 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9681 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9687 && last_insn
.kind
!= last_insn_other
9688 && last_insn
.seg
== now_seg
)
9691 as_warn_where (last_insn
.file
, last_insn
.line
,
9692 _("`%s` skips -malign-branch-boundary on `%s`"),
9693 last_insn
.name
, insn_name (&i
.tm
));
9703 fragS
*insn_start_frag
;
9704 offsetT insn_start_off
;
9705 fragS
*fragP
= NULL
;
9706 enum align_branch_kind branch
= align_branch_none
;
9707 /* The initializer is arbitrary just to avoid uninitialized error.
9708 it's actually either assigned in add_branch_padding_frag_p
9709 or never be used. */
9710 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9713 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9715 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9716 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9717 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9719 if (is_cpu (&i
.tm
, Cpu8087
)
9720 || is_cpu (&i
.tm
, Cpu287
)
9721 || is_cpu (&i
.tm
, Cpu387
)
9722 || is_cpu (&i
.tm
, Cpu687
)
9723 || is_cpu (&i
.tm
, CpuFISTTP
))
9724 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9726 if ((i
.xstate
& xstate_mmx
)
9727 || i
.tm
.mnem_off
== MN_emms
9728 || i
.tm
.mnem_off
== MN_femms
)
9729 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9733 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9734 i
.xstate
|= xstate_zmm
;
9735 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9736 i
.xstate
|= xstate_ymm
;
9737 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9738 i
.xstate
|= xstate_xmm
;
9741 /* vzeroall / vzeroupper */
9742 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9743 i
.xstate
|= xstate_ymm
;
9745 if ((i
.xstate
& xstate_xmm
)
9746 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9747 || (i
.tm
.base_opcode
== 0xae
9748 && (is_cpu (&i
.tm
, CpuSSE
)
9749 || is_cpu (&i
.tm
, CpuAVX
)))
9750 || is_cpu (&i
.tm
, CpuWideKL
)
9751 || is_cpu (&i
.tm
, CpuKL
))
9752 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9754 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9755 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9756 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9757 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9758 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9759 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9760 if (is_cpu (&i
.tm
, CpuFXSR
))
9761 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9762 if (is_cpu (&i
.tm
, CpuXsave
))
9763 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9764 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9765 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9766 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9767 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9769 if (x86_feature_2_used
9770 || is_cpu (&i
.tm
, CpuCMOV
)
9771 || is_cpu (&i
.tm
, CpuSYSCALL
)
9772 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9773 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9774 if (is_cpu (&i
.tm
, CpuSSE3
)
9775 || is_cpu (&i
.tm
, CpuSSSE3
)
9776 || is_cpu (&i
.tm
, CpuSSE4_1
)
9777 || is_cpu (&i
.tm
, CpuSSE4_2
)
9778 || is_cpu (&i
.tm
, CpuCX16
)
9779 || is_cpu (&i
.tm
, CpuPOPCNT
)
9780 /* LAHF-SAHF insns in 64-bit mode. */
9781 || (flag_code
== CODE_64BIT
9782 && (i
.tm
.base_opcode
| 1) == 0x9f
9783 && i
.tm
.opcode_space
== SPACE_BASE
))
9784 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9785 if (is_cpu (&i
.tm
, CpuAVX
)
9786 || is_cpu (&i
.tm
, CpuAVX2
)
9787 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9788 XOP, FMA4, LPW, TBM, and AMX. */
9789 || (i
.tm
.opcode_modifier
.vex
9790 && !is_cpu (&i
.tm
, CpuAVX512F
)
9791 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9792 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9793 && !is_cpu (&i
.tm
, CpuXOP
)
9794 && !is_cpu (&i
.tm
, CpuFMA4
)
9795 && !is_cpu (&i
.tm
, CpuLWP
)
9796 && !is_cpu (&i
.tm
, CpuTBM
)
9797 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9798 || is_cpu (&i
.tm
, CpuF16C
)
9799 || is_cpu (&i
.tm
, CpuFMA
)
9800 || is_cpu (&i
.tm
, CpuLZCNT
)
9801 || is_cpu (&i
.tm
, CpuMovbe
)
9802 || is_cpu (&i
.tm
, CpuXSAVES
)
9803 || (x86_feature_2_used
9804 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9805 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9806 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9807 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9808 if (is_cpu (&i
.tm
, CpuAVX512F
)
9809 || is_cpu (&i
.tm
, CpuAVX512BW
)
9810 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9811 || is_cpu (&i
.tm
, CpuAVX512VL
)
9812 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9813 AVX512-4FMAPS, and AVX512-4VNNIW. */
9814 || (i
.tm
.opcode_modifier
.evex
9815 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9816 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9817 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9818 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9819 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9823 /* Tie dwarf2 debug info to the address at the start of the insn.
9824 We can't do this after the insn has been output as the current
9825 frag may have been closed off. eg. by frag_var. */
9826 dwarf2_emit_insn (0);
9828 insn_start_frag
= frag_now
;
9829 insn_start_off
= frag_now_fix ();
9831 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9834 /* Branch can be 8 bytes. Leave some room for prefixes. */
9835 unsigned int max_branch_padding_size
= 14;
9837 /* Align section to boundary. */
9838 record_alignment (now_seg
, align_branch_power
);
9840 /* Make room for padding. */
9841 frag_grow (max_branch_padding_size
);
9843 /* Start of the padding. */
9848 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9849 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9852 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9853 fragP
->tc_frag_data
.branch_type
= branch
;
9854 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9857 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9858 && !pre_386_16bit_warned
)
9860 as_warn (_("use .code16 to ensure correct addressing mode"));
9861 pre_386_16bit_warned
= true;
9865 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9867 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9868 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9870 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9871 output_interseg_jump ();
9874 /* Output normal instructions here. */
9878 enum mf_cmp_kind mf_cmp
;
9881 && (i
.tm
.base_opcode
== 0xaee8
9882 || i
.tm
.base_opcode
== 0xaef0
9883 || i
.tm
.base_opcode
== 0xaef8))
9885 /* Encode lfence, mfence, and sfence as
9886 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9887 if (flag_code
== CODE_16BIT
)
9888 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9889 else if (omit_lock_prefix
)
9890 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9892 else if (now_seg
!= absolute_section
)
9894 offsetT val
= 0x240483f0ULL
;
9897 md_number_to_chars (p
, val
, 5);
9900 abs_section_offset
+= 5;
9904 /* Some processors fail on LOCK prefix. This options makes
9905 assembler ignore LOCK prefix and serves as a workaround. */
9906 if (omit_lock_prefix
)
9908 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9909 && i
.tm
.opcode_modifier
.isprefix
)
9911 i
.prefix
[LOCK_PREFIX
] = 0;
9915 /* Skip if this is a branch. */
9917 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9919 /* Make room for padding. */
9920 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9925 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9926 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9929 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9930 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9931 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9933 else if (add_branch_prefix_frag_p ())
9935 unsigned int max_prefix_size
= align_branch_prefix_size
;
9937 /* Make room for padding. */
9938 frag_grow (max_prefix_size
);
9943 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9944 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9947 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9950 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9951 don't need the explicit prefix. */
9952 if (!is_any_vex_encoding (&i
.tm
))
9954 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9963 if (!is_cpu (&i
.tm
, CpuPadLock
)
9964 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9968 switch (i
.opcode_length
)
9973 /* Check for pseudo prefixes. */
9974 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9976 as_bad_where (insn_start_frag
->fr_file
,
9977 insn_start_frag
->fr_line
,
9978 _("pseudo prefix without instruction"));
9988 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9989 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9990 R_X86_64_GOTTPOFF relocation so that linker can safely
9991 perform IE->LE optimization. A dummy REX_OPCODE prefix
9992 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9993 relocation for GDesc -> IE/LE optimization. */
9994 if (x86_elf_abi
== X86_64_X32_ABI
9996 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9997 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9998 && i
.prefix
[REX_PREFIX
] == 0)
9999 add_prefix (REX_OPCODE
);
10002 /* The prefix bytes. */
10003 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10005 frag_opcode_byte (*q
);
10009 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10015 frag_opcode_byte (*q
);
10018 /* There should be no other prefixes for instructions
10019 with VEX prefix. */
10023 /* For EVEX instructions i.vrex should become 0 after
10024 build_evex_prefix. For VEX instructions upper 16 registers
10025 aren't available, so VREX should be 0. */
10028 /* Now the VEX prefix. */
10029 if (now_seg
!= absolute_section
)
10031 p
= frag_more (i
.vex
.length
);
10032 for (j
= 0; j
< i
.vex
.length
; j
++)
10033 p
[j
] = i
.vex
.bytes
[j
];
10036 abs_section_offset
+= i
.vex
.length
;
10039 /* Now the opcode; be careful about word order here! */
10040 j
= i
.opcode_length
;
10042 switch (i
.tm
.opcode_space
)
10057 if (now_seg
== absolute_section
)
10058 abs_section_offset
+= j
;
10061 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10067 && i
.tm
.opcode_space
!= SPACE_BASE
)
10070 if (i
.tm
.opcode_space
!= SPACE_0F
)
10071 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10075 switch (i
.opcode_length
)
10078 /* Put out high byte first: can't use md_number_to_chars! */
10079 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10080 /* Fall through. */
10082 *p
= i
.tm
.base_opcode
& 0xff;
10091 /* Now the modrm byte and sib byte (if present). */
10092 if (i
.tm
.opcode_modifier
.modrm
)
10094 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10096 | (i
.rm
.mode
<< 6));
10097 /* If i.rm.regmem == ESP (4)
10098 && i.rm.mode != (Register mode)
10100 ==> need second modrm byte. */
10101 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10103 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10104 frag_opcode_byte ((i
.sib
.base
<< 0)
10105 | (i
.sib
.index
<< 3)
10106 | (i
.sib
.scale
<< 6));
10109 if (i
.disp_operands
)
10110 output_disp (insn_start_frag
, insn_start_off
);
10112 if (i
.imm_operands
)
10113 output_imm (insn_start_frag
, insn_start_off
);
10116 * frag_now_fix () returning plain abs_section_offset when we're in the
10117 * absolute section, and abs_section_offset not getting updated as data
10118 * gets added to the frag breaks the logic below.
10120 if (now_seg
!= absolute_section
)
10122 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10124 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10128 /* NB: Don't add prefix with GOTPC relocation since
10129 output_disp() above depends on the fixed encoding
10130 length. Can't add prefix with TLS relocation since
10131 it breaks TLS linker optimization. */
10132 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10133 /* Prefix count on the current instruction. */
10134 unsigned int count
= i
.vex
.length
;
10136 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10137 /* REX byte is encoded in VEX/EVEX prefix. */
10138 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10141 /* Count prefixes for extended opcode maps. */
10143 switch (i
.tm
.opcode_space
)
10158 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10161 /* Set the maximum prefix size in BRANCH_PREFIX
10163 if (fragP
->tc_frag_data
.max_bytes
> max
)
10164 fragP
->tc_frag_data
.max_bytes
= max
;
10165 if (fragP
->tc_frag_data
.max_bytes
> count
)
10166 fragP
->tc_frag_data
.max_bytes
-= count
;
10168 fragP
->tc_frag_data
.max_bytes
= 0;
10172 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10174 unsigned int max_prefix_size
;
10175 if (align_branch_prefix_size
> max
)
10176 max_prefix_size
= max
;
10178 max_prefix_size
= align_branch_prefix_size
;
10179 if (max_prefix_size
> count
)
10180 fragP
->tc_frag_data
.max_prefix_length
10181 = max_prefix_size
- count
;
10184 /* Use existing segment prefix if possible. Use CS
10185 segment prefix in 64-bit mode. In 32-bit mode, use SS
10186 segment prefix with ESP/EBP base register and use DS
10187 segment prefix without ESP/EBP base register. */
10188 if (i
.prefix
[SEG_PREFIX
])
10189 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10190 else if (flag_code
== CODE_64BIT
)
10191 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10192 else if (i
.base_reg
10193 && (i
.base_reg
->reg_num
== 4
10194 || i
.base_reg
->reg_num
== 5))
10195 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10197 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10202 /* NB: Don't work with COND_JUMP86 without i386. */
10203 if (align_branch_power
10204 && now_seg
!= absolute_section
10205 && cpu_arch_flags
.bitfield
.cpui386
)
10207 /* Terminate each frag so that we can add prefix and check for
10209 frag_wane (frag_now
);
10216 pi ("" /*line*/, &i
);
10218 #endif /* DEBUG386 */
10221 /* Return the size of the displacement operand N. */
10224 disp_size (unsigned int n
)
10228 if (i
.types
[n
].bitfield
.disp64
)
10230 else if (i
.types
[n
].bitfield
.disp8
)
10232 else if (i
.types
[n
].bitfield
.disp16
)
10237 /* Return the size of the immediate operand N. */
10240 imm_size (unsigned int n
)
10243 if (i
.types
[n
].bitfield
.imm64
)
10245 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10247 else if (i
.types
[n
].bitfield
.imm16
)
10253 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10258 for (n
= 0; n
< i
.operands
; n
++)
10260 if (operand_type_check (i
.types
[n
], disp
))
10262 int size
= disp_size (n
);
10264 if (now_seg
== absolute_section
)
10265 abs_section_offset
+= size
;
10266 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10268 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10270 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10272 p
= frag_more (size
);
10273 md_number_to_chars (p
, val
, size
);
10277 enum bfd_reloc_code_real reloc_type
;
10278 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10279 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10280 && (!want_disp32 (&i
.tm
)
10281 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10282 && !i
.types
[n
].bitfield
.baseindex
)))
10286 /* We can't have 8 bit displacement here. */
10287 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10289 /* The PC relative address is computed relative
10290 to the instruction boundary, so in case immediate
10291 fields follows, we need to adjust the value. */
10292 if (pcrel
&& i
.imm_operands
)
10297 for (n1
= 0; n1
< i
.operands
; n1
++)
10298 if (operand_type_check (i
.types
[n1
], imm
))
10300 /* Only one immediate is allowed for PC
10301 relative address, except with .insn. */
10302 gas_assert (sz
== 0 || dot_insn ());
10303 sz
+= imm_size (n1
);
10305 /* We should find at least one immediate. */
10306 gas_assert (sz
!= 0);
10307 i
.op
[n
].disps
->X_add_number
-= sz
;
10310 p
= frag_more (size
);
10311 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10313 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10314 && (((reloc_type
== BFD_RELOC_32
10315 || reloc_type
== BFD_RELOC_X86_64_32S
10316 || (reloc_type
== BFD_RELOC_64
10318 && (i
.op
[n
].disps
->X_op
== O_symbol
10319 || (i
.op
[n
].disps
->X_op
== O_add
10320 && ((symbol_get_value_expression
10321 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10323 || reloc_type
== BFD_RELOC_32_PCREL
))
10327 reloc_type
= BFD_RELOC_386_GOTPC
;
10328 i
.has_gotpc_tls_reloc
= true;
10329 i
.op
[n
].disps
->X_add_number
+=
10330 encoding_length (insn_start_frag
, insn_start_off
, p
);
10332 else if (reloc_type
== BFD_RELOC_64
)
10333 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10335 /* Don't do the adjustment for x86-64, as there
10336 the pcrel addressing is relative to the _next_
10337 insn, and that is taken care of in other code. */
10338 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10340 else if (align_branch_power
)
10342 switch (reloc_type
)
10344 case BFD_RELOC_386_TLS_GD
:
10345 case BFD_RELOC_386_TLS_LDM
:
10346 case BFD_RELOC_386_TLS_IE
:
10347 case BFD_RELOC_386_TLS_IE_32
:
10348 case BFD_RELOC_386_TLS_GOTIE
:
10349 case BFD_RELOC_386_TLS_GOTDESC
:
10350 case BFD_RELOC_386_TLS_DESC_CALL
:
10351 case BFD_RELOC_X86_64_TLSGD
:
10352 case BFD_RELOC_X86_64_TLSLD
:
10353 case BFD_RELOC_X86_64_GOTTPOFF
:
10354 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10355 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10356 i
.has_gotpc_tls_reloc
= true;
10361 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10362 size
, i
.op
[n
].disps
, pcrel
,
10365 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10366 && !i
.prefix
[ADDR_PREFIX
])
10367 fixP
->fx_signed
= 1;
10369 /* Check for "call/jmp *mem", "mov mem, %reg",
10370 "test %reg, mem" and "binop mem, %reg" where binop
10371 is one of adc, add, and, cmp, or, sbb, sub, xor
10372 instructions without data prefix. Always generate
10373 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10374 if (i
.prefix
[DATA_PREFIX
] == 0
10375 && (generate_relax_relocations
10378 && i
.rm
.regmem
== 5))
10380 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10381 && i
.tm
.opcode_space
== SPACE_BASE
10382 && ((i
.operands
== 1
10383 && i
.tm
.base_opcode
== 0xff
10384 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10385 || (i
.operands
== 2
10386 && (i
.tm
.base_opcode
== 0x8b
10387 || i
.tm
.base_opcode
== 0x85
10388 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10392 fixP
->fx_tcbit
= i
.rex
!= 0;
10394 && (i
.base_reg
->reg_num
== RegIP
))
10395 fixP
->fx_tcbit2
= 1;
10398 fixP
->fx_tcbit2
= 1;
10406 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10411 for (n
= 0; n
< i
.operands
; n
++)
10413 if (operand_type_check (i
.types
[n
], imm
))
10415 int size
= imm_size (n
);
10417 if (now_seg
== absolute_section
)
10418 abs_section_offset
+= size
;
10419 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10423 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10425 p
= frag_more (size
);
10426 md_number_to_chars (p
, val
, size
);
10430 /* Not absolute_section.
10431 Need a 32-bit fixup (don't support 8bit
10432 non-absolute imms). Try to support other
10434 enum bfd_reloc_code_real reloc_type
;
10437 if (i
.types
[n
].bitfield
.imm32s
10438 && (i
.suffix
== QWORD_MNEM_SUFFIX
10439 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10445 p
= frag_more (size
);
10446 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10448 /* This is tough to explain. We end up with this one if we
10449 * have operands that look like
10450 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10451 * obtain the absolute address of the GOT, and it is strongly
10452 * preferable from a performance point of view to avoid using
10453 * a runtime relocation for this. The actual sequence of
10454 * instructions often look something like:
10459 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10461 * The call and pop essentially return the absolute address
10462 * of the label .L66 and store it in %ebx. The linker itself
10463 * will ultimately change the first operand of the addl so
10464 * that %ebx points to the GOT, but to keep things simple, the
10465 * .o file must have this operand set so that it generates not
10466 * the absolute address of .L66, but the absolute address of
10467 * itself. This allows the linker itself simply treat a GOTPC
10468 * relocation as asking for a pcrel offset to the GOT to be
10469 * added in, and the addend of the relocation is stored in the
10470 * operand field for the instruction itself.
10472 * Our job here is to fix the operand so that it would add
10473 * the correct offset so that %ebx would point to itself. The
10474 * thing that is tricky is that .-.L66 will point to the
10475 * beginning of the instruction, so we need to further modify
10476 * the operand so that it will point to itself. There are
10477 * other cases where you have something like:
10479 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10481 * and here no correction would be required. Internally in
10482 * the assembler we treat operands of this form as not being
10483 * pcrel since the '.' is explicitly mentioned, and I wonder
10484 * whether it would simplify matters to do it this way. Who
10485 * knows. In earlier versions of the PIC patches, the
10486 * pcrel_adjust field was used to store the correction, but
10487 * since the expression is not pcrel, I felt it would be
10488 * confusing to do it this way. */
10490 if ((reloc_type
== BFD_RELOC_32
10491 || reloc_type
== BFD_RELOC_X86_64_32S
10492 || reloc_type
== BFD_RELOC_64
)
10494 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10495 && (i
.op
[n
].imms
->X_op
== O_symbol
10496 || (i
.op
[n
].imms
->X_op
== O_add
10497 && ((symbol_get_value_expression
10498 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10502 reloc_type
= BFD_RELOC_386_GOTPC
;
10503 else if (size
== 4)
10504 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10505 else if (size
== 8)
10506 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10507 i
.has_gotpc_tls_reloc
= true;
10508 i
.op
[n
].imms
->X_add_number
+=
10509 encoding_length (insn_start_frag
, insn_start_off
, p
);
10511 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10512 i
.op
[n
].imms
, 0, reloc_type
);
10518 /* x86_cons_fix_new is called via the expression parsing code when a
10519 reloc is needed. We use this hook to get the correct .got reloc. */
10520 static int cons_sign
= -1;
10523 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10524 expressionS
*exp
, bfd_reloc_code_real_type r
)
10526 r
= reloc (len
, 0, cons_sign
, r
);
10529 if (exp
->X_op
== O_secrel
)
10531 exp
->X_op
= O_symbol
;
10532 r
= BFD_RELOC_32_SECREL
;
10534 else if (exp
->X_op
== O_secidx
)
10535 r
= BFD_RELOC_16_SECIDX
;
10538 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10541 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10542 purpose of the `.dc.a' internal pseudo-op. */
10545 x86_address_bytes (void)
10547 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10549 return stdoutput
->arch_info
->bits_per_address
/ 8;
10552 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10553 || defined (LEX_AT)) && !defined (TE_PE)
10554 # define lex_got(reloc, adjust, types) NULL
10556 /* Parse operands of the form
10557 <symbol>@GOTOFF+<nnn>
10558 and similar .plt or .got references.
10560 If we find one, set up the correct relocation in RELOC and copy the
10561 input string, minus the `@GOTOFF' into a malloc'd buffer for
10562 parsing by the calling routine. Return this buffer, and if ADJUST
10563 is non-null set it to the length of the string we removed from the
10564 input line. Otherwise return NULL. */
10566 lex_got (enum bfd_reloc_code_real
*rel
,
10568 i386_operand_type
*types
)
10570 /* Some of the relocations depend on the size of what field is to
10571 be relocated. But in our callers i386_immediate and i386_displacement
10572 we don't yet know the operand size (this will be set by insn
10573 matching). Hence we record the word32 relocation here,
10574 and adjust the reloc according to the real size in reloc(). */
10575 static const struct
10579 const enum bfd_reloc_code_real rel
[2];
10580 const i386_operand_type types64
;
10581 bool need_GOT_symbol
;
10586 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10587 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10588 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10589 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10590 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10591 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10592 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10593 { .imm64 = 1, .disp64 = 1 } }
10596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10597 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10598 BFD_RELOC_SIZE32
},
10599 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10601 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10602 BFD_RELOC_X86_64_PLTOFF64
},
10603 { .bitfield
= { .imm64
= 1 } }, true },
10604 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10605 BFD_RELOC_X86_64_PLT32
},
10606 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10607 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10608 BFD_RELOC_X86_64_GOTPLT64
},
10609 OPERAND_TYPE_IMM64_DISP64
, true },
10610 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10611 BFD_RELOC_X86_64_GOTOFF64
},
10612 OPERAND_TYPE_IMM64_DISP64
, true },
10613 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10614 BFD_RELOC_X86_64_GOTPCREL
},
10615 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10616 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10617 BFD_RELOC_X86_64_TLSGD
},
10618 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10619 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10620 _dummy_first_bfd_reloc_code_real
},
10621 OPERAND_TYPE_NONE
, true },
10622 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10623 BFD_RELOC_X86_64_TLSLD
},
10624 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10625 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10626 BFD_RELOC_X86_64_GOTTPOFF
},
10627 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10628 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10629 BFD_RELOC_X86_64_TPOFF32
},
10630 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10631 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10632 _dummy_first_bfd_reloc_code_real
},
10633 OPERAND_TYPE_NONE
, true },
10634 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10635 BFD_RELOC_X86_64_DTPOFF32
},
10636 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10637 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10638 _dummy_first_bfd_reloc_code_real
},
10639 OPERAND_TYPE_NONE
, true },
10640 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10641 _dummy_first_bfd_reloc_code_real
},
10642 OPERAND_TYPE_NONE
, true },
10643 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10644 BFD_RELOC_X86_64_GOT32
},
10645 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10646 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10647 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10648 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10649 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10650 BFD_RELOC_X86_64_TLSDESC_CALL
},
10651 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10653 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10654 BFD_RELOC_32_SECREL
},
10655 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10658 #undef OPERAND_TYPE_IMM32_32S_DISP32
10659 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10660 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10661 #undef OPERAND_TYPE_IMM64_DISP64
10667 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10672 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10673 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10676 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10678 int len
= gotrel
[j
].len
;
10679 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10681 if (gotrel
[j
].rel
[object_64bit
] != 0)
10684 char *tmpbuf
, *past_reloc
;
10686 *rel
= gotrel
[j
].rel
[object_64bit
];
10690 if (flag_code
!= CODE_64BIT
)
10692 types
->bitfield
.imm32
= 1;
10693 types
->bitfield
.disp32
= 1;
10696 *types
= gotrel
[j
].types64
;
10699 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10700 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10702 /* The length of the first part of our input line. */
10703 first
= cp
- input_line_pointer
;
10705 /* The second part goes from after the reloc token until
10706 (and including) an end_of_line char or comma. */
10707 past_reloc
= cp
+ 1 + len
;
10709 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10711 second
= cp
+ 1 - past_reloc
;
10713 /* Allocate and copy string. The trailing NUL shouldn't
10714 be necessary, but be safe. */
10715 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10716 memcpy (tmpbuf
, input_line_pointer
, first
);
10717 if (second
!= 0 && *past_reloc
!= ' ')
10718 /* Replace the relocation token with ' ', so that
10719 errors like foo@GOTOFF1 will be detected. */
10720 tmpbuf
[first
++] = ' ';
10722 /* Increment length by 1 if the relocation token is
10727 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10728 tmpbuf
[first
+ second
] = '\0';
10732 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10733 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10738 /* Might be a symbol version string. Don't as_bad here. */
10743 bfd_reloc_code_real_type
10744 x86_cons (expressionS
*exp
, int size
)
10746 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10748 intel_syntax
= -intel_syntax
;
10750 expr_mode
= expr_operator_none
;
10752 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10753 && !defined (LEX_AT)) \
10755 if (size
== 4 || (object_64bit
&& size
== 8))
10757 /* Handle @GOTOFF and the like in an expression. */
10759 char *gotfree_input_line
;
10762 save
= input_line_pointer
;
10763 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10764 if (gotfree_input_line
)
10765 input_line_pointer
= gotfree_input_line
;
10769 if (gotfree_input_line
)
10771 /* expression () has merrily parsed up to the end of line,
10772 or a comma - in the wrong buffer. Transfer how far
10773 input_line_pointer has moved to the right buffer. */
10774 input_line_pointer
= (save
10775 + (input_line_pointer
- gotfree_input_line
)
10777 free (gotfree_input_line
);
10778 if (exp
->X_op
== O_constant
10779 || exp
->X_op
== O_absent
10780 || exp
->X_op
== O_illegal
10781 || exp
->X_op
== O_register
10782 || exp
->X_op
== O_big
)
10784 char c
= *input_line_pointer
;
10785 *input_line_pointer
= 0;
10786 as_bad (_("missing or invalid expression `%s'"), save
);
10787 *input_line_pointer
= c
;
10789 else if ((got_reloc
== BFD_RELOC_386_PLT32
10790 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10791 && exp
->X_op
!= O_symbol
)
10793 char c
= *input_line_pointer
;
10794 *input_line_pointer
= 0;
10795 as_bad (_("invalid PLT expression `%s'"), save
);
10796 *input_line_pointer
= c
;
10804 intel_syntax
= -intel_syntax
;
10807 i386_intel_simplify (exp
);
10809 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10810 if (size
<= 4 && expr_mode
== expr_operator_present
10811 && exp
->X_op
== O_constant
&& !object_64bit
)
10812 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10818 signed_cons (int size
)
10827 s_insn (int dummy ATTRIBUTE_UNUSED
)
10829 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10830 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10834 bool vex
= false, xop
= false, evex
= false;
10835 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10839 saved_char
= *saved_ilp
;
10842 end
= parse_insn (line
, mnemonic
, true);
10846 *saved_ilp
= saved_char
;
10847 ignore_rest_of_line ();
10851 line
+= end
- line
;
10853 current_templates
= &tt
;
10854 i
.tm
.mnem_off
= MN__insn
;
10855 i
.tm
.extension_opcode
= None
;
10857 if (startswith (line
, "VEX")
10858 && (line
[3] == '.' || is_space_char (line
[3])))
10863 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10866 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10868 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10869 && (*e
== '.' || is_space_char (*e
)))
10872 /* Arrange for build_vex_prefix() to emit 0x8f. */
10873 i
.tm
.opcode_space
= SPACE_XOP08
;
10874 i
.insn_opcode_space
= n
;
10878 else if (startswith (line
, "EVEX")
10879 && (line
[4] == '.' || is_space_char (line
[4])))
10886 ? i
.vec_encoding
== vex_encoding_evex
10888 ? i
.vec_encoding
== vex_encoding_vex
10889 || i
.vec_encoding
== vex_encoding_vex3
10890 : i
.vec_encoding
!= vex_encoding_default
)
10892 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10896 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10897 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10899 if (i
.vec_encoding
!= vex_encoding_default
)
10901 /* Only address size and segment override prefixes are permitted with
10902 VEX/XOP/EVEX encodings. */
10903 const unsigned char *p
= i
.prefix
;
10905 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10916 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
10922 if (line
> end
&& *line
== '.')
10924 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
10932 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10934 i
.tm
.opcode_modifier
.vex
= VEX128
;
10939 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10941 i
.tm
.opcode_modifier
.vex
= VEX256
;
10946 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10951 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
10955 if (line
[3] == 'G')
10958 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10960 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10966 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
10971 if (line
[2] == '2' && line
[3] == '8')
10974 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10976 i
.tm
.opcode_modifier
.vex
= VEX128
;
10982 if (line
[2] == '5' && line
[3] == '6')
10985 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10987 i
.tm
.opcode_modifier
.vex
= VEX256
;
10993 if (evex
&& line
[2] == '1' && line
[3] == '2')
10995 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11002 if (line
> end
&& *line
== '.')
11004 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11008 if (line
[2] == 'P')
11013 if (line
[2] == '6')
11015 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11020 case 'F': case 'f':
11021 if (line
[2] == '3')
11023 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11026 else if (line
[2] == '2')
11028 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11035 if (line
> end
&& !xop
&& *line
== '.')
11037 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11041 if (TOUPPER (line
[2]) != 'F')
11043 if (line
[3] == '.' || is_space_char (line
[3]))
11045 i
.insn_opcode_space
= SPACE_0F
;
11048 else if (line
[3] == '3'
11049 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11050 && (line
[5] == '.' || is_space_char (line
[5])))
11052 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11058 if (ISDIGIT (line
[2]) && line
[2] != '0')
11061 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11063 if (n
<= (evex
? 15 : 31)
11064 && (*e
== '.' || is_space_char (*e
)))
11066 i
.insn_opcode_space
= n
;
11074 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11076 /* VEX.W, XOP.W, EVEX.W */
11080 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11084 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11088 if (line
[3] == 'G')
11090 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11096 if (i
.tm
.opcode_modifier
.vexw
)
11100 if (line
> end
&& *line
&& !is_space_char (*line
))
11102 /* Improve diagnostic a little. */
11103 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11108 /* Before processing the opcode expression, find trailing "+r" or
11109 "/<digit>" specifiers. */
11110 for (ptr
= line
; ; ++ptr
)
11115 ptr
= strpbrk (ptr
, "+/,");
11116 if (ptr
== NULL
|| *ptr
== ',')
11119 if (*ptr
== '+' && ptr
[1] == 'r'
11120 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11124 i
.short_form
= true;
11128 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11129 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11131 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11135 i
.tm
.extension_opcode
= n
;
11136 i
.tm
.opcode_modifier
.modrm
= 1;
11141 input_line_pointer
= line
;
11142 val
= get_absolute_expression ();
11143 line
= input_line_pointer
;
11145 if (i
.short_form
&& (val
& 7))
11146 as_warn ("`+r' assumes low three opcode bits to be clear");
11148 for (j
= 1; j
< sizeof(val
); ++j
)
11149 if (!(val
>> (j
* 8)))
11152 /* Trim off a prefix if present. */
11153 if (j
> 1 && !vex
&& !xop
&& !evex
)
11155 uint8_t byte
= val
>> ((j
- 1) * 8);
11159 case DATA_PREFIX_OPCODE
:
11160 case REPE_PREFIX_OPCODE
:
11161 case REPNE_PREFIX_OPCODE
:
11162 if (!add_prefix (byte
))
11164 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11169 /* Trim off encoding space. */
11170 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11172 uint8_t byte
= val
>> ((--j
- 1) * 8);
11174 i
.insn_opcode_space
= SPACE_0F
;
11175 switch (byte
& -(j
> 1))
11178 i
.insn_opcode_space
= SPACE_0F38
;
11182 i
.insn_opcode_space
= SPACE_0F3A
;
11186 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11187 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11189 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11190 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11191 Also avoid hitting abort() there or in build_evex_prefix(). */
11192 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11197 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11200 i
.opcode_length
= j
;
11202 /* Handle operands, if any. */
11205 i386_operand_type combined
;
11206 expressionS
*disp_exp
= NULL
;
11211 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11219 as_bad (_("expecting operand after ','; got nothing"));
11223 if (i
.mem_operands
> 1)
11225 as_bad (_("too many memory references for `%s'"),
11226 &i386_mnemonics
[MN__insn
]);
11230 /* Are we to emit ModR/M encoding? */
11233 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11234 || i
.tm
.extension_opcode
!= None
))
11235 i
.tm
.opcode_modifier
.modrm
= 1;
11237 if (!i
.tm
.opcode_modifier
.modrm
11239 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11240 || i
.mem_operands
))
11242 as_bad (_("too many register/memory operands"));
11246 /* Enforce certain constraints on operands. */
11247 switch (i
.reg_operands
+ i
.mem_operands
11248 + (i
.tm
.extension_opcode
!= None
))
11253 as_bad (_("too few register/memory operands"));
11256 /* Fall through. */
11258 if (i
.tm
.opcode_modifier
.modrm
)
11260 as_bad (_("too few register/memory operands"));
11270 && (i
.op
[0].imms
->X_op
!= O_constant
11271 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11273 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11276 /* Fall through. */
11278 if (i
.vec_encoding
!= vex_encoding_default
)
11280 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11283 /* Fall through. */
11285 as_bad (_("too many register/memory operands"));
11289 /* Bring operands into canonical order (imm, mem, reg). */
11294 for (j
= 1; j
< i
.operands
; ++j
)
11296 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11297 && operand_type_check (i
.types
[j
], imm
))
11298 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11299 && i
.types
[j
].bitfield
.class == ClassNone
))
11301 swap_2_operands (j
- 1, j
);
11308 /* For Intel syntax swap the order of register operands. */
11310 switch (i
.reg_operands
)
11317 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11318 /* Fall through. */
11321 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11328 /* Enforce constraints when using VSIB. */
11330 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11331 || i
.index_reg
->reg_type
.bitfield
.ymmword
11332 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11334 if (i
.vec_encoding
== vex_encoding_default
)
11336 as_bad (_("VSIB unavailable with legacy encoding"));
11340 if (i
.vec_encoding
== vex_encoding_evex
11341 && i
.reg_operands
> 1)
11343 /* We could allow two register operands, encoding the 2nd one in
11344 an 8-bit immediate like for 4-register-operand insns, but that
11345 would require ugly fiddling with process_operands() and/or
11346 build_modrm_byte(). */
11347 as_bad (_("too many register operands with VSIB"));
11351 i
.tm
.opcode_modifier
.sib
= 1;
11354 /* Establish operand size encoding. */
11355 operand_type_set (&combined
, 0);
11357 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11359 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11361 if (operand_type_check (i
.types
[j
], disp
))
11363 i
.types
[j
].bitfield
.baseindex
= 1;
11364 disp_exp
= i
.op
[j
].disps
;
11367 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11369 unsigned int n
= i
.memshift
;
11371 if (i
.types
[j
].bitfield
.byte
)
11373 else if (i
.types
[j
].bitfield
.word
)
11375 else if (i
.types
[j
].bitfield
.dword
)
11377 else if (i
.types
[j
].bitfield
.qword
)
11379 else if (i
.types
[j
].bitfield
.xmmword
)
11381 else if (i
.types
[j
].bitfield
.ymmword
)
11383 else if (i
.types
[j
].bitfield
.zmmword
)
11386 if (i
.memshift
< 32 && n
!= i
.memshift
)
11387 as_warn ("conflicting memory operand size specifiers");
11391 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11392 && j
== i
.broadcast
.operand
)
11395 combined
= operand_type_or (combined
, i
.types
[j
]);
11396 combined
.bitfield
.class = ClassNone
;
11399 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11400 << (i
.memshift
< 32 ? i
.memshift
: 0))
11402 case 64: combined
.bitfield
.zmmword
= 1; break;
11403 case 32: combined
.bitfield
.ymmword
= 1; break;
11404 case 16: combined
.bitfield
.xmmword
= 1; break;
11405 case 8: combined
.bitfield
.qword
= 1; break;
11406 case 4: combined
.bitfield
.dword
= 1; break;
11409 if (i
.vec_encoding
== vex_encoding_default
)
11411 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11413 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11414 : combined
.bitfield
.word
)
11415 && !add_prefix (DATA_PREFIX_OPCODE
))
11418 else if (!i
.tm
.opcode_modifier
.vexw
)
11420 if (flag_code
== CODE_64BIT
)
11422 if (combined
.bitfield
.qword
)
11423 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11424 else if (combined
.bitfield
.dword
)
11425 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11428 if (!i
.tm
.opcode_modifier
.vexw
)
11429 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11434 if (!i
.tm
.opcode_modifier
.vex
)
11436 if (combined
.bitfield
.ymmword
)
11437 i
.tm
.opcode_modifier
.vex
= VEX256
;
11438 else if (combined
.bitfield
.xmmword
)
11439 i
.tm
.opcode_modifier
.vex
= VEX128
;
11444 if (!i
.tm
.opcode_modifier
.evex
)
11446 /* Do _not_ consider AVX512VL here. */
11447 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11448 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11449 else if (combined
.bitfield
.ymmword
)
11450 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11451 else if (combined
.bitfield
.xmmword
)
11452 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11455 if (i
.memshift
>= 32)
11457 unsigned int n
= 0;
11459 switch (i
.tm
.opcode_modifier
.evex
)
11461 case EVEX512
: n
= 64; break;
11462 case EVEX256
: n
= 32; break;
11463 case EVEX128
: n
= 16; break;
11466 if (i
.broadcast
.type
)
11467 n
/= i
.broadcast
.type
;
11470 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11472 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11473 && disp_exp
->X_add_number
!= 0
11474 && i
.disp_encoding
!= disp_encoding_32bit
)
11476 if (!quiet_warnings
)
11477 as_warn ("cannot determine memory operand size");
11478 i
.disp_encoding
= disp_encoding_32bit
;
11483 if (i
.memshift
>= 32)
11486 i
.vec_encoding
= vex_encoding_error
;
11488 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11491 /* Establish size for immediate operands. */
11492 for (j
= 0; j
< i
.imm_operands
; ++j
)
11494 expressionS
*expP
= i
.op
[j
].imms
;
11496 gas_assert (operand_type_check (i
.types
[j
], imm
));
11497 operand_type_set (&i
.types
[j
], 0);
11499 if (i
.imm_bits
[j
] > 32)
11500 i
.types
[j
].bitfield
.imm64
= 1;
11501 else if (i
.imm_bits
[j
] > 16)
11503 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11504 i
.types
[j
].bitfield
.imm32s
= 1;
11506 i
.types
[j
].bitfield
.imm32
= 1;
11508 else if (i
.imm_bits
[j
] > 8)
11509 i
.types
[j
].bitfield
.imm16
= 1;
11510 else if (i
.imm_bits
[j
] > 0)
11512 if (i
.flags
[j
] & Operand_Signed
)
11513 i
.types
[j
].bitfield
.imm8s
= 1;
11515 i
.types
[j
].bitfield
.imm8
= 1;
11517 else if (expP
->X_op
== O_constant
)
11519 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11520 i
.types
[j
].bitfield
.imm1
= 0;
11521 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11522 zapping since smallest_imm_type() sets it unconditionally. */
11523 if (flag_code
!= CODE_64BIT
)
11525 i
.types
[j
].bitfield
.imm64
= 0;
11526 i
.types
[j
].bitfield
.imm32s
= 0;
11527 i
.types
[j
].bitfield
.imm32
= 1;
11529 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11530 i
.types
[j
].bitfield
.imm64
= 0;
11533 /* Non-constant expressions are sized heuristically. */
11536 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11537 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11538 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11542 for (j
= 0; j
< i
.operands
; ++j
)
11543 i
.tm
.operand_types
[j
] = i
.types
[j
];
11545 process_operands ();
11548 /* Don't set opcode until after processing operands, to avoid any
11549 potential special casing there. */
11550 i
.tm
.base_opcode
|= val
;
11552 if (i
.vec_encoding
== vex_encoding_error
11553 || (i
.vec_encoding
!= vex_encoding_evex
11554 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11555 || i
.rounding
.type
!= rc_none
11557 : (i
.broadcast
.type
|| i
.broadcast
.bytes
)
11558 && i
.rounding
.type
!= rc_none
))
11560 as_bad (_("conflicting .insn operands"));
11566 if (!i
.tm
.opcode_modifier
.vex
)
11567 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11569 build_vex_prefix (NULL
);
11570 i
.rex
&= REX_OPCODE
;
11574 if (!i
.tm
.opcode_modifier
.evex
)
11575 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11577 build_evex_prefix ();
11578 i
.rex
&= REX_OPCODE
;
11580 else if (i
.rex
!= 0)
11581 add_prefix (REX_OPCODE
| i
.rex
);
11586 *saved_ilp
= saved_char
;
11587 input_line_pointer
= line
;
11589 demand_empty_rest_of_line ();
11591 /* Make sure dot_insn() won't yield "true" anymore. */
11597 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11604 if (exp
.X_op
== O_symbol
)
11605 exp
.X_op
= O_secrel
;
11607 emit_expr (&exp
, 4);
11609 while (*input_line_pointer
++ == ',');
11611 input_line_pointer
--;
11612 demand_empty_rest_of_line ();
11616 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11623 if (exp
.X_op
== O_symbol
)
11624 exp
.X_op
= O_secidx
;
11626 emit_expr (&exp
, 2);
11628 while (*input_line_pointer
++ == ',');
11630 input_line_pointer
--;
11631 demand_empty_rest_of_line ();
11635 /* Handle Rounding Control / SAE specifiers. */
11638 RC_SAE_specifier (const char *pstr
)
11642 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11644 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11646 if (i
.rounding
.type
!= rc_none
)
11648 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11652 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11654 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11661 /* Handle Vector operations. */
11664 check_VecOperations (char *op_string
)
11666 const reg_entry
*mask
;
11673 if (*op_string
== '{')
11677 /* Check broadcasts. */
11678 if (startswith (op_string
, "1to"))
11680 unsigned int bcst_type
;
11682 if (i
.broadcast
.type
)
11683 goto duplicated_vec_op
;
11686 if (*op_string
== '8')
11688 else if (*op_string
== '4')
11690 else if (*op_string
== '2')
11692 else if (*op_string
== '1'
11693 && *(op_string
+1) == '6')
11698 else if (*op_string
== '3'
11699 && *(op_string
+1) == '2')
11706 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11711 i
.broadcast
.type
= bcst_type
;
11712 i
.broadcast
.operand
= this_operand
;
11714 /* For .insn a data size specifier may be appended. */
11715 if (dot_insn () && *op_string
== ':')
11716 goto dot_insn_modifier
;
11718 /* Check .insn special cases. */
11719 else if (dot_insn () && *op_string
== ':')
11722 switch (op_string
[1])
11727 if (i
.memshift
< 32)
11728 goto duplicated_vec_op
;
11730 n
= strtoul (op_string
+ 2, &end_op
, 0);
11732 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11734 if (i
.memshift
< 32 && n
== 1)
11735 op_string
= end_op
;
11738 case 's': case 'u':
11739 /* This isn't really a "vector" operation, but a sign/size
11740 specifier for immediate operands of .insn. Note that AT&T
11741 syntax handles the same in i386_immediate(). */
11745 if (i
.imm_bits
[this_operand
])
11746 goto duplicated_vec_op
;
11748 n
= strtoul (op_string
+ 2, &end_op
, 0);
11749 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11751 i
.imm_bits
[this_operand
] = n
;
11752 if (op_string
[1] == 's')
11753 i
.flags
[this_operand
] |= Operand_Signed
;
11754 op_string
= end_op
;
11759 /* Check masking operation. */
11760 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11762 if (mask
== &bad_reg
)
11765 /* k0 can't be used for write mask. */
11766 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11768 as_bad (_("`%s%s' can't be used for write mask"),
11769 register_prefix
, mask
->reg_name
);
11776 i
.mask
.operand
= this_operand
;
11778 else if (i
.mask
.reg
->reg_num
)
11779 goto duplicated_vec_op
;
11784 /* Only "{z}" is allowed here. No need to check
11785 zeroing mask explicitly. */
11786 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11788 as_bad (_("invalid write mask `%s'"), saved
);
11793 op_string
= end_op
;
11795 /* Check zeroing-flag for masking operation. */
11796 else if (*op_string
== 'z')
11800 i
.mask
.reg
= reg_k0
;
11801 i
.mask
.zeroing
= 1;
11802 i
.mask
.operand
= this_operand
;
11806 if (i
.mask
.zeroing
)
11809 as_bad (_("duplicated `%s'"), saved
);
11813 i
.mask
.zeroing
= 1;
11815 /* Only "{%k}" is allowed here. No need to check mask
11816 register explicitly. */
11817 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11819 as_bad (_("invalid zeroing-masking `%s'"),
11827 else if (intel_syntax
11828 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11829 i
.rounding
.modifier
= true;
11831 goto unknown_vec_op
;
11833 if (*op_string
!= '}')
11835 as_bad (_("missing `}' in `%s'"), saved
);
11840 /* Strip whitespace since the addition of pseudo prefixes
11841 changed how the scrubber treats '{'. */
11842 if (is_space_char (*op_string
))
11848 /* We don't know this one. */
11849 as_bad (_("unknown vector operation: `%s'"), saved
);
11853 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11855 as_bad (_("zeroing-masking only allowed with write mask"));
11863 i386_immediate (char *imm_start
)
11865 char *save_input_line_pointer
;
11866 char *gotfree_input_line
;
11869 i386_operand_type types
;
11871 operand_type_set (&types
, ~0);
11873 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11875 as_bad (_("at most %d immediate operands are allowed"),
11876 MAX_IMMEDIATE_OPERANDS
);
11880 exp
= &im_expressions
[i
.imm_operands
++];
11881 i
.op
[this_operand
].imms
= exp
;
11883 if (is_space_char (*imm_start
))
11886 save_input_line_pointer
= input_line_pointer
;
11887 input_line_pointer
= imm_start
;
11889 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11890 if (gotfree_input_line
)
11891 input_line_pointer
= gotfree_input_line
;
11893 expr_mode
= expr_operator_none
;
11894 exp_seg
= expression (exp
);
11896 /* For .insn immediates there may be a size specifier. */
11897 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11898 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11901 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11903 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11905 i
.imm_bits
[this_operand
] = n
;
11906 if (input_line_pointer
[2] == 's')
11907 i
.flags
[this_operand
] |= Operand_Signed
;
11908 input_line_pointer
= e
+ 1;
11912 SKIP_WHITESPACE ();
11913 if (*input_line_pointer
)
11914 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11916 input_line_pointer
= save_input_line_pointer
;
11917 if (gotfree_input_line
)
11919 free (gotfree_input_line
);
11921 if (exp
->X_op
== O_constant
)
11922 exp
->X_op
= O_illegal
;
11925 if (exp_seg
== reg_section
)
11927 as_bad (_("illegal immediate register operand %s"), imm_start
);
11931 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
11935 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11936 i386_operand_type types
, const char *imm_start
)
11938 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
11941 as_bad (_("missing or invalid immediate expression `%s'"),
11945 else if (exp
->X_op
== O_constant
)
11947 /* Size it properly later. */
11948 i
.types
[this_operand
].bitfield
.imm64
= 1;
11950 /* If not 64bit, sign/zero extend val, to account for wraparound
11952 if (expr_mode
== expr_operator_present
11953 && flag_code
!= CODE_64BIT
&& !object_64bit
)
11954 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11956 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11957 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11958 && exp_seg
!= absolute_section
11959 && exp_seg
!= text_section
11960 && exp_seg
!= data_section
11961 && exp_seg
!= bss_section
11962 && exp_seg
!= undefined_section
11963 && !bfd_is_com_section (exp_seg
))
11965 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11971 /* This is an address. The size of the address will be
11972 determined later, depending on destination register,
11973 suffix, or the default for the section. */
11974 i
.types
[this_operand
].bitfield
.imm8
= 1;
11975 i
.types
[this_operand
].bitfield
.imm16
= 1;
11976 i
.types
[this_operand
].bitfield
.imm32
= 1;
11977 i
.types
[this_operand
].bitfield
.imm32s
= 1;
11978 i
.types
[this_operand
].bitfield
.imm64
= 1;
11979 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11987 i386_scale (char *scale
)
11990 char *save
= input_line_pointer
;
11992 input_line_pointer
= scale
;
11993 val
= get_absolute_expression ();
11998 i
.log2_scale_factor
= 0;
12001 i
.log2_scale_factor
= 1;
12004 i
.log2_scale_factor
= 2;
12007 i
.log2_scale_factor
= 3;
12011 char sep
= *input_line_pointer
;
12013 *input_line_pointer
= '\0';
12014 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12016 *input_line_pointer
= sep
;
12017 input_line_pointer
= save
;
12021 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12023 as_warn (_("scale factor of %d without an index register"),
12024 1 << i
.log2_scale_factor
);
12025 i
.log2_scale_factor
= 0;
12027 scale
= input_line_pointer
;
12028 input_line_pointer
= save
;
12033 i386_displacement (char *disp_start
, char *disp_end
)
12037 char *save_input_line_pointer
;
12038 char *gotfree_input_line
;
12040 i386_operand_type bigdisp
, types
= anydisp
;
12043 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12045 as_bad (_("at most %d displacement operands are allowed"),
12046 MAX_MEMORY_OPERANDS
);
12050 operand_type_set (&bigdisp
, 0);
12052 || i
.types
[this_operand
].bitfield
.baseindex
12053 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12054 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12056 i386_addressing_mode ();
12057 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12058 if (flag_code
== CODE_64BIT
)
12060 bigdisp
.bitfield
.disp32
= 1;
12062 bigdisp
.bitfield
.disp64
= 1;
12064 else if ((flag_code
== CODE_16BIT
) ^ override
)
12065 bigdisp
.bitfield
.disp16
= 1;
12067 bigdisp
.bitfield
.disp32
= 1;
12071 /* For PC-relative branches, the width of the displacement may be
12072 dependent upon data size, but is never dependent upon address size.
12073 Also make sure to not unintentionally match against a non-PC-relative
12074 branch template. */
12075 static templates aux_templates
;
12076 const insn_template
*t
= current_templates
->start
;
12077 bool has_intel64
= false;
12079 aux_templates
.start
= t
;
12080 while (++t
< current_templates
->end
)
12082 if (t
->opcode_modifier
.jump
12083 != current_templates
->start
->opcode_modifier
.jump
)
12085 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12086 has_intel64
= true;
12088 if (t
< current_templates
->end
)
12090 aux_templates
.end
= t
;
12091 current_templates
= &aux_templates
;
12094 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12095 if (flag_code
== CODE_64BIT
)
12097 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12098 && (!intel64
|| !has_intel64
))
12099 bigdisp
.bitfield
.disp16
= 1;
12101 bigdisp
.bitfield
.disp32
= 1;
12106 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12108 : LONG_MNEM_SUFFIX
));
12109 bigdisp
.bitfield
.disp32
= 1;
12110 if ((flag_code
== CODE_16BIT
) ^ override
)
12112 bigdisp
.bitfield
.disp32
= 0;
12113 bigdisp
.bitfield
.disp16
= 1;
12117 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12120 exp
= &disp_expressions
[i
.disp_operands
];
12121 i
.op
[this_operand
].disps
= exp
;
12123 save_input_line_pointer
= input_line_pointer
;
12124 input_line_pointer
= disp_start
;
12125 END_STRING_AND_SAVE (disp_end
);
12127 #ifndef GCC_ASM_O_HACK
12128 #define GCC_ASM_O_HACK 0
12131 END_STRING_AND_SAVE (disp_end
+ 1);
12132 if (i
.types
[this_operand
].bitfield
.baseIndex
12133 && displacement_string_end
[-1] == '+')
12135 /* This hack is to avoid a warning when using the "o"
12136 constraint within gcc asm statements.
12139 #define _set_tssldt_desc(n,addr,limit,type) \
12140 __asm__ __volatile__ ( \
12141 "movw %w2,%0\n\t" \
12142 "movw %w1,2+%0\n\t" \
12143 "rorl $16,%1\n\t" \
12144 "movb %b1,4+%0\n\t" \
12145 "movb %4,5+%0\n\t" \
12146 "movb $0,6+%0\n\t" \
12147 "movb %h1,7+%0\n\t" \
12149 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12151 This works great except that the output assembler ends
12152 up looking a bit weird if it turns out that there is
12153 no offset. You end up producing code that looks like:
12166 So here we provide the missing zero. */
12168 *displacement_string_end
= '0';
12171 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12172 if (gotfree_input_line
)
12173 input_line_pointer
= gotfree_input_line
;
12175 expr_mode
= expr_operator_none
;
12176 exp_seg
= expression (exp
);
12178 SKIP_WHITESPACE ();
12179 if (*input_line_pointer
)
12180 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12182 RESTORE_END_STRING (disp_end
+ 1);
12184 input_line_pointer
= save_input_line_pointer
;
12185 if (gotfree_input_line
)
12187 free (gotfree_input_line
);
12189 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12190 exp
->X_op
= O_illegal
;
12193 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12195 RESTORE_END_STRING (disp_end
);
12201 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12202 i386_operand_type types
, const char *disp_start
)
12206 /* We do this to make sure that the section symbol is in
12207 the symbol table. We will ultimately change the relocation
12208 to be relative to the beginning of the section. */
12209 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12210 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12211 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12213 if (exp
->X_op
!= O_symbol
)
12216 if (S_IS_LOCAL (exp
->X_add_symbol
)
12217 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12218 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12219 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12220 exp
->X_op
= O_subtract
;
12221 exp
->X_op_symbol
= GOT_symbol
;
12222 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12223 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12224 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12225 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12227 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12230 else if (exp
->X_op
== O_absent
12231 || exp
->X_op
== O_illegal
12232 || exp
->X_op
== O_big
)
12235 as_bad (_("missing or invalid displacement expression `%s'"),
12240 else if (exp
->X_op
== O_constant
)
12242 /* Sizing gets taken care of by optimize_disp().
12244 If not 64bit, sign/zero extend val, to account for wraparound
12246 if (expr_mode
== expr_operator_present
12247 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12248 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12251 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12252 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12253 && exp_seg
!= absolute_section
12254 && exp_seg
!= text_section
12255 && exp_seg
!= data_section
12256 && exp_seg
!= bss_section
12257 && exp_seg
!= undefined_section
12258 && !bfd_is_com_section (exp_seg
))
12260 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12265 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12266 i
.types
[this_operand
].bitfield
.disp8
= 1;
12268 /* Check if this is a displacement only operand. */
12269 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12270 i
.types
[this_operand
] =
12271 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12272 operand_type_and (i
.types
[this_operand
], types
));
12277 /* Return the active addressing mode, taking address override and
12278 registers forming the address into consideration. Update the
12279 address override prefix if necessary. */
12281 static enum flag_code
12282 i386_addressing_mode (void)
12284 enum flag_code addr_mode
;
12286 if (i
.prefix
[ADDR_PREFIX
])
12287 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12288 else if (flag_code
== CODE_16BIT
12289 && is_cpu (current_templates
->start
, CpuMPX
)
12290 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12291 from md_assemble() by "is not a valid base/index expression"
12292 when there is a base and/or index. */
12293 && !i
.types
[this_operand
].bitfield
.baseindex
)
12295 /* MPX insn memory operands with neither base nor index must be forced
12296 to use 32-bit addressing in 16-bit mode. */
12297 addr_mode
= CODE_32BIT
;
12298 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12300 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12301 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12305 addr_mode
= flag_code
;
12307 #if INFER_ADDR_PREFIX
12308 if (i
.mem_operands
== 0)
12310 /* Infer address prefix from the first memory operand. */
12311 const reg_entry
*addr_reg
= i
.base_reg
;
12313 if (addr_reg
== NULL
)
12314 addr_reg
= i
.index_reg
;
12318 if (addr_reg
->reg_type
.bitfield
.dword
)
12319 addr_mode
= CODE_32BIT
;
12320 else if (flag_code
!= CODE_64BIT
12321 && addr_reg
->reg_type
.bitfield
.word
)
12322 addr_mode
= CODE_16BIT
;
12324 if (addr_mode
!= flag_code
)
12326 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12328 /* Change the size of any displacement too. At most one
12329 of Disp16 or Disp32 is set.
12330 FIXME. There doesn't seem to be any real need for
12331 separate Disp16 and Disp32 flags. The same goes for
12332 Imm16 and Imm32. Removing them would probably clean
12333 up the code quite a lot. */
12334 if (flag_code
!= CODE_64BIT
12335 && (i
.types
[this_operand
].bitfield
.disp16
12336 || i
.types
[this_operand
].bitfield
.disp32
))
12338 static const i386_operand_type disp16_32
= {
12339 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12342 i
.types
[this_operand
]
12343 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12354 /* Make sure the memory operand we've been dealt is valid.
12355 Return 1 on success, 0 on a failure. */
12358 i386_index_check (const char *operand_string
)
12360 const char *kind
= "base/index";
12361 enum flag_code addr_mode
= i386_addressing_mode ();
12362 const insn_template
*t
= current_templates
->end
- 1;
12364 if (t
->opcode_modifier
.isstring
)
12366 /* Memory operands of string insns are special in that they only allow
12367 a single register (rDI, rSI, or rBX) as their memory address. */
12368 const reg_entry
*expected_reg
;
12369 static const char di_si
[][2][4] =
12375 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12377 kind
= "string address";
12379 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12381 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12384 if (!t
->operand_types
[0].bitfield
.baseindex
12385 || ((!i
.mem_operands
!= !intel_syntax
)
12386 && t
->operand_types
[1].bitfield
.baseindex
))
12389 = (const reg_entry
*) str_hash_find (reg_hash
,
12390 di_si
[addr_mode
][op
== es_op
]);
12394 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12396 if (i
.base_reg
!= expected_reg
12398 || operand_type_check (i
.types
[this_operand
], disp
))
12400 /* The second memory operand must have the same size as
12404 && !((addr_mode
== CODE_64BIT
12405 && i
.base_reg
->reg_type
.bitfield
.qword
)
12406 || (addr_mode
== CODE_32BIT
12407 ? i
.base_reg
->reg_type
.bitfield
.dword
12408 : i
.base_reg
->reg_type
.bitfield
.word
)))
12411 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12413 intel_syntax
? '[' : '(',
12415 expected_reg
->reg_name
,
12416 intel_syntax
? ']' : ')');
12423 as_bad (_("`%s' is not a valid %s expression"),
12424 operand_string
, kind
);
12429 t
= current_templates
->start
;
12431 if (addr_mode
!= CODE_16BIT
)
12433 /* 32-bit/64-bit checks. */
12434 if (i
.disp_encoding
== disp_encoding_16bit
)
12437 as_bad (_("invalid `%s' prefix"),
12438 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12443 && ((addr_mode
== CODE_64BIT
12444 ? !i
.base_reg
->reg_type
.bitfield
.qword
12445 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12446 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12447 || i
.base_reg
->reg_num
== RegIZ
))
12449 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12450 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12451 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12452 && ((addr_mode
== CODE_64BIT
12453 ? !i
.index_reg
->reg_type
.bitfield
.qword
12454 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12455 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12458 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12459 if (t
->mnem_off
== MN_bndmk
12460 || t
->mnem_off
== MN_bndldx
12461 || t
->mnem_off
== MN_bndstx
12462 || t
->opcode_modifier
.sib
== SIBMEM
)
12464 /* They cannot use RIP-relative addressing. */
12465 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12467 as_bad (_("`%s' cannot be used here"), operand_string
);
12471 /* bndldx and bndstx ignore their scale factor. */
12472 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12473 && i
.log2_scale_factor
)
12474 as_warn (_("register scaling is being ignored here"));
12479 /* 16-bit checks. */
12480 if (i
.disp_encoding
== disp_encoding_32bit
)
12484 && (!i
.base_reg
->reg_type
.bitfield
.word
12485 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12487 && (!i
.index_reg
->reg_type
.bitfield
.word
12488 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12490 && i
.base_reg
->reg_num
< 6
12491 && i
.index_reg
->reg_num
>= 6
12492 && i
.log2_scale_factor
== 0))))
12499 /* Handle vector immediates. */
12502 RC_SAE_immediate (const char *imm_start
)
12504 const char *pstr
= imm_start
;
12509 pstr
= RC_SAE_specifier (pstr
+ 1);
12513 if (*pstr
++ != '}')
12515 as_bad (_("Missing '}': '%s'"), imm_start
);
12518 /* RC/SAE immediate string should contain nothing more. */;
12521 as_bad (_("Junk after '}': '%s'"), imm_start
);
12525 /* Internally this doesn't count as an operand. */
12531 static INLINE
bool starts_memory_operand (char c
)
12534 || is_name_beginner (c
)
12535 || strchr ("([\"+-!~", c
);
12538 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12542 i386_att_operand (char *operand_string
)
12544 const reg_entry
*r
;
12546 char *op_string
= operand_string
;
12548 if (is_space_char (*op_string
))
12551 /* We check for an absolute prefix (differentiating,
12552 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12553 if (*op_string
== ABSOLUTE_PREFIX
12554 && current_templates
->start
->opcode_modifier
.jump
)
12557 if (is_space_char (*op_string
))
12559 i
.jumpabsolute
= true;
12562 /* Check if operand is a register. */
12563 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12565 i386_operand_type temp
;
12570 /* Check for a segment override by searching for ':' after a
12571 segment register. */
12572 op_string
= end_op
;
12573 if (is_space_char (*op_string
))
12575 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12577 i
.seg
[i
.mem_operands
] = r
;
12579 /* Skip the ':' and whitespace. */
12581 if (is_space_char (*op_string
))
12584 /* Handle case of %es:*foo. */
12585 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12586 && current_templates
->start
->opcode_modifier
.jump
)
12589 if (is_space_char (*op_string
))
12591 i
.jumpabsolute
= true;
12594 if (!starts_memory_operand (*op_string
))
12596 as_bad (_("bad memory operand `%s'"), op_string
);
12599 goto do_memory_reference
;
12602 /* Handle vector operations. */
12603 if (*op_string
== '{')
12605 op_string
= check_VecOperations (op_string
);
12606 if (op_string
== NULL
)
12612 as_bad (_("junk `%s' after register"), op_string
);
12616 /* Reject pseudo registers for .insn. */
12617 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12619 as_bad (_("`%s%s' cannot be used here"),
12620 register_prefix
, r
->reg_name
);
12624 temp
= r
->reg_type
;
12625 temp
.bitfield
.baseindex
= 0;
12626 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12628 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12629 i
.op
[this_operand
].regs
= r
;
12632 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12633 operand was also present earlier on. */
12634 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12635 && i
.reg_operands
== 1)
12639 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12640 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12642 as_bad (_("`%s': misplaced `{%s}'"),
12643 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12647 else if (*op_string
== REGISTER_PREFIX
)
12649 as_bad (_("bad register name `%s'"), op_string
);
12652 else if (*op_string
== IMMEDIATE_PREFIX
)
12655 if (i
.jumpabsolute
)
12657 as_bad (_("immediate operand illegal with absolute jump"));
12660 if (!i386_immediate (op_string
))
12662 if (i
.rounding
.type
!= rc_none
)
12664 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12665 insn_name (current_templates
->start
));
12669 else if (RC_SAE_immediate (operand_string
))
12671 /* If it is a RC or SAE immediate, do the necessary placement check:
12672 Only another immediate or a GPR may precede it. */
12673 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12674 || (i
.reg_operands
== 1
12675 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12677 as_bad (_("`%s': misplaced `%s'"),
12678 insn_name (current_templates
->start
), operand_string
);
12682 else if (starts_memory_operand (*op_string
))
12684 /* This is a memory reference of some sort. */
12687 /* Start and end of displacement string expression (if found). */
12688 char *displacement_string_start
;
12689 char *displacement_string_end
;
12691 do_memory_reference
:
12692 /* Check for base index form. We detect the base index form by
12693 looking for an ')' at the end of the operand, searching
12694 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12696 base_string
= op_string
+ strlen (op_string
);
12698 /* Handle vector operations. */
12700 if (is_space_char (*base_string
))
12703 if (*base_string
== '}')
12705 char *vop_start
= NULL
;
12707 while (base_string
-- > op_string
)
12709 if (*base_string
== '"')
12711 if (*base_string
!= '{')
12714 vop_start
= base_string
;
12717 if (is_space_char (*base_string
))
12720 if (*base_string
!= '}')
12728 as_bad (_("unbalanced figure braces"));
12732 if (check_VecOperations (vop_start
) == NULL
)
12736 /* If we only have a displacement, set-up for it to be parsed later. */
12737 displacement_string_start
= op_string
;
12738 displacement_string_end
= base_string
+ 1;
12740 if (*base_string
== ')')
12743 unsigned int parens_not_balanced
= 0;
12744 bool in_quotes
= false;
12746 /* We've already checked that the number of left & right ()'s are
12747 equal, and that there's a matching set of double quotes. */
12748 end_op
= base_string
;
12749 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12751 if (*temp_string
== '\\' && temp_string
[1] == '"')
12753 else if (*temp_string
== '"')
12754 in_quotes
= !in_quotes
;
12755 else if (!in_quotes
)
12757 if (*temp_string
== '(' && !parens_not_balanced
++)
12758 base_string
= temp_string
;
12759 if (*temp_string
== ')')
12760 --parens_not_balanced
;
12764 temp_string
= base_string
;
12766 /* Skip past '(' and whitespace. */
12767 gas_assert (*base_string
== '(');
12769 if (is_space_char (*base_string
))
12772 if (*base_string
== ','
12773 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12776 displacement_string_end
= temp_string
;
12778 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12782 if (i
.base_reg
== &bad_reg
)
12784 base_string
= end_op
;
12785 if (is_space_char (*base_string
))
12789 /* There may be an index reg or scale factor here. */
12790 if (*base_string
== ',')
12793 if (is_space_char (*base_string
))
12796 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12799 if (i
.index_reg
== &bad_reg
)
12801 base_string
= end_op
;
12802 if (is_space_char (*base_string
))
12804 if (*base_string
== ',')
12807 if (is_space_char (*base_string
))
12810 else if (*base_string
!= ')')
12812 as_bad (_("expecting `,' or `)' "
12813 "after index register in `%s'"),
12818 else if (*base_string
== REGISTER_PREFIX
)
12820 end_op
= strchr (base_string
, ',');
12823 as_bad (_("bad register name `%s'"), base_string
);
12827 /* Check for scale factor. */
12828 if (*base_string
!= ')')
12830 char *end_scale
= i386_scale (base_string
);
12835 base_string
= end_scale
;
12836 if (is_space_char (*base_string
))
12838 if (*base_string
!= ')')
12840 as_bad (_("expecting `)' "
12841 "after scale factor in `%s'"),
12846 else if (!i
.index_reg
)
12848 as_bad (_("expecting index register or scale factor "
12849 "after `,'; got '%c'"),
12854 else if (*base_string
!= ')')
12856 as_bad (_("expecting `,' or `)' "
12857 "after base register in `%s'"),
12862 else if (*base_string
== REGISTER_PREFIX
)
12864 end_op
= strchr (base_string
, ',');
12867 as_bad (_("bad register name `%s'"), base_string
);
12872 /* If there's an expression beginning the operand, parse it,
12873 assuming displacement_string_start and
12874 displacement_string_end are meaningful. */
12875 if (displacement_string_start
!= displacement_string_end
)
12877 if (!i386_displacement (displacement_string_start
,
12878 displacement_string_end
))
12882 /* Special case for (%dx) while doing input/output op. */
12884 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12885 && i
.base_reg
->reg_type
.bitfield
.word
12886 && i
.index_reg
== 0
12887 && i
.log2_scale_factor
== 0
12888 && i
.seg
[i
.mem_operands
] == 0
12889 && !operand_type_check (i
.types
[this_operand
], disp
))
12891 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12892 i
.input_output_operand
= true;
12896 if (i386_index_check (operand_string
) == 0)
12898 i
.flags
[this_operand
] |= Operand_Mem
;
12903 /* It's not a memory operand; argh! */
12904 as_bad (_("invalid char %s beginning operand %d `%s'"),
12905 output_invalid (*op_string
),
12910 return 1; /* Normal return. */
12913 /* Calculate the maximum variable size (i.e., excluding fr_fix)
12914 that an rs_machine_dependent frag may reach. */
12917 i386_frag_max_var (fragS
*frag
)
12919 /* The only relaxable frags are for jumps.
12920 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
12921 gas_assert (frag
->fr_type
== rs_machine_dependent
);
12922 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
12925 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12927 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
12929 /* STT_GNU_IFUNC symbol must go through PLT. */
12930 if ((symbol_get_bfdsym (fr_symbol
)->flags
12931 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
12934 if (!S_IS_EXTERNAL (fr_symbol
))
12935 /* Symbol may be weak or local. */
12936 return !S_IS_WEAK (fr_symbol
);
12938 /* Global symbols with non-default visibility can't be preempted. */
12939 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
12942 if (fr_var
!= NO_RELOC
)
12943 switch ((enum bfd_reloc_code_real
) fr_var
)
12945 case BFD_RELOC_386_PLT32
:
12946 case BFD_RELOC_X86_64_PLT32
:
12947 /* Symbol with PLT relocation may be preempted. */
12953 /* Global symbols with default visibility in a shared library may be
12954 preempted by another definition. */
12959 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
12960 Note also work for Skylake and Cascadelake.
12961 ---------------------------------------------------------------------
12962 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
12963 | ------ | ----------- | ------- | -------- |
12965 | Jno | N | N | Y |
12966 | Jc/Jb | Y | N | Y |
12967 | Jae/Jnb | Y | N | Y |
12968 | Je/Jz | Y | Y | Y |
12969 | Jne/Jnz | Y | Y | Y |
12970 | Jna/Jbe | Y | N | Y |
12971 | Ja/Jnbe | Y | N | Y |
12973 | Jns | N | N | Y |
12974 | Jp/Jpe | N | N | Y |
12975 | Jnp/Jpo | N | N | Y |
12976 | Jl/Jnge | Y | Y | Y |
12977 | Jge/Jnl | Y | Y | Y |
12978 | Jle/Jng | Y | Y | Y |
12979 | Jg/Jnle | Y | Y | Y |
12980 --------------------------------------------------------------------- */
12982 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
12984 if (mf_cmp
== mf_cmp_alu_cmp
)
12985 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
12986 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
12987 if (mf_cmp
== mf_cmp_incdec
)
12988 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
12989 || mf_jcc
== mf_jcc_jle
);
12990 if (mf_cmp
== mf_cmp_test_and
)
12995 /* Return the next non-empty frag. */
12998 i386_next_non_empty_frag (fragS
*fragP
)
13000 /* There may be a frag with a ".fill 0" when there is no room in
13001 the current frag for frag_grow in output_insn. */
13002 for (fragP
= fragP
->fr_next
;
13004 && fragP
->fr_type
== rs_fill
13005 && fragP
->fr_fix
== 0);
13006 fragP
= fragP
->fr_next
)
13011 /* Return the next jcc frag after BRANCH_PADDING. */
13014 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13016 fragS
*branch_fragP
;
13020 if (pad_fragP
->fr_type
== rs_machine_dependent
13021 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13022 == BRANCH_PADDING
))
13024 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13025 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13027 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13028 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13029 pad_fragP
->tc_frag_data
.mf_type
))
13030 return branch_fragP
;
13036 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13039 i386_classify_machine_dependent_frag (fragS
*fragP
)
13043 fragS
*branch_fragP
;
13045 unsigned int max_prefix_length
;
13047 if (fragP
->tc_frag_data
.classified
)
13050 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13051 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13052 for (next_fragP
= fragP
;
13053 next_fragP
!= NULL
;
13054 next_fragP
= next_fragP
->fr_next
)
13056 next_fragP
->tc_frag_data
.classified
= 1;
13057 if (next_fragP
->fr_type
== rs_machine_dependent
)
13058 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13060 case BRANCH_PADDING
:
13061 /* The BRANCH_PADDING frag must be followed by a branch
13063 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13064 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13066 case FUSED_JCC_PADDING
:
13067 /* Check if this is a fused jcc:
13069 CMP like instruction
13073 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13074 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13075 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13078 /* The BRANCH_PADDING frag is merged with the
13079 FUSED_JCC_PADDING frag. */
13080 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13081 /* CMP like instruction size. */
13082 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13083 frag_wane (pad_fragP
);
13084 /* Skip to branch_fragP. */
13085 next_fragP
= branch_fragP
;
13087 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13089 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13091 next_fragP
->fr_subtype
13092 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13093 next_fragP
->tc_frag_data
.max_bytes
13094 = next_fragP
->tc_frag_data
.max_prefix_length
;
13095 /* This will be updated in the BRANCH_PREFIX scan. */
13096 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13099 frag_wane (next_fragP
);
13104 /* Stop if there is no BRANCH_PREFIX. */
13105 if (!align_branch_prefix_size
)
13108 /* Scan for BRANCH_PREFIX. */
13109 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13111 if (fragP
->fr_type
!= rs_machine_dependent
13112 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13116 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13117 COND_JUMP_PREFIX. */
13118 max_prefix_length
= 0;
13119 for (next_fragP
= fragP
;
13120 next_fragP
!= NULL
;
13121 next_fragP
= next_fragP
->fr_next
)
13123 if (next_fragP
->fr_type
== rs_fill
)
13124 /* Skip rs_fill frags. */
13126 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13127 /* Stop for all other frags. */
13130 /* rs_machine_dependent frags. */
13131 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13134 /* Count BRANCH_PREFIX frags. */
13135 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13137 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13138 frag_wane (next_fragP
);
13142 += next_fragP
->tc_frag_data
.max_bytes
;
13144 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13146 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13147 == FUSED_JCC_PADDING
))
13149 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13150 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13154 /* Stop for other rs_machine_dependent frags. */
13158 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13160 /* Skip to the next frag. */
13161 fragP
= next_fragP
;
13165 /* Compute padding size for
13168 CMP like instruction
13170 COND_JUMP/UNCOND_JUMP
13175 COND_JUMP/UNCOND_JUMP
13179 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13181 unsigned int offset
, size
, padding_size
;
13182 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13184 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13186 address
= fragP
->fr_address
;
13187 address
+= fragP
->fr_fix
;
13189 /* CMP like instrunction size. */
13190 size
= fragP
->tc_frag_data
.cmp_size
;
13192 /* The base size of the branch frag. */
13193 size
+= branch_fragP
->fr_fix
;
13195 /* Add opcode and displacement bytes for the rs_machine_dependent
13197 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13198 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13200 /* Check if branch is within boundary and doesn't end at the last
13202 offset
= address
& ((1U << align_branch_power
) - 1);
13203 if ((offset
+ size
) >= (1U << align_branch_power
))
13204 /* Padding needed to avoid crossing boundary. */
13205 padding_size
= (1U << align_branch_power
) - offset
;
13207 /* No padding needed. */
13210 /* The return value may be saved in tc_frag_data.length which is
13212 if (!fits_in_unsigned_byte (padding_size
))
13215 return padding_size
;
13218 /* i386_generic_table_relax_frag()
13220 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13221 grow/shrink padding to align branch frags. Hand others to
13225 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13227 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13228 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13230 long padding_size
= i386_branch_padding_size (fragP
, 0);
13231 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13233 /* When the BRANCH_PREFIX frag is used, the computed address
13234 must match the actual address and there should be no padding. */
13235 if (fragP
->tc_frag_data
.padding_address
13236 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13240 /* Update the padding size. */
13242 fragP
->tc_frag_data
.length
= padding_size
;
13246 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13248 fragS
*padding_fragP
, *next_fragP
;
13249 long padding_size
, left_size
, last_size
;
13251 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13252 if (!padding_fragP
)
13253 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13254 return (fragP
->tc_frag_data
.length
13255 - fragP
->tc_frag_data
.last_length
);
13257 /* Compute the relative address of the padding frag in the very
13258 first time where the BRANCH_PREFIX frag sizes are zero. */
13259 if (!fragP
->tc_frag_data
.padding_address
)
13260 fragP
->tc_frag_data
.padding_address
13261 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13263 /* First update the last length from the previous interation. */
13264 left_size
= fragP
->tc_frag_data
.prefix_length
;
13265 for (next_fragP
= fragP
;
13266 next_fragP
!= padding_fragP
;
13267 next_fragP
= next_fragP
->fr_next
)
13268 if (next_fragP
->fr_type
== rs_machine_dependent
13269 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13274 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13278 if (max
> left_size
)
13283 next_fragP
->tc_frag_data
.last_length
= size
;
13287 next_fragP
->tc_frag_data
.last_length
= 0;
13290 /* Check the padding size for the padding frag. */
13291 padding_size
= i386_branch_padding_size
13292 (padding_fragP
, (fragP
->fr_address
13293 + fragP
->tc_frag_data
.padding_address
));
13295 last_size
= fragP
->tc_frag_data
.prefix_length
;
13296 /* Check if there is change from the last interation. */
13297 if (padding_size
== last_size
)
13299 /* Update the expected address of the padding frag. */
13300 padding_fragP
->tc_frag_data
.padding_address
13301 = (fragP
->fr_address
+ padding_size
13302 + fragP
->tc_frag_data
.padding_address
);
13306 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13308 /* No padding if there is no sufficient room. Clear the
13309 expected address of the padding frag. */
13310 padding_fragP
->tc_frag_data
.padding_address
= 0;
13314 /* Store the expected address of the padding frag. */
13315 padding_fragP
->tc_frag_data
.padding_address
13316 = (fragP
->fr_address
+ padding_size
13317 + fragP
->tc_frag_data
.padding_address
);
13319 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13321 /* Update the length for the current interation. */
13322 left_size
= padding_size
;
13323 for (next_fragP
= fragP
;
13324 next_fragP
!= padding_fragP
;
13325 next_fragP
= next_fragP
->fr_next
)
13326 if (next_fragP
->fr_type
== rs_machine_dependent
13327 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13332 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13336 if (max
> left_size
)
13341 next_fragP
->tc_frag_data
.length
= size
;
13345 next_fragP
->tc_frag_data
.length
= 0;
13348 return (fragP
->tc_frag_data
.length
13349 - fragP
->tc_frag_data
.last_length
);
13351 return relax_frag (segment
, fragP
, stretch
);
13354 /* md_estimate_size_before_relax()
13356 Called just before relax() for rs_machine_dependent frags. The x86
13357 assembler uses these frags to handle variable size jump
13360 Any symbol that is now undefined will not become defined.
13361 Return the correct fr_subtype in the frag.
13362 Return the initial "guess for variable size of frag" to caller.
13363 The guess is actually the growth beyond the fixed part. Whatever
13364 we do to grow the fixed or variable part contributes to our
13368 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13370 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13371 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13372 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13374 i386_classify_machine_dependent_frag (fragP
);
13375 return fragP
->tc_frag_data
.length
;
13378 /* We've already got fragP->fr_subtype right; all we have to do is
13379 check for un-relaxable symbols. On an ELF system, we can't relax
13380 an externally visible symbol, because it may be overridden by a
13382 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13385 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13388 #if defined (OBJ_COFF) && defined (TE_PE)
13389 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13390 && S_IS_WEAK (fragP
->fr_symbol
))
13394 /* Symbol is undefined in this segment, or we need to keep a
13395 reloc so that weak symbols can be overridden. */
13396 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13397 enum bfd_reloc_code_real reloc_type
;
13398 unsigned char *opcode
;
13402 if (fragP
->fr_var
!= NO_RELOC
)
13403 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13404 else if (size
== 2)
13405 reloc_type
= BFD_RELOC_16_PCREL
;
13406 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13407 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13408 && need_plt32_p (fragP
->fr_symbol
))
13409 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13412 reloc_type
= BFD_RELOC_32_PCREL
;
13414 old_fr_fix
= fragP
->fr_fix
;
13415 opcode
= (unsigned char *) fragP
->fr_opcode
;
13417 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13420 /* Make jmp (0xeb) a (d)word displacement jump. */
13422 fragP
->fr_fix
+= size
;
13423 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13425 fragP
->fr_offset
, 1,
13431 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13433 /* Negate the condition, and branch past an
13434 unconditional jump. */
13437 /* Insert an unconditional jump. */
13439 /* We added two extra opcode bytes, and have a two byte
13441 fragP
->fr_fix
+= 2 + 2;
13442 fix_new (fragP
, old_fr_fix
+ 2, 2,
13444 fragP
->fr_offset
, 1,
13448 /* Fall through. */
13451 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13453 fragP
->fr_fix
+= 1;
13454 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13456 fragP
->fr_offset
, 1,
13457 BFD_RELOC_8_PCREL
);
13458 fixP
->fx_signed
= 1;
13462 /* This changes the byte-displacement jump 0x7N
13463 to the (d)word-displacement jump 0x0f,0x8N. */
13464 opcode
[1] = opcode
[0] + 0x10;
13465 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13466 /* We've added an opcode byte. */
13467 fragP
->fr_fix
+= 1 + size
;
13468 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13470 fragP
->fr_offset
, 1,
13475 BAD_CASE (fragP
->fr_subtype
);
13479 /* All jumps handled here are signed, but don't unconditionally use a
13480 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13481 around at 4G (outside of 64-bit mode) and 64k. */
13482 if (size
== 4 && flag_code
== CODE_64BIT
)
13483 fixP
->fx_signed
= 1;
13486 return fragP
->fr_fix
- old_fr_fix
;
13489 /* Guess size depending on current relax state. Initially the relax
13490 state will correspond to a short jump and we return 1, because
13491 the variable part of the frag (the branch offset) is one byte
13492 long. However, we can relax a section more than once and in that
13493 case we must either set fr_subtype back to the unrelaxed state,
13494 or return the value for the appropriate branch. */
13495 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13498 /* Called after relax() is finished.
13500 In: Address of frag.
13501 fr_type == rs_machine_dependent.
13502 fr_subtype is what the address relaxed to.
13504 Out: Any fixSs and constants are set up.
13505 Caller will turn frag into a ".space 0". */
13508 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13511 unsigned char *opcode
;
13512 unsigned char *where_to_put_displacement
= NULL
;
13513 offsetT target_address
;
13514 offsetT opcode_address
;
13515 unsigned int extension
= 0;
13516 offsetT displacement_from_opcode_start
;
13518 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13519 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13522 /* Generate nop padding. */
13523 unsigned int size
= fragP
->tc_frag_data
.length
;
13526 if (size
> fragP
->tc_frag_data
.max_bytes
)
13532 const char *branch
= "branch";
13533 const char *prefix
= "";
13534 fragS
*padding_fragP
;
13535 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13538 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13539 switch (fragP
->tc_frag_data
.default_prefix
)
13544 case CS_PREFIX_OPCODE
:
13547 case DS_PREFIX_OPCODE
:
13550 case ES_PREFIX_OPCODE
:
13553 case FS_PREFIX_OPCODE
:
13556 case GS_PREFIX_OPCODE
:
13559 case SS_PREFIX_OPCODE
:
13564 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13565 "%s within %d-byte boundary\n");
13567 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13568 "align %s within %d-byte boundary\n");
13572 padding_fragP
= fragP
;
13573 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13574 "%s within %d-byte boundary\n");
13578 switch (padding_fragP
->tc_frag_data
.branch_type
)
13580 case align_branch_jcc
:
13583 case align_branch_fused
:
13584 branch
= "fused jcc";
13586 case align_branch_jmp
:
13589 case align_branch_call
:
13592 case align_branch_indirect
:
13593 branch
= "indiret branch";
13595 case align_branch_ret
:
13602 fprintf (stdout
, msg
,
13603 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13604 (long long) fragP
->fr_address
, branch
,
13605 1 << align_branch_power
);
13607 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13608 memset (fragP
->fr_opcode
,
13609 fragP
->tc_frag_data
.default_prefix
, size
);
13611 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13613 fragP
->fr_fix
+= size
;
13618 opcode
= (unsigned char *) fragP
->fr_opcode
;
13620 /* Address we want to reach in file space. */
13621 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13623 /* Address opcode resides at in file space. */
13624 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13626 /* Displacement from opcode start to fill into instruction. */
13627 displacement_from_opcode_start
= target_address
- opcode_address
;
13629 if ((fragP
->fr_subtype
& BIG
) == 0)
13631 /* Don't have to change opcode. */
13632 extension
= 1; /* 1 opcode + 1 displacement */
13633 where_to_put_displacement
= &opcode
[1];
13637 if (no_cond_jump_promotion
13638 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13639 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13640 _("long jump required"));
13642 switch (fragP
->fr_subtype
)
13644 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13645 extension
= 4; /* 1 opcode + 4 displacement */
13647 where_to_put_displacement
= &opcode
[1];
13650 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13651 extension
= 2; /* 1 opcode + 2 displacement */
13653 where_to_put_displacement
= &opcode
[1];
13656 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13657 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13658 extension
= 5; /* 2 opcode + 4 displacement */
13659 opcode
[1] = opcode
[0] + 0x10;
13660 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13661 where_to_put_displacement
= &opcode
[2];
13664 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13665 extension
= 3; /* 2 opcode + 2 displacement */
13666 opcode
[1] = opcode
[0] + 0x10;
13667 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13668 where_to_put_displacement
= &opcode
[2];
13671 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13676 where_to_put_displacement
= &opcode
[3];
13680 BAD_CASE (fragP
->fr_subtype
);
13685 /* If size if less then four we are sure that the operand fits,
13686 but if it's 4, then it could be that the displacement is larger
13688 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13690 && ((addressT
) (displacement_from_opcode_start
- extension
13691 + ((addressT
) 1 << 31))
13692 > (((addressT
) 2 << 31) - 1)))
13694 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13695 _("jump target out of range"));
13696 /* Make us emit 0. */
13697 displacement_from_opcode_start
= extension
;
13699 /* Now put displacement after opcode. */
13700 md_number_to_chars ((char *) where_to_put_displacement
,
13701 (valueT
) (displacement_from_opcode_start
- extension
),
13702 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13703 fragP
->fr_fix
+= extension
;
13706 /* Apply a fixup (fixP) to segment data, once it has been determined
13707 by our caller that we have all the info we need to fix it up.
13709 Parameter valP is the pointer to the value of the bits.
13711 On the 386, immediates, displacements, and data pointers are all in
13712 the same (little-endian) format, so we don't need to care about which
13713 we are handling. */
13716 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13718 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13719 valueT value
= *valP
;
13721 #if !defined (TE_Mach)
13722 if (fixP
->fx_pcrel
)
13724 switch (fixP
->fx_r_type
)
13730 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13733 case BFD_RELOC_X86_64_32S
:
13734 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13737 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13740 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13745 if (fixP
->fx_addsy
!= NULL
13746 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13747 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13748 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13749 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13750 && !use_rela_relocations
)
13752 /* This is a hack. There should be a better way to handle this.
13753 This covers for the fact that bfd_install_relocation will
13754 subtract the current location (for partial_inplace, PC relative
13755 relocations); see more below. */
13759 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13762 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13767 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13769 if ((sym_seg
== seg
13770 || (symbol_section_p (fixP
->fx_addsy
)
13771 && sym_seg
!= absolute_section
))
13772 && !generic_force_reloc (fixP
))
13774 /* Yes, we add the values in twice. This is because
13775 bfd_install_relocation subtracts them out again. I think
13776 bfd_install_relocation is broken, but I don't dare change
13778 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13782 #if defined (OBJ_COFF) && defined (TE_PE)
13783 /* For some reason, the PE format does not store a
13784 section address offset for a PC relative symbol. */
13785 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13786 || S_IS_WEAK (fixP
->fx_addsy
))
13787 value
+= md_pcrel_from (fixP
);
13790 #if defined (OBJ_COFF) && defined (TE_PE)
13791 if (fixP
->fx_addsy
!= NULL
13792 && S_IS_WEAK (fixP
->fx_addsy
)
13793 /* PR 16858: Do not modify weak function references. */
13794 && ! fixP
->fx_pcrel
)
13796 #if !defined (TE_PEP)
13797 /* For x86 PE weak function symbols are neither PC-relative
13798 nor do they set S_IS_FUNCTION. So the only reliable way
13799 to detect them is to check the flags of their containing
13801 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13802 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13806 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13810 /* Fix a few things - the dynamic linker expects certain values here,
13811 and we must not disappoint it. */
13812 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13813 if (IS_ELF
&& fixP
->fx_addsy
)
13814 switch (fixP
->fx_r_type
)
13816 case BFD_RELOC_386_PLT32
:
13817 case BFD_RELOC_X86_64_PLT32
:
13818 /* Make the jump instruction point to the address of the operand.
13819 At runtime we merely add the offset to the actual PLT entry.
13820 NB: Subtract the offset size only for jump instructions. */
13821 if (fixP
->fx_pcrel
)
13825 case BFD_RELOC_386_TLS_GD
:
13826 case BFD_RELOC_386_TLS_LDM
:
13827 case BFD_RELOC_386_TLS_IE_32
:
13828 case BFD_RELOC_386_TLS_IE
:
13829 case BFD_RELOC_386_TLS_GOTIE
:
13830 case BFD_RELOC_386_TLS_GOTDESC
:
13831 case BFD_RELOC_X86_64_TLSGD
:
13832 case BFD_RELOC_X86_64_TLSLD
:
13833 case BFD_RELOC_X86_64_GOTTPOFF
:
13834 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13835 value
= 0; /* Fully resolved at runtime. No addend. */
13837 case BFD_RELOC_386_TLS_LE
:
13838 case BFD_RELOC_386_TLS_LDO_32
:
13839 case BFD_RELOC_386_TLS_LE_32
:
13840 case BFD_RELOC_X86_64_DTPOFF32
:
13841 case BFD_RELOC_X86_64_DTPOFF64
:
13842 case BFD_RELOC_X86_64_TPOFF32
:
13843 case BFD_RELOC_X86_64_TPOFF64
:
13844 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13847 case BFD_RELOC_386_TLS_DESC_CALL
:
13848 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13849 value
= 0; /* Fully resolved at runtime. No addend. */
13850 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13854 case BFD_RELOC_VTABLE_INHERIT
:
13855 case BFD_RELOC_VTABLE_ENTRY
:
13862 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13864 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13866 value
= extend_to_32bit_address (value
);
13869 #endif /* !defined (TE_Mach) */
13871 /* Are we finished with this relocation now? */
13872 if (fixP
->fx_addsy
== NULL
)
13875 switch (fixP
->fx_r_type
)
13877 case BFD_RELOC_X86_64_32S
:
13878 fixP
->fx_signed
= 1;
13885 #if defined (OBJ_COFF) && defined (TE_PE)
13886 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13889 /* Remember value for tc_gen_reloc. */
13890 fixP
->fx_addnumber
= value
;
13891 /* Clear out the frag for now. */
13895 else if (use_rela_relocations
)
13897 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13898 fixP
->fx_no_overflow
= 1;
13899 /* Remember value for tc_gen_reloc. */
13900 fixP
->fx_addnumber
= value
;
13904 md_number_to_chars (p
, value
, fixP
->fx_size
);
13908 md_atof (int type
, char *litP
, int *sizeP
)
13910 /* This outputs the LITTLENUMs in REVERSE order;
13911 in accord with the bigendian 386. */
13912 return ieee_md_atof (type
, litP
, sizeP
, false);
13915 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
13918 output_invalid (int c
)
13921 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13924 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13925 "(0x%x)", (unsigned char) c
);
13926 return output_invalid_buf
;
13929 /* Verify that @r can be used in the current context. */
13931 static bool check_register (const reg_entry
*r
)
13933 if (allow_pseudo_reg
)
13936 if (operand_type_all_zero (&r
->reg_type
))
13939 if ((r
->reg_type
.bitfield
.dword
13940 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
13941 || r
->reg_type
.bitfield
.class == RegCR
13942 || r
->reg_type
.bitfield
.class == RegDR
)
13943 && !cpu_arch_flags
.bitfield
.cpui386
)
13946 if (r
->reg_type
.bitfield
.class == RegTR
13947 && (flag_code
== CODE_64BIT
13948 || !cpu_arch_flags
.bitfield
.cpui386
13949 || cpu_arch_isa_flags
.bitfield
.cpui586
13950 || cpu_arch_isa_flags
.bitfield
.cpui686
))
13953 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
13956 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
13958 if (r
->reg_type
.bitfield
.zmmword
13959 || r
->reg_type
.bitfield
.class == RegMask
)
13962 if (!cpu_arch_flags
.bitfield
.cpuavx
)
13964 if (r
->reg_type
.bitfield
.ymmword
)
13967 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
13972 if (vector_size
< VSZ512
&& r
->reg_type
.bitfield
.zmmword
)
13975 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
13978 if (r
->reg_type
.bitfield
.tmmword
13979 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
13980 || flag_code
!= CODE_64BIT
))
13983 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
13986 /* Don't allow fake index register unless allow_index_reg isn't 0. */
13987 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
13990 /* Upper 16 vector registers are only available with VREX in 64bit
13991 mode, and require EVEX encoding. */
13992 if (r
->reg_flags
& RegVRex
)
13994 if (!cpu_arch_flags
.bitfield
.cpuavx512f
13995 || flag_code
!= CODE_64BIT
)
13998 if (i
.vec_encoding
== vex_encoding_default
)
13999 i
.vec_encoding
= vex_encoding_evex
;
14000 else if (i
.vec_encoding
!= vex_encoding_evex
)
14001 i
.vec_encoding
= vex_encoding_error
;
14004 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14005 && (!cpu_arch_flags
.bitfield
.cpulm
14006 || r
->reg_type
.bitfield
.class != RegCR
14008 && flag_code
!= CODE_64BIT
)
14011 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14018 /* REG_STRING starts *before* REGISTER_PREFIX. */
14020 static const reg_entry
*
14021 parse_real_register (const char *reg_string
, char **end_op
)
14023 const char *s
= reg_string
;
14025 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14026 const reg_entry
*r
;
14028 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14029 if (*s
== REGISTER_PREFIX
)
14032 if (is_space_char (*s
))
14035 p
= reg_name_given
;
14036 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14038 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14039 return (const reg_entry
*) NULL
;
14043 if (is_part_of_name (*s
))
14044 return (const reg_entry
*) NULL
;
14046 *end_op
= (char *) s
;
14048 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14050 /* Handle floating point regs, allowing spaces in the (i) part. */
14053 if (!cpu_arch_flags
.bitfield
.cpu8087
14054 && !cpu_arch_flags
.bitfield
.cpu287
14055 && !cpu_arch_flags
.bitfield
.cpu387
14056 && !allow_pseudo_reg
)
14057 return (const reg_entry
*) NULL
;
14059 if (is_space_char (*s
))
14064 if (is_space_char (*s
))
14066 if (*s
>= '0' && *s
<= '7')
14068 int fpr
= *s
- '0';
14070 if (is_space_char (*s
))
14074 *end_op
= (char *) s
+ 1;
14075 know (r
[fpr
].reg_num
== fpr
);
14079 /* We have "%st(" then garbage. */
14080 return (const reg_entry
*) NULL
;
14084 return r
&& check_register (r
) ? r
: NULL
;
14087 /* REG_STRING starts *before* REGISTER_PREFIX. */
14089 static const reg_entry
*
14090 parse_register (const char *reg_string
, char **end_op
)
14092 const reg_entry
*r
;
14094 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14095 r
= parse_real_register (reg_string
, end_op
);
14100 char *save
= input_line_pointer
;
14101 char *buf
= xstrdup (reg_string
), *name
;
14104 input_line_pointer
= buf
;
14105 get_symbol_name (&name
);
14106 symbolP
= symbol_find (name
);
14107 while (symbolP
&& symbol_equated_p (symbolP
))
14109 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14111 if (e
->X_add_number
)
14113 symbolP
= e
->X_add_symbol
;
14115 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14117 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14119 if (e
->X_op
== O_register
)
14121 know (e
->X_add_number
>= 0
14122 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14123 r
= i386_regtab
+ e
->X_add_number
;
14124 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14126 if (r
&& !check_register (r
))
14128 as_bad (_("register '%s%s' cannot be used here"),
14129 register_prefix
, r
->reg_name
);
14133 input_line_pointer
= save
;
14140 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14142 const reg_entry
*r
= NULL
;
14143 char *end
= input_line_pointer
;
14145 /* We only know the terminating character here. It being double quote could
14146 be the closing one of a quoted symbol name, or an opening one from a
14147 following string (or another quoted symbol name). Since the latter can't
14148 be valid syntax for anything, bailing in either case is good enough. */
14149 if (*nextcharP
== '"')
14153 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14154 r
= parse_real_register (name
, &input_line_pointer
);
14155 if (r
&& end
<= input_line_pointer
)
14157 *nextcharP
= *input_line_pointer
;
14158 *input_line_pointer
= 0;
14159 e
->X_op
= O_register
;
14160 e
->X_add_number
= r
- i386_regtab
;
14163 input_line_pointer
= end
;
14165 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14169 md_operand (expressionS
*e
)
14172 const reg_entry
*r
;
14174 switch (*input_line_pointer
)
14176 case REGISTER_PREFIX
:
14177 r
= parse_real_register (input_line_pointer
, &end
);
14180 e
->X_op
= O_register
;
14181 e
->X_add_number
= r
- i386_regtab
;
14182 input_line_pointer
= end
;
14187 gas_assert (intel_syntax
);
14188 end
= input_line_pointer
++;
14190 if (*input_line_pointer
== ']')
14192 ++input_line_pointer
;
14193 e
->X_op_symbol
= make_expr_symbol (e
);
14194 e
->X_add_symbol
= NULL
;
14195 e
->X_add_number
= 0;
14200 e
->X_op
= O_absent
;
14201 input_line_pointer
= end
;
14208 /* To maintain consistency with !BFD64 builds of gas record, whether any
14209 (binary) operator was involved in an expression. As expressions are
14210 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14211 truncate results. */
14212 bool i386_record_operator (operatorT op
,
14213 const expressionS
*left
,
14214 const expressionS
*right
)
14216 if (op
== O_absent
)
14221 /* Since the expression parser applies unary operators fine to bignum
14222 operands, we don't need to be concerned of respective operands not
14223 fitting in 32 bits. */
14224 if (right
->X_op
== O_constant
&& right
->X_unsigned
14225 && !fits_in_unsigned_long (right
->X_add_number
))
14228 /* This isn't entirely right: The pattern can also result when constant
14229 expressions are folded (e.g. 0xffffffff + 1). */
14230 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14231 && !fits_in_unsigned_long (left
->X_add_number
))
14232 || (right
->X_op
== O_constant
&& right
->X_unsigned
14233 && !fits_in_unsigned_long (right
->X_add_number
)))
14234 expr_mode
= expr_large_value
;
14236 if (expr_mode
!= expr_large_value
)
14237 expr_mode
= expr_operator_present
;
14243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14244 const char *md_shortopts
= "kVQ:sqnO::";
14246 const char *md_shortopts
= "qnO::";
14249 #define OPTION_32 (OPTION_MD_BASE + 0)
14250 #define OPTION_64 (OPTION_MD_BASE + 1)
14251 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14252 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14253 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14254 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14255 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14256 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14257 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14258 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14259 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14260 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14261 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14262 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14263 #define OPTION_X32 (OPTION_MD_BASE + 14)
14264 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14265 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14266 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14267 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14268 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14269 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14270 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14271 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14272 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14273 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14274 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14275 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14276 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14277 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14278 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14279 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14280 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14281 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14282 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14283 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14285 struct option md_longopts
[] =
14287 {"32", no_argument
, NULL
, OPTION_32
},
14288 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14289 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14290 {"64", no_argument
, NULL
, OPTION_64
},
14292 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14293 {"x32", no_argument
, NULL
, OPTION_X32
},
14294 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14295 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14297 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14298 {"march", required_argument
, NULL
, OPTION_MARCH
},
14299 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14300 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14301 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14302 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14303 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14304 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14305 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14306 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14307 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14308 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14309 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14310 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14311 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14312 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14313 # if defined (TE_PE) || defined (TE_PEP)
14314 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14316 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14317 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14318 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14319 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14320 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14321 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14322 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14323 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14324 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14325 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14326 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14327 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14328 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14329 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14330 {NULL
, no_argument
, NULL
, 0}
14332 size_t md_longopts_size
= sizeof (md_longopts
);
14335 md_parse_option (int c
, const char *arg
)
14338 char *arch
, *next
, *saved
, *type
;
14343 optimize_align_code
= 0;
14347 quiet_warnings
= 1;
14350 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14351 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14352 should be emitted or not. FIXME: Not implemented. */
14354 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14358 /* -V: SVR4 argument to print version ID. */
14360 print_version_id ();
14363 /* -k: Ignore for FreeBSD compatibility. */
14368 /* -s: On i386 Solaris, this tells the native assembler to use
14369 .stab instead of .stab.excl. We always use .stab anyhow. */
14372 case OPTION_MSHARED
:
14376 case OPTION_X86_USED_NOTE
:
14377 if (strcasecmp (arg
, "yes") == 0)
14379 else if (strcasecmp (arg
, "no") == 0)
14382 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14387 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14388 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14391 const char **list
, **l
;
14393 list
= bfd_target_list ();
14394 for (l
= list
; *l
!= NULL
; l
++)
14395 if (startswith (*l
, "elf64-x86-64")
14396 || strcmp (*l
, "coff-x86-64") == 0
14397 || strcmp (*l
, "pe-x86-64") == 0
14398 || strcmp (*l
, "pei-x86-64") == 0
14399 || strcmp (*l
, "mach-o-x86-64") == 0)
14401 default_arch
= "x86_64";
14405 as_fatal (_("no compiled in support for x86_64"));
14411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14415 const char **list
, **l
;
14417 list
= bfd_target_list ();
14418 for (l
= list
; *l
!= NULL
; l
++)
14419 if (startswith (*l
, "elf32-x86-64"))
14421 default_arch
= "x86_64:32";
14425 as_fatal (_("no compiled in support for 32bit x86_64"));
14429 as_fatal (_("32bit x86_64 is only supported for ELF"));
14435 const char **list
, **l
;
14437 list
= bfd_target_list ();
14438 for (l
= list
; *l
!= NULL
; l
++)
14439 if (strstr (*l
, "-i386")
14440 || strstr (*l
, "-go32"))
14442 default_arch
= "i386";
14446 as_fatal (_("no compiled in support for ix86"));
14451 case OPTION_DIVIDE
:
14452 #ifdef SVR4_COMMENT_CHARS
14457 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14459 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14463 i386_comment_chars
= n
;
14469 saved
= xstrdup (arg
);
14471 /* Allow -march=+nosse. */
14479 as_fatal (_("invalid -march= option: `%s'"), arg
);
14480 next
= strchr (arch
, '+');
14483 vsz
= strchr (arch
, '/');
14486 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14488 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14491 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14492 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14495 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14498 cpu_arch_name
= cpu_arch
[j
].name
;
14499 free (cpu_sub_arch_name
);
14500 cpu_sub_arch_name
= NULL
;
14501 cpu_arch_flags
= cpu_arch
[j
].enable
;
14502 cpu_arch_isa
= cpu_arch
[j
].type
;
14503 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14504 if (!cpu_arch_tune_set
)
14506 cpu_arch_tune
= cpu_arch_isa
;
14507 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14509 vector_size
= VSZ_DEFAULT
;
14512 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14513 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14514 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14516 /* ISA extension. */
14517 i386_cpu_flags flags
;
14519 flags
= cpu_flags_or (cpu_arch_flags
,
14520 cpu_arch
[j
].enable
);
14522 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14524 extend_cpu_sub_arch_name (arch
);
14525 cpu_arch_flags
= flags
;
14526 cpu_arch_isa_flags
= flags
;
14530 = cpu_flags_or (cpu_arch_isa_flags
,
14531 cpu_arch
[j
].enable
);
14533 switch (cpu_arch
[j
].vsz
)
14542 unsigned long val
= strtoul (vsz
, &end
, 0);
14548 case 512: vector_size
= VSZ512
; break;
14549 case 256: vector_size
= VSZ256
; break;
14550 case 128: vector_size
= VSZ128
; break;
14552 as_warn (_("Unrecognized vector size specifier ignored"));
14557 /* Fall through. */
14559 vector_size
= VSZ_DEFAULT
;
14567 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14569 /* Disable an ISA extension. */
14570 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14571 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14572 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14574 i386_cpu_flags flags
;
14576 flags
= cpu_flags_and_not (cpu_arch_flags
,
14577 cpu_arch
[j
].disable
);
14578 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14580 extend_cpu_sub_arch_name (arch
);
14581 cpu_arch_flags
= flags
;
14582 cpu_arch_isa_flags
= flags
;
14584 if (cpu_arch
[j
].vsz
== vsz_set
)
14585 vector_size
= VSZ_DEFAULT
;
14590 if (j
>= ARRAY_SIZE (cpu_arch
))
14591 as_fatal (_("invalid -march= option: `%s'"), arg
);
14595 while (next
!= NULL
);
14601 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14602 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14604 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14605 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14607 cpu_arch_tune_set
= 1;
14608 cpu_arch_tune
= cpu_arch
[j
].type
;
14609 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14613 if (j
>= ARRAY_SIZE (cpu_arch
))
14614 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14617 case OPTION_MMNEMONIC
:
14618 if (strcasecmp (arg
, "att") == 0)
14619 intel_mnemonic
= 0;
14620 else if (strcasecmp (arg
, "intel") == 0)
14621 intel_mnemonic
= 1;
14623 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14626 case OPTION_MSYNTAX
:
14627 if (strcasecmp (arg
, "att") == 0)
14629 else if (strcasecmp (arg
, "intel") == 0)
14632 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14635 case OPTION_MINDEX_REG
:
14636 allow_index_reg
= 1;
14639 case OPTION_MNAKED_REG
:
14640 allow_naked_reg
= 1;
14643 case OPTION_MSSE2AVX
:
14647 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14648 use_unaligned_vector_move
= 1;
14651 case OPTION_MSSE_CHECK
:
14652 if (strcasecmp (arg
, "error") == 0)
14653 sse_check
= check_error
;
14654 else if (strcasecmp (arg
, "warning") == 0)
14655 sse_check
= check_warning
;
14656 else if (strcasecmp (arg
, "none") == 0)
14657 sse_check
= check_none
;
14659 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14662 case OPTION_MOPERAND_CHECK
:
14663 if (strcasecmp (arg
, "error") == 0)
14664 operand_check
= check_error
;
14665 else if (strcasecmp (arg
, "warning") == 0)
14666 operand_check
= check_warning
;
14667 else if (strcasecmp (arg
, "none") == 0)
14668 operand_check
= check_none
;
14670 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14673 case OPTION_MAVXSCALAR
:
14674 if (strcasecmp (arg
, "128") == 0)
14675 avxscalar
= vex128
;
14676 else if (strcasecmp (arg
, "256") == 0)
14677 avxscalar
= vex256
;
14679 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14682 case OPTION_MVEXWIG
:
14683 if (strcmp (arg
, "0") == 0)
14685 else if (strcmp (arg
, "1") == 0)
14688 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14691 case OPTION_MADD_BND_PREFIX
:
14692 add_bnd_prefix
= 1;
14695 case OPTION_MEVEXLIG
:
14696 if (strcmp (arg
, "128") == 0)
14697 evexlig
= evexl128
;
14698 else if (strcmp (arg
, "256") == 0)
14699 evexlig
= evexl256
;
14700 else if (strcmp (arg
, "512") == 0)
14701 evexlig
= evexl512
;
14703 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14706 case OPTION_MEVEXRCIG
:
14707 if (strcmp (arg
, "rne") == 0)
14709 else if (strcmp (arg
, "rd") == 0)
14711 else if (strcmp (arg
, "ru") == 0)
14713 else if (strcmp (arg
, "rz") == 0)
14716 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14719 case OPTION_MEVEXWIG
:
14720 if (strcmp (arg
, "0") == 0)
14722 else if (strcmp (arg
, "1") == 0)
14725 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14728 # if defined (TE_PE) || defined (TE_PEP)
14729 case OPTION_MBIG_OBJ
:
14734 case OPTION_MOMIT_LOCK_PREFIX
:
14735 if (strcasecmp (arg
, "yes") == 0)
14736 omit_lock_prefix
= 1;
14737 else if (strcasecmp (arg
, "no") == 0)
14738 omit_lock_prefix
= 0;
14740 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14743 case OPTION_MFENCE_AS_LOCK_ADD
:
14744 if (strcasecmp (arg
, "yes") == 0)
14746 else if (strcasecmp (arg
, "no") == 0)
14749 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14752 case OPTION_MLFENCE_AFTER_LOAD
:
14753 if (strcasecmp (arg
, "yes") == 0)
14754 lfence_after_load
= 1;
14755 else if (strcasecmp (arg
, "no") == 0)
14756 lfence_after_load
= 0;
14758 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14761 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14762 if (strcasecmp (arg
, "all") == 0)
14764 lfence_before_indirect_branch
= lfence_branch_all
;
14765 if (lfence_before_ret
== lfence_before_ret_none
)
14766 lfence_before_ret
= lfence_before_ret_shl
;
14768 else if (strcasecmp (arg
, "memory") == 0)
14769 lfence_before_indirect_branch
= lfence_branch_memory
;
14770 else if (strcasecmp (arg
, "register") == 0)
14771 lfence_before_indirect_branch
= lfence_branch_register
;
14772 else if (strcasecmp (arg
, "none") == 0)
14773 lfence_before_indirect_branch
= lfence_branch_none
;
14775 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14779 case OPTION_MLFENCE_BEFORE_RET
:
14780 if (strcasecmp (arg
, "or") == 0)
14781 lfence_before_ret
= lfence_before_ret_or
;
14782 else if (strcasecmp (arg
, "not") == 0)
14783 lfence_before_ret
= lfence_before_ret_not
;
14784 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14785 lfence_before_ret
= lfence_before_ret_shl
;
14786 else if (strcasecmp (arg
, "none") == 0)
14787 lfence_before_ret
= lfence_before_ret_none
;
14789 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14793 case OPTION_MRELAX_RELOCATIONS
:
14794 if (strcasecmp (arg
, "yes") == 0)
14795 generate_relax_relocations
= 1;
14796 else if (strcasecmp (arg
, "no") == 0)
14797 generate_relax_relocations
= 0;
14799 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14802 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14805 long int align
= strtoul (arg
, &end
, 0);
14810 align_branch_power
= 0;
14813 else if (align
>= 16)
14816 for (align_power
= 0;
14818 align
>>= 1, align_power
++)
14820 /* Limit alignment power to 31. */
14821 if (align
== 1 && align_power
< 32)
14823 align_branch_power
= align_power
;
14828 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14832 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14835 int align
= strtoul (arg
, &end
, 0);
14836 /* Some processors only support 5 prefixes. */
14837 if (*end
== '\0' && align
>= 0 && align
< 6)
14839 align_branch_prefix_size
= align
;
14842 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14847 case OPTION_MALIGN_BRANCH
:
14849 saved
= xstrdup (arg
);
14853 next
= strchr (type
, '+');
14856 if (strcasecmp (type
, "jcc") == 0)
14857 align_branch
|= align_branch_jcc_bit
;
14858 else if (strcasecmp (type
, "fused") == 0)
14859 align_branch
|= align_branch_fused_bit
;
14860 else if (strcasecmp (type
, "jmp") == 0)
14861 align_branch
|= align_branch_jmp_bit
;
14862 else if (strcasecmp (type
, "call") == 0)
14863 align_branch
|= align_branch_call_bit
;
14864 else if (strcasecmp (type
, "ret") == 0)
14865 align_branch
|= align_branch_ret_bit
;
14866 else if (strcasecmp (type
, "indirect") == 0)
14867 align_branch
|= align_branch_indirect_bit
;
14869 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14872 while (next
!= NULL
);
14876 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14877 align_branch_power
= 5;
14878 align_branch_prefix_size
= 5;
14879 align_branch
= (align_branch_jcc_bit
14880 | align_branch_fused_bit
14881 | align_branch_jmp_bit
);
14884 case OPTION_MAMD64
:
14888 case OPTION_MINTEL64
:
14896 /* Turn off -Os. */
14897 optimize_for_space
= 0;
14899 else if (*arg
== 's')
14901 optimize_for_space
= 1;
14902 /* Turn on all encoding optimizations. */
14903 optimize
= INT_MAX
;
14907 optimize
= atoi (arg
);
14908 /* Turn off -Os. */
14909 optimize_for_space
= 0;
14919 #define MESSAGE_TEMPLATE \
14923 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14924 int *left_p
, const char *name
, int len
)
14926 int size
= sizeof (MESSAGE_TEMPLATE
);
14927 int left
= *left_p
;
14929 /* Reserve 2 spaces for ", " or ",\0" */
14932 /* Check if there is any room. */
14940 p
= mempcpy (p
, name
, len
);
14944 /* Output the current message now and start a new one. */
14947 fprintf (stream
, "%s\n", message
);
14949 left
= size
- (start
- message
) - len
- 2;
14951 gas_assert (left
>= 0);
14953 p
= mempcpy (p
, name
, len
);
14961 show_arch (FILE *stream
, int ext
, int check
)
14963 static char message
[] = MESSAGE_TEMPLATE
;
14964 char *start
= message
+ 27;
14966 int size
= sizeof (MESSAGE_TEMPLATE
);
14973 left
= size
- (start
- message
);
14977 p
= output_message (stream
, p
, message
, start
, &left
,
14978 STRING_COMMA_LEN ("default"));
14979 p
= output_message (stream
, p
, message
, start
, &left
,
14980 STRING_COMMA_LEN ("push"));
14981 p
= output_message (stream
, p
, message
, start
, &left
,
14982 STRING_COMMA_LEN ("pop"));
14985 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14987 /* Should it be skipped? */
14988 if (cpu_arch
[j
].skip
)
14991 name
= cpu_arch
[j
].name
;
14992 len
= cpu_arch
[j
].len
;
14993 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
14995 /* It is an extension. Skip if we aren't asked to show it. */
14996 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15001 /* It is an processor. Skip if we show only extension. */
15004 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15006 /* It is an impossible processor - skip. */
15010 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15013 /* Display disabled extensions. */
15015 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15019 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15020 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15022 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15023 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15029 fprintf (stream
, "%s\n", message
);
15033 md_show_usage (FILE *stream
)
15035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15036 fprintf (stream
, _("\
15037 -Qy, -Qn ignored\n\
15038 -V print assembler version number\n\
15041 fprintf (stream
, _("\
15042 -n do not optimize code alignment\n\
15043 -O{012s} attempt some code optimizations\n\
15044 -q quieten some warnings\n"));
15045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15046 fprintf (stream
, _("\
15050 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15051 fprintf (stream
, _("\
15052 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15053 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15054 fprintf (stream
, _("\
15055 --32/--64 generate 32bit/64bit object\n"));
15058 #ifdef SVR4_COMMENT_CHARS
15059 fprintf (stream
, _("\
15060 --divide do not treat `/' as a comment character\n"));
15062 fprintf (stream
, _("\
15063 --divide ignored\n"));
15065 fprintf (stream
, _("\
15066 -march=CPU[,+EXTENSION...]\n\
15067 generate code for CPU and EXTENSION, CPU is one of:\n"));
15068 show_arch (stream
, 0, 1);
15069 fprintf (stream
, _("\
15070 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15071 show_arch (stream
, 1, 0);
15072 fprintf (stream
, _("\
15073 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15074 show_arch (stream
, 0, 0);
15075 fprintf (stream
, _("\
15076 -msse2avx encode SSE instructions with VEX prefix\n"));
15077 fprintf (stream
, _("\
15078 -muse-unaligned-vector-move\n\
15079 encode aligned vector move as unaligned vector move\n"));
15080 fprintf (stream
, _("\
15081 -msse-check=[none|error|warning] (default: warning)\n\
15082 check SSE instructions\n"));
15083 fprintf (stream
, _("\
15084 -moperand-check=[none|error|warning] (default: warning)\n\
15085 check operand combinations for validity\n"));
15086 fprintf (stream
, _("\
15087 -mavxscalar=[128|256] (default: 128)\n\
15088 encode scalar AVX instructions with specific vector\n\
15090 fprintf (stream
, _("\
15091 -mvexwig=[0|1] (default: 0)\n\
15092 encode VEX instructions with specific VEX.W value\n\
15093 for VEX.W bit ignored instructions\n"));
15094 fprintf (stream
, _("\
15095 -mevexlig=[128|256|512] (default: 128)\n\
15096 encode scalar EVEX instructions with specific vector\n\
15098 fprintf (stream
, _("\
15099 -mevexwig=[0|1] (default: 0)\n\
15100 encode EVEX instructions with specific EVEX.W value\n\
15101 for EVEX.W bit ignored instructions\n"));
15102 fprintf (stream
, _("\
15103 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15104 encode EVEX instructions with specific EVEX.RC value\n\
15105 for SAE-only ignored instructions\n"));
15106 fprintf (stream
, _("\
15107 -mmnemonic=[att|intel] "));
15108 if (SYSV386_COMPAT
)
15109 fprintf (stream
, _("(default: att)\n"));
15111 fprintf (stream
, _("(default: intel)\n"));
15112 fprintf (stream
, _("\
15113 use AT&T/Intel mnemonic\n"));
15114 fprintf (stream
, _("\
15115 -msyntax=[att|intel] (default: att)\n\
15116 use AT&T/Intel syntax\n"));
15117 fprintf (stream
, _("\
15118 -mindex-reg support pseudo index registers\n"));
15119 fprintf (stream
, _("\
15120 -mnaked-reg don't require `%%' prefix for registers\n"));
15121 fprintf (stream
, _("\
15122 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15124 fprintf (stream
, _("\
15125 -mshared disable branch optimization for shared code\n"));
15126 fprintf (stream
, _("\
15127 -mx86-used-note=[no|yes] "));
15128 if (DEFAULT_X86_USED_NOTE
)
15129 fprintf (stream
, _("(default: yes)\n"));
15131 fprintf (stream
, _("(default: no)\n"));
15132 fprintf (stream
, _("\
15133 generate x86 used ISA and feature properties\n"));
15135 #if defined (TE_PE) || defined (TE_PEP)
15136 fprintf (stream
, _("\
15137 -mbig-obj generate big object files\n"));
15139 fprintf (stream
, _("\
15140 -momit-lock-prefix=[no|yes] (default: no)\n\
15141 strip all lock prefixes\n"));
15142 fprintf (stream
, _("\
15143 -mfence-as-lock-add=[no|yes] (default: no)\n\
15144 encode lfence, mfence and sfence as\n\
15145 lock addl $0x0, (%%{re}sp)\n"));
15146 fprintf (stream
, _("\
15147 -mrelax-relocations=[no|yes] "));
15148 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15149 fprintf (stream
, _("(default: yes)\n"));
15151 fprintf (stream
, _("(default: no)\n"));
15152 fprintf (stream
, _("\
15153 generate relax relocations\n"));
15154 fprintf (stream
, _("\
15155 -malign-branch-boundary=NUM (default: 0)\n\
15156 align branches within NUM byte boundary\n"));
15157 fprintf (stream
, _("\
15158 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15159 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15161 specify types of branches to align\n"));
15162 fprintf (stream
, _("\
15163 -malign-branch-prefix-size=NUM (default: 5)\n\
15164 align branches with NUM prefixes per instruction\n"));
15165 fprintf (stream
, _("\
15166 -mbranches-within-32B-boundaries\n\
15167 align branches within 32 byte boundary\n"));
15168 fprintf (stream
, _("\
15169 -mlfence-after-load=[no|yes] (default: no)\n\
15170 generate lfence after load\n"));
15171 fprintf (stream
, _("\
15172 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15173 generate lfence before indirect near branch\n"));
15174 fprintf (stream
, _("\
15175 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15176 generate lfence before ret\n"));
15177 fprintf (stream
, _("\
15178 -mamd64 accept only AMD64 ISA [default]\n"));
15179 fprintf (stream
, _("\
15180 -mintel64 accept only Intel64 ISA\n"));
15183 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15184 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15185 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15187 /* Pick the target format to use. */
15190 i386_target_format (void)
15192 if (startswith (default_arch
, "x86_64"))
15194 update_code_flag (CODE_64BIT
, 1);
15195 if (default_arch
[6] == '\0')
15196 x86_elf_abi
= X86_64_ABI
;
15198 x86_elf_abi
= X86_64_X32_ABI
;
15200 else if (!strcmp (default_arch
, "i386"))
15201 update_code_flag (CODE_32BIT
, 1);
15202 else if (!strcmp (default_arch
, "iamcu"))
15204 update_code_flag (CODE_32BIT
, 1);
15205 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15207 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15208 cpu_arch_name
= "iamcu";
15209 free (cpu_sub_arch_name
);
15210 cpu_sub_arch_name
= NULL
;
15211 cpu_arch_flags
= iamcu_flags
;
15212 cpu_arch_isa
= PROCESSOR_IAMCU
;
15213 cpu_arch_isa_flags
= iamcu_flags
;
15214 if (!cpu_arch_tune_set
)
15216 cpu_arch_tune
= cpu_arch_isa
;
15217 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
15220 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15221 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15225 as_fatal (_("unknown architecture"));
15227 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15228 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15229 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
15230 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15232 switch (OUTPUT_FLAVOR
)
15234 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15235 case bfd_target_aout_flavour
:
15236 return AOUT_TARGET_FORMAT
;
15238 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15239 # if defined (TE_PE) || defined (TE_PEP)
15240 case bfd_target_coff_flavour
:
15241 if (flag_code
== CODE_64BIT
)
15244 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15246 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15247 # elif defined (TE_GO32)
15248 case bfd_target_coff_flavour
:
15249 return "coff-go32";
15251 case bfd_target_coff_flavour
:
15252 return "coff-i386";
15255 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15256 case bfd_target_elf_flavour
:
15258 const char *format
;
15260 switch (x86_elf_abi
)
15263 format
= ELF_TARGET_FORMAT
;
15265 tls_get_addr
= "___tls_get_addr";
15269 use_rela_relocations
= 1;
15272 tls_get_addr
= "__tls_get_addr";
15274 format
= ELF_TARGET_FORMAT64
;
15276 case X86_64_X32_ABI
:
15277 use_rela_relocations
= 1;
15280 tls_get_addr
= "__tls_get_addr";
15282 disallow_64bit_reloc
= 1;
15283 format
= ELF_TARGET_FORMAT32
;
15286 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15288 if (x86_elf_abi
!= I386_ABI
)
15289 as_fatal (_("Intel MCU is 32bit only"));
15290 return ELF_TARGET_IAMCU_FORMAT
;
15296 #if defined (OBJ_MACH_O)
15297 case bfd_target_mach_o_flavour
:
15298 if (flag_code
== CODE_64BIT
)
15300 use_rela_relocations
= 1;
15302 return "mach-o-x86-64";
15305 return "mach-o-i386";
15313 #endif /* OBJ_MAYBE_ more than one */
15316 md_undefined_symbol (char *name
)
15318 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15319 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15320 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15321 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15325 if (symbol_find (name
))
15326 as_bad (_("GOT already in symbol table"));
15327 GOT_symbol
= symbol_new (name
, undefined_section
,
15328 &zero_address_frag
, 0);
15335 /* Round up a section size to the appropriate boundary. */
15338 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15340 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15341 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15343 /* For a.out, force the section size to be aligned. If we don't do
15344 this, BFD will align it for us, but it will not write out the
15345 final bytes of the section. This may be a bug in BFD, but it is
15346 easier to fix it here since that is how the other a.out targets
15350 align
= bfd_section_alignment (segment
);
15351 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15358 /* On the i386, PC-relative offsets are relative to the start of the
15359 next instruction. That is, the address of the offset, plus its
15360 size, since the offset is always the last part of the insn. */
15363 md_pcrel_from (fixS
*fixP
)
15365 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15371 s_bss (int ignore ATTRIBUTE_UNUSED
)
15375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15377 obj_elf_section_change_hook ();
15379 temp
= get_absolute_expression ();
15380 subseg_set (bss_section
, (subsegT
) temp
);
15381 demand_empty_rest_of_line ();
15386 /* Remember constant directive. */
15389 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15391 if (last_insn
.kind
!= last_insn_directive
15392 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15394 last_insn
.seg
= now_seg
;
15395 last_insn
.kind
= last_insn_directive
;
15396 last_insn
.name
= "constant directive";
15397 last_insn
.file
= as_where (&last_insn
.line
);
15398 if (lfence_before_ret
!= lfence_before_ret_none
)
15400 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15401 as_warn (_("constant directive skips -mlfence-before-ret "
15402 "and -mlfence-before-indirect-branch"));
15404 as_warn (_("constant directive skips -mlfence-before-ret"));
15406 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15407 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15412 i386_validate_fix (fixS
*fixp
)
15414 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15416 reloc_howto_type
*howto
;
15418 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15420 _("invalid %s relocation against register"),
15421 howto
? howto
->name
: "<unknown>");
15425 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15426 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15427 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15428 return IS_ELF
&& fixp
->fx_addsy
15429 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15430 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15433 if (fixp
->fx_subsy
)
15435 if (fixp
->fx_subsy
== GOT_symbol
)
15437 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15442 if (fixp
->fx_tcbit2
)
15443 fixp
->fx_r_type
= (fixp
->fx_tcbit
15444 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15445 : BFD_RELOC_X86_64_GOTPCRELX
);
15448 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15453 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15455 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15457 fixp
->fx_subsy
= 0;
15460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15463 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15464 to section. Since PLT32 relocation must be against symbols,
15465 turn such PLT32 relocation into PC32 relocation. */
15467 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15468 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15469 && symbol_section_p (fixp
->fx_addsy
))
15470 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15473 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15474 && fixp
->fx_tcbit2
)
15475 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15484 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15487 bfd_reloc_code_real_type code
;
15489 switch (fixp
->fx_r_type
)
15491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15494 case BFD_RELOC_SIZE32
:
15495 case BFD_RELOC_SIZE64
:
15497 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15498 && (!fixp
->fx_subsy
15499 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15500 sym
= fixp
->fx_addsy
;
15501 else if (fixp
->fx_subsy
15502 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15503 && (!fixp
->fx_addsy
15504 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15505 sym
= fixp
->fx_subsy
;
15508 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15510 /* Resolve size relocation against local symbol to size of
15511 the symbol plus addend. */
15512 valueT value
= S_GET_SIZE (sym
);
15514 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15515 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15516 if (sym
== fixp
->fx_subsy
)
15519 if (fixp
->fx_addsy
)
15520 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15522 else if (fixp
->fx_subsy
)
15523 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15524 value
+= fixp
->fx_offset
;
15525 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15527 && !fits_in_unsigned_long (value
))
15528 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15529 _("symbol size computation overflow"));
15530 fixp
->fx_addsy
= NULL
;
15531 fixp
->fx_subsy
= NULL
;
15532 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15535 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15537 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15538 "unsupported expression involving @size");
15542 /* Fall through. */
15544 case BFD_RELOC_X86_64_PLT32
:
15545 case BFD_RELOC_X86_64_GOT32
:
15546 case BFD_RELOC_X86_64_GOTPCREL
:
15547 case BFD_RELOC_X86_64_GOTPCRELX
:
15548 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15549 case BFD_RELOC_386_PLT32
:
15550 case BFD_RELOC_386_GOT32
:
15551 case BFD_RELOC_386_GOT32X
:
15552 case BFD_RELOC_386_GOTOFF
:
15553 case BFD_RELOC_386_GOTPC
:
15554 case BFD_RELOC_386_TLS_GD
:
15555 case BFD_RELOC_386_TLS_LDM
:
15556 case BFD_RELOC_386_TLS_LDO_32
:
15557 case BFD_RELOC_386_TLS_IE_32
:
15558 case BFD_RELOC_386_TLS_IE
:
15559 case BFD_RELOC_386_TLS_GOTIE
:
15560 case BFD_RELOC_386_TLS_LE_32
:
15561 case BFD_RELOC_386_TLS_LE
:
15562 case BFD_RELOC_386_TLS_GOTDESC
:
15563 case BFD_RELOC_386_TLS_DESC_CALL
:
15564 case BFD_RELOC_X86_64_TLSGD
:
15565 case BFD_RELOC_X86_64_TLSLD
:
15566 case BFD_RELOC_X86_64_DTPOFF32
:
15567 case BFD_RELOC_X86_64_DTPOFF64
:
15568 case BFD_RELOC_X86_64_GOTTPOFF
:
15569 case BFD_RELOC_X86_64_TPOFF32
:
15570 case BFD_RELOC_X86_64_TPOFF64
:
15571 case BFD_RELOC_X86_64_GOTOFF64
:
15572 case BFD_RELOC_X86_64_GOTPC32
:
15573 case BFD_RELOC_X86_64_GOT64
:
15574 case BFD_RELOC_X86_64_GOTPCREL64
:
15575 case BFD_RELOC_X86_64_GOTPC64
:
15576 case BFD_RELOC_X86_64_GOTPLT64
:
15577 case BFD_RELOC_X86_64_PLTOFF64
:
15578 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15579 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15580 case BFD_RELOC_RVA
:
15581 case BFD_RELOC_VTABLE_ENTRY
:
15582 case BFD_RELOC_VTABLE_INHERIT
:
15584 case BFD_RELOC_32_SECREL
:
15585 case BFD_RELOC_16_SECIDX
:
15587 code
= fixp
->fx_r_type
;
15589 case BFD_RELOC_X86_64_32S
:
15590 if (!fixp
->fx_pcrel
)
15592 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15593 code
= fixp
->fx_r_type
;
15596 /* Fall through. */
15598 if (fixp
->fx_pcrel
)
15600 switch (fixp
->fx_size
)
15603 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15604 _("can not do %d byte pc-relative relocation"),
15606 code
= BFD_RELOC_32_PCREL
;
15608 case 1: code
= BFD_RELOC_8_PCREL
; break;
15609 case 2: code
= BFD_RELOC_16_PCREL
; break;
15610 case 4: code
= BFD_RELOC_32_PCREL
; break;
15612 case 8: code
= BFD_RELOC_64_PCREL
; break;
15618 switch (fixp
->fx_size
)
15621 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15622 _("can not do %d byte relocation"),
15624 code
= BFD_RELOC_32
;
15626 case 1: code
= BFD_RELOC_8
; break;
15627 case 2: code
= BFD_RELOC_16
; break;
15628 case 4: code
= BFD_RELOC_32
; break;
15630 case 8: code
= BFD_RELOC_64
; break;
15637 if ((code
== BFD_RELOC_32
15638 || code
== BFD_RELOC_32_PCREL
15639 || code
== BFD_RELOC_X86_64_32S
)
15641 && fixp
->fx_addsy
== GOT_symbol
)
15644 code
= BFD_RELOC_386_GOTPC
;
15646 code
= BFD_RELOC_X86_64_GOTPC32
;
15648 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15650 && fixp
->fx_addsy
== GOT_symbol
)
15652 code
= BFD_RELOC_X86_64_GOTPC64
;
15655 rel
= XNEW (arelent
);
15656 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15657 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15659 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15661 if (!use_rela_relocations
)
15663 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15664 vtable entry to be used in the relocation's section offset. */
15665 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15666 rel
->address
= fixp
->fx_offset
;
15667 #if defined (OBJ_COFF) && defined (TE_PE)
15668 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15669 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15674 /* Use the rela in 64bit mode. */
15677 if (disallow_64bit_reloc
)
15680 case BFD_RELOC_X86_64_DTPOFF64
:
15681 case BFD_RELOC_X86_64_TPOFF64
:
15682 case BFD_RELOC_64_PCREL
:
15683 case BFD_RELOC_X86_64_GOTOFF64
:
15684 case BFD_RELOC_X86_64_GOT64
:
15685 case BFD_RELOC_X86_64_GOTPCREL64
:
15686 case BFD_RELOC_X86_64_GOTPC64
:
15687 case BFD_RELOC_X86_64_GOTPLT64
:
15688 case BFD_RELOC_X86_64_PLTOFF64
:
15689 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15690 _("cannot represent relocation type %s in x32 mode"),
15691 bfd_get_reloc_code_name (code
));
15697 if (!fixp
->fx_pcrel
)
15698 rel
->addend
= fixp
->fx_offset
;
15702 case BFD_RELOC_X86_64_PLT32
:
15703 case BFD_RELOC_X86_64_GOT32
:
15704 case BFD_RELOC_X86_64_GOTPCREL
:
15705 case BFD_RELOC_X86_64_GOTPCRELX
:
15706 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15707 case BFD_RELOC_X86_64_TLSGD
:
15708 case BFD_RELOC_X86_64_TLSLD
:
15709 case BFD_RELOC_X86_64_GOTTPOFF
:
15710 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15711 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15712 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15715 rel
->addend
= (section
->vma
15717 + fixp
->fx_addnumber
15718 + md_pcrel_from (fixp
));
15723 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15724 if (rel
->howto
== NULL
)
15726 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15727 _("cannot represent relocation type %s"),
15728 bfd_get_reloc_code_name (code
));
15729 /* Set howto to a garbage value so that we can keep going. */
15730 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15731 gas_assert (rel
->howto
!= NULL
);
15737 #include "tc-i386-intel.c"
15740 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15742 int saved_naked_reg
;
15743 char saved_register_dot
;
15745 saved_naked_reg
= allow_naked_reg
;
15746 allow_naked_reg
= 1;
15747 saved_register_dot
= register_chars
['.'];
15748 register_chars
['.'] = '.';
15749 allow_pseudo_reg
= 1;
15750 expression_and_evaluate (exp
);
15751 allow_pseudo_reg
= 0;
15752 register_chars
['.'] = saved_register_dot
;
15753 allow_naked_reg
= saved_naked_reg
;
15755 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15757 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15759 exp
->X_op
= O_constant
;
15760 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15761 .dw2_regnum
[flag_code
>> 1];
15764 exp
->X_op
= O_illegal
;
15769 tc_x86_frame_initial_instructions (void)
15771 static unsigned int sp_regno
[2];
15773 if (!sp_regno
[flag_code
>> 1])
15775 char *saved_input
= input_line_pointer
;
15776 char sp
[][4] = {"esp", "rsp"};
15779 input_line_pointer
= sp
[flag_code
>> 1];
15780 tc_x86_parse_to_dw2regnum (&exp
);
15781 gas_assert (exp
.X_op
== O_constant
);
15782 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15783 input_line_pointer
= saved_input
;
15786 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15787 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15791 x86_dwarf2_addr_size (void)
15793 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15794 if (x86_elf_abi
== X86_64_X32_ABI
)
15797 return bfd_arch_bits_per_address (stdoutput
) / 8;
15801 i386_elf_section_type (const char *str
, size_t len
)
15803 if (flag_code
== CODE_64BIT
15804 && len
== sizeof ("unwind") - 1
15805 && startswith (str
, "unwind"))
15806 return SHT_X86_64_UNWIND
;
15813 i386_solaris_fix_up_eh_frame (segT sec
)
15815 if (flag_code
== CODE_64BIT
)
15816 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15822 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15826 exp
.X_op
= O_secrel
;
15827 exp
.X_add_symbol
= symbol
;
15828 exp
.X_add_number
= 0;
15829 emit_expr (&exp
, size
);
15833 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15834 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15837 x86_64_section_letter (int letter
, const char **ptr_msg
)
15839 if (flag_code
== CODE_64BIT
)
15842 return SHF_X86_64_LARGE
;
15844 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15847 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15852 handle_large_common (int small ATTRIBUTE_UNUSED
)
15854 if (flag_code
!= CODE_64BIT
)
15856 s_comm_internal (0, elf_common_parse
);
15857 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15861 static segT lbss_section
;
15862 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15863 asection
*saved_bss_section
= bss_section
;
15865 if (lbss_section
== NULL
)
15867 flagword applicable
;
15868 segT seg
= now_seg
;
15869 subsegT subseg
= now_subseg
;
15871 /* The .lbss section is for local .largecomm symbols. */
15872 lbss_section
= subseg_new (".lbss", 0);
15873 applicable
= bfd_applicable_section_flags (stdoutput
);
15874 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15875 seg_info (lbss_section
)->bss
= 1;
15877 subseg_set (seg
, subseg
);
15880 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15881 bss_section
= lbss_section
;
15883 s_comm_internal (0, elf_common_parse
);
15885 elf_com_section_ptr
= saved_com_section_ptr
;
15886 bss_section
= saved_bss_section
;
15889 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */