1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
70 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
73 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
75 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
76 static int smallest_imm_type
PARAMS ((offsetT
));
77 static offsetT offset_in_range
PARAMS ((offsetT
, int));
78 static int add_prefix
PARAMS ((unsigned int));
79 static void set_code_flag
PARAMS ((int));
80 static void set_16bit_gcc_code_flag
PARAMS ((int));
81 static void set_intel_syntax
PARAMS ((int));
82 static void set_cpu_arch
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 RELOC_ENUM reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
187 const char extra_symbol_chars
[] = "*%-(@[";
189 const char extra_symbol_chars
[] = "*%-([";
192 #if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
197 /* This array holds the chars that always start a comment. If the
198 pre-processor is disabled, these aren't very useful. */
199 const char comment_chars
[] = "#/";
200 #define PREFIX_SEPARATOR '\\'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "";
213 /* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215 const char comment_chars
[] = "#";
216 #define PREFIX_SEPARATOR '/'
218 const char line_comment_chars
[] = "/";
221 const char line_separator_chars
[] = ";";
223 /* Chars that can be used to separate mant from exp in floating point
225 const char EXP_CHARS
[] = "eE";
227 /* Chars that mean this number is a floating point constant
230 const char FLT_CHARS
[] = "fFdDxX";
232 /* Tables for lexical analysis. */
233 static char mnemonic_chars
[256];
234 static char register_chars
[256];
235 static char operand_chars
[256];
236 static char identifier_chars
[256];
237 static char digit_chars
[256];
239 /* Lexical macros. */
240 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241 #define is_operand_char(x) (operand_chars[(unsigned char) x])
242 #define is_register_char(x) (register_chars[(unsigned char) x])
243 #define is_space_char(x) ((x) == ' ')
244 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245 #define is_digit_char(x) (digit_chars[(unsigned char) x])
247 /* All non-digit non-letter charcters that may occur in an operand. */
248 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
250 /* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
253 assembler instruction). */
254 static char save_stack
[32];
255 static char *save_stack_p
;
256 #define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258 #define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
261 /* The instruction we're assembling. */
264 /* Possible templates for current insn. */
265 static const templates
*current_templates
;
267 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
268 static expressionS disp_expressions
[2], im_expressions
[2];
270 /* Current operand we are working on. */
271 static int this_operand
;
273 /* We support four different modes. FLAG_CODE variable is used to distinguish
280 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
282 static enum flag_code flag_code
;
283 static int use_rela_relocations
= 0;
285 /* The names used to print error messages. */
286 static const char *flag_code_names
[] =
293 /* 1 for intel syntax,
295 static int intel_syntax
= 0;
297 /* 1 if register prefix % not required. */
298 static int allow_naked_reg
= 0;
300 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303 static char stackop_size
= '\0';
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings
= 0;
309 static const char *cpu_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316 static unsigned int no_cond_jump_promotion
= 0;
318 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
321 /* Interface to relax_segment.
322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
327 #define UNCOND_JUMP 0
329 #define COND_JUMP86 2
334 #define SMALL16 (SMALL | CODE16)
336 #define BIG16 (BIG | CODE16)
340 #define INLINE __inline__
346 #define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348 #define TYPE_FROM_RELAX_STATE(s) \
350 #define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
353 /* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
361 const relax_typeS md_relax_table
[] =
364 1) most positive reach of this state,
365 2) most negative reach of this state,
366 3) how many bytes this mode will have in the variable part of the frag
367 4) which index into the table to try if we can't fit into this one. */
369 /* UNCOND_JUMP states. */
370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
385 /* word conditionals add 3 bytes to frag:
386 1 extra opcode byte, 2 displacement bytes. */
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
400 static const arch_entry cpu_arch
[] = {
402 {"i186", Cpu086
|Cpu186
},
403 {"i286", Cpu086
|Cpu186
|Cpu286
},
404 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
405 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
406 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
407 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
408 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
409 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
410 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
411 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
412 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
413 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
417 const pseudo_typeS md_pseudo_table
[] =
419 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes
, 0},
422 {"align", s_align_ptwo
, 0},
424 {"arch", set_cpu_arch
, 0},
428 {"ffloat", float_cons
, 'f'},
429 {"dfloat", float_cons
, 'd'},
430 {"tfloat", float_cons
, 'x'},
432 {"noopt", s_ignore
, 0},
433 {"optim", s_ignore
, 0},
434 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
435 {"code16", set_code_flag
, CODE_16BIT
},
436 {"code32", set_code_flag
, CODE_32BIT
},
437 {"code64", set_code_flag
, CODE_64BIT
},
438 {"intel_syntax", set_intel_syntax
, 1},
439 {"att_syntax", set_intel_syntax
, 0},
440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
441 {"loc", dwarf2_directive_loc
, 0},
445 /* For interface with expression (). */
446 extern char *input_line_pointer
;
448 /* Hash table for instruction mnemonic lookup. */
449 static struct hash_control
*op_hash
;
451 /* Hash table for register lookup. */
452 static struct hash_control
*reg_hash
;
455 i386_align_code (fragP
, count
)
459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
462 static const char f32_1
[] =
464 static const char f32_2
[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3
[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4
[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5
[] =
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6
[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7
[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8
[] =
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9
[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10
[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11
[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12
[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13
[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14
[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15
[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
501 static const char f16_3
[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
503 static const char f16_4
[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5
[] =
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6
[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7
[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8
[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt
[] = {
518 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
519 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
521 static const char *const f16_patt
[] = {
522 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
523 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
526 if (count
<= 0 || count
> 15)
529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code
== CODE_64BIT
)
534 int nnops
= (count
+ 3) / 4;
535 int len
= count
/ nnops
;
536 int remains
= count
- nnops
* len
;
539 for (i
= 0; i
< remains
; i
++)
541 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
542 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
545 for (; i
< nnops
; i
++)
547 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
548 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
553 if (flag_code
== CODE_16BIT
)
555 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
556 f16_patt
[count
- 1], count
);
558 /* Adjust jump offset. */
559 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
562 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
563 f32_patt
[count
- 1], count
);
564 fragP
->fr_var
= count
;
567 static INLINE
unsigned int
568 mode_from_disp_size (t
)
571 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
575 fits_in_signed_byte (num
)
578 return (num
>= -128) && (num
<= 127);
582 fits_in_unsigned_byte (num
)
585 return (num
& 0xff) == num
;
589 fits_in_unsigned_word (num
)
592 return (num
& 0xffff) == num
;
596 fits_in_signed_word (num
)
599 return (-32768 <= num
) && (num
<= 32767);
602 fits_in_signed_long (num
)
603 offsetT num ATTRIBUTE_UNUSED
;
608 return (!(((offsetT
) -1 << 31) & num
)
609 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
611 } /* fits_in_signed_long() */
613 fits_in_unsigned_long (num
)
614 offsetT num ATTRIBUTE_UNUSED
;
619 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
621 } /* fits_in_unsigned_long() */
624 smallest_imm_type (num
)
627 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
635 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
637 return (fits_in_signed_byte (num
)
638 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
639 : fits_in_unsigned_byte (num
)
640 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
641 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
642 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
643 : fits_in_signed_long (num
)
644 ? (Imm32
| Imm32S
| Imm64
)
645 : fits_in_unsigned_long (num
)
651 offset_in_range (val
, size
)
659 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
660 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
661 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
663 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
668 /* If BFD64, sign extend val. */
669 if (!use_rela_relocations
)
670 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
671 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
673 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
675 char buf1
[40], buf2
[40];
677 sprint_value (buf1
, val
);
678 sprint_value (buf2
, val
& mask
);
679 as_warn (_("%s shortened to %s"), buf1
, buf2
);
684 /* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
694 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
695 && flag_code
== CODE_64BIT
)
703 case CS_PREFIX_OPCODE
:
704 case DS_PREFIX_OPCODE
:
705 case ES_PREFIX_OPCODE
:
706 case FS_PREFIX_OPCODE
:
707 case GS_PREFIX_OPCODE
:
708 case SS_PREFIX_OPCODE
:
712 case REPNE_PREFIX_OPCODE
:
713 case REPE_PREFIX_OPCODE
:
716 case LOCK_PREFIX_OPCODE
:
724 case ADDR_PREFIX_OPCODE
:
728 case DATA_PREFIX_OPCODE
:
733 if (i
.prefix
[q
] != 0)
735 as_bad (_("same type of prefix used twice"));
740 i
.prefix
[q
] = prefix
;
745 set_code_flag (value
)
749 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
750 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
751 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
753 as_bad (_("64bit mode not supported on this CPU."));
755 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
757 as_bad (_("32bit mode not supported on this CPU."));
763 set_16bit_gcc_code_flag (new_code_flag
)
766 flag_code
= new_code_flag
;
767 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
768 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
773 set_intel_syntax (syntax_flag
)
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg
= 0;
780 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
782 char *string
= input_line_pointer
;
783 int e
= get_symbol_end ();
785 if (strcmp (string
, "prefix") == 0)
787 else if (strcmp (string
, "noprefix") == 0)
790 as_bad (_("bad argument to syntax directive."));
791 *input_line_pointer
= e
;
793 demand_empty_rest_of_line ();
795 intel_syntax
= syntax_flag
;
797 if (ask_naked_reg
== 0)
800 allow_naked_reg
= (intel_syntax
801 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
803 /* Conservative default. */
808 allow_naked_reg
= (ask_naked_reg
< 0);
813 int dummy ATTRIBUTE_UNUSED
;
817 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
819 char *string
= input_line_pointer
;
820 int e
= get_symbol_end ();
823 for (i
= 0; cpu_arch
[i
].name
; i
++)
825 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
827 cpu_arch_name
= cpu_arch
[i
].name
;
828 cpu_arch_flags
= (cpu_arch
[i
].flags
829 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
833 if (!cpu_arch
[i
].name
)
834 as_bad (_("no such architecture: `%s'"), string
);
836 *input_line_pointer
= e
;
839 as_bad (_("missing cpu architecture"));
841 no_cond_jump_promotion
= 0;
842 if (*input_line_pointer
== ','
843 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
845 char *string
= ++input_line_pointer
;
846 int e
= get_symbol_end ();
848 if (strcmp (string
, "nojumps") == 0)
849 no_cond_jump_promotion
= 1;
850 else if (strcmp (string
, "jumps") == 0)
853 as_bad (_("no such architecture modifier: `%s'"), string
);
855 *input_line_pointer
= e
;
858 demand_empty_rest_of_line ();
865 if (!strcmp (default_arch
, "x86_64"))
866 return bfd_mach_x86_64
;
867 else if (!strcmp (default_arch
, "i386"))
868 return bfd_mach_i386_i386
;
870 as_fatal (_("Unknown architecture"));
877 const char *hash_err
;
879 /* Initialize op_hash hash table. */
880 op_hash
= hash_new ();
883 const template *optab
;
884 templates
*core_optab
;
886 /* Setup for loop. */
888 core_optab
= (templates
*) xmalloc (sizeof (templates
));
889 core_optab
->start
= optab
;
894 if (optab
->name
== NULL
895 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
897 /* different name --> ship out current template list;
898 add to hash table; & begin anew. */
899 core_optab
->end
= optab
;
900 hash_err
= hash_insert (op_hash
,
905 as_fatal (_("Internal Error: Can't hash %s: %s"),
909 if (optab
->name
== NULL
)
911 core_optab
= (templates
*) xmalloc (sizeof (templates
));
912 core_optab
->start
= optab
;
917 /* Initialize reg_hash hash table. */
918 reg_hash
= hash_new ();
920 const reg_entry
*regtab
;
922 for (regtab
= i386_regtab
;
923 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
926 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
928 as_fatal (_("Internal Error: Can't hash %s: %s"),
934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
939 for (c
= 0; c
< 256; c
++)
944 mnemonic_chars
[c
] = c
;
945 register_chars
[c
] = c
;
946 operand_chars
[c
] = c
;
948 else if (ISLOWER (c
))
950 mnemonic_chars
[c
] = c
;
951 register_chars
[c
] = c
;
952 operand_chars
[c
] = c
;
954 else if (ISUPPER (c
))
956 mnemonic_chars
[c
] = TOLOWER (c
);
957 register_chars
[c
] = mnemonic_chars
[c
];
958 operand_chars
[c
] = c
;
961 if (ISALPHA (c
) || ISDIGIT (c
))
962 identifier_chars
[c
] = c
;
965 identifier_chars
[c
] = c
;
966 operand_chars
[c
] = c
;
971 identifier_chars
['@'] = '@';
973 digit_chars
['-'] = '-';
974 identifier_chars
['_'] = '_';
975 identifier_chars
['.'] = '.';
977 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
978 operand_chars
[(unsigned char) *p
] = *p
;
981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
984 record_alignment (text_section
, 2);
985 record_alignment (data_section
, 2);
986 record_alignment (bss_section
, 2);
992 i386_print_statistics (file
)
995 hash_print_statistics (file
, "i386 opcode", op_hash
);
996 hash_print_statistics (file
, "i386 register", reg_hash
);
1001 /* Debugging routines for md_assemble. */
1002 static void pi
PARAMS ((char *, i386_insn
*));
1003 static void pte
PARAMS ((template *));
1004 static void pt
PARAMS ((unsigned int));
1005 static void pe
PARAMS ((expressionS
*));
1006 static void ps
PARAMS ((symbolS
*));
1015 fprintf (stdout
, "%s: template ", line
);
1017 fprintf (stdout
, " address: base %s index %s scale %x\n",
1018 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1019 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1020 x
->log2_scale_factor
);
1021 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1022 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1023 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1024 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1025 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1026 (x
->rex
& REX_MODE64
) != 0,
1027 (x
->rex
& REX_EXTX
) != 0,
1028 (x
->rex
& REX_EXTY
) != 0,
1029 (x
->rex
& REX_EXTZ
) != 0);
1030 for (i
= 0; i
< x
->operands
; i
++)
1032 fprintf (stdout
, " #%d: ", i
+ 1);
1034 fprintf (stdout
, "\n");
1036 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1037 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1038 if (x
->types
[i
] & Imm
)
1040 if (x
->types
[i
] & Disp
)
1041 pe (x
->op
[i
].disps
);
1050 fprintf (stdout
, " %d operands ", t
->operands
);
1051 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1052 if (t
->extension_opcode
!= None
)
1053 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1054 if (t
->opcode_modifier
& D
)
1055 fprintf (stdout
, "D");
1056 if (t
->opcode_modifier
& W
)
1057 fprintf (stdout
, "W");
1058 fprintf (stdout
, "\n");
1059 for (i
= 0; i
< t
->operands
; i
++)
1061 fprintf (stdout
, " #%d type ", i
+ 1);
1062 pt (t
->operand_types
[i
]);
1063 fprintf (stdout
, "\n");
1071 fprintf (stdout
, " operation %d\n", e
->X_op
);
1072 fprintf (stdout
, " add_number %ld (%lx)\n",
1073 (long) e
->X_add_number
, (long) e
->X_add_number
);
1074 if (e
->X_add_symbol
)
1076 fprintf (stdout
, " add_symbol ");
1077 ps (e
->X_add_symbol
);
1078 fprintf (stdout
, "\n");
1082 fprintf (stdout
, " op_symbol ");
1083 ps (e
->X_op_symbol
);
1084 fprintf (stdout
, "\n");
1092 fprintf (stdout
, "%s type %s%s",
1094 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s
)));
1104 static const type_names
[] =
1117 { BaseIndex
, "BaseIndex" },
1121 { Disp32S
, "d32s" },
1123 { InOutPortReg
, "InOutPortReg" },
1124 { ShiftCount
, "ShiftCount" },
1125 { Control
, "control reg" },
1126 { Test
, "test reg" },
1127 { Debug
, "debug reg" },
1128 { FloatReg
, "FReg" },
1129 { FloatAcc
, "FAcc" },
1133 { JumpAbsolute
, "Jump Absolute" },
1144 const struct type_name
*ty
;
1146 for (ty
= type_names
; ty
->mask
; ty
++)
1148 fprintf (stdout
, "%s, ", ty
->tname
);
1152 #endif /* DEBUG386 */
1154 #ifdef BFD_ASSEMBLER
1155 static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1158 static bfd_reloc_code_real_type
1159 reloc (size
, pcrel
, sign
, other
)
1163 bfd_reloc_code_real_type other
;
1165 if (other
!= NO_RELOC
)
1171 as_bad (_("There are no unsigned pc-relative relocations"));
1174 case 1: return BFD_RELOC_8_PCREL
;
1175 case 2: return BFD_RELOC_16_PCREL
;
1176 case 4: return BFD_RELOC_32_PCREL
;
1178 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1185 case 4: return BFD_RELOC_X86_64_32S
;
1190 case 1: return BFD_RELOC_8
;
1191 case 2: return BFD_RELOC_16
;
1192 case 4: return BFD_RELOC_32
;
1193 case 8: return BFD_RELOC_64
;
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign
? "signed" : "unsigned", size
);
1200 return BFD_RELOC_NONE
;
1203 /* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1209 tc_i386_fix_adjustable (fixP
)
1210 fixS
*fixP ATTRIBUTE_UNUSED
;
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1223 /* adjust_reloc_syms doesn't know about the GOT. */
1224 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1225 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1226 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1238 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1239 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1245 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1246 #define BFD_RELOC_8 0
1247 #define BFD_RELOC_16 0
1248 #define BFD_RELOC_32 0
1249 #define BFD_RELOC_8_PCREL 0
1250 #define BFD_RELOC_16_PCREL 0
1251 #define BFD_RELOC_32_PCREL 0
1252 #define BFD_RELOC_386_PLT32 0
1253 #define BFD_RELOC_386_GOT32 0
1254 #define BFD_RELOC_386_GOTOFF 0
1255 #define BFD_RELOC_386_TLS_GD 0
1256 #define BFD_RELOC_386_TLS_LDM 0
1257 #define BFD_RELOC_386_TLS_LDO_32 0
1258 #define BFD_RELOC_386_TLS_IE_32 0
1259 #define BFD_RELOC_386_TLS_IE 0
1260 #define BFD_RELOC_386_TLS_GOTIE 0
1261 #define BFD_RELOC_386_TLS_LE_32 0
1262 #define BFD_RELOC_386_TLS_LE 0
1263 #define BFD_RELOC_X86_64_PLT32 0
1264 #define BFD_RELOC_X86_64_GOT32 0
1265 #define BFD_RELOC_X86_64_GOTPCREL 0
1268 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1271 intel_float_operand (mnemonic
)
1272 const char *mnemonic
;
1274 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1277 if (mnemonic
[0] == 'f')
1283 /* This is the guts of the machine-dependent assembler. LINE points to a
1284 machine dependent instruction. This function is supposed to emit
1285 the frags/bytes it assembles to. */
1292 char mnemonic
[MAX_MNEM_SIZE
];
1294 /* Initialize globals. */
1295 memset (&i
, '\0', sizeof (i
));
1296 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1297 i
.reloc
[j
] = NO_RELOC
;
1298 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1299 memset (im_expressions
, '\0', sizeof (im_expressions
));
1300 save_stack_p
= save_stack
;
1302 /* First parse an instruction mnemonic & call i386_operand for the operands.
1303 We assume that the scrubber has arranged it so that line[0] is the valid
1304 start of a (possibly prefixed) mnemonic. */
1306 line
= parse_insn (line
, mnemonic
);
1310 line
= parse_operands (line
, mnemonic
);
1314 /* Now we've parsed the mnemonic into a set of templates, and have the
1315 operands at hand. */
1317 /* All intel opcodes have reversed operands except for "bound" and
1318 "enter". We also don't reverse intersegment "jmp" and "call"
1319 instructions with 2 immediate operands so that the immediate segment
1320 precedes the offset, as it does when in AT&T mode. "enter" and the
1321 intersegment "jmp" and "call" instructions are the only ones that
1322 have two immediate operands. */
1323 if (intel_syntax
&& i
.operands
> 1
1324 && (strcmp (mnemonic
, "bound") != 0)
1325 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1331 if (i
.disp_operands
)
1334 /* Next, we find a template that matches the given insn,
1335 making sure the overlap of the given operands types is consistent
1336 with the template operand types. */
1338 if (!match_template ())
1343 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1345 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1346 i
.tm
.base_opcode
^= FloatR
;
1348 /* Zap movzx and movsx suffix. The suffix may have been set from
1349 "word ptr" or "byte ptr" on the source operand, but we'll use
1350 the suffix later to choose the destination register. */
1351 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1355 if (i
.tm
.opcode_modifier
& FWait
)
1356 if (!add_prefix (FWAIT_OPCODE
))
1359 /* Check string instruction segment overrides. */
1360 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1362 if (!check_string ())
1366 if (!process_suffix ())
1369 /* Make still unresolved immediate matches conform to size of immediate
1370 given in i.suffix. */
1371 if (!finalize_imm ())
1374 if (i
.types
[0] & Imm1
)
1375 i
.imm_operands
= 0; /* kludge for shift insns. */
1376 if (i
.types
[0] & ImplicitRegister
)
1378 if (i
.types
[1] & ImplicitRegister
)
1380 if (i
.types
[2] & ImplicitRegister
)
1383 if (i
.tm
.opcode_modifier
& ImmExt
)
1385 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1386 opcode suffix which is coded in the same place as an 8-bit
1387 immediate field would be. Here we fake an 8-bit immediate
1388 operand from the opcode suffix stored in tm.extension_opcode. */
1392 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1394 exp
= &im_expressions
[i
.imm_operands
++];
1395 i
.op
[i
.operands
].imms
= exp
;
1396 i
.types
[i
.operands
++] = Imm8
;
1397 exp
->X_op
= O_constant
;
1398 exp
->X_add_number
= i
.tm
.extension_opcode
;
1399 i
.tm
.extension_opcode
= None
;
1402 /* For insns with operands there are more diddles to do to the opcode. */
1405 if (!process_operands ())
1408 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1410 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1411 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1414 /* Handle conversion of 'int $3' --> special int3 insn. */
1415 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1417 i
.tm
.base_opcode
= INT3_OPCODE
;
1421 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1422 && i
.op
[0].disps
->X_op
== O_constant
)
1424 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1425 the absolute address given by the constant. Since ix86 jumps and
1426 calls are pc relative, we need to generate a reloc. */
1427 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1428 i
.op
[0].disps
->X_op
= O_symbol
;
1431 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1432 i
.rex
|= REX_MODE64
;
1434 /* For 8 bit registers we need an empty rex prefix. Also if the
1435 instruction already has a prefix, we need to convert old
1436 registers to new ones. */
1438 if (((i
.types
[0] & Reg8
) != 0
1439 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1440 || ((i
.types
[1] & Reg8
) != 0
1441 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1442 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1447 i
.rex
|= REX_OPCODE
;
1448 for (x
= 0; x
< 2; x
++)
1450 /* Look for 8 bit operand that uses old registers. */
1451 if ((i
.types
[x
] & Reg8
) != 0
1452 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1454 /* In case it is "hi" register, give up. */
1455 if (i
.op
[x
].regs
->reg_num
> 3)
1456 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1457 i
.op
[x
].regs
->reg_name
);
1459 /* Otherwise it is equivalent to the extended register.
1460 Since the encoding doesn't change this is merely
1461 cosmetic cleanup for debug output. */
1463 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1469 add_prefix (REX_OPCODE
| i
.rex
);
1471 /* We are ready to output the insn. */
1476 parse_insn (line
, mnemonic
)
1481 char *token_start
= l
;
1484 /* Non-zero if we found a prefix only acceptable with string insns. */
1485 const char *expecting_string_instruction
= NULL
;
1490 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1493 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1495 as_bad (_("no such instruction: `%s'"), token_start
);
1500 if (!is_space_char (*l
)
1501 && *l
!= END_OF_INSN
1502 && *l
!= PREFIX_SEPARATOR
1505 as_bad (_("invalid character %s in mnemonic"),
1506 output_invalid (*l
));
1509 if (token_start
== l
)
1511 if (*l
== PREFIX_SEPARATOR
)
1512 as_bad (_("expecting prefix; got nothing"));
1514 as_bad (_("expecting mnemonic; got nothing"));
1518 /* Look up instruction (or prefix) via hash table. */
1519 current_templates
= hash_find (op_hash
, mnemonic
);
1521 if (*l
!= END_OF_INSN
1522 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1523 && current_templates
1524 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1526 /* If we are in 16-bit mode, do not allow addr16 or data16.
1527 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1528 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1529 && flag_code
!= CODE_64BIT
1530 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1531 ^ (flag_code
== CODE_16BIT
)))
1533 as_bad (_("redundant %s prefix"),
1534 current_templates
->start
->name
);
1537 /* Add prefix, checking for repeated prefixes. */
1538 switch (add_prefix (current_templates
->start
->base_opcode
))
1543 expecting_string_instruction
= current_templates
->start
->name
;
1546 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1553 if (!current_templates
)
1555 /* See if we can get a match by trimming off a suffix. */
1558 case WORD_MNEM_SUFFIX
:
1559 case BYTE_MNEM_SUFFIX
:
1560 case QWORD_MNEM_SUFFIX
:
1561 i
.suffix
= mnem_p
[-1];
1563 current_templates
= hash_find (op_hash
, mnemonic
);
1565 case SHORT_MNEM_SUFFIX
:
1566 case LONG_MNEM_SUFFIX
:
1569 i
.suffix
= mnem_p
[-1];
1571 current_templates
= hash_find (op_hash
, mnemonic
);
1579 if (intel_float_operand (mnemonic
))
1580 i
.suffix
= SHORT_MNEM_SUFFIX
;
1582 i
.suffix
= LONG_MNEM_SUFFIX
;
1584 current_templates
= hash_find (op_hash
, mnemonic
);
1588 if (!current_templates
)
1590 as_bad (_("no such instruction: `%s'"), token_start
);
1595 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1597 /* Check for a branch hint. We allow ",pt" and ",pn" for
1598 predict taken and predict not taken respectively.
1599 I'm not sure that branch hints actually do anything on loop
1600 and jcxz insns (JumpByte) for current Pentium4 chips. They
1601 may work in the future and it doesn't hurt to accept them
1603 if (l
[0] == ',' && l
[1] == 'p')
1607 if (!add_prefix (DS_PREFIX_OPCODE
))
1611 else if (l
[2] == 'n')
1613 if (!add_prefix (CS_PREFIX_OPCODE
))
1619 /* Any other comma loses. */
1622 as_bad (_("invalid character %s in mnemonic"),
1623 output_invalid (*l
));
1627 /* Check if instruction is supported on specified architecture. */
1628 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1629 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1631 as_warn (_("`%s' is not supported on `%s'"),
1632 current_templates
->start
->name
, cpu_arch_name
);
1634 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1636 as_warn (_("use .code16 to ensure correct addressing mode"));
1639 /* Check for rep/repne without a string instruction. */
1640 if (expecting_string_instruction
1641 && !(current_templates
->start
->opcode_modifier
& IsString
))
1643 as_bad (_("expecting string instruction after `%s'"),
1644 expecting_string_instruction
);
1652 parse_operands (l
, mnemonic
)
1654 const char *mnemonic
;
1658 /* 1 if operand is pending after ','. */
1659 unsigned int expecting_operand
= 0;
1661 /* Non-zero if operand parens not balanced. */
1662 unsigned int paren_not_balanced
;
1664 while (*l
!= END_OF_INSN
)
1666 /* Skip optional white space before operand. */
1667 if (is_space_char (*l
))
1669 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1671 as_bad (_("invalid character %s before operand %d"),
1672 output_invalid (*l
),
1676 token_start
= l
; /* after white space */
1677 paren_not_balanced
= 0;
1678 while (paren_not_balanced
|| *l
!= ',')
1680 if (*l
== END_OF_INSN
)
1682 if (paren_not_balanced
)
1685 as_bad (_("unbalanced parenthesis in operand %d."),
1688 as_bad (_("unbalanced brackets in operand %d."),
1693 break; /* we are done */
1695 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1697 as_bad (_("invalid character %s in operand %d"),
1698 output_invalid (*l
),
1705 ++paren_not_balanced
;
1707 --paren_not_balanced
;
1712 ++paren_not_balanced
;
1714 --paren_not_balanced
;
1718 if (l
!= token_start
)
1719 { /* Yes, we've read in another operand. */
1720 unsigned int operand_ok
;
1721 this_operand
= i
.operands
++;
1722 if (i
.operands
> MAX_OPERANDS
)
1724 as_bad (_("spurious operands; (%d operands/instruction max)"),
1728 /* Now parse operand adding info to 'i' as we go along. */
1729 END_STRING_AND_SAVE (l
);
1733 i386_intel_operand (token_start
,
1734 intel_float_operand (mnemonic
));
1736 operand_ok
= i386_operand (token_start
);
1738 RESTORE_END_STRING (l
);
1744 if (expecting_operand
)
1746 expecting_operand_after_comma
:
1747 as_bad (_("expecting operand after ','; got nothing"));
1752 as_bad (_("expecting operand before ','; got nothing"));
1757 /* Now *l must be either ',' or END_OF_INSN. */
1760 if (*++l
== END_OF_INSN
)
1762 /* Just skip it, if it's \n complain. */
1763 goto expecting_operand_after_comma
;
1765 expecting_operand
= 1;
1774 union i386_op temp_op
;
1775 unsigned int temp_type
;
1776 RELOC_ENUM temp_reloc
;
1780 if (i
.operands
== 2)
1785 else if (i
.operands
== 3)
1790 temp_type
= i
.types
[xchg2
];
1791 i
.types
[xchg2
] = i
.types
[xchg1
];
1792 i
.types
[xchg1
] = temp_type
;
1793 temp_op
= i
.op
[xchg2
];
1794 i
.op
[xchg2
] = i
.op
[xchg1
];
1795 i
.op
[xchg1
] = temp_op
;
1796 temp_reloc
= i
.reloc
[xchg2
];
1797 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1798 i
.reloc
[xchg1
] = temp_reloc
;
1800 if (i
.mem_operands
== 2)
1802 const seg_entry
*temp_seg
;
1803 temp_seg
= i
.seg
[0];
1804 i
.seg
[0] = i
.seg
[1];
1805 i
.seg
[1] = temp_seg
;
1809 /* Try to ensure constant immediates are represented in the smallest
1814 char guess_suffix
= 0;
1818 guess_suffix
= i
.suffix
;
1819 else if (i
.reg_operands
)
1821 /* Figure out a suffix from the last register operand specified.
1822 We can't do this properly yet, ie. excluding InOutPortReg,
1823 but the following works for instructions with immediates.
1824 In any case, we can't set i.suffix yet. */
1825 for (op
= i
.operands
; --op
>= 0;)
1826 if (i
.types
[op
] & Reg
)
1828 if (i
.types
[op
] & Reg8
)
1829 guess_suffix
= BYTE_MNEM_SUFFIX
;
1830 else if (i
.types
[op
] & Reg16
)
1831 guess_suffix
= WORD_MNEM_SUFFIX
;
1832 else if (i
.types
[op
] & Reg32
)
1833 guess_suffix
= LONG_MNEM_SUFFIX
;
1834 else if (i
.types
[op
] & Reg64
)
1835 guess_suffix
= QWORD_MNEM_SUFFIX
;
1839 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1840 guess_suffix
= WORD_MNEM_SUFFIX
;
1842 for (op
= i
.operands
; --op
>= 0;)
1843 if (i
.types
[op
] & Imm
)
1845 switch (i
.op
[op
].imms
->X_op
)
1848 /* If a suffix is given, this operand may be shortened. */
1849 switch (guess_suffix
)
1851 case LONG_MNEM_SUFFIX
:
1852 i
.types
[op
] |= Imm32
| Imm64
;
1854 case WORD_MNEM_SUFFIX
:
1855 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1857 case BYTE_MNEM_SUFFIX
:
1858 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1862 /* If this operand is at most 16 bits, convert it
1863 to a signed 16 bit number before trying to see
1864 whether it will fit in an even smaller size.
1865 This allows a 16-bit operand such as $0xffe0 to
1866 be recognised as within Imm8S range. */
1867 if ((i
.types
[op
] & Imm16
)
1868 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1870 i
.op
[op
].imms
->X_add_number
=
1871 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1873 if ((i
.types
[op
] & Imm32
)
1874 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1877 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1878 ^ ((offsetT
) 1 << 31))
1879 - ((offsetT
) 1 << 31));
1881 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1883 /* We must avoid matching of Imm32 templates when 64bit
1884 only immediate is available. */
1885 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1886 i
.types
[op
] &= ~Imm32
;
1893 /* Symbols and expressions. */
1895 /* Convert symbolic operand to proper sizes for matching. */
1896 switch (guess_suffix
)
1898 case QWORD_MNEM_SUFFIX
:
1899 i
.types
[op
] = Imm64
| Imm32S
;
1901 case LONG_MNEM_SUFFIX
:
1902 i
.types
[op
] = Imm32
| Imm64
;
1904 case WORD_MNEM_SUFFIX
:
1905 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1908 case BYTE_MNEM_SUFFIX
:
1909 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1918 /* Try to use the smallest displacement type too. */
1924 for (op
= i
.operands
; --op
>= 0;)
1925 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1927 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1929 if (i
.types
[op
] & Disp16
)
1931 /* We know this operand is at most 16 bits, so
1932 convert to a signed 16 bit number before trying
1933 to see whether it will fit in an even smaller
1936 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1938 else if (i
.types
[op
] & Disp32
)
1940 /* We know this operand is at most 32 bits, so convert to a
1941 signed 32 bit number before trying to see whether it will
1942 fit in an even smaller size. */
1943 disp
&= (((offsetT
) 2 << 31) - 1);
1944 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1946 if (flag_code
== CODE_64BIT
)
1948 if (fits_in_signed_long (disp
))
1949 i
.types
[op
] |= Disp32S
;
1950 if (fits_in_unsigned_long (disp
))
1951 i
.types
[op
] |= Disp32
;
1953 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1954 && fits_in_signed_byte (disp
))
1955 i
.types
[op
] |= Disp8
;
1962 /* Points to template once we've found it. */
1964 unsigned int overlap0
, overlap1
, overlap2
;
1965 unsigned int found_reverse_match
;
1968 #define MATCH(overlap, given, template) \
1969 ((overlap & ~JumpAbsolute) \
1970 && (((given) & (BaseIndex | JumpAbsolute)) \
1971 == ((overlap) & (BaseIndex | JumpAbsolute))))
1973 /* If given types r0 and r1 are registers they must be of the same type
1974 unless the expected operand type register overlap is null.
1975 Note that Acc in a template matches every size of reg. */
1976 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1977 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1978 || ((g0) & Reg) == ((g1) & Reg) \
1979 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1984 found_reverse_match
= 0;
1985 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1987 : (i
.suffix
== WORD_MNEM_SUFFIX
1989 : (i
.suffix
== SHORT_MNEM_SUFFIX
1991 : (i
.suffix
== LONG_MNEM_SUFFIX
1993 : (i
.suffix
== QWORD_MNEM_SUFFIX
1995 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1996 ? No_xSuf
: 0))))));
1998 for (t
= current_templates
->start
;
1999 t
< current_templates
->end
;
2002 /* Must have right number of operands. */
2003 if (i
.operands
!= t
->operands
)
2006 /* Check the suffix, except for some instructions in intel mode. */
2007 if ((t
->opcode_modifier
& suffix_check
)
2009 && (t
->opcode_modifier
& IgnoreSize
))
2011 && t
->base_opcode
== 0xd9
2012 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2013 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2016 /* Do not verify operands when there are none. */
2017 else if (!t
->operands
)
2019 if (t
->cpu_flags
& ~cpu_arch_flags
)
2021 /* We've found a match; break out of loop. */
2025 overlap0
= i
.types
[0] & t
->operand_types
[0];
2026 switch (t
->operands
)
2029 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2034 overlap1
= i
.types
[1] & t
->operand_types
[1];
2035 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2036 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2037 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2038 t
->operand_types
[0],
2039 overlap1
, i
.types
[1],
2040 t
->operand_types
[1]))
2042 /* Check if other direction is valid ... */
2043 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2046 /* Try reversing direction of operands. */
2047 overlap0
= i
.types
[0] & t
->operand_types
[1];
2048 overlap1
= i
.types
[1] & t
->operand_types
[0];
2049 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2050 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2051 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2052 t
->operand_types
[1],
2053 overlap1
, i
.types
[1],
2054 t
->operand_types
[0]))
2056 /* Does not match either direction. */
2059 /* found_reverse_match holds which of D or FloatDR
2061 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2063 /* Found a forward 2 operand match here. */
2064 else if (t
->operands
== 3)
2066 /* Here we make use of the fact that there are no
2067 reverse match 3 operand instructions, and all 3
2068 operand instructions only need to be checked for
2069 register consistency between operands 2 and 3. */
2070 overlap2
= i
.types
[2] & t
->operand_types
[2];
2071 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2072 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2073 t
->operand_types
[1],
2074 overlap2
, i
.types
[2],
2075 t
->operand_types
[2]))
2079 /* Found either forward/reverse 2 or 3 operand match here:
2080 slip through to break. */
2082 if (t
->cpu_flags
& ~cpu_arch_flags
)
2084 found_reverse_match
= 0;
2087 /* We've found a match; break out of loop. */
2091 if (t
== current_templates
->end
)
2093 /* We found no match. */
2094 as_bad (_("suffix or operands invalid for `%s'"),
2095 current_templates
->start
->name
);
2099 if (!quiet_warnings
)
2102 && ((i
.types
[0] & JumpAbsolute
)
2103 != (t
->operand_types
[0] & JumpAbsolute
)))
2105 as_warn (_("indirect %s without `*'"), t
->name
);
2108 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2109 == (IsPrefix
| IgnoreSize
))
2111 /* Warn them that a data or address size prefix doesn't
2112 affect assembly of the next line of code. */
2113 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2117 /* Copy the template we found. */
2119 if (found_reverse_match
)
2121 /* If we found a reverse match we must alter the opcode
2122 direction bit. found_reverse_match holds bits to change
2123 (different for int & float insns). */
2125 i
.tm
.base_opcode
^= found_reverse_match
;
2127 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2128 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2137 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2138 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2140 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2142 as_bad (_("`%s' operand %d must use `%%es' segment"),
2147 /* There's only ever one segment override allowed per instruction.
2148 This instruction possibly has a legal segment override on the
2149 second operand, so copy the segment to where non-string
2150 instructions store it, allowing common code. */
2151 i
.seg
[0] = i
.seg
[1];
2153 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2155 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2157 as_bad (_("`%s' operand %d must use `%%es' segment"),
2169 /* If matched instruction specifies an explicit instruction mnemonic
2171 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2173 if (i
.tm
.opcode_modifier
& Size16
)
2174 i
.suffix
= WORD_MNEM_SUFFIX
;
2175 else if (i
.tm
.opcode_modifier
& Size64
)
2176 i
.suffix
= QWORD_MNEM_SUFFIX
;
2178 i
.suffix
= LONG_MNEM_SUFFIX
;
2180 else if (i
.reg_operands
)
2182 /* If there's no instruction mnemonic suffix we try to invent one
2183 based on register operands. */
2186 /* We take i.suffix from the last register operand specified,
2187 Destination register type is more significant than source
2190 for (op
= i
.operands
; --op
>= 0;)
2191 if ((i
.types
[op
] & Reg
)
2192 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2194 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2195 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2196 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2201 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2203 if (!check_byte_reg ())
2206 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2208 if (!check_long_reg ())
2211 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2213 if (!check_qword_reg ())
2216 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2218 if (!check_word_reg ())
2221 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2222 /* Do nothing if the instruction is going to ignore the prefix. */
2227 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2229 i
.suffix
= stackop_size
;
2232 /* Change the opcode based on the operand size given by i.suffix;
2233 We need not change things for byte insns. */
2235 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2237 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2241 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2243 /* It's not a byte, select word/dword operation. */
2244 if (i
.tm
.opcode_modifier
& W
)
2246 if (i
.tm
.opcode_modifier
& ShortForm
)
2247 i
.tm
.base_opcode
|= 8;
2249 i
.tm
.base_opcode
|= 1;
2252 /* Now select between word & dword operations via the operand
2253 size prefix, except for instructions that will ignore this
2255 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2256 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2257 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2258 || (flag_code
== CODE_64BIT
2259 && (i
.tm
.opcode_modifier
& JumpByte
))))
2261 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2262 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2263 prefix
= ADDR_PREFIX_OPCODE
;
2265 if (!add_prefix (prefix
))
2269 /* Set mode64 for an operand. */
2270 if (i
.suffix
== QWORD_MNEM_SUFFIX
2271 && flag_code
== CODE_64BIT
2272 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2273 i
.rex
|= REX_MODE64
;
2275 /* Size floating point instruction. */
2276 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2278 if (i
.tm
.opcode_modifier
& FloatMF
)
2279 i
.tm
.base_opcode
^= 4;
2290 for (op
= i
.operands
; --op
>= 0;)
2292 /* If this is an eight bit register, it's OK. If it's the 16 or
2293 32 bit version of an eight bit register, we will just use the
2294 low portion, and that's OK too. */
2295 if (i
.types
[op
] & Reg8
)
2298 /* movzx and movsx should not generate this warning. */
2300 && (i
.tm
.base_opcode
== 0xfb7
2301 || i
.tm
.base_opcode
== 0xfb6
2302 || i
.tm
.base_opcode
== 0x63
2303 || i
.tm
.base_opcode
== 0xfbe
2304 || i
.tm
.base_opcode
== 0xfbf))
2307 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2309 /* Check that the template allows eight bit regs. This
2310 kills insns such as `orb $1,%edx', which maybe should be
2312 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2316 /* Prohibit these changes in the 64bit mode, since the
2317 lowering is more complicated. */
2318 if (flag_code
== CODE_64BIT
2319 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2321 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2322 i
.op
[op
].regs
->reg_name
,
2326 #if REGISTER_WARNINGS
2328 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2329 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2330 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2331 ? REGNAM_AL
- REGNAM_AX
2332 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2333 i
.op
[op
].regs
->reg_name
,
2338 /* Any other register is bad. */
2339 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2341 | Control
| Debug
| Test
2342 | FloatReg
| FloatAcc
))
2344 as_bad (_("`%%%s' not allowed with `%s%c'"),
2345 i
.op
[op
].regs
->reg_name
,
2359 for (op
= i
.operands
; --op
>= 0;)
2360 /* Reject eight bit registers, except where the template requires
2361 them. (eg. movzb) */
2362 if ((i
.types
[op
] & Reg8
) != 0
2363 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2365 as_bad (_("`%%%s' not allowed with `%s%c'"),
2366 i
.op
[op
].regs
->reg_name
,
2371 /* Warn if the e prefix on a general reg is missing. */
2372 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2373 && (i
.types
[op
] & Reg16
) != 0
2374 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2376 /* Prohibit these changes in the 64bit mode, since the
2377 lowering is more complicated. */
2378 if (flag_code
== CODE_64BIT
)
2380 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2381 i
.op
[op
].regs
->reg_name
,
2385 #if REGISTER_WARNINGS
2387 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2388 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2389 i
.op
[op
].regs
->reg_name
,
2393 /* Warn if the r prefix on a general reg is missing. */
2394 else if ((i
.types
[op
] & Reg64
) != 0
2395 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2397 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2398 i
.op
[op
].regs
->reg_name
,
2410 for (op
= i
.operands
; --op
>= 0; )
2411 /* Reject eight bit registers, except where the template requires
2412 them. (eg. movzb) */
2413 if ((i
.types
[op
] & Reg8
) != 0
2414 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2416 as_bad (_("`%%%s' not allowed with `%s%c'"),
2417 i
.op
[op
].regs
->reg_name
,
2422 /* Warn if the e prefix on a general reg is missing. */
2423 else if (((i
.types
[op
] & Reg16
) != 0
2424 || (i
.types
[op
] & Reg32
) != 0)
2425 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2427 /* Prohibit these changes in the 64bit mode, since the
2428 lowering is more complicated. */
2429 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2430 i
.op
[op
].regs
->reg_name
,
2441 for (op
= i
.operands
; --op
>= 0;)
2442 /* Reject eight bit registers, except where the template requires
2443 them. (eg. movzb) */
2444 if ((i
.types
[op
] & Reg8
) != 0
2445 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2447 as_bad (_("`%%%s' not allowed with `%s%c'"),
2448 i
.op
[op
].regs
->reg_name
,
2453 /* Warn if the e prefix on a general reg is present. */
2454 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2455 && (i
.types
[op
] & Reg32
) != 0
2456 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2458 /* Prohibit these changes in the 64bit mode, since the
2459 lowering is more complicated. */
2460 if (flag_code
== CODE_64BIT
)
2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2463 i
.op
[op
].regs
->reg_name
,
2468 #if REGISTER_WARNINGS
2469 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2470 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2471 i
.op
[op
].regs
->reg_name
,
2481 unsigned int overlap0
, overlap1
, overlap2
;
2483 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2484 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2485 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2486 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2487 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2491 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2493 : (i
.suffix
== WORD_MNEM_SUFFIX
2495 : (i
.suffix
== QWORD_MNEM_SUFFIX
2499 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2500 || overlap0
== (Imm16
| Imm32
)
2501 || overlap0
== (Imm16
| Imm32S
))
2503 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2506 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2507 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2508 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2510 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2514 i
.types
[0] = overlap0
;
2516 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2517 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2518 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2519 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2520 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2524 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2526 : (i
.suffix
== WORD_MNEM_SUFFIX
2528 : (i
.suffix
== QWORD_MNEM_SUFFIX
2532 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2533 || overlap1
== (Imm16
| Imm32
)
2534 || overlap1
== (Imm16
| Imm32S
))
2536 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2539 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2540 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2541 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2547 i
.types
[1] = overlap1
;
2549 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2550 assert ((overlap2
& Imm
) == 0);
2551 i
.types
[2] = overlap2
;
2559 /* Default segment register this instruction will use for memory
2560 accesses. 0 means unknown. This is only for optimizing out
2561 unnecessary segment overrides. */
2562 const seg_entry
*default_seg
= 0;
2564 /* The imul $imm, %reg instruction is converted into
2565 imul $imm, %reg, %reg, and the clr %reg instruction
2566 is converted into xor %reg, %reg. */
2567 if (i
.tm
.opcode_modifier
& regKludge
)
2569 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2570 /* Pretend we saw the extra register operand. */
2571 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2572 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2573 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2577 if (i
.tm
.opcode_modifier
& ShortForm
)
2579 /* The register or float register operand is in operand 0 or 1. */
2580 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2581 /* Register goes in low 3 bits of opcode. */
2582 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2583 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2585 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2587 /* Warn about some common errors, but press on regardless.
2588 The first case can be generated by gcc (<= 2.8.1). */
2589 if (i
.operands
== 2)
2591 /* Reversed arguments on faddp, fsubp, etc. */
2592 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2593 i
.op
[1].regs
->reg_name
,
2594 i
.op
[0].regs
->reg_name
);
2598 /* Extraneous `l' suffix on fp insn. */
2599 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2600 i
.op
[0].regs
->reg_name
);
2604 else if (i
.tm
.opcode_modifier
& Modrm
)
2606 /* The opcode is completed (modulo i.tm.extension_opcode which
2607 must be put into the modrm byte). Now, we make the modrm and
2608 index base bytes based on all the info we've collected. */
2610 default_seg
= build_modrm_byte ();
2612 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2614 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2615 && i
.op
[0].regs
->reg_num
== 1)
2617 as_bad (_("you can't `pop %%cs'"));
2620 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2621 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2624 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2628 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2630 /* For the string instructions that allow a segment override
2631 on one of their operands, the default segment is ds. */
2635 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2636 as_warn (_("segment override on `lea' is ineffectual"));
2638 /* If a segment was explicitly specified, and the specified segment
2639 is not the default, use an opcode prefix to select it. If we
2640 never figured out what the default segment is, then default_seg
2641 will be zero at this point, and the specified segment prefix will
2643 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2645 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2651 static const seg_entry
*
2654 const seg_entry
*default_seg
= 0;
2656 /* i.reg_operands MUST be the number of real register operands;
2657 implicit registers do not count. */
2658 if (i
.reg_operands
== 2)
2660 unsigned int source
, dest
;
2661 source
= ((i
.types
[0]
2662 & (Reg
| RegMMX
| RegXMM
2664 | Control
| Debug
| Test
))
2669 /* One of the register operands will be encoded in the i.tm.reg
2670 field, the other in the combined i.tm.mode and i.tm.regmem
2671 fields. If no form of this instruction supports a memory
2672 destination operand, then we assume the source operand may
2673 sometimes be a memory operand and so we need to store the
2674 destination in the i.rm.reg field. */
2675 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2677 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2678 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2679 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2681 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2686 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2687 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2688 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2690 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2695 { /* If it's not 2 reg operands... */
2698 unsigned int fake_zero_displacement
= 0;
2699 unsigned int op
= ((i
.types
[0] & AnyMem
)
2701 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2705 if (i
.base_reg
== 0)
2708 if (!i
.disp_operands
)
2709 fake_zero_displacement
= 1;
2710 if (i
.index_reg
== 0)
2712 /* Operand is just <disp> */
2713 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2714 && (flag_code
!= CODE_64BIT
))
2716 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2717 i
.types
[op
] &= ~Disp
;
2718 i
.types
[op
] |= Disp16
;
2720 else if (flag_code
!= CODE_64BIT
2721 || (i
.prefix
[ADDR_PREFIX
] != 0))
2723 i
.rm
.regmem
= NO_BASE_REGISTER
;
2724 i
.types
[op
] &= ~Disp
;
2725 i
.types
[op
] |= Disp32
;
2729 /* 64bit mode overwrites the 32bit absolute
2730 addressing by RIP relative addressing and
2731 absolute addressing is encoded by one of the
2732 redundant SIB forms. */
2733 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2734 i
.sib
.base
= NO_BASE_REGISTER
;
2735 i
.sib
.index
= NO_INDEX_REGISTER
;
2736 i
.types
[op
] &= ~Disp
;
2737 i
.types
[op
] |= Disp32S
;
2740 else /* !i.base_reg && i.index_reg */
2742 i
.sib
.index
= i
.index_reg
->reg_num
;
2743 i
.sib
.base
= NO_BASE_REGISTER
;
2744 i
.sib
.scale
= i
.log2_scale_factor
;
2745 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2746 i
.types
[op
] &= ~Disp
;
2747 if (flag_code
!= CODE_64BIT
)
2748 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2750 i
.types
[op
] |= Disp32S
;
2751 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2755 /* RIP addressing for 64bit mode. */
2756 else if (i
.base_reg
->reg_type
== BaseIndex
)
2758 i
.rm
.regmem
= NO_BASE_REGISTER
;
2759 i
.types
[op
] &= ~Disp
;
2760 i
.types
[op
] |= Disp32S
;
2761 i
.flags
[op
] = Operand_PCrel
;
2763 else if (i
.base_reg
->reg_type
& Reg16
)
2765 switch (i
.base_reg
->reg_num
)
2768 if (i
.index_reg
== 0)
2770 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2771 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2775 if (i
.index_reg
== 0)
2778 if ((i
.types
[op
] & Disp
) == 0)
2780 /* fake (%bp) into 0(%bp) */
2781 i
.types
[op
] |= Disp8
;
2782 fake_zero_displacement
= 1;
2785 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2786 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2788 default: /* (%si) -> 4 or (%di) -> 5 */
2789 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2791 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2793 else /* i.base_reg and 32/64 bit mode */
2795 if (flag_code
== CODE_64BIT
2796 && (i
.types
[op
] & Disp
))
2798 if (i
.types
[op
] & Disp8
)
2799 i
.types
[op
] = Disp8
| Disp32S
;
2801 i
.types
[op
] = Disp32S
;
2803 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2804 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2806 i
.sib
.base
= i
.base_reg
->reg_num
;
2807 /* x86-64 ignores REX prefix bit here to avoid decoder
2809 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2812 if (i
.disp_operands
== 0)
2814 fake_zero_displacement
= 1;
2815 i
.types
[op
] |= Disp8
;
2818 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2822 i
.sib
.scale
= i
.log2_scale_factor
;
2823 if (i
.index_reg
== 0)
2825 /* <disp>(%esp) becomes two byte modrm with no index
2826 register. We've already stored the code for esp
2827 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2828 Any base register besides %esp will not use the
2829 extra modrm byte. */
2830 i
.sib
.index
= NO_INDEX_REGISTER
;
2831 #if !SCALE1_WHEN_NO_INDEX
2832 /* Another case where we force the second modrm byte. */
2833 if (i
.log2_scale_factor
)
2834 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2839 i
.sib
.index
= i
.index_reg
->reg_num
;
2840 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2841 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2844 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2847 if (fake_zero_displacement
)
2849 /* Fakes a zero displacement assuming that i.types[op]
2850 holds the correct displacement size. */
2853 assert (i
.op
[op
].disps
== 0);
2854 exp
= &disp_expressions
[i
.disp_operands
++];
2855 i
.op
[op
].disps
= exp
;
2856 exp
->X_op
= O_constant
;
2857 exp
->X_add_number
= 0;
2858 exp
->X_add_symbol
= (symbolS
*) 0;
2859 exp
->X_op_symbol
= (symbolS
*) 0;
2863 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2864 (if any) based on i.tm.extension_opcode. Again, we must be
2865 careful to make sure that segment/control/debug/test/MMX
2866 registers are coded into the i.rm.reg field. */
2871 & (Reg
| RegMMX
| RegXMM
2873 | Control
| Debug
| Test
))
2876 & (Reg
| RegMMX
| RegXMM
2878 | Control
| Debug
| Test
))
2881 /* If there is an extension opcode to put here, the register
2882 number must be put into the regmem field. */
2883 if (i
.tm
.extension_opcode
!= None
)
2885 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2886 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2891 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2892 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2896 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2897 must set it to 3 to indicate this is a register operand
2898 in the regmem field. */
2899 if (!i
.mem_operands
)
2903 /* Fill in i.rm.reg field with extension opcode (if any). */
2904 if (i
.tm
.extension_opcode
!= None
)
2905 i
.rm
.reg
= i
.tm
.extension_opcode
;
2916 relax_substateT subtype
;
2921 if (flag_code
== CODE_16BIT
)
2925 if (i
.prefix
[DATA_PREFIX
] != 0)
2931 /* Pentium4 branch hints. */
2932 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2933 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2938 if (i
.prefix
[REX_PREFIX
] != 0)
2944 if (i
.prefixes
!= 0 && !intel_syntax
)
2945 as_warn (_("skipping prefixes on this instruction"));
2947 /* It's always a symbol; End frag & setup for relax.
2948 Make sure there is enough room in this frag for the largest
2949 instruction we may generate in md_convert_frag. This is 2
2950 bytes for the opcode and room for the prefix and largest
2952 frag_grow (prefix
+ 2 + 4);
2953 /* Prefix and 1 opcode byte go in fr_fix. */
2954 p
= frag_more (prefix
+ 1);
2955 if (i
.prefix
[DATA_PREFIX
] != 0)
2956 *p
++ = DATA_PREFIX_OPCODE
;
2957 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2958 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2959 *p
++ = i
.prefix
[SEG_PREFIX
];
2960 if (i
.prefix
[REX_PREFIX
] != 0)
2961 *p
++ = i
.prefix
[REX_PREFIX
];
2962 *p
= i
.tm
.base_opcode
;
2964 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2965 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2966 else if ((cpu_arch_flags
& Cpu386
) != 0)
2967 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2969 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2972 sym
= i
.op
[0].disps
->X_add_symbol
;
2973 off
= i
.op
[0].disps
->X_add_number
;
2975 if (i
.op
[0].disps
->X_op
!= O_constant
2976 && i
.op
[0].disps
->X_op
!= O_symbol
)
2978 /* Handle complex expressions. */
2979 sym
= make_expr_symbol (i
.op
[0].disps
);
2983 /* 1 possible extra opcode + 4 byte displacement go in var part.
2984 Pass reloc in fr_var. */
2985 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2994 if (i
.tm
.opcode_modifier
& JumpByte
)
2996 /* This is a loop or jecxz type instruction. */
2998 if (i
.prefix
[ADDR_PREFIX
] != 0)
3000 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3003 /* Pentium4 branch hints. */
3004 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3005 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3007 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3016 if (flag_code
== CODE_16BIT
)
3019 if (i
.prefix
[DATA_PREFIX
] != 0)
3021 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3031 if (i
.prefix
[REX_PREFIX
] != 0)
3033 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3037 if (i
.prefixes
!= 0 && !intel_syntax
)
3038 as_warn (_("skipping prefixes on this instruction"));
3040 p
= frag_more (1 + size
);
3041 *p
++ = i
.tm
.base_opcode
;
3043 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3044 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3048 output_interseg_jump ()
3056 if (flag_code
== CODE_16BIT
)
3060 if (i
.prefix
[DATA_PREFIX
] != 0)
3066 if (i
.prefix
[REX_PREFIX
] != 0)
3076 if (i
.prefixes
!= 0 && !intel_syntax
)
3077 as_warn (_("skipping prefixes on this instruction"));
3079 /* 1 opcode; 2 segment; offset */
3080 p
= frag_more (prefix
+ 1 + 2 + size
);
3082 if (i
.prefix
[DATA_PREFIX
] != 0)
3083 *p
++ = DATA_PREFIX_OPCODE
;
3085 if (i
.prefix
[REX_PREFIX
] != 0)
3086 *p
++ = i
.prefix
[REX_PREFIX
];
3088 *p
++ = i
.tm
.base_opcode
;
3089 if (i
.op
[1].imms
->X_op
== O_constant
)
3091 offsetT n
= i
.op
[1].imms
->X_add_number
;
3094 && !fits_in_unsigned_word (n
)
3095 && !fits_in_signed_word (n
))
3097 as_bad (_("16-bit jump out of range"));
3100 md_number_to_chars (p
, n
, size
);
3103 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3104 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3105 if (i
.op
[0].imms
->X_op
!= O_constant
)
3106 as_bad (_("can't handle non absolute segment in `%s'"),
3108 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3115 fragS
*insn_start_frag
;
3116 offsetT insn_start_off
;
3118 /* Tie dwarf2 debug info to the address at the start of the insn.
3119 We can't do this after the insn has been output as the current
3120 frag may have been closed off. eg. by frag_var. */
3121 dwarf2_emit_insn (0);
3123 insn_start_frag
= frag_now
;
3124 insn_start_off
= frag_now_fix ();
3127 if (i
.tm
.opcode_modifier
& Jump
)
3129 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3131 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3132 output_interseg_jump ();
3135 /* Output normal instructions here. */
3139 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3140 byte for the SSE instructions to specify a prefix they require. */
3141 if (i
.tm
.base_opcode
& 0xff0000)
3142 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3144 /* The prefix bytes. */
3146 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3152 md_number_to_chars (p
, (valueT
) *q
, 1);
3156 /* Now the opcode; be careful about word order here! */
3157 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3159 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3164 /* Put out high byte first: can't use md_number_to_chars! */
3165 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3166 *p
= i
.tm
.base_opcode
& 0xff;
3169 /* Now the modrm byte and sib byte (if present). */
3170 if (i
.tm
.opcode_modifier
& Modrm
)
3173 md_number_to_chars (p
,
3174 (valueT
) (i
.rm
.regmem
<< 0
3178 /* If i.rm.regmem == ESP (4)
3179 && i.rm.mode != (Register mode)
3181 ==> need second modrm byte. */
3182 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3184 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3187 md_number_to_chars (p
,
3188 (valueT
) (i
.sib
.base
<< 0
3190 | i
.sib
.scale
<< 6),
3195 if (i
.disp_operands
)
3196 output_disp (insn_start_frag
, insn_start_off
);
3199 output_imm (insn_start_frag
, insn_start_off
);
3207 #endif /* DEBUG386 */
3211 output_disp (insn_start_frag
, insn_start_off
)
3212 fragS
*insn_start_frag
;
3213 offsetT insn_start_off
;
3218 for (n
= 0; n
< i
.operands
; n
++)
3220 if (i
.types
[n
] & Disp
)
3222 if (i
.op
[n
].disps
->X_op
== O_constant
)
3228 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3231 if (i
.types
[n
] & Disp8
)
3233 if (i
.types
[n
] & Disp64
)
3236 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3238 p
= frag_more (size
);
3239 md_number_to_chars (p
, val
, size
);
3243 RELOC_ENUM reloc_type
;
3246 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3248 /* The PC relative address is computed relative
3249 to the instruction boundary, so in case immediate
3250 fields follows, we need to adjust the value. */
3251 if (pcrel
&& i
.imm_operands
)
3256 for (n1
= 0; n1
< i
.operands
; n1
++)
3257 if (i
.types
[n1
] & Imm
)
3259 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3262 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3264 if (i
.types
[n1
] & Imm64
)
3269 /* We should find the immediate. */
3270 if (n1
== i
.operands
)
3272 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3275 if (i
.types
[n
] & Disp32S
)
3278 if (i
.types
[n
] & (Disp16
| Disp64
))
3281 if (i
.types
[n
] & Disp64
)
3285 p
= frag_more (size
);
3286 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3287 #ifdef BFD_ASSEMBLER
3288 if (reloc_type
== BFD_RELOC_32
3290 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3291 && (i
.op
[n
].disps
->X_op
== O_symbol
3292 || (i
.op
[n
].disps
->X_op
== O_add
3293 && ((symbol_get_value_expression
3294 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3299 if (insn_start_frag
== frag_now
)
3300 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3305 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3306 for (fr
= insn_start_frag
->fr_next
;
3307 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3309 add
+= p
- frag_now
->fr_literal
;
3312 /* We don't support dynamic linking on x86-64 yet. */
3313 if (flag_code
== CODE_64BIT
)
3315 reloc_type
= BFD_RELOC_386_GOTPC
;
3316 i
.op
[n
].disps
->X_add_number
+= add
;
3319 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3320 i
.op
[n
].disps
, pcrel
, reloc_type
);
3327 output_imm (insn_start_frag
, insn_start_off
)
3328 fragS
*insn_start_frag
;
3329 offsetT insn_start_off
;
3334 for (n
= 0; n
< i
.operands
; n
++)
3336 if (i
.types
[n
] & Imm
)
3338 if (i
.op
[n
].imms
->X_op
== O_constant
)
3344 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3347 if (i
.types
[n
] & (Imm8
| Imm8S
))
3349 else if (i
.types
[n
] & Imm64
)
3352 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3354 p
= frag_more (size
);
3355 md_number_to_chars (p
, val
, size
);
3359 /* Not absolute_section.
3360 Need a 32-bit fixup (don't support 8bit
3361 non-absolute imms). Try to support other
3363 RELOC_ENUM reloc_type
;
3367 if ((i
.types
[n
] & (Imm32S
))
3368 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3370 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3373 if (i
.types
[n
] & (Imm8
| Imm8S
))
3375 if (i
.types
[n
] & Imm64
)
3379 p
= frag_more (size
);
3380 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3381 #ifdef BFD_ASSEMBLER
3382 /* This is tough to explain. We end up with this one if we
3383 * have operands that look like
3384 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3385 * obtain the absolute address of the GOT, and it is strongly
3386 * preferable from a performance point of view to avoid using
3387 * a runtime relocation for this. The actual sequence of
3388 * instructions often look something like:
3393 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3395 * The call and pop essentially return the absolute address
3396 * of the label .L66 and store it in %ebx. The linker itself
3397 * will ultimately change the first operand of the addl so
3398 * that %ebx points to the GOT, but to keep things simple, the
3399 * .o file must have this operand set so that it generates not
3400 * the absolute address of .L66, but the absolute address of
3401 * itself. This allows the linker itself simply treat a GOTPC
3402 * relocation as asking for a pcrel offset to the GOT to be
3403 * added in, and the addend of the relocation is stored in the
3404 * operand field for the instruction itself.
3406 * Our job here is to fix the operand so that it would add
3407 * the correct offset so that %ebx would point to itself. The
3408 * thing that is tricky is that .-.L66 will point to the
3409 * beginning of the instruction, so we need to further modify
3410 * the operand so that it will point to itself. There are
3411 * other cases where you have something like:
3413 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3415 * and here no correction would be required. Internally in
3416 * the assembler we treat operands of this form as not being
3417 * pcrel since the '.' is explicitly mentioned, and I wonder
3418 * whether it would simplify matters to do it this way. Who
3419 * knows. In earlier versions of the PIC patches, the
3420 * pcrel_adjust field was used to store the correction, but
3421 * since the expression is not pcrel, I felt it would be
3422 * confusing to do it this way. */
3424 if (reloc_type
== BFD_RELOC_32
3426 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3427 && (i
.op
[n
].imms
->X_op
== O_symbol
3428 || (i
.op
[n
].imms
->X_op
== O_add
3429 && ((symbol_get_value_expression
3430 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3435 if (insn_start_frag
== frag_now
)
3436 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3441 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3442 for (fr
= insn_start_frag
->fr_next
;
3443 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3445 add
+= p
- frag_now
->fr_literal
;
3448 /* We don't support dynamic linking on x86-64 yet. */
3449 if (flag_code
== CODE_64BIT
)
3451 reloc_type
= BFD_RELOC_386_GOTPC
;
3452 i
.op
[n
].imms
->X_add_number
+= add
;
3455 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3456 i
.op
[n
].imms
, 0, reloc_type
);
3463 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3465 /* Parse operands of the form
3466 <symbol>@GOTOFF+<nnn>
3467 and similar .plt or .got references.
3469 If we find one, set up the correct relocation in RELOC and copy the
3470 input string, minus the `@GOTOFF' into a malloc'd buffer for
3471 parsing by the calling routine. Return this buffer, and if ADJUST
3472 is non-null set it to the length of the string we removed from the
3473 input line. Otherwise return NULL. */
3475 lex_got (reloc
, adjust
)
3479 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3480 static const struct {
3482 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3484 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3485 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3486 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3487 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, 0 } },
3488 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3489 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, 0 } },
3490 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, 0 } },
3491 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3492 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, 0 } },
3493 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3494 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3495 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3500 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3501 if (is_end_of_line
[(unsigned char) *cp
])
3504 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3508 len
= strlen (gotrel
[j
].str
);
3509 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3511 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3514 char *tmpbuf
, *past_reloc
;
3516 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3520 if (GOT_symbol
== NULL
)
3521 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3523 /* Replace the relocation token with ' ', so that
3524 errors like foo@GOTOFF1 will be detected. */
3526 /* The length of the first part of our input line. */
3527 first
= cp
- input_line_pointer
;
3529 /* The second part goes from after the reloc token until
3530 (and including) an end_of_line char. Don't use strlen
3531 here as the end_of_line char may not be a NUL. */
3532 past_reloc
= cp
+ 1 + len
;
3533 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3535 second
= cp
- past_reloc
;
3537 /* Allocate and copy string. The trailing NUL shouldn't
3538 be necessary, but be safe. */
3539 tmpbuf
= xmalloc (first
+ second
+ 2);
3540 memcpy (tmpbuf
, input_line_pointer
, first
);
3541 tmpbuf
[first
] = ' ';
3542 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3543 tmpbuf
[first
+ second
+ 1] = '\0';
3547 as_bad (_("@%s reloc is not supported in %s bit mode"),
3548 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3553 /* Might be a symbol version string. Don't as_bad here. */
3557 /* x86_cons_fix_new is called via the expression parsing code when a
3558 reloc is needed. We use this hook to get the correct .got reloc. */
3559 static RELOC_ENUM got_reloc
= NO_RELOC
;
3562 x86_cons_fix_new (frag
, off
, len
, exp
)
3568 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3569 got_reloc
= NO_RELOC
;
3570 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3574 x86_cons (exp
, size
)
3580 /* Handle @GOTOFF and the like in an expression. */
3582 char *gotfree_input_line
;
3585 save
= input_line_pointer
;
3586 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3587 if (gotfree_input_line
)
3588 input_line_pointer
= gotfree_input_line
;
3592 if (gotfree_input_line
)
3594 /* expression () has merrily parsed up to the end of line,
3595 or a comma - in the wrong buffer. Transfer how far
3596 input_line_pointer has moved to the right buffer. */
3597 input_line_pointer
= (save
3598 + (input_line_pointer
- gotfree_input_line
)
3600 free (gotfree_input_line
);
3608 static int i386_immediate
PARAMS ((char *));
3611 i386_immediate (imm_start
)
3614 char *save_input_line_pointer
;
3616 char *gotfree_input_line
;
3621 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3623 as_bad (_("only 1 or 2 immediate operands are allowed"));
3627 exp
= &im_expressions
[i
.imm_operands
++];
3628 i
.op
[this_operand
].imms
= exp
;
3630 if (is_space_char (*imm_start
))
3633 save_input_line_pointer
= input_line_pointer
;
3634 input_line_pointer
= imm_start
;
3637 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3638 if (gotfree_input_line
)
3639 input_line_pointer
= gotfree_input_line
;
3642 exp_seg
= expression (exp
);
3645 if (*input_line_pointer
)
3646 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3648 input_line_pointer
= save_input_line_pointer
;
3650 if (gotfree_input_line
)
3651 free (gotfree_input_line
);
3654 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3656 /* Missing or bad expr becomes absolute 0. */
3657 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3659 exp
->X_op
= O_constant
;
3660 exp
->X_add_number
= 0;
3661 exp
->X_add_symbol
= (symbolS
*) 0;
3662 exp
->X_op_symbol
= (symbolS
*) 0;
3664 else if (exp
->X_op
== O_constant
)
3666 /* Size it properly later. */
3667 i
.types
[this_operand
] |= Imm64
;
3668 /* If BFD64, sign extend val. */
3669 if (!use_rela_relocations
)
3670 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3671 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3673 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3675 #ifdef BFD_ASSEMBLER
3676 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3678 && exp_seg
!= absolute_section
3679 && exp_seg
!= text_section
3680 && exp_seg
!= data_section
3681 && exp_seg
!= bss_section
3682 && exp_seg
!= undefined_section
3683 #ifdef BFD_ASSEMBLER
3684 && !bfd_is_com_section (exp_seg
)
3688 #ifdef BFD_ASSEMBLER
3689 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3691 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3698 /* This is an address. The size of the address will be
3699 determined later, depending on destination register,
3700 suffix, or the default for the section. */
3701 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3707 static char *i386_scale
PARAMS ((char *));
3714 char *save
= input_line_pointer
;
3716 input_line_pointer
= scale
;
3717 val
= get_absolute_expression ();
3723 i
.log2_scale_factor
= 0;
3726 i
.log2_scale_factor
= 1;
3729 i
.log2_scale_factor
= 2;
3732 i
.log2_scale_factor
= 3;
3735 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3737 input_line_pointer
= save
;
3740 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3742 as_warn (_("scale factor of %d without an index register"),
3743 1 << i
.log2_scale_factor
);
3744 #if SCALE1_WHEN_NO_INDEX
3745 i
.log2_scale_factor
= 0;
3748 scale
= input_line_pointer
;
3749 input_line_pointer
= save
;
3753 static int i386_displacement
PARAMS ((char *, char *));
3756 i386_displacement (disp_start
, disp_end
)
3762 char *save_input_line_pointer
;
3764 char *gotfree_input_line
;
3766 int bigdisp
= Disp32
;
3768 if (flag_code
== CODE_64BIT
)
3770 if (i
.prefix
[ADDR_PREFIX
] == 0)
3773 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3775 i
.types
[this_operand
] |= bigdisp
;
3777 exp
= &disp_expressions
[i
.disp_operands
];
3778 i
.op
[this_operand
].disps
= exp
;
3780 save_input_line_pointer
= input_line_pointer
;
3781 input_line_pointer
= disp_start
;
3782 END_STRING_AND_SAVE (disp_end
);
3784 #ifndef GCC_ASM_O_HACK
3785 #define GCC_ASM_O_HACK 0
3788 END_STRING_AND_SAVE (disp_end
+ 1);
3789 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3790 && displacement_string_end
[-1] == '+')
3792 /* This hack is to avoid a warning when using the "o"
3793 constraint within gcc asm statements.
3796 #define _set_tssldt_desc(n,addr,limit,type) \
3797 __asm__ __volatile__ ( \
3799 "movw %w1,2+%0\n\t" \
3801 "movb %b1,4+%0\n\t" \
3802 "movb %4,5+%0\n\t" \
3803 "movb $0,6+%0\n\t" \
3804 "movb %h1,7+%0\n\t" \
3806 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3808 This works great except that the output assembler ends
3809 up looking a bit weird if it turns out that there is
3810 no offset. You end up producing code that looks like:
3823 So here we provide the missing zero. */
3825 *displacement_string_end
= '0';
3829 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3830 if (gotfree_input_line
)
3831 input_line_pointer
= gotfree_input_line
;
3834 exp_seg
= expression (exp
);
3837 if (*input_line_pointer
)
3838 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3840 RESTORE_END_STRING (disp_end
+ 1);
3842 RESTORE_END_STRING (disp_end
);
3843 input_line_pointer
= save_input_line_pointer
;
3845 if (gotfree_input_line
)
3846 free (gotfree_input_line
);
3849 #ifdef BFD_ASSEMBLER
3850 /* We do this to make sure that the section symbol is in
3851 the symbol table. We will ultimately change the relocation
3852 to be relative to the beginning of the section. */
3853 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3854 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3856 if (exp
->X_op
!= O_symbol
)
3858 as_bad (_("bad expression used with @%s"),
3859 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3865 if (S_IS_LOCAL (exp
->X_add_symbol
)
3866 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3867 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3868 exp
->X_op
= O_subtract
;
3869 exp
->X_op_symbol
= GOT_symbol
;
3870 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3871 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3873 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3877 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3879 /* Missing or bad expr becomes absolute 0. */
3880 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3882 exp
->X_op
= O_constant
;
3883 exp
->X_add_number
= 0;
3884 exp
->X_add_symbol
= (symbolS
*) 0;
3885 exp
->X_op_symbol
= (symbolS
*) 0;
3888 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3889 if (exp
->X_op
!= O_constant
3890 #ifdef BFD_ASSEMBLER
3891 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3893 && exp_seg
!= absolute_section
3894 && exp_seg
!= text_section
3895 && exp_seg
!= data_section
3896 && exp_seg
!= bss_section
3897 && exp_seg
!= undefined_section
3898 #ifdef BFD_ASSEMBLER
3899 && !bfd_is_com_section (exp_seg
)
3903 #ifdef BFD_ASSEMBLER
3904 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3906 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3911 else if (flag_code
== CODE_64BIT
)
3912 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3916 static int i386_index_check
PARAMS ((const char *));
3918 /* Make sure the memory operand we've been dealt is valid.
3919 Return 1 on success, 0 on a failure. */
3922 i386_index_check (operand_string
)
3923 const char *operand_string
;
3926 #if INFER_ADDR_PREFIX
3932 if (flag_code
== CODE_64BIT
)
3934 if (i
.prefix
[ADDR_PREFIX
] == 0)
3938 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3939 && (i
.base_reg
->reg_type
!= BaseIndex
3942 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3943 != (Reg64
| BaseIndex
))))
3950 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3952 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3953 != (Reg32
| BaseIndex
))))
3959 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3963 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3964 != (Reg16
| BaseIndex
)))
3966 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3967 != (Reg16
| BaseIndex
))
3969 && i
.base_reg
->reg_num
< 6
3970 && i
.index_reg
->reg_num
>= 6
3971 && i
.log2_scale_factor
== 0))))
3978 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3980 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3981 != (Reg32
| BaseIndex
))))
3987 #if INFER_ADDR_PREFIX
3988 if (flag_code
!= CODE_64BIT
3989 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3991 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3993 /* Change the size of any displacement too. At most one of
3994 Disp16 or Disp32 is set.
3995 FIXME. There doesn't seem to be any real need for separate
3996 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3997 Removing them would probably clean up the code quite a lot. */
3998 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3999 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4004 as_bad (_("`%s' is not a valid base/index expression"),
4008 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4010 flag_code_names
[flag_code
]);
4016 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4020 i386_operand (operand_string
)
4021 char *operand_string
;
4025 char *op_string
= operand_string
;
4027 if (is_space_char (*op_string
))
4030 /* We check for an absolute prefix (differentiating,
4031 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4032 if (*op_string
== ABSOLUTE_PREFIX
)
4035 if (is_space_char (*op_string
))
4037 i
.types
[this_operand
] |= JumpAbsolute
;
4040 /* Check if operand is a register. */
4041 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4042 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4044 /* Check for a segment override by searching for ':' after a
4045 segment register. */
4047 if (is_space_char (*op_string
))
4049 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4054 i
.seg
[i
.mem_operands
] = &es
;
4057 i
.seg
[i
.mem_operands
] = &cs
;
4060 i
.seg
[i
.mem_operands
] = &ss
;
4063 i
.seg
[i
.mem_operands
] = &ds
;
4066 i
.seg
[i
.mem_operands
] = &fs
;
4069 i
.seg
[i
.mem_operands
] = &gs
;
4073 /* Skip the ':' and whitespace. */
4075 if (is_space_char (*op_string
))
4078 if (!is_digit_char (*op_string
)
4079 && !is_identifier_char (*op_string
)
4080 && *op_string
!= '('
4081 && *op_string
!= ABSOLUTE_PREFIX
)
4083 as_bad (_("bad memory operand `%s'"), op_string
);
4086 /* Handle case of %es:*foo. */
4087 if (*op_string
== ABSOLUTE_PREFIX
)
4090 if (is_space_char (*op_string
))
4092 i
.types
[this_operand
] |= JumpAbsolute
;
4094 goto do_memory_reference
;
4098 as_bad (_("junk `%s' after register"), op_string
);
4101 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4102 i
.op
[this_operand
].regs
= r
;
4105 else if (*op_string
== REGISTER_PREFIX
)
4107 as_bad (_("bad register name `%s'"), op_string
);
4110 else if (*op_string
== IMMEDIATE_PREFIX
)
4113 if (i
.types
[this_operand
] & JumpAbsolute
)
4115 as_bad (_("immediate operand illegal with absolute jump"));
4118 if (!i386_immediate (op_string
))
4121 else if (is_digit_char (*op_string
)
4122 || is_identifier_char (*op_string
)
4123 || *op_string
== '(')
4125 /* This is a memory reference of some sort. */
4128 /* Start and end of displacement string expression (if found). */
4129 char *displacement_string_start
;
4130 char *displacement_string_end
;
4132 do_memory_reference
:
4133 if ((i
.mem_operands
== 1
4134 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4135 || i
.mem_operands
== 2)
4137 as_bad (_("too many memory references for `%s'"),
4138 current_templates
->start
->name
);
4142 /* Check for base index form. We detect the base index form by
4143 looking for an ')' at the end of the operand, searching
4144 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4146 base_string
= op_string
+ strlen (op_string
);
4149 if (is_space_char (*base_string
))
4152 /* If we only have a displacement, set-up for it to be parsed later. */
4153 displacement_string_start
= op_string
;
4154 displacement_string_end
= base_string
+ 1;
4156 if (*base_string
== ')')
4159 unsigned int parens_balanced
= 1;
4160 /* We've already checked that the number of left & right ()'s are
4161 equal, so this loop will not be infinite. */
4165 if (*base_string
== ')')
4167 if (*base_string
== '(')
4170 while (parens_balanced
);
4172 temp_string
= base_string
;
4174 /* Skip past '(' and whitespace. */
4176 if (is_space_char (*base_string
))
4179 if (*base_string
== ','
4180 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4181 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4183 displacement_string_end
= temp_string
;
4185 i
.types
[this_operand
] |= BaseIndex
;
4189 base_string
= end_op
;
4190 if (is_space_char (*base_string
))
4194 /* There may be an index reg or scale factor here. */
4195 if (*base_string
== ',')
4198 if (is_space_char (*base_string
))
4201 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4202 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4204 base_string
= end_op
;
4205 if (is_space_char (*base_string
))
4207 if (*base_string
== ',')
4210 if (is_space_char (*base_string
))
4213 else if (*base_string
!= ')')
4215 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4220 else if (*base_string
== REGISTER_PREFIX
)
4222 as_bad (_("bad register name `%s'"), base_string
);
4226 /* Check for scale factor. */
4227 if (*base_string
!= ')')
4229 char *end_scale
= i386_scale (base_string
);
4234 base_string
= end_scale
;
4235 if (is_space_char (*base_string
))
4237 if (*base_string
!= ')')
4239 as_bad (_("expecting `)' after scale factor in `%s'"),
4244 else if (!i
.index_reg
)
4246 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4251 else if (*base_string
!= ')')
4253 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4258 else if (*base_string
== REGISTER_PREFIX
)
4260 as_bad (_("bad register name `%s'"), base_string
);
4265 /* If there's an expression beginning the operand, parse it,
4266 assuming displacement_string_start and
4267 displacement_string_end are meaningful. */
4268 if (displacement_string_start
!= displacement_string_end
)
4270 if (!i386_displacement (displacement_string_start
,
4271 displacement_string_end
))
4275 /* Special case for (%dx) while doing input/output op. */
4277 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4279 && i
.log2_scale_factor
== 0
4280 && i
.seg
[i
.mem_operands
] == 0
4281 && (i
.types
[this_operand
] & Disp
) == 0)
4283 i
.types
[this_operand
] = InOutPortReg
;
4287 if (i386_index_check (operand_string
) == 0)
4293 /* It's not a memory operand; argh! */
4294 as_bad (_("invalid char %s beginning operand %d `%s'"),
4295 output_invalid (*op_string
),
4300 return 1; /* Normal return. */
4303 /* md_estimate_size_before_relax()
4305 Called just before relax() for rs_machine_dependent frags. The x86
4306 assembler uses these frags to handle variable size jump
4309 Any symbol that is now undefined will not become defined.
4310 Return the correct fr_subtype in the frag.
4311 Return the initial "guess for variable size of frag" to caller.
4312 The guess is actually the growth beyond the fixed part. Whatever
4313 we do to grow the fixed or variable part contributes to our
4317 md_estimate_size_before_relax (fragP
, segment
)
4321 /* We've already got fragP->fr_subtype right; all we have to do is
4322 check for un-relaxable symbols. On an ELF system, we can't relax
4323 an externally visible symbol, because it may be overridden by a
4325 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4326 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4327 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4328 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4329 || S_IS_WEAK (fragP
->fr_symbol
)))
4333 /* Symbol is undefined in this segment, or we need to keep a
4334 reloc so that weak symbols can be overridden. */
4335 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4336 RELOC_ENUM reloc_type
;
4337 unsigned char *opcode
;
4340 if (fragP
->fr_var
!= NO_RELOC
)
4341 reloc_type
= fragP
->fr_var
;
4343 reloc_type
= BFD_RELOC_16_PCREL
;
4345 reloc_type
= BFD_RELOC_32_PCREL
;
4347 old_fr_fix
= fragP
->fr_fix
;
4348 opcode
= (unsigned char *) fragP
->fr_opcode
;
4350 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4353 /* Make jmp (0xeb) a (d)word displacement jump. */
4355 fragP
->fr_fix
+= size
;
4356 fix_new (fragP
, old_fr_fix
, size
,
4358 fragP
->fr_offset
, 1,
4364 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4366 /* Negate the condition, and branch past an
4367 unconditional jump. */
4370 /* Insert an unconditional jump. */
4372 /* We added two extra opcode bytes, and have a two byte
4374 fragP
->fr_fix
+= 2 + 2;
4375 fix_new (fragP
, old_fr_fix
+ 2, 2,
4377 fragP
->fr_offset
, 1,
4384 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4387 fix_new (fragP
, old_fr_fix
, 1,
4389 fragP
->fr_offset
, 1,
4394 /* This changes the byte-displacement jump 0x7N
4395 to the (d)word-displacement jump 0x0f,0x8N. */
4396 opcode
[1] = opcode
[0] + 0x10;
4397 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4398 /* We've added an opcode byte. */
4399 fragP
->fr_fix
+= 1 + size
;
4400 fix_new (fragP
, old_fr_fix
+ 1, size
,
4402 fragP
->fr_offset
, 1,
4407 BAD_CASE (fragP
->fr_subtype
);
4411 return fragP
->fr_fix
- old_fr_fix
;
4414 /* Guess size depending on current relax state. Initially the relax
4415 state will correspond to a short jump and we return 1, because
4416 the variable part of the frag (the branch offset) is one byte
4417 long. However, we can relax a section more than once and in that
4418 case we must either set fr_subtype back to the unrelaxed state,
4419 or return the value for the appropriate branch. */
4420 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4423 /* Called after relax() is finished.
4425 In: Address of frag.
4426 fr_type == rs_machine_dependent.
4427 fr_subtype is what the address relaxed to.
4429 Out: Any fixSs and constants are set up.
4430 Caller will turn frag into a ".space 0". */
4432 #ifndef BFD_ASSEMBLER
4434 md_convert_frag (headers
, sec
, fragP
)
4435 object_headers
*headers ATTRIBUTE_UNUSED
;
4436 segT sec ATTRIBUTE_UNUSED
;
4440 md_convert_frag (abfd
, sec
, fragP
)
4441 bfd
*abfd ATTRIBUTE_UNUSED
;
4442 segT sec ATTRIBUTE_UNUSED
;
4446 unsigned char *opcode
;
4447 unsigned char *where_to_put_displacement
= NULL
;
4448 offsetT target_address
;
4449 offsetT opcode_address
;
4450 unsigned int extension
= 0;
4451 offsetT displacement_from_opcode_start
;
4453 opcode
= (unsigned char *) fragP
->fr_opcode
;
4455 /* Address we want to reach in file space. */
4456 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4458 /* Address opcode resides at in file space. */
4459 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4461 /* Displacement from opcode start to fill into instruction. */
4462 displacement_from_opcode_start
= target_address
- opcode_address
;
4464 if ((fragP
->fr_subtype
& BIG
) == 0)
4466 /* Don't have to change opcode. */
4467 extension
= 1; /* 1 opcode + 1 displacement */
4468 where_to_put_displacement
= &opcode
[1];
4472 if (no_cond_jump_promotion
4473 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4474 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4476 switch (fragP
->fr_subtype
)
4478 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4479 extension
= 4; /* 1 opcode + 4 displacement */
4481 where_to_put_displacement
= &opcode
[1];
4484 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4485 extension
= 2; /* 1 opcode + 2 displacement */
4487 where_to_put_displacement
= &opcode
[1];
4490 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4491 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4492 extension
= 5; /* 2 opcode + 4 displacement */
4493 opcode
[1] = opcode
[0] + 0x10;
4494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4495 where_to_put_displacement
= &opcode
[2];
4498 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4499 extension
= 3; /* 2 opcode + 2 displacement */
4500 opcode
[1] = opcode
[0] + 0x10;
4501 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4502 where_to_put_displacement
= &opcode
[2];
4505 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4510 where_to_put_displacement
= &opcode
[3];
4514 BAD_CASE (fragP
->fr_subtype
);
4519 /* Now put displacement after opcode. */
4520 md_number_to_chars ((char *) where_to_put_displacement
,
4521 (valueT
) (displacement_from_opcode_start
- extension
),
4522 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4523 fragP
->fr_fix
+= extension
;
4526 /* Size of byte displacement jmp. */
4527 int md_short_jump_size
= 2;
4529 /* Size of dword displacement jmp. */
4530 int md_long_jump_size
= 5;
4532 /* Size of relocation record. */
4533 const int md_reloc_size
= 8;
4536 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4538 addressT from_addr
, to_addr
;
4539 fragS
*frag ATTRIBUTE_UNUSED
;
4540 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4544 offset
= to_addr
- (from_addr
+ 2);
4545 /* Opcode for byte-disp jump. */
4546 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4547 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4551 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4553 addressT from_addr
, to_addr
;
4554 fragS
*frag ATTRIBUTE_UNUSED
;
4555 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4559 offset
= to_addr
- (from_addr
+ 5);
4560 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4561 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4564 /* Apply a fixup (fixS) to segment data, once it has been determined
4565 by our caller that we have all the info we need to fix it up.
4567 On the 386, immediates, displacements, and data pointers are all in
4568 the same (little-endian) format, so we don't need to care about which
4572 md_apply_fix3 (fixP
, valP
, seg
)
4573 /* The fix we're to put in. */
4575 /* Pointer to the value of the bits. */
4577 /* Segment fix is from. */
4578 segT seg ATTRIBUTE_UNUSED
;
4580 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4581 valueT value
= *valP
;
4583 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4586 switch (fixP
->fx_r_type
)
4592 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4595 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4598 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4603 if (fixP
->fx_addsy
!= NULL
4604 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4605 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4606 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4607 && !use_rela_relocations
)
4609 /* This is a hack. There should be a better way to handle this.
4610 This covers for the fact that bfd_install_relocation will
4611 subtract the current location (for partial_inplace, PC relative
4612 relocations); see more below. */
4614 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4616 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4619 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4621 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4622 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4624 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4627 || (symbol_section_p (fixP
->fx_addsy
)
4628 && sym_seg
!= absolute_section
))
4629 && !S_FORCE_RELOC (fixP
->fx_addsy
))
4631 /* Yes, we add the values in twice. This is because
4632 bfd_install_relocation subtracts them out again. I think
4633 bfd_install_relocation is broken, but I don't dare change
4635 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4639 #if defined (OBJ_COFF) && defined (TE_PE)
4640 /* For some reason, the PE format does not store a section
4641 address offset for a PC relative symbol. */
4642 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4643 value
+= md_pcrel_from (fixP
);
4647 /* Fix a few things - the dynamic linker expects certain values here,
4648 and we must not dissappoint it. */
4649 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4650 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4652 switch (fixP
->fx_r_type
)
4654 case BFD_RELOC_386_PLT32
:
4655 case BFD_RELOC_X86_64_PLT32
:
4656 /* Make the jump instruction point to the address of the operand. At
4657 runtime we merely add the offset to the actual PLT entry. */
4661 case BFD_RELOC_386_GOT32
:
4662 case BFD_RELOC_386_TLS_GD
:
4663 case BFD_RELOC_386_TLS_LDM
:
4664 case BFD_RELOC_386_TLS_IE_32
:
4665 case BFD_RELOC_386_TLS_IE
:
4666 case BFD_RELOC_386_TLS_GOTIE
:
4667 case BFD_RELOC_X86_64_GOT32
:
4668 value
= 0; /* Fully resolved at runtime. No addend. */
4671 case BFD_RELOC_VTABLE_INHERIT
:
4672 case BFD_RELOC_VTABLE_ENTRY
:
4679 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4681 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4683 /* Are we finished with this relocation now? */
4684 if (fixP
->fx_addsy
== NULL
)
4686 #ifdef BFD_ASSEMBLER
4687 else if (use_rela_relocations
)
4689 fixP
->fx_no_overflow
= 1;
4690 /* Remember value for tc_gen_reloc. */
4691 fixP
->fx_addnumber
= value
;
4695 md_number_to_chars (p
, value
, fixP
->fx_size
);
4698 #define MAX_LITTLENUMS 6
4700 /* Turn the string pointed to by litP into a floating point constant
4701 of type TYPE, and emit the appropriate bytes. The number of
4702 LITTLENUMS emitted is stored in *SIZEP. An error message is
4703 returned, or NULL on OK. */
4706 md_atof (type
, litP
, sizeP
)
4712 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4713 LITTLENUM_TYPE
*wordP
;
4735 return _("Bad call to md_atof ()");
4737 t
= atof_ieee (input_line_pointer
, type
, words
);
4739 input_line_pointer
= t
;
4741 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4742 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4743 the bigendian 386. */
4744 for (wordP
= words
+ prec
- 1; prec
--;)
4746 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4747 litP
+= sizeof (LITTLENUM_TYPE
);
4752 char output_invalid_buf
[8];
4759 sprintf (output_invalid_buf
, "'%c'", c
);
4761 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4762 return output_invalid_buf
;
4765 /* REG_STRING starts *before* REGISTER_PREFIX. */
4767 static const reg_entry
*
4768 parse_register (reg_string
, end_op
)
4772 char *s
= reg_string
;
4774 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4777 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4778 if (*s
== REGISTER_PREFIX
)
4781 if (is_space_char (*s
))
4785 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4787 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4788 return (const reg_entry
*) NULL
;
4792 /* For naked regs, make sure that we are not dealing with an identifier.
4793 This prevents confusing an identifier like `eax_var' with register
4795 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4796 return (const reg_entry
*) NULL
;
4800 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4802 /* Handle floating point regs, allowing spaces in the (i) part. */
4803 if (r
== i386_regtab
/* %st is first entry of table */)
4805 if (is_space_char (*s
))
4810 if (is_space_char (*s
))
4812 if (*s
>= '0' && *s
<= '7')
4814 r
= &i386_float_regtab
[*s
- '0'];
4816 if (is_space_char (*s
))
4824 /* We have "%st(" then garbage. */
4825 return (const reg_entry
*) NULL
;
4830 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4831 && flag_code
!= CODE_64BIT
)
4833 return (const reg_entry
*) NULL
;
4839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4840 const char *md_shortopts
= "kVQ:sq";
4842 const char *md_shortopts
= "q";
4845 struct option md_longopts
[] = {
4846 #define OPTION_32 (OPTION_MD_BASE + 0)
4847 {"32", no_argument
, NULL
, OPTION_32
},
4848 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4849 #define OPTION_64 (OPTION_MD_BASE + 1)
4850 {"64", no_argument
, NULL
, OPTION_64
},
4852 {NULL
, no_argument
, NULL
, 0}
4854 size_t md_longopts_size
= sizeof (md_longopts
);
4857 md_parse_option (c
, arg
)
4859 char *arg ATTRIBUTE_UNUSED
;
4867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4868 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4869 should be emitted or not. FIXME: Not implemented. */
4873 /* -V: SVR4 argument to print version ID. */
4875 print_version_id ();
4878 /* -k: Ignore for FreeBSD compatibility. */
4883 /* -s: On i386 Solaris, this tells the native assembler to use
4884 .stab instead of .stab.excl. We always use .stab anyhow. */
4889 const char **list
, **l
;
4891 list
= bfd_target_list ();
4892 for (l
= list
; *l
!= NULL
; l
++)
4893 if (strcmp (*l
, "elf64-x86-64") == 0)
4895 default_arch
= "x86_64";
4899 as_fatal (_("No compiled in support for x86_64"));
4906 default_arch
= "i386";
4916 md_show_usage (stream
)
4919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4920 fprintf (stream
, _("\
4922 -V print assembler version number\n\
4924 -q quieten some warnings\n\
4927 fprintf (stream
, _("\
4928 -q quieten some warnings\n"));
4932 #ifdef BFD_ASSEMBLER
4933 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4934 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4936 /* Pick the target format to use. */
4939 i386_target_format ()
4941 if (!strcmp (default_arch
, "x86_64"))
4942 set_code_flag (CODE_64BIT
);
4943 else if (!strcmp (default_arch
, "i386"))
4944 set_code_flag (CODE_32BIT
);
4946 as_fatal (_("Unknown architecture"));
4947 switch (OUTPUT_FLAVOR
)
4949 #ifdef OBJ_MAYBE_AOUT
4950 case bfd_target_aout_flavour
:
4951 return AOUT_TARGET_FORMAT
;
4953 #ifdef OBJ_MAYBE_COFF
4954 case bfd_target_coff_flavour
:
4957 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4958 case bfd_target_elf_flavour
:
4960 if (flag_code
== CODE_64BIT
)
4961 use_rela_relocations
= 1;
4962 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
4971 #endif /* OBJ_MAYBE_ more than one */
4973 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4974 void i386_elf_emit_arch_note ()
4976 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4977 && cpu_arch_name
!= NULL
)
4980 asection
*seg
= now_seg
;
4981 subsegT subseg
= now_subseg
;
4982 Elf_Internal_Note i_note
;
4983 Elf_External_Note e_note
;
4984 asection
*note_secp
;
4987 /* Create the .note section. */
4988 note_secp
= subseg_new (".note", 0);
4989 bfd_set_section_flags (stdoutput
,
4991 SEC_HAS_CONTENTS
| SEC_READONLY
);
4993 /* Process the arch string. */
4994 len
= strlen (cpu_arch_name
);
4996 i_note
.namesz
= len
+ 1;
4998 i_note
.type
= NT_ARCH
;
4999 p
= frag_more (sizeof (e_note
.namesz
));
5000 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5001 p
= frag_more (sizeof (e_note
.descsz
));
5002 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5003 p
= frag_more (sizeof (e_note
.type
));
5004 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5005 p
= frag_more (len
+ 1);
5006 strcpy (p
, cpu_arch_name
);
5008 frag_align (2, 0, 0);
5010 subseg_set (seg
, subseg
);
5014 #endif /* BFD_ASSEMBLER */
5017 md_undefined_symbol (name
)
5020 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5021 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5022 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5023 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5027 if (symbol_find (name
))
5028 as_bad (_("GOT already in symbol table"));
5029 GOT_symbol
= symbol_new (name
, undefined_section
,
5030 (valueT
) 0, &zero_address_frag
);
5037 /* Round up a section size to the appropriate boundary. */
5040 md_section_align (segment
, size
)
5041 segT segment ATTRIBUTE_UNUSED
;
5044 #ifdef BFD_ASSEMBLER
5045 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5046 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5048 /* For a.out, force the section size to be aligned. If we don't do
5049 this, BFD will align it for us, but it will not write out the
5050 final bytes of the section. This may be a bug in BFD, but it is
5051 easier to fix it here since that is how the other a.out targets
5055 align
= bfd_get_section_alignment (stdoutput
, segment
);
5056 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5064 /* On the i386, PC-relative offsets are relative to the start of the
5065 next instruction. That is, the address of the offset, plus its
5066 size, since the offset is always the last part of the insn. */
5069 md_pcrel_from (fixP
)
5072 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5079 int ignore ATTRIBUTE_UNUSED
;
5083 temp
= get_absolute_expression ();
5084 subseg_set (bss_section
, (subsegT
) temp
);
5085 demand_empty_rest_of_line ();
5090 #ifdef BFD_ASSEMBLER
5093 i386_validate_fix (fixp
)
5096 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5098 /* GOTOFF relocation are nonsense in 64bit mode. */
5099 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5101 if (flag_code
!= CODE_64BIT
)
5103 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5107 if (flag_code
== CODE_64BIT
)
5109 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5116 i386_force_relocation (fixp
)
5119 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5120 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5123 return S_FORCE_RELOC (fixp
->fx_addsy
);
5127 tc_gen_reloc (section
, fixp
)
5128 asection
*section ATTRIBUTE_UNUSED
;
5132 bfd_reloc_code_real_type code
;
5134 switch (fixp
->fx_r_type
)
5136 case BFD_RELOC_X86_64_PLT32
:
5137 case BFD_RELOC_X86_64_GOT32
:
5138 case BFD_RELOC_X86_64_GOTPCREL
:
5139 case BFD_RELOC_386_PLT32
:
5140 case BFD_RELOC_386_GOT32
:
5141 case BFD_RELOC_386_GOTOFF
:
5142 case BFD_RELOC_386_GOTPC
:
5143 case BFD_RELOC_386_TLS_GD
:
5144 case BFD_RELOC_386_TLS_LDM
:
5145 case BFD_RELOC_386_TLS_LDO_32
:
5146 case BFD_RELOC_386_TLS_IE_32
:
5147 case BFD_RELOC_386_TLS_IE
:
5148 case BFD_RELOC_386_TLS_GOTIE
:
5149 case BFD_RELOC_386_TLS_LE_32
:
5150 case BFD_RELOC_386_TLS_LE
:
5151 case BFD_RELOC_X86_64_32S
:
5153 case BFD_RELOC_VTABLE_ENTRY
:
5154 case BFD_RELOC_VTABLE_INHERIT
:
5155 code
= fixp
->fx_r_type
;
5160 switch (fixp
->fx_size
)
5163 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5164 _("can not do %d byte pc-relative relocation"),
5166 code
= BFD_RELOC_32_PCREL
;
5168 case 1: code
= BFD_RELOC_8_PCREL
; break;
5169 case 2: code
= BFD_RELOC_16_PCREL
; break;
5170 case 4: code
= BFD_RELOC_32_PCREL
; break;
5175 switch (fixp
->fx_size
)
5178 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5179 _("can not do %d byte relocation"),
5181 code
= BFD_RELOC_32
;
5183 case 1: code
= BFD_RELOC_8
; break;
5184 case 2: code
= BFD_RELOC_16
; break;
5185 case 4: code
= BFD_RELOC_32
; break;
5187 case 8: code
= BFD_RELOC_64
; break;
5194 if (code
== BFD_RELOC_32
5196 && fixp
->fx_addsy
== GOT_symbol
)
5198 /* We don't support GOTPC on 64bit targets. */
5199 if (flag_code
== CODE_64BIT
)
5201 code
= BFD_RELOC_386_GOTPC
;
5204 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5205 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5206 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5208 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5209 if (!use_rela_relocations
)
5211 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5212 vtable entry to be used in the relocation's section offset. */
5213 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5214 rel
->address
= fixp
->fx_offset
;
5218 /* Use the rela in 64bit mode. */
5221 if (!fixp
->fx_pcrel
)
5222 rel
->addend
= fixp
->fx_offset
;
5226 case BFD_RELOC_X86_64_PLT32
:
5227 case BFD_RELOC_X86_64_GOT32
:
5228 case BFD_RELOC_X86_64_GOTPCREL
:
5229 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5232 rel
->addend
= (section
->vma
5234 + fixp
->fx_addnumber
5235 + md_pcrel_from (fixp
));
5240 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5241 if (rel
->howto
== NULL
)
5243 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5244 _("cannot represent relocation type %s"),
5245 bfd_get_reloc_code_name (code
));
5246 /* Set howto to a garbage value so that we can keep going. */
5247 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5248 assert (rel
->howto
!= NULL
);
5254 #else /* !BFD_ASSEMBLER */
5256 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5258 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5261 relax_addressT segment_address_in_file
;
5263 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5264 Out: GNU LD relocation length code: 0, 1, or 2. */
5266 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5269 know (fixP
->fx_addsy
!= NULL
);
5271 md_number_to_chars (where
,
5272 (valueT
) (fixP
->fx_frag
->fr_address
5273 + fixP
->fx_where
- segment_address_in_file
),
5276 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5277 ? S_GET_TYPE (fixP
->fx_addsy
)
5278 : fixP
->fx_addsy
->sy_number
);
5280 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5281 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5282 where
[4] = r_symbolnum
& 0x0ff;
5283 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5284 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5285 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5288 #endif /* OBJ_AOUT or OBJ_BOUT. */
5290 #if defined (I386COFF)
5293 tc_coff_fix2rtype (fixP
)
5296 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5299 return (fixP
->fx_pcrel
?
5300 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5301 fixP
->fx_size
== 2 ? R_PCRWORD
:
5303 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5304 fixP
->fx_size
== 2 ? R_RELWORD
:
5309 tc_coff_sizemachdep (frag
)
5313 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5318 #endif /* I386COFF */
5320 #endif /* !BFD_ASSEMBLER */
5322 /* Parse operands using Intel syntax. This implements a recursive descent
5323 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5326 FIXME: We do not recognize the full operand grammar defined in the MASM
5327 documentation. In particular, all the structure/union and
5328 high-level macro operands are missing.
5330 Uppercase words are terminals, lower case words are non-terminals.
5331 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5332 bars '|' denote choices. Most grammar productions are implemented in
5333 functions called 'intel_<production>'.
5335 Initial production is 'expr'.
5341 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5343 constant digits [[ radixOverride ]]
5345 dataType BYTE | WORD | DWORD | QWORD | XWORD
5378 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5379 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5381 hexdigit a | b | c | d | e | f
5382 | A | B | C | D | E | F
5392 register specialRegister
5396 segmentRegister CS | DS | ES | FS | GS | SS
5398 specialRegister CR0 | CR2 | CR3
5399 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5400 | TR3 | TR4 | TR5 | TR6 | TR7
5402 We simplify the grammar in obvious places (e.g., register parsing is
5403 done by calling parse_register) and eliminate immediate left recursion
5404 to implement a recursive-descent parser.
5444 /* Parsing structure for the intel syntax parser. Used to implement the
5445 semantic actions for the operand grammar. */
5446 struct intel_parser_s
5448 char *op_string
; /* The string being parsed. */
5449 int got_a_float
; /* Whether the operand is a float. */
5450 int op_modifier
; /* Operand modifier. */
5451 int is_mem
; /* 1 if operand is memory reference. */
5452 const reg_entry
*reg
; /* Last register reference found. */
5453 char *disp
; /* Displacement string being built. */
5456 static struct intel_parser_s intel_parser
;
5458 /* Token structure for parsing intel syntax. */
5461 int code
; /* Token code. */
5462 const reg_entry
*reg
; /* Register entry for register tokens. */
5463 char *str
; /* String representation. */
5466 static struct intel_token cur_token
, prev_token
;
5468 /* Token codes for the intel parser. Since T_SHORT is already used
5469 by COFF, undefine it first to prevent a warning. */
5484 /* Prototypes for intel parser functions. */
5485 static int intel_match_token
PARAMS ((int code
));
5486 static void intel_get_token
PARAMS ((void));
5487 static void intel_putback_token
PARAMS ((void));
5488 static int intel_expr
PARAMS ((void));
5489 static int intel_e05
PARAMS ((void));
5490 static int intel_e05_1
PARAMS ((void));
5491 static int intel_e06
PARAMS ((void));
5492 static int intel_e06_1
PARAMS ((void));
5493 static int intel_e09
PARAMS ((void));
5494 static int intel_e09_1
PARAMS ((void));
5495 static int intel_e10
PARAMS ((void));
5496 static int intel_e10_1
PARAMS ((void));
5497 static int intel_e11
PARAMS ((void));
5500 i386_intel_operand (operand_string
, got_a_float
)
5501 char *operand_string
;
5507 /* Initialize token holders. */
5508 cur_token
.code
= prev_token
.code
= T_NIL
;
5509 cur_token
.reg
= prev_token
.reg
= NULL
;
5510 cur_token
.str
= prev_token
.str
= NULL
;
5512 /* Initialize parser structure. */
5513 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5516 strcpy (intel_parser
.op_string
, operand_string
);
5517 intel_parser
.got_a_float
= got_a_float
;
5518 intel_parser
.op_modifier
= -1;
5519 intel_parser
.is_mem
= 0;
5520 intel_parser
.reg
= NULL
;
5521 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5522 if (intel_parser
.disp
== NULL
)
5524 intel_parser
.disp
[0] = '\0';
5526 /* Read the first token and start the parser. */
5528 ret
= intel_expr ();
5532 /* If we found a memory reference, hand it over to i386_displacement
5533 to fill in the rest of the operand fields. */
5534 if (intel_parser
.is_mem
)
5536 if ((i
.mem_operands
== 1
5537 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5538 || i
.mem_operands
== 2)
5540 as_bad (_("too many memory references for '%s'"),
5541 current_templates
->start
->name
);
5546 char *s
= intel_parser
.disp
;
5549 /* Add the displacement expression. */
5551 ret
= i386_displacement (s
, s
+ strlen (s
))
5552 && i386_index_check (s
);
5556 /* Constant and OFFSET expressions are handled by i386_immediate. */
5557 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5558 || intel_parser
.reg
== NULL
)
5559 ret
= i386_immediate (intel_parser
.disp
);
5563 free (intel_parser
.disp
);
5573 /* expr SHORT e05 */
5574 if (cur_token
.code
== T_SHORT
)
5576 intel_parser
.op_modifier
= SHORT
;
5577 intel_match_token (T_SHORT
);
5579 return (intel_e05 ());
5584 return intel_e05 ();
5594 return (intel_e06 () && intel_e05_1 ());
5600 /* e05' addOp e06 e05' */
5601 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5603 strcat (intel_parser
.disp
, cur_token
.str
);
5604 intel_match_token (cur_token
.code
);
5606 return (intel_e06 () && intel_e05_1 ());
5621 return (intel_e09 () && intel_e06_1 ());
5627 /* e06' mulOp e09 e06' */
5628 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5630 strcat (intel_parser
.disp
, cur_token
.str
);
5631 intel_match_token (cur_token
.code
);
5633 return (intel_e09 () && intel_e06_1 ());
5641 /* e09 OFFSET e10 e09'
5650 /* e09 OFFSET e10 e09' */
5651 if (cur_token
.code
== T_OFFSET
)
5653 intel_parser
.is_mem
= 0;
5654 intel_parser
.op_modifier
= OFFSET_FLAT
;
5655 intel_match_token (T_OFFSET
);
5657 return (intel_e10 () && intel_e09_1 ());
5662 return (intel_e10 () && intel_e09_1 ());
5668 /* e09' PTR e10 e09' */
5669 if (cur_token
.code
== T_PTR
)
5671 if (prev_token
.code
== T_BYTE
)
5672 i
.suffix
= BYTE_MNEM_SUFFIX
;
5674 else if (prev_token
.code
== T_WORD
)
5676 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5677 i
.suffix
= SHORT_MNEM_SUFFIX
;
5679 i
.suffix
= WORD_MNEM_SUFFIX
;
5682 else if (prev_token
.code
== T_DWORD
)
5684 if (intel_parser
.got_a_float
== 1) /* "f..." */
5685 i
.suffix
= SHORT_MNEM_SUFFIX
;
5687 i
.suffix
= LONG_MNEM_SUFFIX
;
5690 else if (prev_token
.code
== T_QWORD
)
5692 if (intel_parser
.got_a_float
== 1) /* "f..." */
5693 i
.suffix
= LONG_MNEM_SUFFIX
;
5695 i
.suffix
= QWORD_MNEM_SUFFIX
;
5698 else if (prev_token
.code
== T_XWORD
)
5699 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5703 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5707 intel_match_token (T_PTR
);
5709 return (intel_e10 () && intel_e09_1 ());
5712 /* e09 : e10 e09' */
5713 else if (cur_token
.code
== ':')
5715 /* Mark as a memory operand only if it's not already known to be an
5716 offset expression. */
5717 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5718 intel_parser
.is_mem
= 1;
5720 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5735 return (intel_e11 () && intel_e10_1 ());
5741 /* e10' [ expr ] e10' */
5742 if (cur_token
.code
== '[')
5744 intel_match_token ('[');
5746 /* Mark as a memory operand only if it's not already known to be an
5747 offset expression. If it's an offset expression, we need to keep
5749 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5750 intel_parser
.is_mem
= 1;
5752 strcat (intel_parser
.disp
, "[");
5754 /* Add a '+' to the displacement string if necessary. */
5755 if (*intel_parser
.disp
!= '\0'
5756 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5757 strcat (intel_parser
.disp
, "+");
5759 if (intel_expr () && intel_match_token (']'))
5761 /* Preserve brackets when the operand is an offset expression. */
5762 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5763 strcat (intel_parser
.disp
, "]");
5765 return intel_e10_1 ();
5792 if (cur_token
.code
== '(')
5794 intel_match_token ('(');
5795 strcat (intel_parser
.disp
, "(");
5797 if (intel_expr () && intel_match_token (')'))
5799 strcat (intel_parser
.disp
, ")");
5807 else if (cur_token
.code
== '[')
5809 intel_match_token ('[');
5811 /* Mark as a memory operand only if it's not already known to be an
5812 offset expression. If it's an offset expression, we need to keep
5814 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5815 intel_parser
.is_mem
= 1;
5817 strcat (intel_parser
.disp
, "[");
5819 /* Operands for jump/call inside brackets denote absolute addresses. */
5820 if (current_templates
->start
->opcode_modifier
& Jump
5821 || current_templates
->start
->opcode_modifier
& JumpDword
5822 || current_templates
->start
->opcode_modifier
& JumpByte
5823 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5824 i
.types
[this_operand
] |= JumpAbsolute
;
5826 /* Add a '+' to the displacement string if necessary. */
5827 if (*intel_parser
.disp
!= '\0'
5828 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5829 strcat (intel_parser
.disp
, "+");
5831 if (intel_expr () && intel_match_token (']'))
5833 /* Preserve brackets when the operand is an offset expression. */
5834 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5835 strcat (intel_parser
.disp
, "]");
5848 else if (cur_token
.code
== T_BYTE
5849 || cur_token
.code
== T_WORD
5850 || cur_token
.code
== T_DWORD
5851 || cur_token
.code
== T_QWORD
5852 || cur_token
.code
== T_XWORD
)
5854 intel_match_token (cur_token
.code
);
5861 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5863 strcat (intel_parser
.disp
, cur_token
.str
);
5864 intel_match_token (cur_token
.code
);
5866 /* Mark as a memory operand only if it's not already known to be an
5867 offset expression. */
5868 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5869 intel_parser
.is_mem
= 1;
5875 else if (cur_token
.code
== T_REG
)
5877 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5879 intel_match_token (T_REG
);
5881 /* Check for segment change. */
5882 if (cur_token
.code
== ':')
5884 if (reg
->reg_type
& (SReg2
| SReg3
))
5886 switch (reg
->reg_num
)
5889 i
.seg
[i
.mem_operands
] = &es
;
5892 i
.seg
[i
.mem_operands
] = &cs
;
5895 i
.seg
[i
.mem_operands
] = &ss
;
5898 i
.seg
[i
.mem_operands
] = &ds
;
5901 i
.seg
[i
.mem_operands
] = &fs
;
5904 i
.seg
[i
.mem_operands
] = &gs
;
5910 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5915 /* Not a segment register. Check for register scaling. */
5916 else if (cur_token
.code
== '*')
5918 if (!intel_parser
.is_mem
)
5920 as_bad (_("Register scaling only allowed in memory operands."));
5924 /* What follows must be a valid scale. */
5925 if (intel_match_token ('*')
5926 && strchr ("01248", *cur_token
.str
))
5929 i
.types
[this_operand
] |= BaseIndex
;
5931 /* Set the scale after setting the register (otherwise,
5932 i386_scale will complain) */
5933 i386_scale (cur_token
.str
);
5934 intel_match_token (T_CONST
);
5938 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5944 /* No scaling. If this is a memory operand, the register is either a
5945 base register (first occurrence) or an index register (second
5947 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5949 if (i
.base_reg
&& i
.index_reg
)
5951 as_bad (_("Too many register references in memory operand.\n"));
5955 if (i
.base_reg
== NULL
)
5960 i
.types
[this_operand
] |= BaseIndex
;
5963 /* Offset modifier. Add the register to the displacement string to be
5964 parsed as an immediate expression after we're done. */
5965 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5966 strcat (intel_parser
.disp
, reg
->reg_name
);
5968 /* It's neither base nor index nor offset. */
5971 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5972 i
.op
[this_operand
].regs
= reg
;
5976 /* Since registers are not part of the displacement string (except
5977 when we're parsing offset operands), we may need to remove any
5978 preceding '+' from the displacement string. */
5979 if (*intel_parser
.disp
!= '\0'
5980 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5982 char *s
= intel_parser
.disp
;
5983 s
+= strlen (s
) - 1;
5992 else if (cur_token
.code
== T_ID
)
5994 /* Add the identifier to the displacement string. */
5995 strcat (intel_parser
.disp
, cur_token
.str
);
5996 intel_match_token (T_ID
);
5998 /* The identifier represents a memory reference only if it's not
5999 preceded by an offset modifier. */
6000 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6001 intel_parser
.is_mem
= 1;
6007 else if (cur_token
.code
== T_CONST
6008 || cur_token
.code
== '-'
6009 || cur_token
.code
== '+')
6013 /* Allow constants that start with `+' or `-'. */
6014 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6016 strcat (intel_parser
.disp
, cur_token
.str
);
6017 intel_match_token (cur_token
.code
);
6018 if (cur_token
.code
!= T_CONST
)
6020 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6026 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6027 if (save_str
== NULL
)
6029 strcpy (save_str
, cur_token
.str
);
6031 /* Get the next token to check for register scaling. */
6032 intel_match_token (cur_token
.code
);
6034 /* Check if this constant is a scaling factor for an index register. */
6035 if (cur_token
.code
== '*')
6037 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6039 if (!intel_parser
.is_mem
)
6041 as_bad (_("Register scaling only allowed in memory operands."));
6045 /* The constant is followed by `* reg', so it must be
6047 if (strchr ("01248", *save_str
))
6049 i
.index_reg
= cur_token
.reg
;
6050 i
.types
[this_operand
] |= BaseIndex
;
6052 /* Set the scale after setting the register (otherwise,
6053 i386_scale will complain) */
6054 i386_scale (save_str
);
6055 intel_match_token (T_REG
);
6057 /* Since registers are not part of the displacement
6058 string, we may need to remove any preceding '+' from
6059 the displacement string. */
6060 if (*intel_parser
.disp
!= '\0')
6062 char *s
= intel_parser
.disp
;
6063 s
+= strlen (s
) - 1;
6076 /* The constant was not used for register scaling. Since we have
6077 already consumed the token following `*' we now need to put it
6078 back in the stream. */
6080 intel_putback_token ();
6083 /* Add the constant to the displacement string. */
6084 strcat (intel_parser
.disp
, save_str
);
6090 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6094 /* Match the given token against cur_token. If they match, read the next
6095 token from the operand string. */
6097 intel_match_token (code
)
6100 if (cur_token
.code
== code
)
6107 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6112 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6117 const reg_entry
*reg
;
6118 struct intel_token new_token
;
6120 new_token
.code
= T_NIL
;
6121 new_token
.reg
= NULL
;
6122 new_token
.str
= NULL
;
6124 /* Free the memory allocated to the previous token and move
6125 cur_token to prev_token. */
6127 free (prev_token
.str
);
6129 prev_token
= cur_token
;
6131 /* Skip whitespace. */
6132 while (is_space_char (*intel_parser
.op_string
))
6133 intel_parser
.op_string
++;
6135 /* Return an empty token if we find nothing else on the line. */
6136 if (*intel_parser
.op_string
== '\0')
6138 cur_token
= new_token
;
6142 /* The new token cannot be larger than the remainder of the operand
6144 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6145 if (new_token
.str
== NULL
)
6147 new_token
.str
[0] = '\0';
6149 if (strchr ("0123456789", *intel_parser
.op_string
))
6151 char *p
= new_token
.str
;
6152 char *q
= intel_parser
.op_string
;
6153 new_token
.code
= T_CONST
;
6155 /* Allow any kind of identifier char to encompass floating point and
6156 hexadecimal numbers. */
6157 while (is_identifier_char (*q
))
6161 /* Recognize special symbol names [0-9][bf]. */
6162 if (strlen (intel_parser
.op_string
) == 2
6163 && (intel_parser
.op_string
[1] == 'b'
6164 || intel_parser
.op_string
[1] == 'f'))
6165 new_token
.code
= T_ID
;
6168 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6170 new_token
.code
= *intel_parser
.op_string
;
6171 new_token
.str
[0] = *intel_parser
.op_string
;
6172 new_token
.str
[1] = '\0';
6175 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6176 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6178 new_token
.code
= T_REG
;
6179 new_token
.reg
= reg
;
6181 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6183 new_token
.str
[0] = REGISTER_PREFIX
;
6184 new_token
.str
[1] = '\0';
6187 strcat (new_token
.str
, reg
->reg_name
);
6190 else if (is_identifier_char (*intel_parser
.op_string
))
6192 char *p
= new_token
.str
;
6193 char *q
= intel_parser
.op_string
;
6195 /* A '.' or '$' followed by an identifier char is an identifier.
6196 Otherwise, it's operator '.' followed by an expression. */
6197 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6199 new_token
.code
= *q
;
6200 new_token
.str
[0] = *q
;
6201 new_token
.str
[1] = '\0';
6205 while (is_identifier_char (*q
) || *q
== '@')
6209 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6210 new_token
.code
= T_BYTE
;
6212 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6213 new_token
.code
= T_WORD
;
6215 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6216 new_token
.code
= T_DWORD
;
6218 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6219 new_token
.code
= T_QWORD
;
6221 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6222 new_token
.code
= T_XWORD
;
6224 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6225 new_token
.code
= T_PTR
;
6227 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6228 new_token
.code
= T_SHORT
;
6230 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6232 new_token
.code
= T_OFFSET
;
6234 /* ??? This is not mentioned in the MASM grammar but gcc
6235 makes use of it with -mintel-syntax. OFFSET may be
6236 followed by FLAT: */
6237 if (strncasecmp (q
, " FLAT:", 6) == 0)
6238 strcat (new_token
.str
, " FLAT:");
6241 /* ??? This is not mentioned in the MASM grammar. */
6242 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6243 new_token
.code
= T_OFFSET
;
6246 new_token
.code
= T_ID
;
6251 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6253 intel_parser
.op_string
+= strlen (new_token
.str
);
6254 cur_token
= new_token
;
6257 /* Put cur_token back into the token stream and make cur_token point to
6260 intel_putback_token ()
6262 intel_parser
.op_string
-= strlen (cur_token
.str
);
6263 free (cur_token
.str
);
6264 cur_token
= prev_token
;
6266 /* Forget prev_token. */
6267 prev_token
.code
= T_NIL
;
6268 prev_token
.reg
= NULL
;
6269 prev_token
.str
= NULL
;