1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags enable
; /* cpu feature enable flags */
135 i386_cpu_flags disable
; /* cpu feature disable flags */
139 static void update_code_flag (int, int);
140 static void s_insn (int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
150 static void pe_directive_secidx (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (const char *, char **);
163 static const char *parse_insn (const char *, char *, bool);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (unsigned int, unsigned int);
167 static enum flag_code
i386_addressing_mode (void);
168 static void optimize_imm (void);
169 static bool optimize_disp (const insn_template
*t
);
170 static const insn_template
*match_template (char);
171 static int check_string (void);
172 static int process_suffix (void);
173 static int check_byte_reg (void);
174 static int check_long_reg (void);
175 static int check_qword_reg (void);
176 static int check_word_reg (void);
177 static int finalize_imm (void);
178 static int process_operands (void);
179 static const reg_entry
*build_modrm_byte (void);
180 static void output_insn (void);
181 static void output_imm (fragS
*, offsetT
);
182 static void output_disp (fragS
*, offsetT
);
184 static void s_bss (int);
186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
187 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 /* GNU_PROPERTY_X86_ISA_1_USED. */
190 static unsigned int x86_isa_1_used
;
191 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
192 static unsigned int x86_feature_2_used
;
193 /* Generate x86 used ISA and feature properties. */
194 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
197 static const char *default_arch
= DEFAULT_ARCH
;
199 /* parse_register() returns this when a register alias cannot be used. */
200 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
201 { Dw2Inval
, Dw2Inval
} };
203 static const reg_entry
*reg_eax
;
204 static const reg_entry
*reg_ds
;
205 static const reg_entry
*reg_es
;
206 static const reg_entry
*reg_ss
;
207 static const reg_entry
*reg_st0
;
208 static const reg_entry
*reg_k0
;
213 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
214 unsigned char bytes
[4];
216 /* Destination or source register specifier. */
217 const reg_entry
*register_specifier
;
220 /* 'md_assemble ()' gathers together information and puts it into a
227 const reg_entry
*regs
;
232 no_error
, /* Must be first. */
233 operand_size_mismatch
,
234 operand_type_mismatch
,
235 register_type_mismatch
,
236 number_of_operands_mismatch
,
237 invalid_instruction_suffix
,
239 unsupported_with_intel_mnemonic
,
245 invalid_vsib_address
,
246 invalid_vector_register_set
,
247 invalid_tmm_register_set
,
248 invalid_dest_and_src_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 invalid_register_operand
,
261 /* TM holds the template for the insn were currently assembling. */
264 /* SUFFIX holds the instruction size suffix for byte, word, dword
265 or qword, if given. */
268 /* OPCODE_LENGTH holds the number of base opcode bytes. */
269 unsigned char opcode_length
;
271 /* OPERANDS gives the number of given operands. */
272 unsigned int operands
;
274 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
275 of given register, displacement, memory operands and immediate
277 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
279 /* TYPES [i] is the type (see above #defines) which tells us how to
280 use OP[i] for the corresponding operand. */
281 i386_operand_type types
[MAX_OPERANDS
];
283 /* Displacement expression, immediate expression, or register for each
285 union i386_op op
[MAX_OPERANDS
];
287 /* Flags for operands. */
288 unsigned int flags
[MAX_OPERANDS
];
289 #define Operand_PCrel 1
290 #define Operand_Mem 2
291 #define Operand_Signed 4 /* .insn only */
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* PREFIX holds all the given prefix opcodes (usually null).
307 PREFIXES is the number of prefix opcodes. */
308 unsigned int prefixes
;
309 unsigned char prefix
[MAX_PREFIXES
];
311 /* .insn allows for reserved opcode spaces. */
312 unsigned char insn_opcode_space
;
314 /* .insn also allows (requires) specifying immediate size. */
315 unsigned char imm_bits
[MAX_OPERANDS
];
317 /* Register is in low 3 bits of opcode. */
320 /* The operand to a branch insn indicates an absolute branch. */
323 /* The operand to a branch insn indicates a far branch. */
326 /* There is a memory operand of (%dx) which should be only used
327 with input/output instructions. */
328 bool input_output_operand
;
330 /* Extended states. */
338 xstate_ymm
= 1 << 2 | xstate_xmm
,
340 xstate_zmm
= 1 << 3 | xstate_ymm
,
343 /* Use MASK state. */
347 /* Has GOTPC or TLS relocation. */
348 bool has_gotpc_tls_reloc
;
350 /* RM and SIB are the modrm byte and the sib byte where the
351 addressing modes of this insn are encoded. */
358 /* Masking attributes.
360 The struct describes masking, applied to OPERAND in the instruction.
361 REG is a pointer to the corresponding mask register. ZEROING tells
362 whether merging or zeroing mask is used. */
363 struct Mask_Operation
365 const reg_entry
*reg
;
366 unsigned int zeroing
;
367 /* The operand where this operation is associated. */
368 unsigned int operand
;
371 /* Rounding control and SAE attributes. */
383 /* In Intel syntax the operand modifier form is supposed to be used, but
384 we continue to accept the immediate forms as well. */
388 /* Broadcasting attributes.
390 The struct describes broadcasting, applied to OPERAND. TYPE is
391 expresses the broadcast factor. */
392 struct Broadcast_Operation
394 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
397 /* Index of broadcasted operand. */
398 unsigned int operand
;
400 /* Number of bytes to broadcast. */
404 /* Compressed disp8*N attribute. */
405 unsigned int memshift
;
407 /* Prefer load or store in encoding. */
410 dir_encoding_default
= 0,
416 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
419 disp_encoding_default
= 0,
425 /* Prefer the REX byte in encoding. */
428 /* Disable instruction size optimization. */
431 /* How to encode vector instructions. */
434 vex_encoding_default
= 0,
442 const char *rep_prefix
;
445 const char *hle_prefix
;
447 /* Have BND prefix. */
448 const char *bnd_prefix
;
450 /* Have NOTRACK prefix. */
451 const char *notrack_prefix
;
454 enum i386_error error
;
457 typedef struct _i386_insn i386_insn
;
459 /* Link RC type with corresponding string, that'll be looked for in
468 static const struct RC_name RC_NamesTable
[] =
470 { rne
, STRING_COMMA_LEN ("rn-sae") },
471 { rd
, STRING_COMMA_LEN ("rd-sae") },
472 { ru
, STRING_COMMA_LEN ("ru-sae") },
473 { rz
, STRING_COMMA_LEN ("rz-sae") },
474 { saeonly
, STRING_COMMA_LEN ("sae") },
477 /* To be indexed by segment register number. */
478 static const unsigned char i386_seg_prefixes
[] = {
487 /* List of chars besides those in app.c:symbol_chars that can start an
488 operand. Used to prevent the scrubber eating vital white-space. */
489 const char extra_symbol_chars
[] = "*%-([{}"
498 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
499 && !defined (TE_GNU) \
500 && !defined (TE_LINUX) \
501 && !defined (TE_Haiku) \
502 && !defined (TE_FreeBSD) \
503 && !defined (TE_DragonFly) \
504 && !defined (TE_NetBSD))
505 /* This array holds the chars that always start a comment. If the
506 pre-processor is disabled, these aren't very useful. The option
507 --divide will remove '/' from this list. */
508 const char *i386_comment_chars
= "#/";
509 #define SVR4_COMMENT_CHARS 1
510 #define PREFIX_SEPARATOR '\\'
513 const char *i386_comment_chars
= "#";
514 #define PREFIX_SEPARATOR '/'
517 /* This array holds the chars that only start a comment at the beginning of
518 a line. If the line seems to have the form '# 123 filename'
519 .line and .file directives will appear in the pre-processed output.
520 Note that input_file.c hand checks for '#' at the beginning of the
521 first line of the input file. This is because the compiler outputs
522 #NO_APP at the beginning of its output.
523 Also note that comments started like this one will always work if
524 '/' isn't otherwise defined. */
525 const char line_comment_chars
[] = "#/";
527 const char line_separator_chars
[] = ";";
529 /* Chars that can be used to separate mant from exp in floating point
531 const char EXP_CHARS
[] = "eE";
533 /* Chars that mean this number is a floating point constant
536 const char FLT_CHARS
[] = "fFdDxXhHbB";
538 /* Tables for lexical analysis. */
539 static char mnemonic_chars
[256];
540 static char register_chars
[256];
541 static char operand_chars
[256];
543 /* Lexical macros. */
544 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
545 #define is_operand_char(x) (operand_chars[(unsigned char) x])
546 #define is_register_char(x) (register_chars[(unsigned char) x])
547 #define is_space_char(x) ((x) == ' ')
549 /* All non-digit non-letter characters that may occur in an operand. */
550 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
552 /* md_assemble() always leaves the strings it's passed unaltered. To
553 effect this we maintain a stack of saved characters that we've smashed
554 with '\0's (indicating end of strings for various sub-fields of the
555 assembler instruction). */
556 static char save_stack
[32];
557 static char *save_stack_p
;
558 #define END_STRING_AND_SAVE(s) \
559 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
560 #define RESTORE_END_STRING(s) \
561 do { *(s) = *--save_stack_p; } while (0)
563 /* The instruction we're assembling. */
566 /* Possible templates for current insn. */
567 static const templates
*current_templates
;
569 /* Per instruction expressionS buffers: max displacements & immediates. */
570 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
571 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
573 /* Current operand we are working on. */
574 static int this_operand
= -1;
576 /* Are we processing a .insn directive? */
577 #define dot_insn() (i.tm.mnem_off == MN__insn)
579 /* We support four different modes. FLAG_CODE variable is used to distinguish
587 static enum flag_code flag_code
;
588 static unsigned int object_64bit
;
589 static unsigned int disallow_64bit_reloc
;
590 static int use_rela_relocations
= 0;
591 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
592 static const char *tls_get_addr
;
594 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
595 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
596 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
598 /* The ELF ABI to use. */
606 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
609 #if defined (TE_PE) || defined (TE_PEP)
610 /* Use big object file format. */
611 static int use_big_obj
= 0;
614 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
615 /* 1 if generating code for a shared library. */
616 static int shared
= 0;
618 unsigned int x86_sframe_cfa_sp_reg
;
619 /* The other CFA base register for SFrame stack trace info. */
620 unsigned int x86_sframe_cfa_fp_reg
;
621 unsigned int x86_sframe_cfa_ra_reg
;
625 /* 1 for intel syntax,
627 static int intel_syntax
= 0;
629 static enum x86_64_isa
631 amd64
= 1, /* AMD64 ISA. */
632 intel64
/* Intel64 ISA. */
635 /* 1 for intel mnemonic,
636 0 if att mnemonic. */
637 static int intel_mnemonic
= !SYSV386_COMPAT
;
639 /* 1 if pseudo registers are permitted. */
640 static int allow_pseudo_reg
= 0;
642 /* 1 if register prefix % not required. */
643 static int allow_naked_reg
= 0;
645 /* 1 if the assembler should add BND prefix for all control-transferring
646 instructions supporting it, even if this prefix wasn't specified
648 static int add_bnd_prefix
= 0;
650 /* 1 if pseudo index register, eiz/riz, is allowed . */
651 static int allow_index_reg
= 0;
653 /* 1 if the assembler should ignore LOCK prefix, even if it was
654 specified explicitly. */
655 static int omit_lock_prefix
= 0;
657 /* 1 if the assembler should encode lfence, mfence, and sfence as
658 "lock addl $0, (%{re}sp)". */
659 static int avoid_fence
= 0;
661 /* 1 if lfence should be inserted after every load. */
662 static int lfence_after_load
= 0;
664 /* Non-zero if lfence should be inserted before indirect branch. */
665 static enum lfence_before_indirect_branch_kind
667 lfence_branch_none
= 0,
668 lfence_branch_register
,
669 lfence_branch_memory
,
672 lfence_before_indirect_branch
;
674 /* Non-zero if lfence should be inserted before ret. */
675 static enum lfence_before_ret_kind
677 lfence_before_ret_none
= 0,
678 lfence_before_ret_not
,
679 lfence_before_ret_or
,
680 lfence_before_ret_shl
684 /* Types of previous instruction is .byte or prefix. */
699 /* 1 if the assembler should generate relax relocations. */
701 static int generate_relax_relocations
702 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
704 static enum check_kind
710 sse_check
, operand_check
= check_warning
;
712 /* Non-zero if branches should be aligned within power of 2 boundary. */
713 static int align_branch_power
= 0;
715 /* Types of branches to align. */
716 enum align_branch_kind
718 align_branch_none
= 0,
719 align_branch_jcc
= 1,
720 align_branch_fused
= 2,
721 align_branch_jmp
= 3,
722 align_branch_call
= 4,
723 align_branch_indirect
= 5,
727 /* Type bits of branches to align. */
728 enum align_branch_bit
730 align_branch_jcc_bit
= 1 << align_branch_jcc
,
731 align_branch_fused_bit
= 1 << align_branch_fused
,
732 align_branch_jmp_bit
= 1 << align_branch_jmp
,
733 align_branch_call_bit
= 1 << align_branch_call
,
734 align_branch_indirect_bit
= 1 << align_branch_indirect
,
735 align_branch_ret_bit
= 1 << align_branch_ret
738 static unsigned int align_branch
= (align_branch_jcc_bit
739 | align_branch_fused_bit
740 | align_branch_jmp_bit
);
742 /* Types of condition jump used by macro-fusion. */
745 mf_jcc_jo
= 0, /* base opcode 0x70 */
746 mf_jcc_jc
, /* base opcode 0x72 */
747 mf_jcc_je
, /* base opcode 0x74 */
748 mf_jcc_jna
, /* base opcode 0x76 */
749 mf_jcc_js
, /* base opcode 0x78 */
750 mf_jcc_jp
, /* base opcode 0x7a */
751 mf_jcc_jl
, /* base opcode 0x7c */
752 mf_jcc_jle
, /* base opcode 0x7e */
755 /* Types of compare flag-modifying insntructions used by macro-fusion. */
758 mf_cmp_test_and
, /* test/cmp */
759 mf_cmp_alu_cmp
, /* add/sub/cmp */
760 mf_cmp_incdec
/* inc/dec */
763 /* The maximum padding size for fused jcc. CMP like instruction can
764 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
766 #define MAX_FUSED_JCC_PADDING_SIZE 20
768 /* The maximum number of prefixes added for an instruction. */
769 static unsigned int align_branch_prefix_size
= 5;
772 1. Clear the REX_W bit with register operand if possible.
773 2. Above plus use 128bit vector instruction to clear the full vector
776 static int optimize
= 0;
779 1. Clear the REX_W bit with register operand if possible.
780 2. Above plus use 128bit vector instruction to clear the full vector
782 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
785 static int optimize_for_space
= 0;
787 /* Register prefix used for error message. */
788 static const char *register_prefix
= "%";
790 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
791 leave, push, and pop instructions so that gcc has the same stack
792 frame as in 32 bit mode. */
793 static char stackop_size
= '\0';
795 /* Non-zero to optimize code alignment. */
796 int optimize_align_code
= 1;
798 /* Non-zero to quieten some warnings. */
799 static int quiet_warnings
= 0;
801 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
802 static bool pre_386_16bit_warned
;
805 static const char *cpu_arch_name
= NULL
;
806 static char *cpu_sub_arch_name
= NULL
;
808 /* CPU feature flags. */
809 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
811 /* If we have selected a cpu we are generating instructions for. */
812 static int cpu_arch_tune_set
= 0;
814 /* Cpu we are generating instructions for. */
815 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
817 /* CPU feature flags of cpu we are generating instructions for. */
818 static i386_cpu_flags cpu_arch_tune_flags
;
820 /* CPU instruction set architecture used. */
821 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
823 /* CPU feature flags of instruction set architecture used. */
824 i386_cpu_flags cpu_arch_isa_flags
;
826 /* If set, conditional jumps are not automatically promoted to handle
827 larger than a byte offset. */
828 static bool no_cond_jump_promotion
= false;
830 /* This will be set from an expression parser hook if there's any
831 applicable operator involved in an expression. */
834 expr_operator_present
,
838 /* Encode SSE instructions with VEX prefix. */
839 static unsigned int sse2avx
;
841 /* Encode aligned vector move as unaligned vector move. */
842 static unsigned int use_unaligned_vector_move
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
978 static const arch_entry cpu_arch
[] =
980 /* Do not replace the first two entries - i386_target_format() and
981 set_cpu_arch() rely on them being there in this order. */
982 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
983 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
984 ARCH (i8086
, UNKNOWN
, NONE
, false),
985 ARCH (i186
, UNKNOWN
, 186, false),
986 ARCH (i286
, UNKNOWN
, 286, false),
987 ARCH (i386
, I386
, 386, false),
988 ARCH (i486
, I486
, 486, false),
989 ARCH (i586
, PENTIUM
, 586, false),
990 ARCH (i686
, PENTIUMPRO
, 686, false),
991 ARCH (pentium
, PENTIUM
, 586, false),
992 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
993 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
994 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
995 ARCH (pentium4
, PENTIUM4
, P4
, false),
996 ARCH (prescott
, NOCONA
, CORE
, false),
997 ARCH (nocona
, NOCONA
, NOCONA
, false),
998 ARCH (yonah
, CORE
, CORE
, true),
999 ARCH (core
, CORE
, CORE
, false),
1000 ARCH (merom
, CORE2
, CORE2
, true),
1001 ARCH (core2
, CORE2
, CORE2
, false),
1002 ARCH (corei7
, COREI7
, COREI7
, false),
1003 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1004 ARCH (k6
, K6
, K6
, false),
1005 ARCH (k6_2
, K6
, K6_2
, false),
1006 ARCH (athlon
, ATHLON
, ATHLON
, false),
1007 ARCH (sledgehammer
, K8
, K8
, true),
1008 ARCH (opteron
, K8
, K8
, false),
1009 ARCH (k8
, K8
, K8
, false),
1010 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1011 ARCH (bdver1
, BD
, BDVER1
, false),
1012 ARCH (bdver2
, BD
, BDVER2
, false),
1013 ARCH (bdver3
, BD
, BDVER3
, false),
1014 ARCH (bdver4
, BD
, BDVER4
, false),
1015 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1016 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1017 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1018 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1019 ARCH (btver1
, BT
, BTVER1
, false),
1020 ARCH (btver2
, BT
, BTVER2
, false),
1022 SUBARCH (8087, 8087, ANY_8087
, false),
1023 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1024 SUBARCH (287, 287, ANY_287
, false),
1025 SUBARCH (387, 387, ANY_387
, false),
1026 SUBARCH (687, 687, ANY_687
, false),
1027 SUBARCH (cmov
, CMOV
, CMOV
, false),
1028 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1029 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1030 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1031 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1032 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1033 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1034 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1035 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1036 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1037 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1038 SUBARCH (avx
, AVX
, ANY_AVX
, false),
1039 SUBARCH (avx2
, AVX2
, ANY_AVX2
, false),
1040 SUBARCH (avx512f
, AVX512F
, ANY_AVX512F
, false),
1041 SUBARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, false),
1042 SUBARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, false),
1043 SUBARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, false),
1044 SUBARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, false),
1045 SUBARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, false),
1046 SUBARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, false),
1047 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1048 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1049 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1050 SUBARCH (smx
, SMX
, SMX
, false),
1051 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1052 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1053 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1054 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1055 SUBARCH (aes
, AES
, ANY_AES
, false),
1056 SUBARCH (pclmul
, PCLMUL
, ANY_PCLMUL
, false),
1057 SUBARCH (clmul
, PCLMUL
, ANY_PCLMUL
, true),
1058 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1059 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1060 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1061 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1062 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1063 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1064 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1065 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1066 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1067 SUBARCH (cx16
, CX16
, CX16
, false),
1068 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1069 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1070 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1071 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1072 SUBARCH (hle
, HLE
, HLE
, false),
1073 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1074 SUBARCH (tsx
, TSX
, TSX
, false),
1075 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1076 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1077 SUBARCH (nop
, NOP
, NOP
, false),
1078 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1079 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1080 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1081 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1082 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1083 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1084 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1085 SUBARCH (abm
, ABM
, ABM
, false),
1086 SUBARCH (bmi
, BMI
, BMI
, false),
1087 SUBARCH (tbm
, TBM
, TBM
, false),
1088 SUBARCH (adx
, ADX
, ADX
, false),
1089 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1090 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1091 SUBARCH (smap
, SMAP
, SMAP
, false),
1092 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1093 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1094 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1095 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1096 SUBARCH (se1
, SE1
, SE1
, false),
1097 SUBARCH (clwb
, CLWB
, CLWB
, false),
1098 SUBARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, false),
1099 SUBARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, false),
1100 SUBARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, false),
1101 SUBARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, false),
1102 SUBARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, false),
1103 SUBARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, false),
1104 SUBARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, false),
1105 SUBARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, false),
1106 SUBARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, false),
1107 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1108 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1109 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1110 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1111 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1112 SUBARCH (ibt
, IBT
, IBT
, false),
1113 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1114 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1115 SUBARCH (vaes
, VAES
, ANY_VAES
, false),
1116 SUBARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, false),
1117 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1118 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1119 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1120 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1121 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1122 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1123 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1124 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1125 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1126 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1127 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1128 SUBARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, false),
1129 SUBARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1130 ANY_AVX512_VP2INTERSECT
, false),
1131 SUBARCH (tdx
, TDX
, TDX
, false),
1132 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1133 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1134 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1135 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1136 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1137 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1138 SUBARCH (kl
, KL
, ANY_KL
, false),
1139 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1140 SUBARCH (uintr
, UINTR
, UINTR
, false),
1141 SUBARCH (hreset
, HRESET
, HRESET
, false),
1142 SUBARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, false),
1143 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1144 SUBARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, false),
1145 SUBARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, false),
1146 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1147 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1148 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1149 SUBARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, false),
1150 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1151 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1158 /* Like s_lcomm_internal in gas/read.c but the alignment string
1159 is allowed to be optional. */
1162 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1169 && *input_line_pointer
== ',')
1171 align
= parse_align (needs_align
- 1);
1173 if (align
== (addressT
) -1)
1188 bss_alloc (symbolP
, size
, align
);
1193 pe_lcomm (int needs_align
)
1195 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1199 const pseudo_typeS md_pseudo_table
[] =
1201 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1202 {"align", s_align_bytes
, 0},
1204 {"align", s_align_ptwo
, 0},
1206 {"arch", set_cpu_arch
, 0},
1210 {"lcomm", pe_lcomm
, 1},
1212 {"ffloat", float_cons
, 'f'},
1213 {"dfloat", float_cons
, 'd'},
1214 {"tfloat", float_cons
, 'x'},
1215 {"hfloat", float_cons
, 'h'},
1216 {"bfloat16", float_cons
, 'b'},
1218 {"slong", signed_cons
, 4},
1219 {"insn", s_insn
, 0},
1220 {"noopt", s_ignore
, 0},
1221 {"optim", s_ignore
, 0},
1222 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1223 {"code16", set_code_flag
, CODE_16BIT
},
1224 {"code32", set_code_flag
, CODE_32BIT
},
1226 {"code64", set_code_flag
, CODE_64BIT
},
1228 {"intel_syntax", set_intel_syntax
, 1},
1229 {"att_syntax", set_intel_syntax
, 0},
1230 {"intel_mnemonic", set_intel_mnemonic
, 1},
1231 {"att_mnemonic", set_intel_mnemonic
, 0},
1232 {"allow_index_reg", set_allow_index_reg
, 1},
1233 {"disallow_index_reg", set_allow_index_reg
, 0},
1234 {"sse_check", set_check
, 0},
1235 {"operand_check", set_check
, 1},
1236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1237 {"largecomm", handle_large_common
, 0},
1239 {"file", dwarf2_directive_file
, 0},
1240 {"loc", dwarf2_directive_loc
, 0},
1241 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1244 {"secrel32", pe_directive_secrel
, 0},
1245 {"secidx", pe_directive_secidx
, 0},
1250 /* For interface with expression (). */
1251 extern char *input_line_pointer
;
1253 /* Hash table for instruction mnemonic lookup. */
1254 static htab_t op_hash
;
1256 /* Hash table for register lookup. */
1257 static htab_t reg_hash
;
1259 /* Various efficient no-op patterns for aligning code labels.
1260 Note: Don't try to assemble the instructions in the comments.
1261 0L and 0w are not legal. */
1262 static const unsigned char f32_1
[] =
1264 static const unsigned char f32_2
[] =
1265 {0x66,0x90}; /* xchg %ax,%ax */
1266 static const unsigned char f32_3
[] =
1267 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1268 static const unsigned char f32_4
[] =
1269 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1270 static const unsigned char f32_6
[] =
1271 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1272 static const unsigned char f32_7
[] =
1273 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1274 static const unsigned char f16_3
[] =
1275 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1276 static const unsigned char f16_4
[] =
1277 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1278 static const unsigned char jump_disp8
[] =
1279 {0xeb}; /* jmp disp8 */
1280 static const unsigned char jump32_disp32
[] =
1281 {0xe9}; /* jmp disp32 */
1282 static const unsigned char jump16_disp32
[] =
1283 {0x66,0xe9}; /* jmp disp32 */
1284 /* 32-bit NOPs patterns. */
1285 static const unsigned char *const f32_patt
[] = {
1286 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1288 /* 16-bit NOPs patterns. */
1289 static const unsigned char *const f16_patt
[] = {
1290 f32_1
, f32_2
, f16_3
, f16_4
1292 /* nopl (%[re]ax) */
1293 static const unsigned char alt_3
[] =
1295 /* nopl 0(%[re]ax) */
1296 static const unsigned char alt_4
[] =
1297 {0x0f,0x1f,0x40,0x00};
1298 /* nopl 0(%[re]ax,%[re]ax,1) */
1299 static const unsigned char alt_5
[] =
1300 {0x0f,0x1f,0x44,0x00,0x00};
1301 /* nopw 0(%[re]ax,%[re]ax,1) */
1302 static const unsigned char alt_6
[] =
1303 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1304 /* nopl 0L(%[re]ax) */
1305 static const unsigned char alt_7
[] =
1306 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1307 /* nopl 0L(%[re]ax,%[re]ax,1) */
1308 static const unsigned char alt_8
[] =
1309 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1310 /* nopw 0L(%[re]ax,%[re]ax,1) */
1311 static const unsigned char alt_9
[] =
1312 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1313 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1314 static const unsigned char alt_10
[] =
1315 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1316 /* data16 nopw %cs:0L(%eax,%eax,1) */
1317 static const unsigned char alt_11
[] =
1318 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1319 /* 32-bit and 64-bit NOPs patterns. */
1320 static const unsigned char *const alt_patt
[] = {
1321 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1322 alt_9
, alt_10
, alt_11
1325 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1326 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1329 i386_output_nops (char *where
, const unsigned char *const *patt
,
1330 int count
, int max_single_nop_size
)
1333 /* Place the longer NOP first. */
1336 const unsigned char *nops
;
1338 if (max_single_nop_size
< 1)
1340 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1341 max_single_nop_size
);
1345 nops
= patt
[max_single_nop_size
- 1];
1347 /* Use the smaller one if the requsted one isn't available. */
1350 max_single_nop_size
--;
1351 nops
= patt
[max_single_nop_size
- 1];
1354 last
= count
% max_single_nop_size
;
1357 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1358 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1362 nops
= patt
[last
- 1];
1365 /* Use the smaller one plus one-byte NOP if the needed one
1368 nops
= patt
[last
- 1];
1369 memcpy (where
+ offset
, nops
, last
);
1370 where
[offset
+ last
] = *patt
[0];
1373 memcpy (where
+ offset
, nops
, last
);
1378 fits_in_imm7 (offsetT num
)
1380 return (num
& 0x7f) == num
;
1384 fits_in_imm31 (offsetT num
)
1386 return (num
& 0x7fffffff) == num
;
1389 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1390 single NOP instruction LIMIT. */
1393 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1395 const unsigned char *const *patt
= NULL
;
1396 int max_single_nop_size
;
1397 /* Maximum number of NOPs before switching to jump over NOPs. */
1398 int max_number_of_nops
;
1400 switch (fragP
->fr_type
)
1405 case rs_machine_dependent
:
1406 /* Allow NOP padding for jumps and calls. */
1407 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1408 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1415 /* We need to decide which NOP sequence to use for 32bit and
1416 64bit. When -mtune= is used:
1418 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1419 PROCESSOR_GENERIC32, f32_patt will be used.
1420 2. For the rest, alt_patt will be used.
1422 When -mtune= isn't used, alt_patt will be used if
1423 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1426 When -march= or .arch is used, we can't use anything beyond
1427 cpu_arch_isa_flags. */
1429 if (flag_code
== CODE_16BIT
)
1432 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1433 /* Limit number of NOPs to 2 in 16-bit mode. */
1434 max_number_of_nops
= 2;
1438 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1440 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1441 switch (cpu_arch_tune
)
1443 case PROCESSOR_UNKNOWN
:
1444 /* We use cpu_arch_isa_flags to check if we SHOULD
1445 optimize with nops. */
1446 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1451 case PROCESSOR_PENTIUM4
:
1452 case PROCESSOR_NOCONA
:
1453 case PROCESSOR_CORE
:
1454 case PROCESSOR_CORE2
:
1455 case PROCESSOR_COREI7
:
1456 case PROCESSOR_GENERIC64
:
1458 case PROCESSOR_ATHLON
:
1460 case PROCESSOR_AMDFAM10
:
1462 case PROCESSOR_ZNVER
:
1466 case PROCESSOR_I386
:
1467 case PROCESSOR_I486
:
1468 case PROCESSOR_PENTIUM
:
1469 case PROCESSOR_PENTIUMPRO
:
1470 case PROCESSOR_IAMCU
:
1471 case PROCESSOR_GENERIC32
:
1474 case PROCESSOR_NONE
:
1480 switch (fragP
->tc_frag_data
.tune
)
1482 case PROCESSOR_UNKNOWN
:
1483 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1484 PROCESSOR_UNKNOWN. */
1488 case PROCESSOR_I386
:
1489 case PROCESSOR_I486
:
1490 case PROCESSOR_PENTIUM
:
1491 case PROCESSOR_IAMCU
:
1493 case PROCESSOR_ATHLON
:
1495 case PROCESSOR_AMDFAM10
:
1497 case PROCESSOR_ZNVER
:
1499 case PROCESSOR_GENERIC32
:
1500 /* We use cpu_arch_isa_flags to check if we CAN optimize
1502 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1507 case PROCESSOR_PENTIUMPRO
:
1508 case PROCESSOR_PENTIUM4
:
1509 case PROCESSOR_NOCONA
:
1510 case PROCESSOR_CORE
:
1511 case PROCESSOR_CORE2
:
1512 case PROCESSOR_COREI7
:
1513 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1518 case PROCESSOR_GENERIC64
:
1521 case PROCESSOR_NONE
:
1526 if (patt
== f32_patt
)
1528 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1529 /* Limit number of NOPs to 2 for older processors. */
1530 max_number_of_nops
= 2;
1534 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1535 /* Limit number of NOPs to 7 for newer processors. */
1536 max_number_of_nops
= 7;
1541 limit
= max_single_nop_size
;
1543 if (fragP
->fr_type
== rs_fill_nop
)
1545 /* Output NOPs for .nop directive. */
1546 if (limit
> max_single_nop_size
)
1548 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1549 _("invalid single nop size: %d "
1550 "(expect within [0, %d])"),
1551 limit
, max_single_nop_size
);
1555 else if (fragP
->fr_type
!= rs_machine_dependent
)
1556 fragP
->fr_var
= count
;
1558 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1560 /* Generate jump over NOPs. */
1561 offsetT disp
= count
- 2;
1562 if (fits_in_imm7 (disp
))
1564 /* Use "jmp disp8" if possible. */
1566 where
[0] = jump_disp8
[0];
1572 unsigned int size_of_jump
;
1574 if (flag_code
== CODE_16BIT
)
1576 where
[0] = jump16_disp32
[0];
1577 where
[1] = jump16_disp32
[1];
1582 where
[0] = jump32_disp32
[0];
1586 count
-= size_of_jump
+ 4;
1587 if (!fits_in_imm31 (count
))
1589 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1590 _("jump over nop padding out of range"));
1594 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1595 where
+= size_of_jump
+ 4;
1599 /* Generate multiple NOPs. */
1600 i386_output_nops (where
, patt
, count
, limit
);
1604 operand_type_all_zero (const union i386_operand_type
*x
)
1606 switch (ARRAY_SIZE(x
->array
))
1617 return !x
->array
[0];
1624 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1626 switch (ARRAY_SIZE(x
->array
))
1642 x
->bitfield
.class = ClassNone
;
1643 x
->bitfield
.instance
= InstanceNone
;
1647 operand_type_equal (const union i386_operand_type
*x
,
1648 const union i386_operand_type
*y
)
1650 switch (ARRAY_SIZE(x
->array
))
1653 if (x
->array
[2] != y
->array
[2])
1657 if (x
->array
[1] != y
->array
[1])
1661 return x
->array
[0] == y
->array
[0];
1669 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1671 switch (ARRAY_SIZE(x
->array
))
1690 return !x
->array
[0];
1697 cpu_flags_equal (const union i386_cpu_flags
*x
,
1698 const union i386_cpu_flags
*y
)
1700 switch (ARRAY_SIZE(x
->array
))
1703 if (x
->array
[4] != y
->array
[4])
1707 if (x
->array
[3] != y
->array
[3])
1711 if (x
->array
[2] != y
->array
[2])
1715 if (x
->array
[1] != y
->array
[1])
1719 return x
->array
[0] == y
->array
[0];
1727 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1729 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1730 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1733 static INLINE i386_cpu_flags
1734 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1736 switch (ARRAY_SIZE (x
.array
))
1739 x
.array
[4] &= y
.array
[4];
1742 x
.array
[3] &= y
.array
[3];
1745 x
.array
[2] &= y
.array
[2];
1748 x
.array
[1] &= y
.array
[1];
1751 x
.array
[0] &= y
.array
[0];
1759 static INLINE i386_cpu_flags
1760 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1762 switch (ARRAY_SIZE (x
.array
))
1765 x
.array
[4] |= y
.array
[4];
1768 x
.array
[3] |= y
.array
[3];
1771 x
.array
[2] |= y
.array
[2];
1774 x
.array
[1] |= y
.array
[1];
1777 x
.array
[0] |= y
.array
[0];
1785 static INLINE i386_cpu_flags
1786 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1788 switch (ARRAY_SIZE (x
.array
))
1791 x
.array
[4] &= ~y
.array
[4];
1794 x
.array
[3] &= ~y
.array
[3];
1797 x
.array
[2] &= ~y
.array
[2];
1800 x
.array
[1] &= ~y
.array
[1];
1803 x
.array
[0] &= ~y
.array
[0];
1811 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1813 #define CPU_FLAGS_ARCH_MATCH 0x1
1814 #define CPU_FLAGS_64BIT_MATCH 0x2
1816 #define CPU_FLAGS_PERFECT_MATCH \
1817 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1819 /* Return CPU flags match bits. */
1822 cpu_flags_match (const insn_template
*t
)
1824 i386_cpu_flags x
= t
->cpu_flags
;
1825 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1827 x
.bitfield
.cpu64
= 0;
1828 x
.bitfield
.cpuno64
= 0;
1830 if (cpu_flags_all_zero (&x
))
1832 /* This instruction is available on all archs. */
1833 match
|= CPU_FLAGS_ARCH_MATCH
;
1837 /* This instruction is available only on some archs. */
1838 i386_cpu_flags cpu
= cpu_arch_flags
;
1840 /* AVX512VL is no standalone feature - match it and then strip it. */
1841 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1843 x
.bitfield
.cpuavx512vl
= 0;
1845 /* AVX and AVX2 present at the same time express an operand size
1846 dependency - strip AVX2 for the purposes here. The operand size
1847 dependent check occurs in check_vecOperands(). */
1848 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1849 x
.bitfield
.cpuavx2
= 0;
1851 cpu
= cpu_flags_and (x
, cpu
);
1852 if (!cpu_flags_all_zero (&cpu
))
1854 if (x
.bitfield
.cpuavx
)
1856 /* We need to check a few extra flags with AVX. */
1857 if (cpu
.bitfield
.cpuavx
1858 && (!t
->opcode_modifier
.sse2avx
1859 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1860 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1861 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1862 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1863 match
|= CPU_FLAGS_ARCH_MATCH
;
1865 else if (x
.bitfield
.cpuavx512f
)
1867 /* We need to check a few extra flags with AVX512F. */
1868 if (cpu
.bitfield
.cpuavx512f
1869 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1870 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1871 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1872 match
|= CPU_FLAGS_ARCH_MATCH
;
1875 match
|= CPU_FLAGS_ARCH_MATCH
;
1881 static INLINE i386_operand_type
1882 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1884 if (x
.bitfield
.class != y
.bitfield
.class)
1885 x
.bitfield
.class = ClassNone
;
1886 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1887 x
.bitfield
.instance
= InstanceNone
;
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[2] &= y
.array
[2];
1895 x
.array
[1] &= y
.array
[1];
1898 x
.array
[0] &= y
.array
[0];
1906 static INLINE i386_operand_type
1907 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1909 gas_assert (y
.bitfield
.class == ClassNone
);
1910 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[2] &= ~y
.array
[2];
1918 x
.array
[1] &= ~y
.array
[1];
1921 x
.array
[0] &= ~y
.array
[0];
1929 static INLINE i386_operand_type
1930 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1932 gas_assert (x
.bitfield
.class == ClassNone
||
1933 y
.bitfield
.class == ClassNone
||
1934 x
.bitfield
.class == y
.bitfield
.class);
1935 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1936 y
.bitfield
.instance
== InstanceNone
||
1937 x
.bitfield
.instance
== y
.bitfield
.instance
);
1939 switch (ARRAY_SIZE (x
.array
))
1942 x
.array
[2] |= y
.array
[2];
1945 x
.array
[1] |= y
.array
[1];
1948 x
.array
[0] |= y
.array
[0];
1956 static INLINE i386_operand_type
1957 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1959 gas_assert (y
.bitfield
.class == ClassNone
);
1960 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1962 switch (ARRAY_SIZE (x
.array
))
1965 x
.array
[2] ^= y
.array
[2];
1968 x
.array
[1] ^= y
.array
[1];
1971 x
.array
[0] ^= y
.array
[0];
1979 static const i386_operand_type anydisp
= {
1980 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
1992 operand_type_check (i386_operand_type t
, enum operand_type c
)
1997 return t
.bitfield
.class == Reg
;
2000 return (t
.bitfield
.imm8
2004 || t
.bitfield
.imm32s
2005 || t
.bitfield
.imm64
);
2008 return (t
.bitfield
.disp8
2009 || t
.bitfield
.disp16
2010 || t
.bitfield
.disp32
2011 || t
.bitfield
.disp64
);
2014 return (t
.bitfield
.disp8
2015 || t
.bitfield
.disp16
2016 || t
.bitfield
.disp32
2017 || t
.bitfield
.disp64
2018 || t
.bitfield
.baseindex
);
2027 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2028 between operand GIVEN and opeand WANTED for instruction template T. */
2031 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2034 return !((i
.types
[given
].bitfield
.byte
2035 && !t
->operand_types
[wanted
].bitfield
.byte
)
2036 || (i
.types
[given
].bitfield
.word
2037 && !t
->operand_types
[wanted
].bitfield
.word
)
2038 || (i
.types
[given
].bitfield
.dword
2039 && !t
->operand_types
[wanted
].bitfield
.dword
)
2040 || (i
.types
[given
].bitfield
.qword
2041 && (!t
->operand_types
[wanted
].bitfield
.qword
2042 /* Don't allow 64-bit (memory) operands outside of 64-bit
2043 mode, when they're used where a 64-bit GPR could also
2044 be used. Checking is needed for Intel Syntax only. */
2046 && flag_code
!= CODE_64BIT
2047 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2048 || t
->operand_types
[wanted
].bitfield
.class == Accum
2049 || t
->opcode_modifier
.isstring
))))
2050 || (i
.types
[given
].bitfield
.tbyte
2051 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2054 /* Return 1 if there is no conflict in SIMD register between operand
2055 GIVEN and opeand WANTED for instruction template T. */
2058 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2061 return !((i
.types
[given
].bitfield
.xmmword
2062 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2063 || (i
.types
[given
].bitfield
.ymmword
2064 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2065 || (i
.types
[given
].bitfield
.zmmword
2066 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2067 || (i
.types
[given
].bitfield
.tmmword
2068 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2071 /* Return 1 if there is no conflict in any size between operand GIVEN
2072 and opeand WANTED for instruction template T. */
2075 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2078 return (match_operand_size (t
, wanted
, given
)
2079 && !((i
.types
[given
].bitfield
.unspecified
2080 && !i
.broadcast
.type
2081 && !i
.broadcast
.bytes
2082 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2083 || (i
.types
[given
].bitfield
.fword
2084 && !t
->operand_types
[wanted
].bitfield
.fword
)
2085 /* For scalar opcode templates to allow register and memory
2086 operands at the same time, some special casing is needed
2087 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2088 down-conversion vpmov*. */
2089 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2090 && t
->operand_types
[wanted
].bitfield
.byte
2091 + t
->operand_types
[wanted
].bitfield
.word
2092 + t
->operand_types
[wanted
].bitfield
.dword
2093 + t
->operand_types
[wanted
].bitfield
.qword
2094 > !!t
->opcode_modifier
.broadcast
)
2095 ? (i
.types
[given
].bitfield
.xmmword
2096 || i
.types
[given
].bitfield
.ymmword
2097 || i
.types
[given
].bitfield
.zmmword
)
2098 : !match_simd_size(t
, wanted
, given
))));
2101 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2102 operands for instruction template T, and it has MATCH_REVERSE set if there
2103 is no size conflict on any operands for the template with operands reversed
2104 (and the template allows for reversing in the first place). */
2106 #define MATCH_STRAIGHT 1
2107 #define MATCH_REVERSE 2
2109 static INLINE
unsigned int
2110 operand_size_match (const insn_template
*t
)
2112 unsigned int j
, match
= MATCH_STRAIGHT
;
2114 /* Don't check non-absolute jump instructions. */
2115 if (t
->opcode_modifier
.jump
2116 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2119 /* Check memory and accumulator operand size. */
2120 for (j
= 0; j
< i
.operands
; j
++)
2122 if (i
.types
[j
].bitfield
.class != Reg
2123 && i
.types
[j
].bitfield
.class != RegSIMD
2124 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2127 if (t
->operand_types
[j
].bitfield
.class == Reg
2128 && !match_operand_size (t
, j
, j
))
2134 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2135 && !match_simd_size (t
, j
, j
))
2141 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2142 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2148 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2155 if (!t
->opcode_modifier
.d
)
2158 /* Check reverse. */
2159 gas_assert (i
.operands
>= 2);
2161 for (j
= 0; j
< i
.operands
; j
++)
2163 unsigned int given
= i
.operands
- j
- 1;
2165 /* For FMA4 and XOP insns VEX.W controls just the first two
2166 register operands. */
2167 if (t
->cpu_flags
.bitfield
.cpufma4
|| t
->cpu_flags
.bitfield
.cpuxop
)
2168 given
= j
< 2 ? 1 - j
: j
;
2170 if (t
->operand_types
[j
].bitfield
.class == Reg
2171 && !match_operand_size (t
, j
, given
))
2174 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2175 && !match_simd_size (t
, j
, given
))
2178 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2179 && (!match_operand_size (t
, j
, given
)
2180 || !match_simd_size (t
, j
, given
)))
2183 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2187 return match
| MATCH_REVERSE
;
2191 operand_type_match (i386_operand_type overlap
,
2192 i386_operand_type given
)
2194 i386_operand_type temp
= overlap
;
2196 temp
.bitfield
.unspecified
= 0;
2197 temp
.bitfield
.byte
= 0;
2198 temp
.bitfield
.word
= 0;
2199 temp
.bitfield
.dword
= 0;
2200 temp
.bitfield
.fword
= 0;
2201 temp
.bitfield
.qword
= 0;
2202 temp
.bitfield
.tbyte
= 0;
2203 temp
.bitfield
.xmmword
= 0;
2204 temp
.bitfield
.ymmword
= 0;
2205 temp
.bitfield
.zmmword
= 0;
2206 temp
.bitfield
.tmmword
= 0;
2207 if (operand_type_all_zero (&temp
))
2210 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2214 i
.error
= operand_type_mismatch
;
2218 /* If given types g0 and g1 are registers they must be of the same type
2219 unless the expected operand type register overlap is null.
2220 Intel syntax sized memory operands are also checked here. */
2223 operand_type_register_match (i386_operand_type g0
,
2224 i386_operand_type t0
,
2225 i386_operand_type g1
,
2226 i386_operand_type t1
)
2228 if (g0
.bitfield
.class != Reg
2229 && g0
.bitfield
.class != RegSIMD
2230 && (g0
.bitfield
.unspecified
2231 || !operand_type_check (g0
, anymem
)))
2234 if (g1
.bitfield
.class != Reg
2235 && g1
.bitfield
.class != RegSIMD
2236 && (g1
.bitfield
.unspecified
2237 || !operand_type_check (g1
, anymem
)))
2240 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2241 && g0
.bitfield
.word
== g1
.bitfield
.word
2242 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2243 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2244 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2245 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2246 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2249 /* If expectations overlap in no more than a single size, all is fine. */
2250 g0
= operand_type_and (t0
, t1
);
2251 if (g0
.bitfield
.byte
2255 + g0
.bitfield
.xmmword
2256 + g0
.bitfield
.ymmword
2257 + g0
.bitfield
.zmmword
<= 1)
2260 i
.error
= register_type_mismatch
;
2265 static INLINE
unsigned int
2266 register_number (const reg_entry
*r
)
2268 unsigned int nr
= r
->reg_num
;
2270 if (r
->reg_flags
& RegRex
)
2273 if (r
->reg_flags
& RegVRex
)
2279 static INLINE
unsigned int
2280 mode_from_disp_size (i386_operand_type t
)
2282 if (t
.bitfield
.disp8
)
2284 else if (t
.bitfield
.disp16
2285 || t
.bitfield
.disp32
)
2292 fits_in_signed_byte (addressT num
)
2294 return num
+ 0x80 <= 0xff;
2298 fits_in_unsigned_byte (addressT num
)
2304 fits_in_unsigned_word (addressT num
)
2306 return num
<= 0xffff;
2310 fits_in_signed_word (addressT num
)
2312 return num
+ 0x8000 <= 0xffff;
2316 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2321 return num
+ 0x80000000 <= 0xffffffff;
2323 } /* fits_in_signed_long() */
2326 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2331 return num
<= 0xffffffff;
2333 } /* fits_in_unsigned_long() */
2335 static INLINE valueT
extend_to_32bit_address (addressT num
)
2338 if (fits_in_unsigned_long(num
))
2339 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2341 if (!fits_in_signed_long (num
))
2342 return num
& 0xffffffff;
2349 fits_in_disp8 (offsetT num
)
2351 int shift
= i
.memshift
;
2357 mask
= (1 << shift
) - 1;
2359 /* Return 0 if NUM isn't properly aligned. */
2363 /* Check if NUM will fit in 8bit after shift. */
2364 return fits_in_signed_byte (num
>> shift
);
2368 fits_in_imm4 (offsetT num
)
2370 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2371 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2374 static i386_operand_type
2375 smallest_imm_type (offsetT num
)
2377 i386_operand_type t
;
2379 operand_type_set (&t
, 0);
2380 t
.bitfield
.imm64
= 1;
2382 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2384 /* This code is disabled on the 486 because all the Imm1 forms
2385 in the opcode table are slower on the i486. They're the
2386 versions with the implicitly specified single-position
2387 displacement, which has another syntax if you really want to
2389 t
.bitfield
.imm1
= 1;
2390 t
.bitfield
.imm8
= 1;
2391 t
.bitfield
.imm8s
= 1;
2392 t
.bitfield
.imm16
= 1;
2393 t
.bitfield
.imm32
= 1;
2394 t
.bitfield
.imm32s
= 1;
2396 else if (fits_in_signed_byte (num
))
2398 if (fits_in_unsigned_byte (num
))
2399 t
.bitfield
.imm8
= 1;
2400 t
.bitfield
.imm8s
= 1;
2401 t
.bitfield
.imm16
= 1;
2402 t
.bitfield
.imm32
= 1;
2403 t
.bitfield
.imm32s
= 1;
2405 else if (fits_in_unsigned_byte (num
))
2407 t
.bitfield
.imm8
= 1;
2408 t
.bitfield
.imm16
= 1;
2409 t
.bitfield
.imm32
= 1;
2410 t
.bitfield
.imm32s
= 1;
2412 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2414 t
.bitfield
.imm16
= 1;
2415 t
.bitfield
.imm32
= 1;
2416 t
.bitfield
.imm32s
= 1;
2418 else if (fits_in_signed_long (num
))
2420 t
.bitfield
.imm32
= 1;
2421 t
.bitfield
.imm32s
= 1;
2423 else if (fits_in_unsigned_long (num
))
2424 t
.bitfield
.imm32
= 1;
2430 offset_in_range (offsetT val
, int size
)
2436 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2437 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2439 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2441 case sizeof (val
): return val
;
2445 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2446 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2447 (uint64_t) val
, (uint64_t) (val
& mask
));
2452 static INLINE
const char *insn_name (const insn_template
*t
)
2454 return &i386_mnemonics
[t
->mnem_off
];
2467 a. PREFIX_EXIST if attempting to add a prefix where one from the
2468 same class already exists.
2469 b. PREFIX_LOCK if lock prefix is added.
2470 c. PREFIX_REP if rep/repne prefix is added.
2471 d. PREFIX_DS if ds prefix is added.
2472 e. PREFIX_OTHER if other prefix is added.
2475 static enum PREFIX_GROUP
2476 add_prefix (unsigned int prefix
)
2478 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2481 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2482 && flag_code
== CODE_64BIT
)
2484 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2485 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2486 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2487 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2498 case DS_PREFIX_OPCODE
:
2501 case CS_PREFIX_OPCODE
:
2502 case ES_PREFIX_OPCODE
:
2503 case FS_PREFIX_OPCODE
:
2504 case GS_PREFIX_OPCODE
:
2505 case SS_PREFIX_OPCODE
:
2509 case REPNE_PREFIX_OPCODE
:
2510 case REPE_PREFIX_OPCODE
:
2515 case LOCK_PREFIX_OPCODE
:
2524 case ADDR_PREFIX_OPCODE
:
2528 case DATA_PREFIX_OPCODE
:
2532 if (i
.prefix
[q
] != 0)
2540 i
.prefix
[q
] |= prefix
;
2543 as_bad (_("same type of prefix used twice"));
2549 update_code_flag (int value
, int check
)
2551 PRINTF_LIKE ((*as_error
));
2553 flag_code
= (enum flag_code
) value
;
2554 if (flag_code
== CODE_64BIT
)
2556 cpu_arch_flags
.bitfield
.cpu64
= 1;
2557 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2561 cpu_arch_flags
.bitfield
.cpu64
= 0;
2562 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2564 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2567 as_error
= as_fatal
;
2570 (*as_error
) (_("64bit mode not supported on `%s'."),
2571 cpu_arch_name
? cpu_arch_name
: default_arch
);
2573 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2576 as_error
= as_fatal
;
2579 (*as_error
) (_("32bit mode not supported on `%s'."),
2580 cpu_arch_name
? cpu_arch_name
: default_arch
);
2582 stackop_size
= '\0';
2586 set_code_flag (int value
)
2588 update_code_flag (value
, 0);
2592 set_16bit_gcc_code_flag (int new_code_flag
)
2594 flag_code
= (enum flag_code
) new_code_flag
;
2595 if (flag_code
!= CODE_16BIT
)
2597 cpu_arch_flags
.bitfield
.cpu64
= 0;
2598 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2599 stackop_size
= LONG_MNEM_SUFFIX
;
2603 set_intel_syntax (int syntax_flag
)
2605 /* Find out if register prefixing is specified. */
2606 int ask_naked_reg
= 0;
2609 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2612 int e
= get_symbol_name (&string
);
2614 if (strcmp (string
, "prefix") == 0)
2616 else if (strcmp (string
, "noprefix") == 0)
2619 as_bad (_("bad argument to syntax directive."));
2620 (void) restore_line_pointer (e
);
2622 demand_empty_rest_of_line ();
2624 intel_syntax
= syntax_flag
;
2626 if (ask_naked_reg
== 0)
2627 allow_naked_reg
= (intel_syntax
2628 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2630 allow_naked_reg
= (ask_naked_reg
< 0);
2632 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2634 register_prefix
= allow_naked_reg
? "" : "%";
2638 set_intel_mnemonic (int mnemonic_flag
)
2640 intel_mnemonic
= mnemonic_flag
;
2644 set_allow_index_reg (int flag
)
2646 allow_index_reg
= flag
;
2650 set_check (int what
)
2652 enum check_kind
*kind
;
2657 kind
= &operand_check
;
2668 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2671 int e
= get_symbol_name (&string
);
2673 if (strcmp (string
, "none") == 0)
2675 else if (strcmp (string
, "warning") == 0)
2676 *kind
= check_warning
;
2677 else if (strcmp (string
, "error") == 0)
2678 *kind
= check_error
;
2680 as_bad (_("bad argument to %s_check directive."), str
);
2681 (void) restore_line_pointer (e
);
2684 as_bad (_("missing argument for %s_check directive"), str
);
2686 demand_empty_rest_of_line ();
2690 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2691 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2694 static const char *arch
;
2696 /* Intel MCU is only supported on ELF. */
2702 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2703 use default_arch. */
2704 arch
= cpu_arch_name
;
2706 arch
= default_arch
;
2709 /* If we are targeting Intel MCU, we must enable it. */
2710 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2711 == new_flag
.bitfield
.cpuiamcu
)
2714 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2719 extend_cpu_sub_arch_name (const char *name
)
2721 if (cpu_sub_arch_name
)
2722 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2723 ".", name
, (const char *) NULL
);
2725 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2729 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2731 typedef struct arch_stack_entry
2733 const struct arch_stack_entry
*prev
;
2736 i386_cpu_flags flags
;
2737 i386_cpu_flags isa_flags
;
2738 enum processor_type isa
;
2739 enum flag_code flag_code
;
2741 bool no_cond_jump_promotion
;
2743 static const arch_stack_entry
*arch_stack_top
;
2747 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2750 int e
= get_symbol_name (&s
);
2751 const char *string
= s
;
2753 i386_cpu_flags flags
;
2755 if (strcmp (string
, "default") == 0)
2757 if (strcmp (default_arch
, "iamcu") == 0)
2758 string
= default_arch
;
2761 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2763 cpu_arch_name
= NULL
;
2764 free (cpu_sub_arch_name
);
2765 cpu_sub_arch_name
= NULL
;
2766 cpu_arch_flags
= cpu_unknown_flags
;
2767 if (flag_code
== CODE_64BIT
)
2769 cpu_arch_flags
.bitfield
.cpu64
= 1;
2770 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2774 cpu_arch_flags
.bitfield
.cpu64
= 0;
2775 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2777 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2778 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2779 if (!cpu_arch_tune_set
)
2781 cpu_arch_tune
= cpu_arch_isa
;
2782 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2785 j
= ARRAY_SIZE (cpu_arch
) + 1;
2788 else if (strcmp (string
, "push") == 0)
2790 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2792 top
->name
= cpu_arch_name
;
2793 if (cpu_sub_arch_name
)
2794 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2796 top
->sub_name
= NULL
;
2797 top
->flags
= cpu_arch_flags
;
2798 top
->isa
= cpu_arch_isa
;
2799 top
->isa_flags
= cpu_arch_isa_flags
;
2800 top
->flag_code
= flag_code
;
2801 top
->stackop_size
= stackop_size
;
2802 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2804 top
->prev
= arch_stack_top
;
2805 arch_stack_top
= top
;
2807 (void) restore_line_pointer (e
);
2808 demand_empty_rest_of_line ();
2811 else if (strcmp (string
, "pop") == 0)
2813 const arch_stack_entry
*top
= arch_stack_top
;
2816 as_bad (_(".arch stack is empty"));
2817 else if (top
->flag_code
!= flag_code
2818 || top
->stackop_size
!= stackop_size
)
2820 static const unsigned int bits
[] = {
2826 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2827 bits
[top
->flag_code
],
2828 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2832 arch_stack_top
= top
->prev
;
2834 cpu_arch_name
= top
->name
;
2835 free (cpu_sub_arch_name
);
2836 cpu_sub_arch_name
= top
->sub_name
;
2837 cpu_arch_flags
= top
->flags
;
2838 cpu_arch_isa
= top
->isa
;
2839 cpu_arch_isa_flags
= top
->isa_flags
;
2840 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2845 (void) restore_line_pointer (e
);
2846 demand_empty_rest_of_line ();
2850 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2852 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2853 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2857 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2859 cpu_arch_name
= cpu_arch
[j
].name
;
2860 free (cpu_sub_arch_name
);
2861 cpu_sub_arch_name
= NULL
;
2862 cpu_arch_flags
= cpu_arch
[j
].enable
;
2863 if (flag_code
== CODE_64BIT
)
2865 cpu_arch_flags
.bitfield
.cpu64
= 1;
2866 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2870 cpu_arch_flags
.bitfield
.cpu64
= 0;
2871 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2873 cpu_arch_isa
= cpu_arch
[j
].type
;
2874 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2875 if (!cpu_arch_tune_set
)
2877 cpu_arch_tune
= cpu_arch_isa
;
2878 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2880 pre_386_16bit_warned
= false;
2884 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2887 flags
= cpu_flags_or (cpu_arch_flags
,
2888 cpu_arch
[j
].enable
);
2890 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2892 extend_cpu_sub_arch_name (string
+ 1);
2893 cpu_arch_flags
= flags
;
2894 cpu_arch_isa_flags
= flags
;
2898 = cpu_flags_or (cpu_arch_isa_flags
,
2899 cpu_arch
[j
].enable
);
2900 (void) restore_line_pointer (e
);
2901 demand_empty_rest_of_line ();
2906 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
2908 /* Disable an ISA extension. */
2909 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2910 if (cpu_arch
[j
].type
== PROCESSOR_NONE
2911 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
2913 flags
= cpu_flags_and_not (cpu_arch_flags
,
2914 cpu_arch
[j
].disable
);
2915 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2917 extend_cpu_sub_arch_name (string
+ 1);
2918 cpu_arch_flags
= flags
;
2919 cpu_arch_isa_flags
= flags
;
2921 (void) restore_line_pointer (e
);
2922 demand_empty_rest_of_line ();
2927 if (j
== ARRAY_SIZE (cpu_arch
))
2928 as_bad (_("no such architecture: `%s'"), string
);
2930 *input_line_pointer
= e
;
2933 as_bad (_("missing cpu architecture"));
2935 no_cond_jump_promotion
= 0;
2936 if (*input_line_pointer
== ','
2937 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2942 ++input_line_pointer
;
2943 e
= get_symbol_name (&string
);
2945 if (strcmp (string
, "nojumps") == 0)
2946 no_cond_jump_promotion
= 1;
2947 else if (strcmp (string
, "jumps") == 0)
2950 as_bad (_("no such architecture modifier: `%s'"), string
);
2952 (void) restore_line_pointer (e
);
2955 demand_empty_rest_of_line ();
2958 enum bfd_architecture
2961 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2963 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2964 || flag_code
== CODE_64BIT
)
2965 as_fatal (_("Intel MCU is 32bit ELF only"));
2966 return bfd_arch_iamcu
;
2969 return bfd_arch_i386
;
2975 if (startswith (default_arch
, "x86_64"))
2977 if (default_arch
[6] == '\0')
2978 return bfd_mach_x86_64
;
2980 return bfd_mach_x64_32
;
2982 else if (!strcmp (default_arch
, "i386")
2983 || !strcmp (default_arch
, "iamcu"))
2985 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2987 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2988 as_fatal (_("Intel MCU is 32bit ELF only"));
2989 return bfd_mach_i386_iamcu
;
2992 return bfd_mach_i386_i386
;
2995 as_fatal (_("unknown architecture"));
2998 #include "opcodes/i386-tbl.h"
3003 /* Support pseudo prefixes like {disp32}. */
3004 lex_type
['{'] = LEX_BEGIN_NAME
;
3006 /* Initialize op_hash hash table. */
3007 op_hash
= str_htab_create ();
3010 const insn_template
*const *sets
= i386_op_sets
;
3011 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3013 /* Type checks to compensate for the conversion through void * which
3014 occurs during hash table insertion / lookup. */
3015 (void) sizeof (sets
== ¤t_templates
->start
);
3016 (void) sizeof (end
== ¤t_templates
->end
);
3017 for (; sets
< end
; ++sets
)
3018 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3019 as_fatal (_("duplicate %s"), insn_name (*sets
));
3022 /* Initialize reg_hash hash table. */
3023 reg_hash
= str_htab_create ();
3025 const reg_entry
*regtab
;
3026 unsigned int regtab_size
= i386_regtab_size
;
3028 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3030 switch (regtab
->reg_type
.bitfield
.class)
3033 if (regtab
->reg_type
.bitfield
.dword
)
3035 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3038 else if (regtab
->reg_type
.bitfield
.tbyte
)
3040 /* There's no point inserting st(<N>) in the hash table, as
3041 parentheses aren't included in register_chars[] anyway. */
3042 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3049 switch (regtab
->reg_num
)
3051 case 0: reg_es
= regtab
; break;
3052 case 2: reg_ss
= regtab
; break;
3053 case 3: reg_ds
= regtab
; break;
3058 if (!regtab
->reg_num
)
3063 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3064 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3068 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3073 for (c
= 0; c
< 256; c
++)
3075 if (ISDIGIT (c
) || ISLOWER (c
))
3077 mnemonic_chars
[c
] = c
;
3078 register_chars
[c
] = c
;
3079 operand_chars
[c
] = c
;
3081 else if (ISUPPER (c
))
3083 mnemonic_chars
[c
] = TOLOWER (c
);
3084 register_chars
[c
] = mnemonic_chars
[c
];
3085 operand_chars
[c
] = c
;
3087 else if (c
== '{' || c
== '}')
3089 mnemonic_chars
[c
] = c
;
3090 operand_chars
[c
] = c
;
3092 #ifdef SVR4_COMMENT_CHARS
3093 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3094 operand_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3102 operand_chars
['?'] = '?';
3104 mnemonic_chars
['_'] = '_';
3105 mnemonic_chars
['-'] = '-';
3106 mnemonic_chars
['.'] = '.';
3108 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3109 operand_chars
[(unsigned char) *p
] = *p
;
3112 if (flag_code
== CODE_64BIT
)
3114 #if defined (OBJ_COFF) && defined (TE_PE)
3115 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3118 x86_dwarf2_return_column
= 16;
3120 x86_cie_data_alignment
= -8;
3121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3122 x86_sframe_cfa_sp_reg
= 7;
3123 x86_sframe_cfa_fp_reg
= 6;
3128 x86_dwarf2_return_column
= 8;
3129 x86_cie_data_alignment
= -4;
3132 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3133 can be turned into BRANCH_PREFIX frag. */
3134 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3139 i386_print_statistics (FILE *file
)
3141 htab_print_statistics (file
, "i386 opcode", op_hash
);
3142 htab_print_statistics (file
, "i386 register", reg_hash
);
3148 htab_delete (op_hash
);
3149 htab_delete (reg_hash
);
3154 /* Debugging routines for md_assemble. */
3155 static void pte (insn_template
*);
3156 static void pt (i386_operand_type
);
3157 static void pe (expressionS
*);
3158 static void ps (symbolS
*);
3161 pi (const char *line
, i386_insn
*x
)
3165 fprintf (stdout
, "%s: template ", line
);
3167 fprintf (stdout
, " address: base %s index %s scale %x\n",
3168 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3169 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3170 x
->log2_scale_factor
);
3171 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3172 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3173 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3174 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3175 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3176 (x
->rex
& REX_W
) != 0,
3177 (x
->rex
& REX_R
) != 0,
3178 (x
->rex
& REX_X
) != 0,
3179 (x
->rex
& REX_B
) != 0);
3180 for (j
= 0; j
< x
->operands
; j
++)
3182 fprintf (stdout
, " #%d: ", j
+ 1);
3184 fprintf (stdout
, "\n");
3185 if (x
->types
[j
].bitfield
.class == Reg
3186 || x
->types
[j
].bitfield
.class == RegMMX
3187 || x
->types
[j
].bitfield
.class == RegSIMD
3188 || x
->types
[j
].bitfield
.class == RegMask
3189 || x
->types
[j
].bitfield
.class == SReg
3190 || x
->types
[j
].bitfield
.class == RegCR
3191 || x
->types
[j
].bitfield
.class == RegDR
3192 || x
->types
[j
].bitfield
.class == RegTR
3193 || x
->types
[j
].bitfield
.class == RegBND
)
3194 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3195 if (operand_type_check (x
->types
[j
], imm
))
3197 if (operand_type_check (x
->types
[j
], disp
))
3198 pe (x
->op
[j
].disps
);
3203 pte (insn_template
*t
)
3205 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3206 static const char *const opc_spc
[] = {
3207 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3208 "XOP08", "XOP09", "XOP0A",
3212 fprintf (stdout
, " %d operands ", t
->operands
);
3213 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3214 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3215 if (opc_spc
[t
->opcode_space
])
3216 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3217 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3218 if (t
->extension_opcode
!= None
)
3219 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3220 if (t
->opcode_modifier
.d
)
3221 fprintf (stdout
, "D");
3222 if (t
->opcode_modifier
.w
)
3223 fprintf (stdout
, "W");
3224 fprintf (stdout
, "\n");
3225 for (j
= 0; j
< t
->operands
; j
++)
3227 fprintf (stdout
, " #%d type ", j
+ 1);
3228 pt (t
->operand_types
[j
]);
3229 fprintf (stdout
, "\n");
3236 fprintf (stdout
, " operation %d\n", e
->X_op
);
3237 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3238 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3239 if (e
->X_add_symbol
)
3241 fprintf (stdout
, " add_symbol ");
3242 ps (e
->X_add_symbol
);
3243 fprintf (stdout
, "\n");
3247 fprintf (stdout
, " op_symbol ");
3248 ps (e
->X_op_symbol
);
3249 fprintf (stdout
, "\n");
3256 fprintf (stdout
, "%s type %s%s",
3258 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3259 segment_name (S_GET_SEGMENT (s
)));
3262 static struct type_name
3264 i386_operand_type mask
;
3267 const type_names
[] =
3269 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3270 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3271 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3272 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3273 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3274 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3275 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3276 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3277 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3278 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3279 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3280 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3281 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3282 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3283 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3284 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3285 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3286 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3287 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3288 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3289 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3290 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3291 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3292 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3293 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3294 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3295 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3296 { { .bitfield
= { .class = SReg
} }, "SReg" },
3297 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3298 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3299 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3300 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3301 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3302 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3306 pt (i386_operand_type t
)
3309 i386_operand_type a
;
3311 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3313 a
= operand_type_and (t
, type_names
[j
].mask
);
3314 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3315 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3320 #endif /* DEBUG386 */
3322 static bfd_reloc_code_real_type
3323 reloc (unsigned int size
,
3326 bfd_reloc_code_real_type other
)
3328 if (other
!= NO_RELOC
)
3330 reloc_howto_type
*rel
;
3335 case BFD_RELOC_X86_64_GOT32
:
3336 return BFD_RELOC_X86_64_GOT64
;
3338 case BFD_RELOC_X86_64_GOTPLT64
:
3339 return BFD_RELOC_X86_64_GOTPLT64
;
3341 case BFD_RELOC_X86_64_PLTOFF64
:
3342 return BFD_RELOC_X86_64_PLTOFF64
;
3344 case BFD_RELOC_X86_64_GOTPC32
:
3345 other
= BFD_RELOC_X86_64_GOTPC64
;
3347 case BFD_RELOC_X86_64_GOTPCREL
:
3348 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3350 case BFD_RELOC_X86_64_TPOFF32
:
3351 other
= BFD_RELOC_X86_64_TPOFF64
;
3353 case BFD_RELOC_X86_64_DTPOFF32
:
3354 other
= BFD_RELOC_X86_64_DTPOFF64
;
3360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3361 if (other
== BFD_RELOC_SIZE32
)
3364 other
= BFD_RELOC_SIZE64
;
3367 as_bad (_("there are no pc-relative size relocations"));
3373 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3374 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3377 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3379 as_bad (_("unknown relocation (%u)"), other
);
3380 else if (size
!= bfd_get_reloc_size (rel
))
3381 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3382 bfd_get_reloc_size (rel
),
3384 else if (pcrel
&& !rel
->pc_relative
)
3385 as_bad (_("non-pc-relative relocation for pc-relative field"));
3386 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3388 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3390 as_bad (_("relocated field and relocation type differ in signedness"));
3399 as_bad (_("there are no unsigned pc-relative relocations"));
3402 case 1: return BFD_RELOC_8_PCREL
;
3403 case 2: return BFD_RELOC_16_PCREL
;
3404 case 4: return BFD_RELOC_32_PCREL
;
3405 case 8: return BFD_RELOC_64_PCREL
;
3407 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3414 case 4: return BFD_RELOC_X86_64_32S
;
3419 case 1: return BFD_RELOC_8
;
3420 case 2: return BFD_RELOC_16
;
3421 case 4: return BFD_RELOC_32
;
3422 case 8: return BFD_RELOC_64
;
3424 as_bad (_("cannot do %s %u byte relocation"),
3425 sign
> 0 ? "signed" : "unsigned", size
);
3431 /* Here we decide which fixups can be adjusted to make them relative to
3432 the beginning of the section instead of the symbol. Basically we need
3433 to make sure that the dynamic relocations are done correctly, so in
3434 some cases we force the original symbol to be used. */
3437 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3443 /* Don't adjust pc-relative references to merge sections in 64-bit
3445 if (use_rela_relocations
3446 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3450 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3451 and changed later by validate_fix. */
3452 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3453 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3456 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3457 for size relocations. */
3458 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3459 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3460 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3461 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3462 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3487 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3488 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3495 want_disp32 (const insn_template
*t
)
3497 return flag_code
!= CODE_64BIT
3498 || i
.prefix
[ADDR_PREFIX
]
3499 || (t
->mnem_off
== MN_lea
3500 && (!i
.types
[1].bitfield
.qword
3501 || t
->opcode_modifier
.size
== SIZE32
));
3505 intel_float_operand (const char *mnemonic
)
3507 /* Note that the value returned is meaningful only for opcodes with (memory)
3508 operands, hence the code here is free to improperly handle opcodes that
3509 have no operands (for better performance and smaller code). */
3511 if (mnemonic
[0] != 'f')
3512 return 0; /* non-math */
3514 switch (mnemonic
[1])
3516 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3517 the fs segment override prefix not currently handled because no
3518 call path can make opcodes without operands get here */
3520 return 2 /* integer op */;
3522 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3523 return 3; /* fldcw/fldenv */
3526 if (mnemonic
[2] != 'o' /* fnop */)
3527 return 3; /* non-waiting control op */
3530 if (mnemonic
[2] == 's')
3531 return 3; /* frstor/frstpm */
3534 if (mnemonic
[2] == 'a')
3535 return 3; /* fsave */
3536 if (mnemonic
[2] == 't')
3538 switch (mnemonic
[3])
3540 case 'c': /* fstcw */
3541 case 'd': /* fstdw */
3542 case 'e': /* fstenv */
3543 case 's': /* fsts[gw] */
3549 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3550 return 0; /* fxsave/fxrstor are not really math ops */
3558 install_template (const insn_template
*t
)
3564 /* Note that for pseudo prefixes this produces a length of 1. But for them
3565 the length isn't interesting at all. */
3566 for (l
= 1; l
< 4; ++l
)
3567 if (!(t
->base_opcode
>> (8 * l
)))
3570 i
.opcode_length
= l
;
3573 /* Build the VEX prefix. */
3576 build_vex_prefix (const insn_template
*t
)
3578 unsigned int register_specifier
;
3579 unsigned int vector_length
;
3582 /* Check register specifier. */
3583 if (i
.vex
.register_specifier
)
3585 register_specifier
=
3586 ~register_number (i
.vex
.register_specifier
) & 0xf;
3587 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3590 register_specifier
= 0xf;
3592 /* Use 2-byte VEX prefix by swapping destination and source operand
3593 if there are more than 1 register operand. */
3594 if (i
.reg_operands
> 1
3595 && i
.vec_encoding
!= vex_encoding_vex3
3596 && i
.dir_encoding
== dir_encoding_default
3597 && i
.operands
== i
.reg_operands
3598 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3599 && i
.tm
.opcode_space
== SPACE_0F
3600 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3605 swap_2_operands (0, i
.operands
- 1);
3607 gas_assert (i
.rm
.mode
== 3);
3611 i
.rm
.regmem
= i
.rm
.reg
;
3614 if (i
.tm
.opcode_modifier
.d
)
3615 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3616 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3617 else /* Use the next insn. */
3618 install_template (&t
[1]);
3621 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3622 are no memory operands and at least 3 register ones. */
3623 if (i
.reg_operands
>= 3
3624 && i
.vec_encoding
!= vex_encoding_vex3
3625 && i
.reg_operands
== i
.operands
- i
.imm_operands
3626 && i
.tm
.opcode_modifier
.vex
3627 && i
.tm
.opcode_modifier
.commutative
3628 && (i
.tm
.opcode_modifier
.sse2avx
3629 || (optimize
> 1 && !i
.no_optimize
))
3631 && i
.vex
.register_specifier
3632 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3634 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3636 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3637 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3638 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3639 &i
.types
[i
.operands
- 3]));
3640 gas_assert (i
.rm
.mode
== 3);
3642 swap_2_operands (xchg
, xchg
+ 1);
3645 xchg
= i
.rm
.regmem
| 8;
3646 i
.rm
.regmem
= ~register_specifier
& 0xf;
3647 gas_assert (!(i
.rm
.regmem
& 8));
3648 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3649 register_specifier
= ~xchg
& 0xf;
3652 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3653 vector_length
= avxscalar
;
3654 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3656 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3662 /* Determine vector length from the last multi-length vector
3665 for (op
= t
->operands
; op
--;)
3666 if (t
->operand_types
[op
].bitfield
.xmmword
3667 && t
->operand_types
[op
].bitfield
.ymmword
3668 && i
.types
[op
].bitfield
.ymmword
)
3675 /* Check the REX.W bit and VEXW. */
3676 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3677 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3678 else if (i
.tm
.opcode_modifier
.vexw
)
3679 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3681 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3683 /* Use 2-byte VEX prefix if possible. */
3685 && i
.vec_encoding
!= vex_encoding_vex3
3686 && i
.tm
.opcode_space
== SPACE_0F
3687 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3689 /* 2-byte VEX prefix. */
3693 i
.vex
.bytes
[0] = 0xc5;
3695 /* Check the REX.R bit. */
3696 r
= (i
.rex
& REX_R
) ? 0 : 1;
3697 i
.vex
.bytes
[1] = (r
<< 7
3698 | register_specifier
<< 3
3699 | vector_length
<< 2
3700 | i
.tm
.opcode_modifier
.opcodeprefix
);
3704 /* 3-byte VEX prefix. */
3707 switch (i
.tm
.opcode_space
)
3712 i
.vex
.bytes
[0] = 0xc4;
3717 i
.vex
.bytes
[0] = 0x8f;
3723 /* The high 3 bits of the second VEX byte are 1's compliment
3724 of RXB bits from REX. */
3725 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3726 | (!dot_insn () ? i
.tm
.opcode_space
3727 : i
.insn_opcode_space
);
3729 i
.vex
.bytes
[2] = (w
<< 7
3730 | register_specifier
<< 3
3731 | vector_length
<< 2
3732 | i
.tm
.opcode_modifier
.opcodeprefix
);
3737 is_evex_encoding (const insn_template
*t
)
3739 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3740 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3741 || t
->opcode_modifier
.sae
;
3745 is_any_vex_encoding (const insn_template
*t
)
3747 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3751 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3753 unsigned int op
, bytes
;
3754 const i386_operand_type
*types
;
3756 if (i
.broadcast
.type
)
3757 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3759 gas_assert (intel_syntax
);
3761 for (op
= 0; op
< t
->operands
; ++op
)
3762 if (t
->operand_types
[op
].bitfield
.baseindex
)
3765 gas_assert (op
< t
->operands
);
3767 if (t
->opcode_modifier
.evex
3768 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3769 switch (i
.broadcast
.bytes
)
3772 if (t
->operand_types
[op
].bitfield
.word
)
3776 if (t
->operand_types
[op
].bitfield
.dword
)
3780 if (t
->operand_types
[op
].bitfield
.qword
)
3784 if (t
->operand_types
[op
].bitfield
.xmmword
)
3786 if (t
->operand_types
[op
].bitfield
.ymmword
)
3788 if (t
->operand_types
[op
].bitfield
.zmmword
)
3795 gas_assert (op
+ 1 < t
->operands
);
3797 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3798 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3799 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3801 types
= &i
.types
[op
+ 1];
3804 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3805 types
= &t
->operand_types
[op
];
3807 if (types
->bitfield
.zmmword
)
3809 else if (types
->bitfield
.ymmword
)
3815 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3816 insn_name (t
), bytes
* 8);
3821 /* Build the EVEX prefix. */
3824 build_evex_prefix (void)
3826 unsigned int register_specifier
, w
;
3827 rex_byte vrex_used
= 0;
3829 /* Check register specifier. */
3830 if (i
.vex
.register_specifier
)
3832 gas_assert ((i
.vrex
& REX_X
) == 0);
3834 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3835 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3836 register_specifier
+= 8;
3837 /* The upper 16 registers are encoded in the fourth byte of the
3839 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3840 i
.vex
.bytes
[3] = 0x8;
3841 register_specifier
= ~register_specifier
& 0xf;
3845 register_specifier
= 0xf;
3847 /* Encode upper 16 vector index register in the fourth byte of
3849 if (!(i
.vrex
& REX_X
))
3850 i
.vex
.bytes
[3] = 0x8;
3855 /* 4 byte EVEX prefix. */
3857 i
.vex
.bytes
[0] = 0x62;
3859 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3861 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3862 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3863 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3864 | (!dot_insn () ? i
.tm
.opcode_space
3865 : i
.insn_opcode_space
);
3867 /* The fifth bit of the second EVEX byte is 1's compliment of the
3868 REX_R bit in VREX. */
3869 if (!(i
.vrex
& REX_R
))
3870 i
.vex
.bytes
[1] |= 0x10;
3874 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3876 /* When all operands are registers, the REX_X bit in REX is not
3877 used. We reuse it to encode the upper 16 registers, which is
3878 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3879 as 1's compliment. */
3880 if ((i
.vrex
& REX_B
))
3883 i
.vex
.bytes
[1] &= ~0x40;
3887 /* EVEX instructions shouldn't need the REX prefix. */
3888 i
.vrex
&= ~vrex_used
;
3889 gas_assert (i
.vrex
== 0);
3891 /* Check the REX.W bit and VEXW. */
3892 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3893 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3894 else if (i
.tm
.opcode_modifier
.vexw
)
3895 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3897 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3899 /* The third byte of the EVEX prefix. */
3900 i
.vex
.bytes
[2] = ((w
<< 7)
3901 | (register_specifier
<< 3)
3902 | 4 /* Encode the U bit. */
3903 | i
.tm
.opcode_modifier
.opcodeprefix
);
3905 /* The fourth byte of the EVEX prefix. */
3906 /* The zeroing-masking bit. */
3907 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3908 i
.vex
.bytes
[3] |= 0x80;
3910 /* Don't always set the broadcast bit if there is no RC. */
3911 if (i
.rounding
.type
== rc_none
)
3913 /* Encode the vector length. */
3914 unsigned int vec_length
;
3916 if (!i
.tm
.opcode_modifier
.evex
3917 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3921 /* Determine vector length from the last multi-length vector
3923 for (op
= i
.operands
; op
--;)
3924 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3925 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3926 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3928 if (i
.types
[op
].bitfield
.zmmword
)
3930 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3933 else if (i
.types
[op
].bitfield
.ymmword
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3938 else if (i
.types
[op
].bitfield
.xmmword
)
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3943 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
3944 && op
== i
.broadcast
.operand
)
3946 switch (get_broadcast_bytes (&i
.tm
, true))
3949 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3952 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3955 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3964 if (op
>= MAX_OPERANDS
)
3968 switch (i
.tm
.opcode_modifier
.evex
)
3970 case EVEXLIG
: /* LL' is ignored */
3971 vec_length
= evexlig
<< 5;
3974 vec_length
= 0 << 5;
3977 vec_length
= 1 << 5;
3980 vec_length
= 2 << 5;
3985 vec_length
= 3 << 5;
3993 i
.vex
.bytes
[3] |= vec_length
;
3994 /* Encode the broadcast bit. */
3995 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
3996 i
.vex
.bytes
[3] |= 0x10;
3998 else if (i
.rounding
.type
!= saeonly
)
3999 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4001 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4004 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4008 process_immext (void)
4012 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4013 which is coded in the same place as an 8-bit immediate field
4014 would be. Here we fake an 8-bit immediate operand from the
4015 opcode suffix stored in tm.extension_opcode.
4017 AVX instructions also use this encoding, for some of
4018 3 argument instructions. */
4020 gas_assert (i
.imm_operands
<= 1
4022 || (is_any_vex_encoding (&i
.tm
)
4023 && i
.operands
<= 4)));
4025 exp
= &im_expressions
[i
.imm_operands
++];
4026 i
.op
[i
.operands
].imms
= exp
;
4027 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4029 exp
->X_op
= O_constant
;
4030 exp
->X_add_number
= i
.tm
.extension_opcode
;
4031 i
.tm
.extension_opcode
= None
;
4038 switch (i
.tm
.opcode_modifier
.prefixok
)
4046 as_bad (_("invalid instruction `%s' after `%s'"),
4047 insn_name (&i
.tm
), i
.hle_prefix
);
4050 if (i
.prefix
[LOCK_PREFIX
])
4052 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4056 case PrefixHLERelease
:
4057 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4059 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4063 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4065 as_bad (_("memory destination needed for instruction `%s'"
4066 " after `xrelease'"), insn_name (&i
.tm
));
4073 /* Encode aligned vector move as unaligned vector move. */
4076 encode_with_unaligned_vector_move (void)
4078 switch (i
.tm
.base_opcode
)
4080 case 0x28: /* Load instructions. */
4081 case 0x29: /* Store instructions. */
4082 /* movaps/movapd/vmovaps/vmovapd. */
4083 if (i
.tm
.opcode_space
== SPACE_0F
4084 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4085 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4087 case 0x6f: /* Load instructions. */
4088 case 0x7f: /* Store instructions. */
4089 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4090 if (i
.tm
.opcode_space
== SPACE_0F
4091 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4092 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4099 /* Try the shortest encoding by shortening operand size. */
4102 optimize_encoding (void)
4106 if (i
.tm
.mnem_off
== MN_lea
)
4109 lea symbol, %rN -> mov $symbol, %rN
4110 lea (%rM), %rN -> mov %rM, %rN
4111 lea (,%rM,1), %rN -> mov %rM, %rN
4113 and in 32-bit mode for 16-bit addressing
4115 lea (%rM), %rN -> movzx %rM, %rN
4117 and in 64-bit mode zap 32-bit addressing in favor of using a
4118 32-bit (or less) destination.
4120 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4122 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4123 i
.tm
.opcode_modifier
.size
= SIZE32
;
4124 i
.prefix
[ADDR_PREFIX
] = 0;
4127 if (!i
.index_reg
&& !i
.base_reg
)
4130 lea symbol, %rN -> mov $symbol, %rN
4132 if (flag_code
== CODE_64BIT
)
4134 /* Don't transform a relocation to a 16-bit one. */
4136 && i
.op
[0].disps
->X_op
!= O_constant
4137 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4140 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4141 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4143 i
.tm
.base_opcode
= 0xb8;
4144 i
.tm
.opcode_modifier
.modrm
= 0;
4145 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4146 i
.types
[0].bitfield
.imm32
= 1;
4149 i
.tm
.opcode_modifier
.size
= SIZE16
;
4150 i
.types
[0].bitfield
.imm16
= 1;
4155 /* Subject to further optimization below. */
4156 i
.tm
.base_opcode
= 0xc7;
4157 i
.tm
.extension_opcode
= 0;
4158 i
.types
[0].bitfield
.imm32s
= 1;
4159 i
.types
[0].bitfield
.baseindex
= 0;
4162 /* Outside of 64-bit mode address and operand sizes have to match if
4163 a relocation is involved, as otherwise we wouldn't (currently) or
4164 even couldn't express the relocation correctly. */
4165 else if (i
.op
[0].disps
4166 && i
.op
[0].disps
->X_op
!= O_constant
4167 && ((!i
.prefix
[ADDR_PREFIX
])
4168 != (flag_code
== CODE_32BIT
4169 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4170 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4172 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4173 destination is going to grow encoding size. */
4174 else if (flag_code
== CODE_16BIT
4175 && (optimize
<= 1 || optimize_for_space
)
4176 && !i
.prefix
[ADDR_PREFIX
]
4177 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4181 i
.tm
.base_opcode
= 0xb8;
4182 i
.tm
.opcode_modifier
.modrm
= 0;
4183 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4184 i
.types
[0].bitfield
.imm32
= 1;
4186 i
.types
[0].bitfield
.imm16
= 1;
4189 && i
.op
[0].disps
->X_op
== O_constant
4190 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4191 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4193 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4194 i
.op
[0].disps
->X_add_number
&= 0xffff;
4197 i
.tm
.operand_types
[0] = i
.types
[0];
4201 i
.op
[0].imms
= &im_expressions
[0];
4202 i
.op
[0].imms
->X_op
= O_absent
;
4205 else if (i
.op
[0].disps
4206 && (i
.op
[0].disps
->X_op
!= O_constant
4207 || i
.op
[0].disps
->X_add_number
))
4212 lea (%rM), %rN -> mov %rM, %rN
4213 lea (,%rM,1), %rN -> mov %rM, %rN
4214 lea (%rM), %rN -> movzx %rM, %rN
4216 const reg_entry
*addr_reg
;
4218 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4219 addr_reg
= i
.base_reg
;
4220 else if (!i
.base_reg
4221 && i
.index_reg
->reg_num
!= RegIZ
4222 && !i
.log2_scale_factor
)
4223 addr_reg
= i
.index_reg
;
4227 if (addr_reg
->reg_type
.bitfield
.word
4228 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4230 if (flag_code
!= CODE_32BIT
)
4232 i
.tm
.opcode_space
= SPACE_0F
;
4233 i
.tm
.base_opcode
= 0xb7;
4236 i
.tm
.base_opcode
= 0x8b;
4238 if (addr_reg
->reg_type
.bitfield
.dword
4239 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4240 i
.tm
.opcode_modifier
.size
= SIZE32
;
4242 i
.op
[0].regs
= addr_reg
;
4247 i
.disp_operands
= 0;
4248 i
.prefix
[ADDR_PREFIX
] = 0;
4249 i
.prefix
[SEG_PREFIX
] = 0;
4253 if (optimize_for_space
4254 && i
.tm
.mnem_off
== MN_test
4255 && i
.reg_operands
== 1
4256 && i
.imm_operands
== 1
4257 && !i
.types
[1].bitfield
.byte
4258 && i
.op
[0].imms
->X_op
== O_constant
4259 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4262 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4264 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4265 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4267 i
.types
[1].bitfield
.byte
= 1;
4268 /* Ignore the suffix. */
4270 /* Convert to byte registers. */
4271 if (i
.types
[1].bitfield
.word
)
4273 else if (i
.types
[1].bitfield
.dword
)
4277 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4282 else if (flag_code
== CODE_64BIT
4283 && i
.tm
.opcode_space
== SPACE_BASE
4284 && ((i
.types
[1].bitfield
.qword
4285 && i
.reg_operands
== 1
4286 && i
.imm_operands
== 1
4287 && i
.op
[0].imms
->X_op
== O_constant
4288 && ((i
.tm
.base_opcode
== 0xb8
4289 && i
.tm
.extension_opcode
== None
4290 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4291 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4292 && (i
.tm
.base_opcode
== 0x24
4293 || (i
.tm
.base_opcode
== 0x80
4294 && i
.tm
.extension_opcode
== 0x4)
4295 || i
.tm
.mnem_off
== MN_test
4296 || ((i
.tm
.base_opcode
| 1) == 0xc7
4297 && i
.tm
.extension_opcode
== 0x0)))
4298 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4299 && i
.tm
.base_opcode
== 0x83
4300 && i
.tm
.extension_opcode
== 0x4)))
4301 || (i
.types
[0].bitfield
.qword
4302 && ((i
.reg_operands
== 2
4303 && i
.op
[0].regs
== i
.op
[1].regs
4304 && (i
.tm
.mnem_off
== MN_xor
4305 || i
.tm
.mnem_off
== MN_sub
))
4306 || i
.tm
.mnem_off
== MN_clr
))))
4309 andq $imm31, %r64 -> andl $imm31, %r32
4310 andq $imm7, %r64 -> andl $imm7, %r32
4311 testq $imm31, %r64 -> testl $imm31, %r32
4312 xorq %r64, %r64 -> xorl %r32, %r32
4313 subq %r64, %r64 -> subl %r32, %r32
4314 movq $imm31, %r64 -> movl $imm31, %r32
4315 movq $imm32, %r64 -> movl $imm32, %r32
4317 i
.tm
.opcode_modifier
.size
= SIZE32
;
4320 i
.types
[0].bitfield
.imm32
= 1;
4321 i
.types
[0].bitfield
.imm32s
= 0;
4322 i
.types
[0].bitfield
.imm64
= 0;
4326 i
.types
[0].bitfield
.dword
= 1;
4327 i
.types
[0].bitfield
.qword
= 0;
4329 i
.types
[1].bitfield
.dword
= 1;
4330 i
.types
[1].bitfield
.qword
= 0;
4331 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4334 movq $imm31, %r64 -> movl $imm31, %r32
4335 movq $imm32, %r64 -> movl $imm32, %r32
4337 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4338 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4339 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4340 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4343 movq $imm31, %r64 -> movl $imm31, %r32
4345 i
.tm
.base_opcode
= 0xb8;
4346 i
.tm
.extension_opcode
= None
;
4347 i
.tm
.opcode_modifier
.w
= 0;
4348 i
.tm
.opcode_modifier
.modrm
= 0;
4352 else if (optimize
> 1
4353 && !optimize_for_space
4354 && i
.reg_operands
== 2
4355 && i
.op
[0].regs
== i
.op
[1].regs
4356 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4357 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4360 andb %rN, %rN -> testb %rN, %rN
4361 andw %rN, %rN -> testw %rN, %rN
4362 andq %rN, %rN -> testq %rN, %rN
4363 orb %rN, %rN -> testb %rN, %rN
4364 orw %rN, %rN -> testw %rN, %rN
4365 orq %rN, %rN -> testq %rN, %rN
4367 and outside of 64-bit mode
4369 andl %rN, %rN -> testl %rN, %rN
4370 orl %rN, %rN -> testl %rN, %rN
4372 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4374 else if (i
.tm
.base_opcode
== 0xba
4375 && i
.tm
.opcode_space
== SPACE_0F
4376 && i
.reg_operands
== 1
4377 && i
.op
[0].imms
->X_op
== O_constant
4378 && i
.op
[0].imms
->X_add_number
>= 0)
4381 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4382 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4383 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4385 With <BT> one of bts, btr, and bts also:
4386 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4387 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4392 if (i
.tm
.extension_opcode
!= 4)
4394 if (i
.types
[1].bitfield
.qword
4395 && i
.op
[0].imms
->X_add_number
< 32
4396 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4397 i
.tm
.opcode_modifier
.size
= SIZE32
;
4400 if (i
.types
[1].bitfield
.word
4401 && i
.op
[0].imms
->X_add_number
< 16)
4402 i
.tm
.opcode_modifier
.size
= SIZE32
;
4405 if (i
.op
[0].imms
->X_add_number
< 16)
4406 i
.tm
.opcode_modifier
.size
= SIZE16
;
4410 else if (i
.reg_operands
== 3
4411 && i
.op
[0].regs
== i
.op
[1].regs
4412 && !i
.types
[2].bitfield
.xmmword
4413 && (i
.tm
.opcode_modifier
.vex
4414 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4415 && is_evex_encoding (&i
.tm
)
4416 && (i
.vec_encoding
!= vex_encoding_evex
4417 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4418 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4419 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4420 && i
.types
[2].bitfield
.ymmword
))))
4421 && i
.tm
.opcode_space
== SPACE_0F
4422 && ((i
.tm
.base_opcode
| 2) == 0x57
4423 || i
.tm
.base_opcode
== 0xdf
4424 || i
.tm
.base_opcode
== 0xef
4425 || (i
.tm
.base_opcode
| 3) == 0xfb
4426 || i
.tm
.base_opcode
== 0x42
4427 || i
.tm
.base_opcode
== 0x47))
4430 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4432 EVEX VOP %zmmM, %zmmM, %zmmN
4433 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4434 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4435 EVEX VOP %ymmM, %ymmM, %ymmN
4436 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4437 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4438 VEX VOP %ymmM, %ymmM, %ymmN
4439 -> VEX VOP %xmmM, %xmmM, %xmmN
4440 VOP, one of vpandn and vpxor:
4441 VEX VOP %ymmM, %ymmM, %ymmN
4442 -> VEX VOP %xmmM, %xmmM, %xmmN
4443 VOP, one of vpandnd and vpandnq:
4444 EVEX VOP %zmmM, %zmmM, %zmmN
4445 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4446 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4447 EVEX VOP %ymmM, %ymmM, %ymmN
4448 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4449 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4450 VOP, one of vpxord and vpxorq:
4451 EVEX VOP %zmmM, %zmmM, %zmmN
4452 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4453 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4454 EVEX VOP %ymmM, %ymmM, %ymmN
4455 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4456 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4457 VOP, one of kxord and kxorq:
4458 VEX VOP %kM, %kM, %kN
4459 -> VEX kxorw %kM, %kM, %kN
4460 VOP, one of kandnd and kandnq:
4461 VEX VOP %kM, %kM, %kN
4462 -> VEX kandnw %kM, %kM, %kN
4464 if (is_evex_encoding (&i
.tm
))
4466 if (i
.vec_encoding
!= vex_encoding_evex
)
4468 i
.tm
.opcode_modifier
.vex
= VEX128
;
4469 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4470 i
.tm
.opcode_modifier
.evex
= 0;
4472 else if (optimize
> 1)
4473 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4477 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4479 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4480 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4483 i
.tm
.opcode_modifier
.vex
= VEX128
;
4485 if (i
.tm
.opcode_modifier
.vex
)
4486 for (j
= 0; j
< 3; j
++)
4488 i
.types
[j
].bitfield
.xmmword
= 1;
4489 i
.types
[j
].bitfield
.ymmword
= 0;
4492 else if (i
.vec_encoding
!= vex_encoding_evex
4493 && !i
.types
[0].bitfield
.zmmword
4494 && !i
.types
[1].bitfield
.zmmword
4496 && !i
.broadcast
.type
4497 && !i
.broadcast
.bytes
4498 && is_evex_encoding (&i
.tm
)
4499 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4500 || (i
.tm
.base_opcode
& ~4) == 0xdb
4501 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4502 && i
.tm
.extension_opcode
== None
)
4505 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4506 vmovdqu32 and vmovdqu64:
4507 EVEX VOP %xmmM, %xmmN
4508 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4509 EVEX VOP %ymmM, %ymmN
4510 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4512 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4514 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4516 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4518 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4519 VOP, one of vpand, vpandn, vpor, vpxor:
4520 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4521 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4522 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4523 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4524 EVEX VOP{d,q} mem, %xmmM, %xmmN
4525 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4526 EVEX VOP{d,q} mem, %ymmM, %ymmN
4527 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4529 for (j
= 0; j
< i
.operands
; j
++)
4530 if (operand_type_check (i
.types
[j
], disp
)
4531 && i
.op
[j
].disps
->X_op
== O_constant
)
4533 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4534 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4535 bytes, we choose EVEX Disp8 over VEX Disp32. */
4536 int evex_disp8
, vex_disp8
;
4537 unsigned int memshift
= i
.memshift
;
4538 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4540 evex_disp8
= fits_in_disp8 (n
);
4542 vex_disp8
= fits_in_disp8 (n
);
4543 if (evex_disp8
!= vex_disp8
)
4545 i
.memshift
= memshift
;
4549 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4552 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4553 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4554 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4555 i
.tm
.opcode_modifier
.vex
4556 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4557 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4558 /* VPAND, VPOR, and VPXOR are commutative. */
4559 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4560 i
.tm
.opcode_modifier
.commutative
= 1;
4561 i
.tm
.opcode_modifier
.evex
= 0;
4562 i
.tm
.opcode_modifier
.masking
= 0;
4563 i
.tm
.opcode_modifier
.broadcast
= 0;
4564 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4567 i
.types
[j
].bitfield
.disp8
4568 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4572 /* Return non-zero for load instruction. */
4578 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4579 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4583 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4584 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4585 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4589 if (i
.tm
.mnem_off
== MN_pop
)
4593 if (i
.tm
.opcode_space
== SPACE_BASE
)
4596 if (i
.tm
.base_opcode
== 0x9d
4597 || i
.tm
.base_opcode
== 0x61)
4600 /* movs, cmps, lods, scas. */
4601 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4605 if (base_opcode
== 0x6f
4606 || i
.tm
.base_opcode
== 0xd7)
4608 /* NB: For AMD-specific insns with implicit memory operands,
4609 they're intentionally not covered. */
4612 /* No memory operand. */
4613 if (!i
.mem_operands
)
4618 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4621 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4623 /* test, not, neg, mul, imul, div, idiv. */
4624 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4628 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4631 /* add, or, adc, sbb, and, sub, xor, cmp. */
4632 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4635 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4636 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4637 && i
.tm
.extension_opcode
!= 6)
4640 /* Check for x87 instructions. */
4641 if ((base_opcode
| 6) == 0xdf)
4643 /* Skip fst, fstp, fstenv, fstcw. */
4644 if (i
.tm
.base_opcode
== 0xd9
4645 && (i
.tm
.extension_opcode
== 2
4646 || i
.tm
.extension_opcode
== 3
4647 || i
.tm
.extension_opcode
== 6
4648 || i
.tm
.extension_opcode
== 7))
4651 /* Skip fisttp, fist, fistp, fstp. */
4652 if (i
.tm
.base_opcode
== 0xdb
4653 && (i
.tm
.extension_opcode
== 1
4654 || i
.tm
.extension_opcode
== 2
4655 || i
.tm
.extension_opcode
== 3
4656 || i
.tm
.extension_opcode
== 7))
4659 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4660 if (i
.tm
.base_opcode
== 0xdd
4661 && (i
.tm
.extension_opcode
== 1
4662 || i
.tm
.extension_opcode
== 2
4663 || i
.tm
.extension_opcode
== 3
4664 || i
.tm
.extension_opcode
== 6
4665 || i
.tm
.extension_opcode
== 7))
4668 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4669 if (i
.tm
.base_opcode
== 0xdf
4670 && (i
.tm
.extension_opcode
== 1
4671 || i
.tm
.extension_opcode
== 2
4672 || i
.tm
.extension_opcode
== 3
4673 || i
.tm
.extension_opcode
== 6
4674 || i
.tm
.extension_opcode
== 7))
4680 else if (i
.tm
.opcode_space
== SPACE_0F
)
4682 /* bt, bts, btr, btc. */
4683 if (i
.tm
.base_opcode
== 0xba
4684 && (i
.tm
.extension_opcode
| 3) == 7)
4687 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4688 if (i
.tm
.base_opcode
== 0xc7
4689 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4690 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4691 || i
.tm
.extension_opcode
== 6))
4694 /* fxrstor, ldmxcsr, xrstor. */
4695 if (i
.tm
.base_opcode
== 0xae
4696 && (i
.tm
.extension_opcode
== 1
4697 || i
.tm
.extension_opcode
== 2
4698 || i
.tm
.extension_opcode
== 5))
4701 /* lgdt, lidt, lmsw. */
4702 if (i
.tm
.base_opcode
== 0x01
4703 && (i
.tm
.extension_opcode
== 2
4704 || i
.tm
.extension_opcode
== 3
4705 || i
.tm
.extension_opcode
== 6))
4709 dest
= i
.operands
- 1;
4711 /* Check fake imm8 operand and 3 source operands. */
4712 if ((i
.tm
.opcode_modifier
.immext
4713 || i
.reg_operands
+ i
.mem_operands
== 4)
4714 && i
.types
[dest
].bitfield
.imm8
)
4717 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4718 if (i
.tm
.opcode_space
== SPACE_BASE
4719 && ((base_opcode
| 0x38) == 0x39
4720 || (base_opcode
| 2) == 0x87))
4723 if (i
.tm
.mnem_off
== MN_xadd
)
4726 /* Check for load instruction. */
4727 return (i
.types
[dest
].bitfield
.class != ClassNone
4728 || i
.types
[dest
].bitfield
.instance
== Accum
);
4731 /* Output lfence, 0xfaee8, after instruction. */
4734 insert_lfence_after (void)
4736 if (lfence_after_load
&& load_insn_p ())
4738 /* There are also two REP string instructions that require
4739 special treatment. Specifically, the compare string (CMPS)
4740 and scan string (SCAS) instructions set EFLAGS in a manner
4741 that depends on the data being compared/scanned. When used
4742 with a REP prefix, the number of iterations may therefore
4743 vary depending on this data. If the data is a program secret
4744 chosen by the adversary using an LVI method,
4745 then this data-dependent behavior may leak some aspect
4747 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4748 && i
.prefix
[REP_PREFIX
])
4750 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4753 char *p
= frag_more (3);
4760 /* Output lfence, 0xfaee8, before instruction. */
4763 insert_lfence_before (void)
4767 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4770 if (i
.tm
.base_opcode
== 0xff
4771 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4773 /* Insert lfence before indirect branch if needed. */
4775 if (lfence_before_indirect_branch
== lfence_branch_none
)
4778 if (i
.operands
!= 1)
4781 if (i
.reg_operands
== 1)
4783 /* Indirect branch via register. Don't insert lfence with
4784 -mlfence-after-load=yes. */
4785 if (lfence_after_load
4786 || lfence_before_indirect_branch
== lfence_branch_memory
)
4789 else if (i
.mem_operands
== 1
4790 && lfence_before_indirect_branch
!= lfence_branch_register
)
4792 as_warn (_("indirect `%s` with memory operand should be avoided"),
4799 if (last_insn
.kind
!= last_insn_other
4800 && last_insn
.seg
== now_seg
)
4802 as_warn_where (last_insn
.file
, last_insn
.line
,
4803 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4804 last_insn
.name
, insn_name (&i
.tm
));
4815 /* Output or/not/shl and lfence before near ret. */
4816 if (lfence_before_ret
!= lfence_before_ret_none
4817 && (i
.tm
.base_opcode
| 1) == 0xc3)
4819 if (last_insn
.kind
!= last_insn_other
4820 && last_insn
.seg
== now_seg
)
4822 as_warn_where (last_insn
.file
, last_insn
.line
,
4823 _("`%s` skips -mlfence-before-ret on `%s`"),
4824 last_insn
.name
, insn_name (&i
.tm
));
4828 /* Near ret ingore operand size override under CPU64. */
4829 char prefix
= flag_code
== CODE_64BIT
4831 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4833 if (lfence_before_ret
== lfence_before_ret_not
)
4835 /* not: 0xf71424, may add prefix
4836 for operand size override or 64-bit code. */
4837 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4851 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4854 if (lfence_before_ret
== lfence_before_ret_or
)
4856 /* or: 0x830c2400, may add prefix
4857 for operand size override or 64-bit code. */
4863 /* shl: 0xc1242400, may add prefix
4864 for operand size override or 64-bit code. */
4879 /* Shared helper for md_assemble() and s_insn(). */
4880 static void init_globals (void)
4884 memset (&i
, '\0', sizeof (i
));
4885 i
.rounding
.type
= rc_none
;
4886 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4887 i
.reloc
[j
] = NO_RELOC
;
4888 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4889 memset (im_expressions
, '\0', sizeof (im_expressions
));
4890 save_stack_p
= save_stack
;
4893 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
4894 parsing pass. Instead of introducing a rarely use new insn attribute this
4895 utilizes a common pattern between affected templates. It is deemed
4896 acceptable that this will lead to unnecessary pass 2 preparations in a
4897 limited set of cases. */
4898 static INLINE
bool may_need_pass2 (const insn_template
*t
)
4900 return t
->opcode_modifier
.sse2avx
4901 /* Note that all SSE2AVX templates have at least one operand. */
4902 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
4903 : (t
->opcode_space
== SPACE_0F
4904 && (t
->base_opcode
| 1) == 0xbf)
4905 || (t
->opcode_space
== SPACE_BASE
4906 && t
->base_opcode
== 0x63);
4909 /* This is the guts of the machine-dependent assembler. LINE points to a
4910 machine dependent instruction. This function is supposed to emit
4911 the frags/bytes it assembles to. */
4914 md_assemble (char *line
)
4917 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
4918 const char *end
, *pass1_mnem
= NULL
;
4919 enum i386_error pass1_err
= 0;
4920 const insn_template
*t
;
4922 /* Initialize globals. */
4923 current_templates
= NULL
;
4927 /* First parse an instruction mnemonic & call i386_operand for the operands.
4928 We assume that the scrubber has arranged it so that line[0] is the valid
4929 start of a (possibly prefixed) mnemonic. */
4931 end
= parse_insn (line
, mnemonic
, false);
4934 if (pass1_mnem
!= NULL
)
4936 if (i
.error
!= no_error
)
4938 gas_assert (current_templates
!= NULL
);
4939 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
4941 /* No point in trying a 2nd pass - it'll only find the same suffix
4943 mnem_suffix
= i
.suffix
;
4948 t
= current_templates
->start
;
4949 if (may_need_pass2 (t
))
4951 /* Make a copy of the full line in case we need to retry. */
4952 copy
= xstrdup (line
);
4955 mnem_suffix
= i
.suffix
;
4957 line
= parse_operands (line
, mnemonic
);
4965 /* Now we've parsed the mnemonic into a set of templates, and have the
4966 operands at hand. */
4968 /* All Intel opcodes have reversed operands except for "bound", "enter",
4969 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4970 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
4971 intersegment "jmp" and "call" instructions with 2 immediate operands so
4972 that the immediate segment precedes the offset consistently in Intel and
4976 && (t
->mnem_off
!= MN_bound
)
4977 && !startswith (mnemonic
, "invlpg")
4978 && !startswith (mnemonic
, "monitor")
4979 && !startswith (mnemonic
, "mwait")
4980 && (t
->mnem_off
!= MN_pvalidate
)
4981 && !startswith (mnemonic
, "rmp")
4982 && (t
->mnem_off
!= MN_tpause
)
4983 && (t
->mnem_off
!= MN_umwait
)
4984 && !(i
.operands
== 2
4985 && operand_type_check (i
.types
[0], imm
)
4986 && operand_type_check (i
.types
[1], imm
)))
4989 /* The order of the immediates should be reversed
4990 for 2 immediates extrq and insertq instructions */
4991 if (i
.imm_operands
== 2
4992 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
4993 swap_2_operands (0, 1);
4998 if (i
.disp_operands
&& !optimize_disp (t
))
5001 /* Next, we find a template that matches the given insn,
5002 making sure the overlap of the given operands types is consistent
5003 with the template operand types. */
5005 if (!(t
= match_template (mnem_suffix
)))
5007 const char *err_msg
;
5009 if (copy
&& !mnem_suffix
)
5014 pass1_err
= i
.error
;
5015 pass1_mnem
= insn_name (current_templates
->start
);
5019 /* If a non-/only-64bit template (group) was found in pass 1, and if
5020 _some_ template (group) was found in pass 2, squash pass 1's
5022 if (pass1_err
== unsupported_64bit
)
5028 switch (pass1_mnem
? pass1_err
: i
.error
)
5032 case operand_size_mismatch
:
5033 err_msg
= _("operand size mismatch");
5035 case operand_type_mismatch
:
5036 err_msg
= _("operand type mismatch");
5038 case register_type_mismatch
:
5039 err_msg
= _("register type mismatch");
5041 case number_of_operands_mismatch
:
5042 err_msg
= _("number of operands mismatch");
5044 case invalid_instruction_suffix
:
5045 err_msg
= _("invalid instruction suffix");
5048 err_msg
= _("constant doesn't fit in 4 bits");
5050 case unsupported_with_intel_mnemonic
:
5051 err_msg
= _("unsupported with Intel mnemonic");
5053 case unsupported_syntax
:
5054 err_msg
= _("unsupported syntax");
5057 as_bad (_("unsupported instruction `%s'"),
5058 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5060 case unsupported_on_arch
:
5061 as_bad (_("`%s' is not supported on `%s%s'"),
5062 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5063 cpu_arch_name
? cpu_arch_name
: default_arch
,
5064 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5066 case unsupported_64bit
:
5067 if (ISLOWER (mnem_suffix
))
5069 if (flag_code
== CODE_64BIT
)
5070 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5071 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5074 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5075 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5080 if (flag_code
== CODE_64BIT
)
5081 as_bad (_("`%s' is not supported in 64-bit mode"),
5082 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5084 as_bad (_("`%s' is only supported in 64-bit mode"),
5085 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5088 case invalid_sib_address
:
5089 err_msg
= _("invalid SIB address");
5091 case invalid_vsib_address
:
5092 err_msg
= _("invalid VSIB address");
5094 case invalid_vector_register_set
:
5095 err_msg
= _("mask, index, and destination registers must be distinct");
5097 case invalid_tmm_register_set
:
5098 err_msg
= _("all tmm registers must be distinct");
5100 case invalid_dest_and_src_register_set
:
5101 err_msg
= _("destination and source registers must be distinct");
5103 case unsupported_vector_index_register
:
5104 err_msg
= _("unsupported vector index register");
5106 case unsupported_broadcast
:
5107 err_msg
= _("unsupported broadcast");
5109 case broadcast_needed
:
5110 err_msg
= _("broadcast is needed for operand of such type");
5112 case unsupported_masking
:
5113 err_msg
= _("unsupported masking");
5115 case mask_not_on_destination
:
5116 err_msg
= _("mask not on destination operand");
5118 case no_default_mask
:
5119 err_msg
= _("default mask isn't allowed");
5121 case unsupported_rc_sae
:
5122 err_msg
= _("unsupported static rounding/sae");
5124 case invalid_register_operand
:
5125 err_msg
= _("invalid register operand");
5128 as_bad (_("%s for `%s'"), err_msg
,
5129 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5135 if (sse_check
!= check_none
5136 /* The opcode space check isn't strictly needed; it's there only to
5137 bypass the logic below when easily possible. */
5138 && t
->opcode_space
>= SPACE_0F
5139 && t
->opcode_space
<= SPACE_0F3A
5140 && !i
.tm
.cpu_flags
.bitfield
.cpusse4a
5141 && !is_any_vex_encoding (t
))
5145 for (j
= 0; j
< t
->operands
; ++j
)
5147 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5149 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5153 if (j
>= t
->operands
&& simd
)
5154 (sse_check
== check_warning
5156 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5159 if (i
.tm
.opcode_modifier
.fwait
)
5160 if (!add_prefix (FWAIT_OPCODE
))
5163 /* Check if REP prefix is OK. */
5164 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5166 as_bad (_("invalid instruction `%s' after `%s'"),
5167 insn_name (&i
.tm
), i
.rep_prefix
);
5171 /* Check for lock without a lockable instruction. Destination operand
5172 must be memory unless it is xchg (0x86). */
5173 if (i
.prefix
[LOCK_PREFIX
])
5175 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5176 || i
.mem_operands
== 0
5177 || (i
.tm
.base_opcode
!= 0x86
5178 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5180 as_bad (_("expecting lockable instruction after `lock'"));
5184 /* Zap the redundant prefix from XCHG when optimizing. */
5185 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5186 i
.prefix
[LOCK_PREFIX
] = 0;
5189 if (is_any_vex_encoding (&i
.tm
)
5190 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5191 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5193 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5194 if (i
.prefix
[DATA_PREFIX
])
5196 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5200 /* Don't allow e.g. KMOV in TLS code sequences. */
5201 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5204 case BFD_RELOC_386_TLS_GOTIE
:
5205 case BFD_RELOC_386_TLS_LE_32
:
5206 case BFD_RELOC_X86_64_GOTTPOFF
:
5207 case BFD_RELOC_X86_64_TLSLD
:
5208 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5215 /* Check if HLE prefix is OK. */
5216 if (i
.hle_prefix
&& !check_hle ())
5219 /* Check BND prefix. */
5220 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5221 as_bad (_("expecting valid branch instruction after `bnd'"));
5223 /* Check NOTRACK prefix. */
5224 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5225 as_bad (_("expecting indirect branch instruction after `notrack'"));
5227 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5229 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5230 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5231 else if (flag_code
!= CODE_16BIT
5232 ? i
.prefix
[ADDR_PREFIX
]
5233 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5234 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5237 /* Insert BND prefix. */
5238 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5240 if (!i
.prefix
[BND_PREFIX
])
5241 add_prefix (BND_PREFIX_OPCODE
);
5242 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5244 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5245 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5249 /* Check string instruction segment overrides. */
5250 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5252 gas_assert (i
.mem_operands
);
5253 if (!check_string ())
5255 i
.disp_operands
= 0;
5258 /* The memory operand of (%dx) should be only used with input/output
5259 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5260 if (i
.input_output_operand
5261 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5262 || i
.tm
.opcode_space
!= SPACE_BASE
))
5264 as_bad (_("input/output port address isn't allowed with `%s'"),
5269 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5270 optimize_encoding ();
5272 if (use_unaligned_vector_move
)
5273 encode_with_unaligned_vector_move ();
5275 if (!process_suffix ())
5278 /* Check if IP-relative addressing requirements can be satisfied. */
5279 if (i
.tm
.cpu_flags
.bitfield
.cpuprefetchi
5280 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5281 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5283 /* Update operand types and check extended states. */
5284 for (j
= 0; j
< i
.operands
; j
++)
5286 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5287 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5292 i
.xstate
|= xstate_mmx
;
5295 i
.xstate
|= xstate_mask
;
5298 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5299 i
.xstate
|= xstate_tmm
;
5300 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5301 i
.xstate
|= xstate_zmm
;
5302 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5303 i
.xstate
|= xstate_ymm
;
5304 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5305 i
.xstate
|= xstate_xmm
;
5310 /* Make still unresolved immediate matches conform to size of immediate
5311 given in i.suffix. */
5312 if (!finalize_imm ())
5315 if (i
.types
[0].bitfield
.imm1
)
5316 i
.imm_operands
= 0; /* kludge for shift insns. */
5318 /* For insns with operands there are more diddles to do to the opcode. */
5321 if (!process_operands ())
5324 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5326 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5327 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5330 if (is_any_vex_encoding (&i
.tm
))
5332 if (!cpu_arch_flags
.bitfield
.cpui286
)
5334 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5339 /* Check for explicit REX prefix. */
5340 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5342 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5346 if (i
.tm
.opcode_modifier
.vex
)
5347 build_vex_prefix (t
);
5349 build_evex_prefix ();
5351 /* The individual REX.RXBW bits got consumed. */
5352 i
.rex
&= REX_OPCODE
;
5355 /* Handle conversion of 'int $3' --> special int3 insn. */
5356 if (i
.tm
.mnem_off
== MN_int
5357 && i
.op
[0].imms
->X_add_number
== 3)
5359 i
.tm
.base_opcode
= INT3_OPCODE
;
5363 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5364 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5365 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5366 && i
.op
[0].disps
->X_op
== O_constant
)
5368 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5369 the absolute address given by the constant. Since ix86 jumps and
5370 calls are pc relative, we need to generate a reloc. */
5371 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5372 i
.op
[0].disps
->X_op
= O_symbol
;
5375 /* For 8 bit registers we need an empty rex prefix. Also if the
5376 instruction already has a prefix, we need to convert old
5377 registers to new ones. */
5379 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5380 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5381 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5382 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5383 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5384 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5389 i
.rex
|= REX_OPCODE
;
5390 for (x
= 0; x
< 2; x
++)
5392 /* Look for 8 bit operand that uses old registers. */
5393 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5394 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5396 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5397 /* In case it is "hi" register, give up. */
5398 if (i
.op
[x
].regs
->reg_num
> 3)
5399 as_bad (_("can't encode register '%s%s' in an "
5400 "instruction requiring REX prefix."),
5401 register_prefix
, i
.op
[x
].regs
->reg_name
);
5403 /* Otherwise it is equivalent to the extended register.
5404 Since the encoding doesn't change this is merely
5405 cosmetic cleanup for debug output. */
5407 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5412 if (i
.rex
== 0 && i
.rex_encoding
)
5414 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5415 that uses legacy register. If it is "hi" register, don't add
5416 the REX_OPCODE byte. */
5418 for (x
= 0; x
< 2; x
++)
5419 if (i
.types
[x
].bitfield
.class == Reg
5420 && i
.types
[x
].bitfield
.byte
5421 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5422 && i
.op
[x
].regs
->reg_num
> 3)
5424 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5425 i
.rex_encoding
= false;
5434 add_prefix (REX_OPCODE
| i
.rex
);
5436 insert_lfence_before ();
5438 /* We are ready to output the insn. */
5441 insert_lfence_after ();
5443 last_insn
.seg
= now_seg
;
5445 if (i
.tm
.opcode_modifier
.isprefix
)
5447 last_insn
.kind
= last_insn_prefix
;
5448 last_insn
.name
= insn_name (&i
.tm
);
5449 last_insn
.file
= as_where (&last_insn
.line
);
5452 last_insn
.kind
= last_insn_other
;
5455 /* The Q suffix is generally valid only in 64-bit mode, with very few
5456 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5457 and fisttp only one of their two templates is matched below: That's
5458 sufficient since other relevant attributes are the same between both
5459 respective templates. */
5460 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5462 return flag_code
== CODE_64BIT
5463 || (t
->opcode_space
== SPACE_BASE
5464 && t
->base_opcode
== 0xdf
5465 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5466 || t
->mnem_off
== MN_cmpxchg8b
;
5470 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5472 const char *l
= line
, *token_start
= l
;
5474 bool pass1
= !current_templates
;
5476 const insn_template
*t
;
5482 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5487 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5489 as_bad (_("no such instruction: `%s'"), token_start
);
5494 if (!is_space_char (*l
)
5495 && *l
!= END_OF_INSN
5497 || (*l
!= PREFIX_SEPARATOR
5502 as_bad (_("invalid character %s in mnemonic"),
5503 output_invalid (*l
));
5506 if (token_start
== l
)
5508 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5509 as_bad (_("expecting prefix; got nothing"));
5511 as_bad (_("expecting mnemonic; got nothing"));
5515 /* Look up instruction (or prefix) via hash table. */
5516 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5518 if (*l
!= END_OF_INSN
5519 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5520 && current_templates
5521 && current_templates
->start
->opcode_modifier
.isprefix
)
5523 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5525 as_bad ((flag_code
!= CODE_64BIT
5526 ? _("`%s' is only supported in 64-bit mode")
5527 : _("`%s' is not supported in 64-bit mode")),
5528 insn_name (current_templates
->start
));
5531 /* If we are in 16-bit mode, do not allow addr16 or data16.
5532 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5533 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5534 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5535 && flag_code
!= CODE_64BIT
5536 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5537 ^ (flag_code
== CODE_16BIT
)))
5539 as_bad (_("redundant %s prefix"),
5540 insn_name (current_templates
->start
));
5544 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5546 /* Handle pseudo prefixes. */
5547 switch (current_templates
->start
->extension_opcode
)
5551 i
.disp_encoding
= disp_encoding_8bit
;
5555 i
.disp_encoding
= disp_encoding_16bit
;
5559 i
.disp_encoding
= disp_encoding_32bit
;
5563 i
.dir_encoding
= dir_encoding_load
;
5567 i
.dir_encoding
= dir_encoding_store
;
5571 i
.vec_encoding
= vex_encoding_vex
;
5575 i
.vec_encoding
= vex_encoding_vex3
;
5579 i
.vec_encoding
= vex_encoding_evex
;
5583 i
.rex_encoding
= true;
5585 case Prefix_NoOptimize
:
5587 i
.no_optimize
= true;
5595 /* Add prefix, checking for repeated prefixes. */
5596 switch (add_prefix (current_templates
->start
->base_opcode
))
5601 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5602 i
.notrack_prefix
= insn_name (current_templates
->start
);
5605 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5606 i
.hle_prefix
= insn_name (current_templates
->start
);
5607 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5608 i
.bnd_prefix
= insn_name (current_templates
->start
);
5610 i
.rep_prefix
= insn_name (current_templates
->start
);
5616 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5626 if (!current_templates
)
5628 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5629 Check if we should swap operand or force 32bit displacement in
5631 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5632 i
.dir_encoding
= dir_encoding_swap
;
5633 else if (mnem_p
- 3 == dot_p
5636 i
.disp_encoding
= disp_encoding_8bit
;
5637 else if (mnem_p
- 4 == dot_p
5641 i
.disp_encoding
= disp_encoding_32bit
;
5646 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5649 if (!current_templates
|| !pass1
)
5651 current_templates
= NULL
;
5654 if (mnem_p
> mnemonic
)
5656 /* See if we can get a match by trimming off a suffix. */
5659 case WORD_MNEM_SUFFIX
:
5660 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5661 i
.suffix
= SHORT_MNEM_SUFFIX
;
5664 case BYTE_MNEM_SUFFIX
:
5665 case QWORD_MNEM_SUFFIX
:
5666 i
.suffix
= mnem_p
[-1];
5669 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5671 case SHORT_MNEM_SUFFIX
:
5672 case LONG_MNEM_SUFFIX
:
5675 i
.suffix
= mnem_p
[-1];
5678 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5686 if (intel_float_operand (mnemonic
) == 1)
5687 i
.suffix
= SHORT_MNEM_SUFFIX
;
5689 i
.suffix
= LONG_MNEM_SUFFIX
;
5692 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5694 /* For compatibility reasons accept MOVSD and CMPSD without
5695 operands even in AT&T mode. */
5696 else if (*l
== END_OF_INSN
5697 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5701 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5702 if (current_templates
!= NULL
5704 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5705 && current_templates
->start
->opcode_space
5707 && mnem_p
[-2] == 's')
5709 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5710 mnemonic
, mnemonic
);
5711 i
.suffix
= LONG_MNEM_SUFFIX
;
5715 current_templates
= NULL
;
5723 if (!current_templates
)
5726 as_bad (_("no such instruction: `%s'"), token_start
);
5731 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5732 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5734 /* Check for a branch hint. We allow ",pt" and ",pn" for
5735 predict taken and predict not taken respectively.
5736 I'm not sure that branch hints actually do anything on loop
5737 and jcxz insns (JumpByte) for current Pentium4 chips. They
5738 may work in the future and it doesn't hurt to accept them
5740 if (l
[0] == ',' && l
[1] == 'p')
5744 if (!add_prefix (DS_PREFIX_OPCODE
))
5748 else if (l
[2] == 'n')
5750 if (!add_prefix (CS_PREFIX_OPCODE
))
5756 /* Any other comma loses. */
5759 as_bad (_("invalid character %s in mnemonic"),
5760 output_invalid (*l
));
5764 /* Check if instruction is supported on specified architecture. */
5766 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5768 supported
|= cpu_flags_match (t
);
5770 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5771 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5773 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5779 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5780 i
.error
= unsupported_on_arch
;
5782 i
.error
= unsupported_64bit
;
5789 parse_operands (char *l
, const char *mnemonic
)
5793 /* 1 if operand is pending after ','. */
5794 unsigned int expecting_operand
= 0;
5796 while (*l
!= END_OF_INSN
)
5798 /* Non-zero if operand parens not balanced. */
5799 unsigned int paren_not_balanced
= 0;
5800 /* True if inside double quotes. */
5801 bool in_quotes
= false;
5803 /* Skip optional white space before operand. */
5804 if (is_space_char (*l
))
5806 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5808 as_bad (_("invalid character %s before operand %d"),
5809 output_invalid (*l
),
5813 token_start
= l
; /* After white space. */
5814 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5816 if (*l
== END_OF_INSN
)
5820 as_bad (_("unbalanced double quotes in operand %d."),
5824 if (paren_not_balanced
)
5826 know (!intel_syntax
);
5827 as_bad (_("unbalanced parenthesis in operand %d."),
5832 break; /* we are done */
5834 else if (*l
== '\\' && l
[1] == '"')
5837 in_quotes
= !in_quotes
;
5838 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5840 as_bad (_("invalid character %s in operand %d"),
5841 output_invalid (*l
),
5845 if (!intel_syntax
&& !in_quotes
)
5848 ++paren_not_balanced
;
5850 --paren_not_balanced
;
5854 if (l
!= token_start
)
5855 { /* Yes, we've read in another operand. */
5856 unsigned int operand_ok
;
5857 this_operand
= i
.operands
++;
5858 if (i
.operands
> MAX_OPERANDS
)
5860 as_bad (_("spurious operands; (%d operands/instruction max)"),
5864 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5865 /* Now parse operand adding info to 'i' as we go along. */
5866 END_STRING_AND_SAVE (l
);
5868 if (i
.mem_operands
> 1)
5870 as_bad (_("too many memory references for `%s'"),
5877 i386_intel_operand (token_start
,
5878 intel_float_operand (mnemonic
));
5880 operand_ok
= i386_att_operand (token_start
);
5882 RESTORE_END_STRING (l
);
5888 if (expecting_operand
)
5890 expecting_operand_after_comma
:
5891 as_bad (_("expecting operand after ','; got nothing"));
5896 as_bad (_("expecting operand before ','; got nothing"));
5901 /* Now *l must be either ',' or END_OF_INSN. */
5904 if (*++l
== END_OF_INSN
)
5906 /* Just skip it, if it's \n complain. */
5907 goto expecting_operand_after_comma
;
5909 expecting_operand
= 1;
5916 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5918 union i386_op temp_op
;
5919 i386_operand_type temp_type
;
5920 unsigned int temp_flags
;
5921 enum bfd_reloc_code_real temp_reloc
;
5923 temp_type
= i
.types
[xchg2
];
5924 i
.types
[xchg2
] = i
.types
[xchg1
];
5925 i
.types
[xchg1
] = temp_type
;
5927 temp_flags
= i
.flags
[xchg2
];
5928 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5929 i
.flags
[xchg1
] = temp_flags
;
5931 temp_op
= i
.op
[xchg2
];
5932 i
.op
[xchg2
] = i
.op
[xchg1
];
5933 i
.op
[xchg1
] = temp_op
;
5935 temp_reloc
= i
.reloc
[xchg2
];
5936 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5937 i
.reloc
[xchg1
] = temp_reloc
;
5939 temp_flags
= i
.imm_bits
[xchg2
];
5940 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
5941 i
.imm_bits
[xchg1
] = temp_flags
;
5945 if (i
.mask
.operand
== xchg1
)
5946 i
.mask
.operand
= xchg2
;
5947 else if (i
.mask
.operand
== xchg2
)
5948 i
.mask
.operand
= xchg1
;
5950 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
5952 if (i
.broadcast
.operand
== xchg1
)
5953 i
.broadcast
.operand
= xchg2
;
5954 else if (i
.broadcast
.operand
== xchg2
)
5955 i
.broadcast
.operand
= xchg1
;
5960 swap_operands (void)
5966 swap_2_operands (1, i
.operands
- 2);
5970 swap_2_operands (0, i
.operands
- 1);
5976 if (i
.mem_operands
== 2)
5978 const reg_entry
*temp_seg
;
5979 temp_seg
= i
.seg
[0];
5980 i
.seg
[0] = i
.seg
[1];
5981 i
.seg
[1] = temp_seg
;
5985 /* Try to ensure constant immediates are represented in the smallest
5990 char guess_suffix
= 0;
5994 guess_suffix
= i
.suffix
;
5995 else if (i
.reg_operands
)
5997 /* Figure out a suffix from the last register operand specified.
5998 We can't do this properly yet, i.e. excluding special register
5999 instances, but the following works for instructions with
6000 immediates. In any case, we can't set i.suffix yet. */
6001 for (op
= i
.operands
; --op
>= 0;)
6002 if (i
.types
[op
].bitfield
.class != Reg
)
6004 else if (i
.types
[op
].bitfield
.byte
)
6006 guess_suffix
= BYTE_MNEM_SUFFIX
;
6009 else if (i
.types
[op
].bitfield
.word
)
6011 guess_suffix
= WORD_MNEM_SUFFIX
;
6014 else if (i
.types
[op
].bitfield
.dword
)
6016 guess_suffix
= LONG_MNEM_SUFFIX
;
6019 else if (i
.types
[op
].bitfield
.qword
)
6021 guess_suffix
= QWORD_MNEM_SUFFIX
;
6025 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6026 guess_suffix
= WORD_MNEM_SUFFIX
;
6027 else if (flag_code
!= CODE_64BIT
|| !(i
.prefix
[REX_PREFIX
] & REX_W
))
6028 guess_suffix
= LONG_MNEM_SUFFIX
;
6030 for (op
= i
.operands
; --op
>= 0;)
6031 if (operand_type_check (i
.types
[op
], imm
))
6033 switch (i
.op
[op
].imms
->X_op
)
6036 /* If a suffix is given, this operand may be shortened. */
6037 switch (guess_suffix
)
6039 case LONG_MNEM_SUFFIX
:
6040 i
.types
[op
].bitfield
.imm32
= 1;
6041 i
.types
[op
].bitfield
.imm64
= 1;
6043 case WORD_MNEM_SUFFIX
:
6044 i
.types
[op
].bitfield
.imm16
= 1;
6045 i
.types
[op
].bitfield
.imm32
= 1;
6046 i
.types
[op
].bitfield
.imm32s
= 1;
6047 i
.types
[op
].bitfield
.imm64
= 1;
6049 case BYTE_MNEM_SUFFIX
:
6050 i
.types
[op
].bitfield
.imm8
= 1;
6051 i
.types
[op
].bitfield
.imm8s
= 1;
6052 i
.types
[op
].bitfield
.imm16
= 1;
6053 i
.types
[op
].bitfield
.imm32
= 1;
6054 i
.types
[op
].bitfield
.imm32s
= 1;
6055 i
.types
[op
].bitfield
.imm64
= 1;
6059 /* If this operand is at most 16 bits, convert it
6060 to a signed 16 bit number before trying to see
6061 whether it will fit in an even smaller size.
6062 This allows a 16-bit operand such as $0xffe0 to
6063 be recognised as within Imm8S range. */
6064 if ((i
.types
[op
].bitfield
.imm16
)
6065 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6067 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6068 ^ 0x8000) - 0x8000);
6071 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6072 if ((i
.types
[op
].bitfield
.imm32
)
6073 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6075 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6076 ^ ((offsetT
) 1 << 31))
6077 - ((offsetT
) 1 << 31));
6081 = operand_type_or (i
.types
[op
],
6082 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6084 /* We must avoid matching of Imm32 templates when 64bit
6085 only immediate is available. */
6086 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6087 i
.types
[op
].bitfield
.imm32
= 0;
6094 /* Symbols and expressions. */
6096 /* Convert symbolic operand to proper sizes for matching, but don't
6097 prevent matching a set of insns that only supports sizes other
6098 than those matching the insn suffix. */
6100 i386_operand_type mask
, allowed
;
6101 const insn_template
*t
= current_templates
->start
;
6103 operand_type_set (&mask
, 0);
6104 switch (guess_suffix
)
6106 case QWORD_MNEM_SUFFIX
:
6107 mask
.bitfield
.imm64
= 1;
6108 mask
.bitfield
.imm32s
= 1;
6110 case LONG_MNEM_SUFFIX
:
6111 mask
.bitfield
.imm32
= 1;
6113 case WORD_MNEM_SUFFIX
:
6114 mask
.bitfield
.imm16
= 1;
6116 case BYTE_MNEM_SUFFIX
:
6117 mask
.bitfield
.imm8
= 1;
6123 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6124 while (++t
< current_templates
->end
)
6126 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6127 allowed
= operand_type_and (allowed
, mask
);
6130 if (!operand_type_all_zero (&allowed
))
6131 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6138 /* Try to use the smallest displacement type too. */
6140 optimize_disp (const insn_template
*t
)
6144 if (!want_disp32 (t
)
6145 && (!t
->opcode_modifier
.jump
6146 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6148 for (op
= 0; op
< i
.operands
; ++op
)
6150 const expressionS
*exp
= i
.op
[op
].disps
;
6152 if (!operand_type_check (i
.types
[op
], disp
))
6155 if (exp
->X_op
!= O_constant
)
6158 /* Since displacement is signed extended to 64bit, don't allow
6159 disp32 if it is out of range. */
6160 if (fits_in_signed_long (exp
->X_add_number
))
6163 i
.types
[op
].bitfield
.disp32
= 0;
6164 if (i
.types
[op
].bitfield
.baseindex
)
6166 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6167 (uint64_t) exp
->X_add_number
);
6173 /* Don't optimize displacement for movabs since it only takes 64bit
6175 if (i
.disp_encoding
> disp_encoding_8bit
6176 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6179 for (op
= i
.operands
; op
-- > 0;)
6180 if (operand_type_check (i
.types
[op
], disp
))
6182 if (i
.op
[op
].disps
->X_op
== O_constant
)
6184 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6186 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6188 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6189 i
.op
[op
].disps
= NULL
;
6194 if (i
.types
[op
].bitfield
.disp16
6195 && fits_in_unsigned_word (op_disp
))
6197 /* If this operand is at most 16 bits, convert
6198 to a signed 16 bit number and don't use 64bit
6200 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6201 i
.types
[op
].bitfield
.disp64
= 0;
6205 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6206 if ((flag_code
!= CODE_64BIT
6207 ? i
.types
[op
].bitfield
.disp32
6209 && (!t
->opcode_modifier
.jump
6210 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6211 && fits_in_unsigned_long (op_disp
))
6213 /* If this operand is at most 32 bits, convert
6214 to a signed 32 bit number and don't use 64bit
6216 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6217 i
.types
[op
].bitfield
.disp64
= 0;
6218 i
.types
[op
].bitfield
.disp32
= 1;
6221 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6223 i
.types
[op
].bitfield
.disp64
= 0;
6224 i
.types
[op
].bitfield
.disp32
= 1;
6227 if ((i
.types
[op
].bitfield
.disp32
6228 || i
.types
[op
].bitfield
.disp16
)
6229 && fits_in_disp8 (op_disp
))
6230 i
.types
[op
].bitfield
.disp8
= 1;
6232 i
.op
[op
].disps
->X_add_number
= op_disp
;
6234 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6235 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6237 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6238 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6239 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6242 /* We only support 64bit displacement on constants. */
6243 i
.types
[op
].bitfield
.disp64
= 0;
6249 /* Return 1 if there is a match in broadcast bytes between operand
6250 GIVEN and instruction template T. */
6253 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6255 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6256 && i
.types
[given
].bitfield
.byte
)
6257 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6258 && i
.types
[given
].bitfield
.word
)
6259 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6260 && i
.types
[given
].bitfield
.dword
)
6261 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6262 && i
.types
[given
].bitfield
.qword
));
6265 /* Check if operands are valid for the instruction. */
6268 check_VecOperands (const insn_template
*t
)
6273 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6274 any one operand are implicity requiring AVX512VL support if the actual
6275 operand size is YMMword or XMMword. Since this function runs after
6276 template matching, there's no need to check for YMMword/XMMword in
6278 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
6279 if (!cpu_flags_all_zero (&cpu
)
6280 && !t
->cpu_flags
.bitfield
.cpuavx512vl
6281 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6283 for (op
= 0; op
< t
->operands
; ++op
)
6285 if (t
->operand_types
[op
].bitfield
.zmmword
6286 && (i
.types
[op
].bitfield
.ymmword
6287 || i
.types
[op
].bitfield
.xmmword
))
6289 i
.error
= unsupported
;
6295 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6296 requiring AVX2 support if the actual operand size is YMMword. */
6297 if (t
->cpu_flags
.bitfield
.cpuavx
6298 && t
->cpu_flags
.bitfield
.cpuavx2
6299 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6301 for (op
= 0; op
< t
->operands
; ++op
)
6303 if (t
->operand_types
[op
].bitfield
.xmmword
6304 && i
.types
[op
].bitfield
.ymmword
)
6306 i
.error
= unsupported
;
6312 /* Without VSIB byte, we can't have a vector register for index. */
6313 if (!t
->opcode_modifier
.sib
6315 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6316 || i
.index_reg
->reg_type
.bitfield
.ymmword
6317 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6319 i
.error
= unsupported_vector_index_register
;
6323 /* Check if default mask is allowed. */
6324 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6325 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6327 i
.error
= no_default_mask
;
6331 /* For VSIB byte, we need a vector register for index, and all vector
6332 registers must be distinct. */
6333 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6336 || !((t
->opcode_modifier
.sib
== VECSIB128
6337 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6338 || (t
->opcode_modifier
.sib
== VECSIB256
6339 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6340 || (t
->opcode_modifier
.sib
== VECSIB512
6341 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6343 i
.error
= invalid_vsib_address
;
6347 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6348 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6350 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6351 gas_assert (i
.types
[0].bitfield
.xmmword
6352 || i
.types
[0].bitfield
.ymmword
);
6353 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6354 gas_assert (i
.types
[2].bitfield
.xmmword
6355 || i
.types
[2].bitfield
.ymmword
);
6356 if (operand_check
== check_none
)
6358 if (register_number (i
.op
[0].regs
)
6359 != register_number (i
.index_reg
)
6360 && register_number (i
.op
[2].regs
)
6361 != register_number (i
.index_reg
)
6362 && register_number (i
.op
[0].regs
)
6363 != register_number (i
.op
[2].regs
))
6365 if (operand_check
== check_error
)
6367 i
.error
= invalid_vector_register_set
;
6370 as_warn (_("mask, index, and destination registers should be distinct"));
6372 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6374 if (i
.types
[1].bitfield
.class == RegSIMD
6375 && (i
.types
[1].bitfield
.xmmword
6376 || i
.types
[1].bitfield
.ymmword
6377 || i
.types
[1].bitfield
.zmmword
)
6378 && (register_number (i
.op
[1].regs
)
6379 == register_number (i
.index_reg
)))
6381 if (operand_check
== check_error
)
6383 i
.error
= invalid_vector_register_set
;
6386 if (operand_check
!= check_none
)
6387 as_warn (_("index and destination registers should be distinct"));
6392 /* For AMX instructions with 3 TMM register operands, all operands
6393 must be distinct. */
6394 if (i
.reg_operands
== 3
6395 && t
->operand_types
[0].bitfield
.tmmword
6396 && (i
.op
[0].regs
== i
.op
[1].regs
6397 || i
.op
[0].regs
== i
.op
[2].regs
6398 || i
.op
[1].regs
== i
.op
[2].regs
))
6400 i
.error
= invalid_tmm_register_set
;
6404 /* For some special instructions require that destination must be distinct
6405 from source registers. */
6406 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6408 unsigned int dest_reg
= i
.operands
- 1;
6410 know (i
.operands
>= 3);
6412 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6413 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6414 || (i
.reg_operands
> 2
6415 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6417 i
.error
= invalid_dest_and_src_register_set
;
6422 /* Check if broadcast is supported by the instruction and is applied
6423 to the memory operand. */
6424 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6426 i386_operand_type type
, overlap
;
6428 /* Check if specified broadcast is supported in this instruction,
6429 and its broadcast bytes match the memory operand. */
6430 op
= i
.broadcast
.operand
;
6431 if (!t
->opcode_modifier
.broadcast
6432 || !(i
.flags
[op
] & Operand_Mem
)
6433 || (!i
.types
[op
].bitfield
.unspecified
6434 && !match_broadcast_size (t
, op
)))
6437 i
.error
= unsupported_broadcast
;
6441 operand_type_set (&type
, 0);
6442 switch (get_broadcast_bytes (t
, false))
6445 type
.bitfield
.word
= 1;
6448 type
.bitfield
.dword
= 1;
6451 type
.bitfield
.qword
= 1;
6454 type
.bitfield
.xmmword
= 1;
6457 type
.bitfield
.ymmword
= 1;
6460 type
.bitfield
.zmmword
= 1;
6466 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6467 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6468 && t
->operand_types
[op
].bitfield
.byte
6469 + t
->operand_types
[op
].bitfield
.word
6470 + t
->operand_types
[op
].bitfield
.dword
6471 + t
->operand_types
[op
].bitfield
.qword
> 1)
6473 overlap
.bitfield
.xmmword
= 0;
6474 overlap
.bitfield
.ymmword
= 0;
6475 overlap
.bitfield
.zmmword
= 0;
6477 if (operand_type_all_zero (&overlap
))
6480 if (t
->opcode_modifier
.checkoperandsize
)
6484 type
.bitfield
.baseindex
= 1;
6485 for (j
= 0; j
< i
.operands
; ++j
)
6488 && !operand_type_register_match(i
.types
[j
],
6489 t
->operand_types
[j
],
6491 t
->operand_types
[op
]))
6496 /* If broadcast is supported in this instruction, we need to check if
6497 operand of one-element size isn't specified without broadcast. */
6498 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6500 /* Find memory operand. */
6501 for (op
= 0; op
< i
.operands
; op
++)
6502 if (i
.flags
[op
] & Operand_Mem
)
6504 gas_assert (op
< i
.operands
);
6505 /* Check size of the memory operand. */
6506 if (match_broadcast_size (t
, op
))
6508 i
.error
= broadcast_needed
;
6513 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6515 /* Check if requested masking is supported. */
6518 switch (t
->opcode_modifier
.masking
)
6522 case MERGING_MASKING
:
6526 i
.error
= unsupported_masking
;
6530 case DYNAMIC_MASKING
:
6531 /* Memory destinations allow only merging masking. */
6532 if (i
.mask
.zeroing
&& i
.mem_operands
)
6534 /* Find memory operand. */
6535 for (op
= 0; op
< i
.operands
; op
++)
6536 if (i
.flags
[op
] & Operand_Mem
)
6538 gas_assert (op
< i
.operands
);
6539 if (op
== i
.operands
- 1)
6541 i
.error
= unsupported_masking
;
6551 /* Check if masking is applied to dest operand. */
6552 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6554 i
.error
= mask_not_on_destination
;
6559 if (i
.rounding
.type
!= rc_none
)
6561 if (!t
->opcode_modifier
.sae
6562 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6565 i
.error
= unsupported_rc_sae
;
6569 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6571 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6573 for (op
= 0; op
< t
->operands
; ++op
)
6574 if (i
.types
[op
].bitfield
.zmmword
)
6576 if (op
>= t
->operands
)
6578 i
.error
= operand_size_mismatch
;
6584 /* Check the special Imm4 cases; must be the first operand. */
6585 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6587 if (i
.op
[0].imms
->X_op
!= O_constant
6588 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6594 /* Turn off Imm<N> so that update_imm won't complain. */
6595 operand_type_set (&i
.types
[0], 0);
6598 /* Check vector Disp8 operand. */
6599 if (t
->opcode_modifier
.disp8memshift
6600 && i
.disp_encoding
<= disp_encoding_8bit
)
6602 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6603 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6604 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6605 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6608 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6611 for (op
= 0; op
< i
.operands
; op
++)
6612 if (i
.flags
[op
] & Operand_Mem
)
6614 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6615 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6616 else if (t
->operand_types
[op
].bitfield
.xmmword
6617 + t
->operand_types
[op
].bitfield
.ymmword
6618 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6619 type
= &t
->operand_types
[op
];
6620 else if (!i
.types
[op
].bitfield
.unspecified
)
6621 type
= &i
.types
[op
];
6622 else /* Ambiguities get resolved elsewhere. */
6623 fallback
= &t
->operand_types
[op
];
6625 else if (i
.types
[op
].bitfield
.class == RegSIMD
6626 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6628 if (i
.types
[op
].bitfield
.zmmword
)
6630 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6632 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6636 if (!type
&& !i
.memshift
)
6640 if (type
->bitfield
.zmmword
)
6642 else if (type
->bitfield
.ymmword
)
6644 else if (type
->bitfield
.xmmword
)
6648 /* For the check in fits_in_disp8(). */
6649 if (i
.memshift
== 0)
6653 for (op
= 0; op
< i
.operands
; op
++)
6654 if (operand_type_check (i
.types
[op
], disp
)
6655 && i
.op
[op
].disps
->X_op
== O_constant
)
6657 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6659 i
.types
[op
].bitfield
.disp8
= 1;
6662 i
.types
[op
].bitfield
.disp8
= 0;
6671 /* Check if encoding requirements are met by the instruction. */
6674 VEX_check_encoding (const insn_template
*t
)
6676 if (i
.vec_encoding
== vex_encoding_error
)
6678 i
.error
= unsupported
;
6682 if (i
.vec_encoding
== vex_encoding_evex
)
6684 /* This instruction must be encoded with EVEX prefix. */
6685 if (!is_evex_encoding (t
))
6687 i
.error
= unsupported
;
6693 if (!t
->opcode_modifier
.vex
)
6695 /* This instruction template doesn't have VEX prefix. */
6696 if (i
.vec_encoding
!= vex_encoding_default
)
6698 i
.error
= unsupported
;
6707 /* Helper function for the progress() macro in match_template(). */
6708 static INLINE
enum i386_error
progress (enum i386_error
new,
6709 enum i386_error last
,
6710 unsigned int line
, unsigned int *line_p
)
6712 if (line
<= *line_p
)
6718 static const insn_template
*
6719 match_template (char mnem_suffix
)
6721 /* Points to template once we've found it. */
6722 const insn_template
*t
;
6723 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6724 i386_operand_type overlap4
;
6725 unsigned int found_reverse_match
;
6726 i386_operand_type operand_types
[MAX_OPERANDS
];
6727 int addr_prefix_disp
;
6728 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6729 enum i386_error specific_error
= number_of_operands_mismatch
;
6730 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6732 #if MAX_OPERANDS != 5
6733 # error "MAX_OPERANDS must be 5."
6736 found_reverse_match
= 0;
6737 addr_prefix_disp
= -1;
6739 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6741 addr_prefix_disp
= -1;
6742 found_reverse_match
= 0;
6744 /* Must have right number of operands. */
6745 if (i
.operands
!= t
->operands
)
6748 /* Check processor support. */
6749 specific_error
= progress (unsupported
);
6750 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6753 /* Check AT&T mnemonic. */
6754 specific_error
= progress (unsupported_with_intel_mnemonic
);
6755 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6758 /* Check AT&T/Intel syntax. */
6759 specific_error
= progress (unsupported_syntax
);
6760 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6761 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6764 /* Check Intel64/AMD64 ISA. */
6768 /* Default: Don't accept Intel64. */
6769 if (t
->opcode_modifier
.isa64
== INTEL64
)
6773 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6774 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6778 /* -mintel64: Don't accept AMD64. */
6779 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6784 /* Check the suffix. */
6785 specific_error
= progress (invalid_instruction_suffix
);
6786 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6787 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6788 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6789 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6790 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6793 specific_error
= progress (operand_size_mismatch
);
6794 size_match
= operand_size_match (t
);
6798 /* This is intentionally not
6800 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6802 as the case of a missing * on the operand is accepted (perhaps with
6803 a warning, issued further down). */
6804 specific_error
= progress (operand_type_mismatch
);
6805 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6808 /* In Intel syntax, normally we can check for memory operand size when
6809 there is no mnemonic suffix. But jmp and call have 2 different
6810 encodings with Dword memory operand size. Skip the "near" one
6811 (permitting a register operand) when "far" was requested. */
6813 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
6814 && t
->operand_types
[0].bitfield
.class == Reg
)
6817 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6818 operand_types
[j
] = t
->operand_types
[j
];
6820 /* In general, don't allow 32-bit operands on pre-386. */
6821 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
6822 : operand_size_mismatch
);
6823 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6824 if (i
.suffix
== LONG_MNEM_SUFFIX
6825 && !cpu_arch_flags
.bitfield
.cpui386
6827 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6828 && !intel_float_operand (insn_name (t
)))
6829 : intel_float_operand (insn_name (t
)) != 2)
6830 && (t
->operands
== i
.imm_operands
6831 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6832 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6833 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6834 || (operand_types
[j
].bitfield
.class != RegMMX
6835 && operand_types
[j
].bitfield
.class != RegSIMD
6836 && operand_types
[j
].bitfield
.class != RegMask
))
6837 && !t
->opcode_modifier
.sib
)
6840 /* Do not verify operands when there are none. */
6843 if (VEX_check_encoding (t
))
6845 specific_error
= progress (i
.error
);
6849 /* We've found a match; break out of loop. */
6853 if (!t
->opcode_modifier
.jump
6854 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6856 /* There should be only one Disp operand. */
6857 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6858 if (operand_type_check (operand_types
[j
], disp
))
6860 if (j
< MAX_OPERANDS
)
6862 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6864 addr_prefix_disp
= j
;
6866 /* Address size prefix will turn Disp64 operand into Disp32 and
6867 Disp32/Disp16 one into Disp16/Disp32 respectively. */
6871 override
= !override
;
6874 if (operand_types
[j
].bitfield
.disp32
6875 && operand_types
[j
].bitfield
.disp16
)
6877 operand_types
[j
].bitfield
.disp16
= override
;
6878 operand_types
[j
].bitfield
.disp32
= !override
;
6880 gas_assert (!operand_types
[j
].bitfield
.disp64
);
6884 if (operand_types
[j
].bitfield
.disp64
)
6886 gas_assert (!operand_types
[j
].bitfield
.disp32
);
6887 operand_types
[j
].bitfield
.disp32
= override
;
6888 operand_types
[j
].bitfield
.disp64
= !override
;
6890 operand_types
[j
].bitfield
.disp16
= 0;
6896 /* We check register size if needed. */
6897 if (t
->opcode_modifier
.checkoperandsize
)
6899 check_register
= (1 << t
->operands
) - 1;
6900 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6901 check_register
&= ~(1 << i
.broadcast
.operand
);
6906 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6907 switch (t
->operands
)
6910 if (!operand_type_match (overlap0
, i
.types
[0]))
6913 /* Allow the ModR/M encoding to be requested by using the {load} or
6914 {store} pseudo prefix on an applicable insn. */
6915 if (!t
->opcode_modifier
.modrm
6916 && i
.reg_operands
== 1
6917 && ((i
.dir_encoding
== dir_encoding_load
6918 && t
->mnem_off
!= MN_pop
)
6919 || (i
.dir_encoding
== dir_encoding_store
6920 && t
->mnem_off
!= MN_push
))
6922 && t
->mnem_off
!= MN_bswap
)
6927 /* xchg %eax, %eax is a special case. It is an alias for nop
6928 only in 32bit mode and we can use opcode 0x90. In 64bit
6929 mode, we can't use 0x90 for xchg %eax, %eax since it should
6930 zero-extend %eax to %rax. */
6931 if (t
->base_opcode
== 0x90
6932 && t
->opcode_space
== SPACE_BASE
)
6934 if (flag_code
== CODE_64BIT
6935 && i
.types
[0].bitfield
.instance
== Accum
6936 && i
.types
[0].bitfield
.dword
6937 && i
.types
[1].bitfield
.instance
== Accum
)
6940 /* Allow the ModR/M encoding to be requested by using the
6941 {load} or {store} pseudo prefix. */
6942 if (i
.dir_encoding
== dir_encoding_load
6943 || i
.dir_encoding
== dir_encoding_store
)
6947 if (t
->base_opcode
== MOV_AX_DISP32
6948 && t
->opcode_space
== SPACE_BASE
6949 && t
->mnem_off
!= MN_movabs
)
6951 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6952 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
6955 /* xrelease mov %eax, <disp> is another special case. It must not
6956 match the accumulator-only encoding of mov. */
6960 /* Allow the ModR/M encoding to be requested by using a suitable
6961 {load} or {store} pseudo prefix. */
6962 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
6963 ? dir_encoding_store
6964 : dir_encoding_load
)
6965 && !i
.types
[0].bitfield
.disp64
6966 && !i
.types
[1].bitfield
.disp64
)
6970 /* Allow the ModR/M encoding to be requested by using the {load} or
6971 {store} pseudo prefix on an applicable insn. */
6972 if (!t
->opcode_modifier
.modrm
6973 && i
.reg_operands
== 1
6974 && i
.imm_operands
== 1
6975 && (i
.dir_encoding
== dir_encoding_load
6976 || i
.dir_encoding
== dir_encoding_store
)
6977 && t
->opcode_space
== SPACE_BASE
)
6979 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
6980 && i
.dir_encoding
== dir_encoding_store
)
6983 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
6984 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
6985 || i
.dir_encoding
== dir_encoding_load
))
6988 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
6989 && i
.dir_encoding
== dir_encoding_load
)
6995 if (!(size_match
& MATCH_STRAIGHT
))
6997 /* Reverse direction of operands if swapping is possible in the first
6998 place (operands need to be symmetric) and
6999 - the load form is requested, and the template is a store form,
7000 - the store form is requested, and the template is a load form,
7001 - the non-default (swapped) form is requested. */
7002 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7003 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7004 && !operand_type_all_zero (&overlap1
))
7005 switch (i
.dir_encoding
)
7007 case dir_encoding_load
:
7008 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7009 || t
->opcode_modifier
.regmem
)
7013 case dir_encoding_store
:
7014 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7015 && !t
->opcode_modifier
.regmem
)
7019 case dir_encoding_swap
:
7022 case dir_encoding_default
:
7025 /* If we want store form, we skip the current load. */
7026 if ((i
.dir_encoding
== dir_encoding_store
7027 || i
.dir_encoding
== dir_encoding_swap
)
7028 && i
.mem_operands
== 0
7029 && t
->opcode_modifier
.load
)
7034 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7035 if (!operand_type_match (overlap0
, i
.types
[0])
7036 || !operand_type_match (overlap1
, i
.types
[1])
7037 || ((check_register
& 3) == 3
7038 && !operand_type_register_match (i
.types
[0],
7043 specific_error
= progress (i
.error
);
7045 /* Check if other direction is valid ... */
7046 if (!t
->opcode_modifier
.d
)
7050 if (!(size_match
& MATCH_REVERSE
))
7052 /* Try reversing direction of operands. */
7053 j
= t
->cpu_flags
.bitfield
.cpufma4
7054 || t
->cpu_flags
.bitfield
.cpuxop
? 1 : i
.operands
- 1;
7055 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7056 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7057 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7058 gas_assert (t
->operands
!= 3 || !check_register
);
7059 if (!operand_type_match (overlap0
, i
.types
[0])
7060 || !operand_type_match (overlap1
, i
.types
[j
])
7061 || (t
->operands
== 3
7062 && !operand_type_match (overlap2
, i
.types
[1]))
7064 && !operand_type_register_match (i
.types
[0],
7069 /* Does not match either direction. */
7070 specific_error
= progress (i
.error
);
7073 /* found_reverse_match holds which variant of D
7075 if (!t
->opcode_modifier
.d
)
7076 found_reverse_match
= 0;
7077 else if (operand_types
[0].bitfield
.tbyte
)
7079 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7080 found_reverse_match
= Opcode_FloatD
;
7082 found_reverse_match
= ~0;
7083 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7084 if ((t
->extension_opcode
& 4)
7085 && (intel_syntax
|| intel_mnemonic
))
7086 found_reverse_match
|= Opcode_FloatR
;
7088 else if (t
->cpu_flags
.bitfield
.cpufma4
7089 || t
->cpu_flags
.bitfield
.cpuxop
)
7091 found_reverse_match
= Opcode_VexW
;
7092 goto check_operands_345
;
7094 else if (t
->opcode_space
!= SPACE_BASE
7095 && (t
->opcode_space
!= SPACE_0F
7096 /* MOV to/from CR/DR/TR, as an exception, follow
7097 the base opcode space encoding model. */
7098 || (t
->base_opcode
| 7) != 0x27))
7099 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7100 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7101 else if (!t
->opcode_modifier
.commutative
)
7102 found_reverse_match
= Opcode_D
;
7104 found_reverse_match
= ~0;
7108 /* Found a forward 2 operand match here. */
7110 switch (t
->operands
)
7113 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7114 if (!operand_type_match (overlap4
, i
.types
[4])
7115 || !operand_type_register_match (i
.types
[3],
7120 specific_error
= progress (i
.error
);
7125 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7126 if (!operand_type_match (overlap3
, i
.types
[3])
7127 || ((check_register
& 0xa) == 0xa
7128 && !operand_type_register_match (i
.types
[1],
7132 || ((check_register
& 0xc) == 0xc
7133 && !operand_type_register_match (i
.types
[2],
7138 specific_error
= progress (i
.error
);
7143 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7144 if (!operand_type_match (overlap2
, i
.types
[2])
7145 || ((check_register
& 5) == 5
7146 && !operand_type_register_match (i
.types
[0],
7150 || ((check_register
& 6) == 6
7151 && !operand_type_register_match (i
.types
[1],
7156 specific_error
= progress (i
.error
);
7162 /* Found either forward/reverse 2, 3 or 4 operand match here:
7163 slip through to break. */
7166 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7167 if (VEX_check_encoding (t
))
7169 specific_error
= progress (i
.error
);
7173 /* Check if vector operands are valid. */
7174 if (check_VecOperands (t
))
7176 specific_error
= progress (i
.error
);
7180 /* We've found a match; break out of loop. */
7186 if (t
== current_templates
->end
)
7188 /* We found no match. */
7189 i
.error
= specific_error
;
7193 if (!quiet_warnings
)
7196 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7197 as_warn (_("indirect %s without `*'"), insn_name (t
));
7199 if (t
->opcode_modifier
.isprefix
7200 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7202 /* Warn them that a data or address size prefix doesn't
7203 affect assembly of the next line of code. */
7204 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7208 /* Copy the template we found. */
7209 install_template (t
);
7211 if (addr_prefix_disp
!= -1)
7212 i
.tm
.operand_types
[addr_prefix_disp
]
7213 = operand_types
[addr_prefix_disp
];
7215 switch (found_reverse_match
)
7221 case Opcode_FloatR
| Opcode_FloatD
:
7222 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7223 found_reverse_match
&= Opcode_FloatD
;
7227 /* If we found a reverse match we must alter the opcode direction
7228 bit and clear/flip the regmem modifier one. found_reverse_match
7229 holds bits to change (different for int & float insns). */
7231 i
.tm
.base_opcode
^= found_reverse_match
;
7233 /* Certain SIMD insns have their load forms specified in the opcode
7234 table, and hence we need to _set_ RegMem instead of clearing it.
7235 We need to avoid setting the bit though on insns like KMOVW. */
7236 i
.tm
.opcode_modifier
.regmem
7237 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7238 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7239 && !i
.tm
.opcode_modifier
.regmem
;
7243 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7244 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7248 /* Only the first two register operands need reversing, alongside
7250 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7252 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7253 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7254 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7264 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7265 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7267 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7269 as_bad (_("`%s' operand %u must use `%ses' segment"),
7271 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7276 /* There's only ever one segment override allowed per instruction.
7277 This instruction possibly has a legal segment override on the
7278 second operand, so copy the segment to where non-string
7279 instructions store it, allowing common code. */
7280 i
.seg
[op
] = i
.seg
[1];
7286 process_suffix (void)
7288 bool is_movx
= false;
7290 /* If matched instruction specifies an explicit instruction mnemonic
7292 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7293 i
.suffix
= WORD_MNEM_SUFFIX
;
7294 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7295 i
.suffix
= LONG_MNEM_SUFFIX
;
7296 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7297 i
.suffix
= QWORD_MNEM_SUFFIX
;
7298 else if (i
.reg_operands
7299 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7300 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7302 unsigned int numop
= i
.operands
;
7305 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7306 && (i
.tm
.base_opcode
| 8) == 0xbe)
7307 || (i
.tm
.opcode_space
== SPACE_BASE
7308 && i
.tm
.base_opcode
== 0x63
7309 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
7311 /* movsx/movzx want only their source operand considered here, for the
7312 ambiguity checking below. The suffix will be replaced afterwards
7313 to represent the destination (register). */
7314 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7317 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7318 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7321 /* If there's no instruction mnemonic suffix we try to invent one
7322 based on GPR operands. */
7325 /* We take i.suffix from the last register operand specified,
7326 Destination register type is more significant than source
7327 register type. crc32 in SSE4.2 prefers source register
7329 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7332 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7333 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7335 if (i
.types
[op
].bitfield
.class != Reg
)
7337 if (i
.types
[op
].bitfield
.byte
)
7338 i
.suffix
= BYTE_MNEM_SUFFIX
;
7339 else if (i
.types
[op
].bitfield
.word
)
7340 i
.suffix
= WORD_MNEM_SUFFIX
;
7341 else if (i
.types
[op
].bitfield
.dword
)
7342 i
.suffix
= LONG_MNEM_SUFFIX
;
7343 else if (i
.types
[op
].bitfield
.qword
)
7344 i
.suffix
= QWORD_MNEM_SUFFIX
;
7350 /* As an exception, movsx/movzx silently default to a byte source
7352 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7353 i
.suffix
= BYTE_MNEM_SUFFIX
;
7355 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7357 if (!check_byte_reg ())
7360 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7362 if (!check_long_reg ())
7365 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7367 if (!check_qword_reg ())
7370 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7372 if (!check_word_reg ())
7375 else if (intel_syntax
7376 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7377 /* Do nothing if the instruction is going to ignore the prefix. */
7382 /* Undo the movsx/movzx change done above. */
7385 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7388 i
.suffix
= stackop_size
;
7389 if (stackop_size
== LONG_MNEM_SUFFIX
)
7391 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7392 .code16gcc directive to support 16-bit mode with
7393 32-bit address. For IRET without a suffix, generate
7394 16-bit IRET (opcode 0xcf) to return from an interrupt
7396 if (i
.tm
.base_opcode
== 0xcf)
7398 i
.suffix
= WORD_MNEM_SUFFIX
;
7399 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7401 /* Warn about changed behavior for segment register push/pop. */
7402 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7403 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7408 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7409 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7410 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7411 || (i
.tm
.opcode_space
== SPACE_0F
7412 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7413 && i
.tm
.extension_opcode
<= 3)))
7418 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7420 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7421 || i
.tm
.opcode_modifier
.no_lsuf
)
7422 i
.suffix
= QWORD_MNEM_SUFFIX
;
7427 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7428 i
.suffix
= LONG_MNEM_SUFFIX
;
7431 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7432 i
.suffix
= WORD_MNEM_SUFFIX
;
7438 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7439 /* Also cover lret/retf/iret in 64-bit mode. */
7440 || (flag_code
== CODE_64BIT
7441 && !i
.tm
.opcode_modifier
.no_lsuf
7442 && !i
.tm
.opcode_modifier
.no_qsuf
))
7443 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7444 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7445 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7446 /* Accept FLDENV et al without suffix. */
7447 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7449 unsigned int suffixes
, evex
= 0;
7451 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7452 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7454 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7456 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7458 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7461 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7462 also suitable for AT&T syntax mode, it was requested that this be
7463 restricted to just Intel syntax. */
7464 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7465 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7469 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7471 if (is_evex_encoding (&i
.tm
)
7472 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7474 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7475 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7476 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7477 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7478 if (!i
.tm
.opcode_modifier
.evex
7479 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7480 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7483 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7484 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7485 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7488 /* Any properly sized operand disambiguates the insn. */
7489 if (i
.types
[op
].bitfield
.xmmword
7490 || i
.types
[op
].bitfield
.ymmword
7491 || i
.types
[op
].bitfield
.zmmword
)
7493 suffixes
&= ~(7 << 6);
7498 if ((i
.flags
[op
] & Operand_Mem
)
7499 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7501 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7503 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7505 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7507 if (is_evex_encoding (&i
.tm
))
7513 /* Are multiple suffixes / operand sizes allowed? */
7514 if (suffixes
& (suffixes
- 1))
7517 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7518 || operand_check
== check_error
))
7520 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7523 if (operand_check
== check_error
)
7525 as_bad (_("no instruction mnemonic suffix given and "
7526 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7529 if (operand_check
== check_warning
)
7530 as_warn (_("%s; using default for `%s'"),
7532 ? _("ambiguous operand size")
7533 : _("no instruction mnemonic suffix given and "
7534 "no register operands"),
7537 if (i
.tm
.opcode_modifier
.floatmf
)
7538 i
.suffix
= SHORT_MNEM_SUFFIX
;
7540 /* handled below */;
7542 i
.tm
.opcode_modifier
.evex
= evex
;
7543 else if (flag_code
== CODE_16BIT
)
7544 i
.suffix
= WORD_MNEM_SUFFIX
;
7545 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7546 i
.suffix
= LONG_MNEM_SUFFIX
;
7548 i
.suffix
= QWORD_MNEM_SUFFIX
;
7554 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7555 In AT&T syntax, if there is no suffix (warned about above), the default
7556 will be byte extension. */
7557 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7558 i
.tm
.base_opcode
|= 1;
7560 /* For further processing, the suffix should represent the destination
7561 (register). This is already the case when one was used with
7562 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7563 no suffix to begin with. */
7564 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7566 if (i
.types
[1].bitfield
.word
)
7567 i
.suffix
= WORD_MNEM_SUFFIX
;
7568 else if (i
.types
[1].bitfield
.qword
)
7569 i
.suffix
= QWORD_MNEM_SUFFIX
;
7571 i
.suffix
= LONG_MNEM_SUFFIX
;
7573 i
.tm
.opcode_modifier
.w
= 0;
7577 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7578 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7579 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7581 /* Change the opcode based on the operand size given by i.suffix. */
7584 /* Size floating point instruction. */
7585 case LONG_MNEM_SUFFIX
:
7586 if (i
.tm
.opcode_modifier
.floatmf
)
7588 i
.tm
.base_opcode
^= 4;
7592 case WORD_MNEM_SUFFIX
:
7593 case QWORD_MNEM_SUFFIX
:
7594 /* It's not a byte, select word/dword operation. */
7595 if (i
.tm
.opcode_modifier
.w
)
7598 i
.tm
.base_opcode
|= 8;
7600 i
.tm
.base_opcode
|= 1;
7603 case SHORT_MNEM_SUFFIX
:
7604 /* Now select between word & dword operations via the operand
7605 size prefix, except for instructions that will ignore this
7607 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7608 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7609 && !i
.tm
.opcode_modifier
.floatmf
7610 && !is_any_vex_encoding (&i
.tm
)
7611 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7612 || (flag_code
== CODE_64BIT
7613 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7615 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7617 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7618 prefix
= ADDR_PREFIX_OPCODE
;
7620 if (!add_prefix (prefix
))
7624 /* Set mode64 for an operand. */
7625 if (i
.suffix
== QWORD_MNEM_SUFFIX
7626 && flag_code
== CODE_64BIT
7627 && !i
.tm
.opcode_modifier
.norex64
7628 && !i
.tm
.opcode_modifier
.vexw
7629 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7631 && ! (i
.operands
== 2
7632 && i
.tm
.base_opcode
== 0x90
7633 && i
.tm
.opcode_space
== SPACE_BASE
7634 && i
.types
[0].bitfield
.instance
== Accum
7635 && i
.types
[0].bitfield
.qword
7636 && i
.types
[1].bitfield
.instance
== Accum
))
7642 /* Select word/dword/qword operation with explicit data sizing prefix
7643 when there are no suitable register operands. */
7644 if (i
.tm
.opcode_modifier
.w
7645 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7647 || (i
.reg_operands
== 1
7649 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7651 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7652 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7653 || i
.tm
.mnem_off
== MN_crc32
))))
7654 i
.tm
.base_opcode
|= 1;
7658 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7660 gas_assert (!i
.suffix
);
7661 gas_assert (i
.reg_operands
);
7663 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7666 /* The address size override prefix changes the size of the
7668 if (flag_code
== CODE_64BIT
7669 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7671 as_bad (_("16-bit addressing unavailable for `%s'"),
7676 if ((flag_code
== CODE_32BIT
7677 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7678 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7679 && !add_prefix (ADDR_PREFIX_OPCODE
))
7684 /* Check invalid register operand when the address size override
7685 prefix changes the size of register operands. */
7687 enum { need_word
, need_dword
, need_qword
} need
;
7689 /* Check the register operand for the address size prefix if
7690 the memory operand has no real registers, like symbol, DISP
7691 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7692 if (i
.mem_operands
== 1
7693 && i
.reg_operands
== 1
7695 && i
.types
[1].bitfield
.class == Reg
7696 && (flag_code
== CODE_32BIT
7697 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7698 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7699 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7700 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7701 || (x86_elf_abi
== X86_64_X32_ABI
7703 && i
.base_reg
->reg_num
== RegIP
7704 && i
.base_reg
->reg_type
.bitfield
.qword
))
7708 && !add_prefix (ADDR_PREFIX_OPCODE
))
7711 if (flag_code
== CODE_32BIT
)
7712 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7713 else if (i
.prefix
[ADDR_PREFIX
])
7716 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7718 for (op
= 0; op
< i
.operands
; op
++)
7720 if (i
.types
[op
].bitfield
.class != Reg
)
7726 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7730 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7734 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7739 as_bad (_("invalid register operand size for `%s'"),
7750 check_byte_reg (void)
7754 for (op
= i
.operands
; --op
>= 0;)
7756 /* Skip non-register operands. */
7757 if (i
.types
[op
].bitfield
.class != Reg
)
7760 /* If this is an eight bit register, it's OK. If it's the 16 or
7761 32 bit version of an eight bit register, we will just use the
7762 low portion, and that's OK too. */
7763 if (i
.types
[op
].bitfield
.byte
)
7766 /* I/O port address operands are OK too. */
7767 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7768 && i
.tm
.operand_types
[op
].bitfield
.word
)
7771 /* crc32 only wants its source operand checked here. */
7772 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
7775 /* Any other register is bad. */
7776 as_bad (_("`%s%s' not allowed with `%s%c'"),
7777 register_prefix
, i
.op
[op
].regs
->reg_name
,
7778 insn_name (&i
.tm
), i
.suffix
);
7785 check_long_reg (void)
7789 for (op
= i
.operands
; --op
>= 0;)
7790 /* Skip non-register operands. */
7791 if (i
.types
[op
].bitfield
.class != Reg
)
7793 /* Reject eight bit registers, except where the template requires
7794 them. (eg. movzb) */
7795 else if (i
.types
[op
].bitfield
.byte
7796 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7797 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7798 && (i
.tm
.operand_types
[op
].bitfield
.word
7799 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7801 as_bad (_("`%s%s' not allowed with `%s%c'"),
7803 i
.op
[op
].regs
->reg_name
,
7808 /* Error if the e prefix on a general reg is missing. */
7809 else if (i
.types
[op
].bitfield
.word
7810 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7811 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7812 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7814 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7815 register_prefix
, i
.op
[op
].regs
->reg_name
,
7819 /* Warn if the r prefix on a general reg is present. */
7820 else if (i
.types
[op
].bitfield
.qword
7821 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7822 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7823 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7825 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7826 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7833 check_qword_reg (void)
7837 for (op
= i
.operands
; --op
>= 0; )
7838 /* Skip non-register operands. */
7839 if (i
.types
[op
].bitfield
.class != Reg
)
7841 /* Reject eight bit registers, except where the template requires
7842 them. (eg. movzb) */
7843 else if (i
.types
[op
].bitfield
.byte
7844 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7845 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7846 && (i
.tm
.operand_types
[op
].bitfield
.word
7847 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7849 as_bad (_("`%s%s' not allowed with `%s%c'"),
7851 i
.op
[op
].regs
->reg_name
,
7856 /* Warn if the r prefix on a general reg is missing. */
7857 else if ((i
.types
[op
].bitfield
.word
7858 || i
.types
[op
].bitfield
.dword
)
7859 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7860 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7861 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7863 /* Prohibit these changes in the 64bit mode, since the
7864 lowering is more complicated. */
7865 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7866 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7873 check_word_reg (void)
7876 for (op
= i
.operands
; --op
>= 0;)
7877 /* Skip non-register operands. */
7878 if (i
.types
[op
].bitfield
.class != Reg
)
7880 /* Reject eight bit registers, except where the template requires
7881 them. (eg. movzb) */
7882 else if (i
.types
[op
].bitfield
.byte
7883 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7884 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7885 && (i
.tm
.operand_types
[op
].bitfield
.word
7886 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7888 as_bad (_("`%s%s' not allowed with `%s%c'"),
7890 i
.op
[op
].regs
->reg_name
,
7895 /* Error if the e or r prefix on a general reg is present. */
7896 else if ((i
.types
[op
].bitfield
.dword
7897 || i
.types
[op
].bitfield
.qword
)
7898 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7899 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7900 && i
.tm
.operand_types
[op
].bitfield
.word
)
7902 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7903 register_prefix
, i
.op
[op
].regs
->reg_name
,
7911 update_imm (unsigned int j
)
7913 i386_operand_type overlap
= i
.types
[j
];
7915 if (i
.tm
.operand_types
[j
].bitfield
.imm8
7916 && i
.tm
.operand_types
[j
].bitfield
.imm8s
7917 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
7919 /* This combination is used on 8-bit immediates where e.g. $~0 is
7920 desirable to permit. We're past operand type matching, so simply
7921 put things back in the shape they were before introducing the
7922 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
7923 overlap
.bitfield
.imm8s
= 0;
7926 if (overlap
.bitfield
.imm8
7927 + overlap
.bitfield
.imm8s
7928 + overlap
.bitfield
.imm16
7929 + overlap
.bitfield
.imm32
7930 + overlap
.bitfield
.imm32s
7931 + overlap
.bitfield
.imm64
> 1)
7933 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
7934 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
7935 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
7936 static const i386_operand_type imm16_32
= { .bitfield
=
7937 { .imm16
= 1, .imm32
= 1 }
7939 static const i386_operand_type imm16_32s
= { .bitfield
=
7940 { .imm16
= 1, .imm32s
= 1 }
7942 static const i386_operand_type imm16_32_32s
= { .bitfield
=
7943 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
7948 i386_operand_type temp
;
7950 operand_type_set (&temp
, 0);
7951 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7953 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7954 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7956 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7957 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7958 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7960 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7961 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7964 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7967 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7968 || operand_type_equal (&overlap
, &imm16_32
)
7969 || operand_type_equal (&overlap
, &imm16_32s
))
7971 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7976 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7977 overlap
= operand_type_and (overlap
, imm32s
);
7978 else if (i
.prefix
[DATA_PREFIX
])
7979 overlap
= operand_type_and (overlap
,
7980 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7981 if (overlap
.bitfield
.imm8
7982 + overlap
.bitfield
.imm8s
7983 + overlap
.bitfield
.imm16
7984 + overlap
.bitfield
.imm32
7985 + overlap
.bitfield
.imm32s
7986 + overlap
.bitfield
.imm64
!= 1)
7988 as_bad (_("no instruction mnemonic suffix given; "
7989 "can't determine immediate size"));
7993 i
.types
[j
] = overlap
;
8003 /* Update the first 2 immediate operands. */
8004 n
= i
.operands
> 2 ? 2 : i
.operands
;
8007 for (j
= 0; j
< n
; j
++)
8008 if (update_imm (j
) == 0)
8011 /* The 3rd operand can't be immediate operand. */
8012 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8018 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8021 if (r
->reg_flags
& RegRex
)
8023 if (i
.rex
& rex_bit
)
8024 as_bad (_("same type of prefix used twice"));
8027 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8029 gas_assert (i
.vex
.register_specifier
== r
);
8030 i
.vex
.register_specifier
+= 8;
8033 if (r
->reg_flags
& RegVRex
)
8038 process_operands (void)
8040 /* Default segment register this instruction will use for memory
8041 accesses. 0 means unknown. This is only for optimizing out
8042 unnecessary segment overrides. */
8043 const reg_entry
*default_seg
= NULL
;
8045 /* We only need to check those implicit registers for instructions
8046 with 3 operands or less. */
8047 if (i
.operands
<= 3)
8048 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8049 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8052 if (i
.tm
.opcode_modifier
.sse2avx
)
8054 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8056 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8057 i
.prefix
[REX_PREFIX
] = 0;
8060 /* ImmExt should be processed after SSE2AVX. */
8061 else if (i
.tm
.opcode_modifier
.immext
)
8064 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8065 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8066 new destination operand here, while converting the source one to register
8068 if (i
.tm
.mnem_off
== MN_tilezero
)
8070 i
.op
[1].regs
= i
.op
[0].regs
;
8071 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8072 i
.types
[1] = i
.types
[0];
8073 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8074 i
.flags
[1] = i
.flags
[0];
8080 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8082 static const i386_operand_type regxmm
= {
8083 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8085 unsigned int dupl
= i
.operands
;
8086 unsigned int dest
= dupl
- 1;
8089 /* The destination must be an xmm register. */
8090 gas_assert (i
.reg_operands
8091 && MAX_OPERANDS
> dupl
8092 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8094 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8095 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8097 /* Keep xmm0 for instructions with VEX prefix and 3
8099 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8100 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8105 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8107 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8109 /* Add the implicit xmm0 for instructions with VEX prefix
8111 for (j
= i
.operands
; j
> 0; j
--)
8113 i
.op
[j
] = i
.op
[j
- 1];
8114 i
.types
[j
] = i
.types
[j
- 1];
8115 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8116 i
.flags
[j
] = i
.flags
[j
- 1];
8119 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8120 i
.types
[0] = regxmm
;
8121 i
.tm
.operand_types
[0] = regxmm
;
8124 i
.reg_operands
+= 2;
8129 i
.op
[dupl
] = i
.op
[dest
];
8130 i
.types
[dupl
] = i
.types
[dest
];
8131 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8132 i
.flags
[dupl
] = i
.flags
[dest
];
8141 i
.op
[dupl
] = i
.op
[dest
];
8142 i
.types
[dupl
] = i
.types
[dest
];
8143 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8144 i
.flags
[dupl
] = i
.flags
[dest
];
8147 if (i
.tm
.opcode_modifier
.immext
)
8150 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8151 && i
.tm
.opcode_modifier
.modrm
)
8155 for (j
= 1; j
< i
.operands
; j
++)
8157 i
.op
[j
- 1] = i
.op
[j
];
8158 i
.types
[j
- 1] = i
.types
[j
];
8160 /* We need to adjust fields in i.tm since they are used by
8161 build_modrm_byte. */
8162 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8164 i
.flags
[j
- 1] = i
.flags
[j
];
8167 /* No adjustment to i.reg_operands: This was already done at the top
8172 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8174 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8176 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8177 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8178 regnum
= register_number (i
.op
[1].regs
);
8179 first_reg_in_group
= regnum
& ~3;
8180 last_reg_in_group
= first_reg_in_group
+ 3;
8181 if (regnum
!= first_reg_in_group
)
8182 as_warn (_("source register `%s%s' implicitly denotes"
8183 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8184 register_prefix
, i
.op
[1].regs
->reg_name
,
8185 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8186 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8189 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8191 /* The imul $imm, %reg instruction is converted into
8192 imul $imm, %reg, %reg, and the clr %reg instruction
8193 is converted into xor %reg, %reg. */
8195 unsigned int first_reg_op
;
8197 if (operand_type_check (i
.types
[0], reg
))
8201 /* Pretend we saw the extra register operand. */
8202 gas_assert (i
.reg_operands
== 1
8203 && i
.op
[first_reg_op
+ 1].regs
== 0);
8204 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8205 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8210 if (i
.tm
.opcode_modifier
.modrm
)
8212 /* The opcode is completed (modulo i.tm.extension_opcode which
8213 must be put into the modrm byte). Now, we make the modrm and
8214 index base bytes based on all the info we've collected. */
8216 default_seg
= build_modrm_byte ();
8218 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8220 /* Warn about some common errors, but press on regardless. */
8221 if (i
.operands
== 2)
8223 /* Reversed arguments on faddp or fmulp. */
8224 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8225 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8226 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8228 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8230 /* Extraneous `l' suffix on fp insn. */
8231 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8232 register_prefix
, i
.op
[0].regs
->reg_name
);
8236 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8238 if (flag_code
!= CODE_64BIT
8239 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8240 && i
.op
[0].regs
->reg_num
== 1
8241 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8242 && i
.op
[0].regs
->reg_num
< 4)
8244 as_bad (_("you can't `%s %s%s'"),
8245 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8248 if (i
.op
[0].regs
->reg_num
> 3
8249 && i
.tm
.opcode_space
== SPACE_BASE
)
8251 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8252 i
.tm
.opcode_space
= SPACE_0F
;
8254 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8256 else if (i
.tm
.opcode_space
== SPACE_BASE
8257 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8259 default_seg
= reg_ds
;
8261 else if (i
.tm
.opcode_modifier
.isstring
)
8263 /* For the string instructions that allow a segment override
8264 on one of their operands, the default segment is ds. */
8265 default_seg
= reg_ds
;
8267 else if (i
.short_form
)
8269 /* The register operand is in the 1st or 2nd non-immediate operand. */
8270 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8273 && r
->reg_type
.bitfield
.instance
== Accum
8274 && i
.op
[i
.imm_operands
+ 1].regs
)
8275 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8276 /* Register goes in low 3 bits of opcode. */
8277 i
.tm
.base_opcode
|= r
->reg_num
;
8278 set_rex_vrex (r
, REX_B
, false);
8280 if (dot_insn () && i
.reg_operands
== 2)
8282 gas_assert (is_any_vex_encoding (&i
.tm
)
8283 || i
.vec_encoding
!= vex_encoding_default
);
8284 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8287 else if (i
.reg_operands
== 1
8288 && !i
.flags
[i
.operands
- 1]
8289 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8292 gas_assert (is_any_vex_encoding (&i
.tm
)
8293 || i
.vec_encoding
!= vex_encoding_default
);
8294 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8297 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8298 && i
.tm
.mnem_off
== MN_lea
)
8300 if (!quiet_warnings
)
8301 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8302 if (optimize
&& !i
.no_optimize
)
8305 i
.prefix
[SEG_PREFIX
] = 0;
8309 /* If a segment was explicitly specified, and the specified segment
8310 is neither the default nor the one already recorded from a prefix,
8311 use an opcode prefix to select it. If we never figured out what
8312 the default segment is, then default_seg will be zero at this
8313 point, and the specified segment prefix will always be used. */
8315 && i
.seg
[0] != default_seg
8316 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8318 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8324 static const reg_entry
*
8325 build_modrm_byte (void)
8327 const reg_entry
*default_seg
= NULL
;
8328 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8329 /* Compensate for kludge in md_assemble(). */
8330 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8331 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8332 unsigned int v
, op
, reg_slot
= ~0;
8334 /* Accumulator (in particular %st), shift count (%cl), and alike need
8335 to be skipped just like immediate operands do. */
8336 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8338 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8341 for (op
= source
; op
< i
.operands
; ++op
)
8342 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8345 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8349 /* There are 2 kinds of instructions:
8350 1. 5 operands: 4 register operands or 3 register operands
8351 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8352 VexW0 or VexW1. The destination must be either XMM, YMM or
8354 2. 4 operands: 4 register operands or 3 register operands
8355 plus 1 memory operand, with VexXDS.
8356 3. Other equivalent combinations when coming from s_insn(). */
8357 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8358 && i
.tm
.opcode_modifier
.vexw
);
8359 gas_assert (dot_insn ()
8360 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8362 /* Of the first two non-immediate operands the one with the template
8363 not allowing for a memory one is encoded in the immediate operand. */
8365 reg_slot
= source
+ 1;
8367 reg_slot
= source
++;
8371 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8372 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8375 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8377 if (i
.imm_operands
== 0)
8379 /* When there is no immediate operand, generate an 8bit
8380 immediate operand to encode the first operand. */
8381 exp
= &im_expressions
[i
.imm_operands
++];
8382 i
.op
[i
.operands
].imms
= exp
;
8383 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8386 exp
->X_op
= O_constant
;
8390 gas_assert (i
.imm_operands
== 1);
8391 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8392 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8394 /* Turn on Imm8 again so that output_imm will generate it. */
8395 i
.types
[0].bitfield
.imm8
= 1;
8399 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8400 << (3 + !(is_evex_encoding (&i
.tm
)
8401 || i
.vec_encoding
== vex_encoding_evex
));
8404 for (v
= source
+ 1; v
< dest
; ++v
)
8409 if (i
.tm
.extension_opcode
!= None
)
8415 gas_assert (source
< dest
);
8416 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8419 unsigned int tmp
= source
;
8425 if (v
< MAX_OPERANDS
)
8427 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8428 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8431 if (op
< i
.operands
)
8435 unsigned int fake_zero_displacement
= 0;
8437 gas_assert (i
.flags
[op
] & Operand_Mem
);
8439 if (i
.tm
.opcode_modifier
.sib
)
8441 /* The index register of VSIB shouldn't be RegIZ. */
8442 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8443 && i
.index_reg
->reg_num
== RegIZ
)
8446 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8449 i
.sib
.base
= NO_BASE_REGISTER
;
8450 i
.sib
.scale
= i
.log2_scale_factor
;
8451 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8452 i
.types
[op
].bitfield
.disp32
= 1;
8455 /* Since the mandatory SIB always has index register, so
8456 the code logic remains unchanged. The non-mandatory SIB
8457 without index register is allowed and will be handled
8461 if (i
.index_reg
->reg_num
== RegIZ
)
8462 i
.sib
.index
= NO_INDEX_REGISTER
;
8464 i
.sib
.index
= i
.index_reg
->reg_num
;
8465 set_rex_vrex (i
.index_reg
, REX_X
, false);
8469 default_seg
= reg_ds
;
8471 if (i
.base_reg
== 0)
8474 if (!i
.disp_operands
)
8475 fake_zero_displacement
= 1;
8476 if (i
.index_reg
== 0)
8478 /* Both check for VSIB and mandatory non-vector SIB. */
8479 gas_assert (!i
.tm
.opcode_modifier
.sib
8480 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8481 /* Operand is just <disp> */
8482 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8483 if (flag_code
== CODE_64BIT
)
8485 /* 64bit mode overwrites the 32bit absolute
8486 addressing by RIP relative addressing and
8487 absolute addressing is encoded by one of the
8488 redundant SIB forms. */
8489 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8490 i
.sib
.base
= NO_BASE_REGISTER
;
8491 i
.sib
.index
= NO_INDEX_REGISTER
;
8492 i
.types
[op
].bitfield
.disp32
= 1;
8494 else if ((flag_code
== CODE_16BIT
)
8495 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8497 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8498 i
.types
[op
].bitfield
.disp16
= 1;
8502 i
.rm
.regmem
= NO_BASE_REGISTER
;
8503 i
.types
[op
].bitfield
.disp32
= 1;
8506 else if (!i
.tm
.opcode_modifier
.sib
)
8508 /* !i.base_reg && i.index_reg */
8509 if (i
.index_reg
->reg_num
== RegIZ
)
8510 i
.sib
.index
= NO_INDEX_REGISTER
;
8512 i
.sib
.index
= i
.index_reg
->reg_num
;
8513 i
.sib
.base
= NO_BASE_REGISTER
;
8514 i
.sib
.scale
= i
.log2_scale_factor
;
8515 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8516 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8517 i
.types
[op
].bitfield
.disp32
= 1;
8518 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8522 /* RIP addressing for 64bit mode. */
8523 else if (i
.base_reg
->reg_num
== RegIP
)
8525 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8526 i
.rm
.regmem
= NO_BASE_REGISTER
;
8527 i
.types
[op
].bitfield
.disp8
= 0;
8528 i
.types
[op
].bitfield
.disp16
= 0;
8529 i
.types
[op
].bitfield
.disp32
= 1;
8530 i
.types
[op
].bitfield
.disp64
= 0;
8531 i
.flags
[op
] |= Operand_PCrel
;
8532 if (! i
.disp_operands
)
8533 fake_zero_displacement
= 1;
8535 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8537 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8538 switch (i
.base_reg
->reg_num
)
8541 if (i
.index_reg
== 0)
8543 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8544 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8547 default_seg
= reg_ss
;
8548 if (i
.index_reg
== 0)
8551 if (operand_type_check (i
.types
[op
], disp
) == 0)
8553 /* fake (%bp) into 0(%bp) */
8554 if (i
.disp_encoding
== disp_encoding_16bit
)
8555 i
.types
[op
].bitfield
.disp16
= 1;
8557 i
.types
[op
].bitfield
.disp8
= 1;
8558 fake_zero_displacement
= 1;
8561 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8562 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8564 default: /* (%si) -> 4 or (%di) -> 5 */
8565 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8567 if (!fake_zero_displacement
8571 fake_zero_displacement
= 1;
8572 if (i
.disp_encoding
== disp_encoding_8bit
)
8573 i
.types
[op
].bitfield
.disp8
= 1;
8575 i
.types
[op
].bitfield
.disp16
= 1;
8577 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8579 else /* i.base_reg and 32/64 bit mode */
8581 if (operand_type_check (i
.types
[op
], disp
))
8583 i
.types
[op
].bitfield
.disp16
= 0;
8584 i
.types
[op
].bitfield
.disp64
= 0;
8585 i
.types
[op
].bitfield
.disp32
= 1;
8588 if (!i
.tm
.opcode_modifier
.sib
)
8589 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8590 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8592 i
.sib
.base
= i
.base_reg
->reg_num
;
8593 /* x86-64 ignores REX prefix bit here to avoid decoder
8595 if (!(i
.base_reg
->reg_flags
& RegRex
)
8596 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8597 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8598 default_seg
= reg_ss
;
8599 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8601 fake_zero_displacement
= 1;
8602 if (i
.disp_encoding
== disp_encoding_32bit
)
8603 i
.types
[op
].bitfield
.disp32
= 1;
8605 i
.types
[op
].bitfield
.disp8
= 1;
8607 i
.sib
.scale
= i
.log2_scale_factor
;
8608 if (i
.index_reg
== 0)
8610 /* Only check for VSIB. */
8611 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8612 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8613 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8615 /* <disp>(%esp) becomes two byte modrm with no index
8616 register. We've already stored the code for esp
8617 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8618 Any base register besides %esp will not use the
8619 extra modrm byte. */
8620 i
.sib
.index
= NO_INDEX_REGISTER
;
8622 else if (!i
.tm
.opcode_modifier
.sib
)
8624 if (i
.index_reg
->reg_num
== RegIZ
)
8625 i
.sib
.index
= NO_INDEX_REGISTER
;
8627 i
.sib
.index
= i
.index_reg
->reg_num
;
8628 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8629 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8634 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8635 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8639 if (!fake_zero_displacement
8643 fake_zero_displacement
= 1;
8644 if (i
.disp_encoding
== disp_encoding_8bit
)
8645 i
.types
[op
].bitfield
.disp8
= 1;
8647 i
.types
[op
].bitfield
.disp32
= 1;
8649 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8653 if (fake_zero_displacement
)
8655 /* Fakes a zero displacement assuming that i.types[op]
8656 holds the correct displacement size. */
8659 gas_assert (i
.op
[op
].disps
== 0);
8660 exp
= &disp_expressions
[i
.disp_operands
++];
8661 i
.op
[op
].disps
= exp
;
8662 exp
->X_op
= O_constant
;
8663 exp
->X_add_number
= 0;
8664 exp
->X_add_symbol
= (symbolS
*) 0;
8665 exp
->X_op_symbol
= (symbolS
*) 0;
8671 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8672 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8683 if (!i
.tm
.opcode_modifier
.regmem
)
8685 gas_assert (source
< MAX_OPERANDS
);
8686 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8687 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8688 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8693 gas_assert (dest
< MAX_OPERANDS
);
8694 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8695 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8700 /* Fill in i.rm.reg field with extension opcode (if any) or the
8701 appropriate register. */
8702 if (i
.tm
.extension_opcode
!= None
)
8703 i
.rm
.reg
= i
.tm
.extension_opcode
;
8704 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
8706 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8707 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8711 gas_assert (source
< MAX_OPERANDS
);
8712 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8713 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8716 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8718 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
8720 add_prefix (LOCK_PREFIX_OPCODE
);
8727 frag_opcode_byte (unsigned char byte
)
8729 if (now_seg
!= absolute_section
)
8730 FRAG_APPEND_1_CHAR (byte
);
8732 ++abs_section_offset
;
8736 flip_code16 (unsigned int code16
)
8738 gas_assert (i
.tm
.operands
== 1);
8740 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8741 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8742 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8747 output_branch (void)
8753 relax_substateT subtype
;
8757 if (now_seg
== absolute_section
)
8759 as_bad (_("relaxable branches not supported in absolute section"));
8763 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8764 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8767 if (i
.prefix
[DATA_PREFIX
] != 0)
8771 code16
^= flip_code16(code16
);
8773 /* Pentium4 branch hints. */
8774 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8775 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8780 if (i
.prefix
[REX_PREFIX
] != 0)
8786 /* BND prefixed jump. */
8787 if (i
.prefix
[BND_PREFIX
] != 0)
8793 if (i
.prefixes
!= 0)
8794 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8796 /* It's always a symbol; End frag & setup for relax.
8797 Make sure there is enough room in this frag for the largest
8798 instruction we may generate in md_convert_frag. This is 2
8799 bytes for the opcode and room for the prefix and largest
8801 frag_grow (prefix
+ 2 + 4);
8802 /* Prefix and 1 opcode byte go in fr_fix. */
8803 p
= frag_more (prefix
+ 1);
8804 if (i
.prefix
[DATA_PREFIX
] != 0)
8805 *p
++ = DATA_PREFIX_OPCODE
;
8806 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8807 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8808 *p
++ = i
.prefix
[SEG_PREFIX
];
8809 if (i
.prefix
[BND_PREFIX
] != 0)
8810 *p
++ = BND_PREFIX_OPCODE
;
8811 if (i
.prefix
[REX_PREFIX
] != 0)
8812 *p
++ = i
.prefix
[REX_PREFIX
];
8813 *p
= i
.tm
.base_opcode
;
8815 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8816 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8817 else if (cpu_arch_flags
.bitfield
.cpui386
)
8818 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8820 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8823 sym
= i
.op
[0].disps
->X_add_symbol
;
8824 off
= i
.op
[0].disps
->X_add_number
;
8826 if (i
.op
[0].disps
->X_op
!= O_constant
8827 && i
.op
[0].disps
->X_op
!= O_symbol
)
8829 /* Handle complex expressions. */
8830 sym
= make_expr_symbol (i
.op
[0].disps
);
8834 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
8836 /* 1 possible extra opcode + 4 byte displacement go in var part.
8837 Pass reloc in fr_var. */
8838 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8841 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8842 /* Return TRUE iff PLT32 relocation should be used for branching to
8846 need_plt32_p (symbolS
*s
)
8848 /* PLT32 relocation is ELF only. */
8853 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8854 krtld support it. */
8858 /* Since there is no need to prepare for PLT branch on x86-64, we
8859 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8860 be used as a marker for 32-bit PC-relative branches. */
8867 /* Weak or undefined symbol need PLT32 relocation. */
8868 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8871 /* Non-global symbol doesn't need PLT32 relocation. */
8872 if (! S_IS_EXTERNAL (s
))
8875 /* Other global symbols need PLT32 relocation. NB: Symbol with
8876 non-default visibilities are treated as normal global symbol
8877 so that PLT32 relocation can be used as a marker for 32-bit
8878 PC-relative branches. It is useful for linker relaxation. */
8889 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8891 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8893 /* This is a loop or jecxz type instruction. */
8895 if (i
.prefix
[ADDR_PREFIX
] != 0)
8897 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8900 /* Pentium4 branch hints. */
8901 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8902 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8904 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8913 if (flag_code
== CODE_16BIT
)
8916 if (i
.prefix
[DATA_PREFIX
] != 0)
8918 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8920 code16
^= flip_code16(code16
);
8928 /* BND prefixed jump. */
8929 if (i
.prefix
[BND_PREFIX
] != 0)
8931 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8935 if (i
.prefix
[REX_PREFIX
] != 0)
8937 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8941 if (i
.prefixes
!= 0)
8942 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8944 if (now_seg
== absolute_section
)
8946 abs_section_offset
+= i
.opcode_length
+ size
;
8950 p
= frag_more (i
.opcode_length
+ size
);
8951 switch (i
.opcode_length
)
8954 *p
++ = i
.tm
.base_opcode
>> 8;
8957 *p
++ = i
.tm
.base_opcode
;
8963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8964 if (flag_code
== CODE_64BIT
&& size
== 4
8965 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
8966 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8967 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8970 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8972 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8973 i
.op
[0].disps
, 1, jump_reloc
);
8975 /* All jumps handled here are signed, but don't unconditionally use a
8976 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8977 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8982 fixP
->fx_signed
= 1;
8986 if (i
.tm
.mnem_off
== MN_xbegin
)
8987 fixP
->fx_signed
= 1;
8991 if (flag_code
== CODE_64BIT
)
8992 fixP
->fx_signed
= 1;
8998 output_interseg_jump (void)
9006 if (flag_code
== CODE_16BIT
)
9010 if (i
.prefix
[DATA_PREFIX
] != 0)
9017 gas_assert (!i
.prefix
[REX_PREFIX
]);
9023 if (i
.prefixes
!= 0)
9024 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9026 if (now_seg
== absolute_section
)
9028 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9032 /* 1 opcode; 2 segment; offset */
9033 p
= frag_more (prefix
+ 1 + 2 + size
);
9035 if (i
.prefix
[DATA_PREFIX
] != 0)
9036 *p
++ = DATA_PREFIX_OPCODE
;
9038 if (i
.prefix
[REX_PREFIX
] != 0)
9039 *p
++ = i
.prefix
[REX_PREFIX
];
9041 *p
++ = i
.tm
.base_opcode
;
9042 if (i
.op
[1].imms
->X_op
== O_constant
)
9044 offsetT n
= i
.op
[1].imms
->X_add_number
;
9047 && !fits_in_unsigned_word (n
)
9048 && !fits_in_signed_word (n
))
9050 as_bad (_("16-bit jump out of range"));
9053 md_number_to_chars (p
, n
, size
);
9056 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9057 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9060 if (i
.op
[0].imms
->X_op
== O_constant
)
9061 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9063 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9064 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9072 asection
*seg
= now_seg
;
9073 subsegT subseg
= now_subseg
;
9075 unsigned int alignment
, align_size_1
;
9076 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9077 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9078 unsigned int padding
;
9080 if (!IS_ELF
|| !x86_used_note
)
9083 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9085 /* The .note.gnu.property section layout:
9087 Field Length Contents
9090 n_descsz 4 The note descriptor size
9091 n_type 4 NT_GNU_PROPERTY_TYPE_0
9093 n_desc n_descsz The program property array
9097 /* Create the .note.gnu.property section. */
9098 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9099 bfd_set_section_flags (sec
,
9106 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9117 bfd_set_section_alignment (sec
, alignment
);
9118 elf_section_type (sec
) = SHT_NOTE
;
9120 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9122 isa_1_descsz_raw
= 4 + 4 + 4;
9123 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9124 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9126 feature_2_descsz_raw
= isa_1_descsz
;
9127 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9129 feature_2_descsz_raw
+= 4 + 4 + 4;
9130 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9131 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9134 descsz
= feature_2_descsz
;
9135 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9136 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9138 /* Write n_namsz. */
9139 md_number_to_chars (p
, (valueT
) 4, 4);
9141 /* Write n_descsz. */
9142 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9145 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9148 memcpy (p
+ 4 * 3, "GNU", 4);
9150 /* Write 4-byte type. */
9151 md_number_to_chars (p
+ 4 * 4,
9152 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9154 /* Write 4-byte data size. */
9155 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9157 /* Write 4-byte data. */
9158 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9160 /* Zero out paddings. */
9161 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9163 memset (p
+ 4 * 7, 0, padding
);
9165 /* Write 4-byte type. */
9166 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9167 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9169 /* Write 4-byte data size. */
9170 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9172 /* Write 4-byte data. */
9173 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9174 (valueT
) x86_feature_2_used
, 4);
9176 /* Zero out paddings. */
9177 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9179 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9181 /* We probably can't restore the current segment, for there likely
9184 subseg_set (seg
, subseg
);
9188 x86_support_sframe_p (void)
9190 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9191 return (x86_elf_abi
== X86_64_ABI
);
9195 x86_sframe_ra_tracking_p (void)
9197 /* In AMD64, return address is always stored on the stack at a fixed offset
9198 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9199 Do not track explicitly via an SFrame Frame Row Entry. */
9204 x86_sframe_cfa_ra_offset (void)
9206 gas_assert (x86_elf_abi
== X86_64_ABI
);
9207 return (offsetT
) -8;
9211 x86_sframe_get_abi_arch (void)
9213 unsigned char sframe_abi_arch
= 0;
9215 if (x86_support_sframe_p ())
9217 gas_assert (!target_big_endian
);
9218 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9221 return sframe_abi_arch
;
9227 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9228 const char *frag_now_ptr
)
9230 unsigned int len
= 0;
9232 if (start_frag
!= frag_now
)
9234 const fragS
*fr
= start_frag
;
9239 } while (fr
&& fr
!= frag_now
);
9242 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9245 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9246 be macro-fused with conditional jumps.
9247 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9248 or is one of the following format:
9261 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9263 /* No RIP address. */
9264 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9267 /* No opcodes outside of base encoding space. */
9268 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9271 /* add, sub without add/sub m, imm. */
9272 if (i
.tm
.base_opcode
<= 5
9273 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9274 || ((i
.tm
.base_opcode
| 3) == 0x83
9275 && (i
.tm
.extension_opcode
== 0x5
9276 || i
.tm
.extension_opcode
== 0x0)))
9278 *mf_cmp_p
= mf_cmp_alu_cmp
;
9279 return !(i
.mem_operands
&& i
.imm_operands
);
9282 /* and without and m, imm. */
9283 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9284 || ((i
.tm
.base_opcode
| 3) == 0x83
9285 && i
.tm
.extension_opcode
== 0x4))
9287 *mf_cmp_p
= mf_cmp_test_and
;
9288 return !(i
.mem_operands
&& i
.imm_operands
);
9291 /* test without test m imm. */
9292 if ((i
.tm
.base_opcode
| 1) == 0x85
9293 || (i
.tm
.base_opcode
| 1) == 0xa9
9294 || ((i
.tm
.base_opcode
| 1) == 0xf7
9295 && i
.tm
.extension_opcode
== 0))
9297 *mf_cmp_p
= mf_cmp_test_and
;
9298 return !(i
.mem_operands
&& i
.imm_operands
);
9301 /* cmp without cmp m, imm. */
9302 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9303 || ((i
.tm
.base_opcode
| 3) == 0x83
9304 && (i
.tm
.extension_opcode
== 0x7)))
9306 *mf_cmp_p
= mf_cmp_alu_cmp
;
9307 return !(i
.mem_operands
&& i
.imm_operands
);
9310 /* inc, dec without inc/dec m. */
9311 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9312 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9313 || ((i
.tm
.base_opcode
| 1) == 0xff
9314 && i
.tm
.extension_opcode
<= 0x1))
9316 *mf_cmp_p
= mf_cmp_incdec
;
9317 return !i
.mem_operands
;
9323 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9326 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9328 /* NB: Don't work with COND_JUMP86 without i386. */
9329 if (!align_branch_power
9330 || now_seg
== absolute_section
9331 || !cpu_arch_flags
.bitfield
.cpui386
9332 || !(align_branch
& align_branch_fused_bit
))
9335 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9337 if (last_insn
.kind
== last_insn_other
9338 || last_insn
.seg
!= now_seg
)
9341 as_warn_where (last_insn
.file
, last_insn
.line
,
9342 _("`%s` skips -malign-branch-boundary on `%s`"),
9343 last_insn
.name
, insn_name (&i
.tm
));
9349 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9352 add_branch_prefix_frag_p (void)
9354 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9355 to PadLock instructions since they include prefixes in opcode. */
9356 if (!align_branch_power
9357 || !align_branch_prefix_size
9358 || now_seg
== absolute_section
9359 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9360 || !cpu_arch_flags
.bitfield
.cpui386
)
9363 /* Don't add prefix if it is a prefix or there is no operand in case
9364 that segment prefix is special. */
9365 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9368 if (last_insn
.kind
== last_insn_other
9369 || last_insn
.seg
!= now_seg
)
9373 as_warn_where (last_insn
.file
, last_insn
.line
,
9374 _("`%s` skips -malign-branch-boundary on `%s`"),
9375 last_insn
.name
, insn_name (&i
.tm
));
9380 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9383 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9384 enum mf_jcc_kind
*mf_jcc_p
)
9388 /* NB: Don't work with COND_JUMP86 without i386. */
9389 if (!align_branch_power
9390 || now_seg
== absolute_section
9391 || !cpu_arch_flags
.bitfield
.cpui386
9392 || i
.tm
.opcode_space
!= SPACE_BASE
)
9397 /* Check for jcc and direct jmp. */
9398 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9400 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9402 *branch_p
= align_branch_jmp
;
9403 add_padding
= align_branch
& align_branch_jmp_bit
;
9407 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9408 igore the lowest bit. */
9409 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9410 *branch_p
= align_branch_jcc
;
9411 if ((align_branch
& align_branch_jcc_bit
))
9415 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9418 *branch_p
= align_branch_ret
;
9419 if ((align_branch
& align_branch_ret_bit
))
9424 /* Check for indirect jmp, direct and indirect calls. */
9425 if (i
.tm
.base_opcode
== 0xe8)
9428 *branch_p
= align_branch_call
;
9429 if ((align_branch
& align_branch_call_bit
))
9432 else if (i
.tm
.base_opcode
== 0xff
9433 && (i
.tm
.extension_opcode
== 2
9434 || i
.tm
.extension_opcode
== 4))
9436 /* Indirect call and jmp. */
9437 *branch_p
= align_branch_indirect
;
9438 if ((align_branch
& align_branch_indirect_bit
))
9445 && (i
.op
[0].disps
->X_op
== O_symbol
9446 || (i
.op
[0].disps
->X_op
== O_subtract
9447 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9449 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9450 /* No padding to call to global or undefined tls_get_addr. */
9451 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9452 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9458 && last_insn
.kind
!= last_insn_other
9459 && last_insn
.seg
== now_seg
)
9462 as_warn_where (last_insn
.file
, last_insn
.line
,
9463 _("`%s` skips -malign-branch-boundary on `%s`"),
9464 last_insn
.name
, insn_name (&i
.tm
));
9474 fragS
*insn_start_frag
;
9475 offsetT insn_start_off
;
9476 fragS
*fragP
= NULL
;
9477 enum align_branch_kind branch
= align_branch_none
;
9478 /* The initializer is arbitrary just to avoid uninitialized error.
9479 it's actually either assigned in add_branch_padding_frag_p
9480 or never be used. */
9481 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9484 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9486 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9487 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9488 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9490 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9491 || i
.tm
.cpu_flags
.bitfield
.cpu287
9492 || i
.tm
.cpu_flags
.bitfield
.cpu387
9493 || i
.tm
.cpu_flags
.bitfield
.cpu687
9494 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9495 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9497 if ((i
.xstate
& xstate_mmx
)
9498 || i
.tm
.mnem_off
== MN_emms
9499 || i
.tm
.mnem_off
== MN_femms
)
9500 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9504 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9505 i
.xstate
|= xstate_zmm
;
9506 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9507 i
.xstate
|= xstate_ymm
;
9508 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9509 i
.xstate
|= xstate_xmm
;
9512 /* vzeroall / vzeroupper */
9513 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9514 i
.xstate
|= xstate_ymm
;
9516 if ((i
.xstate
& xstate_xmm
)
9517 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9518 || (i
.tm
.base_opcode
== 0xae
9519 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9520 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9521 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9522 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9523 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9525 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9526 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9527 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9528 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9529 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9530 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9531 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9532 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9533 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9534 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9535 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9536 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9537 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9538 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9540 if (x86_feature_2_used
9541 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9542 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9543 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9544 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9545 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9546 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9547 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9548 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9549 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9550 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9551 /* LAHF-SAHF insns in 64-bit mode. */
9552 || (flag_code
== CODE_64BIT
9553 && (i
.tm
.base_opcode
| 1) == 0x9f
9554 && i
.tm
.opcode_space
== SPACE_BASE
))
9555 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9556 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9557 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9558 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9559 XOP, FMA4, LPW, TBM, and AMX. */
9560 || (i
.tm
.opcode_modifier
.vex
9561 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9562 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9563 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9564 && !i
.tm
.cpu_flags
.bitfield
.cpuxop
9565 && !i
.tm
.cpu_flags
.bitfield
.cpufma4
9566 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9567 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9568 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9569 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9570 || i
.tm
.cpu_flags
.bitfield
.cpufma
9571 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9572 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9573 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9574 || (x86_feature_2_used
9575 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9576 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9577 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9578 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9579 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9580 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9581 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9582 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9583 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9584 AVX512-4FMAPS, and AVX512-4VNNIW. */
9585 || (i
.tm
.opcode_modifier
.evex
9586 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9587 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9588 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
9589 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9590 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9594 /* Tie dwarf2 debug info to the address at the start of the insn.
9595 We can't do this after the insn has been output as the current
9596 frag may have been closed off. eg. by frag_var. */
9597 dwarf2_emit_insn (0);
9599 insn_start_frag
= frag_now
;
9600 insn_start_off
= frag_now_fix ();
9602 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9605 /* Branch can be 8 bytes. Leave some room for prefixes. */
9606 unsigned int max_branch_padding_size
= 14;
9608 /* Align section to boundary. */
9609 record_alignment (now_seg
, align_branch_power
);
9611 /* Make room for padding. */
9612 frag_grow (max_branch_padding_size
);
9614 /* Start of the padding. */
9619 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9620 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9623 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9624 fragP
->tc_frag_data
.branch_type
= branch
;
9625 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9628 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9629 && !pre_386_16bit_warned
)
9631 as_warn (_("use .code16 to ensure correct addressing mode"));
9632 pre_386_16bit_warned
= true;
9636 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9638 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9639 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9641 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9642 output_interseg_jump ();
9645 /* Output normal instructions here. */
9649 enum mf_cmp_kind mf_cmp
;
9652 && (i
.tm
.base_opcode
== 0xaee8
9653 || i
.tm
.base_opcode
== 0xaef0
9654 || i
.tm
.base_opcode
== 0xaef8))
9656 /* Encode lfence, mfence, and sfence as
9657 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9658 if (flag_code
== CODE_16BIT
)
9659 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9660 else if (omit_lock_prefix
)
9661 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9663 else if (now_seg
!= absolute_section
)
9665 offsetT val
= 0x240483f0ULL
;
9668 md_number_to_chars (p
, val
, 5);
9671 abs_section_offset
+= 5;
9675 /* Some processors fail on LOCK prefix. This options makes
9676 assembler ignore LOCK prefix and serves as a workaround. */
9677 if (omit_lock_prefix
)
9679 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9680 && i
.tm
.opcode_modifier
.isprefix
)
9682 i
.prefix
[LOCK_PREFIX
] = 0;
9686 /* Skip if this is a branch. */
9688 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9690 /* Make room for padding. */
9691 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9696 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9697 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9700 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9701 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9702 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9704 else if (add_branch_prefix_frag_p ())
9706 unsigned int max_prefix_size
= align_branch_prefix_size
;
9708 /* Make room for padding. */
9709 frag_grow (max_prefix_size
);
9714 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9715 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9718 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9721 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9722 don't need the explicit prefix. */
9723 if (!is_any_vex_encoding (&i
.tm
))
9725 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9734 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9735 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9739 switch (i
.opcode_length
)
9744 /* Check for pseudo prefixes. */
9745 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9747 as_bad_where (insn_start_frag
->fr_file
,
9748 insn_start_frag
->fr_line
,
9749 _("pseudo prefix without instruction"));
9759 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9760 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9761 R_X86_64_GOTTPOFF relocation so that linker can safely
9762 perform IE->LE optimization. A dummy REX_OPCODE prefix
9763 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9764 relocation for GDesc -> IE/LE optimization. */
9765 if (x86_elf_abi
== X86_64_X32_ABI
9767 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9768 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9769 && i
.prefix
[REX_PREFIX
] == 0)
9770 add_prefix (REX_OPCODE
);
9773 /* The prefix bytes. */
9774 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9776 frag_opcode_byte (*q
);
9780 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9786 frag_opcode_byte (*q
);
9789 /* There should be no other prefixes for instructions
9794 /* For EVEX instructions i.vrex should become 0 after
9795 build_evex_prefix. For VEX instructions upper 16 registers
9796 aren't available, so VREX should be 0. */
9799 /* Now the VEX prefix. */
9800 if (now_seg
!= absolute_section
)
9802 p
= frag_more (i
.vex
.length
);
9803 for (j
= 0; j
< i
.vex
.length
; j
++)
9804 p
[j
] = i
.vex
.bytes
[j
];
9807 abs_section_offset
+= i
.vex
.length
;
9810 /* Now the opcode; be careful about word order here! */
9811 j
= i
.opcode_length
;
9813 switch (i
.tm
.opcode_space
)
9828 if (now_seg
== absolute_section
)
9829 abs_section_offset
+= j
;
9832 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9838 && i
.tm
.opcode_space
!= SPACE_BASE
)
9841 if (i
.tm
.opcode_space
!= SPACE_0F
)
9842 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
9846 switch (i
.opcode_length
)
9849 /* Put out high byte first: can't use md_number_to_chars! */
9850 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9853 *p
= i
.tm
.base_opcode
& 0xff;
9862 /* Now the modrm byte and sib byte (if present). */
9863 if (i
.tm
.opcode_modifier
.modrm
)
9865 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9867 | (i
.rm
.mode
<< 6));
9868 /* If i.rm.regmem == ESP (4)
9869 && i.rm.mode != (Register mode)
9871 ==> need second modrm byte. */
9872 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9874 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9875 frag_opcode_byte ((i
.sib
.base
<< 0)
9876 | (i
.sib
.index
<< 3)
9877 | (i
.sib
.scale
<< 6));
9880 if (i
.disp_operands
)
9881 output_disp (insn_start_frag
, insn_start_off
);
9884 output_imm (insn_start_frag
, insn_start_off
);
9887 * frag_now_fix () returning plain abs_section_offset when we're in the
9888 * absolute section, and abs_section_offset not getting updated as data
9889 * gets added to the frag breaks the logic below.
9891 if (now_seg
!= absolute_section
)
9893 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9895 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9899 /* NB: Don't add prefix with GOTPC relocation since
9900 output_disp() above depends on the fixed encoding
9901 length. Can't add prefix with TLS relocation since
9902 it breaks TLS linker optimization. */
9903 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9904 /* Prefix count on the current instruction. */
9905 unsigned int count
= i
.vex
.length
;
9907 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9908 /* REX byte is encoded in VEX/EVEX prefix. */
9909 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9912 /* Count prefixes for extended opcode maps. */
9914 switch (i
.tm
.opcode_space
)
9929 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9932 /* Set the maximum prefix size in BRANCH_PREFIX
9934 if (fragP
->tc_frag_data
.max_bytes
> max
)
9935 fragP
->tc_frag_data
.max_bytes
= max
;
9936 if (fragP
->tc_frag_data
.max_bytes
> count
)
9937 fragP
->tc_frag_data
.max_bytes
-= count
;
9939 fragP
->tc_frag_data
.max_bytes
= 0;
9943 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9945 unsigned int max_prefix_size
;
9946 if (align_branch_prefix_size
> max
)
9947 max_prefix_size
= max
;
9949 max_prefix_size
= align_branch_prefix_size
;
9950 if (max_prefix_size
> count
)
9951 fragP
->tc_frag_data
.max_prefix_length
9952 = max_prefix_size
- count
;
9955 /* Use existing segment prefix if possible. Use CS
9956 segment prefix in 64-bit mode. In 32-bit mode, use SS
9957 segment prefix with ESP/EBP base register and use DS
9958 segment prefix without ESP/EBP base register. */
9959 if (i
.prefix
[SEG_PREFIX
])
9960 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9961 else if (flag_code
== CODE_64BIT
)
9962 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9964 && (i
.base_reg
->reg_num
== 4
9965 || i
.base_reg
->reg_num
== 5))
9966 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9968 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9973 /* NB: Don't work with COND_JUMP86 without i386. */
9974 if (align_branch_power
9975 && now_seg
!= absolute_section
9976 && cpu_arch_flags
.bitfield
.cpui386
)
9978 /* Terminate each frag so that we can add prefix and check for
9980 frag_wane (frag_now
);
9987 pi ("" /*line*/, &i
);
9989 #endif /* DEBUG386 */
9992 /* Return the size of the displacement operand N. */
9995 disp_size (unsigned int n
)
9999 if (i
.types
[n
].bitfield
.disp64
)
10001 else if (i
.types
[n
].bitfield
.disp8
)
10003 else if (i
.types
[n
].bitfield
.disp16
)
10008 /* Return the size of the immediate operand N. */
10011 imm_size (unsigned int n
)
10014 if (i
.types
[n
].bitfield
.imm64
)
10016 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10018 else if (i
.types
[n
].bitfield
.imm16
)
10024 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10029 for (n
= 0; n
< i
.operands
; n
++)
10031 if (operand_type_check (i
.types
[n
], disp
))
10033 int size
= disp_size (n
);
10035 if (now_seg
== absolute_section
)
10036 abs_section_offset
+= size
;
10037 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10039 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10041 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10043 p
= frag_more (size
);
10044 md_number_to_chars (p
, val
, size
);
10048 enum bfd_reloc_code_real reloc_type
;
10049 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10050 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10051 && (!want_disp32 (&i
.tm
)
10052 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10053 && !i
.types
[n
].bitfield
.baseindex
)))
10057 /* We can't have 8 bit displacement here. */
10058 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10060 /* The PC relative address is computed relative
10061 to the instruction boundary, so in case immediate
10062 fields follows, we need to adjust the value. */
10063 if (pcrel
&& i
.imm_operands
)
10068 for (n1
= 0; n1
< i
.operands
; n1
++)
10069 if (operand_type_check (i
.types
[n1
], imm
))
10071 /* Only one immediate is allowed for PC
10072 relative address, except with .insn. */
10073 gas_assert (sz
== 0 || dot_insn ());
10074 sz
+= imm_size (n1
);
10076 /* We should find at least one immediate. */
10077 gas_assert (sz
!= 0);
10078 i
.op
[n
].disps
->X_add_number
-= sz
;
10081 p
= frag_more (size
);
10082 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10084 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10085 && (((reloc_type
== BFD_RELOC_32
10086 || reloc_type
== BFD_RELOC_X86_64_32S
10087 || (reloc_type
== BFD_RELOC_64
10089 && (i
.op
[n
].disps
->X_op
== O_symbol
10090 || (i
.op
[n
].disps
->X_op
== O_add
10091 && ((symbol_get_value_expression
10092 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10094 || reloc_type
== BFD_RELOC_32_PCREL
))
10098 reloc_type
= BFD_RELOC_386_GOTPC
;
10099 i
.has_gotpc_tls_reloc
= true;
10100 i
.op
[n
].disps
->X_add_number
+=
10101 encoding_length (insn_start_frag
, insn_start_off
, p
);
10103 else if (reloc_type
== BFD_RELOC_64
)
10104 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10106 /* Don't do the adjustment for x86-64, as there
10107 the pcrel addressing is relative to the _next_
10108 insn, and that is taken care of in other code. */
10109 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10111 else if (align_branch_power
)
10113 switch (reloc_type
)
10115 case BFD_RELOC_386_TLS_GD
:
10116 case BFD_RELOC_386_TLS_LDM
:
10117 case BFD_RELOC_386_TLS_IE
:
10118 case BFD_RELOC_386_TLS_IE_32
:
10119 case BFD_RELOC_386_TLS_GOTIE
:
10120 case BFD_RELOC_386_TLS_GOTDESC
:
10121 case BFD_RELOC_386_TLS_DESC_CALL
:
10122 case BFD_RELOC_X86_64_TLSGD
:
10123 case BFD_RELOC_X86_64_TLSLD
:
10124 case BFD_RELOC_X86_64_GOTTPOFF
:
10125 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10126 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10127 i
.has_gotpc_tls_reloc
= true;
10132 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10133 size
, i
.op
[n
].disps
, pcrel
,
10136 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10137 && !i
.prefix
[ADDR_PREFIX
])
10138 fixP
->fx_signed
= 1;
10140 /* Check for "call/jmp *mem", "mov mem, %reg",
10141 "test %reg, mem" and "binop mem, %reg" where binop
10142 is one of adc, add, and, cmp, or, sbb, sub, xor
10143 instructions without data prefix. Always generate
10144 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10145 if (i
.prefix
[DATA_PREFIX
] == 0
10146 && (generate_relax_relocations
10149 && i
.rm
.regmem
== 5))
10151 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10152 && i
.tm
.opcode_space
== SPACE_BASE
10153 && ((i
.operands
== 1
10154 && i
.tm
.base_opcode
== 0xff
10155 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10156 || (i
.operands
== 2
10157 && (i
.tm
.base_opcode
== 0x8b
10158 || i
.tm
.base_opcode
== 0x85
10159 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10163 fixP
->fx_tcbit
= i
.rex
!= 0;
10165 && (i
.base_reg
->reg_num
== RegIP
))
10166 fixP
->fx_tcbit2
= 1;
10169 fixP
->fx_tcbit2
= 1;
10177 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10182 for (n
= 0; n
< i
.operands
; n
++)
10184 if (operand_type_check (i
.types
[n
], imm
))
10186 int size
= imm_size (n
);
10188 if (now_seg
== absolute_section
)
10189 abs_section_offset
+= size
;
10190 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10194 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10196 p
= frag_more (size
);
10197 md_number_to_chars (p
, val
, size
);
10201 /* Not absolute_section.
10202 Need a 32-bit fixup (don't support 8bit
10203 non-absolute imms). Try to support other
10205 enum bfd_reloc_code_real reloc_type
;
10208 if (i
.types
[n
].bitfield
.imm32s
10209 && (i
.suffix
== QWORD_MNEM_SUFFIX
10210 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10216 p
= frag_more (size
);
10217 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10219 /* This is tough to explain. We end up with this one if we
10220 * have operands that look like
10221 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10222 * obtain the absolute address of the GOT, and it is strongly
10223 * preferable from a performance point of view to avoid using
10224 * a runtime relocation for this. The actual sequence of
10225 * instructions often look something like:
10230 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10232 * The call and pop essentially return the absolute address
10233 * of the label .L66 and store it in %ebx. The linker itself
10234 * will ultimately change the first operand of the addl so
10235 * that %ebx points to the GOT, but to keep things simple, the
10236 * .o file must have this operand set so that it generates not
10237 * the absolute address of .L66, but the absolute address of
10238 * itself. This allows the linker itself simply treat a GOTPC
10239 * relocation as asking for a pcrel offset to the GOT to be
10240 * added in, and the addend of the relocation is stored in the
10241 * operand field for the instruction itself.
10243 * Our job here is to fix the operand so that it would add
10244 * the correct offset so that %ebx would point to itself. The
10245 * thing that is tricky is that .-.L66 will point to the
10246 * beginning of the instruction, so we need to further modify
10247 * the operand so that it will point to itself. There are
10248 * other cases where you have something like:
10250 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10252 * and here no correction would be required. Internally in
10253 * the assembler we treat operands of this form as not being
10254 * pcrel since the '.' is explicitly mentioned, and I wonder
10255 * whether it would simplify matters to do it this way. Who
10256 * knows. In earlier versions of the PIC patches, the
10257 * pcrel_adjust field was used to store the correction, but
10258 * since the expression is not pcrel, I felt it would be
10259 * confusing to do it this way. */
10261 if ((reloc_type
== BFD_RELOC_32
10262 || reloc_type
== BFD_RELOC_X86_64_32S
10263 || reloc_type
== BFD_RELOC_64
)
10265 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10266 && (i
.op
[n
].imms
->X_op
== O_symbol
10267 || (i
.op
[n
].imms
->X_op
== O_add
10268 && ((symbol_get_value_expression
10269 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10273 reloc_type
= BFD_RELOC_386_GOTPC
;
10274 else if (size
== 4)
10275 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10276 else if (size
== 8)
10277 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10278 i
.has_gotpc_tls_reloc
= true;
10279 i
.op
[n
].imms
->X_add_number
+=
10280 encoding_length (insn_start_frag
, insn_start_off
, p
);
10282 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10283 i
.op
[n
].imms
, 0, reloc_type
);
10289 /* x86_cons_fix_new is called via the expression parsing code when a
10290 reloc is needed. We use this hook to get the correct .got reloc. */
10291 static int cons_sign
= -1;
10294 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10295 expressionS
*exp
, bfd_reloc_code_real_type r
)
10297 r
= reloc (len
, 0, cons_sign
, r
);
10300 if (exp
->X_op
== O_secrel
)
10302 exp
->X_op
= O_symbol
;
10303 r
= BFD_RELOC_32_SECREL
;
10305 else if (exp
->X_op
== O_secidx
)
10306 r
= BFD_RELOC_16_SECIDX
;
10309 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10312 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10313 purpose of the `.dc.a' internal pseudo-op. */
10316 x86_address_bytes (void)
10318 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10320 return stdoutput
->arch_info
->bits_per_address
/ 8;
10323 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10324 || defined (LEX_AT)) && !defined (TE_PE)
10325 # define lex_got(reloc, adjust, types) NULL
10327 /* Parse operands of the form
10328 <symbol>@GOTOFF+<nnn>
10329 and similar .plt or .got references.
10331 If we find one, set up the correct relocation in RELOC and copy the
10332 input string, minus the `@GOTOFF' into a malloc'd buffer for
10333 parsing by the calling routine. Return this buffer, and if ADJUST
10334 is non-null set it to the length of the string we removed from the
10335 input line. Otherwise return NULL. */
10337 lex_got (enum bfd_reloc_code_real
*rel
,
10339 i386_operand_type
*types
)
10341 /* Some of the relocations depend on the size of what field is to
10342 be relocated. But in our callers i386_immediate and i386_displacement
10343 we don't yet know the operand size (this will be set by insn
10344 matching). Hence we record the word32 relocation here,
10345 and adjust the reloc according to the real size in reloc(). */
10346 static const struct
10350 const enum bfd_reloc_code_real rel
[2];
10351 const i386_operand_type types64
;
10352 bool need_GOT_symbol
;
10357 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10358 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10359 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10360 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10361 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10362 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10363 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10364 { .imm64 = 1, .disp64 = 1 } }
10367 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10368 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10369 BFD_RELOC_SIZE32
},
10370 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10372 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10373 BFD_RELOC_X86_64_PLTOFF64
},
10374 { .bitfield
= { .imm64
= 1 } }, true },
10375 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10376 BFD_RELOC_X86_64_PLT32
},
10377 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10378 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10379 BFD_RELOC_X86_64_GOTPLT64
},
10380 OPERAND_TYPE_IMM64_DISP64
, true },
10381 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10382 BFD_RELOC_X86_64_GOTOFF64
},
10383 OPERAND_TYPE_IMM64_DISP64
, true },
10384 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10385 BFD_RELOC_X86_64_GOTPCREL
},
10386 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10387 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10388 BFD_RELOC_X86_64_TLSGD
},
10389 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10390 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10391 _dummy_first_bfd_reloc_code_real
},
10392 OPERAND_TYPE_NONE
, true },
10393 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10394 BFD_RELOC_X86_64_TLSLD
},
10395 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10396 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10397 BFD_RELOC_X86_64_GOTTPOFF
},
10398 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10399 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10400 BFD_RELOC_X86_64_TPOFF32
},
10401 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10402 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10403 _dummy_first_bfd_reloc_code_real
},
10404 OPERAND_TYPE_NONE
, true },
10405 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10406 BFD_RELOC_X86_64_DTPOFF32
},
10407 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10408 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10409 _dummy_first_bfd_reloc_code_real
},
10410 OPERAND_TYPE_NONE
, true },
10411 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10412 _dummy_first_bfd_reloc_code_real
},
10413 OPERAND_TYPE_NONE
, true },
10414 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10415 BFD_RELOC_X86_64_GOT32
},
10416 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10417 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10418 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10419 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10420 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10421 BFD_RELOC_X86_64_TLSDESC_CALL
},
10422 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10424 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10425 BFD_RELOC_32_SECREL
},
10426 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10429 #undef OPERAND_TYPE_IMM32_32S_DISP32
10430 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10431 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10432 #undef OPERAND_TYPE_IMM64_DISP64
10438 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10443 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10444 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10447 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10449 int len
= gotrel
[j
].len
;
10450 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10452 if (gotrel
[j
].rel
[object_64bit
] != 0)
10455 char *tmpbuf
, *past_reloc
;
10457 *rel
= gotrel
[j
].rel
[object_64bit
];
10461 if (flag_code
!= CODE_64BIT
)
10463 types
->bitfield
.imm32
= 1;
10464 types
->bitfield
.disp32
= 1;
10467 *types
= gotrel
[j
].types64
;
10470 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10471 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10473 /* The length of the first part of our input line. */
10474 first
= cp
- input_line_pointer
;
10476 /* The second part goes from after the reloc token until
10477 (and including) an end_of_line char or comma. */
10478 past_reloc
= cp
+ 1 + len
;
10480 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10482 second
= cp
+ 1 - past_reloc
;
10484 /* Allocate and copy string. The trailing NUL shouldn't
10485 be necessary, but be safe. */
10486 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10487 memcpy (tmpbuf
, input_line_pointer
, first
);
10488 if (second
!= 0 && *past_reloc
!= ' ')
10489 /* Replace the relocation token with ' ', so that
10490 errors like foo@GOTOFF1 will be detected. */
10491 tmpbuf
[first
++] = ' ';
10493 /* Increment length by 1 if the relocation token is
10498 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10499 tmpbuf
[first
+ second
] = '\0';
10503 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10504 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10509 /* Might be a symbol version string. Don't as_bad here. */
10514 bfd_reloc_code_real_type
10515 x86_cons (expressionS
*exp
, int size
)
10517 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10519 intel_syntax
= -intel_syntax
;
10521 expr_mode
= expr_operator_none
;
10523 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10524 && !defined (LEX_AT)) \
10526 if (size
== 4 || (object_64bit
&& size
== 8))
10528 /* Handle @GOTOFF and the like in an expression. */
10530 char *gotfree_input_line
;
10533 save
= input_line_pointer
;
10534 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10535 if (gotfree_input_line
)
10536 input_line_pointer
= gotfree_input_line
;
10540 if (gotfree_input_line
)
10542 /* expression () has merrily parsed up to the end of line,
10543 or a comma - in the wrong buffer. Transfer how far
10544 input_line_pointer has moved to the right buffer. */
10545 input_line_pointer
= (save
10546 + (input_line_pointer
- gotfree_input_line
)
10548 free (gotfree_input_line
);
10549 if (exp
->X_op
== O_constant
10550 || exp
->X_op
== O_absent
10551 || exp
->X_op
== O_illegal
10552 || exp
->X_op
== O_register
10553 || exp
->X_op
== O_big
)
10555 char c
= *input_line_pointer
;
10556 *input_line_pointer
= 0;
10557 as_bad (_("missing or invalid expression `%s'"), save
);
10558 *input_line_pointer
= c
;
10560 else if ((got_reloc
== BFD_RELOC_386_PLT32
10561 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10562 && exp
->X_op
!= O_symbol
)
10564 char c
= *input_line_pointer
;
10565 *input_line_pointer
= 0;
10566 as_bad (_("invalid PLT expression `%s'"), save
);
10567 *input_line_pointer
= c
;
10575 intel_syntax
= -intel_syntax
;
10578 i386_intel_simplify (exp
);
10580 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10581 if (size
<= 4 && expr_mode
== expr_operator_present
10582 && exp
->X_op
== O_constant
&& !object_64bit
)
10583 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10589 signed_cons (int size
)
10598 s_insn (int dummy ATTRIBUTE_UNUSED
)
10600 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10601 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10605 bool vex
= false, xop
= false, evex
= false;
10606 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10610 saved_char
= *saved_ilp
;
10613 end
= parse_insn (line
, mnemonic
, true);
10617 *saved_ilp
= saved_char
;
10618 ignore_rest_of_line ();
10622 line
+= end
- line
;
10624 current_templates
= &tt
;
10625 i
.tm
.mnem_off
= MN__insn
;
10626 i
.tm
.extension_opcode
= None
;
10628 if (startswith (line
, "VEX")
10629 && (line
[3] == '.' || is_space_char (line
[3])))
10634 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10637 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10639 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10640 && (*e
== '.' || is_space_char (*e
)))
10643 /* Arrange for build_vex_prefix() to emit 0x8f. */
10644 i
.tm
.opcode_space
= SPACE_XOP08
;
10645 i
.insn_opcode_space
= n
;
10649 else if (startswith (line
, "EVEX")
10650 && (line
[4] == '.' || is_space_char (line
[4])))
10657 ? i
.vec_encoding
== vex_encoding_evex
10659 ? i
.vec_encoding
== vex_encoding_vex
10660 || i
.vec_encoding
== vex_encoding_vex3
10661 : i
.vec_encoding
!= vex_encoding_default
)
10663 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10667 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10668 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10670 if (line
> end
&& *line
== '.')
10672 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
10680 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10682 i
.tm
.opcode_modifier
.vex
= VEX128
;
10687 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10689 i
.tm
.opcode_modifier
.vex
= VEX256
;
10694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10699 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
10703 if (line
[3] == 'G')
10706 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10708 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10714 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
10719 if (line
[2] == '2' && line
[3] == '8')
10722 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10724 i
.tm
.opcode_modifier
.vex
= VEX128
;
10730 if (line
[2] == '5' && line
[3] == '6')
10733 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10735 i
.tm
.opcode_modifier
.vex
= VEX256
;
10741 if (evex
&& line
[2] == '1' && line
[3] == '2')
10743 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10750 if (line
> end
&& *line
== '.')
10752 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
10756 if (line
[2] == 'P')
10761 if (line
[2] == '6')
10763 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
10768 case 'F': case 'f':
10769 if (line
[2] == '3')
10771 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
10774 else if (line
[2] == '2')
10776 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
10783 if (line
> end
&& !xop
&& *line
== '.')
10785 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
10789 if (TOUPPER (line
[2]) != 'F')
10791 if (line
[3] == '.' || is_space_char (line
[3]))
10793 i
.insn_opcode_space
= SPACE_0F
;
10796 else if (line
[3] == '3'
10797 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
10798 && (line
[5] == '.' || is_space_char (line
[5])))
10800 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
10806 if (ISDIGIT (line
[2]) && line
[2] != '0')
10809 unsigned long n
= strtoul (line
+ 2, &e
, 10);
10811 if (n
<= (evex
? 15 : 31)
10812 && (*e
== '.' || is_space_char (*e
)))
10814 i
.insn_opcode_space
= n
;
10822 if (line
> end
&& *line
== '.' && line
[1] == 'W')
10824 /* VEX.W, XOP.W, EVEX.W */
10828 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
10832 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
10836 if (line
[3] == 'G')
10838 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
10844 if (i
.tm
.opcode_modifier
.vexw
)
10848 if (line
> end
&& *line
&& !is_space_char (*line
))
10850 /* Improve diagnostic a little. */
10851 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
10856 /* Before processing the opcode expression, find trailing "+r" or
10857 "/<digit>" specifiers. */
10858 for (ptr
= line
; ; ++ptr
)
10863 ptr
= strpbrk (ptr
, "+/,");
10864 if (ptr
== NULL
|| *ptr
== ',')
10867 if (*ptr
== '+' && ptr
[1] == 'r'
10868 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
10872 i
.short_form
= true;
10876 if (*ptr
== '/' && ISDIGIT (ptr
[1])
10877 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
10879 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
10883 i
.tm
.extension_opcode
= n
;
10884 i
.tm
.opcode_modifier
.modrm
= 1;
10889 input_line_pointer
= line
;
10890 val
= get_absolute_expression ();
10891 line
= input_line_pointer
;
10893 if (i
.short_form
&& (val
& 7))
10894 as_warn ("`+r' assumes low three opcode bits to be clear");
10896 for (j
= 1; j
< sizeof(val
); ++j
)
10897 if (!(val
>> (j
* 8)))
10900 /* Trim off a prefix if present. */
10901 if (j
> 1 && !vex
&& !xop
&& !evex
)
10903 uint8_t byte
= val
>> ((j
- 1) * 8);
10907 case DATA_PREFIX_OPCODE
:
10908 case REPE_PREFIX_OPCODE
:
10909 case REPNE_PREFIX_OPCODE
:
10910 if (!add_prefix (byte
))
10912 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
10917 /* Trim off encoding space. */
10918 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
10920 uint8_t byte
= val
>> ((--j
- 1) * 8);
10922 i
.insn_opcode_space
= SPACE_0F
;
10923 switch (byte
& -(j
> 1))
10926 i
.insn_opcode_space
= SPACE_0F38
;
10930 i
.insn_opcode_space
= SPACE_0F3A
;
10934 i
.tm
.opcode_space
= i
.insn_opcode_space
;
10935 val
&= ((uint64_t)1 << (j
* 8)) - 1;
10937 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
10938 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
10939 Also avoid hitting abort() there or in build_evex_prefix(). */
10940 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
10945 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
10948 i
.opcode_length
= j
;
10950 /* Handle operands, if any. */
10953 i386_operand_type combined
;
10954 expressionS
*disp_exp
= NULL
;
10959 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
10967 as_bad (_("expecting operand after ','; got nothing"));
10971 if (i
.mem_operands
> 1)
10973 as_bad (_("too many memory references for `%s'"),
10974 &i386_mnemonics
[MN__insn
]);
10978 /* Are we to emit ModR/M encoding? */
10981 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
10982 || i
.tm
.extension_opcode
!= None
))
10983 i
.tm
.opcode_modifier
.modrm
= 1;
10985 if (!i
.tm
.opcode_modifier
.modrm
10987 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
10988 || i
.mem_operands
))
10990 as_bad (_("too many register/memory operands"));
10994 /* Enforce certain constraints on operands. */
10995 switch (i
.reg_operands
+ i
.mem_operands
10996 + (i
.tm
.extension_opcode
!= None
))
11001 as_bad (_("too few register/memory operands"));
11004 /* Fall through. */
11006 if (i
.tm
.opcode_modifier
.modrm
)
11008 as_bad (_("too few register/memory operands"));
11018 && (i
.op
[0].imms
->X_op
!= O_constant
11019 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11021 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11024 /* Fall through. */
11026 if (i
.vec_encoding
!= vex_encoding_default
)
11028 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11031 /* Fall through. */
11033 as_bad (_("too many register/memory operands"));
11037 /* Bring operands into canonical order (imm, mem, reg). */
11042 for (j
= 1; j
< i
.operands
; ++j
)
11044 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11045 && operand_type_check (i
.types
[j
], imm
))
11046 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11047 && i
.types
[j
].bitfield
.class == ClassNone
))
11049 swap_2_operands (j
- 1, j
);
11056 /* For Intel syntax swap the order of register operands. */
11058 switch (i
.reg_operands
)
11065 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11066 /* Fall through. */
11069 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11076 /* Enforce constraints when using VSIB. */
11078 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11079 || i
.index_reg
->reg_type
.bitfield
.ymmword
11080 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11082 if (i
.vec_encoding
== vex_encoding_default
)
11084 as_bad (_("VSIB unavailable with legacy encoding"));
11088 if (i
.vec_encoding
== vex_encoding_evex
11089 && i
.reg_operands
> 1)
11091 /* We could allow two register operands, encoding the 2nd one in
11092 an 8-bit immediate like for 4-register-operand insns, but that
11093 would require ugly fiddling with process_operands() and/or
11094 build_modrm_byte(). */
11095 as_bad (_("too many register operands with VSIB"));
11099 i
.tm
.opcode_modifier
.sib
= 1;
11102 /* Establish operand size encoding. */
11103 operand_type_set (&combined
, 0);
11105 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11107 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11109 if (operand_type_check (i
.types
[j
], disp
))
11111 i
.types
[j
].bitfield
.baseindex
= 1;
11112 disp_exp
= i
.op
[j
].disps
;
11115 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11117 unsigned int n
= i
.memshift
;
11119 if (i
.types
[j
].bitfield
.byte
)
11121 else if (i
.types
[j
].bitfield
.word
)
11123 else if (i
.types
[j
].bitfield
.dword
)
11125 else if (i
.types
[j
].bitfield
.qword
)
11127 else if (i
.types
[j
].bitfield
.xmmword
)
11129 else if (i
.types
[j
].bitfield
.ymmword
)
11131 else if (i
.types
[j
].bitfield
.zmmword
)
11134 if (i
.memshift
< 32 && n
!= i
.memshift
)
11135 as_warn ("conflicting memory operand size specifiers");
11139 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11140 && j
== i
.broadcast
.operand
)
11143 combined
= operand_type_or (combined
, i
.types
[j
]);
11144 combined
.bitfield
.class = ClassNone
;
11147 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11148 << (i
.memshift
< 32 ? i
.memshift
: 0))
11150 case 64: combined
.bitfield
.zmmword
= 1; break;
11151 case 32: combined
.bitfield
.ymmword
= 1; break;
11152 case 16: combined
.bitfield
.xmmword
= 1; break;
11153 case 8: combined
.bitfield
.qword
= 1; break;
11154 case 4: combined
.bitfield
.dword
= 1; break;
11157 if (i
.vec_encoding
== vex_encoding_default
)
11159 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11161 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11162 : combined
.bitfield
.word
)
11163 && !add_prefix (DATA_PREFIX_OPCODE
))
11166 else if (!i
.tm
.opcode_modifier
.vexw
)
11168 if (flag_code
== CODE_64BIT
)
11170 if (combined
.bitfield
.qword
)
11171 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11172 else if (combined
.bitfield
.dword
)
11173 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11176 if (!i
.tm
.opcode_modifier
.vexw
)
11177 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11182 if (!i
.tm
.opcode_modifier
.vex
)
11184 if (combined
.bitfield
.ymmword
)
11185 i
.tm
.opcode_modifier
.vex
= VEX256
;
11186 else if (combined
.bitfield
.xmmword
)
11187 i
.tm
.opcode_modifier
.vex
= VEX128
;
11192 if (!i
.tm
.opcode_modifier
.evex
)
11194 /* Do _not_ consider AVX512VL here. */
11195 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11196 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11197 else if (combined
.bitfield
.ymmword
)
11198 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11199 else if (combined
.bitfield
.xmmword
)
11200 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11203 if (i
.memshift
>= 32)
11205 unsigned int n
= 0;
11207 switch (i
.tm
.opcode_modifier
.evex
)
11209 case EVEX512
: n
= 64; break;
11210 case EVEX256
: n
= 32; break;
11211 case EVEX128
: n
= 16; break;
11214 if (i
.broadcast
.type
)
11215 n
/= i
.broadcast
.type
;
11218 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11220 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11221 && disp_exp
->X_add_number
!= 0
11222 && i
.disp_encoding
!= disp_encoding_32bit
)
11224 if (!quiet_warnings
)
11225 as_warn ("cannot determine memory operand size");
11226 i
.disp_encoding
= disp_encoding_32bit
;
11231 if (i
.memshift
>= 32)
11234 i
.vec_encoding
= vex_encoding_error
;
11236 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11239 /* Establish size for immediate operands. */
11240 for (j
= 0; j
< i
.imm_operands
; ++j
)
11242 expressionS
*expP
= i
.op
[j
].imms
;
11244 gas_assert (operand_type_check (i
.types
[j
], imm
));
11245 operand_type_set (&i
.types
[j
], 0);
11247 if (i
.imm_bits
[j
] > 32)
11248 i
.types
[j
].bitfield
.imm64
= 1;
11249 else if (i
.imm_bits
[j
] > 16)
11251 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11252 i
.types
[j
].bitfield
.imm32s
= 1;
11254 i
.types
[j
].bitfield
.imm32
= 1;
11256 else if (i
.imm_bits
[j
] > 8)
11257 i
.types
[j
].bitfield
.imm16
= 1;
11258 else if (i
.imm_bits
[j
] > 0)
11260 if (i
.flags
[j
] & Operand_Signed
)
11261 i
.types
[j
].bitfield
.imm8s
= 1;
11263 i
.types
[j
].bitfield
.imm8
= 1;
11265 else if (expP
->X_op
== O_constant
)
11267 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11268 i
.types
[j
].bitfield
.imm1
= 0;
11269 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11270 zapping since smallest_imm_type() sets it unconditionally. */
11271 if (flag_code
!= CODE_64BIT
)
11273 i
.types
[j
].bitfield
.imm64
= 0;
11274 i
.types
[j
].bitfield
.imm32s
= 0;
11275 i
.types
[j
].bitfield
.imm32
= 1;
11277 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11278 i
.types
[j
].bitfield
.imm64
= 0;
11281 /* Non-constant expressions are sized heuristically. */
11284 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11285 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11286 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11290 for (j
= 0; j
< i
.operands
; ++j
)
11291 i
.tm
.operand_types
[j
] = i
.types
[j
];
11293 process_operands ();
11296 /* Don't set opcode until after processing operands, to avoid any
11297 potential special casing there. */
11298 i
.tm
.base_opcode
|= val
;
11300 if (i
.vec_encoding
== vex_encoding_error
11301 || (i
.vec_encoding
!= vex_encoding_evex
11302 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11303 || i
.rounding
.type
!= rc_none
11305 : (i
.broadcast
.type
|| i
.broadcast
.bytes
)
11306 && i
.rounding
.type
!= rc_none
))
11308 as_bad (_("conflicting .insn operands"));
11314 if (!i
.tm
.opcode_modifier
.vex
)
11315 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11317 build_vex_prefix (NULL
);
11318 i
.rex
&= REX_OPCODE
;
11322 if (!i
.tm
.opcode_modifier
.evex
)
11323 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11325 build_evex_prefix ();
11326 i
.rex
&= REX_OPCODE
;
11328 else if (i
.rex
!= 0)
11329 add_prefix (REX_OPCODE
| i
.rex
);
11334 *saved_ilp
= saved_char
;
11335 input_line_pointer
= line
;
11337 demand_empty_rest_of_line ();
11339 /* Make sure dot_insn() won't yield "true" anymore. */
11345 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11352 if (exp
.X_op
== O_symbol
)
11353 exp
.X_op
= O_secrel
;
11355 emit_expr (&exp
, 4);
11357 while (*input_line_pointer
++ == ',');
11359 input_line_pointer
--;
11360 demand_empty_rest_of_line ();
11364 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11371 if (exp
.X_op
== O_symbol
)
11372 exp
.X_op
= O_secidx
;
11374 emit_expr (&exp
, 2);
11376 while (*input_line_pointer
++ == ',');
11378 input_line_pointer
--;
11379 demand_empty_rest_of_line ();
11383 /* Handle Rounding Control / SAE specifiers. */
11386 RC_SAE_specifier (const char *pstr
)
11390 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11392 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11394 if (i
.rounding
.type
!= rc_none
)
11396 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11400 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11402 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11409 /* Handle Vector operations. */
11412 check_VecOperations (char *op_string
)
11414 const reg_entry
*mask
;
11421 if (*op_string
== '{')
11425 /* Check broadcasts. */
11426 if (startswith (op_string
, "1to"))
11428 unsigned int bcst_type
;
11430 if (i
.broadcast
.type
)
11431 goto duplicated_vec_op
;
11434 if (*op_string
== '8')
11436 else if (*op_string
== '4')
11438 else if (*op_string
== '2')
11440 else if (*op_string
== '1'
11441 && *(op_string
+1) == '6')
11446 else if (*op_string
== '3'
11447 && *(op_string
+1) == '2')
11454 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11459 i
.broadcast
.type
= bcst_type
;
11460 i
.broadcast
.operand
= this_operand
;
11462 /* For .insn a data size specifier may be appended. */
11463 if (dot_insn () && *op_string
== ':')
11464 goto dot_insn_modifier
;
11466 /* Check .insn special cases. */
11467 else if (dot_insn () && *op_string
== ':')
11470 switch (op_string
[1])
11475 if (i
.memshift
< 32)
11476 goto duplicated_vec_op
;
11478 n
= strtoul (op_string
+ 2, &end_op
, 0);
11480 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11482 if (i
.memshift
< 32 && n
== 1)
11483 op_string
= end_op
;
11486 case 's': case 'u':
11487 /* This isn't really a "vector" operation, but a sign/size
11488 specifier for immediate operands of .insn. Note that AT&T
11489 syntax handles the same in i386_immediate(). */
11493 if (i
.imm_bits
[this_operand
])
11494 goto duplicated_vec_op
;
11496 n
= strtoul (op_string
+ 2, &end_op
, 0);
11497 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11499 i
.imm_bits
[this_operand
] = n
;
11500 if (op_string
[1] == 's')
11501 i
.flags
[this_operand
] |= Operand_Signed
;
11502 op_string
= end_op
;
11507 /* Check masking operation. */
11508 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11510 if (mask
== &bad_reg
)
11513 /* k0 can't be used for write mask. */
11514 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11516 as_bad (_("`%s%s' can't be used for write mask"),
11517 register_prefix
, mask
->reg_name
);
11524 i
.mask
.operand
= this_operand
;
11526 else if (i
.mask
.reg
->reg_num
)
11527 goto duplicated_vec_op
;
11532 /* Only "{z}" is allowed here. No need to check
11533 zeroing mask explicitly. */
11534 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11536 as_bad (_("invalid write mask `%s'"), saved
);
11541 op_string
= end_op
;
11543 /* Check zeroing-flag for masking operation. */
11544 else if (*op_string
== 'z')
11548 i
.mask
.reg
= reg_k0
;
11549 i
.mask
.zeroing
= 1;
11550 i
.mask
.operand
= this_operand
;
11554 if (i
.mask
.zeroing
)
11557 as_bad (_("duplicated `%s'"), saved
);
11561 i
.mask
.zeroing
= 1;
11563 /* Only "{%k}" is allowed here. No need to check mask
11564 register explicitly. */
11565 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11567 as_bad (_("invalid zeroing-masking `%s'"),
11575 else if (intel_syntax
11576 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11577 i
.rounding
.modifier
= true;
11579 goto unknown_vec_op
;
11581 if (*op_string
!= '}')
11583 as_bad (_("missing `}' in `%s'"), saved
);
11588 /* Strip whitespace since the addition of pseudo prefixes
11589 changed how the scrubber treats '{'. */
11590 if (is_space_char (*op_string
))
11596 /* We don't know this one. */
11597 as_bad (_("unknown vector operation: `%s'"), saved
);
11601 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11603 as_bad (_("zeroing-masking only allowed with write mask"));
11611 i386_immediate (char *imm_start
)
11613 char *save_input_line_pointer
;
11614 char *gotfree_input_line
;
11617 i386_operand_type types
;
11619 operand_type_set (&types
, ~0);
11621 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11623 as_bad (_("at most %d immediate operands are allowed"),
11624 MAX_IMMEDIATE_OPERANDS
);
11628 exp
= &im_expressions
[i
.imm_operands
++];
11629 i
.op
[this_operand
].imms
= exp
;
11631 if (is_space_char (*imm_start
))
11634 save_input_line_pointer
= input_line_pointer
;
11635 input_line_pointer
= imm_start
;
11637 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11638 if (gotfree_input_line
)
11639 input_line_pointer
= gotfree_input_line
;
11641 expr_mode
= expr_operator_none
;
11642 exp_seg
= expression (exp
);
11644 /* For .insn immediates there may be a size specifier. */
11645 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11646 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11649 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11651 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11653 i
.imm_bits
[this_operand
] = n
;
11654 if (input_line_pointer
[2] == 's')
11655 i
.flags
[this_operand
] |= Operand_Signed
;
11656 input_line_pointer
= e
+ 1;
11660 SKIP_WHITESPACE ();
11661 if (*input_line_pointer
)
11662 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11664 input_line_pointer
= save_input_line_pointer
;
11665 if (gotfree_input_line
)
11667 free (gotfree_input_line
);
11669 if (exp
->X_op
== O_constant
)
11670 exp
->X_op
= O_illegal
;
11673 if (exp_seg
== reg_section
)
11675 as_bad (_("illegal immediate register operand %s"), imm_start
);
11679 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
11683 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11684 i386_operand_type types
, const char *imm_start
)
11686 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
11689 as_bad (_("missing or invalid immediate expression `%s'"),
11693 else if (exp
->X_op
== O_constant
)
11695 /* Size it properly later. */
11696 i
.types
[this_operand
].bitfield
.imm64
= 1;
11698 /* If not 64bit, sign/zero extend val, to account for wraparound
11700 if (expr_mode
== expr_operator_present
11701 && flag_code
!= CODE_64BIT
&& !object_64bit
)
11702 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11704 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11705 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11706 && exp_seg
!= absolute_section
11707 && exp_seg
!= text_section
11708 && exp_seg
!= data_section
11709 && exp_seg
!= bss_section
11710 && exp_seg
!= undefined_section
11711 && !bfd_is_com_section (exp_seg
))
11713 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11719 /* This is an address. The size of the address will be
11720 determined later, depending on destination register,
11721 suffix, or the default for the section. */
11722 i
.types
[this_operand
].bitfield
.imm8
= 1;
11723 i
.types
[this_operand
].bitfield
.imm16
= 1;
11724 i
.types
[this_operand
].bitfield
.imm32
= 1;
11725 i
.types
[this_operand
].bitfield
.imm32s
= 1;
11726 i
.types
[this_operand
].bitfield
.imm64
= 1;
11727 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11735 i386_scale (char *scale
)
11738 char *save
= input_line_pointer
;
11740 input_line_pointer
= scale
;
11741 val
= get_absolute_expression ();
11746 i
.log2_scale_factor
= 0;
11749 i
.log2_scale_factor
= 1;
11752 i
.log2_scale_factor
= 2;
11755 i
.log2_scale_factor
= 3;
11759 char sep
= *input_line_pointer
;
11761 *input_line_pointer
= '\0';
11762 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
11764 *input_line_pointer
= sep
;
11765 input_line_pointer
= save
;
11769 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
11771 as_warn (_("scale factor of %d without an index register"),
11772 1 << i
.log2_scale_factor
);
11773 i
.log2_scale_factor
= 0;
11775 scale
= input_line_pointer
;
11776 input_line_pointer
= save
;
11781 i386_displacement (char *disp_start
, char *disp_end
)
11785 char *save_input_line_pointer
;
11786 char *gotfree_input_line
;
11788 i386_operand_type bigdisp
, types
= anydisp
;
11791 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
11793 as_bad (_("at most %d displacement operands are allowed"),
11794 MAX_MEMORY_OPERANDS
);
11798 operand_type_set (&bigdisp
, 0);
11800 || i
.types
[this_operand
].bitfield
.baseindex
11801 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
11802 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
11804 i386_addressing_mode ();
11805 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
11806 if (flag_code
== CODE_64BIT
)
11808 bigdisp
.bitfield
.disp32
= 1;
11810 bigdisp
.bitfield
.disp64
= 1;
11812 else if ((flag_code
== CODE_16BIT
) ^ override
)
11813 bigdisp
.bitfield
.disp16
= 1;
11815 bigdisp
.bitfield
.disp32
= 1;
11819 /* For PC-relative branches, the width of the displacement may be
11820 dependent upon data size, but is never dependent upon address size.
11821 Also make sure to not unintentionally match against a non-PC-relative
11822 branch template. */
11823 static templates aux_templates
;
11824 const insn_template
*t
= current_templates
->start
;
11825 bool has_intel64
= false;
11827 aux_templates
.start
= t
;
11828 while (++t
< current_templates
->end
)
11830 if (t
->opcode_modifier
.jump
11831 != current_templates
->start
->opcode_modifier
.jump
)
11833 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
11834 has_intel64
= true;
11836 if (t
< current_templates
->end
)
11838 aux_templates
.end
= t
;
11839 current_templates
= &aux_templates
;
11842 override
= (i
.prefix
[DATA_PREFIX
] != 0);
11843 if (flag_code
== CODE_64BIT
)
11845 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
11846 && (!intel64
|| !has_intel64
))
11847 bigdisp
.bitfield
.disp16
= 1;
11849 bigdisp
.bitfield
.disp32
= 1;
11854 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
11856 : LONG_MNEM_SUFFIX
));
11857 bigdisp
.bitfield
.disp32
= 1;
11858 if ((flag_code
== CODE_16BIT
) ^ override
)
11860 bigdisp
.bitfield
.disp32
= 0;
11861 bigdisp
.bitfield
.disp16
= 1;
11865 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11868 exp
= &disp_expressions
[i
.disp_operands
];
11869 i
.op
[this_operand
].disps
= exp
;
11871 save_input_line_pointer
= input_line_pointer
;
11872 input_line_pointer
= disp_start
;
11873 END_STRING_AND_SAVE (disp_end
);
11875 #ifndef GCC_ASM_O_HACK
11876 #define GCC_ASM_O_HACK 0
11879 END_STRING_AND_SAVE (disp_end
+ 1);
11880 if (i
.types
[this_operand
].bitfield
.baseIndex
11881 && displacement_string_end
[-1] == '+')
11883 /* This hack is to avoid a warning when using the "o"
11884 constraint within gcc asm statements.
11887 #define _set_tssldt_desc(n,addr,limit,type) \
11888 __asm__ __volatile__ ( \
11889 "movw %w2,%0\n\t" \
11890 "movw %w1,2+%0\n\t" \
11891 "rorl $16,%1\n\t" \
11892 "movb %b1,4+%0\n\t" \
11893 "movb %4,5+%0\n\t" \
11894 "movb $0,6+%0\n\t" \
11895 "movb %h1,7+%0\n\t" \
11897 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
11899 This works great except that the output assembler ends
11900 up looking a bit weird if it turns out that there is
11901 no offset. You end up producing code that looks like:
11914 So here we provide the missing zero. */
11916 *displacement_string_end
= '0';
11919 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11920 if (gotfree_input_line
)
11921 input_line_pointer
= gotfree_input_line
;
11923 expr_mode
= expr_operator_none
;
11924 exp_seg
= expression (exp
);
11926 SKIP_WHITESPACE ();
11927 if (*input_line_pointer
)
11928 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11930 RESTORE_END_STRING (disp_end
+ 1);
11932 input_line_pointer
= save_input_line_pointer
;
11933 if (gotfree_input_line
)
11935 free (gotfree_input_line
);
11937 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
11938 exp
->X_op
= O_illegal
;
11941 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
11943 RESTORE_END_STRING (disp_end
);
11949 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11950 i386_operand_type types
, const char *disp_start
)
11954 /* We do this to make sure that the section symbol is in
11955 the symbol table. We will ultimately change the relocation
11956 to be relative to the beginning of the section. */
11957 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
11958 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
11959 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11961 if (exp
->X_op
!= O_symbol
)
11964 if (S_IS_LOCAL (exp
->X_add_symbol
)
11965 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
11966 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
11967 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
11968 exp
->X_op
= O_subtract
;
11969 exp
->X_op_symbol
= GOT_symbol
;
11970 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
11971 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
11972 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11973 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11975 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11978 else if (exp
->X_op
== O_absent
11979 || exp
->X_op
== O_illegal
11980 || exp
->X_op
== O_big
)
11983 as_bad (_("missing or invalid displacement expression `%s'"),
11988 else if (exp
->X_op
== O_constant
)
11990 /* Sizing gets taken care of by optimize_disp().
11992 If not 64bit, sign/zero extend val, to account for wraparound
11994 if (expr_mode
== expr_operator_present
11995 && flag_code
!= CODE_64BIT
&& !object_64bit
)
11996 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11999 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12000 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12001 && exp_seg
!= absolute_section
12002 && exp_seg
!= text_section
12003 && exp_seg
!= data_section
12004 && exp_seg
!= bss_section
12005 && exp_seg
!= undefined_section
12006 && !bfd_is_com_section (exp_seg
))
12008 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12013 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12014 i
.types
[this_operand
].bitfield
.disp8
= 1;
12016 /* Check if this is a displacement only operand. */
12017 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12018 i
.types
[this_operand
] =
12019 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12020 operand_type_and (i
.types
[this_operand
], types
));
12025 /* Return the active addressing mode, taking address override and
12026 registers forming the address into consideration. Update the
12027 address override prefix if necessary. */
12029 static enum flag_code
12030 i386_addressing_mode (void)
12032 enum flag_code addr_mode
;
12034 if (i
.prefix
[ADDR_PREFIX
])
12035 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12036 else if (flag_code
== CODE_16BIT
12037 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
12038 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12039 from md_assemble() by "is not a valid base/index expression"
12040 when there is a base and/or index. */
12041 && !i
.types
[this_operand
].bitfield
.baseindex
)
12043 /* MPX insn memory operands with neither base nor index must be forced
12044 to use 32-bit addressing in 16-bit mode. */
12045 addr_mode
= CODE_32BIT
;
12046 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12048 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12049 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12053 addr_mode
= flag_code
;
12055 #if INFER_ADDR_PREFIX
12056 if (i
.mem_operands
== 0)
12058 /* Infer address prefix from the first memory operand. */
12059 const reg_entry
*addr_reg
= i
.base_reg
;
12061 if (addr_reg
== NULL
)
12062 addr_reg
= i
.index_reg
;
12066 if (addr_reg
->reg_type
.bitfield
.dword
)
12067 addr_mode
= CODE_32BIT
;
12068 else if (flag_code
!= CODE_64BIT
12069 && addr_reg
->reg_type
.bitfield
.word
)
12070 addr_mode
= CODE_16BIT
;
12072 if (addr_mode
!= flag_code
)
12074 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12076 /* Change the size of any displacement too. At most one
12077 of Disp16 or Disp32 is set.
12078 FIXME. There doesn't seem to be any real need for
12079 separate Disp16 and Disp32 flags. The same goes for
12080 Imm16 and Imm32. Removing them would probably clean
12081 up the code quite a lot. */
12082 if (flag_code
!= CODE_64BIT
12083 && (i
.types
[this_operand
].bitfield
.disp16
12084 || i
.types
[this_operand
].bitfield
.disp32
))
12086 static const i386_operand_type disp16_32
= {
12087 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12090 i
.types
[this_operand
]
12091 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12102 /* Make sure the memory operand we've been dealt is valid.
12103 Return 1 on success, 0 on a failure. */
12106 i386_index_check (const char *operand_string
)
12108 const char *kind
= "base/index";
12109 enum flag_code addr_mode
= i386_addressing_mode ();
12110 const insn_template
*t
= current_templates
->end
- 1;
12112 if (t
->opcode_modifier
.isstring
)
12114 /* Memory operands of string insns are special in that they only allow
12115 a single register (rDI, rSI, or rBX) as their memory address. */
12116 const reg_entry
*expected_reg
;
12117 static const char *di_si
[][2] =
12123 static const char *bx
[] = { "ebx", "bx", "rbx" };
12125 kind
= "string address";
12127 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12129 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12132 if (!t
->operand_types
[0].bitfield
.baseindex
12133 || ((!i
.mem_operands
!= !intel_syntax
)
12134 && t
->operand_types
[1].bitfield
.baseindex
))
12137 = (const reg_entry
*) str_hash_find (reg_hash
,
12138 di_si
[addr_mode
][op
== es_op
]);
12142 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12144 if (i
.base_reg
!= expected_reg
12146 || operand_type_check (i
.types
[this_operand
], disp
))
12148 /* The second memory operand must have the same size as
12152 && !((addr_mode
== CODE_64BIT
12153 && i
.base_reg
->reg_type
.bitfield
.qword
)
12154 || (addr_mode
== CODE_32BIT
12155 ? i
.base_reg
->reg_type
.bitfield
.dword
12156 : i
.base_reg
->reg_type
.bitfield
.word
)))
12159 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12161 intel_syntax
? '[' : '(',
12163 expected_reg
->reg_name
,
12164 intel_syntax
? ']' : ')');
12171 as_bad (_("`%s' is not a valid %s expression"),
12172 operand_string
, kind
);
12177 t
= current_templates
->start
;
12179 if (addr_mode
!= CODE_16BIT
)
12181 /* 32-bit/64-bit checks. */
12182 if (i
.disp_encoding
== disp_encoding_16bit
)
12185 as_bad (_("invalid `%s' prefix"),
12186 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12191 && ((addr_mode
== CODE_64BIT
12192 ? !i
.base_reg
->reg_type
.bitfield
.qword
12193 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12194 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12195 || i
.base_reg
->reg_num
== RegIZ
))
12197 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12198 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12199 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12200 && ((addr_mode
== CODE_64BIT
12201 ? !i
.index_reg
->reg_type
.bitfield
.qword
12202 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12203 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12206 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12207 if (t
->mnem_off
== MN_bndmk
12208 || t
->mnem_off
== MN_bndldx
12209 || t
->mnem_off
== MN_bndstx
12210 || t
->opcode_modifier
.sib
== SIBMEM
)
12212 /* They cannot use RIP-relative addressing. */
12213 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12215 as_bad (_("`%s' cannot be used here"), operand_string
);
12219 /* bndldx and bndstx ignore their scale factor. */
12220 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12221 && i
.log2_scale_factor
)
12222 as_warn (_("register scaling is being ignored here"));
12227 /* 16-bit checks. */
12228 if (i
.disp_encoding
== disp_encoding_32bit
)
12232 && (!i
.base_reg
->reg_type
.bitfield
.word
12233 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12235 && (!i
.index_reg
->reg_type
.bitfield
.word
12236 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12238 && i
.base_reg
->reg_num
< 6
12239 && i
.index_reg
->reg_num
>= 6
12240 && i
.log2_scale_factor
== 0))))
12247 /* Handle vector immediates. */
12250 RC_SAE_immediate (const char *imm_start
)
12252 const char *pstr
= imm_start
;
12257 pstr
= RC_SAE_specifier (pstr
+ 1);
12261 if (*pstr
++ != '}')
12263 as_bad (_("Missing '}': '%s'"), imm_start
);
12266 /* RC/SAE immediate string should contain nothing more. */;
12269 as_bad (_("Junk after '}': '%s'"), imm_start
);
12273 /* Internally this doesn't count as an operand. */
12279 static INLINE
bool starts_memory_operand (char c
)
12282 || is_name_beginner (c
)
12283 || strchr ("([\"+-!~", c
);
12286 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12290 i386_att_operand (char *operand_string
)
12292 const reg_entry
*r
;
12294 char *op_string
= operand_string
;
12296 if (is_space_char (*op_string
))
12299 /* We check for an absolute prefix (differentiating,
12300 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12301 if (*op_string
== ABSOLUTE_PREFIX
12302 && current_templates
->start
->opcode_modifier
.jump
)
12305 if (is_space_char (*op_string
))
12307 i
.jumpabsolute
= true;
12310 /* Check if operand is a register. */
12311 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12313 i386_operand_type temp
;
12318 /* Check for a segment override by searching for ':' after a
12319 segment register. */
12320 op_string
= end_op
;
12321 if (is_space_char (*op_string
))
12323 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12325 i
.seg
[i
.mem_operands
] = r
;
12327 /* Skip the ':' and whitespace. */
12329 if (is_space_char (*op_string
))
12332 /* Handle case of %es:*foo. */
12333 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12334 && current_templates
->start
->opcode_modifier
.jump
)
12337 if (is_space_char (*op_string
))
12339 i
.jumpabsolute
= true;
12342 if (!starts_memory_operand (*op_string
))
12344 as_bad (_("bad memory operand `%s'"), op_string
);
12347 goto do_memory_reference
;
12350 /* Handle vector operations. */
12351 if (*op_string
== '{')
12353 op_string
= check_VecOperations (op_string
);
12354 if (op_string
== NULL
)
12360 as_bad (_("junk `%s' after register"), op_string
);
12364 /* Reject pseudo registers for .insn. */
12365 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12367 as_bad (_("`%s%s' cannot be used here"),
12368 register_prefix
, r
->reg_name
);
12372 temp
= r
->reg_type
;
12373 temp
.bitfield
.baseindex
= 0;
12374 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12376 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12377 i
.op
[this_operand
].regs
= r
;
12380 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12381 operand was also present earlier on. */
12382 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12383 && i
.reg_operands
== 1)
12387 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12388 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12390 as_bad (_("`%s': misplaced `{%s}'"),
12391 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12395 else if (*op_string
== REGISTER_PREFIX
)
12397 as_bad (_("bad register name `%s'"), op_string
);
12400 else if (*op_string
== IMMEDIATE_PREFIX
)
12403 if (i
.jumpabsolute
)
12405 as_bad (_("immediate operand illegal with absolute jump"));
12408 if (!i386_immediate (op_string
))
12410 if (i
.rounding
.type
!= rc_none
)
12412 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12413 insn_name (current_templates
->start
));
12417 else if (RC_SAE_immediate (operand_string
))
12419 /* If it is a RC or SAE immediate, do the necessary placement check:
12420 Only another immediate or a GPR may precede it. */
12421 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12422 || (i
.reg_operands
== 1
12423 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12425 as_bad (_("`%s': misplaced `%s'"),
12426 insn_name (current_templates
->start
), operand_string
);
12430 else if (starts_memory_operand (*op_string
))
12432 /* This is a memory reference of some sort. */
12435 /* Start and end of displacement string expression (if found). */
12436 char *displacement_string_start
;
12437 char *displacement_string_end
;
12439 do_memory_reference
:
12440 /* Check for base index form. We detect the base index form by
12441 looking for an ')' at the end of the operand, searching
12442 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12444 base_string
= op_string
+ strlen (op_string
);
12446 /* Handle vector operations. */
12448 if (is_space_char (*base_string
))
12451 if (*base_string
== '}')
12453 char *vop_start
= NULL
;
12455 while (base_string
-- > op_string
)
12457 if (*base_string
== '"')
12459 if (*base_string
!= '{')
12462 vop_start
= base_string
;
12465 if (is_space_char (*base_string
))
12468 if (*base_string
!= '}')
12476 as_bad (_("unbalanced figure braces"));
12480 if (check_VecOperations (vop_start
) == NULL
)
12484 /* If we only have a displacement, set-up for it to be parsed later. */
12485 displacement_string_start
= op_string
;
12486 displacement_string_end
= base_string
+ 1;
12488 if (*base_string
== ')')
12491 unsigned int parens_not_balanced
= 0;
12492 bool in_quotes
= false;
12494 /* We've already checked that the number of left & right ()'s are
12495 equal, and that there's a matching set of double quotes. */
12496 end_op
= base_string
;
12497 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12499 if (*temp_string
== '\\' && temp_string
[1] == '"')
12501 else if (*temp_string
== '"')
12502 in_quotes
= !in_quotes
;
12503 else if (!in_quotes
)
12505 if (*temp_string
== '(' && !parens_not_balanced
++)
12506 base_string
= temp_string
;
12507 if (*temp_string
== ')')
12508 --parens_not_balanced
;
12512 temp_string
= base_string
;
12514 /* Skip past '(' and whitespace. */
12515 gas_assert (*base_string
== '(');
12517 if (is_space_char (*base_string
))
12520 if (*base_string
== ','
12521 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12524 displacement_string_end
= temp_string
;
12526 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12530 if (i
.base_reg
== &bad_reg
)
12532 base_string
= end_op
;
12533 if (is_space_char (*base_string
))
12537 /* There may be an index reg or scale factor here. */
12538 if (*base_string
== ',')
12541 if (is_space_char (*base_string
))
12544 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12547 if (i
.index_reg
== &bad_reg
)
12549 base_string
= end_op
;
12550 if (is_space_char (*base_string
))
12552 if (*base_string
== ',')
12555 if (is_space_char (*base_string
))
12558 else if (*base_string
!= ')')
12560 as_bad (_("expecting `,' or `)' "
12561 "after index register in `%s'"),
12566 else if (*base_string
== REGISTER_PREFIX
)
12568 end_op
= strchr (base_string
, ',');
12571 as_bad (_("bad register name `%s'"), base_string
);
12575 /* Check for scale factor. */
12576 if (*base_string
!= ')')
12578 char *end_scale
= i386_scale (base_string
);
12583 base_string
= end_scale
;
12584 if (is_space_char (*base_string
))
12586 if (*base_string
!= ')')
12588 as_bad (_("expecting `)' "
12589 "after scale factor in `%s'"),
12594 else if (!i
.index_reg
)
12596 as_bad (_("expecting index register or scale factor "
12597 "after `,'; got '%c'"),
12602 else if (*base_string
!= ')')
12604 as_bad (_("expecting `,' or `)' "
12605 "after base register in `%s'"),
12610 else if (*base_string
== REGISTER_PREFIX
)
12612 end_op
= strchr (base_string
, ',');
12615 as_bad (_("bad register name `%s'"), base_string
);
12620 /* If there's an expression beginning the operand, parse it,
12621 assuming displacement_string_start and
12622 displacement_string_end are meaningful. */
12623 if (displacement_string_start
!= displacement_string_end
)
12625 if (!i386_displacement (displacement_string_start
,
12626 displacement_string_end
))
12630 /* Special case for (%dx) while doing input/output op. */
12632 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12633 && i
.base_reg
->reg_type
.bitfield
.word
12634 && i
.index_reg
== 0
12635 && i
.log2_scale_factor
== 0
12636 && i
.seg
[i
.mem_operands
] == 0
12637 && !operand_type_check (i
.types
[this_operand
], disp
))
12639 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12640 i
.input_output_operand
= true;
12644 if (i386_index_check (operand_string
) == 0)
12646 i
.flags
[this_operand
] |= Operand_Mem
;
12651 /* It's not a memory operand; argh! */
12652 as_bad (_("invalid char %s beginning operand %d `%s'"),
12653 output_invalid (*op_string
),
12658 return 1; /* Normal return. */
12661 /* Calculate the maximum variable size (i.e., excluding fr_fix)
12662 that an rs_machine_dependent frag may reach. */
12665 i386_frag_max_var (fragS
*frag
)
12667 /* The only relaxable frags are for jumps.
12668 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
12669 gas_assert (frag
->fr_type
== rs_machine_dependent
);
12670 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
12673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12675 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
12677 /* STT_GNU_IFUNC symbol must go through PLT. */
12678 if ((symbol_get_bfdsym (fr_symbol
)->flags
12679 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
12682 if (!S_IS_EXTERNAL (fr_symbol
))
12683 /* Symbol may be weak or local. */
12684 return !S_IS_WEAK (fr_symbol
);
12686 /* Global symbols with non-default visibility can't be preempted. */
12687 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
12690 if (fr_var
!= NO_RELOC
)
12691 switch ((enum bfd_reloc_code_real
) fr_var
)
12693 case BFD_RELOC_386_PLT32
:
12694 case BFD_RELOC_X86_64_PLT32
:
12695 /* Symbol with PLT relocation may be preempted. */
12701 /* Global symbols with default visibility in a shared library may be
12702 preempted by another definition. */
12707 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
12708 Note also work for Skylake and Cascadelake.
12709 ---------------------------------------------------------------------
12710 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
12711 | ------ | ----------- | ------- | -------- |
12713 | Jno | N | N | Y |
12714 | Jc/Jb | Y | N | Y |
12715 | Jae/Jnb | Y | N | Y |
12716 | Je/Jz | Y | Y | Y |
12717 | Jne/Jnz | Y | Y | Y |
12718 | Jna/Jbe | Y | N | Y |
12719 | Ja/Jnbe | Y | N | Y |
12721 | Jns | N | N | Y |
12722 | Jp/Jpe | N | N | Y |
12723 | Jnp/Jpo | N | N | Y |
12724 | Jl/Jnge | Y | Y | Y |
12725 | Jge/Jnl | Y | Y | Y |
12726 | Jle/Jng | Y | Y | Y |
12727 | Jg/Jnle | Y | Y | Y |
12728 --------------------------------------------------------------------- */
12730 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
12732 if (mf_cmp
== mf_cmp_alu_cmp
)
12733 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
12734 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
12735 if (mf_cmp
== mf_cmp_incdec
)
12736 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
12737 || mf_jcc
== mf_jcc_jle
);
12738 if (mf_cmp
== mf_cmp_test_and
)
12743 /* Return the next non-empty frag. */
12746 i386_next_non_empty_frag (fragS
*fragP
)
12748 /* There may be a frag with a ".fill 0" when there is no room in
12749 the current frag for frag_grow in output_insn. */
12750 for (fragP
= fragP
->fr_next
;
12752 && fragP
->fr_type
== rs_fill
12753 && fragP
->fr_fix
== 0);
12754 fragP
= fragP
->fr_next
)
12759 /* Return the next jcc frag after BRANCH_PADDING. */
12762 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
12764 fragS
*branch_fragP
;
12768 if (pad_fragP
->fr_type
== rs_machine_dependent
12769 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
12770 == BRANCH_PADDING
))
12772 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
12773 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
12775 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
12776 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
12777 pad_fragP
->tc_frag_data
.mf_type
))
12778 return branch_fragP
;
12784 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
12787 i386_classify_machine_dependent_frag (fragS
*fragP
)
12791 fragS
*branch_fragP
;
12793 unsigned int max_prefix_length
;
12795 if (fragP
->tc_frag_data
.classified
)
12798 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
12799 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
12800 for (next_fragP
= fragP
;
12801 next_fragP
!= NULL
;
12802 next_fragP
= next_fragP
->fr_next
)
12804 next_fragP
->tc_frag_data
.classified
= 1;
12805 if (next_fragP
->fr_type
== rs_machine_dependent
)
12806 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
12808 case BRANCH_PADDING
:
12809 /* The BRANCH_PADDING frag must be followed by a branch
12811 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
12812 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12814 case FUSED_JCC_PADDING
:
12815 /* Check if this is a fused jcc:
12817 CMP like instruction
12821 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
12822 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
12823 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
12826 /* The BRANCH_PADDING frag is merged with the
12827 FUSED_JCC_PADDING frag. */
12828 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12829 /* CMP like instruction size. */
12830 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
12831 frag_wane (pad_fragP
);
12832 /* Skip to branch_fragP. */
12833 next_fragP
= branch_fragP
;
12835 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
12837 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
12839 next_fragP
->fr_subtype
12840 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
12841 next_fragP
->tc_frag_data
.max_bytes
12842 = next_fragP
->tc_frag_data
.max_prefix_length
;
12843 /* This will be updated in the BRANCH_PREFIX scan. */
12844 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
12847 frag_wane (next_fragP
);
12852 /* Stop if there is no BRANCH_PREFIX. */
12853 if (!align_branch_prefix_size
)
12856 /* Scan for BRANCH_PREFIX. */
12857 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
12859 if (fragP
->fr_type
!= rs_machine_dependent
12860 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12864 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
12865 COND_JUMP_PREFIX. */
12866 max_prefix_length
= 0;
12867 for (next_fragP
= fragP
;
12868 next_fragP
!= NULL
;
12869 next_fragP
= next_fragP
->fr_next
)
12871 if (next_fragP
->fr_type
== rs_fill
)
12872 /* Skip rs_fill frags. */
12874 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
12875 /* Stop for all other frags. */
12878 /* rs_machine_dependent frags. */
12879 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12882 /* Count BRANCH_PREFIX frags. */
12883 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
12885 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
12886 frag_wane (next_fragP
);
12890 += next_fragP
->tc_frag_data
.max_bytes
;
12892 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12894 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12895 == FUSED_JCC_PADDING
))
12897 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
12898 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
12902 /* Stop for other rs_machine_dependent frags. */
12906 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
12908 /* Skip to the next frag. */
12909 fragP
= next_fragP
;
12913 /* Compute padding size for
12916 CMP like instruction
12918 COND_JUMP/UNCOND_JUMP
12923 COND_JUMP/UNCOND_JUMP
12927 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
12929 unsigned int offset
, size
, padding_size
;
12930 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
12932 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
12934 address
= fragP
->fr_address
;
12935 address
+= fragP
->fr_fix
;
12937 /* CMP like instrunction size. */
12938 size
= fragP
->tc_frag_data
.cmp_size
;
12940 /* The base size of the branch frag. */
12941 size
+= branch_fragP
->fr_fix
;
12943 /* Add opcode and displacement bytes for the rs_machine_dependent
12945 if (branch_fragP
->fr_type
== rs_machine_dependent
)
12946 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
12948 /* Check if branch is within boundary and doesn't end at the last
12950 offset
= address
& ((1U << align_branch_power
) - 1);
12951 if ((offset
+ size
) >= (1U << align_branch_power
))
12952 /* Padding needed to avoid crossing boundary. */
12953 padding_size
= (1U << align_branch_power
) - offset
;
12955 /* No padding needed. */
12958 /* The return value may be saved in tc_frag_data.length which is
12960 if (!fits_in_unsigned_byte (padding_size
))
12963 return padding_size
;
12966 /* i386_generic_table_relax_frag()
12968 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12969 grow/shrink padding to align branch frags. Hand others to
12973 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12975 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12976 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12978 long padding_size
= i386_branch_padding_size (fragP
, 0);
12979 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12981 /* When the BRANCH_PREFIX frag is used, the computed address
12982 must match the actual address and there should be no padding. */
12983 if (fragP
->tc_frag_data
.padding_address
12984 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12988 /* Update the padding size. */
12990 fragP
->tc_frag_data
.length
= padding_size
;
12994 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12996 fragS
*padding_fragP
, *next_fragP
;
12997 long padding_size
, left_size
, last_size
;
12999 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13000 if (!padding_fragP
)
13001 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13002 return (fragP
->tc_frag_data
.length
13003 - fragP
->tc_frag_data
.last_length
);
13005 /* Compute the relative address of the padding frag in the very
13006 first time where the BRANCH_PREFIX frag sizes are zero. */
13007 if (!fragP
->tc_frag_data
.padding_address
)
13008 fragP
->tc_frag_data
.padding_address
13009 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13011 /* First update the last length from the previous interation. */
13012 left_size
= fragP
->tc_frag_data
.prefix_length
;
13013 for (next_fragP
= fragP
;
13014 next_fragP
!= padding_fragP
;
13015 next_fragP
= next_fragP
->fr_next
)
13016 if (next_fragP
->fr_type
== rs_machine_dependent
13017 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13022 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13026 if (max
> left_size
)
13031 next_fragP
->tc_frag_data
.last_length
= size
;
13035 next_fragP
->tc_frag_data
.last_length
= 0;
13038 /* Check the padding size for the padding frag. */
13039 padding_size
= i386_branch_padding_size
13040 (padding_fragP
, (fragP
->fr_address
13041 + fragP
->tc_frag_data
.padding_address
));
13043 last_size
= fragP
->tc_frag_data
.prefix_length
;
13044 /* Check if there is change from the last interation. */
13045 if (padding_size
== last_size
)
13047 /* Update the expected address of the padding frag. */
13048 padding_fragP
->tc_frag_data
.padding_address
13049 = (fragP
->fr_address
+ padding_size
13050 + fragP
->tc_frag_data
.padding_address
);
13054 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13056 /* No padding if there is no sufficient room. Clear the
13057 expected address of the padding frag. */
13058 padding_fragP
->tc_frag_data
.padding_address
= 0;
13062 /* Store the expected address of the padding frag. */
13063 padding_fragP
->tc_frag_data
.padding_address
13064 = (fragP
->fr_address
+ padding_size
13065 + fragP
->tc_frag_data
.padding_address
);
13067 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13069 /* Update the length for the current interation. */
13070 left_size
= padding_size
;
13071 for (next_fragP
= fragP
;
13072 next_fragP
!= padding_fragP
;
13073 next_fragP
= next_fragP
->fr_next
)
13074 if (next_fragP
->fr_type
== rs_machine_dependent
13075 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13080 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13084 if (max
> left_size
)
13089 next_fragP
->tc_frag_data
.length
= size
;
13093 next_fragP
->tc_frag_data
.length
= 0;
13096 return (fragP
->tc_frag_data
.length
13097 - fragP
->tc_frag_data
.last_length
);
13099 return relax_frag (segment
, fragP
, stretch
);
13102 /* md_estimate_size_before_relax()
13104 Called just before relax() for rs_machine_dependent frags. The x86
13105 assembler uses these frags to handle variable size jump
13108 Any symbol that is now undefined will not become defined.
13109 Return the correct fr_subtype in the frag.
13110 Return the initial "guess for variable size of frag" to caller.
13111 The guess is actually the growth beyond the fixed part. Whatever
13112 we do to grow the fixed or variable part contributes to our
13116 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13118 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13119 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13120 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13122 i386_classify_machine_dependent_frag (fragP
);
13123 return fragP
->tc_frag_data
.length
;
13126 /* We've already got fragP->fr_subtype right; all we have to do is
13127 check for un-relaxable symbols. On an ELF system, we can't relax
13128 an externally visible symbol, because it may be overridden by a
13130 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13131 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13133 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13136 #if defined (OBJ_COFF) && defined (TE_PE)
13137 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13138 && S_IS_WEAK (fragP
->fr_symbol
))
13142 /* Symbol is undefined in this segment, or we need to keep a
13143 reloc so that weak symbols can be overridden. */
13144 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13145 enum bfd_reloc_code_real reloc_type
;
13146 unsigned char *opcode
;
13150 if (fragP
->fr_var
!= NO_RELOC
)
13151 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13152 else if (size
== 2)
13153 reloc_type
= BFD_RELOC_16_PCREL
;
13154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13155 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13156 && need_plt32_p (fragP
->fr_symbol
))
13157 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13160 reloc_type
= BFD_RELOC_32_PCREL
;
13162 old_fr_fix
= fragP
->fr_fix
;
13163 opcode
= (unsigned char *) fragP
->fr_opcode
;
13165 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13168 /* Make jmp (0xeb) a (d)word displacement jump. */
13170 fragP
->fr_fix
+= size
;
13171 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13173 fragP
->fr_offset
, 1,
13179 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13181 /* Negate the condition, and branch past an
13182 unconditional jump. */
13185 /* Insert an unconditional jump. */
13187 /* We added two extra opcode bytes, and have a two byte
13189 fragP
->fr_fix
+= 2 + 2;
13190 fix_new (fragP
, old_fr_fix
+ 2, 2,
13192 fragP
->fr_offset
, 1,
13196 /* Fall through. */
13199 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13201 fragP
->fr_fix
+= 1;
13202 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13204 fragP
->fr_offset
, 1,
13205 BFD_RELOC_8_PCREL
);
13206 fixP
->fx_signed
= 1;
13210 /* This changes the byte-displacement jump 0x7N
13211 to the (d)word-displacement jump 0x0f,0x8N. */
13212 opcode
[1] = opcode
[0] + 0x10;
13213 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13214 /* We've added an opcode byte. */
13215 fragP
->fr_fix
+= 1 + size
;
13216 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13218 fragP
->fr_offset
, 1,
13223 BAD_CASE (fragP
->fr_subtype
);
13227 /* All jumps handled here are signed, but don't unconditionally use a
13228 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13229 around at 4G (outside of 64-bit mode) and 64k. */
13230 if (size
== 4 && flag_code
== CODE_64BIT
)
13231 fixP
->fx_signed
= 1;
13234 return fragP
->fr_fix
- old_fr_fix
;
13237 /* Guess size depending on current relax state. Initially the relax
13238 state will correspond to a short jump and we return 1, because
13239 the variable part of the frag (the branch offset) is one byte
13240 long. However, we can relax a section more than once and in that
13241 case we must either set fr_subtype back to the unrelaxed state,
13242 or return the value for the appropriate branch. */
13243 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13246 /* Called after relax() is finished.
13248 In: Address of frag.
13249 fr_type == rs_machine_dependent.
13250 fr_subtype is what the address relaxed to.
13252 Out: Any fixSs and constants are set up.
13253 Caller will turn frag into a ".space 0". */
13256 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13259 unsigned char *opcode
;
13260 unsigned char *where_to_put_displacement
= NULL
;
13261 offsetT target_address
;
13262 offsetT opcode_address
;
13263 unsigned int extension
= 0;
13264 offsetT displacement_from_opcode_start
;
13266 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13267 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13268 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13270 /* Generate nop padding. */
13271 unsigned int size
= fragP
->tc_frag_data
.length
;
13274 if (size
> fragP
->tc_frag_data
.max_bytes
)
13280 const char *branch
= "branch";
13281 const char *prefix
= "";
13282 fragS
*padding_fragP
;
13283 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13286 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13287 switch (fragP
->tc_frag_data
.default_prefix
)
13292 case CS_PREFIX_OPCODE
:
13295 case DS_PREFIX_OPCODE
:
13298 case ES_PREFIX_OPCODE
:
13301 case FS_PREFIX_OPCODE
:
13304 case GS_PREFIX_OPCODE
:
13307 case SS_PREFIX_OPCODE
:
13312 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13313 "%s within %d-byte boundary\n");
13315 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13316 "align %s within %d-byte boundary\n");
13320 padding_fragP
= fragP
;
13321 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13322 "%s within %d-byte boundary\n");
13326 switch (padding_fragP
->tc_frag_data
.branch_type
)
13328 case align_branch_jcc
:
13331 case align_branch_fused
:
13332 branch
= "fused jcc";
13334 case align_branch_jmp
:
13337 case align_branch_call
:
13340 case align_branch_indirect
:
13341 branch
= "indiret branch";
13343 case align_branch_ret
:
13350 fprintf (stdout
, msg
,
13351 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13352 (long long) fragP
->fr_address
, branch
,
13353 1 << align_branch_power
);
13355 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13356 memset (fragP
->fr_opcode
,
13357 fragP
->tc_frag_data
.default_prefix
, size
);
13359 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13361 fragP
->fr_fix
+= size
;
13366 opcode
= (unsigned char *) fragP
->fr_opcode
;
13368 /* Address we want to reach in file space. */
13369 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13371 /* Address opcode resides at in file space. */
13372 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13374 /* Displacement from opcode start to fill into instruction. */
13375 displacement_from_opcode_start
= target_address
- opcode_address
;
13377 if ((fragP
->fr_subtype
& BIG
) == 0)
13379 /* Don't have to change opcode. */
13380 extension
= 1; /* 1 opcode + 1 displacement */
13381 where_to_put_displacement
= &opcode
[1];
13385 if (no_cond_jump_promotion
13386 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13387 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13388 _("long jump required"));
13390 switch (fragP
->fr_subtype
)
13392 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13393 extension
= 4; /* 1 opcode + 4 displacement */
13395 where_to_put_displacement
= &opcode
[1];
13398 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13399 extension
= 2; /* 1 opcode + 2 displacement */
13401 where_to_put_displacement
= &opcode
[1];
13404 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13405 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13406 extension
= 5; /* 2 opcode + 4 displacement */
13407 opcode
[1] = opcode
[0] + 0x10;
13408 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13409 where_to_put_displacement
= &opcode
[2];
13412 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13413 extension
= 3; /* 2 opcode + 2 displacement */
13414 opcode
[1] = opcode
[0] + 0x10;
13415 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13416 where_to_put_displacement
= &opcode
[2];
13419 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13424 where_to_put_displacement
= &opcode
[3];
13428 BAD_CASE (fragP
->fr_subtype
);
13433 /* If size if less then four we are sure that the operand fits,
13434 but if it's 4, then it could be that the displacement is larger
13436 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13438 && ((addressT
) (displacement_from_opcode_start
- extension
13439 + ((addressT
) 1 << 31))
13440 > (((addressT
) 2 << 31) - 1)))
13442 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13443 _("jump target out of range"));
13444 /* Make us emit 0. */
13445 displacement_from_opcode_start
= extension
;
13447 /* Now put displacement after opcode. */
13448 md_number_to_chars ((char *) where_to_put_displacement
,
13449 (valueT
) (displacement_from_opcode_start
- extension
),
13450 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13451 fragP
->fr_fix
+= extension
;
13454 /* Apply a fixup (fixP) to segment data, once it has been determined
13455 by our caller that we have all the info we need to fix it up.
13457 Parameter valP is the pointer to the value of the bits.
13459 On the 386, immediates, displacements, and data pointers are all in
13460 the same (little-endian) format, so we don't need to care about which
13461 we are handling. */
13464 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13466 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13467 valueT value
= *valP
;
13469 #if !defined (TE_Mach)
13470 if (fixP
->fx_pcrel
)
13472 switch (fixP
->fx_r_type
)
13478 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13481 case BFD_RELOC_X86_64_32S
:
13482 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13485 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13488 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13493 if (fixP
->fx_addsy
!= NULL
13494 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13495 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13496 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13497 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13498 && !use_rela_relocations
)
13500 /* This is a hack. There should be a better way to handle this.
13501 This covers for the fact that bfd_install_relocation will
13502 subtract the current location (for partial_inplace, PC relative
13503 relocations); see more below. */
13507 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13510 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13515 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13517 if ((sym_seg
== seg
13518 || (symbol_section_p (fixP
->fx_addsy
)
13519 && sym_seg
!= absolute_section
))
13520 && !generic_force_reloc (fixP
))
13522 /* Yes, we add the values in twice. This is because
13523 bfd_install_relocation subtracts them out again. I think
13524 bfd_install_relocation is broken, but I don't dare change
13526 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13530 #if defined (OBJ_COFF) && defined (TE_PE)
13531 /* For some reason, the PE format does not store a
13532 section address offset for a PC relative symbol. */
13533 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13534 || S_IS_WEAK (fixP
->fx_addsy
))
13535 value
+= md_pcrel_from (fixP
);
13538 #if defined (OBJ_COFF) && defined (TE_PE)
13539 if (fixP
->fx_addsy
!= NULL
13540 && S_IS_WEAK (fixP
->fx_addsy
)
13541 /* PR 16858: Do not modify weak function references. */
13542 && ! fixP
->fx_pcrel
)
13544 #if !defined (TE_PEP)
13545 /* For x86 PE weak function symbols are neither PC-relative
13546 nor do they set S_IS_FUNCTION. So the only reliable way
13547 to detect them is to check the flags of their containing
13549 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13550 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13554 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13558 /* Fix a few things - the dynamic linker expects certain values here,
13559 and we must not disappoint it. */
13560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13561 if (IS_ELF
&& fixP
->fx_addsy
)
13562 switch (fixP
->fx_r_type
)
13564 case BFD_RELOC_386_PLT32
:
13565 case BFD_RELOC_X86_64_PLT32
:
13566 /* Make the jump instruction point to the address of the operand.
13567 At runtime we merely add the offset to the actual PLT entry.
13568 NB: Subtract the offset size only for jump instructions. */
13569 if (fixP
->fx_pcrel
)
13573 case BFD_RELOC_386_TLS_GD
:
13574 case BFD_RELOC_386_TLS_LDM
:
13575 case BFD_RELOC_386_TLS_IE_32
:
13576 case BFD_RELOC_386_TLS_IE
:
13577 case BFD_RELOC_386_TLS_GOTIE
:
13578 case BFD_RELOC_386_TLS_GOTDESC
:
13579 case BFD_RELOC_X86_64_TLSGD
:
13580 case BFD_RELOC_X86_64_TLSLD
:
13581 case BFD_RELOC_X86_64_GOTTPOFF
:
13582 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13583 value
= 0; /* Fully resolved at runtime. No addend. */
13585 case BFD_RELOC_386_TLS_LE
:
13586 case BFD_RELOC_386_TLS_LDO_32
:
13587 case BFD_RELOC_386_TLS_LE_32
:
13588 case BFD_RELOC_X86_64_DTPOFF32
:
13589 case BFD_RELOC_X86_64_DTPOFF64
:
13590 case BFD_RELOC_X86_64_TPOFF32
:
13591 case BFD_RELOC_X86_64_TPOFF64
:
13592 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13595 case BFD_RELOC_386_TLS_DESC_CALL
:
13596 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13597 value
= 0; /* Fully resolved at runtime. No addend. */
13598 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13602 case BFD_RELOC_VTABLE_INHERIT
:
13603 case BFD_RELOC_VTABLE_ENTRY
:
13610 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13612 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13614 value
= extend_to_32bit_address (value
);
13617 #endif /* !defined (TE_Mach) */
13619 /* Are we finished with this relocation now? */
13620 if (fixP
->fx_addsy
== NULL
)
13623 switch (fixP
->fx_r_type
)
13625 case BFD_RELOC_X86_64_32S
:
13626 fixP
->fx_signed
= 1;
13633 #if defined (OBJ_COFF) && defined (TE_PE)
13634 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13637 /* Remember value for tc_gen_reloc. */
13638 fixP
->fx_addnumber
= value
;
13639 /* Clear out the frag for now. */
13643 else if (use_rela_relocations
)
13645 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13646 fixP
->fx_no_overflow
= 1;
13647 /* Remember value for tc_gen_reloc. */
13648 fixP
->fx_addnumber
= value
;
13652 md_number_to_chars (p
, value
, fixP
->fx_size
);
13656 md_atof (int type
, char *litP
, int *sizeP
)
13658 /* This outputs the LITTLENUMs in REVERSE order;
13659 in accord with the bigendian 386. */
13660 return ieee_md_atof (type
, litP
, sizeP
, false);
13663 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
13666 output_invalid (int c
)
13669 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13672 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13673 "(0x%x)", (unsigned char) c
);
13674 return output_invalid_buf
;
13677 /* Verify that @r can be used in the current context. */
13679 static bool check_register (const reg_entry
*r
)
13681 if (allow_pseudo_reg
)
13684 if (operand_type_all_zero (&r
->reg_type
))
13687 if ((r
->reg_type
.bitfield
.dword
13688 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
13689 || r
->reg_type
.bitfield
.class == RegCR
13690 || r
->reg_type
.bitfield
.class == RegDR
)
13691 && !cpu_arch_flags
.bitfield
.cpui386
)
13694 if (r
->reg_type
.bitfield
.class == RegTR
13695 && (flag_code
== CODE_64BIT
13696 || !cpu_arch_flags
.bitfield
.cpui386
13697 || cpu_arch_isa_flags
.bitfield
.cpui586
13698 || cpu_arch_isa_flags
.bitfield
.cpui686
))
13701 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
13704 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
13706 if (r
->reg_type
.bitfield
.zmmword
13707 || r
->reg_type
.bitfield
.class == RegMask
)
13710 if (!cpu_arch_flags
.bitfield
.cpuavx
)
13712 if (r
->reg_type
.bitfield
.ymmword
)
13715 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
13720 if (r
->reg_type
.bitfield
.tmmword
13721 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
13722 || flag_code
!= CODE_64BIT
))
13725 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
13728 /* Don't allow fake index register unless allow_index_reg isn't 0. */
13729 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
13732 /* Upper 16 vector registers are only available with VREX in 64bit
13733 mode, and require EVEX encoding. */
13734 if (r
->reg_flags
& RegVRex
)
13736 if (!cpu_arch_flags
.bitfield
.cpuavx512f
13737 || flag_code
!= CODE_64BIT
)
13740 if (i
.vec_encoding
== vex_encoding_default
)
13741 i
.vec_encoding
= vex_encoding_evex
;
13742 else if (i
.vec_encoding
!= vex_encoding_evex
)
13743 i
.vec_encoding
= vex_encoding_error
;
13746 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
13747 && (!cpu_arch_flags
.bitfield
.cpulm
13748 || r
->reg_type
.bitfield
.class != RegCR
13750 && flag_code
!= CODE_64BIT
)
13753 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
13760 /* REG_STRING starts *before* REGISTER_PREFIX. */
13762 static const reg_entry
*
13763 parse_real_register (const char *reg_string
, char **end_op
)
13765 const char *s
= reg_string
;
13767 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
13768 const reg_entry
*r
;
13770 /* Skip possible REGISTER_PREFIX and possible whitespace. */
13771 if (*s
== REGISTER_PREFIX
)
13774 if (is_space_char (*s
))
13777 p
= reg_name_given
;
13778 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
13780 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
13781 return (const reg_entry
*) NULL
;
13785 if (is_part_of_name (*s
))
13786 return (const reg_entry
*) NULL
;
13788 *end_op
= (char *) s
;
13790 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
13792 /* Handle floating point regs, allowing spaces in the (i) part. */
13795 if (!cpu_arch_flags
.bitfield
.cpu8087
13796 && !cpu_arch_flags
.bitfield
.cpu287
13797 && !cpu_arch_flags
.bitfield
.cpu387
13798 && !allow_pseudo_reg
)
13799 return (const reg_entry
*) NULL
;
13801 if (is_space_char (*s
))
13806 if (is_space_char (*s
))
13808 if (*s
>= '0' && *s
<= '7')
13810 int fpr
= *s
- '0';
13812 if (is_space_char (*s
))
13816 *end_op
= (char *) s
+ 1;
13817 know (r
[fpr
].reg_num
== fpr
);
13821 /* We have "%st(" then garbage. */
13822 return (const reg_entry
*) NULL
;
13826 return r
&& check_register (r
) ? r
: NULL
;
13829 /* REG_STRING starts *before* REGISTER_PREFIX. */
13831 static const reg_entry
*
13832 parse_register (const char *reg_string
, char **end_op
)
13834 const reg_entry
*r
;
13836 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
13837 r
= parse_real_register (reg_string
, end_op
);
13842 char *save
= input_line_pointer
;
13843 char *buf
= xstrdup (reg_string
), *name
;
13846 input_line_pointer
= buf
;
13847 get_symbol_name (&name
);
13848 symbolP
= symbol_find (name
);
13849 while (symbolP
&& symbol_equated_p (symbolP
))
13851 const expressionS
*e
= symbol_get_value_expression(symbolP
);
13853 if (e
->X_add_number
)
13855 symbolP
= e
->X_add_symbol
;
13857 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
13859 const expressionS
*e
= symbol_get_value_expression (symbolP
);
13861 if (e
->X_op
== O_register
)
13863 know (e
->X_add_number
>= 0
13864 && (valueT
) e
->X_add_number
< i386_regtab_size
);
13865 r
= i386_regtab
+ e
->X_add_number
;
13866 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
13868 if (r
&& !check_register (r
))
13870 as_bad (_("register '%s%s' cannot be used here"),
13871 register_prefix
, r
->reg_name
);
13875 input_line_pointer
= save
;
13882 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
13884 const reg_entry
*r
= NULL
;
13885 char *end
= input_line_pointer
;
13888 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
13889 r
= parse_real_register (name
, &input_line_pointer
);
13890 if (r
&& end
<= input_line_pointer
)
13892 *nextcharP
= *input_line_pointer
;
13893 *input_line_pointer
= 0;
13894 e
->X_op
= O_register
;
13895 e
->X_add_number
= r
- i386_regtab
;
13898 input_line_pointer
= end
;
13900 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
13904 md_operand (expressionS
*e
)
13907 const reg_entry
*r
;
13909 switch (*input_line_pointer
)
13911 case REGISTER_PREFIX
:
13912 r
= parse_real_register (input_line_pointer
, &end
);
13915 e
->X_op
= O_register
;
13916 e
->X_add_number
= r
- i386_regtab
;
13917 input_line_pointer
= end
;
13922 gas_assert (intel_syntax
);
13923 end
= input_line_pointer
++;
13925 if (*input_line_pointer
== ']')
13927 ++input_line_pointer
;
13928 e
->X_op_symbol
= make_expr_symbol (e
);
13929 e
->X_add_symbol
= NULL
;
13930 e
->X_add_number
= 0;
13935 e
->X_op
= O_absent
;
13936 input_line_pointer
= end
;
13943 /* To maintain consistency with !BFD64 builds of gas record, whether any
13944 (binary) operator was involved in an expression. As expressions are
13945 evaluated in only 32 bits when !BFD64, we use this to decide whether to
13946 truncate results. */
13947 bool i386_record_operator (operatorT op
,
13948 const expressionS
*left
,
13949 const expressionS
*right
)
13951 if (op
== O_absent
)
13956 /* Since the expression parser applies unary operators fine to bignum
13957 operands, we don't need to be concerned of respective operands not
13958 fitting in 32 bits. */
13959 if (right
->X_op
== O_constant
&& right
->X_unsigned
13960 && !fits_in_unsigned_long (right
->X_add_number
))
13963 /* This isn't entirely right: The pattern can also result when constant
13964 expressions are folded (e.g. 0xffffffff + 1). */
13965 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
13966 && !fits_in_unsigned_long (left
->X_add_number
))
13967 || (right
->X_op
== O_constant
&& right
->X_unsigned
13968 && !fits_in_unsigned_long (right
->X_add_number
)))
13969 expr_mode
= expr_large_value
;
13971 if (expr_mode
!= expr_large_value
)
13972 expr_mode
= expr_operator_present
;
13978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13979 const char *md_shortopts
= "kVQ:sqnO::";
13981 const char *md_shortopts
= "qnO::";
13984 #define OPTION_32 (OPTION_MD_BASE + 0)
13985 #define OPTION_64 (OPTION_MD_BASE + 1)
13986 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
13987 #define OPTION_MARCH (OPTION_MD_BASE + 3)
13988 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
13989 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
13990 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
13991 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13992 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13993 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13994 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13995 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13996 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13997 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13998 #define OPTION_X32 (OPTION_MD_BASE + 14)
13999 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14000 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14001 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14002 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14003 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14004 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14005 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14006 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14007 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14008 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14009 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14010 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14011 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14012 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14013 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14014 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14015 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14016 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14017 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14018 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14020 struct option md_longopts
[] =
14022 {"32", no_argument
, NULL
, OPTION_32
},
14023 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14024 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14025 {"64", no_argument
, NULL
, OPTION_64
},
14027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14028 {"x32", no_argument
, NULL
, OPTION_X32
},
14029 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14030 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14032 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14033 {"march", required_argument
, NULL
, OPTION_MARCH
},
14034 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14035 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14036 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14037 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14038 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14039 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14040 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14041 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14042 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14043 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14044 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14045 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14046 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14047 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14048 # if defined (TE_PE) || defined (TE_PEP)
14049 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14051 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14052 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14053 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14054 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14055 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14056 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14057 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14058 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14059 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14060 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14061 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14062 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14063 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14064 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14065 {NULL
, no_argument
, NULL
, 0}
14067 size_t md_longopts_size
= sizeof (md_longopts
);
14070 md_parse_option (int c
, const char *arg
)
14073 char *arch
, *next
, *saved
, *type
;
14078 optimize_align_code
= 0;
14082 quiet_warnings
= 1;
14085 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14086 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14087 should be emitted or not. FIXME: Not implemented. */
14089 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14093 /* -V: SVR4 argument to print version ID. */
14095 print_version_id ();
14098 /* -k: Ignore for FreeBSD compatibility. */
14103 /* -s: On i386 Solaris, this tells the native assembler to use
14104 .stab instead of .stab.excl. We always use .stab anyhow. */
14107 case OPTION_MSHARED
:
14111 case OPTION_X86_USED_NOTE
:
14112 if (strcasecmp (arg
, "yes") == 0)
14114 else if (strcasecmp (arg
, "no") == 0)
14117 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14122 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14123 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14126 const char **list
, **l
;
14128 list
= bfd_target_list ();
14129 for (l
= list
; *l
!= NULL
; l
++)
14130 if (startswith (*l
, "elf64-x86-64")
14131 || strcmp (*l
, "coff-x86-64") == 0
14132 || strcmp (*l
, "pe-x86-64") == 0
14133 || strcmp (*l
, "pei-x86-64") == 0
14134 || strcmp (*l
, "mach-o-x86-64") == 0)
14136 default_arch
= "x86_64";
14140 as_fatal (_("no compiled in support for x86_64"));
14146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14150 const char **list
, **l
;
14152 list
= bfd_target_list ();
14153 for (l
= list
; *l
!= NULL
; l
++)
14154 if (startswith (*l
, "elf32-x86-64"))
14156 default_arch
= "x86_64:32";
14160 as_fatal (_("no compiled in support for 32bit x86_64"));
14164 as_fatal (_("32bit x86_64 is only supported for ELF"));
14169 default_arch
= "i386";
14172 case OPTION_DIVIDE
:
14173 #ifdef SVR4_COMMENT_CHARS
14178 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14180 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14184 i386_comment_chars
= n
;
14190 saved
= xstrdup (arg
);
14192 /* Allow -march=+nosse. */
14198 as_fatal (_("invalid -march= option: `%s'"), arg
);
14199 next
= strchr (arch
, '+');
14202 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14204 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14205 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14208 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14211 cpu_arch_name
= cpu_arch
[j
].name
;
14212 free (cpu_sub_arch_name
);
14213 cpu_sub_arch_name
= NULL
;
14214 cpu_arch_flags
= cpu_arch
[j
].enable
;
14215 cpu_arch_isa
= cpu_arch
[j
].type
;
14216 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14217 if (!cpu_arch_tune_set
)
14219 cpu_arch_tune
= cpu_arch_isa
;
14220 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14224 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14225 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14226 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14228 /* ISA extension. */
14229 i386_cpu_flags flags
;
14231 flags
= cpu_flags_or (cpu_arch_flags
,
14232 cpu_arch
[j
].enable
);
14234 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14236 extend_cpu_sub_arch_name (arch
);
14237 cpu_arch_flags
= flags
;
14238 cpu_arch_isa_flags
= flags
;
14242 = cpu_flags_or (cpu_arch_isa_flags
,
14243 cpu_arch
[j
].enable
);
14248 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14250 /* Disable an ISA extension. */
14251 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14252 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14253 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14255 i386_cpu_flags flags
;
14257 flags
= cpu_flags_and_not (cpu_arch_flags
,
14258 cpu_arch
[j
].disable
);
14259 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14261 extend_cpu_sub_arch_name (arch
);
14262 cpu_arch_flags
= flags
;
14263 cpu_arch_isa_flags
= flags
;
14269 if (j
>= ARRAY_SIZE (cpu_arch
))
14270 as_fatal (_("invalid -march= option: `%s'"), arg
);
14274 while (next
!= NULL
);
14280 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14281 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14283 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14284 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14286 cpu_arch_tune_set
= 1;
14287 cpu_arch_tune
= cpu_arch
[j
].type
;
14288 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14292 if (j
>= ARRAY_SIZE (cpu_arch
))
14293 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14296 case OPTION_MMNEMONIC
:
14297 if (strcasecmp (arg
, "att") == 0)
14298 intel_mnemonic
= 0;
14299 else if (strcasecmp (arg
, "intel") == 0)
14300 intel_mnemonic
= 1;
14302 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14305 case OPTION_MSYNTAX
:
14306 if (strcasecmp (arg
, "att") == 0)
14308 else if (strcasecmp (arg
, "intel") == 0)
14311 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14314 case OPTION_MINDEX_REG
:
14315 allow_index_reg
= 1;
14318 case OPTION_MNAKED_REG
:
14319 allow_naked_reg
= 1;
14322 case OPTION_MSSE2AVX
:
14326 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14327 use_unaligned_vector_move
= 1;
14330 case OPTION_MSSE_CHECK
:
14331 if (strcasecmp (arg
, "error") == 0)
14332 sse_check
= check_error
;
14333 else if (strcasecmp (arg
, "warning") == 0)
14334 sse_check
= check_warning
;
14335 else if (strcasecmp (arg
, "none") == 0)
14336 sse_check
= check_none
;
14338 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14341 case OPTION_MOPERAND_CHECK
:
14342 if (strcasecmp (arg
, "error") == 0)
14343 operand_check
= check_error
;
14344 else if (strcasecmp (arg
, "warning") == 0)
14345 operand_check
= check_warning
;
14346 else if (strcasecmp (arg
, "none") == 0)
14347 operand_check
= check_none
;
14349 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14352 case OPTION_MAVXSCALAR
:
14353 if (strcasecmp (arg
, "128") == 0)
14354 avxscalar
= vex128
;
14355 else if (strcasecmp (arg
, "256") == 0)
14356 avxscalar
= vex256
;
14358 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14361 case OPTION_MVEXWIG
:
14362 if (strcmp (arg
, "0") == 0)
14364 else if (strcmp (arg
, "1") == 0)
14367 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14370 case OPTION_MADD_BND_PREFIX
:
14371 add_bnd_prefix
= 1;
14374 case OPTION_MEVEXLIG
:
14375 if (strcmp (arg
, "128") == 0)
14376 evexlig
= evexl128
;
14377 else if (strcmp (arg
, "256") == 0)
14378 evexlig
= evexl256
;
14379 else if (strcmp (arg
, "512") == 0)
14380 evexlig
= evexl512
;
14382 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14385 case OPTION_MEVEXRCIG
:
14386 if (strcmp (arg
, "rne") == 0)
14388 else if (strcmp (arg
, "rd") == 0)
14390 else if (strcmp (arg
, "ru") == 0)
14392 else if (strcmp (arg
, "rz") == 0)
14395 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14398 case OPTION_MEVEXWIG
:
14399 if (strcmp (arg
, "0") == 0)
14401 else if (strcmp (arg
, "1") == 0)
14404 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14407 # if defined (TE_PE) || defined (TE_PEP)
14408 case OPTION_MBIG_OBJ
:
14413 case OPTION_MOMIT_LOCK_PREFIX
:
14414 if (strcasecmp (arg
, "yes") == 0)
14415 omit_lock_prefix
= 1;
14416 else if (strcasecmp (arg
, "no") == 0)
14417 omit_lock_prefix
= 0;
14419 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14422 case OPTION_MFENCE_AS_LOCK_ADD
:
14423 if (strcasecmp (arg
, "yes") == 0)
14425 else if (strcasecmp (arg
, "no") == 0)
14428 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14431 case OPTION_MLFENCE_AFTER_LOAD
:
14432 if (strcasecmp (arg
, "yes") == 0)
14433 lfence_after_load
= 1;
14434 else if (strcasecmp (arg
, "no") == 0)
14435 lfence_after_load
= 0;
14437 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14440 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14441 if (strcasecmp (arg
, "all") == 0)
14443 lfence_before_indirect_branch
= lfence_branch_all
;
14444 if (lfence_before_ret
== lfence_before_ret_none
)
14445 lfence_before_ret
= lfence_before_ret_shl
;
14447 else if (strcasecmp (arg
, "memory") == 0)
14448 lfence_before_indirect_branch
= lfence_branch_memory
;
14449 else if (strcasecmp (arg
, "register") == 0)
14450 lfence_before_indirect_branch
= lfence_branch_register
;
14451 else if (strcasecmp (arg
, "none") == 0)
14452 lfence_before_indirect_branch
= lfence_branch_none
;
14454 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14458 case OPTION_MLFENCE_BEFORE_RET
:
14459 if (strcasecmp (arg
, "or") == 0)
14460 lfence_before_ret
= lfence_before_ret_or
;
14461 else if (strcasecmp (arg
, "not") == 0)
14462 lfence_before_ret
= lfence_before_ret_not
;
14463 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14464 lfence_before_ret
= lfence_before_ret_shl
;
14465 else if (strcasecmp (arg
, "none") == 0)
14466 lfence_before_ret
= lfence_before_ret_none
;
14468 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14472 case OPTION_MRELAX_RELOCATIONS
:
14473 if (strcasecmp (arg
, "yes") == 0)
14474 generate_relax_relocations
= 1;
14475 else if (strcasecmp (arg
, "no") == 0)
14476 generate_relax_relocations
= 0;
14478 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14481 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14484 long int align
= strtoul (arg
, &end
, 0);
14489 align_branch_power
= 0;
14492 else if (align
>= 16)
14495 for (align_power
= 0;
14497 align
>>= 1, align_power
++)
14499 /* Limit alignment power to 31. */
14500 if (align
== 1 && align_power
< 32)
14502 align_branch_power
= align_power
;
14507 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14511 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14514 int align
= strtoul (arg
, &end
, 0);
14515 /* Some processors only support 5 prefixes. */
14516 if (*end
== '\0' && align
>= 0 && align
< 6)
14518 align_branch_prefix_size
= align
;
14521 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14526 case OPTION_MALIGN_BRANCH
:
14528 saved
= xstrdup (arg
);
14532 next
= strchr (type
, '+');
14535 if (strcasecmp (type
, "jcc") == 0)
14536 align_branch
|= align_branch_jcc_bit
;
14537 else if (strcasecmp (type
, "fused") == 0)
14538 align_branch
|= align_branch_fused_bit
;
14539 else if (strcasecmp (type
, "jmp") == 0)
14540 align_branch
|= align_branch_jmp_bit
;
14541 else if (strcasecmp (type
, "call") == 0)
14542 align_branch
|= align_branch_call_bit
;
14543 else if (strcasecmp (type
, "ret") == 0)
14544 align_branch
|= align_branch_ret_bit
;
14545 else if (strcasecmp (type
, "indirect") == 0)
14546 align_branch
|= align_branch_indirect_bit
;
14548 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14551 while (next
!= NULL
);
14555 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14556 align_branch_power
= 5;
14557 align_branch_prefix_size
= 5;
14558 align_branch
= (align_branch_jcc_bit
14559 | align_branch_fused_bit
14560 | align_branch_jmp_bit
);
14563 case OPTION_MAMD64
:
14567 case OPTION_MINTEL64
:
14575 /* Turn off -Os. */
14576 optimize_for_space
= 0;
14578 else if (*arg
== 's')
14580 optimize_for_space
= 1;
14581 /* Turn on all encoding optimizations. */
14582 optimize
= INT_MAX
;
14586 optimize
= atoi (arg
);
14587 /* Turn off -Os. */
14588 optimize_for_space
= 0;
14598 #define MESSAGE_TEMPLATE \
14602 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14603 int *left_p
, const char *name
, int len
)
14605 int size
= sizeof (MESSAGE_TEMPLATE
);
14606 int left
= *left_p
;
14608 /* Reserve 2 spaces for ", " or ",\0" */
14611 /* Check if there is any room. */
14619 p
= mempcpy (p
, name
, len
);
14623 /* Output the current message now and start a new one. */
14626 fprintf (stream
, "%s\n", message
);
14628 left
= size
- (start
- message
) - len
- 2;
14630 gas_assert (left
>= 0);
14632 p
= mempcpy (p
, name
, len
);
14640 show_arch (FILE *stream
, int ext
, int check
)
14642 static char message
[] = MESSAGE_TEMPLATE
;
14643 char *start
= message
+ 27;
14645 int size
= sizeof (MESSAGE_TEMPLATE
);
14652 left
= size
- (start
- message
);
14656 p
= output_message (stream
, p
, message
, start
, &left
,
14657 STRING_COMMA_LEN ("default"));
14658 p
= output_message (stream
, p
, message
, start
, &left
,
14659 STRING_COMMA_LEN ("push"));
14660 p
= output_message (stream
, p
, message
, start
, &left
,
14661 STRING_COMMA_LEN ("pop"));
14664 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14666 /* Should it be skipped? */
14667 if (cpu_arch
[j
].skip
)
14670 name
= cpu_arch
[j
].name
;
14671 len
= cpu_arch
[j
].len
;
14672 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
14674 /* It is an extension. Skip if we aren't asked to show it. */
14675 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14680 /* It is an processor. Skip if we show only extension. */
14683 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14685 /* It is an impossible processor - skip. */
14689 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
14692 /* Display disabled extensions. */
14694 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14698 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14699 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14701 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
14702 p
= output_message (stream
, p
, message
, start
, &left
, str
,
14708 fprintf (stream
, "%s\n", message
);
14712 md_show_usage (FILE *stream
)
14714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14715 fprintf (stream
, _("\
14716 -Qy, -Qn ignored\n\
14717 -V print assembler version number\n\
14720 fprintf (stream
, _("\
14721 -n do not optimize code alignment\n\
14722 -O{012s} attempt some code optimizations\n\
14723 -q quieten some warnings\n"));
14724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14725 fprintf (stream
, _("\
14729 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14730 fprintf (stream
, _("\
14731 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
14732 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
14733 fprintf (stream
, _("\
14734 --32/--64 generate 32bit/64bit object\n"));
14737 #ifdef SVR4_COMMENT_CHARS
14738 fprintf (stream
, _("\
14739 --divide do not treat `/' as a comment character\n"));
14741 fprintf (stream
, _("\
14742 --divide ignored\n"));
14744 fprintf (stream
, _("\
14745 -march=CPU[,+EXTENSION...]\n\
14746 generate code for CPU and EXTENSION, CPU is one of:\n"));
14747 show_arch (stream
, 0, 1);
14748 fprintf (stream
, _("\
14749 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
14750 show_arch (stream
, 1, 0);
14751 fprintf (stream
, _("\
14752 -mtune=CPU optimize for CPU, CPU is one of:\n"));
14753 show_arch (stream
, 0, 0);
14754 fprintf (stream
, _("\
14755 -msse2avx encode SSE instructions with VEX prefix\n"));
14756 fprintf (stream
, _("\
14757 -muse-unaligned-vector-move\n\
14758 encode aligned vector move as unaligned vector move\n"));
14759 fprintf (stream
, _("\
14760 -msse-check=[none|error|warning] (default: warning)\n\
14761 check SSE instructions\n"));
14762 fprintf (stream
, _("\
14763 -moperand-check=[none|error|warning] (default: warning)\n\
14764 check operand combinations for validity\n"));
14765 fprintf (stream
, _("\
14766 -mavxscalar=[128|256] (default: 128)\n\
14767 encode scalar AVX instructions with specific vector\n\
14769 fprintf (stream
, _("\
14770 -mvexwig=[0|1] (default: 0)\n\
14771 encode VEX instructions with specific VEX.W value\n\
14772 for VEX.W bit ignored instructions\n"));
14773 fprintf (stream
, _("\
14774 -mevexlig=[128|256|512] (default: 128)\n\
14775 encode scalar EVEX instructions with specific vector\n\
14777 fprintf (stream
, _("\
14778 -mevexwig=[0|1] (default: 0)\n\
14779 encode EVEX instructions with specific EVEX.W value\n\
14780 for EVEX.W bit ignored instructions\n"));
14781 fprintf (stream
, _("\
14782 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
14783 encode EVEX instructions with specific EVEX.RC value\n\
14784 for SAE-only ignored instructions\n"));
14785 fprintf (stream
, _("\
14786 -mmnemonic=[att|intel] "));
14787 if (SYSV386_COMPAT
)
14788 fprintf (stream
, _("(default: att)\n"));
14790 fprintf (stream
, _("(default: intel)\n"));
14791 fprintf (stream
, _("\
14792 use AT&T/Intel mnemonic\n"));
14793 fprintf (stream
, _("\
14794 -msyntax=[att|intel] (default: att)\n\
14795 use AT&T/Intel syntax\n"));
14796 fprintf (stream
, _("\
14797 -mindex-reg support pseudo index registers\n"));
14798 fprintf (stream
, _("\
14799 -mnaked-reg don't require `%%' prefix for registers\n"));
14800 fprintf (stream
, _("\
14801 -madd-bnd-prefix add BND prefix for all valid branches\n"));
14802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14803 fprintf (stream
, _("\
14804 -mshared disable branch optimization for shared code\n"));
14805 fprintf (stream
, _("\
14806 -mx86-used-note=[no|yes] "));
14807 if (DEFAULT_X86_USED_NOTE
)
14808 fprintf (stream
, _("(default: yes)\n"));
14810 fprintf (stream
, _("(default: no)\n"));
14811 fprintf (stream
, _("\
14812 generate x86 used ISA and feature properties\n"));
14814 #if defined (TE_PE) || defined (TE_PEP)
14815 fprintf (stream
, _("\
14816 -mbig-obj generate big object files\n"));
14818 fprintf (stream
, _("\
14819 -momit-lock-prefix=[no|yes] (default: no)\n\
14820 strip all lock prefixes\n"));
14821 fprintf (stream
, _("\
14822 -mfence-as-lock-add=[no|yes] (default: no)\n\
14823 encode lfence, mfence and sfence as\n\
14824 lock addl $0x0, (%%{re}sp)\n"));
14825 fprintf (stream
, _("\
14826 -mrelax-relocations=[no|yes] "));
14827 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
14828 fprintf (stream
, _("(default: yes)\n"));
14830 fprintf (stream
, _("(default: no)\n"));
14831 fprintf (stream
, _("\
14832 generate relax relocations\n"));
14833 fprintf (stream
, _("\
14834 -malign-branch-boundary=NUM (default: 0)\n\
14835 align branches within NUM byte boundary\n"));
14836 fprintf (stream
, _("\
14837 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
14838 TYPE is combination of jcc, fused, jmp, call, ret,\n\
14840 specify types of branches to align\n"));
14841 fprintf (stream
, _("\
14842 -malign-branch-prefix-size=NUM (default: 5)\n\
14843 align branches with NUM prefixes per instruction\n"));
14844 fprintf (stream
, _("\
14845 -mbranches-within-32B-boundaries\n\
14846 align branches within 32 byte boundary\n"));
14847 fprintf (stream
, _("\
14848 -mlfence-after-load=[no|yes] (default: no)\n\
14849 generate lfence after load\n"));
14850 fprintf (stream
, _("\
14851 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
14852 generate lfence before indirect near branch\n"));
14853 fprintf (stream
, _("\
14854 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
14855 generate lfence before ret\n"));
14856 fprintf (stream
, _("\
14857 -mamd64 accept only AMD64 ISA [default]\n"));
14858 fprintf (stream
, _("\
14859 -mintel64 accept only Intel64 ISA\n"));
14862 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
14863 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14864 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14866 /* Pick the target format to use. */
14869 i386_target_format (void)
14871 if (startswith (default_arch
, "x86_64"))
14873 update_code_flag (CODE_64BIT
, 1);
14874 if (default_arch
[6] == '\0')
14875 x86_elf_abi
= X86_64_ABI
;
14877 x86_elf_abi
= X86_64_X32_ABI
;
14879 else if (!strcmp (default_arch
, "i386"))
14880 update_code_flag (CODE_32BIT
, 1);
14881 else if (!strcmp (default_arch
, "iamcu"))
14883 update_code_flag (CODE_32BIT
, 1);
14884 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
14886 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
14887 cpu_arch_name
= "iamcu";
14888 free (cpu_sub_arch_name
);
14889 cpu_sub_arch_name
= NULL
;
14890 cpu_arch_flags
= iamcu_flags
;
14891 cpu_arch_isa
= PROCESSOR_IAMCU
;
14892 cpu_arch_isa_flags
= iamcu_flags
;
14893 if (!cpu_arch_tune_set
)
14895 cpu_arch_tune
= cpu_arch_isa
;
14896 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14899 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
14900 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
14904 as_fatal (_("unknown architecture"));
14906 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
14907 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14908 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
14909 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14911 switch (OUTPUT_FLAVOR
)
14913 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
14914 case bfd_target_aout_flavour
:
14915 return AOUT_TARGET_FORMAT
;
14917 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
14918 # if defined (TE_PE) || defined (TE_PEP)
14919 case bfd_target_coff_flavour
:
14920 if (flag_code
== CODE_64BIT
)
14923 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
14925 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
14926 # elif defined (TE_GO32)
14927 case bfd_target_coff_flavour
:
14928 return "coff-go32";
14930 case bfd_target_coff_flavour
:
14931 return "coff-i386";
14934 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14935 case bfd_target_elf_flavour
:
14937 const char *format
;
14939 switch (x86_elf_abi
)
14942 format
= ELF_TARGET_FORMAT
;
14944 tls_get_addr
= "___tls_get_addr";
14948 use_rela_relocations
= 1;
14951 tls_get_addr
= "__tls_get_addr";
14953 format
= ELF_TARGET_FORMAT64
;
14955 case X86_64_X32_ABI
:
14956 use_rela_relocations
= 1;
14959 tls_get_addr
= "__tls_get_addr";
14961 disallow_64bit_reloc
= 1;
14962 format
= ELF_TARGET_FORMAT32
;
14965 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
14967 if (x86_elf_abi
!= I386_ABI
)
14968 as_fatal (_("Intel MCU is 32bit only"));
14969 return ELF_TARGET_IAMCU_FORMAT
;
14975 #if defined (OBJ_MACH_O)
14976 case bfd_target_mach_o_flavour
:
14977 if (flag_code
== CODE_64BIT
)
14979 use_rela_relocations
= 1;
14981 return "mach-o-x86-64";
14984 return "mach-o-i386";
14992 #endif /* OBJ_MAYBE_ more than one */
14995 md_undefined_symbol (char *name
)
14997 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14998 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14999 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15000 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15004 if (symbol_find (name
))
15005 as_bad (_("GOT already in symbol table"));
15006 GOT_symbol
= symbol_new (name
, undefined_section
,
15007 &zero_address_frag
, 0);
15014 /* Round up a section size to the appropriate boundary. */
15017 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15019 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15020 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15022 /* For a.out, force the section size to be aligned. If we don't do
15023 this, BFD will align it for us, but it will not write out the
15024 final bytes of the section. This may be a bug in BFD, but it is
15025 easier to fix it here since that is how the other a.out targets
15029 align
= bfd_section_alignment (segment
);
15030 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15037 /* On the i386, PC-relative offsets are relative to the start of the
15038 next instruction. That is, the address of the offset, plus its
15039 size, since the offset is always the last part of the insn. */
15042 md_pcrel_from (fixS
*fixP
)
15044 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15050 s_bss (int ignore ATTRIBUTE_UNUSED
)
15054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15056 obj_elf_section_change_hook ();
15058 temp
= get_absolute_expression ();
15059 subseg_set (bss_section
, (subsegT
) temp
);
15060 demand_empty_rest_of_line ();
15065 /* Remember constant directive. */
15068 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15070 if (last_insn
.kind
!= last_insn_directive
15071 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15073 last_insn
.seg
= now_seg
;
15074 last_insn
.kind
= last_insn_directive
;
15075 last_insn
.name
= "constant directive";
15076 last_insn
.file
= as_where (&last_insn
.line
);
15077 if (lfence_before_ret
!= lfence_before_ret_none
)
15079 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15080 as_warn (_("constant directive skips -mlfence-before-ret "
15081 "and -mlfence-before-indirect-branch"));
15083 as_warn (_("constant directive skips -mlfence-before-ret"));
15085 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15086 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15091 i386_validate_fix (fixS
*fixp
)
15093 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15095 reloc_howto_type
*howto
;
15097 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15099 _("invalid %s relocation against register"),
15100 howto
? howto
->name
: "<unknown>");
15104 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15105 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15106 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15107 return IS_ELF
&& fixp
->fx_addsy
15108 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15109 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15112 if (fixp
->fx_subsy
)
15114 if (fixp
->fx_subsy
== GOT_symbol
)
15116 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15121 if (fixp
->fx_tcbit2
)
15122 fixp
->fx_r_type
= (fixp
->fx_tcbit
15123 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15124 : BFD_RELOC_X86_64_GOTPCRELX
);
15127 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15132 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15134 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15136 fixp
->fx_subsy
= 0;
15139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15142 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15143 to section. Since PLT32 relocation must be against symbols,
15144 turn such PLT32 relocation into PC32 relocation. */
15146 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15147 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15148 && symbol_section_p (fixp
->fx_addsy
))
15149 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15152 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15153 && fixp
->fx_tcbit2
)
15154 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15163 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15166 bfd_reloc_code_real_type code
;
15168 switch (fixp
->fx_r_type
)
15170 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15173 case BFD_RELOC_SIZE32
:
15174 case BFD_RELOC_SIZE64
:
15176 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15177 && (!fixp
->fx_subsy
15178 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15179 sym
= fixp
->fx_addsy
;
15180 else if (fixp
->fx_subsy
15181 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15182 && (!fixp
->fx_addsy
15183 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15184 sym
= fixp
->fx_subsy
;
15187 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15189 /* Resolve size relocation against local symbol to size of
15190 the symbol plus addend. */
15191 valueT value
= S_GET_SIZE (sym
);
15193 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15194 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15195 if (sym
== fixp
->fx_subsy
)
15198 if (fixp
->fx_addsy
)
15199 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15201 else if (fixp
->fx_subsy
)
15202 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15203 value
+= fixp
->fx_offset
;
15204 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15206 && !fits_in_unsigned_long (value
))
15207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15208 _("symbol size computation overflow"));
15209 fixp
->fx_addsy
= NULL
;
15210 fixp
->fx_subsy
= NULL
;
15211 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15214 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15216 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15217 "unsupported expression involving @size");
15221 /* Fall through. */
15223 case BFD_RELOC_X86_64_PLT32
:
15224 case BFD_RELOC_X86_64_GOT32
:
15225 case BFD_RELOC_X86_64_GOTPCREL
:
15226 case BFD_RELOC_X86_64_GOTPCRELX
:
15227 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15228 case BFD_RELOC_386_PLT32
:
15229 case BFD_RELOC_386_GOT32
:
15230 case BFD_RELOC_386_GOT32X
:
15231 case BFD_RELOC_386_GOTOFF
:
15232 case BFD_RELOC_386_GOTPC
:
15233 case BFD_RELOC_386_TLS_GD
:
15234 case BFD_RELOC_386_TLS_LDM
:
15235 case BFD_RELOC_386_TLS_LDO_32
:
15236 case BFD_RELOC_386_TLS_IE_32
:
15237 case BFD_RELOC_386_TLS_IE
:
15238 case BFD_RELOC_386_TLS_GOTIE
:
15239 case BFD_RELOC_386_TLS_LE_32
:
15240 case BFD_RELOC_386_TLS_LE
:
15241 case BFD_RELOC_386_TLS_GOTDESC
:
15242 case BFD_RELOC_386_TLS_DESC_CALL
:
15243 case BFD_RELOC_X86_64_TLSGD
:
15244 case BFD_RELOC_X86_64_TLSLD
:
15245 case BFD_RELOC_X86_64_DTPOFF32
:
15246 case BFD_RELOC_X86_64_DTPOFF64
:
15247 case BFD_RELOC_X86_64_GOTTPOFF
:
15248 case BFD_RELOC_X86_64_TPOFF32
:
15249 case BFD_RELOC_X86_64_TPOFF64
:
15250 case BFD_RELOC_X86_64_GOTOFF64
:
15251 case BFD_RELOC_X86_64_GOTPC32
:
15252 case BFD_RELOC_X86_64_GOT64
:
15253 case BFD_RELOC_X86_64_GOTPCREL64
:
15254 case BFD_RELOC_X86_64_GOTPC64
:
15255 case BFD_RELOC_X86_64_GOTPLT64
:
15256 case BFD_RELOC_X86_64_PLTOFF64
:
15257 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15258 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15259 case BFD_RELOC_RVA
:
15260 case BFD_RELOC_VTABLE_ENTRY
:
15261 case BFD_RELOC_VTABLE_INHERIT
:
15263 case BFD_RELOC_32_SECREL
:
15264 case BFD_RELOC_16_SECIDX
:
15266 code
= fixp
->fx_r_type
;
15268 case BFD_RELOC_X86_64_32S
:
15269 if (!fixp
->fx_pcrel
)
15271 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15272 code
= fixp
->fx_r_type
;
15275 /* Fall through. */
15277 if (fixp
->fx_pcrel
)
15279 switch (fixp
->fx_size
)
15282 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15283 _("can not do %d byte pc-relative relocation"),
15285 code
= BFD_RELOC_32_PCREL
;
15287 case 1: code
= BFD_RELOC_8_PCREL
; break;
15288 case 2: code
= BFD_RELOC_16_PCREL
; break;
15289 case 4: code
= BFD_RELOC_32_PCREL
; break;
15291 case 8: code
= BFD_RELOC_64_PCREL
; break;
15297 switch (fixp
->fx_size
)
15300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15301 _("can not do %d byte relocation"),
15303 code
= BFD_RELOC_32
;
15305 case 1: code
= BFD_RELOC_8
; break;
15306 case 2: code
= BFD_RELOC_16
; break;
15307 case 4: code
= BFD_RELOC_32
; break;
15309 case 8: code
= BFD_RELOC_64
; break;
15316 if ((code
== BFD_RELOC_32
15317 || code
== BFD_RELOC_32_PCREL
15318 || code
== BFD_RELOC_X86_64_32S
)
15320 && fixp
->fx_addsy
== GOT_symbol
)
15323 code
= BFD_RELOC_386_GOTPC
;
15325 code
= BFD_RELOC_X86_64_GOTPC32
;
15327 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15329 && fixp
->fx_addsy
== GOT_symbol
)
15331 code
= BFD_RELOC_X86_64_GOTPC64
;
15334 rel
= XNEW (arelent
);
15335 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15336 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15338 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15340 if (!use_rela_relocations
)
15342 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15343 vtable entry to be used in the relocation's section offset. */
15344 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15345 rel
->address
= fixp
->fx_offset
;
15346 #if defined (OBJ_COFF) && defined (TE_PE)
15347 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15348 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15353 /* Use the rela in 64bit mode. */
15356 if (disallow_64bit_reloc
)
15359 case BFD_RELOC_X86_64_DTPOFF64
:
15360 case BFD_RELOC_X86_64_TPOFF64
:
15361 case BFD_RELOC_64_PCREL
:
15362 case BFD_RELOC_X86_64_GOTOFF64
:
15363 case BFD_RELOC_X86_64_GOT64
:
15364 case BFD_RELOC_X86_64_GOTPCREL64
:
15365 case BFD_RELOC_X86_64_GOTPC64
:
15366 case BFD_RELOC_X86_64_GOTPLT64
:
15367 case BFD_RELOC_X86_64_PLTOFF64
:
15368 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15369 _("cannot represent relocation type %s in x32 mode"),
15370 bfd_get_reloc_code_name (code
));
15376 if (!fixp
->fx_pcrel
)
15377 rel
->addend
= fixp
->fx_offset
;
15381 case BFD_RELOC_X86_64_PLT32
:
15382 case BFD_RELOC_X86_64_GOT32
:
15383 case BFD_RELOC_X86_64_GOTPCREL
:
15384 case BFD_RELOC_X86_64_GOTPCRELX
:
15385 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15386 case BFD_RELOC_X86_64_TLSGD
:
15387 case BFD_RELOC_X86_64_TLSLD
:
15388 case BFD_RELOC_X86_64_GOTTPOFF
:
15389 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15390 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15391 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15394 rel
->addend
= (section
->vma
15396 + fixp
->fx_addnumber
15397 + md_pcrel_from (fixp
));
15402 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15403 if (rel
->howto
== NULL
)
15405 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15406 _("cannot represent relocation type %s"),
15407 bfd_get_reloc_code_name (code
));
15408 /* Set howto to a garbage value so that we can keep going. */
15409 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15410 gas_assert (rel
->howto
!= NULL
);
15416 #include "tc-i386-intel.c"
15419 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15421 int saved_naked_reg
;
15422 char saved_register_dot
;
15424 saved_naked_reg
= allow_naked_reg
;
15425 allow_naked_reg
= 1;
15426 saved_register_dot
= register_chars
['.'];
15427 register_chars
['.'] = '.';
15428 allow_pseudo_reg
= 1;
15429 expression_and_evaluate (exp
);
15430 allow_pseudo_reg
= 0;
15431 register_chars
['.'] = saved_register_dot
;
15432 allow_naked_reg
= saved_naked_reg
;
15434 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15436 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15438 exp
->X_op
= O_constant
;
15439 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15440 .dw2_regnum
[flag_code
>> 1];
15443 exp
->X_op
= O_illegal
;
15448 tc_x86_frame_initial_instructions (void)
15450 static unsigned int sp_regno
[2];
15452 if (!sp_regno
[flag_code
>> 1])
15454 char *saved_input
= input_line_pointer
;
15455 char sp
[][4] = {"esp", "rsp"};
15458 input_line_pointer
= sp
[flag_code
>> 1];
15459 tc_x86_parse_to_dw2regnum (&exp
);
15460 gas_assert (exp
.X_op
== O_constant
);
15461 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15462 input_line_pointer
= saved_input
;
15465 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15466 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15470 x86_dwarf2_addr_size (void)
15472 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15473 if (x86_elf_abi
== X86_64_X32_ABI
)
15476 return bfd_arch_bits_per_address (stdoutput
) / 8;
15480 i386_elf_section_type (const char *str
, size_t len
)
15482 if (flag_code
== CODE_64BIT
15483 && len
== sizeof ("unwind") - 1
15484 && startswith (str
, "unwind"))
15485 return SHT_X86_64_UNWIND
;
15492 i386_solaris_fix_up_eh_frame (segT sec
)
15494 if (flag_code
== CODE_64BIT
)
15495 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15501 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15505 exp
.X_op
= O_secrel
;
15506 exp
.X_add_symbol
= symbol
;
15507 exp
.X_add_number
= 0;
15508 emit_expr (&exp
, size
);
15512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15513 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15516 x86_64_section_letter (int letter
, const char **ptr_msg
)
15518 if (flag_code
== CODE_64BIT
)
15521 return SHF_X86_64_LARGE
;
15523 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15526 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15531 x86_64_section_word (char *str
, size_t len
)
15533 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
15534 return SHF_X86_64_LARGE
;
15540 handle_large_common (int small ATTRIBUTE_UNUSED
)
15542 if (flag_code
!= CODE_64BIT
)
15544 s_comm_internal (0, elf_common_parse
);
15545 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15549 static segT lbss_section
;
15550 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15551 asection
*saved_bss_section
= bss_section
;
15553 if (lbss_section
== NULL
)
15555 flagword applicable
;
15556 segT seg
= now_seg
;
15557 subsegT subseg
= now_subseg
;
15559 /* The .lbss section is for local .largecomm symbols. */
15560 lbss_section
= subseg_new (".lbss", 0);
15561 applicable
= bfd_applicable_section_flags (stdoutput
);
15562 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15563 seg_info (lbss_section
)->bss
= 1;
15565 subseg_set (seg
, subseg
);
15568 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15569 bss_section
= lbss_section
;
15571 s_comm_internal (0, elf_common_parse
);
15573 elf_com_section_ptr
= saved_com_section_ptr
;
15574 bss_section
= saved_bss_section
;
15577 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */