1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPCODE_LENGTH holds the number of base opcode bytes. */
318 unsigned char opcode_length
;
320 /* OPERANDS gives the number of given operands. */
321 unsigned int operands
;
323 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
324 of given register, displacement, memory operands and immediate
326 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
328 /* TYPES [i] is the type (see above #defines) which tells us how to
329 use OP[i] for the corresponding operand. */
330 i386_operand_type types
[MAX_OPERANDS
];
332 /* Displacement expression, immediate expression, or register for each
334 union i386_op op
[MAX_OPERANDS
];
336 /* Flags for operands. */
337 unsigned int flags
[MAX_OPERANDS
];
338 #define Operand_PCrel 1
339 #define Operand_Mem 2
341 /* Relocation type for operand */
342 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
344 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
345 the base index byte below. */
346 const reg_entry
*base_reg
;
347 const reg_entry
*index_reg
;
348 unsigned int log2_scale_factor
;
350 /* SEG gives the seg_entries of this insn. They are zero unless
351 explicit segment overrides are given. */
352 const seg_entry
*seg
[2];
354 /* Copied first memory operand string, for re-checking. */
357 /* PREFIX holds all the given prefix opcodes (usually null).
358 PREFIXES is the number of prefix opcodes. */
359 unsigned int prefixes
;
360 unsigned char prefix
[MAX_PREFIXES
];
362 /* Register is in low 3 bits of opcode. */
363 bfd_boolean short_form
;
365 /* The operand to a branch insn indicates an absolute branch. */
366 bfd_boolean jumpabsolute
;
368 /* Extended states. */
376 xstate_ymm
= 1 << 2 | xstate_xmm
,
378 xstate_zmm
= 1 << 3 | xstate_ymm
,
381 /* Use MASK state. */
385 /* Has GOTPC or TLS relocation. */
386 bfd_boolean has_gotpc_tls_reloc
;
388 /* RM and SIB are the modrm byte and the sib byte where the
389 addressing modes of this insn are encoded. */
396 /* Masking attributes. */
397 struct Mask_Operation
*mask
;
399 /* Rounding control and SAE attributes. */
400 struct RC_Operation
*rounding
;
402 /* Broadcasting attributes. */
403 struct Broadcast_Operation
*broadcast
;
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
427 bfd_boolean rex_encoding
;
429 /* Disable instruction size optimization. */
430 bfd_boolean no_optimize
;
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
443 const char *rep_prefix
;
446 const char *hle_prefix
;
448 /* Have BND prefix. */
449 const char *bnd_prefix
;
451 /* Have NOTRACK prefix. */
452 const char *notrack_prefix
;
455 enum i386_error error
;
458 typedef struct _i386_insn i386_insn
;
460 /* Link RC type with corresponding string, that'll be looked for in
469 static const struct RC_name RC_NamesTable
[] =
471 { rne
, STRING_COMMA_LEN ("rn-sae") },
472 { rd
, STRING_COMMA_LEN ("rd-sae") },
473 { ru
, STRING_COMMA_LEN ("ru-sae") },
474 { rz
, STRING_COMMA_LEN ("rz-sae") },
475 { saeonly
, STRING_COMMA_LEN ("sae") },
478 /* List of chars besides those in app.c:symbol_chars that can start an
479 operand. Used to prevent the scrubber eating vital white-space. */
480 const char extra_symbol_chars
[] = "*%-([{}"
489 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
490 && !defined (TE_GNU) \
491 && !defined (TE_LINUX) \
492 && !defined (TE_FreeBSD) \
493 && !defined (TE_DragonFly) \
494 && !defined (TE_NetBSD))
495 /* This array holds the chars that always start a comment. If the
496 pre-processor is disabled, these aren't very useful. The option
497 --divide will remove '/' from this list. */
498 const char *i386_comment_chars
= "#/";
499 #define SVR4_COMMENT_CHARS 1
500 #define PREFIX_SEPARATOR '\\'
503 const char *i386_comment_chars
= "#";
504 #define PREFIX_SEPARATOR '/'
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output.
510 Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output.
513 Also note that comments started like this one will always work if
514 '/' isn't otherwise defined. */
515 const char line_comment_chars
[] = "#/";
517 const char line_separator_chars
[] = ";";
519 /* Chars that can be used to separate mant from exp in floating point
521 const char EXP_CHARS
[] = "eE";
523 /* Chars that mean this number is a floating point constant
526 const char FLT_CHARS
[] = "fFdDxX";
528 /* Tables for lexical analysis. */
529 static char mnemonic_chars
[256];
530 static char register_chars
[256];
531 static char operand_chars
[256];
532 static char identifier_chars
[256];
533 static char digit_chars
[256];
535 /* Lexical macros. */
536 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
537 #define is_operand_char(x) (operand_chars[(unsigned char) x])
538 #define is_register_char(x) (register_chars[(unsigned char) x])
539 #define is_space_char(x) ((x) == ' ')
540 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
541 #define is_digit_char(x) (digit_chars[(unsigned char) x])
543 /* All non-digit non-letter characters that may occur in an operand. */
544 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
546 /* md_assemble() always leaves the strings it's passed unaltered. To
547 effect this we maintain a stack of saved characters that we've smashed
548 with '\0's (indicating end of strings for various sub-fields of the
549 assembler instruction). */
550 static char save_stack
[32];
551 static char *save_stack_p
;
552 #define END_STRING_AND_SAVE(s) \
553 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
554 #define RESTORE_END_STRING(s) \
555 do { *(s) = *--save_stack_p; } while (0)
557 /* The instruction we're assembling. */
560 /* Possible templates for current insn. */
561 static const templates
*current_templates
;
563 /* Per instruction expressionS buffers: max displacements & immediates. */
564 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
565 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
567 /* Current operand we are working on. */
568 static int this_operand
= -1;
570 /* We support four different modes. FLAG_CODE variable is used to distinguish
578 static enum flag_code flag_code
;
579 static unsigned int object_64bit
;
580 static unsigned int disallow_64bit_reloc
;
581 static int use_rela_relocations
= 0;
582 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
583 static const char *tls_get_addr
;
585 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
586 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
587 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
589 /* The ELF ABI to use. */
597 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
600 #if defined (TE_PE) || defined (TE_PEP)
601 /* Use big object file format. */
602 static int use_big_obj
= 0;
605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
606 /* 1 if generating code for a shared library. */
607 static int shared
= 0;
610 /* 1 for intel syntax,
612 static int intel_syntax
= 0;
614 static enum x86_64_isa
616 amd64
= 1, /* AMD64 ISA. */
617 intel64
/* Intel64 ISA. */
620 /* 1 for intel mnemonic,
621 0 if att mnemonic. */
622 static int intel_mnemonic
= !SYSV386_COMPAT
;
624 /* 1 if pseudo registers are permitted. */
625 static int allow_pseudo_reg
= 0;
627 /* 1 if register prefix % not required. */
628 static int allow_naked_reg
= 0;
630 /* 1 if the assembler should add BND prefix for all control-transferring
631 instructions supporting it, even if this prefix wasn't specified
633 static int add_bnd_prefix
= 0;
635 /* 1 if pseudo index register, eiz/riz, is allowed . */
636 static int allow_index_reg
= 0;
638 /* 1 if the assembler should ignore LOCK prefix, even if it was
639 specified explicitly. */
640 static int omit_lock_prefix
= 0;
642 /* 1 if the assembler should encode lfence, mfence, and sfence as
643 "lock addl $0, (%{re}sp)". */
644 static int avoid_fence
= 0;
646 /* 1 if lfence should be inserted after every load. */
647 static int lfence_after_load
= 0;
649 /* Non-zero if lfence should be inserted before indirect branch. */
650 static enum lfence_before_indirect_branch_kind
652 lfence_branch_none
= 0,
653 lfence_branch_register
,
654 lfence_branch_memory
,
657 lfence_before_indirect_branch
;
659 /* Non-zero if lfence should be inserted before ret. */
660 static enum lfence_before_ret_kind
662 lfence_before_ret_none
= 0,
663 lfence_before_ret_not
,
664 lfence_before_ret_or
,
665 lfence_before_ret_shl
669 /* Types of previous instruction is .byte or prefix. */
684 /* 1 if the assembler should generate relax relocations. */
686 static int generate_relax_relocations
687 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
689 static enum check_kind
695 sse_check
, operand_check
= check_warning
;
697 /* Non-zero if branches should be aligned within power of 2 boundary. */
698 static int align_branch_power
= 0;
700 /* Types of branches to align. */
701 enum align_branch_kind
703 align_branch_none
= 0,
704 align_branch_jcc
= 1,
705 align_branch_fused
= 2,
706 align_branch_jmp
= 3,
707 align_branch_call
= 4,
708 align_branch_indirect
= 5,
712 /* Type bits of branches to align. */
713 enum align_branch_bit
715 align_branch_jcc_bit
= 1 << align_branch_jcc
,
716 align_branch_fused_bit
= 1 << align_branch_fused
,
717 align_branch_jmp_bit
= 1 << align_branch_jmp
,
718 align_branch_call_bit
= 1 << align_branch_call
,
719 align_branch_indirect_bit
= 1 << align_branch_indirect
,
720 align_branch_ret_bit
= 1 << align_branch_ret
723 static unsigned int align_branch
= (align_branch_jcc_bit
724 | align_branch_fused_bit
725 | align_branch_jmp_bit
);
727 /* Types of condition jump used by macro-fusion. */
730 mf_jcc_jo
= 0, /* base opcode 0x70 */
731 mf_jcc_jc
, /* base opcode 0x72 */
732 mf_jcc_je
, /* base opcode 0x74 */
733 mf_jcc_jna
, /* base opcode 0x76 */
734 mf_jcc_js
, /* base opcode 0x78 */
735 mf_jcc_jp
, /* base opcode 0x7a */
736 mf_jcc_jl
, /* base opcode 0x7c */
737 mf_jcc_jle
, /* base opcode 0x7e */
740 /* Types of compare flag-modifying insntructions used by macro-fusion. */
743 mf_cmp_test_and
, /* test/cmp */
744 mf_cmp_alu_cmp
, /* add/sub/cmp */
745 mf_cmp_incdec
/* inc/dec */
748 /* The maximum padding size for fused jcc. CMP like instruction can
749 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
751 #define MAX_FUSED_JCC_PADDING_SIZE 20
753 /* The maximum number of prefixes added for an instruction. */
754 static unsigned int align_branch_prefix_size
= 5;
757 1. Clear the REX_W bit with register operand if possible.
758 2. Above plus use 128bit vector instruction to clear the full vector
761 static int optimize
= 0;
764 1. Clear the REX_W bit with register operand if possible.
765 2. Above plus use 128bit vector instruction to clear the full vector
767 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
770 static int optimize_for_space
= 0;
772 /* Register prefix used for error message. */
773 static const char *register_prefix
= "%";
775 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
776 leave, push, and pop instructions so that gcc has the same stack
777 frame as in 32 bit mode. */
778 static char stackop_size
= '\0';
780 /* Non-zero to optimize code alignment. */
781 int optimize_align_code
= 1;
783 /* Non-zero to quieten some warnings. */
784 static int quiet_warnings
= 0;
787 static const char *cpu_arch_name
= NULL
;
788 static char *cpu_sub_arch_name
= NULL
;
790 /* CPU feature flags. */
791 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
793 /* If we have selected a cpu we are generating instructions for. */
794 static int cpu_arch_tune_set
= 0;
796 /* Cpu we are generating instructions for. */
797 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
799 /* CPU feature flags of cpu we are generating instructions for. */
800 static i386_cpu_flags cpu_arch_tune_flags
;
802 /* CPU instruction set architecture used. */
803 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
805 /* CPU feature flags of instruction set architecture used. */
806 i386_cpu_flags cpu_arch_isa_flags
;
808 /* If set, conditional jumps are not automatically promoted to handle
809 larger than a byte offset. */
810 static unsigned int no_cond_jump_promotion
= 0;
812 /* Encode SSE instructions with VEX prefix. */
813 static unsigned int sse2avx
;
815 /* Encode scalar AVX instructions with specific vector length. */
822 /* Encode VEX WIG instructions with specific vex.w. */
829 /* Encode scalar EVEX LIG instructions with specific vector length. */
837 /* Encode EVEX WIG instructions with specific evex.w. */
844 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
845 static enum rc_type evexrcig
= rne
;
847 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
848 static symbolS
*GOT_symbol
;
850 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
851 unsigned int x86_dwarf2_return_column
;
853 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
854 int x86_cie_data_alignment
;
856 /* Interface to relax_segment.
857 There are 3 major relax states for 386 jump insns because the
858 different types of jumps add different sizes to frags when we're
859 figuring out what sort of jump to choose to reach a given label.
861 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
862 branches which are handled by md_estimate_size_before_relax() and
863 i386_generic_table_relax_frag(). */
866 #define UNCOND_JUMP 0
868 #define COND_JUMP86 2
869 #define BRANCH_PADDING 3
870 #define BRANCH_PREFIX 4
871 #define FUSED_JCC_PADDING 5
876 #define SMALL16 (SMALL | CODE16)
878 #define BIG16 (BIG | CODE16)
882 #define INLINE __inline__
888 #define ENCODE_RELAX_STATE(type, size) \
889 ((relax_substateT) (((type) << 2) | (size)))
890 #define TYPE_FROM_RELAX_STATE(s) \
892 #define DISP_SIZE_FROM_RELAX_STATE(s) \
893 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
895 /* This table is used by relax_frag to promote short jumps to long
896 ones where necessary. SMALL (short) jumps may be promoted to BIG
897 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
898 don't allow a short jump in a 32 bit code segment to be promoted to
899 a 16 bit offset jump because it's slower (requires data size
900 prefix), and doesn't work, unless the destination is in the bottom
901 64k of the code segment (The top 16 bits of eip are zeroed). */
903 const relax_typeS md_relax_table
[] =
906 1) most positive reach of this state,
907 2) most negative reach of this state,
908 3) how many bytes this mode will have in the variable part of the frag
909 4) which index into the table to try if we can't fit into this one. */
911 /* UNCOND_JUMP states. */
912 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
914 /* dword jmp adds 4 bytes to frag:
915 0 extra opcode bytes, 4 displacement bytes. */
917 /* word jmp adds 2 byte2 to frag:
918 0 extra opcode bytes, 2 displacement bytes. */
921 /* COND_JUMP states. */
922 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
924 /* dword conditionals adds 5 bytes to frag:
925 1 extra opcode byte, 4 displacement bytes. */
927 /* word conditionals add 3 bytes to frag:
928 1 extra opcode byte, 2 displacement bytes. */
931 /* COND_JUMP86 states. */
932 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
933 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
934 /* dword conditionals adds 5 bytes to frag:
935 1 extra opcode byte, 4 displacement bytes. */
937 /* word conditionals add 4 bytes to frag:
938 1 displacement byte and a 3 byte long branch insn. */
942 static const arch_entry cpu_arch
[] =
944 /* Do not replace the first two entries - i386_target_format()
945 relies on them being there in this order. */
946 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
947 CPU_GENERIC32_FLAGS
, 0 },
948 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
949 CPU_GENERIC64_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
958 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
960 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
962 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
964 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
966 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
967 CPU_PENTIUMPRO_FLAGS
, 0 },
968 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
970 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
972 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
974 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
976 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
977 CPU_NOCONA_FLAGS
, 0 },
978 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
980 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
982 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
983 CPU_CORE2_FLAGS
, 1 },
984 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
985 CPU_CORE2_FLAGS
, 0 },
986 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
987 CPU_COREI7_FLAGS
, 0 },
988 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
990 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
992 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
993 CPU_IAMCU_FLAGS
, 0 },
994 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
996 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
998 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
999 CPU_ATHLON_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
1002 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1004 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1006 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1007 CPU_AMDFAM10_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1009 CPU_BDVER1_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1011 CPU_BDVER2_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1013 CPU_BDVER3_FLAGS
, 0 },
1014 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1015 CPU_BDVER4_FLAGS
, 0 },
1016 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1017 CPU_ZNVER1_FLAGS
, 0 },
1018 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1019 CPU_ZNVER2_FLAGS
, 0 },
1020 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1021 CPU_ZNVER3_FLAGS
, 0 },
1022 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1023 CPU_BTVER1_FLAGS
, 0 },
1024 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1025 CPU_BTVER2_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1027 CPU_8087_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1032 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1034 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1035 CPU_CMOV_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1037 CPU_FXSR_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1040 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1042 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1045 CPU_SSE3_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1047 CPU_SSE4A_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1049 CPU_SSSE3_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1051 CPU_SSE4_1_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1053 CPU_SSE4_2_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1055 CPU_SSE4_2_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX2_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512F_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1063 CPU_AVX512CD_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1065 CPU_AVX512ER_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1067 CPU_AVX512PF_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1069 CPU_AVX512DQ_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1071 CPU_AVX512BW_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1073 CPU_AVX512VL_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1076 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1077 CPU_VMFUNC_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1080 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1081 CPU_XSAVE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1083 CPU_XSAVEOPT_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1085 CPU_XSAVEC_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1087 CPU_XSAVES_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1091 CPU_PCLMUL_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1093 CPU_PCLMUL_FLAGS
, 1 },
1094 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1095 CPU_FSGSBASE_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1097 CPU_RDRND_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1099 CPU_F16C_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1101 CPU_BMI2_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1105 CPU_FMA4_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1108 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1111 CPU_MOVBE_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1113 CPU_CX16_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1116 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1117 CPU_LZCNT_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1119 CPU_POPCNT_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1122 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1124 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1125 CPU_INVPCID_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1127 CPU_CLFLUSH_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1130 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1131 CPU_SYSCALL_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1133 CPU_RDTSCP_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1135 CPU_3DNOW_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1137 CPU_3DNOWA_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1139 CPU_PADLOCK_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1141 CPU_SVME_FLAGS
, 1 },
1142 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1143 CPU_SVME_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1145 CPU_SSE4A_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1148 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1154 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1155 CPU_RDSEED_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1157 CPU_PRFCHW_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1159 CPU_SMAP_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1162 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1164 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1165 CPU_CLFLUSHOPT_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1167 CPU_PREFETCHWT1_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1170 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1171 CPU_CLWB_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512IFMA_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512VBMI_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1177 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1179 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1181 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1183 CPU_AVX512_VBMI2_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1185 CPU_AVX512_VNNI_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1187 CPU_AVX512_BITALG_FLAGS
, 0 },
1188 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1189 CPU_AVX_VNNI_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1191 CPU_CLZERO_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1193 CPU_MWAITX_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1195 CPU_OSPKE_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1197 CPU_RDPID_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1199 CPU_PTWRITE_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1202 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1203 CPU_SHSTK_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1205 CPU_GFNI_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1207 CPU_VAES_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1209 CPU_VPCLMULQDQ_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1211 CPU_WBNOINVD_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1213 CPU_PCONFIG_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1215 CPU_WAITPKG_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1217 CPU_CLDEMOTE_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1219 CPU_AMX_INT8_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1221 CPU_AMX_BF16_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1223 CPU_AMX_TILE_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1225 CPU_MOVDIRI_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1227 CPU_MOVDIR64B_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1229 CPU_AVX512_BF16_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1231 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1234 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1235 CPU_ENQCMD_FLAGS
, 0 },
1236 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1237 CPU_SERIALIZE_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1239 CPU_RDPRU_FLAGS
, 0 },
1240 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1241 CPU_MCOMMIT_FLAGS
, 0 },
1242 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1243 CPU_SEV_ES_FLAGS
, 0 },
1244 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1245 CPU_TSXLDTRK_FLAGS
, 0 },
1246 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1248 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1249 CPU_WIDEKL_FLAGS
, 0 },
1250 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1251 CPU_UINTR_FLAGS
, 0 },
1252 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1253 CPU_HRESET_FLAGS
, 0 },
1256 static const noarch_entry cpu_noarch
[] =
1258 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1259 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1260 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1261 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1262 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1263 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1264 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1266 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1269 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1270 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1271 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1272 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1288 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1289 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1290 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1291 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1292 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1293 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1294 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1295 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1296 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1297 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1298 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1299 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1300 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1301 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1302 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1303 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1304 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1305 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1306 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1307 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1308 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1312 /* Like s_lcomm_internal in gas/read.c but the alignment string
1313 is allowed to be optional. */
1316 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1323 && *input_line_pointer
== ',')
1325 align
= parse_align (needs_align
- 1);
1327 if (align
== (addressT
) -1)
1342 bss_alloc (symbolP
, size
, align
);
1347 pe_lcomm (int needs_align
)
1349 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1353 const pseudo_typeS md_pseudo_table
[] =
1355 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1356 {"align", s_align_bytes
, 0},
1358 {"align", s_align_ptwo
, 0},
1360 {"arch", set_cpu_arch
, 0},
1364 {"lcomm", pe_lcomm
, 1},
1366 {"ffloat", float_cons
, 'f'},
1367 {"dfloat", float_cons
, 'd'},
1368 {"tfloat", float_cons
, 'x'},
1370 {"slong", signed_cons
, 4},
1371 {"noopt", s_ignore
, 0},
1372 {"optim", s_ignore
, 0},
1373 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1374 {"code16", set_code_flag
, CODE_16BIT
},
1375 {"code32", set_code_flag
, CODE_32BIT
},
1377 {"code64", set_code_flag
, CODE_64BIT
},
1379 {"intel_syntax", set_intel_syntax
, 1},
1380 {"att_syntax", set_intel_syntax
, 0},
1381 {"intel_mnemonic", set_intel_mnemonic
, 1},
1382 {"att_mnemonic", set_intel_mnemonic
, 0},
1383 {"allow_index_reg", set_allow_index_reg
, 1},
1384 {"disallow_index_reg", set_allow_index_reg
, 0},
1385 {"sse_check", set_check
, 0},
1386 {"operand_check", set_check
, 1},
1387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1388 {"largecomm", handle_large_common
, 0},
1390 {"file", dwarf2_directive_file
, 0},
1391 {"loc", dwarf2_directive_loc
, 0},
1392 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1395 {"secrel32", pe_directive_secrel
, 0},
1400 /* For interface with expression (). */
1401 extern char *input_line_pointer
;
1403 /* Hash table for instruction mnemonic lookup. */
1404 static htab_t op_hash
;
1406 /* Hash table for register lookup. */
1407 static htab_t reg_hash
;
1409 /* Various efficient no-op patterns for aligning code labels.
1410 Note: Don't try to assemble the instructions in the comments.
1411 0L and 0w are not legal. */
1412 static const unsigned char f32_1
[] =
1414 static const unsigned char f32_2
[] =
1415 {0x66,0x90}; /* xchg %ax,%ax */
1416 static const unsigned char f32_3
[] =
1417 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1418 static const unsigned char f32_4
[] =
1419 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1420 static const unsigned char f32_6
[] =
1421 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1422 static const unsigned char f32_7
[] =
1423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1424 static const unsigned char f16_3
[] =
1425 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1426 static const unsigned char f16_4
[] =
1427 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1428 static const unsigned char jump_disp8
[] =
1429 {0xeb}; /* jmp disp8 */
1430 static const unsigned char jump32_disp32
[] =
1431 {0xe9}; /* jmp disp32 */
1432 static const unsigned char jump16_disp32
[] =
1433 {0x66,0xe9}; /* jmp disp32 */
1434 /* 32-bit NOPs patterns. */
1435 static const unsigned char *const f32_patt
[] = {
1436 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1438 /* 16-bit NOPs patterns. */
1439 static const unsigned char *const f16_patt
[] = {
1440 f32_1
, f32_2
, f16_3
, f16_4
1442 /* nopl (%[re]ax) */
1443 static const unsigned char alt_3
[] =
1445 /* nopl 0(%[re]ax) */
1446 static const unsigned char alt_4
[] =
1447 {0x0f,0x1f,0x40,0x00};
1448 /* nopl 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_5
[] =
1450 {0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopw 0(%[re]ax,%[re]ax,1) */
1452 static const unsigned char alt_6
[] =
1453 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1454 /* nopl 0L(%[re]ax) */
1455 static const unsigned char alt_7
[] =
1456 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1457 /* nopl 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_8
[] =
1459 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw 0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_9
[] =
1462 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1464 static const unsigned char alt_10
[] =
1465 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* data16 nopw %cs:0L(%eax,%eax,1) */
1467 static const unsigned char alt_11
[] =
1468 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1469 /* 32-bit and 64-bit NOPs patterns. */
1470 static const unsigned char *const alt_patt
[] = {
1471 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1472 alt_9
, alt_10
, alt_11
1475 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1476 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1479 i386_output_nops (char *where
, const unsigned char *const *patt
,
1480 int count
, int max_single_nop_size
)
1483 /* Place the longer NOP first. */
1486 const unsigned char *nops
;
1488 if (max_single_nop_size
< 1)
1490 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1491 max_single_nop_size
);
1495 nops
= patt
[max_single_nop_size
- 1];
1497 /* Use the smaller one if the requsted one isn't available. */
1500 max_single_nop_size
--;
1501 nops
= patt
[max_single_nop_size
- 1];
1504 last
= count
% max_single_nop_size
;
1507 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1508 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1512 nops
= patt
[last
- 1];
1515 /* Use the smaller one plus one-byte NOP if the needed one
1518 nops
= patt
[last
- 1];
1519 memcpy (where
+ offset
, nops
, last
);
1520 where
[offset
+ last
] = *patt
[0];
1523 memcpy (where
+ offset
, nops
, last
);
1528 fits_in_imm7 (offsetT num
)
1530 return (num
& 0x7f) == num
;
1534 fits_in_imm31 (offsetT num
)
1536 return (num
& 0x7fffffff) == num
;
1539 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1540 single NOP instruction LIMIT. */
1543 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1545 const unsigned char *const *patt
= NULL
;
1546 int max_single_nop_size
;
1547 /* Maximum number of NOPs before switching to jump over NOPs. */
1548 int max_number_of_nops
;
1550 switch (fragP
->fr_type
)
1555 case rs_machine_dependent
:
1556 /* Allow NOP padding for jumps and calls. */
1557 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1558 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1565 /* We need to decide which NOP sequence to use for 32bit and
1566 64bit. When -mtune= is used:
1568 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1569 PROCESSOR_GENERIC32, f32_patt will be used.
1570 2. For the rest, alt_patt will be used.
1572 When -mtune= isn't used, alt_patt will be used if
1573 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1576 When -march= or .arch is used, we can't use anything beyond
1577 cpu_arch_isa_flags. */
1579 if (flag_code
== CODE_16BIT
)
1582 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1583 /* Limit number of NOPs to 2 in 16-bit mode. */
1584 max_number_of_nops
= 2;
1588 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1590 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1591 switch (cpu_arch_tune
)
1593 case PROCESSOR_UNKNOWN
:
1594 /* We use cpu_arch_isa_flags to check if we SHOULD
1595 optimize with nops. */
1596 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1601 case PROCESSOR_PENTIUM4
:
1602 case PROCESSOR_NOCONA
:
1603 case PROCESSOR_CORE
:
1604 case PROCESSOR_CORE2
:
1605 case PROCESSOR_COREI7
:
1606 case PROCESSOR_L1OM
:
1607 case PROCESSOR_K1OM
:
1608 case PROCESSOR_GENERIC64
:
1610 case PROCESSOR_ATHLON
:
1612 case PROCESSOR_AMDFAM10
:
1614 case PROCESSOR_ZNVER
:
1618 case PROCESSOR_I386
:
1619 case PROCESSOR_I486
:
1620 case PROCESSOR_PENTIUM
:
1621 case PROCESSOR_PENTIUMPRO
:
1622 case PROCESSOR_IAMCU
:
1623 case PROCESSOR_GENERIC32
:
1630 switch (fragP
->tc_frag_data
.tune
)
1632 case PROCESSOR_UNKNOWN
:
1633 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1634 PROCESSOR_UNKNOWN. */
1638 case PROCESSOR_I386
:
1639 case PROCESSOR_I486
:
1640 case PROCESSOR_PENTIUM
:
1641 case PROCESSOR_IAMCU
:
1643 case PROCESSOR_ATHLON
:
1645 case PROCESSOR_AMDFAM10
:
1647 case PROCESSOR_ZNVER
:
1649 case PROCESSOR_GENERIC32
:
1650 /* We use cpu_arch_isa_flags to check if we CAN optimize
1652 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1657 case PROCESSOR_PENTIUMPRO
:
1658 case PROCESSOR_PENTIUM4
:
1659 case PROCESSOR_NOCONA
:
1660 case PROCESSOR_CORE
:
1661 case PROCESSOR_CORE2
:
1662 case PROCESSOR_COREI7
:
1663 case PROCESSOR_L1OM
:
1664 case PROCESSOR_K1OM
:
1665 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1670 case PROCESSOR_GENERIC64
:
1676 if (patt
== f32_patt
)
1678 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1679 /* Limit number of NOPs to 2 for older processors. */
1680 max_number_of_nops
= 2;
1684 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1685 /* Limit number of NOPs to 7 for newer processors. */
1686 max_number_of_nops
= 7;
1691 limit
= max_single_nop_size
;
1693 if (fragP
->fr_type
== rs_fill_nop
)
1695 /* Output NOPs for .nop directive. */
1696 if (limit
> max_single_nop_size
)
1698 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1699 _("invalid single nop size: %d "
1700 "(expect within [0, %d])"),
1701 limit
, max_single_nop_size
);
1705 else if (fragP
->fr_type
!= rs_machine_dependent
)
1706 fragP
->fr_var
= count
;
1708 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1710 /* Generate jump over NOPs. */
1711 offsetT disp
= count
- 2;
1712 if (fits_in_imm7 (disp
))
1714 /* Use "jmp disp8" if possible. */
1716 where
[0] = jump_disp8
[0];
1722 unsigned int size_of_jump
;
1724 if (flag_code
== CODE_16BIT
)
1726 where
[0] = jump16_disp32
[0];
1727 where
[1] = jump16_disp32
[1];
1732 where
[0] = jump32_disp32
[0];
1736 count
-= size_of_jump
+ 4;
1737 if (!fits_in_imm31 (count
))
1739 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1740 _("jump over nop padding out of range"));
1744 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1745 where
+= size_of_jump
+ 4;
1749 /* Generate multiple NOPs. */
1750 i386_output_nops (where
, patt
, count
, limit
);
1754 operand_type_all_zero (const union i386_operand_type
*x
)
1756 switch (ARRAY_SIZE(x
->array
))
1767 return !x
->array
[0];
1774 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1776 switch (ARRAY_SIZE(x
->array
))
1792 x
->bitfield
.class = ClassNone
;
1793 x
->bitfield
.instance
= InstanceNone
;
1797 operand_type_equal (const union i386_operand_type
*x
,
1798 const union i386_operand_type
*y
)
1800 switch (ARRAY_SIZE(x
->array
))
1803 if (x
->array
[2] != y
->array
[2])
1807 if (x
->array
[1] != y
->array
[1])
1811 return x
->array
[0] == y
->array
[0];
1819 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1821 switch (ARRAY_SIZE(x
->array
))
1836 return !x
->array
[0];
1843 cpu_flags_equal (const union i386_cpu_flags
*x
,
1844 const union i386_cpu_flags
*y
)
1846 switch (ARRAY_SIZE(x
->array
))
1849 if (x
->array
[3] != y
->array
[3])
1853 if (x
->array
[2] != y
->array
[2])
1857 if (x
->array
[1] != y
->array
[1])
1861 return x
->array
[0] == y
->array
[0];
1869 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1871 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1872 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1875 static INLINE i386_cpu_flags
1876 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1878 switch (ARRAY_SIZE (x
.array
))
1881 x
.array
[3] &= y
.array
[3];
1884 x
.array
[2] &= y
.array
[2];
1887 x
.array
[1] &= y
.array
[1];
1890 x
.array
[0] &= y
.array
[0];
1898 static INLINE i386_cpu_flags
1899 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1901 switch (ARRAY_SIZE (x
.array
))
1904 x
.array
[3] |= y
.array
[3];
1907 x
.array
[2] |= y
.array
[2];
1910 x
.array
[1] |= y
.array
[1];
1913 x
.array
[0] |= y
.array
[0];
1921 static INLINE i386_cpu_flags
1922 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1924 switch (ARRAY_SIZE (x
.array
))
1927 x
.array
[3] &= ~y
.array
[3];
1930 x
.array
[2] &= ~y
.array
[2];
1933 x
.array
[1] &= ~y
.array
[1];
1936 x
.array
[0] &= ~y
.array
[0];
1944 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1946 #define CPU_FLAGS_ARCH_MATCH 0x1
1947 #define CPU_FLAGS_64BIT_MATCH 0x2
1949 #define CPU_FLAGS_PERFECT_MATCH \
1950 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1952 /* Return CPU flags match bits. */
1955 cpu_flags_match (const insn_template
*t
)
1957 i386_cpu_flags x
= t
->cpu_flags
;
1958 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1960 x
.bitfield
.cpu64
= 0;
1961 x
.bitfield
.cpuno64
= 0;
1963 if (cpu_flags_all_zero (&x
))
1965 /* This instruction is available on all archs. */
1966 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 /* This instruction is available only on some archs. */
1971 i386_cpu_flags cpu
= cpu_arch_flags
;
1973 /* AVX512VL is no standalone feature - match it and then strip it. */
1974 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1976 x
.bitfield
.cpuavx512vl
= 0;
1978 cpu
= cpu_flags_and (x
, cpu
);
1979 if (!cpu_flags_all_zero (&cpu
))
1981 if (x
.bitfield
.cpuavx
)
1983 /* We need to check a few extra flags with AVX. */
1984 if (cpu
.bitfield
.cpuavx
1985 && (!t
->opcode_modifier
.sse2avx
1986 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1987 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1988 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1989 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1990 match
|= CPU_FLAGS_ARCH_MATCH
;
1992 else if (x
.bitfield
.cpuavx512f
)
1994 /* We need to check a few extra flags with AVX512F. */
1995 if (cpu
.bitfield
.cpuavx512f
1996 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1997 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1998 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2002 match
|= CPU_FLAGS_ARCH_MATCH
;
2008 static INLINE i386_operand_type
2009 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2011 if (x
.bitfield
.class != y
.bitfield
.class)
2012 x
.bitfield
.class = ClassNone
;
2013 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2014 x
.bitfield
.instance
= InstanceNone
;
2016 switch (ARRAY_SIZE (x
.array
))
2019 x
.array
[2] &= y
.array
[2];
2022 x
.array
[1] &= y
.array
[1];
2025 x
.array
[0] &= y
.array
[0];
2033 static INLINE i386_operand_type
2034 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2036 gas_assert (y
.bitfield
.class == ClassNone
);
2037 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2039 switch (ARRAY_SIZE (x
.array
))
2042 x
.array
[2] &= ~y
.array
[2];
2045 x
.array
[1] &= ~y
.array
[1];
2048 x
.array
[0] &= ~y
.array
[0];
2056 static INLINE i386_operand_type
2057 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2059 gas_assert (x
.bitfield
.class == ClassNone
||
2060 y
.bitfield
.class == ClassNone
||
2061 x
.bitfield
.class == y
.bitfield
.class);
2062 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2063 y
.bitfield
.instance
== InstanceNone
||
2064 x
.bitfield
.instance
== y
.bitfield
.instance
);
2066 switch (ARRAY_SIZE (x
.array
))
2069 x
.array
[2] |= y
.array
[2];
2072 x
.array
[1] |= y
.array
[1];
2075 x
.array
[0] |= y
.array
[0];
2083 static INLINE i386_operand_type
2084 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2086 gas_assert (y
.bitfield
.class == ClassNone
);
2087 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2089 switch (ARRAY_SIZE (x
.array
))
2092 x
.array
[2] ^= y
.array
[2];
2095 x
.array
[1] ^= y
.array
[1];
2098 x
.array
[0] ^= y
.array
[0];
2106 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2107 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2108 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2109 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2110 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2111 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2112 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2113 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2114 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2115 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2116 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2117 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2118 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2119 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2120 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2121 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2122 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2133 operand_type_check (i386_operand_type t
, enum operand_type c
)
2138 return t
.bitfield
.class == Reg
;
2141 return (t
.bitfield
.imm8
2145 || t
.bitfield
.imm32s
2146 || t
.bitfield
.imm64
);
2149 return (t
.bitfield
.disp8
2150 || t
.bitfield
.disp16
2151 || t
.bitfield
.disp32
2152 || t
.bitfield
.disp32s
2153 || t
.bitfield
.disp64
);
2156 return (t
.bitfield
.disp8
2157 || t
.bitfield
.disp16
2158 || t
.bitfield
.disp32
2159 || t
.bitfield
.disp32s
2160 || t
.bitfield
.disp64
2161 || t
.bitfield
.baseindex
);
2170 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2171 between operand GIVEN and opeand WANTED for instruction template T. */
2174 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2177 return !((i
.types
[given
].bitfield
.byte
2178 && !t
->operand_types
[wanted
].bitfield
.byte
)
2179 || (i
.types
[given
].bitfield
.word
2180 && !t
->operand_types
[wanted
].bitfield
.word
)
2181 || (i
.types
[given
].bitfield
.dword
2182 && !t
->operand_types
[wanted
].bitfield
.dword
)
2183 || (i
.types
[given
].bitfield
.qword
2184 && !t
->operand_types
[wanted
].bitfield
.qword
)
2185 || (i
.types
[given
].bitfield
.tbyte
2186 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2189 /* Return 1 if there is no conflict in SIMD register between operand
2190 GIVEN and opeand WANTED for instruction template T. */
2193 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2196 return !((i
.types
[given
].bitfield
.xmmword
2197 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2198 || (i
.types
[given
].bitfield
.ymmword
2199 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2200 || (i
.types
[given
].bitfield
.zmmword
2201 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2202 || (i
.types
[given
].bitfield
.tmmword
2203 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2206 /* Return 1 if there is no conflict in any size between operand GIVEN
2207 and opeand WANTED for instruction template T. */
2210 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2213 return (match_operand_size (t
, wanted
, given
)
2214 && !((i
.types
[given
].bitfield
.unspecified
2216 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2217 || (i
.types
[given
].bitfield
.fword
2218 && !t
->operand_types
[wanted
].bitfield
.fword
)
2219 /* For scalar opcode templates to allow register and memory
2220 operands at the same time, some special casing is needed
2221 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2222 down-conversion vpmov*. */
2223 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2224 && t
->operand_types
[wanted
].bitfield
.byte
2225 + t
->operand_types
[wanted
].bitfield
.word
2226 + t
->operand_types
[wanted
].bitfield
.dword
2227 + t
->operand_types
[wanted
].bitfield
.qword
2228 > !!t
->opcode_modifier
.broadcast
)
2229 ? (i
.types
[given
].bitfield
.xmmword
2230 || i
.types
[given
].bitfield
.ymmword
2231 || i
.types
[given
].bitfield
.zmmword
)
2232 : !match_simd_size(t
, wanted
, given
))));
2235 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2236 operands for instruction template T, and it has MATCH_REVERSE set if there
2237 is no size conflict on any operands for the template with operands reversed
2238 (and the template allows for reversing in the first place). */
2240 #define MATCH_STRAIGHT 1
2241 #define MATCH_REVERSE 2
2243 static INLINE
unsigned int
2244 operand_size_match (const insn_template
*t
)
2246 unsigned int j
, match
= MATCH_STRAIGHT
;
2248 /* Don't check non-absolute jump instructions. */
2249 if (t
->opcode_modifier
.jump
2250 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2253 /* Check memory and accumulator operand size. */
2254 for (j
= 0; j
< i
.operands
; j
++)
2256 if (i
.types
[j
].bitfield
.class != Reg
2257 && i
.types
[j
].bitfield
.class != RegSIMD
2258 && t
->opcode_modifier
.anysize
)
2261 if (t
->operand_types
[j
].bitfield
.class == Reg
2262 && !match_operand_size (t
, j
, j
))
2268 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2269 && !match_simd_size (t
, j
, j
))
2275 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2276 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2282 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2289 if (!t
->opcode_modifier
.d
)
2293 i
.error
= operand_size_mismatch
;
2297 /* Check reverse. */
2298 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2300 for (j
= 0; j
< i
.operands
; j
++)
2302 unsigned int given
= i
.operands
- j
- 1;
2304 if (t
->operand_types
[j
].bitfield
.class == Reg
2305 && !match_operand_size (t
, j
, given
))
2308 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2309 && !match_simd_size (t
, j
, given
))
2312 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2313 && (!match_operand_size (t
, j
, given
)
2314 || !match_simd_size (t
, j
, given
)))
2317 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2321 return match
| MATCH_REVERSE
;
2325 operand_type_match (i386_operand_type overlap
,
2326 i386_operand_type given
)
2328 i386_operand_type temp
= overlap
;
2330 temp
.bitfield
.unspecified
= 0;
2331 temp
.bitfield
.byte
= 0;
2332 temp
.bitfield
.word
= 0;
2333 temp
.bitfield
.dword
= 0;
2334 temp
.bitfield
.fword
= 0;
2335 temp
.bitfield
.qword
= 0;
2336 temp
.bitfield
.tbyte
= 0;
2337 temp
.bitfield
.xmmword
= 0;
2338 temp
.bitfield
.ymmword
= 0;
2339 temp
.bitfield
.zmmword
= 0;
2340 temp
.bitfield
.tmmword
= 0;
2341 if (operand_type_all_zero (&temp
))
2344 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2348 i
.error
= operand_type_mismatch
;
2352 /* If given types g0 and g1 are registers they must be of the same type
2353 unless the expected operand type register overlap is null.
2354 Some Intel syntax memory operand size checking also happens here. */
2357 operand_type_register_match (i386_operand_type g0
,
2358 i386_operand_type t0
,
2359 i386_operand_type g1
,
2360 i386_operand_type t1
)
2362 if (g0
.bitfield
.class != Reg
2363 && g0
.bitfield
.class != RegSIMD
2364 && (!operand_type_check (g0
, anymem
)
2365 || g0
.bitfield
.unspecified
2366 || (t0
.bitfield
.class != Reg
2367 && t0
.bitfield
.class != RegSIMD
)))
2370 if (g1
.bitfield
.class != Reg
2371 && g1
.bitfield
.class != RegSIMD
2372 && (!operand_type_check (g1
, anymem
)
2373 || g1
.bitfield
.unspecified
2374 || (t1
.bitfield
.class != Reg
2375 && t1
.bitfield
.class != RegSIMD
)))
2378 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2379 && g0
.bitfield
.word
== g1
.bitfield
.word
2380 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2381 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2382 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2383 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2384 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2387 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2388 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2389 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2390 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2391 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2392 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2393 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2396 i
.error
= register_type_mismatch
;
2401 static INLINE
unsigned int
2402 register_number (const reg_entry
*r
)
2404 unsigned int nr
= r
->reg_num
;
2406 if (r
->reg_flags
& RegRex
)
2409 if (r
->reg_flags
& RegVRex
)
2415 static INLINE
unsigned int
2416 mode_from_disp_size (i386_operand_type t
)
2418 if (t
.bitfield
.disp8
)
2420 else if (t
.bitfield
.disp16
2421 || t
.bitfield
.disp32
2422 || t
.bitfield
.disp32s
)
2429 fits_in_signed_byte (addressT num
)
2431 return num
+ 0x80 <= 0xff;
2435 fits_in_unsigned_byte (addressT num
)
2441 fits_in_unsigned_word (addressT num
)
2443 return num
<= 0xffff;
2447 fits_in_signed_word (addressT num
)
2449 return num
+ 0x8000 <= 0xffff;
2453 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2458 return num
+ 0x80000000 <= 0xffffffff;
2460 } /* fits_in_signed_long() */
2463 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2468 return num
<= 0xffffffff;
2470 } /* fits_in_unsigned_long() */
2473 fits_in_disp8 (offsetT num
)
2475 int shift
= i
.memshift
;
2481 mask
= (1 << shift
) - 1;
2483 /* Return 0 if NUM isn't properly aligned. */
2487 /* Check if NUM will fit in 8bit after shift. */
2488 return fits_in_signed_byte (num
>> shift
);
2492 fits_in_imm4 (offsetT num
)
2494 return (num
& 0xf) == num
;
2497 static i386_operand_type
2498 smallest_imm_type (offsetT num
)
2500 i386_operand_type t
;
2502 operand_type_set (&t
, 0);
2503 t
.bitfield
.imm64
= 1;
2505 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2507 /* This code is disabled on the 486 because all the Imm1 forms
2508 in the opcode table are slower on the i486. They're the
2509 versions with the implicitly specified single-position
2510 displacement, which has another syntax if you really want to
2512 t
.bitfield
.imm1
= 1;
2513 t
.bitfield
.imm8
= 1;
2514 t
.bitfield
.imm8s
= 1;
2515 t
.bitfield
.imm16
= 1;
2516 t
.bitfield
.imm32
= 1;
2517 t
.bitfield
.imm32s
= 1;
2519 else if (fits_in_signed_byte (num
))
2521 t
.bitfield
.imm8
= 1;
2522 t
.bitfield
.imm8s
= 1;
2523 t
.bitfield
.imm16
= 1;
2524 t
.bitfield
.imm32
= 1;
2525 t
.bitfield
.imm32s
= 1;
2527 else if (fits_in_unsigned_byte (num
))
2529 t
.bitfield
.imm8
= 1;
2530 t
.bitfield
.imm16
= 1;
2531 t
.bitfield
.imm32
= 1;
2532 t
.bitfield
.imm32s
= 1;
2534 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2536 t
.bitfield
.imm16
= 1;
2537 t
.bitfield
.imm32
= 1;
2538 t
.bitfield
.imm32s
= 1;
2540 else if (fits_in_signed_long (num
))
2542 t
.bitfield
.imm32
= 1;
2543 t
.bitfield
.imm32s
= 1;
2545 else if (fits_in_unsigned_long (num
))
2546 t
.bitfield
.imm32
= 1;
2552 offset_in_range (offsetT val
, int size
)
2558 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2559 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2560 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2562 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2567 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2569 char buf1
[40], buf2
[40];
2571 sprint_value (buf1
, val
);
2572 sprint_value (buf2
, val
& mask
);
2573 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2588 a. PREFIX_EXIST if attempting to add a prefix where one from the
2589 same class already exists.
2590 b. PREFIX_LOCK if lock prefix is added.
2591 c. PREFIX_REP if rep/repne prefix is added.
2592 d. PREFIX_DS if ds prefix is added.
2593 e. PREFIX_OTHER if other prefix is added.
2596 static enum PREFIX_GROUP
2597 add_prefix (unsigned int prefix
)
2599 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2602 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2603 && flag_code
== CODE_64BIT
)
2605 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2606 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2607 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2608 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2619 case DS_PREFIX_OPCODE
:
2622 case CS_PREFIX_OPCODE
:
2623 case ES_PREFIX_OPCODE
:
2624 case FS_PREFIX_OPCODE
:
2625 case GS_PREFIX_OPCODE
:
2626 case SS_PREFIX_OPCODE
:
2630 case REPNE_PREFIX_OPCODE
:
2631 case REPE_PREFIX_OPCODE
:
2636 case LOCK_PREFIX_OPCODE
:
2645 case ADDR_PREFIX_OPCODE
:
2649 case DATA_PREFIX_OPCODE
:
2653 if (i
.prefix
[q
] != 0)
2661 i
.prefix
[q
] |= prefix
;
2664 as_bad (_("same type of prefix used twice"));
2670 update_code_flag (int value
, int check
)
2672 PRINTF_LIKE ((*as_error
));
2674 flag_code
= (enum flag_code
) value
;
2675 if (flag_code
== CODE_64BIT
)
2677 cpu_arch_flags
.bitfield
.cpu64
= 1;
2678 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2682 cpu_arch_flags
.bitfield
.cpu64
= 0;
2683 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2685 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2688 as_error
= as_fatal
;
2691 (*as_error
) (_("64bit mode not supported on `%s'."),
2692 cpu_arch_name
? cpu_arch_name
: default_arch
);
2694 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2697 as_error
= as_fatal
;
2700 (*as_error
) (_("32bit mode not supported on `%s'."),
2701 cpu_arch_name
? cpu_arch_name
: default_arch
);
2703 stackop_size
= '\0';
2707 set_code_flag (int value
)
2709 update_code_flag (value
, 0);
2713 set_16bit_gcc_code_flag (int new_code_flag
)
2715 flag_code
= (enum flag_code
) new_code_flag
;
2716 if (flag_code
!= CODE_16BIT
)
2718 cpu_arch_flags
.bitfield
.cpu64
= 0;
2719 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2720 stackop_size
= LONG_MNEM_SUFFIX
;
2724 set_intel_syntax (int syntax_flag
)
2726 /* Find out if register prefixing is specified. */
2727 int ask_naked_reg
= 0;
2730 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2733 int e
= get_symbol_name (&string
);
2735 if (strcmp (string
, "prefix") == 0)
2737 else if (strcmp (string
, "noprefix") == 0)
2740 as_bad (_("bad argument to syntax directive."));
2741 (void) restore_line_pointer (e
);
2743 demand_empty_rest_of_line ();
2745 intel_syntax
= syntax_flag
;
2747 if (ask_naked_reg
== 0)
2748 allow_naked_reg
= (intel_syntax
2749 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2751 allow_naked_reg
= (ask_naked_reg
< 0);
2753 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2755 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2756 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2757 register_prefix
= allow_naked_reg
? "" : "%";
2761 set_intel_mnemonic (int mnemonic_flag
)
2763 intel_mnemonic
= mnemonic_flag
;
2767 set_allow_index_reg (int flag
)
2769 allow_index_reg
= flag
;
2773 set_check (int what
)
2775 enum check_kind
*kind
;
2780 kind
= &operand_check
;
2791 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2794 int e
= get_symbol_name (&string
);
2796 if (strcmp (string
, "none") == 0)
2798 else if (strcmp (string
, "warning") == 0)
2799 *kind
= check_warning
;
2800 else if (strcmp (string
, "error") == 0)
2801 *kind
= check_error
;
2803 as_bad (_("bad argument to %s_check directive."), str
);
2804 (void) restore_line_pointer (e
);
2807 as_bad (_("missing argument for %s_check directive"), str
);
2809 demand_empty_rest_of_line ();
2813 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2814 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2817 static const char *arch
;
2819 /* Intel LIOM is only supported on ELF. */
2825 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2826 use default_arch. */
2827 arch
= cpu_arch_name
;
2829 arch
= default_arch
;
2832 /* If we are targeting Intel MCU, we must enable it. */
2833 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2834 || new_flag
.bitfield
.cpuiamcu
)
2837 /* If we are targeting Intel L1OM, we must enable it. */
2838 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2839 || new_flag
.bitfield
.cpul1om
)
2842 /* If we are targeting Intel K1OM, we must enable it. */
2843 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2844 || new_flag
.bitfield
.cpuk1om
)
2847 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2852 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2856 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2859 int e
= get_symbol_name (&string
);
2861 i386_cpu_flags flags
;
2863 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2865 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2867 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2871 cpu_arch_name
= cpu_arch
[j
].name
;
2872 cpu_sub_arch_name
= NULL
;
2873 cpu_arch_flags
= cpu_arch
[j
].flags
;
2874 if (flag_code
== CODE_64BIT
)
2876 cpu_arch_flags
.bitfield
.cpu64
= 1;
2877 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2881 cpu_arch_flags
.bitfield
.cpu64
= 0;
2882 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2884 cpu_arch_isa
= cpu_arch
[j
].type
;
2885 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2886 if (!cpu_arch_tune_set
)
2888 cpu_arch_tune
= cpu_arch_isa
;
2889 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2894 flags
= cpu_flags_or (cpu_arch_flags
,
2897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2899 if (cpu_sub_arch_name
)
2901 char *name
= cpu_sub_arch_name
;
2902 cpu_sub_arch_name
= concat (name
,
2904 (const char *) NULL
);
2908 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2909 cpu_arch_flags
= flags
;
2910 cpu_arch_isa_flags
= flags
;
2914 = cpu_flags_or (cpu_arch_isa_flags
,
2916 (void) restore_line_pointer (e
);
2917 demand_empty_rest_of_line ();
2922 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2924 /* Disable an ISA extension. */
2925 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2926 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2928 flags
= cpu_flags_and_not (cpu_arch_flags
,
2929 cpu_noarch
[j
].flags
);
2930 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2932 if (cpu_sub_arch_name
)
2934 char *name
= cpu_sub_arch_name
;
2935 cpu_sub_arch_name
= concat (name
, string
,
2936 (const char *) NULL
);
2940 cpu_sub_arch_name
= xstrdup (string
);
2941 cpu_arch_flags
= flags
;
2942 cpu_arch_isa_flags
= flags
;
2944 (void) restore_line_pointer (e
);
2945 demand_empty_rest_of_line ();
2949 j
= ARRAY_SIZE (cpu_arch
);
2952 if (j
>= ARRAY_SIZE (cpu_arch
))
2953 as_bad (_("no such architecture: `%s'"), string
);
2955 *input_line_pointer
= e
;
2958 as_bad (_("missing cpu architecture"));
2960 no_cond_jump_promotion
= 0;
2961 if (*input_line_pointer
== ','
2962 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2967 ++input_line_pointer
;
2968 e
= get_symbol_name (&string
);
2970 if (strcmp (string
, "nojumps") == 0)
2971 no_cond_jump_promotion
= 1;
2972 else if (strcmp (string
, "jumps") == 0)
2975 as_bad (_("no such architecture modifier: `%s'"), string
);
2977 (void) restore_line_pointer (e
);
2980 demand_empty_rest_of_line ();
2983 enum bfd_architecture
2986 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2988 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2989 || flag_code
!= CODE_64BIT
)
2990 as_fatal (_("Intel L1OM is 64bit ELF only"));
2991 return bfd_arch_l1om
;
2993 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2995 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2996 || flag_code
!= CODE_64BIT
)
2997 as_fatal (_("Intel K1OM is 64bit ELF only"));
2998 return bfd_arch_k1om
;
3000 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3002 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3003 || flag_code
== CODE_64BIT
)
3004 as_fatal (_("Intel MCU is 32bit ELF only"));
3005 return bfd_arch_iamcu
;
3008 return bfd_arch_i386
;
3014 if (!strncmp (default_arch
, "x86_64", 6))
3016 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3018 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3019 || default_arch
[6] != '\0')
3020 as_fatal (_("Intel L1OM is 64bit ELF only"));
3021 return bfd_mach_l1om
;
3023 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3025 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3026 || default_arch
[6] != '\0')
3027 as_fatal (_("Intel K1OM is 64bit ELF only"));
3028 return bfd_mach_k1om
;
3030 else if (default_arch
[6] == '\0')
3031 return bfd_mach_x86_64
;
3033 return bfd_mach_x64_32
;
3035 else if (!strcmp (default_arch
, "i386")
3036 || !strcmp (default_arch
, "iamcu"))
3038 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3040 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3041 as_fatal (_("Intel MCU is 32bit ELF only"));
3042 return bfd_mach_i386_iamcu
;
3045 return bfd_mach_i386_i386
;
3048 as_fatal (_("unknown architecture"));
3054 /* Support pseudo prefixes like {disp32}. */
3055 lex_type
['{'] = LEX_BEGIN_NAME
;
3057 /* Initialize op_hash hash table. */
3058 op_hash
= str_htab_create ();
3061 const insn_template
*optab
;
3062 templates
*core_optab
;
3064 /* Setup for loop. */
3066 core_optab
= XNEW (templates
);
3067 core_optab
->start
= optab
;
3072 if (optab
->name
== NULL
3073 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3075 /* different name --> ship out current template list;
3076 add to hash table; & begin anew. */
3077 core_optab
->end
= optab
;
3078 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3079 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3081 if (optab
->name
== NULL
)
3083 core_optab
= XNEW (templates
);
3084 core_optab
->start
= optab
;
3089 /* Initialize reg_hash hash table. */
3090 reg_hash
= str_htab_create ();
3092 const reg_entry
*regtab
;
3093 unsigned int regtab_size
= i386_regtab_size
;
3095 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3096 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3097 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3100 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3105 for (c
= 0; c
< 256; c
++)
3110 mnemonic_chars
[c
] = c
;
3111 register_chars
[c
] = c
;
3112 operand_chars
[c
] = c
;
3114 else if (ISLOWER (c
))
3116 mnemonic_chars
[c
] = c
;
3117 register_chars
[c
] = c
;
3118 operand_chars
[c
] = c
;
3120 else if (ISUPPER (c
))
3122 mnemonic_chars
[c
] = TOLOWER (c
);
3123 register_chars
[c
] = mnemonic_chars
[c
];
3124 operand_chars
[c
] = c
;
3126 else if (c
== '{' || c
== '}')
3128 mnemonic_chars
[c
] = c
;
3129 operand_chars
[c
] = c
;
3131 #ifdef SVR4_COMMENT_CHARS
3132 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3133 operand_chars
[c
] = c
;
3136 if (ISALPHA (c
) || ISDIGIT (c
))
3137 identifier_chars
[c
] = c
;
3140 identifier_chars
[c
] = c
;
3141 operand_chars
[c
] = c
;
3146 identifier_chars
['@'] = '@';
3149 identifier_chars
['?'] = '?';
3150 operand_chars
['?'] = '?';
3152 digit_chars
['-'] = '-';
3153 mnemonic_chars
['_'] = '_';
3154 mnemonic_chars
['-'] = '-';
3155 mnemonic_chars
['.'] = '.';
3156 identifier_chars
['_'] = '_';
3157 identifier_chars
['.'] = '.';
3159 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3160 operand_chars
[(unsigned char) *p
] = *p
;
3163 if (flag_code
== CODE_64BIT
)
3165 #if defined (OBJ_COFF) && defined (TE_PE)
3166 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3169 x86_dwarf2_return_column
= 16;
3171 x86_cie_data_alignment
= -8;
3175 x86_dwarf2_return_column
= 8;
3176 x86_cie_data_alignment
= -4;
3179 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3180 can be turned into BRANCH_PREFIX frag. */
3181 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3186 i386_print_statistics (FILE *file
)
3188 htab_print_statistics (file
, "i386 opcode", op_hash
);
3189 htab_print_statistics (file
, "i386 register", reg_hash
);
3194 /* Debugging routines for md_assemble. */
3195 static void pte (insn_template
*);
3196 static void pt (i386_operand_type
);
3197 static void pe (expressionS
*);
3198 static void ps (symbolS
*);
3201 pi (const char *line
, i386_insn
*x
)
3205 fprintf (stdout
, "%s: template ", line
);
3207 fprintf (stdout
, " address: base %s index %s scale %x\n",
3208 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3209 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3210 x
->log2_scale_factor
);
3211 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3212 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3213 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3214 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3215 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3216 (x
->rex
& REX_W
) != 0,
3217 (x
->rex
& REX_R
) != 0,
3218 (x
->rex
& REX_X
) != 0,
3219 (x
->rex
& REX_B
) != 0);
3220 for (j
= 0; j
< x
->operands
; j
++)
3222 fprintf (stdout
, " #%d: ", j
+ 1);
3224 fprintf (stdout
, "\n");
3225 if (x
->types
[j
].bitfield
.class == Reg
3226 || x
->types
[j
].bitfield
.class == RegMMX
3227 || x
->types
[j
].bitfield
.class == RegSIMD
3228 || x
->types
[j
].bitfield
.class == RegMask
3229 || x
->types
[j
].bitfield
.class == SReg
3230 || x
->types
[j
].bitfield
.class == RegCR
3231 || x
->types
[j
].bitfield
.class == RegDR
3232 || x
->types
[j
].bitfield
.class == RegTR
3233 || x
->types
[j
].bitfield
.class == RegBND
)
3234 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3235 if (operand_type_check (x
->types
[j
], imm
))
3237 if (operand_type_check (x
->types
[j
], disp
))
3238 pe (x
->op
[j
].disps
);
3243 pte (insn_template
*t
)
3245 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3246 static const char *const opc_spc
[] = {
3247 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3248 "XOP08", "XOP09", "XOP0A",
3252 fprintf (stdout
, " %d operands ", t
->operands
);
3253 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3254 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3255 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3256 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3257 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3258 if (t
->extension_opcode
!= None
)
3259 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3260 if (t
->opcode_modifier
.d
)
3261 fprintf (stdout
, "D");
3262 if (t
->opcode_modifier
.w
)
3263 fprintf (stdout
, "W");
3264 fprintf (stdout
, "\n");
3265 for (j
= 0; j
< t
->operands
; j
++)
3267 fprintf (stdout
, " #%d type ", j
+ 1);
3268 pt (t
->operand_types
[j
]);
3269 fprintf (stdout
, "\n");
3276 fprintf (stdout
, " operation %d\n", e
->X_op
);
3277 fprintf (stdout
, " add_number %ld (%lx)\n",
3278 (long) e
->X_add_number
, (long) e
->X_add_number
);
3279 if (e
->X_add_symbol
)
3281 fprintf (stdout
, " add_symbol ");
3282 ps (e
->X_add_symbol
);
3283 fprintf (stdout
, "\n");
3287 fprintf (stdout
, " op_symbol ");
3288 ps (e
->X_op_symbol
);
3289 fprintf (stdout
, "\n");
3296 fprintf (stdout
, "%s type %s%s",
3298 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3299 segment_name (S_GET_SEGMENT (s
)));
3302 static struct type_name
3304 i386_operand_type mask
;
3307 const type_names
[] =
3309 { OPERAND_TYPE_REG8
, "r8" },
3310 { OPERAND_TYPE_REG16
, "r16" },
3311 { OPERAND_TYPE_REG32
, "r32" },
3312 { OPERAND_TYPE_REG64
, "r64" },
3313 { OPERAND_TYPE_ACC8
, "acc8" },
3314 { OPERAND_TYPE_ACC16
, "acc16" },
3315 { OPERAND_TYPE_ACC32
, "acc32" },
3316 { OPERAND_TYPE_ACC64
, "acc64" },
3317 { OPERAND_TYPE_IMM8
, "i8" },
3318 { OPERAND_TYPE_IMM8
, "i8s" },
3319 { OPERAND_TYPE_IMM16
, "i16" },
3320 { OPERAND_TYPE_IMM32
, "i32" },
3321 { OPERAND_TYPE_IMM32S
, "i32s" },
3322 { OPERAND_TYPE_IMM64
, "i64" },
3323 { OPERAND_TYPE_IMM1
, "i1" },
3324 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3325 { OPERAND_TYPE_DISP8
, "d8" },
3326 { OPERAND_TYPE_DISP16
, "d16" },
3327 { OPERAND_TYPE_DISP32
, "d32" },
3328 { OPERAND_TYPE_DISP32S
, "d32s" },
3329 { OPERAND_TYPE_DISP64
, "d64" },
3330 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3331 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3332 { OPERAND_TYPE_CONTROL
, "control reg" },
3333 { OPERAND_TYPE_TEST
, "test reg" },
3334 { OPERAND_TYPE_DEBUG
, "debug reg" },
3335 { OPERAND_TYPE_FLOATREG
, "FReg" },
3336 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3337 { OPERAND_TYPE_SREG
, "SReg" },
3338 { OPERAND_TYPE_REGMMX
, "rMMX" },
3339 { OPERAND_TYPE_REGXMM
, "rXMM" },
3340 { OPERAND_TYPE_REGYMM
, "rYMM" },
3341 { OPERAND_TYPE_REGZMM
, "rZMM" },
3342 { OPERAND_TYPE_REGTMM
, "rTMM" },
3343 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3347 pt (i386_operand_type t
)
3350 i386_operand_type a
;
3352 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3354 a
= operand_type_and (t
, type_names
[j
].mask
);
3355 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3356 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3361 #endif /* DEBUG386 */
3363 static bfd_reloc_code_real_type
3364 reloc (unsigned int size
,
3367 bfd_reloc_code_real_type other
)
3369 if (other
!= NO_RELOC
)
3371 reloc_howto_type
*rel
;
3376 case BFD_RELOC_X86_64_GOT32
:
3377 return BFD_RELOC_X86_64_GOT64
;
3379 case BFD_RELOC_X86_64_GOTPLT64
:
3380 return BFD_RELOC_X86_64_GOTPLT64
;
3382 case BFD_RELOC_X86_64_PLTOFF64
:
3383 return BFD_RELOC_X86_64_PLTOFF64
;
3385 case BFD_RELOC_X86_64_GOTPC32
:
3386 other
= BFD_RELOC_X86_64_GOTPC64
;
3388 case BFD_RELOC_X86_64_GOTPCREL
:
3389 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3391 case BFD_RELOC_X86_64_TPOFF32
:
3392 other
= BFD_RELOC_X86_64_TPOFF64
;
3394 case BFD_RELOC_X86_64_DTPOFF32
:
3395 other
= BFD_RELOC_X86_64_DTPOFF64
;
3401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3402 if (other
== BFD_RELOC_SIZE32
)
3405 other
= BFD_RELOC_SIZE64
;
3408 as_bad (_("there are no pc-relative size relocations"));
3414 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3415 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3418 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3420 as_bad (_("unknown relocation (%u)"), other
);
3421 else if (size
!= bfd_get_reloc_size (rel
))
3422 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3423 bfd_get_reloc_size (rel
),
3425 else if (pcrel
&& !rel
->pc_relative
)
3426 as_bad (_("non-pc-relative relocation for pc-relative field"));
3427 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3429 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3431 as_bad (_("relocated field and relocation type differ in signedness"));
3440 as_bad (_("there are no unsigned pc-relative relocations"));
3443 case 1: return BFD_RELOC_8_PCREL
;
3444 case 2: return BFD_RELOC_16_PCREL
;
3445 case 4: return BFD_RELOC_32_PCREL
;
3446 case 8: return BFD_RELOC_64_PCREL
;
3448 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3455 case 4: return BFD_RELOC_X86_64_32S
;
3460 case 1: return BFD_RELOC_8
;
3461 case 2: return BFD_RELOC_16
;
3462 case 4: return BFD_RELOC_32
;
3463 case 8: return BFD_RELOC_64
;
3465 as_bad (_("cannot do %s %u byte relocation"),
3466 sign
> 0 ? "signed" : "unsigned", size
);
3472 /* Here we decide which fixups can be adjusted to make them relative to
3473 the beginning of the section instead of the symbol. Basically we need
3474 to make sure that the dynamic relocations are done correctly, so in
3475 some cases we force the original symbol to be used. */
3478 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3484 /* Don't adjust pc-relative references to merge sections in 64-bit
3486 if (use_rela_relocations
3487 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3491 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3492 and changed later by validate_fix. */
3493 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3494 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3497 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3498 for size relocations. */
3499 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3500 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3501 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3502 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3503 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3504 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3505 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3506 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3507 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3508 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3509 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3510 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3511 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3512 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3513 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3515 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3516 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3517 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3518 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3519 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3520 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3521 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3522 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3523 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3524 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3525 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3526 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3527 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3528 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3529 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3536 intel_float_operand (const char *mnemonic
)
3538 /* Note that the value returned is meaningful only for opcodes with (memory)
3539 operands, hence the code here is free to improperly handle opcodes that
3540 have no operands (for better performance and smaller code). */
3542 if (mnemonic
[0] != 'f')
3543 return 0; /* non-math */
3545 switch (mnemonic
[1])
3547 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3548 the fs segment override prefix not currently handled because no
3549 call path can make opcodes without operands get here */
3551 return 2 /* integer op */;
3553 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3554 return 3; /* fldcw/fldenv */
3557 if (mnemonic
[2] != 'o' /* fnop */)
3558 return 3; /* non-waiting control op */
3561 if (mnemonic
[2] == 's')
3562 return 3; /* frstor/frstpm */
3565 if (mnemonic
[2] == 'a')
3566 return 3; /* fsave */
3567 if (mnemonic
[2] == 't')
3569 switch (mnemonic
[3])
3571 case 'c': /* fstcw */
3572 case 'd': /* fstdw */
3573 case 'e': /* fstenv */
3574 case 's': /* fsts[gw] */
3580 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3581 return 0; /* fxsave/fxrstor are not really math ops */
3589 install_template (const insn_template
*t
)
3595 /* Note that for pseudo prefixes this produces a length of 1. But for them
3596 the length isn't interesting at all. */
3597 for (l
= 1; l
< 4; ++l
)
3598 if (!(t
->base_opcode
>> (8 * l
)))
3601 i
.opcode_length
= l
;
3604 /* Build the VEX prefix. */
3607 build_vex_prefix (const insn_template
*t
)
3609 unsigned int register_specifier
;
3610 unsigned int vector_length
;
3613 /* Check register specifier. */
3614 if (i
.vex
.register_specifier
)
3616 register_specifier
=
3617 ~register_number (i
.vex
.register_specifier
) & 0xf;
3618 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3621 register_specifier
= 0xf;
3623 /* Use 2-byte VEX prefix by swapping destination and source operand
3624 if there are more than 1 register operand. */
3625 if (i
.reg_operands
> 1
3626 && i
.vec_encoding
!= vex_encoding_vex3
3627 && i
.dir_encoding
== dir_encoding_default
3628 && i
.operands
== i
.reg_operands
3629 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3630 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3631 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3634 unsigned int xchg
= i
.operands
- 1;
3635 union i386_op temp_op
;
3636 i386_operand_type temp_type
;
3638 temp_type
= i
.types
[xchg
];
3639 i
.types
[xchg
] = i
.types
[0];
3640 i
.types
[0] = temp_type
;
3641 temp_op
= i
.op
[xchg
];
3642 i
.op
[xchg
] = i
.op
[0];
3645 gas_assert (i
.rm
.mode
== 3);
3649 i
.rm
.regmem
= i
.rm
.reg
;
3652 if (i
.tm
.opcode_modifier
.d
)
3653 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3654 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3655 else /* Use the next insn. */
3656 install_template (&t
[1]);
3659 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3660 are no memory operands and at least 3 register ones. */
3661 if (i
.reg_operands
>= 3
3662 && i
.vec_encoding
!= vex_encoding_vex3
3663 && i
.reg_operands
== i
.operands
- i
.imm_operands
3664 && i
.tm
.opcode_modifier
.vex
3665 && i
.tm
.opcode_modifier
.commutative
3666 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3668 && i
.vex
.register_specifier
3669 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3671 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3672 union i386_op temp_op
;
3673 i386_operand_type temp_type
;
3675 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3676 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3677 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3678 &i
.types
[i
.operands
- 3]));
3679 gas_assert (i
.rm
.mode
== 3);
3681 temp_type
= i
.types
[xchg
];
3682 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3683 i
.types
[xchg
+ 1] = temp_type
;
3684 temp_op
= i
.op
[xchg
];
3685 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3686 i
.op
[xchg
+ 1] = temp_op
;
3689 xchg
= i
.rm
.regmem
| 8;
3690 i
.rm
.regmem
= ~register_specifier
& 0xf;
3691 gas_assert (!(i
.rm
.regmem
& 8));
3692 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3693 register_specifier
= ~xchg
& 0xf;
3696 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3697 vector_length
= avxscalar
;
3698 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3704 /* Determine vector length from the last multi-length vector
3707 for (op
= t
->operands
; op
--;)
3708 if (t
->operand_types
[op
].bitfield
.xmmword
3709 && t
->operand_types
[op
].bitfield
.ymmword
3710 && i
.types
[op
].bitfield
.ymmword
)
3717 /* Check the REX.W bit and VEXW. */
3718 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3719 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3720 else if (i
.tm
.opcode_modifier
.vexw
)
3721 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3723 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3725 /* Use 2-byte VEX prefix if possible. */
3727 && i
.vec_encoding
!= vex_encoding_vex3
3728 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3729 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3731 /* 2-byte VEX prefix. */
3735 i
.vex
.bytes
[0] = 0xc5;
3737 /* Check the REX.R bit. */
3738 r
= (i
.rex
& REX_R
) ? 0 : 1;
3739 i
.vex
.bytes
[1] = (r
<< 7
3740 | register_specifier
<< 3
3741 | vector_length
<< 2
3742 | i
.tm
.opcode_modifier
.opcodeprefix
);
3746 /* 3-byte VEX prefix. */
3749 switch (i
.tm
.opcode_modifier
.opcodespace
)
3754 i
.vex
.bytes
[0] = 0xc4;
3759 i
.vex
.bytes
[0] = 0x8f;
3765 /* The high 3 bits of the second VEX byte are 1's compliment
3766 of RXB bits from REX. */
3767 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3769 i
.vex
.bytes
[2] = (w
<< 7
3770 | register_specifier
<< 3
3771 | vector_length
<< 2
3772 | i
.tm
.opcode_modifier
.opcodeprefix
);
3776 static INLINE bfd_boolean
3777 is_evex_encoding (const insn_template
*t
)
3779 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3780 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3781 || t
->opcode_modifier
.sae
;
3784 static INLINE bfd_boolean
3785 is_any_vex_encoding (const insn_template
*t
)
3787 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3790 /* Build the EVEX prefix. */
3793 build_evex_prefix (void)
3795 unsigned int register_specifier
, w
;
3796 rex_byte vrex_used
= 0;
3798 /* Check register specifier. */
3799 if (i
.vex
.register_specifier
)
3801 gas_assert ((i
.vrex
& REX_X
) == 0);
3803 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3804 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3805 register_specifier
+= 8;
3806 /* The upper 16 registers are encoded in the fourth byte of the
3808 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3809 i
.vex
.bytes
[3] = 0x8;
3810 register_specifier
= ~register_specifier
& 0xf;
3814 register_specifier
= 0xf;
3816 /* Encode upper 16 vector index register in the fourth byte of
3818 if (!(i
.vrex
& REX_X
))
3819 i
.vex
.bytes
[3] = 0x8;
3824 /* 4 byte EVEX prefix. */
3826 i
.vex
.bytes
[0] = 0x62;
3828 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3830 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3831 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3832 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3834 /* The fifth bit of the second EVEX byte is 1's compliment of the
3835 REX_R bit in VREX. */
3836 if (!(i
.vrex
& REX_R
))
3837 i
.vex
.bytes
[1] |= 0x10;
3841 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3843 /* When all operands are registers, the REX_X bit in REX is not
3844 used. We reuse it to encode the upper 16 registers, which is
3845 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3846 as 1's compliment. */
3847 if ((i
.vrex
& REX_B
))
3850 i
.vex
.bytes
[1] &= ~0x40;
3854 /* EVEX instructions shouldn't need the REX prefix. */
3855 i
.vrex
&= ~vrex_used
;
3856 gas_assert (i
.vrex
== 0);
3858 /* Check the REX.W bit and VEXW. */
3859 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3860 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3861 else if (i
.tm
.opcode_modifier
.vexw
)
3862 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3864 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3866 /* The third byte of the EVEX prefix. */
3867 i
.vex
.bytes
[2] = ((w
<< 7)
3868 | (register_specifier
<< 3)
3869 | 4 /* Encode the U bit. */
3870 | i
.tm
.opcode_modifier
.opcodeprefix
);
3872 /* The fourth byte of the EVEX prefix. */
3873 /* The zeroing-masking bit. */
3874 if (i
.mask
&& i
.mask
->zeroing
)
3875 i
.vex
.bytes
[3] |= 0x80;
3877 /* Don't always set the broadcast bit if there is no RC. */
3880 /* Encode the vector length. */
3881 unsigned int vec_length
;
3883 if (!i
.tm
.opcode_modifier
.evex
3884 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3888 /* Determine vector length from the last multi-length vector
3890 for (op
= i
.operands
; op
--;)
3891 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3892 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3893 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3895 if (i
.types
[op
].bitfield
.zmmword
)
3897 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3900 else if (i
.types
[op
].bitfield
.ymmword
)
3902 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3905 else if (i
.types
[op
].bitfield
.xmmword
)
3907 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3910 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3912 switch (i
.broadcast
->bytes
)
3915 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3918 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3921 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 if (op
>= MAX_OPERANDS
)
3934 switch (i
.tm
.opcode_modifier
.evex
)
3936 case EVEXLIG
: /* LL' is ignored */
3937 vec_length
= evexlig
<< 5;
3940 vec_length
= 0 << 5;
3943 vec_length
= 1 << 5;
3946 vec_length
= 2 << 5;
3952 i
.vex
.bytes
[3] |= vec_length
;
3953 /* Encode the broadcast bit. */
3955 i
.vex
.bytes
[3] |= 0x10;
3959 if (i
.rounding
->type
!= saeonly
)
3960 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3962 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3965 if (i
.mask
&& i
.mask
->mask
)
3966 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3970 process_immext (void)
3974 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3975 which is coded in the same place as an 8-bit immediate field
3976 would be. Here we fake an 8-bit immediate operand from the
3977 opcode suffix stored in tm.extension_opcode.
3979 AVX instructions also use this encoding, for some of
3980 3 argument instructions. */
3982 gas_assert (i
.imm_operands
<= 1
3984 || (is_any_vex_encoding (&i
.tm
)
3985 && i
.operands
<= 4)));
3987 exp
= &im_expressions
[i
.imm_operands
++];
3988 i
.op
[i
.operands
].imms
= exp
;
3989 i
.types
[i
.operands
] = imm8
;
3991 exp
->X_op
= O_constant
;
3992 exp
->X_add_number
= i
.tm
.extension_opcode
;
3993 i
.tm
.extension_opcode
= None
;
4000 switch (i
.tm
.opcode_modifier
.prefixok
)
4008 as_bad (_("invalid instruction `%s' after `%s'"),
4009 i
.tm
.name
, i
.hle_prefix
);
4012 if (i
.prefix
[LOCK_PREFIX
])
4014 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4018 case PrefixHLERelease
:
4019 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4021 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4025 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4027 as_bad (_("memory destination needed for instruction `%s'"
4028 " after `xrelease'"), i
.tm
.name
);
4035 /* Try the shortest encoding by shortening operand size. */
4038 optimize_encoding (void)
4042 if (optimize_for_space
4043 && !is_any_vex_encoding (&i
.tm
)
4044 && i
.reg_operands
== 1
4045 && i
.imm_operands
== 1
4046 && !i
.types
[1].bitfield
.byte
4047 && i
.op
[0].imms
->X_op
== O_constant
4048 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4049 && (i
.tm
.base_opcode
== 0xa8
4050 || (i
.tm
.base_opcode
== 0xf6
4051 && i
.tm
.extension_opcode
== 0x0)))
4054 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4056 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4057 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4059 i
.types
[1].bitfield
.byte
= 1;
4060 /* Ignore the suffix. */
4062 /* Convert to byte registers. */
4063 if (i
.types
[1].bitfield
.word
)
4065 else if (i
.types
[1].bitfield
.dword
)
4069 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4074 else if (flag_code
== CODE_64BIT
4075 && !is_any_vex_encoding (&i
.tm
)
4076 && ((i
.types
[1].bitfield
.qword
4077 && i
.reg_operands
== 1
4078 && i
.imm_operands
== 1
4079 && i
.op
[0].imms
->X_op
== O_constant
4080 && ((i
.tm
.base_opcode
== 0xb8
4081 && i
.tm
.extension_opcode
== None
4082 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4083 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4084 && ((i
.tm
.base_opcode
== 0x24
4085 || i
.tm
.base_opcode
== 0xa8)
4086 || (i
.tm
.base_opcode
== 0x80
4087 && i
.tm
.extension_opcode
== 0x4)
4088 || ((i
.tm
.base_opcode
== 0xf6
4089 || (i
.tm
.base_opcode
| 1) == 0xc7)
4090 && i
.tm
.extension_opcode
== 0x0)))
4091 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4092 && i
.tm
.base_opcode
== 0x83
4093 && i
.tm
.extension_opcode
== 0x4)))
4094 || (i
.types
[0].bitfield
.qword
4095 && ((i
.reg_operands
== 2
4096 && i
.op
[0].regs
== i
.op
[1].regs
4097 && (i
.tm
.base_opcode
== 0x30
4098 || i
.tm
.base_opcode
== 0x28))
4099 || (i
.reg_operands
== 1
4101 && i
.tm
.base_opcode
== 0x30)))))
4104 andq $imm31, %r64 -> andl $imm31, %r32
4105 andq $imm7, %r64 -> andl $imm7, %r32
4106 testq $imm31, %r64 -> testl $imm31, %r32
4107 xorq %r64, %r64 -> xorl %r32, %r32
4108 subq %r64, %r64 -> subl %r32, %r32
4109 movq $imm31, %r64 -> movl $imm31, %r32
4110 movq $imm32, %r64 -> movl $imm32, %r32
4112 i
.tm
.opcode_modifier
.norex64
= 1;
4113 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4116 movq $imm31, %r64 -> movl $imm31, %r32
4117 movq $imm32, %r64 -> movl $imm32, %r32
4119 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4120 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4121 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4122 i
.types
[0].bitfield
.imm32
= 1;
4123 i
.types
[0].bitfield
.imm32s
= 0;
4124 i
.types
[0].bitfield
.imm64
= 0;
4125 i
.types
[1].bitfield
.dword
= 1;
4126 i
.types
[1].bitfield
.qword
= 0;
4127 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4130 movq $imm31, %r64 -> movl $imm31, %r32
4132 i
.tm
.base_opcode
= 0xb8;
4133 i
.tm
.extension_opcode
= None
;
4134 i
.tm
.opcode_modifier
.w
= 0;
4135 i
.tm
.opcode_modifier
.modrm
= 0;
4139 else if (optimize
> 1
4140 && !optimize_for_space
4141 && !is_any_vex_encoding (&i
.tm
)
4142 && i
.reg_operands
== 2
4143 && i
.op
[0].regs
== i
.op
[1].regs
4144 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4145 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4146 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4149 andb %rN, %rN -> testb %rN, %rN
4150 andw %rN, %rN -> testw %rN, %rN
4151 andq %rN, %rN -> testq %rN, %rN
4152 orb %rN, %rN -> testb %rN, %rN
4153 orw %rN, %rN -> testw %rN, %rN
4154 orq %rN, %rN -> testq %rN, %rN
4156 and outside of 64-bit mode
4158 andl %rN, %rN -> testl %rN, %rN
4159 orl %rN, %rN -> testl %rN, %rN
4161 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4163 else if (i
.reg_operands
== 3
4164 && i
.op
[0].regs
== i
.op
[1].regs
4165 && !i
.types
[2].bitfield
.xmmword
4166 && (i
.tm
.opcode_modifier
.vex
4167 || ((!i
.mask
|| i
.mask
->zeroing
)
4169 && is_evex_encoding (&i
.tm
)
4170 && (i
.vec_encoding
!= vex_encoding_evex
4171 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4172 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4173 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4174 && i
.types
[2].bitfield
.ymmword
))))
4175 && ((i
.tm
.base_opcode
== 0x55
4176 || i
.tm
.base_opcode
== 0x57
4177 || i
.tm
.base_opcode
== 0xdf
4178 || i
.tm
.base_opcode
== 0xef
4179 || i
.tm
.base_opcode
== 0xf8
4180 || i
.tm
.base_opcode
== 0xf9
4181 || i
.tm
.base_opcode
== 0xfa
4182 || i
.tm
.base_opcode
== 0xfb
4183 || i
.tm
.base_opcode
== 0x42
4184 || i
.tm
.base_opcode
== 0x47)
4185 && i
.tm
.extension_opcode
== None
))
4188 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4190 EVEX VOP %zmmM, %zmmM, %zmmN
4191 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4192 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4193 EVEX VOP %ymmM, %ymmM, %ymmN
4194 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4195 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4196 VEX VOP %ymmM, %ymmM, %ymmN
4197 -> VEX VOP %xmmM, %xmmM, %xmmN
4198 VOP, one of vpandn and vpxor:
4199 VEX VOP %ymmM, %ymmM, %ymmN
4200 -> VEX VOP %xmmM, %xmmM, %xmmN
4201 VOP, one of vpandnd and vpandnq:
4202 EVEX VOP %zmmM, %zmmM, %zmmN
4203 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4204 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4205 EVEX VOP %ymmM, %ymmM, %ymmN
4206 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4207 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4208 VOP, one of vpxord and vpxorq:
4209 EVEX VOP %zmmM, %zmmM, %zmmN
4210 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4211 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4212 EVEX VOP %ymmM, %ymmM, %ymmN
4213 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4214 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4215 VOP, one of kxord and kxorq:
4216 VEX VOP %kM, %kM, %kN
4217 -> VEX kxorw %kM, %kM, %kN
4218 VOP, one of kandnd and kandnq:
4219 VEX VOP %kM, %kM, %kN
4220 -> VEX kandnw %kM, %kM, %kN
4222 if (is_evex_encoding (&i
.tm
))
4224 if (i
.vec_encoding
!= vex_encoding_evex
)
4226 i
.tm
.opcode_modifier
.vex
= VEX128
;
4227 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4228 i
.tm
.opcode_modifier
.evex
= 0;
4230 else if (optimize
> 1)
4231 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4235 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4237 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4238 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4241 i
.tm
.opcode_modifier
.vex
= VEX128
;
4243 if (i
.tm
.opcode_modifier
.vex
)
4244 for (j
= 0; j
< 3; j
++)
4246 i
.types
[j
].bitfield
.xmmword
= 1;
4247 i
.types
[j
].bitfield
.ymmword
= 0;
4250 else if (i
.vec_encoding
!= vex_encoding_evex
4251 && !i
.types
[0].bitfield
.zmmword
4252 && !i
.types
[1].bitfield
.zmmword
4255 && is_evex_encoding (&i
.tm
)
4256 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4257 || (i
.tm
.base_opcode
& ~4) == 0xdb
4258 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4259 && i
.tm
.extension_opcode
== None
)
4262 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4263 vmovdqu32 and vmovdqu64:
4264 EVEX VOP %xmmM, %xmmN
4265 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4266 EVEX VOP %ymmM, %ymmN
4267 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4269 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4271 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4273 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4275 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4276 VOP, one of vpand, vpandn, vpor, vpxor:
4277 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4278 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4279 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4280 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4281 EVEX VOP{d,q} mem, %xmmM, %xmmN
4282 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4283 EVEX VOP{d,q} mem, %ymmM, %ymmN
4284 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4286 for (j
= 0; j
< i
.operands
; j
++)
4287 if (operand_type_check (i
.types
[j
], disp
)
4288 && i
.op
[j
].disps
->X_op
== O_constant
)
4290 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4291 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4292 bytes, we choose EVEX Disp8 over VEX Disp32. */
4293 int evex_disp8
, vex_disp8
;
4294 unsigned int memshift
= i
.memshift
;
4295 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4297 evex_disp8
= fits_in_disp8 (n
);
4299 vex_disp8
= fits_in_disp8 (n
);
4300 if (evex_disp8
!= vex_disp8
)
4302 i
.memshift
= memshift
;
4306 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4309 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4310 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4311 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4312 i
.tm
.opcode_modifier
.vex
4313 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4314 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4315 /* VPAND, VPOR, and VPXOR are commutative. */
4316 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4317 i
.tm
.opcode_modifier
.commutative
= 1;
4318 i
.tm
.opcode_modifier
.evex
= 0;
4319 i
.tm
.opcode_modifier
.masking
= 0;
4320 i
.tm
.opcode_modifier
.broadcast
= 0;
4321 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4324 i
.types
[j
].bitfield
.disp8
4325 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4329 /* Return non-zero for load instruction. */
4335 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4336 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4340 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4341 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4342 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4343 if (i
.tm
.opcode_modifier
.anysize
)
4346 /* pop, popf, popa. */
4347 if (strcmp (i
.tm
.name
, "pop") == 0
4348 || i
.tm
.base_opcode
== 0x9d
4349 || i
.tm
.base_opcode
== 0x61)
4352 /* movs, cmps, lods, scas. */
4353 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4357 if (base_opcode
== 0x6f
4358 || i
.tm
.base_opcode
== 0xd7)
4360 /* NB: For AMD-specific insns with implicit memory operands,
4361 they're intentionally not covered. */
4364 /* No memory operand. */
4365 if (!i
.mem_operands
)
4371 if (i
.tm
.base_opcode
== 0xae
4372 && i
.tm
.opcode_modifier
.vex
4373 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4374 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4375 && i
.tm
.extension_opcode
== 2)
4380 /* test, not, neg, mul, imul, div, idiv. */
4381 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4382 && i
.tm
.extension_opcode
!= 1)
4386 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4389 /* add, or, adc, sbb, and, sub, xor, cmp. */
4390 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4393 /* bt, bts, btr, btc. */
4394 if (i
.tm
.base_opcode
== 0xfba
4395 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4398 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4399 if ((base_opcode
== 0xc1
4400 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4401 && i
.tm
.extension_opcode
!= 6)
4404 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4405 if (i
.tm
.base_opcode
== 0xfc7
4406 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4407 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4408 || i
.tm
.extension_opcode
== 6))
4411 /* fxrstor, ldmxcsr, xrstor. */
4412 if (i
.tm
.base_opcode
== 0xfae
4413 && (i
.tm
.extension_opcode
== 1
4414 || i
.tm
.extension_opcode
== 2
4415 || i
.tm
.extension_opcode
== 5))
4418 /* lgdt, lidt, lmsw. */
4419 if (i
.tm
.base_opcode
== 0xf01
4420 && (i
.tm
.extension_opcode
== 2
4421 || i
.tm
.extension_opcode
== 3
4422 || i
.tm
.extension_opcode
== 6))
4425 /* Check for x87 instructions. */
4426 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4428 /* Skip fst, fstp, fstenv, fstcw. */
4429 if (i
.tm
.base_opcode
== 0xd9
4430 && (i
.tm
.extension_opcode
== 2
4431 || i
.tm
.extension_opcode
== 3
4432 || i
.tm
.extension_opcode
== 6
4433 || i
.tm
.extension_opcode
== 7))
4436 /* Skip fisttp, fist, fistp, fstp. */
4437 if (i
.tm
.base_opcode
== 0xdb
4438 && (i
.tm
.extension_opcode
== 1
4439 || i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 7))
4444 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4445 if (i
.tm
.base_opcode
== 0xdd
4446 && (i
.tm
.extension_opcode
== 1
4447 || i
.tm
.extension_opcode
== 2
4448 || i
.tm
.extension_opcode
== 3
4449 || i
.tm
.extension_opcode
== 6
4450 || i
.tm
.extension_opcode
== 7))
4453 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4454 if (i
.tm
.base_opcode
== 0xdf
4455 && (i
.tm
.extension_opcode
== 1
4456 || i
.tm
.extension_opcode
== 2
4457 || i
.tm
.extension_opcode
== 3
4458 || i
.tm
.extension_opcode
== 6
4459 || i
.tm
.extension_opcode
== 7))
4466 dest
= i
.operands
- 1;
4468 /* Check fake imm8 operand and 3 source operands. */
4469 if ((i
.tm
.opcode_modifier
.immext
4470 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4471 && i
.types
[dest
].bitfield
.imm8
)
4474 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4476 && (base_opcode
== 0x1
4477 || base_opcode
== 0x9
4478 || base_opcode
== 0x11
4479 || base_opcode
== 0x19
4480 || base_opcode
== 0x21
4481 || base_opcode
== 0x29
4482 || base_opcode
== 0x31
4483 || base_opcode
== 0x39
4484 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4485 || base_opcode
== 0xfc1))
4488 /* Check for load instruction. */
4489 return (i
.types
[dest
].bitfield
.class != ClassNone
4490 || i
.types
[dest
].bitfield
.instance
== Accum
);
4493 /* Output lfence, 0xfaee8, after instruction. */
4496 insert_lfence_after (void)
4498 if (lfence_after_load
&& load_insn_p ())
4500 /* There are also two REP string instructions that require
4501 special treatment. Specifically, the compare string (CMPS)
4502 and scan string (SCAS) instructions set EFLAGS in a manner
4503 that depends on the data being compared/scanned. When used
4504 with a REP prefix, the number of iterations may therefore
4505 vary depending on this data. If the data is a program secret
4506 chosen by the adversary using an LVI method,
4507 then this data-dependent behavior may leak some aspect
4509 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4510 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4511 && i
.prefix
[REP_PREFIX
])
4513 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4516 char *p
= frag_more (3);
4523 /* Output lfence, 0xfaee8, before instruction. */
4526 insert_lfence_before (void)
4530 if (is_any_vex_encoding (&i
.tm
))
4533 if (i
.tm
.base_opcode
== 0xff
4534 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4536 /* Insert lfence before indirect branch if needed. */
4538 if (lfence_before_indirect_branch
== lfence_branch_none
)
4541 if (i
.operands
!= 1)
4544 if (i
.reg_operands
== 1)
4546 /* Indirect branch via register. Don't insert lfence with
4547 -mlfence-after-load=yes. */
4548 if (lfence_after_load
4549 || lfence_before_indirect_branch
== lfence_branch_memory
)
4552 else if (i
.mem_operands
== 1
4553 && lfence_before_indirect_branch
!= lfence_branch_register
)
4555 as_warn (_("indirect `%s` with memory operand should be avoided"),
4562 if (last_insn
.kind
!= last_insn_other
4563 && last_insn
.seg
== now_seg
)
4565 as_warn_where (last_insn
.file
, last_insn
.line
,
4566 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4567 last_insn
.name
, i
.tm
.name
);
4578 /* Output or/not/shl and lfence before near ret. */
4579 if (lfence_before_ret
!= lfence_before_ret_none
4580 && (i
.tm
.base_opcode
== 0xc2
4581 || i
.tm
.base_opcode
== 0xc3))
4583 if (last_insn
.kind
!= last_insn_other
4584 && last_insn
.seg
== now_seg
)
4586 as_warn_where (last_insn
.file
, last_insn
.line
,
4587 _("`%s` skips -mlfence-before-ret on `%s`"),
4588 last_insn
.name
, i
.tm
.name
);
4592 /* Near ret ingore operand size override under CPU64. */
4593 char prefix
= flag_code
== CODE_64BIT
4595 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4597 if (lfence_before_ret
== lfence_before_ret_not
)
4599 /* not: 0xf71424, may add prefix
4600 for operand size override or 64-bit code. */
4601 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4615 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4618 if (lfence_before_ret
== lfence_before_ret_or
)
4620 /* or: 0x830c2400, may add prefix
4621 for operand size override or 64-bit code. */
4627 /* shl: 0xc1242400, may add prefix
4628 for operand size override or 64-bit code. */
4643 /* This is the guts of the machine-dependent assembler. LINE points to a
4644 machine dependent instruction. This function is supposed to emit
4645 the frags/bytes it assembles to. */
4648 md_assemble (char *line
)
4651 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4652 const insn_template
*t
;
4654 /* Initialize globals. */
4655 memset (&i
, '\0', sizeof (i
));
4656 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4657 i
.reloc
[j
] = NO_RELOC
;
4658 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4659 memset (im_expressions
, '\0', sizeof (im_expressions
));
4660 save_stack_p
= save_stack
;
4662 /* First parse an instruction mnemonic & call i386_operand for the operands.
4663 We assume that the scrubber has arranged it so that line[0] is the valid
4664 start of a (possibly prefixed) mnemonic. */
4666 line
= parse_insn (line
, mnemonic
);
4669 mnem_suffix
= i
.suffix
;
4671 line
= parse_operands (line
, mnemonic
);
4673 xfree (i
.memop1_string
);
4674 i
.memop1_string
= NULL
;
4678 /* Now we've parsed the mnemonic into a set of templates, and have the
4679 operands at hand. */
4681 /* All Intel opcodes have reversed operands except for "bound", "enter",
4682 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4683 "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
4684 and "call" instructions with 2 immediate operands so that the immediate
4685 segment precedes the offset consistently in Intel and AT&T modes. */
4688 && (strcmp (mnemonic
, "bound") != 0)
4689 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4690 && (strncmp (mnemonic
, "monitor", 7) != 0)
4691 && (strncmp (mnemonic
, "mwait", 5) != 0)
4692 && (strcmp (mnemonic
, "pvalidate") != 0)
4693 && (strncmp (mnemonic
, "rmp", 3) != 0)
4694 && (strcmp (mnemonic
, "tpause") != 0)
4695 && (strcmp (mnemonic
, "umwait") != 0)
4696 && !(operand_type_check (i
.types
[0], imm
)
4697 && operand_type_check (i
.types
[1], imm
)))
4700 /* The order of the immediates should be reversed
4701 for 2 immediates extrq and insertq instructions */
4702 if (i
.imm_operands
== 2
4703 && (strcmp (mnemonic
, "extrq") == 0
4704 || strcmp (mnemonic
, "insertq") == 0))
4705 swap_2_operands (0, 1);
4710 /* Don't optimize displacement for movabs since it only takes 64bit
4713 && i
.disp_encoding
!= disp_encoding_32bit
4714 && (flag_code
!= CODE_64BIT
4715 || strcmp (mnemonic
, "movabs") != 0))
4718 /* Next, we find a template that matches the given insn,
4719 making sure the overlap of the given operands types is consistent
4720 with the template operand types. */
4722 if (!(t
= match_template (mnem_suffix
)))
4725 if (sse_check
!= check_none
4726 && !i
.tm
.opcode_modifier
.noavx
4727 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4728 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4729 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4730 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4731 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4732 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4733 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4734 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4735 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4736 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4737 || i
.tm
.cpu_flags
.bitfield
.cpusha
4738 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4740 (sse_check
== check_warning
4742 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4745 if (i
.tm
.opcode_modifier
.fwait
)
4746 if (!add_prefix (FWAIT_OPCODE
))
4749 /* Check if REP prefix is OK. */
4750 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4752 as_bad (_("invalid instruction `%s' after `%s'"),
4753 i
.tm
.name
, i
.rep_prefix
);
4757 /* Check for lock without a lockable instruction. Destination operand
4758 must be memory unless it is xchg (0x86). */
4759 if (i
.prefix
[LOCK_PREFIX
]
4760 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4761 || i
.mem_operands
== 0
4762 || (i
.tm
.base_opcode
!= 0x86
4763 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4765 as_bad (_("expecting lockable instruction after `lock'"));
4769 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4770 if (i
.prefix
[DATA_PREFIX
]
4771 && (is_any_vex_encoding (&i
.tm
)
4772 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4773 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4775 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4779 /* Check if HLE prefix is OK. */
4780 if (i
.hle_prefix
&& !check_hle ())
4783 /* Check BND prefix. */
4784 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4785 as_bad (_("expecting valid branch instruction after `bnd'"));
4787 /* Check NOTRACK prefix. */
4788 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
4789 as_bad (_("expecting indirect branch instruction after `notrack'"));
4791 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4793 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4794 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4795 else if (flag_code
!= CODE_16BIT
4796 ? i
.prefix
[ADDR_PREFIX
]
4797 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4798 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4801 /* Insert BND prefix. */
4802 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4804 if (!i
.prefix
[BND_PREFIX
])
4805 add_prefix (BND_PREFIX_OPCODE
);
4806 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4808 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4809 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4813 /* Check string instruction segment overrides. */
4814 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4816 gas_assert (i
.mem_operands
);
4817 if (!check_string ())
4819 i
.disp_operands
= 0;
4822 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4823 optimize_encoding ();
4825 if (!process_suffix ())
4828 /* Update operand types and check extended states. */
4829 for (j
= 0; j
< i
.operands
; j
++)
4831 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4832 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4837 i
.xstate
|= xstate_mmx
;
4840 i
.xstate
|= xstate_mask
;
4843 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4844 i
.xstate
|= xstate_tmm
;
4845 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4846 i
.xstate
|= xstate_zmm
;
4847 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4848 i
.xstate
|= xstate_ymm
;
4849 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4850 i
.xstate
|= xstate_xmm
;
4855 /* Make still unresolved immediate matches conform to size of immediate
4856 given in i.suffix. */
4857 if (!finalize_imm ())
4860 if (i
.types
[0].bitfield
.imm1
)
4861 i
.imm_operands
= 0; /* kludge for shift insns. */
4863 /* We only need to check those implicit registers for instructions
4864 with 3 operands or less. */
4865 if (i
.operands
<= 3)
4866 for (j
= 0; j
< i
.operands
; j
++)
4867 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4868 && !i
.types
[j
].bitfield
.xmmword
)
4871 /* For insns with operands there are more diddles to do to the opcode. */
4874 if (!process_operands ())
4877 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4879 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4880 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4883 if (is_any_vex_encoding (&i
.tm
))
4885 if (!cpu_arch_flags
.bitfield
.cpui286
)
4887 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4892 /* Check for explicit REX prefix. */
4893 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4895 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4899 if (i
.tm
.opcode_modifier
.vex
)
4900 build_vex_prefix (t
);
4902 build_evex_prefix ();
4904 /* The individual REX.RXBW bits got consumed. */
4905 i
.rex
&= REX_OPCODE
;
4908 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4909 instructions may define INT_OPCODE as well, so avoid this corner
4910 case for those instructions that use MODRM. */
4911 if (i
.tm
.base_opcode
== INT_OPCODE
4912 && !i
.tm
.opcode_modifier
.modrm
4913 && i
.op
[0].imms
->X_add_number
== 3)
4915 i
.tm
.base_opcode
= INT3_OPCODE
;
4919 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4920 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4921 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4922 && i
.op
[0].disps
->X_op
== O_constant
)
4924 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4925 the absolute address given by the constant. Since ix86 jumps and
4926 calls are pc relative, we need to generate a reloc. */
4927 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4928 i
.op
[0].disps
->X_op
= O_symbol
;
4931 /* For 8 bit registers we need an empty rex prefix. Also if the
4932 instruction already has a prefix, we need to convert old
4933 registers to new ones. */
4935 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4936 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4937 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4938 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4939 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4940 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4945 i
.rex
|= REX_OPCODE
;
4946 for (x
= 0; x
< 2; x
++)
4948 /* Look for 8 bit operand that uses old registers. */
4949 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4950 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4952 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4953 /* In case it is "hi" register, give up. */
4954 if (i
.op
[x
].regs
->reg_num
> 3)
4955 as_bad (_("can't encode register '%s%s' in an "
4956 "instruction requiring REX prefix."),
4957 register_prefix
, i
.op
[x
].regs
->reg_name
);
4959 /* Otherwise it is equivalent to the extended register.
4960 Since the encoding doesn't change this is merely
4961 cosmetic cleanup for debug output. */
4963 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4968 if (i
.rex
== 0 && i
.rex_encoding
)
4970 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4971 that uses legacy register. If it is "hi" register, don't add
4972 the REX_OPCODE byte. */
4974 for (x
= 0; x
< 2; x
++)
4975 if (i
.types
[x
].bitfield
.class == Reg
4976 && i
.types
[x
].bitfield
.byte
4977 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4978 && i
.op
[x
].regs
->reg_num
> 3)
4980 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4981 i
.rex_encoding
= FALSE
;
4990 add_prefix (REX_OPCODE
| i
.rex
);
4992 insert_lfence_before ();
4994 /* We are ready to output the insn. */
4997 insert_lfence_after ();
4999 last_insn
.seg
= now_seg
;
5001 if (i
.tm
.opcode_modifier
.isprefix
)
5003 last_insn
.kind
= last_insn_prefix
;
5004 last_insn
.name
= i
.tm
.name
;
5005 last_insn
.file
= as_where (&last_insn
.line
);
5008 last_insn
.kind
= last_insn_other
;
5012 parse_insn (char *line
, char *mnemonic
)
5015 char *token_start
= l
;
5018 const insn_template
*t
;
5024 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5029 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5031 as_bad (_("no such instruction: `%s'"), token_start
);
5036 if (!is_space_char (*l
)
5037 && *l
!= END_OF_INSN
5039 || (*l
!= PREFIX_SEPARATOR
5042 as_bad (_("invalid character %s in mnemonic"),
5043 output_invalid (*l
));
5046 if (token_start
== l
)
5048 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5049 as_bad (_("expecting prefix; got nothing"));
5051 as_bad (_("expecting mnemonic; got nothing"));
5055 /* Look up instruction (or prefix) via hash table. */
5056 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5058 if (*l
!= END_OF_INSN
5059 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5060 && current_templates
5061 && current_templates
->start
->opcode_modifier
.isprefix
)
5063 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5065 as_bad ((flag_code
!= CODE_64BIT
5066 ? _("`%s' is only supported in 64-bit mode")
5067 : _("`%s' is not supported in 64-bit mode")),
5068 current_templates
->start
->name
);
5071 /* If we are in 16-bit mode, do not allow addr16 or data16.
5072 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5073 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5074 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5075 && flag_code
!= CODE_64BIT
5076 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5077 ^ (flag_code
== CODE_16BIT
)))
5079 as_bad (_("redundant %s prefix"),
5080 current_templates
->start
->name
);
5084 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5086 /* Handle pseudo prefixes. */
5087 switch (current_templates
->start
->extension_opcode
)
5091 i
.disp_encoding
= disp_encoding_8bit
;
5095 i
.disp_encoding
= disp_encoding_16bit
;
5099 i
.disp_encoding
= disp_encoding_32bit
;
5103 i
.dir_encoding
= dir_encoding_load
;
5107 i
.dir_encoding
= dir_encoding_store
;
5111 i
.vec_encoding
= vex_encoding_vex
;
5115 i
.vec_encoding
= vex_encoding_vex3
;
5119 i
.vec_encoding
= vex_encoding_evex
;
5123 i
.rex_encoding
= TRUE
;
5125 case Prefix_NoOptimize
:
5127 i
.no_optimize
= TRUE
;
5135 /* Add prefix, checking for repeated prefixes. */
5136 switch (add_prefix (current_templates
->start
->base_opcode
))
5141 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5142 i
.notrack_prefix
= current_templates
->start
->name
;
5145 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5146 i
.hle_prefix
= current_templates
->start
->name
;
5147 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5148 i
.bnd_prefix
= current_templates
->start
->name
;
5150 i
.rep_prefix
= current_templates
->start
->name
;
5156 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5163 if (!current_templates
)
5165 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5166 Check if we should swap operand or force 32bit displacement in
5168 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5169 i
.dir_encoding
= dir_encoding_swap
;
5170 else if (mnem_p
- 3 == dot_p
5173 i
.disp_encoding
= disp_encoding_8bit
;
5174 else if (mnem_p
- 4 == dot_p
5178 i
.disp_encoding
= disp_encoding_32bit
;
5183 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5186 if (!current_templates
)
5189 if (mnem_p
> mnemonic
)
5191 /* See if we can get a match by trimming off a suffix. */
5194 case WORD_MNEM_SUFFIX
:
5195 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5196 i
.suffix
= SHORT_MNEM_SUFFIX
;
5199 case BYTE_MNEM_SUFFIX
:
5200 case QWORD_MNEM_SUFFIX
:
5201 i
.suffix
= mnem_p
[-1];
5204 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5206 case SHORT_MNEM_SUFFIX
:
5207 case LONG_MNEM_SUFFIX
:
5210 i
.suffix
= mnem_p
[-1];
5213 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5221 if (intel_float_operand (mnemonic
) == 1)
5222 i
.suffix
= SHORT_MNEM_SUFFIX
;
5224 i
.suffix
= LONG_MNEM_SUFFIX
;
5227 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5233 if (!current_templates
)
5235 as_bad (_("no such instruction: `%s'"), token_start
);
5240 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5241 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5243 /* Check for a branch hint. We allow ",pt" and ",pn" for
5244 predict taken and predict not taken respectively.
5245 I'm not sure that branch hints actually do anything on loop
5246 and jcxz insns (JumpByte) for current Pentium4 chips. They
5247 may work in the future and it doesn't hurt to accept them
5249 if (l
[0] == ',' && l
[1] == 'p')
5253 if (!add_prefix (DS_PREFIX_OPCODE
))
5257 else if (l
[2] == 'n')
5259 if (!add_prefix (CS_PREFIX_OPCODE
))
5265 /* Any other comma loses. */
5268 as_bad (_("invalid character %s in mnemonic"),
5269 output_invalid (*l
));
5273 /* Check if instruction is supported on specified architecture. */
5275 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5277 supported
|= cpu_flags_match (t
);
5278 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5280 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5281 as_warn (_("use .code16 to ensure correct addressing mode"));
5287 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5288 as_bad (flag_code
== CODE_64BIT
5289 ? _("`%s' is not supported in 64-bit mode")
5290 : _("`%s' is only supported in 64-bit mode"),
5291 current_templates
->start
->name
);
5293 as_bad (_("`%s' is not supported on `%s%s'"),
5294 current_templates
->start
->name
,
5295 cpu_arch_name
? cpu_arch_name
: default_arch
,
5296 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5302 parse_operands (char *l
, const char *mnemonic
)
5306 /* 1 if operand is pending after ','. */
5307 unsigned int expecting_operand
= 0;
5309 /* Non-zero if operand parens not balanced. */
5310 unsigned int paren_not_balanced
;
5312 while (*l
!= END_OF_INSN
)
5314 /* Skip optional white space before operand. */
5315 if (is_space_char (*l
))
5317 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5319 as_bad (_("invalid character %s before operand %d"),
5320 output_invalid (*l
),
5324 token_start
= l
; /* After white space. */
5325 paren_not_balanced
= 0;
5326 while (paren_not_balanced
|| *l
!= ',')
5328 if (*l
== END_OF_INSN
)
5330 if (paren_not_balanced
)
5333 as_bad (_("unbalanced parenthesis in operand %d."),
5336 as_bad (_("unbalanced brackets in operand %d."),
5341 break; /* we are done */
5343 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5345 as_bad (_("invalid character %s in operand %d"),
5346 output_invalid (*l
),
5353 ++paren_not_balanced
;
5355 --paren_not_balanced
;
5360 ++paren_not_balanced
;
5362 --paren_not_balanced
;
5366 if (l
!= token_start
)
5367 { /* Yes, we've read in another operand. */
5368 unsigned int operand_ok
;
5369 this_operand
= i
.operands
++;
5370 if (i
.operands
> MAX_OPERANDS
)
5372 as_bad (_("spurious operands; (%d operands/instruction max)"),
5376 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5377 /* Now parse operand adding info to 'i' as we go along. */
5378 END_STRING_AND_SAVE (l
);
5380 if (i
.mem_operands
> 1)
5382 as_bad (_("too many memory references for `%s'"),
5389 i386_intel_operand (token_start
,
5390 intel_float_operand (mnemonic
));
5392 operand_ok
= i386_att_operand (token_start
);
5394 RESTORE_END_STRING (l
);
5400 if (expecting_operand
)
5402 expecting_operand_after_comma
:
5403 as_bad (_("expecting operand after ','; got nothing"));
5408 as_bad (_("expecting operand before ','; got nothing"));
5413 /* Now *l must be either ',' or END_OF_INSN. */
5416 if (*++l
== END_OF_INSN
)
5418 /* Just skip it, if it's \n complain. */
5419 goto expecting_operand_after_comma
;
5421 expecting_operand
= 1;
5428 swap_2_operands (int xchg1
, int xchg2
)
5430 union i386_op temp_op
;
5431 i386_operand_type temp_type
;
5432 unsigned int temp_flags
;
5433 enum bfd_reloc_code_real temp_reloc
;
5435 temp_type
= i
.types
[xchg2
];
5436 i
.types
[xchg2
] = i
.types
[xchg1
];
5437 i
.types
[xchg1
] = temp_type
;
5439 temp_flags
= i
.flags
[xchg2
];
5440 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5441 i
.flags
[xchg1
] = temp_flags
;
5443 temp_op
= i
.op
[xchg2
];
5444 i
.op
[xchg2
] = i
.op
[xchg1
];
5445 i
.op
[xchg1
] = temp_op
;
5447 temp_reloc
= i
.reloc
[xchg2
];
5448 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5449 i
.reloc
[xchg1
] = temp_reloc
;
5453 if (i
.mask
->operand
== xchg1
)
5454 i
.mask
->operand
= xchg2
;
5455 else if (i
.mask
->operand
== xchg2
)
5456 i
.mask
->operand
= xchg1
;
5460 if (i
.broadcast
->operand
== xchg1
)
5461 i
.broadcast
->operand
= xchg2
;
5462 else if (i
.broadcast
->operand
== xchg2
)
5463 i
.broadcast
->operand
= xchg1
;
5467 if (i
.rounding
->operand
== xchg1
)
5468 i
.rounding
->operand
= xchg2
;
5469 else if (i
.rounding
->operand
== xchg2
)
5470 i
.rounding
->operand
= xchg1
;
5475 swap_operands (void)
5481 swap_2_operands (1, i
.operands
- 2);
5485 swap_2_operands (0, i
.operands
- 1);
5491 if (i
.mem_operands
== 2)
5493 const seg_entry
*temp_seg
;
5494 temp_seg
= i
.seg
[0];
5495 i
.seg
[0] = i
.seg
[1];
5496 i
.seg
[1] = temp_seg
;
5500 /* Try to ensure constant immediates are represented in the smallest
5505 char guess_suffix
= 0;
5509 guess_suffix
= i
.suffix
;
5510 else if (i
.reg_operands
)
5512 /* Figure out a suffix from the last register operand specified.
5513 We can't do this properly yet, i.e. excluding special register
5514 instances, but the following works for instructions with
5515 immediates. In any case, we can't set i.suffix yet. */
5516 for (op
= i
.operands
; --op
>= 0;)
5517 if (i
.types
[op
].bitfield
.class != Reg
)
5519 else if (i
.types
[op
].bitfield
.byte
)
5521 guess_suffix
= BYTE_MNEM_SUFFIX
;
5524 else if (i
.types
[op
].bitfield
.word
)
5526 guess_suffix
= WORD_MNEM_SUFFIX
;
5529 else if (i
.types
[op
].bitfield
.dword
)
5531 guess_suffix
= LONG_MNEM_SUFFIX
;
5534 else if (i
.types
[op
].bitfield
.qword
)
5536 guess_suffix
= QWORD_MNEM_SUFFIX
;
5540 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5541 guess_suffix
= WORD_MNEM_SUFFIX
;
5543 for (op
= i
.operands
; --op
>= 0;)
5544 if (operand_type_check (i
.types
[op
], imm
))
5546 switch (i
.op
[op
].imms
->X_op
)
5549 /* If a suffix is given, this operand may be shortened. */
5550 switch (guess_suffix
)
5552 case LONG_MNEM_SUFFIX
:
5553 i
.types
[op
].bitfield
.imm32
= 1;
5554 i
.types
[op
].bitfield
.imm64
= 1;
5556 case WORD_MNEM_SUFFIX
:
5557 i
.types
[op
].bitfield
.imm16
= 1;
5558 i
.types
[op
].bitfield
.imm32
= 1;
5559 i
.types
[op
].bitfield
.imm32s
= 1;
5560 i
.types
[op
].bitfield
.imm64
= 1;
5562 case BYTE_MNEM_SUFFIX
:
5563 i
.types
[op
].bitfield
.imm8
= 1;
5564 i
.types
[op
].bitfield
.imm8s
= 1;
5565 i
.types
[op
].bitfield
.imm16
= 1;
5566 i
.types
[op
].bitfield
.imm32
= 1;
5567 i
.types
[op
].bitfield
.imm32s
= 1;
5568 i
.types
[op
].bitfield
.imm64
= 1;
5572 /* If this operand is at most 16 bits, convert it
5573 to a signed 16 bit number before trying to see
5574 whether it will fit in an even smaller size.
5575 This allows a 16-bit operand such as $0xffe0 to
5576 be recognised as within Imm8S range. */
5577 if ((i
.types
[op
].bitfield
.imm16
)
5578 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5580 i
.op
[op
].imms
->X_add_number
=
5581 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5584 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5585 if ((i
.types
[op
].bitfield
.imm32
)
5586 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5589 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5590 ^ ((offsetT
) 1 << 31))
5591 - ((offsetT
) 1 << 31));
5595 = operand_type_or (i
.types
[op
],
5596 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5598 /* We must avoid matching of Imm32 templates when 64bit
5599 only immediate is available. */
5600 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5601 i
.types
[op
].bitfield
.imm32
= 0;
5608 /* Symbols and expressions. */
5610 /* Convert symbolic operand to proper sizes for matching, but don't
5611 prevent matching a set of insns that only supports sizes other
5612 than those matching the insn suffix. */
5614 i386_operand_type mask
, allowed
;
5615 const insn_template
*t
;
5617 operand_type_set (&mask
, 0);
5618 operand_type_set (&allowed
, 0);
5620 for (t
= current_templates
->start
;
5621 t
< current_templates
->end
;
5624 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5625 allowed
= operand_type_and (allowed
, anyimm
);
5627 switch (guess_suffix
)
5629 case QWORD_MNEM_SUFFIX
:
5630 mask
.bitfield
.imm64
= 1;
5631 mask
.bitfield
.imm32s
= 1;
5633 case LONG_MNEM_SUFFIX
:
5634 mask
.bitfield
.imm32
= 1;
5636 case WORD_MNEM_SUFFIX
:
5637 mask
.bitfield
.imm16
= 1;
5639 case BYTE_MNEM_SUFFIX
:
5640 mask
.bitfield
.imm8
= 1;
5645 allowed
= operand_type_and (mask
, allowed
);
5646 if (!operand_type_all_zero (&allowed
))
5647 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5654 /* Try to use the smallest displacement type too. */
5656 optimize_disp (void)
5660 for (op
= i
.operands
; --op
>= 0;)
5661 if (operand_type_check (i
.types
[op
], disp
))
5663 if (i
.op
[op
].disps
->X_op
== O_constant
)
5665 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5667 if (i
.types
[op
].bitfield
.disp16
5668 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5670 /* If this operand is at most 16 bits, convert
5671 to a signed 16 bit number and don't use 64bit
5673 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5674 i
.types
[op
].bitfield
.disp64
= 0;
5677 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5678 if (i
.types
[op
].bitfield
.disp32
5679 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5681 /* If this operand is at most 32 bits, convert
5682 to a signed 32 bit number and don't use 64bit
5684 op_disp
&= (((offsetT
) 2 << 31) - 1);
5685 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5686 i
.types
[op
].bitfield
.disp64
= 0;
5689 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5691 i
.types
[op
].bitfield
.disp8
= 0;
5692 i
.types
[op
].bitfield
.disp16
= 0;
5693 i
.types
[op
].bitfield
.disp32
= 0;
5694 i
.types
[op
].bitfield
.disp32s
= 0;
5695 i
.types
[op
].bitfield
.disp64
= 0;
5699 else if (flag_code
== CODE_64BIT
)
5701 if (fits_in_signed_long (op_disp
))
5703 i
.types
[op
].bitfield
.disp64
= 0;
5704 i
.types
[op
].bitfield
.disp32s
= 1;
5706 if (i
.prefix
[ADDR_PREFIX
]
5707 && fits_in_unsigned_long (op_disp
))
5708 i
.types
[op
].bitfield
.disp32
= 1;
5710 if ((i
.types
[op
].bitfield
.disp32
5711 || i
.types
[op
].bitfield
.disp32s
5712 || i
.types
[op
].bitfield
.disp16
)
5713 && fits_in_disp8 (op_disp
))
5714 i
.types
[op
].bitfield
.disp8
= 1;
5716 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5717 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5719 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5720 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5721 i
.types
[op
].bitfield
.disp8
= 0;
5722 i
.types
[op
].bitfield
.disp16
= 0;
5723 i
.types
[op
].bitfield
.disp32
= 0;
5724 i
.types
[op
].bitfield
.disp32s
= 0;
5725 i
.types
[op
].bitfield
.disp64
= 0;
5728 /* We only support 64bit displacement on constants. */
5729 i
.types
[op
].bitfield
.disp64
= 0;
5733 /* Return 1 if there is a match in broadcast bytes between operand
5734 GIVEN and instruction template T. */
5737 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5739 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5740 && i
.types
[given
].bitfield
.byte
)
5741 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5742 && i
.types
[given
].bitfield
.word
)
5743 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5744 && i
.types
[given
].bitfield
.dword
)
5745 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5746 && i
.types
[given
].bitfield
.qword
));
5749 /* Check if operands are valid for the instruction. */
5752 check_VecOperands (const insn_template
*t
)
5757 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5758 any one operand are implicity requiring AVX512VL support if the actual
5759 operand size is YMMword or XMMword. Since this function runs after
5760 template matching, there's no need to check for YMMword/XMMword in
5762 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5763 if (!cpu_flags_all_zero (&cpu
)
5764 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5765 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5767 for (op
= 0; op
< t
->operands
; ++op
)
5769 if (t
->operand_types
[op
].bitfield
.zmmword
5770 && (i
.types
[op
].bitfield
.ymmword
5771 || i
.types
[op
].bitfield
.xmmword
))
5773 i
.error
= unsupported
;
5779 /* Without VSIB byte, we can't have a vector register for index. */
5780 if (!t
->opcode_modifier
.sib
5782 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5783 || i
.index_reg
->reg_type
.bitfield
.ymmword
5784 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5786 i
.error
= unsupported_vector_index_register
;
5790 /* Check if default mask is allowed. */
5791 if (t
->opcode_modifier
.nodefmask
5792 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5794 i
.error
= no_default_mask
;
5798 /* For VSIB byte, we need a vector register for index, and all vector
5799 registers must be distinct. */
5800 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5803 || !((t
->opcode_modifier
.sib
== VECSIB128
5804 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5805 || (t
->opcode_modifier
.sib
== VECSIB256
5806 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5807 || (t
->opcode_modifier
.sib
== VECSIB512
5808 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5810 i
.error
= invalid_vsib_address
;
5814 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5815 if (i
.reg_operands
== 2 && !i
.mask
)
5817 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5818 gas_assert (i
.types
[0].bitfield
.xmmword
5819 || i
.types
[0].bitfield
.ymmword
);
5820 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5821 gas_assert (i
.types
[2].bitfield
.xmmword
5822 || i
.types
[2].bitfield
.ymmword
);
5823 if (operand_check
== check_none
)
5825 if (register_number (i
.op
[0].regs
)
5826 != register_number (i
.index_reg
)
5827 && register_number (i
.op
[2].regs
)
5828 != register_number (i
.index_reg
)
5829 && register_number (i
.op
[0].regs
)
5830 != register_number (i
.op
[2].regs
))
5832 if (operand_check
== check_error
)
5834 i
.error
= invalid_vector_register_set
;
5837 as_warn (_("mask, index, and destination registers should be distinct"));
5839 else if (i
.reg_operands
== 1 && i
.mask
)
5841 if (i
.types
[1].bitfield
.class == RegSIMD
5842 && (i
.types
[1].bitfield
.xmmword
5843 || i
.types
[1].bitfield
.ymmword
5844 || i
.types
[1].bitfield
.zmmword
)
5845 && (register_number (i
.op
[1].regs
)
5846 == register_number (i
.index_reg
)))
5848 if (operand_check
== check_error
)
5850 i
.error
= invalid_vector_register_set
;
5853 if (operand_check
!= check_none
)
5854 as_warn (_("index and destination registers should be distinct"));
5859 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5861 if (t
->operand_types
[0].bitfield
.tmmword
5862 && i
.reg_operands
== 3)
5864 if (register_number (i
.op
[0].regs
)
5865 == register_number (i
.op
[1].regs
)
5866 || register_number (i
.op
[0].regs
)
5867 == register_number (i
.op
[2].regs
)
5868 || register_number (i
.op
[1].regs
)
5869 == register_number (i
.op
[2].regs
))
5871 i
.error
= invalid_tmm_register_set
;
5876 /* Check if broadcast is supported by the instruction and is applied
5877 to the memory operand. */
5880 i386_operand_type type
, overlap
;
5882 /* Check if specified broadcast is supported in this instruction,
5883 and its broadcast bytes match the memory operand. */
5884 op
= i
.broadcast
->operand
;
5885 if (!t
->opcode_modifier
.broadcast
5886 || !(i
.flags
[op
] & Operand_Mem
)
5887 || (!i
.types
[op
].bitfield
.unspecified
5888 && !match_broadcast_size (t
, op
)))
5891 i
.error
= unsupported_broadcast
;
5895 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5896 * i
.broadcast
->type
);
5897 operand_type_set (&type
, 0);
5898 switch (i
.broadcast
->bytes
)
5901 type
.bitfield
.word
= 1;
5904 type
.bitfield
.dword
= 1;
5907 type
.bitfield
.qword
= 1;
5910 type
.bitfield
.xmmword
= 1;
5913 type
.bitfield
.ymmword
= 1;
5916 type
.bitfield
.zmmword
= 1;
5922 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5923 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5924 && t
->operand_types
[op
].bitfield
.byte
5925 + t
->operand_types
[op
].bitfield
.word
5926 + t
->operand_types
[op
].bitfield
.dword
5927 + t
->operand_types
[op
].bitfield
.qword
> 1)
5929 overlap
.bitfield
.xmmword
= 0;
5930 overlap
.bitfield
.ymmword
= 0;
5931 overlap
.bitfield
.zmmword
= 0;
5933 if (operand_type_all_zero (&overlap
))
5936 if (t
->opcode_modifier
.checkregsize
)
5940 type
.bitfield
.baseindex
= 1;
5941 for (j
= 0; j
< i
.operands
; ++j
)
5944 && !operand_type_register_match(i
.types
[j
],
5945 t
->operand_types
[j
],
5947 t
->operand_types
[op
]))
5952 /* If broadcast is supported in this instruction, we need to check if
5953 operand of one-element size isn't specified without broadcast. */
5954 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5956 /* Find memory operand. */
5957 for (op
= 0; op
< i
.operands
; op
++)
5958 if (i
.flags
[op
] & Operand_Mem
)
5960 gas_assert (op
< i
.operands
);
5961 /* Check size of the memory operand. */
5962 if (match_broadcast_size (t
, op
))
5964 i
.error
= broadcast_needed
;
5969 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5971 /* Check if requested masking is supported. */
5974 switch (t
->opcode_modifier
.masking
)
5978 case MERGING_MASKING
:
5979 if (i
.mask
->zeroing
)
5982 i
.error
= unsupported_masking
;
5986 case DYNAMIC_MASKING
:
5987 /* Memory destinations allow only merging masking. */
5988 if (i
.mask
->zeroing
&& i
.mem_operands
)
5990 /* Find memory operand. */
5991 for (op
= 0; op
< i
.operands
; op
++)
5992 if (i
.flags
[op
] & Operand_Mem
)
5994 gas_assert (op
< i
.operands
);
5995 if (op
== i
.operands
- 1)
5997 i
.error
= unsupported_masking
;
6007 /* Check if masking is applied to dest operand. */
6008 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6010 i
.error
= mask_not_on_destination
;
6017 if (!t
->opcode_modifier
.sae
6018 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6020 i
.error
= unsupported_rc_sae
;
6023 /* If the instruction has several immediate operands and one of
6024 them is rounding, the rounding operand should be the last
6025 immediate operand. */
6026 if (i
.imm_operands
> 1
6027 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6029 i
.error
= rc_sae_operand_not_last_imm
;
6034 /* Check the special Imm4 cases; must be the first operand. */
6035 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6037 if (i
.op
[0].imms
->X_op
!= O_constant
6038 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6044 /* Turn off Imm<N> so that update_imm won't complain. */
6045 operand_type_set (&i
.types
[0], 0);
6048 /* Check vector Disp8 operand. */
6049 if (t
->opcode_modifier
.disp8memshift
6050 && i
.disp_encoding
!= disp_encoding_32bit
)
6053 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6054 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6055 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6058 const i386_operand_type
*type
= NULL
;
6061 for (op
= 0; op
< i
.operands
; op
++)
6062 if (i
.flags
[op
] & Operand_Mem
)
6064 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6065 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6066 else if (t
->operand_types
[op
].bitfield
.xmmword
6067 + t
->operand_types
[op
].bitfield
.ymmword
6068 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6069 type
= &t
->operand_types
[op
];
6070 else if (!i
.types
[op
].bitfield
.unspecified
)
6071 type
= &i
.types
[op
];
6073 else if (i
.types
[op
].bitfield
.class == RegSIMD
6074 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6076 if (i
.types
[op
].bitfield
.zmmword
)
6078 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6080 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6086 if (type
->bitfield
.zmmword
)
6088 else if (type
->bitfield
.ymmword
)
6090 else if (type
->bitfield
.xmmword
)
6094 /* For the check in fits_in_disp8(). */
6095 if (i
.memshift
== 0)
6099 for (op
= 0; op
< i
.operands
; op
++)
6100 if (operand_type_check (i
.types
[op
], disp
)
6101 && i
.op
[op
].disps
->X_op
== O_constant
)
6103 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6105 i
.types
[op
].bitfield
.disp8
= 1;
6108 i
.types
[op
].bitfield
.disp8
= 0;
6117 /* Check if encoding requirements are met by the instruction. */
6120 VEX_check_encoding (const insn_template
*t
)
6122 if (i
.vec_encoding
== vex_encoding_error
)
6124 i
.error
= unsupported
;
6128 if (i
.vec_encoding
== vex_encoding_evex
)
6130 /* This instruction must be encoded with EVEX prefix. */
6131 if (!is_evex_encoding (t
))
6133 i
.error
= unsupported
;
6139 if (!t
->opcode_modifier
.vex
)
6141 /* This instruction template doesn't have VEX prefix. */
6142 if (i
.vec_encoding
!= vex_encoding_default
)
6144 i
.error
= unsupported
;
6153 static const insn_template
*
6154 match_template (char mnem_suffix
)
6156 /* Points to template once we've found it. */
6157 const insn_template
*t
;
6158 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6159 i386_operand_type overlap4
;
6160 unsigned int found_reverse_match
;
6161 i386_opcode_modifier suffix_check
;
6162 i386_operand_type operand_types
[MAX_OPERANDS
];
6163 int addr_prefix_disp
;
6164 unsigned int j
, size_match
, check_register
;
6165 enum i386_error specific_error
= 0;
6167 #if MAX_OPERANDS != 5
6168 # error "MAX_OPERANDS must be 5."
6171 found_reverse_match
= 0;
6172 addr_prefix_disp
= -1;
6174 /* Prepare for mnemonic suffix check. */
6175 memset (&suffix_check
, 0, sizeof (suffix_check
));
6176 switch (mnem_suffix
)
6178 case BYTE_MNEM_SUFFIX
:
6179 suffix_check
.no_bsuf
= 1;
6181 case WORD_MNEM_SUFFIX
:
6182 suffix_check
.no_wsuf
= 1;
6184 case SHORT_MNEM_SUFFIX
:
6185 suffix_check
.no_ssuf
= 1;
6187 case LONG_MNEM_SUFFIX
:
6188 suffix_check
.no_lsuf
= 1;
6190 case QWORD_MNEM_SUFFIX
:
6191 suffix_check
.no_qsuf
= 1;
6194 /* NB: In Intel syntax, normally we can check for memory operand
6195 size when there is no mnemonic suffix. But jmp and call have
6196 2 different encodings with Dword memory operand size, one with
6197 No_ldSuf and the other without. i.suffix is set to
6198 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6199 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6200 suffix_check
.no_ldsuf
= 1;
6203 /* Must have right number of operands. */
6204 i
.error
= number_of_operands_mismatch
;
6206 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6208 addr_prefix_disp
= -1;
6209 found_reverse_match
= 0;
6211 if (i
.operands
!= t
->operands
)
6214 /* Check processor support. */
6215 i
.error
= unsupported
;
6216 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6219 /* Check Pseudo Prefix. */
6220 i
.error
= unsupported
;
6221 if (t
->opcode_modifier
.pseudovexprefix
6222 && !(i
.vec_encoding
== vex_encoding_vex
6223 || i
.vec_encoding
== vex_encoding_vex3
))
6226 /* Check AT&T mnemonic. */
6227 i
.error
= unsupported_with_intel_mnemonic
;
6228 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6231 /* Check AT&T/Intel syntax. */
6232 i
.error
= unsupported_syntax
;
6233 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6234 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6237 /* Check Intel64/AMD64 ISA. */
6241 /* Default: Don't accept Intel64. */
6242 if (t
->opcode_modifier
.isa64
== INTEL64
)
6246 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6247 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6251 /* -mintel64: Don't accept AMD64. */
6252 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6257 /* Check the suffix. */
6258 i
.error
= invalid_instruction_suffix
;
6259 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6260 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6261 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6262 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6263 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6264 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6267 size_match
= operand_size_match (t
);
6271 /* This is intentionally not
6273 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6275 as the case of a missing * on the operand is accepted (perhaps with
6276 a warning, issued further down). */
6277 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6279 i
.error
= operand_type_mismatch
;
6283 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6284 operand_types
[j
] = t
->operand_types
[j
];
6286 /* In general, don't allow
6287 - 64-bit operands outside of 64-bit mode,
6288 - 32-bit operands on pre-386. */
6289 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6290 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6291 && flag_code
!= CODE_64BIT
6292 && !(t
->base_opcode
== 0xfc7
6293 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6294 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6295 || (i
.suffix
== LONG_MNEM_SUFFIX
6296 && !cpu_arch_flags
.bitfield
.cpui386
))
6298 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6299 && !intel_float_operand (t
->name
))
6300 : intel_float_operand (t
->name
) != 2)
6301 && (t
->operands
== i
.imm_operands
6302 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6303 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6304 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6305 || (operand_types
[j
].bitfield
.class != RegMMX
6306 && operand_types
[j
].bitfield
.class != RegSIMD
6307 && operand_types
[j
].bitfield
.class != RegMask
))
6308 && !t
->opcode_modifier
.sib
)
6311 /* Do not verify operands when there are none. */
6314 if (VEX_check_encoding (t
))
6316 specific_error
= i
.error
;
6320 /* We've found a match; break out of loop. */
6324 if (!t
->opcode_modifier
.jump
6325 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6327 /* There should be only one Disp operand. */
6328 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6329 if (operand_type_check (operand_types
[j
], disp
))
6331 if (j
< MAX_OPERANDS
)
6333 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6335 addr_prefix_disp
= j
;
6337 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6338 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6342 override
= !override
;
6345 if (operand_types
[j
].bitfield
.disp32
6346 && operand_types
[j
].bitfield
.disp16
)
6348 operand_types
[j
].bitfield
.disp16
= override
;
6349 operand_types
[j
].bitfield
.disp32
= !override
;
6351 operand_types
[j
].bitfield
.disp32s
= 0;
6352 operand_types
[j
].bitfield
.disp64
= 0;
6356 if (operand_types
[j
].bitfield
.disp32s
6357 || operand_types
[j
].bitfield
.disp64
)
6359 operand_types
[j
].bitfield
.disp64
&= !override
;
6360 operand_types
[j
].bitfield
.disp32s
&= !override
;
6361 operand_types
[j
].bitfield
.disp32
= override
;
6363 operand_types
[j
].bitfield
.disp16
= 0;
6369 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6370 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6371 && t
->base_opcode
== 0xa0
6372 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6375 /* We check register size if needed. */
6376 if (t
->opcode_modifier
.checkregsize
)
6378 check_register
= (1 << t
->operands
) - 1;
6380 check_register
&= ~(1 << i
.broadcast
->operand
);
6385 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6386 switch (t
->operands
)
6389 if (!operand_type_match (overlap0
, i
.types
[0]))
6393 /* xchg %eax, %eax is a special case. It is an alias for nop
6394 only in 32bit mode and we can use opcode 0x90. In 64bit
6395 mode, we can't use 0x90 for xchg %eax, %eax since it should
6396 zero-extend %eax to %rax. */
6397 if (flag_code
== CODE_64BIT
6398 && t
->base_opcode
== 0x90
6399 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6400 && i
.types
[0].bitfield
.instance
== Accum
6401 && i
.types
[0].bitfield
.dword
6402 && i
.types
[1].bitfield
.instance
== Accum
6403 && i
.types
[1].bitfield
.dword
)
6405 /* xrelease mov %eax, <disp> is another special case. It must not
6406 match the accumulator-only encoding of mov. */
6407 if (flag_code
!= CODE_64BIT
6409 && t
->base_opcode
== 0xa0
6410 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6411 && i
.types
[0].bitfield
.instance
== Accum
6412 && (i
.flags
[1] & Operand_Mem
))
6417 if (!(size_match
& MATCH_STRAIGHT
))
6419 /* Reverse direction of operands if swapping is possible in the first
6420 place (operands need to be symmetric) and
6421 - the load form is requested, and the template is a store form,
6422 - the store form is requested, and the template is a load form,
6423 - the non-default (swapped) form is requested. */
6424 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6425 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6426 && !operand_type_all_zero (&overlap1
))
6427 switch (i
.dir_encoding
)
6429 case dir_encoding_load
:
6430 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6431 || t
->opcode_modifier
.regmem
)
6435 case dir_encoding_store
:
6436 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6437 && !t
->opcode_modifier
.regmem
)
6441 case dir_encoding_swap
:
6444 case dir_encoding_default
:
6447 /* If we want store form, we skip the current load. */
6448 if ((i
.dir_encoding
== dir_encoding_store
6449 || i
.dir_encoding
== dir_encoding_swap
)
6450 && i
.mem_operands
== 0
6451 && t
->opcode_modifier
.load
)
6456 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6457 if (!operand_type_match (overlap0
, i
.types
[0])
6458 || !operand_type_match (overlap1
, i
.types
[1])
6459 || ((check_register
& 3) == 3
6460 && !operand_type_register_match (i
.types
[0],
6465 /* Check if other direction is valid ... */
6466 if (!t
->opcode_modifier
.d
)
6470 if (!(size_match
& MATCH_REVERSE
))
6472 /* Try reversing direction of operands. */
6473 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6474 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6475 if (!operand_type_match (overlap0
, i
.types
[0])
6476 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6478 && !operand_type_register_match (i
.types
[0],
6479 operand_types
[i
.operands
- 1],
6480 i
.types
[i
.operands
- 1],
6483 /* Does not match either direction. */
6486 /* found_reverse_match holds which of D or FloatR
6488 if (!t
->opcode_modifier
.d
)
6489 found_reverse_match
= 0;
6490 else if (operand_types
[0].bitfield
.tbyte
)
6491 found_reverse_match
= Opcode_FloatD
;
6492 else if (operand_types
[0].bitfield
.xmmword
6493 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6494 || operand_types
[0].bitfield
.class == RegMMX
6495 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6496 || is_any_vex_encoding(t
))
6497 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6498 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6500 found_reverse_match
= Opcode_D
;
6501 if (t
->opcode_modifier
.floatr
)
6502 found_reverse_match
|= Opcode_FloatR
;
6506 /* Found a forward 2 operand match here. */
6507 switch (t
->operands
)
6510 overlap4
= operand_type_and (i
.types
[4],
6514 overlap3
= operand_type_and (i
.types
[3],
6518 overlap2
= operand_type_and (i
.types
[2],
6523 switch (t
->operands
)
6526 if (!operand_type_match (overlap4
, i
.types
[4])
6527 || !operand_type_register_match (i
.types
[3],
6534 if (!operand_type_match (overlap3
, i
.types
[3])
6535 || ((check_register
& 0xa) == 0xa
6536 && !operand_type_register_match (i
.types
[1],
6540 || ((check_register
& 0xc) == 0xc
6541 && !operand_type_register_match (i
.types
[2],
6548 /* Here we make use of the fact that there are no
6549 reverse match 3 operand instructions. */
6550 if (!operand_type_match (overlap2
, i
.types
[2])
6551 || ((check_register
& 5) == 5
6552 && !operand_type_register_match (i
.types
[0],
6556 || ((check_register
& 6) == 6
6557 && !operand_type_register_match (i
.types
[1],
6565 /* Found either forward/reverse 2, 3 or 4 operand match here:
6566 slip through to break. */
6569 /* Check if vector operands are valid. */
6570 if (check_VecOperands (t
))
6572 specific_error
= i
.error
;
6576 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6577 if (VEX_check_encoding (t
))
6579 specific_error
= i
.error
;
6583 /* We've found a match; break out of loop. */
6587 if (t
== current_templates
->end
)
6589 /* We found no match. */
6590 const char *err_msg
;
6591 switch (specific_error
? specific_error
: i
.error
)
6595 case operand_size_mismatch
:
6596 err_msg
= _("operand size mismatch");
6598 case operand_type_mismatch
:
6599 err_msg
= _("operand type mismatch");
6601 case register_type_mismatch
:
6602 err_msg
= _("register type mismatch");
6604 case number_of_operands_mismatch
:
6605 err_msg
= _("number of operands mismatch");
6607 case invalid_instruction_suffix
:
6608 err_msg
= _("invalid instruction suffix");
6611 err_msg
= _("constant doesn't fit in 4 bits");
6613 case unsupported_with_intel_mnemonic
:
6614 err_msg
= _("unsupported with Intel mnemonic");
6616 case unsupported_syntax
:
6617 err_msg
= _("unsupported syntax");
6620 as_bad (_("unsupported instruction `%s'"),
6621 current_templates
->start
->name
);
6623 case invalid_sib_address
:
6624 err_msg
= _("invalid SIB address");
6626 case invalid_vsib_address
:
6627 err_msg
= _("invalid VSIB address");
6629 case invalid_vector_register_set
:
6630 err_msg
= _("mask, index, and destination registers must be distinct");
6632 case invalid_tmm_register_set
:
6633 err_msg
= _("all tmm registers must be distinct");
6635 case unsupported_vector_index_register
:
6636 err_msg
= _("unsupported vector index register");
6638 case unsupported_broadcast
:
6639 err_msg
= _("unsupported broadcast");
6641 case broadcast_needed
:
6642 err_msg
= _("broadcast is needed for operand of such type");
6644 case unsupported_masking
:
6645 err_msg
= _("unsupported masking");
6647 case mask_not_on_destination
:
6648 err_msg
= _("mask not on destination operand");
6650 case no_default_mask
:
6651 err_msg
= _("default mask isn't allowed");
6653 case unsupported_rc_sae
:
6654 err_msg
= _("unsupported static rounding/sae");
6656 case rc_sae_operand_not_last_imm
:
6658 err_msg
= _("RC/SAE operand must precede immediate operands");
6660 err_msg
= _("RC/SAE operand must follow immediate operands");
6662 case invalid_register_operand
:
6663 err_msg
= _("invalid register operand");
6666 as_bad (_("%s for `%s'"), err_msg
,
6667 current_templates
->start
->name
);
6671 if (!quiet_warnings
)
6674 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6675 as_warn (_("indirect %s without `*'"), t
->name
);
6677 if (t
->opcode_modifier
.isprefix
6678 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6680 /* Warn them that a data or address size prefix doesn't
6681 affect assembly of the next line of code. */
6682 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6686 /* Copy the template we found. */
6687 install_template (t
);
6689 if (addr_prefix_disp
!= -1)
6690 i
.tm
.operand_types
[addr_prefix_disp
]
6691 = operand_types
[addr_prefix_disp
];
6693 if (found_reverse_match
)
6695 /* If we found a reverse match we must alter the opcode direction
6696 bit and clear/flip the regmem modifier one. found_reverse_match
6697 holds bits to change (different for int & float insns). */
6699 i
.tm
.base_opcode
^= found_reverse_match
;
6701 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6702 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6704 /* Certain SIMD insns have their load forms specified in the opcode
6705 table, and hence we need to _set_ RegMem instead of clearing it.
6706 We need to avoid setting the bit though on insns like KMOVW. */
6707 i
.tm
.opcode_modifier
.regmem
6708 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6709 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6710 && !i
.tm
.opcode_modifier
.regmem
;
6719 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6720 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6722 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6724 as_bad (_("`%s' operand %u must use `%ses' segment"),
6726 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6731 /* There's only ever one segment override allowed per instruction.
6732 This instruction possibly has a legal segment override on the
6733 second operand, so copy the segment to where non-string
6734 instructions store it, allowing common code. */
6735 i
.seg
[op
] = i
.seg
[1];
6741 process_suffix (void)
6743 bfd_boolean is_crc32
= FALSE
;
6745 /* If matched instruction specifies an explicit instruction mnemonic
6747 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6748 i
.suffix
= WORD_MNEM_SUFFIX
;
6749 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6750 i
.suffix
= LONG_MNEM_SUFFIX
;
6751 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6752 i
.suffix
= QWORD_MNEM_SUFFIX
;
6753 else if (i
.reg_operands
6754 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6755 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6757 unsigned int numop
= i
.operands
;
6759 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6760 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6762 /* movsx/movzx want only their source operand considered here, for the
6763 ambiguity checking below. The suffix will be replaced afterwards
6764 to represent the destination (register). */
6765 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6766 || (i
.tm
.base_opcode
== 0x63
6767 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6768 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6771 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6772 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6775 /* If there's no instruction mnemonic suffix we try to invent one
6776 based on GPR operands. */
6779 /* We take i.suffix from the last register operand specified,
6780 Destination register type is more significant than source
6781 register type. crc32 in SSE4.2 prefers source register
6783 unsigned int op
= is_crc32
? 1 : i
.operands
;
6786 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6787 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6789 if (i
.types
[op
].bitfield
.class != Reg
)
6791 if (i
.types
[op
].bitfield
.byte
)
6792 i
.suffix
= BYTE_MNEM_SUFFIX
;
6793 else if (i
.types
[op
].bitfield
.word
)
6794 i
.suffix
= WORD_MNEM_SUFFIX
;
6795 else if (i
.types
[op
].bitfield
.dword
)
6796 i
.suffix
= LONG_MNEM_SUFFIX
;
6797 else if (i
.types
[op
].bitfield
.qword
)
6798 i
.suffix
= QWORD_MNEM_SUFFIX
;
6804 /* As an exception, movsx/movzx silently default to a byte source
6806 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6807 && !i
.suffix
&& !intel_syntax
)
6808 i
.suffix
= BYTE_MNEM_SUFFIX
;
6810 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6813 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6814 && i
.tm
.opcode_modifier
.no_bsuf
)
6816 else if (!check_byte_reg ())
6819 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6822 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6823 && i
.tm
.opcode_modifier
.no_lsuf
6824 && !i
.tm
.opcode_modifier
.todword
6825 && !i
.tm
.opcode_modifier
.toqword
)
6827 else if (!check_long_reg ())
6830 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6833 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6834 && i
.tm
.opcode_modifier
.no_qsuf
6835 && !i
.tm
.opcode_modifier
.todword
6836 && !i
.tm
.opcode_modifier
.toqword
)
6838 else if (!check_qword_reg ())
6841 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6844 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6845 && i
.tm
.opcode_modifier
.no_wsuf
)
6847 else if (!check_word_reg ())
6850 else if (intel_syntax
6851 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6852 /* Do nothing if the instruction is going to ignore the prefix. */
6857 /* Undo the movsx/movzx change done above. */
6860 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6863 i
.suffix
= stackop_size
;
6864 if (stackop_size
== LONG_MNEM_SUFFIX
)
6866 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6867 .code16gcc directive to support 16-bit mode with
6868 32-bit address. For IRET without a suffix, generate
6869 16-bit IRET (opcode 0xcf) to return from an interrupt
6871 if (i
.tm
.base_opcode
== 0xcf)
6873 i
.suffix
= WORD_MNEM_SUFFIX
;
6874 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6876 /* Warn about changed behavior for segment register push/pop. */
6877 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6878 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6883 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6884 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6885 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6886 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6887 && i
.tm
.extension_opcode
<= 3)))
6892 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6894 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6895 || i
.tm
.opcode_modifier
.no_lsuf
)
6896 i
.suffix
= QWORD_MNEM_SUFFIX
;
6901 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6902 i
.suffix
= LONG_MNEM_SUFFIX
;
6905 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6906 i
.suffix
= WORD_MNEM_SUFFIX
;
6912 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6913 /* Also cover lret/retf/iret in 64-bit mode. */
6914 || (flag_code
== CODE_64BIT
6915 && !i
.tm
.opcode_modifier
.no_lsuf
6916 && !i
.tm
.opcode_modifier
.no_qsuf
))
6917 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6918 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6919 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6920 /* Accept FLDENV et al without suffix. */
6921 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6923 unsigned int suffixes
, evex
= 0;
6925 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6926 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6928 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6930 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6932 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6934 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6937 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6938 also suitable for AT&T syntax mode, it was requested that this be
6939 restricted to just Intel syntax. */
6940 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6944 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6946 if (is_evex_encoding (&i
.tm
)
6947 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6949 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6950 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6951 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6952 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6953 if (!i
.tm
.opcode_modifier
.evex
6954 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6955 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6958 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6959 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6960 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6963 /* Any properly sized operand disambiguates the insn. */
6964 if (i
.types
[op
].bitfield
.xmmword
6965 || i
.types
[op
].bitfield
.ymmword
6966 || i
.types
[op
].bitfield
.zmmword
)
6968 suffixes
&= ~(7 << 6);
6973 if ((i
.flags
[op
] & Operand_Mem
)
6974 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6976 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6978 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6980 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6982 if (is_evex_encoding (&i
.tm
))
6988 /* Are multiple suffixes / operand sizes allowed? */
6989 if (suffixes
& (suffixes
- 1))
6992 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6993 || operand_check
== check_error
))
6995 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6998 if (operand_check
== check_error
)
7000 as_bad (_("no instruction mnemonic suffix given and "
7001 "no register operands; can't size `%s'"), i
.tm
.name
);
7004 if (operand_check
== check_warning
)
7005 as_warn (_("%s; using default for `%s'"),
7007 ? _("ambiguous operand size")
7008 : _("no instruction mnemonic suffix given and "
7009 "no register operands"),
7012 if (i
.tm
.opcode_modifier
.floatmf
)
7013 i
.suffix
= SHORT_MNEM_SUFFIX
;
7014 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7015 || (i
.tm
.base_opcode
== 0x63
7016 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7017 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7018 /* handled below */;
7020 i
.tm
.opcode_modifier
.evex
= evex
;
7021 else if (flag_code
== CODE_16BIT
)
7022 i
.suffix
= WORD_MNEM_SUFFIX
;
7023 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7024 i
.suffix
= LONG_MNEM_SUFFIX
;
7026 i
.suffix
= QWORD_MNEM_SUFFIX
;
7030 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7031 || (i
.tm
.base_opcode
== 0x63
7032 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7033 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7035 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7036 In AT&T syntax, if there is no suffix (warned about above), the default
7037 will be byte extension. */
7038 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7039 i
.tm
.base_opcode
|= 1;
7041 /* For further processing, the suffix should represent the destination
7042 (register). This is already the case when one was used with
7043 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7044 no suffix to begin with. */
7045 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7047 if (i
.types
[1].bitfield
.word
)
7048 i
.suffix
= WORD_MNEM_SUFFIX
;
7049 else if (i
.types
[1].bitfield
.qword
)
7050 i
.suffix
= QWORD_MNEM_SUFFIX
;
7052 i
.suffix
= LONG_MNEM_SUFFIX
;
7054 i
.tm
.opcode_modifier
.w
= 0;
7058 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7059 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7060 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7062 /* Change the opcode based on the operand size given by i.suffix. */
7065 /* Size floating point instruction. */
7066 case LONG_MNEM_SUFFIX
:
7067 if (i
.tm
.opcode_modifier
.floatmf
)
7069 i
.tm
.base_opcode
^= 4;
7073 case WORD_MNEM_SUFFIX
:
7074 case QWORD_MNEM_SUFFIX
:
7075 /* It's not a byte, select word/dword operation. */
7076 if (i
.tm
.opcode_modifier
.w
)
7079 i
.tm
.base_opcode
|= 8;
7081 i
.tm
.base_opcode
|= 1;
7084 case SHORT_MNEM_SUFFIX
:
7085 /* Now select between word & dword operations via the operand
7086 size prefix, except for instructions that will ignore this
7088 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7089 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7090 && !i
.tm
.opcode_modifier
.floatmf
7091 && !is_any_vex_encoding (&i
.tm
)
7092 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7093 || (flag_code
== CODE_64BIT
7094 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7096 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7098 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7099 prefix
= ADDR_PREFIX_OPCODE
;
7101 if (!add_prefix (prefix
))
7105 /* Set mode64 for an operand. */
7106 if (i
.suffix
== QWORD_MNEM_SUFFIX
7107 && flag_code
== CODE_64BIT
7108 && !i
.tm
.opcode_modifier
.norex64
7109 && !i
.tm
.opcode_modifier
.vexw
7110 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7112 && ! (i
.operands
== 2
7113 && i
.tm
.base_opcode
== 0x90
7114 && i
.tm
.extension_opcode
== None
7115 && i
.types
[0].bitfield
.instance
== Accum
7116 && i
.types
[0].bitfield
.qword
7117 && i
.types
[1].bitfield
.instance
== Accum
7118 && i
.types
[1].bitfield
.qword
))
7124 /* Select word/dword/qword operation with explicit data sizing prefix
7125 when there are no suitable register operands. */
7126 if (i
.tm
.opcode_modifier
.w
7127 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7129 || (i
.reg_operands
== 1
7131 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7133 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7134 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7137 i
.tm
.base_opcode
|= 1;
7141 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7143 gas_assert (!i
.suffix
);
7144 gas_assert (i
.reg_operands
);
7146 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7149 /* The address size override prefix changes the size of the
7151 if (flag_code
== CODE_64BIT
7152 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7154 as_bad (_("16-bit addressing unavailable for `%s'"),
7159 if ((flag_code
== CODE_32BIT
7160 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7161 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7162 && !add_prefix (ADDR_PREFIX_OPCODE
))
7167 /* Check invalid register operand when the address size override
7168 prefix changes the size of register operands. */
7170 enum { need_word
, need_dword
, need_qword
} need
;
7172 /* Check the register operand for the address size prefix if
7173 the memory operand has no real registers, like symbol, DISP
7174 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7175 if (i
.mem_operands
== 1
7176 && i
.reg_operands
== 1
7178 && i
.types
[1].bitfield
.class == Reg
7179 && (flag_code
== CODE_32BIT
7180 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7181 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7182 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7183 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7184 || (x86_elf_abi
== X86_64_X32_ABI
7186 && i
.base_reg
->reg_num
== RegIP
7187 && i
.base_reg
->reg_type
.bitfield
.qword
))
7191 && !add_prefix (ADDR_PREFIX_OPCODE
))
7194 if (flag_code
== CODE_32BIT
)
7195 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7196 else if (i
.prefix
[ADDR_PREFIX
])
7199 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7201 for (op
= 0; op
< i
.operands
; op
++)
7203 if (i
.types
[op
].bitfield
.class != Reg
)
7209 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7213 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7217 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7222 as_bad (_("invalid register operand size for `%s'"),
7233 check_byte_reg (void)
7237 for (op
= i
.operands
; --op
>= 0;)
7239 /* Skip non-register operands. */
7240 if (i
.types
[op
].bitfield
.class != Reg
)
7243 /* If this is an eight bit register, it's OK. If it's the 16 or
7244 32 bit version of an eight bit register, we will just use the
7245 low portion, and that's OK too. */
7246 if (i
.types
[op
].bitfield
.byte
)
7249 /* I/O port address operands are OK too. */
7250 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7251 && i
.tm
.operand_types
[op
].bitfield
.word
)
7254 /* crc32 only wants its source operand checked here. */
7255 if (i
.tm
.base_opcode
== 0xf38f0
7256 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7260 /* Any other register is bad. */
7261 as_bad (_("`%s%s' not allowed with `%s%c'"),
7262 register_prefix
, i
.op
[op
].regs
->reg_name
,
7263 i
.tm
.name
, i
.suffix
);
7270 check_long_reg (void)
7274 for (op
= i
.operands
; --op
>= 0;)
7275 /* Skip non-register operands. */
7276 if (i
.types
[op
].bitfield
.class != Reg
)
7278 /* Reject eight bit registers, except where the template requires
7279 them. (eg. movzb) */
7280 else if (i
.types
[op
].bitfield
.byte
7281 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7282 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7283 && (i
.tm
.operand_types
[op
].bitfield
.word
7284 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7286 as_bad (_("`%s%s' not allowed with `%s%c'"),
7288 i
.op
[op
].regs
->reg_name
,
7293 /* Error if the e prefix on a general reg is missing. */
7294 else if (i
.types
[op
].bitfield
.word
7295 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7296 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7297 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7299 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7300 register_prefix
, i
.op
[op
].regs
->reg_name
,
7304 /* Warn if the r prefix on a general reg is present. */
7305 else if (i
.types
[op
].bitfield
.qword
7306 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7307 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7308 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7311 && i
.tm
.opcode_modifier
.toqword
7312 && i
.types
[0].bitfield
.class != RegSIMD
)
7314 /* Convert to QWORD. We want REX byte. */
7315 i
.suffix
= QWORD_MNEM_SUFFIX
;
7319 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7320 register_prefix
, i
.op
[op
].regs
->reg_name
,
7329 check_qword_reg (void)
7333 for (op
= i
.operands
; --op
>= 0; )
7334 /* Skip non-register operands. */
7335 if (i
.types
[op
].bitfield
.class != Reg
)
7337 /* Reject eight bit registers, except where the template requires
7338 them. (eg. movzb) */
7339 else if (i
.types
[op
].bitfield
.byte
7340 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7341 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7342 && (i
.tm
.operand_types
[op
].bitfield
.word
7343 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7345 as_bad (_("`%s%s' not allowed with `%s%c'"),
7347 i
.op
[op
].regs
->reg_name
,
7352 /* Warn if the r prefix on a general reg is missing. */
7353 else if ((i
.types
[op
].bitfield
.word
7354 || i
.types
[op
].bitfield
.dword
)
7355 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7356 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7357 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7359 /* Prohibit these changes in the 64bit mode, since the
7360 lowering is more complicated. */
7362 && i
.tm
.opcode_modifier
.todword
7363 && i
.types
[0].bitfield
.class != RegSIMD
)
7365 /* Convert to DWORD. We don't want REX byte. */
7366 i
.suffix
= LONG_MNEM_SUFFIX
;
7370 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7371 register_prefix
, i
.op
[op
].regs
->reg_name
,
7380 check_word_reg (void)
7383 for (op
= i
.operands
; --op
>= 0;)
7384 /* Skip non-register operands. */
7385 if (i
.types
[op
].bitfield
.class != Reg
)
7387 /* Reject eight bit registers, except where the template requires
7388 them. (eg. movzb) */
7389 else if (i
.types
[op
].bitfield
.byte
7390 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7391 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7392 && (i
.tm
.operand_types
[op
].bitfield
.word
7393 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7395 as_bad (_("`%s%s' not allowed with `%s%c'"),
7397 i
.op
[op
].regs
->reg_name
,
7402 /* Error if the e or r prefix on a general reg is present. */
7403 else if ((i
.types
[op
].bitfield
.dword
7404 || i
.types
[op
].bitfield
.qword
)
7405 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7406 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7407 && i
.tm
.operand_types
[op
].bitfield
.word
)
7409 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7410 register_prefix
, i
.op
[op
].regs
->reg_name
,
7418 update_imm (unsigned int j
)
7420 i386_operand_type overlap
= i
.types
[j
];
7421 if ((overlap
.bitfield
.imm8
7422 || overlap
.bitfield
.imm8s
7423 || overlap
.bitfield
.imm16
7424 || overlap
.bitfield
.imm32
7425 || overlap
.bitfield
.imm32s
7426 || overlap
.bitfield
.imm64
)
7427 && !operand_type_equal (&overlap
, &imm8
)
7428 && !operand_type_equal (&overlap
, &imm8s
)
7429 && !operand_type_equal (&overlap
, &imm16
)
7430 && !operand_type_equal (&overlap
, &imm32
)
7431 && !operand_type_equal (&overlap
, &imm32s
)
7432 && !operand_type_equal (&overlap
, &imm64
))
7436 i386_operand_type temp
;
7438 operand_type_set (&temp
, 0);
7439 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7441 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7442 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7444 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7445 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7446 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7448 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7449 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7452 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7455 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7456 || operand_type_equal (&overlap
, &imm16_32
)
7457 || operand_type_equal (&overlap
, &imm16_32s
))
7459 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7464 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7465 overlap
= operand_type_and (overlap
, imm32s
);
7466 else if (i
.prefix
[DATA_PREFIX
])
7467 overlap
= operand_type_and (overlap
,
7468 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7469 if (!operand_type_equal (&overlap
, &imm8
)
7470 && !operand_type_equal (&overlap
, &imm8s
)
7471 && !operand_type_equal (&overlap
, &imm16
)
7472 && !operand_type_equal (&overlap
, &imm32
)
7473 && !operand_type_equal (&overlap
, &imm32s
)
7474 && !operand_type_equal (&overlap
, &imm64
))
7476 as_bad (_("no instruction mnemonic suffix given; "
7477 "can't determine immediate size"));
7481 i
.types
[j
] = overlap
;
7491 /* Update the first 2 immediate operands. */
7492 n
= i
.operands
> 2 ? 2 : i
.operands
;
7495 for (j
= 0; j
< n
; j
++)
7496 if (update_imm (j
) == 0)
7499 /* The 3rd operand can't be immediate operand. */
7500 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7507 process_operands (void)
7509 /* Default segment register this instruction will use for memory
7510 accesses. 0 means unknown. This is only for optimizing out
7511 unnecessary segment overrides. */
7512 const seg_entry
*default_seg
= 0;
7514 if (i
.tm
.opcode_modifier
.sse2avx
)
7516 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7518 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7519 i
.prefix
[REX_PREFIX
] = 0;
7522 /* ImmExt should be processed after SSE2AVX. */
7523 else if (i
.tm
.opcode_modifier
.immext
)
7526 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7528 unsigned int dupl
= i
.operands
;
7529 unsigned int dest
= dupl
- 1;
7532 /* The destination must be an xmm register. */
7533 gas_assert (i
.reg_operands
7534 && MAX_OPERANDS
> dupl
7535 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7537 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7538 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7540 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7542 /* Keep xmm0 for instructions with VEX prefix and 3
7544 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7545 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7550 /* We remove the first xmm0 and keep the number of
7551 operands unchanged, which in fact duplicates the
7553 for (j
= 1; j
< i
.operands
; j
++)
7555 i
.op
[j
- 1] = i
.op
[j
];
7556 i
.types
[j
- 1] = i
.types
[j
];
7557 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7558 i
.flags
[j
- 1] = i
.flags
[j
];
7562 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7564 gas_assert ((MAX_OPERANDS
- 1) > dupl
7565 && (i
.tm
.opcode_modifier
.vexsources
7568 /* Add the implicit xmm0 for instructions with VEX prefix
7570 for (j
= i
.operands
; j
> 0; j
--)
7572 i
.op
[j
] = i
.op
[j
- 1];
7573 i
.types
[j
] = i
.types
[j
- 1];
7574 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7575 i
.flags
[j
] = i
.flags
[j
- 1];
7578 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7579 i
.types
[0] = regxmm
;
7580 i
.tm
.operand_types
[0] = regxmm
;
7583 i
.reg_operands
+= 2;
7588 i
.op
[dupl
] = i
.op
[dest
];
7589 i
.types
[dupl
] = i
.types
[dest
];
7590 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7591 i
.flags
[dupl
] = i
.flags
[dest
];
7600 i
.op
[dupl
] = i
.op
[dest
];
7601 i
.types
[dupl
] = i
.types
[dest
];
7602 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7603 i
.flags
[dupl
] = i
.flags
[dest
];
7606 if (i
.tm
.opcode_modifier
.immext
)
7609 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7610 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7614 for (j
= 1; j
< i
.operands
; j
++)
7616 i
.op
[j
- 1] = i
.op
[j
];
7617 i
.types
[j
- 1] = i
.types
[j
];
7619 /* We need to adjust fields in i.tm since they are used by
7620 build_modrm_byte. */
7621 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7623 i
.flags
[j
- 1] = i
.flags
[j
];
7630 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7632 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7634 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7635 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7636 regnum
= register_number (i
.op
[1].regs
);
7637 first_reg_in_group
= regnum
& ~3;
7638 last_reg_in_group
= first_reg_in_group
+ 3;
7639 if (regnum
!= first_reg_in_group
)
7640 as_warn (_("source register `%s%s' implicitly denotes"
7641 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7642 register_prefix
, i
.op
[1].regs
->reg_name
,
7643 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7644 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7647 else if (i
.tm
.opcode_modifier
.regkludge
)
7649 /* The imul $imm, %reg instruction is converted into
7650 imul $imm, %reg, %reg, and the clr %reg instruction
7651 is converted into xor %reg, %reg. */
7653 unsigned int first_reg_op
;
7655 if (operand_type_check (i
.types
[0], reg
))
7659 /* Pretend we saw the extra register operand. */
7660 gas_assert (i
.reg_operands
== 1
7661 && i
.op
[first_reg_op
+ 1].regs
== 0);
7662 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7663 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7668 if (i
.tm
.opcode_modifier
.modrm
)
7670 /* The opcode is completed (modulo i.tm.extension_opcode which
7671 must be put into the modrm byte). Now, we make the modrm and
7672 index base bytes based on all the info we've collected. */
7674 default_seg
= build_modrm_byte ();
7676 else if (i
.types
[0].bitfield
.class == SReg
)
7678 if (flag_code
!= CODE_64BIT
7679 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7680 && i
.op
[0].regs
->reg_num
== 1
7681 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7682 && i
.op
[0].regs
->reg_num
< 4)
7684 as_bad (_("you can't `%s %s%s'"),
7685 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7688 if ( i
.op
[0].regs
->reg_num
> 3 && i
.opcode_length
== 1 )
7690 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7691 i
.opcode_length
= 2;
7693 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7695 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7699 else if (i
.tm
.opcode_modifier
.isstring
)
7701 /* For the string instructions that allow a segment override
7702 on one of their operands, the default segment is ds. */
7705 else if (i
.short_form
)
7707 /* The register or float register operand is in operand
7709 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7711 /* Register goes in low 3 bits of opcode. */
7712 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7713 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7715 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7717 /* Warn about some common errors, but press on regardless.
7718 The first case can be generated by gcc (<= 2.8.1). */
7719 if (i
.operands
== 2)
7721 /* Reversed arguments on faddp, fsubp, etc. */
7722 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7723 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7724 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7728 /* Extraneous `l' suffix on fp insn. */
7729 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7730 register_prefix
, i
.op
[0].regs
->reg_name
);
7735 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7736 && i
.tm
.base_opcode
== 0x8d /* lea */
7737 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7738 && !is_any_vex_encoding(&i
.tm
))
7740 if (!quiet_warnings
)
7741 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7745 i
.prefix
[SEG_PREFIX
] = 0;
7749 /* If a segment was explicitly specified, and the specified segment
7750 is neither the default nor the one already recorded from a prefix,
7751 use an opcode prefix to select it. If we never figured out what
7752 the default segment is, then default_seg will be zero at this
7753 point, and the specified segment prefix will always be used. */
7755 && i
.seg
[0] != default_seg
7756 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7758 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7764 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7765 bfd_boolean do_sse2avx
)
7767 if (r
->reg_flags
& RegRex
)
7769 if (i
.rex
& rex_bit
)
7770 as_bad (_("same type of prefix used twice"));
7773 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7775 gas_assert (i
.vex
.register_specifier
== r
);
7776 i
.vex
.register_specifier
+= 8;
7779 if (r
->reg_flags
& RegVRex
)
7783 static const seg_entry
*
7784 build_modrm_byte (void)
7786 const seg_entry
*default_seg
= 0;
7787 unsigned int source
, dest
;
7790 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7793 unsigned int nds
, reg_slot
;
7796 dest
= i
.operands
- 1;
7799 /* There are 2 kinds of instructions:
7800 1. 5 operands: 4 register operands or 3 register operands
7801 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7802 VexW0 or VexW1. The destination must be either XMM, YMM or
7804 2. 4 operands: 4 register operands or 3 register operands
7805 plus 1 memory operand, with VexXDS. */
7806 gas_assert ((i
.reg_operands
== 4
7807 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7808 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7809 && i
.tm
.opcode_modifier
.vexw
7810 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7812 /* If VexW1 is set, the first non-immediate operand is the source and
7813 the second non-immediate one is encoded in the immediate operand. */
7814 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7816 source
= i
.imm_operands
;
7817 reg_slot
= i
.imm_operands
+ 1;
7821 source
= i
.imm_operands
+ 1;
7822 reg_slot
= i
.imm_operands
;
7825 if (i
.imm_operands
== 0)
7827 /* When there is no immediate operand, generate an 8bit
7828 immediate operand to encode the first operand. */
7829 exp
= &im_expressions
[i
.imm_operands
++];
7830 i
.op
[i
.operands
].imms
= exp
;
7831 i
.types
[i
.operands
] = imm8
;
7834 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7835 exp
->X_op
= O_constant
;
7836 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7837 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7841 gas_assert (i
.imm_operands
== 1);
7842 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7843 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7845 /* Turn on Imm8 again so that output_imm will generate it. */
7846 i
.types
[0].bitfield
.imm8
= 1;
7848 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7849 i
.op
[0].imms
->X_add_number
7850 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7851 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7854 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7855 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7860 /* i.reg_operands MUST be the number of real register operands;
7861 implicit registers do not count. If there are 3 register
7862 operands, it must be a instruction with VexNDS. For a
7863 instruction with VexNDD, the destination register is encoded
7864 in VEX prefix. If there are 4 register operands, it must be
7865 a instruction with VEX prefix and 3 sources. */
7866 if (i
.mem_operands
== 0
7867 && ((i
.reg_operands
== 2
7868 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7869 || (i
.reg_operands
== 3
7870 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7871 || (i
.reg_operands
== 4 && vex_3_sources
)))
7879 /* When there are 3 operands, one of them may be immediate,
7880 which may be the first or the last operand. Otherwise,
7881 the first operand must be shift count register (cl) or it
7882 is an instruction with VexNDS. */
7883 gas_assert (i
.imm_operands
== 1
7884 || (i
.imm_operands
== 0
7885 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7886 || (i
.types
[0].bitfield
.instance
== RegC
7887 && i
.types
[0].bitfield
.byte
))));
7888 if (operand_type_check (i
.types
[0], imm
)
7889 || (i
.types
[0].bitfield
.instance
== RegC
7890 && i
.types
[0].bitfield
.byte
))
7896 /* When there are 4 operands, the first two must be 8bit
7897 immediate operands. The source operand will be the 3rd
7900 For instructions with VexNDS, if the first operand
7901 an imm8, the source operand is the 2nd one. If the last
7902 operand is imm8, the source operand is the first one. */
7903 gas_assert ((i
.imm_operands
== 2
7904 && i
.types
[0].bitfield
.imm8
7905 && i
.types
[1].bitfield
.imm8
)
7906 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7907 && i
.imm_operands
== 1
7908 && (i
.types
[0].bitfield
.imm8
7909 || i
.types
[i
.operands
- 1].bitfield
.imm8
7911 if (i
.imm_operands
== 2)
7915 if (i
.types
[0].bitfield
.imm8
)
7922 if (is_evex_encoding (&i
.tm
))
7924 /* For EVEX instructions, when there are 5 operands, the
7925 first one must be immediate operand. If the second one
7926 is immediate operand, the source operand is the 3th
7927 one. If the last one is immediate operand, the source
7928 operand is the 2nd one. */
7929 gas_assert (i
.imm_operands
== 2
7930 && i
.tm
.opcode_modifier
.sae
7931 && operand_type_check (i
.types
[0], imm
));
7932 if (operand_type_check (i
.types
[1], imm
))
7934 else if (operand_type_check (i
.types
[4], imm
))
7948 /* RC/SAE operand could be between DEST and SRC. That happens
7949 when one operand is GPR and the other one is XMM/YMM/ZMM
7951 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7954 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7956 /* For instructions with VexNDS, the register-only source
7957 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7958 register. It is encoded in VEX prefix. */
7960 i386_operand_type op
;
7963 /* Swap two source operands if needed. */
7964 if (i
.tm
.opcode_modifier
.swapsources
)
7972 op
= i
.tm
.operand_types
[vvvv
];
7973 if ((dest
+ 1) >= i
.operands
7974 || ((op
.bitfield
.class != Reg
7975 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7976 && op
.bitfield
.class != RegSIMD
7977 && !operand_type_equal (&op
, ®mask
)))
7979 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7985 /* One of the register operands will be encoded in the i.rm.reg
7986 field, the other in the combined i.rm.mode and i.rm.regmem
7987 fields. If no form of this instruction supports a memory
7988 destination operand, then we assume the source operand may
7989 sometimes be a memory operand and so we need to store the
7990 destination in the i.rm.reg field. */
7991 if (!i
.tm
.opcode_modifier
.regmem
7992 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7994 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7995 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7996 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7997 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8001 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8002 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8003 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8004 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8006 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8008 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8011 add_prefix (LOCK_PREFIX_OPCODE
);
8015 { /* If it's not 2 reg operands... */
8020 unsigned int fake_zero_displacement
= 0;
8023 for (op
= 0; op
< i
.operands
; op
++)
8024 if (i
.flags
[op
] & Operand_Mem
)
8026 gas_assert (op
< i
.operands
);
8028 if (i
.tm
.opcode_modifier
.sib
)
8030 /* The index register of VSIB shouldn't be RegIZ. */
8031 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8032 && i
.index_reg
->reg_num
== RegIZ
)
8035 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8038 i
.sib
.base
= NO_BASE_REGISTER
;
8039 i
.sib
.scale
= i
.log2_scale_factor
;
8040 i
.types
[op
].bitfield
.disp8
= 0;
8041 i
.types
[op
].bitfield
.disp16
= 0;
8042 i
.types
[op
].bitfield
.disp64
= 0;
8043 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8045 /* Must be 32 bit */
8046 i
.types
[op
].bitfield
.disp32
= 1;
8047 i
.types
[op
].bitfield
.disp32s
= 0;
8051 i
.types
[op
].bitfield
.disp32
= 0;
8052 i
.types
[op
].bitfield
.disp32s
= 1;
8056 /* Since the mandatory SIB always has index register, so
8057 the code logic remains unchanged. The non-mandatory SIB
8058 without index register is allowed and will be handled
8062 if (i
.index_reg
->reg_num
== RegIZ
)
8063 i
.sib
.index
= NO_INDEX_REGISTER
;
8065 i
.sib
.index
= i
.index_reg
->reg_num
;
8066 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8072 if (i
.base_reg
== 0)
8075 if (!i
.disp_operands
)
8076 fake_zero_displacement
= 1;
8077 if (i
.index_reg
== 0)
8079 i386_operand_type newdisp
;
8081 /* Both check for VSIB and mandatory non-vector SIB. */
8082 gas_assert (!i
.tm
.opcode_modifier
.sib
8083 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8084 /* Operand is just <disp> */
8085 if (flag_code
== CODE_64BIT
)
8087 /* 64bit mode overwrites the 32bit absolute
8088 addressing by RIP relative addressing and
8089 absolute addressing is encoded by one of the
8090 redundant SIB forms. */
8091 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8092 i
.sib
.base
= NO_BASE_REGISTER
;
8093 i
.sib
.index
= NO_INDEX_REGISTER
;
8094 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8096 else if ((flag_code
== CODE_16BIT
)
8097 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8099 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8104 i
.rm
.regmem
= NO_BASE_REGISTER
;
8107 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8108 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8110 else if (!i
.tm
.opcode_modifier
.sib
)
8112 /* !i.base_reg && i.index_reg */
8113 if (i
.index_reg
->reg_num
== RegIZ
)
8114 i
.sib
.index
= NO_INDEX_REGISTER
;
8116 i
.sib
.index
= i
.index_reg
->reg_num
;
8117 i
.sib
.base
= NO_BASE_REGISTER
;
8118 i
.sib
.scale
= i
.log2_scale_factor
;
8119 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8120 i
.types
[op
].bitfield
.disp8
= 0;
8121 i
.types
[op
].bitfield
.disp16
= 0;
8122 i
.types
[op
].bitfield
.disp64
= 0;
8123 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8125 /* Must be 32 bit */
8126 i
.types
[op
].bitfield
.disp32
= 1;
8127 i
.types
[op
].bitfield
.disp32s
= 0;
8131 i
.types
[op
].bitfield
.disp32
= 0;
8132 i
.types
[op
].bitfield
.disp32s
= 1;
8134 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8138 /* RIP addressing for 64bit mode. */
8139 else if (i
.base_reg
->reg_num
== RegIP
)
8141 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8142 i
.rm
.regmem
= NO_BASE_REGISTER
;
8143 i
.types
[op
].bitfield
.disp8
= 0;
8144 i
.types
[op
].bitfield
.disp16
= 0;
8145 i
.types
[op
].bitfield
.disp32
= 0;
8146 i
.types
[op
].bitfield
.disp32s
= 1;
8147 i
.types
[op
].bitfield
.disp64
= 0;
8148 i
.flags
[op
] |= Operand_PCrel
;
8149 if (! i
.disp_operands
)
8150 fake_zero_displacement
= 1;
8152 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8154 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8155 switch (i
.base_reg
->reg_num
)
8158 if (i
.index_reg
== 0)
8160 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8161 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8165 if (i
.index_reg
== 0)
8168 if (operand_type_check (i
.types
[op
], disp
) == 0)
8170 /* fake (%bp) into 0(%bp) */
8171 if (i
.disp_encoding
== disp_encoding_16bit
)
8172 i
.types
[op
].bitfield
.disp16
= 1;
8174 i
.types
[op
].bitfield
.disp8
= 1;
8175 fake_zero_displacement
= 1;
8178 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8179 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8181 default: /* (%si) -> 4 or (%di) -> 5 */
8182 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8184 if (!fake_zero_displacement
8188 fake_zero_displacement
= 1;
8189 if (i
.disp_encoding
== disp_encoding_8bit
)
8190 i
.types
[op
].bitfield
.disp8
= 1;
8192 i
.types
[op
].bitfield
.disp16
= 1;
8194 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8196 else /* i.base_reg and 32/64 bit mode */
8198 if (flag_code
== CODE_64BIT
8199 && operand_type_check (i
.types
[op
], disp
))
8201 i
.types
[op
].bitfield
.disp16
= 0;
8202 i
.types
[op
].bitfield
.disp64
= 0;
8203 if (i
.prefix
[ADDR_PREFIX
] == 0)
8205 i
.types
[op
].bitfield
.disp32
= 0;
8206 i
.types
[op
].bitfield
.disp32s
= 1;
8210 i
.types
[op
].bitfield
.disp32
= 1;
8211 i
.types
[op
].bitfield
.disp32s
= 0;
8215 if (!i
.tm
.opcode_modifier
.sib
)
8216 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8217 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8219 i
.sib
.base
= i
.base_reg
->reg_num
;
8220 /* x86-64 ignores REX prefix bit here to avoid decoder
8222 if (!(i
.base_reg
->reg_flags
& RegRex
)
8223 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8224 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8226 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8228 fake_zero_displacement
= 1;
8229 if (i
.disp_encoding
== disp_encoding_32bit
)
8230 i
.types
[op
].bitfield
.disp32
= 1;
8232 i
.types
[op
].bitfield
.disp8
= 1;
8234 i
.sib
.scale
= i
.log2_scale_factor
;
8235 if (i
.index_reg
== 0)
8237 /* Only check for VSIB. */
8238 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8239 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8240 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8242 /* <disp>(%esp) becomes two byte modrm with no index
8243 register. We've already stored the code for esp
8244 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8245 Any base register besides %esp will not use the
8246 extra modrm byte. */
8247 i
.sib
.index
= NO_INDEX_REGISTER
;
8249 else if (!i
.tm
.opcode_modifier
.sib
)
8251 if (i
.index_reg
->reg_num
== RegIZ
)
8252 i
.sib
.index
= NO_INDEX_REGISTER
;
8254 i
.sib
.index
= i
.index_reg
->reg_num
;
8255 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8256 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8261 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8262 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8266 if (!fake_zero_displacement
8270 fake_zero_displacement
= 1;
8271 if (i
.disp_encoding
== disp_encoding_8bit
)
8272 i
.types
[op
].bitfield
.disp8
= 1;
8274 i
.types
[op
].bitfield
.disp32
= 1;
8276 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8280 if (fake_zero_displacement
)
8282 /* Fakes a zero displacement assuming that i.types[op]
8283 holds the correct displacement size. */
8286 gas_assert (i
.op
[op
].disps
== 0);
8287 exp
= &disp_expressions
[i
.disp_operands
++];
8288 i
.op
[op
].disps
= exp
;
8289 exp
->X_op
= O_constant
;
8290 exp
->X_add_number
= 0;
8291 exp
->X_add_symbol
= (symbolS
*) 0;
8292 exp
->X_op_symbol
= (symbolS
*) 0;
8300 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8302 if (operand_type_check (i
.types
[0], imm
))
8303 i
.vex
.register_specifier
= NULL
;
8306 /* VEX.vvvv encodes one of the sources when the first
8307 operand is not an immediate. */
8308 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8309 i
.vex
.register_specifier
= i
.op
[0].regs
;
8311 i
.vex
.register_specifier
= i
.op
[1].regs
;
8314 /* Destination is a XMM register encoded in the ModRM.reg
8316 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8317 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8320 /* ModRM.rm and VEX.B encodes the other source. */
8321 if (!i
.mem_operands
)
8325 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8326 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8328 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8330 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8334 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8336 i
.vex
.register_specifier
= i
.op
[2].regs
;
8337 if (!i
.mem_operands
)
8340 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8341 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8345 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8346 (if any) based on i.tm.extension_opcode. Again, we must be
8347 careful to make sure that segment/control/debug/test/MMX
8348 registers are coded into the i.rm.reg field. */
8349 else if (i
.reg_operands
)
8352 unsigned int vex_reg
= ~0;
8354 for (op
= 0; op
< i
.operands
; op
++)
8355 if (i
.types
[op
].bitfield
.class == Reg
8356 || i
.types
[op
].bitfield
.class == RegBND
8357 || i
.types
[op
].bitfield
.class == RegMask
8358 || i
.types
[op
].bitfield
.class == SReg
8359 || i
.types
[op
].bitfield
.class == RegCR
8360 || i
.types
[op
].bitfield
.class == RegDR
8361 || i
.types
[op
].bitfield
.class == RegTR
8362 || i
.types
[op
].bitfield
.class == RegSIMD
8363 || i
.types
[op
].bitfield
.class == RegMMX
)
8368 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8370 /* For instructions with VexNDS, the register-only
8371 source operand is encoded in VEX prefix. */
8372 gas_assert (mem
!= (unsigned int) ~0);
8377 gas_assert (op
< i
.operands
);
8381 /* Check register-only source operand when two source
8382 operands are swapped. */
8383 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8384 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8388 gas_assert (mem
== (vex_reg
+ 1)
8389 && op
< i
.operands
);
8394 gas_assert (vex_reg
< i
.operands
);
8398 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8400 /* For instructions with VexNDD, the register destination
8401 is encoded in VEX prefix. */
8402 if (i
.mem_operands
== 0)
8404 /* There is no memory operand. */
8405 gas_assert ((op
+ 2) == i
.operands
);
8410 /* There are only 2 non-immediate operands. */
8411 gas_assert (op
< i
.imm_operands
+ 2
8412 && i
.operands
== i
.imm_operands
+ 2);
8413 vex_reg
= i
.imm_operands
+ 1;
8417 gas_assert (op
< i
.operands
);
8419 if (vex_reg
!= (unsigned int) ~0)
8421 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8423 if ((type
->bitfield
.class != Reg
8424 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8425 && type
->bitfield
.class != RegSIMD
8426 && !operand_type_equal (type
, ®mask
))
8429 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8432 /* Don't set OP operand twice. */
8435 /* If there is an extension opcode to put here, the
8436 register number must be put into the regmem field. */
8437 if (i
.tm
.extension_opcode
!= None
)
8439 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8440 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8441 i
.tm
.opcode_modifier
.sse2avx
);
8445 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8446 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8447 i
.tm
.opcode_modifier
.sse2avx
);
8451 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8452 must set it to 3 to indicate this is a register operand
8453 in the regmem field. */
8454 if (!i
.mem_operands
)
8458 /* Fill in i.rm.reg field with extension opcode (if any). */
8459 if (i
.tm
.extension_opcode
!= None
)
8460 i
.rm
.reg
= i
.tm
.extension_opcode
;
8466 frag_opcode_byte (unsigned char byte
)
8468 if (now_seg
!= absolute_section
)
8469 FRAG_APPEND_1_CHAR (byte
);
8471 ++abs_section_offset
;
8475 flip_code16 (unsigned int code16
)
8477 gas_assert (i
.tm
.operands
== 1);
8479 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8480 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8481 || i
.tm
.operand_types
[0].bitfield
.disp32s
8482 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8487 output_branch (void)
8493 relax_substateT subtype
;
8497 if (now_seg
== absolute_section
)
8499 as_bad (_("relaxable branches not supported in absolute section"));
8503 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8504 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8507 if (i
.prefix
[DATA_PREFIX
] != 0)
8511 code16
^= flip_code16(code16
);
8513 /* Pentium4 branch hints. */
8514 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8515 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8520 if (i
.prefix
[REX_PREFIX
] != 0)
8526 /* BND prefixed jump. */
8527 if (i
.prefix
[BND_PREFIX
] != 0)
8533 if (i
.prefixes
!= 0)
8534 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8536 /* It's always a symbol; End frag & setup for relax.
8537 Make sure there is enough room in this frag for the largest
8538 instruction we may generate in md_convert_frag. This is 2
8539 bytes for the opcode and room for the prefix and largest
8541 frag_grow (prefix
+ 2 + 4);
8542 /* Prefix and 1 opcode byte go in fr_fix. */
8543 p
= frag_more (prefix
+ 1);
8544 if (i
.prefix
[DATA_PREFIX
] != 0)
8545 *p
++ = DATA_PREFIX_OPCODE
;
8546 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8547 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8548 *p
++ = i
.prefix
[SEG_PREFIX
];
8549 if (i
.prefix
[BND_PREFIX
] != 0)
8550 *p
++ = BND_PREFIX_OPCODE
;
8551 if (i
.prefix
[REX_PREFIX
] != 0)
8552 *p
++ = i
.prefix
[REX_PREFIX
];
8553 *p
= i
.tm
.base_opcode
;
8555 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8556 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8557 else if (cpu_arch_flags
.bitfield
.cpui386
)
8558 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8560 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8563 sym
= i
.op
[0].disps
->X_add_symbol
;
8564 off
= i
.op
[0].disps
->X_add_number
;
8566 if (i
.op
[0].disps
->X_op
!= O_constant
8567 && i
.op
[0].disps
->X_op
!= O_symbol
)
8569 /* Handle complex expressions. */
8570 sym
= make_expr_symbol (i
.op
[0].disps
);
8574 /* 1 possible extra opcode + 4 byte displacement go in var part.
8575 Pass reloc in fr_var. */
8576 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8579 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8580 /* Return TRUE iff PLT32 relocation should be used for branching to
8584 need_plt32_p (symbolS
*s
)
8586 /* PLT32 relocation is ELF only. */
8591 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8592 krtld support it. */
8596 /* Since there is no need to prepare for PLT branch on x86-64, we
8597 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8598 be used as a marker for 32-bit PC-relative branches. */
8605 /* Weak or undefined symbol need PLT32 relocation. */
8606 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8609 /* Non-global symbol doesn't need PLT32 relocation. */
8610 if (! S_IS_EXTERNAL (s
))
8613 /* Other global symbols need PLT32 relocation. NB: Symbol with
8614 non-default visibilities are treated as normal global symbol
8615 so that PLT32 relocation can be used as a marker for 32-bit
8616 PC-relative branches. It is useful for linker relaxation. */
8627 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8629 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8631 /* This is a loop or jecxz type instruction. */
8633 if (i
.prefix
[ADDR_PREFIX
] != 0)
8635 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8638 /* Pentium4 branch hints. */
8639 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8640 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8642 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8651 if (flag_code
== CODE_16BIT
)
8654 if (i
.prefix
[DATA_PREFIX
] != 0)
8656 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8658 code16
^= flip_code16(code16
);
8666 /* BND prefixed jump. */
8667 if (i
.prefix
[BND_PREFIX
] != 0)
8669 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8673 if (i
.prefix
[REX_PREFIX
] != 0)
8675 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8679 if (i
.prefixes
!= 0)
8680 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8682 if (now_seg
== absolute_section
)
8684 abs_section_offset
+= i
.opcode_length
+ size
;
8688 p
= frag_more (i
.opcode_length
+ size
);
8689 switch (i
.opcode_length
)
8692 *p
++ = i
.tm
.base_opcode
>> 8;
8695 *p
++ = i
.tm
.base_opcode
;
8701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8703 && jump_reloc
== NO_RELOC
8704 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8705 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8708 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8710 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8711 i
.op
[0].disps
, 1, jump_reloc
);
8713 /* All jumps handled here are signed, but don't use a signed limit
8714 check for 32 and 16 bit jumps as we want to allow wrap around at
8715 4G and 64k respectively. */
8717 fixP
->fx_signed
= 1;
8721 output_interseg_jump (void)
8729 if (flag_code
== CODE_16BIT
)
8733 if (i
.prefix
[DATA_PREFIX
] != 0)
8740 gas_assert (!i
.prefix
[REX_PREFIX
]);
8746 if (i
.prefixes
!= 0)
8747 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8749 if (now_seg
== absolute_section
)
8751 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8755 /* 1 opcode; 2 segment; offset */
8756 p
= frag_more (prefix
+ 1 + 2 + size
);
8758 if (i
.prefix
[DATA_PREFIX
] != 0)
8759 *p
++ = DATA_PREFIX_OPCODE
;
8761 if (i
.prefix
[REX_PREFIX
] != 0)
8762 *p
++ = i
.prefix
[REX_PREFIX
];
8764 *p
++ = i
.tm
.base_opcode
;
8765 if (i
.op
[1].imms
->X_op
== O_constant
)
8767 offsetT n
= i
.op
[1].imms
->X_add_number
;
8770 && !fits_in_unsigned_word (n
)
8771 && !fits_in_signed_word (n
))
8773 as_bad (_("16-bit jump out of range"));
8776 md_number_to_chars (p
, n
, size
);
8779 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8780 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8783 if (i
.op
[0].imms
->X_op
== O_constant
)
8784 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8786 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8787 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8795 asection
*seg
= now_seg
;
8796 subsegT subseg
= now_subseg
;
8798 unsigned int alignment
, align_size_1
;
8799 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8800 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8801 unsigned int padding
;
8803 if (!IS_ELF
|| !x86_used_note
)
8806 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8808 /* The .note.gnu.property section layout:
8810 Field Length Contents
8813 n_descsz 4 The note descriptor size
8814 n_type 4 NT_GNU_PROPERTY_TYPE_0
8816 n_desc n_descsz The program property array
8820 /* Create the .note.gnu.property section. */
8821 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8822 bfd_set_section_flags (sec
,
8829 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8840 bfd_set_section_alignment (sec
, alignment
);
8841 elf_section_type (sec
) = SHT_NOTE
;
8843 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8845 isa_1_descsz_raw
= 4 + 4 + 4;
8846 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8847 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8849 feature_2_descsz_raw
= isa_1_descsz
;
8850 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8852 feature_2_descsz_raw
+= 4 + 4 + 4;
8853 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8854 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8857 descsz
= feature_2_descsz
;
8858 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8859 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8861 /* Write n_namsz. */
8862 md_number_to_chars (p
, (valueT
) 4, 4);
8864 /* Write n_descsz. */
8865 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8868 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8871 memcpy (p
+ 4 * 3, "GNU", 4);
8873 /* Write 4-byte type. */
8874 md_number_to_chars (p
+ 4 * 4,
8875 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8877 /* Write 4-byte data size. */
8878 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8880 /* Write 4-byte data. */
8881 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8883 /* Zero out paddings. */
8884 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8886 memset (p
+ 4 * 7, 0, padding
);
8888 /* Write 4-byte type. */
8889 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8890 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8892 /* Write 4-byte data size. */
8893 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8895 /* Write 4-byte data. */
8896 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8897 (valueT
) x86_feature_2_used
, 4);
8899 /* Zero out paddings. */
8900 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8902 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8904 /* We probably can't restore the current segment, for there likely
8907 subseg_set (seg
, subseg
);
8912 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8913 const char *frag_now_ptr
)
8915 unsigned int len
= 0;
8917 if (start_frag
!= frag_now
)
8919 const fragS
*fr
= start_frag
;
8924 } while (fr
&& fr
!= frag_now
);
8927 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8930 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8931 be macro-fused with conditional jumps.
8932 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8933 or is one of the following format:
8946 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8948 /* No RIP address. */
8949 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8952 /* No VEX/EVEX encoding. */
8953 if (is_any_vex_encoding (&i
.tm
))
8956 /* add, sub without add/sub m, imm. */
8957 if (i
.tm
.base_opcode
<= 5
8958 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8959 || ((i
.tm
.base_opcode
| 3) == 0x83
8960 && (i
.tm
.extension_opcode
== 0x5
8961 || i
.tm
.extension_opcode
== 0x0)))
8963 *mf_cmp_p
= mf_cmp_alu_cmp
;
8964 return !(i
.mem_operands
&& i
.imm_operands
);
8967 /* and without and m, imm. */
8968 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8969 || ((i
.tm
.base_opcode
| 3) == 0x83
8970 && i
.tm
.extension_opcode
== 0x4))
8972 *mf_cmp_p
= mf_cmp_test_and
;
8973 return !(i
.mem_operands
&& i
.imm_operands
);
8976 /* test without test m imm. */
8977 if ((i
.tm
.base_opcode
| 1) == 0x85
8978 || (i
.tm
.base_opcode
| 1) == 0xa9
8979 || ((i
.tm
.base_opcode
| 1) == 0xf7
8980 && i
.tm
.extension_opcode
== 0))
8982 *mf_cmp_p
= mf_cmp_test_and
;
8983 return !(i
.mem_operands
&& i
.imm_operands
);
8986 /* cmp without cmp m, imm. */
8987 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8988 || ((i
.tm
.base_opcode
| 3) == 0x83
8989 && (i
.tm
.extension_opcode
== 0x7)))
8991 *mf_cmp_p
= mf_cmp_alu_cmp
;
8992 return !(i
.mem_operands
&& i
.imm_operands
);
8995 /* inc, dec without inc/dec m. */
8996 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8997 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8998 || ((i
.tm
.base_opcode
| 1) == 0xff
8999 && i
.tm
.extension_opcode
<= 0x1))
9001 *mf_cmp_p
= mf_cmp_incdec
;
9002 return !i
.mem_operands
;
9008 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9011 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9013 /* NB: Don't work with COND_JUMP86 without i386. */
9014 if (!align_branch_power
9015 || now_seg
== absolute_section
9016 || !cpu_arch_flags
.bitfield
.cpui386
9017 || !(align_branch
& align_branch_fused_bit
))
9020 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9022 if (last_insn
.kind
== last_insn_other
9023 || last_insn
.seg
!= now_seg
)
9026 as_warn_where (last_insn
.file
, last_insn
.line
,
9027 _("`%s` skips -malign-branch-boundary on `%s`"),
9028 last_insn
.name
, i
.tm
.name
);
9034 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9037 add_branch_prefix_frag_p (void)
9039 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9040 to PadLock instructions since they include prefixes in opcode. */
9041 if (!align_branch_power
9042 || !align_branch_prefix_size
9043 || now_seg
== absolute_section
9044 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9045 || !cpu_arch_flags
.bitfield
.cpui386
)
9048 /* Don't add prefix if it is a prefix or there is no operand in case
9049 that segment prefix is special. */
9050 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9053 if (last_insn
.kind
== last_insn_other
9054 || last_insn
.seg
!= now_seg
)
9058 as_warn_where (last_insn
.file
, last_insn
.line
,
9059 _("`%s` skips -malign-branch-boundary on `%s`"),
9060 last_insn
.name
, i
.tm
.name
);
9065 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9068 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9069 enum mf_jcc_kind
*mf_jcc_p
)
9073 /* NB: Don't work with COND_JUMP86 without i386. */
9074 if (!align_branch_power
9075 || now_seg
== absolute_section
9076 || !cpu_arch_flags
.bitfield
.cpui386
)
9081 /* Check for jcc and direct jmp. */
9082 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9084 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9086 *branch_p
= align_branch_jmp
;
9087 add_padding
= align_branch
& align_branch_jmp_bit
;
9091 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9092 igore the lowest bit. */
9093 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9094 *branch_p
= align_branch_jcc
;
9095 if ((align_branch
& align_branch_jcc_bit
))
9099 else if (is_any_vex_encoding (&i
.tm
))
9101 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9104 *branch_p
= align_branch_ret
;
9105 if ((align_branch
& align_branch_ret_bit
))
9110 /* Check for indirect jmp, direct and indirect calls. */
9111 if (i
.tm
.base_opcode
== 0xe8)
9114 *branch_p
= align_branch_call
;
9115 if ((align_branch
& align_branch_call_bit
))
9118 else if (i
.tm
.base_opcode
== 0xff
9119 && (i
.tm
.extension_opcode
== 2
9120 || i
.tm
.extension_opcode
== 4))
9122 /* Indirect call and jmp. */
9123 *branch_p
= align_branch_indirect
;
9124 if ((align_branch
& align_branch_indirect_bit
))
9131 && (i
.op
[0].disps
->X_op
== O_symbol
9132 || (i
.op
[0].disps
->X_op
== O_subtract
9133 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9135 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9136 /* No padding to call to global or undefined tls_get_addr. */
9137 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9138 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9144 && last_insn
.kind
!= last_insn_other
9145 && last_insn
.seg
== now_seg
)
9148 as_warn_where (last_insn
.file
, last_insn
.line
,
9149 _("`%s` skips -malign-branch-boundary on `%s`"),
9150 last_insn
.name
, i
.tm
.name
);
9160 fragS
*insn_start_frag
;
9161 offsetT insn_start_off
;
9162 fragS
*fragP
= NULL
;
9163 enum align_branch_kind branch
= align_branch_none
;
9164 /* The initializer is arbitrary just to avoid uninitialized error.
9165 it's actually either assigned in add_branch_padding_frag_p
9166 or never be used. */
9167 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9170 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9172 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9173 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9174 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9176 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9177 || i
.tm
.cpu_flags
.bitfield
.cpu287
9178 || i
.tm
.cpu_flags
.bitfield
.cpu387
9179 || i
.tm
.cpu_flags
.bitfield
.cpu687
9180 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9181 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9183 if ((i
.xstate
& xstate_mmx
)
9184 || i
.tm
.base_opcode
== 0xf77 /* emms */
9185 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9186 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9190 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9191 i
.xstate
|= xstate_zmm
;
9192 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9193 i
.xstate
|= xstate_ymm
;
9194 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9195 i
.xstate
|= xstate_xmm
;
9198 /* vzeroall / vzeroupper */
9199 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9200 i
.xstate
|= xstate_ymm
;
9202 if ((i
.xstate
& xstate_xmm
)
9203 /* ldmxcsr / stmxcsr */
9204 || (i
.tm
.base_opcode
== 0xfae && i
.tm
.cpu_flags
.bitfield
.cpusse
)
9205 /* vldmxcsr / vstmxcsr */
9206 || (i
.tm
.base_opcode
== 0xae && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9207 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9208 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9209 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9211 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9212 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9213 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9214 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9215 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9216 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9217 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9218 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9219 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9220 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9221 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9222 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9223 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9224 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9226 if (x86_feature_2_used
9227 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9228 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9229 || (i
.tm
.base_opcode
== 0xfc7
9230 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9231 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9232 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9233 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9234 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9235 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9236 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9237 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9238 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9239 /* LAHF-SAHF insns in 64-bit mode. */
9240 || (flag_code
== CODE_64BIT
9241 && (i
.tm
.base_opcode
| 1) == 0x9f
9242 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9243 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9244 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9245 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9246 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9247 CpuAVX512DQ, LPW, TBM and AMX. */
9248 || (i
.tm
.opcode_modifier
.vex
9249 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9250 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9251 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9252 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9253 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9254 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9255 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9256 || i
.tm
.cpu_flags
.bitfield
.cpufma
9257 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9258 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9259 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9260 || (x86_feature_2_used
9261 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9262 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9263 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9264 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9265 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9266 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9267 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9268 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9269 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9271 || (i
.tm
.opcode_modifier
.evex
9272 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9273 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9274 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9275 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9279 /* Tie dwarf2 debug info to the address at the start of the insn.
9280 We can't do this after the insn has been output as the current
9281 frag may have been closed off. eg. by frag_var. */
9282 dwarf2_emit_insn (0);
9284 insn_start_frag
= frag_now
;
9285 insn_start_off
= frag_now_fix ();
9287 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9290 /* Branch can be 8 bytes. Leave some room for prefixes. */
9291 unsigned int max_branch_padding_size
= 14;
9293 /* Align section to boundary. */
9294 record_alignment (now_seg
, align_branch_power
);
9296 /* Make room for padding. */
9297 frag_grow (max_branch_padding_size
);
9299 /* Start of the padding. */
9304 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9305 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9308 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9309 fragP
->tc_frag_data
.branch_type
= branch
;
9310 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9314 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9316 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9317 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9319 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9320 output_interseg_jump ();
9323 /* Output normal instructions here. */
9327 enum mf_cmp_kind mf_cmp
;
9330 && (i
.tm
.base_opcode
== 0xfaee8
9331 || i
.tm
.base_opcode
== 0xfaef0
9332 || i
.tm
.base_opcode
== 0xfaef8))
9334 /* Encode lfence, mfence, and sfence as
9335 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9336 if (now_seg
!= absolute_section
)
9338 offsetT val
= 0x240483f0ULL
;
9341 md_number_to_chars (p
, val
, 5);
9344 abs_section_offset
+= 5;
9348 /* Some processors fail on LOCK prefix. This options makes
9349 assembler ignore LOCK prefix and serves as a workaround. */
9350 if (omit_lock_prefix
)
9352 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9353 && i
.tm
.opcode_modifier
.isprefix
)
9355 i
.prefix
[LOCK_PREFIX
] = 0;
9359 /* Skip if this is a branch. */
9361 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9363 /* Make room for padding. */
9364 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9369 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9370 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9373 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9374 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9375 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9377 else if (add_branch_prefix_frag_p ())
9379 unsigned int max_prefix_size
= align_branch_prefix_size
;
9381 /* Make room for padding. */
9382 frag_grow (max_prefix_size
);
9387 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9388 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9391 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9394 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9395 don't need the explicit prefix. */
9396 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9398 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9407 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9408 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9412 switch (i
.opcode_length
)
9418 /* Check for pseudo prefixes. */
9419 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9421 as_bad_where (insn_start_frag
->fr_file
,
9422 insn_start_frag
->fr_line
,
9423 _("pseudo prefix without instruction"));
9433 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9434 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9435 R_X86_64_GOTTPOFF relocation so that linker can safely
9436 perform IE->LE optimization. A dummy REX_OPCODE prefix
9437 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9438 relocation for GDesc -> IE/LE optimization. */
9439 if (x86_elf_abi
== X86_64_X32_ABI
9441 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9442 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9443 && i
.prefix
[REX_PREFIX
] == 0)
9444 add_prefix (REX_OPCODE
);
9447 /* The prefix bytes. */
9448 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9450 frag_opcode_byte (*q
);
9454 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9460 frag_opcode_byte (*q
);
9463 /* There should be no other prefixes for instructions
9468 /* For EVEX instructions i.vrex should become 0 after
9469 build_evex_prefix. For VEX instructions upper 16 registers
9470 aren't available, so VREX should be 0. */
9473 /* Now the VEX prefix. */
9474 if (now_seg
!= absolute_section
)
9476 p
= frag_more (i
.vex
.length
);
9477 for (j
= 0; j
< i
.vex
.length
; j
++)
9478 p
[j
] = i
.vex
.bytes
[j
];
9481 abs_section_offset
+= i
.vex
.length
;
9484 /* Now the opcode; be careful about word order here! */
9485 if (now_seg
== absolute_section
)
9486 abs_section_offset
+= i
.opcode_length
;
9487 else if (i
.opcode_length
== 1)
9489 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9493 switch (i
.opcode_length
)
9497 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9498 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9502 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9512 /* Put out high byte first: can't use md_number_to_chars! */
9513 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9514 *p
= i
.tm
.base_opcode
& 0xff;
9517 /* Now the modrm byte and sib byte (if present). */
9518 if (i
.tm
.opcode_modifier
.modrm
)
9520 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9522 | (i
.rm
.mode
<< 6));
9523 /* If i.rm.regmem == ESP (4)
9524 && i.rm.mode != (Register mode)
9526 ==> need second modrm byte. */
9527 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9529 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9530 frag_opcode_byte ((i
.sib
.base
<< 0)
9531 | (i
.sib
.index
<< 3)
9532 | (i
.sib
.scale
<< 6));
9535 if (i
.disp_operands
)
9536 output_disp (insn_start_frag
, insn_start_off
);
9539 output_imm (insn_start_frag
, insn_start_off
);
9542 * frag_now_fix () returning plain abs_section_offset when we're in the
9543 * absolute section, and abs_section_offset not getting updated as data
9544 * gets added to the frag breaks the logic below.
9546 if (now_seg
!= absolute_section
)
9548 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9550 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9554 /* NB: Don't add prefix with GOTPC relocation since
9555 output_disp() above depends on the fixed encoding
9556 length. Can't add prefix with TLS relocation since
9557 it breaks TLS linker optimization. */
9558 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9559 /* Prefix count on the current instruction. */
9560 unsigned int count
= i
.vex
.length
;
9562 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9563 /* REX byte is encoded in VEX/EVEX prefix. */
9564 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9567 /* Count prefixes for extended opcode maps. */
9569 switch (i
.opcode_length
)
9572 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9575 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9587 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9596 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9599 /* Set the maximum prefix size in BRANCH_PREFIX
9601 if (fragP
->tc_frag_data
.max_bytes
> max
)
9602 fragP
->tc_frag_data
.max_bytes
= max
;
9603 if (fragP
->tc_frag_data
.max_bytes
> count
)
9604 fragP
->tc_frag_data
.max_bytes
-= count
;
9606 fragP
->tc_frag_data
.max_bytes
= 0;
9610 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9612 unsigned int max_prefix_size
;
9613 if (align_branch_prefix_size
> max
)
9614 max_prefix_size
= max
;
9616 max_prefix_size
= align_branch_prefix_size
;
9617 if (max_prefix_size
> count
)
9618 fragP
->tc_frag_data
.max_prefix_length
9619 = max_prefix_size
- count
;
9622 /* Use existing segment prefix if possible. Use CS
9623 segment prefix in 64-bit mode. In 32-bit mode, use SS
9624 segment prefix with ESP/EBP base register and use DS
9625 segment prefix without ESP/EBP base register. */
9626 if (i
.prefix
[SEG_PREFIX
])
9627 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9628 else if (flag_code
== CODE_64BIT
)
9629 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9631 && (i
.base_reg
->reg_num
== 4
9632 || i
.base_reg
->reg_num
== 5))
9633 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9635 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9640 /* NB: Don't work with COND_JUMP86 without i386. */
9641 if (align_branch_power
9642 && now_seg
!= absolute_section
9643 && cpu_arch_flags
.bitfield
.cpui386
)
9645 /* Terminate each frag so that we can add prefix and check for
9647 frag_wane (frag_now
);
9654 pi ("" /*line*/, &i
);
9656 #endif /* DEBUG386 */
9659 /* Return the size of the displacement operand N. */
9662 disp_size (unsigned int n
)
9666 if (i
.types
[n
].bitfield
.disp64
)
9668 else if (i
.types
[n
].bitfield
.disp8
)
9670 else if (i
.types
[n
].bitfield
.disp16
)
9675 /* Return the size of the immediate operand N. */
9678 imm_size (unsigned int n
)
9681 if (i
.types
[n
].bitfield
.imm64
)
9683 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9685 else if (i
.types
[n
].bitfield
.imm16
)
9691 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9696 for (n
= 0; n
< i
.operands
; n
++)
9698 if (operand_type_check (i
.types
[n
], disp
))
9700 int size
= disp_size (n
);
9702 if (now_seg
== absolute_section
)
9703 abs_section_offset
+= size
;
9704 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9706 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9708 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9710 p
= frag_more (size
);
9711 md_number_to_chars (p
, val
, size
);
9715 enum bfd_reloc_code_real reloc_type
;
9716 int sign
= i
.types
[n
].bitfield
.disp32s
;
9717 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9720 /* We can't have 8 bit displacement here. */
9721 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9723 /* The PC relative address is computed relative
9724 to the instruction boundary, so in case immediate
9725 fields follows, we need to adjust the value. */
9726 if (pcrel
&& i
.imm_operands
)
9731 for (n1
= 0; n1
< i
.operands
; n1
++)
9732 if (operand_type_check (i
.types
[n1
], imm
))
9734 /* Only one immediate is allowed for PC
9735 relative address. */
9736 gas_assert (sz
== 0);
9738 i
.op
[n
].disps
->X_add_number
-= sz
;
9740 /* We should find the immediate. */
9741 gas_assert (sz
!= 0);
9744 p
= frag_more (size
);
9745 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9747 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9748 && (((reloc_type
== BFD_RELOC_32
9749 || reloc_type
== BFD_RELOC_X86_64_32S
9750 || (reloc_type
== BFD_RELOC_64
9752 && (i
.op
[n
].disps
->X_op
== O_symbol
9753 || (i
.op
[n
].disps
->X_op
== O_add
9754 && ((symbol_get_value_expression
9755 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9757 || reloc_type
== BFD_RELOC_32_PCREL
))
9761 reloc_type
= BFD_RELOC_386_GOTPC
;
9762 i
.has_gotpc_tls_reloc
= TRUE
;
9763 i
.op
[n
].imms
->X_add_number
+=
9764 encoding_length (insn_start_frag
, insn_start_off
, p
);
9766 else if (reloc_type
== BFD_RELOC_64
)
9767 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9769 /* Don't do the adjustment for x86-64, as there
9770 the pcrel addressing is relative to the _next_
9771 insn, and that is taken care of in other code. */
9772 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9774 else if (align_branch_power
)
9778 case BFD_RELOC_386_TLS_GD
:
9779 case BFD_RELOC_386_TLS_LDM
:
9780 case BFD_RELOC_386_TLS_IE
:
9781 case BFD_RELOC_386_TLS_IE_32
:
9782 case BFD_RELOC_386_TLS_GOTIE
:
9783 case BFD_RELOC_386_TLS_GOTDESC
:
9784 case BFD_RELOC_386_TLS_DESC_CALL
:
9785 case BFD_RELOC_X86_64_TLSGD
:
9786 case BFD_RELOC_X86_64_TLSLD
:
9787 case BFD_RELOC_X86_64_GOTTPOFF
:
9788 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9789 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9790 i
.has_gotpc_tls_reloc
= TRUE
;
9795 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9796 size
, i
.op
[n
].disps
, pcrel
,
9798 /* Check for "call/jmp *mem", "mov mem, %reg",
9799 "test %reg, mem" and "binop mem, %reg" where binop
9800 is one of adc, add, and, cmp, or, sbb, sub, xor
9801 instructions without data prefix. Always generate
9802 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9803 if (i
.prefix
[DATA_PREFIX
] == 0
9804 && (generate_relax_relocations
9807 && i
.rm
.regmem
== 5))
9809 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9810 && !is_any_vex_encoding(&i
.tm
)
9811 && ((i
.operands
== 1
9812 && i
.tm
.base_opcode
== 0xff
9813 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9815 && (i
.tm
.base_opcode
== 0x8b
9816 || i
.tm
.base_opcode
== 0x85
9817 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9821 fixP
->fx_tcbit
= i
.rex
!= 0;
9823 && (i
.base_reg
->reg_num
== RegIP
))
9824 fixP
->fx_tcbit2
= 1;
9827 fixP
->fx_tcbit2
= 1;
9835 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9840 for (n
= 0; n
< i
.operands
; n
++)
9842 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9843 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9846 if (operand_type_check (i
.types
[n
], imm
))
9848 int size
= imm_size (n
);
9850 if (now_seg
== absolute_section
)
9851 abs_section_offset
+= size
;
9852 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9856 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9858 p
= frag_more (size
);
9859 md_number_to_chars (p
, val
, size
);
9863 /* Not absolute_section.
9864 Need a 32-bit fixup (don't support 8bit
9865 non-absolute imms). Try to support other
9867 enum bfd_reloc_code_real reloc_type
;
9870 if (i
.types
[n
].bitfield
.imm32s
9871 && (i
.suffix
== QWORD_MNEM_SUFFIX
9872 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9877 p
= frag_more (size
);
9878 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9880 /* This is tough to explain. We end up with this one if we
9881 * have operands that look like
9882 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9883 * obtain the absolute address of the GOT, and it is strongly
9884 * preferable from a performance point of view to avoid using
9885 * a runtime relocation for this. The actual sequence of
9886 * instructions often look something like:
9891 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9893 * The call and pop essentially return the absolute address
9894 * of the label .L66 and store it in %ebx. The linker itself
9895 * will ultimately change the first operand of the addl so
9896 * that %ebx points to the GOT, but to keep things simple, the
9897 * .o file must have this operand set so that it generates not
9898 * the absolute address of .L66, but the absolute address of
9899 * itself. This allows the linker itself simply treat a GOTPC
9900 * relocation as asking for a pcrel offset to the GOT to be
9901 * added in, and the addend of the relocation is stored in the
9902 * operand field for the instruction itself.
9904 * Our job here is to fix the operand so that it would add
9905 * the correct offset so that %ebx would point to itself. The
9906 * thing that is tricky is that .-.L66 will point to the
9907 * beginning of the instruction, so we need to further modify
9908 * the operand so that it will point to itself. There are
9909 * other cases where you have something like:
9911 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9913 * and here no correction would be required. Internally in
9914 * the assembler we treat operands of this form as not being
9915 * pcrel since the '.' is explicitly mentioned, and I wonder
9916 * whether it would simplify matters to do it this way. Who
9917 * knows. In earlier versions of the PIC patches, the
9918 * pcrel_adjust field was used to store the correction, but
9919 * since the expression is not pcrel, I felt it would be
9920 * confusing to do it this way. */
9922 if ((reloc_type
== BFD_RELOC_32
9923 || reloc_type
== BFD_RELOC_X86_64_32S
9924 || reloc_type
== BFD_RELOC_64
)
9926 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9927 && (i
.op
[n
].imms
->X_op
== O_symbol
9928 || (i
.op
[n
].imms
->X_op
== O_add
9929 && ((symbol_get_value_expression
9930 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9934 reloc_type
= BFD_RELOC_386_GOTPC
;
9936 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9938 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9939 i
.has_gotpc_tls_reloc
= TRUE
;
9940 i
.op
[n
].imms
->X_add_number
+=
9941 encoding_length (insn_start_frag
, insn_start_off
, p
);
9943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9944 i
.op
[n
].imms
, 0, reloc_type
);
9950 /* x86_cons_fix_new is called via the expression parsing code when a
9951 reloc is needed. We use this hook to get the correct .got reloc. */
9952 static int cons_sign
= -1;
9955 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9956 expressionS
*exp
, bfd_reloc_code_real_type r
)
9958 r
= reloc (len
, 0, cons_sign
, r
);
9961 if (exp
->X_op
== O_secrel
)
9963 exp
->X_op
= O_symbol
;
9964 r
= BFD_RELOC_32_SECREL
;
9968 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9971 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9972 purpose of the `.dc.a' internal pseudo-op. */
9975 x86_address_bytes (void)
9977 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9979 return stdoutput
->arch_info
->bits_per_address
/ 8;
9982 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9984 # define lex_got(reloc, adjust, types) NULL
9986 /* Parse operands of the form
9987 <symbol>@GOTOFF+<nnn>
9988 and similar .plt or .got references.
9990 If we find one, set up the correct relocation in RELOC and copy the
9991 input string, minus the `@GOTOFF' into a malloc'd buffer for
9992 parsing by the calling routine. Return this buffer, and if ADJUST
9993 is non-null set it to the length of the string we removed from the
9994 input line. Otherwise return NULL. */
9996 lex_got (enum bfd_reloc_code_real
*rel
,
9998 i386_operand_type
*types
)
10000 /* Some of the relocations depend on the size of what field is to
10001 be relocated. But in our callers i386_immediate and i386_displacement
10002 we don't yet know the operand size (this will be set by insn
10003 matching). Hence we record the word32 relocation here,
10004 and adjust the reloc according to the real size in reloc(). */
10005 static const struct {
10008 const enum bfd_reloc_code_real rel
[2];
10009 const i386_operand_type types64
;
10010 bfd_boolean need_GOT_symbol
;
10012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10013 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10014 BFD_RELOC_SIZE32
},
10015 OPERAND_TYPE_IMM32_64
, FALSE
},
10017 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10018 BFD_RELOC_X86_64_PLTOFF64
},
10019 OPERAND_TYPE_IMM64
, TRUE
},
10020 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10021 BFD_RELOC_X86_64_PLT32
},
10022 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10023 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10024 BFD_RELOC_X86_64_GOTPLT64
},
10025 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10026 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10027 BFD_RELOC_X86_64_GOTOFF64
},
10028 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10029 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10030 BFD_RELOC_X86_64_GOTPCREL
},
10031 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10032 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10033 BFD_RELOC_X86_64_TLSGD
},
10034 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10035 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10036 _dummy_first_bfd_reloc_code_real
},
10037 OPERAND_TYPE_NONE
, TRUE
},
10038 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10039 BFD_RELOC_X86_64_TLSLD
},
10040 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10041 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10042 BFD_RELOC_X86_64_GOTTPOFF
},
10043 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10044 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10045 BFD_RELOC_X86_64_TPOFF32
},
10046 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10047 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10048 _dummy_first_bfd_reloc_code_real
},
10049 OPERAND_TYPE_NONE
, TRUE
},
10050 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10051 BFD_RELOC_X86_64_DTPOFF32
},
10052 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10053 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10054 _dummy_first_bfd_reloc_code_real
},
10055 OPERAND_TYPE_NONE
, TRUE
},
10056 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10057 _dummy_first_bfd_reloc_code_real
},
10058 OPERAND_TYPE_NONE
, TRUE
},
10059 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10060 BFD_RELOC_X86_64_GOT32
},
10061 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10062 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10063 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10064 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10065 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10066 BFD_RELOC_X86_64_TLSDESC_CALL
},
10067 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10072 #if defined (OBJ_MAYBE_ELF)
10077 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10078 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10081 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10083 int len
= gotrel
[j
].len
;
10084 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10086 if (gotrel
[j
].rel
[object_64bit
] != 0)
10089 char *tmpbuf
, *past_reloc
;
10091 *rel
= gotrel
[j
].rel
[object_64bit
];
10095 if (flag_code
!= CODE_64BIT
)
10097 types
->bitfield
.imm32
= 1;
10098 types
->bitfield
.disp32
= 1;
10101 *types
= gotrel
[j
].types64
;
10104 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10105 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10107 /* The length of the first part of our input line. */
10108 first
= cp
- input_line_pointer
;
10110 /* The second part goes from after the reloc token until
10111 (and including) an end_of_line char or comma. */
10112 past_reloc
= cp
+ 1 + len
;
10114 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10116 second
= cp
+ 1 - past_reloc
;
10118 /* Allocate and copy string. The trailing NUL shouldn't
10119 be necessary, but be safe. */
10120 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10121 memcpy (tmpbuf
, input_line_pointer
, first
);
10122 if (second
!= 0 && *past_reloc
!= ' ')
10123 /* Replace the relocation token with ' ', so that
10124 errors like foo@GOTOFF1 will be detected. */
10125 tmpbuf
[first
++] = ' ';
10127 /* Increment length by 1 if the relocation token is
10132 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10133 tmpbuf
[first
+ second
] = '\0';
10137 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10138 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10143 /* Might be a symbol version string. Don't as_bad here. */
10152 /* Parse operands of the form
10153 <symbol>@SECREL32+<nnn>
10155 If we find one, set up the correct relocation in RELOC and copy the
10156 input string, minus the `@SECREL32' into a malloc'd buffer for
10157 parsing by the calling routine. Return this buffer, and if ADJUST
10158 is non-null set it to the length of the string we removed from the
10159 input line. Otherwise return NULL.
10161 This function is copied from the ELF version above adjusted for PE targets. */
10164 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10165 int *adjust ATTRIBUTE_UNUSED
,
10166 i386_operand_type
*types
)
10168 static const struct
10172 const enum bfd_reloc_code_real rel
[2];
10173 const i386_operand_type types64
;
10177 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10178 BFD_RELOC_32_SECREL
},
10179 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10185 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10186 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10189 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10191 int len
= gotrel
[j
].len
;
10193 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10195 if (gotrel
[j
].rel
[object_64bit
] != 0)
10198 char *tmpbuf
, *past_reloc
;
10200 *rel
= gotrel
[j
].rel
[object_64bit
];
10206 if (flag_code
!= CODE_64BIT
)
10208 types
->bitfield
.imm32
= 1;
10209 types
->bitfield
.disp32
= 1;
10212 *types
= gotrel
[j
].types64
;
10215 /* The length of the first part of our input line. */
10216 first
= cp
- input_line_pointer
;
10218 /* The second part goes from after the reloc token until
10219 (and including) an end_of_line char or comma. */
10220 past_reloc
= cp
+ 1 + len
;
10222 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10224 second
= cp
+ 1 - past_reloc
;
10226 /* Allocate and copy string. The trailing NUL shouldn't
10227 be necessary, but be safe. */
10228 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10229 memcpy (tmpbuf
, input_line_pointer
, first
);
10230 if (second
!= 0 && *past_reloc
!= ' ')
10231 /* Replace the relocation token with ' ', so that
10232 errors like foo@SECLREL321 will be detected. */
10233 tmpbuf
[first
++] = ' ';
10234 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10235 tmpbuf
[first
+ second
] = '\0';
10239 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10240 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10245 /* Might be a symbol version string. Don't as_bad here. */
10251 bfd_reloc_code_real_type
10252 x86_cons (expressionS
*exp
, int size
)
10254 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10256 intel_syntax
= -intel_syntax
;
10259 if (size
== 4 || (object_64bit
&& size
== 8))
10261 /* Handle @GOTOFF and the like in an expression. */
10263 char *gotfree_input_line
;
10266 save
= input_line_pointer
;
10267 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10268 if (gotfree_input_line
)
10269 input_line_pointer
= gotfree_input_line
;
10273 if (gotfree_input_line
)
10275 /* expression () has merrily parsed up to the end of line,
10276 or a comma - in the wrong buffer. Transfer how far
10277 input_line_pointer has moved to the right buffer. */
10278 input_line_pointer
= (save
10279 + (input_line_pointer
- gotfree_input_line
)
10281 free (gotfree_input_line
);
10282 if (exp
->X_op
== O_constant
10283 || exp
->X_op
== O_absent
10284 || exp
->X_op
== O_illegal
10285 || exp
->X_op
== O_register
10286 || exp
->X_op
== O_big
)
10288 char c
= *input_line_pointer
;
10289 *input_line_pointer
= 0;
10290 as_bad (_("missing or invalid expression `%s'"), save
);
10291 *input_line_pointer
= c
;
10293 else if ((got_reloc
== BFD_RELOC_386_PLT32
10294 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10295 && exp
->X_op
!= O_symbol
)
10297 char c
= *input_line_pointer
;
10298 *input_line_pointer
= 0;
10299 as_bad (_("invalid PLT expression `%s'"), save
);
10300 *input_line_pointer
= c
;
10307 intel_syntax
= -intel_syntax
;
10310 i386_intel_simplify (exp
);
10316 signed_cons (int size
)
10318 if (flag_code
== CODE_64BIT
)
10326 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10333 if (exp
.X_op
== O_symbol
)
10334 exp
.X_op
= O_secrel
;
10336 emit_expr (&exp
, 4);
10338 while (*input_line_pointer
++ == ',');
10340 input_line_pointer
--;
10341 demand_empty_rest_of_line ();
10345 /* Handle Vector operations. */
10348 check_VecOperations (char *op_string
, char *op_end
)
10350 const reg_entry
*mask
;
10355 && (op_end
== NULL
|| op_string
< op_end
))
10358 if (*op_string
== '{')
10362 /* Check broadcasts. */
10363 if (strncmp (op_string
, "1to", 3) == 0)
10368 goto duplicated_vec_op
;
10371 if (*op_string
== '8')
10373 else if (*op_string
== '4')
10375 else if (*op_string
== '2')
10377 else if (*op_string
== '1'
10378 && *(op_string
+1) == '6')
10385 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10390 broadcast_op
.type
= bcst_type
;
10391 broadcast_op
.operand
= this_operand
;
10392 broadcast_op
.bytes
= 0;
10393 i
.broadcast
= &broadcast_op
;
10395 /* Check masking operation. */
10396 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10398 if (mask
== &bad_reg
)
10401 /* k0 can't be used for write mask. */
10402 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10404 as_bad (_("`%s%s' can't be used for write mask"),
10405 register_prefix
, mask
->reg_name
);
10411 mask_op
.mask
= mask
;
10412 mask_op
.zeroing
= 0;
10413 mask_op
.operand
= this_operand
;
10419 goto duplicated_vec_op
;
10421 i
.mask
->mask
= mask
;
10423 /* Only "{z}" is allowed here. No need to check
10424 zeroing mask explicitly. */
10425 if (i
.mask
->operand
!= this_operand
)
10427 as_bad (_("invalid write mask `%s'"), saved
);
10432 op_string
= end_op
;
10434 /* Check zeroing-flag for masking operation. */
10435 else if (*op_string
== 'z')
10439 mask_op
.mask
= NULL
;
10440 mask_op
.zeroing
= 1;
10441 mask_op
.operand
= this_operand
;
10446 if (i
.mask
->zeroing
)
10449 as_bad (_("duplicated `%s'"), saved
);
10453 i
.mask
->zeroing
= 1;
10455 /* Only "{%k}" is allowed here. No need to check mask
10456 register explicitly. */
10457 if (i
.mask
->operand
!= this_operand
)
10459 as_bad (_("invalid zeroing-masking `%s'"),
10468 goto unknown_vec_op
;
10470 if (*op_string
!= '}')
10472 as_bad (_("missing `}' in `%s'"), saved
);
10477 /* Strip whitespace since the addition of pseudo prefixes
10478 changed how the scrubber treats '{'. */
10479 if (is_space_char (*op_string
))
10485 /* We don't know this one. */
10486 as_bad (_("unknown vector operation: `%s'"), saved
);
10490 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10492 as_bad (_("zeroing-masking only allowed with write mask"));
10500 i386_immediate (char *imm_start
)
10502 char *save_input_line_pointer
;
10503 char *gotfree_input_line
;
10506 i386_operand_type types
;
10508 operand_type_set (&types
, ~0);
10510 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10512 as_bad (_("at most %d immediate operands are allowed"),
10513 MAX_IMMEDIATE_OPERANDS
);
10517 exp
= &im_expressions
[i
.imm_operands
++];
10518 i
.op
[this_operand
].imms
= exp
;
10520 if (is_space_char (*imm_start
))
10523 save_input_line_pointer
= input_line_pointer
;
10524 input_line_pointer
= imm_start
;
10526 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10527 if (gotfree_input_line
)
10528 input_line_pointer
= gotfree_input_line
;
10530 exp_seg
= expression (exp
);
10532 SKIP_WHITESPACE ();
10534 /* Handle vector operations. */
10535 if (*input_line_pointer
== '{')
10537 input_line_pointer
= check_VecOperations (input_line_pointer
,
10539 if (input_line_pointer
== NULL
)
10543 if (*input_line_pointer
)
10544 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10546 input_line_pointer
= save_input_line_pointer
;
10547 if (gotfree_input_line
)
10549 free (gotfree_input_line
);
10551 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10552 exp
->X_op
= O_illegal
;
10555 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10559 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10560 i386_operand_type types
, const char *imm_start
)
10562 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10565 as_bad (_("missing or invalid immediate expression `%s'"),
10569 else if (exp
->X_op
== O_constant
)
10571 /* Size it properly later. */
10572 i
.types
[this_operand
].bitfield
.imm64
= 1;
10573 /* If not 64bit, sign extend val. */
10574 if (flag_code
!= CODE_64BIT
10575 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10577 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10579 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10580 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10581 && exp_seg
!= absolute_section
10582 && exp_seg
!= text_section
10583 && exp_seg
!= data_section
10584 && exp_seg
!= bss_section
10585 && exp_seg
!= undefined_section
10586 && !bfd_is_com_section (exp_seg
))
10588 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10592 else if (!intel_syntax
&& exp_seg
== reg_section
)
10595 as_bad (_("illegal immediate register operand %s"), imm_start
);
10600 /* This is an address. The size of the address will be
10601 determined later, depending on destination register,
10602 suffix, or the default for the section. */
10603 i
.types
[this_operand
].bitfield
.imm8
= 1;
10604 i
.types
[this_operand
].bitfield
.imm16
= 1;
10605 i
.types
[this_operand
].bitfield
.imm32
= 1;
10606 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10607 i
.types
[this_operand
].bitfield
.imm64
= 1;
10608 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10616 i386_scale (char *scale
)
10619 char *save
= input_line_pointer
;
10621 input_line_pointer
= scale
;
10622 val
= get_absolute_expression ();
10627 i
.log2_scale_factor
= 0;
10630 i
.log2_scale_factor
= 1;
10633 i
.log2_scale_factor
= 2;
10636 i
.log2_scale_factor
= 3;
10640 char sep
= *input_line_pointer
;
10642 *input_line_pointer
= '\0';
10643 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10645 *input_line_pointer
= sep
;
10646 input_line_pointer
= save
;
10650 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10652 as_warn (_("scale factor of %d without an index register"),
10653 1 << i
.log2_scale_factor
);
10654 i
.log2_scale_factor
= 0;
10656 scale
= input_line_pointer
;
10657 input_line_pointer
= save
;
10662 i386_displacement (char *disp_start
, char *disp_end
)
10666 char *save_input_line_pointer
;
10667 char *gotfree_input_line
;
10669 i386_operand_type bigdisp
, types
= anydisp
;
10672 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10674 as_bad (_("at most %d displacement operands are allowed"),
10675 MAX_MEMORY_OPERANDS
);
10679 operand_type_set (&bigdisp
, 0);
10681 || i
.types
[this_operand
].bitfield
.baseindex
10682 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10683 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10685 i386_addressing_mode ();
10686 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10687 if (flag_code
== CODE_64BIT
)
10691 bigdisp
.bitfield
.disp32s
= 1;
10692 bigdisp
.bitfield
.disp64
= 1;
10695 bigdisp
.bitfield
.disp32
= 1;
10697 else if ((flag_code
== CODE_16BIT
) ^ override
)
10698 bigdisp
.bitfield
.disp16
= 1;
10700 bigdisp
.bitfield
.disp32
= 1;
10704 /* For PC-relative branches, the width of the displacement may be
10705 dependent upon data size, but is never dependent upon address size.
10706 Also make sure to not unintentionally match against a non-PC-relative
10707 branch template. */
10708 static templates aux_templates
;
10709 const insn_template
*t
= current_templates
->start
;
10710 bfd_boolean has_intel64
= FALSE
;
10712 aux_templates
.start
= t
;
10713 while (++t
< current_templates
->end
)
10715 if (t
->opcode_modifier
.jump
10716 != current_templates
->start
->opcode_modifier
.jump
)
10718 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10719 has_intel64
= TRUE
;
10721 if (t
< current_templates
->end
)
10723 aux_templates
.end
= t
;
10724 current_templates
= &aux_templates
;
10727 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10728 if (flag_code
== CODE_64BIT
)
10730 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10731 && (!intel64
|| !has_intel64
))
10732 bigdisp
.bitfield
.disp16
= 1;
10734 bigdisp
.bitfield
.disp32s
= 1;
10739 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10741 : LONG_MNEM_SUFFIX
));
10742 bigdisp
.bitfield
.disp32
= 1;
10743 if ((flag_code
== CODE_16BIT
) ^ override
)
10745 bigdisp
.bitfield
.disp32
= 0;
10746 bigdisp
.bitfield
.disp16
= 1;
10750 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10753 exp
= &disp_expressions
[i
.disp_operands
];
10754 i
.op
[this_operand
].disps
= exp
;
10756 save_input_line_pointer
= input_line_pointer
;
10757 input_line_pointer
= disp_start
;
10758 END_STRING_AND_SAVE (disp_end
);
10760 #ifndef GCC_ASM_O_HACK
10761 #define GCC_ASM_O_HACK 0
10764 END_STRING_AND_SAVE (disp_end
+ 1);
10765 if (i
.types
[this_operand
].bitfield
.baseIndex
10766 && displacement_string_end
[-1] == '+')
10768 /* This hack is to avoid a warning when using the "o"
10769 constraint within gcc asm statements.
10772 #define _set_tssldt_desc(n,addr,limit,type) \
10773 __asm__ __volatile__ ( \
10774 "movw %w2,%0\n\t" \
10775 "movw %w1,2+%0\n\t" \
10776 "rorl $16,%1\n\t" \
10777 "movb %b1,4+%0\n\t" \
10778 "movb %4,5+%0\n\t" \
10779 "movb $0,6+%0\n\t" \
10780 "movb %h1,7+%0\n\t" \
10782 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10784 This works great except that the output assembler ends
10785 up looking a bit weird if it turns out that there is
10786 no offset. You end up producing code that looks like:
10799 So here we provide the missing zero. */
10801 *displacement_string_end
= '0';
10804 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10805 if (gotfree_input_line
)
10806 input_line_pointer
= gotfree_input_line
;
10808 exp_seg
= expression (exp
);
10810 SKIP_WHITESPACE ();
10811 if (*input_line_pointer
)
10812 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10814 RESTORE_END_STRING (disp_end
+ 1);
10816 input_line_pointer
= save_input_line_pointer
;
10817 if (gotfree_input_line
)
10819 free (gotfree_input_line
);
10821 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10822 exp
->X_op
= O_illegal
;
10825 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10827 RESTORE_END_STRING (disp_end
);
10833 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10834 i386_operand_type types
, const char *disp_start
)
10836 i386_operand_type bigdisp
;
10839 /* We do this to make sure that the section symbol is in
10840 the symbol table. We will ultimately change the relocation
10841 to be relative to the beginning of the section. */
10842 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10843 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10844 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10846 if (exp
->X_op
!= O_symbol
)
10849 if (S_IS_LOCAL (exp
->X_add_symbol
)
10850 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10851 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10852 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10853 exp
->X_op
= O_subtract
;
10854 exp
->X_op_symbol
= GOT_symbol
;
10855 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10856 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10857 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10858 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10860 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10863 else if (exp
->X_op
== O_absent
10864 || exp
->X_op
== O_illegal
10865 || exp
->X_op
== O_big
)
10868 as_bad (_("missing or invalid displacement expression `%s'"),
10873 else if (flag_code
== CODE_64BIT
10874 && !i
.prefix
[ADDR_PREFIX
]
10875 && exp
->X_op
== O_constant
)
10877 /* Since displacement is signed extended to 64bit, don't allow
10878 disp32 and turn off disp32s if they are out of range. */
10879 i
.types
[this_operand
].bitfield
.disp32
= 0;
10880 if (!fits_in_signed_long (exp
->X_add_number
))
10882 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10883 if (i
.types
[this_operand
].bitfield
.baseindex
)
10885 as_bad (_("0x%lx out range of signed 32bit displacement"),
10886 (long) exp
->X_add_number
);
10892 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10893 else if (exp
->X_op
!= O_constant
10894 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10895 && exp_seg
!= absolute_section
10896 && exp_seg
!= text_section
10897 && exp_seg
!= data_section
10898 && exp_seg
!= bss_section
10899 && exp_seg
!= undefined_section
10900 && !bfd_is_com_section (exp_seg
))
10902 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10907 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10908 /* Constants get taken care of by optimize_disp(). */
10909 && exp
->X_op
!= O_constant
)
10910 i
.types
[this_operand
].bitfield
.disp8
= 1;
10912 /* Check if this is a displacement only operand. */
10913 bigdisp
= i
.types
[this_operand
];
10914 bigdisp
.bitfield
.disp8
= 0;
10915 bigdisp
.bitfield
.disp16
= 0;
10916 bigdisp
.bitfield
.disp32
= 0;
10917 bigdisp
.bitfield
.disp32s
= 0;
10918 bigdisp
.bitfield
.disp64
= 0;
10919 if (operand_type_all_zero (&bigdisp
))
10920 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10926 /* Return the active addressing mode, taking address override and
10927 registers forming the address into consideration. Update the
10928 address override prefix if necessary. */
10930 static enum flag_code
10931 i386_addressing_mode (void)
10933 enum flag_code addr_mode
;
10935 if (i
.prefix
[ADDR_PREFIX
])
10936 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10937 else if (flag_code
== CODE_16BIT
10938 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10939 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10940 from md_assemble() by "is not a valid base/index expression"
10941 when there is a base and/or index. */
10942 && !i
.types
[this_operand
].bitfield
.baseindex
)
10944 /* MPX insn memory operands with neither base nor index must be forced
10945 to use 32-bit addressing in 16-bit mode. */
10946 addr_mode
= CODE_32BIT
;
10947 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10949 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10950 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10954 addr_mode
= flag_code
;
10956 #if INFER_ADDR_PREFIX
10957 if (i
.mem_operands
== 0)
10959 /* Infer address prefix from the first memory operand. */
10960 const reg_entry
*addr_reg
= i
.base_reg
;
10962 if (addr_reg
== NULL
)
10963 addr_reg
= i
.index_reg
;
10967 if (addr_reg
->reg_type
.bitfield
.dword
)
10968 addr_mode
= CODE_32BIT
;
10969 else if (flag_code
!= CODE_64BIT
10970 && addr_reg
->reg_type
.bitfield
.word
)
10971 addr_mode
= CODE_16BIT
;
10973 if (addr_mode
!= flag_code
)
10975 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10977 /* Change the size of any displacement too. At most one
10978 of Disp16 or Disp32 is set.
10979 FIXME. There doesn't seem to be any real need for
10980 separate Disp16 and Disp32 flags. The same goes for
10981 Imm16 and Imm32. Removing them would probably clean
10982 up the code quite a lot. */
10983 if (flag_code
!= CODE_64BIT
10984 && (i
.types
[this_operand
].bitfield
.disp16
10985 || i
.types
[this_operand
].bitfield
.disp32
))
10986 i
.types
[this_operand
]
10987 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10997 /* Make sure the memory operand we've been dealt is valid.
10998 Return 1 on success, 0 on a failure. */
11001 i386_index_check (const char *operand_string
)
11003 const char *kind
= "base/index";
11004 enum flag_code addr_mode
= i386_addressing_mode ();
11005 const insn_template
*t
= current_templates
->start
;
11007 if (t
->opcode_modifier
.isstring
11008 && !t
->cpu_flags
.bitfield
.cpupadlock
11009 && (current_templates
->end
[-1].opcode_modifier
.isstring
11010 || i
.mem_operands
))
11012 /* Memory operands of string insns are special in that they only allow
11013 a single register (rDI, rSI, or rBX) as their memory address. */
11014 const reg_entry
*expected_reg
;
11015 static const char *di_si
[][2] =
11021 static const char *bx
[] = { "ebx", "bx", "rbx" };
11023 kind
= "string address";
11025 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11027 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11028 - IS_STRING_ES_OP0
;
11031 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11032 || ((!i
.mem_operands
!= !intel_syntax
)
11033 && current_templates
->end
[-1].operand_types
[1]
11034 .bitfield
.baseindex
))
11037 = (const reg_entry
*) str_hash_find (reg_hash
,
11038 di_si
[addr_mode
][op
== es_op
]);
11042 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11044 if (i
.base_reg
!= expected_reg
11046 || operand_type_check (i
.types
[this_operand
], disp
))
11048 /* The second memory operand must have the same size as
11052 && !((addr_mode
== CODE_64BIT
11053 && i
.base_reg
->reg_type
.bitfield
.qword
)
11054 || (addr_mode
== CODE_32BIT
11055 ? i
.base_reg
->reg_type
.bitfield
.dword
11056 : i
.base_reg
->reg_type
.bitfield
.word
)))
11059 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11061 intel_syntax
? '[' : '(',
11063 expected_reg
->reg_name
,
11064 intel_syntax
? ']' : ')');
11071 as_bad (_("`%s' is not a valid %s expression"),
11072 operand_string
, kind
);
11077 if (addr_mode
!= CODE_16BIT
)
11079 /* 32-bit/64-bit checks. */
11080 if (i
.disp_encoding
== disp_encoding_16bit
)
11083 as_bad (_("invalid `%s' prefix"),
11084 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11089 && ((addr_mode
== CODE_64BIT
11090 ? !i
.base_reg
->reg_type
.bitfield
.qword
11091 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11092 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11093 || i
.base_reg
->reg_num
== RegIZ
))
11095 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11096 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11097 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11098 && ((addr_mode
== CODE_64BIT
11099 ? !i
.index_reg
->reg_type
.bitfield
.qword
11100 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11101 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11104 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11105 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11106 && t
->base_opcode
== 0x0f1b)
11107 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11108 && (t
->base_opcode
& ~1) == 0x0f1a)
11109 || t
->opcode_modifier
.sib
== SIBMEM
)
11111 /* They cannot use RIP-relative addressing. */
11112 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11114 as_bad (_("`%s' cannot be used here"), operand_string
);
11118 /* bndldx and bndstx ignore their scale factor. */
11119 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11120 && (t
->base_opcode
& ~1) == 0x0f1a
11121 && i
.log2_scale_factor
)
11122 as_warn (_("register scaling is being ignored here"));
11127 /* 16-bit checks. */
11128 if (i
.disp_encoding
== disp_encoding_32bit
)
11132 && (!i
.base_reg
->reg_type
.bitfield
.word
11133 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11135 && (!i
.index_reg
->reg_type
.bitfield
.word
11136 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11138 && i
.base_reg
->reg_num
< 6
11139 && i
.index_reg
->reg_num
>= 6
11140 && i
.log2_scale_factor
== 0))))
11147 /* Handle vector immediates. */
11150 RC_SAE_immediate (const char *imm_start
)
11152 unsigned int match_found
, j
;
11153 const char *pstr
= imm_start
;
11161 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11163 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11167 rc_op
.type
= RC_NamesTable
[j
].type
;
11168 rc_op
.operand
= this_operand
;
11169 i
.rounding
= &rc_op
;
11173 as_bad (_("duplicated `%s'"), imm_start
);
11176 pstr
+= RC_NamesTable
[j
].len
;
11184 if (*pstr
++ != '}')
11186 as_bad (_("Missing '}': '%s'"), imm_start
);
11189 /* RC/SAE immediate string should contain nothing more. */;
11192 as_bad (_("Junk after '}': '%s'"), imm_start
);
11196 exp
= &im_expressions
[i
.imm_operands
++];
11197 i
.op
[this_operand
].imms
= exp
;
11199 exp
->X_op
= O_constant
;
11200 exp
->X_add_number
= 0;
11201 exp
->X_add_symbol
= (symbolS
*) 0;
11202 exp
->X_op_symbol
= (symbolS
*) 0;
11204 i
.types
[this_operand
].bitfield
.imm8
= 1;
11208 /* Only string instructions can have a second memory operand, so
11209 reduce current_templates to just those if it contains any. */
11211 maybe_adjust_templates (void)
11213 const insn_template
*t
;
11215 gas_assert (i
.mem_operands
== 1);
11217 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11218 if (t
->opcode_modifier
.isstring
)
11221 if (t
< current_templates
->end
)
11223 static templates aux_templates
;
11224 bfd_boolean recheck
;
11226 aux_templates
.start
= t
;
11227 for (; t
< current_templates
->end
; ++t
)
11228 if (!t
->opcode_modifier
.isstring
)
11230 aux_templates
.end
= t
;
11232 /* Determine whether to re-check the first memory operand. */
11233 recheck
= (aux_templates
.start
!= current_templates
->start
11234 || t
!= current_templates
->end
);
11236 current_templates
= &aux_templates
;
11240 i
.mem_operands
= 0;
11241 if (i
.memop1_string
!= NULL
11242 && i386_index_check (i
.memop1_string
) == 0)
11244 i
.mem_operands
= 1;
11251 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11255 i386_att_operand (char *operand_string
)
11257 const reg_entry
*r
;
11259 char *op_string
= operand_string
;
11261 if (is_space_char (*op_string
))
11264 /* We check for an absolute prefix (differentiating,
11265 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11266 if (*op_string
== ABSOLUTE_PREFIX
)
11269 if (is_space_char (*op_string
))
11271 i
.jumpabsolute
= TRUE
;
11274 /* Check if operand is a register. */
11275 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11277 i386_operand_type temp
;
11282 /* Check for a segment override by searching for ':' after a
11283 segment register. */
11284 op_string
= end_op
;
11285 if (is_space_char (*op_string
))
11287 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11289 switch (r
->reg_num
)
11292 i
.seg
[i
.mem_operands
] = &es
;
11295 i
.seg
[i
.mem_operands
] = &cs
;
11298 i
.seg
[i
.mem_operands
] = &ss
;
11301 i
.seg
[i
.mem_operands
] = &ds
;
11304 i
.seg
[i
.mem_operands
] = &fs
;
11307 i
.seg
[i
.mem_operands
] = &gs
;
11311 /* Skip the ':' and whitespace. */
11313 if (is_space_char (*op_string
))
11316 if (!is_digit_char (*op_string
)
11317 && !is_identifier_char (*op_string
)
11318 && *op_string
!= '('
11319 && *op_string
!= ABSOLUTE_PREFIX
)
11321 as_bad (_("bad memory operand `%s'"), op_string
);
11324 /* Handle case of %es:*foo. */
11325 if (*op_string
== ABSOLUTE_PREFIX
)
11328 if (is_space_char (*op_string
))
11330 i
.jumpabsolute
= TRUE
;
11332 goto do_memory_reference
;
11335 /* Handle vector operations. */
11336 if (*op_string
== '{')
11338 op_string
= check_VecOperations (op_string
, NULL
);
11339 if (op_string
== NULL
)
11345 as_bad (_("junk `%s' after register"), op_string
);
11348 temp
= r
->reg_type
;
11349 temp
.bitfield
.baseindex
= 0;
11350 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11352 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11353 i
.op
[this_operand
].regs
= r
;
11356 else if (*op_string
== REGISTER_PREFIX
)
11358 as_bad (_("bad register name `%s'"), op_string
);
11361 else if (*op_string
== IMMEDIATE_PREFIX
)
11364 if (i
.jumpabsolute
)
11366 as_bad (_("immediate operand illegal with absolute jump"));
11369 if (!i386_immediate (op_string
))
11372 else if (RC_SAE_immediate (operand_string
))
11374 /* If it is a RC or SAE immediate, do nothing. */
11377 else if (is_digit_char (*op_string
)
11378 || is_identifier_char (*op_string
)
11379 || *op_string
== '"'
11380 || *op_string
== '(')
11382 /* This is a memory reference of some sort. */
11385 /* Start and end of displacement string expression (if found). */
11386 char *displacement_string_start
;
11387 char *displacement_string_end
;
11390 do_memory_reference
:
11391 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11393 if ((i
.mem_operands
== 1
11394 && !current_templates
->start
->opcode_modifier
.isstring
)
11395 || i
.mem_operands
== 2)
11397 as_bad (_("too many memory references for `%s'"),
11398 current_templates
->start
->name
);
11402 /* Check for base index form. We detect the base index form by
11403 looking for an ')' at the end of the operand, searching
11404 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11406 base_string
= op_string
+ strlen (op_string
);
11408 /* Handle vector operations. */
11409 vop_start
= strchr (op_string
, '{');
11410 if (vop_start
&& vop_start
< base_string
)
11412 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11414 base_string
= vop_start
;
11418 if (is_space_char (*base_string
))
11421 /* If we only have a displacement, set-up for it to be parsed later. */
11422 displacement_string_start
= op_string
;
11423 displacement_string_end
= base_string
+ 1;
11425 if (*base_string
== ')')
11428 unsigned int parens_balanced
= 1;
11429 /* We've already checked that the number of left & right ()'s are
11430 equal, so this loop will not be infinite. */
11434 if (*base_string
== ')')
11436 if (*base_string
== '(')
11439 while (parens_balanced
);
11441 temp_string
= base_string
;
11443 /* Skip past '(' and whitespace. */
11445 if (is_space_char (*base_string
))
11448 if (*base_string
== ','
11449 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11452 displacement_string_end
= temp_string
;
11454 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11458 if (i
.base_reg
== &bad_reg
)
11460 base_string
= end_op
;
11461 if (is_space_char (*base_string
))
11465 /* There may be an index reg or scale factor here. */
11466 if (*base_string
== ',')
11469 if (is_space_char (*base_string
))
11472 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11475 if (i
.index_reg
== &bad_reg
)
11477 base_string
= end_op
;
11478 if (is_space_char (*base_string
))
11480 if (*base_string
== ',')
11483 if (is_space_char (*base_string
))
11486 else if (*base_string
!= ')')
11488 as_bad (_("expecting `,' or `)' "
11489 "after index register in `%s'"),
11494 else if (*base_string
== REGISTER_PREFIX
)
11496 end_op
= strchr (base_string
, ',');
11499 as_bad (_("bad register name `%s'"), base_string
);
11503 /* Check for scale factor. */
11504 if (*base_string
!= ')')
11506 char *end_scale
= i386_scale (base_string
);
11511 base_string
= end_scale
;
11512 if (is_space_char (*base_string
))
11514 if (*base_string
!= ')')
11516 as_bad (_("expecting `)' "
11517 "after scale factor in `%s'"),
11522 else if (!i
.index_reg
)
11524 as_bad (_("expecting index register or scale factor "
11525 "after `,'; got '%c'"),
11530 else if (*base_string
!= ')')
11532 as_bad (_("expecting `,' or `)' "
11533 "after base register in `%s'"),
11538 else if (*base_string
== REGISTER_PREFIX
)
11540 end_op
= strchr (base_string
, ',');
11543 as_bad (_("bad register name `%s'"), base_string
);
11548 /* If there's an expression beginning the operand, parse it,
11549 assuming displacement_string_start and
11550 displacement_string_end are meaningful. */
11551 if (displacement_string_start
!= displacement_string_end
)
11553 if (!i386_displacement (displacement_string_start
,
11554 displacement_string_end
))
11558 /* Special case for (%dx) while doing input/output op. */
11560 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11561 && i
.base_reg
->reg_type
.bitfield
.word
11562 && i
.index_reg
== 0
11563 && i
.log2_scale_factor
== 0
11564 && i
.seg
[i
.mem_operands
] == 0
11565 && !operand_type_check (i
.types
[this_operand
], disp
))
11567 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11571 if (i386_index_check (operand_string
) == 0)
11573 i
.flags
[this_operand
] |= Operand_Mem
;
11574 if (i
.mem_operands
== 0)
11575 i
.memop1_string
= xstrdup (operand_string
);
11580 /* It's not a memory operand; argh! */
11581 as_bad (_("invalid char %s beginning operand %d `%s'"),
11582 output_invalid (*op_string
),
11587 return 1; /* Normal return. */
11590 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11591 that an rs_machine_dependent frag may reach. */
11594 i386_frag_max_var (fragS
*frag
)
11596 /* The only relaxable frags are for jumps.
11597 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11598 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11599 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11604 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11606 /* STT_GNU_IFUNC symbol must go through PLT. */
11607 if ((symbol_get_bfdsym (fr_symbol
)->flags
11608 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11611 if (!S_IS_EXTERNAL (fr_symbol
))
11612 /* Symbol may be weak or local. */
11613 return !S_IS_WEAK (fr_symbol
);
11615 /* Global symbols with non-default visibility can't be preempted. */
11616 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11619 if (fr_var
!= NO_RELOC
)
11620 switch ((enum bfd_reloc_code_real
) fr_var
)
11622 case BFD_RELOC_386_PLT32
:
11623 case BFD_RELOC_X86_64_PLT32
:
11624 /* Symbol with PLT relocation may be preempted. */
11630 /* Global symbols with default visibility in a shared library may be
11631 preempted by another definition. */
11636 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11637 Note also work for Skylake and Cascadelake.
11638 ---------------------------------------------------------------------
11639 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11640 | ------ | ----------- | ------- | -------- |
11642 | Jno | N | N | Y |
11643 | Jc/Jb | Y | N | Y |
11644 | Jae/Jnb | Y | N | Y |
11645 | Je/Jz | Y | Y | Y |
11646 | Jne/Jnz | Y | Y | Y |
11647 | Jna/Jbe | Y | N | Y |
11648 | Ja/Jnbe | Y | N | Y |
11650 | Jns | N | N | Y |
11651 | Jp/Jpe | N | N | Y |
11652 | Jnp/Jpo | N | N | Y |
11653 | Jl/Jnge | Y | Y | Y |
11654 | Jge/Jnl | Y | Y | Y |
11655 | Jle/Jng | Y | Y | Y |
11656 | Jg/Jnle | Y | Y | Y |
11657 --------------------------------------------------------------------- */
11659 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11661 if (mf_cmp
== mf_cmp_alu_cmp
)
11662 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11663 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11664 if (mf_cmp
== mf_cmp_incdec
)
11665 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11666 || mf_jcc
== mf_jcc_jle
);
11667 if (mf_cmp
== mf_cmp_test_and
)
11672 /* Return the next non-empty frag. */
11675 i386_next_non_empty_frag (fragS
*fragP
)
11677 /* There may be a frag with a ".fill 0" when there is no room in
11678 the current frag for frag_grow in output_insn. */
11679 for (fragP
= fragP
->fr_next
;
11681 && fragP
->fr_type
== rs_fill
11682 && fragP
->fr_fix
== 0);
11683 fragP
= fragP
->fr_next
)
11688 /* Return the next jcc frag after BRANCH_PADDING. */
11691 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11693 fragS
*branch_fragP
;
11697 if (pad_fragP
->fr_type
== rs_machine_dependent
11698 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11699 == BRANCH_PADDING
))
11701 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11702 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11704 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11705 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11706 pad_fragP
->tc_frag_data
.mf_type
))
11707 return branch_fragP
;
11713 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11716 i386_classify_machine_dependent_frag (fragS
*fragP
)
11720 fragS
*branch_fragP
;
11722 unsigned int max_prefix_length
;
11724 if (fragP
->tc_frag_data
.classified
)
11727 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11728 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11729 for (next_fragP
= fragP
;
11730 next_fragP
!= NULL
;
11731 next_fragP
= next_fragP
->fr_next
)
11733 next_fragP
->tc_frag_data
.classified
= 1;
11734 if (next_fragP
->fr_type
== rs_machine_dependent
)
11735 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11737 case BRANCH_PADDING
:
11738 /* The BRANCH_PADDING frag must be followed by a branch
11740 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11741 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11743 case FUSED_JCC_PADDING
:
11744 /* Check if this is a fused jcc:
11746 CMP like instruction
11750 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11751 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11752 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11755 /* The BRANCH_PADDING frag is merged with the
11756 FUSED_JCC_PADDING frag. */
11757 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11758 /* CMP like instruction size. */
11759 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11760 frag_wane (pad_fragP
);
11761 /* Skip to branch_fragP. */
11762 next_fragP
= branch_fragP
;
11764 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11766 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11768 next_fragP
->fr_subtype
11769 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11770 next_fragP
->tc_frag_data
.max_bytes
11771 = next_fragP
->tc_frag_data
.max_prefix_length
;
11772 /* This will be updated in the BRANCH_PREFIX scan. */
11773 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11776 frag_wane (next_fragP
);
11781 /* Stop if there is no BRANCH_PREFIX. */
11782 if (!align_branch_prefix_size
)
11785 /* Scan for BRANCH_PREFIX. */
11786 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11788 if (fragP
->fr_type
!= rs_machine_dependent
11789 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11793 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11794 COND_JUMP_PREFIX. */
11795 max_prefix_length
= 0;
11796 for (next_fragP
= fragP
;
11797 next_fragP
!= NULL
;
11798 next_fragP
= next_fragP
->fr_next
)
11800 if (next_fragP
->fr_type
== rs_fill
)
11801 /* Skip rs_fill frags. */
11803 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11804 /* Stop for all other frags. */
11807 /* rs_machine_dependent frags. */
11808 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11811 /* Count BRANCH_PREFIX frags. */
11812 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11814 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11815 frag_wane (next_fragP
);
11819 += next_fragP
->tc_frag_data
.max_bytes
;
11821 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11823 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11824 == FUSED_JCC_PADDING
))
11826 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11827 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11831 /* Stop for other rs_machine_dependent frags. */
11835 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11837 /* Skip to the next frag. */
11838 fragP
= next_fragP
;
11842 /* Compute padding size for
11845 CMP like instruction
11847 COND_JUMP/UNCOND_JUMP
11852 COND_JUMP/UNCOND_JUMP
11856 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11858 unsigned int offset
, size
, padding_size
;
11859 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11861 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11863 address
= fragP
->fr_address
;
11864 address
+= fragP
->fr_fix
;
11866 /* CMP like instrunction size. */
11867 size
= fragP
->tc_frag_data
.cmp_size
;
11869 /* The base size of the branch frag. */
11870 size
+= branch_fragP
->fr_fix
;
11872 /* Add opcode and displacement bytes for the rs_machine_dependent
11874 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11875 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11877 /* Check if branch is within boundary and doesn't end at the last
11879 offset
= address
& ((1U << align_branch_power
) - 1);
11880 if ((offset
+ size
) >= (1U << align_branch_power
))
11881 /* Padding needed to avoid crossing boundary. */
11882 padding_size
= (1U << align_branch_power
) - offset
;
11884 /* No padding needed. */
11887 /* The return value may be saved in tc_frag_data.length which is
11889 if (!fits_in_unsigned_byte (padding_size
))
11892 return padding_size
;
11895 /* i386_generic_table_relax_frag()
11897 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11898 grow/shrink padding to align branch frags. Hand others to
11902 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11904 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11905 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11907 long padding_size
= i386_branch_padding_size (fragP
, 0);
11908 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11910 /* When the BRANCH_PREFIX frag is used, the computed address
11911 must match the actual address and there should be no padding. */
11912 if (fragP
->tc_frag_data
.padding_address
11913 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11917 /* Update the padding size. */
11919 fragP
->tc_frag_data
.length
= padding_size
;
11923 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11925 fragS
*padding_fragP
, *next_fragP
;
11926 long padding_size
, left_size
, last_size
;
11928 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11929 if (!padding_fragP
)
11930 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11931 return (fragP
->tc_frag_data
.length
11932 - fragP
->tc_frag_data
.last_length
);
11934 /* Compute the relative address of the padding frag in the very
11935 first time where the BRANCH_PREFIX frag sizes are zero. */
11936 if (!fragP
->tc_frag_data
.padding_address
)
11937 fragP
->tc_frag_data
.padding_address
11938 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11940 /* First update the last length from the previous interation. */
11941 left_size
= fragP
->tc_frag_data
.prefix_length
;
11942 for (next_fragP
= fragP
;
11943 next_fragP
!= padding_fragP
;
11944 next_fragP
= next_fragP
->fr_next
)
11945 if (next_fragP
->fr_type
== rs_machine_dependent
11946 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11951 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11955 if (max
> left_size
)
11960 next_fragP
->tc_frag_data
.last_length
= size
;
11964 next_fragP
->tc_frag_data
.last_length
= 0;
11967 /* Check the padding size for the padding frag. */
11968 padding_size
= i386_branch_padding_size
11969 (padding_fragP
, (fragP
->fr_address
11970 + fragP
->tc_frag_data
.padding_address
));
11972 last_size
= fragP
->tc_frag_data
.prefix_length
;
11973 /* Check if there is change from the last interation. */
11974 if (padding_size
== last_size
)
11976 /* Update the expected address of the padding frag. */
11977 padding_fragP
->tc_frag_data
.padding_address
11978 = (fragP
->fr_address
+ padding_size
11979 + fragP
->tc_frag_data
.padding_address
);
11983 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11985 /* No padding if there is no sufficient room. Clear the
11986 expected address of the padding frag. */
11987 padding_fragP
->tc_frag_data
.padding_address
= 0;
11991 /* Store the expected address of the padding frag. */
11992 padding_fragP
->tc_frag_data
.padding_address
11993 = (fragP
->fr_address
+ padding_size
11994 + fragP
->tc_frag_data
.padding_address
);
11996 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11998 /* Update the length for the current interation. */
11999 left_size
= padding_size
;
12000 for (next_fragP
= fragP
;
12001 next_fragP
!= padding_fragP
;
12002 next_fragP
= next_fragP
->fr_next
)
12003 if (next_fragP
->fr_type
== rs_machine_dependent
12004 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12009 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12013 if (max
> left_size
)
12018 next_fragP
->tc_frag_data
.length
= size
;
12022 next_fragP
->tc_frag_data
.length
= 0;
12025 return (fragP
->tc_frag_data
.length
12026 - fragP
->tc_frag_data
.last_length
);
12028 return relax_frag (segment
, fragP
, stretch
);
12031 /* md_estimate_size_before_relax()
12033 Called just before relax() for rs_machine_dependent frags. The x86
12034 assembler uses these frags to handle variable size jump
12037 Any symbol that is now undefined will not become defined.
12038 Return the correct fr_subtype in the frag.
12039 Return the initial "guess for variable size of frag" to caller.
12040 The guess is actually the growth beyond the fixed part. Whatever
12041 we do to grow the fixed or variable part contributes to our
12045 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12047 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12048 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12049 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12051 i386_classify_machine_dependent_frag (fragP
);
12052 return fragP
->tc_frag_data
.length
;
12055 /* We've already got fragP->fr_subtype right; all we have to do is
12056 check for un-relaxable symbols. On an ELF system, we can't relax
12057 an externally visible symbol, because it may be overridden by a
12059 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12060 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12062 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12065 #if defined (OBJ_COFF) && defined (TE_PE)
12066 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12067 && S_IS_WEAK (fragP
->fr_symbol
))
12071 /* Symbol is undefined in this segment, or we need to keep a
12072 reloc so that weak symbols can be overridden. */
12073 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12074 enum bfd_reloc_code_real reloc_type
;
12075 unsigned char *opcode
;
12078 if (fragP
->fr_var
!= NO_RELOC
)
12079 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12080 else if (size
== 2)
12081 reloc_type
= BFD_RELOC_16_PCREL
;
12082 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12083 else if (need_plt32_p (fragP
->fr_symbol
))
12084 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12087 reloc_type
= BFD_RELOC_32_PCREL
;
12089 old_fr_fix
= fragP
->fr_fix
;
12090 opcode
= (unsigned char *) fragP
->fr_opcode
;
12092 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12095 /* Make jmp (0xeb) a (d)word displacement jump. */
12097 fragP
->fr_fix
+= size
;
12098 fix_new (fragP
, old_fr_fix
, size
,
12100 fragP
->fr_offset
, 1,
12106 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12108 /* Negate the condition, and branch past an
12109 unconditional jump. */
12112 /* Insert an unconditional jump. */
12114 /* We added two extra opcode bytes, and have a two byte
12116 fragP
->fr_fix
+= 2 + 2;
12117 fix_new (fragP
, old_fr_fix
+ 2, 2,
12119 fragP
->fr_offset
, 1,
12123 /* Fall through. */
12126 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12130 fragP
->fr_fix
+= 1;
12131 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12133 fragP
->fr_offset
, 1,
12134 BFD_RELOC_8_PCREL
);
12135 fixP
->fx_signed
= 1;
12139 /* This changes the byte-displacement jump 0x7N
12140 to the (d)word-displacement jump 0x0f,0x8N. */
12141 opcode
[1] = opcode
[0] + 0x10;
12142 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12143 /* We've added an opcode byte. */
12144 fragP
->fr_fix
+= 1 + size
;
12145 fix_new (fragP
, old_fr_fix
+ 1, size
,
12147 fragP
->fr_offset
, 1,
12152 BAD_CASE (fragP
->fr_subtype
);
12156 return fragP
->fr_fix
- old_fr_fix
;
12159 /* Guess size depending on current relax state. Initially the relax
12160 state will correspond to a short jump and we return 1, because
12161 the variable part of the frag (the branch offset) is one byte
12162 long. However, we can relax a section more than once and in that
12163 case we must either set fr_subtype back to the unrelaxed state,
12164 or return the value for the appropriate branch. */
12165 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12168 /* Called after relax() is finished.
12170 In: Address of frag.
12171 fr_type == rs_machine_dependent.
12172 fr_subtype is what the address relaxed to.
12174 Out: Any fixSs and constants are set up.
12175 Caller will turn frag into a ".space 0". */
12178 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12181 unsigned char *opcode
;
12182 unsigned char *where_to_put_displacement
= NULL
;
12183 offsetT target_address
;
12184 offsetT opcode_address
;
12185 unsigned int extension
= 0;
12186 offsetT displacement_from_opcode_start
;
12188 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12189 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12190 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12192 /* Generate nop padding. */
12193 unsigned int size
= fragP
->tc_frag_data
.length
;
12196 if (size
> fragP
->tc_frag_data
.max_bytes
)
12202 const char *branch
= "branch";
12203 const char *prefix
= "";
12204 fragS
*padding_fragP
;
12205 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12208 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12209 switch (fragP
->tc_frag_data
.default_prefix
)
12214 case CS_PREFIX_OPCODE
:
12217 case DS_PREFIX_OPCODE
:
12220 case ES_PREFIX_OPCODE
:
12223 case FS_PREFIX_OPCODE
:
12226 case GS_PREFIX_OPCODE
:
12229 case SS_PREFIX_OPCODE
:
12234 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12235 "%s within %d-byte boundary\n");
12237 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12238 "align %s within %d-byte boundary\n");
12242 padding_fragP
= fragP
;
12243 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12244 "%s within %d-byte boundary\n");
12248 switch (padding_fragP
->tc_frag_data
.branch_type
)
12250 case align_branch_jcc
:
12253 case align_branch_fused
:
12254 branch
= "fused jcc";
12256 case align_branch_jmp
:
12259 case align_branch_call
:
12262 case align_branch_indirect
:
12263 branch
= "indiret branch";
12265 case align_branch_ret
:
12272 fprintf (stdout
, msg
,
12273 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12274 (long long) fragP
->fr_address
, branch
,
12275 1 << align_branch_power
);
12277 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12278 memset (fragP
->fr_opcode
,
12279 fragP
->tc_frag_data
.default_prefix
, size
);
12281 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12283 fragP
->fr_fix
+= size
;
12288 opcode
= (unsigned char *) fragP
->fr_opcode
;
12290 /* Address we want to reach in file space. */
12291 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12293 /* Address opcode resides at in file space. */
12294 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12296 /* Displacement from opcode start to fill into instruction. */
12297 displacement_from_opcode_start
= target_address
- opcode_address
;
12299 if ((fragP
->fr_subtype
& BIG
) == 0)
12301 /* Don't have to change opcode. */
12302 extension
= 1; /* 1 opcode + 1 displacement */
12303 where_to_put_displacement
= &opcode
[1];
12307 if (no_cond_jump_promotion
12308 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12309 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12310 _("long jump required"));
12312 switch (fragP
->fr_subtype
)
12314 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12315 extension
= 4; /* 1 opcode + 4 displacement */
12317 where_to_put_displacement
= &opcode
[1];
12320 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12321 extension
= 2; /* 1 opcode + 2 displacement */
12323 where_to_put_displacement
= &opcode
[1];
12326 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12327 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12328 extension
= 5; /* 2 opcode + 4 displacement */
12329 opcode
[1] = opcode
[0] + 0x10;
12330 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12331 where_to_put_displacement
= &opcode
[2];
12334 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12335 extension
= 3; /* 2 opcode + 2 displacement */
12336 opcode
[1] = opcode
[0] + 0x10;
12337 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12338 where_to_put_displacement
= &opcode
[2];
12341 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12346 where_to_put_displacement
= &opcode
[3];
12350 BAD_CASE (fragP
->fr_subtype
);
12355 /* If size if less then four we are sure that the operand fits,
12356 but if it's 4, then it could be that the displacement is larger
12358 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12360 && ((addressT
) (displacement_from_opcode_start
- extension
12361 + ((addressT
) 1 << 31))
12362 > (((addressT
) 2 << 31) - 1)))
12364 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12365 _("jump target out of range"));
12366 /* Make us emit 0. */
12367 displacement_from_opcode_start
= extension
;
12369 /* Now put displacement after opcode. */
12370 md_number_to_chars ((char *) where_to_put_displacement
,
12371 (valueT
) (displacement_from_opcode_start
- extension
),
12372 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12373 fragP
->fr_fix
+= extension
;
12376 /* Apply a fixup (fixP) to segment data, once it has been determined
12377 by our caller that we have all the info we need to fix it up.
12379 Parameter valP is the pointer to the value of the bits.
12381 On the 386, immediates, displacements, and data pointers are all in
12382 the same (little-endian) format, so we don't need to care about which
12383 we are handling. */
12386 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12388 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12389 valueT value
= *valP
;
12391 #if !defined (TE_Mach)
12392 if (fixP
->fx_pcrel
)
12394 switch (fixP
->fx_r_type
)
12400 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12403 case BFD_RELOC_X86_64_32S
:
12404 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12407 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12410 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12415 if (fixP
->fx_addsy
!= NULL
12416 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12417 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12418 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12419 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12420 && !use_rela_relocations
)
12422 /* This is a hack. There should be a better way to handle this.
12423 This covers for the fact that bfd_install_relocation will
12424 subtract the current location (for partial_inplace, PC relative
12425 relocations); see more below. */
12429 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12432 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12434 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12437 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12439 if ((sym_seg
== seg
12440 || (symbol_section_p (fixP
->fx_addsy
)
12441 && sym_seg
!= absolute_section
))
12442 && !generic_force_reloc (fixP
))
12444 /* Yes, we add the values in twice. This is because
12445 bfd_install_relocation subtracts them out again. I think
12446 bfd_install_relocation is broken, but I don't dare change
12448 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12452 #if defined (OBJ_COFF) && defined (TE_PE)
12453 /* For some reason, the PE format does not store a
12454 section address offset for a PC relative symbol. */
12455 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12456 || S_IS_WEAK (fixP
->fx_addsy
))
12457 value
+= md_pcrel_from (fixP
);
12460 #if defined (OBJ_COFF) && defined (TE_PE)
12461 if (fixP
->fx_addsy
!= NULL
12462 && S_IS_WEAK (fixP
->fx_addsy
)
12463 /* PR 16858: Do not modify weak function references. */
12464 && ! fixP
->fx_pcrel
)
12466 #if !defined (TE_PEP)
12467 /* For x86 PE weak function symbols are neither PC-relative
12468 nor do they set S_IS_FUNCTION. So the only reliable way
12469 to detect them is to check the flags of their containing
12471 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12472 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12476 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12480 /* Fix a few things - the dynamic linker expects certain values here,
12481 and we must not disappoint it. */
12482 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12483 if (IS_ELF
&& fixP
->fx_addsy
)
12484 switch (fixP
->fx_r_type
)
12486 case BFD_RELOC_386_PLT32
:
12487 case BFD_RELOC_X86_64_PLT32
:
12488 /* Make the jump instruction point to the address of the operand.
12489 At runtime we merely add the offset to the actual PLT entry.
12490 NB: Subtract the offset size only for jump instructions. */
12491 if (fixP
->fx_pcrel
)
12495 case BFD_RELOC_386_TLS_GD
:
12496 case BFD_RELOC_386_TLS_LDM
:
12497 case BFD_RELOC_386_TLS_IE_32
:
12498 case BFD_RELOC_386_TLS_IE
:
12499 case BFD_RELOC_386_TLS_GOTIE
:
12500 case BFD_RELOC_386_TLS_GOTDESC
:
12501 case BFD_RELOC_X86_64_TLSGD
:
12502 case BFD_RELOC_X86_64_TLSLD
:
12503 case BFD_RELOC_X86_64_GOTTPOFF
:
12504 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12505 value
= 0; /* Fully resolved at runtime. No addend. */
12507 case BFD_RELOC_386_TLS_LE
:
12508 case BFD_RELOC_386_TLS_LDO_32
:
12509 case BFD_RELOC_386_TLS_LE_32
:
12510 case BFD_RELOC_X86_64_DTPOFF32
:
12511 case BFD_RELOC_X86_64_DTPOFF64
:
12512 case BFD_RELOC_X86_64_TPOFF32
:
12513 case BFD_RELOC_X86_64_TPOFF64
:
12514 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12517 case BFD_RELOC_386_TLS_DESC_CALL
:
12518 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12519 value
= 0; /* Fully resolved at runtime. No addend. */
12520 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12524 case BFD_RELOC_VTABLE_INHERIT
:
12525 case BFD_RELOC_VTABLE_ENTRY
:
12532 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12534 #endif /* !defined (TE_Mach) */
12536 /* Are we finished with this relocation now? */
12537 if (fixP
->fx_addsy
== NULL
)
12539 #if defined (OBJ_COFF) && defined (TE_PE)
12540 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12543 /* Remember value for tc_gen_reloc. */
12544 fixP
->fx_addnumber
= value
;
12545 /* Clear out the frag for now. */
12549 else if (use_rela_relocations
)
12551 fixP
->fx_no_overflow
= 1;
12552 /* Remember value for tc_gen_reloc. */
12553 fixP
->fx_addnumber
= value
;
12557 md_number_to_chars (p
, value
, fixP
->fx_size
);
12561 md_atof (int type
, char *litP
, int *sizeP
)
12563 /* This outputs the LITTLENUMs in REVERSE order;
12564 in accord with the bigendian 386. */
12565 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12568 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12571 output_invalid (int c
)
12574 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12577 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12578 "(0x%x)", (unsigned char) c
);
12579 return output_invalid_buf
;
12582 /* Verify that @r can be used in the current context. */
12584 static bfd_boolean
check_register (const reg_entry
*r
)
12586 if (allow_pseudo_reg
)
12589 if (operand_type_all_zero (&r
->reg_type
))
12592 if ((r
->reg_type
.bitfield
.dword
12593 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12594 || r
->reg_type
.bitfield
.class == RegCR
12595 || r
->reg_type
.bitfield
.class == RegDR
)
12596 && !cpu_arch_flags
.bitfield
.cpui386
)
12599 if (r
->reg_type
.bitfield
.class == RegTR
12600 && (flag_code
== CODE_64BIT
12601 || !cpu_arch_flags
.bitfield
.cpui386
12602 || cpu_arch_isa_flags
.bitfield
.cpui586
12603 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12606 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12609 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12611 if (r
->reg_type
.bitfield
.zmmword
12612 || r
->reg_type
.bitfield
.class == RegMask
)
12615 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12617 if (r
->reg_type
.bitfield
.ymmword
)
12620 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12625 if (r
->reg_type
.bitfield
.tmmword
12626 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12627 || flag_code
!= CODE_64BIT
))
12630 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12633 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12634 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12637 /* Upper 16 vector registers are only available with VREX in 64bit
12638 mode, and require EVEX encoding. */
12639 if (r
->reg_flags
& RegVRex
)
12641 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12642 || flag_code
!= CODE_64BIT
)
12645 if (i
.vec_encoding
== vex_encoding_default
)
12646 i
.vec_encoding
= vex_encoding_evex
;
12647 else if (i
.vec_encoding
!= vex_encoding_evex
)
12648 i
.vec_encoding
= vex_encoding_error
;
12651 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12652 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12653 && flag_code
!= CODE_64BIT
)
12656 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12663 /* REG_STRING starts *before* REGISTER_PREFIX. */
12665 static const reg_entry
*
12666 parse_real_register (char *reg_string
, char **end_op
)
12668 char *s
= reg_string
;
12670 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12671 const reg_entry
*r
;
12673 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12674 if (*s
== REGISTER_PREFIX
)
12677 if (is_space_char (*s
))
12680 p
= reg_name_given
;
12681 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12683 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12684 return (const reg_entry
*) NULL
;
12688 /* For naked regs, make sure that we are not dealing with an identifier.
12689 This prevents confusing an identifier like `eax_var' with register
12691 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12692 return (const reg_entry
*) NULL
;
12696 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12698 /* Handle floating point regs, allowing spaces in the (i) part. */
12699 if (r
== i386_regtab
/* %st is first entry of table */)
12701 if (!cpu_arch_flags
.bitfield
.cpu8087
12702 && !cpu_arch_flags
.bitfield
.cpu287
12703 && !cpu_arch_flags
.bitfield
.cpu387
12704 && !allow_pseudo_reg
)
12705 return (const reg_entry
*) NULL
;
12707 if (is_space_char (*s
))
12712 if (is_space_char (*s
))
12714 if (*s
>= '0' && *s
<= '7')
12716 int fpr
= *s
- '0';
12718 if (is_space_char (*s
))
12723 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12728 /* We have "%st(" then garbage. */
12729 return (const reg_entry
*) NULL
;
12733 return r
&& check_register (r
) ? r
: NULL
;
12736 /* REG_STRING starts *before* REGISTER_PREFIX. */
12738 static const reg_entry
*
12739 parse_register (char *reg_string
, char **end_op
)
12741 const reg_entry
*r
;
12743 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12744 r
= parse_real_register (reg_string
, end_op
);
12749 char *save
= input_line_pointer
;
12753 input_line_pointer
= reg_string
;
12754 c
= get_symbol_name (®_string
);
12755 symbolP
= symbol_find (reg_string
);
12756 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12758 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12760 know (e
->X_op
== O_register
);
12761 know (e
->X_add_number
>= 0
12762 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12763 r
= i386_regtab
+ e
->X_add_number
;
12764 if (!check_register (r
))
12766 as_bad (_("register '%s%s' cannot be used here"),
12767 register_prefix
, r
->reg_name
);
12770 *end_op
= input_line_pointer
;
12772 *input_line_pointer
= c
;
12773 input_line_pointer
= save
;
12779 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12781 const reg_entry
*r
;
12782 char *end
= input_line_pointer
;
12785 r
= parse_register (name
, &input_line_pointer
);
12786 if (r
&& end
<= input_line_pointer
)
12788 *nextcharP
= *input_line_pointer
;
12789 *input_line_pointer
= 0;
12792 e
->X_op
= O_register
;
12793 e
->X_add_number
= r
- i386_regtab
;
12796 e
->X_op
= O_illegal
;
12799 input_line_pointer
= end
;
12801 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12805 md_operand (expressionS
*e
)
12808 const reg_entry
*r
;
12810 switch (*input_line_pointer
)
12812 case REGISTER_PREFIX
:
12813 r
= parse_real_register (input_line_pointer
, &end
);
12816 e
->X_op
= O_register
;
12817 e
->X_add_number
= r
- i386_regtab
;
12818 input_line_pointer
= end
;
12823 gas_assert (intel_syntax
);
12824 end
= input_line_pointer
++;
12826 if (*input_line_pointer
== ']')
12828 ++input_line_pointer
;
12829 e
->X_op_symbol
= make_expr_symbol (e
);
12830 e
->X_add_symbol
= NULL
;
12831 e
->X_add_number
= 0;
12836 e
->X_op
= O_absent
;
12837 input_line_pointer
= end
;
12844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12845 const char *md_shortopts
= "kVQ:sqnO::";
12847 const char *md_shortopts
= "qnO::";
12850 #define OPTION_32 (OPTION_MD_BASE + 0)
12851 #define OPTION_64 (OPTION_MD_BASE + 1)
12852 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12853 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12854 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12855 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12856 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12857 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12858 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12859 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12860 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12861 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12862 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12863 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12864 #define OPTION_X32 (OPTION_MD_BASE + 14)
12865 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12866 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12867 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12868 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12869 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12870 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12871 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12872 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12873 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12874 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12875 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12876 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12877 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12878 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12879 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12880 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12881 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12882 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12883 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12885 struct option md_longopts
[] =
12887 {"32", no_argument
, NULL
, OPTION_32
},
12888 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12889 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12890 {"64", no_argument
, NULL
, OPTION_64
},
12892 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12893 {"x32", no_argument
, NULL
, OPTION_X32
},
12894 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12895 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12897 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12898 {"march", required_argument
, NULL
, OPTION_MARCH
},
12899 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12900 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12901 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12902 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12903 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12904 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12905 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12906 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12907 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12908 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12909 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12910 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12911 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12912 # if defined (TE_PE) || defined (TE_PEP)
12913 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12915 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12916 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12917 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12918 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12919 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12920 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12921 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12922 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12923 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12924 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12925 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12926 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12927 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12928 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12929 {NULL
, no_argument
, NULL
, 0}
12931 size_t md_longopts_size
= sizeof (md_longopts
);
12934 md_parse_option (int c
, const char *arg
)
12937 char *arch
, *next
, *saved
, *type
;
12942 optimize_align_code
= 0;
12946 quiet_warnings
= 1;
12949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12950 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12951 should be emitted or not. FIXME: Not implemented. */
12953 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12957 /* -V: SVR4 argument to print version ID. */
12959 print_version_id ();
12962 /* -k: Ignore for FreeBSD compatibility. */
12967 /* -s: On i386 Solaris, this tells the native assembler to use
12968 .stab instead of .stab.excl. We always use .stab anyhow. */
12971 case OPTION_MSHARED
:
12975 case OPTION_X86_USED_NOTE
:
12976 if (strcasecmp (arg
, "yes") == 0)
12978 else if (strcasecmp (arg
, "no") == 0)
12981 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12986 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12987 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12990 const char **list
, **l
;
12992 list
= bfd_target_list ();
12993 for (l
= list
; *l
!= NULL
; l
++)
12994 if (startswith (*l
, "elf64-x86-64")
12995 || strcmp (*l
, "coff-x86-64") == 0
12996 || strcmp (*l
, "pe-x86-64") == 0
12997 || strcmp (*l
, "pei-x86-64") == 0
12998 || strcmp (*l
, "mach-o-x86-64") == 0)
13000 default_arch
= "x86_64";
13004 as_fatal (_("no compiled in support for x86_64"));
13010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13014 const char **list
, **l
;
13016 list
= bfd_target_list ();
13017 for (l
= list
; *l
!= NULL
; l
++)
13018 if (startswith (*l
, "elf32-x86-64"))
13020 default_arch
= "x86_64:32";
13024 as_fatal (_("no compiled in support for 32bit x86_64"));
13028 as_fatal (_("32bit x86_64 is only supported for ELF"));
13033 default_arch
= "i386";
13036 case OPTION_DIVIDE
:
13037 #ifdef SVR4_COMMENT_CHARS
13042 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13044 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13048 i386_comment_chars
= n
;
13054 saved
= xstrdup (arg
);
13056 /* Allow -march=+nosse. */
13062 as_fatal (_("invalid -march= option: `%s'"), arg
);
13063 next
= strchr (arch
, '+');
13066 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13068 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13071 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13074 cpu_arch_name
= cpu_arch
[j
].name
;
13075 cpu_sub_arch_name
= NULL
;
13076 cpu_arch_flags
= cpu_arch
[j
].flags
;
13077 cpu_arch_isa
= cpu_arch
[j
].type
;
13078 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13079 if (!cpu_arch_tune_set
)
13081 cpu_arch_tune
= cpu_arch_isa
;
13082 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13086 else if (*cpu_arch
[j
].name
== '.'
13087 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13089 /* ISA extension. */
13090 i386_cpu_flags flags
;
13092 flags
= cpu_flags_or (cpu_arch_flags
,
13093 cpu_arch
[j
].flags
);
13095 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13097 if (cpu_sub_arch_name
)
13099 char *name
= cpu_sub_arch_name
;
13100 cpu_sub_arch_name
= concat (name
,
13102 (const char *) NULL
);
13106 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13107 cpu_arch_flags
= flags
;
13108 cpu_arch_isa_flags
= flags
;
13112 = cpu_flags_or (cpu_arch_isa_flags
,
13113 cpu_arch
[j
].flags
);
13118 if (j
>= ARRAY_SIZE (cpu_arch
))
13120 /* Disable an ISA extension. */
13121 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13122 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13124 i386_cpu_flags flags
;
13126 flags
= cpu_flags_and_not (cpu_arch_flags
,
13127 cpu_noarch
[j
].flags
);
13128 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13130 if (cpu_sub_arch_name
)
13132 char *name
= cpu_sub_arch_name
;
13133 cpu_sub_arch_name
= concat (arch
,
13134 (const char *) NULL
);
13138 cpu_sub_arch_name
= xstrdup (arch
);
13139 cpu_arch_flags
= flags
;
13140 cpu_arch_isa_flags
= flags
;
13145 if (j
>= ARRAY_SIZE (cpu_noarch
))
13146 j
= ARRAY_SIZE (cpu_arch
);
13149 if (j
>= ARRAY_SIZE (cpu_arch
))
13150 as_fatal (_("invalid -march= option: `%s'"), arg
);
13154 while (next
!= NULL
);
13160 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13161 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13163 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13165 cpu_arch_tune_set
= 1;
13166 cpu_arch_tune
= cpu_arch
[j
].type
;
13167 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13171 if (j
>= ARRAY_SIZE (cpu_arch
))
13172 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13175 case OPTION_MMNEMONIC
:
13176 if (strcasecmp (arg
, "att") == 0)
13177 intel_mnemonic
= 0;
13178 else if (strcasecmp (arg
, "intel") == 0)
13179 intel_mnemonic
= 1;
13181 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13184 case OPTION_MSYNTAX
:
13185 if (strcasecmp (arg
, "att") == 0)
13187 else if (strcasecmp (arg
, "intel") == 0)
13190 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13193 case OPTION_MINDEX_REG
:
13194 allow_index_reg
= 1;
13197 case OPTION_MNAKED_REG
:
13198 allow_naked_reg
= 1;
13201 case OPTION_MSSE2AVX
:
13205 case OPTION_MSSE_CHECK
:
13206 if (strcasecmp (arg
, "error") == 0)
13207 sse_check
= check_error
;
13208 else if (strcasecmp (arg
, "warning") == 0)
13209 sse_check
= check_warning
;
13210 else if (strcasecmp (arg
, "none") == 0)
13211 sse_check
= check_none
;
13213 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13216 case OPTION_MOPERAND_CHECK
:
13217 if (strcasecmp (arg
, "error") == 0)
13218 operand_check
= check_error
;
13219 else if (strcasecmp (arg
, "warning") == 0)
13220 operand_check
= check_warning
;
13221 else if (strcasecmp (arg
, "none") == 0)
13222 operand_check
= check_none
;
13224 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13227 case OPTION_MAVXSCALAR
:
13228 if (strcasecmp (arg
, "128") == 0)
13229 avxscalar
= vex128
;
13230 else if (strcasecmp (arg
, "256") == 0)
13231 avxscalar
= vex256
;
13233 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13236 case OPTION_MVEXWIG
:
13237 if (strcmp (arg
, "0") == 0)
13239 else if (strcmp (arg
, "1") == 0)
13242 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13245 case OPTION_MADD_BND_PREFIX
:
13246 add_bnd_prefix
= 1;
13249 case OPTION_MEVEXLIG
:
13250 if (strcmp (arg
, "128") == 0)
13251 evexlig
= evexl128
;
13252 else if (strcmp (arg
, "256") == 0)
13253 evexlig
= evexl256
;
13254 else if (strcmp (arg
, "512") == 0)
13255 evexlig
= evexl512
;
13257 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13260 case OPTION_MEVEXRCIG
:
13261 if (strcmp (arg
, "rne") == 0)
13263 else if (strcmp (arg
, "rd") == 0)
13265 else if (strcmp (arg
, "ru") == 0)
13267 else if (strcmp (arg
, "rz") == 0)
13270 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13273 case OPTION_MEVEXWIG
:
13274 if (strcmp (arg
, "0") == 0)
13276 else if (strcmp (arg
, "1") == 0)
13279 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13282 # if defined (TE_PE) || defined (TE_PEP)
13283 case OPTION_MBIG_OBJ
:
13288 case OPTION_MOMIT_LOCK_PREFIX
:
13289 if (strcasecmp (arg
, "yes") == 0)
13290 omit_lock_prefix
= 1;
13291 else if (strcasecmp (arg
, "no") == 0)
13292 omit_lock_prefix
= 0;
13294 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13297 case OPTION_MFENCE_AS_LOCK_ADD
:
13298 if (strcasecmp (arg
, "yes") == 0)
13300 else if (strcasecmp (arg
, "no") == 0)
13303 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13306 case OPTION_MLFENCE_AFTER_LOAD
:
13307 if (strcasecmp (arg
, "yes") == 0)
13308 lfence_after_load
= 1;
13309 else if (strcasecmp (arg
, "no") == 0)
13310 lfence_after_load
= 0;
13312 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13315 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13316 if (strcasecmp (arg
, "all") == 0)
13318 lfence_before_indirect_branch
= lfence_branch_all
;
13319 if (lfence_before_ret
== lfence_before_ret_none
)
13320 lfence_before_ret
= lfence_before_ret_shl
;
13322 else if (strcasecmp (arg
, "memory") == 0)
13323 lfence_before_indirect_branch
= lfence_branch_memory
;
13324 else if (strcasecmp (arg
, "register") == 0)
13325 lfence_before_indirect_branch
= lfence_branch_register
;
13326 else if (strcasecmp (arg
, "none") == 0)
13327 lfence_before_indirect_branch
= lfence_branch_none
;
13329 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13333 case OPTION_MLFENCE_BEFORE_RET
:
13334 if (strcasecmp (arg
, "or") == 0)
13335 lfence_before_ret
= lfence_before_ret_or
;
13336 else if (strcasecmp (arg
, "not") == 0)
13337 lfence_before_ret
= lfence_before_ret_not
;
13338 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13339 lfence_before_ret
= lfence_before_ret_shl
;
13340 else if (strcasecmp (arg
, "none") == 0)
13341 lfence_before_ret
= lfence_before_ret_none
;
13343 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13347 case OPTION_MRELAX_RELOCATIONS
:
13348 if (strcasecmp (arg
, "yes") == 0)
13349 generate_relax_relocations
= 1;
13350 else if (strcasecmp (arg
, "no") == 0)
13351 generate_relax_relocations
= 0;
13353 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13356 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13359 long int align
= strtoul (arg
, &end
, 0);
13364 align_branch_power
= 0;
13367 else if (align
>= 16)
13370 for (align_power
= 0;
13372 align
>>= 1, align_power
++)
13374 /* Limit alignment power to 31. */
13375 if (align
== 1 && align_power
< 32)
13377 align_branch_power
= align_power
;
13382 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13386 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13389 int align
= strtoul (arg
, &end
, 0);
13390 /* Some processors only support 5 prefixes. */
13391 if (*end
== '\0' && align
>= 0 && align
< 6)
13393 align_branch_prefix_size
= align
;
13396 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13401 case OPTION_MALIGN_BRANCH
:
13403 saved
= xstrdup (arg
);
13407 next
= strchr (type
, '+');
13410 if (strcasecmp (type
, "jcc") == 0)
13411 align_branch
|= align_branch_jcc_bit
;
13412 else if (strcasecmp (type
, "fused") == 0)
13413 align_branch
|= align_branch_fused_bit
;
13414 else if (strcasecmp (type
, "jmp") == 0)
13415 align_branch
|= align_branch_jmp_bit
;
13416 else if (strcasecmp (type
, "call") == 0)
13417 align_branch
|= align_branch_call_bit
;
13418 else if (strcasecmp (type
, "ret") == 0)
13419 align_branch
|= align_branch_ret_bit
;
13420 else if (strcasecmp (type
, "indirect") == 0)
13421 align_branch
|= align_branch_indirect_bit
;
13423 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13426 while (next
!= NULL
);
13430 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13431 align_branch_power
= 5;
13432 align_branch_prefix_size
= 5;
13433 align_branch
= (align_branch_jcc_bit
13434 | align_branch_fused_bit
13435 | align_branch_jmp_bit
);
13438 case OPTION_MAMD64
:
13442 case OPTION_MINTEL64
:
13450 /* Turn off -Os. */
13451 optimize_for_space
= 0;
13453 else if (*arg
== 's')
13455 optimize_for_space
= 1;
13456 /* Turn on all encoding optimizations. */
13457 optimize
= INT_MAX
;
13461 optimize
= atoi (arg
);
13462 /* Turn off -Os. */
13463 optimize_for_space
= 0;
13473 #define MESSAGE_TEMPLATE \
13477 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13478 int *left_p
, const char *name
, int len
)
13480 int size
= sizeof (MESSAGE_TEMPLATE
);
13481 int left
= *left_p
;
13483 /* Reserve 2 spaces for ", " or ",\0" */
13486 /* Check if there is any room. */
13494 p
= mempcpy (p
, name
, len
);
13498 /* Output the current message now and start a new one. */
13501 fprintf (stream
, "%s\n", message
);
13503 left
= size
- (start
- message
) - len
- 2;
13505 gas_assert (left
>= 0);
13507 p
= mempcpy (p
, name
, len
);
13515 show_arch (FILE *stream
, int ext
, int check
)
13517 static char message
[] = MESSAGE_TEMPLATE
;
13518 char *start
= message
+ 27;
13520 int size
= sizeof (MESSAGE_TEMPLATE
);
13527 left
= size
- (start
- message
);
13528 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13530 /* Should it be skipped? */
13531 if (cpu_arch
[j
].skip
)
13534 name
= cpu_arch
[j
].name
;
13535 len
= cpu_arch
[j
].len
;
13538 /* It is an extension. Skip if we aren't asked to show it. */
13549 /* It is an processor. Skip if we show only extension. */
13552 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13554 /* It is an impossible processor - skip. */
13558 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13561 /* Display disabled extensions. */
13563 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13565 name
= cpu_noarch
[j
].name
;
13566 len
= cpu_noarch
[j
].len
;
13567 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13572 fprintf (stream
, "%s\n", message
);
13576 md_show_usage (FILE *stream
)
13578 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13579 fprintf (stream
, _("\
13580 -Qy, -Qn ignored\n\
13581 -V print assembler version number\n\
13584 fprintf (stream
, _("\
13585 -n Do not optimize code alignment\n\
13586 -q quieten some warnings\n"));
13587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13588 fprintf (stream
, _("\
13591 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13592 || defined (TE_PE) || defined (TE_PEP))
13593 fprintf (stream
, _("\
13594 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13596 #ifdef SVR4_COMMENT_CHARS
13597 fprintf (stream
, _("\
13598 --divide do not treat `/' as a comment character\n"));
13600 fprintf (stream
, _("\
13601 --divide ignored\n"));
13603 fprintf (stream
, _("\
13604 -march=CPU[,+EXTENSION...]\n\
13605 generate code for CPU and EXTENSION, CPU is one of:\n"));
13606 show_arch (stream
, 0, 1);
13607 fprintf (stream
, _("\
13608 EXTENSION is combination of:\n"));
13609 show_arch (stream
, 1, 0);
13610 fprintf (stream
, _("\
13611 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13612 show_arch (stream
, 0, 0);
13613 fprintf (stream
, _("\
13614 -msse2avx encode SSE instructions with VEX prefix\n"));
13615 fprintf (stream
, _("\
13616 -msse-check=[none|error|warning] (default: warning)\n\
13617 check SSE instructions\n"));
13618 fprintf (stream
, _("\
13619 -moperand-check=[none|error|warning] (default: warning)\n\
13620 check operand combinations for validity\n"));
13621 fprintf (stream
, _("\
13622 -mavxscalar=[128|256] (default: 128)\n\
13623 encode scalar AVX instructions with specific vector\n\
13625 fprintf (stream
, _("\
13626 -mvexwig=[0|1] (default: 0)\n\
13627 encode VEX instructions with specific VEX.W value\n\
13628 for VEX.W bit ignored instructions\n"));
13629 fprintf (stream
, _("\
13630 -mevexlig=[128|256|512] (default: 128)\n\
13631 encode scalar EVEX instructions with specific vector\n\
13633 fprintf (stream
, _("\
13634 -mevexwig=[0|1] (default: 0)\n\
13635 encode EVEX instructions with specific EVEX.W value\n\
13636 for EVEX.W bit ignored instructions\n"));
13637 fprintf (stream
, _("\
13638 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13639 encode EVEX instructions with specific EVEX.RC value\n\
13640 for SAE-only ignored instructions\n"));
13641 fprintf (stream
, _("\
13642 -mmnemonic=[att|intel] "));
13643 if (SYSV386_COMPAT
)
13644 fprintf (stream
, _("(default: att)\n"));
13646 fprintf (stream
, _("(default: intel)\n"));
13647 fprintf (stream
, _("\
13648 use AT&T/Intel mnemonic\n"));
13649 fprintf (stream
, _("\
13650 -msyntax=[att|intel] (default: att)\n\
13651 use AT&T/Intel syntax\n"));
13652 fprintf (stream
, _("\
13653 -mindex-reg support pseudo index registers\n"));
13654 fprintf (stream
, _("\
13655 -mnaked-reg don't require `%%' prefix for registers\n"));
13656 fprintf (stream
, _("\
13657 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13658 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13659 fprintf (stream
, _("\
13660 -mshared disable branch optimization for shared code\n"));
13661 fprintf (stream
, _("\
13662 -mx86-used-note=[no|yes] "));
13663 if (DEFAULT_X86_USED_NOTE
)
13664 fprintf (stream
, _("(default: yes)\n"));
13666 fprintf (stream
, _("(default: no)\n"));
13667 fprintf (stream
, _("\
13668 generate x86 used ISA and feature properties\n"));
13670 #if defined (TE_PE) || defined (TE_PEP)
13671 fprintf (stream
, _("\
13672 -mbig-obj generate big object files\n"));
13674 fprintf (stream
, _("\
13675 -momit-lock-prefix=[no|yes] (default: no)\n\
13676 strip all lock prefixes\n"));
13677 fprintf (stream
, _("\
13678 -mfence-as-lock-add=[no|yes] (default: no)\n\
13679 encode lfence, mfence and sfence as\n\
13680 lock addl $0x0, (%%{re}sp)\n"));
13681 fprintf (stream
, _("\
13682 -mrelax-relocations=[no|yes] "));
13683 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13684 fprintf (stream
, _("(default: yes)\n"));
13686 fprintf (stream
, _("(default: no)\n"));
13687 fprintf (stream
, _("\
13688 generate relax relocations\n"));
13689 fprintf (stream
, _("\
13690 -malign-branch-boundary=NUM (default: 0)\n\
13691 align branches within NUM byte boundary\n"));
13692 fprintf (stream
, _("\
13693 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13694 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13696 specify types of branches to align\n"));
13697 fprintf (stream
, _("\
13698 -malign-branch-prefix-size=NUM (default: 5)\n\
13699 align branches with NUM prefixes per instruction\n"));
13700 fprintf (stream
, _("\
13701 -mbranches-within-32B-boundaries\n\
13702 align branches within 32 byte boundary\n"));
13703 fprintf (stream
, _("\
13704 -mlfence-after-load=[no|yes] (default: no)\n\
13705 generate lfence after load\n"));
13706 fprintf (stream
, _("\
13707 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13708 generate lfence before indirect near branch\n"));
13709 fprintf (stream
, _("\
13710 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13711 generate lfence before ret\n"));
13712 fprintf (stream
, _("\
13713 -mamd64 accept only AMD64 ISA [default]\n"));
13714 fprintf (stream
, _("\
13715 -mintel64 accept only Intel64 ISA\n"));
13718 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13719 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13720 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13722 /* Pick the target format to use. */
13725 i386_target_format (void)
13727 if (!strncmp (default_arch
, "x86_64", 6))
13729 update_code_flag (CODE_64BIT
, 1);
13730 if (default_arch
[6] == '\0')
13731 x86_elf_abi
= X86_64_ABI
;
13733 x86_elf_abi
= X86_64_X32_ABI
;
13735 else if (!strcmp (default_arch
, "i386"))
13736 update_code_flag (CODE_32BIT
, 1);
13737 else if (!strcmp (default_arch
, "iamcu"))
13739 update_code_flag (CODE_32BIT
, 1);
13740 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13742 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13743 cpu_arch_name
= "iamcu";
13744 cpu_sub_arch_name
= NULL
;
13745 cpu_arch_flags
= iamcu_flags
;
13746 cpu_arch_isa
= PROCESSOR_IAMCU
;
13747 cpu_arch_isa_flags
= iamcu_flags
;
13748 if (!cpu_arch_tune_set
)
13750 cpu_arch_tune
= cpu_arch_isa
;
13751 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13754 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13755 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13759 as_fatal (_("unknown architecture"));
13761 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13762 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13763 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13764 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13766 switch (OUTPUT_FLAVOR
)
13768 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13769 case bfd_target_aout_flavour
:
13770 return AOUT_TARGET_FORMAT
;
13772 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13773 # if defined (TE_PE) || defined (TE_PEP)
13774 case bfd_target_coff_flavour
:
13775 if (flag_code
== CODE_64BIT
)
13776 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13778 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13779 # elif defined (TE_GO32)
13780 case bfd_target_coff_flavour
:
13781 return "coff-go32";
13783 case bfd_target_coff_flavour
:
13784 return "coff-i386";
13787 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13788 case bfd_target_elf_flavour
:
13790 const char *format
;
13792 switch (x86_elf_abi
)
13795 format
= ELF_TARGET_FORMAT
;
13797 tls_get_addr
= "___tls_get_addr";
13801 use_rela_relocations
= 1;
13804 tls_get_addr
= "__tls_get_addr";
13806 format
= ELF_TARGET_FORMAT64
;
13808 case X86_64_X32_ABI
:
13809 use_rela_relocations
= 1;
13812 tls_get_addr
= "__tls_get_addr";
13814 disallow_64bit_reloc
= 1;
13815 format
= ELF_TARGET_FORMAT32
;
13818 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13820 if (x86_elf_abi
!= X86_64_ABI
)
13821 as_fatal (_("Intel L1OM is 64bit only"));
13822 return ELF_TARGET_L1OM_FORMAT
;
13824 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13826 if (x86_elf_abi
!= X86_64_ABI
)
13827 as_fatal (_("Intel K1OM is 64bit only"));
13828 return ELF_TARGET_K1OM_FORMAT
;
13830 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13832 if (x86_elf_abi
!= I386_ABI
)
13833 as_fatal (_("Intel MCU is 32bit only"));
13834 return ELF_TARGET_IAMCU_FORMAT
;
13840 #if defined (OBJ_MACH_O)
13841 case bfd_target_mach_o_flavour
:
13842 if (flag_code
== CODE_64BIT
)
13844 use_rela_relocations
= 1;
13846 return "mach-o-x86-64";
13849 return "mach-o-i386";
13857 #endif /* OBJ_MAYBE_ more than one */
13860 md_undefined_symbol (char *name
)
13862 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13863 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13864 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13865 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13869 if (symbol_find (name
))
13870 as_bad (_("GOT already in symbol table"));
13871 GOT_symbol
= symbol_new (name
, undefined_section
,
13872 &zero_address_frag
, 0);
13879 /* Round up a section size to the appropriate boundary. */
13882 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13884 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13885 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13887 /* For a.out, force the section size to be aligned. If we don't do
13888 this, BFD will align it for us, but it will not write out the
13889 final bytes of the section. This may be a bug in BFD, but it is
13890 easier to fix it here since that is how the other a.out targets
13894 align
= bfd_section_alignment (segment
);
13895 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13902 /* On the i386, PC-relative offsets are relative to the start of the
13903 next instruction. That is, the address of the offset, plus its
13904 size, since the offset is always the last part of the insn. */
13907 md_pcrel_from (fixS
*fixP
)
13909 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13915 s_bss (int ignore ATTRIBUTE_UNUSED
)
13919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13921 obj_elf_section_change_hook ();
13923 temp
= get_absolute_expression ();
13924 subseg_set (bss_section
, (subsegT
) temp
);
13925 demand_empty_rest_of_line ();
13930 /* Remember constant directive. */
13933 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13935 if (last_insn
.kind
!= last_insn_directive
13936 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13938 last_insn
.seg
= now_seg
;
13939 last_insn
.kind
= last_insn_directive
;
13940 last_insn
.name
= "constant directive";
13941 last_insn
.file
= as_where (&last_insn
.line
);
13942 if (lfence_before_ret
!= lfence_before_ret_none
)
13944 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13945 as_warn (_("constant directive skips -mlfence-before-ret "
13946 "and -mlfence-before-indirect-branch"));
13948 as_warn (_("constant directive skips -mlfence-before-ret"));
13950 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13951 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13956 i386_validate_fix (fixS
*fixp
)
13958 if (fixp
->fx_subsy
)
13960 if (fixp
->fx_subsy
== GOT_symbol
)
13962 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13967 if (fixp
->fx_tcbit2
)
13968 fixp
->fx_r_type
= (fixp
->fx_tcbit
13969 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13970 : BFD_RELOC_X86_64_GOTPCRELX
);
13973 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13978 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13980 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13982 fixp
->fx_subsy
= 0;
13985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13988 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13989 to section. Since PLT32 relocation must be against symbols,
13990 turn such PLT32 relocation into PC32 relocation. */
13992 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13993 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13994 && symbol_section_p (fixp
->fx_addsy
))
13995 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13998 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13999 && fixp
->fx_tcbit2
)
14000 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14007 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14010 bfd_reloc_code_real_type code
;
14012 switch (fixp
->fx_r_type
)
14014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14015 case BFD_RELOC_SIZE32
:
14016 case BFD_RELOC_SIZE64
:
14017 if (S_IS_DEFINED (fixp
->fx_addsy
)
14018 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14020 /* Resolve size relocation against local symbol to size of
14021 the symbol plus addend. */
14022 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14023 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14024 && !fits_in_unsigned_long (value
))
14025 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14026 _("symbol size computation overflow"));
14027 fixp
->fx_addsy
= NULL
;
14028 fixp
->fx_subsy
= NULL
;
14029 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14033 /* Fall through. */
14035 case BFD_RELOC_X86_64_PLT32
:
14036 case BFD_RELOC_X86_64_GOT32
:
14037 case BFD_RELOC_X86_64_GOTPCREL
:
14038 case BFD_RELOC_X86_64_GOTPCRELX
:
14039 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14040 case BFD_RELOC_386_PLT32
:
14041 case BFD_RELOC_386_GOT32
:
14042 case BFD_RELOC_386_GOT32X
:
14043 case BFD_RELOC_386_GOTOFF
:
14044 case BFD_RELOC_386_GOTPC
:
14045 case BFD_RELOC_386_TLS_GD
:
14046 case BFD_RELOC_386_TLS_LDM
:
14047 case BFD_RELOC_386_TLS_LDO_32
:
14048 case BFD_RELOC_386_TLS_IE_32
:
14049 case BFD_RELOC_386_TLS_IE
:
14050 case BFD_RELOC_386_TLS_GOTIE
:
14051 case BFD_RELOC_386_TLS_LE_32
:
14052 case BFD_RELOC_386_TLS_LE
:
14053 case BFD_RELOC_386_TLS_GOTDESC
:
14054 case BFD_RELOC_386_TLS_DESC_CALL
:
14055 case BFD_RELOC_X86_64_TLSGD
:
14056 case BFD_RELOC_X86_64_TLSLD
:
14057 case BFD_RELOC_X86_64_DTPOFF32
:
14058 case BFD_RELOC_X86_64_DTPOFF64
:
14059 case BFD_RELOC_X86_64_GOTTPOFF
:
14060 case BFD_RELOC_X86_64_TPOFF32
:
14061 case BFD_RELOC_X86_64_TPOFF64
:
14062 case BFD_RELOC_X86_64_GOTOFF64
:
14063 case BFD_RELOC_X86_64_GOTPC32
:
14064 case BFD_RELOC_X86_64_GOT64
:
14065 case BFD_RELOC_X86_64_GOTPCREL64
:
14066 case BFD_RELOC_X86_64_GOTPC64
:
14067 case BFD_RELOC_X86_64_GOTPLT64
:
14068 case BFD_RELOC_X86_64_PLTOFF64
:
14069 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14070 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14071 case BFD_RELOC_RVA
:
14072 case BFD_RELOC_VTABLE_ENTRY
:
14073 case BFD_RELOC_VTABLE_INHERIT
:
14075 case BFD_RELOC_32_SECREL
:
14077 code
= fixp
->fx_r_type
;
14079 case BFD_RELOC_X86_64_32S
:
14080 if (!fixp
->fx_pcrel
)
14082 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14083 code
= fixp
->fx_r_type
;
14086 /* Fall through. */
14088 if (fixp
->fx_pcrel
)
14090 switch (fixp
->fx_size
)
14093 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14094 _("can not do %d byte pc-relative relocation"),
14096 code
= BFD_RELOC_32_PCREL
;
14098 case 1: code
= BFD_RELOC_8_PCREL
; break;
14099 case 2: code
= BFD_RELOC_16_PCREL
; break;
14100 case 4: code
= BFD_RELOC_32_PCREL
; break;
14102 case 8: code
= BFD_RELOC_64_PCREL
; break;
14108 switch (fixp
->fx_size
)
14111 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14112 _("can not do %d byte relocation"),
14114 code
= BFD_RELOC_32
;
14116 case 1: code
= BFD_RELOC_8
; break;
14117 case 2: code
= BFD_RELOC_16
; break;
14118 case 4: code
= BFD_RELOC_32
; break;
14120 case 8: code
= BFD_RELOC_64
; break;
14127 if ((code
== BFD_RELOC_32
14128 || code
== BFD_RELOC_32_PCREL
14129 || code
== BFD_RELOC_X86_64_32S
)
14131 && fixp
->fx_addsy
== GOT_symbol
)
14134 code
= BFD_RELOC_386_GOTPC
;
14136 code
= BFD_RELOC_X86_64_GOTPC32
;
14138 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14140 && fixp
->fx_addsy
== GOT_symbol
)
14142 code
= BFD_RELOC_X86_64_GOTPC64
;
14145 rel
= XNEW (arelent
);
14146 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14147 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14149 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14151 if (!use_rela_relocations
)
14153 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14154 vtable entry to be used in the relocation's section offset. */
14155 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14156 rel
->address
= fixp
->fx_offset
;
14157 #if defined (OBJ_COFF) && defined (TE_PE)
14158 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14159 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14164 /* Use the rela in 64bit mode. */
14167 if (disallow_64bit_reloc
)
14170 case BFD_RELOC_X86_64_DTPOFF64
:
14171 case BFD_RELOC_X86_64_TPOFF64
:
14172 case BFD_RELOC_64_PCREL
:
14173 case BFD_RELOC_X86_64_GOTOFF64
:
14174 case BFD_RELOC_X86_64_GOT64
:
14175 case BFD_RELOC_X86_64_GOTPCREL64
:
14176 case BFD_RELOC_X86_64_GOTPC64
:
14177 case BFD_RELOC_X86_64_GOTPLT64
:
14178 case BFD_RELOC_X86_64_PLTOFF64
:
14179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14180 _("cannot represent relocation type %s in x32 mode"),
14181 bfd_get_reloc_code_name (code
));
14187 if (!fixp
->fx_pcrel
)
14188 rel
->addend
= fixp
->fx_offset
;
14192 case BFD_RELOC_X86_64_PLT32
:
14193 case BFD_RELOC_X86_64_GOT32
:
14194 case BFD_RELOC_X86_64_GOTPCREL
:
14195 case BFD_RELOC_X86_64_GOTPCRELX
:
14196 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14197 case BFD_RELOC_X86_64_TLSGD
:
14198 case BFD_RELOC_X86_64_TLSLD
:
14199 case BFD_RELOC_X86_64_GOTTPOFF
:
14200 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14201 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14202 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14205 rel
->addend
= (section
->vma
14207 + fixp
->fx_addnumber
14208 + md_pcrel_from (fixp
));
14213 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14214 if (rel
->howto
== NULL
)
14216 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14217 _("cannot represent relocation type %s"),
14218 bfd_get_reloc_code_name (code
));
14219 /* Set howto to a garbage value so that we can keep going. */
14220 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14221 gas_assert (rel
->howto
!= NULL
);
14227 #include "tc-i386-intel.c"
14230 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14232 int saved_naked_reg
;
14233 char saved_register_dot
;
14235 saved_naked_reg
= allow_naked_reg
;
14236 allow_naked_reg
= 1;
14237 saved_register_dot
= register_chars
['.'];
14238 register_chars
['.'] = '.';
14239 allow_pseudo_reg
= 1;
14240 expression_and_evaluate (exp
);
14241 allow_pseudo_reg
= 0;
14242 register_chars
['.'] = saved_register_dot
;
14243 allow_naked_reg
= saved_naked_reg
;
14245 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14247 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14249 exp
->X_op
= O_constant
;
14250 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14251 .dw2_regnum
[flag_code
>> 1];
14254 exp
->X_op
= O_illegal
;
14259 tc_x86_frame_initial_instructions (void)
14261 static unsigned int sp_regno
[2];
14263 if (!sp_regno
[flag_code
>> 1])
14265 char *saved_input
= input_line_pointer
;
14266 char sp
[][4] = {"esp", "rsp"};
14269 input_line_pointer
= sp
[flag_code
>> 1];
14270 tc_x86_parse_to_dw2regnum (&exp
);
14271 gas_assert (exp
.X_op
== O_constant
);
14272 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14273 input_line_pointer
= saved_input
;
14276 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14277 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14281 x86_dwarf2_addr_size (void)
14283 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14284 if (x86_elf_abi
== X86_64_X32_ABI
)
14287 return bfd_arch_bits_per_address (stdoutput
) / 8;
14291 i386_elf_section_type (const char *str
, size_t len
)
14293 if (flag_code
== CODE_64BIT
14294 && len
== sizeof ("unwind") - 1
14295 && strncmp (str
, "unwind", 6) == 0)
14296 return SHT_X86_64_UNWIND
;
14303 i386_solaris_fix_up_eh_frame (segT sec
)
14305 if (flag_code
== CODE_64BIT
)
14306 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14312 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14316 exp
.X_op
= O_secrel
;
14317 exp
.X_add_symbol
= symbol
;
14318 exp
.X_add_number
= 0;
14319 emit_expr (&exp
, size
);
14323 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14324 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14327 x86_64_section_letter (int letter
, const char **ptr_msg
)
14329 if (flag_code
== CODE_64BIT
)
14332 return SHF_X86_64_LARGE
;
14334 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14337 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14342 x86_64_section_word (char *str
, size_t len
)
14344 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14345 return SHF_X86_64_LARGE
;
14351 handle_large_common (int small ATTRIBUTE_UNUSED
)
14353 if (flag_code
!= CODE_64BIT
)
14355 s_comm_internal (0, elf_common_parse
);
14356 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14360 static segT lbss_section
;
14361 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14362 asection
*saved_bss_section
= bss_section
;
14364 if (lbss_section
== NULL
)
14366 flagword applicable
;
14367 segT seg
= now_seg
;
14368 subsegT subseg
= now_subseg
;
14370 /* The .lbss section is for local .largecomm symbols. */
14371 lbss_section
= subseg_new (".lbss", 0);
14372 applicable
= bfd_applicable_section_flags (stdoutput
);
14373 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14374 seg_info (lbss_section
)->bss
= 1;
14376 subseg_set (seg
, subseg
);
14379 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14380 bss_section
= lbss_section
;
14382 s_comm_internal (0, elf_common_parse
);
14384 elf_com_section_ptr
= saved_com_section_ptr
;
14385 bss_section
= saved_bss_section
;
14388 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */