1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
380 /* Has GOTPC or TLS relocation. */
381 bfd_boolean has_gotpc_tls_reloc
;
383 /* RM and SIB are the modrm byte and the sib byte where the
384 addressing modes of this insn are encoded. */
391 /* Masking attributes. */
392 struct Mask_Operation
*mask
;
394 /* Rounding control and SAE attributes. */
395 struct RC_Operation
*rounding
;
397 /* Broadcasting attributes. */
398 struct Broadcast_Operation
*broadcast
;
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift
;
403 /* Prefer load or store in encoding. */
406 dir_encoding_default
= 0,
412 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
415 disp_encoding_default
= 0,
421 /* Prefer the REX byte in encoding. */
422 bfd_boolean rex_encoding
;
424 /* Disable instruction size optimization. */
425 bfd_boolean no_optimize
;
427 /* How to encode vector instructions. */
430 vex_encoding_default
= 0,
438 const char *rep_prefix
;
441 const char *hle_prefix
;
443 /* Have BND prefix. */
444 const char *bnd_prefix
;
446 /* Have NOTRACK prefix. */
447 const char *notrack_prefix
;
450 enum i386_error error
;
453 typedef struct _i386_insn i386_insn
;
455 /* Link RC type with corresponding string, that'll be looked for in
464 static const struct RC_name RC_NamesTable
[] =
466 { rne
, STRING_COMMA_LEN ("rn-sae") },
467 { rd
, STRING_COMMA_LEN ("rd-sae") },
468 { ru
, STRING_COMMA_LEN ("ru-sae") },
469 { rz
, STRING_COMMA_LEN ("rz-sae") },
470 { saeonly
, STRING_COMMA_LEN ("sae") },
473 /* List of chars besides those in app.c:symbol_chars that can start an
474 operand. Used to prevent the scrubber eating vital white-space. */
475 const char extra_symbol_chars
[] = "*%-([{}"
484 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
485 && !defined (TE_GNU) \
486 && !defined (TE_LINUX) \
487 && !defined (TE_FreeBSD) \
488 && !defined (TE_DragonFly) \
489 && !defined (TE_NetBSD))
490 /* This array holds the chars that always start a comment. If the
491 pre-processor is disabled, these aren't very useful. The option
492 --divide will remove '/' from this list. */
493 const char *i386_comment_chars
= "#/";
494 #define SVR4_COMMENT_CHARS 1
495 #define PREFIX_SEPARATOR '\\'
498 const char *i386_comment_chars
= "#";
499 #define PREFIX_SEPARATOR '/'
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output.
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
508 Also note that comments started like this one will always work if
509 '/' isn't otherwise defined. */
510 const char line_comment_chars
[] = "#/";
512 const char line_separator_chars
[] = ";";
514 /* Chars that can be used to separate mant from exp in floating point
516 const char EXP_CHARS
[] = "eE";
518 /* Chars that mean this number is a floating point constant
521 const char FLT_CHARS
[] = "fFdDxX";
523 /* Tables for lexical analysis. */
524 static char mnemonic_chars
[256];
525 static char register_chars
[256];
526 static char operand_chars
[256];
527 static char identifier_chars
[256];
528 static char digit_chars
[256];
530 /* Lexical macros. */
531 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
532 #define is_operand_char(x) (operand_chars[(unsigned char) x])
533 #define is_register_char(x) (register_chars[(unsigned char) x])
534 #define is_space_char(x) ((x) == ' ')
535 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
536 #define is_digit_char(x) (digit_chars[(unsigned char) x])
538 /* All non-digit non-letter characters that may occur in an operand. */
539 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
541 /* md_assemble() always leaves the strings it's passed unaltered. To
542 effect this we maintain a stack of saved characters that we've smashed
543 with '\0's (indicating end of strings for various sub-fields of the
544 assembler instruction). */
545 static char save_stack
[32];
546 static char *save_stack_p
;
547 #define END_STRING_AND_SAVE(s) \
548 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
549 #define RESTORE_END_STRING(s) \
550 do { *(s) = *--save_stack_p; } while (0)
552 /* The instruction we're assembling. */
555 /* Possible templates for current insn. */
556 static const templates
*current_templates
;
558 /* Per instruction expressionS buffers: max displacements & immediates. */
559 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
560 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
562 /* Current operand we are working on. */
563 static int this_operand
= -1;
565 /* We support four different modes. FLAG_CODE variable is used to distinguish
573 static enum flag_code flag_code
;
574 static unsigned int object_64bit
;
575 static unsigned int disallow_64bit_reloc
;
576 static int use_rela_relocations
= 0;
577 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
578 static const char *tls_get_addr
;
580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
584 /* The ELF ABI to use. */
592 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
595 #if defined (TE_PE) || defined (TE_PEP)
596 /* Use big object file format. */
597 static int use_big_obj
= 0;
600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
601 /* 1 if generating code for a shared library. */
602 static int shared
= 0;
605 /* 1 for intel syntax,
607 static int intel_syntax
= 0;
609 static enum x86_64_isa
611 amd64
= 1, /* AMD64 ISA. */
612 intel64
/* Intel64 ISA. */
615 /* 1 for intel mnemonic,
616 0 if att mnemonic. */
617 static int intel_mnemonic
= !SYSV386_COMPAT
;
619 /* 1 if pseudo registers are permitted. */
620 static int allow_pseudo_reg
= 0;
622 /* 1 if register prefix % not required. */
623 static int allow_naked_reg
= 0;
625 /* 1 if the assembler should add BND prefix for all control-transferring
626 instructions supporting it, even if this prefix wasn't specified
628 static int add_bnd_prefix
= 0;
630 /* 1 if pseudo index register, eiz/riz, is allowed . */
631 static int allow_index_reg
= 0;
633 /* 1 if the assembler should ignore LOCK prefix, even if it was
634 specified explicitly. */
635 static int omit_lock_prefix
= 0;
637 /* 1 if the assembler should encode lfence, mfence, and sfence as
638 "lock addl $0, (%{re}sp)". */
639 static int avoid_fence
= 0;
641 /* 1 if lfence should be inserted after every load. */
642 static int lfence_after_load
= 0;
644 /* Non-zero if lfence should be inserted before indirect branch. */
645 static enum lfence_before_indirect_branch_kind
647 lfence_branch_none
= 0,
648 lfence_branch_register
,
649 lfence_branch_memory
,
652 lfence_before_indirect_branch
;
654 /* Non-zero if lfence should be inserted before ret. */
655 static enum lfence_before_ret_kind
657 lfence_before_ret_none
= 0,
658 lfence_before_ret_not
,
659 lfence_before_ret_or
,
660 lfence_before_ret_shl
664 /* Types of previous instruction is .byte or prefix. */
679 /* 1 if the assembler should generate relax relocations. */
681 static int generate_relax_relocations
682 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
684 static enum check_kind
690 sse_check
, operand_check
= check_warning
;
692 /* Non-zero if branches should be aligned within power of 2 boundary. */
693 static int align_branch_power
= 0;
695 /* Types of branches to align. */
696 enum align_branch_kind
698 align_branch_none
= 0,
699 align_branch_jcc
= 1,
700 align_branch_fused
= 2,
701 align_branch_jmp
= 3,
702 align_branch_call
= 4,
703 align_branch_indirect
= 5,
707 /* Type bits of branches to align. */
708 enum align_branch_bit
710 align_branch_jcc_bit
= 1 << align_branch_jcc
,
711 align_branch_fused_bit
= 1 << align_branch_fused
,
712 align_branch_jmp_bit
= 1 << align_branch_jmp
,
713 align_branch_call_bit
= 1 << align_branch_call
,
714 align_branch_indirect_bit
= 1 << align_branch_indirect
,
715 align_branch_ret_bit
= 1 << align_branch_ret
718 static unsigned int align_branch
= (align_branch_jcc_bit
719 | align_branch_fused_bit
720 | align_branch_jmp_bit
);
722 /* Types of condition jump used by macro-fusion. */
725 mf_jcc_jo
= 0, /* base opcode 0x70 */
726 mf_jcc_jc
, /* base opcode 0x72 */
727 mf_jcc_je
, /* base opcode 0x74 */
728 mf_jcc_jna
, /* base opcode 0x76 */
729 mf_jcc_js
, /* base opcode 0x78 */
730 mf_jcc_jp
, /* base opcode 0x7a */
731 mf_jcc_jl
, /* base opcode 0x7c */
732 mf_jcc_jle
, /* base opcode 0x7e */
735 /* Types of compare flag-modifying insntructions used by macro-fusion. */
738 mf_cmp_test_and
, /* test/cmp */
739 mf_cmp_alu_cmp
, /* add/sub/cmp */
740 mf_cmp_incdec
/* inc/dec */
743 /* The maximum padding size for fused jcc. CMP like instruction can
744 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
746 #define MAX_FUSED_JCC_PADDING_SIZE 20
748 /* The maximum number of prefixes added for an instruction. */
749 static unsigned int align_branch_prefix_size
= 5;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
756 static int optimize
= 0;
759 1. Clear the REX_W bit with register operand if possible.
760 2. Above plus use 128bit vector instruction to clear the full vector
762 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
765 static int optimize_for_space
= 0;
767 /* Register prefix used for error message. */
768 static const char *register_prefix
= "%";
770 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
771 leave, push, and pop instructions so that gcc has the same stack
772 frame as in 32 bit mode. */
773 static char stackop_size
= '\0';
775 /* Non-zero to optimize code alignment. */
776 int optimize_align_code
= 1;
778 /* Non-zero to quieten some warnings. */
779 static int quiet_warnings
= 0;
782 static const char *cpu_arch_name
= NULL
;
783 static char *cpu_sub_arch_name
= NULL
;
785 /* CPU feature flags. */
786 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
788 /* If we have selected a cpu we are generating instructions for. */
789 static int cpu_arch_tune_set
= 0;
791 /* Cpu we are generating instructions for. */
792 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
794 /* CPU feature flags of cpu we are generating instructions for. */
795 static i386_cpu_flags cpu_arch_tune_flags
;
797 /* CPU instruction set architecture used. */
798 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
800 /* CPU feature flags of instruction set architecture used. */
801 i386_cpu_flags cpu_arch_isa_flags
;
803 /* If set, conditional jumps are not automatically promoted to handle
804 larger than a byte offset. */
805 static unsigned int no_cond_jump_promotion
= 0;
807 /* Encode SSE instructions with VEX prefix. */
808 static unsigned int sse2avx
;
810 /* Encode scalar AVX instructions with specific vector length. */
817 /* Encode VEX WIG instructions with specific vex.w. */
824 /* Encode scalar EVEX LIG instructions with specific vector length. */
832 /* Encode EVEX WIG instructions with specific evex.w. */
839 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
840 static enum rc_type evexrcig
= rne
;
842 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
843 static symbolS
*GOT_symbol
;
845 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
846 unsigned int x86_dwarf2_return_column
;
848 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
849 int x86_cie_data_alignment
;
851 /* Interface to relax_segment.
852 There are 3 major relax states for 386 jump insns because the
853 different types of jumps add different sizes to frags when we're
854 figuring out what sort of jump to choose to reach a given label.
856 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
857 branches which are handled by md_estimate_size_before_relax() and
858 i386_generic_table_relax_frag(). */
861 #define UNCOND_JUMP 0
863 #define COND_JUMP86 2
864 #define BRANCH_PADDING 3
865 #define BRANCH_PREFIX 4
866 #define FUSED_JCC_PADDING 5
871 #define SMALL16 (SMALL | CODE16)
873 #define BIG16 (BIG | CODE16)
877 #define INLINE __inline__
883 #define ENCODE_RELAX_STATE(type, size) \
884 ((relax_substateT) (((type) << 2) | (size)))
885 #define TYPE_FROM_RELAX_STATE(s) \
887 #define DISP_SIZE_FROM_RELAX_STATE(s) \
888 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
890 /* This table is used by relax_frag to promote short jumps to long
891 ones where necessary. SMALL (short) jumps may be promoted to BIG
892 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
893 don't allow a short jump in a 32 bit code segment to be promoted to
894 a 16 bit offset jump because it's slower (requires data size
895 prefix), and doesn't work, unless the destination is in the bottom
896 64k of the code segment (The top 16 bits of eip are zeroed). */
898 const relax_typeS md_relax_table
[] =
901 1) most positive reach of this state,
902 2) most negative reach of this state,
903 3) how many bytes this mode will have in the variable part of the frag
904 4) which index into the table to try if we can't fit into this one. */
906 /* UNCOND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
909 /* dword jmp adds 4 bytes to frag:
910 0 extra opcode bytes, 4 displacement bytes. */
912 /* word jmp adds 2 byte2 to frag:
913 0 extra opcode bytes, 2 displacement bytes. */
916 /* COND_JUMP states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
922 /* word conditionals add 3 bytes to frag:
923 1 extra opcode byte, 2 displacement bytes. */
926 /* COND_JUMP86 states. */
927 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
928 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
929 /* dword conditionals adds 5 bytes to frag:
930 1 extra opcode byte, 4 displacement bytes. */
932 /* word conditionals add 4 bytes to frag:
933 1 displacement byte and a 3 byte long branch insn. */
937 static const arch_entry cpu_arch
[] =
939 /* Do not replace the first two entries - i386_target_format()
940 relies on them being there in this order. */
941 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
942 CPU_GENERIC32_FLAGS
, 0 },
943 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
944 CPU_GENERIC64_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
953 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
955 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
959 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
961 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
962 CPU_PENTIUMPRO_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
965 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
969 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
971 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
972 CPU_NOCONA_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
975 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
978 CPU_CORE2_FLAGS
, 1 },
979 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
982 CPU_COREI7_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
985 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
987 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
988 CPU_IAMCU_FLAGS
, 0 },
989 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
991 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
994 CPU_ATHLON_FLAGS
, 0 },
995 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1002 CPU_AMDFAM10_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1004 CPU_BDVER1_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1006 CPU_BDVER2_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1008 CPU_BDVER3_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1010 CPU_BDVER4_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1012 CPU_ZNVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1016 CPU_BTVER1_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1018 CPU_BTVER2_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1020 CPU_8087_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1028 CPU_CMOV_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1030 CPU_FXSR_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE2_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4A_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_1_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512F_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512CD_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512ER_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512PF_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512DQ_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512BW_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512VL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1070 CPU_VMFUNC_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVE_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVEOPT_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEC_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVES_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1084 CPU_PCLMUL_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 1 },
1087 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1088 CPU_FSGSBASE_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1090 CPU_RDRND_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1092 CPU_F16C_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1094 CPU_BMI2_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1098 CPU_FMA4_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1104 CPU_MOVBE_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1106 CPU_CX16_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1110 CPU_LZCNT_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_POPCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1118 CPU_INVPCID_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1120 CPU_CLFLUSH_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1124 CPU_SYSCALL_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1126 CPU_RDTSCP_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1128 CPU_3DNOW_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOWA_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1132 CPU_PADLOCK_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1134 CPU_SVME_FLAGS
, 1 },
1135 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1138 CPU_SSE4A_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1148 CPU_RDSEED_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1150 CPU_PRFCHW_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1152 CPU_SMAP_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1155 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1158 CPU_CLFLUSHOPT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1160 CPU_PREFETCHWT1_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1163 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1164 CPU_CLWB_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512IFMA_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512VBMI_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VBMI2_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VNNI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_BITALG_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1182 CPU_CLZERO_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1184 CPU_MWAITX_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1186 CPU_OSPKE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPID_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1190 CPU_PTWRITE_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1193 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1194 CPU_SHSTK_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1196 CPU_GFNI_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1198 CPU_VAES_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1200 CPU_VPCLMULQDQ_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1202 CPU_WBNOINVD_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1204 CPU_PCONFIG_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1206 CPU_WAITPKG_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1208 CPU_CLDEMOTE_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1210 CPU_AMX_INT8_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1212 CPU_AMX_BF16_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_TILE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1216 CPU_MOVDIRI_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1218 CPU_MOVDIR64B_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1220 CPU_AVX512_BF16_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1222 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1225 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1226 CPU_ENQCMD_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1228 CPU_SERIALIZE_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1230 CPU_RDPRU_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1232 CPU_MCOMMIT_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1234 CPU_SEV_ES_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1236 CPU_TSXLDTRK_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1239 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1240 CPU_WIDEKL_FLAGS
, 0 },
1243 static const noarch_entry cpu_noarch
[] =
1245 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1246 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1247 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1248 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1249 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1250 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1251 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1255 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1256 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1257 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1258 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1259 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1277 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1278 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1279 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1280 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1282 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1283 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1286 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1287 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1288 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1289 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1290 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1291 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1292 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1296 /* Like s_lcomm_internal in gas/read.c but the alignment string
1297 is allowed to be optional. */
1300 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1307 && *input_line_pointer
== ',')
1309 align
= parse_align (needs_align
- 1);
1311 if (align
== (addressT
) -1)
1326 bss_alloc (symbolP
, size
, align
);
1331 pe_lcomm (int needs_align
)
1333 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1337 const pseudo_typeS md_pseudo_table
[] =
1339 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1340 {"align", s_align_bytes
, 0},
1342 {"align", s_align_ptwo
, 0},
1344 {"arch", set_cpu_arch
, 0},
1348 {"lcomm", pe_lcomm
, 1},
1350 {"ffloat", float_cons
, 'f'},
1351 {"dfloat", float_cons
, 'd'},
1352 {"tfloat", float_cons
, 'x'},
1354 {"slong", signed_cons
, 4},
1355 {"noopt", s_ignore
, 0},
1356 {"optim", s_ignore
, 0},
1357 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1358 {"code16", set_code_flag
, CODE_16BIT
},
1359 {"code32", set_code_flag
, CODE_32BIT
},
1361 {"code64", set_code_flag
, CODE_64BIT
},
1363 {"intel_syntax", set_intel_syntax
, 1},
1364 {"att_syntax", set_intel_syntax
, 0},
1365 {"intel_mnemonic", set_intel_mnemonic
, 1},
1366 {"att_mnemonic", set_intel_mnemonic
, 0},
1367 {"allow_index_reg", set_allow_index_reg
, 1},
1368 {"disallow_index_reg", set_allow_index_reg
, 0},
1369 {"sse_check", set_check
, 0},
1370 {"operand_check", set_check
, 1},
1371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1372 {"largecomm", handle_large_common
, 0},
1374 {"file", dwarf2_directive_file
, 0},
1375 {"loc", dwarf2_directive_loc
, 0},
1376 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1379 {"secrel32", pe_directive_secrel
, 0},
1384 /* For interface with expression (). */
1385 extern char *input_line_pointer
;
1387 /* Hash table for instruction mnemonic lookup. */
1388 static htab_t op_hash
;
1390 /* Hash table for register lookup. */
1391 static htab_t reg_hash
;
1393 /* Various efficient no-op patterns for aligning code labels.
1394 Note: Don't try to assemble the instructions in the comments.
1395 0L and 0w are not legal. */
1396 static const unsigned char f32_1
[] =
1398 static const unsigned char f32_2
[] =
1399 {0x66,0x90}; /* xchg %ax,%ax */
1400 static const unsigned char f32_3
[] =
1401 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1402 static const unsigned char f32_4
[] =
1403 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1404 static const unsigned char f32_6
[] =
1405 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1406 static const unsigned char f32_7
[] =
1407 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1408 static const unsigned char f16_3
[] =
1409 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1410 static const unsigned char f16_4
[] =
1411 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1412 static const unsigned char jump_disp8
[] =
1413 {0xeb}; /* jmp disp8 */
1414 static const unsigned char jump32_disp32
[] =
1415 {0xe9}; /* jmp disp32 */
1416 static const unsigned char jump16_disp32
[] =
1417 {0x66,0xe9}; /* jmp disp32 */
1418 /* 32-bit NOPs patterns. */
1419 static const unsigned char *const f32_patt
[] = {
1420 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1422 /* 16-bit NOPs patterns. */
1423 static const unsigned char *const f16_patt
[] = {
1424 f32_1
, f32_2
, f16_3
, f16_4
1426 /* nopl (%[re]ax) */
1427 static const unsigned char alt_3
[] =
1429 /* nopl 0(%[re]ax) */
1430 static const unsigned char alt_4
[] =
1431 {0x0f,0x1f,0x40,0x00};
1432 /* nopl 0(%[re]ax,%[re]ax,1) */
1433 static const unsigned char alt_5
[] =
1434 {0x0f,0x1f,0x44,0x00,0x00};
1435 /* nopw 0(%[re]ax,%[re]ax,1) */
1436 static const unsigned char alt_6
[] =
1437 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1438 /* nopl 0L(%[re]ax) */
1439 static const unsigned char alt_7
[] =
1440 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1441 /* nopl 0L(%[re]ax,%[re]ax,1) */
1442 static const unsigned char alt_8
[] =
1443 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1444 /* nopw 0L(%[re]ax,%[re]ax,1) */
1445 static const unsigned char alt_9
[] =
1446 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1447 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1448 static const unsigned char alt_10
[] =
1449 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1450 /* data16 nopw %cs:0L(%eax,%eax,1) */
1451 static const unsigned char alt_11
[] =
1452 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1453 /* 32-bit and 64-bit NOPs patterns. */
1454 static const unsigned char *const alt_patt
[] = {
1455 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1456 alt_9
, alt_10
, alt_11
1459 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1460 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1463 i386_output_nops (char *where
, const unsigned char *const *patt
,
1464 int count
, int max_single_nop_size
)
1467 /* Place the longer NOP first. */
1470 const unsigned char *nops
;
1472 if (max_single_nop_size
< 1)
1474 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1475 max_single_nop_size
);
1479 nops
= patt
[max_single_nop_size
- 1];
1481 /* Use the smaller one if the requsted one isn't available. */
1484 max_single_nop_size
--;
1485 nops
= patt
[max_single_nop_size
- 1];
1488 last
= count
% max_single_nop_size
;
1491 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1492 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1496 nops
= patt
[last
- 1];
1499 /* Use the smaller one plus one-byte NOP if the needed one
1502 nops
= patt
[last
- 1];
1503 memcpy (where
+ offset
, nops
, last
);
1504 where
[offset
+ last
] = *patt
[0];
1507 memcpy (where
+ offset
, nops
, last
);
1512 fits_in_imm7 (offsetT num
)
1514 return (num
& 0x7f) == num
;
1518 fits_in_imm31 (offsetT num
)
1520 return (num
& 0x7fffffff) == num
;
1523 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1524 single NOP instruction LIMIT. */
1527 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1529 const unsigned char *const *patt
= NULL
;
1530 int max_single_nop_size
;
1531 /* Maximum number of NOPs before switching to jump over NOPs. */
1532 int max_number_of_nops
;
1534 switch (fragP
->fr_type
)
1539 case rs_machine_dependent
:
1540 /* Allow NOP padding for jumps and calls. */
1541 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1542 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1549 /* We need to decide which NOP sequence to use for 32bit and
1550 64bit. When -mtune= is used:
1552 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1553 PROCESSOR_GENERIC32, f32_patt will be used.
1554 2. For the rest, alt_patt will be used.
1556 When -mtune= isn't used, alt_patt will be used if
1557 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1560 When -march= or .arch is used, we can't use anything beyond
1561 cpu_arch_isa_flags. */
1563 if (flag_code
== CODE_16BIT
)
1566 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1567 /* Limit number of NOPs to 2 in 16-bit mode. */
1568 max_number_of_nops
= 2;
1572 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1574 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1575 switch (cpu_arch_tune
)
1577 case PROCESSOR_UNKNOWN
:
1578 /* We use cpu_arch_isa_flags to check if we SHOULD
1579 optimize with nops. */
1580 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1585 case PROCESSOR_PENTIUM4
:
1586 case PROCESSOR_NOCONA
:
1587 case PROCESSOR_CORE
:
1588 case PROCESSOR_CORE2
:
1589 case PROCESSOR_COREI7
:
1590 case PROCESSOR_L1OM
:
1591 case PROCESSOR_K1OM
:
1592 case PROCESSOR_GENERIC64
:
1594 case PROCESSOR_ATHLON
:
1596 case PROCESSOR_AMDFAM10
:
1598 case PROCESSOR_ZNVER
:
1602 case PROCESSOR_I386
:
1603 case PROCESSOR_I486
:
1604 case PROCESSOR_PENTIUM
:
1605 case PROCESSOR_PENTIUMPRO
:
1606 case PROCESSOR_IAMCU
:
1607 case PROCESSOR_GENERIC32
:
1614 switch (fragP
->tc_frag_data
.tune
)
1616 case PROCESSOR_UNKNOWN
:
1617 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1618 PROCESSOR_UNKNOWN. */
1622 case PROCESSOR_I386
:
1623 case PROCESSOR_I486
:
1624 case PROCESSOR_PENTIUM
:
1625 case PROCESSOR_IAMCU
:
1627 case PROCESSOR_ATHLON
:
1629 case PROCESSOR_AMDFAM10
:
1631 case PROCESSOR_ZNVER
:
1633 case PROCESSOR_GENERIC32
:
1634 /* We use cpu_arch_isa_flags to check if we CAN optimize
1636 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1641 case PROCESSOR_PENTIUMPRO
:
1642 case PROCESSOR_PENTIUM4
:
1643 case PROCESSOR_NOCONA
:
1644 case PROCESSOR_CORE
:
1645 case PROCESSOR_CORE2
:
1646 case PROCESSOR_COREI7
:
1647 case PROCESSOR_L1OM
:
1648 case PROCESSOR_K1OM
:
1649 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1654 case PROCESSOR_GENERIC64
:
1660 if (patt
== f32_patt
)
1662 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1663 /* Limit number of NOPs to 2 for older processors. */
1664 max_number_of_nops
= 2;
1668 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1669 /* Limit number of NOPs to 7 for newer processors. */
1670 max_number_of_nops
= 7;
1675 limit
= max_single_nop_size
;
1677 if (fragP
->fr_type
== rs_fill_nop
)
1679 /* Output NOPs for .nop directive. */
1680 if (limit
> max_single_nop_size
)
1682 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1683 _("invalid single nop size: %d "
1684 "(expect within [0, %d])"),
1685 limit
, max_single_nop_size
);
1689 else if (fragP
->fr_type
!= rs_machine_dependent
)
1690 fragP
->fr_var
= count
;
1692 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1694 /* Generate jump over NOPs. */
1695 offsetT disp
= count
- 2;
1696 if (fits_in_imm7 (disp
))
1698 /* Use "jmp disp8" if possible. */
1700 where
[0] = jump_disp8
[0];
1706 unsigned int size_of_jump
;
1708 if (flag_code
== CODE_16BIT
)
1710 where
[0] = jump16_disp32
[0];
1711 where
[1] = jump16_disp32
[1];
1716 where
[0] = jump32_disp32
[0];
1720 count
-= size_of_jump
+ 4;
1721 if (!fits_in_imm31 (count
))
1723 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1724 _("jump over nop padding out of range"));
1728 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1729 where
+= size_of_jump
+ 4;
1733 /* Generate multiple NOPs. */
1734 i386_output_nops (where
, patt
, count
, limit
);
1738 operand_type_all_zero (const union i386_operand_type
*x
)
1740 switch (ARRAY_SIZE(x
->array
))
1751 return !x
->array
[0];
1758 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1760 switch (ARRAY_SIZE(x
->array
))
1776 x
->bitfield
.class = ClassNone
;
1777 x
->bitfield
.instance
= InstanceNone
;
1781 operand_type_equal (const union i386_operand_type
*x
,
1782 const union i386_operand_type
*y
)
1784 switch (ARRAY_SIZE(x
->array
))
1787 if (x
->array
[2] != y
->array
[2])
1791 if (x
->array
[1] != y
->array
[1])
1795 return x
->array
[0] == y
->array
[0];
1803 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1805 switch (ARRAY_SIZE(x
->array
))
1820 return !x
->array
[0];
1827 cpu_flags_equal (const union i386_cpu_flags
*x
,
1828 const union i386_cpu_flags
*y
)
1830 switch (ARRAY_SIZE(x
->array
))
1833 if (x
->array
[3] != y
->array
[3])
1837 if (x
->array
[2] != y
->array
[2])
1841 if (x
->array
[1] != y
->array
[1])
1845 return x
->array
[0] == y
->array
[0];
1853 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1855 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1856 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1859 static INLINE i386_cpu_flags
1860 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1862 switch (ARRAY_SIZE (x
.array
))
1865 x
.array
[3] &= y
.array
[3];
1868 x
.array
[2] &= y
.array
[2];
1871 x
.array
[1] &= y
.array
[1];
1874 x
.array
[0] &= y
.array
[0];
1882 static INLINE i386_cpu_flags
1883 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1885 switch (ARRAY_SIZE (x
.array
))
1888 x
.array
[3] |= y
.array
[3];
1891 x
.array
[2] |= y
.array
[2];
1894 x
.array
[1] |= y
.array
[1];
1897 x
.array
[0] |= y
.array
[0];
1905 static INLINE i386_cpu_flags
1906 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1908 switch (ARRAY_SIZE (x
.array
))
1911 x
.array
[3] &= ~y
.array
[3];
1914 x
.array
[2] &= ~y
.array
[2];
1917 x
.array
[1] &= ~y
.array
[1];
1920 x
.array
[0] &= ~y
.array
[0];
1928 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1930 #define CPU_FLAGS_ARCH_MATCH 0x1
1931 #define CPU_FLAGS_64BIT_MATCH 0x2
1933 #define CPU_FLAGS_PERFECT_MATCH \
1934 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1936 /* Return CPU flags match bits. */
1939 cpu_flags_match (const insn_template
*t
)
1941 i386_cpu_flags x
= t
->cpu_flags
;
1942 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1944 x
.bitfield
.cpu64
= 0;
1945 x
.bitfield
.cpuno64
= 0;
1947 if (cpu_flags_all_zero (&x
))
1949 /* This instruction is available on all archs. */
1950 match
|= CPU_FLAGS_ARCH_MATCH
;
1954 /* This instruction is available only on some archs. */
1955 i386_cpu_flags cpu
= cpu_arch_flags
;
1957 /* AVX512VL is no standalone feature - match it and then strip it. */
1958 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1960 x
.bitfield
.cpuavx512vl
= 0;
1962 cpu
= cpu_flags_and (x
, cpu
);
1963 if (!cpu_flags_all_zero (&cpu
))
1965 if (x
.bitfield
.cpuavx
)
1967 /* We need to check a few extra flags with AVX. */
1968 if (cpu
.bitfield
.cpuavx
1969 && (!t
->opcode_modifier
.sse2avx
1970 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1971 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1972 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1973 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1974 match
|= CPU_FLAGS_ARCH_MATCH
;
1976 else if (x
.bitfield
.cpuavx512f
)
1978 /* We need to check a few extra flags with AVX512F. */
1979 if (cpu
.bitfield
.cpuavx512f
1980 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1981 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1982 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1983 match
|= CPU_FLAGS_ARCH_MATCH
;
1986 match
|= CPU_FLAGS_ARCH_MATCH
;
1992 static INLINE i386_operand_type
1993 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1995 if (x
.bitfield
.class != y
.bitfield
.class)
1996 x
.bitfield
.class = ClassNone
;
1997 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1998 x
.bitfield
.instance
= InstanceNone
;
2000 switch (ARRAY_SIZE (x
.array
))
2003 x
.array
[2] &= y
.array
[2];
2006 x
.array
[1] &= y
.array
[1];
2009 x
.array
[0] &= y
.array
[0];
2017 static INLINE i386_operand_type
2018 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2020 gas_assert (y
.bitfield
.class == ClassNone
);
2021 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2023 switch (ARRAY_SIZE (x
.array
))
2026 x
.array
[2] &= ~y
.array
[2];
2029 x
.array
[1] &= ~y
.array
[1];
2032 x
.array
[0] &= ~y
.array
[0];
2040 static INLINE i386_operand_type
2041 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2043 gas_assert (x
.bitfield
.class == ClassNone
||
2044 y
.bitfield
.class == ClassNone
||
2045 x
.bitfield
.class == y
.bitfield
.class);
2046 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2047 y
.bitfield
.instance
== InstanceNone
||
2048 x
.bitfield
.instance
== y
.bitfield
.instance
);
2050 switch (ARRAY_SIZE (x
.array
))
2053 x
.array
[2] |= y
.array
[2];
2056 x
.array
[1] |= y
.array
[1];
2059 x
.array
[0] |= y
.array
[0];
2067 static INLINE i386_operand_type
2068 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2070 gas_assert (y
.bitfield
.class == ClassNone
);
2071 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2073 switch (ARRAY_SIZE (x
.array
))
2076 x
.array
[2] ^= y
.array
[2];
2079 x
.array
[1] ^= y
.array
[1];
2082 x
.array
[0] ^= y
.array
[0];
2090 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2091 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2092 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2093 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2094 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2095 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2096 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2097 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2098 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2099 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2100 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2101 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2102 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2103 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2104 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2105 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2106 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2117 operand_type_check (i386_operand_type t
, enum operand_type c
)
2122 return t
.bitfield
.class == Reg
;
2125 return (t
.bitfield
.imm8
2129 || t
.bitfield
.imm32s
2130 || t
.bitfield
.imm64
);
2133 return (t
.bitfield
.disp8
2134 || t
.bitfield
.disp16
2135 || t
.bitfield
.disp32
2136 || t
.bitfield
.disp32s
2137 || t
.bitfield
.disp64
);
2140 return (t
.bitfield
.disp8
2141 || t
.bitfield
.disp16
2142 || t
.bitfield
.disp32
2143 || t
.bitfield
.disp32s
2144 || t
.bitfield
.disp64
2145 || t
.bitfield
.baseindex
);
2154 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2155 between operand GIVEN and opeand WANTED for instruction template T. */
2158 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2161 return !((i
.types
[given
].bitfield
.byte
2162 && !t
->operand_types
[wanted
].bitfield
.byte
)
2163 || (i
.types
[given
].bitfield
.word
2164 && !t
->operand_types
[wanted
].bitfield
.word
)
2165 || (i
.types
[given
].bitfield
.dword
2166 && !t
->operand_types
[wanted
].bitfield
.dword
)
2167 || (i
.types
[given
].bitfield
.qword
2168 && !t
->operand_types
[wanted
].bitfield
.qword
)
2169 || (i
.types
[given
].bitfield
.tbyte
2170 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2173 /* Return 1 if there is no conflict in SIMD register between operand
2174 GIVEN and opeand WANTED for instruction template T. */
2177 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2180 return !((i
.types
[given
].bitfield
.xmmword
2181 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2182 || (i
.types
[given
].bitfield
.ymmword
2183 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2184 || (i
.types
[given
].bitfield
.zmmword
2185 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2186 || (i
.types
[given
].bitfield
.tmmword
2187 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2190 /* Return 1 if there is no conflict in any size between operand GIVEN
2191 and opeand WANTED for instruction template T. */
2194 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2197 return (match_operand_size (t
, wanted
, given
)
2198 && !((i
.types
[given
].bitfield
.unspecified
2200 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2201 || (i
.types
[given
].bitfield
.fword
2202 && !t
->operand_types
[wanted
].bitfield
.fword
)
2203 /* For scalar opcode templates to allow register and memory
2204 operands at the same time, some special casing is needed
2205 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2206 down-conversion vpmov*. */
2207 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2208 && t
->operand_types
[wanted
].bitfield
.byte
2209 + t
->operand_types
[wanted
].bitfield
.word
2210 + t
->operand_types
[wanted
].bitfield
.dword
2211 + t
->operand_types
[wanted
].bitfield
.qword
2212 > !!t
->opcode_modifier
.broadcast
)
2213 ? (i
.types
[given
].bitfield
.xmmword
2214 || i
.types
[given
].bitfield
.ymmword
2215 || i
.types
[given
].bitfield
.zmmword
)
2216 : !match_simd_size(t
, wanted
, given
))));
2219 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2220 operands for instruction template T, and it has MATCH_REVERSE set if there
2221 is no size conflict on any operands for the template with operands reversed
2222 (and the template allows for reversing in the first place). */
2224 #define MATCH_STRAIGHT 1
2225 #define MATCH_REVERSE 2
2227 static INLINE
unsigned int
2228 operand_size_match (const insn_template
*t
)
2230 unsigned int j
, match
= MATCH_STRAIGHT
;
2232 /* Don't check non-absolute jump instructions. */
2233 if (t
->opcode_modifier
.jump
2234 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2237 /* Check memory and accumulator operand size. */
2238 for (j
= 0; j
< i
.operands
; j
++)
2240 if (i
.types
[j
].bitfield
.class != Reg
2241 && i
.types
[j
].bitfield
.class != RegSIMD
2242 && t
->opcode_modifier
.anysize
)
2245 if (t
->operand_types
[j
].bitfield
.class == Reg
2246 && !match_operand_size (t
, j
, j
))
2252 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2253 && !match_simd_size (t
, j
, j
))
2259 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2260 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2266 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2273 if (!t
->opcode_modifier
.d
)
2277 i
.error
= operand_size_mismatch
;
2281 /* Check reverse. */
2282 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2284 for (j
= 0; j
< i
.operands
; j
++)
2286 unsigned int given
= i
.operands
- j
- 1;
2288 if (t
->operand_types
[j
].bitfield
.class == Reg
2289 && !match_operand_size (t
, j
, given
))
2292 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2293 && !match_simd_size (t
, j
, given
))
2296 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2297 && (!match_operand_size (t
, j
, given
)
2298 || !match_simd_size (t
, j
, given
)))
2301 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2305 return match
| MATCH_REVERSE
;
2309 operand_type_match (i386_operand_type overlap
,
2310 i386_operand_type given
)
2312 i386_operand_type temp
= overlap
;
2314 temp
.bitfield
.unspecified
= 0;
2315 temp
.bitfield
.byte
= 0;
2316 temp
.bitfield
.word
= 0;
2317 temp
.bitfield
.dword
= 0;
2318 temp
.bitfield
.fword
= 0;
2319 temp
.bitfield
.qword
= 0;
2320 temp
.bitfield
.tbyte
= 0;
2321 temp
.bitfield
.xmmword
= 0;
2322 temp
.bitfield
.ymmword
= 0;
2323 temp
.bitfield
.zmmword
= 0;
2324 temp
.bitfield
.tmmword
= 0;
2325 if (operand_type_all_zero (&temp
))
2328 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2332 i
.error
= operand_type_mismatch
;
2336 /* If given types g0 and g1 are registers they must be of the same type
2337 unless the expected operand type register overlap is null.
2338 Some Intel syntax memory operand size checking also happens here. */
2341 operand_type_register_match (i386_operand_type g0
,
2342 i386_operand_type t0
,
2343 i386_operand_type g1
,
2344 i386_operand_type t1
)
2346 if (g0
.bitfield
.class != Reg
2347 && g0
.bitfield
.class != RegSIMD
2348 && (!operand_type_check (g0
, anymem
)
2349 || g0
.bitfield
.unspecified
2350 || (t0
.bitfield
.class != Reg
2351 && t0
.bitfield
.class != RegSIMD
)))
2354 if (g1
.bitfield
.class != Reg
2355 && g1
.bitfield
.class != RegSIMD
2356 && (!operand_type_check (g1
, anymem
)
2357 || g1
.bitfield
.unspecified
2358 || (t1
.bitfield
.class != Reg
2359 && t1
.bitfield
.class != RegSIMD
)))
2362 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2363 && g0
.bitfield
.word
== g1
.bitfield
.word
2364 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2365 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2366 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2367 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2368 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2371 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2372 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2373 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2374 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2375 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2376 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2377 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2380 i
.error
= register_type_mismatch
;
2385 static INLINE
unsigned int
2386 register_number (const reg_entry
*r
)
2388 unsigned int nr
= r
->reg_num
;
2390 if (r
->reg_flags
& RegRex
)
2393 if (r
->reg_flags
& RegVRex
)
2399 static INLINE
unsigned int
2400 mode_from_disp_size (i386_operand_type t
)
2402 if (t
.bitfield
.disp8
)
2404 else if (t
.bitfield
.disp16
2405 || t
.bitfield
.disp32
2406 || t
.bitfield
.disp32s
)
2413 fits_in_signed_byte (addressT num
)
2415 return num
+ 0x80 <= 0xff;
2419 fits_in_unsigned_byte (addressT num
)
2425 fits_in_unsigned_word (addressT num
)
2427 return num
<= 0xffff;
2431 fits_in_signed_word (addressT num
)
2433 return num
+ 0x8000 <= 0xffff;
2437 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2442 return num
+ 0x80000000 <= 0xffffffff;
2444 } /* fits_in_signed_long() */
2447 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2452 return num
<= 0xffffffff;
2454 } /* fits_in_unsigned_long() */
2457 fits_in_disp8 (offsetT num
)
2459 int shift
= i
.memshift
;
2465 mask
= (1 << shift
) - 1;
2467 /* Return 0 if NUM isn't properly aligned. */
2471 /* Check if NUM will fit in 8bit after shift. */
2472 return fits_in_signed_byte (num
>> shift
);
2476 fits_in_imm4 (offsetT num
)
2478 return (num
& 0xf) == num
;
2481 static i386_operand_type
2482 smallest_imm_type (offsetT num
)
2484 i386_operand_type t
;
2486 operand_type_set (&t
, 0);
2487 t
.bitfield
.imm64
= 1;
2489 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2491 /* This code is disabled on the 486 because all the Imm1 forms
2492 in the opcode table are slower on the i486. They're the
2493 versions with the implicitly specified single-position
2494 displacement, which has another syntax if you really want to
2496 t
.bitfield
.imm1
= 1;
2497 t
.bitfield
.imm8
= 1;
2498 t
.bitfield
.imm8s
= 1;
2499 t
.bitfield
.imm16
= 1;
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_signed_byte (num
))
2505 t
.bitfield
.imm8
= 1;
2506 t
.bitfield
.imm8s
= 1;
2507 t
.bitfield
.imm16
= 1;
2508 t
.bitfield
.imm32
= 1;
2509 t
.bitfield
.imm32s
= 1;
2511 else if (fits_in_unsigned_byte (num
))
2513 t
.bitfield
.imm8
= 1;
2514 t
.bitfield
.imm16
= 1;
2515 t
.bitfield
.imm32
= 1;
2516 t
.bitfield
.imm32s
= 1;
2518 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2520 t
.bitfield
.imm16
= 1;
2521 t
.bitfield
.imm32
= 1;
2522 t
.bitfield
.imm32s
= 1;
2524 else if (fits_in_signed_long (num
))
2526 t
.bitfield
.imm32
= 1;
2527 t
.bitfield
.imm32s
= 1;
2529 else if (fits_in_unsigned_long (num
))
2530 t
.bitfield
.imm32
= 1;
2536 offset_in_range (offsetT val
, int size
)
2542 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2543 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2544 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2546 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2551 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2553 char buf1
[40], buf2
[40];
2555 sprint_value (buf1
, val
);
2556 sprint_value (buf2
, val
& mask
);
2557 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2572 a. PREFIX_EXIST if attempting to add a prefix where one from the
2573 same class already exists.
2574 b. PREFIX_LOCK if lock prefix is added.
2575 c. PREFIX_REP if rep/repne prefix is added.
2576 d. PREFIX_DS if ds prefix is added.
2577 e. PREFIX_OTHER if other prefix is added.
2580 static enum PREFIX_GROUP
2581 add_prefix (unsigned int prefix
)
2583 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2586 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2587 && flag_code
== CODE_64BIT
)
2589 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2590 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2591 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2592 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2603 case DS_PREFIX_OPCODE
:
2606 case CS_PREFIX_OPCODE
:
2607 case ES_PREFIX_OPCODE
:
2608 case FS_PREFIX_OPCODE
:
2609 case GS_PREFIX_OPCODE
:
2610 case SS_PREFIX_OPCODE
:
2614 case REPNE_PREFIX_OPCODE
:
2615 case REPE_PREFIX_OPCODE
:
2620 case LOCK_PREFIX_OPCODE
:
2629 case ADDR_PREFIX_OPCODE
:
2633 case DATA_PREFIX_OPCODE
:
2637 if (i
.prefix
[q
] != 0)
2645 i
.prefix
[q
] |= prefix
;
2648 as_bad (_("same type of prefix used twice"));
2654 update_code_flag (int value
, int check
)
2656 PRINTF_LIKE ((*as_error
));
2658 flag_code
= (enum flag_code
) value
;
2659 if (flag_code
== CODE_64BIT
)
2661 cpu_arch_flags
.bitfield
.cpu64
= 1;
2662 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2666 cpu_arch_flags
.bitfield
.cpu64
= 0;
2667 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2669 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2672 as_error
= as_fatal
;
2675 (*as_error
) (_("64bit mode not supported on `%s'."),
2676 cpu_arch_name
? cpu_arch_name
: default_arch
);
2678 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2681 as_error
= as_fatal
;
2684 (*as_error
) (_("32bit mode not supported on `%s'."),
2685 cpu_arch_name
? cpu_arch_name
: default_arch
);
2687 stackop_size
= '\0';
2691 set_code_flag (int value
)
2693 update_code_flag (value
, 0);
2697 set_16bit_gcc_code_flag (int new_code_flag
)
2699 flag_code
= (enum flag_code
) new_code_flag
;
2700 if (flag_code
!= CODE_16BIT
)
2702 cpu_arch_flags
.bitfield
.cpu64
= 0;
2703 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2704 stackop_size
= LONG_MNEM_SUFFIX
;
2708 set_intel_syntax (int syntax_flag
)
2710 /* Find out if register prefixing is specified. */
2711 int ask_naked_reg
= 0;
2714 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2717 int e
= get_symbol_name (&string
);
2719 if (strcmp (string
, "prefix") == 0)
2721 else if (strcmp (string
, "noprefix") == 0)
2724 as_bad (_("bad argument to syntax directive."));
2725 (void) restore_line_pointer (e
);
2727 demand_empty_rest_of_line ();
2729 intel_syntax
= syntax_flag
;
2731 if (ask_naked_reg
== 0)
2732 allow_naked_reg
= (intel_syntax
2733 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2735 allow_naked_reg
= (ask_naked_reg
< 0);
2737 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2739 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2740 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2741 register_prefix
= allow_naked_reg
? "" : "%";
2745 set_intel_mnemonic (int mnemonic_flag
)
2747 intel_mnemonic
= mnemonic_flag
;
2751 set_allow_index_reg (int flag
)
2753 allow_index_reg
= flag
;
2757 set_check (int what
)
2759 enum check_kind
*kind
;
2764 kind
= &operand_check
;
2775 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2778 int e
= get_symbol_name (&string
);
2780 if (strcmp (string
, "none") == 0)
2782 else if (strcmp (string
, "warning") == 0)
2783 *kind
= check_warning
;
2784 else if (strcmp (string
, "error") == 0)
2785 *kind
= check_error
;
2787 as_bad (_("bad argument to %s_check directive."), str
);
2788 (void) restore_line_pointer (e
);
2791 as_bad (_("missing argument for %s_check directive"), str
);
2793 demand_empty_rest_of_line ();
2797 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2798 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2801 static const char *arch
;
2803 /* Intel LIOM is only supported on ELF. */
2809 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2810 use default_arch. */
2811 arch
= cpu_arch_name
;
2813 arch
= default_arch
;
2816 /* If we are targeting Intel MCU, we must enable it. */
2817 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2818 || new_flag
.bitfield
.cpuiamcu
)
2821 /* If we are targeting Intel L1OM, we must enable it. */
2822 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2823 || new_flag
.bitfield
.cpul1om
)
2826 /* If we are targeting Intel K1OM, we must enable it. */
2827 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2828 || new_flag
.bitfield
.cpuk1om
)
2831 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2836 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2840 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2843 int e
= get_symbol_name (&string
);
2845 i386_cpu_flags flags
;
2847 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2849 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2851 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2855 cpu_arch_name
= cpu_arch
[j
].name
;
2856 cpu_sub_arch_name
= NULL
;
2857 cpu_arch_flags
= cpu_arch
[j
].flags
;
2858 if (flag_code
== CODE_64BIT
)
2860 cpu_arch_flags
.bitfield
.cpu64
= 1;
2861 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2865 cpu_arch_flags
.bitfield
.cpu64
= 0;
2866 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2868 cpu_arch_isa
= cpu_arch
[j
].type
;
2869 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2870 if (!cpu_arch_tune_set
)
2872 cpu_arch_tune
= cpu_arch_isa
;
2873 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2878 flags
= cpu_flags_or (cpu_arch_flags
,
2881 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2883 if (cpu_sub_arch_name
)
2885 char *name
= cpu_sub_arch_name
;
2886 cpu_sub_arch_name
= concat (name
,
2888 (const char *) NULL
);
2892 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2893 cpu_arch_flags
= flags
;
2894 cpu_arch_isa_flags
= flags
;
2898 = cpu_flags_or (cpu_arch_isa_flags
,
2900 (void) restore_line_pointer (e
);
2901 demand_empty_rest_of_line ();
2906 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2908 /* Disable an ISA extension. */
2909 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2910 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2912 flags
= cpu_flags_and_not (cpu_arch_flags
,
2913 cpu_noarch
[j
].flags
);
2914 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2916 if (cpu_sub_arch_name
)
2918 char *name
= cpu_sub_arch_name
;
2919 cpu_sub_arch_name
= concat (name
, string
,
2920 (const char *) NULL
);
2924 cpu_sub_arch_name
= xstrdup (string
);
2925 cpu_arch_flags
= flags
;
2926 cpu_arch_isa_flags
= flags
;
2928 (void) restore_line_pointer (e
);
2929 demand_empty_rest_of_line ();
2933 j
= ARRAY_SIZE (cpu_arch
);
2936 if (j
>= ARRAY_SIZE (cpu_arch
))
2937 as_bad (_("no such architecture: `%s'"), string
);
2939 *input_line_pointer
= e
;
2942 as_bad (_("missing cpu architecture"));
2944 no_cond_jump_promotion
= 0;
2945 if (*input_line_pointer
== ','
2946 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2951 ++input_line_pointer
;
2952 e
= get_symbol_name (&string
);
2954 if (strcmp (string
, "nojumps") == 0)
2955 no_cond_jump_promotion
= 1;
2956 else if (strcmp (string
, "jumps") == 0)
2959 as_bad (_("no such architecture modifier: `%s'"), string
);
2961 (void) restore_line_pointer (e
);
2964 demand_empty_rest_of_line ();
2967 enum bfd_architecture
2970 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2972 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2973 || flag_code
!= CODE_64BIT
)
2974 as_fatal (_("Intel L1OM is 64bit ELF only"));
2975 return bfd_arch_l1om
;
2977 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2979 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2980 || flag_code
!= CODE_64BIT
)
2981 as_fatal (_("Intel K1OM is 64bit ELF only"));
2982 return bfd_arch_k1om
;
2984 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2986 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2987 || flag_code
== CODE_64BIT
)
2988 as_fatal (_("Intel MCU is 32bit ELF only"));
2989 return bfd_arch_iamcu
;
2992 return bfd_arch_i386
;
2998 if (!strncmp (default_arch
, "x86_64", 6))
3000 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3002 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3003 || default_arch
[6] != '\0')
3004 as_fatal (_("Intel L1OM is 64bit ELF only"));
3005 return bfd_mach_l1om
;
3007 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3009 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3010 || default_arch
[6] != '\0')
3011 as_fatal (_("Intel K1OM is 64bit ELF only"));
3012 return bfd_mach_k1om
;
3014 else if (default_arch
[6] == '\0')
3015 return bfd_mach_x86_64
;
3017 return bfd_mach_x64_32
;
3019 else if (!strcmp (default_arch
, "i386")
3020 || !strcmp (default_arch
, "iamcu"))
3022 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3024 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3025 as_fatal (_("Intel MCU is 32bit ELF only"));
3026 return bfd_mach_i386_iamcu
;
3029 return bfd_mach_i386_i386
;
3032 as_fatal (_("unknown architecture"));
3038 /* Support pseudo prefixes like {disp32}. */
3039 lex_type
['{'] = LEX_BEGIN_NAME
;
3041 /* Initialize op_hash hash table. */
3042 op_hash
= str_htab_create ();
3045 const insn_template
*optab
;
3046 templates
*core_optab
;
3048 /* Setup for loop. */
3050 core_optab
= XNEW (templates
);
3051 core_optab
->start
= optab
;
3056 if (optab
->name
== NULL
3057 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3059 /* different name --> ship out current template list;
3060 add to hash table; & begin anew. */
3061 core_optab
->end
= optab
;
3062 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3063 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3065 if (optab
->name
== NULL
)
3067 core_optab
= XNEW (templates
);
3068 core_optab
->start
= optab
;
3073 /* Initialize reg_hash hash table. */
3074 reg_hash
= str_htab_create ();
3076 const reg_entry
*regtab
;
3077 unsigned int regtab_size
= i386_regtab_size
;
3079 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3080 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3081 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3084 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3089 for (c
= 0; c
< 256; c
++)
3094 mnemonic_chars
[c
] = c
;
3095 register_chars
[c
] = c
;
3096 operand_chars
[c
] = c
;
3098 else if (ISLOWER (c
))
3100 mnemonic_chars
[c
] = c
;
3101 register_chars
[c
] = c
;
3102 operand_chars
[c
] = c
;
3104 else if (ISUPPER (c
))
3106 mnemonic_chars
[c
] = TOLOWER (c
);
3107 register_chars
[c
] = mnemonic_chars
[c
];
3108 operand_chars
[c
] = c
;
3110 else if (c
== '{' || c
== '}')
3112 mnemonic_chars
[c
] = c
;
3113 operand_chars
[c
] = c
;
3115 #ifdef SVR4_COMMENT_CHARS
3116 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3117 operand_chars
[c
] = c
;
3120 if (ISALPHA (c
) || ISDIGIT (c
))
3121 identifier_chars
[c
] = c
;
3124 identifier_chars
[c
] = c
;
3125 operand_chars
[c
] = c
;
3130 identifier_chars
['@'] = '@';
3133 identifier_chars
['?'] = '?';
3134 operand_chars
['?'] = '?';
3136 digit_chars
['-'] = '-';
3137 mnemonic_chars
['_'] = '_';
3138 mnemonic_chars
['-'] = '-';
3139 mnemonic_chars
['.'] = '.';
3140 identifier_chars
['_'] = '_';
3141 identifier_chars
['.'] = '.';
3143 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3144 operand_chars
[(unsigned char) *p
] = *p
;
3147 if (flag_code
== CODE_64BIT
)
3149 #if defined (OBJ_COFF) && defined (TE_PE)
3150 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3153 x86_dwarf2_return_column
= 16;
3155 x86_cie_data_alignment
= -8;
3159 x86_dwarf2_return_column
= 8;
3160 x86_cie_data_alignment
= -4;
3163 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3164 can be turned into BRANCH_PREFIX frag. */
3165 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3170 i386_print_statistics (FILE *file
)
3172 htab_print_statistics (file
, "i386 opcode", op_hash
);
3173 htab_print_statistics (file
, "i386 register", reg_hash
);
3178 /* Debugging routines for md_assemble. */
3179 static void pte (insn_template
*);
3180 static void pt (i386_operand_type
);
3181 static void pe (expressionS
*);
3182 static void ps (symbolS
*);
3185 pi (const char *line
, i386_insn
*x
)
3189 fprintf (stdout
, "%s: template ", line
);
3191 fprintf (stdout
, " address: base %s index %s scale %x\n",
3192 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3193 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3194 x
->log2_scale_factor
);
3195 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3196 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3197 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3198 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3199 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3200 (x
->rex
& REX_W
) != 0,
3201 (x
->rex
& REX_R
) != 0,
3202 (x
->rex
& REX_X
) != 0,
3203 (x
->rex
& REX_B
) != 0);
3204 for (j
= 0; j
< x
->operands
; j
++)
3206 fprintf (stdout
, " #%d: ", j
+ 1);
3208 fprintf (stdout
, "\n");
3209 if (x
->types
[j
].bitfield
.class == Reg
3210 || x
->types
[j
].bitfield
.class == RegMMX
3211 || x
->types
[j
].bitfield
.class == RegSIMD
3212 || x
->types
[j
].bitfield
.class == RegMask
3213 || x
->types
[j
].bitfield
.class == SReg
3214 || x
->types
[j
].bitfield
.class == RegCR
3215 || x
->types
[j
].bitfield
.class == RegDR
3216 || x
->types
[j
].bitfield
.class == RegTR
3217 || x
->types
[j
].bitfield
.class == RegBND
)
3218 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3219 if (operand_type_check (x
->types
[j
], imm
))
3221 if (operand_type_check (x
->types
[j
], disp
))
3222 pe (x
->op
[j
].disps
);
3227 pte (insn_template
*t
)
3230 fprintf (stdout
, " %d operands ", t
->operands
);
3231 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3232 if (t
->extension_opcode
!= None
)
3233 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3234 if (t
->opcode_modifier
.d
)
3235 fprintf (stdout
, "D");
3236 if (t
->opcode_modifier
.w
)
3237 fprintf (stdout
, "W");
3238 fprintf (stdout
, "\n");
3239 for (j
= 0; j
< t
->operands
; j
++)
3241 fprintf (stdout
, " #%d type ", j
+ 1);
3242 pt (t
->operand_types
[j
]);
3243 fprintf (stdout
, "\n");
3250 fprintf (stdout
, " operation %d\n", e
->X_op
);
3251 fprintf (stdout
, " add_number %ld (%lx)\n",
3252 (long) e
->X_add_number
, (long) e
->X_add_number
);
3253 if (e
->X_add_symbol
)
3255 fprintf (stdout
, " add_symbol ");
3256 ps (e
->X_add_symbol
);
3257 fprintf (stdout
, "\n");
3261 fprintf (stdout
, " op_symbol ");
3262 ps (e
->X_op_symbol
);
3263 fprintf (stdout
, "\n");
3270 fprintf (stdout
, "%s type %s%s",
3272 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3273 segment_name (S_GET_SEGMENT (s
)));
3276 static struct type_name
3278 i386_operand_type mask
;
3281 const type_names
[] =
3283 { OPERAND_TYPE_REG8
, "r8" },
3284 { OPERAND_TYPE_REG16
, "r16" },
3285 { OPERAND_TYPE_REG32
, "r32" },
3286 { OPERAND_TYPE_REG64
, "r64" },
3287 { OPERAND_TYPE_ACC8
, "acc8" },
3288 { OPERAND_TYPE_ACC16
, "acc16" },
3289 { OPERAND_TYPE_ACC32
, "acc32" },
3290 { OPERAND_TYPE_ACC64
, "acc64" },
3291 { OPERAND_TYPE_IMM8
, "i8" },
3292 { OPERAND_TYPE_IMM8
, "i8s" },
3293 { OPERAND_TYPE_IMM16
, "i16" },
3294 { OPERAND_TYPE_IMM32
, "i32" },
3295 { OPERAND_TYPE_IMM32S
, "i32s" },
3296 { OPERAND_TYPE_IMM64
, "i64" },
3297 { OPERAND_TYPE_IMM1
, "i1" },
3298 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3299 { OPERAND_TYPE_DISP8
, "d8" },
3300 { OPERAND_TYPE_DISP16
, "d16" },
3301 { OPERAND_TYPE_DISP32
, "d32" },
3302 { OPERAND_TYPE_DISP32S
, "d32s" },
3303 { OPERAND_TYPE_DISP64
, "d64" },
3304 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3305 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3306 { OPERAND_TYPE_CONTROL
, "control reg" },
3307 { OPERAND_TYPE_TEST
, "test reg" },
3308 { OPERAND_TYPE_DEBUG
, "debug reg" },
3309 { OPERAND_TYPE_FLOATREG
, "FReg" },
3310 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3311 { OPERAND_TYPE_SREG
, "SReg" },
3312 { OPERAND_TYPE_REGMMX
, "rMMX" },
3313 { OPERAND_TYPE_REGXMM
, "rXMM" },
3314 { OPERAND_TYPE_REGYMM
, "rYMM" },
3315 { OPERAND_TYPE_REGZMM
, "rZMM" },
3316 { OPERAND_TYPE_REGTMM
, "rTMM" },
3317 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3321 pt (i386_operand_type t
)
3324 i386_operand_type a
;
3326 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3328 a
= operand_type_and (t
, type_names
[j
].mask
);
3329 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3330 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3335 #endif /* DEBUG386 */
3337 static bfd_reloc_code_real_type
3338 reloc (unsigned int size
,
3341 bfd_reloc_code_real_type other
)
3343 if (other
!= NO_RELOC
)
3345 reloc_howto_type
*rel
;
3350 case BFD_RELOC_X86_64_GOT32
:
3351 return BFD_RELOC_X86_64_GOT64
;
3353 case BFD_RELOC_X86_64_GOTPLT64
:
3354 return BFD_RELOC_X86_64_GOTPLT64
;
3356 case BFD_RELOC_X86_64_PLTOFF64
:
3357 return BFD_RELOC_X86_64_PLTOFF64
;
3359 case BFD_RELOC_X86_64_GOTPC32
:
3360 other
= BFD_RELOC_X86_64_GOTPC64
;
3362 case BFD_RELOC_X86_64_GOTPCREL
:
3363 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3365 case BFD_RELOC_X86_64_TPOFF32
:
3366 other
= BFD_RELOC_X86_64_TPOFF64
;
3368 case BFD_RELOC_X86_64_DTPOFF32
:
3369 other
= BFD_RELOC_X86_64_DTPOFF64
;
3375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3376 if (other
== BFD_RELOC_SIZE32
)
3379 other
= BFD_RELOC_SIZE64
;
3382 as_bad (_("there are no pc-relative size relocations"));
3388 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3389 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3392 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3394 as_bad (_("unknown relocation (%u)"), other
);
3395 else if (size
!= bfd_get_reloc_size (rel
))
3396 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3397 bfd_get_reloc_size (rel
),
3399 else if (pcrel
&& !rel
->pc_relative
)
3400 as_bad (_("non-pc-relative relocation for pc-relative field"));
3401 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3403 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3405 as_bad (_("relocated field and relocation type differ in signedness"));
3414 as_bad (_("there are no unsigned pc-relative relocations"));
3417 case 1: return BFD_RELOC_8_PCREL
;
3418 case 2: return BFD_RELOC_16_PCREL
;
3419 case 4: return BFD_RELOC_32_PCREL
;
3420 case 8: return BFD_RELOC_64_PCREL
;
3422 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3429 case 4: return BFD_RELOC_X86_64_32S
;
3434 case 1: return BFD_RELOC_8
;
3435 case 2: return BFD_RELOC_16
;
3436 case 4: return BFD_RELOC_32
;
3437 case 8: return BFD_RELOC_64
;
3439 as_bad (_("cannot do %s %u byte relocation"),
3440 sign
> 0 ? "signed" : "unsigned", size
);
3446 /* Here we decide which fixups can be adjusted to make them relative to
3447 the beginning of the section instead of the symbol. Basically we need
3448 to make sure that the dynamic relocations are done correctly, so in
3449 some cases we force the original symbol to be used. */
3452 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3458 /* Don't adjust pc-relative references to merge sections in 64-bit
3460 if (use_rela_relocations
3461 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3465 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3466 and changed later by validate_fix. */
3467 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3468 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3471 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3472 for size relocations. */
3473 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3474 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3475 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3476 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3477 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3479 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3480 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3481 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3485 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3486 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3487 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3499 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3500 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3502 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3503 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3510 intel_float_operand (const char *mnemonic
)
3512 /* Note that the value returned is meaningful only for opcodes with (memory)
3513 operands, hence the code here is free to improperly handle opcodes that
3514 have no operands (for better performance and smaller code). */
3516 if (mnemonic
[0] != 'f')
3517 return 0; /* non-math */
3519 switch (mnemonic
[1])
3521 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3522 the fs segment override prefix not currently handled because no
3523 call path can make opcodes without operands get here */
3525 return 2 /* integer op */;
3527 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3528 return 3; /* fldcw/fldenv */
3531 if (mnemonic
[2] != 'o' /* fnop */)
3532 return 3; /* non-waiting control op */
3535 if (mnemonic
[2] == 's')
3536 return 3; /* frstor/frstpm */
3539 if (mnemonic
[2] == 'a')
3540 return 3; /* fsave */
3541 if (mnemonic
[2] == 't')
3543 switch (mnemonic
[3])
3545 case 'c': /* fstcw */
3546 case 'd': /* fstdw */
3547 case 'e': /* fstenv */
3548 case 's': /* fsts[gw] */
3554 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3555 return 0; /* fxsave/fxrstor are not really math ops */
3562 /* Build the VEX prefix. */
3565 build_vex_prefix (const insn_template
*t
)
3567 unsigned int register_specifier
;
3568 unsigned int implied_prefix
;
3569 unsigned int vector_length
;
3572 /* Check register specifier. */
3573 if (i
.vex
.register_specifier
)
3575 register_specifier
=
3576 ~register_number (i
.vex
.register_specifier
) & 0xf;
3577 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3580 register_specifier
= 0xf;
3582 /* Use 2-byte VEX prefix by swapping destination and source operand
3583 if there are more than 1 register operand. */
3584 if (i
.reg_operands
> 1
3585 && i
.vec_encoding
!= vex_encoding_vex3
3586 && i
.dir_encoding
== dir_encoding_default
3587 && i
.operands
== i
.reg_operands
3588 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3589 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3590 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3593 unsigned int xchg
= i
.operands
- 1;
3594 union i386_op temp_op
;
3595 i386_operand_type temp_type
;
3597 temp_type
= i
.types
[xchg
];
3598 i
.types
[xchg
] = i
.types
[0];
3599 i
.types
[0] = temp_type
;
3600 temp_op
= i
.op
[xchg
];
3601 i
.op
[xchg
] = i
.op
[0];
3604 gas_assert (i
.rm
.mode
== 3);
3608 i
.rm
.regmem
= i
.rm
.reg
;
3611 if (i
.tm
.opcode_modifier
.d
)
3612 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3613 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3614 else /* Use the next insn. */
3618 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3619 are no memory operands and at least 3 register ones. */
3620 if (i
.reg_operands
>= 3
3621 && i
.vec_encoding
!= vex_encoding_vex3
3622 && i
.reg_operands
== i
.operands
- i
.imm_operands
3623 && i
.tm
.opcode_modifier
.vex
3624 && i
.tm
.opcode_modifier
.commutative
3625 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3627 && i
.vex
.register_specifier
3628 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3630 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3631 union i386_op temp_op
;
3632 i386_operand_type temp_type
;
3634 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3635 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3636 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3637 &i
.types
[i
.operands
- 3]));
3638 gas_assert (i
.rm
.mode
== 3);
3640 temp_type
= i
.types
[xchg
];
3641 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3642 i
.types
[xchg
+ 1] = temp_type
;
3643 temp_op
= i
.op
[xchg
];
3644 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3645 i
.op
[xchg
+ 1] = temp_op
;
3648 xchg
= i
.rm
.regmem
| 8;
3649 i
.rm
.regmem
= ~register_specifier
& 0xf;
3650 gas_assert (!(i
.rm
.regmem
& 8));
3651 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3652 register_specifier
= ~xchg
& 0xf;
3655 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3656 vector_length
= avxscalar
;
3657 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3663 /* Determine vector length from the last multi-length vector
3666 for (op
= t
->operands
; op
--;)
3667 if (t
->operand_types
[op
].bitfield
.xmmword
3668 && t
->operand_types
[op
].bitfield
.ymmword
3669 && i
.types
[op
].bitfield
.ymmword
)
3676 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3681 case DATA_PREFIX_OPCODE
:
3684 case REPE_PREFIX_OPCODE
:
3687 case REPNE_PREFIX_OPCODE
:
3694 /* Check the REX.W bit and VEXW. */
3695 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3696 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3697 else if (i
.tm
.opcode_modifier
.vexw
)
3698 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3700 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3702 /* Use 2-byte VEX prefix if possible. */
3704 && i
.vec_encoding
!= vex_encoding_vex3
3705 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3706 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3708 /* 2-byte VEX prefix. */
3712 i
.vex
.bytes
[0] = 0xc5;
3714 /* Check the REX.R bit. */
3715 r
= (i
.rex
& REX_R
) ? 0 : 1;
3716 i
.vex
.bytes
[1] = (r
<< 7
3717 | register_specifier
<< 3
3718 | vector_length
<< 2
3723 /* 3-byte VEX prefix. */
3728 switch (i
.tm
.opcode_modifier
.vexopcode
)
3732 i
.vex
.bytes
[0] = 0xc4;
3736 i
.vex
.bytes
[0] = 0xc4;
3740 i
.vex
.bytes
[0] = 0xc4;
3744 i
.vex
.bytes
[0] = 0x8f;
3748 i
.vex
.bytes
[0] = 0x8f;
3752 i
.vex
.bytes
[0] = 0x8f;
3758 /* The high 3 bits of the second VEX byte are 1's compliment
3759 of RXB bits from REX. */
3760 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3762 i
.vex
.bytes
[2] = (w
<< 7
3763 | register_specifier
<< 3
3764 | vector_length
<< 2
3769 static INLINE bfd_boolean
3770 is_evex_encoding (const insn_template
*t
)
3772 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3773 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3774 || t
->opcode_modifier
.sae
;
3777 static INLINE bfd_boolean
3778 is_any_vex_encoding (const insn_template
*t
)
3780 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3781 || is_evex_encoding (t
);
3784 /* Build the EVEX prefix. */
3787 build_evex_prefix (void)
3789 unsigned int register_specifier
;
3790 unsigned int implied_prefix
;
3792 rex_byte vrex_used
= 0;
3794 /* Check register specifier. */
3795 if (i
.vex
.register_specifier
)
3797 gas_assert ((i
.vrex
& REX_X
) == 0);
3799 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3800 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3801 register_specifier
+= 8;
3802 /* The upper 16 registers are encoded in the fourth byte of the
3804 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3805 i
.vex
.bytes
[3] = 0x8;
3806 register_specifier
= ~register_specifier
& 0xf;
3810 register_specifier
= 0xf;
3812 /* Encode upper 16 vector index register in the fourth byte of
3814 if (!(i
.vrex
& REX_X
))
3815 i
.vex
.bytes
[3] = 0x8;
3820 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3825 case DATA_PREFIX_OPCODE
:
3828 case REPE_PREFIX_OPCODE
:
3831 case REPNE_PREFIX_OPCODE
:
3838 /* 4 byte EVEX prefix. */
3840 i
.vex
.bytes
[0] = 0x62;
3843 switch (i
.tm
.opcode_modifier
.vexopcode
)
3859 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3861 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3863 /* The fifth bit of the second EVEX byte is 1's compliment of the
3864 REX_R bit in VREX. */
3865 if (!(i
.vrex
& REX_R
))
3866 i
.vex
.bytes
[1] |= 0x10;
3870 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3872 /* When all operands are registers, the REX_X bit in REX is not
3873 used. We reuse it to encode the upper 16 registers, which is
3874 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3875 as 1's compliment. */
3876 if ((i
.vrex
& REX_B
))
3879 i
.vex
.bytes
[1] &= ~0x40;
3883 /* EVEX instructions shouldn't need the REX prefix. */
3884 i
.vrex
&= ~vrex_used
;
3885 gas_assert (i
.vrex
== 0);
3887 /* Check the REX.W bit and VEXW. */
3888 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3889 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3890 else if (i
.tm
.opcode_modifier
.vexw
)
3891 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3893 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3895 /* Encode the U bit. */
3896 implied_prefix
|= 0x4;
3898 /* The third byte of the EVEX prefix. */
3899 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3901 /* The fourth byte of the EVEX prefix. */
3902 /* The zeroing-masking bit. */
3903 if (i
.mask
&& i
.mask
->zeroing
)
3904 i
.vex
.bytes
[3] |= 0x80;
3906 /* Don't always set the broadcast bit if there is no RC. */
3909 /* Encode the vector length. */
3910 unsigned int vec_length
;
3912 if (!i
.tm
.opcode_modifier
.evex
3913 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3917 /* Determine vector length from the last multi-length vector
3919 for (op
= i
.operands
; op
--;)
3920 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3921 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3922 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3924 if (i
.types
[op
].bitfield
.zmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3929 else if (i
.types
[op
].bitfield
.ymmword
)
3931 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3934 else if (i
.types
[op
].bitfield
.xmmword
)
3936 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3939 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3941 switch (i
.broadcast
->bytes
)
3944 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3947 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3950 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3959 if (op
>= MAX_OPERANDS
)
3963 switch (i
.tm
.opcode_modifier
.evex
)
3965 case EVEXLIG
: /* LL' is ignored */
3966 vec_length
= evexlig
<< 5;
3969 vec_length
= 0 << 5;
3972 vec_length
= 1 << 5;
3975 vec_length
= 2 << 5;
3981 i
.vex
.bytes
[3] |= vec_length
;
3982 /* Encode the broadcast bit. */
3984 i
.vex
.bytes
[3] |= 0x10;
3988 if (i
.rounding
->type
!= saeonly
)
3989 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3991 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3994 if (i
.mask
&& i
.mask
->mask
)
3995 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3999 process_immext (void)
4003 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4004 which is coded in the same place as an 8-bit immediate field
4005 would be. Here we fake an 8-bit immediate operand from the
4006 opcode suffix stored in tm.extension_opcode.
4008 AVX instructions also use this encoding, for some of
4009 3 argument instructions. */
4011 gas_assert (i
.imm_operands
<= 1
4013 || (is_any_vex_encoding (&i
.tm
)
4014 && i
.operands
<= 4)));
4016 exp
= &im_expressions
[i
.imm_operands
++];
4017 i
.op
[i
.operands
].imms
= exp
;
4018 i
.types
[i
.operands
] = imm8
;
4020 exp
->X_op
= O_constant
;
4021 exp
->X_add_number
= i
.tm
.extension_opcode
;
4022 i
.tm
.extension_opcode
= None
;
4029 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4034 as_bad (_("invalid instruction `%s' after `%s'"),
4035 i
.tm
.name
, i
.hle_prefix
);
4038 if (i
.prefix
[LOCK_PREFIX
])
4040 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4044 case HLEPrefixRelease
:
4045 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4047 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4051 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4053 as_bad (_("memory destination needed for instruction `%s'"
4054 " after `xrelease'"), i
.tm
.name
);
4061 /* Try the shortest encoding by shortening operand size. */
4064 optimize_encoding (void)
4068 if (optimize_for_space
4069 && !is_any_vex_encoding (&i
.tm
)
4070 && i
.reg_operands
== 1
4071 && i
.imm_operands
== 1
4072 && !i
.types
[1].bitfield
.byte
4073 && i
.op
[0].imms
->X_op
== O_constant
4074 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4075 && (i
.tm
.base_opcode
== 0xa8
4076 || (i
.tm
.base_opcode
== 0xf6
4077 && i
.tm
.extension_opcode
== 0x0)))
4080 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4082 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4083 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4085 i
.types
[1].bitfield
.byte
= 1;
4086 /* Ignore the suffix. */
4088 /* Convert to byte registers. */
4089 if (i
.types
[1].bitfield
.word
)
4091 else if (i
.types
[1].bitfield
.dword
)
4095 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4100 else if (flag_code
== CODE_64BIT
4101 && !is_any_vex_encoding (&i
.tm
)
4102 && ((i
.types
[1].bitfield
.qword
4103 && i
.reg_operands
== 1
4104 && i
.imm_operands
== 1
4105 && i
.op
[0].imms
->X_op
== O_constant
4106 && ((i
.tm
.base_opcode
== 0xb8
4107 && i
.tm
.extension_opcode
== None
4108 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4109 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4110 && ((i
.tm
.base_opcode
== 0x24
4111 || i
.tm
.base_opcode
== 0xa8)
4112 || (i
.tm
.base_opcode
== 0x80
4113 && i
.tm
.extension_opcode
== 0x4)
4114 || ((i
.tm
.base_opcode
== 0xf6
4115 || (i
.tm
.base_opcode
| 1) == 0xc7)
4116 && i
.tm
.extension_opcode
== 0x0)))
4117 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4118 && i
.tm
.base_opcode
== 0x83
4119 && i
.tm
.extension_opcode
== 0x4)))
4120 || (i
.types
[0].bitfield
.qword
4121 && ((i
.reg_operands
== 2
4122 && i
.op
[0].regs
== i
.op
[1].regs
4123 && (i
.tm
.base_opcode
== 0x30
4124 || i
.tm
.base_opcode
== 0x28))
4125 || (i
.reg_operands
== 1
4127 && i
.tm
.base_opcode
== 0x30)))))
4130 andq $imm31, %r64 -> andl $imm31, %r32
4131 andq $imm7, %r64 -> andl $imm7, %r32
4132 testq $imm31, %r64 -> testl $imm31, %r32
4133 xorq %r64, %r64 -> xorl %r32, %r32
4134 subq %r64, %r64 -> subl %r32, %r32
4135 movq $imm31, %r64 -> movl $imm31, %r32
4136 movq $imm32, %r64 -> movl $imm32, %r32
4138 i
.tm
.opcode_modifier
.norex64
= 1;
4139 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4142 movq $imm31, %r64 -> movl $imm31, %r32
4143 movq $imm32, %r64 -> movl $imm32, %r32
4145 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4146 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4147 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4148 i
.types
[0].bitfield
.imm32
= 1;
4149 i
.types
[0].bitfield
.imm32s
= 0;
4150 i
.types
[0].bitfield
.imm64
= 0;
4151 i
.types
[1].bitfield
.dword
= 1;
4152 i
.types
[1].bitfield
.qword
= 0;
4153 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4156 movq $imm31, %r64 -> movl $imm31, %r32
4158 i
.tm
.base_opcode
= 0xb8;
4159 i
.tm
.extension_opcode
= None
;
4160 i
.tm
.opcode_modifier
.w
= 0;
4161 i
.tm
.opcode_modifier
.modrm
= 0;
4165 else if (optimize
> 1
4166 && !optimize_for_space
4167 && !is_any_vex_encoding (&i
.tm
)
4168 && i
.reg_operands
== 2
4169 && i
.op
[0].regs
== i
.op
[1].regs
4170 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4171 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4172 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4175 andb %rN, %rN -> testb %rN, %rN
4176 andw %rN, %rN -> testw %rN, %rN
4177 andq %rN, %rN -> testq %rN, %rN
4178 orb %rN, %rN -> testb %rN, %rN
4179 orw %rN, %rN -> testw %rN, %rN
4180 orq %rN, %rN -> testq %rN, %rN
4182 and outside of 64-bit mode
4184 andl %rN, %rN -> testl %rN, %rN
4185 orl %rN, %rN -> testl %rN, %rN
4187 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4189 else if (i
.reg_operands
== 3
4190 && i
.op
[0].regs
== i
.op
[1].regs
4191 && !i
.types
[2].bitfield
.xmmword
4192 && (i
.tm
.opcode_modifier
.vex
4193 || ((!i
.mask
|| i
.mask
->zeroing
)
4195 && is_evex_encoding (&i
.tm
)
4196 && (i
.vec_encoding
!= vex_encoding_evex
4197 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4198 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4199 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4200 && i
.types
[2].bitfield
.ymmword
))))
4201 && ((i
.tm
.base_opcode
== 0x55
4202 || i
.tm
.base_opcode
== 0x6655
4203 || i
.tm
.base_opcode
== 0x66df
4204 || i
.tm
.base_opcode
== 0x57
4205 || i
.tm
.base_opcode
== 0x6657
4206 || i
.tm
.base_opcode
== 0x66ef
4207 || i
.tm
.base_opcode
== 0x66f8
4208 || i
.tm
.base_opcode
== 0x66f9
4209 || i
.tm
.base_opcode
== 0x66fa
4210 || i
.tm
.base_opcode
== 0x66fb
4211 || i
.tm
.base_opcode
== 0x42
4212 || i
.tm
.base_opcode
== 0x6642
4213 || i
.tm
.base_opcode
== 0x47
4214 || i
.tm
.base_opcode
== 0x6647)
4215 && i
.tm
.extension_opcode
== None
))
4218 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4220 EVEX VOP %zmmM, %zmmM, %zmmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4222 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4223 EVEX VOP %ymmM, %ymmM, %ymmN
4224 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 VEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX VOP %xmmM, %xmmM, %xmmN
4228 VOP, one of vpandn and vpxor:
4229 VEX VOP %ymmM, %ymmM, %ymmN
4230 -> VEX VOP %xmmM, %xmmM, %xmmN
4231 VOP, one of vpandnd and vpandnq:
4232 EVEX VOP %zmmM, %zmmM, %zmmN
4233 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4234 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4235 EVEX VOP %ymmM, %ymmM, %ymmN
4236 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4237 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4238 VOP, one of vpxord and vpxorq:
4239 EVEX VOP %zmmM, %zmmM, %zmmN
4240 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4241 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4242 EVEX VOP %ymmM, %ymmM, %ymmN
4243 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4244 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4245 VOP, one of kxord and kxorq:
4246 VEX VOP %kM, %kM, %kN
4247 -> VEX kxorw %kM, %kM, %kN
4248 VOP, one of kandnd and kandnq:
4249 VEX VOP %kM, %kM, %kN
4250 -> VEX kandnw %kM, %kM, %kN
4252 if (is_evex_encoding (&i
.tm
))
4254 if (i
.vec_encoding
!= vex_encoding_evex
)
4256 i
.tm
.opcode_modifier
.vex
= VEX128
;
4257 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4258 i
.tm
.opcode_modifier
.evex
= 0;
4260 else if (optimize
> 1)
4261 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4265 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4267 i
.tm
.base_opcode
&= 0xff;
4268 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4271 i
.tm
.opcode_modifier
.vex
= VEX128
;
4273 if (i
.tm
.opcode_modifier
.vex
)
4274 for (j
= 0; j
< 3; j
++)
4276 i
.types
[j
].bitfield
.xmmword
= 1;
4277 i
.types
[j
].bitfield
.ymmword
= 0;
4280 else if (i
.vec_encoding
!= vex_encoding_evex
4281 && !i
.types
[0].bitfield
.zmmword
4282 && !i
.types
[1].bitfield
.zmmword
4285 && is_evex_encoding (&i
.tm
)
4286 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4287 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4288 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4289 || (i
.tm
.base_opcode
& ~4) == 0x66db
4290 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4291 && i
.tm
.extension_opcode
== None
)
4294 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4295 vmovdqu32 and vmovdqu64:
4296 EVEX VOP %xmmM, %xmmN
4297 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4298 EVEX VOP %ymmM, %ymmN
4299 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4301 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4303 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4305 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4307 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4308 VOP, one of vpand, vpandn, vpor, vpxor:
4309 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4310 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4311 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4312 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4313 EVEX VOP{d,q} mem, %xmmM, %xmmN
4314 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4315 EVEX VOP{d,q} mem, %ymmM, %ymmN
4316 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4318 for (j
= 0; j
< i
.operands
; j
++)
4319 if (operand_type_check (i
.types
[j
], disp
)
4320 && i
.op
[j
].disps
->X_op
== O_constant
)
4322 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4323 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4324 bytes, we choose EVEX Disp8 over VEX Disp32. */
4325 int evex_disp8
, vex_disp8
;
4326 unsigned int memshift
= i
.memshift
;
4327 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4329 evex_disp8
= fits_in_disp8 (n
);
4331 vex_disp8
= fits_in_disp8 (n
);
4332 if (evex_disp8
!= vex_disp8
)
4334 i
.memshift
= memshift
;
4338 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4341 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4342 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4343 i
.tm
.opcode_modifier
.vex
4344 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4345 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4346 /* VPAND, VPOR, and VPXOR are commutative. */
4347 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4348 i
.tm
.opcode_modifier
.commutative
= 1;
4349 i
.tm
.opcode_modifier
.evex
= 0;
4350 i
.tm
.opcode_modifier
.masking
= 0;
4351 i
.tm
.opcode_modifier
.broadcast
= 0;
4352 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4355 i
.types
[j
].bitfield
.disp8
4356 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4360 /* Return non-zero for load instruction. */
4366 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4367 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4371 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4372 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4373 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4374 if (i
.tm
.opcode_modifier
.anysize
)
4377 /* pop, popf, popa. */
4378 if (strcmp (i
.tm
.name
, "pop") == 0
4379 || i
.tm
.base_opcode
== 0x9d
4380 || i
.tm
.base_opcode
== 0x61)
4383 /* movs, cmps, lods, scas. */
4384 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4388 if (base_opcode
== 0x6f
4389 || i
.tm
.base_opcode
== 0xd7)
4391 /* NB: For AMD-specific insns with implicit memory operands,
4392 they're intentionally not covered. */
4395 /* No memory operand. */
4396 if (!i
.mem_operands
)
4402 if (i
.tm
.base_opcode
== 0xae
4403 && i
.tm
.opcode_modifier
.vex
4404 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4405 && i
.tm
.extension_opcode
== 2)
4410 /* test, not, neg, mul, imul, div, idiv. */
4411 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4412 && i
.tm
.extension_opcode
!= 1)
4416 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4419 /* add, or, adc, sbb, and, sub, xor, cmp. */
4420 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4423 /* bt, bts, btr, btc. */
4424 if (i
.tm
.base_opcode
== 0xfba
4425 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4428 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4429 if ((base_opcode
== 0xc1
4430 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4431 && i
.tm
.extension_opcode
!= 6)
4434 /* cmpxchg8b, cmpxchg16b, xrstors. */
4435 if (i
.tm
.base_opcode
== 0xfc7
4436 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4439 /* fxrstor, ldmxcsr, xrstor. */
4440 if (i
.tm
.base_opcode
== 0xfae
4441 && (i
.tm
.extension_opcode
== 1
4442 || i
.tm
.extension_opcode
== 2
4443 || i
.tm
.extension_opcode
== 5))
4446 /* lgdt, lidt, lmsw. */
4447 if (i
.tm
.base_opcode
== 0xf01
4448 && (i
.tm
.extension_opcode
== 2
4449 || i
.tm
.extension_opcode
== 3
4450 || i
.tm
.extension_opcode
== 6))
4454 if (i
.tm
.base_opcode
== 0xfc7
4455 && i
.tm
.extension_opcode
== 6)
4458 /* Check for x87 instructions. */
4459 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4461 /* Skip fst, fstp, fstenv, fstcw. */
4462 if (i
.tm
.base_opcode
== 0xd9
4463 && (i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 6
4466 || i
.tm
.extension_opcode
== 7))
4469 /* Skip fisttp, fist, fistp, fstp. */
4470 if (i
.tm
.base_opcode
== 0xdb
4471 && (i
.tm
.extension_opcode
== 1
4472 || i
.tm
.extension_opcode
== 2
4473 || i
.tm
.extension_opcode
== 3
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4478 if (i
.tm
.base_opcode
== 0xdd
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4486 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4487 if (i
.tm
.base_opcode
== 0xdf
4488 && (i
.tm
.extension_opcode
== 1
4489 || i
.tm
.extension_opcode
== 2
4490 || i
.tm
.extension_opcode
== 3
4491 || i
.tm
.extension_opcode
== 6
4492 || i
.tm
.extension_opcode
== 7))
4499 dest
= i
.operands
- 1;
4501 /* Check fake imm8 operand and 3 source operands. */
4502 if ((i
.tm
.opcode_modifier
.immext
4503 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4504 && i
.types
[dest
].bitfield
.imm8
)
4507 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4509 && (base_opcode
== 0x1
4510 || base_opcode
== 0x9
4511 || base_opcode
== 0x11
4512 || base_opcode
== 0x19
4513 || base_opcode
== 0x21
4514 || base_opcode
== 0x29
4515 || base_opcode
== 0x31
4516 || base_opcode
== 0x39
4517 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4518 || base_opcode
== 0xfc1))
4521 /* Check for load instruction. */
4522 return (i
.types
[dest
].bitfield
.class != ClassNone
4523 || i
.types
[dest
].bitfield
.instance
== Accum
);
4526 /* Output lfence, 0xfaee8, after instruction. */
4529 insert_lfence_after (void)
4531 if (lfence_after_load
&& load_insn_p ())
4533 /* There are also two REP string instructions that require
4534 special treatment. Specifically, the compare string (CMPS)
4535 and scan string (SCAS) instructions set EFLAGS in a manner
4536 that depends on the data being compared/scanned. When used
4537 with a REP prefix, the number of iterations may therefore
4538 vary depending on this data. If the data is a program secret
4539 chosen by the adversary using an LVI method,
4540 then this data-dependent behavior may leak some aspect
4542 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4543 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4544 && i
.prefix
[REP_PREFIX
])
4546 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4549 char *p
= frag_more (3);
4556 /* Output lfence, 0xfaee8, before instruction. */
4559 insert_lfence_before (void)
4563 if (is_any_vex_encoding (&i
.tm
))
4566 if (i
.tm
.base_opcode
== 0xff
4567 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4569 /* Insert lfence before indirect branch if needed. */
4571 if (lfence_before_indirect_branch
== lfence_branch_none
)
4574 if (i
.operands
!= 1)
4577 if (i
.reg_operands
== 1)
4579 /* Indirect branch via register. Don't insert lfence with
4580 -mlfence-after-load=yes. */
4581 if (lfence_after_load
4582 || lfence_before_indirect_branch
== lfence_branch_memory
)
4585 else if (i
.mem_operands
== 1
4586 && lfence_before_indirect_branch
!= lfence_branch_register
)
4588 as_warn (_("indirect `%s` with memory operand should be avoided"),
4595 if (last_insn
.kind
!= last_insn_other
4596 && last_insn
.seg
== now_seg
)
4598 as_warn_where (last_insn
.file
, last_insn
.line
,
4599 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4600 last_insn
.name
, i
.tm
.name
);
4611 /* Output or/not/shl and lfence before near ret. */
4612 if (lfence_before_ret
!= lfence_before_ret_none
4613 && (i
.tm
.base_opcode
== 0xc2
4614 || i
.tm
.base_opcode
== 0xc3))
4616 if (last_insn
.kind
!= last_insn_other
4617 && last_insn
.seg
== now_seg
)
4619 as_warn_where (last_insn
.file
, last_insn
.line
,
4620 _("`%s` skips -mlfence-before-ret on `%s`"),
4621 last_insn
.name
, i
.tm
.name
);
4625 /* Near ret ingore operand size override under CPU64. */
4626 char prefix
= flag_code
== CODE_64BIT
4628 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4630 if (lfence_before_ret
== lfence_before_ret_not
)
4632 /* not: 0xf71424, may add prefix
4633 for operand size override or 64-bit code. */
4634 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4648 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4651 if (lfence_before_ret
== lfence_before_ret_or
)
4653 /* or: 0x830c2400, may add prefix
4654 for operand size override or 64-bit code. */
4660 /* shl: 0xc1242400, may add prefix
4661 for operand size override or 64-bit code. */
4676 /* This is the guts of the machine-dependent assembler. LINE points to a
4677 machine dependent instruction. This function is supposed to emit
4678 the frags/bytes it assembles to. */
4681 md_assemble (char *line
)
4684 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4685 const insn_template
*t
;
4687 /* Initialize globals. */
4688 memset (&i
, '\0', sizeof (i
));
4689 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4690 i
.reloc
[j
] = NO_RELOC
;
4691 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4692 memset (im_expressions
, '\0', sizeof (im_expressions
));
4693 save_stack_p
= save_stack
;
4695 /* First parse an instruction mnemonic & call i386_operand for the operands.
4696 We assume that the scrubber has arranged it so that line[0] is the valid
4697 start of a (possibly prefixed) mnemonic. */
4699 line
= parse_insn (line
, mnemonic
);
4702 mnem_suffix
= i
.suffix
;
4704 line
= parse_operands (line
, mnemonic
);
4706 xfree (i
.memop1_string
);
4707 i
.memop1_string
= NULL
;
4711 /* Now we've parsed the mnemonic into a set of templates, and have the
4712 operands at hand. */
4714 /* All Intel opcodes have reversed operands except for "bound", "enter",
4715 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4716 intersegment "jmp" and "call" instructions with 2 immediate operands so
4717 that the immediate segment precedes the offset, as it does when in AT&T
4721 && (strcmp (mnemonic
, "bound") != 0)
4722 && (strcmp (mnemonic
, "invlpga") != 0)
4723 && (strncmp (mnemonic
, "monitor", 7) != 0)
4724 && (strncmp (mnemonic
, "mwait", 5) != 0)
4725 && (strcmp (mnemonic
, "tpause") != 0)
4726 && (strcmp (mnemonic
, "umwait") != 0)
4727 && !(operand_type_check (i
.types
[0], imm
)
4728 && operand_type_check (i
.types
[1], imm
)))
4731 /* The order of the immediates should be reversed
4732 for 2 immediates extrq and insertq instructions */
4733 if (i
.imm_operands
== 2
4734 && (strcmp (mnemonic
, "extrq") == 0
4735 || strcmp (mnemonic
, "insertq") == 0))
4736 swap_2_operands (0, 1);
4741 /* Don't optimize displacement for movabs since it only takes 64bit
4744 && i
.disp_encoding
!= disp_encoding_32bit
4745 && (flag_code
!= CODE_64BIT
4746 || strcmp (mnemonic
, "movabs") != 0))
4749 /* Next, we find a template that matches the given insn,
4750 making sure the overlap of the given operands types is consistent
4751 with the template operand types. */
4753 if (!(t
= match_template (mnem_suffix
)))
4756 if (sse_check
!= check_none
4757 && !i
.tm
.opcode_modifier
.noavx
4758 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4759 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4760 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4761 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4762 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4763 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4764 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4765 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4766 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4767 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4768 || i
.tm
.cpu_flags
.bitfield
.cpusha
4769 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4771 (sse_check
== check_warning
4773 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4776 if (i
.tm
.opcode_modifier
.fwait
)
4777 if (!add_prefix (FWAIT_OPCODE
))
4780 /* Check if REP prefix is OK. */
4781 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4783 as_bad (_("invalid instruction `%s' after `%s'"),
4784 i
.tm
.name
, i
.rep_prefix
);
4788 /* Check for lock without a lockable instruction. Destination operand
4789 must be memory unless it is xchg (0x86). */
4790 if (i
.prefix
[LOCK_PREFIX
]
4791 && (!i
.tm
.opcode_modifier
.islockable
4792 || i
.mem_operands
== 0
4793 || (i
.tm
.base_opcode
!= 0x86
4794 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4796 as_bad (_("expecting lockable instruction after `lock'"));
4800 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4801 if (i
.prefix
[DATA_PREFIX
]
4802 && (is_any_vex_encoding (&i
.tm
)
4803 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4804 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4806 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4810 /* Check if HLE prefix is OK. */
4811 if (i
.hle_prefix
&& !check_hle ())
4814 /* Check BND prefix. */
4815 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4816 as_bad (_("expecting valid branch instruction after `bnd'"));
4818 /* Check NOTRACK prefix. */
4819 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4820 as_bad (_("expecting indirect branch instruction after `notrack'"));
4822 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4824 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4825 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4826 else if (flag_code
!= CODE_16BIT
4827 ? i
.prefix
[ADDR_PREFIX
]
4828 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4829 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4832 /* Insert BND prefix. */
4833 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4835 if (!i
.prefix
[BND_PREFIX
])
4836 add_prefix (BND_PREFIX_OPCODE
);
4837 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4839 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4840 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4844 /* Check string instruction segment overrides. */
4845 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4847 gas_assert (i
.mem_operands
);
4848 if (!check_string ())
4850 i
.disp_operands
= 0;
4853 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4854 optimize_encoding ();
4856 if (!process_suffix ())
4859 /* Update operand types and check extended states. */
4860 for (j
= 0; j
< i
.operands
; j
++)
4862 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4863 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4868 i
.xstate
|= xstate_mmx
;
4871 i
.xstate
|= xstate_zmm
;
4874 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4875 i
.xstate
|= xstate_tmm
;
4876 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4877 i
.xstate
|= xstate_zmm
;
4878 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4879 i
.xstate
|= xstate_ymm
;
4880 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4881 i
.xstate
|= xstate_xmm
;
4886 /* Make still unresolved immediate matches conform to size of immediate
4887 given in i.suffix. */
4888 if (!finalize_imm ())
4891 if (i
.types
[0].bitfield
.imm1
)
4892 i
.imm_operands
= 0; /* kludge for shift insns. */
4894 /* We only need to check those implicit registers for instructions
4895 with 3 operands or less. */
4896 if (i
.operands
<= 3)
4897 for (j
= 0; j
< i
.operands
; j
++)
4898 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4899 && !i
.types
[j
].bitfield
.xmmword
)
4902 /* For insns with operands there are more diddles to do to the opcode. */
4905 if (!process_operands ())
4908 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4910 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4911 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4914 if (is_any_vex_encoding (&i
.tm
))
4916 if (!cpu_arch_flags
.bitfield
.cpui286
)
4918 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4923 /* Check for explicit REX prefix. */
4924 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4926 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4930 if (i
.tm
.opcode_modifier
.vex
)
4931 build_vex_prefix (t
);
4933 build_evex_prefix ();
4935 /* The individual REX.RXBW bits got consumed. */
4936 i
.rex
&= REX_OPCODE
;
4939 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4940 instructions may define INT_OPCODE as well, so avoid this corner
4941 case for those instructions that use MODRM. */
4942 if (i
.tm
.base_opcode
== INT_OPCODE
4943 && !i
.tm
.opcode_modifier
.modrm
4944 && i
.op
[0].imms
->X_add_number
== 3)
4946 i
.tm
.base_opcode
= INT3_OPCODE
;
4950 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4951 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4952 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4953 && i
.op
[0].disps
->X_op
== O_constant
)
4955 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4956 the absolute address given by the constant. Since ix86 jumps and
4957 calls are pc relative, we need to generate a reloc. */
4958 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4959 i
.op
[0].disps
->X_op
= O_symbol
;
4962 /* For 8 bit registers we need an empty rex prefix. Also if the
4963 instruction already has a prefix, we need to convert old
4964 registers to new ones. */
4966 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4967 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4968 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4969 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4970 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4971 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4976 i
.rex
|= REX_OPCODE
;
4977 for (x
= 0; x
< 2; x
++)
4979 /* Look for 8 bit operand that uses old registers. */
4980 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4981 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4983 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4984 /* In case it is "hi" register, give up. */
4985 if (i
.op
[x
].regs
->reg_num
> 3)
4986 as_bad (_("can't encode register '%s%s' in an "
4987 "instruction requiring REX prefix."),
4988 register_prefix
, i
.op
[x
].regs
->reg_name
);
4990 /* Otherwise it is equivalent to the extended register.
4991 Since the encoding doesn't change this is merely
4992 cosmetic cleanup for debug output. */
4994 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4999 if (i
.rex
== 0 && i
.rex_encoding
)
5001 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5002 that uses legacy register. If it is "hi" register, don't add
5003 the REX_OPCODE byte. */
5005 for (x
= 0; x
< 2; x
++)
5006 if (i
.types
[x
].bitfield
.class == Reg
5007 && i
.types
[x
].bitfield
.byte
5008 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5009 && i
.op
[x
].regs
->reg_num
> 3)
5011 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5012 i
.rex_encoding
= FALSE
;
5021 add_prefix (REX_OPCODE
| i
.rex
);
5023 insert_lfence_before ();
5025 /* We are ready to output the insn. */
5028 insert_lfence_after ();
5030 last_insn
.seg
= now_seg
;
5032 if (i
.tm
.opcode_modifier
.isprefix
)
5034 last_insn
.kind
= last_insn_prefix
;
5035 last_insn
.name
= i
.tm
.name
;
5036 last_insn
.file
= as_where (&last_insn
.line
);
5039 last_insn
.kind
= last_insn_other
;
5043 parse_insn (char *line
, char *mnemonic
)
5046 char *token_start
= l
;
5049 const insn_template
*t
;
5055 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5060 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5062 as_bad (_("no such instruction: `%s'"), token_start
);
5067 if (!is_space_char (*l
)
5068 && *l
!= END_OF_INSN
5070 || (*l
!= PREFIX_SEPARATOR
5073 as_bad (_("invalid character %s in mnemonic"),
5074 output_invalid (*l
));
5077 if (token_start
== l
)
5079 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5080 as_bad (_("expecting prefix; got nothing"));
5082 as_bad (_("expecting mnemonic; got nothing"));
5086 /* Look up instruction (or prefix) via hash table. */
5087 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5089 if (*l
!= END_OF_INSN
5090 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5091 && current_templates
5092 && current_templates
->start
->opcode_modifier
.isprefix
)
5094 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5096 as_bad ((flag_code
!= CODE_64BIT
5097 ? _("`%s' is only supported in 64-bit mode")
5098 : _("`%s' is not supported in 64-bit mode")),
5099 current_templates
->start
->name
);
5102 /* If we are in 16-bit mode, do not allow addr16 or data16.
5103 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5104 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5105 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5106 && flag_code
!= CODE_64BIT
5107 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5108 ^ (flag_code
== CODE_16BIT
)))
5110 as_bad (_("redundant %s prefix"),
5111 current_templates
->start
->name
);
5114 if (current_templates
->start
->opcode_length
== 0)
5116 /* Handle pseudo prefixes. */
5117 switch (current_templates
->start
->base_opcode
)
5121 i
.disp_encoding
= disp_encoding_8bit
;
5125 i
.disp_encoding
= disp_encoding_16bit
;
5129 i
.disp_encoding
= disp_encoding_32bit
;
5133 i
.dir_encoding
= dir_encoding_load
;
5137 i
.dir_encoding
= dir_encoding_store
;
5141 i
.vec_encoding
= vex_encoding_vex
;
5145 i
.vec_encoding
= vex_encoding_vex3
;
5149 i
.vec_encoding
= vex_encoding_evex
;
5153 i
.rex_encoding
= TRUE
;
5155 case Prefix_NoOptimize
:
5157 i
.no_optimize
= TRUE
;
5165 /* Add prefix, checking for repeated prefixes. */
5166 switch (add_prefix (current_templates
->start
->base_opcode
))
5171 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5172 i
.notrack_prefix
= current_templates
->start
->name
;
5175 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5176 i
.hle_prefix
= current_templates
->start
->name
;
5177 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5178 i
.bnd_prefix
= current_templates
->start
->name
;
5180 i
.rep_prefix
= current_templates
->start
->name
;
5186 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5193 if (!current_templates
)
5195 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5196 Check if we should swap operand or force 32bit displacement in
5198 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5199 i
.dir_encoding
= dir_encoding_swap
;
5200 else if (mnem_p
- 3 == dot_p
5203 i
.disp_encoding
= disp_encoding_8bit
;
5204 else if (mnem_p
- 4 == dot_p
5208 i
.disp_encoding
= disp_encoding_32bit
;
5213 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5216 if (!current_templates
)
5219 if (mnem_p
> mnemonic
)
5221 /* See if we can get a match by trimming off a suffix. */
5224 case WORD_MNEM_SUFFIX
:
5225 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5226 i
.suffix
= SHORT_MNEM_SUFFIX
;
5229 case BYTE_MNEM_SUFFIX
:
5230 case QWORD_MNEM_SUFFIX
:
5231 i
.suffix
= mnem_p
[-1];
5234 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5236 case SHORT_MNEM_SUFFIX
:
5237 case LONG_MNEM_SUFFIX
:
5240 i
.suffix
= mnem_p
[-1];
5243 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5251 if (intel_float_operand (mnemonic
) == 1)
5252 i
.suffix
= SHORT_MNEM_SUFFIX
;
5254 i
.suffix
= LONG_MNEM_SUFFIX
;
5257 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5263 if (!current_templates
)
5265 as_bad (_("no such instruction: `%s'"), token_start
);
5270 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5271 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5273 /* Check for a branch hint. We allow ",pt" and ",pn" for
5274 predict taken and predict not taken respectively.
5275 I'm not sure that branch hints actually do anything on loop
5276 and jcxz insns (JumpByte) for current Pentium4 chips. They
5277 may work in the future and it doesn't hurt to accept them
5279 if (l
[0] == ',' && l
[1] == 'p')
5283 if (!add_prefix (DS_PREFIX_OPCODE
))
5287 else if (l
[2] == 'n')
5289 if (!add_prefix (CS_PREFIX_OPCODE
))
5295 /* Any other comma loses. */
5298 as_bad (_("invalid character %s in mnemonic"),
5299 output_invalid (*l
));
5303 /* Check if instruction is supported on specified architecture. */
5305 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5307 supported
|= cpu_flags_match (t
);
5308 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5310 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5311 as_warn (_("use .code16 to ensure correct addressing mode"));
5317 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5318 as_bad (flag_code
== CODE_64BIT
5319 ? _("`%s' is not supported in 64-bit mode")
5320 : _("`%s' is only supported in 64-bit mode"),
5321 current_templates
->start
->name
);
5323 as_bad (_("`%s' is not supported on `%s%s'"),
5324 current_templates
->start
->name
,
5325 cpu_arch_name
? cpu_arch_name
: default_arch
,
5326 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5332 parse_operands (char *l
, const char *mnemonic
)
5336 /* 1 if operand is pending after ','. */
5337 unsigned int expecting_operand
= 0;
5339 /* Non-zero if operand parens not balanced. */
5340 unsigned int paren_not_balanced
;
5342 while (*l
!= END_OF_INSN
)
5344 /* Skip optional white space before operand. */
5345 if (is_space_char (*l
))
5347 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5349 as_bad (_("invalid character %s before operand %d"),
5350 output_invalid (*l
),
5354 token_start
= l
; /* After white space. */
5355 paren_not_balanced
= 0;
5356 while (paren_not_balanced
|| *l
!= ',')
5358 if (*l
== END_OF_INSN
)
5360 if (paren_not_balanced
)
5363 as_bad (_("unbalanced parenthesis in operand %d."),
5366 as_bad (_("unbalanced brackets in operand %d."),
5371 break; /* we are done */
5373 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5375 as_bad (_("invalid character %s in operand %d"),
5376 output_invalid (*l
),
5383 ++paren_not_balanced
;
5385 --paren_not_balanced
;
5390 ++paren_not_balanced
;
5392 --paren_not_balanced
;
5396 if (l
!= token_start
)
5397 { /* Yes, we've read in another operand. */
5398 unsigned int operand_ok
;
5399 this_operand
= i
.operands
++;
5400 if (i
.operands
> MAX_OPERANDS
)
5402 as_bad (_("spurious operands; (%d operands/instruction max)"),
5406 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5407 /* Now parse operand adding info to 'i' as we go along. */
5408 END_STRING_AND_SAVE (l
);
5410 if (i
.mem_operands
> 1)
5412 as_bad (_("too many memory references for `%s'"),
5419 i386_intel_operand (token_start
,
5420 intel_float_operand (mnemonic
));
5422 operand_ok
= i386_att_operand (token_start
);
5424 RESTORE_END_STRING (l
);
5430 if (expecting_operand
)
5432 expecting_operand_after_comma
:
5433 as_bad (_("expecting operand after ','; got nothing"));
5438 as_bad (_("expecting operand before ','; got nothing"));
5443 /* Now *l must be either ',' or END_OF_INSN. */
5446 if (*++l
== END_OF_INSN
)
5448 /* Just skip it, if it's \n complain. */
5449 goto expecting_operand_after_comma
;
5451 expecting_operand
= 1;
5458 swap_2_operands (int xchg1
, int xchg2
)
5460 union i386_op temp_op
;
5461 i386_operand_type temp_type
;
5462 unsigned int temp_flags
;
5463 enum bfd_reloc_code_real temp_reloc
;
5465 temp_type
= i
.types
[xchg2
];
5466 i
.types
[xchg2
] = i
.types
[xchg1
];
5467 i
.types
[xchg1
] = temp_type
;
5469 temp_flags
= i
.flags
[xchg2
];
5470 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5471 i
.flags
[xchg1
] = temp_flags
;
5473 temp_op
= i
.op
[xchg2
];
5474 i
.op
[xchg2
] = i
.op
[xchg1
];
5475 i
.op
[xchg1
] = temp_op
;
5477 temp_reloc
= i
.reloc
[xchg2
];
5478 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5479 i
.reloc
[xchg1
] = temp_reloc
;
5483 if (i
.mask
->operand
== xchg1
)
5484 i
.mask
->operand
= xchg2
;
5485 else if (i
.mask
->operand
== xchg2
)
5486 i
.mask
->operand
= xchg1
;
5490 if (i
.broadcast
->operand
== xchg1
)
5491 i
.broadcast
->operand
= xchg2
;
5492 else if (i
.broadcast
->operand
== xchg2
)
5493 i
.broadcast
->operand
= xchg1
;
5497 if (i
.rounding
->operand
== xchg1
)
5498 i
.rounding
->operand
= xchg2
;
5499 else if (i
.rounding
->operand
== xchg2
)
5500 i
.rounding
->operand
= xchg1
;
5505 swap_operands (void)
5511 swap_2_operands (1, i
.operands
- 2);
5515 swap_2_operands (0, i
.operands
- 1);
5521 if (i
.mem_operands
== 2)
5523 const seg_entry
*temp_seg
;
5524 temp_seg
= i
.seg
[0];
5525 i
.seg
[0] = i
.seg
[1];
5526 i
.seg
[1] = temp_seg
;
5530 /* Try to ensure constant immediates are represented in the smallest
5535 char guess_suffix
= 0;
5539 guess_suffix
= i
.suffix
;
5540 else if (i
.reg_operands
)
5542 /* Figure out a suffix from the last register operand specified.
5543 We can't do this properly yet, i.e. excluding special register
5544 instances, but the following works for instructions with
5545 immediates. In any case, we can't set i.suffix yet. */
5546 for (op
= i
.operands
; --op
>= 0;)
5547 if (i
.types
[op
].bitfield
.class != Reg
)
5549 else if (i
.types
[op
].bitfield
.byte
)
5551 guess_suffix
= BYTE_MNEM_SUFFIX
;
5554 else if (i
.types
[op
].bitfield
.word
)
5556 guess_suffix
= WORD_MNEM_SUFFIX
;
5559 else if (i
.types
[op
].bitfield
.dword
)
5561 guess_suffix
= LONG_MNEM_SUFFIX
;
5564 else if (i
.types
[op
].bitfield
.qword
)
5566 guess_suffix
= QWORD_MNEM_SUFFIX
;
5570 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5571 guess_suffix
= WORD_MNEM_SUFFIX
;
5573 for (op
= i
.operands
; --op
>= 0;)
5574 if (operand_type_check (i
.types
[op
], imm
))
5576 switch (i
.op
[op
].imms
->X_op
)
5579 /* If a suffix is given, this operand may be shortened. */
5580 switch (guess_suffix
)
5582 case LONG_MNEM_SUFFIX
:
5583 i
.types
[op
].bitfield
.imm32
= 1;
5584 i
.types
[op
].bitfield
.imm64
= 1;
5586 case WORD_MNEM_SUFFIX
:
5587 i
.types
[op
].bitfield
.imm16
= 1;
5588 i
.types
[op
].bitfield
.imm32
= 1;
5589 i
.types
[op
].bitfield
.imm32s
= 1;
5590 i
.types
[op
].bitfield
.imm64
= 1;
5592 case BYTE_MNEM_SUFFIX
:
5593 i
.types
[op
].bitfield
.imm8
= 1;
5594 i
.types
[op
].bitfield
.imm8s
= 1;
5595 i
.types
[op
].bitfield
.imm16
= 1;
5596 i
.types
[op
].bitfield
.imm32
= 1;
5597 i
.types
[op
].bitfield
.imm32s
= 1;
5598 i
.types
[op
].bitfield
.imm64
= 1;
5602 /* If this operand is at most 16 bits, convert it
5603 to a signed 16 bit number before trying to see
5604 whether it will fit in an even smaller size.
5605 This allows a 16-bit operand such as $0xffe0 to
5606 be recognised as within Imm8S range. */
5607 if ((i
.types
[op
].bitfield
.imm16
)
5608 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5610 i
.op
[op
].imms
->X_add_number
=
5611 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5614 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5615 if ((i
.types
[op
].bitfield
.imm32
)
5616 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5619 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5620 ^ ((offsetT
) 1 << 31))
5621 - ((offsetT
) 1 << 31));
5625 = operand_type_or (i
.types
[op
],
5626 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5628 /* We must avoid matching of Imm32 templates when 64bit
5629 only immediate is available. */
5630 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5631 i
.types
[op
].bitfield
.imm32
= 0;
5638 /* Symbols and expressions. */
5640 /* Convert symbolic operand to proper sizes for matching, but don't
5641 prevent matching a set of insns that only supports sizes other
5642 than those matching the insn suffix. */
5644 i386_operand_type mask
, allowed
;
5645 const insn_template
*t
;
5647 operand_type_set (&mask
, 0);
5648 operand_type_set (&allowed
, 0);
5650 for (t
= current_templates
->start
;
5651 t
< current_templates
->end
;
5654 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5655 allowed
= operand_type_and (allowed
, anyimm
);
5657 switch (guess_suffix
)
5659 case QWORD_MNEM_SUFFIX
:
5660 mask
.bitfield
.imm64
= 1;
5661 mask
.bitfield
.imm32s
= 1;
5663 case LONG_MNEM_SUFFIX
:
5664 mask
.bitfield
.imm32
= 1;
5666 case WORD_MNEM_SUFFIX
:
5667 mask
.bitfield
.imm16
= 1;
5669 case BYTE_MNEM_SUFFIX
:
5670 mask
.bitfield
.imm8
= 1;
5675 allowed
= operand_type_and (mask
, allowed
);
5676 if (!operand_type_all_zero (&allowed
))
5677 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5684 /* Try to use the smallest displacement type too. */
5686 optimize_disp (void)
5690 for (op
= i
.operands
; --op
>= 0;)
5691 if (operand_type_check (i
.types
[op
], disp
))
5693 if (i
.op
[op
].disps
->X_op
== O_constant
)
5695 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5697 if (i
.types
[op
].bitfield
.disp16
5698 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5700 /* If this operand is at most 16 bits, convert
5701 to a signed 16 bit number and don't use 64bit
5703 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5704 i
.types
[op
].bitfield
.disp64
= 0;
5707 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5708 if (i
.types
[op
].bitfield
.disp32
5709 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5711 /* If this operand is at most 32 bits, convert
5712 to a signed 32 bit number and don't use 64bit
5714 op_disp
&= (((offsetT
) 2 << 31) - 1);
5715 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5716 i
.types
[op
].bitfield
.disp64
= 0;
5719 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5721 i
.types
[op
].bitfield
.disp8
= 0;
5722 i
.types
[op
].bitfield
.disp16
= 0;
5723 i
.types
[op
].bitfield
.disp32
= 0;
5724 i
.types
[op
].bitfield
.disp32s
= 0;
5725 i
.types
[op
].bitfield
.disp64
= 0;
5729 else if (flag_code
== CODE_64BIT
)
5731 if (fits_in_signed_long (op_disp
))
5733 i
.types
[op
].bitfield
.disp64
= 0;
5734 i
.types
[op
].bitfield
.disp32s
= 1;
5736 if (i
.prefix
[ADDR_PREFIX
]
5737 && fits_in_unsigned_long (op_disp
))
5738 i
.types
[op
].bitfield
.disp32
= 1;
5740 if ((i
.types
[op
].bitfield
.disp32
5741 || i
.types
[op
].bitfield
.disp32s
5742 || i
.types
[op
].bitfield
.disp16
)
5743 && fits_in_disp8 (op_disp
))
5744 i
.types
[op
].bitfield
.disp8
= 1;
5746 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5747 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5749 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5750 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5751 i
.types
[op
].bitfield
.disp8
= 0;
5752 i
.types
[op
].bitfield
.disp16
= 0;
5753 i
.types
[op
].bitfield
.disp32
= 0;
5754 i
.types
[op
].bitfield
.disp32s
= 0;
5755 i
.types
[op
].bitfield
.disp64
= 0;
5758 /* We only support 64bit displacement on constants. */
5759 i
.types
[op
].bitfield
.disp64
= 0;
5763 /* Return 1 if there is a match in broadcast bytes between operand
5764 GIVEN and instruction template T. */
5767 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5769 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5770 && i
.types
[given
].bitfield
.byte
)
5771 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5772 && i
.types
[given
].bitfield
.word
)
5773 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5774 && i
.types
[given
].bitfield
.dword
)
5775 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5776 && i
.types
[given
].bitfield
.qword
));
5779 /* Check if operands are valid for the instruction. */
5782 check_VecOperands (const insn_template
*t
)
5787 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5788 any one operand are implicity requiring AVX512VL support if the actual
5789 operand size is YMMword or XMMword. Since this function runs after
5790 template matching, there's no need to check for YMMword/XMMword in
5792 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5793 if (!cpu_flags_all_zero (&cpu
)
5794 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5795 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5797 for (op
= 0; op
< t
->operands
; ++op
)
5799 if (t
->operand_types
[op
].bitfield
.zmmword
5800 && (i
.types
[op
].bitfield
.ymmword
5801 || i
.types
[op
].bitfield
.xmmword
))
5803 i
.error
= unsupported
;
5809 /* Without VSIB byte, we can't have a vector register for index. */
5810 if (!t
->opcode_modifier
.sib
5812 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5813 || i
.index_reg
->reg_type
.bitfield
.ymmword
5814 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5816 i
.error
= unsupported_vector_index_register
;
5820 /* Check if default mask is allowed. */
5821 if (t
->opcode_modifier
.nodefmask
5822 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5824 i
.error
= no_default_mask
;
5828 /* For VSIB byte, we need a vector register for index, and all vector
5829 registers must be distinct. */
5830 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5833 || !((t
->opcode_modifier
.sib
== VECSIB128
5834 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5835 || (t
->opcode_modifier
.sib
== VECSIB256
5836 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5837 || (t
->opcode_modifier
.sib
== VECSIB512
5838 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5840 i
.error
= invalid_vsib_address
;
5844 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5845 if (i
.reg_operands
== 2 && !i
.mask
)
5847 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5848 gas_assert (i
.types
[0].bitfield
.xmmword
5849 || i
.types
[0].bitfield
.ymmword
);
5850 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5851 gas_assert (i
.types
[2].bitfield
.xmmword
5852 || i
.types
[2].bitfield
.ymmword
);
5853 if (operand_check
== check_none
)
5855 if (register_number (i
.op
[0].regs
)
5856 != register_number (i
.index_reg
)
5857 && register_number (i
.op
[2].regs
)
5858 != register_number (i
.index_reg
)
5859 && register_number (i
.op
[0].regs
)
5860 != register_number (i
.op
[2].regs
))
5862 if (operand_check
== check_error
)
5864 i
.error
= invalid_vector_register_set
;
5867 as_warn (_("mask, index, and destination registers should be distinct"));
5869 else if (i
.reg_operands
== 1 && i
.mask
)
5871 if (i
.types
[1].bitfield
.class == RegSIMD
5872 && (i
.types
[1].bitfield
.xmmword
5873 || i
.types
[1].bitfield
.ymmword
5874 || i
.types
[1].bitfield
.zmmword
)
5875 && (register_number (i
.op
[1].regs
)
5876 == register_number (i
.index_reg
)))
5878 if (operand_check
== check_error
)
5880 i
.error
= invalid_vector_register_set
;
5883 if (operand_check
!= check_none
)
5884 as_warn (_("index and destination registers should be distinct"));
5889 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5891 if (t
->operand_types
[0].bitfield
.tmmword
5892 && i
.reg_operands
== 3)
5894 if (register_number (i
.op
[0].regs
)
5895 == register_number (i
.op
[1].regs
)
5896 || register_number (i
.op
[0].regs
)
5897 == register_number (i
.op
[2].regs
)
5898 || register_number (i
.op
[1].regs
)
5899 == register_number (i
.op
[2].regs
))
5901 i
.error
= invalid_tmm_register_set
;
5906 /* Check if broadcast is supported by the instruction and is applied
5907 to the memory operand. */
5910 i386_operand_type type
, overlap
;
5912 /* Check if specified broadcast is supported in this instruction,
5913 and its broadcast bytes match the memory operand. */
5914 op
= i
.broadcast
->operand
;
5915 if (!t
->opcode_modifier
.broadcast
5916 || !(i
.flags
[op
] & Operand_Mem
)
5917 || (!i
.types
[op
].bitfield
.unspecified
5918 && !match_broadcast_size (t
, op
)))
5921 i
.error
= unsupported_broadcast
;
5925 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5926 * i
.broadcast
->type
);
5927 operand_type_set (&type
, 0);
5928 switch (i
.broadcast
->bytes
)
5931 type
.bitfield
.word
= 1;
5934 type
.bitfield
.dword
= 1;
5937 type
.bitfield
.qword
= 1;
5940 type
.bitfield
.xmmword
= 1;
5943 type
.bitfield
.ymmword
= 1;
5946 type
.bitfield
.zmmword
= 1;
5952 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5953 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5954 && t
->operand_types
[op
].bitfield
.byte
5955 + t
->operand_types
[op
].bitfield
.word
5956 + t
->operand_types
[op
].bitfield
.dword
5957 + t
->operand_types
[op
].bitfield
.qword
> 1)
5959 overlap
.bitfield
.xmmword
= 0;
5960 overlap
.bitfield
.ymmword
= 0;
5961 overlap
.bitfield
.zmmword
= 0;
5963 if (operand_type_all_zero (&overlap
))
5966 if (t
->opcode_modifier
.checkregsize
)
5970 type
.bitfield
.baseindex
= 1;
5971 for (j
= 0; j
< i
.operands
; ++j
)
5974 && !operand_type_register_match(i
.types
[j
],
5975 t
->operand_types
[j
],
5977 t
->operand_types
[op
]))
5982 /* If broadcast is supported in this instruction, we need to check if
5983 operand of one-element size isn't specified without broadcast. */
5984 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5986 /* Find memory operand. */
5987 for (op
= 0; op
< i
.operands
; op
++)
5988 if (i
.flags
[op
] & Operand_Mem
)
5990 gas_assert (op
< i
.operands
);
5991 /* Check size of the memory operand. */
5992 if (match_broadcast_size (t
, op
))
5994 i
.error
= broadcast_needed
;
5999 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6001 /* Check if requested masking is supported. */
6004 switch (t
->opcode_modifier
.masking
)
6008 case MERGING_MASKING
:
6009 if (i
.mask
->zeroing
)
6012 i
.error
= unsupported_masking
;
6016 case DYNAMIC_MASKING
:
6017 /* Memory destinations allow only merging masking. */
6018 if (i
.mask
->zeroing
&& i
.mem_operands
)
6020 /* Find memory operand. */
6021 for (op
= 0; op
< i
.operands
; op
++)
6022 if (i
.flags
[op
] & Operand_Mem
)
6024 gas_assert (op
< i
.operands
);
6025 if (op
== i
.operands
- 1)
6027 i
.error
= unsupported_masking
;
6037 /* Check if masking is applied to dest operand. */
6038 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6040 i
.error
= mask_not_on_destination
;
6047 if (!t
->opcode_modifier
.sae
6048 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6050 i
.error
= unsupported_rc_sae
;
6053 /* If the instruction has several immediate operands and one of
6054 them is rounding, the rounding operand should be the last
6055 immediate operand. */
6056 if (i
.imm_operands
> 1
6057 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6059 i
.error
= rc_sae_operand_not_last_imm
;
6064 /* Check the special Imm4 cases; must be the first operand. */
6065 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6067 if (i
.op
[0].imms
->X_op
!= O_constant
6068 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6074 /* Turn off Imm<N> so that update_imm won't complain. */
6075 operand_type_set (&i
.types
[0], 0);
6078 /* Check vector Disp8 operand. */
6079 if (t
->opcode_modifier
.disp8memshift
6080 && i
.disp_encoding
!= disp_encoding_32bit
)
6083 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6084 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6085 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6088 const i386_operand_type
*type
= NULL
;
6091 for (op
= 0; op
< i
.operands
; op
++)
6092 if (i
.flags
[op
] & Operand_Mem
)
6094 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6095 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6096 else if (t
->operand_types
[op
].bitfield
.xmmword
6097 + t
->operand_types
[op
].bitfield
.ymmword
6098 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6099 type
= &t
->operand_types
[op
];
6100 else if (!i
.types
[op
].bitfield
.unspecified
)
6101 type
= &i
.types
[op
];
6103 else if (i
.types
[op
].bitfield
.class == RegSIMD
6104 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6106 if (i
.types
[op
].bitfield
.zmmword
)
6108 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6110 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6116 if (type
->bitfield
.zmmword
)
6118 else if (type
->bitfield
.ymmword
)
6120 else if (type
->bitfield
.xmmword
)
6124 /* For the check in fits_in_disp8(). */
6125 if (i
.memshift
== 0)
6129 for (op
= 0; op
< i
.operands
; op
++)
6130 if (operand_type_check (i
.types
[op
], disp
)
6131 && i
.op
[op
].disps
->X_op
== O_constant
)
6133 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6135 i
.types
[op
].bitfield
.disp8
= 1;
6138 i
.types
[op
].bitfield
.disp8
= 0;
6147 /* Check if encoding requirements are met by the instruction. */
6150 VEX_check_encoding (const insn_template
*t
)
6152 if (i
.vec_encoding
== vex_encoding_error
)
6154 i
.error
= unsupported
;
6158 if (i
.vec_encoding
== vex_encoding_evex
)
6160 /* This instruction must be encoded with EVEX prefix. */
6161 if (!is_evex_encoding (t
))
6163 i
.error
= unsupported
;
6169 if (!t
->opcode_modifier
.vex
)
6171 /* This instruction template doesn't have VEX prefix. */
6172 if (i
.vec_encoding
!= vex_encoding_default
)
6174 i
.error
= unsupported
;
6183 static const insn_template
*
6184 match_template (char mnem_suffix
)
6186 /* Points to template once we've found it. */
6187 const insn_template
*t
;
6188 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6189 i386_operand_type overlap4
;
6190 unsigned int found_reverse_match
;
6191 i386_opcode_modifier suffix_check
;
6192 i386_operand_type operand_types
[MAX_OPERANDS
];
6193 int addr_prefix_disp
;
6194 unsigned int j
, size_match
, check_register
;
6195 enum i386_error specific_error
= 0;
6197 #if MAX_OPERANDS != 5
6198 # error "MAX_OPERANDS must be 5."
6201 found_reverse_match
= 0;
6202 addr_prefix_disp
= -1;
6204 /* Prepare for mnemonic suffix check. */
6205 memset (&suffix_check
, 0, sizeof (suffix_check
));
6206 switch (mnem_suffix
)
6208 case BYTE_MNEM_SUFFIX
:
6209 suffix_check
.no_bsuf
= 1;
6211 case WORD_MNEM_SUFFIX
:
6212 suffix_check
.no_wsuf
= 1;
6214 case SHORT_MNEM_SUFFIX
:
6215 suffix_check
.no_ssuf
= 1;
6217 case LONG_MNEM_SUFFIX
:
6218 suffix_check
.no_lsuf
= 1;
6220 case QWORD_MNEM_SUFFIX
:
6221 suffix_check
.no_qsuf
= 1;
6224 /* NB: In Intel syntax, normally we can check for memory operand
6225 size when there is no mnemonic suffix. But jmp and call have
6226 2 different encodings with Dword memory operand size, one with
6227 No_ldSuf and the other without. i.suffix is set to
6228 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6229 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6230 suffix_check
.no_ldsuf
= 1;
6233 /* Must have right number of operands. */
6234 i
.error
= number_of_operands_mismatch
;
6236 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6238 addr_prefix_disp
= -1;
6239 found_reverse_match
= 0;
6241 if (i
.operands
!= t
->operands
)
6244 /* Check processor support. */
6245 i
.error
= unsupported
;
6246 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6249 /* Check AT&T mnemonic. */
6250 i
.error
= unsupported_with_intel_mnemonic
;
6251 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6254 /* Check AT&T/Intel syntax. */
6255 i
.error
= unsupported_syntax
;
6256 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6257 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6260 /* Check Intel64/AMD64 ISA. */
6264 /* Default: Don't accept Intel64. */
6265 if (t
->opcode_modifier
.isa64
== INTEL64
)
6269 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6270 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6274 /* -mintel64: Don't accept AMD64. */
6275 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6280 /* Check the suffix. */
6281 i
.error
= invalid_instruction_suffix
;
6282 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6283 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6284 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6285 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6286 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6287 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6290 size_match
= operand_size_match (t
);
6294 /* This is intentionally not
6296 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6298 as the case of a missing * on the operand is accepted (perhaps with
6299 a warning, issued further down). */
6300 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6302 i
.error
= operand_type_mismatch
;
6306 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6307 operand_types
[j
] = t
->operand_types
[j
];
6309 /* In general, don't allow
6310 - 64-bit operands outside of 64-bit mode,
6311 - 32-bit operands on pre-386. */
6312 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6313 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6314 && flag_code
!= CODE_64BIT
6315 && (t
->base_opcode
!= 0x0fc7
6316 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6317 || (i
.suffix
== LONG_MNEM_SUFFIX
6318 && !cpu_arch_flags
.bitfield
.cpui386
))
6320 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6321 && !intel_float_operand (t
->name
))
6322 : intel_float_operand (t
->name
) != 2)
6323 && (t
->operands
== i
.imm_operands
6324 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6325 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6326 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6327 || (operand_types
[j
].bitfield
.class != RegMMX
6328 && operand_types
[j
].bitfield
.class != RegSIMD
6329 && operand_types
[j
].bitfield
.class != RegMask
))
6330 && !t
->opcode_modifier
.sib
)
6333 /* Do not verify operands when there are none. */
6336 if (VEX_check_encoding (t
))
6338 specific_error
= i
.error
;
6342 /* We've found a match; break out of loop. */
6346 if (!t
->opcode_modifier
.jump
6347 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6349 /* There should be only one Disp operand. */
6350 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6351 if (operand_type_check (operand_types
[j
], disp
))
6353 if (j
< MAX_OPERANDS
)
6355 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6357 addr_prefix_disp
= j
;
6359 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6360 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6364 override
= !override
;
6367 if (operand_types
[j
].bitfield
.disp32
6368 && operand_types
[j
].bitfield
.disp16
)
6370 operand_types
[j
].bitfield
.disp16
= override
;
6371 operand_types
[j
].bitfield
.disp32
= !override
;
6373 operand_types
[j
].bitfield
.disp32s
= 0;
6374 operand_types
[j
].bitfield
.disp64
= 0;
6378 if (operand_types
[j
].bitfield
.disp32s
6379 || operand_types
[j
].bitfield
.disp64
)
6381 operand_types
[j
].bitfield
.disp64
&= !override
;
6382 operand_types
[j
].bitfield
.disp32s
&= !override
;
6383 operand_types
[j
].bitfield
.disp32
= override
;
6385 operand_types
[j
].bitfield
.disp16
= 0;
6391 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6392 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6395 /* We check register size if needed. */
6396 if (t
->opcode_modifier
.checkregsize
)
6398 check_register
= (1 << t
->operands
) - 1;
6400 check_register
&= ~(1 << i
.broadcast
->operand
);
6405 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6406 switch (t
->operands
)
6409 if (!operand_type_match (overlap0
, i
.types
[0]))
6413 /* xchg %eax, %eax is a special case. It is an alias for nop
6414 only in 32bit mode and we can use opcode 0x90. In 64bit
6415 mode, we can't use 0x90 for xchg %eax, %eax since it should
6416 zero-extend %eax to %rax. */
6417 if (flag_code
== CODE_64BIT
6418 && t
->base_opcode
== 0x90
6419 && i
.types
[0].bitfield
.instance
== Accum
6420 && i
.types
[0].bitfield
.dword
6421 && i
.types
[1].bitfield
.instance
== Accum
6422 && i
.types
[1].bitfield
.dword
)
6424 /* xrelease mov %eax, <disp> is another special case. It must not
6425 match the accumulator-only encoding of mov. */
6426 if (flag_code
!= CODE_64BIT
6428 && t
->base_opcode
== 0xa0
6429 && i
.types
[0].bitfield
.instance
== Accum
6430 && (i
.flags
[1] & Operand_Mem
))
6435 if (!(size_match
& MATCH_STRAIGHT
))
6437 /* Reverse direction of operands if swapping is possible in the first
6438 place (operands need to be symmetric) and
6439 - the load form is requested, and the template is a store form,
6440 - the store form is requested, and the template is a load form,
6441 - the non-default (swapped) form is requested. */
6442 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6443 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6444 && !operand_type_all_zero (&overlap1
))
6445 switch (i
.dir_encoding
)
6447 case dir_encoding_load
:
6448 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6449 || t
->opcode_modifier
.regmem
)
6453 case dir_encoding_store
:
6454 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6455 && !t
->opcode_modifier
.regmem
)
6459 case dir_encoding_swap
:
6462 case dir_encoding_default
:
6465 /* If we want store form, we skip the current load. */
6466 if ((i
.dir_encoding
== dir_encoding_store
6467 || i
.dir_encoding
== dir_encoding_swap
)
6468 && i
.mem_operands
== 0
6469 && t
->opcode_modifier
.load
)
6474 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6475 if (!operand_type_match (overlap0
, i
.types
[0])
6476 || !operand_type_match (overlap1
, i
.types
[1])
6477 || ((check_register
& 3) == 3
6478 && !operand_type_register_match (i
.types
[0],
6483 /* Check if other direction is valid ... */
6484 if (!t
->opcode_modifier
.d
)
6488 if (!(size_match
& MATCH_REVERSE
))
6490 /* Try reversing direction of operands. */
6491 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6492 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6493 if (!operand_type_match (overlap0
, i
.types
[0])
6494 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6496 && !operand_type_register_match (i
.types
[0],
6497 operand_types
[i
.operands
- 1],
6498 i
.types
[i
.operands
- 1],
6501 /* Does not match either direction. */
6504 /* found_reverse_match holds which of D or FloatR
6506 if (!t
->opcode_modifier
.d
)
6507 found_reverse_match
= 0;
6508 else if (operand_types
[0].bitfield
.tbyte
)
6509 found_reverse_match
= Opcode_FloatD
;
6510 else if (operand_types
[0].bitfield
.xmmword
6511 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6512 || operand_types
[0].bitfield
.class == RegMMX
6513 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6514 || is_any_vex_encoding(t
))
6515 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6516 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6518 found_reverse_match
= Opcode_D
;
6519 if (t
->opcode_modifier
.floatr
)
6520 found_reverse_match
|= Opcode_FloatR
;
6524 /* Found a forward 2 operand match here. */
6525 switch (t
->operands
)
6528 overlap4
= operand_type_and (i
.types
[4],
6532 overlap3
= operand_type_and (i
.types
[3],
6536 overlap2
= operand_type_and (i
.types
[2],
6541 switch (t
->operands
)
6544 if (!operand_type_match (overlap4
, i
.types
[4])
6545 || !operand_type_register_match (i
.types
[3],
6552 if (!operand_type_match (overlap3
, i
.types
[3])
6553 || ((check_register
& 0xa) == 0xa
6554 && !operand_type_register_match (i
.types
[1],
6558 || ((check_register
& 0xc) == 0xc
6559 && !operand_type_register_match (i
.types
[2],
6566 /* Here we make use of the fact that there are no
6567 reverse match 3 operand instructions. */
6568 if (!operand_type_match (overlap2
, i
.types
[2])
6569 || ((check_register
& 5) == 5
6570 && !operand_type_register_match (i
.types
[0],
6574 || ((check_register
& 6) == 6
6575 && !operand_type_register_match (i
.types
[1],
6583 /* Found either forward/reverse 2, 3 or 4 operand match here:
6584 slip through to break. */
6587 /* Check if vector operands are valid. */
6588 if (check_VecOperands (t
))
6590 specific_error
= i
.error
;
6594 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6595 if (VEX_check_encoding (t
))
6597 specific_error
= i
.error
;
6601 /* We've found a match; break out of loop. */
6605 if (t
== current_templates
->end
)
6607 /* We found no match. */
6608 const char *err_msg
;
6609 switch (specific_error
? specific_error
: i
.error
)
6613 case operand_size_mismatch
:
6614 err_msg
= _("operand size mismatch");
6616 case operand_type_mismatch
:
6617 err_msg
= _("operand type mismatch");
6619 case register_type_mismatch
:
6620 err_msg
= _("register type mismatch");
6622 case number_of_operands_mismatch
:
6623 err_msg
= _("number of operands mismatch");
6625 case invalid_instruction_suffix
:
6626 err_msg
= _("invalid instruction suffix");
6629 err_msg
= _("constant doesn't fit in 4 bits");
6631 case unsupported_with_intel_mnemonic
:
6632 err_msg
= _("unsupported with Intel mnemonic");
6634 case unsupported_syntax
:
6635 err_msg
= _("unsupported syntax");
6638 as_bad (_("unsupported instruction `%s'"),
6639 current_templates
->start
->name
);
6641 case invalid_sib_address
:
6642 err_msg
= _("invalid SIB address");
6644 case invalid_vsib_address
:
6645 err_msg
= _("invalid VSIB address");
6647 case invalid_vector_register_set
:
6648 err_msg
= _("mask, index, and destination registers must be distinct");
6650 case invalid_tmm_register_set
:
6651 err_msg
= _("all tmm registers must be distinct");
6653 case unsupported_vector_index_register
:
6654 err_msg
= _("unsupported vector index register");
6656 case unsupported_broadcast
:
6657 err_msg
= _("unsupported broadcast");
6659 case broadcast_needed
:
6660 err_msg
= _("broadcast is needed for operand of such type");
6662 case unsupported_masking
:
6663 err_msg
= _("unsupported masking");
6665 case mask_not_on_destination
:
6666 err_msg
= _("mask not on destination operand");
6668 case no_default_mask
:
6669 err_msg
= _("default mask isn't allowed");
6671 case unsupported_rc_sae
:
6672 err_msg
= _("unsupported static rounding/sae");
6674 case rc_sae_operand_not_last_imm
:
6676 err_msg
= _("RC/SAE operand must precede immediate operands");
6678 err_msg
= _("RC/SAE operand must follow immediate operands");
6680 case invalid_register_operand
:
6681 err_msg
= _("invalid register operand");
6684 as_bad (_("%s for `%s'"), err_msg
,
6685 current_templates
->start
->name
);
6689 if (!quiet_warnings
)
6692 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6693 as_warn (_("indirect %s without `*'"), t
->name
);
6695 if (t
->opcode_modifier
.isprefix
6696 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6698 /* Warn them that a data or address size prefix doesn't
6699 affect assembly of the next line of code. */
6700 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6704 /* Copy the template we found. */
6707 if (addr_prefix_disp
!= -1)
6708 i
.tm
.operand_types
[addr_prefix_disp
]
6709 = operand_types
[addr_prefix_disp
];
6711 if (found_reverse_match
)
6713 /* If we found a reverse match we must alter the opcode direction
6714 bit and clear/flip the regmem modifier one. found_reverse_match
6715 holds bits to change (different for int & float insns). */
6717 i
.tm
.base_opcode
^= found_reverse_match
;
6719 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6720 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6722 /* Certain SIMD insns have their load forms specified in the opcode
6723 table, and hence we need to _set_ RegMem instead of clearing it.
6724 We need to avoid setting the bit though on insns like KMOVW. */
6725 i
.tm
.opcode_modifier
.regmem
6726 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6727 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6728 && !i
.tm
.opcode_modifier
.regmem
;
6737 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6738 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6740 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6742 as_bad (_("`%s' operand %u must use `%ses' segment"),
6744 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6749 /* There's only ever one segment override allowed per instruction.
6750 This instruction possibly has a legal segment override on the
6751 second operand, so copy the segment to where non-string
6752 instructions store it, allowing common code. */
6753 i
.seg
[op
] = i
.seg
[1];
6759 process_suffix (void)
6761 /* If matched instruction specifies an explicit instruction mnemonic
6763 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6764 i
.suffix
= WORD_MNEM_SUFFIX
;
6765 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6766 i
.suffix
= LONG_MNEM_SUFFIX
;
6767 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6768 i
.suffix
= QWORD_MNEM_SUFFIX
;
6769 else if (i
.reg_operands
6770 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6771 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6773 unsigned int numop
= i
.operands
;
6775 /* movsx/movzx want only their source operand considered here, for the
6776 ambiguity checking below. The suffix will be replaced afterwards
6777 to represent the destination (register). */
6778 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6779 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6782 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6783 if (i
.tm
.base_opcode
== 0xf20f38f0
6784 && i
.tm
.operand_types
[1].bitfield
.qword
)
6787 /* If there's no instruction mnemonic suffix we try to invent one
6788 based on GPR operands. */
6791 /* We take i.suffix from the last register operand specified,
6792 Destination register type is more significant than source
6793 register type. crc32 in SSE4.2 prefers source register
6795 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6798 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6799 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6801 if (i
.types
[op
].bitfield
.class != Reg
)
6803 if (i
.types
[op
].bitfield
.byte
)
6804 i
.suffix
= BYTE_MNEM_SUFFIX
;
6805 else if (i
.types
[op
].bitfield
.word
)
6806 i
.suffix
= WORD_MNEM_SUFFIX
;
6807 else if (i
.types
[op
].bitfield
.dword
)
6808 i
.suffix
= LONG_MNEM_SUFFIX
;
6809 else if (i
.types
[op
].bitfield
.qword
)
6810 i
.suffix
= QWORD_MNEM_SUFFIX
;
6816 /* As an exception, movsx/movzx silently default to a byte source
6818 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6819 && !i
.suffix
&& !intel_syntax
)
6820 i
.suffix
= BYTE_MNEM_SUFFIX
;
6822 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6825 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6826 && i
.tm
.opcode_modifier
.no_bsuf
)
6828 else if (!check_byte_reg ())
6831 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6834 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6835 && i
.tm
.opcode_modifier
.no_lsuf
6836 && !i
.tm
.opcode_modifier
.todword
6837 && !i
.tm
.opcode_modifier
.toqword
)
6839 else if (!check_long_reg ())
6842 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6845 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6846 && i
.tm
.opcode_modifier
.no_qsuf
6847 && !i
.tm
.opcode_modifier
.todword
6848 && !i
.tm
.opcode_modifier
.toqword
)
6850 else if (!check_qword_reg ())
6853 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6856 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6857 && i
.tm
.opcode_modifier
.no_wsuf
)
6859 else if (!check_word_reg ())
6862 else if (intel_syntax
6863 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6864 /* Do nothing if the instruction is going to ignore the prefix. */
6869 /* Undo the movsx/movzx change done above. */
6872 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6875 i
.suffix
= stackop_size
;
6876 if (stackop_size
== LONG_MNEM_SUFFIX
)
6878 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6879 .code16gcc directive to support 16-bit mode with
6880 32-bit address. For IRET without a suffix, generate
6881 16-bit IRET (opcode 0xcf) to return from an interrupt
6883 if (i
.tm
.base_opcode
== 0xcf)
6885 i
.suffix
= WORD_MNEM_SUFFIX
;
6886 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6888 /* Warn about changed behavior for segment register push/pop. */
6889 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6890 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6895 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6896 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6897 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6898 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6899 && i
.tm
.extension_opcode
<= 3)))
6904 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6906 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6907 || i
.tm
.opcode_modifier
.no_lsuf
)
6908 i
.suffix
= QWORD_MNEM_SUFFIX
;
6913 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6914 i
.suffix
= LONG_MNEM_SUFFIX
;
6917 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6918 i
.suffix
= WORD_MNEM_SUFFIX
;
6924 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6925 /* Also cover lret/retf/iret in 64-bit mode. */
6926 || (flag_code
== CODE_64BIT
6927 && !i
.tm
.opcode_modifier
.no_lsuf
6928 && !i
.tm
.opcode_modifier
.no_qsuf
))
6929 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6930 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6931 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6932 /* Accept FLDENV et al without suffix. */
6933 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6935 unsigned int suffixes
, evex
= 0;
6937 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6938 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6940 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6942 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6944 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6946 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6949 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6950 also suitable for AT&T syntax mode, it was requested that this be
6951 restricted to just Intel syntax. */
6952 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6956 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6958 if (is_evex_encoding (&i
.tm
)
6959 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6961 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6962 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6963 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6964 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6965 if (!i
.tm
.opcode_modifier
.evex
6966 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6967 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6970 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6971 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6972 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6975 /* Any properly sized operand disambiguates the insn. */
6976 if (i
.types
[op
].bitfield
.xmmword
6977 || i
.types
[op
].bitfield
.ymmword
6978 || i
.types
[op
].bitfield
.zmmword
)
6980 suffixes
&= ~(7 << 6);
6985 if ((i
.flags
[op
] & Operand_Mem
)
6986 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6988 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6990 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6992 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6994 if (is_evex_encoding (&i
.tm
))
7000 /* Are multiple suffixes / operand sizes allowed? */
7001 if (suffixes
& (suffixes
- 1))
7004 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7005 || operand_check
== check_error
))
7007 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7010 if (operand_check
== check_error
)
7012 as_bad (_("no instruction mnemonic suffix given and "
7013 "no register operands; can't size `%s'"), i
.tm
.name
);
7016 if (operand_check
== check_warning
)
7017 as_warn (_("%s; using default for `%s'"),
7019 ? _("ambiguous operand size")
7020 : _("no instruction mnemonic suffix given and "
7021 "no register operands"),
7024 if (i
.tm
.opcode_modifier
.floatmf
)
7025 i
.suffix
= SHORT_MNEM_SUFFIX
;
7026 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7027 || (i
.tm
.base_opcode
== 0x63
7028 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7029 /* handled below */;
7031 i
.tm
.opcode_modifier
.evex
= evex
;
7032 else if (flag_code
== CODE_16BIT
)
7033 i
.suffix
= WORD_MNEM_SUFFIX
;
7034 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7035 i
.suffix
= LONG_MNEM_SUFFIX
;
7037 i
.suffix
= QWORD_MNEM_SUFFIX
;
7041 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7042 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7044 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7045 In AT&T syntax, if there is no suffix (warned about above), the default
7046 will be byte extension. */
7047 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7048 i
.tm
.base_opcode
|= 1;
7050 /* For further processing, the suffix should represent the destination
7051 (register). This is already the case when one was used with
7052 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7053 no suffix to begin with. */
7054 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7056 if (i
.types
[1].bitfield
.word
)
7057 i
.suffix
= WORD_MNEM_SUFFIX
;
7058 else if (i
.types
[1].bitfield
.qword
)
7059 i
.suffix
= QWORD_MNEM_SUFFIX
;
7061 i
.suffix
= LONG_MNEM_SUFFIX
;
7063 i
.tm
.opcode_modifier
.w
= 0;
7067 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7068 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7069 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7071 /* Change the opcode based on the operand size given by i.suffix. */
7074 /* Size floating point instruction. */
7075 case LONG_MNEM_SUFFIX
:
7076 if (i
.tm
.opcode_modifier
.floatmf
)
7078 i
.tm
.base_opcode
^= 4;
7082 case WORD_MNEM_SUFFIX
:
7083 case QWORD_MNEM_SUFFIX
:
7084 /* It's not a byte, select word/dword operation. */
7085 if (i
.tm
.opcode_modifier
.w
)
7088 i
.tm
.base_opcode
|= 8;
7090 i
.tm
.base_opcode
|= 1;
7093 case SHORT_MNEM_SUFFIX
:
7094 /* Now select between word & dword operations via the operand
7095 size prefix, except for instructions that will ignore this
7097 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7098 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7099 && !i
.tm
.opcode_modifier
.floatmf
7100 && !is_any_vex_encoding (&i
.tm
)
7101 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7102 || (flag_code
== CODE_64BIT
7103 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7105 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7107 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7108 prefix
= ADDR_PREFIX_OPCODE
;
7110 if (!add_prefix (prefix
))
7114 /* Set mode64 for an operand. */
7115 if (i
.suffix
== QWORD_MNEM_SUFFIX
7116 && flag_code
== CODE_64BIT
7117 && !i
.tm
.opcode_modifier
.norex64
7118 && !i
.tm
.opcode_modifier
.vexw
7119 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7121 && ! (i
.operands
== 2
7122 && i
.tm
.base_opcode
== 0x90
7123 && i
.tm
.extension_opcode
== None
7124 && i
.types
[0].bitfield
.instance
== Accum
7125 && i
.types
[0].bitfield
.qword
7126 && i
.types
[1].bitfield
.instance
== Accum
7127 && i
.types
[1].bitfield
.qword
))
7133 /* Select word/dword/qword operation with explict data sizing prefix
7134 when there are no suitable register operands. */
7135 if (i
.tm
.opcode_modifier
.w
7136 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7138 || (i
.reg_operands
== 1
7140 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7142 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7143 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7145 || i
.tm
.base_opcode
== 0xf20f38f0))))
7146 i
.tm
.base_opcode
|= 1;
7150 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7152 gas_assert (!i
.suffix
);
7153 gas_assert (i
.reg_operands
);
7155 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7158 /* The address size override prefix changes the size of the
7160 if (flag_code
== CODE_64BIT
7161 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7163 as_bad (_("16-bit addressing unavailable for `%s'"),
7168 if ((flag_code
== CODE_32BIT
7169 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7170 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7171 && !add_prefix (ADDR_PREFIX_OPCODE
))
7176 /* Check invalid register operand when the address size override
7177 prefix changes the size of register operands. */
7179 enum { need_word
, need_dword
, need_qword
} need
;
7181 /* Check the register operand for the address size prefix if
7182 the memory operand has no real registers, like symbol, DISP
7184 if (i
.mem_operands
== 1
7185 && i
.reg_operands
== 1
7187 && i
.types
[1].bitfield
.class == Reg
7188 && (flag_code
== CODE_32BIT
7189 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7190 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7191 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7193 && i
.base_reg
->reg_num
== RegIP
7194 && i
.base_reg
->reg_type
.bitfield
.qword
))
7195 && !add_prefix (ADDR_PREFIX_OPCODE
))
7198 if (flag_code
== CODE_32BIT
)
7199 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7200 else if (i
.prefix
[ADDR_PREFIX
])
7203 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7205 for (op
= 0; op
< i
.operands
; op
++)
7207 if (i
.types
[op
].bitfield
.class != Reg
)
7213 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7217 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7221 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7226 as_bad (_("invalid register operand size for `%s'"),
7237 check_byte_reg (void)
7241 for (op
= i
.operands
; --op
>= 0;)
7243 /* Skip non-register operands. */
7244 if (i
.types
[op
].bitfield
.class != Reg
)
7247 /* If this is an eight bit register, it's OK. If it's the 16 or
7248 32 bit version of an eight bit register, we will just use the
7249 low portion, and that's OK too. */
7250 if (i
.types
[op
].bitfield
.byte
)
7253 /* I/O port address operands are OK too. */
7254 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7255 && i
.tm
.operand_types
[op
].bitfield
.word
)
7258 /* crc32 only wants its source operand checked here. */
7259 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7262 /* Any other register is bad. */
7263 as_bad (_("`%s%s' not allowed with `%s%c'"),
7264 register_prefix
, i
.op
[op
].regs
->reg_name
,
7265 i
.tm
.name
, i
.suffix
);
7272 check_long_reg (void)
7276 for (op
= i
.operands
; --op
>= 0;)
7277 /* Skip non-register operands. */
7278 if (i
.types
[op
].bitfield
.class != Reg
)
7280 /* Reject eight bit registers, except where the template requires
7281 them. (eg. movzb) */
7282 else if (i
.types
[op
].bitfield
.byte
7283 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7284 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7285 && (i
.tm
.operand_types
[op
].bitfield
.word
7286 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7288 as_bad (_("`%s%s' not allowed with `%s%c'"),
7290 i
.op
[op
].regs
->reg_name
,
7295 /* Error if the e prefix on a general reg is missing. */
7296 else if (i
.types
[op
].bitfield
.word
7297 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7298 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7299 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7301 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7302 register_prefix
, i
.op
[op
].regs
->reg_name
,
7306 /* Warn if the r prefix on a general reg is present. */
7307 else if (i
.types
[op
].bitfield
.qword
7308 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7309 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7310 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7313 && i
.tm
.opcode_modifier
.toqword
7314 && i
.types
[0].bitfield
.class != RegSIMD
)
7316 /* Convert to QWORD. We want REX byte. */
7317 i
.suffix
= QWORD_MNEM_SUFFIX
;
7321 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7322 register_prefix
, i
.op
[op
].regs
->reg_name
,
7331 check_qword_reg (void)
7335 for (op
= i
.operands
; --op
>= 0; )
7336 /* Skip non-register operands. */
7337 if (i
.types
[op
].bitfield
.class != Reg
)
7339 /* Reject eight bit registers, except where the template requires
7340 them. (eg. movzb) */
7341 else if (i
.types
[op
].bitfield
.byte
7342 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7343 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7344 && (i
.tm
.operand_types
[op
].bitfield
.word
7345 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7347 as_bad (_("`%s%s' not allowed with `%s%c'"),
7349 i
.op
[op
].regs
->reg_name
,
7354 /* Warn if the r prefix on a general reg is missing. */
7355 else if ((i
.types
[op
].bitfield
.word
7356 || i
.types
[op
].bitfield
.dword
)
7357 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7358 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7359 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7361 /* Prohibit these changes in the 64bit mode, since the
7362 lowering is more complicated. */
7364 && i
.tm
.opcode_modifier
.todword
7365 && i
.types
[0].bitfield
.class != RegSIMD
)
7367 /* Convert to DWORD. We don't want REX byte. */
7368 i
.suffix
= LONG_MNEM_SUFFIX
;
7372 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7373 register_prefix
, i
.op
[op
].regs
->reg_name
,
7382 check_word_reg (void)
7385 for (op
= i
.operands
; --op
>= 0;)
7386 /* Skip non-register operands. */
7387 if (i
.types
[op
].bitfield
.class != Reg
)
7389 /* Reject eight bit registers, except where the template requires
7390 them. (eg. movzb) */
7391 else if (i
.types
[op
].bitfield
.byte
7392 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7393 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7394 && (i
.tm
.operand_types
[op
].bitfield
.word
7395 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7397 as_bad (_("`%s%s' not allowed with `%s%c'"),
7399 i
.op
[op
].regs
->reg_name
,
7404 /* Error if the e or r prefix on a general reg is present. */
7405 else if ((i
.types
[op
].bitfield
.dword
7406 || i
.types
[op
].bitfield
.qword
)
7407 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7408 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7409 && i
.tm
.operand_types
[op
].bitfield
.word
)
7411 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7412 register_prefix
, i
.op
[op
].regs
->reg_name
,
7420 update_imm (unsigned int j
)
7422 i386_operand_type overlap
= i
.types
[j
];
7423 if ((overlap
.bitfield
.imm8
7424 || overlap
.bitfield
.imm8s
7425 || overlap
.bitfield
.imm16
7426 || overlap
.bitfield
.imm32
7427 || overlap
.bitfield
.imm32s
7428 || overlap
.bitfield
.imm64
)
7429 && !operand_type_equal (&overlap
, &imm8
)
7430 && !operand_type_equal (&overlap
, &imm8s
)
7431 && !operand_type_equal (&overlap
, &imm16
)
7432 && !operand_type_equal (&overlap
, &imm32
)
7433 && !operand_type_equal (&overlap
, &imm32s
)
7434 && !operand_type_equal (&overlap
, &imm64
))
7438 i386_operand_type temp
;
7440 operand_type_set (&temp
, 0);
7441 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7443 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7444 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7446 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7447 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7448 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7450 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7451 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7454 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7457 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7458 || operand_type_equal (&overlap
, &imm16_32
)
7459 || operand_type_equal (&overlap
, &imm16_32s
))
7461 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7466 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7467 overlap
= operand_type_and (overlap
, imm32s
);
7468 else if (i
.prefix
[DATA_PREFIX
])
7469 overlap
= operand_type_and (overlap
,
7470 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7471 if (!operand_type_equal (&overlap
, &imm8
)
7472 && !operand_type_equal (&overlap
, &imm8s
)
7473 && !operand_type_equal (&overlap
, &imm16
)
7474 && !operand_type_equal (&overlap
, &imm32
)
7475 && !operand_type_equal (&overlap
, &imm32s
)
7476 && !operand_type_equal (&overlap
, &imm64
))
7478 as_bad (_("no instruction mnemonic suffix given; "
7479 "can't determine immediate size"));
7483 i
.types
[j
] = overlap
;
7493 /* Update the first 2 immediate operands. */
7494 n
= i
.operands
> 2 ? 2 : i
.operands
;
7497 for (j
= 0; j
< n
; j
++)
7498 if (update_imm (j
) == 0)
7501 /* The 3rd operand can't be immediate operand. */
7502 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7509 process_operands (void)
7511 /* Default segment register this instruction will use for memory
7512 accesses. 0 means unknown. This is only for optimizing out
7513 unnecessary segment overrides. */
7514 const seg_entry
*default_seg
= 0;
7516 if (i
.tm
.opcode_modifier
.sse2avx
)
7518 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7520 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7521 i
.prefix
[REX_PREFIX
] = 0;
7524 /* ImmExt should be processed after SSE2AVX. */
7525 else if (i
.tm
.opcode_modifier
.immext
)
7528 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7530 unsigned int dupl
= i
.operands
;
7531 unsigned int dest
= dupl
- 1;
7534 /* The destination must be an xmm register. */
7535 gas_assert (i
.reg_operands
7536 && MAX_OPERANDS
> dupl
7537 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7539 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7540 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7542 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7544 /* Keep xmm0 for instructions with VEX prefix and 3
7546 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7547 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7552 /* We remove the first xmm0 and keep the number of
7553 operands unchanged, which in fact duplicates the
7555 for (j
= 1; j
< i
.operands
; j
++)
7557 i
.op
[j
- 1] = i
.op
[j
];
7558 i
.types
[j
- 1] = i
.types
[j
];
7559 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7560 i
.flags
[j
- 1] = i
.flags
[j
];
7564 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7566 gas_assert ((MAX_OPERANDS
- 1) > dupl
7567 && (i
.tm
.opcode_modifier
.vexsources
7570 /* Add the implicit xmm0 for instructions with VEX prefix
7572 for (j
= i
.operands
; j
> 0; j
--)
7574 i
.op
[j
] = i
.op
[j
- 1];
7575 i
.types
[j
] = i
.types
[j
- 1];
7576 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7577 i
.flags
[j
] = i
.flags
[j
- 1];
7580 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7581 i
.types
[0] = regxmm
;
7582 i
.tm
.operand_types
[0] = regxmm
;
7585 i
.reg_operands
+= 2;
7590 i
.op
[dupl
] = i
.op
[dest
];
7591 i
.types
[dupl
] = i
.types
[dest
];
7592 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7593 i
.flags
[dupl
] = i
.flags
[dest
];
7602 i
.op
[dupl
] = i
.op
[dest
];
7603 i
.types
[dupl
] = i
.types
[dest
];
7604 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7605 i
.flags
[dupl
] = i
.flags
[dest
];
7608 if (i
.tm
.opcode_modifier
.immext
)
7611 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7612 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7616 for (j
= 1; j
< i
.operands
; j
++)
7618 i
.op
[j
- 1] = i
.op
[j
];
7619 i
.types
[j
- 1] = i
.types
[j
];
7621 /* We need to adjust fields in i.tm since they are used by
7622 build_modrm_byte. */
7623 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7625 i
.flags
[j
- 1] = i
.flags
[j
];
7632 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7634 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7636 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7637 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7638 regnum
= register_number (i
.op
[1].regs
);
7639 first_reg_in_group
= regnum
& ~3;
7640 last_reg_in_group
= first_reg_in_group
+ 3;
7641 if (regnum
!= first_reg_in_group
)
7642 as_warn (_("source register `%s%s' implicitly denotes"
7643 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7644 register_prefix
, i
.op
[1].regs
->reg_name
,
7645 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7646 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7649 else if (i
.tm
.opcode_modifier
.regkludge
)
7651 /* The imul $imm, %reg instruction is converted into
7652 imul $imm, %reg, %reg, and the clr %reg instruction
7653 is converted into xor %reg, %reg. */
7655 unsigned int first_reg_op
;
7657 if (operand_type_check (i
.types
[0], reg
))
7661 /* Pretend we saw the extra register operand. */
7662 gas_assert (i
.reg_operands
== 1
7663 && i
.op
[first_reg_op
+ 1].regs
== 0);
7664 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7665 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7670 if (i
.tm
.opcode_modifier
.modrm
)
7672 /* The opcode is completed (modulo i.tm.extension_opcode which
7673 must be put into the modrm byte). Now, we make the modrm and
7674 index base bytes based on all the info we've collected. */
7676 default_seg
= build_modrm_byte ();
7678 else if (i
.types
[0].bitfield
.class == SReg
)
7680 if (flag_code
!= CODE_64BIT
7681 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7682 && i
.op
[0].regs
->reg_num
== 1
7683 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7684 && i
.op
[0].regs
->reg_num
< 4)
7686 as_bad (_("you can't `%s %s%s'"),
7687 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7690 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7692 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7693 i
.tm
.opcode_length
= 2;
7695 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7697 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7701 else if (i
.tm
.opcode_modifier
.isstring
)
7703 /* For the string instructions that allow a segment override
7704 on one of their operands, the default segment is ds. */
7707 else if (i
.short_form
)
7709 /* The register or float register operand is in operand
7711 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7713 /* Register goes in low 3 bits of opcode. */
7714 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7715 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7717 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7719 /* Warn about some common errors, but press on regardless.
7720 The first case can be generated by gcc (<= 2.8.1). */
7721 if (i
.operands
== 2)
7723 /* Reversed arguments on faddp, fsubp, etc. */
7724 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7725 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7726 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7730 /* Extraneous `l' suffix on fp insn. */
7731 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7732 register_prefix
, i
.op
[0].regs
->reg_name
);
7737 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7738 && i
.tm
.base_opcode
== 0x8d /* lea */
7739 && !is_any_vex_encoding(&i
.tm
))
7741 if (!quiet_warnings
)
7742 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7746 i
.prefix
[SEG_PREFIX
] = 0;
7750 /* If a segment was explicitly specified, and the specified segment
7751 is neither the default nor the one already recorded from a prefix,
7752 use an opcode prefix to select it. If we never figured out what
7753 the default segment is, then default_seg will be zero at this
7754 point, and the specified segment prefix will always be used. */
7756 && i
.seg
[0] != default_seg
7757 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7759 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7765 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7766 bfd_boolean do_sse2avx
)
7768 if (r
->reg_flags
& RegRex
)
7770 if (i
.rex
& rex_bit
)
7771 as_bad (_("same type of prefix used twice"));
7774 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7776 gas_assert (i
.vex
.register_specifier
== r
);
7777 i
.vex
.register_specifier
+= 8;
7780 if (r
->reg_flags
& RegVRex
)
7784 static const seg_entry
*
7785 build_modrm_byte (void)
7787 const seg_entry
*default_seg
= 0;
7788 unsigned int source
, dest
;
7791 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7794 unsigned int nds
, reg_slot
;
7797 dest
= i
.operands
- 1;
7800 /* There are 2 kinds of instructions:
7801 1. 5 operands: 4 register operands or 3 register operands
7802 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7803 VexW0 or VexW1. The destination must be either XMM, YMM or
7805 2. 4 operands: 4 register operands or 3 register operands
7806 plus 1 memory operand, with VexXDS. */
7807 gas_assert ((i
.reg_operands
== 4
7808 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7809 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7810 && i
.tm
.opcode_modifier
.vexw
7811 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7813 /* If VexW1 is set, the first non-immediate operand is the source and
7814 the second non-immediate one is encoded in the immediate operand. */
7815 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7817 source
= i
.imm_operands
;
7818 reg_slot
= i
.imm_operands
+ 1;
7822 source
= i
.imm_operands
+ 1;
7823 reg_slot
= i
.imm_operands
;
7826 if (i
.imm_operands
== 0)
7828 /* When there is no immediate operand, generate an 8bit
7829 immediate operand to encode the first operand. */
7830 exp
= &im_expressions
[i
.imm_operands
++];
7831 i
.op
[i
.operands
].imms
= exp
;
7832 i
.types
[i
.operands
] = imm8
;
7835 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7836 exp
->X_op
= O_constant
;
7837 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7838 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7842 gas_assert (i
.imm_operands
== 1);
7843 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7844 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7846 /* Turn on Imm8 again so that output_imm will generate it. */
7847 i
.types
[0].bitfield
.imm8
= 1;
7849 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7850 i
.op
[0].imms
->X_add_number
7851 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7852 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7855 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7856 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7861 /* i.reg_operands MUST be the number of real register operands;
7862 implicit registers do not count. If there are 3 register
7863 operands, it must be a instruction with VexNDS. For a
7864 instruction with VexNDD, the destination register is encoded
7865 in VEX prefix. If there are 4 register operands, it must be
7866 a instruction with VEX prefix and 3 sources. */
7867 if (i
.mem_operands
== 0
7868 && ((i
.reg_operands
== 2
7869 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7870 || (i
.reg_operands
== 3
7871 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7872 || (i
.reg_operands
== 4 && vex_3_sources
)))
7880 /* When there are 3 operands, one of them may be immediate,
7881 which may be the first or the last operand. Otherwise,
7882 the first operand must be shift count register (cl) or it
7883 is an instruction with VexNDS. */
7884 gas_assert (i
.imm_operands
== 1
7885 || (i
.imm_operands
== 0
7886 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7887 || (i
.types
[0].bitfield
.instance
== RegC
7888 && i
.types
[0].bitfield
.byte
))));
7889 if (operand_type_check (i
.types
[0], imm
)
7890 || (i
.types
[0].bitfield
.instance
== RegC
7891 && i
.types
[0].bitfield
.byte
))
7897 /* When there are 4 operands, the first two must be 8bit
7898 immediate operands. The source operand will be the 3rd
7901 For instructions with VexNDS, if the first operand
7902 an imm8, the source operand is the 2nd one. If the last
7903 operand is imm8, the source operand is the first one. */
7904 gas_assert ((i
.imm_operands
== 2
7905 && i
.types
[0].bitfield
.imm8
7906 && i
.types
[1].bitfield
.imm8
)
7907 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7908 && i
.imm_operands
== 1
7909 && (i
.types
[0].bitfield
.imm8
7910 || i
.types
[i
.operands
- 1].bitfield
.imm8
7912 if (i
.imm_operands
== 2)
7916 if (i
.types
[0].bitfield
.imm8
)
7923 if (is_evex_encoding (&i
.tm
))
7925 /* For EVEX instructions, when there are 5 operands, the
7926 first one must be immediate operand. If the second one
7927 is immediate operand, the source operand is the 3th
7928 one. If the last one is immediate operand, the source
7929 operand is the 2nd one. */
7930 gas_assert (i
.imm_operands
== 2
7931 && i
.tm
.opcode_modifier
.sae
7932 && operand_type_check (i
.types
[0], imm
));
7933 if (operand_type_check (i
.types
[1], imm
))
7935 else if (operand_type_check (i
.types
[4], imm
))
7949 /* RC/SAE operand could be between DEST and SRC. That happens
7950 when one operand is GPR and the other one is XMM/YMM/ZMM
7952 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7955 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7957 /* For instructions with VexNDS, the register-only source
7958 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7959 register. It is encoded in VEX prefix. */
7961 i386_operand_type op
;
7964 /* Swap two source operands if needed. */
7965 if (i
.tm
.opcode_modifier
.swapsources
)
7973 op
= i
.tm
.operand_types
[vvvv
];
7974 if ((dest
+ 1) >= i
.operands
7975 || ((op
.bitfield
.class != Reg
7976 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7977 && op
.bitfield
.class != RegSIMD
7978 && !operand_type_equal (&op
, ®mask
)))
7980 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7986 /* One of the register operands will be encoded in the i.rm.reg
7987 field, the other in the combined i.rm.mode and i.rm.regmem
7988 fields. If no form of this instruction supports a memory
7989 destination operand, then we assume the source operand may
7990 sometimes be a memory operand and so we need to store the
7991 destination in the i.rm.reg field. */
7992 if (!i
.tm
.opcode_modifier
.regmem
7993 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7995 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7996 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7997 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7998 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8002 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8003 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8004 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8005 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8007 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8009 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8012 add_prefix (LOCK_PREFIX_OPCODE
);
8016 { /* If it's not 2 reg operands... */
8021 unsigned int fake_zero_displacement
= 0;
8024 for (op
= 0; op
< i
.operands
; op
++)
8025 if (i
.flags
[op
] & Operand_Mem
)
8027 gas_assert (op
< i
.operands
);
8029 if (i
.tm
.opcode_modifier
.sib
)
8031 /* The index register of VSIB shouldn't be RegIZ. */
8032 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8033 && i
.index_reg
->reg_num
== RegIZ
)
8036 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8039 i
.sib
.base
= NO_BASE_REGISTER
;
8040 i
.sib
.scale
= i
.log2_scale_factor
;
8041 i
.types
[op
].bitfield
.disp8
= 0;
8042 i
.types
[op
].bitfield
.disp16
= 0;
8043 i
.types
[op
].bitfield
.disp64
= 0;
8044 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8046 /* Must be 32 bit */
8047 i
.types
[op
].bitfield
.disp32
= 1;
8048 i
.types
[op
].bitfield
.disp32s
= 0;
8052 i
.types
[op
].bitfield
.disp32
= 0;
8053 i
.types
[op
].bitfield
.disp32s
= 1;
8057 /* Since the mandatory SIB always has index register, so
8058 the code logic remains unchanged. The non-mandatory SIB
8059 without index register is allowed and will be handled
8063 if (i
.index_reg
->reg_num
== RegIZ
)
8064 i
.sib
.index
= NO_INDEX_REGISTER
;
8066 i
.sib
.index
= i
.index_reg
->reg_num
;
8067 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8073 if (i
.base_reg
== 0)
8076 if (!i
.disp_operands
)
8077 fake_zero_displacement
= 1;
8078 if (i
.index_reg
== 0)
8080 i386_operand_type newdisp
;
8082 /* Both check for VSIB and mandatory non-vector SIB. */
8083 gas_assert (!i
.tm
.opcode_modifier
.sib
8084 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8085 /* Operand is just <disp> */
8086 if (flag_code
== CODE_64BIT
)
8088 /* 64bit mode overwrites the 32bit absolute
8089 addressing by RIP relative addressing and
8090 absolute addressing is encoded by one of the
8091 redundant SIB forms. */
8092 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8093 i
.sib
.base
= NO_BASE_REGISTER
;
8094 i
.sib
.index
= NO_INDEX_REGISTER
;
8095 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8097 else if ((flag_code
== CODE_16BIT
)
8098 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8100 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8105 i
.rm
.regmem
= NO_BASE_REGISTER
;
8108 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8109 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8111 else if (!i
.tm
.opcode_modifier
.sib
)
8113 /* !i.base_reg && i.index_reg */
8114 if (i
.index_reg
->reg_num
== RegIZ
)
8115 i
.sib
.index
= NO_INDEX_REGISTER
;
8117 i
.sib
.index
= i
.index_reg
->reg_num
;
8118 i
.sib
.base
= NO_BASE_REGISTER
;
8119 i
.sib
.scale
= i
.log2_scale_factor
;
8120 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8121 i
.types
[op
].bitfield
.disp8
= 0;
8122 i
.types
[op
].bitfield
.disp16
= 0;
8123 i
.types
[op
].bitfield
.disp64
= 0;
8124 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8126 /* Must be 32 bit */
8127 i
.types
[op
].bitfield
.disp32
= 1;
8128 i
.types
[op
].bitfield
.disp32s
= 0;
8132 i
.types
[op
].bitfield
.disp32
= 0;
8133 i
.types
[op
].bitfield
.disp32s
= 1;
8135 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8139 /* RIP addressing for 64bit mode. */
8140 else if (i
.base_reg
->reg_num
== RegIP
)
8142 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8143 i
.rm
.regmem
= NO_BASE_REGISTER
;
8144 i
.types
[op
].bitfield
.disp8
= 0;
8145 i
.types
[op
].bitfield
.disp16
= 0;
8146 i
.types
[op
].bitfield
.disp32
= 0;
8147 i
.types
[op
].bitfield
.disp32s
= 1;
8148 i
.types
[op
].bitfield
.disp64
= 0;
8149 i
.flags
[op
] |= Operand_PCrel
;
8150 if (! i
.disp_operands
)
8151 fake_zero_displacement
= 1;
8153 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8155 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8156 switch (i
.base_reg
->reg_num
)
8159 if (i
.index_reg
== 0)
8161 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8162 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8166 if (i
.index_reg
== 0)
8169 if (operand_type_check (i
.types
[op
], disp
) == 0)
8171 /* fake (%bp) into 0(%bp) */
8172 if (i
.disp_encoding
== disp_encoding_16bit
)
8173 i
.types
[op
].bitfield
.disp16
= 1;
8175 i
.types
[op
].bitfield
.disp8
= 1;
8176 fake_zero_displacement
= 1;
8179 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8180 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8182 default: /* (%si) -> 4 or (%di) -> 5 */
8183 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8185 if (!fake_zero_displacement
8189 fake_zero_displacement
= 1;
8190 if (i
.disp_encoding
== disp_encoding_8bit
)
8191 i
.types
[op
].bitfield
.disp8
= 1;
8193 i
.types
[op
].bitfield
.disp16
= 1;
8195 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8197 else /* i.base_reg and 32/64 bit mode */
8199 if (flag_code
== CODE_64BIT
8200 && operand_type_check (i
.types
[op
], disp
))
8202 i
.types
[op
].bitfield
.disp16
= 0;
8203 i
.types
[op
].bitfield
.disp64
= 0;
8204 if (i
.prefix
[ADDR_PREFIX
] == 0)
8206 i
.types
[op
].bitfield
.disp32
= 0;
8207 i
.types
[op
].bitfield
.disp32s
= 1;
8211 i
.types
[op
].bitfield
.disp32
= 1;
8212 i
.types
[op
].bitfield
.disp32s
= 0;
8216 if (!i
.tm
.opcode_modifier
.sib
)
8217 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8218 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8220 i
.sib
.base
= i
.base_reg
->reg_num
;
8221 /* x86-64 ignores REX prefix bit here to avoid decoder
8223 if (!(i
.base_reg
->reg_flags
& RegRex
)
8224 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8225 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8227 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8229 fake_zero_displacement
= 1;
8230 if (i
.disp_encoding
== disp_encoding_32bit
)
8231 i
.types
[op
].bitfield
.disp32
= 1;
8233 i
.types
[op
].bitfield
.disp8
= 1;
8235 i
.sib
.scale
= i
.log2_scale_factor
;
8236 if (i
.index_reg
== 0)
8238 /* Only check for VSIB. */
8239 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8240 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8241 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8243 /* <disp>(%esp) becomes two byte modrm with no index
8244 register. We've already stored the code for esp
8245 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8246 Any base register besides %esp will not use the
8247 extra modrm byte. */
8248 i
.sib
.index
= NO_INDEX_REGISTER
;
8250 else if (!i
.tm
.opcode_modifier
.sib
)
8252 if (i
.index_reg
->reg_num
== RegIZ
)
8253 i
.sib
.index
= NO_INDEX_REGISTER
;
8255 i
.sib
.index
= i
.index_reg
->reg_num
;
8256 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8257 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8262 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8263 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8267 if (!fake_zero_displacement
8271 fake_zero_displacement
= 1;
8272 if (i
.disp_encoding
== disp_encoding_8bit
)
8273 i
.types
[op
].bitfield
.disp8
= 1;
8275 i
.types
[op
].bitfield
.disp32
= 1;
8277 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8281 if (fake_zero_displacement
)
8283 /* Fakes a zero displacement assuming that i.types[op]
8284 holds the correct displacement size. */
8287 gas_assert (i
.op
[op
].disps
== 0);
8288 exp
= &disp_expressions
[i
.disp_operands
++];
8289 i
.op
[op
].disps
= exp
;
8290 exp
->X_op
= O_constant
;
8291 exp
->X_add_number
= 0;
8292 exp
->X_add_symbol
= (symbolS
*) 0;
8293 exp
->X_op_symbol
= (symbolS
*) 0;
8301 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8303 if (operand_type_check (i
.types
[0], imm
))
8304 i
.vex
.register_specifier
= NULL
;
8307 /* VEX.vvvv encodes one of the sources when the first
8308 operand is not an immediate. */
8309 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8310 i
.vex
.register_specifier
= i
.op
[0].regs
;
8312 i
.vex
.register_specifier
= i
.op
[1].regs
;
8315 /* Destination is a XMM register encoded in the ModRM.reg
8317 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8318 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8321 /* ModRM.rm and VEX.B encodes the other source. */
8322 if (!i
.mem_operands
)
8326 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8327 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8329 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8331 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8335 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8337 i
.vex
.register_specifier
= i
.op
[2].regs
;
8338 if (!i
.mem_operands
)
8341 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8342 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8346 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8347 (if any) based on i.tm.extension_opcode. Again, we must be
8348 careful to make sure that segment/control/debug/test/MMX
8349 registers are coded into the i.rm.reg field. */
8350 else if (i
.reg_operands
)
8353 unsigned int vex_reg
= ~0;
8355 for (op
= 0; op
< i
.operands
; op
++)
8356 if (i
.types
[op
].bitfield
.class == Reg
8357 || i
.types
[op
].bitfield
.class == RegBND
8358 || i
.types
[op
].bitfield
.class == RegMask
8359 || i
.types
[op
].bitfield
.class == SReg
8360 || i
.types
[op
].bitfield
.class == RegCR
8361 || i
.types
[op
].bitfield
.class == RegDR
8362 || i
.types
[op
].bitfield
.class == RegTR
8363 || i
.types
[op
].bitfield
.class == RegSIMD
8364 || i
.types
[op
].bitfield
.class == RegMMX
)
8369 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8371 /* For instructions with VexNDS, the register-only
8372 source operand is encoded in VEX prefix. */
8373 gas_assert (mem
!= (unsigned int) ~0);
8378 gas_assert (op
< i
.operands
);
8382 /* Check register-only source operand when two source
8383 operands are swapped. */
8384 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8385 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8389 gas_assert (mem
== (vex_reg
+ 1)
8390 && op
< i
.operands
);
8395 gas_assert (vex_reg
< i
.operands
);
8399 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8401 /* For instructions with VexNDD, the register destination
8402 is encoded in VEX prefix. */
8403 if (i
.mem_operands
== 0)
8405 /* There is no memory operand. */
8406 gas_assert ((op
+ 2) == i
.operands
);
8411 /* There are only 2 non-immediate operands. */
8412 gas_assert (op
< i
.imm_operands
+ 2
8413 && i
.operands
== i
.imm_operands
+ 2);
8414 vex_reg
= i
.imm_operands
+ 1;
8418 gas_assert (op
< i
.operands
);
8420 if (vex_reg
!= (unsigned int) ~0)
8422 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8424 if ((type
->bitfield
.class != Reg
8425 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8426 && type
->bitfield
.class != RegSIMD
8427 && !operand_type_equal (type
, ®mask
))
8430 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8433 /* Don't set OP operand twice. */
8436 /* If there is an extension opcode to put here, the
8437 register number must be put into the regmem field. */
8438 if (i
.tm
.extension_opcode
!= None
)
8440 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8441 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8442 i
.tm
.opcode_modifier
.sse2avx
);
8446 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8447 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8448 i
.tm
.opcode_modifier
.sse2avx
);
8452 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8453 must set it to 3 to indicate this is a register operand
8454 in the regmem field. */
8455 if (!i
.mem_operands
)
8459 /* Fill in i.rm.reg field with extension opcode (if any). */
8460 if (i
.tm
.extension_opcode
!= None
)
8461 i
.rm
.reg
= i
.tm
.extension_opcode
;
8467 frag_opcode_byte (unsigned char byte
)
8469 if (now_seg
!= absolute_section
)
8470 FRAG_APPEND_1_CHAR (byte
);
8472 ++abs_section_offset
;
8476 flip_code16 (unsigned int code16
)
8478 gas_assert (i
.tm
.operands
== 1);
8480 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8481 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8482 || i
.tm
.operand_types
[0].bitfield
.disp32s
8483 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8488 output_branch (void)
8494 relax_substateT subtype
;
8498 if (now_seg
== absolute_section
)
8500 as_bad (_("relaxable branches not supported in absolute section"));
8504 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8505 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8508 if (i
.prefix
[DATA_PREFIX
] != 0)
8512 code16
^= flip_code16(code16
);
8514 /* Pentium4 branch hints. */
8515 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8516 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8521 if (i
.prefix
[REX_PREFIX
] != 0)
8527 /* BND prefixed jump. */
8528 if (i
.prefix
[BND_PREFIX
] != 0)
8534 if (i
.prefixes
!= 0)
8535 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8537 /* It's always a symbol; End frag & setup for relax.
8538 Make sure there is enough room in this frag for the largest
8539 instruction we may generate in md_convert_frag. This is 2
8540 bytes for the opcode and room for the prefix and largest
8542 frag_grow (prefix
+ 2 + 4);
8543 /* Prefix and 1 opcode byte go in fr_fix. */
8544 p
= frag_more (prefix
+ 1);
8545 if (i
.prefix
[DATA_PREFIX
] != 0)
8546 *p
++ = DATA_PREFIX_OPCODE
;
8547 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8548 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8549 *p
++ = i
.prefix
[SEG_PREFIX
];
8550 if (i
.prefix
[BND_PREFIX
] != 0)
8551 *p
++ = BND_PREFIX_OPCODE
;
8552 if (i
.prefix
[REX_PREFIX
] != 0)
8553 *p
++ = i
.prefix
[REX_PREFIX
];
8554 *p
= i
.tm
.base_opcode
;
8556 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8557 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8558 else if (cpu_arch_flags
.bitfield
.cpui386
)
8559 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8561 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8564 sym
= i
.op
[0].disps
->X_add_symbol
;
8565 off
= i
.op
[0].disps
->X_add_number
;
8567 if (i
.op
[0].disps
->X_op
!= O_constant
8568 && i
.op
[0].disps
->X_op
!= O_symbol
)
8570 /* Handle complex expressions. */
8571 sym
= make_expr_symbol (i
.op
[0].disps
);
8575 /* 1 possible extra opcode + 4 byte displacement go in var part.
8576 Pass reloc in fr_var. */
8577 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8581 /* Return TRUE iff PLT32 relocation should be used for branching to
8585 need_plt32_p (symbolS
*s
)
8587 /* PLT32 relocation is ELF only. */
8592 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8593 krtld support it. */
8597 /* Since there is no need to prepare for PLT branch on x86-64, we
8598 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8599 be used as a marker for 32-bit PC-relative branches. */
8603 /* Weak or undefined symbol need PLT32 relocation. */
8604 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8607 /* Non-global symbol doesn't need PLT32 relocation. */
8608 if (! S_IS_EXTERNAL (s
))
8611 /* Other global symbols need PLT32 relocation. NB: Symbol with
8612 non-default visibilities are treated as normal global symbol
8613 so that PLT32 relocation can be used as a marker for 32-bit
8614 PC-relative branches. It is useful for linker relaxation. */
8625 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8627 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8629 /* This is a loop or jecxz type instruction. */
8631 if (i
.prefix
[ADDR_PREFIX
] != 0)
8633 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8636 /* Pentium4 branch hints. */
8637 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8638 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8640 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8649 if (flag_code
== CODE_16BIT
)
8652 if (i
.prefix
[DATA_PREFIX
] != 0)
8654 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8656 code16
^= flip_code16(code16
);
8664 /* BND prefixed jump. */
8665 if (i
.prefix
[BND_PREFIX
] != 0)
8667 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8671 if (i
.prefix
[REX_PREFIX
] != 0)
8673 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8677 if (i
.prefixes
!= 0)
8678 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8680 if (now_seg
== absolute_section
)
8682 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8686 p
= frag_more (i
.tm
.opcode_length
+ size
);
8687 switch (i
.tm
.opcode_length
)
8690 *p
++ = i
.tm
.base_opcode
>> 8;
8693 *p
++ = i
.tm
.base_opcode
;
8699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8701 && jump_reloc
== NO_RELOC
8702 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8703 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8706 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8708 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8709 i
.op
[0].disps
, 1, jump_reloc
);
8711 /* All jumps handled here are signed, but don't use a signed limit
8712 check for 32 and 16 bit jumps as we want to allow wrap around at
8713 4G and 64k respectively. */
8715 fixP
->fx_signed
= 1;
8719 output_interseg_jump (void)
8727 if (flag_code
== CODE_16BIT
)
8731 if (i
.prefix
[DATA_PREFIX
] != 0)
8738 gas_assert (!i
.prefix
[REX_PREFIX
]);
8744 if (i
.prefixes
!= 0)
8745 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8747 if (now_seg
== absolute_section
)
8749 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8753 /* 1 opcode; 2 segment; offset */
8754 p
= frag_more (prefix
+ 1 + 2 + size
);
8756 if (i
.prefix
[DATA_PREFIX
] != 0)
8757 *p
++ = DATA_PREFIX_OPCODE
;
8759 if (i
.prefix
[REX_PREFIX
] != 0)
8760 *p
++ = i
.prefix
[REX_PREFIX
];
8762 *p
++ = i
.tm
.base_opcode
;
8763 if (i
.op
[1].imms
->X_op
== O_constant
)
8765 offsetT n
= i
.op
[1].imms
->X_add_number
;
8768 && !fits_in_unsigned_word (n
)
8769 && !fits_in_signed_word (n
))
8771 as_bad (_("16-bit jump out of range"));
8774 md_number_to_chars (p
, n
, size
);
8777 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8778 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8781 if (i
.op
[0].imms
->X_op
== O_constant
)
8782 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8784 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8785 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8788 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8793 asection
*seg
= now_seg
;
8794 subsegT subseg
= now_subseg
;
8796 unsigned int alignment
, align_size_1
;
8797 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8798 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8799 unsigned int padding
;
8801 if (!IS_ELF
|| !x86_used_note
)
8804 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8806 /* The .note.gnu.property section layout:
8808 Field Length Contents
8811 n_descsz 4 The note descriptor size
8812 n_type 4 NT_GNU_PROPERTY_TYPE_0
8814 n_desc n_descsz The program property array
8818 /* Create the .note.gnu.property section. */
8819 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8820 bfd_set_section_flags (sec
,
8827 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8838 bfd_set_section_alignment (sec
, alignment
);
8839 elf_section_type (sec
) = SHT_NOTE
;
8841 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8843 isa_1_descsz_raw
= 4 + 4 + 4;
8844 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8845 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8847 feature_2_descsz_raw
= isa_1_descsz
;
8848 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8850 feature_2_descsz_raw
+= 4 + 4 + 4;
8851 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8852 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8855 descsz
= feature_2_descsz
;
8856 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8857 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8859 /* Write n_namsz. */
8860 md_number_to_chars (p
, (valueT
) 4, 4);
8862 /* Write n_descsz. */
8863 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8866 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8869 memcpy (p
+ 4 * 3, "GNU", 4);
8871 /* Write 4-byte type. */
8872 md_number_to_chars (p
+ 4 * 4,
8873 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8875 /* Write 4-byte data size. */
8876 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8878 /* Write 4-byte data. */
8879 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8881 /* Zero out paddings. */
8882 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8884 memset (p
+ 4 * 7, 0, padding
);
8886 /* Write 4-byte type. */
8887 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8888 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8890 /* Write 4-byte data size. */
8891 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8893 /* Write 4-byte data. */
8894 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8895 (valueT
) x86_feature_2_used
, 4);
8897 /* Zero out paddings. */
8898 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8900 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8902 /* We probably can't restore the current segment, for there likely
8905 subseg_set (seg
, subseg
);
8910 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8911 const char *frag_now_ptr
)
8913 unsigned int len
= 0;
8915 if (start_frag
!= frag_now
)
8917 const fragS
*fr
= start_frag
;
8922 } while (fr
&& fr
!= frag_now
);
8925 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8928 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8929 be macro-fused with conditional jumps.
8930 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8931 or is one of the following format:
8944 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8946 /* No RIP address. */
8947 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8950 /* No VEX/EVEX encoding. */
8951 if (is_any_vex_encoding (&i
.tm
))
8954 /* add, sub without add/sub m, imm. */
8955 if (i
.tm
.base_opcode
<= 5
8956 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8957 || ((i
.tm
.base_opcode
| 3) == 0x83
8958 && (i
.tm
.extension_opcode
== 0x5
8959 || i
.tm
.extension_opcode
== 0x0)))
8961 *mf_cmp_p
= mf_cmp_alu_cmp
;
8962 return !(i
.mem_operands
&& i
.imm_operands
);
8965 /* and without and m, imm. */
8966 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8967 || ((i
.tm
.base_opcode
| 3) == 0x83
8968 && i
.tm
.extension_opcode
== 0x4))
8970 *mf_cmp_p
= mf_cmp_test_and
;
8971 return !(i
.mem_operands
&& i
.imm_operands
);
8974 /* test without test m imm. */
8975 if ((i
.tm
.base_opcode
| 1) == 0x85
8976 || (i
.tm
.base_opcode
| 1) == 0xa9
8977 || ((i
.tm
.base_opcode
| 1) == 0xf7
8978 && i
.tm
.extension_opcode
== 0))
8980 *mf_cmp_p
= mf_cmp_test_and
;
8981 return !(i
.mem_operands
&& i
.imm_operands
);
8984 /* cmp without cmp m, imm. */
8985 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8986 || ((i
.tm
.base_opcode
| 3) == 0x83
8987 && (i
.tm
.extension_opcode
== 0x7)))
8989 *mf_cmp_p
= mf_cmp_alu_cmp
;
8990 return !(i
.mem_operands
&& i
.imm_operands
);
8993 /* inc, dec without inc/dec m. */
8994 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8995 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8996 || ((i
.tm
.base_opcode
| 1) == 0xff
8997 && i
.tm
.extension_opcode
<= 0x1))
8999 *mf_cmp_p
= mf_cmp_incdec
;
9000 return !i
.mem_operands
;
9006 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9009 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9011 /* NB: Don't work with COND_JUMP86 without i386. */
9012 if (!align_branch_power
9013 || now_seg
== absolute_section
9014 || !cpu_arch_flags
.bitfield
.cpui386
9015 || !(align_branch
& align_branch_fused_bit
))
9018 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9020 if (last_insn
.kind
== last_insn_other
9021 || last_insn
.seg
!= now_seg
)
9024 as_warn_where (last_insn
.file
, last_insn
.line
,
9025 _("`%s` skips -malign-branch-boundary on `%s`"),
9026 last_insn
.name
, i
.tm
.name
);
9032 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9035 add_branch_prefix_frag_p (void)
9037 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9038 to PadLock instructions since they include prefixes in opcode. */
9039 if (!align_branch_power
9040 || !align_branch_prefix_size
9041 || now_seg
== absolute_section
9042 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9043 || !cpu_arch_flags
.bitfield
.cpui386
)
9046 /* Don't add prefix if it is a prefix or there is no operand in case
9047 that segment prefix is special. */
9048 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9051 if (last_insn
.kind
== last_insn_other
9052 || last_insn
.seg
!= now_seg
)
9056 as_warn_where (last_insn
.file
, last_insn
.line
,
9057 _("`%s` skips -malign-branch-boundary on `%s`"),
9058 last_insn
.name
, i
.tm
.name
);
9063 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9066 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9067 enum mf_jcc_kind
*mf_jcc_p
)
9071 /* NB: Don't work with COND_JUMP86 without i386. */
9072 if (!align_branch_power
9073 || now_seg
== absolute_section
9074 || !cpu_arch_flags
.bitfield
.cpui386
)
9079 /* Check for jcc and direct jmp. */
9080 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9082 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9084 *branch_p
= align_branch_jmp
;
9085 add_padding
= align_branch
& align_branch_jmp_bit
;
9089 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9090 igore the lowest bit. */
9091 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9092 *branch_p
= align_branch_jcc
;
9093 if ((align_branch
& align_branch_jcc_bit
))
9097 else if (is_any_vex_encoding (&i
.tm
))
9099 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9102 *branch_p
= align_branch_ret
;
9103 if ((align_branch
& align_branch_ret_bit
))
9108 /* Check for indirect jmp, direct and indirect calls. */
9109 if (i
.tm
.base_opcode
== 0xe8)
9112 *branch_p
= align_branch_call
;
9113 if ((align_branch
& align_branch_call_bit
))
9116 else if (i
.tm
.base_opcode
== 0xff
9117 && (i
.tm
.extension_opcode
== 2
9118 || i
.tm
.extension_opcode
== 4))
9120 /* Indirect call and jmp. */
9121 *branch_p
= align_branch_indirect
;
9122 if ((align_branch
& align_branch_indirect_bit
))
9129 && (i
.op
[0].disps
->X_op
== O_symbol
9130 || (i
.op
[0].disps
->X_op
== O_subtract
9131 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9133 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9134 /* No padding to call to global or undefined tls_get_addr. */
9135 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9136 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9142 && last_insn
.kind
!= last_insn_other
9143 && last_insn
.seg
== now_seg
)
9146 as_warn_where (last_insn
.file
, last_insn
.line
,
9147 _("`%s` skips -malign-branch-boundary on `%s`"),
9148 last_insn
.name
, i
.tm
.name
);
9158 fragS
*insn_start_frag
;
9159 offsetT insn_start_off
;
9160 fragS
*fragP
= NULL
;
9161 enum align_branch_kind branch
= align_branch_none
;
9162 /* The initializer is arbitrary just to avoid uninitialized error.
9163 it's actually either assigned in add_branch_padding_frag_p
9164 or never be used. */
9165 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9168 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9170 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9171 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9172 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9173 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9174 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9175 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9176 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9177 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9178 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9179 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9180 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9181 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9182 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9183 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9184 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9186 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9187 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9188 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9189 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9190 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9191 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9192 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9193 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9194 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9195 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9196 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9197 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9198 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9199 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9200 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9201 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9202 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9203 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9204 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9205 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9206 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9207 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9208 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9209 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9210 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9211 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9212 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9213 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9214 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9215 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9216 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9217 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9218 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9219 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9221 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9222 || i
.tm
.cpu_flags
.bitfield
.cpu287
9223 || i
.tm
.cpu_flags
.bitfield
.cpu387
9224 || i
.tm
.cpu_flags
.bitfield
.cpu687
9225 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9226 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9227 if ((i
.xstate
& xstate_mmx
)
9228 || i
.tm
.base_opcode
== 0xf77 /* emms */
9229 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9230 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9231 if ((i
.xstate
& xstate_xmm
)
9232 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9233 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9234 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9235 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9236 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9237 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9238 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9239 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9240 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9241 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9242 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9243 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9244 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9245 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9246 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9248 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9249 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9250 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9254 /* Tie dwarf2 debug info to the address at the start of the insn.
9255 We can't do this after the insn has been output as the current
9256 frag may have been closed off. eg. by frag_var. */
9257 dwarf2_emit_insn (0);
9259 insn_start_frag
= frag_now
;
9260 insn_start_off
= frag_now_fix ();
9262 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9265 /* Branch can be 8 bytes. Leave some room for prefixes. */
9266 unsigned int max_branch_padding_size
= 14;
9268 /* Align section to boundary. */
9269 record_alignment (now_seg
, align_branch_power
);
9271 /* Make room for padding. */
9272 frag_grow (max_branch_padding_size
);
9274 /* Start of the padding. */
9279 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9280 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9283 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9284 fragP
->tc_frag_data
.branch_type
= branch
;
9285 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9289 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9291 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9292 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9294 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9295 output_interseg_jump ();
9298 /* Output normal instructions here. */
9302 unsigned int prefix
;
9303 enum mf_cmp_kind mf_cmp
;
9306 && (i
.tm
.base_opcode
== 0xfaee8
9307 || i
.tm
.base_opcode
== 0xfaef0
9308 || i
.tm
.base_opcode
== 0xfaef8))
9310 /* Encode lfence, mfence, and sfence as
9311 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9312 if (now_seg
!= absolute_section
)
9314 offsetT val
= 0x240483f0ULL
;
9317 md_number_to_chars (p
, val
, 5);
9320 abs_section_offset
+= 5;
9324 /* Some processors fail on LOCK prefix. This options makes
9325 assembler ignore LOCK prefix and serves as a workaround. */
9326 if (omit_lock_prefix
)
9328 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9330 i
.prefix
[LOCK_PREFIX
] = 0;
9334 /* Skip if this is a branch. */
9336 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9338 /* Make room for padding. */
9339 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9344 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9345 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9348 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9349 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9350 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9352 else if (add_branch_prefix_frag_p ())
9354 unsigned int max_prefix_size
= align_branch_prefix_size
;
9356 /* Make room for padding. */
9357 frag_grow (max_prefix_size
);
9362 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9363 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9366 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9369 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9370 don't need the explicit prefix. */
9371 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9373 switch (i
.tm
.opcode_length
)
9376 if (i
.tm
.base_opcode
& 0xff000000)
9378 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9379 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9380 || prefix
!= REPE_PREFIX_OPCODE
9381 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9382 add_prefix (prefix
);
9386 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9388 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9389 add_prefix (prefix
);
9395 /* Check for pseudo prefixes. */
9396 as_bad_where (insn_start_frag
->fr_file
,
9397 insn_start_frag
->fr_line
,
9398 _("pseudo prefix without instruction"));
9404 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9405 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9406 R_X86_64_GOTTPOFF relocation so that linker can safely
9407 perform IE->LE optimization. A dummy REX_OPCODE prefix
9408 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9409 relocation for GDesc -> IE/LE optimization. */
9410 if (x86_elf_abi
== X86_64_X32_ABI
9412 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9413 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9414 && i
.prefix
[REX_PREFIX
] == 0)
9415 add_prefix (REX_OPCODE
);
9418 /* The prefix bytes. */
9419 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9421 frag_opcode_byte (*q
);
9425 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9431 frag_opcode_byte (*q
);
9434 /* There should be no other prefixes for instructions
9439 /* For EVEX instructions i.vrex should become 0 after
9440 build_evex_prefix. For VEX instructions upper 16 registers
9441 aren't available, so VREX should be 0. */
9444 /* Now the VEX prefix. */
9445 if (now_seg
!= absolute_section
)
9447 p
= frag_more (i
.vex
.length
);
9448 for (j
= 0; j
< i
.vex
.length
; j
++)
9449 p
[j
] = i
.vex
.bytes
[j
];
9452 abs_section_offset
+= i
.vex
.length
;
9455 /* Now the opcode; be careful about word order here! */
9456 if (now_seg
== absolute_section
)
9457 abs_section_offset
+= i
.tm
.opcode_length
;
9458 else if (i
.tm
.opcode_length
== 1)
9460 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9464 switch (i
.tm
.opcode_length
)
9468 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9469 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9473 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9483 /* Put out high byte first: can't use md_number_to_chars! */
9484 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9485 *p
= i
.tm
.base_opcode
& 0xff;
9488 /* Now the modrm byte and sib byte (if present). */
9489 if (i
.tm
.opcode_modifier
.modrm
)
9491 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9493 | (i
.rm
.mode
<< 6));
9494 /* If i.rm.regmem == ESP (4)
9495 && i.rm.mode != (Register mode)
9497 ==> need second modrm byte. */
9498 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9500 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9501 frag_opcode_byte ((i
.sib
.base
<< 0)
9502 | (i
.sib
.index
<< 3)
9503 | (i
.sib
.scale
<< 6));
9506 if (i
.disp_operands
)
9507 output_disp (insn_start_frag
, insn_start_off
);
9510 output_imm (insn_start_frag
, insn_start_off
);
9513 * frag_now_fix () returning plain abs_section_offset when we're in the
9514 * absolute section, and abs_section_offset not getting updated as data
9515 * gets added to the frag breaks the logic below.
9517 if (now_seg
!= absolute_section
)
9519 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9521 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9525 /* NB: Don't add prefix with GOTPC relocation since
9526 output_disp() above depends on the fixed encoding
9527 length. Can't add prefix with TLS relocation since
9528 it breaks TLS linker optimization. */
9529 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9530 /* Prefix count on the current instruction. */
9531 unsigned int count
= i
.vex
.length
;
9533 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9534 /* REX byte is encoded in VEX/EVEX prefix. */
9535 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9538 /* Count prefixes for extended opcode maps. */
9540 switch (i
.tm
.opcode_length
)
9543 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9546 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9558 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9567 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9570 /* Set the maximum prefix size in BRANCH_PREFIX
9572 if (fragP
->tc_frag_data
.max_bytes
> max
)
9573 fragP
->tc_frag_data
.max_bytes
= max
;
9574 if (fragP
->tc_frag_data
.max_bytes
> count
)
9575 fragP
->tc_frag_data
.max_bytes
-= count
;
9577 fragP
->tc_frag_data
.max_bytes
= 0;
9581 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9583 unsigned int max_prefix_size
;
9584 if (align_branch_prefix_size
> max
)
9585 max_prefix_size
= max
;
9587 max_prefix_size
= align_branch_prefix_size
;
9588 if (max_prefix_size
> count
)
9589 fragP
->tc_frag_data
.max_prefix_length
9590 = max_prefix_size
- count
;
9593 /* Use existing segment prefix if possible. Use CS
9594 segment prefix in 64-bit mode. In 32-bit mode, use SS
9595 segment prefix with ESP/EBP base register and use DS
9596 segment prefix without ESP/EBP base register. */
9597 if (i
.prefix
[SEG_PREFIX
])
9598 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9599 else if (flag_code
== CODE_64BIT
)
9600 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9602 && (i
.base_reg
->reg_num
== 4
9603 || i
.base_reg
->reg_num
== 5))
9604 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9606 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9611 /* NB: Don't work with COND_JUMP86 without i386. */
9612 if (align_branch_power
9613 && now_seg
!= absolute_section
9614 && cpu_arch_flags
.bitfield
.cpui386
)
9616 /* Terminate each frag so that we can add prefix and check for
9618 frag_wane (frag_now
);
9625 pi ("" /*line*/, &i
);
9627 #endif /* DEBUG386 */
9630 /* Return the size of the displacement operand N. */
9633 disp_size (unsigned int n
)
9637 if (i
.types
[n
].bitfield
.disp64
)
9639 else if (i
.types
[n
].bitfield
.disp8
)
9641 else if (i
.types
[n
].bitfield
.disp16
)
9646 /* Return the size of the immediate operand N. */
9649 imm_size (unsigned int n
)
9652 if (i
.types
[n
].bitfield
.imm64
)
9654 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9656 else if (i
.types
[n
].bitfield
.imm16
)
9662 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9667 for (n
= 0; n
< i
.operands
; n
++)
9669 if (operand_type_check (i
.types
[n
], disp
))
9671 int size
= disp_size (n
);
9673 if (now_seg
== absolute_section
)
9674 abs_section_offset
+= size
;
9675 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9677 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9679 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9681 p
= frag_more (size
);
9682 md_number_to_chars (p
, val
, size
);
9686 enum bfd_reloc_code_real reloc_type
;
9687 int sign
= i
.types
[n
].bitfield
.disp32s
;
9688 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9691 /* We can't have 8 bit displacement here. */
9692 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9694 /* The PC relative address is computed relative
9695 to the instruction boundary, so in case immediate
9696 fields follows, we need to adjust the value. */
9697 if (pcrel
&& i
.imm_operands
)
9702 for (n1
= 0; n1
< i
.operands
; n1
++)
9703 if (operand_type_check (i
.types
[n1
], imm
))
9705 /* Only one immediate is allowed for PC
9706 relative address. */
9707 gas_assert (sz
== 0);
9709 i
.op
[n
].disps
->X_add_number
-= sz
;
9711 /* We should find the immediate. */
9712 gas_assert (sz
!= 0);
9715 p
= frag_more (size
);
9716 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9718 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9719 && (((reloc_type
== BFD_RELOC_32
9720 || reloc_type
== BFD_RELOC_X86_64_32S
9721 || (reloc_type
== BFD_RELOC_64
9723 && (i
.op
[n
].disps
->X_op
== O_symbol
9724 || (i
.op
[n
].disps
->X_op
== O_add
9725 && ((symbol_get_value_expression
9726 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9728 || reloc_type
== BFD_RELOC_32_PCREL
))
9732 reloc_type
= BFD_RELOC_386_GOTPC
;
9733 i
.has_gotpc_tls_reloc
= TRUE
;
9734 i
.op
[n
].imms
->X_add_number
+=
9735 encoding_length (insn_start_frag
, insn_start_off
, p
);
9737 else if (reloc_type
== BFD_RELOC_64
)
9738 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9740 /* Don't do the adjustment for x86-64, as there
9741 the pcrel addressing is relative to the _next_
9742 insn, and that is taken care of in other code. */
9743 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9745 else if (align_branch_power
)
9749 case BFD_RELOC_386_TLS_GD
:
9750 case BFD_RELOC_386_TLS_LDM
:
9751 case BFD_RELOC_386_TLS_IE
:
9752 case BFD_RELOC_386_TLS_IE_32
:
9753 case BFD_RELOC_386_TLS_GOTIE
:
9754 case BFD_RELOC_386_TLS_GOTDESC
:
9755 case BFD_RELOC_386_TLS_DESC_CALL
:
9756 case BFD_RELOC_X86_64_TLSGD
:
9757 case BFD_RELOC_X86_64_TLSLD
:
9758 case BFD_RELOC_X86_64_GOTTPOFF
:
9759 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9760 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9761 i
.has_gotpc_tls_reloc
= TRUE
;
9766 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9767 size
, i
.op
[n
].disps
, pcrel
,
9769 /* Check for "call/jmp *mem", "mov mem, %reg",
9770 "test %reg, mem" and "binop mem, %reg" where binop
9771 is one of adc, add, and, cmp, or, sbb, sub, xor
9772 instructions without data prefix. Always generate
9773 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9774 if (i
.prefix
[DATA_PREFIX
] == 0
9775 && (generate_relax_relocations
9778 && i
.rm
.regmem
== 5))
9780 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9781 && !is_any_vex_encoding(&i
.tm
)
9782 && ((i
.operands
== 1
9783 && i
.tm
.base_opcode
== 0xff
9784 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9786 && (i
.tm
.base_opcode
== 0x8b
9787 || i
.tm
.base_opcode
== 0x85
9788 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9792 fixP
->fx_tcbit
= i
.rex
!= 0;
9794 && (i
.base_reg
->reg_num
== RegIP
))
9795 fixP
->fx_tcbit2
= 1;
9798 fixP
->fx_tcbit2
= 1;
9806 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9811 for (n
= 0; n
< i
.operands
; n
++)
9813 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9814 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9817 if (operand_type_check (i
.types
[n
], imm
))
9819 int size
= imm_size (n
);
9821 if (now_seg
== absolute_section
)
9822 abs_section_offset
+= size
;
9823 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9827 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9829 p
= frag_more (size
);
9830 md_number_to_chars (p
, val
, size
);
9834 /* Not absolute_section.
9835 Need a 32-bit fixup (don't support 8bit
9836 non-absolute imms). Try to support other
9838 enum bfd_reloc_code_real reloc_type
;
9841 if (i
.types
[n
].bitfield
.imm32s
9842 && (i
.suffix
== QWORD_MNEM_SUFFIX
9843 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9848 p
= frag_more (size
);
9849 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9851 /* This is tough to explain. We end up with this one if we
9852 * have operands that look like
9853 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9854 * obtain the absolute address of the GOT, and it is strongly
9855 * preferable from a performance point of view to avoid using
9856 * a runtime relocation for this. The actual sequence of
9857 * instructions often look something like:
9862 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9864 * The call and pop essentially return the absolute address
9865 * of the label .L66 and store it in %ebx. The linker itself
9866 * will ultimately change the first operand of the addl so
9867 * that %ebx points to the GOT, but to keep things simple, the
9868 * .o file must have this operand set so that it generates not
9869 * the absolute address of .L66, but the absolute address of
9870 * itself. This allows the linker itself simply treat a GOTPC
9871 * relocation as asking for a pcrel offset to the GOT to be
9872 * added in, and the addend of the relocation is stored in the
9873 * operand field for the instruction itself.
9875 * Our job here is to fix the operand so that it would add
9876 * the correct offset so that %ebx would point to itself. The
9877 * thing that is tricky is that .-.L66 will point to the
9878 * beginning of the instruction, so we need to further modify
9879 * the operand so that it will point to itself. There are
9880 * other cases where you have something like:
9882 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9884 * and here no correction would be required. Internally in
9885 * the assembler we treat operands of this form as not being
9886 * pcrel since the '.' is explicitly mentioned, and I wonder
9887 * whether it would simplify matters to do it this way. Who
9888 * knows. In earlier versions of the PIC patches, the
9889 * pcrel_adjust field was used to store the correction, but
9890 * since the expression is not pcrel, I felt it would be
9891 * confusing to do it this way. */
9893 if ((reloc_type
== BFD_RELOC_32
9894 || reloc_type
== BFD_RELOC_X86_64_32S
9895 || reloc_type
== BFD_RELOC_64
)
9897 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9898 && (i
.op
[n
].imms
->X_op
== O_symbol
9899 || (i
.op
[n
].imms
->X_op
== O_add
9900 && ((symbol_get_value_expression
9901 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9905 reloc_type
= BFD_RELOC_386_GOTPC
;
9907 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9909 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9910 i
.has_gotpc_tls_reloc
= TRUE
;
9911 i
.op
[n
].imms
->X_add_number
+=
9912 encoding_length (insn_start_frag
, insn_start_off
, p
);
9914 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9915 i
.op
[n
].imms
, 0, reloc_type
);
9921 /* x86_cons_fix_new is called via the expression parsing code when a
9922 reloc is needed. We use this hook to get the correct .got reloc. */
9923 static int cons_sign
= -1;
9926 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9927 expressionS
*exp
, bfd_reloc_code_real_type r
)
9929 r
= reloc (len
, 0, cons_sign
, r
);
9932 if (exp
->X_op
== O_secrel
)
9934 exp
->X_op
= O_symbol
;
9935 r
= BFD_RELOC_32_SECREL
;
9939 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9942 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9943 purpose of the `.dc.a' internal pseudo-op. */
9946 x86_address_bytes (void)
9948 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9950 return stdoutput
->arch_info
->bits_per_address
/ 8;
9953 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9955 # define lex_got(reloc, adjust, types) NULL
9957 /* Parse operands of the form
9958 <symbol>@GOTOFF+<nnn>
9959 and similar .plt or .got references.
9961 If we find one, set up the correct relocation in RELOC and copy the
9962 input string, minus the `@GOTOFF' into a malloc'd buffer for
9963 parsing by the calling routine. Return this buffer, and if ADJUST
9964 is non-null set it to the length of the string we removed from the
9965 input line. Otherwise return NULL. */
9967 lex_got (enum bfd_reloc_code_real
*rel
,
9969 i386_operand_type
*types
)
9971 /* Some of the relocations depend on the size of what field is to
9972 be relocated. But in our callers i386_immediate and i386_displacement
9973 we don't yet know the operand size (this will be set by insn
9974 matching). Hence we record the word32 relocation here,
9975 and adjust the reloc according to the real size in reloc(). */
9976 static const struct {
9979 const enum bfd_reloc_code_real rel
[2];
9980 const i386_operand_type types64
;
9982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9983 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9985 OPERAND_TYPE_IMM32_64
},
9987 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9988 BFD_RELOC_X86_64_PLTOFF64
},
9989 OPERAND_TYPE_IMM64
},
9990 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9991 BFD_RELOC_X86_64_PLT32
},
9992 OPERAND_TYPE_IMM32_32S_DISP32
},
9993 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9994 BFD_RELOC_X86_64_GOTPLT64
},
9995 OPERAND_TYPE_IMM64_DISP64
},
9996 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9997 BFD_RELOC_X86_64_GOTOFF64
},
9998 OPERAND_TYPE_IMM64_DISP64
},
9999 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10000 BFD_RELOC_X86_64_GOTPCREL
},
10001 OPERAND_TYPE_IMM32_32S_DISP32
},
10002 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10003 BFD_RELOC_X86_64_TLSGD
},
10004 OPERAND_TYPE_IMM32_32S_DISP32
},
10005 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10006 _dummy_first_bfd_reloc_code_real
},
10007 OPERAND_TYPE_NONE
},
10008 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10009 BFD_RELOC_X86_64_TLSLD
},
10010 OPERAND_TYPE_IMM32_32S_DISP32
},
10011 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10012 BFD_RELOC_X86_64_GOTTPOFF
},
10013 OPERAND_TYPE_IMM32_32S_DISP32
},
10014 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10015 BFD_RELOC_X86_64_TPOFF32
},
10016 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10017 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10018 _dummy_first_bfd_reloc_code_real
},
10019 OPERAND_TYPE_NONE
},
10020 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10021 BFD_RELOC_X86_64_DTPOFF32
},
10022 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10023 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10024 _dummy_first_bfd_reloc_code_real
},
10025 OPERAND_TYPE_NONE
},
10026 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10027 _dummy_first_bfd_reloc_code_real
},
10028 OPERAND_TYPE_NONE
},
10029 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10030 BFD_RELOC_X86_64_GOT32
},
10031 OPERAND_TYPE_IMM32_32S_64_DISP32
},
10032 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10033 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10034 OPERAND_TYPE_IMM32_32S_DISP32
},
10035 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10036 BFD_RELOC_X86_64_TLSDESC_CALL
},
10037 OPERAND_TYPE_IMM32_32S_DISP32
},
10042 #if defined (OBJ_MAYBE_ELF)
10047 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10048 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10051 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10053 int len
= gotrel
[j
].len
;
10054 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10056 if (gotrel
[j
].rel
[object_64bit
] != 0)
10059 char *tmpbuf
, *past_reloc
;
10061 *rel
= gotrel
[j
].rel
[object_64bit
];
10065 if (flag_code
!= CODE_64BIT
)
10067 types
->bitfield
.imm32
= 1;
10068 types
->bitfield
.disp32
= 1;
10071 *types
= gotrel
[j
].types64
;
10074 if (j
!= 0 && GOT_symbol
== NULL
)
10075 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10077 /* The length of the first part of our input line. */
10078 first
= cp
- input_line_pointer
;
10080 /* The second part goes from after the reloc token until
10081 (and including) an end_of_line char or comma. */
10082 past_reloc
= cp
+ 1 + len
;
10084 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10086 second
= cp
+ 1 - past_reloc
;
10088 /* Allocate and copy string. The trailing NUL shouldn't
10089 be necessary, but be safe. */
10090 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10091 memcpy (tmpbuf
, input_line_pointer
, first
);
10092 if (second
!= 0 && *past_reloc
!= ' ')
10093 /* Replace the relocation token with ' ', so that
10094 errors like foo@GOTOFF1 will be detected. */
10095 tmpbuf
[first
++] = ' ';
10097 /* Increment length by 1 if the relocation token is
10102 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10103 tmpbuf
[first
+ second
] = '\0';
10107 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10108 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10113 /* Might be a symbol version string. Don't as_bad here. */
10122 /* Parse operands of the form
10123 <symbol>@SECREL32+<nnn>
10125 If we find one, set up the correct relocation in RELOC and copy the
10126 input string, minus the `@SECREL32' into a malloc'd buffer for
10127 parsing by the calling routine. Return this buffer, and if ADJUST
10128 is non-null set it to the length of the string we removed from the
10129 input line. Otherwise return NULL.
10131 This function is copied from the ELF version above adjusted for PE targets. */
10134 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10135 int *adjust ATTRIBUTE_UNUSED
,
10136 i386_operand_type
*types
)
10138 static const struct
10142 const enum bfd_reloc_code_real rel
[2];
10143 const i386_operand_type types64
;
10147 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10148 BFD_RELOC_32_SECREL
},
10149 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10155 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10156 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10159 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10161 int len
= gotrel
[j
].len
;
10163 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10165 if (gotrel
[j
].rel
[object_64bit
] != 0)
10168 char *tmpbuf
, *past_reloc
;
10170 *rel
= gotrel
[j
].rel
[object_64bit
];
10176 if (flag_code
!= CODE_64BIT
)
10178 types
->bitfield
.imm32
= 1;
10179 types
->bitfield
.disp32
= 1;
10182 *types
= gotrel
[j
].types64
;
10185 /* The length of the first part of our input line. */
10186 first
= cp
- input_line_pointer
;
10188 /* The second part goes from after the reloc token until
10189 (and including) an end_of_line char or comma. */
10190 past_reloc
= cp
+ 1 + len
;
10192 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10194 second
= cp
+ 1 - past_reloc
;
10196 /* Allocate and copy string. The trailing NUL shouldn't
10197 be necessary, but be safe. */
10198 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10199 memcpy (tmpbuf
, input_line_pointer
, first
);
10200 if (second
!= 0 && *past_reloc
!= ' ')
10201 /* Replace the relocation token with ' ', so that
10202 errors like foo@SECLREL321 will be detected. */
10203 tmpbuf
[first
++] = ' ';
10204 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10205 tmpbuf
[first
+ second
] = '\0';
10209 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10210 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10215 /* Might be a symbol version string. Don't as_bad here. */
10221 bfd_reloc_code_real_type
10222 x86_cons (expressionS
*exp
, int size
)
10224 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10226 intel_syntax
= -intel_syntax
;
10229 if (size
== 4 || (object_64bit
&& size
== 8))
10231 /* Handle @GOTOFF and the like in an expression. */
10233 char *gotfree_input_line
;
10236 save
= input_line_pointer
;
10237 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10238 if (gotfree_input_line
)
10239 input_line_pointer
= gotfree_input_line
;
10243 if (gotfree_input_line
)
10245 /* expression () has merrily parsed up to the end of line,
10246 or a comma - in the wrong buffer. Transfer how far
10247 input_line_pointer has moved to the right buffer. */
10248 input_line_pointer
= (save
10249 + (input_line_pointer
- gotfree_input_line
)
10251 free (gotfree_input_line
);
10252 if (exp
->X_op
== O_constant
10253 || exp
->X_op
== O_absent
10254 || exp
->X_op
== O_illegal
10255 || exp
->X_op
== O_register
10256 || exp
->X_op
== O_big
)
10258 char c
= *input_line_pointer
;
10259 *input_line_pointer
= 0;
10260 as_bad (_("missing or invalid expression `%s'"), save
);
10261 *input_line_pointer
= c
;
10263 else if ((got_reloc
== BFD_RELOC_386_PLT32
10264 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10265 && exp
->X_op
!= O_symbol
)
10267 char c
= *input_line_pointer
;
10268 *input_line_pointer
= 0;
10269 as_bad (_("invalid PLT expression `%s'"), save
);
10270 *input_line_pointer
= c
;
10277 intel_syntax
= -intel_syntax
;
10280 i386_intel_simplify (exp
);
10286 signed_cons (int size
)
10288 if (flag_code
== CODE_64BIT
)
10296 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10303 if (exp
.X_op
== O_symbol
)
10304 exp
.X_op
= O_secrel
;
10306 emit_expr (&exp
, 4);
10308 while (*input_line_pointer
++ == ',');
10310 input_line_pointer
--;
10311 demand_empty_rest_of_line ();
10315 /* Handle Vector operations. */
10318 check_VecOperations (char *op_string
, char *op_end
)
10320 const reg_entry
*mask
;
10325 && (op_end
== NULL
|| op_string
< op_end
))
10328 if (*op_string
== '{')
10332 /* Check broadcasts. */
10333 if (strncmp (op_string
, "1to", 3) == 0)
10338 goto duplicated_vec_op
;
10341 if (*op_string
== '8')
10343 else if (*op_string
== '4')
10345 else if (*op_string
== '2')
10347 else if (*op_string
== '1'
10348 && *(op_string
+1) == '6')
10355 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10360 broadcast_op
.type
= bcst_type
;
10361 broadcast_op
.operand
= this_operand
;
10362 broadcast_op
.bytes
= 0;
10363 i
.broadcast
= &broadcast_op
;
10365 /* Check masking operation. */
10366 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10368 if (mask
== &bad_reg
)
10371 /* k0 can't be used for write mask. */
10372 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10374 as_bad (_("`%s%s' can't be used for write mask"),
10375 register_prefix
, mask
->reg_name
);
10381 mask_op
.mask
= mask
;
10382 mask_op
.zeroing
= 0;
10383 mask_op
.operand
= this_operand
;
10389 goto duplicated_vec_op
;
10391 i
.mask
->mask
= mask
;
10393 /* Only "{z}" is allowed here. No need to check
10394 zeroing mask explicitly. */
10395 if (i
.mask
->operand
!= this_operand
)
10397 as_bad (_("invalid write mask `%s'"), saved
);
10402 op_string
= end_op
;
10404 /* Check zeroing-flag for masking operation. */
10405 else if (*op_string
== 'z')
10409 mask_op
.mask
= NULL
;
10410 mask_op
.zeroing
= 1;
10411 mask_op
.operand
= this_operand
;
10416 if (i
.mask
->zeroing
)
10419 as_bad (_("duplicated `%s'"), saved
);
10423 i
.mask
->zeroing
= 1;
10425 /* Only "{%k}" is allowed here. No need to check mask
10426 register explicitly. */
10427 if (i
.mask
->operand
!= this_operand
)
10429 as_bad (_("invalid zeroing-masking `%s'"),
10438 goto unknown_vec_op
;
10440 if (*op_string
!= '}')
10442 as_bad (_("missing `}' in `%s'"), saved
);
10447 /* Strip whitespace since the addition of pseudo prefixes
10448 changed how the scrubber treats '{'. */
10449 if (is_space_char (*op_string
))
10455 /* We don't know this one. */
10456 as_bad (_("unknown vector operation: `%s'"), saved
);
10460 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10462 as_bad (_("zeroing-masking only allowed with write mask"));
10470 i386_immediate (char *imm_start
)
10472 char *save_input_line_pointer
;
10473 char *gotfree_input_line
;
10476 i386_operand_type types
;
10478 operand_type_set (&types
, ~0);
10480 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10482 as_bad (_("at most %d immediate operands are allowed"),
10483 MAX_IMMEDIATE_OPERANDS
);
10487 exp
= &im_expressions
[i
.imm_operands
++];
10488 i
.op
[this_operand
].imms
= exp
;
10490 if (is_space_char (*imm_start
))
10493 save_input_line_pointer
= input_line_pointer
;
10494 input_line_pointer
= imm_start
;
10496 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10497 if (gotfree_input_line
)
10498 input_line_pointer
= gotfree_input_line
;
10500 exp_seg
= expression (exp
);
10502 SKIP_WHITESPACE ();
10504 /* Handle vector operations. */
10505 if (*input_line_pointer
== '{')
10507 input_line_pointer
= check_VecOperations (input_line_pointer
,
10509 if (input_line_pointer
== NULL
)
10513 if (*input_line_pointer
)
10514 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10516 input_line_pointer
= save_input_line_pointer
;
10517 if (gotfree_input_line
)
10519 free (gotfree_input_line
);
10521 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10522 exp
->X_op
= O_illegal
;
10525 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10529 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10530 i386_operand_type types
, const char *imm_start
)
10532 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10535 as_bad (_("missing or invalid immediate expression `%s'"),
10539 else if (exp
->X_op
== O_constant
)
10541 /* Size it properly later. */
10542 i
.types
[this_operand
].bitfield
.imm64
= 1;
10543 /* If not 64bit, sign extend val. */
10544 if (flag_code
!= CODE_64BIT
10545 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10547 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10549 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10550 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10551 && exp_seg
!= absolute_section
10552 && exp_seg
!= text_section
10553 && exp_seg
!= data_section
10554 && exp_seg
!= bss_section
10555 && exp_seg
!= undefined_section
10556 && !bfd_is_com_section (exp_seg
))
10558 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10562 else if (!intel_syntax
&& exp_seg
== reg_section
)
10565 as_bad (_("illegal immediate register operand %s"), imm_start
);
10570 /* This is an address. The size of the address will be
10571 determined later, depending on destination register,
10572 suffix, or the default for the section. */
10573 i
.types
[this_operand
].bitfield
.imm8
= 1;
10574 i
.types
[this_operand
].bitfield
.imm16
= 1;
10575 i
.types
[this_operand
].bitfield
.imm32
= 1;
10576 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10577 i
.types
[this_operand
].bitfield
.imm64
= 1;
10578 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10586 i386_scale (char *scale
)
10589 char *save
= input_line_pointer
;
10591 input_line_pointer
= scale
;
10592 val
= get_absolute_expression ();
10597 i
.log2_scale_factor
= 0;
10600 i
.log2_scale_factor
= 1;
10603 i
.log2_scale_factor
= 2;
10606 i
.log2_scale_factor
= 3;
10610 char sep
= *input_line_pointer
;
10612 *input_line_pointer
= '\0';
10613 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10615 *input_line_pointer
= sep
;
10616 input_line_pointer
= save
;
10620 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10622 as_warn (_("scale factor of %d without an index register"),
10623 1 << i
.log2_scale_factor
);
10624 i
.log2_scale_factor
= 0;
10626 scale
= input_line_pointer
;
10627 input_line_pointer
= save
;
10632 i386_displacement (char *disp_start
, char *disp_end
)
10636 char *save_input_line_pointer
;
10637 char *gotfree_input_line
;
10639 i386_operand_type bigdisp
, types
= anydisp
;
10642 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10644 as_bad (_("at most %d displacement operands are allowed"),
10645 MAX_MEMORY_OPERANDS
);
10649 operand_type_set (&bigdisp
, 0);
10651 || i
.types
[this_operand
].bitfield
.baseindex
10652 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10653 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10655 i386_addressing_mode ();
10656 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10657 if (flag_code
== CODE_64BIT
)
10661 bigdisp
.bitfield
.disp32s
= 1;
10662 bigdisp
.bitfield
.disp64
= 1;
10665 bigdisp
.bitfield
.disp32
= 1;
10667 else if ((flag_code
== CODE_16BIT
) ^ override
)
10668 bigdisp
.bitfield
.disp16
= 1;
10670 bigdisp
.bitfield
.disp32
= 1;
10674 /* For PC-relative branches, the width of the displacement may be
10675 dependent upon data size, but is never dependent upon address size.
10676 Also make sure to not unintentionally match against a non-PC-relative
10677 branch template. */
10678 static templates aux_templates
;
10679 const insn_template
*t
= current_templates
->start
;
10680 bfd_boolean has_intel64
= FALSE
;
10682 aux_templates
.start
= t
;
10683 while (++t
< current_templates
->end
)
10685 if (t
->opcode_modifier
.jump
10686 != current_templates
->start
->opcode_modifier
.jump
)
10688 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10689 has_intel64
= TRUE
;
10691 if (t
< current_templates
->end
)
10693 aux_templates
.end
= t
;
10694 current_templates
= &aux_templates
;
10697 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10698 if (flag_code
== CODE_64BIT
)
10700 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10701 && (!intel64
|| !has_intel64
))
10702 bigdisp
.bitfield
.disp16
= 1;
10704 bigdisp
.bitfield
.disp32s
= 1;
10709 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10711 : LONG_MNEM_SUFFIX
));
10712 bigdisp
.bitfield
.disp32
= 1;
10713 if ((flag_code
== CODE_16BIT
) ^ override
)
10715 bigdisp
.bitfield
.disp32
= 0;
10716 bigdisp
.bitfield
.disp16
= 1;
10720 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10723 exp
= &disp_expressions
[i
.disp_operands
];
10724 i
.op
[this_operand
].disps
= exp
;
10726 save_input_line_pointer
= input_line_pointer
;
10727 input_line_pointer
= disp_start
;
10728 END_STRING_AND_SAVE (disp_end
);
10730 #ifndef GCC_ASM_O_HACK
10731 #define GCC_ASM_O_HACK 0
10734 END_STRING_AND_SAVE (disp_end
+ 1);
10735 if (i
.types
[this_operand
].bitfield
.baseIndex
10736 && displacement_string_end
[-1] == '+')
10738 /* This hack is to avoid a warning when using the "o"
10739 constraint within gcc asm statements.
10742 #define _set_tssldt_desc(n,addr,limit,type) \
10743 __asm__ __volatile__ ( \
10744 "movw %w2,%0\n\t" \
10745 "movw %w1,2+%0\n\t" \
10746 "rorl $16,%1\n\t" \
10747 "movb %b1,4+%0\n\t" \
10748 "movb %4,5+%0\n\t" \
10749 "movb $0,6+%0\n\t" \
10750 "movb %h1,7+%0\n\t" \
10752 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10754 This works great except that the output assembler ends
10755 up looking a bit weird if it turns out that there is
10756 no offset. You end up producing code that looks like:
10769 So here we provide the missing zero. */
10771 *displacement_string_end
= '0';
10774 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10775 if (gotfree_input_line
)
10776 input_line_pointer
= gotfree_input_line
;
10778 exp_seg
= expression (exp
);
10780 SKIP_WHITESPACE ();
10781 if (*input_line_pointer
)
10782 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10784 RESTORE_END_STRING (disp_end
+ 1);
10786 input_line_pointer
= save_input_line_pointer
;
10787 if (gotfree_input_line
)
10789 free (gotfree_input_line
);
10791 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10792 exp
->X_op
= O_illegal
;
10795 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10797 RESTORE_END_STRING (disp_end
);
10803 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10804 i386_operand_type types
, const char *disp_start
)
10806 i386_operand_type bigdisp
;
10809 /* We do this to make sure that the section symbol is in
10810 the symbol table. We will ultimately change the relocation
10811 to be relative to the beginning of the section. */
10812 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10813 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10814 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10816 if (exp
->X_op
!= O_symbol
)
10819 if (S_IS_LOCAL (exp
->X_add_symbol
)
10820 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10821 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10822 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10823 exp
->X_op
= O_subtract
;
10824 exp
->X_op_symbol
= GOT_symbol
;
10825 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10826 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10827 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10828 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10830 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10833 else if (exp
->X_op
== O_absent
10834 || exp
->X_op
== O_illegal
10835 || exp
->X_op
== O_big
)
10838 as_bad (_("missing or invalid displacement expression `%s'"),
10843 else if (flag_code
== CODE_64BIT
10844 && !i
.prefix
[ADDR_PREFIX
]
10845 && exp
->X_op
== O_constant
)
10847 /* Since displacement is signed extended to 64bit, don't allow
10848 disp32 and turn off disp32s if they are out of range. */
10849 i
.types
[this_operand
].bitfield
.disp32
= 0;
10850 if (!fits_in_signed_long (exp
->X_add_number
))
10852 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10853 if (i
.types
[this_operand
].bitfield
.baseindex
)
10855 as_bad (_("0x%lx out range of signed 32bit displacement"),
10856 (long) exp
->X_add_number
);
10862 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10863 else if (exp
->X_op
!= O_constant
10864 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10865 && exp_seg
!= absolute_section
10866 && exp_seg
!= text_section
10867 && exp_seg
!= data_section
10868 && exp_seg
!= bss_section
10869 && exp_seg
!= undefined_section
10870 && !bfd_is_com_section (exp_seg
))
10872 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10877 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10878 /* Constants get taken care of by optimize_disp(). */
10879 && exp
->X_op
!= O_constant
)
10880 i
.types
[this_operand
].bitfield
.disp8
= 1;
10882 /* Check if this is a displacement only operand. */
10883 bigdisp
= i
.types
[this_operand
];
10884 bigdisp
.bitfield
.disp8
= 0;
10885 bigdisp
.bitfield
.disp16
= 0;
10886 bigdisp
.bitfield
.disp32
= 0;
10887 bigdisp
.bitfield
.disp32s
= 0;
10888 bigdisp
.bitfield
.disp64
= 0;
10889 if (operand_type_all_zero (&bigdisp
))
10890 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10896 /* Return the active addressing mode, taking address override and
10897 registers forming the address into consideration. Update the
10898 address override prefix if necessary. */
10900 static enum flag_code
10901 i386_addressing_mode (void)
10903 enum flag_code addr_mode
;
10905 if (i
.prefix
[ADDR_PREFIX
])
10906 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10907 else if (flag_code
== CODE_16BIT
10908 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10909 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10910 from md_assemble() by "is not a valid base/index expression"
10911 when there is a base and/or index. */
10912 && !i
.types
[this_operand
].bitfield
.baseindex
)
10914 /* MPX insn memory operands with neither base nor index must be forced
10915 to use 32-bit addressing in 16-bit mode. */
10916 addr_mode
= CODE_32BIT
;
10917 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10919 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10920 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10924 addr_mode
= flag_code
;
10926 #if INFER_ADDR_PREFIX
10927 if (i
.mem_operands
== 0)
10929 /* Infer address prefix from the first memory operand. */
10930 const reg_entry
*addr_reg
= i
.base_reg
;
10932 if (addr_reg
== NULL
)
10933 addr_reg
= i
.index_reg
;
10937 if (addr_reg
->reg_type
.bitfield
.dword
)
10938 addr_mode
= CODE_32BIT
;
10939 else if (flag_code
!= CODE_64BIT
10940 && addr_reg
->reg_type
.bitfield
.word
)
10941 addr_mode
= CODE_16BIT
;
10943 if (addr_mode
!= flag_code
)
10945 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10947 /* Change the size of any displacement too. At most one
10948 of Disp16 or Disp32 is set.
10949 FIXME. There doesn't seem to be any real need for
10950 separate Disp16 and Disp32 flags. The same goes for
10951 Imm16 and Imm32. Removing them would probably clean
10952 up the code quite a lot. */
10953 if (flag_code
!= CODE_64BIT
10954 && (i
.types
[this_operand
].bitfield
.disp16
10955 || i
.types
[this_operand
].bitfield
.disp32
))
10956 i
.types
[this_operand
]
10957 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10967 /* Make sure the memory operand we've been dealt is valid.
10968 Return 1 on success, 0 on a failure. */
10971 i386_index_check (const char *operand_string
)
10973 const char *kind
= "base/index";
10974 enum flag_code addr_mode
= i386_addressing_mode ();
10976 if (current_templates
->start
->opcode_modifier
.isstring
10977 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10978 && (current_templates
->end
[-1].opcode_modifier
.isstring
10979 || i
.mem_operands
))
10981 /* Memory operands of string insns are special in that they only allow
10982 a single register (rDI, rSI, or rBX) as their memory address. */
10983 const reg_entry
*expected_reg
;
10984 static const char *di_si
[][2] =
10990 static const char *bx
[] = { "ebx", "bx", "rbx" };
10992 kind
= "string address";
10994 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10996 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10997 - IS_STRING_ES_OP0
;
11000 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11001 || ((!i
.mem_operands
!= !intel_syntax
)
11002 && current_templates
->end
[-1].operand_types
[1]
11003 .bitfield
.baseindex
))
11006 = (const reg_entry
*) str_hash_find (reg_hash
,
11007 di_si
[addr_mode
][op
== es_op
]);
11011 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11013 if (i
.base_reg
!= expected_reg
11015 || operand_type_check (i
.types
[this_operand
], disp
))
11017 /* The second memory operand must have the same size as
11021 && !((addr_mode
== CODE_64BIT
11022 && i
.base_reg
->reg_type
.bitfield
.qword
)
11023 || (addr_mode
== CODE_32BIT
11024 ? i
.base_reg
->reg_type
.bitfield
.dword
11025 : i
.base_reg
->reg_type
.bitfield
.word
)))
11028 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11030 intel_syntax
? '[' : '(',
11032 expected_reg
->reg_name
,
11033 intel_syntax
? ']' : ')');
11040 as_bad (_("`%s' is not a valid %s expression"),
11041 operand_string
, kind
);
11046 if (addr_mode
!= CODE_16BIT
)
11048 /* 32-bit/64-bit checks. */
11049 if (i
.disp_encoding
== disp_encoding_16bit
)
11052 as_bad (_("invalid `%s' prefix"),
11053 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11058 && ((addr_mode
== CODE_64BIT
11059 ? !i
.base_reg
->reg_type
.bitfield
.qword
11060 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11061 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11062 || i
.base_reg
->reg_num
== RegIZ
))
11064 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11065 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11066 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11067 && ((addr_mode
== CODE_64BIT
11068 ? !i
.index_reg
->reg_type
.bitfield
.qword
11069 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11070 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11073 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11074 if (current_templates
->start
->base_opcode
== 0xf30f1b
11075 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11076 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11078 /* They cannot use RIP-relative addressing. */
11079 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11081 as_bad (_("`%s' cannot be used here"), operand_string
);
11085 /* bndldx and bndstx ignore their scale factor. */
11086 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11087 && i
.log2_scale_factor
)
11088 as_warn (_("register scaling is being ignored here"));
11093 /* 16-bit checks. */
11094 if (i
.disp_encoding
== disp_encoding_32bit
)
11098 && (!i
.base_reg
->reg_type
.bitfield
.word
11099 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11101 && (!i
.index_reg
->reg_type
.bitfield
.word
11102 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11104 && i
.base_reg
->reg_num
< 6
11105 && i
.index_reg
->reg_num
>= 6
11106 && i
.log2_scale_factor
== 0))))
11113 /* Handle vector immediates. */
11116 RC_SAE_immediate (const char *imm_start
)
11118 unsigned int match_found
, j
;
11119 const char *pstr
= imm_start
;
11127 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11129 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11133 rc_op
.type
= RC_NamesTable
[j
].type
;
11134 rc_op
.operand
= this_operand
;
11135 i
.rounding
= &rc_op
;
11139 as_bad (_("duplicated `%s'"), imm_start
);
11142 pstr
+= RC_NamesTable
[j
].len
;
11150 if (*pstr
++ != '}')
11152 as_bad (_("Missing '}': '%s'"), imm_start
);
11155 /* RC/SAE immediate string should contain nothing more. */;
11158 as_bad (_("Junk after '}': '%s'"), imm_start
);
11162 exp
= &im_expressions
[i
.imm_operands
++];
11163 i
.op
[this_operand
].imms
= exp
;
11165 exp
->X_op
= O_constant
;
11166 exp
->X_add_number
= 0;
11167 exp
->X_add_symbol
= (symbolS
*) 0;
11168 exp
->X_op_symbol
= (symbolS
*) 0;
11170 i
.types
[this_operand
].bitfield
.imm8
= 1;
11174 /* Only string instructions can have a second memory operand, so
11175 reduce current_templates to just those if it contains any. */
11177 maybe_adjust_templates (void)
11179 const insn_template
*t
;
11181 gas_assert (i
.mem_operands
== 1);
11183 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11184 if (t
->opcode_modifier
.isstring
)
11187 if (t
< current_templates
->end
)
11189 static templates aux_templates
;
11190 bfd_boolean recheck
;
11192 aux_templates
.start
= t
;
11193 for (; t
< current_templates
->end
; ++t
)
11194 if (!t
->opcode_modifier
.isstring
)
11196 aux_templates
.end
= t
;
11198 /* Determine whether to re-check the first memory operand. */
11199 recheck
= (aux_templates
.start
!= current_templates
->start
11200 || t
!= current_templates
->end
);
11202 current_templates
= &aux_templates
;
11206 i
.mem_operands
= 0;
11207 if (i
.memop1_string
!= NULL
11208 && i386_index_check (i
.memop1_string
) == 0)
11210 i
.mem_operands
= 1;
11217 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11221 i386_att_operand (char *operand_string
)
11223 const reg_entry
*r
;
11225 char *op_string
= operand_string
;
11227 if (is_space_char (*op_string
))
11230 /* We check for an absolute prefix (differentiating,
11231 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11232 if (*op_string
== ABSOLUTE_PREFIX
)
11235 if (is_space_char (*op_string
))
11237 i
.jumpabsolute
= TRUE
;
11240 /* Check if operand is a register. */
11241 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11243 i386_operand_type temp
;
11248 /* Check for a segment override by searching for ':' after a
11249 segment register. */
11250 op_string
= end_op
;
11251 if (is_space_char (*op_string
))
11253 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11255 switch (r
->reg_num
)
11258 i
.seg
[i
.mem_operands
] = &es
;
11261 i
.seg
[i
.mem_operands
] = &cs
;
11264 i
.seg
[i
.mem_operands
] = &ss
;
11267 i
.seg
[i
.mem_operands
] = &ds
;
11270 i
.seg
[i
.mem_operands
] = &fs
;
11273 i
.seg
[i
.mem_operands
] = &gs
;
11277 /* Skip the ':' and whitespace. */
11279 if (is_space_char (*op_string
))
11282 if (!is_digit_char (*op_string
)
11283 && !is_identifier_char (*op_string
)
11284 && *op_string
!= '('
11285 && *op_string
!= ABSOLUTE_PREFIX
)
11287 as_bad (_("bad memory operand `%s'"), op_string
);
11290 /* Handle case of %es:*foo. */
11291 if (*op_string
== ABSOLUTE_PREFIX
)
11294 if (is_space_char (*op_string
))
11296 i
.jumpabsolute
= TRUE
;
11298 goto do_memory_reference
;
11301 /* Handle vector operations. */
11302 if (*op_string
== '{')
11304 op_string
= check_VecOperations (op_string
, NULL
);
11305 if (op_string
== NULL
)
11311 as_bad (_("junk `%s' after register"), op_string
);
11314 temp
= r
->reg_type
;
11315 temp
.bitfield
.baseindex
= 0;
11316 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11318 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11319 i
.op
[this_operand
].regs
= r
;
11322 else if (*op_string
== REGISTER_PREFIX
)
11324 as_bad (_("bad register name `%s'"), op_string
);
11327 else if (*op_string
== IMMEDIATE_PREFIX
)
11330 if (i
.jumpabsolute
)
11332 as_bad (_("immediate operand illegal with absolute jump"));
11335 if (!i386_immediate (op_string
))
11338 else if (RC_SAE_immediate (operand_string
))
11340 /* If it is a RC or SAE immediate, do nothing. */
11343 else if (is_digit_char (*op_string
)
11344 || is_identifier_char (*op_string
)
11345 || *op_string
== '"'
11346 || *op_string
== '(')
11348 /* This is a memory reference of some sort. */
11351 /* Start and end of displacement string expression (if found). */
11352 char *displacement_string_start
;
11353 char *displacement_string_end
;
11356 do_memory_reference
:
11357 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11359 if ((i
.mem_operands
== 1
11360 && !current_templates
->start
->opcode_modifier
.isstring
)
11361 || i
.mem_operands
== 2)
11363 as_bad (_("too many memory references for `%s'"),
11364 current_templates
->start
->name
);
11368 /* Check for base index form. We detect the base index form by
11369 looking for an ')' at the end of the operand, searching
11370 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11372 base_string
= op_string
+ strlen (op_string
);
11374 /* Handle vector operations. */
11375 vop_start
= strchr (op_string
, '{');
11376 if (vop_start
&& vop_start
< base_string
)
11378 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11380 base_string
= vop_start
;
11384 if (is_space_char (*base_string
))
11387 /* If we only have a displacement, set-up for it to be parsed later. */
11388 displacement_string_start
= op_string
;
11389 displacement_string_end
= base_string
+ 1;
11391 if (*base_string
== ')')
11394 unsigned int parens_balanced
= 1;
11395 /* We've already checked that the number of left & right ()'s are
11396 equal, so this loop will not be infinite. */
11400 if (*base_string
== ')')
11402 if (*base_string
== '(')
11405 while (parens_balanced
);
11407 temp_string
= base_string
;
11409 /* Skip past '(' and whitespace. */
11411 if (is_space_char (*base_string
))
11414 if (*base_string
== ','
11415 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11418 displacement_string_end
= temp_string
;
11420 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11424 if (i
.base_reg
== &bad_reg
)
11426 base_string
= end_op
;
11427 if (is_space_char (*base_string
))
11431 /* There may be an index reg or scale factor here. */
11432 if (*base_string
== ',')
11435 if (is_space_char (*base_string
))
11438 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11441 if (i
.index_reg
== &bad_reg
)
11443 base_string
= end_op
;
11444 if (is_space_char (*base_string
))
11446 if (*base_string
== ',')
11449 if (is_space_char (*base_string
))
11452 else if (*base_string
!= ')')
11454 as_bad (_("expecting `,' or `)' "
11455 "after index register in `%s'"),
11460 else if (*base_string
== REGISTER_PREFIX
)
11462 end_op
= strchr (base_string
, ',');
11465 as_bad (_("bad register name `%s'"), base_string
);
11469 /* Check for scale factor. */
11470 if (*base_string
!= ')')
11472 char *end_scale
= i386_scale (base_string
);
11477 base_string
= end_scale
;
11478 if (is_space_char (*base_string
))
11480 if (*base_string
!= ')')
11482 as_bad (_("expecting `)' "
11483 "after scale factor in `%s'"),
11488 else if (!i
.index_reg
)
11490 as_bad (_("expecting index register or scale factor "
11491 "after `,'; got '%c'"),
11496 else if (*base_string
!= ')')
11498 as_bad (_("expecting `,' or `)' "
11499 "after base register in `%s'"),
11504 else if (*base_string
== REGISTER_PREFIX
)
11506 end_op
= strchr (base_string
, ',');
11509 as_bad (_("bad register name `%s'"), base_string
);
11514 /* If there's an expression beginning the operand, parse it,
11515 assuming displacement_string_start and
11516 displacement_string_end are meaningful. */
11517 if (displacement_string_start
!= displacement_string_end
)
11519 if (!i386_displacement (displacement_string_start
,
11520 displacement_string_end
))
11524 /* Special case for (%dx) while doing input/output op. */
11526 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11527 && i
.base_reg
->reg_type
.bitfield
.word
11528 && i
.index_reg
== 0
11529 && i
.log2_scale_factor
== 0
11530 && i
.seg
[i
.mem_operands
] == 0
11531 && !operand_type_check (i
.types
[this_operand
], disp
))
11533 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11537 if (i386_index_check (operand_string
) == 0)
11539 i
.flags
[this_operand
] |= Operand_Mem
;
11540 if (i
.mem_operands
== 0)
11541 i
.memop1_string
= xstrdup (operand_string
);
11546 /* It's not a memory operand; argh! */
11547 as_bad (_("invalid char %s beginning operand %d `%s'"),
11548 output_invalid (*op_string
),
11553 return 1; /* Normal return. */
11556 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11557 that an rs_machine_dependent frag may reach. */
11560 i386_frag_max_var (fragS
*frag
)
11562 /* The only relaxable frags are for jumps.
11563 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11564 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11565 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11570 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11572 /* STT_GNU_IFUNC symbol must go through PLT. */
11573 if ((symbol_get_bfdsym (fr_symbol
)->flags
11574 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11577 if (!S_IS_EXTERNAL (fr_symbol
))
11578 /* Symbol may be weak or local. */
11579 return !S_IS_WEAK (fr_symbol
);
11581 /* Global symbols with non-default visibility can't be preempted. */
11582 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11585 if (fr_var
!= NO_RELOC
)
11586 switch ((enum bfd_reloc_code_real
) fr_var
)
11588 case BFD_RELOC_386_PLT32
:
11589 case BFD_RELOC_X86_64_PLT32
:
11590 /* Symbol with PLT relocation may be preempted. */
11596 /* Global symbols with default visibility in a shared library may be
11597 preempted by another definition. */
11602 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11603 Note also work for Skylake and Cascadelake.
11604 ---------------------------------------------------------------------
11605 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11606 | ------ | ----------- | ------- | -------- |
11608 | Jno | N | N | Y |
11609 | Jc/Jb | Y | N | Y |
11610 | Jae/Jnb | Y | N | Y |
11611 | Je/Jz | Y | Y | Y |
11612 | Jne/Jnz | Y | Y | Y |
11613 | Jna/Jbe | Y | N | Y |
11614 | Ja/Jnbe | Y | N | Y |
11616 | Jns | N | N | Y |
11617 | Jp/Jpe | N | N | Y |
11618 | Jnp/Jpo | N | N | Y |
11619 | Jl/Jnge | Y | Y | Y |
11620 | Jge/Jnl | Y | Y | Y |
11621 | Jle/Jng | Y | Y | Y |
11622 | Jg/Jnle | Y | Y | Y |
11623 --------------------------------------------------------------------- */
11625 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11627 if (mf_cmp
== mf_cmp_alu_cmp
)
11628 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11629 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11630 if (mf_cmp
== mf_cmp_incdec
)
11631 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11632 || mf_jcc
== mf_jcc_jle
);
11633 if (mf_cmp
== mf_cmp_test_and
)
11638 /* Return the next non-empty frag. */
11641 i386_next_non_empty_frag (fragS
*fragP
)
11643 /* There may be a frag with a ".fill 0" when there is no room in
11644 the current frag for frag_grow in output_insn. */
11645 for (fragP
= fragP
->fr_next
;
11647 && fragP
->fr_type
== rs_fill
11648 && fragP
->fr_fix
== 0);
11649 fragP
= fragP
->fr_next
)
11654 /* Return the next jcc frag after BRANCH_PADDING. */
11657 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11659 fragS
*branch_fragP
;
11663 if (pad_fragP
->fr_type
== rs_machine_dependent
11664 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11665 == BRANCH_PADDING
))
11667 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11668 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11670 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11671 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11672 pad_fragP
->tc_frag_data
.mf_type
))
11673 return branch_fragP
;
11679 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11682 i386_classify_machine_dependent_frag (fragS
*fragP
)
11686 fragS
*branch_fragP
;
11688 unsigned int max_prefix_length
;
11690 if (fragP
->tc_frag_data
.classified
)
11693 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11694 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11695 for (next_fragP
= fragP
;
11696 next_fragP
!= NULL
;
11697 next_fragP
= next_fragP
->fr_next
)
11699 next_fragP
->tc_frag_data
.classified
= 1;
11700 if (next_fragP
->fr_type
== rs_machine_dependent
)
11701 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11703 case BRANCH_PADDING
:
11704 /* The BRANCH_PADDING frag must be followed by a branch
11706 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11707 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11709 case FUSED_JCC_PADDING
:
11710 /* Check if this is a fused jcc:
11712 CMP like instruction
11716 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11717 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11718 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11721 /* The BRANCH_PADDING frag is merged with the
11722 FUSED_JCC_PADDING frag. */
11723 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11724 /* CMP like instruction size. */
11725 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11726 frag_wane (pad_fragP
);
11727 /* Skip to branch_fragP. */
11728 next_fragP
= branch_fragP
;
11730 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11732 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11734 next_fragP
->fr_subtype
11735 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11736 next_fragP
->tc_frag_data
.max_bytes
11737 = next_fragP
->tc_frag_data
.max_prefix_length
;
11738 /* This will be updated in the BRANCH_PREFIX scan. */
11739 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11742 frag_wane (next_fragP
);
11747 /* Stop if there is no BRANCH_PREFIX. */
11748 if (!align_branch_prefix_size
)
11751 /* Scan for BRANCH_PREFIX. */
11752 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11754 if (fragP
->fr_type
!= rs_machine_dependent
11755 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11759 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11760 COND_JUMP_PREFIX. */
11761 max_prefix_length
= 0;
11762 for (next_fragP
= fragP
;
11763 next_fragP
!= NULL
;
11764 next_fragP
= next_fragP
->fr_next
)
11766 if (next_fragP
->fr_type
== rs_fill
)
11767 /* Skip rs_fill frags. */
11769 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11770 /* Stop for all other frags. */
11773 /* rs_machine_dependent frags. */
11774 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11777 /* Count BRANCH_PREFIX frags. */
11778 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11780 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11781 frag_wane (next_fragP
);
11785 += next_fragP
->tc_frag_data
.max_bytes
;
11787 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11789 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11790 == FUSED_JCC_PADDING
))
11792 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11793 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11797 /* Stop for other rs_machine_dependent frags. */
11801 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11803 /* Skip to the next frag. */
11804 fragP
= next_fragP
;
11808 /* Compute padding size for
11811 CMP like instruction
11813 COND_JUMP/UNCOND_JUMP
11818 COND_JUMP/UNCOND_JUMP
11822 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11824 unsigned int offset
, size
, padding_size
;
11825 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11827 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11829 address
= fragP
->fr_address
;
11830 address
+= fragP
->fr_fix
;
11832 /* CMP like instrunction size. */
11833 size
= fragP
->tc_frag_data
.cmp_size
;
11835 /* The base size of the branch frag. */
11836 size
+= branch_fragP
->fr_fix
;
11838 /* Add opcode and displacement bytes for the rs_machine_dependent
11840 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11841 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11843 /* Check if branch is within boundary and doesn't end at the last
11845 offset
= address
& ((1U << align_branch_power
) - 1);
11846 if ((offset
+ size
) >= (1U << align_branch_power
))
11847 /* Padding needed to avoid crossing boundary. */
11848 padding_size
= (1U << align_branch_power
) - offset
;
11850 /* No padding needed. */
11853 /* The return value may be saved in tc_frag_data.length which is
11855 if (!fits_in_unsigned_byte (padding_size
))
11858 return padding_size
;
11861 /* i386_generic_table_relax_frag()
11863 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11864 grow/shrink padding to align branch frags. Hand others to
11868 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11870 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11871 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11873 long padding_size
= i386_branch_padding_size (fragP
, 0);
11874 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11876 /* When the BRANCH_PREFIX frag is used, the computed address
11877 must match the actual address and there should be no padding. */
11878 if (fragP
->tc_frag_data
.padding_address
11879 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11883 /* Update the padding size. */
11885 fragP
->tc_frag_data
.length
= padding_size
;
11889 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11891 fragS
*padding_fragP
, *next_fragP
;
11892 long padding_size
, left_size
, last_size
;
11894 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11895 if (!padding_fragP
)
11896 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11897 return (fragP
->tc_frag_data
.length
11898 - fragP
->tc_frag_data
.last_length
);
11900 /* Compute the relative address of the padding frag in the very
11901 first time where the BRANCH_PREFIX frag sizes are zero. */
11902 if (!fragP
->tc_frag_data
.padding_address
)
11903 fragP
->tc_frag_data
.padding_address
11904 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11906 /* First update the last length from the previous interation. */
11907 left_size
= fragP
->tc_frag_data
.prefix_length
;
11908 for (next_fragP
= fragP
;
11909 next_fragP
!= padding_fragP
;
11910 next_fragP
= next_fragP
->fr_next
)
11911 if (next_fragP
->fr_type
== rs_machine_dependent
11912 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11917 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11921 if (max
> left_size
)
11926 next_fragP
->tc_frag_data
.last_length
= size
;
11930 next_fragP
->tc_frag_data
.last_length
= 0;
11933 /* Check the padding size for the padding frag. */
11934 padding_size
= i386_branch_padding_size
11935 (padding_fragP
, (fragP
->fr_address
11936 + fragP
->tc_frag_data
.padding_address
));
11938 last_size
= fragP
->tc_frag_data
.prefix_length
;
11939 /* Check if there is change from the last interation. */
11940 if (padding_size
== last_size
)
11942 /* Update the expected address of the padding frag. */
11943 padding_fragP
->tc_frag_data
.padding_address
11944 = (fragP
->fr_address
+ padding_size
11945 + fragP
->tc_frag_data
.padding_address
);
11949 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11951 /* No padding if there is no sufficient room. Clear the
11952 expected address of the padding frag. */
11953 padding_fragP
->tc_frag_data
.padding_address
= 0;
11957 /* Store the expected address of the padding frag. */
11958 padding_fragP
->tc_frag_data
.padding_address
11959 = (fragP
->fr_address
+ padding_size
11960 + fragP
->tc_frag_data
.padding_address
);
11962 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11964 /* Update the length for the current interation. */
11965 left_size
= padding_size
;
11966 for (next_fragP
= fragP
;
11967 next_fragP
!= padding_fragP
;
11968 next_fragP
= next_fragP
->fr_next
)
11969 if (next_fragP
->fr_type
== rs_machine_dependent
11970 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11975 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11979 if (max
> left_size
)
11984 next_fragP
->tc_frag_data
.length
= size
;
11988 next_fragP
->tc_frag_data
.length
= 0;
11991 return (fragP
->tc_frag_data
.length
11992 - fragP
->tc_frag_data
.last_length
);
11994 return relax_frag (segment
, fragP
, stretch
);
11997 /* md_estimate_size_before_relax()
11999 Called just before relax() for rs_machine_dependent frags. The x86
12000 assembler uses these frags to handle variable size jump
12003 Any symbol that is now undefined will not become defined.
12004 Return the correct fr_subtype in the frag.
12005 Return the initial "guess for variable size of frag" to caller.
12006 The guess is actually the growth beyond the fixed part. Whatever
12007 we do to grow the fixed or variable part contributes to our
12011 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12013 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12014 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12015 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12017 i386_classify_machine_dependent_frag (fragP
);
12018 return fragP
->tc_frag_data
.length
;
12021 /* We've already got fragP->fr_subtype right; all we have to do is
12022 check for un-relaxable symbols. On an ELF system, we can't relax
12023 an externally visible symbol, because it may be overridden by a
12025 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12028 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12031 #if defined (OBJ_COFF) && defined (TE_PE)
12032 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12033 && S_IS_WEAK (fragP
->fr_symbol
))
12037 /* Symbol is undefined in this segment, or we need to keep a
12038 reloc so that weak symbols can be overridden. */
12039 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12040 enum bfd_reloc_code_real reloc_type
;
12041 unsigned char *opcode
;
12044 if (fragP
->fr_var
!= NO_RELOC
)
12045 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12046 else if (size
== 2)
12047 reloc_type
= BFD_RELOC_16_PCREL
;
12048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12049 else if (need_plt32_p (fragP
->fr_symbol
))
12050 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12053 reloc_type
= BFD_RELOC_32_PCREL
;
12055 old_fr_fix
= fragP
->fr_fix
;
12056 opcode
= (unsigned char *) fragP
->fr_opcode
;
12058 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12061 /* Make jmp (0xeb) a (d)word displacement jump. */
12063 fragP
->fr_fix
+= size
;
12064 fix_new (fragP
, old_fr_fix
, size
,
12066 fragP
->fr_offset
, 1,
12072 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12074 /* Negate the condition, and branch past an
12075 unconditional jump. */
12078 /* Insert an unconditional jump. */
12080 /* We added two extra opcode bytes, and have a two byte
12082 fragP
->fr_fix
+= 2 + 2;
12083 fix_new (fragP
, old_fr_fix
+ 2, 2,
12085 fragP
->fr_offset
, 1,
12089 /* Fall through. */
12092 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12096 fragP
->fr_fix
+= 1;
12097 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12099 fragP
->fr_offset
, 1,
12100 BFD_RELOC_8_PCREL
);
12101 fixP
->fx_signed
= 1;
12105 /* This changes the byte-displacement jump 0x7N
12106 to the (d)word-displacement jump 0x0f,0x8N. */
12107 opcode
[1] = opcode
[0] + 0x10;
12108 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12109 /* We've added an opcode byte. */
12110 fragP
->fr_fix
+= 1 + size
;
12111 fix_new (fragP
, old_fr_fix
+ 1, size
,
12113 fragP
->fr_offset
, 1,
12118 BAD_CASE (fragP
->fr_subtype
);
12122 return fragP
->fr_fix
- old_fr_fix
;
12125 /* Guess size depending on current relax state. Initially the relax
12126 state will correspond to a short jump and we return 1, because
12127 the variable part of the frag (the branch offset) is one byte
12128 long. However, we can relax a section more than once and in that
12129 case we must either set fr_subtype back to the unrelaxed state,
12130 or return the value for the appropriate branch. */
12131 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12134 /* Called after relax() is finished.
12136 In: Address of frag.
12137 fr_type == rs_machine_dependent.
12138 fr_subtype is what the address relaxed to.
12140 Out: Any fixSs and constants are set up.
12141 Caller will turn frag into a ".space 0". */
12144 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12147 unsigned char *opcode
;
12148 unsigned char *where_to_put_displacement
= NULL
;
12149 offsetT target_address
;
12150 offsetT opcode_address
;
12151 unsigned int extension
= 0;
12152 offsetT displacement_from_opcode_start
;
12154 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12155 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12156 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12158 /* Generate nop padding. */
12159 unsigned int size
= fragP
->tc_frag_data
.length
;
12162 if (size
> fragP
->tc_frag_data
.max_bytes
)
12168 const char *branch
= "branch";
12169 const char *prefix
= "";
12170 fragS
*padding_fragP
;
12171 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12174 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12175 switch (fragP
->tc_frag_data
.default_prefix
)
12180 case CS_PREFIX_OPCODE
:
12183 case DS_PREFIX_OPCODE
:
12186 case ES_PREFIX_OPCODE
:
12189 case FS_PREFIX_OPCODE
:
12192 case GS_PREFIX_OPCODE
:
12195 case SS_PREFIX_OPCODE
:
12200 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12201 "%s within %d-byte boundary\n");
12203 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12204 "align %s within %d-byte boundary\n");
12208 padding_fragP
= fragP
;
12209 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12210 "%s within %d-byte boundary\n");
12214 switch (padding_fragP
->tc_frag_data
.branch_type
)
12216 case align_branch_jcc
:
12219 case align_branch_fused
:
12220 branch
= "fused jcc";
12222 case align_branch_jmp
:
12225 case align_branch_call
:
12228 case align_branch_indirect
:
12229 branch
= "indiret branch";
12231 case align_branch_ret
:
12238 fprintf (stdout
, msg
,
12239 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12240 (long long) fragP
->fr_address
, branch
,
12241 1 << align_branch_power
);
12243 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12244 memset (fragP
->fr_opcode
,
12245 fragP
->tc_frag_data
.default_prefix
, size
);
12247 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12249 fragP
->fr_fix
+= size
;
12254 opcode
= (unsigned char *) fragP
->fr_opcode
;
12256 /* Address we want to reach in file space. */
12257 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12259 /* Address opcode resides at in file space. */
12260 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12262 /* Displacement from opcode start to fill into instruction. */
12263 displacement_from_opcode_start
= target_address
- opcode_address
;
12265 if ((fragP
->fr_subtype
& BIG
) == 0)
12267 /* Don't have to change opcode. */
12268 extension
= 1; /* 1 opcode + 1 displacement */
12269 where_to_put_displacement
= &opcode
[1];
12273 if (no_cond_jump_promotion
12274 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12275 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12276 _("long jump required"));
12278 switch (fragP
->fr_subtype
)
12280 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12281 extension
= 4; /* 1 opcode + 4 displacement */
12283 where_to_put_displacement
= &opcode
[1];
12286 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12287 extension
= 2; /* 1 opcode + 2 displacement */
12289 where_to_put_displacement
= &opcode
[1];
12292 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12293 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12294 extension
= 5; /* 2 opcode + 4 displacement */
12295 opcode
[1] = opcode
[0] + 0x10;
12296 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12297 where_to_put_displacement
= &opcode
[2];
12300 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12301 extension
= 3; /* 2 opcode + 2 displacement */
12302 opcode
[1] = opcode
[0] + 0x10;
12303 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12304 where_to_put_displacement
= &opcode
[2];
12307 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12312 where_to_put_displacement
= &opcode
[3];
12316 BAD_CASE (fragP
->fr_subtype
);
12321 /* If size if less then four we are sure that the operand fits,
12322 but if it's 4, then it could be that the displacement is larger
12324 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12326 && ((addressT
) (displacement_from_opcode_start
- extension
12327 + ((addressT
) 1 << 31))
12328 > (((addressT
) 2 << 31) - 1)))
12330 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12331 _("jump target out of range"));
12332 /* Make us emit 0. */
12333 displacement_from_opcode_start
= extension
;
12335 /* Now put displacement after opcode. */
12336 md_number_to_chars ((char *) where_to_put_displacement
,
12337 (valueT
) (displacement_from_opcode_start
- extension
),
12338 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12339 fragP
->fr_fix
+= extension
;
12342 /* Apply a fixup (fixP) to segment data, once it has been determined
12343 by our caller that we have all the info we need to fix it up.
12345 Parameter valP is the pointer to the value of the bits.
12347 On the 386, immediates, displacements, and data pointers are all in
12348 the same (little-endian) format, so we don't need to care about which
12349 we are handling. */
12352 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12354 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12355 valueT value
= *valP
;
12357 #if !defined (TE_Mach)
12358 if (fixP
->fx_pcrel
)
12360 switch (fixP
->fx_r_type
)
12366 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12369 case BFD_RELOC_X86_64_32S
:
12370 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12373 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12376 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12381 if (fixP
->fx_addsy
!= NULL
12382 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12383 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12384 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12385 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12386 && !use_rela_relocations
)
12388 /* This is a hack. There should be a better way to handle this.
12389 This covers for the fact that bfd_install_relocation will
12390 subtract the current location (for partial_inplace, PC relative
12391 relocations); see more below. */
12395 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12398 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12403 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12405 if ((sym_seg
== seg
12406 || (symbol_section_p (fixP
->fx_addsy
)
12407 && sym_seg
!= absolute_section
))
12408 && !generic_force_reloc (fixP
))
12410 /* Yes, we add the values in twice. This is because
12411 bfd_install_relocation subtracts them out again. I think
12412 bfd_install_relocation is broken, but I don't dare change
12414 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12418 #if defined (OBJ_COFF) && defined (TE_PE)
12419 /* For some reason, the PE format does not store a
12420 section address offset for a PC relative symbol. */
12421 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12422 || S_IS_WEAK (fixP
->fx_addsy
))
12423 value
+= md_pcrel_from (fixP
);
12426 #if defined (OBJ_COFF) && defined (TE_PE)
12427 if (fixP
->fx_addsy
!= NULL
12428 && S_IS_WEAK (fixP
->fx_addsy
)
12429 /* PR 16858: Do not modify weak function references. */
12430 && ! fixP
->fx_pcrel
)
12432 #if !defined (TE_PEP)
12433 /* For x86 PE weak function symbols are neither PC-relative
12434 nor do they set S_IS_FUNCTION. So the only reliable way
12435 to detect them is to check the flags of their containing
12437 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12438 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12442 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12446 /* Fix a few things - the dynamic linker expects certain values here,
12447 and we must not disappoint it. */
12448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12449 if (IS_ELF
&& fixP
->fx_addsy
)
12450 switch (fixP
->fx_r_type
)
12452 case BFD_RELOC_386_PLT32
:
12453 case BFD_RELOC_X86_64_PLT32
:
12454 /* Make the jump instruction point to the address of the operand.
12455 At runtime we merely add the offset to the actual PLT entry.
12456 NB: Subtract the offset size only for jump instructions. */
12457 if (fixP
->fx_pcrel
)
12461 case BFD_RELOC_386_TLS_GD
:
12462 case BFD_RELOC_386_TLS_LDM
:
12463 case BFD_RELOC_386_TLS_IE_32
:
12464 case BFD_RELOC_386_TLS_IE
:
12465 case BFD_RELOC_386_TLS_GOTIE
:
12466 case BFD_RELOC_386_TLS_GOTDESC
:
12467 case BFD_RELOC_X86_64_TLSGD
:
12468 case BFD_RELOC_X86_64_TLSLD
:
12469 case BFD_RELOC_X86_64_GOTTPOFF
:
12470 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12471 value
= 0; /* Fully resolved at runtime. No addend. */
12473 case BFD_RELOC_386_TLS_LE
:
12474 case BFD_RELOC_386_TLS_LDO_32
:
12475 case BFD_RELOC_386_TLS_LE_32
:
12476 case BFD_RELOC_X86_64_DTPOFF32
:
12477 case BFD_RELOC_X86_64_DTPOFF64
:
12478 case BFD_RELOC_X86_64_TPOFF32
:
12479 case BFD_RELOC_X86_64_TPOFF64
:
12480 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12483 case BFD_RELOC_386_TLS_DESC_CALL
:
12484 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12485 value
= 0; /* Fully resolved at runtime. No addend. */
12486 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12490 case BFD_RELOC_VTABLE_INHERIT
:
12491 case BFD_RELOC_VTABLE_ENTRY
:
12498 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12500 #endif /* !defined (TE_Mach) */
12502 /* Are we finished with this relocation now? */
12503 if (fixP
->fx_addsy
== NULL
)
12505 #if defined (OBJ_COFF) && defined (TE_PE)
12506 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12509 /* Remember value for tc_gen_reloc. */
12510 fixP
->fx_addnumber
= value
;
12511 /* Clear out the frag for now. */
12515 else if (use_rela_relocations
)
12517 fixP
->fx_no_overflow
= 1;
12518 /* Remember value for tc_gen_reloc. */
12519 fixP
->fx_addnumber
= value
;
12523 md_number_to_chars (p
, value
, fixP
->fx_size
);
12527 md_atof (int type
, char *litP
, int *sizeP
)
12529 /* This outputs the LITTLENUMs in REVERSE order;
12530 in accord with the bigendian 386. */
12531 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12534 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12537 output_invalid (int c
)
12540 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12543 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12544 "(0x%x)", (unsigned char) c
);
12545 return output_invalid_buf
;
12548 /* Verify that @r can be used in the current context. */
12550 static bfd_boolean
check_register (const reg_entry
*r
)
12552 if (allow_pseudo_reg
)
12555 if (operand_type_all_zero (&r
->reg_type
))
12558 if ((r
->reg_type
.bitfield
.dword
12559 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12560 || r
->reg_type
.bitfield
.class == RegCR
12561 || r
->reg_type
.bitfield
.class == RegDR
)
12562 && !cpu_arch_flags
.bitfield
.cpui386
)
12565 if (r
->reg_type
.bitfield
.class == RegTR
12566 && (flag_code
== CODE_64BIT
12567 || !cpu_arch_flags
.bitfield
.cpui386
12568 || cpu_arch_isa_flags
.bitfield
.cpui586
12569 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12572 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12575 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12577 if (r
->reg_type
.bitfield
.zmmword
12578 || r
->reg_type
.bitfield
.class == RegMask
)
12581 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12583 if (r
->reg_type
.bitfield
.ymmword
)
12586 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12591 if (r
->reg_type
.bitfield
.tmmword
12592 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12593 || flag_code
!= CODE_64BIT
))
12596 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12599 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12600 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12603 /* Upper 16 vector registers are only available with VREX in 64bit
12604 mode, and require EVEX encoding. */
12605 if (r
->reg_flags
& RegVRex
)
12607 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12608 || flag_code
!= CODE_64BIT
)
12611 if (i
.vec_encoding
== vex_encoding_default
)
12612 i
.vec_encoding
= vex_encoding_evex
;
12613 else if (i
.vec_encoding
!= vex_encoding_evex
)
12614 i
.vec_encoding
= vex_encoding_error
;
12617 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12618 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12619 && flag_code
!= CODE_64BIT
)
12622 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12629 /* REG_STRING starts *before* REGISTER_PREFIX. */
12631 static const reg_entry
*
12632 parse_real_register (char *reg_string
, char **end_op
)
12634 char *s
= reg_string
;
12636 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12637 const reg_entry
*r
;
12639 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12640 if (*s
== REGISTER_PREFIX
)
12643 if (is_space_char (*s
))
12646 p
= reg_name_given
;
12647 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12649 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12650 return (const reg_entry
*) NULL
;
12654 /* For naked regs, make sure that we are not dealing with an identifier.
12655 This prevents confusing an identifier like `eax_var' with register
12657 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12658 return (const reg_entry
*) NULL
;
12662 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12664 /* Handle floating point regs, allowing spaces in the (i) part. */
12665 if (r
== i386_regtab
/* %st is first entry of table */)
12667 if (!cpu_arch_flags
.bitfield
.cpu8087
12668 && !cpu_arch_flags
.bitfield
.cpu287
12669 && !cpu_arch_flags
.bitfield
.cpu387
12670 && !allow_pseudo_reg
)
12671 return (const reg_entry
*) NULL
;
12673 if (is_space_char (*s
))
12678 if (is_space_char (*s
))
12680 if (*s
>= '0' && *s
<= '7')
12682 int fpr
= *s
- '0';
12684 if (is_space_char (*s
))
12689 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12694 /* We have "%st(" then garbage. */
12695 return (const reg_entry
*) NULL
;
12699 return r
&& check_register (r
) ? r
: NULL
;
12702 /* REG_STRING starts *before* REGISTER_PREFIX. */
12704 static const reg_entry
*
12705 parse_register (char *reg_string
, char **end_op
)
12707 const reg_entry
*r
;
12709 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12710 r
= parse_real_register (reg_string
, end_op
);
12715 char *save
= input_line_pointer
;
12719 input_line_pointer
= reg_string
;
12720 c
= get_symbol_name (®_string
);
12721 symbolP
= symbol_find (reg_string
);
12722 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12724 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12726 know (e
->X_op
== O_register
);
12727 know (e
->X_add_number
>= 0
12728 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12729 r
= i386_regtab
+ e
->X_add_number
;
12730 if (!check_register (r
))
12732 as_bad (_("register '%s%s' cannot be used here"),
12733 register_prefix
, r
->reg_name
);
12736 *end_op
= input_line_pointer
;
12738 *input_line_pointer
= c
;
12739 input_line_pointer
= save
;
12745 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12747 const reg_entry
*r
;
12748 char *end
= input_line_pointer
;
12751 r
= parse_register (name
, &input_line_pointer
);
12752 if (r
&& end
<= input_line_pointer
)
12754 *nextcharP
= *input_line_pointer
;
12755 *input_line_pointer
= 0;
12758 e
->X_op
= O_register
;
12759 e
->X_add_number
= r
- i386_regtab
;
12762 e
->X_op
= O_illegal
;
12765 input_line_pointer
= end
;
12767 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12771 md_operand (expressionS
*e
)
12774 const reg_entry
*r
;
12776 switch (*input_line_pointer
)
12778 case REGISTER_PREFIX
:
12779 r
= parse_real_register (input_line_pointer
, &end
);
12782 e
->X_op
= O_register
;
12783 e
->X_add_number
= r
- i386_regtab
;
12784 input_line_pointer
= end
;
12789 gas_assert (intel_syntax
);
12790 end
= input_line_pointer
++;
12792 if (*input_line_pointer
== ']')
12794 ++input_line_pointer
;
12795 e
->X_op_symbol
= make_expr_symbol (e
);
12796 e
->X_add_symbol
= NULL
;
12797 e
->X_add_number
= 0;
12802 e
->X_op
= O_absent
;
12803 input_line_pointer
= end
;
12810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12811 const char *md_shortopts
= "kVQ:sqnO::";
12813 const char *md_shortopts
= "qnO::";
12816 #define OPTION_32 (OPTION_MD_BASE + 0)
12817 #define OPTION_64 (OPTION_MD_BASE + 1)
12818 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12819 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12820 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12821 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12822 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12823 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12824 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12825 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12826 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12827 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12828 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12829 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12830 #define OPTION_X32 (OPTION_MD_BASE + 14)
12831 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12832 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12833 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12834 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12835 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12836 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12837 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12838 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12839 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12840 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12841 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12842 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12843 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12844 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12845 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12846 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12847 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12848 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12849 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12851 struct option md_longopts
[] =
12853 {"32", no_argument
, NULL
, OPTION_32
},
12854 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12855 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12856 {"64", no_argument
, NULL
, OPTION_64
},
12858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12859 {"x32", no_argument
, NULL
, OPTION_X32
},
12860 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12861 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12863 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12864 {"march", required_argument
, NULL
, OPTION_MARCH
},
12865 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12866 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12867 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12868 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12869 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12870 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12871 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12872 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12873 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12874 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12875 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12876 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12877 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12878 # if defined (TE_PE) || defined (TE_PEP)
12879 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12881 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12882 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12883 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12884 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12885 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12886 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12887 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12888 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12889 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12890 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12891 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12892 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12893 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12894 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12895 {NULL
, no_argument
, NULL
, 0}
12897 size_t md_longopts_size
= sizeof (md_longopts
);
12900 md_parse_option (int c
, const char *arg
)
12903 char *arch
, *next
, *saved
, *type
;
12908 optimize_align_code
= 0;
12912 quiet_warnings
= 1;
12915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12916 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12917 should be emitted or not. FIXME: Not implemented. */
12919 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12923 /* -V: SVR4 argument to print version ID. */
12925 print_version_id ();
12928 /* -k: Ignore for FreeBSD compatibility. */
12933 /* -s: On i386 Solaris, this tells the native assembler to use
12934 .stab instead of .stab.excl. We always use .stab anyhow. */
12937 case OPTION_MSHARED
:
12941 case OPTION_X86_USED_NOTE
:
12942 if (strcasecmp (arg
, "yes") == 0)
12944 else if (strcasecmp (arg
, "no") == 0)
12947 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12952 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12953 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12956 const char **list
, **l
;
12958 list
= bfd_target_list ();
12959 for (l
= list
; *l
!= NULL
; l
++)
12960 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12961 || strcmp (*l
, "coff-x86-64") == 0
12962 || strcmp (*l
, "pe-x86-64") == 0
12963 || strcmp (*l
, "pei-x86-64") == 0
12964 || strcmp (*l
, "mach-o-x86-64") == 0)
12966 default_arch
= "x86_64";
12970 as_fatal (_("no compiled in support for x86_64"));
12976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12980 const char **list
, **l
;
12982 list
= bfd_target_list ();
12983 for (l
= list
; *l
!= NULL
; l
++)
12984 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12986 default_arch
= "x86_64:32";
12990 as_fatal (_("no compiled in support for 32bit x86_64"));
12994 as_fatal (_("32bit x86_64 is only supported for ELF"));
12999 default_arch
= "i386";
13002 case OPTION_DIVIDE
:
13003 #ifdef SVR4_COMMENT_CHARS
13008 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13010 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13014 i386_comment_chars
= n
;
13020 saved
= xstrdup (arg
);
13022 /* Allow -march=+nosse. */
13028 as_fatal (_("invalid -march= option: `%s'"), arg
);
13029 next
= strchr (arch
, '+');
13032 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13034 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13037 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13040 cpu_arch_name
= cpu_arch
[j
].name
;
13041 cpu_sub_arch_name
= NULL
;
13042 cpu_arch_flags
= cpu_arch
[j
].flags
;
13043 cpu_arch_isa
= cpu_arch
[j
].type
;
13044 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13045 if (!cpu_arch_tune_set
)
13047 cpu_arch_tune
= cpu_arch_isa
;
13048 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13052 else if (*cpu_arch
[j
].name
== '.'
13053 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13055 /* ISA extension. */
13056 i386_cpu_flags flags
;
13058 flags
= cpu_flags_or (cpu_arch_flags
,
13059 cpu_arch
[j
].flags
);
13061 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13063 if (cpu_sub_arch_name
)
13065 char *name
= cpu_sub_arch_name
;
13066 cpu_sub_arch_name
= concat (name
,
13068 (const char *) NULL
);
13072 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13073 cpu_arch_flags
= flags
;
13074 cpu_arch_isa_flags
= flags
;
13078 = cpu_flags_or (cpu_arch_isa_flags
,
13079 cpu_arch
[j
].flags
);
13084 if (j
>= ARRAY_SIZE (cpu_arch
))
13086 /* Disable an ISA extension. */
13087 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13088 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13090 i386_cpu_flags flags
;
13092 flags
= cpu_flags_and_not (cpu_arch_flags
,
13093 cpu_noarch
[j
].flags
);
13094 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13096 if (cpu_sub_arch_name
)
13098 char *name
= cpu_sub_arch_name
;
13099 cpu_sub_arch_name
= concat (arch
,
13100 (const char *) NULL
);
13104 cpu_sub_arch_name
= xstrdup (arch
);
13105 cpu_arch_flags
= flags
;
13106 cpu_arch_isa_flags
= flags
;
13111 if (j
>= ARRAY_SIZE (cpu_noarch
))
13112 j
= ARRAY_SIZE (cpu_arch
);
13115 if (j
>= ARRAY_SIZE (cpu_arch
))
13116 as_fatal (_("invalid -march= option: `%s'"), arg
);
13120 while (next
!= NULL
);
13126 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13127 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13129 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13131 cpu_arch_tune_set
= 1;
13132 cpu_arch_tune
= cpu_arch
[j
].type
;
13133 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13137 if (j
>= ARRAY_SIZE (cpu_arch
))
13138 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13141 case OPTION_MMNEMONIC
:
13142 if (strcasecmp (arg
, "att") == 0)
13143 intel_mnemonic
= 0;
13144 else if (strcasecmp (arg
, "intel") == 0)
13145 intel_mnemonic
= 1;
13147 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13150 case OPTION_MSYNTAX
:
13151 if (strcasecmp (arg
, "att") == 0)
13153 else if (strcasecmp (arg
, "intel") == 0)
13156 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13159 case OPTION_MINDEX_REG
:
13160 allow_index_reg
= 1;
13163 case OPTION_MNAKED_REG
:
13164 allow_naked_reg
= 1;
13167 case OPTION_MSSE2AVX
:
13171 case OPTION_MSSE_CHECK
:
13172 if (strcasecmp (arg
, "error") == 0)
13173 sse_check
= check_error
;
13174 else if (strcasecmp (arg
, "warning") == 0)
13175 sse_check
= check_warning
;
13176 else if (strcasecmp (arg
, "none") == 0)
13177 sse_check
= check_none
;
13179 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13182 case OPTION_MOPERAND_CHECK
:
13183 if (strcasecmp (arg
, "error") == 0)
13184 operand_check
= check_error
;
13185 else if (strcasecmp (arg
, "warning") == 0)
13186 operand_check
= check_warning
;
13187 else if (strcasecmp (arg
, "none") == 0)
13188 operand_check
= check_none
;
13190 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13193 case OPTION_MAVXSCALAR
:
13194 if (strcasecmp (arg
, "128") == 0)
13195 avxscalar
= vex128
;
13196 else if (strcasecmp (arg
, "256") == 0)
13197 avxscalar
= vex256
;
13199 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13202 case OPTION_MVEXWIG
:
13203 if (strcmp (arg
, "0") == 0)
13205 else if (strcmp (arg
, "1") == 0)
13208 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13211 case OPTION_MADD_BND_PREFIX
:
13212 add_bnd_prefix
= 1;
13215 case OPTION_MEVEXLIG
:
13216 if (strcmp (arg
, "128") == 0)
13217 evexlig
= evexl128
;
13218 else if (strcmp (arg
, "256") == 0)
13219 evexlig
= evexl256
;
13220 else if (strcmp (arg
, "512") == 0)
13221 evexlig
= evexl512
;
13223 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13226 case OPTION_MEVEXRCIG
:
13227 if (strcmp (arg
, "rne") == 0)
13229 else if (strcmp (arg
, "rd") == 0)
13231 else if (strcmp (arg
, "ru") == 0)
13233 else if (strcmp (arg
, "rz") == 0)
13236 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13239 case OPTION_MEVEXWIG
:
13240 if (strcmp (arg
, "0") == 0)
13242 else if (strcmp (arg
, "1") == 0)
13245 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13248 # if defined (TE_PE) || defined (TE_PEP)
13249 case OPTION_MBIG_OBJ
:
13254 case OPTION_MOMIT_LOCK_PREFIX
:
13255 if (strcasecmp (arg
, "yes") == 0)
13256 omit_lock_prefix
= 1;
13257 else if (strcasecmp (arg
, "no") == 0)
13258 omit_lock_prefix
= 0;
13260 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13263 case OPTION_MFENCE_AS_LOCK_ADD
:
13264 if (strcasecmp (arg
, "yes") == 0)
13266 else if (strcasecmp (arg
, "no") == 0)
13269 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13272 case OPTION_MLFENCE_AFTER_LOAD
:
13273 if (strcasecmp (arg
, "yes") == 0)
13274 lfence_after_load
= 1;
13275 else if (strcasecmp (arg
, "no") == 0)
13276 lfence_after_load
= 0;
13278 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13281 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13282 if (strcasecmp (arg
, "all") == 0)
13284 lfence_before_indirect_branch
= lfence_branch_all
;
13285 if (lfence_before_ret
== lfence_before_ret_none
)
13286 lfence_before_ret
= lfence_before_ret_shl
;
13288 else if (strcasecmp (arg
, "memory") == 0)
13289 lfence_before_indirect_branch
= lfence_branch_memory
;
13290 else if (strcasecmp (arg
, "register") == 0)
13291 lfence_before_indirect_branch
= lfence_branch_register
;
13292 else if (strcasecmp (arg
, "none") == 0)
13293 lfence_before_indirect_branch
= lfence_branch_none
;
13295 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13299 case OPTION_MLFENCE_BEFORE_RET
:
13300 if (strcasecmp (arg
, "or") == 0)
13301 lfence_before_ret
= lfence_before_ret_or
;
13302 else if (strcasecmp (arg
, "not") == 0)
13303 lfence_before_ret
= lfence_before_ret_not
;
13304 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13305 lfence_before_ret
= lfence_before_ret_shl
;
13306 else if (strcasecmp (arg
, "none") == 0)
13307 lfence_before_ret
= lfence_before_ret_none
;
13309 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13313 case OPTION_MRELAX_RELOCATIONS
:
13314 if (strcasecmp (arg
, "yes") == 0)
13315 generate_relax_relocations
= 1;
13316 else if (strcasecmp (arg
, "no") == 0)
13317 generate_relax_relocations
= 0;
13319 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13322 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13325 long int align
= strtoul (arg
, &end
, 0);
13330 align_branch_power
= 0;
13333 else if (align
>= 16)
13336 for (align_power
= 0;
13338 align
>>= 1, align_power
++)
13340 /* Limit alignment power to 31. */
13341 if (align
== 1 && align_power
< 32)
13343 align_branch_power
= align_power
;
13348 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13352 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13355 int align
= strtoul (arg
, &end
, 0);
13356 /* Some processors only support 5 prefixes. */
13357 if (*end
== '\0' && align
>= 0 && align
< 6)
13359 align_branch_prefix_size
= align
;
13362 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13367 case OPTION_MALIGN_BRANCH
:
13369 saved
= xstrdup (arg
);
13373 next
= strchr (type
, '+');
13376 if (strcasecmp (type
, "jcc") == 0)
13377 align_branch
|= align_branch_jcc_bit
;
13378 else if (strcasecmp (type
, "fused") == 0)
13379 align_branch
|= align_branch_fused_bit
;
13380 else if (strcasecmp (type
, "jmp") == 0)
13381 align_branch
|= align_branch_jmp_bit
;
13382 else if (strcasecmp (type
, "call") == 0)
13383 align_branch
|= align_branch_call_bit
;
13384 else if (strcasecmp (type
, "ret") == 0)
13385 align_branch
|= align_branch_ret_bit
;
13386 else if (strcasecmp (type
, "indirect") == 0)
13387 align_branch
|= align_branch_indirect_bit
;
13389 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13392 while (next
!= NULL
);
13396 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13397 align_branch_power
= 5;
13398 align_branch_prefix_size
= 5;
13399 align_branch
= (align_branch_jcc_bit
13400 | align_branch_fused_bit
13401 | align_branch_jmp_bit
);
13404 case OPTION_MAMD64
:
13408 case OPTION_MINTEL64
:
13416 /* Turn off -Os. */
13417 optimize_for_space
= 0;
13419 else if (*arg
== 's')
13421 optimize_for_space
= 1;
13422 /* Turn on all encoding optimizations. */
13423 optimize
= INT_MAX
;
13427 optimize
= atoi (arg
);
13428 /* Turn off -Os. */
13429 optimize_for_space
= 0;
13439 #define MESSAGE_TEMPLATE \
13443 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13444 int *left_p
, const char *name
, int len
)
13446 int size
= sizeof (MESSAGE_TEMPLATE
);
13447 int left
= *left_p
;
13449 /* Reserve 2 spaces for ", " or ",\0" */
13452 /* Check if there is any room. */
13460 p
= mempcpy (p
, name
, len
);
13464 /* Output the current message now and start a new one. */
13467 fprintf (stream
, "%s\n", message
);
13469 left
= size
- (start
- message
) - len
- 2;
13471 gas_assert (left
>= 0);
13473 p
= mempcpy (p
, name
, len
);
13481 show_arch (FILE *stream
, int ext
, int check
)
13483 static char message
[] = MESSAGE_TEMPLATE
;
13484 char *start
= message
+ 27;
13486 int size
= sizeof (MESSAGE_TEMPLATE
);
13493 left
= size
- (start
- message
);
13494 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13496 /* Should it be skipped? */
13497 if (cpu_arch
[j
].skip
)
13500 name
= cpu_arch
[j
].name
;
13501 len
= cpu_arch
[j
].len
;
13504 /* It is an extension. Skip if we aren't asked to show it. */
13515 /* It is an processor. Skip if we show only extension. */
13518 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13520 /* It is an impossible processor - skip. */
13524 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13527 /* Display disabled extensions. */
13529 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13531 name
= cpu_noarch
[j
].name
;
13532 len
= cpu_noarch
[j
].len
;
13533 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13538 fprintf (stream
, "%s\n", message
);
13542 md_show_usage (FILE *stream
)
13544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13545 fprintf (stream
, _("\
13546 -Qy, -Qn ignored\n\
13547 -V print assembler version number\n\
13550 fprintf (stream
, _("\
13551 -n Do not optimize code alignment\n\
13552 -q quieten some warnings\n"));
13553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13554 fprintf (stream
, _("\
13557 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13558 || defined (TE_PE) || defined (TE_PEP))
13559 fprintf (stream
, _("\
13560 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13562 #ifdef SVR4_COMMENT_CHARS
13563 fprintf (stream
, _("\
13564 --divide do not treat `/' as a comment character\n"));
13566 fprintf (stream
, _("\
13567 --divide ignored\n"));
13569 fprintf (stream
, _("\
13570 -march=CPU[,+EXTENSION...]\n\
13571 generate code for CPU and EXTENSION, CPU is one of:\n"));
13572 show_arch (stream
, 0, 1);
13573 fprintf (stream
, _("\
13574 EXTENSION is combination of:\n"));
13575 show_arch (stream
, 1, 0);
13576 fprintf (stream
, _("\
13577 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13578 show_arch (stream
, 0, 0);
13579 fprintf (stream
, _("\
13580 -msse2avx encode SSE instructions with VEX prefix\n"));
13581 fprintf (stream
, _("\
13582 -msse-check=[none|error|warning] (default: warning)\n\
13583 check SSE instructions\n"));
13584 fprintf (stream
, _("\
13585 -moperand-check=[none|error|warning] (default: warning)\n\
13586 check operand combinations for validity\n"));
13587 fprintf (stream
, _("\
13588 -mavxscalar=[128|256] (default: 128)\n\
13589 encode scalar AVX instructions with specific vector\n\
13591 fprintf (stream
, _("\
13592 -mvexwig=[0|1] (default: 0)\n\
13593 encode VEX instructions with specific VEX.W value\n\
13594 for VEX.W bit ignored instructions\n"));
13595 fprintf (stream
, _("\
13596 -mevexlig=[128|256|512] (default: 128)\n\
13597 encode scalar EVEX instructions with specific vector\n\
13599 fprintf (stream
, _("\
13600 -mevexwig=[0|1] (default: 0)\n\
13601 encode EVEX instructions with specific EVEX.W value\n\
13602 for EVEX.W bit ignored instructions\n"));
13603 fprintf (stream
, _("\
13604 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13605 encode EVEX instructions with specific EVEX.RC value\n\
13606 for SAE-only ignored instructions\n"));
13607 fprintf (stream
, _("\
13608 -mmnemonic=[att|intel] "));
13609 if (SYSV386_COMPAT
)
13610 fprintf (stream
, _("(default: att)\n"));
13612 fprintf (stream
, _("(default: intel)\n"));
13613 fprintf (stream
, _("\
13614 use AT&T/Intel mnemonic\n"));
13615 fprintf (stream
, _("\
13616 -msyntax=[att|intel] (default: att)\n\
13617 use AT&T/Intel syntax\n"));
13618 fprintf (stream
, _("\
13619 -mindex-reg support pseudo index registers\n"));
13620 fprintf (stream
, _("\
13621 -mnaked-reg don't require `%%' prefix for registers\n"));
13622 fprintf (stream
, _("\
13623 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13625 fprintf (stream
, _("\
13626 -mshared disable branch optimization for shared code\n"));
13627 fprintf (stream
, _("\
13628 -mx86-used-note=[no|yes] "));
13629 if (DEFAULT_X86_USED_NOTE
)
13630 fprintf (stream
, _("(default: yes)\n"));
13632 fprintf (stream
, _("(default: no)\n"));
13633 fprintf (stream
, _("\
13634 generate x86 used ISA and feature properties\n"));
13636 #if defined (TE_PE) || defined (TE_PEP)
13637 fprintf (stream
, _("\
13638 -mbig-obj generate big object files\n"));
13640 fprintf (stream
, _("\
13641 -momit-lock-prefix=[no|yes] (default: no)\n\
13642 strip all lock prefixes\n"));
13643 fprintf (stream
, _("\
13644 -mfence-as-lock-add=[no|yes] (default: no)\n\
13645 encode lfence, mfence and sfence as\n\
13646 lock addl $0x0, (%%{re}sp)\n"));
13647 fprintf (stream
, _("\
13648 -mrelax-relocations=[no|yes] "));
13649 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13650 fprintf (stream
, _("(default: yes)\n"));
13652 fprintf (stream
, _("(default: no)\n"));
13653 fprintf (stream
, _("\
13654 generate relax relocations\n"));
13655 fprintf (stream
, _("\
13656 -malign-branch-boundary=NUM (default: 0)\n\
13657 align branches within NUM byte boundary\n"));
13658 fprintf (stream
, _("\
13659 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13660 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13662 specify types of branches to align\n"));
13663 fprintf (stream
, _("\
13664 -malign-branch-prefix-size=NUM (default: 5)\n\
13665 align branches with NUM prefixes per instruction\n"));
13666 fprintf (stream
, _("\
13667 -mbranches-within-32B-boundaries\n\
13668 align branches within 32 byte boundary\n"));
13669 fprintf (stream
, _("\
13670 -mlfence-after-load=[no|yes] (default: no)\n\
13671 generate lfence after load\n"));
13672 fprintf (stream
, _("\
13673 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13674 generate lfence before indirect near branch\n"));
13675 fprintf (stream
, _("\
13676 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13677 generate lfence before ret\n"));
13678 fprintf (stream
, _("\
13679 -mamd64 accept only AMD64 ISA [default]\n"));
13680 fprintf (stream
, _("\
13681 -mintel64 accept only Intel64 ISA\n"));
13684 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13685 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13686 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13688 /* Pick the target format to use. */
13691 i386_target_format (void)
13693 if (!strncmp (default_arch
, "x86_64", 6))
13695 update_code_flag (CODE_64BIT
, 1);
13696 if (default_arch
[6] == '\0')
13697 x86_elf_abi
= X86_64_ABI
;
13699 x86_elf_abi
= X86_64_X32_ABI
;
13701 else if (!strcmp (default_arch
, "i386"))
13702 update_code_flag (CODE_32BIT
, 1);
13703 else if (!strcmp (default_arch
, "iamcu"))
13705 update_code_flag (CODE_32BIT
, 1);
13706 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13708 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13709 cpu_arch_name
= "iamcu";
13710 cpu_sub_arch_name
= NULL
;
13711 cpu_arch_flags
= iamcu_flags
;
13712 cpu_arch_isa
= PROCESSOR_IAMCU
;
13713 cpu_arch_isa_flags
= iamcu_flags
;
13714 if (!cpu_arch_tune_set
)
13716 cpu_arch_tune
= cpu_arch_isa
;
13717 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13720 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13721 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13725 as_fatal (_("unknown architecture"));
13727 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13728 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13729 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13730 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13732 switch (OUTPUT_FLAVOR
)
13734 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13735 case bfd_target_aout_flavour
:
13736 return AOUT_TARGET_FORMAT
;
13738 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13739 # if defined (TE_PE) || defined (TE_PEP)
13740 case bfd_target_coff_flavour
:
13741 if (flag_code
== CODE_64BIT
)
13742 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13744 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13745 # elif defined (TE_GO32)
13746 case bfd_target_coff_flavour
:
13747 return "coff-go32";
13749 case bfd_target_coff_flavour
:
13750 return "coff-i386";
13753 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13754 case bfd_target_elf_flavour
:
13756 const char *format
;
13758 switch (x86_elf_abi
)
13761 format
= ELF_TARGET_FORMAT
;
13763 tls_get_addr
= "___tls_get_addr";
13767 use_rela_relocations
= 1;
13770 tls_get_addr
= "__tls_get_addr";
13772 format
= ELF_TARGET_FORMAT64
;
13774 case X86_64_X32_ABI
:
13775 use_rela_relocations
= 1;
13778 tls_get_addr
= "__tls_get_addr";
13780 disallow_64bit_reloc
= 1;
13781 format
= ELF_TARGET_FORMAT32
;
13784 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13786 if (x86_elf_abi
!= X86_64_ABI
)
13787 as_fatal (_("Intel L1OM is 64bit only"));
13788 return ELF_TARGET_L1OM_FORMAT
;
13790 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13792 if (x86_elf_abi
!= X86_64_ABI
)
13793 as_fatal (_("Intel K1OM is 64bit only"));
13794 return ELF_TARGET_K1OM_FORMAT
;
13796 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13798 if (x86_elf_abi
!= I386_ABI
)
13799 as_fatal (_("Intel MCU is 32bit only"));
13800 return ELF_TARGET_IAMCU_FORMAT
;
13806 #if defined (OBJ_MACH_O)
13807 case bfd_target_mach_o_flavour
:
13808 if (flag_code
== CODE_64BIT
)
13810 use_rela_relocations
= 1;
13812 return "mach-o-x86-64";
13815 return "mach-o-i386";
13823 #endif /* OBJ_MAYBE_ more than one */
13826 md_undefined_symbol (char *name
)
13828 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13829 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13830 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13831 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13835 if (symbol_find (name
))
13836 as_bad (_("GOT already in symbol table"));
13837 GOT_symbol
= symbol_new (name
, undefined_section
,
13838 &zero_address_frag
, 0);
13845 /* Round up a section size to the appropriate boundary. */
13848 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13850 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13851 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13853 /* For a.out, force the section size to be aligned. If we don't do
13854 this, BFD will align it for us, but it will not write out the
13855 final bytes of the section. This may be a bug in BFD, but it is
13856 easier to fix it here since that is how the other a.out targets
13860 align
= bfd_section_alignment (segment
);
13861 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13868 /* On the i386, PC-relative offsets are relative to the start of the
13869 next instruction. That is, the address of the offset, plus its
13870 size, since the offset is always the last part of the insn. */
13873 md_pcrel_from (fixS
*fixP
)
13875 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13881 s_bss (int ignore ATTRIBUTE_UNUSED
)
13885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13887 obj_elf_section_change_hook ();
13889 temp
= get_absolute_expression ();
13890 subseg_set (bss_section
, (subsegT
) temp
);
13891 demand_empty_rest_of_line ();
13896 /* Remember constant directive. */
13899 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13901 if (last_insn
.kind
!= last_insn_directive
13902 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13904 last_insn
.seg
= now_seg
;
13905 last_insn
.kind
= last_insn_directive
;
13906 last_insn
.name
= "constant directive";
13907 last_insn
.file
= as_where (&last_insn
.line
);
13908 if (lfence_before_ret
!= lfence_before_ret_none
)
13910 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13911 as_warn (_("constant directive skips -mlfence-before-ret "
13912 "and -mlfence-before-indirect-branch"));
13914 as_warn (_("constant directive skips -mlfence-before-ret"));
13916 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13917 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13922 i386_validate_fix (fixS
*fixp
)
13924 if (fixp
->fx_subsy
)
13926 if (fixp
->fx_subsy
== GOT_symbol
)
13928 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13933 if (fixp
->fx_tcbit2
)
13934 fixp
->fx_r_type
= (fixp
->fx_tcbit
13935 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13936 : BFD_RELOC_X86_64_GOTPCRELX
);
13939 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13944 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13946 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13948 fixp
->fx_subsy
= 0;
13951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13954 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13955 to section. Since PLT32 relocation must be against symbols,
13956 turn such PLT32 relocation into PC32 relocation. */
13958 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13959 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13960 && symbol_section_p (fixp
->fx_addsy
))
13961 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13964 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13965 && fixp
->fx_tcbit2
)
13966 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13973 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13976 bfd_reloc_code_real_type code
;
13978 switch (fixp
->fx_r_type
)
13980 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13981 case BFD_RELOC_SIZE32
:
13982 case BFD_RELOC_SIZE64
:
13983 if (S_IS_DEFINED (fixp
->fx_addsy
)
13984 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13986 /* Resolve size relocation against local symbol to size of
13987 the symbol plus addend. */
13988 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13989 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13990 && !fits_in_unsigned_long (value
))
13991 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13992 _("symbol size computation overflow"));
13993 fixp
->fx_addsy
= NULL
;
13994 fixp
->fx_subsy
= NULL
;
13995 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13999 /* Fall through. */
14001 case BFD_RELOC_X86_64_PLT32
:
14002 case BFD_RELOC_X86_64_GOT32
:
14003 case BFD_RELOC_X86_64_GOTPCREL
:
14004 case BFD_RELOC_X86_64_GOTPCRELX
:
14005 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14006 case BFD_RELOC_386_PLT32
:
14007 case BFD_RELOC_386_GOT32
:
14008 case BFD_RELOC_386_GOT32X
:
14009 case BFD_RELOC_386_GOTOFF
:
14010 case BFD_RELOC_386_GOTPC
:
14011 case BFD_RELOC_386_TLS_GD
:
14012 case BFD_RELOC_386_TLS_LDM
:
14013 case BFD_RELOC_386_TLS_LDO_32
:
14014 case BFD_RELOC_386_TLS_IE_32
:
14015 case BFD_RELOC_386_TLS_IE
:
14016 case BFD_RELOC_386_TLS_GOTIE
:
14017 case BFD_RELOC_386_TLS_LE_32
:
14018 case BFD_RELOC_386_TLS_LE
:
14019 case BFD_RELOC_386_TLS_GOTDESC
:
14020 case BFD_RELOC_386_TLS_DESC_CALL
:
14021 case BFD_RELOC_X86_64_TLSGD
:
14022 case BFD_RELOC_X86_64_TLSLD
:
14023 case BFD_RELOC_X86_64_DTPOFF32
:
14024 case BFD_RELOC_X86_64_DTPOFF64
:
14025 case BFD_RELOC_X86_64_GOTTPOFF
:
14026 case BFD_RELOC_X86_64_TPOFF32
:
14027 case BFD_RELOC_X86_64_TPOFF64
:
14028 case BFD_RELOC_X86_64_GOTOFF64
:
14029 case BFD_RELOC_X86_64_GOTPC32
:
14030 case BFD_RELOC_X86_64_GOT64
:
14031 case BFD_RELOC_X86_64_GOTPCREL64
:
14032 case BFD_RELOC_X86_64_GOTPC64
:
14033 case BFD_RELOC_X86_64_GOTPLT64
:
14034 case BFD_RELOC_X86_64_PLTOFF64
:
14035 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14036 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14037 case BFD_RELOC_RVA
:
14038 case BFD_RELOC_VTABLE_ENTRY
:
14039 case BFD_RELOC_VTABLE_INHERIT
:
14041 case BFD_RELOC_32_SECREL
:
14043 code
= fixp
->fx_r_type
;
14045 case BFD_RELOC_X86_64_32S
:
14046 if (!fixp
->fx_pcrel
)
14048 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14049 code
= fixp
->fx_r_type
;
14052 /* Fall through. */
14054 if (fixp
->fx_pcrel
)
14056 switch (fixp
->fx_size
)
14059 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14060 _("can not do %d byte pc-relative relocation"),
14062 code
= BFD_RELOC_32_PCREL
;
14064 case 1: code
= BFD_RELOC_8_PCREL
; break;
14065 case 2: code
= BFD_RELOC_16_PCREL
; break;
14066 case 4: code
= BFD_RELOC_32_PCREL
; break;
14068 case 8: code
= BFD_RELOC_64_PCREL
; break;
14074 switch (fixp
->fx_size
)
14077 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14078 _("can not do %d byte relocation"),
14080 code
= BFD_RELOC_32
;
14082 case 1: code
= BFD_RELOC_8
; break;
14083 case 2: code
= BFD_RELOC_16
; break;
14084 case 4: code
= BFD_RELOC_32
; break;
14086 case 8: code
= BFD_RELOC_64
; break;
14093 if ((code
== BFD_RELOC_32
14094 || code
== BFD_RELOC_32_PCREL
14095 || code
== BFD_RELOC_X86_64_32S
)
14097 && fixp
->fx_addsy
== GOT_symbol
)
14100 code
= BFD_RELOC_386_GOTPC
;
14102 code
= BFD_RELOC_X86_64_GOTPC32
;
14104 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14106 && fixp
->fx_addsy
== GOT_symbol
)
14108 code
= BFD_RELOC_X86_64_GOTPC64
;
14111 rel
= XNEW (arelent
);
14112 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14113 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14115 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14117 if (!use_rela_relocations
)
14119 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14120 vtable entry to be used in the relocation's section offset. */
14121 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14122 rel
->address
= fixp
->fx_offset
;
14123 #if defined (OBJ_COFF) && defined (TE_PE)
14124 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14125 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14130 /* Use the rela in 64bit mode. */
14133 if (disallow_64bit_reloc
)
14136 case BFD_RELOC_X86_64_DTPOFF64
:
14137 case BFD_RELOC_X86_64_TPOFF64
:
14138 case BFD_RELOC_64_PCREL
:
14139 case BFD_RELOC_X86_64_GOTOFF64
:
14140 case BFD_RELOC_X86_64_GOT64
:
14141 case BFD_RELOC_X86_64_GOTPCREL64
:
14142 case BFD_RELOC_X86_64_GOTPC64
:
14143 case BFD_RELOC_X86_64_GOTPLT64
:
14144 case BFD_RELOC_X86_64_PLTOFF64
:
14145 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14146 _("cannot represent relocation type %s in x32 mode"),
14147 bfd_get_reloc_code_name (code
));
14153 if (!fixp
->fx_pcrel
)
14154 rel
->addend
= fixp
->fx_offset
;
14158 case BFD_RELOC_X86_64_PLT32
:
14159 case BFD_RELOC_X86_64_GOT32
:
14160 case BFD_RELOC_X86_64_GOTPCREL
:
14161 case BFD_RELOC_X86_64_GOTPCRELX
:
14162 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14163 case BFD_RELOC_X86_64_TLSGD
:
14164 case BFD_RELOC_X86_64_TLSLD
:
14165 case BFD_RELOC_X86_64_GOTTPOFF
:
14166 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14167 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14168 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14171 rel
->addend
= (section
->vma
14173 + fixp
->fx_addnumber
14174 + md_pcrel_from (fixp
));
14179 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14180 if (rel
->howto
== NULL
)
14182 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14183 _("cannot represent relocation type %s"),
14184 bfd_get_reloc_code_name (code
));
14185 /* Set howto to a garbage value so that we can keep going. */
14186 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14187 gas_assert (rel
->howto
!= NULL
);
14193 #include "tc-i386-intel.c"
14196 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14198 int saved_naked_reg
;
14199 char saved_register_dot
;
14201 saved_naked_reg
= allow_naked_reg
;
14202 allow_naked_reg
= 1;
14203 saved_register_dot
= register_chars
['.'];
14204 register_chars
['.'] = '.';
14205 allow_pseudo_reg
= 1;
14206 expression_and_evaluate (exp
);
14207 allow_pseudo_reg
= 0;
14208 register_chars
['.'] = saved_register_dot
;
14209 allow_naked_reg
= saved_naked_reg
;
14211 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14213 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14215 exp
->X_op
= O_constant
;
14216 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14217 .dw2_regnum
[flag_code
>> 1];
14220 exp
->X_op
= O_illegal
;
14225 tc_x86_frame_initial_instructions (void)
14227 static unsigned int sp_regno
[2];
14229 if (!sp_regno
[flag_code
>> 1])
14231 char *saved_input
= input_line_pointer
;
14232 char sp
[][4] = {"esp", "rsp"};
14235 input_line_pointer
= sp
[flag_code
>> 1];
14236 tc_x86_parse_to_dw2regnum (&exp
);
14237 gas_assert (exp
.X_op
== O_constant
);
14238 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14239 input_line_pointer
= saved_input
;
14242 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14243 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14247 x86_dwarf2_addr_size (void)
14249 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14250 if (x86_elf_abi
== X86_64_X32_ABI
)
14253 return bfd_arch_bits_per_address (stdoutput
) / 8;
14257 i386_elf_section_type (const char *str
, size_t len
)
14259 if (flag_code
== CODE_64BIT
14260 && len
== sizeof ("unwind") - 1
14261 && strncmp (str
, "unwind", 6) == 0)
14262 return SHT_X86_64_UNWIND
;
14269 i386_solaris_fix_up_eh_frame (segT sec
)
14271 if (flag_code
== CODE_64BIT
)
14272 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14278 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14282 exp
.X_op
= O_secrel
;
14283 exp
.X_add_symbol
= symbol
;
14284 exp
.X_add_number
= 0;
14285 emit_expr (&exp
, size
);
14289 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14290 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14293 x86_64_section_letter (int letter
, const char **ptr_msg
)
14295 if (flag_code
== CODE_64BIT
)
14298 return SHF_X86_64_LARGE
;
14300 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14303 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14308 x86_64_section_word (char *str
, size_t len
)
14310 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14311 return SHF_X86_64_LARGE
;
14317 handle_large_common (int small ATTRIBUTE_UNUSED
)
14319 if (flag_code
!= CODE_64BIT
)
14321 s_comm_internal (0, elf_common_parse
);
14322 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14326 static segT lbss_section
;
14327 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14328 asection
*saved_bss_section
= bss_section
;
14330 if (lbss_section
== NULL
)
14332 flagword applicable
;
14333 segT seg
= now_seg
;
14334 subsegT subseg
= now_subseg
;
14336 /* The .lbss section is for local .largecomm symbols. */
14337 lbss_section
= subseg_new (".lbss", 0);
14338 applicable
= bfd_applicable_section_flags (stdoutput
);
14339 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14340 seg_info (lbss_section
)->bss
= 1;
14342 subseg_set (seg
, subseg
);
14345 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14346 bss_section
= lbss_section
;
14348 s_comm_internal (0, elf_common_parse
);
14350 elf_com_section_ptr
= saved_com_section_ptr
;
14351 bss_section
= saved_bss_section
;
14354 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */