1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
378 /* Use MASK state. */
382 /* Has GOTPC or TLS relocation. */
383 bfd_boolean has_gotpc_tls_reloc
;
385 /* RM and SIB are the modrm byte and the sib byte where the
386 addressing modes of this insn are encoded. */
393 /* Masking attributes. */
394 struct Mask_Operation
*mask
;
396 /* Rounding control and SAE attributes. */
397 struct RC_Operation
*rounding
;
399 /* Broadcasting attributes. */
400 struct Broadcast_Operation
*broadcast
;
402 /* Compressed disp8*N attribute. */
403 unsigned int memshift
;
405 /* Prefer load or store in encoding. */
408 dir_encoding_default
= 0,
414 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
417 disp_encoding_default
= 0,
423 /* Prefer the REX byte in encoding. */
424 bfd_boolean rex_encoding
;
426 /* Disable instruction size optimization. */
427 bfd_boolean no_optimize
;
429 /* How to encode vector instructions. */
432 vex_encoding_default
= 0,
440 const char *rep_prefix
;
443 const char *hle_prefix
;
445 /* Have BND prefix. */
446 const char *bnd_prefix
;
448 /* Have NOTRACK prefix. */
449 const char *notrack_prefix
;
452 enum i386_error error
;
455 typedef struct _i386_insn i386_insn
;
457 /* Link RC type with corresponding string, that'll be looked for in
466 static const struct RC_name RC_NamesTable
[] =
468 { rne
, STRING_COMMA_LEN ("rn-sae") },
469 { rd
, STRING_COMMA_LEN ("rd-sae") },
470 { ru
, STRING_COMMA_LEN ("ru-sae") },
471 { rz
, STRING_COMMA_LEN ("rz-sae") },
472 { saeonly
, STRING_COMMA_LEN ("sae") },
475 /* List of chars besides those in app.c:symbol_chars that can start an
476 operand. Used to prevent the scrubber eating vital white-space. */
477 const char extra_symbol_chars
[] = "*%-([{}"
486 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
487 && !defined (TE_GNU) \
488 && !defined (TE_LINUX) \
489 && !defined (TE_FreeBSD) \
490 && !defined (TE_DragonFly) \
491 && !defined (TE_NetBSD))
492 /* This array holds the chars that always start a comment. If the
493 pre-processor is disabled, these aren't very useful. The option
494 --divide will remove '/' from this list. */
495 const char *i386_comment_chars
= "#/";
496 #define SVR4_COMMENT_CHARS 1
497 #define PREFIX_SEPARATOR '\\'
500 const char *i386_comment_chars
= "#";
501 #define PREFIX_SEPARATOR '/'
504 /* This array holds the chars that only start a comment at the beginning of
505 a line. If the line seems to have the form '# 123 filename'
506 .line and .file directives will appear in the pre-processed output.
507 Note that input_file.c hand checks for '#' at the beginning of the
508 first line of the input file. This is because the compiler outputs
509 #NO_APP at the beginning of its output.
510 Also note that comments started like this one will always work if
511 '/' isn't otherwise defined. */
512 const char line_comment_chars
[] = "#/";
514 const char line_separator_chars
[] = ";";
516 /* Chars that can be used to separate mant from exp in floating point
518 const char EXP_CHARS
[] = "eE";
520 /* Chars that mean this number is a floating point constant
523 const char FLT_CHARS
[] = "fFdDxX";
525 /* Tables for lexical analysis. */
526 static char mnemonic_chars
[256];
527 static char register_chars
[256];
528 static char operand_chars
[256];
529 static char identifier_chars
[256];
530 static char digit_chars
[256];
532 /* Lexical macros. */
533 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
534 #define is_operand_char(x) (operand_chars[(unsigned char) x])
535 #define is_register_char(x) (register_chars[(unsigned char) x])
536 #define is_space_char(x) ((x) == ' ')
537 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
538 #define is_digit_char(x) (digit_chars[(unsigned char) x])
540 /* All non-digit non-letter characters that may occur in an operand. */
541 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
543 /* md_assemble() always leaves the strings it's passed unaltered. To
544 effect this we maintain a stack of saved characters that we've smashed
545 with '\0's (indicating end of strings for various sub-fields of the
546 assembler instruction). */
547 static char save_stack
[32];
548 static char *save_stack_p
;
549 #define END_STRING_AND_SAVE(s) \
550 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
551 #define RESTORE_END_STRING(s) \
552 do { *(s) = *--save_stack_p; } while (0)
554 /* The instruction we're assembling. */
557 /* Possible templates for current insn. */
558 static const templates
*current_templates
;
560 /* Per instruction expressionS buffers: max displacements & immediates. */
561 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
562 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
564 /* Current operand we are working on. */
565 static int this_operand
= -1;
567 /* We support four different modes. FLAG_CODE variable is used to distinguish
575 static enum flag_code flag_code
;
576 static unsigned int object_64bit
;
577 static unsigned int disallow_64bit_reloc
;
578 static int use_rela_relocations
= 0;
579 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
580 static const char *tls_get_addr
;
582 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
583 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
586 /* The ELF ABI to use. */
594 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
597 #if defined (TE_PE) || defined (TE_PEP)
598 /* Use big object file format. */
599 static int use_big_obj
= 0;
602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
603 /* 1 if generating code for a shared library. */
604 static int shared
= 0;
607 /* 1 for intel syntax,
609 static int intel_syntax
= 0;
611 static enum x86_64_isa
613 amd64
= 1, /* AMD64 ISA. */
614 intel64
/* Intel64 ISA. */
617 /* 1 for intel mnemonic,
618 0 if att mnemonic. */
619 static int intel_mnemonic
= !SYSV386_COMPAT
;
621 /* 1 if pseudo registers are permitted. */
622 static int allow_pseudo_reg
= 0;
624 /* 1 if register prefix % not required. */
625 static int allow_naked_reg
= 0;
627 /* 1 if the assembler should add BND prefix for all control-transferring
628 instructions supporting it, even if this prefix wasn't specified
630 static int add_bnd_prefix
= 0;
632 /* 1 if pseudo index register, eiz/riz, is allowed . */
633 static int allow_index_reg
= 0;
635 /* 1 if the assembler should ignore LOCK prefix, even if it was
636 specified explicitly. */
637 static int omit_lock_prefix
= 0;
639 /* 1 if the assembler should encode lfence, mfence, and sfence as
640 "lock addl $0, (%{re}sp)". */
641 static int avoid_fence
= 0;
643 /* 1 if lfence should be inserted after every load. */
644 static int lfence_after_load
= 0;
646 /* Non-zero if lfence should be inserted before indirect branch. */
647 static enum lfence_before_indirect_branch_kind
649 lfence_branch_none
= 0,
650 lfence_branch_register
,
651 lfence_branch_memory
,
654 lfence_before_indirect_branch
;
656 /* Non-zero if lfence should be inserted before ret. */
657 static enum lfence_before_ret_kind
659 lfence_before_ret_none
= 0,
660 lfence_before_ret_not
,
661 lfence_before_ret_or
,
662 lfence_before_ret_shl
666 /* Types of previous instruction is .byte or prefix. */
681 /* 1 if the assembler should generate relax relocations. */
683 static int generate_relax_relocations
684 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
686 static enum check_kind
692 sse_check
, operand_check
= check_warning
;
694 /* Non-zero if branches should be aligned within power of 2 boundary. */
695 static int align_branch_power
= 0;
697 /* Types of branches to align. */
698 enum align_branch_kind
700 align_branch_none
= 0,
701 align_branch_jcc
= 1,
702 align_branch_fused
= 2,
703 align_branch_jmp
= 3,
704 align_branch_call
= 4,
705 align_branch_indirect
= 5,
709 /* Type bits of branches to align. */
710 enum align_branch_bit
712 align_branch_jcc_bit
= 1 << align_branch_jcc
,
713 align_branch_fused_bit
= 1 << align_branch_fused
,
714 align_branch_jmp_bit
= 1 << align_branch_jmp
,
715 align_branch_call_bit
= 1 << align_branch_call
,
716 align_branch_indirect_bit
= 1 << align_branch_indirect
,
717 align_branch_ret_bit
= 1 << align_branch_ret
720 static unsigned int align_branch
= (align_branch_jcc_bit
721 | align_branch_fused_bit
722 | align_branch_jmp_bit
);
724 /* Types of condition jump used by macro-fusion. */
727 mf_jcc_jo
= 0, /* base opcode 0x70 */
728 mf_jcc_jc
, /* base opcode 0x72 */
729 mf_jcc_je
, /* base opcode 0x74 */
730 mf_jcc_jna
, /* base opcode 0x76 */
731 mf_jcc_js
, /* base opcode 0x78 */
732 mf_jcc_jp
, /* base opcode 0x7a */
733 mf_jcc_jl
, /* base opcode 0x7c */
734 mf_jcc_jle
, /* base opcode 0x7e */
737 /* Types of compare flag-modifying insntructions used by macro-fusion. */
740 mf_cmp_test_and
, /* test/cmp */
741 mf_cmp_alu_cmp
, /* add/sub/cmp */
742 mf_cmp_incdec
/* inc/dec */
745 /* The maximum padding size for fused jcc. CMP like instruction can
746 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
748 #define MAX_FUSED_JCC_PADDING_SIZE 20
750 /* The maximum number of prefixes added for an instruction. */
751 static unsigned int align_branch_prefix_size
= 5;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
758 static int optimize
= 0;
761 1. Clear the REX_W bit with register operand if possible.
762 2. Above plus use 128bit vector instruction to clear the full vector
764 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
767 static int optimize_for_space
= 0;
769 /* Register prefix used for error message. */
770 static const char *register_prefix
= "%";
772 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
773 leave, push, and pop instructions so that gcc has the same stack
774 frame as in 32 bit mode. */
775 static char stackop_size
= '\0';
777 /* Non-zero to optimize code alignment. */
778 int optimize_align_code
= 1;
780 /* Non-zero to quieten some warnings. */
781 static int quiet_warnings
= 0;
784 static const char *cpu_arch_name
= NULL
;
785 static char *cpu_sub_arch_name
= NULL
;
787 /* CPU feature flags. */
788 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
790 /* If we have selected a cpu we are generating instructions for. */
791 static int cpu_arch_tune_set
= 0;
793 /* Cpu we are generating instructions for. */
794 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of cpu we are generating instructions for. */
797 static i386_cpu_flags cpu_arch_tune_flags
;
799 /* CPU instruction set architecture used. */
800 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
802 /* CPU feature flags of instruction set architecture used. */
803 i386_cpu_flags cpu_arch_isa_flags
;
805 /* If set, conditional jumps are not automatically promoted to handle
806 larger than a byte offset. */
807 static unsigned int no_cond_jump_promotion
= 0;
809 /* Encode SSE instructions with VEX prefix. */
810 static unsigned int sse2avx
;
812 /* Encode scalar AVX instructions with specific vector length. */
819 /* Encode VEX WIG instructions with specific vex.w. */
826 /* Encode scalar EVEX LIG instructions with specific vector length. */
834 /* Encode EVEX WIG instructions with specific evex.w. */
841 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
842 static enum rc_type evexrcig
= rne
;
844 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
845 static symbolS
*GOT_symbol
;
847 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
848 unsigned int x86_dwarf2_return_column
;
850 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
851 int x86_cie_data_alignment
;
853 /* Interface to relax_segment.
854 There are 3 major relax states for 386 jump insns because the
855 different types of jumps add different sizes to frags when we're
856 figuring out what sort of jump to choose to reach a given label.
858 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
859 branches which are handled by md_estimate_size_before_relax() and
860 i386_generic_table_relax_frag(). */
863 #define UNCOND_JUMP 0
865 #define COND_JUMP86 2
866 #define BRANCH_PADDING 3
867 #define BRANCH_PREFIX 4
868 #define FUSED_JCC_PADDING 5
873 #define SMALL16 (SMALL | CODE16)
875 #define BIG16 (BIG | CODE16)
879 #define INLINE __inline__
885 #define ENCODE_RELAX_STATE(type, size) \
886 ((relax_substateT) (((type) << 2) | (size)))
887 #define TYPE_FROM_RELAX_STATE(s) \
889 #define DISP_SIZE_FROM_RELAX_STATE(s) \
890 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
892 /* This table is used by relax_frag to promote short jumps to long
893 ones where necessary. SMALL (short) jumps may be promoted to BIG
894 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
895 don't allow a short jump in a 32 bit code segment to be promoted to
896 a 16 bit offset jump because it's slower (requires data size
897 prefix), and doesn't work, unless the destination is in the bottom
898 64k of the code segment (The top 16 bits of eip are zeroed). */
900 const relax_typeS md_relax_table
[] =
903 1) most positive reach of this state,
904 2) most negative reach of this state,
905 3) how many bytes this mode will have in the variable part of the frag
906 4) which index into the table to try if we can't fit into this one. */
908 /* UNCOND_JUMP states. */
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
911 /* dword jmp adds 4 bytes to frag:
912 0 extra opcode bytes, 4 displacement bytes. */
914 /* word jmp adds 2 byte2 to frag:
915 0 extra opcode bytes, 2 displacement bytes. */
918 /* COND_JUMP states. */
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
921 /* dword conditionals adds 5 bytes to frag:
922 1 extra opcode byte, 4 displacement bytes. */
924 /* word conditionals add 3 bytes to frag:
925 1 extra opcode byte, 2 displacement bytes. */
928 /* COND_JUMP86 states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
931 /* dword conditionals adds 5 bytes to frag:
932 1 extra opcode byte, 4 displacement bytes. */
934 /* word conditionals add 4 bytes to frag:
935 1 displacement byte and a 3 byte long branch insn. */
939 static const arch_entry cpu_arch
[] =
941 /* Do not replace the first two entries - i386_target_format()
942 relies on them being there in this order. */
943 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
944 CPU_GENERIC32_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
946 CPU_GENERIC64_FLAGS
, 0 },
947 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
955 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
957 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
959 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
963 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
964 CPU_PENTIUMPRO_FLAGS
, 0 },
965 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
969 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
971 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
973 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
974 CPU_NOCONA_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
979 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 1 },
981 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
982 CPU_CORE2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
984 CPU_COREI7_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
987 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
989 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
990 CPU_IAMCU_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
995 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
996 CPU_ATHLON_FLAGS
, 0 },
997 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1003 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1004 CPU_AMDFAM10_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1006 CPU_BDVER1_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1008 CPU_BDVER2_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1010 CPU_BDVER3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1012 CPU_BDVER4_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER1_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1016 CPU_ZNVER2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1018 CPU_ZNVER3_FLAGS
, 0 },
1019 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1020 CPU_BTVER1_FLAGS
, 0 },
1021 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1022 CPU_BTVER2_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1024 CPU_8087_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1032 CPU_CMOV_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1034 CPU_FXSR_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE2_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4A_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1046 CPU_SSSE3_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_1_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1050 CPU_SSE4_2_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1052 CPU_SSE4_2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1055 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX2_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512F_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512CD_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512ER_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512PF_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512DQ_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1068 CPU_AVX512BW_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1070 CPU_AVX512VL_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1074 CPU_VMFUNC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVEOPT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1082 CPU_XSAVEC_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1084 CPU_XSAVES_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1088 CPU_PCLMUL_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1090 CPU_PCLMUL_FLAGS
, 1 },
1091 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1092 CPU_FSGSBASE_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1094 CPU_RDRND_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1096 CPU_F16C_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1098 CPU_BMI2_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1102 CPU_FMA4_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1107 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1108 CPU_MOVBE_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1110 CPU_CX16_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1114 CPU_LZCNT_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1116 CPU_POPCNT_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1121 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1122 CPU_INVPCID_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1124 CPU_CLFLUSH_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1127 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1128 CPU_SYSCALL_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1130 CPU_RDTSCP_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1132 CPU_3DNOW_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1134 CPU_3DNOWA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1136 CPU_PADLOCK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1138 CPU_SVME_FLAGS
, 1 },
1139 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1140 CPU_SVME_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1142 CPU_SSE4A_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1149 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1152 CPU_RDSEED_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1154 CPU_PRFCHW_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1156 CPU_SMAP_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1162 CPU_CLFLUSHOPT_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1164 CPU_PREFETCHWT1_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1167 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1168 CPU_CLWB_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512IFMA_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512VBMI_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_VBMI2_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_VNNI_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_BITALG_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1186 CPU_AVX_VNNI_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1188 CPU_CLZERO_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1190 CPU_MWAITX_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1192 CPU_OSPKE_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1194 CPU_RDPID_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1196 CPU_PTWRITE_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1199 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1200 CPU_SHSTK_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1202 CPU_GFNI_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1204 CPU_VAES_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1206 CPU_VPCLMULQDQ_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1208 CPU_WBNOINVD_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1210 CPU_PCONFIG_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1212 CPU_WAITPKG_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1214 CPU_CLDEMOTE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1216 CPU_AMX_INT8_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1218 CPU_AMX_BF16_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1220 CPU_AMX_TILE_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1222 CPU_MOVDIRI_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1224 CPU_MOVDIR64B_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1226 CPU_AVX512_BF16_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1228 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1231 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1232 CPU_ENQCMD_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1234 CPU_SERIALIZE_FLAGS
, 0 },
1235 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1236 CPU_RDPRU_FLAGS
, 0 },
1237 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1238 CPU_MCOMMIT_FLAGS
, 0 },
1239 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1240 CPU_SEV_ES_FLAGS
, 0 },
1241 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1242 CPU_TSXLDTRK_FLAGS
, 0 },
1243 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1245 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1246 CPU_WIDEKL_FLAGS
, 0 },
1247 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1248 CPU_UINTR_FLAGS
, 0 },
1249 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1250 CPU_HRESET_FLAGS
, 0 },
1253 static const noarch_entry cpu_noarch
[] =
1255 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1256 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1257 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1258 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1259 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1260 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1261 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1262 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1263 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1264 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1266 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1269 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1288 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1289 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1290 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1291 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1292 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1293 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1294 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1295 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1296 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1297 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1298 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1299 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1300 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1301 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1302 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1303 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1304 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1305 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1309 /* Like s_lcomm_internal in gas/read.c but the alignment string
1310 is allowed to be optional. */
1313 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1320 && *input_line_pointer
== ',')
1322 align
= parse_align (needs_align
- 1);
1324 if (align
== (addressT
) -1)
1339 bss_alloc (symbolP
, size
, align
);
1344 pe_lcomm (int needs_align
)
1346 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1350 const pseudo_typeS md_pseudo_table
[] =
1352 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1353 {"align", s_align_bytes
, 0},
1355 {"align", s_align_ptwo
, 0},
1357 {"arch", set_cpu_arch
, 0},
1361 {"lcomm", pe_lcomm
, 1},
1363 {"ffloat", float_cons
, 'f'},
1364 {"dfloat", float_cons
, 'd'},
1365 {"tfloat", float_cons
, 'x'},
1367 {"slong", signed_cons
, 4},
1368 {"noopt", s_ignore
, 0},
1369 {"optim", s_ignore
, 0},
1370 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1371 {"code16", set_code_flag
, CODE_16BIT
},
1372 {"code32", set_code_flag
, CODE_32BIT
},
1374 {"code64", set_code_flag
, CODE_64BIT
},
1376 {"intel_syntax", set_intel_syntax
, 1},
1377 {"att_syntax", set_intel_syntax
, 0},
1378 {"intel_mnemonic", set_intel_mnemonic
, 1},
1379 {"att_mnemonic", set_intel_mnemonic
, 0},
1380 {"allow_index_reg", set_allow_index_reg
, 1},
1381 {"disallow_index_reg", set_allow_index_reg
, 0},
1382 {"sse_check", set_check
, 0},
1383 {"operand_check", set_check
, 1},
1384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1385 {"largecomm", handle_large_common
, 0},
1387 {"file", dwarf2_directive_file
, 0},
1388 {"loc", dwarf2_directive_loc
, 0},
1389 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1392 {"secrel32", pe_directive_secrel
, 0},
1397 /* For interface with expression (). */
1398 extern char *input_line_pointer
;
1400 /* Hash table for instruction mnemonic lookup. */
1401 static htab_t op_hash
;
1403 /* Hash table for register lookup. */
1404 static htab_t reg_hash
;
1406 /* Various efficient no-op patterns for aligning code labels.
1407 Note: Don't try to assemble the instructions in the comments.
1408 0L and 0w are not legal. */
1409 static const unsigned char f32_1
[] =
1411 static const unsigned char f32_2
[] =
1412 {0x66,0x90}; /* xchg %ax,%ax */
1413 static const unsigned char f32_3
[] =
1414 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1415 static const unsigned char f32_4
[] =
1416 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1417 static const unsigned char f32_6
[] =
1418 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1419 static const unsigned char f32_7
[] =
1420 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1421 static const unsigned char f16_3
[] =
1422 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1423 static const unsigned char f16_4
[] =
1424 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1425 static const unsigned char jump_disp8
[] =
1426 {0xeb}; /* jmp disp8 */
1427 static const unsigned char jump32_disp32
[] =
1428 {0xe9}; /* jmp disp32 */
1429 static const unsigned char jump16_disp32
[] =
1430 {0x66,0xe9}; /* jmp disp32 */
1431 /* 32-bit NOPs patterns. */
1432 static const unsigned char *const f32_patt
[] = {
1433 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1435 /* 16-bit NOPs patterns. */
1436 static const unsigned char *const f16_patt
[] = {
1437 f32_1
, f32_2
, f16_3
, f16_4
1439 /* nopl (%[re]ax) */
1440 static const unsigned char alt_3
[] =
1442 /* nopl 0(%[re]ax) */
1443 static const unsigned char alt_4
[] =
1444 {0x0f,0x1f,0x40,0x00};
1445 /* nopl 0(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_5
[] =
1447 {0x0f,0x1f,0x44,0x00,0x00};
1448 /* nopw 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_6
[] =
1450 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopl 0L(%[re]ax) */
1452 static const unsigned char alt_7
[] =
1453 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1454 /* nopl 0L(%[re]ax,%[re]ax,1) */
1455 static const unsigned char alt_8
[] =
1456 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* nopw 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_9
[] =
1459 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_10
[] =
1462 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* data16 nopw %cs:0L(%eax,%eax,1) */
1464 static const unsigned char alt_11
[] =
1465 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* 32-bit and 64-bit NOPs patterns. */
1467 static const unsigned char *const alt_patt
[] = {
1468 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1469 alt_9
, alt_10
, alt_11
1472 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1473 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1476 i386_output_nops (char *where
, const unsigned char *const *patt
,
1477 int count
, int max_single_nop_size
)
1480 /* Place the longer NOP first. */
1483 const unsigned char *nops
;
1485 if (max_single_nop_size
< 1)
1487 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1488 max_single_nop_size
);
1492 nops
= patt
[max_single_nop_size
- 1];
1494 /* Use the smaller one if the requsted one isn't available. */
1497 max_single_nop_size
--;
1498 nops
= patt
[max_single_nop_size
- 1];
1501 last
= count
% max_single_nop_size
;
1504 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1505 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1509 nops
= patt
[last
- 1];
1512 /* Use the smaller one plus one-byte NOP if the needed one
1515 nops
= patt
[last
- 1];
1516 memcpy (where
+ offset
, nops
, last
);
1517 where
[offset
+ last
] = *patt
[0];
1520 memcpy (where
+ offset
, nops
, last
);
1525 fits_in_imm7 (offsetT num
)
1527 return (num
& 0x7f) == num
;
1531 fits_in_imm31 (offsetT num
)
1533 return (num
& 0x7fffffff) == num
;
1536 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1537 single NOP instruction LIMIT. */
1540 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1542 const unsigned char *const *patt
= NULL
;
1543 int max_single_nop_size
;
1544 /* Maximum number of NOPs before switching to jump over NOPs. */
1545 int max_number_of_nops
;
1547 switch (fragP
->fr_type
)
1552 case rs_machine_dependent
:
1553 /* Allow NOP padding for jumps and calls. */
1554 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1555 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1562 /* We need to decide which NOP sequence to use for 32bit and
1563 64bit. When -mtune= is used:
1565 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1566 PROCESSOR_GENERIC32, f32_patt will be used.
1567 2. For the rest, alt_patt will be used.
1569 When -mtune= isn't used, alt_patt will be used if
1570 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1573 When -march= or .arch is used, we can't use anything beyond
1574 cpu_arch_isa_flags. */
1576 if (flag_code
== CODE_16BIT
)
1579 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1580 /* Limit number of NOPs to 2 in 16-bit mode. */
1581 max_number_of_nops
= 2;
1585 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1587 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1588 switch (cpu_arch_tune
)
1590 case PROCESSOR_UNKNOWN
:
1591 /* We use cpu_arch_isa_flags to check if we SHOULD
1592 optimize with nops. */
1593 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1598 case PROCESSOR_PENTIUM4
:
1599 case PROCESSOR_NOCONA
:
1600 case PROCESSOR_CORE
:
1601 case PROCESSOR_CORE2
:
1602 case PROCESSOR_COREI7
:
1603 case PROCESSOR_L1OM
:
1604 case PROCESSOR_K1OM
:
1605 case PROCESSOR_GENERIC64
:
1607 case PROCESSOR_ATHLON
:
1609 case PROCESSOR_AMDFAM10
:
1611 case PROCESSOR_ZNVER
:
1615 case PROCESSOR_I386
:
1616 case PROCESSOR_I486
:
1617 case PROCESSOR_PENTIUM
:
1618 case PROCESSOR_PENTIUMPRO
:
1619 case PROCESSOR_IAMCU
:
1620 case PROCESSOR_GENERIC32
:
1627 switch (fragP
->tc_frag_data
.tune
)
1629 case PROCESSOR_UNKNOWN
:
1630 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1631 PROCESSOR_UNKNOWN. */
1635 case PROCESSOR_I386
:
1636 case PROCESSOR_I486
:
1637 case PROCESSOR_PENTIUM
:
1638 case PROCESSOR_IAMCU
:
1640 case PROCESSOR_ATHLON
:
1642 case PROCESSOR_AMDFAM10
:
1644 case PROCESSOR_ZNVER
:
1646 case PROCESSOR_GENERIC32
:
1647 /* We use cpu_arch_isa_flags to check if we CAN optimize
1649 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1654 case PROCESSOR_PENTIUMPRO
:
1655 case PROCESSOR_PENTIUM4
:
1656 case PROCESSOR_NOCONA
:
1657 case PROCESSOR_CORE
:
1658 case PROCESSOR_CORE2
:
1659 case PROCESSOR_COREI7
:
1660 case PROCESSOR_L1OM
:
1661 case PROCESSOR_K1OM
:
1662 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1667 case PROCESSOR_GENERIC64
:
1673 if (patt
== f32_patt
)
1675 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1676 /* Limit number of NOPs to 2 for older processors. */
1677 max_number_of_nops
= 2;
1681 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1682 /* Limit number of NOPs to 7 for newer processors. */
1683 max_number_of_nops
= 7;
1688 limit
= max_single_nop_size
;
1690 if (fragP
->fr_type
== rs_fill_nop
)
1692 /* Output NOPs for .nop directive. */
1693 if (limit
> max_single_nop_size
)
1695 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1696 _("invalid single nop size: %d "
1697 "(expect within [0, %d])"),
1698 limit
, max_single_nop_size
);
1702 else if (fragP
->fr_type
!= rs_machine_dependent
)
1703 fragP
->fr_var
= count
;
1705 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1707 /* Generate jump over NOPs. */
1708 offsetT disp
= count
- 2;
1709 if (fits_in_imm7 (disp
))
1711 /* Use "jmp disp8" if possible. */
1713 where
[0] = jump_disp8
[0];
1719 unsigned int size_of_jump
;
1721 if (flag_code
== CODE_16BIT
)
1723 where
[0] = jump16_disp32
[0];
1724 where
[1] = jump16_disp32
[1];
1729 where
[0] = jump32_disp32
[0];
1733 count
-= size_of_jump
+ 4;
1734 if (!fits_in_imm31 (count
))
1736 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1737 _("jump over nop padding out of range"));
1741 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1742 where
+= size_of_jump
+ 4;
1746 /* Generate multiple NOPs. */
1747 i386_output_nops (where
, patt
, count
, limit
);
1751 operand_type_all_zero (const union i386_operand_type
*x
)
1753 switch (ARRAY_SIZE(x
->array
))
1764 return !x
->array
[0];
1771 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1773 switch (ARRAY_SIZE(x
->array
))
1789 x
->bitfield
.class = ClassNone
;
1790 x
->bitfield
.instance
= InstanceNone
;
1794 operand_type_equal (const union i386_operand_type
*x
,
1795 const union i386_operand_type
*y
)
1797 switch (ARRAY_SIZE(x
->array
))
1800 if (x
->array
[2] != y
->array
[2])
1804 if (x
->array
[1] != y
->array
[1])
1808 return x
->array
[0] == y
->array
[0];
1816 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1818 switch (ARRAY_SIZE(x
->array
))
1833 return !x
->array
[0];
1840 cpu_flags_equal (const union i386_cpu_flags
*x
,
1841 const union i386_cpu_flags
*y
)
1843 switch (ARRAY_SIZE(x
->array
))
1846 if (x
->array
[3] != y
->array
[3])
1850 if (x
->array
[2] != y
->array
[2])
1854 if (x
->array
[1] != y
->array
[1])
1858 return x
->array
[0] == y
->array
[0];
1866 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1868 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1869 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1872 static INLINE i386_cpu_flags
1873 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1875 switch (ARRAY_SIZE (x
.array
))
1878 x
.array
[3] &= y
.array
[3];
1881 x
.array
[2] &= y
.array
[2];
1884 x
.array
[1] &= y
.array
[1];
1887 x
.array
[0] &= y
.array
[0];
1895 static INLINE i386_cpu_flags
1896 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1898 switch (ARRAY_SIZE (x
.array
))
1901 x
.array
[3] |= y
.array
[3];
1904 x
.array
[2] |= y
.array
[2];
1907 x
.array
[1] |= y
.array
[1];
1910 x
.array
[0] |= y
.array
[0];
1918 static INLINE i386_cpu_flags
1919 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1921 switch (ARRAY_SIZE (x
.array
))
1924 x
.array
[3] &= ~y
.array
[3];
1927 x
.array
[2] &= ~y
.array
[2];
1930 x
.array
[1] &= ~y
.array
[1];
1933 x
.array
[0] &= ~y
.array
[0];
1941 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1943 #define CPU_FLAGS_ARCH_MATCH 0x1
1944 #define CPU_FLAGS_64BIT_MATCH 0x2
1946 #define CPU_FLAGS_PERFECT_MATCH \
1947 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1949 /* Return CPU flags match bits. */
1952 cpu_flags_match (const insn_template
*t
)
1954 i386_cpu_flags x
= t
->cpu_flags
;
1955 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1957 x
.bitfield
.cpu64
= 0;
1958 x
.bitfield
.cpuno64
= 0;
1960 if (cpu_flags_all_zero (&x
))
1962 /* This instruction is available on all archs. */
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 /* This instruction is available only on some archs. */
1968 i386_cpu_flags cpu
= cpu_arch_flags
;
1970 /* AVX512VL is no standalone feature - match it and then strip it. */
1971 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1973 x
.bitfield
.cpuavx512vl
= 0;
1975 cpu
= cpu_flags_and (x
, cpu
);
1976 if (!cpu_flags_all_zero (&cpu
))
1978 if (x
.bitfield
.cpuavx
)
1980 /* We need to check a few extra flags with AVX. */
1981 if (cpu
.bitfield
.cpuavx
1982 && (!t
->opcode_modifier
.sse2avx
1983 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1984 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1985 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1986 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1989 else if (x
.bitfield
.cpuavx512f
)
1991 /* We need to check a few extra flags with AVX512F. */
1992 if (cpu
.bitfield
.cpuavx512f
1993 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1994 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1995 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1996 match
|= CPU_FLAGS_ARCH_MATCH
;
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2005 static INLINE i386_operand_type
2006 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2008 if (x
.bitfield
.class != y
.bitfield
.class)
2009 x
.bitfield
.class = ClassNone
;
2010 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2011 x
.bitfield
.instance
= InstanceNone
;
2013 switch (ARRAY_SIZE (x
.array
))
2016 x
.array
[2] &= y
.array
[2];
2019 x
.array
[1] &= y
.array
[1];
2022 x
.array
[0] &= y
.array
[0];
2030 static INLINE i386_operand_type
2031 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2033 gas_assert (y
.bitfield
.class == ClassNone
);
2034 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2036 switch (ARRAY_SIZE (x
.array
))
2039 x
.array
[2] &= ~y
.array
[2];
2042 x
.array
[1] &= ~y
.array
[1];
2045 x
.array
[0] &= ~y
.array
[0];
2053 static INLINE i386_operand_type
2054 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2056 gas_assert (x
.bitfield
.class == ClassNone
||
2057 y
.bitfield
.class == ClassNone
||
2058 x
.bitfield
.class == y
.bitfield
.class);
2059 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2060 y
.bitfield
.instance
== InstanceNone
||
2061 x
.bitfield
.instance
== y
.bitfield
.instance
);
2063 switch (ARRAY_SIZE (x
.array
))
2066 x
.array
[2] |= y
.array
[2];
2069 x
.array
[1] |= y
.array
[1];
2072 x
.array
[0] |= y
.array
[0];
2080 static INLINE i386_operand_type
2081 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2083 gas_assert (y
.bitfield
.class == ClassNone
);
2084 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2086 switch (ARRAY_SIZE (x
.array
))
2089 x
.array
[2] ^= y
.array
[2];
2092 x
.array
[1] ^= y
.array
[1];
2095 x
.array
[0] ^= y
.array
[0];
2103 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2104 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2105 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2106 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2107 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2108 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2109 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2110 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2111 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2112 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2113 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2114 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2115 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2116 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2117 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2118 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2119 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2130 operand_type_check (i386_operand_type t
, enum operand_type c
)
2135 return t
.bitfield
.class == Reg
;
2138 return (t
.bitfield
.imm8
2142 || t
.bitfield
.imm32s
2143 || t
.bitfield
.imm64
);
2146 return (t
.bitfield
.disp8
2147 || t
.bitfield
.disp16
2148 || t
.bitfield
.disp32
2149 || t
.bitfield
.disp32s
2150 || t
.bitfield
.disp64
);
2153 return (t
.bitfield
.disp8
2154 || t
.bitfield
.disp16
2155 || t
.bitfield
.disp32
2156 || t
.bitfield
.disp32s
2157 || t
.bitfield
.disp64
2158 || t
.bitfield
.baseindex
);
2167 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2168 between operand GIVEN and opeand WANTED for instruction template T. */
2171 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2174 return !((i
.types
[given
].bitfield
.byte
2175 && !t
->operand_types
[wanted
].bitfield
.byte
)
2176 || (i
.types
[given
].bitfield
.word
2177 && !t
->operand_types
[wanted
].bitfield
.word
)
2178 || (i
.types
[given
].bitfield
.dword
2179 && !t
->operand_types
[wanted
].bitfield
.dword
)
2180 || (i
.types
[given
].bitfield
.qword
2181 && !t
->operand_types
[wanted
].bitfield
.qword
)
2182 || (i
.types
[given
].bitfield
.tbyte
2183 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2186 /* Return 1 if there is no conflict in SIMD register between operand
2187 GIVEN and opeand WANTED for instruction template T. */
2190 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2193 return !((i
.types
[given
].bitfield
.xmmword
2194 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2195 || (i
.types
[given
].bitfield
.ymmword
2196 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2197 || (i
.types
[given
].bitfield
.zmmword
2198 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2199 || (i
.types
[given
].bitfield
.tmmword
2200 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2203 /* Return 1 if there is no conflict in any size between operand GIVEN
2204 and opeand WANTED for instruction template T. */
2207 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2210 return (match_operand_size (t
, wanted
, given
)
2211 && !((i
.types
[given
].bitfield
.unspecified
2213 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2214 || (i
.types
[given
].bitfield
.fword
2215 && !t
->operand_types
[wanted
].bitfield
.fword
)
2216 /* For scalar opcode templates to allow register and memory
2217 operands at the same time, some special casing is needed
2218 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2219 down-conversion vpmov*. */
2220 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2221 && t
->operand_types
[wanted
].bitfield
.byte
2222 + t
->operand_types
[wanted
].bitfield
.word
2223 + t
->operand_types
[wanted
].bitfield
.dword
2224 + t
->operand_types
[wanted
].bitfield
.qword
2225 > !!t
->opcode_modifier
.broadcast
)
2226 ? (i
.types
[given
].bitfield
.xmmword
2227 || i
.types
[given
].bitfield
.ymmword
2228 || i
.types
[given
].bitfield
.zmmword
)
2229 : !match_simd_size(t
, wanted
, given
))));
2232 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2233 operands for instruction template T, and it has MATCH_REVERSE set if there
2234 is no size conflict on any operands for the template with operands reversed
2235 (and the template allows for reversing in the first place). */
2237 #define MATCH_STRAIGHT 1
2238 #define MATCH_REVERSE 2
2240 static INLINE
unsigned int
2241 operand_size_match (const insn_template
*t
)
2243 unsigned int j
, match
= MATCH_STRAIGHT
;
2245 /* Don't check non-absolute jump instructions. */
2246 if (t
->opcode_modifier
.jump
2247 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2250 /* Check memory and accumulator operand size. */
2251 for (j
= 0; j
< i
.operands
; j
++)
2253 if (i
.types
[j
].bitfield
.class != Reg
2254 && i
.types
[j
].bitfield
.class != RegSIMD
2255 && t
->opcode_modifier
.anysize
)
2258 if (t
->operand_types
[j
].bitfield
.class == Reg
2259 && !match_operand_size (t
, j
, j
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, j
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2279 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2286 if (!t
->opcode_modifier
.d
)
2290 i
.error
= operand_size_mismatch
;
2294 /* Check reverse. */
2295 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2297 for (j
= 0; j
< i
.operands
; j
++)
2299 unsigned int given
= i
.operands
- j
- 1;
2301 if (t
->operand_types
[j
].bitfield
.class == Reg
2302 && !match_operand_size (t
, j
, given
))
2305 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2306 && !match_simd_size (t
, j
, given
))
2309 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2310 && (!match_operand_size (t
, j
, given
)
2311 || !match_simd_size (t
, j
, given
)))
2314 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2318 return match
| MATCH_REVERSE
;
2322 operand_type_match (i386_operand_type overlap
,
2323 i386_operand_type given
)
2325 i386_operand_type temp
= overlap
;
2327 temp
.bitfield
.unspecified
= 0;
2328 temp
.bitfield
.byte
= 0;
2329 temp
.bitfield
.word
= 0;
2330 temp
.bitfield
.dword
= 0;
2331 temp
.bitfield
.fword
= 0;
2332 temp
.bitfield
.qword
= 0;
2333 temp
.bitfield
.tbyte
= 0;
2334 temp
.bitfield
.xmmword
= 0;
2335 temp
.bitfield
.ymmword
= 0;
2336 temp
.bitfield
.zmmword
= 0;
2337 temp
.bitfield
.tmmword
= 0;
2338 if (operand_type_all_zero (&temp
))
2341 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2345 i
.error
= operand_type_mismatch
;
2349 /* If given types g0 and g1 are registers they must be of the same type
2350 unless the expected operand type register overlap is null.
2351 Some Intel syntax memory operand size checking also happens here. */
2354 operand_type_register_match (i386_operand_type g0
,
2355 i386_operand_type t0
,
2356 i386_operand_type g1
,
2357 i386_operand_type t1
)
2359 if (g0
.bitfield
.class != Reg
2360 && g0
.bitfield
.class != RegSIMD
2361 && (!operand_type_check (g0
, anymem
)
2362 || g0
.bitfield
.unspecified
2363 || (t0
.bitfield
.class != Reg
2364 && t0
.bitfield
.class != RegSIMD
)))
2367 if (g1
.bitfield
.class != Reg
2368 && g1
.bitfield
.class != RegSIMD
2369 && (!operand_type_check (g1
, anymem
)
2370 || g1
.bitfield
.unspecified
2371 || (t1
.bitfield
.class != Reg
2372 && t1
.bitfield
.class != RegSIMD
)))
2375 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2376 && g0
.bitfield
.word
== g1
.bitfield
.word
2377 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2378 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2379 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2380 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2381 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2384 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2385 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2386 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2387 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2388 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2389 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2390 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2393 i
.error
= register_type_mismatch
;
2398 static INLINE
unsigned int
2399 register_number (const reg_entry
*r
)
2401 unsigned int nr
= r
->reg_num
;
2403 if (r
->reg_flags
& RegRex
)
2406 if (r
->reg_flags
& RegVRex
)
2412 static INLINE
unsigned int
2413 mode_from_disp_size (i386_operand_type t
)
2415 if (t
.bitfield
.disp8
)
2417 else if (t
.bitfield
.disp16
2418 || t
.bitfield
.disp32
2419 || t
.bitfield
.disp32s
)
2426 fits_in_signed_byte (addressT num
)
2428 return num
+ 0x80 <= 0xff;
2432 fits_in_unsigned_byte (addressT num
)
2438 fits_in_unsigned_word (addressT num
)
2440 return num
<= 0xffff;
2444 fits_in_signed_word (addressT num
)
2446 return num
+ 0x8000 <= 0xffff;
2450 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2455 return num
+ 0x80000000 <= 0xffffffff;
2457 } /* fits_in_signed_long() */
2460 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2465 return num
<= 0xffffffff;
2467 } /* fits_in_unsigned_long() */
2470 fits_in_disp8 (offsetT num
)
2472 int shift
= i
.memshift
;
2478 mask
= (1 << shift
) - 1;
2480 /* Return 0 if NUM isn't properly aligned. */
2484 /* Check if NUM will fit in 8bit after shift. */
2485 return fits_in_signed_byte (num
>> shift
);
2489 fits_in_imm4 (offsetT num
)
2491 return (num
& 0xf) == num
;
2494 static i386_operand_type
2495 smallest_imm_type (offsetT num
)
2497 i386_operand_type t
;
2499 operand_type_set (&t
, 0);
2500 t
.bitfield
.imm64
= 1;
2502 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2504 /* This code is disabled on the 486 because all the Imm1 forms
2505 in the opcode table are slower on the i486. They're the
2506 versions with the implicitly specified single-position
2507 displacement, which has another syntax if you really want to
2509 t
.bitfield
.imm1
= 1;
2510 t
.bitfield
.imm8
= 1;
2511 t
.bitfield
.imm8s
= 1;
2512 t
.bitfield
.imm16
= 1;
2513 t
.bitfield
.imm32
= 1;
2514 t
.bitfield
.imm32s
= 1;
2516 else if (fits_in_signed_byte (num
))
2518 t
.bitfield
.imm8
= 1;
2519 t
.bitfield
.imm8s
= 1;
2520 t
.bitfield
.imm16
= 1;
2521 t
.bitfield
.imm32
= 1;
2522 t
.bitfield
.imm32s
= 1;
2524 else if (fits_in_unsigned_byte (num
))
2526 t
.bitfield
.imm8
= 1;
2527 t
.bitfield
.imm16
= 1;
2528 t
.bitfield
.imm32
= 1;
2529 t
.bitfield
.imm32s
= 1;
2531 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2533 t
.bitfield
.imm16
= 1;
2534 t
.bitfield
.imm32
= 1;
2535 t
.bitfield
.imm32s
= 1;
2537 else if (fits_in_signed_long (num
))
2539 t
.bitfield
.imm32
= 1;
2540 t
.bitfield
.imm32s
= 1;
2542 else if (fits_in_unsigned_long (num
))
2543 t
.bitfield
.imm32
= 1;
2549 offset_in_range (offsetT val
, int size
)
2555 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2556 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2557 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2559 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2564 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2566 char buf1
[40], buf2
[40];
2568 sprint_value (buf1
, val
);
2569 sprint_value (buf2
, val
& mask
);
2570 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2585 a. PREFIX_EXIST if attempting to add a prefix where one from the
2586 same class already exists.
2587 b. PREFIX_LOCK if lock prefix is added.
2588 c. PREFIX_REP if rep/repne prefix is added.
2589 d. PREFIX_DS if ds prefix is added.
2590 e. PREFIX_OTHER if other prefix is added.
2593 static enum PREFIX_GROUP
2594 add_prefix (unsigned int prefix
)
2596 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2599 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2600 && flag_code
== CODE_64BIT
)
2602 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2603 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2604 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2605 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2616 case DS_PREFIX_OPCODE
:
2619 case CS_PREFIX_OPCODE
:
2620 case ES_PREFIX_OPCODE
:
2621 case FS_PREFIX_OPCODE
:
2622 case GS_PREFIX_OPCODE
:
2623 case SS_PREFIX_OPCODE
:
2627 case REPNE_PREFIX_OPCODE
:
2628 case REPE_PREFIX_OPCODE
:
2633 case LOCK_PREFIX_OPCODE
:
2642 case ADDR_PREFIX_OPCODE
:
2646 case DATA_PREFIX_OPCODE
:
2650 if (i
.prefix
[q
] != 0)
2658 i
.prefix
[q
] |= prefix
;
2661 as_bad (_("same type of prefix used twice"));
2667 update_code_flag (int value
, int check
)
2669 PRINTF_LIKE ((*as_error
));
2671 flag_code
= (enum flag_code
) value
;
2672 if (flag_code
== CODE_64BIT
)
2674 cpu_arch_flags
.bitfield
.cpu64
= 1;
2675 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2679 cpu_arch_flags
.bitfield
.cpu64
= 0;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2682 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2685 as_error
= as_fatal
;
2688 (*as_error
) (_("64bit mode not supported on `%s'."),
2689 cpu_arch_name
? cpu_arch_name
: default_arch
);
2691 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2694 as_error
= as_fatal
;
2697 (*as_error
) (_("32bit mode not supported on `%s'."),
2698 cpu_arch_name
? cpu_arch_name
: default_arch
);
2700 stackop_size
= '\0';
2704 set_code_flag (int value
)
2706 update_code_flag (value
, 0);
2710 set_16bit_gcc_code_flag (int new_code_flag
)
2712 flag_code
= (enum flag_code
) new_code_flag
;
2713 if (flag_code
!= CODE_16BIT
)
2715 cpu_arch_flags
.bitfield
.cpu64
= 0;
2716 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2717 stackop_size
= LONG_MNEM_SUFFIX
;
2721 set_intel_syntax (int syntax_flag
)
2723 /* Find out if register prefixing is specified. */
2724 int ask_naked_reg
= 0;
2727 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2730 int e
= get_symbol_name (&string
);
2732 if (strcmp (string
, "prefix") == 0)
2734 else if (strcmp (string
, "noprefix") == 0)
2737 as_bad (_("bad argument to syntax directive."));
2738 (void) restore_line_pointer (e
);
2740 demand_empty_rest_of_line ();
2742 intel_syntax
= syntax_flag
;
2744 if (ask_naked_reg
== 0)
2745 allow_naked_reg
= (intel_syntax
2746 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2748 allow_naked_reg
= (ask_naked_reg
< 0);
2750 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2752 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2753 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2754 register_prefix
= allow_naked_reg
? "" : "%";
2758 set_intel_mnemonic (int mnemonic_flag
)
2760 intel_mnemonic
= mnemonic_flag
;
2764 set_allow_index_reg (int flag
)
2766 allow_index_reg
= flag
;
2770 set_check (int what
)
2772 enum check_kind
*kind
;
2777 kind
= &operand_check
;
2788 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2791 int e
= get_symbol_name (&string
);
2793 if (strcmp (string
, "none") == 0)
2795 else if (strcmp (string
, "warning") == 0)
2796 *kind
= check_warning
;
2797 else if (strcmp (string
, "error") == 0)
2798 *kind
= check_error
;
2800 as_bad (_("bad argument to %s_check directive."), str
);
2801 (void) restore_line_pointer (e
);
2804 as_bad (_("missing argument for %s_check directive"), str
);
2806 demand_empty_rest_of_line ();
2810 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2811 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2814 static const char *arch
;
2816 /* Intel LIOM is only supported on ELF. */
2822 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2823 use default_arch. */
2824 arch
= cpu_arch_name
;
2826 arch
= default_arch
;
2829 /* If we are targeting Intel MCU, we must enable it. */
2830 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2831 || new_flag
.bitfield
.cpuiamcu
)
2834 /* If we are targeting Intel L1OM, we must enable it. */
2835 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2836 || new_flag
.bitfield
.cpul1om
)
2839 /* If we are targeting Intel K1OM, we must enable it. */
2840 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2841 || new_flag
.bitfield
.cpuk1om
)
2844 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2849 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2853 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2856 int e
= get_symbol_name (&string
);
2858 i386_cpu_flags flags
;
2860 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2862 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2864 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2868 cpu_arch_name
= cpu_arch
[j
].name
;
2869 cpu_sub_arch_name
= NULL
;
2870 cpu_arch_flags
= cpu_arch
[j
].flags
;
2871 if (flag_code
== CODE_64BIT
)
2873 cpu_arch_flags
.bitfield
.cpu64
= 1;
2874 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2878 cpu_arch_flags
.bitfield
.cpu64
= 0;
2879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2881 cpu_arch_isa
= cpu_arch
[j
].type
;
2882 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2883 if (!cpu_arch_tune_set
)
2885 cpu_arch_tune
= cpu_arch_isa
;
2886 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2891 flags
= cpu_flags_or (cpu_arch_flags
,
2894 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2896 if (cpu_sub_arch_name
)
2898 char *name
= cpu_sub_arch_name
;
2899 cpu_sub_arch_name
= concat (name
,
2901 (const char *) NULL
);
2905 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2906 cpu_arch_flags
= flags
;
2907 cpu_arch_isa_flags
= flags
;
2911 = cpu_flags_or (cpu_arch_isa_flags
,
2913 (void) restore_line_pointer (e
);
2914 demand_empty_rest_of_line ();
2919 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2921 /* Disable an ISA extension. */
2922 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2923 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2925 flags
= cpu_flags_and_not (cpu_arch_flags
,
2926 cpu_noarch
[j
].flags
);
2927 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2929 if (cpu_sub_arch_name
)
2931 char *name
= cpu_sub_arch_name
;
2932 cpu_sub_arch_name
= concat (name
, string
,
2933 (const char *) NULL
);
2937 cpu_sub_arch_name
= xstrdup (string
);
2938 cpu_arch_flags
= flags
;
2939 cpu_arch_isa_flags
= flags
;
2941 (void) restore_line_pointer (e
);
2942 demand_empty_rest_of_line ();
2946 j
= ARRAY_SIZE (cpu_arch
);
2949 if (j
>= ARRAY_SIZE (cpu_arch
))
2950 as_bad (_("no such architecture: `%s'"), string
);
2952 *input_line_pointer
= e
;
2955 as_bad (_("missing cpu architecture"));
2957 no_cond_jump_promotion
= 0;
2958 if (*input_line_pointer
== ','
2959 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2964 ++input_line_pointer
;
2965 e
= get_symbol_name (&string
);
2967 if (strcmp (string
, "nojumps") == 0)
2968 no_cond_jump_promotion
= 1;
2969 else if (strcmp (string
, "jumps") == 0)
2972 as_bad (_("no such architecture modifier: `%s'"), string
);
2974 (void) restore_line_pointer (e
);
2977 demand_empty_rest_of_line ();
2980 enum bfd_architecture
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || flag_code
!= CODE_64BIT
)
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_arch_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || flag_code
!= CODE_64BIT
)
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_arch_k1om
;
2997 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2999 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3000 || flag_code
== CODE_64BIT
)
3001 as_fatal (_("Intel MCU is 32bit ELF only"));
3002 return bfd_arch_iamcu
;
3005 return bfd_arch_i386
;
3011 if (!strncmp (default_arch
, "x86_64", 6))
3013 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3016 || default_arch
[6] != '\0')
3017 as_fatal (_("Intel L1OM is 64bit ELF only"));
3018 return bfd_mach_l1om
;
3020 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3022 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3023 || default_arch
[6] != '\0')
3024 as_fatal (_("Intel K1OM is 64bit ELF only"));
3025 return bfd_mach_k1om
;
3027 else if (default_arch
[6] == '\0')
3028 return bfd_mach_x86_64
;
3030 return bfd_mach_x64_32
;
3032 else if (!strcmp (default_arch
, "i386")
3033 || !strcmp (default_arch
, "iamcu"))
3035 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3037 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3038 as_fatal (_("Intel MCU is 32bit ELF only"));
3039 return bfd_mach_i386_iamcu
;
3042 return bfd_mach_i386_i386
;
3045 as_fatal (_("unknown architecture"));
3051 /* Support pseudo prefixes like {disp32}. */
3052 lex_type
['{'] = LEX_BEGIN_NAME
;
3054 /* Initialize op_hash hash table. */
3055 op_hash
= str_htab_create ();
3058 const insn_template
*optab
;
3059 templates
*core_optab
;
3061 /* Setup for loop. */
3063 core_optab
= XNEW (templates
);
3064 core_optab
->start
= optab
;
3069 if (optab
->name
== NULL
3070 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3072 /* different name --> ship out current template list;
3073 add to hash table; & begin anew. */
3074 core_optab
->end
= optab
;
3075 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3076 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3078 if (optab
->name
== NULL
)
3080 core_optab
= XNEW (templates
);
3081 core_optab
->start
= optab
;
3086 /* Initialize reg_hash hash table. */
3087 reg_hash
= str_htab_create ();
3089 const reg_entry
*regtab
;
3090 unsigned int regtab_size
= i386_regtab_size
;
3092 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3093 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3094 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3097 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3102 for (c
= 0; c
< 256; c
++)
3107 mnemonic_chars
[c
] = c
;
3108 register_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3111 else if (ISLOWER (c
))
3113 mnemonic_chars
[c
] = c
;
3114 register_chars
[c
] = c
;
3115 operand_chars
[c
] = c
;
3117 else if (ISUPPER (c
))
3119 mnemonic_chars
[c
] = TOLOWER (c
);
3120 register_chars
[c
] = mnemonic_chars
[c
];
3121 operand_chars
[c
] = c
;
3123 else if (c
== '{' || c
== '}')
3125 mnemonic_chars
[c
] = c
;
3126 operand_chars
[c
] = c
;
3128 #ifdef SVR4_COMMENT_CHARS
3129 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3130 operand_chars
[c
] = c
;
3133 if (ISALPHA (c
) || ISDIGIT (c
))
3134 identifier_chars
[c
] = c
;
3137 identifier_chars
[c
] = c
;
3138 operand_chars
[c
] = c
;
3143 identifier_chars
['@'] = '@';
3146 identifier_chars
['?'] = '?';
3147 operand_chars
['?'] = '?';
3149 digit_chars
['-'] = '-';
3150 mnemonic_chars
['_'] = '_';
3151 mnemonic_chars
['-'] = '-';
3152 mnemonic_chars
['.'] = '.';
3153 identifier_chars
['_'] = '_';
3154 identifier_chars
['.'] = '.';
3156 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3157 operand_chars
[(unsigned char) *p
] = *p
;
3160 if (flag_code
== CODE_64BIT
)
3162 #if defined (OBJ_COFF) && defined (TE_PE)
3163 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3166 x86_dwarf2_return_column
= 16;
3168 x86_cie_data_alignment
= -8;
3172 x86_dwarf2_return_column
= 8;
3173 x86_cie_data_alignment
= -4;
3176 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3177 can be turned into BRANCH_PREFIX frag. */
3178 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3183 i386_print_statistics (FILE *file
)
3185 htab_print_statistics (file
, "i386 opcode", op_hash
);
3186 htab_print_statistics (file
, "i386 register", reg_hash
);
3191 /* Debugging routines for md_assemble. */
3192 static void pte (insn_template
*);
3193 static void pt (i386_operand_type
);
3194 static void pe (expressionS
*);
3195 static void ps (symbolS
*);
3198 pi (const char *line
, i386_insn
*x
)
3202 fprintf (stdout
, "%s: template ", line
);
3204 fprintf (stdout
, " address: base %s index %s scale %x\n",
3205 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3206 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3207 x
->log2_scale_factor
);
3208 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3209 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3210 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3211 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3212 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3213 (x
->rex
& REX_W
) != 0,
3214 (x
->rex
& REX_R
) != 0,
3215 (x
->rex
& REX_X
) != 0,
3216 (x
->rex
& REX_B
) != 0);
3217 for (j
= 0; j
< x
->operands
; j
++)
3219 fprintf (stdout
, " #%d: ", j
+ 1);
3221 fprintf (stdout
, "\n");
3222 if (x
->types
[j
].bitfield
.class == Reg
3223 || x
->types
[j
].bitfield
.class == RegMMX
3224 || x
->types
[j
].bitfield
.class == RegSIMD
3225 || x
->types
[j
].bitfield
.class == RegMask
3226 || x
->types
[j
].bitfield
.class == SReg
3227 || x
->types
[j
].bitfield
.class == RegCR
3228 || x
->types
[j
].bitfield
.class == RegDR
3229 || x
->types
[j
].bitfield
.class == RegTR
3230 || x
->types
[j
].bitfield
.class == RegBND
)
3231 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3232 if (operand_type_check (x
->types
[j
], imm
))
3234 if (operand_type_check (x
->types
[j
], disp
))
3235 pe (x
->op
[j
].disps
);
3240 pte (insn_template
*t
)
3243 fprintf (stdout
, " %d operands ", t
->operands
);
3244 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3245 if (t
->extension_opcode
!= None
)
3246 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3247 if (t
->opcode_modifier
.d
)
3248 fprintf (stdout
, "D");
3249 if (t
->opcode_modifier
.w
)
3250 fprintf (stdout
, "W");
3251 fprintf (stdout
, "\n");
3252 for (j
= 0; j
< t
->operands
; j
++)
3254 fprintf (stdout
, " #%d type ", j
+ 1);
3255 pt (t
->operand_types
[j
]);
3256 fprintf (stdout
, "\n");
3263 fprintf (stdout
, " operation %d\n", e
->X_op
);
3264 fprintf (stdout
, " add_number %ld (%lx)\n",
3265 (long) e
->X_add_number
, (long) e
->X_add_number
);
3266 if (e
->X_add_symbol
)
3268 fprintf (stdout
, " add_symbol ");
3269 ps (e
->X_add_symbol
);
3270 fprintf (stdout
, "\n");
3274 fprintf (stdout
, " op_symbol ");
3275 ps (e
->X_op_symbol
);
3276 fprintf (stdout
, "\n");
3283 fprintf (stdout
, "%s type %s%s",
3285 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3286 segment_name (S_GET_SEGMENT (s
)));
3289 static struct type_name
3291 i386_operand_type mask
;
3294 const type_names
[] =
3296 { OPERAND_TYPE_REG8
, "r8" },
3297 { OPERAND_TYPE_REG16
, "r16" },
3298 { OPERAND_TYPE_REG32
, "r32" },
3299 { OPERAND_TYPE_REG64
, "r64" },
3300 { OPERAND_TYPE_ACC8
, "acc8" },
3301 { OPERAND_TYPE_ACC16
, "acc16" },
3302 { OPERAND_TYPE_ACC32
, "acc32" },
3303 { OPERAND_TYPE_ACC64
, "acc64" },
3304 { OPERAND_TYPE_IMM8
, "i8" },
3305 { OPERAND_TYPE_IMM8
, "i8s" },
3306 { OPERAND_TYPE_IMM16
, "i16" },
3307 { OPERAND_TYPE_IMM32
, "i32" },
3308 { OPERAND_TYPE_IMM32S
, "i32s" },
3309 { OPERAND_TYPE_IMM64
, "i64" },
3310 { OPERAND_TYPE_IMM1
, "i1" },
3311 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3312 { OPERAND_TYPE_DISP8
, "d8" },
3313 { OPERAND_TYPE_DISP16
, "d16" },
3314 { OPERAND_TYPE_DISP32
, "d32" },
3315 { OPERAND_TYPE_DISP32S
, "d32s" },
3316 { OPERAND_TYPE_DISP64
, "d64" },
3317 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3318 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3319 { OPERAND_TYPE_CONTROL
, "control reg" },
3320 { OPERAND_TYPE_TEST
, "test reg" },
3321 { OPERAND_TYPE_DEBUG
, "debug reg" },
3322 { OPERAND_TYPE_FLOATREG
, "FReg" },
3323 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3324 { OPERAND_TYPE_SREG
, "SReg" },
3325 { OPERAND_TYPE_REGMMX
, "rMMX" },
3326 { OPERAND_TYPE_REGXMM
, "rXMM" },
3327 { OPERAND_TYPE_REGYMM
, "rYMM" },
3328 { OPERAND_TYPE_REGZMM
, "rZMM" },
3329 { OPERAND_TYPE_REGTMM
, "rTMM" },
3330 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3334 pt (i386_operand_type t
)
3337 i386_operand_type a
;
3339 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3341 a
= operand_type_and (t
, type_names
[j
].mask
);
3342 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3343 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3348 #endif /* DEBUG386 */
3350 static bfd_reloc_code_real_type
3351 reloc (unsigned int size
,
3354 bfd_reloc_code_real_type other
)
3356 if (other
!= NO_RELOC
)
3358 reloc_howto_type
*rel
;
3363 case BFD_RELOC_X86_64_GOT32
:
3364 return BFD_RELOC_X86_64_GOT64
;
3366 case BFD_RELOC_X86_64_GOTPLT64
:
3367 return BFD_RELOC_X86_64_GOTPLT64
;
3369 case BFD_RELOC_X86_64_PLTOFF64
:
3370 return BFD_RELOC_X86_64_PLTOFF64
;
3372 case BFD_RELOC_X86_64_GOTPC32
:
3373 other
= BFD_RELOC_X86_64_GOTPC64
;
3375 case BFD_RELOC_X86_64_GOTPCREL
:
3376 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3378 case BFD_RELOC_X86_64_TPOFF32
:
3379 other
= BFD_RELOC_X86_64_TPOFF64
;
3381 case BFD_RELOC_X86_64_DTPOFF32
:
3382 other
= BFD_RELOC_X86_64_DTPOFF64
;
3388 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3389 if (other
== BFD_RELOC_SIZE32
)
3392 other
= BFD_RELOC_SIZE64
;
3395 as_bad (_("there are no pc-relative size relocations"));
3401 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3402 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3405 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3407 as_bad (_("unknown relocation (%u)"), other
);
3408 else if (size
!= bfd_get_reloc_size (rel
))
3409 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3410 bfd_get_reloc_size (rel
),
3412 else if (pcrel
&& !rel
->pc_relative
)
3413 as_bad (_("non-pc-relative relocation for pc-relative field"));
3414 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3416 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3418 as_bad (_("relocated field and relocation type differ in signedness"));
3427 as_bad (_("there are no unsigned pc-relative relocations"));
3430 case 1: return BFD_RELOC_8_PCREL
;
3431 case 2: return BFD_RELOC_16_PCREL
;
3432 case 4: return BFD_RELOC_32_PCREL
;
3433 case 8: return BFD_RELOC_64_PCREL
;
3435 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3442 case 4: return BFD_RELOC_X86_64_32S
;
3447 case 1: return BFD_RELOC_8
;
3448 case 2: return BFD_RELOC_16
;
3449 case 4: return BFD_RELOC_32
;
3450 case 8: return BFD_RELOC_64
;
3452 as_bad (_("cannot do %s %u byte relocation"),
3453 sign
> 0 ? "signed" : "unsigned", size
);
3459 /* Here we decide which fixups can be adjusted to make them relative to
3460 the beginning of the section instead of the symbol. Basically we need
3461 to make sure that the dynamic relocations are done correctly, so in
3462 some cases we force the original symbol to be used. */
3465 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3467 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3471 /* Don't adjust pc-relative references to merge sections in 64-bit
3473 if (use_rela_relocations
3474 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3478 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3479 and changed later by validate_fix. */
3480 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3481 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3484 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3485 for size relocations. */
3486 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3487 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3488 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3489 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3490 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3492 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3493 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3494 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3495 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3496 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3497 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3498 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3499 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3500 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3506 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3507 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3508 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3509 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3510 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3511 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3512 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3513 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3515 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3516 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3523 intel_float_operand (const char *mnemonic
)
3525 /* Note that the value returned is meaningful only for opcodes with (memory)
3526 operands, hence the code here is free to improperly handle opcodes that
3527 have no operands (for better performance and smaller code). */
3529 if (mnemonic
[0] != 'f')
3530 return 0; /* non-math */
3532 switch (mnemonic
[1])
3534 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3535 the fs segment override prefix not currently handled because no
3536 call path can make opcodes without operands get here */
3538 return 2 /* integer op */;
3540 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3541 return 3; /* fldcw/fldenv */
3544 if (mnemonic
[2] != 'o' /* fnop */)
3545 return 3; /* non-waiting control op */
3548 if (mnemonic
[2] == 's')
3549 return 3; /* frstor/frstpm */
3552 if (mnemonic
[2] == 'a')
3553 return 3; /* fsave */
3554 if (mnemonic
[2] == 't')
3556 switch (mnemonic
[3])
3558 case 'c': /* fstcw */
3559 case 'd': /* fstdw */
3560 case 'e': /* fstenv */
3561 case 's': /* fsts[gw] */
3567 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3568 return 0; /* fxsave/fxrstor are not really math ops */
3575 /* Build the VEX prefix. */
3578 build_vex_prefix (const insn_template
*t
)
3580 unsigned int register_specifier
;
3581 unsigned int implied_prefix
;
3582 unsigned int vector_length
;
3585 /* Check register specifier. */
3586 if (i
.vex
.register_specifier
)
3588 register_specifier
=
3589 ~register_number (i
.vex
.register_specifier
) & 0xf;
3590 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3593 register_specifier
= 0xf;
3595 /* Use 2-byte VEX prefix by swapping destination and source operand
3596 if there are more than 1 register operand. */
3597 if (i
.reg_operands
> 1
3598 && i
.vec_encoding
!= vex_encoding_vex3
3599 && i
.dir_encoding
== dir_encoding_default
3600 && i
.operands
== i
.reg_operands
3601 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3602 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3603 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3606 unsigned int xchg
= i
.operands
- 1;
3607 union i386_op temp_op
;
3608 i386_operand_type temp_type
;
3610 temp_type
= i
.types
[xchg
];
3611 i
.types
[xchg
] = i
.types
[0];
3612 i
.types
[0] = temp_type
;
3613 temp_op
= i
.op
[xchg
];
3614 i
.op
[xchg
] = i
.op
[0];
3617 gas_assert (i
.rm
.mode
== 3);
3621 i
.rm
.regmem
= i
.rm
.reg
;
3624 if (i
.tm
.opcode_modifier
.d
)
3625 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3626 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3627 else /* Use the next insn. */
3631 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3632 are no memory operands and at least 3 register ones. */
3633 if (i
.reg_operands
>= 3
3634 && i
.vec_encoding
!= vex_encoding_vex3
3635 && i
.reg_operands
== i
.operands
- i
.imm_operands
3636 && i
.tm
.opcode_modifier
.vex
3637 && i
.tm
.opcode_modifier
.commutative
3638 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3640 && i
.vex
.register_specifier
3641 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3643 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3644 union i386_op temp_op
;
3645 i386_operand_type temp_type
;
3647 gas_assert (i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
);
3648 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3649 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3650 &i
.types
[i
.operands
- 3]));
3651 gas_assert (i
.rm
.mode
== 3);
3653 temp_type
= i
.types
[xchg
];
3654 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3655 i
.types
[xchg
+ 1] = temp_type
;
3656 temp_op
= i
.op
[xchg
];
3657 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3658 i
.op
[xchg
+ 1] = temp_op
;
3661 xchg
= i
.rm
.regmem
| 8;
3662 i
.rm
.regmem
= ~register_specifier
& 0xf;
3663 gas_assert (!(i
.rm
.regmem
& 8));
3664 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3665 register_specifier
= ~xchg
& 0xf;
3668 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3669 vector_length
= avxscalar
;
3670 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3676 /* Determine vector length from the last multi-length vector
3679 for (op
= t
->operands
; op
--;)
3680 if (t
->operand_types
[op
].bitfield
.xmmword
3681 && t
->operand_types
[op
].bitfield
.ymmword
3682 && i
.types
[op
].bitfield
.ymmword
)
3689 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3694 case DATA_PREFIX_OPCODE
:
3697 case REPE_PREFIX_OPCODE
:
3700 case REPNE_PREFIX_OPCODE
:
3707 /* Check the REX.W bit and VEXW. */
3708 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3709 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3710 else if (i
.tm
.opcode_modifier
.vexw
)
3711 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3713 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3715 /* Use 2-byte VEX prefix if possible. */
3717 && i
.vec_encoding
!= vex_encoding_vex3
3718 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
3719 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3721 /* 2-byte VEX prefix. */
3725 i
.vex
.bytes
[0] = 0xc5;
3727 /* Check the REX.R bit. */
3728 r
= (i
.rex
& REX_R
) ? 0 : 1;
3729 i
.vex
.bytes
[1] = (r
<< 7
3730 | register_specifier
<< 3
3731 | vector_length
<< 2
3736 /* 3-byte VEX prefix. */
3741 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3745 i
.vex
.bytes
[0] = 0xc4;
3749 i
.vex
.bytes
[0] = 0xc4;
3753 i
.vex
.bytes
[0] = 0xc4;
3757 i
.vex
.bytes
[0] = 0x8f;
3761 i
.vex
.bytes
[0] = 0x8f;
3765 i
.vex
.bytes
[0] = 0x8f;
3771 /* The high 3 bits of the second VEX byte are 1's compliment
3772 of RXB bits from REX. */
3773 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3775 i
.vex
.bytes
[2] = (w
<< 7
3776 | register_specifier
<< 3
3777 | vector_length
<< 2
3782 static INLINE bfd_boolean
3783 is_evex_encoding (const insn_template
*t
)
3785 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3786 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3787 || t
->opcode_modifier
.sae
;
3790 static INLINE bfd_boolean
3791 is_any_vex_encoding (const insn_template
*t
)
3793 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3796 /* Build the EVEX prefix. */
3799 build_evex_prefix (void)
3801 unsigned int register_specifier
;
3802 unsigned int implied_prefix
;
3804 rex_byte vrex_used
= 0;
3806 /* Check register specifier. */
3807 if (i
.vex
.register_specifier
)
3809 gas_assert ((i
.vrex
& REX_X
) == 0);
3811 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3812 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3813 register_specifier
+= 8;
3814 /* The upper 16 registers are encoded in the fourth byte of the
3816 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3817 i
.vex
.bytes
[3] = 0x8;
3818 register_specifier
= ~register_specifier
& 0xf;
3822 register_specifier
= 0xf;
3824 /* Encode upper 16 vector index register in the fourth byte of
3826 if (!(i
.vrex
& REX_X
))
3827 i
.vex
.bytes
[3] = 0x8;
3832 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3837 case DATA_PREFIX_OPCODE
:
3840 case REPE_PREFIX_OPCODE
:
3843 case REPNE_PREFIX_OPCODE
:
3850 /* 4 byte EVEX prefix. */
3852 i
.vex
.bytes
[0] = 0x62;
3855 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
3871 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3873 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3875 /* The fifth bit of the second EVEX byte is 1's compliment of the
3876 REX_R bit in VREX. */
3877 if (!(i
.vrex
& REX_R
))
3878 i
.vex
.bytes
[1] |= 0x10;
3882 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3884 /* When all operands are registers, the REX_X bit in REX is not
3885 used. We reuse it to encode the upper 16 registers, which is
3886 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3887 as 1's compliment. */
3888 if ((i
.vrex
& REX_B
))
3891 i
.vex
.bytes
[1] &= ~0x40;
3895 /* EVEX instructions shouldn't need the REX prefix. */
3896 i
.vrex
&= ~vrex_used
;
3897 gas_assert (i
.vrex
== 0);
3899 /* Check the REX.W bit and VEXW. */
3900 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3901 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3902 else if (i
.tm
.opcode_modifier
.vexw
)
3903 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3905 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3907 /* Encode the U bit. */
3908 implied_prefix
|= 0x4;
3910 /* The third byte of the EVEX prefix. */
3911 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3913 /* The fourth byte of the EVEX prefix. */
3914 /* The zeroing-masking bit. */
3915 if (i
.mask
&& i
.mask
->zeroing
)
3916 i
.vex
.bytes
[3] |= 0x80;
3918 /* Don't always set the broadcast bit if there is no RC. */
3921 /* Encode the vector length. */
3922 unsigned int vec_length
;
3924 if (!i
.tm
.opcode_modifier
.evex
3925 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3929 /* Determine vector length from the last multi-length vector
3931 for (op
= i
.operands
; op
--;)
3932 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3933 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3934 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3936 if (i
.types
[op
].bitfield
.zmmword
)
3938 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3941 else if (i
.types
[op
].bitfield
.ymmword
)
3943 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3946 else if (i
.types
[op
].bitfield
.xmmword
)
3948 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3951 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3953 switch (i
.broadcast
->bytes
)
3956 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3959 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3962 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3971 if (op
>= MAX_OPERANDS
)
3975 switch (i
.tm
.opcode_modifier
.evex
)
3977 case EVEXLIG
: /* LL' is ignored */
3978 vec_length
= evexlig
<< 5;
3981 vec_length
= 0 << 5;
3984 vec_length
= 1 << 5;
3987 vec_length
= 2 << 5;
3993 i
.vex
.bytes
[3] |= vec_length
;
3994 /* Encode the broadcast bit. */
3996 i
.vex
.bytes
[3] |= 0x10;
4000 if (i
.rounding
->type
!= saeonly
)
4001 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
4003 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4006 if (i
.mask
&& i
.mask
->mask
)
4007 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4011 process_immext (void)
4015 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4016 which is coded in the same place as an 8-bit immediate field
4017 would be. Here we fake an 8-bit immediate operand from the
4018 opcode suffix stored in tm.extension_opcode.
4020 AVX instructions also use this encoding, for some of
4021 3 argument instructions. */
4023 gas_assert (i
.imm_operands
<= 1
4025 || (is_any_vex_encoding (&i
.tm
)
4026 && i
.operands
<= 4)));
4028 exp
= &im_expressions
[i
.imm_operands
++];
4029 i
.op
[i
.operands
].imms
= exp
;
4030 i
.types
[i
.operands
] = imm8
;
4032 exp
->X_op
= O_constant
;
4033 exp
->X_add_number
= i
.tm
.extension_opcode
;
4034 i
.tm
.extension_opcode
= None
;
4041 switch (i
.tm
.opcode_modifier
.prefixok
)
4049 as_bad (_("invalid instruction `%s' after `%s'"),
4050 i
.tm
.name
, i
.hle_prefix
);
4053 if (i
.prefix
[LOCK_PREFIX
])
4055 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4059 case PrefixHLERelease
:
4060 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4062 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4066 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4068 as_bad (_("memory destination needed for instruction `%s'"
4069 " after `xrelease'"), i
.tm
.name
);
4076 /* Try the shortest encoding by shortening operand size. */
4079 optimize_encoding (void)
4083 if (optimize_for_space
4084 && !is_any_vex_encoding (&i
.tm
)
4085 && i
.reg_operands
== 1
4086 && i
.imm_operands
== 1
4087 && !i
.types
[1].bitfield
.byte
4088 && i
.op
[0].imms
->X_op
== O_constant
4089 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4090 && (i
.tm
.base_opcode
== 0xa8
4091 || (i
.tm
.base_opcode
== 0xf6
4092 && i
.tm
.extension_opcode
== 0x0)))
4095 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4097 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4098 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4100 i
.types
[1].bitfield
.byte
= 1;
4101 /* Ignore the suffix. */
4103 /* Convert to byte registers. */
4104 if (i
.types
[1].bitfield
.word
)
4106 else if (i
.types
[1].bitfield
.dword
)
4110 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4115 else if (flag_code
== CODE_64BIT
4116 && !is_any_vex_encoding (&i
.tm
)
4117 && ((i
.types
[1].bitfield
.qword
4118 && i
.reg_operands
== 1
4119 && i
.imm_operands
== 1
4120 && i
.op
[0].imms
->X_op
== O_constant
4121 && ((i
.tm
.base_opcode
== 0xb8
4122 && i
.tm
.extension_opcode
== None
4123 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4124 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4125 && ((i
.tm
.base_opcode
== 0x24
4126 || i
.tm
.base_opcode
== 0xa8)
4127 || (i
.tm
.base_opcode
== 0x80
4128 && i
.tm
.extension_opcode
== 0x4)
4129 || ((i
.tm
.base_opcode
== 0xf6
4130 || (i
.tm
.base_opcode
| 1) == 0xc7)
4131 && i
.tm
.extension_opcode
== 0x0)))
4132 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4133 && i
.tm
.base_opcode
== 0x83
4134 && i
.tm
.extension_opcode
== 0x4)))
4135 || (i
.types
[0].bitfield
.qword
4136 && ((i
.reg_operands
== 2
4137 && i
.op
[0].regs
== i
.op
[1].regs
4138 && (i
.tm
.base_opcode
== 0x30
4139 || i
.tm
.base_opcode
== 0x28))
4140 || (i
.reg_operands
== 1
4142 && i
.tm
.base_opcode
== 0x30)))))
4145 andq $imm31, %r64 -> andl $imm31, %r32
4146 andq $imm7, %r64 -> andl $imm7, %r32
4147 testq $imm31, %r64 -> testl $imm31, %r32
4148 xorq %r64, %r64 -> xorl %r32, %r32
4149 subq %r64, %r64 -> subl %r32, %r32
4150 movq $imm31, %r64 -> movl $imm31, %r32
4151 movq $imm32, %r64 -> movl $imm32, %r32
4153 i
.tm
.opcode_modifier
.norex64
= 1;
4154 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4157 movq $imm31, %r64 -> movl $imm31, %r32
4158 movq $imm32, %r64 -> movl $imm32, %r32
4160 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4161 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4162 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4163 i
.types
[0].bitfield
.imm32
= 1;
4164 i
.types
[0].bitfield
.imm32s
= 0;
4165 i
.types
[0].bitfield
.imm64
= 0;
4166 i
.types
[1].bitfield
.dword
= 1;
4167 i
.types
[1].bitfield
.qword
= 0;
4168 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4171 movq $imm31, %r64 -> movl $imm31, %r32
4173 i
.tm
.base_opcode
= 0xb8;
4174 i
.tm
.extension_opcode
= None
;
4175 i
.tm
.opcode_modifier
.w
= 0;
4176 i
.tm
.opcode_modifier
.modrm
= 0;
4180 else if (optimize
> 1
4181 && !optimize_for_space
4182 && !is_any_vex_encoding (&i
.tm
)
4183 && i
.reg_operands
== 2
4184 && i
.op
[0].regs
== i
.op
[1].regs
4185 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4186 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4187 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4190 andb %rN, %rN -> testb %rN, %rN
4191 andw %rN, %rN -> testw %rN, %rN
4192 andq %rN, %rN -> testq %rN, %rN
4193 orb %rN, %rN -> testb %rN, %rN
4194 orw %rN, %rN -> testw %rN, %rN
4195 orq %rN, %rN -> testq %rN, %rN
4197 and outside of 64-bit mode
4199 andl %rN, %rN -> testl %rN, %rN
4200 orl %rN, %rN -> testl %rN, %rN
4202 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4204 else if (i
.reg_operands
== 3
4205 && i
.op
[0].regs
== i
.op
[1].regs
4206 && !i
.types
[2].bitfield
.xmmword
4207 && (i
.tm
.opcode_modifier
.vex
4208 || ((!i
.mask
|| i
.mask
->zeroing
)
4210 && is_evex_encoding (&i
.tm
)
4211 && (i
.vec_encoding
!= vex_encoding_evex
4212 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4213 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4214 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4215 && i
.types
[2].bitfield
.ymmword
))))
4216 && ((i
.tm
.base_opcode
== 0x55
4217 || i
.tm
.base_opcode
== 0x6655
4218 || i
.tm
.base_opcode
== 0x66df
4219 || i
.tm
.base_opcode
== 0x57
4220 || i
.tm
.base_opcode
== 0x6657
4221 || i
.tm
.base_opcode
== 0x66ef
4222 || i
.tm
.base_opcode
== 0x66f8
4223 || i
.tm
.base_opcode
== 0x66f9
4224 || i
.tm
.base_opcode
== 0x66fa
4225 || i
.tm
.base_opcode
== 0x66fb
4226 || i
.tm
.base_opcode
== 0x42
4227 || i
.tm
.base_opcode
== 0x6642
4228 || i
.tm
.base_opcode
== 0x47
4229 || i
.tm
.base_opcode
== 0x6647)
4230 && i
.tm
.extension_opcode
== None
))
4233 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4235 EVEX VOP %zmmM, %zmmM, %zmmN
4236 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4237 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4238 EVEX VOP %ymmM, %ymmM, %ymmN
4239 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4240 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4241 VEX VOP %ymmM, %ymmM, %ymmN
4242 -> VEX VOP %xmmM, %xmmM, %xmmN
4243 VOP, one of vpandn and vpxor:
4244 VEX VOP %ymmM, %ymmM, %ymmN
4245 -> VEX VOP %xmmM, %xmmM, %xmmN
4246 VOP, one of vpandnd and vpandnq:
4247 EVEX VOP %zmmM, %zmmM, %zmmN
4248 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4249 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4250 EVEX VOP %ymmM, %ymmM, %ymmN
4251 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4252 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4253 VOP, one of vpxord and vpxorq:
4254 EVEX VOP %zmmM, %zmmM, %zmmN
4255 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4256 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4257 EVEX VOP %ymmM, %ymmM, %ymmN
4258 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4259 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4260 VOP, one of kxord and kxorq:
4261 VEX VOP %kM, %kM, %kN
4262 -> VEX kxorw %kM, %kM, %kN
4263 VOP, one of kandnd and kandnq:
4264 VEX VOP %kM, %kM, %kN
4265 -> VEX kandnw %kM, %kM, %kN
4267 if (is_evex_encoding (&i
.tm
))
4269 if (i
.vec_encoding
!= vex_encoding_evex
)
4271 i
.tm
.opcode_modifier
.vex
= VEX128
;
4272 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4273 i
.tm
.opcode_modifier
.evex
= 0;
4275 else if (optimize
> 1)
4276 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4280 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4282 i
.tm
.base_opcode
&= 0xff;
4283 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4286 i
.tm
.opcode_modifier
.vex
= VEX128
;
4288 if (i
.tm
.opcode_modifier
.vex
)
4289 for (j
= 0; j
< 3; j
++)
4291 i
.types
[j
].bitfield
.xmmword
= 1;
4292 i
.types
[j
].bitfield
.ymmword
= 0;
4295 else if (i
.vec_encoding
!= vex_encoding_evex
4296 && !i
.types
[0].bitfield
.zmmword
4297 && !i
.types
[1].bitfield
.zmmword
4300 && is_evex_encoding (&i
.tm
)
4301 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4302 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4303 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4304 || (i
.tm
.base_opcode
& ~4) == 0x66db
4305 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4306 && i
.tm
.extension_opcode
== None
)
4309 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4310 vmovdqu32 and vmovdqu64:
4311 EVEX VOP %xmmM, %xmmN
4312 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4313 EVEX VOP %ymmM, %ymmN
4314 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4316 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4318 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4320 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4322 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4323 VOP, one of vpand, vpandn, vpor, vpxor:
4324 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4325 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4326 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4327 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4328 EVEX VOP{d,q} mem, %xmmM, %xmmN
4329 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4330 EVEX VOP{d,q} mem, %ymmM, %ymmN
4331 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4333 for (j
= 0; j
< i
.operands
; j
++)
4334 if (operand_type_check (i
.types
[j
], disp
)
4335 && i
.op
[j
].disps
->X_op
== O_constant
)
4337 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4338 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4339 bytes, we choose EVEX Disp8 over VEX Disp32. */
4340 int evex_disp8
, vex_disp8
;
4341 unsigned int memshift
= i
.memshift
;
4342 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4344 evex_disp8
= fits_in_disp8 (n
);
4346 vex_disp8
= fits_in_disp8 (n
);
4347 if (evex_disp8
!= vex_disp8
)
4349 i
.memshift
= memshift
;
4353 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4356 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4357 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4358 i
.tm
.opcode_modifier
.vex
4359 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4360 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4361 /* VPAND, VPOR, and VPXOR are commutative. */
4362 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4363 i
.tm
.opcode_modifier
.commutative
= 1;
4364 i
.tm
.opcode_modifier
.evex
= 0;
4365 i
.tm
.opcode_modifier
.masking
= 0;
4366 i
.tm
.opcode_modifier
.broadcast
= 0;
4367 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4370 i
.types
[j
].bitfield
.disp8
4371 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4375 /* Return non-zero for load instruction. */
4381 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4382 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4386 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4387 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4388 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4389 if (i
.tm
.opcode_modifier
.anysize
)
4392 /* pop, popf, popa. */
4393 if (strcmp (i
.tm
.name
, "pop") == 0
4394 || i
.tm
.base_opcode
== 0x9d
4395 || i
.tm
.base_opcode
== 0x61)
4398 /* movs, cmps, lods, scas. */
4399 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4403 if (base_opcode
== 0x6f
4404 || i
.tm
.base_opcode
== 0xd7)
4406 /* NB: For AMD-specific insns with implicit memory operands,
4407 they're intentionally not covered. */
4410 /* No memory operand. */
4411 if (!i
.mem_operands
)
4417 if (i
.tm
.base_opcode
== 0xae
4418 && i
.tm
.opcode_modifier
.vex
4419 && i
.tm
.opcode_modifier
.opcodeprefix
== VEX0F
4420 && i
.tm
.extension_opcode
== 2)
4425 /* test, not, neg, mul, imul, div, idiv. */
4426 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4427 && i
.tm
.extension_opcode
!= 1)
4431 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4434 /* add, or, adc, sbb, and, sub, xor, cmp. */
4435 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4438 /* bt, bts, btr, btc. */
4439 if (i
.tm
.base_opcode
== 0xfba
4440 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4443 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4444 if ((base_opcode
== 0xc1
4445 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4446 && i
.tm
.extension_opcode
!= 6)
4449 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4450 if (i
.tm
.base_opcode
== 0xfc7
4451 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4452 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4453 || i
.tm
.extension_opcode
== 6))
4456 /* fxrstor, ldmxcsr, xrstor. */
4457 if (i
.tm
.base_opcode
== 0xfae
4458 && (i
.tm
.extension_opcode
== 1
4459 || i
.tm
.extension_opcode
== 2
4460 || i
.tm
.extension_opcode
== 5))
4463 /* lgdt, lidt, lmsw. */
4464 if (i
.tm
.base_opcode
== 0xf01
4465 && (i
.tm
.extension_opcode
== 2
4466 || i
.tm
.extension_opcode
== 3
4467 || i
.tm
.extension_opcode
== 6))
4470 /* Check for x87 instructions. */
4471 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4473 /* Skip fst, fstp, fstenv, fstcw. */
4474 if (i
.tm
.base_opcode
== 0xd9
4475 && (i
.tm
.extension_opcode
== 2
4476 || i
.tm
.extension_opcode
== 3
4477 || i
.tm
.extension_opcode
== 6
4478 || i
.tm
.extension_opcode
== 7))
4481 /* Skip fisttp, fist, fistp, fstp. */
4482 if (i
.tm
.base_opcode
== 0xdb
4483 && (i
.tm
.extension_opcode
== 1
4484 || i
.tm
.extension_opcode
== 2
4485 || i
.tm
.extension_opcode
== 3
4486 || i
.tm
.extension_opcode
== 7))
4489 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4490 if (i
.tm
.base_opcode
== 0xdd
4491 && (i
.tm
.extension_opcode
== 1
4492 || i
.tm
.extension_opcode
== 2
4493 || i
.tm
.extension_opcode
== 3
4494 || i
.tm
.extension_opcode
== 6
4495 || i
.tm
.extension_opcode
== 7))
4498 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4499 if (i
.tm
.base_opcode
== 0xdf
4500 && (i
.tm
.extension_opcode
== 1
4501 || i
.tm
.extension_opcode
== 2
4502 || i
.tm
.extension_opcode
== 3
4503 || i
.tm
.extension_opcode
== 6
4504 || i
.tm
.extension_opcode
== 7))
4511 dest
= i
.operands
- 1;
4513 /* Check fake imm8 operand and 3 source operands. */
4514 if ((i
.tm
.opcode_modifier
.immext
4515 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4516 && i
.types
[dest
].bitfield
.imm8
)
4519 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4521 && (base_opcode
== 0x1
4522 || base_opcode
== 0x9
4523 || base_opcode
== 0x11
4524 || base_opcode
== 0x19
4525 || base_opcode
== 0x21
4526 || base_opcode
== 0x29
4527 || base_opcode
== 0x31
4528 || base_opcode
== 0x39
4529 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4530 || base_opcode
== 0xfc1))
4533 /* Check for load instruction. */
4534 return (i
.types
[dest
].bitfield
.class != ClassNone
4535 || i
.types
[dest
].bitfield
.instance
== Accum
);
4538 /* Output lfence, 0xfaee8, after instruction. */
4541 insert_lfence_after (void)
4543 if (lfence_after_load
&& load_insn_p ())
4545 /* There are also two REP string instructions that require
4546 special treatment. Specifically, the compare string (CMPS)
4547 and scan string (SCAS) instructions set EFLAGS in a manner
4548 that depends on the data being compared/scanned. When used
4549 with a REP prefix, the number of iterations may therefore
4550 vary depending on this data. If the data is a program secret
4551 chosen by the adversary using an LVI method,
4552 then this data-dependent behavior may leak some aspect
4554 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4555 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4556 && i
.prefix
[REP_PREFIX
])
4558 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4561 char *p
= frag_more (3);
4568 /* Output lfence, 0xfaee8, before instruction. */
4571 insert_lfence_before (void)
4575 if (is_any_vex_encoding (&i
.tm
))
4578 if (i
.tm
.base_opcode
== 0xff
4579 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4581 /* Insert lfence before indirect branch if needed. */
4583 if (lfence_before_indirect_branch
== lfence_branch_none
)
4586 if (i
.operands
!= 1)
4589 if (i
.reg_operands
== 1)
4591 /* Indirect branch via register. Don't insert lfence with
4592 -mlfence-after-load=yes. */
4593 if (lfence_after_load
4594 || lfence_before_indirect_branch
== lfence_branch_memory
)
4597 else if (i
.mem_operands
== 1
4598 && lfence_before_indirect_branch
!= lfence_branch_register
)
4600 as_warn (_("indirect `%s` with memory operand should be avoided"),
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4623 /* Output or/not/shl and lfence before near ret. */
4624 if (lfence_before_ret
!= lfence_before_ret_none
4625 && (i
.tm
.base_opcode
== 0xc2
4626 || i
.tm
.base_opcode
== 0xc3))
4628 if (last_insn
.kind
!= last_insn_other
4629 && last_insn
.seg
== now_seg
)
4631 as_warn_where (last_insn
.file
, last_insn
.line
,
4632 _("`%s` skips -mlfence-before-ret on `%s`"),
4633 last_insn
.name
, i
.tm
.name
);
4637 /* Near ret ingore operand size override under CPU64. */
4638 char prefix
= flag_code
== CODE_64BIT
4640 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4642 if (lfence_before_ret
== lfence_before_ret_not
)
4644 /* not: 0xf71424, may add prefix
4645 for operand size override or 64-bit code. */
4646 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4660 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4663 if (lfence_before_ret
== lfence_before_ret_or
)
4665 /* or: 0x830c2400, may add prefix
4666 for operand size override or 64-bit code. */
4672 /* shl: 0xc1242400, may add prefix
4673 for operand size override or 64-bit code. */
4688 /* This is the guts of the machine-dependent assembler. LINE points to a
4689 machine dependent instruction. This function is supposed to emit
4690 the frags/bytes it assembles to. */
4693 md_assemble (char *line
)
4696 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4697 const insn_template
*t
;
4699 /* Initialize globals. */
4700 memset (&i
, '\0', sizeof (i
));
4701 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4702 i
.reloc
[j
] = NO_RELOC
;
4703 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4704 memset (im_expressions
, '\0', sizeof (im_expressions
));
4705 save_stack_p
= save_stack
;
4707 /* First parse an instruction mnemonic & call i386_operand for the operands.
4708 We assume that the scrubber has arranged it so that line[0] is the valid
4709 start of a (possibly prefixed) mnemonic. */
4711 line
= parse_insn (line
, mnemonic
);
4714 mnem_suffix
= i
.suffix
;
4716 line
= parse_operands (line
, mnemonic
);
4718 xfree (i
.memop1_string
);
4719 i
.memop1_string
= NULL
;
4723 /* Now we've parsed the mnemonic into a set of templates, and have the
4724 operands at hand. */
4726 /* All Intel opcodes have reversed operands except for "bound", "enter",
4727 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4728 intersegment "jmp" and "call" instructions with 2 immediate operands so
4729 that the immediate segment precedes the offset, as it does when in AT&T
4733 && (strcmp (mnemonic
, "bound") != 0)
4734 && (strcmp (mnemonic
, "invlpga") != 0)
4735 && (strncmp (mnemonic
, "monitor", 7) != 0)
4736 && (strncmp (mnemonic
, "mwait", 5) != 0)
4737 && (strcmp (mnemonic
, "tpause") != 0)
4738 && (strcmp (mnemonic
, "umwait") != 0)
4739 && !(operand_type_check (i
.types
[0], imm
)
4740 && operand_type_check (i
.types
[1], imm
)))
4743 /* The order of the immediates should be reversed
4744 for 2 immediates extrq and insertq instructions */
4745 if (i
.imm_operands
== 2
4746 && (strcmp (mnemonic
, "extrq") == 0
4747 || strcmp (mnemonic
, "insertq") == 0))
4748 swap_2_operands (0, 1);
4753 /* Don't optimize displacement for movabs since it only takes 64bit
4756 && i
.disp_encoding
!= disp_encoding_32bit
4757 && (flag_code
!= CODE_64BIT
4758 || strcmp (mnemonic
, "movabs") != 0))
4761 /* Next, we find a template that matches the given insn,
4762 making sure the overlap of the given operands types is consistent
4763 with the template operand types. */
4765 if (!(t
= match_template (mnem_suffix
)))
4768 if (sse_check
!= check_none
4769 && !i
.tm
.opcode_modifier
.noavx
4770 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4771 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4772 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4773 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4774 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4775 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4776 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4777 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4778 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4779 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4780 || i
.tm
.cpu_flags
.bitfield
.cpusha
4781 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4783 (sse_check
== check_warning
4785 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4788 if (i
.tm
.opcode_modifier
.fwait
)
4789 if (!add_prefix (FWAIT_OPCODE
))
4792 /* Check if REP prefix is OK. */
4793 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4795 as_bad (_("invalid instruction `%s' after `%s'"),
4796 i
.tm
.name
, i
.rep_prefix
);
4800 /* Check for lock without a lockable instruction. Destination operand
4801 must be memory unless it is xchg (0x86). */
4802 if (i
.prefix
[LOCK_PREFIX
]
4803 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4804 || i
.mem_operands
== 0
4805 || (i
.tm
.base_opcode
!= 0x86
4806 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4808 as_bad (_("expecting lockable instruction after `lock'"));
4812 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4813 if (i
.prefix
[DATA_PREFIX
]
4814 && (is_any_vex_encoding (&i
.tm
)
4815 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4816 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4818 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4822 /* Check if HLE prefix is OK. */
4823 if (i
.hle_prefix
&& !check_hle ())
4826 /* Check BND prefix. */
4827 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4828 as_bad (_("expecting valid branch instruction after `bnd'"));
4830 /* Check NOTRACK prefix. */
4831 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
4832 as_bad (_("expecting indirect branch instruction after `notrack'"));
4834 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4836 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4837 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4838 else if (flag_code
!= CODE_16BIT
4839 ? i
.prefix
[ADDR_PREFIX
]
4840 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4841 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4844 /* Insert BND prefix. */
4845 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4847 if (!i
.prefix
[BND_PREFIX
])
4848 add_prefix (BND_PREFIX_OPCODE
);
4849 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4851 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4852 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4856 /* Check string instruction segment overrides. */
4857 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4859 gas_assert (i
.mem_operands
);
4860 if (!check_string ())
4862 i
.disp_operands
= 0;
4865 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4866 optimize_encoding ();
4868 if (!process_suffix ())
4871 /* Update operand types and check extended states. */
4872 for (j
= 0; j
< i
.operands
; j
++)
4874 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4875 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4880 i
.xstate
|= xstate_mmx
;
4883 i
.xstate
|= xstate_mask
;
4886 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4887 i
.xstate
|= xstate_tmm
;
4888 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4889 i
.xstate
|= xstate_zmm
;
4890 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4891 i
.xstate
|= xstate_ymm
;
4892 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4893 i
.xstate
|= xstate_xmm
;
4898 /* Make still unresolved immediate matches conform to size of immediate
4899 given in i.suffix. */
4900 if (!finalize_imm ())
4903 if (i
.types
[0].bitfield
.imm1
)
4904 i
.imm_operands
= 0; /* kludge for shift insns. */
4906 /* We only need to check those implicit registers for instructions
4907 with 3 operands or less. */
4908 if (i
.operands
<= 3)
4909 for (j
= 0; j
< i
.operands
; j
++)
4910 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4911 && !i
.types
[j
].bitfield
.xmmword
)
4914 /* For insns with operands there are more diddles to do to the opcode. */
4917 if (!process_operands ())
4920 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4922 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4923 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4926 if (is_any_vex_encoding (&i
.tm
))
4928 if (!cpu_arch_flags
.bitfield
.cpui286
)
4930 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4935 /* Check for explicit REX prefix. */
4936 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4938 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4942 if (i
.tm
.opcode_modifier
.vex
)
4943 build_vex_prefix (t
);
4945 build_evex_prefix ();
4947 /* The individual REX.RXBW bits got consumed. */
4948 i
.rex
&= REX_OPCODE
;
4951 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4952 instructions may define INT_OPCODE as well, so avoid this corner
4953 case for those instructions that use MODRM. */
4954 if (i
.tm
.base_opcode
== INT_OPCODE
4955 && !i
.tm
.opcode_modifier
.modrm
4956 && i
.op
[0].imms
->X_add_number
== 3)
4958 i
.tm
.base_opcode
= INT3_OPCODE
;
4962 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4963 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4964 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4965 && i
.op
[0].disps
->X_op
== O_constant
)
4967 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4968 the absolute address given by the constant. Since ix86 jumps and
4969 calls are pc relative, we need to generate a reloc. */
4970 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4971 i
.op
[0].disps
->X_op
= O_symbol
;
4974 /* For 8 bit registers we need an empty rex prefix. Also if the
4975 instruction already has a prefix, we need to convert old
4976 registers to new ones. */
4978 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4979 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4980 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4981 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4982 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4983 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4988 i
.rex
|= REX_OPCODE
;
4989 for (x
= 0; x
< 2; x
++)
4991 /* Look for 8 bit operand that uses old registers. */
4992 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4993 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4995 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4996 /* In case it is "hi" register, give up. */
4997 if (i
.op
[x
].regs
->reg_num
> 3)
4998 as_bad (_("can't encode register '%s%s' in an "
4999 "instruction requiring REX prefix."),
5000 register_prefix
, i
.op
[x
].regs
->reg_name
);
5002 /* Otherwise it is equivalent to the extended register.
5003 Since the encoding doesn't change this is merely
5004 cosmetic cleanup for debug output. */
5006 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5011 if (i
.rex
== 0 && i
.rex_encoding
)
5013 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5014 that uses legacy register. If it is "hi" register, don't add
5015 the REX_OPCODE byte. */
5017 for (x
= 0; x
< 2; x
++)
5018 if (i
.types
[x
].bitfield
.class == Reg
5019 && i
.types
[x
].bitfield
.byte
5020 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5021 && i
.op
[x
].regs
->reg_num
> 3)
5023 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5024 i
.rex_encoding
= FALSE
;
5033 add_prefix (REX_OPCODE
| i
.rex
);
5035 insert_lfence_before ();
5037 /* We are ready to output the insn. */
5040 insert_lfence_after ();
5042 last_insn
.seg
= now_seg
;
5044 if (i
.tm
.opcode_modifier
.isprefix
)
5046 last_insn
.kind
= last_insn_prefix
;
5047 last_insn
.name
= i
.tm
.name
;
5048 last_insn
.file
= as_where (&last_insn
.line
);
5051 last_insn
.kind
= last_insn_other
;
5055 parse_insn (char *line
, char *mnemonic
)
5058 char *token_start
= l
;
5061 const insn_template
*t
;
5067 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5072 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5074 as_bad (_("no such instruction: `%s'"), token_start
);
5079 if (!is_space_char (*l
)
5080 && *l
!= END_OF_INSN
5082 || (*l
!= PREFIX_SEPARATOR
5085 as_bad (_("invalid character %s in mnemonic"),
5086 output_invalid (*l
));
5089 if (token_start
== l
)
5091 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5092 as_bad (_("expecting prefix; got nothing"));
5094 as_bad (_("expecting mnemonic; got nothing"));
5098 /* Look up instruction (or prefix) via hash table. */
5099 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5101 if (*l
!= END_OF_INSN
5102 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5103 && current_templates
5104 && current_templates
->start
->opcode_modifier
.isprefix
)
5106 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5108 as_bad ((flag_code
!= CODE_64BIT
5109 ? _("`%s' is only supported in 64-bit mode")
5110 : _("`%s' is not supported in 64-bit mode")),
5111 current_templates
->start
->name
);
5114 /* If we are in 16-bit mode, do not allow addr16 or data16.
5115 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5116 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5117 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5118 && flag_code
!= CODE_64BIT
5119 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5120 ^ (flag_code
== CODE_16BIT
)))
5122 as_bad (_("redundant %s prefix"),
5123 current_templates
->start
->name
);
5126 if (current_templates
->start
->opcode_length
== 0)
5128 /* Handle pseudo prefixes. */
5129 switch (current_templates
->start
->base_opcode
)
5133 i
.disp_encoding
= disp_encoding_8bit
;
5137 i
.disp_encoding
= disp_encoding_16bit
;
5141 i
.disp_encoding
= disp_encoding_32bit
;
5145 i
.dir_encoding
= dir_encoding_load
;
5149 i
.dir_encoding
= dir_encoding_store
;
5153 i
.vec_encoding
= vex_encoding_vex
;
5157 i
.vec_encoding
= vex_encoding_vex3
;
5161 i
.vec_encoding
= vex_encoding_evex
;
5165 i
.rex_encoding
= TRUE
;
5167 case Prefix_NoOptimize
:
5169 i
.no_optimize
= TRUE
;
5177 /* Add prefix, checking for repeated prefixes. */
5178 switch (add_prefix (current_templates
->start
->base_opcode
))
5183 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5184 i
.notrack_prefix
= current_templates
->start
->name
;
5187 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5188 i
.hle_prefix
= current_templates
->start
->name
;
5189 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5190 i
.bnd_prefix
= current_templates
->start
->name
;
5192 i
.rep_prefix
= current_templates
->start
->name
;
5198 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5205 if (!current_templates
)
5207 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5208 Check if we should swap operand or force 32bit displacement in
5210 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5211 i
.dir_encoding
= dir_encoding_swap
;
5212 else if (mnem_p
- 3 == dot_p
5215 i
.disp_encoding
= disp_encoding_8bit
;
5216 else if (mnem_p
- 4 == dot_p
5220 i
.disp_encoding
= disp_encoding_32bit
;
5225 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5228 if (!current_templates
)
5231 if (mnem_p
> mnemonic
)
5233 /* See if we can get a match by trimming off a suffix. */
5236 case WORD_MNEM_SUFFIX
:
5237 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5238 i
.suffix
= SHORT_MNEM_SUFFIX
;
5241 case BYTE_MNEM_SUFFIX
:
5242 case QWORD_MNEM_SUFFIX
:
5243 i
.suffix
= mnem_p
[-1];
5246 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5248 case SHORT_MNEM_SUFFIX
:
5249 case LONG_MNEM_SUFFIX
:
5252 i
.suffix
= mnem_p
[-1];
5255 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5263 if (intel_float_operand (mnemonic
) == 1)
5264 i
.suffix
= SHORT_MNEM_SUFFIX
;
5266 i
.suffix
= LONG_MNEM_SUFFIX
;
5269 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5275 if (!current_templates
)
5277 as_bad (_("no such instruction: `%s'"), token_start
);
5282 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5283 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5285 /* Check for a branch hint. We allow ",pt" and ",pn" for
5286 predict taken and predict not taken respectively.
5287 I'm not sure that branch hints actually do anything on loop
5288 and jcxz insns (JumpByte) for current Pentium4 chips. They
5289 may work in the future and it doesn't hurt to accept them
5291 if (l
[0] == ',' && l
[1] == 'p')
5295 if (!add_prefix (DS_PREFIX_OPCODE
))
5299 else if (l
[2] == 'n')
5301 if (!add_prefix (CS_PREFIX_OPCODE
))
5307 /* Any other comma loses. */
5310 as_bad (_("invalid character %s in mnemonic"),
5311 output_invalid (*l
));
5315 /* Check if instruction is supported on specified architecture. */
5317 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5319 supported
|= cpu_flags_match (t
);
5320 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5322 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5323 as_warn (_("use .code16 to ensure correct addressing mode"));
5329 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5330 as_bad (flag_code
== CODE_64BIT
5331 ? _("`%s' is not supported in 64-bit mode")
5332 : _("`%s' is only supported in 64-bit mode"),
5333 current_templates
->start
->name
);
5335 as_bad (_("`%s' is not supported on `%s%s'"),
5336 current_templates
->start
->name
,
5337 cpu_arch_name
? cpu_arch_name
: default_arch
,
5338 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5344 parse_operands (char *l
, const char *mnemonic
)
5348 /* 1 if operand is pending after ','. */
5349 unsigned int expecting_operand
= 0;
5351 /* Non-zero if operand parens not balanced. */
5352 unsigned int paren_not_balanced
;
5354 while (*l
!= END_OF_INSN
)
5356 /* Skip optional white space before operand. */
5357 if (is_space_char (*l
))
5359 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5361 as_bad (_("invalid character %s before operand %d"),
5362 output_invalid (*l
),
5366 token_start
= l
; /* After white space. */
5367 paren_not_balanced
= 0;
5368 while (paren_not_balanced
|| *l
!= ',')
5370 if (*l
== END_OF_INSN
)
5372 if (paren_not_balanced
)
5375 as_bad (_("unbalanced parenthesis in operand %d."),
5378 as_bad (_("unbalanced brackets in operand %d."),
5383 break; /* we are done */
5385 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5387 as_bad (_("invalid character %s in operand %d"),
5388 output_invalid (*l
),
5395 ++paren_not_balanced
;
5397 --paren_not_balanced
;
5402 ++paren_not_balanced
;
5404 --paren_not_balanced
;
5408 if (l
!= token_start
)
5409 { /* Yes, we've read in another operand. */
5410 unsigned int operand_ok
;
5411 this_operand
= i
.operands
++;
5412 if (i
.operands
> MAX_OPERANDS
)
5414 as_bad (_("spurious operands; (%d operands/instruction max)"),
5418 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5419 /* Now parse operand adding info to 'i' as we go along. */
5420 END_STRING_AND_SAVE (l
);
5422 if (i
.mem_operands
> 1)
5424 as_bad (_("too many memory references for `%s'"),
5431 i386_intel_operand (token_start
,
5432 intel_float_operand (mnemonic
));
5434 operand_ok
= i386_att_operand (token_start
);
5436 RESTORE_END_STRING (l
);
5442 if (expecting_operand
)
5444 expecting_operand_after_comma
:
5445 as_bad (_("expecting operand after ','; got nothing"));
5450 as_bad (_("expecting operand before ','; got nothing"));
5455 /* Now *l must be either ',' or END_OF_INSN. */
5458 if (*++l
== END_OF_INSN
)
5460 /* Just skip it, if it's \n complain. */
5461 goto expecting_operand_after_comma
;
5463 expecting_operand
= 1;
5470 swap_2_operands (int xchg1
, int xchg2
)
5472 union i386_op temp_op
;
5473 i386_operand_type temp_type
;
5474 unsigned int temp_flags
;
5475 enum bfd_reloc_code_real temp_reloc
;
5477 temp_type
= i
.types
[xchg2
];
5478 i
.types
[xchg2
] = i
.types
[xchg1
];
5479 i
.types
[xchg1
] = temp_type
;
5481 temp_flags
= i
.flags
[xchg2
];
5482 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5483 i
.flags
[xchg1
] = temp_flags
;
5485 temp_op
= i
.op
[xchg2
];
5486 i
.op
[xchg2
] = i
.op
[xchg1
];
5487 i
.op
[xchg1
] = temp_op
;
5489 temp_reloc
= i
.reloc
[xchg2
];
5490 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5491 i
.reloc
[xchg1
] = temp_reloc
;
5495 if (i
.mask
->operand
== xchg1
)
5496 i
.mask
->operand
= xchg2
;
5497 else if (i
.mask
->operand
== xchg2
)
5498 i
.mask
->operand
= xchg1
;
5502 if (i
.broadcast
->operand
== xchg1
)
5503 i
.broadcast
->operand
= xchg2
;
5504 else if (i
.broadcast
->operand
== xchg2
)
5505 i
.broadcast
->operand
= xchg1
;
5509 if (i
.rounding
->operand
== xchg1
)
5510 i
.rounding
->operand
= xchg2
;
5511 else if (i
.rounding
->operand
== xchg2
)
5512 i
.rounding
->operand
= xchg1
;
5517 swap_operands (void)
5523 swap_2_operands (1, i
.operands
- 2);
5527 swap_2_operands (0, i
.operands
- 1);
5533 if (i
.mem_operands
== 2)
5535 const seg_entry
*temp_seg
;
5536 temp_seg
= i
.seg
[0];
5537 i
.seg
[0] = i
.seg
[1];
5538 i
.seg
[1] = temp_seg
;
5542 /* Try to ensure constant immediates are represented in the smallest
5547 char guess_suffix
= 0;
5551 guess_suffix
= i
.suffix
;
5552 else if (i
.reg_operands
)
5554 /* Figure out a suffix from the last register operand specified.
5555 We can't do this properly yet, i.e. excluding special register
5556 instances, but the following works for instructions with
5557 immediates. In any case, we can't set i.suffix yet. */
5558 for (op
= i
.operands
; --op
>= 0;)
5559 if (i
.types
[op
].bitfield
.class != Reg
)
5561 else if (i
.types
[op
].bitfield
.byte
)
5563 guess_suffix
= BYTE_MNEM_SUFFIX
;
5566 else if (i
.types
[op
].bitfield
.word
)
5568 guess_suffix
= WORD_MNEM_SUFFIX
;
5571 else if (i
.types
[op
].bitfield
.dword
)
5573 guess_suffix
= LONG_MNEM_SUFFIX
;
5576 else if (i
.types
[op
].bitfield
.qword
)
5578 guess_suffix
= QWORD_MNEM_SUFFIX
;
5582 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5583 guess_suffix
= WORD_MNEM_SUFFIX
;
5585 for (op
= i
.operands
; --op
>= 0;)
5586 if (operand_type_check (i
.types
[op
], imm
))
5588 switch (i
.op
[op
].imms
->X_op
)
5591 /* If a suffix is given, this operand may be shortened. */
5592 switch (guess_suffix
)
5594 case LONG_MNEM_SUFFIX
:
5595 i
.types
[op
].bitfield
.imm32
= 1;
5596 i
.types
[op
].bitfield
.imm64
= 1;
5598 case WORD_MNEM_SUFFIX
:
5599 i
.types
[op
].bitfield
.imm16
= 1;
5600 i
.types
[op
].bitfield
.imm32
= 1;
5601 i
.types
[op
].bitfield
.imm32s
= 1;
5602 i
.types
[op
].bitfield
.imm64
= 1;
5604 case BYTE_MNEM_SUFFIX
:
5605 i
.types
[op
].bitfield
.imm8
= 1;
5606 i
.types
[op
].bitfield
.imm8s
= 1;
5607 i
.types
[op
].bitfield
.imm16
= 1;
5608 i
.types
[op
].bitfield
.imm32
= 1;
5609 i
.types
[op
].bitfield
.imm32s
= 1;
5610 i
.types
[op
].bitfield
.imm64
= 1;
5614 /* If this operand is at most 16 bits, convert it
5615 to a signed 16 bit number before trying to see
5616 whether it will fit in an even smaller size.
5617 This allows a 16-bit operand such as $0xffe0 to
5618 be recognised as within Imm8S range. */
5619 if ((i
.types
[op
].bitfield
.imm16
)
5620 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5622 i
.op
[op
].imms
->X_add_number
=
5623 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5626 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5627 if ((i
.types
[op
].bitfield
.imm32
)
5628 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5631 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5632 ^ ((offsetT
) 1 << 31))
5633 - ((offsetT
) 1 << 31));
5637 = operand_type_or (i
.types
[op
],
5638 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5640 /* We must avoid matching of Imm32 templates when 64bit
5641 only immediate is available. */
5642 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5643 i
.types
[op
].bitfield
.imm32
= 0;
5650 /* Symbols and expressions. */
5652 /* Convert symbolic operand to proper sizes for matching, but don't
5653 prevent matching a set of insns that only supports sizes other
5654 than those matching the insn suffix. */
5656 i386_operand_type mask
, allowed
;
5657 const insn_template
*t
;
5659 operand_type_set (&mask
, 0);
5660 operand_type_set (&allowed
, 0);
5662 for (t
= current_templates
->start
;
5663 t
< current_templates
->end
;
5666 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5667 allowed
= operand_type_and (allowed
, anyimm
);
5669 switch (guess_suffix
)
5671 case QWORD_MNEM_SUFFIX
:
5672 mask
.bitfield
.imm64
= 1;
5673 mask
.bitfield
.imm32s
= 1;
5675 case LONG_MNEM_SUFFIX
:
5676 mask
.bitfield
.imm32
= 1;
5678 case WORD_MNEM_SUFFIX
:
5679 mask
.bitfield
.imm16
= 1;
5681 case BYTE_MNEM_SUFFIX
:
5682 mask
.bitfield
.imm8
= 1;
5687 allowed
= operand_type_and (mask
, allowed
);
5688 if (!operand_type_all_zero (&allowed
))
5689 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5696 /* Try to use the smallest displacement type too. */
5698 optimize_disp (void)
5702 for (op
= i
.operands
; --op
>= 0;)
5703 if (operand_type_check (i
.types
[op
], disp
))
5705 if (i
.op
[op
].disps
->X_op
== O_constant
)
5707 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5709 if (i
.types
[op
].bitfield
.disp16
5710 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5712 /* If this operand is at most 16 bits, convert
5713 to a signed 16 bit number and don't use 64bit
5715 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5716 i
.types
[op
].bitfield
.disp64
= 0;
5719 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5720 if (i
.types
[op
].bitfield
.disp32
5721 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5723 /* If this operand is at most 32 bits, convert
5724 to a signed 32 bit number and don't use 64bit
5726 op_disp
&= (((offsetT
) 2 << 31) - 1);
5727 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5728 i
.types
[op
].bitfield
.disp64
= 0;
5731 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5733 i
.types
[op
].bitfield
.disp8
= 0;
5734 i
.types
[op
].bitfield
.disp16
= 0;
5735 i
.types
[op
].bitfield
.disp32
= 0;
5736 i
.types
[op
].bitfield
.disp32s
= 0;
5737 i
.types
[op
].bitfield
.disp64
= 0;
5741 else if (flag_code
== CODE_64BIT
)
5743 if (fits_in_signed_long (op_disp
))
5745 i
.types
[op
].bitfield
.disp64
= 0;
5746 i
.types
[op
].bitfield
.disp32s
= 1;
5748 if (i
.prefix
[ADDR_PREFIX
]
5749 && fits_in_unsigned_long (op_disp
))
5750 i
.types
[op
].bitfield
.disp32
= 1;
5752 if ((i
.types
[op
].bitfield
.disp32
5753 || i
.types
[op
].bitfield
.disp32s
5754 || i
.types
[op
].bitfield
.disp16
)
5755 && fits_in_disp8 (op_disp
))
5756 i
.types
[op
].bitfield
.disp8
= 1;
5758 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5759 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5761 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5762 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5763 i
.types
[op
].bitfield
.disp8
= 0;
5764 i
.types
[op
].bitfield
.disp16
= 0;
5765 i
.types
[op
].bitfield
.disp32
= 0;
5766 i
.types
[op
].bitfield
.disp32s
= 0;
5767 i
.types
[op
].bitfield
.disp64
= 0;
5770 /* We only support 64bit displacement on constants. */
5771 i
.types
[op
].bitfield
.disp64
= 0;
5775 /* Return 1 if there is a match in broadcast bytes between operand
5776 GIVEN and instruction template T. */
5779 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5781 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5782 && i
.types
[given
].bitfield
.byte
)
5783 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5784 && i
.types
[given
].bitfield
.word
)
5785 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5786 && i
.types
[given
].bitfield
.dword
)
5787 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5788 && i
.types
[given
].bitfield
.qword
));
5791 /* Check if operands are valid for the instruction. */
5794 check_VecOperands (const insn_template
*t
)
5799 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5800 any one operand are implicity requiring AVX512VL support if the actual
5801 operand size is YMMword or XMMword. Since this function runs after
5802 template matching, there's no need to check for YMMword/XMMword in
5804 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5805 if (!cpu_flags_all_zero (&cpu
)
5806 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5807 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5809 for (op
= 0; op
< t
->operands
; ++op
)
5811 if (t
->operand_types
[op
].bitfield
.zmmword
5812 && (i
.types
[op
].bitfield
.ymmword
5813 || i
.types
[op
].bitfield
.xmmword
))
5815 i
.error
= unsupported
;
5821 /* Without VSIB byte, we can't have a vector register for index. */
5822 if (!t
->opcode_modifier
.sib
5824 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5825 || i
.index_reg
->reg_type
.bitfield
.ymmword
5826 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5828 i
.error
= unsupported_vector_index_register
;
5832 /* Check if default mask is allowed. */
5833 if (t
->opcode_modifier
.nodefmask
5834 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5836 i
.error
= no_default_mask
;
5840 /* For VSIB byte, we need a vector register for index, and all vector
5841 registers must be distinct. */
5842 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5845 || !((t
->opcode_modifier
.sib
== VECSIB128
5846 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5847 || (t
->opcode_modifier
.sib
== VECSIB256
5848 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5849 || (t
->opcode_modifier
.sib
== VECSIB512
5850 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5852 i
.error
= invalid_vsib_address
;
5856 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5857 if (i
.reg_operands
== 2 && !i
.mask
)
5859 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5860 gas_assert (i
.types
[0].bitfield
.xmmword
5861 || i
.types
[0].bitfield
.ymmword
);
5862 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5863 gas_assert (i
.types
[2].bitfield
.xmmword
5864 || i
.types
[2].bitfield
.ymmword
);
5865 if (operand_check
== check_none
)
5867 if (register_number (i
.op
[0].regs
)
5868 != register_number (i
.index_reg
)
5869 && register_number (i
.op
[2].regs
)
5870 != register_number (i
.index_reg
)
5871 && register_number (i
.op
[0].regs
)
5872 != register_number (i
.op
[2].regs
))
5874 if (operand_check
== check_error
)
5876 i
.error
= invalid_vector_register_set
;
5879 as_warn (_("mask, index, and destination registers should be distinct"));
5881 else if (i
.reg_operands
== 1 && i
.mask
)
5883 if (i
.types
[1].bitfield
.class == RegSIMD
5884 && (i
.types
[1].bitfield
.xmmword
5885 || i
.types
[1].bitfield
.ymmword
5886 || i
.types
[1].bitfield
.zmmword
)
5887 && (register_number (i
.op
[1].regs
)
5888 == register_number (i
.index_reg
)))
5890 if (operand_check
== check_error
)
5892 i
.error
= invalid_vector_register_set
;
5895 if (operand_check
!= check_none
)
5896 as_warn (_("index and destination registers should be distinct"));
5901 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5903 if (t
->operand_types
[0].bitfield
.tmmword
5904 && i
.reg_operands
== 3)
5906 if (register_number (i
.op
[0].regs
)
5907 == register_number (i
.op
[1].regs
)
5908 || register_number (i
.op
[0].regs
)
5909 == register_number (i
.op
[2].regs
)
5910 || register_number (i
.op
[1].regs
)
5911 == register_number (i
.op
[2].regs
))
5913 i
.error
= invalid_tmm_register_set
;
5918 /* Check if broadcast is supported by the instruction and is applied
5919 to the memory operand. */
5922 i386_operand_type type
, overlap
;
5924 /* Check if specified broadcast is supported in this instruction,
5925 and its broadcast bytes match the memory operand. */
5926 op
= i
.broadcast
->operand
;
5927 if (!t
->opcode_modifier
.broadcast
5928 || !(i
.flags
[op
] & Operand_Mem
)
5929 || (!i
.types
[op
].bitfield
.unspecified
5930 && !match_broadcast_size (t
, op
)))
5933 i
.error
= unsupported_broadcast
;
5937 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5938 * i
.broadcast
->type
);
5939 operand_type_set (&type
, 0);
5940 switch (i
.broadcast
->bytes
)
5943 type
.bitfield
.word
= 1;
5946 type
.bitfield
.dword
= 1;
5949 type
.bitfield
.qword
= 1;
5952 type
.bitfield
.xmmword
= 1;
5955 type
.bitfield
.ymmword
= 1;
5958 type
.bitfield
.zmmword
= 1;
5964 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5965 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5966 && t
->operand_types
[op
].bitfield
.byte
5967 + t
->operand_types
[op
].bitfield
.word
5968 + t
->operand_types
[op
].bitfield
.dword
5969 + t
->operand_types
[op
].bitfield
.qword
> 1)
5971 overlap
.bitfield
.xmmword
= 0;
5972 overlap
.bitfield
.ymmword
= 0;
5973 overlap
.bitfield
.zmmword
= 0;
5975 if (operand_type_all_zero (&overlap
))
5978 if (t
->opcode_modifier
.checkregsize
)
5982 type
.bitfield
.baseindex
= 1;
5983 for (j
= 0; j
< i
.operands
; ++j
)
5986 && !operand_type_register_match(i
.types
[j
],
5987 t
->operand_types
[j
],
5989 t
->operand_types
[op
]))
5994 /* If broadcast is supported in this instruction, we need to check if
5995 operand of one-element size isn't specified without broadcast. */
5996 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5998 /* Find memory operand. */
5999 for (op
= 0; op
< i
.operands
; op
++)
6000 if (i
.flags
[op
] & Operand_Mem
)
6002 gas_assert (op
< i
.operands
);
6003 /* Check size of the memory operand. */
6004 if (match_broadcast_size (t
, op
))
6006 i
.error
= broadcast_needed
;
6011 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6013 /* Check if requested masking is supported. */
6016 switch (t
->opcode_modifier
.masking
)
6020 case MERGING_MASKING
:
6021 if (i
.mask
->zeroing
)
6024 i
.error
= unsupported_masking
;
6028 case DYNAMIC_MASKING
:
6029 /* Memory destinations allow only merging masking. */
6030 if (i
.mask
->zeroing
&& i
.mem_operands
)
6032 /* Find memory operand. */
6033 for (op
= 0; op
< i
.operands
; op
++)
6034 if (i
.flags
[op
] & Operand_Mem
)
6036 gas_assert (op
< i
.operands
);
6037 if (op
== i
.operands
- 1)
6039 i
.error
= unsupported_masking
;
6049 /* Check if masking is applied to dest operand. */
6050 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6052 i
.error
= mask_not_on_destination
;
6059 if (!t
->opcode_modifier
.sae
6060 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6062 i
.error
= unsupported_rc_sae
;
6065 /* If the instruction has several immediate operands and one of
6066 them is rounding, the rounding operand should be the last
6067 immediate operand. */
6068 if (i
.imm_operands
> 1
6069 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6071 i
.error
= rc_sae_operand_not_last_imm
;
6076 /* Check the special Imm4 cases; must be the first operand. */
6077 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6079 if (i
.op
[0].imms
->X_op
!= O_constant
6080 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6086 /* Turn off Imm<N> so that update_imm won't complain. */
6087 operand_type_set (&i
.types
[0], 0);
6090 /* Check vector Disp8 operand. */
6091 if (t
->opcode_modifier
.disp8memshift
6092 && i
.disp_encoding
!= disp_encoding_32bit
)
6095 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6096 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6097 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6100 const i386_operand_type
*type
= NULL
;
6103 for (op
= 0; op
< i
.operands
; op
++)
6104 if (i
.flags
[op
] & Operand_Mem
)
6106 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6107 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6108 else if (t
->operand_types
[op
].bitfield
.xmmword
6109 + t
->operand_types
[op
].bitfield
.ymmword
6110 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6111 type
= &t
->operand_types
[op
];
6112 else if (!i
.types
[op
].bitfield
.unspecified
)
6113 type
= &i
.types
[op
];
6115 else if (i
.types
[op
].bitfield
.class == RegSIMD
6116 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6118 if (i
.types
[op
].bitfield
.zmmword
)
6120 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6122 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6128 if (type
->bitfield
.zmmword
)
6130 else if (type
->bitfield
.ymmword
)
6132 else if (type
->bitfield
.xmmword
)
6136 /* For the check in fits_in_disp8(). */
6137 if (i
.memshift
== 0)
6141 for (op
= 0; op
< i
.operands
; op
++)
6142 if (operand_type_check (i
.types
[op
], disp
)
6143 && i
.op
[op
].disps
->X_op
== O_constant
)
6145 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6147 i
.types
[op
].bitfield
.disp8
= 1;
6150 i
.types
[op
].bitfield
.disp8
= 0;
6159 /* Check if encoding requirements are met by the instruction. */
6162 VEX_check_encoding (const insn_template
*t
)
6164 if (i
.vec_encoding
== vex_encoding_error
)
6166 i
.error
= unsupported
;
6170 if (i
.vec_encoding
== vex_encoding_evex
)
6172 /* This instruction must be encoded with EVEX prefix. */
6173 if (!is_evex_encoding (t
))
6175 i
.error
= unsupported
;
6181 if (!t
->opcode_modifier
.vex
)
6183 /* This instruction template doesn't have VEX prefix. */
6184 if (i
.vec_encoding
!= vex_encoding_default
)
6186 i
.error
= unsupported
;
6195 static const insn_template
*
6196 match_template (char mnem_suffix
)
6198 /* Points to template once we've found it. */
6199 const insn_template
*t
;
6200 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6201 i386_operand_type overlap4
;
6202 unsigned int found_reverse_match
;
6203 i386_opcode_modifier suffix_check
;
6204 i386_operand_type operand_types
[MAX_OPERANDS
];
6205 int addr_prefix_disp
;
6206 unsigned int j
, size_match
, check_register
;
6207 enum i386_error specific_error
= 0;
6209 #if MAX_OPERANDS != 5
6210 # error "MAX_OPERANDS must be 5."
6213 found_reverse_match
= 0;
6214 addr_prefix_disp
= -1;
6216 /* Prepare for mnemonic suffix check. */
6217 memset (&suffix_check
, 0, sizeof (suffix_check
));
6218 switch (mnem_suffix
)
6220 case BYTE_MNEM_SUFFIX
:
6221 suffix_check
.no_bsuf
= 1;
6223 case WORD_MNEM_SUFFIX
:
6224 suffix_check
.no_wsuf
= 1;
6226 case SHORT_MNEM_SUFFIX
:
6227 suffix_check
.no_ssuf
= 1;
6229 case LONG_MNEM_SUFFIX
:
6230 suffix_check
.no_lsuf
= 1;
6232 case QWORD_MNEM_SUFFIX
:
6233 suffix_check
.no_qsuf
= 1;
6236 /* NB: In Intel syntax, normally we can check for memory operand
6237 size when there is no mnemonic suffix. But jmp and call have
6238 2 different encodings with Dword memory operand size, one with
6239 No_ldSuf and the other without. i.suffix is set to
6240 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6241 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6242 suffix_check
.no_ldsuf
= 1;
6245 /* Must have right number of operands. */
6246 i
.error
= number_of_operands_mismatch
;
6248 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6250 addr_prefix_disp
= -1;
6251 found_reverse_match
= 0;
6253 if (i
.operands
!= t
->operands
)
6256 /* Check processor support. */
6257 i
.error
= unsupported
;
6258 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6261 /* Check Pseudo Prefix. */
6262 i
.error
= unsupported
;
6263 if (t
->opcode_modifier
.pseudovexprefix
6264 && !(i
.vec_encoding
== vex_encoding_vex
6265 || i
.vec_encoding
== vex_encoding_vex3
))
6268 /* Check AT&T mnemonic. */
6269 i
.error
= unsupported_with_intel_mnemonic
;
6270 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6273 /* Check AT&T/Intel syntax. */
6274 i
.error
= unsupported_syntax
;
6275 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6276 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6279 /* Check Intel64/AMD64 ISA. */
6283 /* Default: Don't accept Intel64. */
6284 if (t
->opcode_modifier
.isa64
== INTEL64
)
6288 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6289 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6293 /* -mintel64: Don't accept AMD64. */
6294 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6299 /* Check the suffix. */
6300 i
.error
= invalid_instruction_suffix
;
6301 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6302 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6303 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6304 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6305 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6306 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6309 size_match
= operand_size_match (t
);
6313 /* This is intentionally not
6315 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6317 as the case of a missing * on the operand is accepted (perhaps with
6318 a warning, issued further down). */
6319 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6321 i
.error
= operand_type_mismatch
;
6325 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6326 operand_types
[j
] = t
->operand_types
[j
];
6328 /* In general, don't allow
6329 - 64-bit operands outside of 64-bit mode,
6330 - 32-bit operands on pre-386. */
6331 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6332 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6333 && flag_code
!= CODE_64BIT
6334 && !(t
->base_opcode
== 0xfc7
6335 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
6336 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6337 || (i
.suffix
== LONG_MNEM_SUFFIX
6338 && !cpu_arch_flags
.bitfield
.cpui386
))
6340 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6341 && !intel_float_operand (t
->name
))
6342 : intel_float_operand (t
->name
) != 2)
6343 && (t
->operands
== i
.imm_operands
6344 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6345 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6346 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6347 || (operand_types
[j
].bitfield
.class != RegMMX
6348 && operand_types
[j
].bitfield
.class != RegSIMD
6349 && operand_types
[j
].bitfield
.class != RegMask
))
6350 && !t
->opcode_modifier
.sib
)
6353 /* Do not verify operands when there are none. */
6356 if (VEX_check_encoding (t
))
6358 specific_error
= i
.error
;
6362 /* We've found a match; break out of loop. */
6366 if (!t
->opcode_modifier
.jump
6367 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6369 /* There should be only one Disp operand. */
6370 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6371 if (operand_type_check (operand_types
[j
], disp
))
6373 if (j
< MAX_OPERANDS
)
6375 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6377 addr_prefix_disp
= j
;
6379 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6380 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6384 override
= !override
;
6387 if (operand_types
[j
].bitfield
.disp32
6388 && operand_types
[j
].bitfield
.disp16
)
6390 operand_types
[j
].bitfield
.disp16
= override
;
6391 operand_types
[j
].bitfield
.disp32
= !override
;
6393 operand_types
[j
].bitfield
.disp32s
= 0;
6394 operand_types
[j
].bitfield
.disp64
= 0;
6398 if (operand_types
[j
].bitfield
.disp32s
6399 || operand_types
[j
].bitfield
.disp64
)
6401 operand_types
[j
].bitfield
.disp64
&= !override
;
6402 operand_types
[j
].bitfield
.disp32s
&= !override
;
6403 operand_types
[j
].bitfield
.disp32
= override
;
6405 operand_types
[j
].bitfield
.disp16
= 0;
6411 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6412 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6415 /* We check register size if needed. */
6416 if (t
->opcode_modifier
.checkregsize
)
6418 check_register
= (1 << t
->operands
) - 1;
6420 check_register
&= ~(1 << i
.broadcast
->operand
);
6425 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6426 switch (t
->operands
)
6429 if (!operand_type_match (overlap0
, i
.types
[0]))
6433 /* xchg %eax, %eax is a special case. It is an alias for nop
6434 only in 32bit mode and we can use opcode 0x90. In 64bit
6435 mode, we can't use 0x90 for xchg %eax, %eax since it should
6436 zero-extend %eax to %rax. */
6437 if (flag_code
== CODE_64BIT
6438 && t
->base_opcode
== 0x90
6439 && i
.types
[0].bitfield
.instance
== Accum
6440 && i
.types
[0].bitfield
.dword
6441 && i
.types
[1].bitfield
.instance
== Accum
6442 && i
.types
[1].bitfield
.dword
)
6444 /* xrelease mov %eax, <disp> is another special case. It must not
6445 match the accumulator-only encoding of mov. */
6446 if (flag_code
!= CODE_64BIT
6448 && t
->base_opcode
== 0xa0
6449 && i
.types
[0].bitfield
.instance
== Accum
6450 && (i
.flags
[1] & Operand_Mem
))
6455 if (!(size_match
& MATCH_STRAIGHT
))
6457 /* Reverse direction of operands if swapping is possible in the first
6458 place (operands need to be symmetric) and
6459 - the load form is requested, and the template is a store form,
6460 - the store form is requested, and the template is a load form,
6461 - the non-default (swapped) form is requested. */
6462 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6463 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6464 && !operand_type_all_zero (&overlap1
))
6465 switch (i
.dir_encoding
)
6467 case dir_encoding_load
:
6468 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6469 || t
->opcode_modifier
.regmem
)
6473 case dir_encoding_store
:
6474 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6475 && !t
->opcode_modifier
.regmem
)
6479 case dir_encoding_swap
:
6482 case dir_encoding_default
:
6485 /* If we want store form, we skip the current load. */
6486 if ((i
.dir_encoding
== dir_encoding_store
6487 || i
.dir_encoding
== dir_encoding_swap
)
6488 && i
.mem_operands
== 0
6489 && t
->opcode_modifier
.load
)
6494 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6495 if (!operand_type_match (overlap0
, i
.types
[0])
6496 || !operand_type_match (overlap1
, i
.types
[1])
6497 || ((check_register
& 3) == 3
6498 && !operand_type_register_match (i
.types
[0],
6503 /* Check if other direction is valid ... */
6504 if (!t
->opcode_modifier
.d
)
6508 if (!(size_match
& MATCH_REVERSE
))
6510 /* Try reversing direction of operands. */
6511 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6512 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6513 if (!operand_type_match (overlap0
, i
.types
[0])
6514 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6516 && !operand_type_register_match (i
.types
[0],
6517 operand_types
[i
.operands
- 1],
6518 i
.types
[i
.operands
- 1],
6521 /* Does not match either direction. */
6524 /* found_reverse_match holds which of D or FloatR
6526 if (!t
->opcode_modifier
.d
)
6527 found_reverse_match
= 0;
6528 else if (operand_types
[0].bitfield
.tbyte
)
6529 found_reverse_match
= Opcode_FloatD
;
6530 else if (operand_types
[0].bitfield
.xmmword
6531 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6532 || operand_types
[0].bitfield
.class == RegMMX
6533 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6534 || is_any_vex_encoding(t
))
6535 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6536 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6538 found_reverse_match
= Opcode_D
;
6539 if (t
->opcode_modifier
.floatr
)
6540 found_reverse_match
|= Opcode_FloatR
;
6544 /* Found a forward 2 operand match here. */
6545 switch (t
->operands
)
6548 overlap4
= operand_type_and (i
.types
[4],
6552 overlap3
= operand_type_and (i
.types
[3],
6556 overlap2
= operand_type_and (i
.types
[2],
6561 switch (t
->operands
)
6564 if (!operand_type_match (overlap4
, i
.types
[4])
6565 || !operand_type_register_match (i
.types
[3],
6572 if (!operand_type_match (overlap3
, i
.types
[3])
6573 || ((check_register
& 0xa) == 0xa
6574 && !operand_type_register_match (i
.types
[1],
6578 || ((check_register
& 0xc) == 0xc
6579 && !operand_type_register_match (i
.types
[2],
6586 /* Here we make use of the fact that there are no
6587 reverse match 3 operand instructions. */
6588 if (!operand_type_match (overlap2
, i
.types
[2])
6589 || ((check_register
& 5) == 5
6590 && !operand_type_register_match (i
.types
[0],
6594 || ((check_register
& 6) == 6
6595 && !operand_type_register_match (i
.types
[1],
6603 /* Found either forward/reverse 2, 3 or 4 operand match here:
6604 slip through to break. */
6607 /* Check if vector operands are valid. */
6608 if (check_VecOperands (t
))
6610 specific_error
= i
.error
;
6614 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6615 if (VEX_check_encoding (t
))
6617 specific_error
= i
.error
;
6621 /* We've found a match; break out of loop. */
6625 if (t
== current_templates
->end
)
6627 /* We found no match. */
6628 const char *err_msg
;
6629 switch (specific_error
? specific_error
: i
.error
)
6633 case operand_size_mismatch
:
6634 err_msg
= _("operand size mismatch");
6636 case operand_type_mismatch
:
6637 err_msg
= _("operand type mismatch");
6639 case register_type_mismatch
:
6640 err_msg
= _("register type mismatch");
6642 case number_of_operands_mismatch
:
6643 err_msg
= _("number of operands mismatch");
6645 case invalid_instruction_suffix
:
6646 err_msg
= _("invalid instruction suffix");
6649 err_msg
= _("constant doesn't fit in 4 bits");
6651 case unsupported_with_intel_mnemonic
:
6652 err_msg
= _("unsupported with Intel mnemonic");
6654 case unsupported_syntax
:
6655 err_msg
= _("unsupported syntax");
6658 as_bad (_("unsupported instruction `%s'"),
6659 current_templates
->start
->name
);
6661 case invalid_sib_address
:
6662 err_msg
= _("invalid SIB address");
6664 case invalid_vsib_address
:
6665 err_msg
= _("invalid VSIB address");
6667 case invalid_vector_register_set
:
6668 err_msg
= _("mask, index, and destination registers must be distinct");
6670 case invalid_tmm_register_set
:
6671 err_msg
= _("all tmm registers must be distinct");
6673 case unsupported_vector_index_register
:
6674 err_msg
= _("unsupported vector index register");
6676 case unsupported_broadcast
:
6677 err_msg
= _("unsupported broadcast");
6679 case broadcast_needed
:
6680 err_msg
= _("broadcast is needed for operand of such type");
6682 case unsupported_masking
:
6683 err_msg
= _("unsupported masking");
6685 case mask_not_on_destination
:
6686 err_msg
= _("mask not on destination operand");
6688 case no_default_mask
:
6689 err_msg
= _("default mask isn't allowed");
6691 case unsupported_rc_sae
:
6692 err_msg
= _("unsupported static rounding/sae");
6694 case rc_sae_operand_not_last_imm
:
6696 err_msg
= _("RC/SAE operand must precede immediate operands");
6698 err_msg
= _("RC/SAE operand must follow immediate operands");
6700 case invalid_register_operand
:
6701 err_msg
= _("invalid register operand");
6704 as_bad (_("%s for `%s'"), err_msg
,
6705 current_templates
->start
->name
);
6709 if (!quiet_warnings
)
6712 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6713 as_warn (_("indirect %s without `*'"), t
->name
);
6715 if (t
->opcode_modifier
.isprefix
6716 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6718 /* Warn them that a data or address size prefix doesn't
6719 affect assembly of the next line of code. */
6720 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6724 /* Copy the template we found. */
6727 if (addr_prefix_disp
!= -1)
6728 i
.tm
.operand_types
[addr_prefix_disp
]
6729 = operand_types
[addr_prefix_disp
];
6731 if (found_reverse_match
)
6733 /* If we found a reverse match we must alter the opcode direction
6734 bit and clear/flip the regmem modifier one. found_reverse_match
6735 holds bits to change (different for int & float insns). */
6737 i
.tm
.base_opcode
^= found_reverse_match
;
6739 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6740 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6742 /* Certain SIMD insns have their load forms specified in the opcode
6743 table, and hence we need to _set_ RegMem instead of clearing it.
6744 We need to avoid setting the bit though on insns like KMOVW. */
6745 i
.tm
.opcode_modifier
.regmem
6746 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6747 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6748 && !i
.tm
.opcode_modifier
.regmem
;
6757 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6758 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6760 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6762 as_bad (_("`%s' operand %u must use `%ses' segment"),
6764 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6769 /* There's only ever one segment override allowed per instruction.
6770 This instruction possibly has a legal segment override on the
6771 second operand, so copy the segment to where non-string
6772 instructions store it, allowing common code. */
6773 i
.seg
[op
] = i
.seg
[1];
6779 process_suffix (void)
6781 bfd_boolean is_crc32
= FALSE
;
6783 /* If matched instruction specifies an explicit instruction mnemonic
6785 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6786 i
.suffix
= WORD_MNEM_SUFFIX
;
6787 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6788 i
.suffix
= LONG_MNEM_SUFFIX
;
6789 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6790 i
.suffix
= QWORD_MNEM_SUFFIX
;
6791 else if (i
.reg_operands
6792 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6793 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6795 unsigned int numop
= i
.operands
;
6797 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6798 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6800 /* movsx/movzx want only their source operand considered here, for the
6801 ambiguity checking below. The suffix will be replaced afterwards
6802 to represent the destination (register). */
6803 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6804 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6807 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6808 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6811 /* If there's no instruction mnemonic suffix we try to invent one
6812 based on GPR operands. */
6815 /* We take i.suffix from the last register operand specified,
6816 Destination register type is more significant than source
6817 register type. crc32 in SSE4.2 prefers source register
6819 unsigned int op
= is_crc32
? 1 : i
.operands
;
6822 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6823 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6825 if (i
.types
[op
].bitfield
.class != Reg
)
6827 if (i
.types
[op
].bitfield
.byte
)
6828 i
.suffix
= BYTE_MNEM_SUFFIX
;
6829 else if (i
.types
[op
].bitfield
.word
)
6830 i
.suffix
= WORD_MNEM_SUFFIX
;
6831 else if (i
.types
[op
].bitfield
.dword
)
6832 i
.suffix
= LONG_MNEM_SUFFIX
;
6833 else if (i
.types
[op
].bitfield
.qword
)
6834 i
.suffix
= QWORD_MNEM_SUFFIX
;
6840 /* As an exception, movsx/movzx silently default to a byte source
6842 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6843 && !i
.suffix
&& !intel_syntax
)
6844 i
.suffix
= BYTE_MNEM_SUFFIX
;
6846 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6849 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6850 && i
.tm
.opcode_modifier
.no_bsuf
)
6852 else if (!check_byte_reg ())
6855 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6858 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6859 && i
.tm
.opcode_modifier
.no_lsuf
6860 && !i
.tm
.opcode_modifier
.todword
6861 && !i
.tm
.opcode_modifier
.toqword
)
6863 else if (!check_long_reg ())
6866 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6869 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6870 && i
.tm
.opcode_modifier
.no_qsuf
6871 && !i
.tm
.opcode_modifier
.todword
6872 && !i
.tm
.opcode_modifier
.toqword
)
6874 else if (!check_qword_reg ())
6877 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6880 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6881 && i
.tm
.opcode_modifier
.no_wsuf
)
6883 else if (!check_word_reg ())
6886 else if (intel_syntax
6887 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6888 /* Do nothing if the instruction is going to ignore the prefix. */
6893 /* Undo the movsx/movzx change done above. */
6896 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6899 i
.suffix
= stackop_size
;
6900 if (stackop_size
== LONG_MNEM_SUFFIX
)
6902 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6903 .code16gcc directive to support 16-bit mode with
6904 32-bit address. For IRET without a suffix, generate
6905 16-bit IRET (opcode 0xcf) to return from an interrupt
6907 if (i
.tm
.base_opcode
== 0xcf)
6909 i
.suffix
= WORD_MNEM_SUFFIX
;
6910 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6912 /* Warn about changed behavior for segment register push/pop. */
6913 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6914 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6919 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6920 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6921 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6922 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6923 && i
.tm
.extension_opcode
<= 3)))
6928 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6930 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6931 || i
.tm
.opcode_modifier
.no_lsuf
)
6932 i
.suffix
= QWORD_MNEM_SUFFIX
;
6937 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6938 i
.suffix
= LONG_MNEM_SUFFIX
;
6941 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6942 i
.suffix
= WORD_MNEM_SUFFIX
;
6948 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6949 /* Also cover lret/retf/iret in 64-bit mode. */
6950 || (flag_code
== CODE_64BIT
6951 && !i
.tm
.opcode_modifier
.no_lsuf
6952 && !i
.tm
.opcode_modifier
.no_qsuf
))
6953 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6954 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6955 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6956 /* Accept FLDENV et al without suffix. */
6957 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6959 unsigned int suffixes
, evex
= 0;
6961 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6962 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6964 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6966 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6968 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6970 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6973 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6974 also suitable for AT&T syntax mode, it was requested that this be
6975 restricted to just Intel syntax. */
6976 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6980 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6982 if (is_evex_encoding (&i
.tm
)
6983 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6985 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6986 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6987 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6988 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6989 if (!i
.tm
.opcode_modifier
.evex
6990 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6991 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6994 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6995 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6996 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6999 /* Any properly sized operand disambiguates the insn. */
7000 if (i
.types
[op
].bitfield
.xmmword
7001 || i
.types
[op
].bitfield
.ymmword
7002 || i
.types
[op
].bitfield
.zmmword
)
7004 suffixes
&= ~(7 << 6);
7009 if ((i
.flags
[op
] & Operand_Mem
)
7010 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7012 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7014 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7016 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7018 if (is_evex_encoding (&i
.tm
))
7024 /* Are multiple suffixes / operand sizes allowed? */
7025 if (suffixes
& (suffixes
- 1))
7028 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7029 || operand_check
== check_error
))
7031 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7034 if (operand_check
== check_error
)
7036 as_bad (_("no instruction mnemonic suffix given and "
7037 "no register operands; can't size `%s'"), i
.tm
.name
);
7040 if (operand_check
== check_warning
)
7041 as_warn (_("%s; using default for `%s'"),
7043 ? _("ambiguous operand size")
7044 : _("no instruction mnemonic suffix given and "
7045 "no register operands"),
7048 if (i
.tm
.opcode_modifier
.floatmf
)
7049 i
.suffix
= SHORT_MNEM_SUFFIX
;
7050 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7051 || (i
.tm
.base_opcode
== 0x63
7052 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7053 /* handled below */;
7055 i
.tm
.opcode_modifier
.evex
= evex
;
7056 else if (flag_code
== CODE_16BIT
)
7057 i
.suffix
= WORD_MNEM_SUFFIX
;
7058 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7059 i
.suffix
= LONG_MNEM_SUFFIX
;
7061 i
.suffix
= QWORD_MNEM_SUFFIX
;
7065 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7066 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7068 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7069 In AT&T syntax, if there is no suffix (warned about above), the default
7070 will be byte extension. */
7071 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7072 i
.tm
.base_opcode
|= 1;
7074 /* For further processing, the suffix should represent the destination
7075 (register). This is already the case when one was used with
7076 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7077 no suffix to begin with. */
7078 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7080 if (i
.types
[1].bitfield
.word
)
7081 i
.suffix
= WORD_MNEM_SUFFIX
;
7082 else if (i
.types
[1].bitfield
.qword
)
7083 i
.suffix
= QWORD_MNEM_SUFFIX
;
7085 i
.suffix
= LONG_MNEM_SUFFIX
;
7087 i
.tm
.opcode_modifier
.w
= 0;
7091 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7092 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7093 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7095 /* Change the opcode based on the operand size given by i.suffix. */
7098 /* Size floating point instruction. */
7099 case LONG_MNEM_SUFFIX
:
7100 if (i
.tm
.opcode_modifier
.floatmf
)
7102 i
.tm
.base_opcode
^= 4;
7106 case WORD_MNEM_SUFFIX
:
7107 case QWORD_MNEM_SUFFIX
:
7108 /* It's not a byte, select word/dword operation. */
7109 if (i
.tm
.opcode_modifier
.w
)
7112 i
.tm
.base_opcode
|= 8;
7114 i
.tm
.base_opcode
|= 1;
7117 case SHORT_MNEM_SUFFIX
:
7118 /* Now select between word & dword operations via the operand
7119 size prefix, except for instructions that will ignore this
7121 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7122 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7123 && !i
.tm
.opcode_modifier
.floatmf
7124 && !is_any_vex_encoding (&i
.tm
)
7125 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7126 || (flag_code
== CODE_64BIT
7127 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7129 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7131 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7132 prefix
= ADDR_PREFIX_OPCODE
;
7134 if (!add_prefix (prefix
))
7138 /* Set mode64 for an operand. */
7139 if (i
.suffix
== QWORD_MNEM_SUFFIX
7140 && flag_code
== CODE_64BIT
7141 && !i
.tm
.opcode_modifier
.norex64
7142 && !i
.tm
.opcode_modifier
.vexw
7143 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7145 && ! (i
.operands
== 2
7146 && i
.tm
.base_opcode
== 0x90
7147 && i
.tm
.extension_opcode
== None
7148 && i
.types
[0].bitfield
.instance
== Accum
7149 && i
.types
[0].bitfield
.qword
7150 && i
.types
[1].bitfield
.instance
== Accum
7151 && i
.types
[1].bitfield
.qword
))
7157 /* Select word/dword/qword operation with explicit data sizing prefix
7158 when there are no suitable register operands. */
7159 if (i
.tm
.opcode_modifier
.w
7160 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7162 || (i
.reg_operands
== 1
7164 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7166 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7167 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7170 i
.tm
.base_opcode
|= 1;
7174 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7176 gas_assert (!i
.suffix
);
7177 gas_assert (i
.reg_operands
);
7179 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7182 /* The address size override prefix changes the size of the
7184 if (flag_code
== CODE_64BIT
7185 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7187 as_bad (_("16-bit addressing unavailable for `%s'"),
7192 if ((flag_code
== CODE_32BIT
7193 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7194 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7195 && !add_prefix (ADDR_PREFIX_OPCODE
))
7200 /* Check invalid register operand when the address size override
7201 prefix changes the size of register operands. */
7203 enum { need_word
, need_dword
, need_qword
} need
;
7205 /* Check the register operand for the address size prefix if
7206 the memory operand has no real registers, like symbol, DISP
7208 if (i
.mem_operands
== 1
7209 && i
.reg_operands
== 1
7211 && i
.types
[1].bitfield
.class == Reg
7212 && (flag_code
== CODE_32BIT
7213 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7214 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7215 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7217 && i
.base_reg
->reg_num
== RegIP
7218 && i
.base_reg
->reg_type
.bitfield
.qword
))
7219 && !add_prefix (ADDR_PREFIX_OPCODE
))
7222 if (flag_code
== CODE_32BIT
)
7223 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7224 else if (i
.prefix
[ADDR_PREFIX
])
7227 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7229 for (op
= 0; op
< i
.operands
; op
++)
7231 if (i
.types
[op
].bitfield
.class != Reg
)
7237 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7241 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7245 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7250 as_bad (_("invalid register operand size for `%s'"),
7261 check_byte_reg (void)
7265 for (op
= i
.operands
; --op
>= 0;)
7267 /* Skip non-register operands. */
7268 if (i
.types
[op
].bitfield
.class != Reg
)
7271 /* If this is an eight bit register, it's OK. If it's the 16 or
7272 32 bit version of an eight bit register, we will just use the
7273 low portion, and that's OK too. */
7274 if (i
.types
[op
].bitfield
.byte
)
7277 /* I/O port address operands are OK too. */
7278 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7279 && i
.tm
.operand_types
[op
].bitfield
.word
)
7282 /* crc32 only wants its source operand checked here. */
7283 if (i
.tm
.base_opcode
== 0xf38f0
7284 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7288 /* Any other register is bad. */
7289 as_bad (_("`%s%s' not allowed with `%s%c'"),
7290 register_prefix
, i
.op
[op
].regs
->reg_name
,
7291 i
.tm
.name
, i
.suffix
);
7298 check_long_reg (void)
7302 for (op
= i
.operands
; --op
>= 0;)
7303 /* Skip non-register operands. */
7304 if (i
.types
[op
].bitfield
.class != Reg
)
7306 /* Reject eight bit registers, except where the template requires
7307 them. (eg. movzb) */
7308 else if (i
.types
[op
].bitfield
.byte
7309 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7310 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7311 && (i
.tm
.operand_types
[op
].bitfield
.word
7312 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7314 as_bad (_("`%s%s' not allowed with `%s%c'"),
7316 i
.op
[op
].regs
->reg_name
,
7321 /* Error if the e prefix on a general reg is missing. */
7322 else if (i
.types
[op
].bitfield
.word
7323 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7324 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7325 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7327 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7328 register_prefix
, i
.op
[op
].regs
->reg_name
,
7332 /* Warn if the r prefix on a general reg is present. */
7333 else if (i
.types
[op
].bitfield
.qword
7334 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7335 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7336 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7339 && i
.tm
.opcode_modifier
.toqword
7340 && i
.types
[0].bitfield
.class != RegSIMD
)
7342 /* Convert to QWORD. We want REX byte. */
7343 i
.suffix
= QWORD_MNEM_SUFFIX
;
7347 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7348 register_prefix
, i
.op
[op
].regs
->reg_name
,
7357 check_qword_reg (void)
7361 for (op
= i
.operands
; --op
>= 0; )
7362 /* Skip non-register operands. */
7363 if (i
.types
[op
].bitfield
.class != Reg
)
7365 /* Reject eight bit registers, except where the template requires
7366 them. (eg. movzb) */
7367 else if (i
.types
[op
].bitfield
.byte
7368 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7369 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7370 && (i
.tm
.operand_types
[op
].bitfield
.word
7371 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7373 as_bad (_("`%s%s' not allowed with `%s%c'"),
7375 i
.op
[op
].regs
->reg_name
,
7380 /* Warn if the r prefix on a general reg is missing. */
7381 else if ((i
.types
[op
].bitfield
.word
7382 || i
.types
[op
].bitfield
.dword
)
7383 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7384 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7385 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7387 /* Prohibit these changes in the 64bit mode, since the
7388 lowering is more complicated. */
7390 && i
.tm
.opcode_modifier
.todword
7391 && i
.types
[0].bitfield
.class != RegSIMD
)
7393 /* Convert to DWORD. We don't want REX byte. */
7394 i
.suffix
= LONG_MNEM_SUFFIX
;
7398 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7399 register_prefix
, i
.op
[op
].regs
->reg_name
,
7408 check_word_reg (void)
7411 for (op
= i
.operands
; --op
>= 0;)
7412 /* Skip non-register operands. */
7413 if (i
.types
[op
].bitfield
.class != Reg
)
7415 /* Reject eight bit registers, except where the template requires
7416 them. (eg. movzb) */
7417 else if (i
.types
[op
].bitfield
.byte
7418 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7419 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7420 && (i
.tm
.operand_types
[op
].bitfield
.word
7421 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7423 as_bad (_("`%s%s' not allowed with `%s%c'"),
7425 i
.op
[op
].regs
->reg_name
,
7430 /* Error if the e or r prefix on a general reg is present. */
7431 else if ((i
.types
[op
].bitfield
.dword
7432 || i
.types
[op
].bitfield
.qword
)
7433 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7434 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7435 && i
.tm
.operand_types
[op
].bitfield
.word
)
7437 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7438 register_prefix
, i
.op
[op
].regs
->reg_name
,
7446 update_imm (unsigned int j
)
7448 i386_operand_type overlap
= i
.types
[j
];
7449 if ((overlap
.bitfield
.imm8
7450 || overlap
.bitfield
.imm8s
7451 || overlap
.bitfield
.imm16
7452 || overlap
.bitfield
.imm32
7453 || overlap
.bitfield
.imm32s
7454 || overlap
.bitfield
.imm64
)
7455 && !operand_type_equal (&overlap
, &imm8
)
7456 && !operand_type_equal (&overlap
, &imm8s
)
7457 && !operand_type_equal (&overlap
, &imm16
)
7458 && !operand_type_equal (&overlap
, &imm32
)
7459 && !operand_type_equal (&overlap
, &imm32s
)
7460 && !operand_type_equal (&overlap
, &imm64
))
7464 i386_operand_type temp
;
7466 operand_type_set (&temp
, 0);
7467 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7469 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7470 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7472 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7473 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7474 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7476 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7477 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7480 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7483 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7484 || operand_type_equal (&overlap
, &imm16_32
)
7485 || operand_type_equal (&overlap
, &imm16_32s
))
7487 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7492 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7493 overlap
= operand_type_and (overlap
, imm32s
);
7494 else if (i
.prefix
[DATA_PREFIX
])
7495 overlap
= operand_type_and (overlap
,
7496 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7497 if (!operand_type_equal (&overlap
, &imm8
)
7498 && !operand_type_equal (&overlap
, &imm8s
)
7499 && !operand_type_equal (&overlap
, &imm16
)
7500 && !operand_type_equal (&overlap
, &imm32
)
7501 && !operand_type_equal (&overlap
, &imm32s
)
7502 && !operand_type_equal (&overlap
, &imm64
))
7504 as_bad (_("no instruction mnemonic suffix given; "
7505 "can't determine immediate size"));
7509 i
.types
[j
] = overlap
;
7519 /* Update the first 2 immediate operands. */
7520 n
= i
.operands
> 2 ? 2 : i
.operands
;
7523 for (j
= 0; j
< n
; j
++)
7524 if (update_imm (j
) == 0)
7527 /* The 3rd operand can't be immediate operand. */
7528 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7535 process_operands (void)
7537 /* Default segment register this instruction will use for memory
7538 accesses. 0 means unknown. This is only for optimizing out
7539 unnecessary segment overrides. */
7540 const seg_entry
*default_seg
= 0;
7542 if (i
.tm
.opcode_modifier
.sse2avx
)
7544 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7546 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7547 i
.prefix
[REX_PREFIX
] = 0;
7550 /* ImmExt should be processed after SSE2AVX. */
7551 else if (i
.tm
.opcode_modifier
.immext
)
7554 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7556 unsigned int dupl
= i
.operands
;
7557 unsigned int dest
= dupl
- 1;
7560 /* The destination must be an xmm register. */
7561 gas_assert (i
.reg_operands
7562 && MAX_OPERANDS
> dupl
7563 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7565 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7566 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7568 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7570 /* Keep xmm0 for instructions with VEX prefix and 3
7572 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7573 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7578 /* We remove the first xmm0 and keep the number of
7579 operands unchanged, which in fact duplicates the
7581 for (j
= 1; j
< i
.operands
; j
++)
7583 i
.op
[j
- 1] = i
.op
[j
];
7584 i
.types
[j
- 1] = i
.types
[j
];
7585 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7586 i
.flags
[j
- 1] = i
.flags
[j
];
7590 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7592 gas_assert ((MAX_OPERANDS
- 1) > dupl
7593 && (i
.tm
.opcode_modifier
.vexsources
7596 /* Add the implicit xmm0 for instructions with VEX prefix
7598 for (j
= i
.operands
; j
> 0; j
--)
7600 i
.op
[j
] = i
.op
[j
- 1];
7601 i
.types
[j
] = i
.types
[j
- 1];
7602 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7603 i
.flags
[j
] = i
.flags
[j
- 1];
7606 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7607 i
.types
[0] = regxmm
;
7608 i
.tm
.operand_types
[0] = regxmm
;
7611 i
.reg_operands
+= 2;
7616 i
.op
[dupl
] = i
.op
[dest
];
7617 i
.types
[dupl
] = i
.types
[dest
];
7618 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7619 i
.flags
[dupl
] = i
.flags
[dest
];
7628 i
.op
[dupl
] = i
.op
[dest
];
7629 i
.types
[dupl
] = i
.types
[dest
];
7630 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7631 i
.flags
[dupl
] = i
.flags
[dest
];
7634 if (i
.tm
.opcode_modifier
.immext
)
7637 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7638 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7642 for (j
= 1; j
< i
.operands
; j
++)
7644 i
.op
[j
- 1] = i
.op
[j
];
7645 i
.types
[j
- 1] = i
.types
[j
];
7647 /* We need to adjust fields in i.tm since they are used by
7648 build_modrm_byte. */
7649 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7651 i
.flags
[j
- 1] = i
.flags
[j
];
7658 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7660 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7662 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7663 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7664 regnum
= register_number (i
.op
[1].regs
);
7665 first_reg_in_group
= regnum
& ~3;
7666 last_reg_in_group
= first_reg_in_group
+ 3;
7667 if (regnum
!= first_reg_in_group
)
7668 as_warn (_("source register `%s%s' implicitly denotes"
7669 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7670 register_prefix
, i
.op
[1].regs
->reg_name
,
7671 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7672 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7675 else if (i
.tm
.opcode_modifier
.regkludge
)
7677 /* The imul $imm, %reg instruction is converted into
7678 imul $imm, %reg, %reg, and the clr %reg instruction
7679 is converted into xor %reg, %reg. */
7681 unsigned int first_reg_op
;
7683 if (operand_type_check (i
.types
[0], reg
))
7687 /* Pretend we saw the extra register operand. */
7688 gas_assert (i
.reg_operands
== 1
7689 && i
.op
[first_reg_op
+ 1].regs
== 0);
7690 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7691 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7696 if (i
.tm
.opcode_modifier
.modrm
)
7698 /* The opcode is completed (modulo i.tm.extension_opcode which
7699 must be put into the modrm byte). Now, we make the modrm and
7700 index base bytes based on all the info we've collected. */
7702 default_seg
= build_modrm_byte ();
7704 else if (i
.types
[0].bitfield
.class == SReg
)
7706 if (flag_code
!= CODE_64BIT
7707 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7708 && i
.op
[0].regs
->reg_num
== 1
7709 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7710 && i
.op
[0].regs
->reg_num
< 4)
7712 as_bad (_("you can't `%s %s%s'"),
7713 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7716 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7718 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7719 i
.tm
.opcode_length
= 2;
7721 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7723 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7727 else if (i
.tm
.opcode_modifier
.isstring
)
7729 /* For the string instructions that allow a segment override
7730 on one of their operands, the default segment is ds. */
7733 else if (i
.short_form
)
7735 /* The register or float register operand is in operand
7737 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7739 /* Register goes in low 3 bits of opcode. */
7740 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7741 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7743 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7745 /* Warn about some common errors, but press on regardless.
7746 The first case can be generated by gcc (<= 2.8.1). */
7747 if (i
.operands
== 2)
7749 /* Reversed arguments on faddp, fsubp, etc. */
7750 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7751 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7752 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7756 /* Extraneous `l' suffix on fp insn. */
7757 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7758 register_prefix
, i
.op
[0].regs
->reg_name
);
7763 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7764 && i
.tm
.base_opcode
== 0x8d /* lea */
7765 && !is_any_vex_encoding(&i
.tm
))
7767 if (!quiet_warnings
)
7768 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7772 i
.prefix
[SEG_PREFIX
] = 0;
7776 /* If a segment was explicitly specified, and the specified segment
7777 is neither the default nor the one already recorded from a prefix,
7778 use an opcode prefix to select it. If we never figured out what
7779 the default segment is, then default_seg will be zero at this
7780 point, and the specified segment prefix will always be used. */
7782 && i
.seg
[0] != default_seg
7783 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7785 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7791 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7792 bfd_boolean do_sse2avx
)
7794 if (r
->reg_flags
& RegRex
)
7796 if (i
.rex
& rex_bit
)
7797 as_bad (_("same type of prefix used twice"));
7800 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7802 gas_assert (i
.vex
.register_specifier
== r
);
7803 i
.vex
.register_specifier
+= 8;
7806 if (r
->reg_flags
& RegVRex
)
7810 static const seg_entry
*
7811 build_modrm_byte (void)
7813 const seg_entry
*default_seg
= 0;
7814 unsigned int source
, dest
;
7817 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7820 unsigned int nds
, reg_slot
;
7823 dest
= i
.operands
- 1;
7826 /* There are 2 kinds of instructions:
7827 1. 5 operands: 4 register operands or 3 register operands
7828 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7829 VexW0 or VexW1. The destination must be either XMM, YMM or
7831 2. 4 operands: 4 register operands or 3 register operands
7832 plus 1 memory operand, with VexXDS. */
7833 gas_assert ((i
.reg_operands
== 4
7834 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7835 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7836 && i
.tm
.opcode_modifier
.vexw
7837 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7839 /* If VexW1 is set, the first non-immediate operand is the source and
7840 the second non-immediate one is encoded in the immediate operand. */
7841 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7843 source
= i
.imm_operands
;
7844 reg_slot
= i
.imm_operands
+ 1;
7848 source
= i
.imm_operands
+ 1;
7849 reg_slot
= i
.imm_operands
;
7852 if (i
.imm_operands
== 0)
7854 /* When there is no immediate operand, generate an 8bit
7855 immediate operand to encode the first operand. */
7856 exp
= &im_expressions
[i
.imm_operands
++];
7857 i
.op
[i
.operands
].imms
= exp
;
7858 i
.types
[i
.operands
] = imm8
;
7861 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7862 exp
->X_op
= O_constant
;
7863 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7864 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7868 gas_assert (i
.imm_operands
== 1);
7869 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7870 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7872 /* Turn on Imm8 again so that output_imm will generate it. */
7873 i
.types
[0].bitfield
.imm8
= 1;
7875 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7876 i
.op
[0].imms
->X_add_number
7877 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7878 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7881 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7882 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7887 /* i.reg_operands MUST be the number of real register operands;
7888 implicit registers do not count. If there are 3 register
7889 operands, it must be a instruction with VexNDS. For a
7890 instruction with VexNDD, the destination register is encoded
7891 in VEX prefix. If there are 4 register operands, it must be
7892 a instruction with VEX prefix and 3 sources. */
7893 if (i
.mem_operands
== 0
7894 && ((i
.reg_operands
== 2
7895 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7896 || (i
.reg_operands
== 3
7897 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7898 || (i
.reg_operands
== 4 && vex_3_sources
)))
7906 /* When there are 3 operands, one of them may be immediate,
7907 which may be the first or the last operand. Otherwise,
7908 the first operand must be shift count register (cl) or it
7909 is an instruction with VexNDS. */
7910 gas_assert (i
.imm_operands
== 1
7911 || (i
.imm_operands
== 0
7912 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7913 || (i
.types
[0].bitfield
.instance
== RegC
7914 && i
.types
[0].bitfield
.byte
))));
7915 if (operand_type_check (i
.types
[0], imm
)
7916 || (i
.types
[0].bitfield
.instance
== RegC
7917 && i
.types
[0].bitfield
.byte
))
7923 /* When there are 4 operands, the first two must be 8bit
7924 immediate operands. The source operand will be the 3rd
7927 For instructions with VexNDS, if the first operand
7928 an imm8, the source operand is the 2nd one. If the last
7929 operand is imm8, the source operand is the first one. */
7930 gas_assert ((i
.imm_operands
== 2
7931 && i
.types
[0].bitfield
.imm8
7932 && i
.types
[1].bitfield
.imm8
)
7933 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7934 && i
.imm_operands
== 1
7935 && (i
.types
[0].bitfield
.imm8
7936 || i
.types
[i
.operands
- 1].bitfield
.imm8
7938 if (i
.imm_operands
== 2)
7942 if (i
.types
[0].bitfield
.imm8
)
7949 if (is_evex_encoding (&i
.tm
))
7951 /* For EVEX instructions, when there are 5 operands, the
7952 first one must be immediate operand. If the second one
7953 is immediate operand, the source operand is the 3th
7954 one. If the last one is immediate operand, the source
7955 operand is the 2nd one. */
7956 gas_assert (i
.imm_operands
== 2
7957 && i
.tm
.opcode_modifier
.sae
7958 && operand_type_check (i
.types
[0], imm
));
7959 if (operand_type_check (i
.types
[1], imm
))
7961 else if (operand_type_check (i
.types
[4], imm
))
7975 /* RC/SAE operand could be between DEST and SRC. That happens
7976 when one operand is GPR and the other one is XMM/YMM/ZMM
7978 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7981 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7983 /* For instructions with VexNDS, the register-only source
7984 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7985 register. It is encoded in VEX prefix. */
7987 i386_operand_type op
;
7990 /* Swap two source operands if needed. */
7991 if (i
.tm
.opcode_modifier
.swapsources
)
7999 op
= i
.tm
.operand_types
[vvvv
];
8000 if ((dest
+ 1) >= i
.operands
8001 || ((op
.bitfield
.class != Reg
8002 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8003 && op
.bitfield
.class != RegSIMD
8004 && !operand_type_equal (&op
, ®mask
)))
8006 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8012 /* One of the register operands will be encoded in the i.rm.reg
8013 field, the other in the combined i.rm.mode and i.rm.regmem
8014 fields. If no form of this instruction supports a memory
8015 destination operand, then we assume the source operand may
8016 sometimes be a memory operand and so we need to store the
8017 destination in the i.rm.reg field. */
8018 if (!i
.tm
.opcode_modifier
.regmem
8019 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8021 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8022 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8023 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8024 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
8028 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8029 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8030 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8031 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
8033 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8035 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8038 add_prefix (LOCK_PREFIX_OPCODE
);
8042 { /* If it's not 2 reg operands... */
8047 unsigned int fake_zero_displacement
= 0;
8050 for (op
= 0; op
< i
.operands
; op
++)
8051 if (i
.flags
[op
] & Operand_Mem
)
8053 gas_assert (op
< i
.operands
);
8055 if (i
.tm
.opcode_modifier
.sib
)
8057 /* The index register of VSIB shouldn't be RegIZ. */
8058 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8059 && i
.index_reg
->reg_num
== RegIZ
)
8062 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8065 i
.sib
.base
= NO_BASE_REGISTER
;
8066 i
.sib
.scale
= i
.log2_scale_factor
;
8067 i
.types
[op
].bitfield
.disp8
= 0;
8068 i
.types
[op
].bitfield
.disp16
= 0;
8069 i
.types
[op
].bitfield
.disp64
= 0;
8070 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8072 /* Must be 32 bit */
8073 i
.types
[op
].bitfield
.disp32
= 1;
8074 i
.types
[op
].bitfield
.disp32s
= 0;
8078 i
.types
[op
].bitfield
.disp32
= 0;
8079 i
.types
[op
].bitfield
.disp32s
= 1;
8083 /* Since the mandatory SIB always has index register, so
8084 the code logic remains unchanged. The non-mandatory SIB
8085 without index register is allowed and will be handled
8089 if (i
.index_reg
->reg_num
== RegIZ
)
8090 i
.sib
.index
= NO_INDEX_REGISTER
;
8092 i
.sib
.index
= i
.index_reg
->reg_num
;
8093 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8099 if (i
.base_reg
== 0)
8102 if (!i
.disp_operands
)
8103 fake_zero_displacement
= 1;
8104 if (i
.index_reg
== 0)
8106 i386_operand_type newdisp
;
8108 /* Both check for VSIB and mandatory non-vector SIB. */
8109 gas_assert (!i
.tm
.opcode_modifier
.sib
8110 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8111 /* Operand is just <disp> */
8112 if (flag_code
== CODE_64BIT
)
8114 /* 64bit mode overwrites the 32bit absolute
8115 addressing by RIP relative addressing and
8116 absolute addressing is encoded by one of the
8117 redundant SIB forms. */
8118 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8119 i
.sib
.base
= NO_BASE_REGISTER
;
8120 i
.sib
.index
= NO_INDEX_REGISTER
;
8121 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8123 else if ((flag_code
== CODE_16BIT
)
8124 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8126 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8131 i
.rm
.regmem
= NO_BASE_REGISTER
;
8134 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8135 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8137 else if (!i
.tm
.opcode_modifier
.sib
)
8139 /* !i.base_reg && i.index_reg */
8140 if (i
.index_reg
->reg_num
== RegIZ
)
8141 i
.sib
.index
= NO_INDEX_REGISTER
;
8143 i
.sib
.index
= i
.index_reg
->reg_num
;
8144 i
.sib
.base
= NO_BASE_REGISTER
;
8145 i
.sib
.scale
= i
.log2_scale_factor
;
8146 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8147 i
.types
[op
].bitfield
.disp8
= 0;
8148 i
.types
[op
].bitfield
.disp16
= 0;
8149 i
.types
[op
].bitfield
.disp64
= 0;
8150 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8152 /* Must be 32 bit */
8153 i
.types
[op
].bitfield
.disp32
= 1;
8154 i
.types
[op
].bitfield
.disp32s
= 0;
8158 i
.types
[op
].bitfield
.disp32
= 0;
8159 i
.types
[op
].bitfield
.disp32s
= 1;
8161 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8165 /* RIP addressing for 64bit mode. */
8166 else if (i
.base_reg
->reg_num
== RegIP
)
8168 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8169 i
.rm
.regmem
= NO_BASE_REGISTER
;
8170 i
.types
[op
].bitfield
.disp8
= 0;
8171 i
.types
[op
].bitfield
.disp16
= 0;
8172 i
.types
[op
].bitfield
.disp32
= 0;
8173 i
.types
[op
].bitfield
.disp32s
= 1;
8174 i
.types
[op
].bitfield
.disp64
= 0;
8175 i
.flags
[op
] |= Operand_PCrel
;
8176 if (! i
.disp_operands
)
8177 fake_zero_displacement
= 1;
8179 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8181 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8182 switch (i
.base_reg
->reg_num
)
8185 if (i
.index_reg
== 0)
8187 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8188 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8192 if (i
.index_reg
== 0)
8195 if (operand_type_check (i
.types
[op
], disp
) == 0)
8197 /* fake (%bp) into 0(%bp) */
8198 if (i
.disp_encoding
== disp_encoding_16bit
)
8199 i
.types
[op
].bitfield
.disp16
= 1;
8201 i
.types
[op
].bitfield
.disp8
= 1;
8202 fake_zero_displacement
= 1;
8205 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8206 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8208 default: /* (%si) -> 4 or (%di) -> 5 */
8209 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8211 if (!fake_zero_displacement
8215 fake_zero_displacement
= 1;
8216 if (i
.disp_encoding
== disp_encoding_8bit
)
8217 i
.types
[op
].bitfield
.disp8
= 1;
8219 i
.types
[op
].bitfield
.disp16
= 1;
8221 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8223 else /* i.base_reg and 32/64 bit mode */
8225 if (flag_code
== CODE_64BIT
8226 && operand_type_check (i
.types
[op
], disp
))
8228 i
.types
[op
].bitfield
.disp16
= 0;
8229 i
.types
[op
].bitfield
.disp64
= 0;
8230 if (i
.prefix
[ADDR_PREFIX
] == 0)
8232 i
.types
[op
].bitfield
.disp32
= 0;
8233 i
.types
[op
].bitfield
.disp32s
= 1;
8237 i
.types
[op
].bitfield
.disp32
= 1;
8238 i
.types
[op
].bitfield
.disp32s
= 0;
8242 if (!i
.tm
.opcode_modifier
.sib
)
8243 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8244 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8246 i
.sib
.base
= i
.base_reg
->reg_num
;
8247 /* x86-64 ignores REX prefix bit here to avoid decoder
8249 if (!(i
.base_reg
->reg_flags
& RegRex
)
8250 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8251 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8253 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8255 fake_zero_displacement
= 1;
8256 if (i
.disp_encoding
== disp_encoding_32bit
)
8257 i
.types
[op
].bitfield
.disp32
= 1;
8259 i
.types
[op
].bitfield
.disp8
= 1;
8261 i
.sib
.scale
= i
.log2_scale_factor
;
8262 if (i
.index_reg
== 0)
8264 /* Only check for VSIB. */
8265 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8266 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8267 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8269 /* <disp>(%esp) becomes two byte modrm with no index
8270 register. We've already stored the code for esp
8271 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8272 Any base register besides %esp will not use the
8273 extra modrm byte. */
8274 i
.sib
.index
= NO_INDEX_REGISTER
;
8276 else if (!i
.tm
.opcode_modifier
.sib
)
8278 if (i
.index_reg
->reg_num
== RegIZ
)
8279 i
.sib
.index
= NO_INDEX_REGISTER
;
8281 i
.sib
.index
= i
.index_reg
->reg_num
;
8282 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8283 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8288 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8289 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8293 if (!fake_zero_displacement
8297 fake_zero_displacement
= 1;
8298 if (i
.disp_encoding
== disp_encoding_8bit
)
8299 i
.types
[op
].bitfield
.disp8
= 1;
8301 i
.types
[op
].bitfield
.disp32
= 1;
8303 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8307 if (fake_zero_displacement
)
8309 /* Fakes a zero displacement assuming that i.types[op]
8310 holds the correct displacement size. */
8313 gas_assert (i
.op
[op
].disps
== 0);
8314 exp
= &disp_expressions
[i
.disp_operands
++];
8315 i
.op
[op
].disps
= exp
;
8316 exp
->X_op
= O_constant
;
8317 exp
->X_add_number
= 0;
8318 exp
->X_add_symbol
= (symbolS
*) 0;
8319 exp
->X_op_symbol
= (symbolS
*) 0;
8327 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8329 if (operand_type_check (i
.types
[0], imm
))
8330 i
.vex
.register_specifier
= NULL
;
8333 /* VEX.vvvv encodes one of the sources when the first
8334 operand is not an immediate. */
8335 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8336 i
.vex
.register_specifier
= i
.op
[0].regs
;
8338 i
.vex
.register_specifier
= i
.op
[1].regs
;
8341 /* Destination is a XMM register encoded in the ModRM.reg
8343 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8344 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8347 /* ModRM.rm and VEX.B encodes the other source. */
8348 if (!i
.mem_operands
)
8352 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8353 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8355 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8357 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8361 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8363 i
.vex
.register_specifier
= i
.op
[2].regs
;
8364 if (!i
.mem_operands
)
8367 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8368 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8372 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8373 (if any) based on i.tm.extension_opcode. Again, we must be
8374 careful to make sure that segment/control/debug/test/MMX
8375 registers are coded into the i.rm.reg field. */
8376 else if (i
.reg_operands
)
8379 unsigned int vex_reg
= ~0;
8381 for (op
= 0; op
< i
.operands
; op
++)
8382 if (i
.types
[op
].bitfield
.class == Reg
8383 || i
.types
[op
].bitfield
.class == RegBND
8384 || i
.types
[op
].bitfield
.class == RegMask
8385 || i
.types
[op
].bitfield
.class == SReg
8386 || i
.types
[op
].bitfield
.class == RegCR
8387 || i
.types
[op
].bitfield
.class == RegDR
8388 || i
.types
[op
].bitfield
.class == RegTR
8389 || i
.types
[op
].bitfield
.class == RegSIMD
8390 || i
.types
[op
].bitfield
.class == RegMMX
)
8395 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8397 /* For instructions with VexNDS, the register-only
8398 source operand is encoded in VEX prefix. */
8399 gas_assert (mem
!= (unsigned int) ~0);
8404 gas_assert (op
< i
.operands
);
8408 /* Check register-only source operand when two source
8409 operands are swapped. */
8410 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8411 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8415 gas_assert (mem
== (vex_reg
+ 1)
8416 && op
< i
.operands
);
8421 gas_assert (vex_reg
< i
.operands
);
8425 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8427 /* For instructions with VexNDD, the register destination
8428 is encoded in VEX prefix. */
8429 if (i
.mem_operands
== 0)
8431 /* There is no memory operand. */
8432 gas_assert ((op
+ 2) == i
.operands
);
8437 /* There are only 2 non-immediate operands. */
8438 gas_assert (op
< i
.imm_operands
+ 2
8439 && i
.operands
== i
.imm_operands
+ 2);
8440 vex_reg
= i
.imm_operands
+ 1;
8444 gas_assert (op
< i
.operands
);
8446 if (vex_reg
!= (unsigned int) ~0)
8448 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8450 if ((type
->bitfield
.class != Reg
8451 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8452 && type
->bitfield
.class != RegSIMD
8453 && !operand_type_equal (type
, ®mask
))
8456 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8459 /* Don't set OP operand twice. */
8462 /* If there is an extension opcode to put here, the
8463 register number must be put into the regmem field. */
8464 if (i
.tm
.extension_opcode
!= None
)
8466 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8467 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8468 i
.tm
.opcode_modifier
.sse2avx
);
8472 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8473 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8474 i
.tm
.opcode_modifier
.sse2avx
);
8478 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8479 must set it to 3 to indicate this is a register operand
8480 in the regmem field. */
8481 if (!i
.mem_operands
)
8485 /* Fill in i.rm.reg field with extension opcode (if any). */
8486 if (i
.tm
.extension_opcode
!= None
)
8487 i
.rm
.reg
= i
.tm
.extension_opcode
;
8493 frag_opcode_byte (unsigned char byte
)
8495 if (now_seg
!= absolute_section
)
8496 FRAG_APPEND_1_CHAR (byte
);
8498 ++abs_section_offset
;
8502 flip_code16 (unsigned int code16
)
8504 gas_assert (i
.tm
.operands
== 1);
8506 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8507 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8508 || i
.tm
.operand_types
[0].bitfield
.disp32s
8509 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8514 output_branch (void)
8520 relax_substateT subtype
;
8524 if (now_seg
== absolute_section
)
8526 as_bad (_("relaxable branches not supported in absolute section"));
8530 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8531 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8534 if (i
.prefix
[DATA_PREFIX
] != 0)
8538 code16
^= flip_code16(code16
);
8540 /* Pentium4 branch hints. */
8541 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8542 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8547 if (i
.prefix
[REX_PREFIX
] != 0)
8553 /* BND prefixed jump. */
8554 if (i
.prefix
[BND_PREFIX
] != 0)
8560 if (i
.prefixes
!= 0)
8561 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8563 /* It's always a symbol; End frag & setup for relax.
8564 Make sure there is enough room in this frag for the largest
8565 instruction we may generate in md_convert_frag. This is 2
8566 bytes for the opcode and room for the prefix and largest
8568 frag_grow (prefix
+ 2 + 4);
8569 /* Prefix and 1 opcode byte go in fr_fix. */
8570 p
= frag_more (prefix
+ 1);
8571 if (i
.prefix
[DATA_PREFIX
] != 0)
8572 *p
++ = DATA_PREFIX_OPCODE
;
8573 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8574 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8575 *p
++ = i
.prefix
[SEG_PREFIX
];
8576 if (i
.prefix
[BND_PREFIX
] != 0)
8577 *p
++ = BND_PREFIX_OPCODE
;
8578 if (i
.prefix
[REX_PREFIX
] != 0)
8579 *p
++ = i
.prefix
[REX_PREFIX
];
8580 *p
= i
.tm
.base_opcode
;
8582 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8583 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8584 else if (cpu_arch_flags
.bitfield
.cpui386
)
8585 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8587 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8590 sym
= i
.op
[0].disps
->X_add_symbol
;
8591 off
= i
.op
[0].disps
->X_add_number
;
8593 if (i
.op
[0].disps
->X_op
!= O_constant
8594 && i
.op
[0].disps
->X_op
!= O_symbol
)
8596 /* Handle complex expressions. */
8597 sym
= make_expr_symbol (i
.op
[0].disps
);
8601 /* 1 possible extra opcode + 4 byte displacement go in var part.
8602 Pass reloc in fr_var. */
8603 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8607 /* Return TRUE iff PLT32 relocation should be used for branching to
8611 need_plt32_p (symbolS
*s
)
8613 /* PLT32 relocation is ELF only. */
8618 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8619 krtld support it. */
8623 /* Since there is no need to prepare for PLT branch on x86-64, we
8624 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8625 be used as a marker for 32-bit PC-relative branches. */
8632 /* Weak or undefined symbol need PLT32 relocation. */
8633 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8636 /* Non-global symbol doesn't need PLT32 relocation. */
8637 if (! S_IS_EXTERNAL (s
))
8640 /* Other global symbols need PLT32 relocation. NB: Symbol with
8641 non-default visibilities are treated as normal global symbol
8642 so that PLT32 relocation can be used as a marker for 32-bit
8643 PC-relative branches. It is useful for linker relaxation. */
8654 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8656 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8658 /* This is a loop or jecxz type instruction. */
8660 if (i
.prefix
[ADDR_PREFIX
] != 0)
8662 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8665 /* Pentium4 branch hints. */
8666 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8667 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8669 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8678 if (flag_code
== CODE_16BIT
)
8681 if (i
.prefix
[DATA_PREFIX
] != 0)
8683 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8685 code16
^= flip_code16(code16
);
8693 /* BND prefixed jump. */
8694 if (i
.prefix
[BND_PREFIX
] != 0)
8696 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8700 if (i
.prefix
[REX_PREFIX
] != 0)
8702 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8706 if (i
.prefixes
!= 0)
8707 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8709 if (now_seg
== absolute_section
)
8711 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8715 p
= frag_more (i
.tm
.opcode_length
+ size
);
8716 switch (i
.tm
.opcode_length
)
8719 *p
++ = i
.tm
.base_opcode
>> 8;
8722 *p
++ = i
.tm
.base_opcode
;
8728 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8730 && jump_reloc
== NO_RELOC
8731 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8732 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8735 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8737 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8738 i
.op
[0].disps
, 1, jump_reloc
);
8740 /* All jumps handled here are signed, but don't use a signed limit
8741 check for 32 and 16 bit jumps as we want to allow wrap around at
8742 4G and 64k respectively. */
8744 fixP
->fx_signed
= 1;
8748 output_interseg_jump (void)
8756 if (flag_code
== CODE_16BIT
)
8760 if (i
.prefix
[DATA_PREFIX
] != 0)
8767 gas_assert (!i
.prefix
[REX_PREFIX
]);
8773 if (i
.prefixes
!= 0)
8774 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8776 if (now_seg
== absolute_section
)
8778 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8782 /* 1 opcode; 2 segment; offset */
8783 p
= frag_more (prefix
+ 1 + 2 + size
);
8785 if (i
.prefix
[DATA_PREFIX
] != 0)
8786 *p
++ = DATA_PREFIX_OPCODE
;
8788 if (i
.prefix
[REX_PREFIX
] != 0)
8789 *p
++ = i
.prefix
[REX_PREFIX
];
8791 *p
++ = i
.tm
.base_opcode
;
8792 if (i
.op
[1].imms
->X_op
== O_constant
)
8794 offsetT n
= i
.op
[1].imms
->X_add_number
;
8797 && !fits_in_unsigned_word (n
)
8798 && !fits_in_signed_word (n
))
8800 as_bad (_("16-bit jump out of range"));
8803 md_number_to_chars (p
, n
, size
);
8806 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8807 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8810 if (i
.op
[0].imms
->X_op
== O_constant
)
8811 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8813 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8814 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8822 asection
*seg
= now_seg
;
8823 subsegT subseg
= now_subseg
;
8825 unsigned int alignment
, align_size_1
;
8826 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8827 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8828 unsigned int padding
;
8830 if (!IS_ELF
|| !x86_used_note
)
8833 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8835 /* The .note.gnu.property section layout:
8837 Field Length Contents
8840 n_descsz 4 The note descriptor size
8841 n_type 4 NT_GNU_PROPERTY_TYPE_0
8843 n_desc n_descsz The program property array
8847 /* Create the .note.gnu.property section. */
8848 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8849 bfd_set_section_flags (sec
,
8856 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8867 bfd_set_section_alignment (sec
, alignment
);
8868 elf_section_type (sec
) = SHT_NOTE
;
8870 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8872 isa_1_descsz_raw
= 4 + 4 + 4;
8873 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8874 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8876 feature_2_descsz_raw
= isa_1_descsz
;
8877 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8879 feature_2_descsz_raw
+= 4 + 4 + 4;
8880 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8881 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8884 descsz
= feature_2_descsz
;
8885 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8886 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8888 /* Write n_namsz. */
8889 md_number_to_chars (p
, (valueT
) 4, 4);
8891 /* Write n_descsz. */
8892 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8895 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8898 memcpy (p
+ 4 * 3, "GNU", 4);
8900 /* Write 4-byte type. */
8901 md_number_to_chars (p
+ 4 * 4,
8902 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8904 /* Write 4-byte data size. */
8905 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8907 /* Write 4-byte data. */
8908 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8910 /* Zero out paddings. */
8911 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8913 memset (p
+ 4 * 7, 0, padding
);
8915 /* Write 4-byte type. */
8916 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8917 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8919 /* Write 4-byte data size. */
8920 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8922 /* Write 4-byte data. */
8923 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8924 (valueT
) x86_feature_2_used
, 4);
8926 /* Zero out paddings. */
8927 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8929 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8931 /* We probably can't restore the current segment, for there likely
8934 subseg_set (seg
, subseg
);
8939 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8940 const char *frag_now_ptr
)
8942 unsigned int len
= 0;
8944 if (start_frag
!= frag_now
)
8946 const fragS
*fr
= start_frag
;
8951 } while (fr
&& fr
!= frag_now
);
8954 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8957 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8958 be macro-fused with conditional jumps.
8959 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8960 or is one of the following format:
8973 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8975 /* No RIP address. */
8976 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8979 /* No VEX/EVEX encoding. */
8980 if (is_any_vex_encoding (&i
.tm
))
8983 /* add, sub without add/sub m, imm. */
8984 if (i
.tm
.base_opcode
<= 5
8985 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8986 || ((i
.tm
.base_opcode
| 3) == 0x83
8987 && (i
.tm
.extension_opcode
== 0x5
8988 || i
.tm
.extension_opcode
== 0x0)))
8990 *mf_cmp_p
= mf_cmp_alu_cmp
;
8991 return !(i
.mem_operands
&& i
.imm_operands
);
8994 /* and without and m, imm. */
8995 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8996 || ((i
.tm
.base_opcode
| 3) == 0x83
8997 && i
.tm
.extension_opcode
== 0x4))
8999 *mf_cmp_p
= mf_cmp_test_and
;
9000 return !(i
.mem_operands
&& i
.imm_operands
);
9003 /* test without test m imm. */
9004 if ((i
.tm
.base_opcode
| 1) == 0x85
9005 || (i
.tm
.base_opcode
| 1) == 0xa9
9006 || ((i
.tm
.base_opcode
| 1) == 0xf7
9007 && i
.tm
.extension_opcode
== 0))
9009 *mf_cmp_p
= mf_cmp_test_and
;
9010 return !(i
.mem_operands
&& i
.imm_operands
);
9013 /* cmp without cmp m, imm. */
9014 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9015 || ((i
.tm
.base_opcode
| 3) == 0x83
9016 && (i
.tm
.extension_opcode
== 0x7)))
9018 *mf_cmp_p
= mf_cmp_alu_cmp
;
9019 return !(i
.mem_operands
&& i
.imm_operands
);
9022 /* inc, dec without inc/dec m. */
9023 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9024 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9025 || ((i
.tm
.base_opcode
| 1) == 0xff
9026 && i
.tm
.extension_opcode
<= 0x1))
9028 *mf_cmp_p
= mf_cmp_incdec
;
9029 return !i
.mem_operands
;
9035 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9038 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9040 /* NB: Don't work with COND_JUMP86 without i386. */
9041 if (!align_branch_power
9042 || now_seg
== absolute_section
9043 || !cpu_arch_flags
.bitfield
.cpui386
9044 || !(align_branch
& align_branch_fused_bit
))
9047 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9049 if (last_insn
.kind
== last_insn_other
9050 || last_insn
.seg
!= now_seg
)
9053 as_warn_where (last_insn
.file
, last_insn
.line
,
9054 _("`%s` skips -malign-branch-boundary on `%s`"),
9055 last_insn
.name
, i
.tm
.name
);
9061 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9064 add_branch_prefix_frag_p (void)
9066 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9067 to PadLock instructions since they include prefixes in opcode. */
9068 if (!align_branch_power
9069 || !align_branch_prefix_size
9070 || now_seg
== absolute_section
9071 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9072 || !cpu_arch_flags
.bitfield
.cpui386
)
9075 /* Don't add prefix if it is a prefix or there is no operand in case
9076 that segment prefix is special. */
9077 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9080 if (last_insn
.kind
== last_insn_other
9081 || last_insn
.seg
!= now_seg
)
9085 as_warn_where (last_insn
.file
, last_insn
.line
,
9086 _("`%s` skips -malign-branch-boundary on `%s`"),
9087 last_insn
.name
, i
.tm
.name
);
9092 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9095 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9096 enum mf_jcc_kind
*mf_jcc_p
)
9100 /* NB: Don't work with COND_JUMP86 without i386. */
9101 if (!align_branch_power
9102 || now_seg
== absolute_section
9103 || !cpu_arch_flags
.bitfield
.cpui386
)
9108 /* Check for jcc and direct jmp. */
9109 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9111 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9113 *branch_p
= align_branch_jmp
;
9114 add_padding
= align_branch
& align_branch_jmp_bit
;
9118 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9119 igore the lowest bit. */
9120 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9121 *branch_p
= align_branch_jcc
;
9122 if ((align_branch
& align_branch_jcc_bit
))
9126 else if (is_any_vex_encoding (&i
.tm
))
9128 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9131 *branch_p
= align_branch_ret
;
9132 if ((align_branch
& align_branch_ret_bit
))
9137 /* Check for indirect jmp, direct and indirect calls. */
9138 if (i
.tm
.base_opcode
== 0xe8)
9141 *branch_p
= align_branch_call
;
9142 if ((align_branch
& align_branch_call_bit
))
9145 else if (i
.tm
.base_opcode
== 0xff
9146 && (i
.tm
.extension_opcode
== 2
9147 || i
.tm
.extension_opcode
== 4))
9149 /* Indirect call and jmp. */
9150 *branch_p
= align_branch_indirect
;
9151 if ((align_branch
& align_branch_indirect_bit
))
9158 && (i
.op
[0].disps
->X_op
== O_symbol
9159 || (i
.op
[0].disps
->X_op
== O_subtract
9160 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9162 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9163 /* No padding to call to global or undefined tls_get_addr. */
9164 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9165 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9171 && last_insn
.kind
!= last_insn_other
9172 && last_insn
.seg
== now_seg
)
9175 as_warn_where (last_insn
.file
, last_insn
.line
,
9176 _("`%s` skips -malign-branch-boundary on `%s`"),
9177 last_insn
.name
, i
.tm
.name
);
9187 fragS
*insn_start_frag
;
9188 offsetT insn_start_off
;
9189 fragS
*fragP
= NULL
;
9190 enum align_branch_kind branch
= align_branch_none
;
9191 /* The initializer is arbitrary just to avoid uninitialized error.
9192 it's actually either assigned in add_branch_padding_frag_p
9193 or never be used. */
9194 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9197 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9199 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9200 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9201 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9203 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9204 || i
.tm
.cpu_flags
.bitfield
.cpu287
9205 || i
.tm
.cpu_flags
.bitfield
.cpu387
9206 || i
.tm
.cpu_flags
.bitfield
.cpu687
9207 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9208 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9210 if ((i
.xstate
& xstate_mmx
)
9211 || i
.tm
.base_opcode
== 0xf77 /* emms */
9212 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9213 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9217 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9218 i
.xstate
|= xstate_zmm
;
9219 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9220 i
.xstate
|= xstate_ymm
;
9221 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9222 i
.xstate
|= xstate_xmm
;
9225 /* vzeroall / vzeroupper */
9226 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9227 i
.xstate
|= xstate_ymm
;
9229 if ((i
.xstate
& xstate_xmm
)
9230 /* ldmxcsr / stmxcsr */
9231 || (i
.tm
.base_opcode
== 0xfae && i
.tm
.cpu_flags
.bitfield
.cpusse
)
9232 /* vldmxcsr / vstmxcsr */
9233 || (i
.tm
.base_opcode
== 0xae && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9234 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9235 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9236 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9238 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9239 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9240 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9241 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9242 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9243 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9244 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9245 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9246 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9247 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9248 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9249 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9250 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9251 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9253 if (x86_feature_2_used
9254 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9255 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9256 || (i
.tm
.base_opcode
== 0xfc7
9257 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9258 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9259 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9260 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9261 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9262 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9263 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9264 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9265 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9266 /* LAHF-SAHF insns in 64-bit mode. */
9267 || (flag_code
== CODE_64BIT
9268 && (i
.tm
.base_opcode
| 1) == 0x9f))
9269 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9270 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9271 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9272 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9273 CpuAVX512DQ, LPW, TBM and AMX. */
9274 || (i
.tm
.opcode_modifier
.vex
9275 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9276 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9277 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9278 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9279 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9280 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9281 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9282 || i
.tm
.cpu_flags
.bitfield
.cpufma
9283 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9284 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9285 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9286 || (x86_feature_2_used
9287 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9288 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9289 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9290 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9291 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9292 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9293 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9294 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9295 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9297 || (i
.tm
.opcode_modifier
.evex
9298 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9299 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9300 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9301 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9305 /* Tie dwarf2 debug info to the address at the start of the insn.
9306 We can't do this after the insn has been output as the current
9307 frag may have been closed off. eg. by frag_var. */
9308 dwarf2_emit_insn (0);
9310 insn_start_frag
= frag_now
;
9311 insn_start_off
= frag_now_fix ();
9313 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9316 /* Branch can be 8 bytes. Leave some room for prefixes. */
9317 unsigned int max_branch_padding_size
= 14;
9319 /* Align section to boundary. */
9320 record_alignment (now_seg
, align_branch_power
);
9322 /* Make room for padding. */
9323 frag_grow (max_branch_padding_size
);
9325 /* Start of the padding. */
9330 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9331 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9334 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9335 fragP
->tc_frag_data
.branch_type
= branch
;
9336 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9340 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9342 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9343 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9345 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9346 output_interseg_jump ();
9349 /* Output normal instructions here. */
9353 enum mf_cmp_kind mf_cmp
;
9356 && (i
.tm
.base_opcode
== 0xfaee8
9357 || i
.tm
.base_opcode
== 0xfaef0
9358 || i
.tm
.base_opcode
== 0xfaef8))
9360 /* Encode lfence, mfence, and sfence as
9361 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9362 if (now_seg
!= absolute_section
)
9364 offsetT val
= 0x240483f0ULL
;
9367 md_number_to_chars (p
, val
, 5);
9370 abs_section_offset
+= 5;
9374 /* Some processors fail on LOCK prefix. This options makes
9375 assembler ignore LOCK prefix and serves as a workaround. */
9376 if (omit_lock_prefix
)
9378 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9380 i
.prefix
[LOCK_PREFIX
] = 0;
9384 /* Skip if this is a branch. */
9386 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9388 /* Make room for padding. */
9389 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9394 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9395 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9398 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9399 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9400 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9402 else if (add_branch_prefix_frag_p ())
9404 unsigned int max_prefix_size
= align_branch_prefix_size
;
9406 /* Make room for padding. */
9407 frag_grow (max_prefix_size
);
9412 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9413 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9416 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9419 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9420 don't need the explicit prefix. */
9421 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9423 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9432 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9433 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9437 switch (i
.tm
.opcode_length
)
9444 /* Check for pseudo prefixes. */
9445 as_bad_where (insn_start_frag
->fr_file
,
9446 insn_start_frag
->fr_line
,
9447 _("pseudo prefix without instruction"));
9457 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9458 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9459 R_X86_64_GOTTPOFF relocation so that linker can safely
9460 perform IE->LE optimization. A dummy REX_OPCODE prefix
9461 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9462 relocation for GDesc -> IE/LE optimization. */
9463 if (x86_elf_abi
== X86_64_X32_ABI
9465 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9466 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9467 && i
.prefix
[REX_PREFIX
] == 0)
9468 add_prefix (REX_OPCODE
);
9471 /* The prefix bytes. */
9472 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9474 frag_opcode_byte (*q
);
9478 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9484 frag_opcode_byte (*q
);
9487 /* There should be no other prefixes for instructions
9492 /* For EVEX instructions i.vrex should become 0 after
9493 build_evex_prefix. For VEX instructions upper 16 registers
9494 aren't available, so VREX should be 0. */
9497 /* Now the VEX prefix. */
9498 if (now_seg
!= absolute_section
)
9500 p
= frag_more (i
.vex
.length
);
9501 for (j
= 0; j
< i
.vex
.length
; j
++)
9502 p
[j
] = i
.vex
.bytes
[j
];
9505 abs_section_offset
+= i
.vex
.length
;
9508 /* Now the opcode; be careful about word order here! */
9509 if (now_seg
== absolute_section
)
9510 abs_section_offset
+= i
.tm
.opcode_length
;
9511 else if (i
.tm
.opcode_length
== 1)
9513 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9517 switch (i
.tm
.opcode_length
)
9521 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9522 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9526 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9536 /* Put out high byte first: can't use md_number_to_chars! */
9537 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9538 *p
= i
.tm
.base_opcode
& 0xff;
9541 /* Now the modrm byte and sib byte (if present). */
9542 if (i
.tm
.opcode_modifier
.modrm
)
9544 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9546 | (i
.rm
.mode
<< 6));
9547 /* If i.rm.regmem == ESP (4)
9548 && i.rm.mode != (Register mode)
9550 ==> need second modrm byte. */
9551 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9553 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9554 frag_opcode_byte ((i
.sib
.base
<< 0)
9555 | (i
.sib
.index
<< 3)
9556 | (i
.sib
.scale
<< 6));
9559 if (i
.disp_operands
)
9560 output_disp (insn_start_frag
, insn_start_off
);
9563 output_imm (insn_start_frag
, insn_start_off
);
9566 * frag_now_fix () returning plain abs_section_offset when we're in the
9567 * absolute section, and abs_section_offset not getting updated as data
9568 * gets added to the frag breaks the logic below.
9570 if (now_seg
!= absolute_section
)
9572 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9574 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9578 /* NB: Don't add prefix with GOTPC relocation since
9579 output_disp() above depends on the fixed encoding
9580 length. Can't add prefix with TLS relocation since
9581 it breaks TLS linker optimization. */
9582 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9583 /* Prefix count on the current instruction. */
9584 unsigned int count
= i
.vex
.length
;
9586 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9587 /* REX byte is encoded in VEX/EVEX prefix. */
9588 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9591 /* Count prefixes for extended opcode maps. */
9593 switch (i
.tm
.opcode_length
)
9596 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9599 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9611 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9620 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9623 /* Set the maximum prefix size in BRANCH_PREFIX
9625 if (fragP
->tc_frag_data
.max_bytes
> max
)
9626 fragP
->tc_frag_data
.max_bytes
= max
;
9627 if (fragP
->tc_frag_data
.max_bytes
> count
)
9628 fragP
->tc_frag_data
.max_bytes
-= count
;
9630 fragP
->tc_frag_data
.max_bytes
= 0;
9634 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9636 unsigned int max_prefix_size
;
9637 if (align_branch_prefix_size
> max
)
9638 max_prefix_size
= max
;
9640 max_prefix_size
= align_branch_prefix_size
;
9641 if (max_prefix_size
> count
)
9642 fragP
->tc_frag_data
.max_prefix_length
9643 = max_prefix_size
- count
;
9646 /* Use existing segment prefix if possible. Use CS
9647 segment prefix in 64-bit mode. In 32-bit mode, use SS
9648 segment prefix with ESP/EBP base register and use DS
9649 segment prefix without ESP/EBP base register. */
9650 if (i
.prefix
[SEG_PREFIX
])
9651 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9652 else if (flag_code
== CODE_64BIT
)
9653 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9655 && (i
.base_reg
->reg_num
== 4
9656 || i
.base_reg
->reg_num
== 5))
9657 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9659 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9664 /* NB: Don't work with COND_JUMP86 without i386. */
9665 if (align_branch_power
9666 && now_seg
!= absolute_section
9667 && cpu_arch_flags
.bitfield
.cpui386
)
9669 /* Terminate each frag so that we can add prefix and check for
9671 frag_wane (frag_now
);
9678 pi ("" /*line*/, &i
);
9680 #endif /* DEBUG386 */
9683 /* Return the size of the displacement operand N. */
9686 disp_size (unsigned int n
)
9690 if (i
.types
[n
].bitfield
.disp64
)
9692 else if (i
.types
[n
].bitfield
.disp8
)
9694 else if (i
.types
[n
].bitfield
.disp16
)
9699 /* Return the size of the immediate operand N. */
9702 imm_size (unsigned int n
)
9705 if (i
.types
[n
].bitfield
.imm64
)
9707 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9709 else if (i
.types
[n
].bitfield
.imm16
)
9715 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9720 for (n
= 0; n
< i
.operands
; n
++)
9722 if (operand_type_check (i
.types
[n
], disp
))
9724 int size
= disp_size (n
);
9726 if (now_seg
== absolute_section
)
9727 abs_section_offset
+= size
;
9728 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9730 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9732 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9734 p
= frag_more (size
);
9735 md_number_to_chars (p
, val
, size
);
9739 enum bfd_reloc_code_real reloc_type
;
9740 int sign
= i
.types
[n
].bitfield
.disp32s
;
9741 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9744 /* We can't have 8 bit displacement here. */
9745 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9747 /* The PC relative address is computed relative
9748 to the instruction boundary, so in case immediate
9749 fields follows, we need to adjust the value. */
9750 if (pcrel
&& i
.imm_operands
)
9755 for (n1
= 0; n1
< i
.operands
; n1
++)
9756 if (operand_type_check (i
.types
[n1
], imm
))
9758 /* Only one immediate is allowed for PC
9759 relative address. */
9760 gas_assert (sz
== 0);
9762 i
.op
[n
].disps
->X_add_number
-= sz
;
9764 /* We should find the immediate. */
9765 gas_assert (sz
!= 0);
9768 p
= frag_more (size
);
9769 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9771 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9772 && (((reloc_type
== BFD_RELOC_32
9773 || reloc_type
== BFD_RELOC_X86_64_32S
9774 || (reloc_type
== BFD_RELOC_64
9776 && (i
.op
[n
].disps
->X_op
== O_symbol
9777 || (i
.op
[n
].disps
->X_op
== O_add
9778 && ((symbol_get_value_expression
9779 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9781 || reloc_type
== BFD_RELOC_32_PCREL
))
9785 reloc_type
= BFD_RELOC_386_GOTPC
;
9786 i
.has_gotpc_tls_reloc
= TRUE
;
9787 i
.op
[n
].imms
->X_add_number
+=
9788 encoding_length (insn_start_frag
, insn_start_off
, p
);
9790 else if (reloc_type
== BFD_RELOC_64
)
9791 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9793 /* Don't do the adjustment for x86-64, as there
9794 the pcrel addressing is relative to the _next_
9795 insn, and that is taken care of in other code. */
9796 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9798 else if (align_branch_power
)
9802 case BFD_RELOC_386_TLS_GD
:
9803 case BFD_RELOC_386_TLS_LDM
:
9804 case BFD_RELOC_386_TLS_IE
:
9805 case BFD_RELOC_386_TLS_IE_32
:
9806 case BFD_RELOC_386_TLS_GOTIE
:
9807 case BFD_RELOC_386_TLS_GOTDESC
:
9808 case BFD_RELOC_386_TLS_DESC_CALL
:
9809 case BFD_RELOC_X86_64_TLSGD
:
9810 case BFD_RELOC_X86_64_TLSLD
:
9811 case BFD_RELOC_X86_64_GOTTPOFF
:
9812 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9813 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9814 i
.has_gotpc_tls_reloc
= TRUE
;
9819 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9820 size
, i
.op
[n
].disps
, pcrel
,
9822 /* Check for "call/jmp *mem", "mov mem, %reg",
9823 "test %reg, mem" and "binop mem, %reg" where binop
9824 is one of adc, add, and, cmp, or, sbb, sub, xor
9825 instructions without data prefix. Always generate
9826 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9827 if (i
.prefix
[DATA_PREFIX
] == 0
9828 && (generate_relax_relocations
9831 && i
.rm
.regmem
== 5))
9833 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9834 && !is_any_vex_encoding(&i
.tm
)
9835 && ((i
.operands
== 1
9836 && i
.tm
.base_opcode
== 0xff
9837 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9839 && (i
.tm
.base_opcode
== 0x8b
9840 || i
.tm
.base_opcode
== 0x85
9841 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9845 fixP
->fx_tcbit
= i
.rex
!= 0;
9847 && (i
.base_reg
->reg_num
== RegIP
))
9848 fixP
->fx_tcbit2
= 1;
9851 fixP
->fx_tcbit2
= 1;
9859 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9864 for (n
= 0; n
< i
.operands
; n
++)
9866 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9867 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9870 if (operand_type_check (i
.types
[n
], imm
))
9872 int size
= imm_size (n
);
9874 if (now_seg
== absolute_section
)
9875 abs_section_offset
+= size
;
9876 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9880 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9882 p
= frag_more (size
);
9883 md_number_to_chars (p
, val
, size
);
9887 /* Not absolute_section.
9888 Need a 32-bit fixup (don't support 8bit
9889 non-absolute imms). Try to support other
9891 enum bfd_reloc_code_real reloc_type
;
9894 if (i
.types
[n
].bitfield
.imm32s
9895 && (i
.suffix
== QWORD_MNEM_SUFFIX
9896 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9901 p
= frag_more (size
);
9902 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9904 /* This is tough to explain. We end up with this one if we
9905 * have operands that look like
9906 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9907 * obtain the absolute address of the GOT, and it is strongly
9908 * preferable from a performance point of view to avoid using
9909 * a runtime relocation for this. The actual sequence of
9910 * instructions often look something like:
9915 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9917 * The call and pop essentially return the absolute address
9918 * of the label .L66 and store it in %ebx. The linker itself
9919 * will ultimately change the first operand of the addl so
9920 * that %ebx points to the GOT, but to keep things simple, the
9921 * .o file must have this operand set so that it generates not
9922 * the absolute address of .L66, but the absolute address of
9923 * itself. This allows the linker itself simply treat a GOTPC
9924 * relocation as asking for a pcrel offset to the GOT to be
9925 * added in, and the addend of the relocation is stored in the
9926 * operand field for the instruction itself.
9928 * Our job here is to fix the operand so that it would add
9929 * the correct offset so that %ebx would point to itself. The
9930 * thing that is tricky is that .-.L66 will point to the
9931 * beginning of the instruction, so we need to further modify
9932 * the operand so that it will point to itself. There are
9933 * other cases where you have something like:
9935 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9937 * and here no correction would be required. Internally in
9938 * the assembler we treat operands of this form as not being
9939 * pcrel since the '.' is explicitly mentioned, and I wonder
9940 * whether it would simplify matters to do it this way. Who
9941 * knows. In earlier versions of the PIC patches, the
9942 * pcrel_adjust field was used to store the correction, but
9943 * since the expression is not pcrel, I felt it would be
9944 * confusing to do it this way. */
9946 if ((reloc_type
== BFD_RELOC_32
9947 || reloc_type
== BFD_RELOC_X86_64_32S
9948 || reloc_type
== BFD_RELOC_64
)
9950 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9951 && (i
.op
[n
].imms
->X_op
== O_symbol
9952 || (i
.op
[n
].imms
->X_op
== O_add
9953 && ((symbol_get_value_expression
9954 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9958 reloc_type
= BFD_RELOC_386_GOTPC
;
9960 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9962 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9963 i
.has_gotpc_tls_reloc
= TRUE
;
9964 i
.op
[n
].imms
->X_add_number
+=
9965 encoding_length (insn_start_frag
, insn_start_off
, p
);
9967 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9968 i
.op
[n
].imms
, 0, reloc_type
);
9974 /* x86_cons_fix_new is called via the expression parsing code when a
9975 reloc is needed. We use this hook to get the correct .got reloc. */
9976 static int cons_sign
= -1;
9979 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9980 expressionS
*exp
, bfd_reloc_code_real_type r
)
9982 r
= reloc (len
, 0, cons_sign
, r
);
9985 if (exp
->X_op
== O_secrel
)
9987 exp
->X_op
= O_symbol
;
9988 r
= BFD_RELOC_32_SECREL
;
9992 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9995 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9996 purpose of the `.dc.a' internal pseudo-op. */
9999 x86_address_bytes (void)
10001 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10003 return stdoutput
->arch_info
->bits_per_address
/ 8;
10006 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10007 || defined (LEX_AT)
10008 # define lex_got(reloc, adjust, types) NULL
10010 /* Parse operands of the form
10011 <symbol>@GOTOFF+<nnn>
10012 and similar .plt or .got references.
10014 If we find one, set up the correct relocation in RELOC and copy the
10015 input string, minus the `@GOTOFF' into a malloc'd buffer for
10016 parsing by the calling routine. Return this buffer, and if ADJUST
10017 is non-null set it to the length of the string we removed from the
10018 input line. Otherwise return NULL. */
10020 lex_got (enum bfd_reloc_code_real
*rel
,
10022 i386_operand_type
*types
)
10024 /* Some of the relocations depend on the size of what field is to
10025 be relocated. But in our callers i386_immediate and i386_displacement
10026 we don't yet know the operand size (this will be set by insn
10027 matching). Hence we record the word32 relocation here,
10028 and adjust the reloc according to the real size in reloc(). */
10029 static const struct {
10032 const enum bfd_reloc_code_real rel
[2];
10033 const i386_operand_type types64
;
10034 bfd_boolean need_GOT_symbol
;
10036 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10037 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10038 BFD_RELOC_SIZE32
},
10039 OPERAND_TYPE_IMM32_64
, FALSE
},
10041 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10042 BFD_RELOC_X86_64_PLTOFF64
},
10043 OPERAND_TYPE_IMM64
, TRUE
},
10044 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10045 BFD_RELOC_X86_64_PLT32
},
10046 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10047 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10048 BFD_RELOC_X86_64_GOTPLT64
},
10049 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10050 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10051 BFD_RELOC_X86_64_GOTOFF64
},
10052 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10053 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10054 BFD_RELOC_X86_64_GOTPCREL
},
10055 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10056 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10057 BFD_RELOC_X86_64_TLSGD
},
10058 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10059 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10060 _dummy_first_bfd_reloc_code_real
},
10061 OPERAND_TYPE_NONE
, TRUE
},
10062 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10063 BFD_RELOC_X86_64_TLSLD
},
10064 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10065 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10066 BFD_RELOC_X86_64_GOTTPOFF
},
10067 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10068 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10069 BFD_RELOC_X86_64_TPOFF32
},
10070 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10071 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10072 _dummy_first_bfd_reloc_code_real
},
10073 OPERAND_TYPE_NONE
, TRUE
},
10074 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10075 BFD_RELOC_X86_64_DTPOFF32
},
10076 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10077 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10078 _dummy_first_bfd_reloc_code_real
},
10079 OPERAND_TYPE_NONE
, TRUE
},
10080 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10081 _dummy_first_bfd_reloc_code_real
},
10082 OPERAND_TYPE_NONE
, TRUE
},
10083 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10084 BFD_RELOC_X86_64_GOT32
},
10085 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10086 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10087 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10088 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10089 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10090 BFD_RELOC_X86_64_TLSDESC_CALL
},
10091 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10096 #if defined (OBJ_MAYBE_ELF)
10101 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10102 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10105 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10107 int len
= gotrel
[j
].len
;
10108 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10110 if (gotrel
[j
].rel
[object_64bit
] != 0)
10113 char *tmpbuf
, *past_reloc
;
10115 *rel
= gotrel
[j
].rel
[object_64bit
];
10119 if (flag_code
!= CODE_64BIT
)
10121 types
->bitfield
.imm32
= 1;
10122 types
->bitfield
.disp32
= 1;
10125 *types
= gotrel
[j
].types64
;
10128 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10129 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10131 /* The length of the first part of our input line. */
10132 first
= cp
- input_line_pointer
;
10134 /* The second part goes from after the reloc token until
10135 (and including) an end_of_line char or comma. */
10136 past_reloc
= cp
+ 1 + len
;
10138 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10140 second
= cp
+ 1 - past_reloc
;
10142 /* Allocate and copy string. The trailing NUL shouldn't
10143 be necessary, but be safe. */
10144 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10145 memcpy (tmpbuf
, input_line_pointer
, first
);
10146 if (second
!= 0 && *past_reloc
!= ' ')
10147 /* Replace the relocation token with ' ', so that
10148 errors like foo@GOTOFF1 will be detected. */
10149 tmpbuf
[first
++] = ' ';
10151 /* Increment length by 1 if the relocation token is
10156 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10157 tmpbuf
[first
+ second
] = '\0';
10161 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10162 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10167 /* Might be a symbol version string. Don't as_bad here. */
10176 /* Parse operands of the form
10177 <symbol>@SECREL32+<nnn>
10179 If we find one, set up the correct relocation in RELOC and copy the
10180 input string, minus the `@SECREL32' into a malloc'd buffer for
10181 parsing by the calling routine. Return this buffer, and if ADJUST
10182 is non-null set it to the length of the string we removed from the
10183 input line. Otherwise return NULL.
10185 This function is copied from the ELF version above adjusted for PE targets. */
10188 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10189 int *adjust ATTRIBUTE_UNUSED
,
10190 i386_operand_type
*types
)
10192 static const struct
10196 const enum bfd_reloc_code_real rel
[2];
10197 const i386_operand_type types64
;
10201 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10202 BFD_RELOC_32_SECREL
},
10203 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10209 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10210 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10213 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10215 int len
= gotrel
[j
].len
;
10217 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10219 if (gotrel
[j
].rel
[object_64bit
] != 0)
10222 char *tmpbuf
, *past_reloc
;
10224 *rel
= gotrel
[j
].rel
[object_64bit
];
10230 if (flag_code
!= CODE_64BIT
)
10232 types
->bitfield
.imm32
= 1;
10233 types
->bitfield
.disp32
= 1;
10236 *types
= gotrel
[j
].types64
;
10239 /* The length of the first part of our input line. */
10240 first
= cp
- input_line_pointer
;
10242 /* The second part goes from after the reloc token until
10243 (and including) an end_of_line char or comma. */
10244 past_reloc
= cp
+ 1 + len
;
10246 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10248 second
= cp
+ 1 - past_reloc
;
10250 /* Allocate and copy string. The trailing NUL shouldn't
10251 be necessary, but be safe. */
10252 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10253 memcpy (tmpbuf
, input_line_pointer
, first
);
10254 if (second
!= 0 && *past_reloc
!= ' ')
10255 /* Replace the relocation token with ' ', so that
10256 errors like foo@SECLREL321 will be detected. */
10257 tmpbuf
[first
++] = ' ';
10258 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10259 tmpbuf
[first
+ second
] = '\0';
10263 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10264 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10269 /* Might be a symbol version string. Don't as_bad here. */
10275 bfd_reloc_code_real_type
10276 x86_cons (expressionS
*exp
, int size
)
10278 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10280 intel_syntax
= -intel_syntax
;
10283 if (size
== 4 || (object_64bit
&& size
== 8))
10285 /* Handle @GOTOFF and the like in an expression. */
10287 char *gotfree_input_line
;
10290 save
= input_line_pointer
;
10291 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10292 if (gotfree_input_line
)
10293 input_line_pointer
= gotfree_input_line
;
10297 if (gotfree_input_line
)
10299 /* expression () has merrily parsed up to the end of line,
10300 or a comma - in the wrong buffer. Transfer how far
10301 input_line_pointer has moved to the right buffer. */
10302 input_line_pointer
= (save
10303 + (input_line_pointer
- gotfree_input_line
)
10305 free (gotfree_input_line
);
10306 if (exp
->X_op
== O_constant
10307 || exp
->X_op
== O_absent
10308 || exp
->X_op
== O_illegal
10309 || exp
->X_op
== O_register
10310 || exp
->X_op
== O_big
)
10312 char c
= *input_line_pointer
;
10313 *input_line_pointer
= 0;
10314 as_bad (_("missing or invalid expression `%s'"), save
);
10315 *input_line_pointer
= c
;
10317 else if ((got_reloc
== BFD_RELOC_386_PLT32
10318 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10319 && exp
->X_op
!= O_symbol
)
10321 char c
= *input_line_pointer
;
10322 *input_line_pointer
= 0;
10323 as_bad (_("invalid PLT expression `%s'"), save
);
10324 *input_line_pointer
= c
;
10331 intel_syntax
= -intel_syntax
;
10334 i386_intel_simplify (exp
);
10340 signed_cons (int size
)
10342 if (flag_code
== CODE_64BIT
)
10350 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10357 if (exp
.X_op
== O_symbol
)
10358 exp
.X_op
= O_secrel
;
10360 emit_expr (&exp
, 4);
10362 while (*input_line_pointer
++ == ',');
10364 input_line_pointer
--;
10365 demand_empty_rest_of_line ();
10369 /* Handle Vector operations. */
10372 check_VecOperations (char *op_string
, char *op_end
)
10374 const reg_entry
*mask
;
10379 && (op_end
== NULL
|| op_string
< op_end
))
10382 if (*op_string
== '{')
10386 /* Check broadcasts. */
10387 if (strncmp (op_string
, "1to", 3) == 0)
10392 goto duplicated_vec_op
;
10395 if (*op_string
== '8')
10397 else if (*op_string
== '4')
10399 else if (*op_string
== '2')
10401 else if (*op_string
== '1'
10402 && *(op_string
+1) == '6')
10409 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10414 broadcast_op
.type
= bcst_type
;
10415 broadcast_op
.operand
= this_operand
;
10416 broadcast_op
.bytes
= 0;
10417 i
.broadcast
= &broadcast_op
;
10419 /* Check masking operation. */
10420 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10422 if (mask
== &bad_reg
)
10425 /* k0 can't be used for write mask. */
10426 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10428 as_bad (_("`%s%s' can't be used for write mask"),
10429 register_prefix
, mask
->reg_name
);
10435 mask_op
.mask
= mask
;
10436 mask_op
.zeroing
= 0;
10437 mask_op
.operand
= this_operand
;
10443 goto duplicated_vec_op
;
10445 i
.mask
->mask
= mask
;
10447 /* Only "{z}" is allowed here. No need to check
10448 zeroing mask explicitly. */
10449 if (i
.mask
->operand
!= this_operand
)
10451 as_bad (_("invalid write mask `%s'"), saved
);
10456 op_string
= end_op
;
10458 /* Check zeroing-flag for masking operation. */
10459 else if (*op_string
== 'z')
10463 mask_op
.mask
= NULL
;
10464 mask_op
.zeroing
= 1;
10465 mask_op
.operand
= this_operand
;
10470 if (i
.mask
->zeroing
)
10473 as_bad (_("duplicated `%s'"), saved
);
10477 i
.mask
->zeroing
= 1;
10479 /* Only "{%k}" is allowed here. No need to check mask
10480 register explicitly. */
10481 if (i
.mask
->operand
!= this_operand
)
10483 as_bad (_("invalid zeroing-masking `%s'"),
10492 goto unknown_vec_op
;
10494 if (*op_string
!= '}')
10496 as_bad (_("missing `}' in `%s'"), saved
);
10501 /* Strip whitespace since the addition of pseudo prefixes
10502 changed how the scrubber treats '{'. */
10503 if (is_space_char (*op_string
))
10509 /* We don't know this one. */
10510 as_bad (_("unknown vector operation: `%s'"), saved
);
10514 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10516 as_bad (_("zeroing-masking only allowed with write mask"));
10524 i386_immediate (char *imm_start
)
10526 char *save_input_line_pointer
;
10527 char *gotfree_input_line
;
10530 i386_operand_type types
;
10532 operand_type_set (&types
, ~0);
10534 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10536 as_bad (_("at most %d immediate operands are allowed"),
10537 MAX_IMMEDIATE_OPERANDS
);
10541 exp
= &im_expressions
[i
.imm_operands
++];
10542 i
.op
[this_operand
].imms
= exp
;
10544 if (is_space_char (*imm_start
))
10547 save_input_line_pointer
= input_line_pointer
;
10548 input_line_pointer
= imm_start
;
10550 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10551 if (gotfree_input_line
)
10552 input_line_pointer
= gotfree_input_line
;
10554 exp_seg
= expression (exp
);
10556 SKIP_WHITESPACE ();
10558 /* Handle vector operations. */
10559 if (*input_line_pointer
== '{')
10561 input_line_pointer
= check_VecOperations (input_line_pointer
,
10563 if (input_line_pointer
== NULL
)
10567 if (*input_line_pointer
)
10568 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10570 input_line_pointer
= save_input_line_pointer
;
10571 if (gotfree_input_line
)
10573 free (gotfree_input_line
);
10575 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10576 exp
->X_op
= O_illegal
;
10579 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10583 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10584 i386_operand_type types
, const char *imm_start
)
10586 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10589 as_bad (_("missing or invalid immediate expression `%s'"),
10593 else if (exp
->X_op
== O_constant
)
10595 /* Size it properly later. */
10596 i
.types
[this_operand
].bitfield
.imm64
= 1;
10597 /* If not 64bit, sign extend val. */
10598 if (flag_code
!= CODE_64BIT
10599 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10601 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10603 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10604 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10605 && exp_seg
!= absolute_section
10606 && exp_seg
!= text_section
10607 && exp_seg
!= data_section
10608 && exp_seg
!= bss_section
10609 && exp_seg
!= undefined_section
10610 && !bfd_is_com_section (exp_seg
))
10612 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10616 else if (!intel_syntax
&& exp_seg
== reg_section
)
10619 as_bad (_("illegal immediate register operand %s"), imm_start
);
10624 /* This is an address. The size of the address will be
10625 determined later, depending on destination register,
10626 suffix, or the default for the section. */
10627 i
.types
[this_operand
].bitfield
.imm8
= 1;
10628 i
.types
[this_operand
].bitfield
.imm16
= 1;
10629 i
.types
[this_operand
].bitfield
.imm32
= 1;
10630 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10631 i
.types
[this_operand
].bitfield
.imm64
= 1;
10632 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10640 i386_scale (char *scale
)
10643 char *save
= input_line_pointer
;
10645 input_line_pointer
= scale
;
10646 val
= get_absolute_expression ();
10651 i
.log2_scale_factor
= 0;
10654 i
.log2_scale_factor
= 1;
10657 i
.log2_scale_factor
= 2;
10660 i
.log2_scale_factor
= 3;
10664 char sep
= *input_line_pointer
;
10666 *input_line_pointer
= '\0';
10667 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10669 *input_line_pointer
= sep
;
10670 input_line_pointer
= save
;
10674 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10676 as_warn (_("scale factor of %d without an index register"),
10677 1 << i
.log2_scale_factor
);
10678 i
.log2_scale_factor
= 0;
10680 scale
= input_line_pointer
;
10681 input_line_pointer
= save
;
10686 i386_displacement (char *disp_start
, char *disp_end
)
10690 char *save_input_line_pointer
;
10691 char *gotfree_input_line
;
10693 i386_operand_type bigdisp
, types
= anydisp
;
10696 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10698 as_bad (_("at most %d displacement operands are allowed"),
10699 MAX_MEMORY_OPERANDS
);
10703 operand_type_set (&bigdisp
, 0);
10705 || i
.types
[this_operand
].bitfield
.baseindex
10706 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10707 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10709 i386_addressing_mode ();
10710 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10711 if (flag_code
== CODE_64BIT
)
10715 bigdisp
.bitfield
.disp32s
= 1;
10716 bigdisp
.bitfield
.disp64
= 1;
10719 bigdisp
.bitfield
.disp32
= 1;
10721 else if ((flag_code
== CODE_16BIT
) ^ override
)
10722 bigdisp
.bitfield
.disp16
= 1;
10724 bigdisp
.bitfield
.disp32
= 1;
10728 /* For PC-relative branches, the width of the displacement may be
10729 dependent upon data size, but is never dependent upon address size.
10730 Also make sure to not unintentionally match against a non-PC-relative
10731 branch template. */
10732 static templates aux_templates
;
10733 const insn_template
*t
= current_templates
->start
;
10734 bfd_boolean has_intel64
= FALSE
;
10736 aux_templates
.start
= t
;
10737 while (++t
< current_templates
->end
)
10739 if (t
->opcode_modifier
.jump
10740 != current_templates
->start
->opcode_modifier
.jump
)
10742 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10743 has_intel64
= TRUE
;
10745 if (t
< current_templates
->end
)
10747 aux_templates
.end
= t
;
10748 current_templates
= &aux_templates
;
10751 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10752 if (flag_code
== CODE_64BIT
)
10754 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10755 && (!intel64
|| !has_intel64
))
10756 bigdisp
.bitfield
.disp16
= 1;
10758 bigdisp
.bitfield
.disp32s
= 1;
10763 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10765 : LONG_MNEM_SUFFIX
));
10766 bigdisp
.bitfield
.disp32
= 1;
10767 if ((flag_code
== CODE_16BIT
) ^ override
)
10769 bigdisp
.bitfield
.disp32
= 0;
10770 bigdisp
.bitfield
.disp16
= 1;
10774 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10777 exp
= &disp_expressions
[i
.disp_operands
];
10778 i
.op
[this_operand
].disps
= exp
;
10780 save_input_line_pointer
= input_line_pointer
;
10781 input_line_pointer
= disp_start
;
10782 END_STRING_AND_SAVE (disp_end
);
10784 #ifndef GCC_ASM_O_HACK
10785 #define GCC_ASM_O_HACK 0
10788 END_STRING_AND_SAVE (disp_end
+ 1);
10789 if (i
.types
[this_operand
].bitfield
.baseIndex
10790 && displacement_string_end
[-1] == '+')
10792 /* This hack is to avoid a warning when using the "o"
10793 constraint within gcc asm statements.
10796 #define _set_tssldt_desc(n,addr,limit,type) \
10797 __asm__ __volatile__ ( \
10798 "movw %w2,%0\n\t" \
10799 "movw %w1,2+%0\n\t" \
10800 "rorl $16,%1\n\t" \
10801 "movb %b1,4+%0\n\t" \
10802 "movb %4,5+%0\n\t" \
10803 "movb $0,6+%0\n\t" \
10804 "movb %h1,7+%0\n\t" \
10806 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10808 This works great except that the output assembler ends
10809 up looking a bit weird if it turns out that there is
10810 no offset. You end up producing code that looks like:
10823 So here we provide the missing zero. */
10825 *displacement_string_end
= '0';
10828 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10829 if (gotfree_input_line
)
10830 input_line_pointer
= gotfree_input_line
;
10832 exp_seg
= expression (exp
);
10834 SKIP_WHITESPACE ();
10835 if (*input_line_pointer
)
10836 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10838 RESTORE_END_STRING (disp_end
+ 1);
10840 input_line_pointer
= save_input_line_pointer
;
10841 if (gotfree_input_line
)
10843 free (gotfree_input_line
);
10845 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10846 exp
->X_op
= O_illegal
;
10849 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10851 RESTORE_END_STRING (disp_end
);
10857 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10858 i386_operand_type types
, const char *disp_start
)
10860 i386_operand_type bigdisp
;
10863 /* We do this to make sure that the section symbol is in
10864 the symbol table. We will ultimately change the relocation
10865 to be relative to the beginning of the section. */
10866 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10867 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10868 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10870 if (exp
->X_op
!= O_symbol
)
10873 if (S_IS_LOCAL (exp
->X_add_symbol
)
10874 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10875 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10876 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10877 exp
->X_op
= O_subtract
;
10878 exp
->X_op_symbol
= GOT_symbol
;
10879 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10880 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10881 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10882 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10884 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10887 else if (exp
->X_op
== O_absent
10888 || exp
->X_op
== O_illegal
10889 || exp
->X_op
== O_big
)
10892 as_bad (_("missing or invalid displacement expression `%s'"),
10897 else if (flag_code
== CODE_64BIT
10898 && !i
.prefix
[ADDR_PREFIX
]
10899 && exp
->X_op
== O_constant
)
10901 /* Since displacement is signed extended to 64bit, don't allow
10902 disp32 and turn off disp32s if they are out of range. */
10903 i
.types
[this_operand
].bitfield
.disp32
= 0;
10904 if (!fits_in_signed_long (exp
->X_add_number
))
10906 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10907 if (i
.types
[this_operand
].bitfield
.baseindex
)
10909 as_bad (_("0x%lx out range of signed 32bit displacement"),
10910 (long) exp
->X_add_number
);
10916 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10917 else if (exp
->X_op
!= O_constant
10918 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10919 && exp_seg
!= absolute_section
10920 && exp_seg
!= text_section
10921 && exp_seg
!= data_section
10922 && exp_seg
!= bss_section
10923 && exp_seg
!= undefined_section
10924 && !bfd_is_com_section (exp_seg
))
10926 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10931 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10932 /* Constants get taken care of by optimize_disp(). */
10933 && exp
->X_op
!= O_constant
)
10934 i
.types
[this_operand
].bitfield
.disp8
= 1;
10936 /* Check if this is a displacement only operand. */
10937 bigdisp
= i
.types
[this_operand
];
10938 bigdisp
.bitfield
.disp8
= 0;
10939 bigdisp
.bitfield
.disp16
= 0;
10940 bigdisp
.bitfield
.disp32
= 0;
10941 bigdisp
.bitfield
.disp32s
= 0;
10942 bigdisp
.bitfield
.disp64
= 0;
10943 if (operand_type_all_zero (&bigdisp
))
10944 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10950 /* Return the active addressing mode, taking address override and
10951 registers forming the address into consideration. Update the
10952 address override prefix if necessary. */
10954 static enum flag_code
10955 i386_addressing_mode (void)
10957 enum flag_code addr_mode
;
10959 if (i
.prefix
[ADDR_PREFIX
])
10960 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10961 else if (flag_code
== CODE_16BIT
10962 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10963 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10964 from md_assemble() by "is not a valid base/index expression"
10965 when there is a base and/or index. */
10966 && !i
.types
[this_operand
].bitfield
.baseindex
)
10968 /* MPX insn memory operands with neither base nor index must be forced
10969 to use 32-bit addressing in 16-bit mode. */
10970 addr_mode
= CODE_32BIT
;
10971 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10973 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10974 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10978 addr_mode
= flag_code
;
10980 #if INFER_ADDR_PREFIX
10981 if (i
.mem_operands
== 0)
10983 /* Infer address prefix from the first memory operand. */
10984 const reg_entry
*addr_reg
= i
.base_reg
;
10986 if (addr_reg
== NULL
)
10987 addr_reg
= i
.index_reg
;
10991 if (addr_reg
->reg_type
.bitfield
.dword
)
10992 addr_mode
= CODE_32BIT
;
10993 else if (flag_code
!= CODE_64BIT
10994 && addr_reg
->reg_type
.bitfield
.word
)
10995 addr_mode
= CODE_16BIT
;
10997 if (addr_mode
!= flag_code
)
10999 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11001 /* Change the size of any displacement too. At most one
11002 of Disp16 or Disp32 is set.
11003 FIXME. There doesn't seem to be any real need for
11004 separate Disp16 and Disp32 flags. The same goes for
11005 Imm16 and Imm32. Removing them would probably clean
11006 up the code quite a lot. */
11007 if (flag_code
!= CODE_64BIT
11008 && (i
.types
[this_operand
].bitfield
.disp16
11009 || i
.types
[this_operand
].bitfield
.disp32
))
11010 i
.types
[this_operand
]
11011 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11021 /* Make sure the memory operand we've been dealt is valid.
11022 Return 1 on success, 0 on a failure. */
11025 i386_index_check (const char *operand_string
)
11027 const char *kind
= "base/index";
11028 enum flag_code addr_mode
= i386_addressing_mode ();
11029 const insn_template
*t
= current_templates
->start
;
11031 if (t
->opcode_modifier
.isstring
11032 && !t
->cpu_flags
.bitfield
.cpupadlock
11033 && (current_templates
->end
[-1].opcode_modifier
.isstring
11034 || i
.mem_operands
))
11036 /* Memory operands of string insns are special in that they only allow
11037 a single register (rDI, rSI, or rBX) as their memory address. */
11038 const reg_entry
*expected_reg
;
11039 static const char *di_si
[][2] =
11045 static const char *bx
[] = { "ebx", "bx", "rbx" };
11047 kind
= "string address";
11049 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11051 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11052 - IS_STRING_ES_OP0
;
11055 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11056 || ((!i
.mem_operands
!= !intel_syntax
)
11057 && current_templates
->end
[-1].operand_types
[1]
11058 .bitfield
.baseindex
))
11061 = (const reg_entry
*) str_hash_find (reg_hash
,
11062 di_si
[addr_mode
][op
== es_op
]);
11066 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11068 if (i
.base_reg
!= expected_reg
11070 || operand_type_check (i
.types
[this_operand
], disp
))
11072 /* The second memory operand must have the same size as
11076 && !((addr_mode
== CODE_64BIT
11077 && i
.base_reg
->reg_type
.bitfield
.qword
)
11078 || (addr_mode
== CODE_32BIT
11079 ? i
.base_reg
->reg_type
.bitfield
.dword
11080 : i
.base_reg
->reg_type
.bitfield
.word
)))
11083 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11085 intel_syntax
? '[' : '(',
11087 expected_reg
->reg_name
,
11088 intel_syntax
? ']' : ')');
11095 as_bad (_("`%s' is not a valid %s expression"),
11096 operand_string
, kind
);
11101 if (addr_mode
!= CODE_16BIT
)
11103 /* 32-bit/64-bit checks. */
11104 if (i
.disp_encoding
== disp_encoding_16bit
)
11107 as_bad (_("invalid `%s' prefix"),
11108 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11113 && ((addr_mode
== CODE_64BIT
11114 ? !i
.base_reg
->reg_type
.bitfield
.qword
11115 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11116 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11117 || i
.base_reg
->reg_num
== RegIZ
))
11119 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11120 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11121 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11122 && ((addr_mode
== CODE_64BIT
11123 ? !i
.index_reg
->reg_type
.bitfield
.qword
11124 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11125 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11128 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11129 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11130 && t
->base_opcode
== 0x0f1b)
11131 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11132 && (t
->base_opcode
& ~1) == 0x0f1a)
11133 || t
->opcode_modifier
.sib
== SIBMEM
)
11135 /* They cannot use RIP-relative addressing. */
11136 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11138 as_bad (_("`%s' cannot be used here"), operand_string
);
11142 /* bndldx and bndstx ignore their scale factor. */
11143 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11144 && (t
->base_opcode
& ~1) == 0x0f1a
11145 && i
.log2_scale_factor
)
11146 as_warn (_("register scaling is being ignored here"));
11151 /* 16-bit checks. */
11152 if (i
.disp_encoding
== disp_encoding_32bit
)
11156 && (!i
.base_reg
->reg_type
.bitfield
.word
11157 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11159 && (!i
.index_reg
->reg_type
.bitfield
.word
11160 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11162 && i
.base_reg
->reg_num
< 6
11163 && i
.index_reg
->reg_num
>= 6
11164 && i
.log2_scale_factor
== 0))))
11171 /* Handle vector immediates. */
11174 RC_SAE_immediate (const char *imm_start
)
11176 unsigned int match_found
, j
;
11177 const char *pstr
= imm_start
;
11185 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11187 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11191 rc_op
.type
= RC_NamesTable
[j
].type
;
11192 rc_op
.operand
= this_operand
;
11193 i
.rounding
= &rc_op
;
11197 as_bad (_("duplicated `%s'"), imm_start
);
11200 pstr
+= RC_NamesTable
[j
].len
;
11208 if (*pstr
++ != '}')
11210 as_bad (_("Missing '}': '%s'"), imm_start
);
11213 /* RC/SAE immediate string should contain nothing more. */;
11216 as_bad (_("Junk after '}': '%s'"), imm_start
);
11220 exp
= &im_expressions
[i
.imm_operands
++];
11221 i
.op
[this_operand
].imms
= exp
;
11223 exp
->X_op
= O_constant
;
11224 exp
->X_add_number
= 0;
11225 exp
->X_add_symbol
= (symbolS
*) 0;
11226 exp
->X_op_symbol
= (symbolS
*) 0;
11228 i
.types
[this_operand
].bitfield
.imm8
= 1;
11232 /* Only string instructions can have a second memory operand, so
11233 reduce current_templates to just those if it contains any. */
11235 maybe_adjust_templates (void)
11237 const insn_template
*t
;
11239 gas_assert (i
.mem_operands
== 1);
11241 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11242 if (t
->opcode_modifier
.isstring
)
11245 if (t
< current_templates
->end
)
11247 static templates aux_templates
;
11248 bfd_boolean recheck
;
11250 aux_templates
.start
= t
;
11251 for (; t
< current_templates
->end
; ++t
)
11252 if (!t
->opcode_modifier
.isstring
)
11254 aux_templates
.end
= t
;
11256 /* Determine whether to re-check the first memory operand. */
11257 recheck
= (aux_templates
.start
!= current_templates
->start
11258 || t
!= current_templates
->end
);
11260 current_templates
= &aux_templates
;
11264 i
.mem_operands
= 0;
11265 if (i
.memop1_string
!= NULL
11266 && i386_index_check (i
.memop1_string
) == 0)
11268 i
.mem_operands
= 1;
11275 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11279 i386_att_operand (char *operand_string
)
11281 const reg_entry
*r
;
11283 char *op_string
= operand_string
;
11285 if (is_space_char (*op_string
))
11288 /* We check for an absolute prefix (differentiating,
11289 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11290 if (*op_string
== ABSOLUTE_PREFIX
)
11293 if (is_space_char (*op_string
))
11295 i
.jumpabsolute
= TRUE
;
11298 /* Check if operand is a register. */
11299 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11301 i386_operand_type temp
;
11306 /* Check for a segment override by searching for ':' after a
11307 segment register. */
11308 op_string
= end_op
;
11309 if (is_space_char (*op_string
))
11311 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11313 switch (r
->reg_num
)
11316 i
.seg
[i
.mem_operands
] = &es
;
11319 i
.seg
[i
.mem_operands
] = &cs
;
11322 i
.seg
[i
.mem_operands
] = &ss
;
11325 i
.seg
[i
.mem_operands
] = &ds
;
11328 i
.seg
[i
.mem_operands
] = &fs
;
11331 i
.seg
[i
.mem_operands
] = &gs
;
11335 /* Skip the ':' and whitespace. */
11337 if (is_space_char (*op_string
))
11340 if (!is_digit_char (*op_string
)
11341 && !is_identifier_char (*op_string
)
11342 && *op_string
!= '('
11343 && *op_string
!= ABSOLUTE_PREFIX
)
11345 as_bad (_("bad memory operand `%s'"), op_string
);
11348 /* Handle case of %es:*foo. */
11349 if (*op_string
== ABSOLUTE_PREFIX
)
11352 if (is_space_char (*op_string
))
11354 i
.jumpabsolute
= TRUE
;
11356 goto do_memory_reference
;
11359 /* Handle vector operations. */
11360 if (*op_string
== '{')
11362 op_string
= check_VecOperations (op_string
, NULL
);
11363 if (op_string
== NULL
)
11369 as_bad (_("junk `%s' after register"), op_string
);
11372 temp
= r
->reg_type
;
11373 temp
.bitfield
.baseindex
= 0;
11374 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11376 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11377 i
.op
[this_operand
].regs
= r
;
11380 else if (*op_string
== REGISTER_PREFIX
)
11382 as_bad (_("bad register name `%s'"), op_string
);
11385 else if (*op_string
== IMMEDIATE_PREFIX
)
11388 if (i
.jumpabsolute
)
11390 as_bad (_("immediate operand illegal with absolute jump"));
11393 if (!i386_immediate (op_string
))
11396 else if (RC_SAE_immediate (operand_string
))
11398 /* If it is a RC or SAE immediate, do nothing. */
11401 else if (is_digit_char (*op_string
)
11402 || is_identifier_char (*op_string
)
11403 || *op_string
== '"'
11404 || *op_string
== '(')
11406 /* This is a memory reference of some sort. */
11409 /* Start and end of displacement string expression (if found). */
11410 char *displacement_string_start
;
11411 char *displacement_string_end
;
11414 do_memory_reference
:
11415 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11417 if ((i
.mem_operands
== 1
11418 && !current_templates
->start
->opcode_modifier
.isstring
)
11419 || i
.mem_operands
== 2)
11421 as_bad (_("too many memory references for `%s'"),
11422 current_templates
->start
->name
);
11426 /* Check for base index form. We detect the base index form by
11427 looking for an ')' at the end of the operand, searching
11428 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11430 base_string
= op_string
+ strlen (op_string
);
11432 /* Handle vector operations. */
11433 vop_start
= strchr (op_string
, '{');
11434 if (vop_start
&& vop_start
< base_string
)
11436 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11438 base_string
= vop_start
;
11442 if (is_space_char (*base_string
))
11445 /* If we only have a displacement, set-up for it to be parsed later. */
11446 displacement_string_start
= op_string
;
11447 displacement_string_end
= base_string
+ 1;
11449 if (*base_string
== ')')
11452 unsigned int parens_balanced
= 1;
11453 /* We've already checked that the number of left & right ()'s are
11454 equal, so this loop will not be infinite. */
11458 if (*base_string
== ')')
11460 if (*base_string
== '(')
11463 while (parens_balanced
);
11465 temp_string
= base_string
;
11467 /* Skip past '(' and whitespace. */
11469 if (is_space_char (*base_string
))
11472 if (*base_string
== ','
11473 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11476 displacement_string_end
= temp_string
;
11478 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11482 if (i
.base_reg
== &bad_reg
)
11484 base_string
= end_op
;
11485 if (is_space_char (*base_string
))
11489 /* There may be an index reg or scale factor here. */
11490 if (*base_string
== ',')
11493 if (is_space_char (*base_string
))
11496 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11499 if (i
.index_reg
== &bad_reg
)
11501 base_string
= end_op
;
11502 if (is_space_char (*base_string
))
11504 if (*base_string
== ',')
11507 if (is_space_char (*base_string
))
11510 else if (*base_string
!= ')')
11512 as_bad (_("expecting `,' or `)' "
11513 "after index register in `%s'"),
11518 else if (*base_string
== REGISTER_PREFIX
)
11520 end_op
= strchr (base_string
, ',');
11523 as_bad (_("bad register name `%s'"), base_string
);
11527 /* Check for scale factor. */
11528 if (*base_string
!= ')')
11530 char *end_scale
= i386_scale (base_string
);
11535 base_string
= end_scale
;
11536 if (is_space_char (*base_string
))
11538 if (*base_string
!= ')')
11540 as_bad (_("expecting `)' "
11541 "after scale factor in `%s'"),
11546 else if (!i
.index_reg
)
11548 as_bad (_("expecting index register or scale factor "
11549 "after `,'; got '%c'"),
11554 else if (*base_string
!= ')')
11556 as_bad (_("expecting `,' or `)' "
11557 "after base register in `%s'"),
11562 else if (*base_string
== REGISTER_PREFIX
)
11564 end_op
= strchr (base_string
, ',');
11567 as_bad (_("bad register name `%s'"), base_string
);
11572 /* If there's an expression beginning the operand, parse it,
11573 assuming displacement_string_start and
11574 displacement_string_end are meaningful. */
11575 if (displacement_string_start
!= displacement_string_end
)
11577 if (!i386_displacement (displacement_string_start
,
11578 displacement_string_end
))
11582 /* Special case for (%dx) while doing input/output op. */
11584 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11585 && i
.base_reg
->reg_type
.bitfield
.word
11586 && i
.index_reg
== 0
11587 && i
.log2_scale_factor
== 0
11588 && i
.seg
[i
.mem_operands
] == 0
11589 && !operand_type_check (i
.types
[this_operand
], disp
))
11591 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11595 if (i386_index_check (operand_string
) == 0)
11597 i
.flags
[this_operand
] |= Operand_Mem
;
11598 if (i
.mem_operands
== 0)
11599 i
.memop1_string
= xstrdup (operand_string
);
11604 /* It's not a memory operand; argh! */
11605 as_bad (_("invalid char %s beginning operand %d `%s'"),
11606 output_invalid (*op_string
),
11611 return 1; /* Normal return. */
11614 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11615 that an rs_machine_dependent frag may reach. */
11618 i386_frag_max_var (fragS
*frag
)
11620 /* The only relaxable frags are for jumps.
11621 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11622 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11623 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11628 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11630 /* STT_GNU_IFUNC symbol must go through PLT. */
11631 if ((symbol_get_bfdsym (fr_symbol
)->flags
11632 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11635 if (!S_IS_EXTERNAL (fr_symbol
))
11636 /* Symbol may be weak or local. */
11637 return !S_IS_WEAK (fr_symbol
);
11639 /* Global symbols with non-default visibility can't be preempted. */
11640 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11643 if (fr_var
!= NO_RELOC
)
11644 switch ((enum bfd_reloc_code_real
) fr_var
)
11646 case BFD_RELOC_386_PLT32
:
11647 case BFD_RELOC_X86_64_PLT32
:
11648 /* Symbol with PLT relocation may be preempted. */
11654 /* Global symbols with default visibility in a shared library may be
11655 preempted by another definition. */
11660 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11661 Note also work for Skylake and Cascadelake.
11662 ---------------------------------------------------------------------
11663 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11664 | ------ | ----------- | ------- | -------- |
11666 | Jno | N | N | Y |
11667 | Jc/Jb | Y | N | Y |
11668 | Jae/Jnb | Y | N | Y |
11669 | Je/Jz | Y | Y | Y |
11670 | Jne/Jnz | Y | Y | Y |
11671 | Jna/Jbe | Y | N | Y |
11672 | Ja/Jnbe | Y | N | Y |
11674 | Jns | N | N | Y |
11675 | Jp/Jpe | N | N | Y |
11676 | Jnp/Jpo | N | N | Y |
11677 | Jl/Jnge | Y | Y | Y |
11678 | Jge/Jnl | Y | Y | Y |
11679 | Jle/Jng | Y | Y | Y |
11680 | Jg/Jnle | Y | Y | Y |
11681 --------------------------------------------------------------------- */
11683 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11685 if (mf_cmp
== mf_cmp_alu_cmp
)
11686 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11687 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11688 if (mf_cmp
== mf_cmp_incdec
)
11689 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11690 || mf_jcc
== mf_jcc_jle
);
11691 if (mf_cmp
== mf_cmp_test_and
)
11696 /* Return the next non-empty frag. */
11699 i386_next_non_empty_frag (fragS
*fragP
)
11701 /* There may be a frag with a ".fill 0" when there is no room in
11702 the current frag for frag_grow in output_insn. */
11703 for (fragP
= fragP
->fr_next
;
11705 && fragP
->fr_type
== rs_fill
11706 && fragP
->fr_fix
== 0);
11707 fragP
= fragP
->fr_next
)
11712 /* Return the next jcc frag after BRANCH_PADDING. */
11715 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11717 fragS
*branch_fragP
;
11721 if (pad_fragP
->fr_type
== rs_machine_dependent
11722 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11723 == BRANCH_PADDING
))
11725 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11726 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11728 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11729 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11730 pad_fragP
->tc_frag_data
.mf_type
))
11731 return branch_fragP
;
11737 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11740 i386_classify_machine_dependent_frag (fragS
*fragP
)
11744 fragS
*branch_fragP
;
11746 unsigned int max_prefix_length
;
11748 if (fragP
->tc_frag_data
.classified
)
11751 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11752 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11753 for (next_fragP
= fragP
;
11754 next_fragP
!= NULL
;
11755 next_fragP
= next_fragP
->fr_next
)
11757 next_fragP
->tc_frag_data
.classified
= 1;
11758 if (next_fragP
->fr_type
== rs_machine_dependent
)
11759 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11761 case BRANCH_PADDING
:
11762 /* The BRANCH_PADDING frag must be followed by a branch
11764 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11765 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11767 case FUSED_JCC_PADDING
:
11768 /* Check if this is a fused jcc:
11770 CMP like instruction
11774 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11775 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11776 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11779 /* The BRANCH_PADDING frag is merged with the
11780 FUSED_JCC_PADDING frag. */
11781 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11782 /* CMP like instruction size. */
11783 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11784 frag_wane (pad_fragP
);
11785 /* Skip to branch_fragP. */
11786 next_fragP
= branch_fragP
;
11788 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11790 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11792 next_fragP
->fr_subtype
11793 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11794 next_fragP
->tc_frag_data
.max_bytes
11795 = next_fragP
->tc_frag_data
.max_prefix_length
;
11796 /* This will be updated in the BRANCH_PREFIX scan. */
11797 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11800 frag_wane (next_fragP
);
11805 /* Stop if there is no BRANCH_PREFIX. */
11806 if (!align_branch_prefix_size
)
11809 /* Scan for BRANCH_PREFIX. */
11810 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11812 if (fragP
->fr_type
!= rs_machine_dependent
11813 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11817 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11818 COND_JUMP_PREFIX. */
11819 max_prefix_length
= 0;
11820 for (next_fragP
= fragP
;
11821 next_fragP
!= NULL
;
11822 next_fragP
= next_fragP
->fr_next
)
11824 if (next_fragP
->fr_type
== rs_fill
)
11825 /* Skip rs_fill frags. */
11827 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11828 /* Stop for all other frags. */
11831 /* rs_machine_dependent frags. */
11832 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11835 /* Count BRANCH_PREFIX frags. */
11836 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11838 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11839 frag_wane (next_fragP
);
11843 += next_fragP
->tc_frag_data
.max_bytes
;
11845 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11847 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11848 == FUSED_JCC_PADDING
))
11850 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11851 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11855 /* Stop for other rs_machine_dependent frags. */
11859 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11861 /* Skip to the next frag. */
11862 fragP
= next_fragP
;
11866 /* Compute padding size for
11869 CMP like instruction
11871 COND_JUMP/UNCOND_JUMP
11876 COND_JUMP/UNCOND_JUMP
11880 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11882 unsigned int offset
, size
, padding_size
;
11883 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11885 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11887 address
= fragP
->fr_address
;
11888 address
+= fragP
->fr_fix
;
11890 /* CMP like instrunction size. */
11891 size
= fragP
->tc_frag_data
.cmp_size
;
11893 /* The base size of the branch frag. */
11894 size
+= branch_fragP
->fr_fix
;
11896 /* Add opcode and displacement bytes for the rs_machine_dependent
11898 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11899 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11901 /* Check if branch is within boundary and doesn't end at the last
11903 offset
= address
& ((1U << align_branch_power
) - 1);
11904 if ((offset
+ size
) >= (1U << align_branch_power
))
11905 /* Padding needed to avoid crossing boundary. */
11906 padding_size
= (1U << align_branch_power
) - offset
;
11908 /* No padding needed. */
11911 /* The return value may be saved in tc_frag_data.length which is
11913 if (!fits_in_unsigned_byte (padding_size
))
11916 return padding_size
;
11919 /* i386_generic_table_relax_frag()
11921 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11922 grow/shrink padding to align branch frags. Hand others to
11926 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11928 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11929 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11931 long padding_size
= i386_branch_padding_size (fragP
, 0);
11932 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11934 /* When the BRANCH_PREFIX frag is used, the computed address
11935 must match the actual address and there should be no padding. */
11936 if (fragP
->tc_frag_data
.padding_address
11937 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11941 /* Update the padding size. */
11943 fragP
->tc_frag_data
.length
= padding_size
;
11947 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11949 fragS
*padding_fragP
, *next_fragP
;
11950 long padding_size
, left_size
, last_size
;
11952 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11953 if (!padding_fragP
)
11954 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11955 return (fragP
->tc_frag_data
.length
11956 - fragP
->tc_frag_data
.last_length
);
11958 /* Compute the relative address of the padding frag in the very
11959 first time where the BRANCH_PREFIX frag sizes are zero. */
11960 if (!fragP
->tc_frag_data
.padding_address
)
11961 fragP
->tc_frag_data
.padding_address
11962 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11964 /* First update the last length from the previous interation. */
11965 left_size
= fragP
->tc_frag_data
.prefix_length
;
11966 for (next_fragP
= fragP
;
11967 next_fragP
!= padding_fragP
;
11968 next_fragP
= next_fragP
->fr_next
)
11969 if (next_fragP
->fr_type
== rs_machine_dependent
11970 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11975 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11979 if (max
> left_size
)
11984 next_fragP
->tc_frag_data
.last_length
= size
;
11988 next_fragP
->tc_frag_data
.last_length
= 0;
11991 /* Check the padding size for the padding frag. */
11992 padding_size
= i386_branch_padding_size
11993 (padding_fragP
, (fragP
->fr_address
11994 + fragP
->tc_frag_data
.padding_address
));
11996 last_size
= fragP
->tc_frag_data
.prefix_length
;
11997 /* Check if there is change from the last interation. */
11998 if (padding_size
== last_size
)
12000 /* Update the expected address of the padding frag. */
12001 padding_fragP
->tc_frag_data
.padding_address
12002 = (fragP
->fr_address
+ padding_size
12003 + fragP
->tc_frag_data
.padding_address
);
12007 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12009 /* No padding if there is no sufficient room. Clear the
12010 expected address of the padding frag. */
12011 padding_fragP
->tc_frag_data
.padding_address
= 0;
12015 /* Store the expected address of the padding frag. */
12016 padding_fragP
->tc_frag_data
.padding_address
12017 = (fragP
->fr_address
+ padding_size
12018 + fragP
->tc_frag_data
.padding_address
);
12020 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12022 /* Update the length for the current interation. */
12023 left_size
= padding_size
;
12024 for (next_fragP
= fragP
;
12025 next_fragP
!= padding_fragP
;
12026 next_fragP
= next_fragP
->fr_next
)
12027 if (next_fragP
->fr_type
== rs_machine_dependent
12028 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12033 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12037 if (max
> left_size
)
12042 next_fragP
->tc_frag_data
.length
= size
;
12046 next_fragP
->tc_frag_data
.length
= 0;
12049 return (fragP
->tc_frag_data
.length
12050 - fragP
->tc_frag_data
.last_length
);
12052 return relax_frag (segment
, fragP
, stretch
);
12055 /* md_estimate_size_before_relax()
12057 Called just before relax() for rs_machine_dependent frags. The x86
12058 assembler uses these frags to handle variable size jump
12061 Any symbol that is now undefined will not become defined.
12062 Return the correct fr_subtype in the frag.
12063 Return the initial "guess for variable size of frag" to caller.
12064 The guess is actually the growth beyond the fixed part. Whatever
12065 we do to grow the fixed or variable part contributes to our
12069 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12071 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12072 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12073 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12075 i386_classify_machine_dependent_frag (fragP
);
12076 return fragP
->tc_frag_data
.length
;
12079 /* We've already got fragP->fr_subtype right; all we have to do is
12080 check for un-relaxable symbols. On an ELF system, we can't relax
12081 an externally visible symbol, because it may be overridden by a
12083 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12086 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12089 #if defined (OBJ_COFF) && defined (TE_PE)
12090 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12091 && S_IS_WEAK (fragP
->fr_symbol
))
12095 /* Symbol is undefined in this segment, or we need to keep a
12096 reloc so that weak symbols can be overridden. */
12097 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12098 enum bfd_reloc_code_real reloc_type
;
12099 unsigned char *opcode
;
12102 if (fragP
->fr_var
!= NO_RELOC
)
12103 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12104 else if (size
== 2)
12105 reloc_type
= BFD_RELOC_16_PCREL
;
12106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12107 else if (need_plt32_p (fragP
->fr_symbol
))
12108 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12111 reloc_type
= BFD_RELOC_32_PCREL
;
12113 old_fr_fix
= fragP
->fr_fix
;
12114 opcode
= (unsigned char *) fragP
->fr_opcode
;
12116 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12119 /* Make jmp (0xeb) a (d)word displacement jump. */
12121 fragP
->fr_fix
+= size
;
12122 fix_new (fragP
, old_fr_fix
, size
,
12124 fragP
->fr_offset
, 1,
12130 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12132 /* Negate the condition, and branch past an
12133 unconditional jump. */
12136 /* Insert an unconditional jump. */
12138 /* We added two extra opcode bytes, and have a two byte
12140 fragP
->fr_fix
+= 2 + 2;
12141 fix_new (fragP
, old_fr_fix
+ 2, 2,
12143 fragP
->fr_offset
, 1,
12147 /* Fall through. */
12150 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12154 fragP
->fr_fix
+= 1;
12155 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12157 fragP
->fr_offset
, 1,
12158 BFD_RELOC_8_PCREL
);
12159 fixP
->fx_signed
= 1;
12163 /* This changes the byte-displacement jump 0x7N
12164 to the (d)word-displacement jump 0x0f,0x8N. */
12165 opcode
[1] = opcode
[0] + 0x10;
12166 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12167 /* We've added an opcode byte. */
12168 fragP
->fr_fix
+= 1 + size
;
12169 fix_new (fragP
, old_fr_fix
+ 1, size
,
12171 fragP
->fr_offset
, 1,
12176 BAD_CASE (fragP
->fr_subtype
);
12180 return fragP
->fr_fix
- old_fr_fix
;
12183 /* Guess size depending on current relax state. Initially the relax
12184 state will correspond to a short jump and we return 1, because
12185 the variable part of the frag (the branch offset) is one byte
12186 long. However, we can relax a section more than once and in that
12187 case we must either set fr_subtype back to the unrelaxed state,
12188 or return the value for the appropriate branch. */
12189 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12192 /* Called after relax() is finished.
12194 In: Address of frag.
12195 fr_type == rs_machine_dependent.
12196 fr_subtype is what the address relaxed to.
12198 Out: Any fixSs and constants are set up.
12199 Caller will turn frag into a ".space 0". */
12202 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12205 unsigned char *opcode
;
12206 unsigned char *where_to_put_displacement
= NULL
;
12207 offsetT target_address
;
12208 offsetT opcode_address
;
12209 unsigned int extension
= 0;
12210 offsetT displacement_from_opcode_start
;
12212 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12213 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12214 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12216 /* Generate nop padding. */
12217 unsigned int size
= fragP
->tc_frag_data
.length
;
12220 if (size
> fragP
->tc_frag_data
.max_bytes
)
12226 const char *branch
= "branch";
12227 const char *prefix
= "";
12228 fragS
*padding_fragP
;
12229 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12232 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12233 switch (fragP
->tc_frag_data
.default_prefix
)
12238 case CS_PREFIX_OPCODE
:
12241 case DS_PREFIX_OPCODE
:
12244 case ES_PREFIX_OPCODE
:
12247 case FS_PREFIX_OPCODE
:
12250 case GS_PREFIX_OPCODE
:
12253 case SS_PREFIX_OPCODE
:
12258 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12259 "%s within %d-byte boundary\n");
12261 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12262 "align %s within %d-byte boundary\n");
12266 padding_fragP
= fragP
;
12267 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12268 "%s within %d-byte boundary\n");
12272 switch (padding_fragP
->tc_frag_data
.branch_type
)
12274 case align_branch_jcc
:
12277 case align_branch_fused
:
12278 branch
= "fused jcc";
12280 case align_branch_jmp
:
12283 case align_branch_call
:
12286 case align_branch_indirect
:
12287 branch
= "indiret branch";
12289 case align_branch_ret
:
12296 fprintf (stdout
, msg
,
12297 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12298 (long long) fragP
->fr_address
, branch
,
12299 1 << align_branch_power
);
12301 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12302 memset (fragP
->fr_opcode
,
12303 fragP
->tc_frag_data
.default_prefix
, size
);
12305 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12307 fragP
->fr_fix
+= size
;
12312 opcode
= (unsigned char *) fragP
->fr_opcode
;
12314 /* Address we want to reach in file space. */
12315 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12317 /* Address opcode resides at in file space. */
12318 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12320 /* Displacement from opcode start to fill into instruction. */
12321 displacement_from_opcode_start
= target_address
- opcode_address
;
12323 if ((fragP
->fr_subtype
& BIG
) == 0)
12325 /* Don't have to change opcode. */
12326 extension
= 1; /* 1 opcode + 1 displacement */
12327 where_to_put_displacement
= &opcode
[1];
12331 if (no_cond_jump_promotion
12332 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12333 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12334 _("long jump required"));
12336 switch (fragP
->fr_subtype
)
12338 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12339 extension
= 4; /* 1 opcode + 4 displacement */
12341 where_to_put_displacement
= &opcode
[1];
12344 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12345 extension
= 2; /* 1 opcode + 2 displacement */
12347 where_to_put_displacement
= &opcode
[1];
12350 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12351 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12352 extension
= 5; /* 2 opcode + 4 displacement */
12353 opcode
[1] = opcode
[0] + 0x10;
12354 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12355 where_to_put_displacement
= &opcode
[2];
12358 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12359 extension
= 3; /* 2 opcode + 2 displacement */
12360 opcode
[1] = opcode
[0] + 0x10;
12361 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12362 where_to_put_displacement
= &opcode
[2];
12365 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12370 where_to_put_displacement
= &opcode
[3];
12374 BAD_CASE (fragP
->fr_subtype
);
12379 /* If size if less then four we are sure that the operand fits,
12380 but if it's 4, then it could be that the displacement is larger
12382 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12384 && ((addressT
) (displacement_from_opcode_start
- extension
12385 + ((addressT
) 1 << 31))
12386 > (((addressT
) 2 << 31) - 1)))
12388 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12389 _("jump target out of range"));
12390 /* Make us emit 0. */
12391 displacement_from_opcode_start
= extension
;
12393 /* Now put displacement after opcode. */
12394 md_number_to_chars ((char *) where_to_put_displacement
,
12395 (valueT
) (displacement_from_opcode_start
- extension
),
12396 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12397 fragP
->fr_fix
+= extension
;
12400 /* Apply a fixup (fixP) to segment data, once it has been determined
12401 by our caller that we have all the info we need to fix it up.
12403 Parameter valP is the pointer to the value of the bits.
12405 On the 386, immediates, displacements, and data pointers are all in
12406 the same (little-endian) format, so we don't need to care about which
12407 we are handling. */
12410 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12412 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12413 valueT value
= *valP
;
12415 #if !defined (TE_Mach)
12416 if (fixP
->fx_pcrel
)
12418 switch (fixP
->fx_r_type
)
12424 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12427 case BFD_RELOC_X86_64_32S
:
12428 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12431 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12434 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12439 if (fixP
->fx_addsy
!= NULL
12440 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12441 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12442 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12443 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12444 && !use_rela_relocations
)
12446 /* This is a hack. There should be a better way to handle this.
12447 This covers for the fact that bfd_install_relocation will
12448 subtract the current location (for partial_inplace, PC relative
12449 relocations); see more below. */
12453 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12456 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12461 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12463 if ((sym_seg
== seg
12464 || (symbol_section_p (fixP
->fx_addsy
)
12465 && sym_seg
!= absolute_section
))
12466 && !generic_force_reloc (fixP
))
12468 /* Yes, we add the values in twice. This is because
12469 bfd_install_relocation subtracts them out again. I think
12470 bfd_install_relocation is broken, but I don't dare change
12472 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12476 #if defined (OBJ_COFF) && defined (TE_PE)
12477 /* For some reason, the PE format does not store a
12478 section address offset for a PC relative symbol. */
12479 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12480 || S_IS_WEAK (fixP
->fx_addsy
))
12481 value
+= md_pcrel_from (fixP
);
12484 #if defined (OBJ_COFF) && defined (TE_PE)
12485 if (fixP
->fx_addsy
!= NULL
12486 && S_IS_WEAK (fixP
->fx_addsy
)
12487 /* PR 16858: Do not modify weak function references. */
12488 && ! fixP
->fx_pcrel
)
12490 #if !defined (TE_PEP)
12491 /* For x86 PE weak function symbols are neither PC-relative
12492 nor do they set S_IS_FUNCTION. So the only reliable way
12493 to detect them is to check the flags of their containing
12495 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12496 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12500 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12504 /* Fix a few things - the dynamic linker expects certain values here,
12505 and we must not disappoint it. */
12506 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12507 if (IS_ELF
&& fixP
->fx_addsy
)
12508 switch (fixP
->fx_r_type
)
12510 case BFD_RELOC_386_PLT32
:
12511 case BFD_RELOC_X86_64_PLT32
:
12512 /* Make the jump instruction point to the address of the operand.
12513 At runtime we merely add the offset to the actual PLT entry.
12514 NB: Subtract the offset size only for jump instructions. */
12515 if (fixP
->fx_pcrel
)
12519 case BFD_RELOC_386_TLS_GD
:
12520 case BFD_RELOC_386_TLS_LDM
:
12521 case BFD_RELOC_386_TLS_IE_32
:
12522 case BFD_RELOC_386_TLS_IE
:
12523 case BFD_RELOC_386_TLS_GOTIE
:
12524 case BFD_RELOC_386_TLS_GOTDESC
:
12525 case BFD_RELOC_X86_64_TLSGD
:
12526 case BFD_RELOC_X86_64_TLSLD
:
12527 case BFD_RELOC_X86_64_GOTTPOFF
:
12528 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12529 value
= 0; /* Fully resolved at runtime. No addend. */
12531 case BFD_RELOC_386_TLS_LE
:
12532 case BFD_RELOC_386_TLS_LDO_32
:
12533 case BFD_RELOC_386_TLS_LE_32
:
12534 case BFD_RELOC_X86_64_DTPOFF32
:
12535 case BFD_RELOC_X86_64_DTPOFF64
:
12536 case BFD_RELOC_X86_64_TPOFF32
:
12537 case BFD_RELOC_X86_64_TPOFF64
:
12538 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12541 case BFD_RELOC_386_TLS_DESC_CALL
:
12542 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12543 value
= 0; /* Fully resolved at runtime. No addend. */
12544 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12548 case BFD_RELOC_VTABLE_INHERIT
:
12549 case BFD_RELOC_VTABLE_ENTRY
:
12556 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12558 #endif /* !defined (TE_Mach) */
12560 /* Are we finished with this relocation now? */
12561 if (fixP
->fx_addsy
== NULL
)
12563 #if defined (OBJ_COFF) && defined (TE_PE)
12564 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12567 /* Remember value for tc_gen_reloc. */
12568 fixP
->fx_addnumber
= value
;
12569 /* Clear out the frag for now. */
12573 else if (use_rela_relocations
)
12575 fixP
->fx_no_overflow
= 1;
12576 /* Remember value for tc_gen_reloc. */
12577 fixP
->fx_addnumber
= value
;
12581 md_number_to_chars (p
, value
, fixP
->fx_size
);
12585 md_atof (int type
, char *litP
, int *sizeP
)
12587 /* This outputs the LITTLENUMs in REVERSE order;
12588 in accord with the bigendian 386. */
12589 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12592 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12595 output_invalid (int c
)
12598 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12601 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12602 "(0x%x)", (unsigned char) c
);
12603 return output_invalid_buf
;
12606 /* Verify that @r can be used in the current context. */
12608 static bfd_boolean
check_register (const reg_entry
*r
)
12610 if (allow_pseudo_reg
)
12613 if (operand_type_all_zero (&r
->reg_type
))
12616 if ((r
->reg_type
.bitfield
.dword
12617 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12618 || r
->reg_type
.bitfield
.class == RegCR
12619 || r
->reg_type
.bitfield
.class == RegDR
)
12620 && !cpu_arch_flags
.bitfield
.cpui386
)
12623 if (r
->reg_type
.bitfield
.class == RegTR
12624 && (flag_code
== CODE_64BIT
12625 || !cpu_arch_flags
.bitfield
.cpui386
12626 || cpu_arch_isa_flags
.bitfield
.cpui586
12627 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12630 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12633 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12635 if (r
->reg_type
.bitfield
.zmmword
12636 || r
->reg_type
.bitfield
.class == RegMask
)
12639 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12641 if (r
->reg_type
.bitfield
.ymmword
)
12644 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12649 if (r
->reg_type
.bitfield
.tmmword
12650 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12651 || flag_code
!= CODE_64BIT
))
12654 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12657 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12658 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12661 /* Upper 16 vector registers are only available with VREX in 64bit
12662 mode, and require EVEX encoding. */
12663 if (r
->reg_flags
& RegVRex
)
12665 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12666 || flag_code
!= CODE_64BIT
)
12669 if (i
.vec_encoding
== vex_encoding_default
)
12670 i
.vec_encoding
= vex_encoding_evex
;
12671 else if (i
.vec_encoding
!= vex_encoding_evex
)
12672 i
.vec_encoding
= vex_encoding_error
;
12675 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12676 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12677 && flag_code
!= CODE_64BIT
)
12680 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12687 /* REG_STRING starts *before* REGISTER_PREFIX. */
12689 static const reg_entry
*
12690 parse_real_register (char *reg_string
, char **end_op
)
12692 char *s
= reg_string
;
12694 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12695 const reg_entry
*r
;
12697 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12698 if (*s
== REGISTER_PREFIX
)
12701 if (is_space_char (*s
))
12704 p
= reg_name_given
;
12705 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12707 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12708 return (const reg_entry
*) NULL
;
12712 /* For naked regs, make sure that we are not dealing with an identifier.
12713 This prevents confusing an identifier like `eax_var' with register
12715 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12716 return (const reg_entry
*) NULL
;
12720 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12722 /* Handle floating point regs, allowing spaces in the (i) part. */
12723 if (r
== i386_regtab
/* %st is first entry of table */)
12725 if (!cpu_arch_flags
.bitfield
.cpu8087
12726 && !cpu_arch_flags
.bitfield
.cpu287
12727 && !cpu_arch_flags
.bitfield
.cpu387
12728 && !allow_pseudo_reg
)
12729 return (const reg_entry
*) NULL
;
12731 if (is_space_char (*s
))
12736 if (is_space_char (*s
))
12738 if (*s
>= '0' && *s
<= '7')
12740 int fpr
= *s
- '0';
12742 if (is_space_char (*s
))
12747 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12752 /* We have "%st(" then garbage. */
12753 return (const reg_entry
*) NULL
;
12757 return r
&& check_register (r
) ? r
: NULL
;
12760 /* REG_STRING starts *before* REGISTER_PREFIX. */
12762 static const reg_entry
*
12763 parse_register (char *reg_string
, char **end_op
)
12765 const reg_entry
*r
;
12767 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12768 r
= parse_real_register (reg_string
, end_op
);
12773 char *save
= input_line_pointer
;
12777 input_line_pointer
= reg_string
;
12778 c
= get_symbol_name (®_string
);
12779 symbolP
= symbol_find (reg_string
);
12780 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12782 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12784 know (e
->X_op
== O_register
);
12785 know (e
->X_add_number
>= 0
12786 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12787 r
= i386_regtab
+ e
->X_add_number
;
12788 if (!check_register (r
))
12790 as_bad (_("register '%s%s' cannot be used here"),
12791 register_prefix
, r
->reg_name
);
12794 *end_op
= input_line_pointer
;
12796 *input_line_pointer
= c
;
12797 input_line_pointer
= save
;
12803 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12805 const reg_entry
*r
;
12806 char *end
= input_line_pointer
;
12809 r
= parse_register (name
, &input_line_pointer
);
12810 if (r
&& end
<= input_line_pointer
)
12812 *nextcharP
= *input_line_pointer
;
12813 *input_line_pointer
= 0;
12816 e
->X_op
= O_register
;
12817 e
->X_add_number
= r
- i386_regtab
;
12820 e
->X_op
= O_illegal
;
12823 input_line_pointer
= end
;
12825 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12829 md_operand (expressionS
*e
)
12832 const reg_entry
*r
;
12834 switch (*input_line_pointer
)
12836 case REGISTER_PREFIX
:
12837 r
= parse_real_register (input_line_pointer
, &end
);
12840 e
->X_op
= O_register
;
12841 e
->X_add_number
= r
- i386_regtab
;
12842 input_line_pointer
= end
;
12847 gas_assert (intel_syntax
);
12848 end
= input_line_pointer
++;
12850 if (*input_line_pointer
== ']')
12852 ++input_line_pointer
;
12853 e
->X_op_symbol
= make_expr_symbol (e
);
12854 e
->X_add_symbol
= NULL
;
12855 e
->X_add_number
= 0;
12860 e
->X_op
= O_absent
;
12861 input_line_pointer
= end
;
12868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12869 const char *md_shortopts
= "kVQ:sqnO::";
12871 const char *md_shortopts
= "qnO::";
12874 #define OPTION_32 (OPTION_MD_BASE + 0)
12875 #define OPTION_64 (OPTION_MD_BASE + 1)
12876 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12877 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12878 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12879 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12880 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12881 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12882 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12883 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12884 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12885 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12886 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12887 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12888 #define OPTION_X32 (OPTION_MD_BASE + 14)
12889 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12890 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12891 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12892 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12893 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12894 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12895 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12896 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12897 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12898 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12899 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12900 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12901 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12902 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12903 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12904 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12905 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12906 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12907 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12909 struct option md_longopts
[] =
12911 {"32", no_argument
, NULL
, OPTION_32
},
12912 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12913 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12914 {"64", no_argument
, NULL
, OPTION_64
},
12916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12917 {"x32", no_argument
, NULL
, OPTION_X32
},
12918 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12919 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12921 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12922 {"march", required_argument
, NULL
, OPTION_MARCH
},
12923 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12924 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12925 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12926 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12927 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12928 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12929 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12930 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12931 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12932 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12933 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12934 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12935 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12936 # if defined (TE_PE) || defined (TE_PEP)
12937 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12939 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12940 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12941 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12942 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12943 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12944 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12945 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12946 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12947 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12948 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12949 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12950 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12951 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12952 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12953 {NULL
, no_argument
, NULL
, 0}
12955 size_t md_longopts_size
= sizeof (md_longopts
);
12958 md_parse_option (int c
, const char *arg
)
12961 char *arch
, *next
, *saved
, *type
;
12966 optimize_align_code
= 0;
12970 quiet_warnings
= 1;
12973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12974 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12975 should be emitted or not. FIXME: Not implemented. */
12977 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12981 /* -V: SVR4 argument to print version ID. */
12983 print_version_id ();
12986 /* -k: Ignore for FreeBSD compatibility. */
12991 /* -s: On i386 Solaris, this tells the native assembler to use
12992 .stab instead of .stab.excl. We always use .stab anyhow. */
12995 case OPTION_MSHARED
:
12999 case OPTION_X86_USED_NOTE
:
13000 if (strcasecmp (arg
, "yes") == 0)
13002 else if (strcasecmp (arg
, "no") == 0)
13005 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13010 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13011 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13014 const char **list
, **l
;
13016 list
= bfd_target_list ();
13017 for (l
= list
; *l
!= NULL
; l
++)
13018 if (startswith (*l
, "elf64-x86-64")
13019 || strcmp (*l
, "coff-x86-64") == 0
13020 || strcmp (*l
, "pe-x86-64") == 0
13021 || strcmp (*l
, "pei-x86-64") == 0
13022 || strcmp (*l
, "mach-o-x86-64") == 0)
13024 default_arch
= "x86_64";
13028 as_fatal (_("no compiled in support for x86_64"));
13034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13038 const char **list
, **l
;
13040 list
= bfd_target_list ();
13041 for (l
= list
; *l
!= NULL
; l
++)
13042 if (startswith (*l
, "elf32-x86-64"))
13044 default_arch
= "x86_64:32";
13048 as_fatal (_("no compiled in support for 32bit x86_64"));
13052 as_fatal (_("32bit x86_64 is only supported for ELF"));
13057 default_arch
= "i386";
13060 case OPTION_DIVIDE
:
13061 #ifdef SVR4_COMMENT_CHARS
13066 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13068 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13072 i386_comment_chars
= n
;
13078 saved
= xstrdup (arg
);
13080 /* Allow -march=+nosse. */
13086 as_fatal (_("invalid -march= option: `%s'"), arg
);
13087 next
= strchr (arch
, '+');
13090 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13092 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13095 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13098 cpu_arch_name
= cpu_arch
[j
].name
;
13099 cpu_sub_arch_name
= NULL
;
13100 cpu_arch_flags
= cpu_arch
[j
].flags
;
13101 cpu_arch_isa
= cpu_arch
[j
].type
;
13102 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13103 if (!cpu_arch_tune_set
)
13105 cpu_arch_tune
= cpu_arch_isa
;
13106 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13110 else if (*cpu_arch
[j
].name
== '.'
13111 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13113 /* ISA extension. */
13114 i386_cpu_flags flags
;
13116 flags
= cpu_flags_or (cpu_arch_flags
,
13117 cpu_arch
[j
].flags
);
13119 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13121 if (cpu_sub_arch_name
)
13123 char *name
= cpu_sub_arch_name
;
13124 cpu_sub_arch_name
= concat (name
,
13126 (const char *) NULL
);
13130 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13131 cpu_arch_flags
= flags
;
13132 cpu_arch_isa_flags
= flags
;
13136 = cpu_flags_or (cpu_arch_isa_flags
,
13137 cpu_arch
[j
].flags
);
13142 if (j
>= ARRAY_SIZE (cpu_arch
))
13144 /* Disable an ISA extension. */
13145 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13146 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13148 i386_cpu_flags flags
;
13150 flags
= cpu_flags_and_not (cpu_arch_flags
,
13151 cpu_noarch
[j
].flags
);
13152 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13154 if (cpu_sub_arch_name
)
13156 char *name
= cpu_sub_arch_name
;
13157 cpu_sub_arch_name
= concat (arch
,
13158 (const char *) NULL
);
13162 cpu_sub_arch_name
= xstrdup (arch
);
13163 cpu_arch_flags
= flags
;
13164 cpu_arch_isa_flags
= flags
;
13169 if (j
>= ARRAY_SIZE (cpu_noarch
))
13170 j
= ARRAY_SIZE (cpu_arch
);
13173 if (j
>= ARRAY_SIZE (cpu_arch
))
13174 as_fatal (_("invalid -march= option: `%s'"), arg
);
13178 while (next
!= NULL
);
13184 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13185 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13187 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13189 cpu_arch_tune_set
= 1;
13190 cpu_arch_tune
= cpu_arch
[j
].type
;
13191 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13195 if (j
>= ARRAY_SIZE (cpu_arch
))
13196 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13199 case OPTION_MMNEMONIC
:
13200 if (strcasecmp (arg
, "att") == 0)
13201 intel_mnemonic
= 0;
13202 else if (strcasecmp (arg
, "intel") == 0)
13203 intel_mnemonic
= 1;
13205 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13208 case OPTION_MSYNTAX
:
13209 if (strcasecmp (arg
, "att") == 0)
13211 else if (strcasecmp (arg
, "intel") == 0)
13214 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13217 case OPTION_MINDEX_REG
:
13218 allow_index_reg
= 1;
13221 case OPTION_MNAKED_REG
:
13222 allow_naked_reg
= 1;
13225 case OPTION_MSSE2AVX
:
13229 case OPTION_MSSE_CHECK
:
13230 if (strcasecmp (arg
, "error") == 0)
13231 sse_check
= check_error
;
13232 else if (strcasecmp (arg
, "warning") == 0)
13233 sse_check
= check_warning
;
13234 else if (strcasecmp (arg
, "none") == 0)
13235 sse_check
= check_none
;
13237 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13240 case OPTION_MOPERAND_CHECK
:
13241 if (strcasecmp (arg
, "error") == 0)
13242 operand_check
= check_error
;
13243 else if (strcasecmp (arg
, "warning") == 0)
13244 operand_check
= check_warning
;
13245 else if (strcasecmp (arg
, "none") == 0)
13246 operand_check
= check_none
;
13248 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13251 case OPTION_MAVXSCALAR
:
13252 if (strcasecmp (arg
, "128") == 0)
13253 avxscalar
= vex128
;
13254 else if (strcasecmp (arg
, "256") == 0)
13255 avxscalar
= vex256
;
13257 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13260 case OPTION_MVEXWIG
:
13261 if (strcmp (arg
, "0") == 0)
13263 else if (strcmp (arg
, "1") == 0)
13266 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13269 case OPTION_MADD_BND_PREFIX
:
13270 add_bnd_prefix
= 1;
13273 case OPTION_MEVEXLIG
:
13274 if (strcmp (arg
, "128") == 0)
13275 evexlig
= evexl128
;
13276 else if (strcmp (arg
, "256") == 0)
13277 evexlig
= evexl256
;
13278 else if (strcmp (arg
, "512") == 0)
13279 evexlig
= evexl512
;
13281 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13284 case OPTION_MEVEXRCIG
:
13285 if (strcmp (arg
, "rne") == 0)
13287 else if (strcmp (arg
, "rd") == 0)
13289 else if (strcmp (arg
, "ru") == 0)
13291 else if (strcmp (arg
, "rz") == 0)
13294 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13297 case OPTION_MEVEXWIG
:
13298 if (strcmp (arg
, "0") == 0)
13300 else if (strcmp (arg
, "1") == 0)
13303 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13306 # if defined (TE_PE) || defined (TE_PEP)
13307 case OPTION_MBIG_OBJ
:
13312 case OPTION_MOMIT_LOCK_PREFIX
:
13313 if (strcasecmp (arg
, "yes") == 0)
13314 omit_lock_prefix
= 1;
13315 else if (strcasecmp (arg
, "no") == 0)
13316 omit_lock_prefix
= 0;
13318 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13321 case OPTION_MFENCE_AS_LOCK_ADD
:
13322 if (strcasecmp (arg
, "yes") == 0)
13324 else if (strcasecmp (arg
, "no") == 0)
13327 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13330 case OPTION_MLFENCE_AFTER_LOAD
:
13331 if (strcasecmp (arg
, "yes") == 0)
13332 lfence_after_load
= 1;
13333 else if (strcasecmp (arg
, "no") == 0)
13334 lfence_after_load
= 0;
13336 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13339 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13340 if (strcasecmp (arg
, "all") == 0)
13342 lfence_before_indirect_branch
= lfence_branch_all
;
13343 if (lfence_before_ret
== lfence_before_ret_none
)
13344 lfence_before_ret
= lfence_before_ret_shl
;
13346 else if (strcasecmp (arg
, "memory") == 0)
13347 lfence_before_indirect_branch
= lfence_branch_memory
;
13348 else if (strcasecmp (arg
, "register") == 0)
13349 lfence_before_indirect_branch
= lfence_branch_register
;
13350 else if (strcasecmp (arg
, "none") == 0)
13351 lfence_before_indirect_branch
= lfence_branch_none
;
13353 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13357 case OPTION_MLFENCE_BEFORE_RET
:
13358 if (strcasecmp (arg
, "or") == 0)
13359 lfence_before_ret
= lfence_before_ret_or
;
13360 else if (strcasecmp (arg
, "not") == 0)
13361 lfence_before_ret
= lfence_before_ret_not
;
13362 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13363 lfence_before_ret
= lfence_before_ret_shl
;
13364 else if (strcasecmp (arg
, "none") == 0)
13365 lfence_before_ret
= lfence_before_ret_none
;
13367 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13371 case OPTION_MRELAX_RELOCATIONS
:
13372 if (strcasecmp (arg
, "yes") == 0)
13373 generate_relax_relocations
= 1;
13374 else if (strcasecmp (arg
, "no") == 0)
13375 generate_relax_relocations
= 0;
13377 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13380 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13383 long int align
= strtoul (arg
, &end
, 0);
13388 align_branch_power
= 0;
13391 else if (align
>= 16)
13394 for (align_power
= 0;
13396 align
>>= 1, align_power
++)
13398 /* Limit alignment power to 31. */
13399 if (align
== 1 && align_power
< 32)
13401 align_branch_power
= align_power
;
13406 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13410 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13413 int align
= strtoul (arg
, &end
, 0);
13414 /* Some processors only support 5 prefixes. */
13415 if (*end
== '\0' && align
>= 0 && align
< 6)
13417 align_branch_prefix_size
= align
;
13420 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13425 case OPTION_MALIGN_BRANCH
:
13427 saved
= xstrdup (arg
);
13431 next
= strchr (type
, '+');
13434 if (strcasecmp (type
, "jcc") == 0)
13435 align_branch
|= align_branch_jcc_bit
;
13436 else if (strcasecmp (type
, "fused") == 0)
13437 align_branch
|= align_branch_fused_bit
;
13438 else if (strcasecmp (type
, "jmp") == 0)
13439 align_branch
|= align_branch_jmp_bit
;
13440 else if (strcasecmp (type
, "call") == 0)
13441 align_branch
|= align_branch_call_bit
;
13442 else if (strcasecmp (type
, "ret") == 0)
13443 align_branch
|= align_branch_ret_bit
;
13444 else if (strcasecmp (type
, "indirect") == 0)
13445 align_branch
|= align_branch_indirect_bit
;
13447 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13450 while (next
!= NULL
);
13454 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13455 align_branch_power
= 5;
13456 align_branch_prefix_size
= 5;
13457 align_branch
= (align_branch_jcc_bit
13458 | align_branch_fused_bit
13459 | align_branch_jmp_bit
);
13462 case OPTION_MAMD64
:
13466 case OPTION_MINTEL64
:
13474 /* Turn off -Os. */
13475 optimize_for_space
= 0;
13477 else if (*arg
== 's')
13479 optimize_for_space
= 1;
13480 /* Turn on all encoding optimizations. */
13481 optimize
= INT_MAX
;
13485 optimize
= atoi (arg
);
13486 /* Turn off -Os. */
13487 optimize_for_space
= 0;
13497 #define MESSAGE_TEMPLATE \
13501 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13502 int *left_p
, const char *name
, int len
)
13504 int size
= sizeof (MESSAGE_TEMPLATE
);
13505 int left
= *left_p
;
13507 /* Reserve 2 spaces for ", " or ",\0" */
13510 /* Check if there is any room. */
13518 p
= mempcpy (p
, name
, len
);
13522 /* Output the current message now and start a new one. */
13525 fprintf (stream
, "%s\n", message
);
13527 left
= size
- (start
- message
) - len
- 2;
13529 gas_assert (left
>= 0);
13531 p
= mempcpy (p
, name
, len
);
13539 show_arch (FILE *stream
, int ext
, int check
)
13541 static char message
[] = MESSAGE_TEMPLATE
;
13542 char *start
= message
+ 27;
13544 int size
= sizeof (MESSAGE_TEMPLATE
);
13551 left
= size
- (start
- message
);
13552 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13554 /* Should it be skipped? */
13555 if (cpu_arch
[j
].skip
)
13558 name
= cpu_arch
[j
].name
;
13559 len
= cpu_arch
[j
].len
;
13562 /* It is an extension. Skip if we aren't asked to show it. */
13573 /* It is an processor. Skip if we show only extension. */
13576 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13578 /* It is an impossible processor - skip. */
13582 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13585 /* Display disabled extensions. */
13587 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13589 name
= cpu_noarch
[j
].name
;
13590 len
= cpu_noarch
[j
].len
;
13591 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13596 fprintf (stream
, "%s\n", message
);
13600 md_show_usage (FILE *stream
)
13602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13603 fprintf (stream
, _("\
13604 -Qy, -Qn ignored\n\
13605 -V print assembler version number\n\
13608 fprintf (stream
, _("\
13609 -n Do not optimize code alignment\n\
13610 -q quieten some warnings\n"));
13611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13612 fprintf (stream
, _("\
13615 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13616 || defined (TE_PE) || defined (TE_PEP))
13617 fprintf (stream
, _("\
13618 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13620 #ifdef SVR4_COMMENT_CHARS
13621 fprintf (stream
, _("\
13622 --divide do not treat `/' as a comment character\n"));
13624 fprintf (stream
, _("\
13625 --divide ignored\n"));
13627 fprintf (stream
, _("\
13628 -march=CPU[,+EXTENSION...]\n\
13629 generate code for CPU and EXTENSION, CPU is one of:\n"));
13630 show_arch (stream
, 0, 1);
13631 fprintf (stream
, _("\
13632 EXTENSION is combination of:\n"));
13633 show_arch (stream
, 1, 0);
13634 fprintf (stream
, _("\
13635 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13636 show_arch (stream
, 0, 0);
13637 fprintf (stream
, _("\
13638 -msse2avx encode SSE instructions with VEX prefix\n"));
13639 fprintf (stream
, _("\
13640 -msse-check=[none|error|warning] (default: warning)\n\
13641 check SSE instructions\n"));
13642 fprintf (stream
, _("\
13643 -moperand-check=[none|error|warning] (default: warning)\n\
13644 check operand combinations for validity\n"));
13645 fprintf (stream
, _("\
13646 -mavxscalar=[128|256] (default: 128)\n\
13647 encode scalar AVX instructions with specific vector\n\
13649 fprintf (stream
, _("\
13650 -mvexwig=[0|1] (default: 0)\n\
13651 encode VEX instructions with specific VEX.W value\n\
13652 for VEX.W bit ignored instructions\n"));
13653 fprintf (stream
, _("\
13654 -mevexlig=[128|256|512] (default: 128)\n\
13655 encode scalar EVEX instructions with specific vector\n\
13657 fprintf (stream
, _("\
13658 -mevexwig=[0|1] (default: 0)\n\
13659 encode EVEX instructions with specific EVEX.W value\n\
13660 for EVEX.W bit ignored instructions\n"));
13661 fprintf (stream
, _("\
13662 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13663 encode EVEX instructions with specific EVEX.RC value\n\
13664 for SAE-only ignored instructions\n"));
13665 fprintf (stream
, _("\
13666 -mmnemonic=[att|intel] "));
13667 if (SYSV386_COMPAT
)
13668 fprintf (stream
, _("(default: att)\n"));
13670 fprintf (stream
, _("(default: intel)\n"));
13671 fprintf (stream
, _("\
13672 use AT&T/Intel mnemonic\n"));
13673 fprintf (stream
, _("\
13674 -msyntax=[att|intel] (default: att)\n\
13675 use AT&T/Intel syntax\n"));
13676 fprintf (stream
, _("\
13677 -mindex-reg support pseudo index registers\n"));
13678 fprintf (stream
, _("\
13679 -mnaked-reg don't require `%%' prefix for registers\n"));
13680 fprintf (stream
, _("\
13681 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13683 fprintf (stream
, _("\
13684 -mshared disable branch optimization for shared code\n"));
13685 fprintf (stream
, _("\
13686 -mx86-used-note=[no|yes] "));
13687 if (DEFAULT_X86_USED_NOTE
)
13688 fprintf (stream
, _("(default: yes)\n"));
13690 fprintf (stream
, _("(default: no)\n"));
13691 fprintf (stream
, _("\
13692 generate x86 used ISA and feature properties\n"));
13694 #if defined (TE_PE) || defined (TE_PEP)
13695 fprintf (stream
, _("\
13696 -mbig-obj generate big object files\n"));
13698 fprintf (stream
, _("\
13699 -momit-lock-prefix=[no|yes] (default: no)\n\
13700 strip all lock prefixes\n"));
13701 fprintf (stream
, _("\
13702 -mfence-as-lock-add=[no|yes] (default: no)\n\
13703 encode lfence, mfence and sfence as\n\
13704 lock addl $0x0, (%%{re}sp)\n"));
13705 fprintf (stream
, _("\
13706 -mrelax-relocations=[no|yes] "));
13707 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13708 fprintf (stream
, _("(default: yes)\n"));
13710 fprintf (stream
, _("(default: no)\n"));
13711 fprintf (stream
, _("\
13712 generate relax relocations\n"));
13713 fprintf (stream
, _("\
13714 -malign-branch-boundary=NUM (default: 0)\n\
13715 align branches within NUM byte boundary\n"));
13716 fprintf (stream
, _("\
13717 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13718 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13720 specify types of branches to align\n"));
13721 fprintf (stream
, _("\
13722 -malign-branch-prefix-size=NUM (default: 5)\n\
13723 align branches with NUM prefixes per instruction\n"));
13724 fprintf (stream
, _("\
13725 -mbranches-within-32B-boundaries\n\
13726 align branches within 32 byte boundary\n"));
13727 fprintf (stream
, _("\
13728 -mlfence-after-load=[no|yes] (default: no)\n\
13729 generate lfence after load\n"));
13730 fprintf (stream
, _("\
13731 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13732 generate lfence before indirect near branch\n"));
13733 fprintf (stream
, _("\
13734 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13735 generate lfence before ret\n"));
13736 fprintf (stream
, _("\
13737 -mamd64 accept only AMD64 ISA [default]\n"));
13738 fprintf (stream
, _("\
13739 -mintel64 accept only Intel64 ISA\n"));
13742 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13743 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13744 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13746 /* Pick the target format to use. */
13749 i386_target_format (void)
13751 if (!strncmp (default_arch
, "x86_64", 6))
13753 update_code_flag (CODE_64BIT
, 1);
13754 if (default_arch
[6] == '\0')
13755 x86_elf_abi
= X86_64_ABI
;
13757 x86_elf_abi
= X86_64_X32_ABI
;
13759 else if (!strcmp (default_arch
, "i386"))
13760 update_code_flag (CODE_32BIT
, 1);
13761 else if (!strcmp (default_arch
, "iamcu"))
13763 update_code_flag (CODE_32BIT
, 1);
13764 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13766 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13767 cpu_arch_name
= "iamcu";
13768 cpu_sub_arch_name
= NULL
;
13769 cpu_arch_flags
= iamcu_flags
;
13770 cpu_arch_isa
= PROCESSOR_IAMCU
;
13771 cpu_arch_isa_flags
= iamcu_flags
;
13772 if (!cpu_arch_tune_set
)
13774 cpu_arch_tune
= cpu_arch_isa
;
13775 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13778 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13779 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13783 as_fatal (_("unknown architecture"));
13785 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13786 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13787 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13788 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13790 switch (OUTPUT_FLAVOR
)
13792 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13793 case bfd_target_aout_flavour
:
13794 return AOUT_TARGET_FORMAT
;
13796 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13797 # if defined (TE_PE) || defined (TE_PEP)
13798 case bfd_target_coff_flavour
:
13799 if (flag_code
== CODE_64BIT
)
13800 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13802 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13803 # elif defined (TE_GO32)
13804 case bfd_target_coff_flavour
:
13805 return "coff-go32";
13807 case bfd_target_coff_flavour
:
13808 return "coff-i386";
13811 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13812 case bfd_target_elf_flavour
:
13814 const char *format
;
13816 switch (x86_elf_abi
)
13819 format
= ELF_TARGET_FORMAT
;
13821 tls_get_addr
= "___tls_get_addr";
13825 use_rela_relocations
= 1;
13828 tls_get_addr
= "__tls_get_addr";
13830 format
= ELF_TARGET_FORMAT64
;
13832 case X86_64_X32_ABI
:
13833 use_rela_relocations
= 1;
13836 tls_get_addr
= "__tls_get_addr";
13838 disallow_64bit_reloc
= 1;
13839 format
= ELF_TARGET_FORMAT32
;
13842 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13844 if (x86_elf_abi
!= X86_64_ABI
)
13845 as_fatal (_("Intel L1OM is 64bit only"));
13846 return ELF_TARGET_L1OM_FORMAT
;
13848 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13850 if (x86_elf_abi
!= X86_64_ABI
)
13851 as_fatal (_("Intel K1OM is 64bit only"));
13852 return ELF_TARGET_K1OM_FORMAT
;
13854 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13856 if (x86_elf_abi
!= I386_ABI
)
13857 as_fatal (_("Intel MCU is 32bit only"));
13858 return ELF_TARGET_IAMCU_FORMAT
;
13864 #if defined (OBJ_MACH_O)
13865 case bfd_target_mach_o_flavour
:
13866 if (flag_code
== CODE_64BIT
)
13868 use_rela_relocations
= 1;
13870 return "mach-o-x86-64";
13873 return "mach-o-i386";
13881 #endif /* OBJ_MAYBE_ more than one */
13884 md_undefined_symbol (char *name
)
13886 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13887 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13888 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13889 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13893 if (symbol_find (name
))
13894 as_bad (_("GOT already in symbol table"));
13895 GOT_symbol
= symbol_new (name
, undefined_section
,
13896 &zero_address_frag
, 0);
13903 /* Round up a section size to the appropriate boundary. */
13906 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13908 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13909 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13911 /* For a.out, force the section size to be aligned. If we don't do
13912 this, BFD will align it for us, but it will not write out the
13913 final bytes of the section. This may be a bug in BFD, but it is
13914 easier to fix it here since that is how the other a.out targets
13918 align
= bfd_section_alignment (segment
);
13919 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13926 /* On the i386, PC-relative offsets are relative to the start of the
13927 next instruction. That is, the address of the offset, plus its
13928 size, since the offset is always the last part of the insn. */
13931 md_pcrel_from (fixS
*fixP
)
13933 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13939 s_bss (int ignore ATTRIBUTE_UNUSED
)
13943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13945 obj_elf_section_change_hook ();
13947 temp
= get_absolute_expression ();
13948 subseg_set (bss_section
, (subsegT
) temp
);
13949 demand_empty_rest_of_line ();
13954 /* Remember constant directive. */
13957 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13959 if (last_insn
.kind
!= last_insn_directive
13960 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13962 last_insn
.seg
= now_seg
;
13963 last_insn
.kind
= last_insn_directive
;
13964 last_insn
.name
= "constant directive";
13965 last_insn
.file
= as_where (&last_insn
.line
);
13966 if (lfence_before_ret
!= lfence_before_ret_none
)
13968 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13969 as_warn (_("constant directive skips -mlfence-before-ret "
13970 "and -mlfence-before-indirect-branch"));
13972 as_warn (_("constant directive skips -mlfence-before-ret"));
13974 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13975 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13980 i386_validate_fix (fixS
*fixp
)
13982 if (fixp
->fx_subsy
)
13984 if (fixp
->fx_subsy
== GOT_symbol
)
13986 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13991 if (fixp
->fx_tcbit2
)
13992 fixp
->fx_r_type
= (fixp
->fx_tcbit
13993 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13994 : BFD_RELOC_X86_64_GOTPCRELX
);
13997 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14002 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14004 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14006 fixp
->fx_subsy
= 0;
14009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14012 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14013 to section. Since PLT32 relocation must be against symbols,
14014 turn such PLT32 relocation into PC32 relocation. */
14016 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14017 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14018 && symbol_section_p (fixp
->fx_addsy
))
14019 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14022 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14023 && fixp
->fx_tcbit2
)
14024 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14031 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14034 bfd_reloc_code_real_type code
;
14036 switch (fixp
->fx_r_type
)
14038 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14039 case BFD_RELOC_SIZE32
:
14040 case BFD_RELOC_SIZE64
:
14041 if (S_IS_DEFINED (fixp
->fx_addsy
)
14042 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14044 /* Resolve size relocation against local symbol to size of
14045 the symbol plus addend. */
14046 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14047 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14048 && !fits_in_unsigned_long (value
))
14049 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14050 _("symbol size computation overflow"));
14051 fixp
->fx_addsy
= NULL
;
14052 fixp
->fx_subsy
= NULL
;
14053 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14057 /* Fall through. */
14059 case BFD_RELOC_X86_64_PLT32
:
14060 case BFD_RELOC_X86_64_GOT32
:
14061 case BFD_RELOC_X86_64_GOTPCREL
:
14062 case BFD_RELOC_X86_64_GOTPCRELX
:
14063 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14064 case BFD_RELOC_386_PLT32
:
14065 case BFD_RELOC_386_GOT32
:
14066 case BFD_RELOC_386_GOT32X
:
14067 case BFD_RELOC_386_GOTOFF
:
14068 case BFD_RELOC_386_GOTPC
:
14069 case BFD_RELOC_386_TLS_GD
:
14070 case BFD_RELOC_386_TLS_LDM
:
14071 case BFD_RELOC_386_TLS_LDO_32
:
14072 case BFD_RELOC_386_TLS_IE_32
:
14073 case BFD_RELOC_386_TLS_IE
:
14074 case BFD_RELOC_386_TLS_GOTIE
:
14075 case BFD_RELOC_386_TLS_LE_32
:
14076 case BFD_RELOC_386_TLS_LE
:
14077 case BFD_RELOC_386_TLS_GOTDESC
:
14078 case BFD_RELOC_386_TLS_DESC_CALL
:
14079 case BFD_RELOC_X86_64_TLSGD
:
14080 case BFD_RELOC_X86_64_TLSLD
:
14081 case BFD_RELOC_X86_64_DTPOFF32
:
14082 case BFD_RELOC_X86_64_DTPOFF64
:
14083 case BFD_RELOC_X86_64_GOTTPOFF
:
14084 case BFD_RELOC_X86_64_TPOFF32
:
14085 case BFD_RELOC_X86_64_TPOFF64
:
14086 case BFD_RELOC_X86_64_GOTOFF64
:
14087 case BFD_RELOC_X86_64_GOTPC32
:
14088 case BFD_RELOC_X86_64_GOT64
:
14089 case BFD_RELOC_X86_64_GOTPCREL64
:
14090 case BFD_RELOC_X86_64_GOTPC64
:
14091 case BFD_RELOC_X86_64_GOTPLT64
:
14092 case BFD_RELOC_X86_64_PLTOFF64
:
14093 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14094 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14095 case BFD_RELOC_RVA
:
14096 case BFD_RELOC_VTABLE_ENTRY
:
14097 case BFD_RELOC_VTABLE_INHERIT
:
14099 case BFD_RELOC_32_SECREL
:
14101 code
= fixp
->fx_r_type
;
14103 case BFD_RELOC_X86_64_32S
:
14104 if (!fixp
->fx_pcrel
)
14106 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14107 code
= fixp
->fx_r_type
;
14110 /* Fall through. */
14112 if (fixp
->fx_pcrel
)
14114 switch (fixp
->fx_size
)
14117 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14118 _("can not do %d byte pc-relative relocation"),
14120 code
= BFD_RELOC_32_PCREL
;
14122 case 1: code
= BFD_RELOC_8_PCREL
; break;
14123 case 2: code
= BFD_RELOC_16_PCREL
; break;
14124 case 4: code
= BFD_RELOC_32_PCREL
; break;
14126 case 8: code
= BFD_RELOC_64_PCREL
; break;
14132 switch (fixp
->fx_size
)
14135 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14136 _("can not do %d byte relocation"),
14138 code
= BFD_RELOC_32
;
14140 case 1: code
= BFD_RELOC_8
; break;
14141 case 2: code
= BFD_RELOC_16
; break;
14142 case 4: code
= BFD_RELOC_32
; break;
14144 case 8: code
= BFD_RELOC_64
; break;
14151 if ((code
== BFD_RELOC_32
14152 || code
== BFD_RELOC_32_PCREL
14153 || code
== BFD_RELOC_X86_64_32S
)
14155 && fixp
->fx_addsy
== GOT_symbol
)
14158 code
= BFD_RELOC_386_GOTPC
;
14160 code
= BFD_RELOC_X86_64_GOTPC32
;
14162 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14164 && fixp
->fx_addsy
== GOT_symbol
)
14166 code
= BFD_RELOC_X86_64_GOTPC64
;
14169 rel
= XNEW (arelent
);
14170 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14171 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14173 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14175 if (!use_rela_relocations
)
14177 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14178 vtable entry to be used in the relocation's section offset. */
14179 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14180 rel
->address
= fixp
->fx_offset
;
14181 #if defined (OBJ_COFF) && defined (TE_PE)
14182 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14183 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14188 /* Use the rela in 64bit mode. */
14191 if (disallow_64bit_reloc
)
14194 case BFD_RELOC_X86_64_DTPOFF64
:
14195 case BFD_RELOC_X86_64_TPOFF64
:
14196 case BFD_RELOC_64_PCREL
:
14197 case BFD_RELOC_X86_64_GOTOFF64
:
14198 case BFD_RELOC_X86_64_GOT64
:
14199 case BFD_RELOC_X86_64_GOTPCREL64
:
14200 case BFD_RELOC_X86_64_GOTPC64
:
14201 case BFD_RELOC_X86_64_GOTPLT64
:
14202 case BFD_RELOC_X86_64_PLTOFF64
:
14203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14204 _("cannot represent relocation type %s in x32 mode"),
14205 bfd_get_reloc_code_name (code
));
14211 if (!fixp
->fx_pcrel
)
14212 rel
->addend
= fixp
->fx_offset
;
14216 case BFD_RELOC_X86_64_PLT32
:
14217 case BFD_RELOC_X86_64_GOT32
:
14218 case BFD_RELOC_X86_64_GOTPCREL
:
14219 case BFD_RELOC_X86_64_GOTPCRELX
:
14220 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14221 case BFD_RELOC_X86_64_TLSGD
:
14222 case BFD_RELOC_X86_64_TLSLD
:
14223 case BFD_RELOC_X86_64_GOTTPOFF
:
14224 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14225 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14226 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14229 rel
->addend
= (section
->vma
14231 + fixp
->fx_addnumber
14232 + md_pcrel_from (fixp
));
14237 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14238 if (rel
->howto
== NULL
)
14240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14241 _("cannot represent relocation type %s"),
14242 bfd_get_reloc_code_name (code
));
14243 /* Set howto to a garbage value so that we can keep going. */
14244 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14245 gas_assert (rel
->howto
!= NULL
);
14251 #include "tc-i386-intel.c"
14254 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14256 int saved_naked_reg
;
14257 char saved_register_dot
;
14259 saved_naked_reg
= allow_naked_reg
;
14260 allow_naked_reg
= 1;
14261 saved_register_dot
= register_chars
['.'];
14262 register_chars
['.'] = '.';
14263 allow_pseudo_reg
= 1;
14264 expression_and_evaluate (exp
);
14265 allow_pseudo_reg
= 0;
14266 register_chars
['.'] = saved_register_dot
;
14267 allow_naked_reg
= saved_naked_reg
;
14269 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14271 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14273 exp
->X_op
= O_constant
;
14274 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14275 .dw2_regnum
[flag_code
>> 1];
14278 exp
->X_op
= O_illegal
;
14283 tc_x86_frame_initial_instructions (void)
14285 static unsigned int sp_regno
[2];
14287 if (!sp_regno
[flag_code
>> 1])
14289 char *saved_input
= input_line_pointer
;
14290 char sp
[][4] = {"esp", "rsp"};
14293 input_line_pointer
= sp
[flag_code
>> 1];
14294 tc_x86_parse_to_dw2regnum (&exp
);
14295 gas_assert (exp
.X_op
== O_constant
);
14296 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14297 input_line_pointer
= saved_input
;
14300 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14301 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14305 x86_dwarf2_addr_size (void)
14307 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14308 if (x86_elf_abi
== X86_64_X32_ABI
)
14311 return bfd_arch_bits_per_address (stdoutput
) / 8;
14315 i386_elf_section_type (const char *str
, size_t len
)
14317 if (flag_code
== CODE_64BIT
14318 && len
== sizeof ("unwind") - 1
14319 && strncmp (str
, "unwind", 6) == 0)
14320 return SHT_X86_64_UNWIND
;
14327 i386_solaris_fix_up_eh_frame (segT sec
)
14329 if (flag_code
== CODE_64BIT
)
14330 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14336 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14340 exp
.X_op
= O_secrel
;
14341 exp
.X_add_symbol
= symbol
;
14342 exp
.X_add_number
= 0;
14343 emit_expr (&exp
, size
);
14347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14348 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14351 x86_64_section_letter (int letter
, const char **ptr_msg
)
14353 if (flag_code
== CODE_64BIT
)
14356 return SHF_X86_64_LARGE
;
14358 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14361 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14366 x86_64_section_word (char *str
, size_t len
)
14368 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14369 return SHF_X86_64_LARGE
;
14375 handle_large_common (int small ATTRIBUTE_UNUSED
)
14377 if (flag_code
!= CODE_64BIT
)
14379 s_comm_internal (0, elf_common_parse
);
14380 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14384 static segT lbss_section
;
14385 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14386 asection
*saved_bss_section
= bss_section
;
14388 if (lbss_section
== NULL
)
14390 flagword applicable
;
14391 segT seg
= now_seg
;
14392 subsegT subseg
= now_subseg
;
14394 /* The .lbss section is for local .largecomm symbols. */
14395 lbss_section
= subseg_new (".lbss", 0);
14396 applicable
= bfd_applicable_section_flags (stdoutput
);
14397 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14398 seg_info (lbss_section
)->bss
= 1;
14400 subseg_set (seg
, subseg
);
14403 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14404 bss_section
= lbss_section
;
14406 s_comm_internal (0, elf_common_parse
);
14408 elf_com_section_ptr
= saved_com_section_ptr
;
14409 bss_section
= saved_bss_section
;
14412 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */