1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* If set, conditional jumps are not automatically promoted to handle
277 larger than a byte offset. */
278 static unsigned int no_cond_jump_promotion
= 0;
280 /* Interface to relax_segment.
281 There are 3 major relax states for 386 jump insns because the
282 different types of jumps add different sizes to frags when we're
283 figuring out what sort of jump to choose to reach a given label. */
286 #define UNCOND_JUMP 1
288 #define COND_JUMP86 3
293 #define SMALL16 (SMALL|CODE16)
295 #define BIG16 (BIG|CODE16)
299 #define INLINE __inline__
305 #define ENCODE_RELAX_STATE(type, size) \
306 ((relax_substateT) (((type) << 2) | (size)))
307 #define TYPE_FROM_RELAX_STATE(s) \
309 #define DISP_SIZE_FROM_RELAX_STATE(s) \
310 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
312 /* This table is used by relax_frag to promote short jumps to long
313 ones where necessary. SMALL (short) jumps may be promoted to BIG
314 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
315 don't allow a short jump in a 32 bit code segment to be promoted to
316 a 16 bit offset jump because it's slower (requires data size
317 prefix), and doesn't work, unless the destination is in the bottom
318 64k of the code segment (The top 16 bits of eip are zeroed). */
320 const relax_typeS md_relax_table
[] =
323 1) most positive reach of this state,
324 2) most negative reach of this state,
325 3) how many bytes this mode will add to the size of the current frag
326 4) which index into the table to try if we can't fit into this one. */
332 /* UNCOND_JUMP states. */
333 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
335 /* dword jmp adds 3 bytes to frag:
336 0 extra opcode bytes, 3 extra displacement bytes. */
338 /* word jmp adds 1 byte to frag:
339 0 extra opcode bytes, 1 extra displacement byte. */
342 /* COND_JUMP states. */
343 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
344 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
345 /* dword conditionals adds 4 bytes to frag:
346 1 extra opcode byte, 3 extra displacement bytes. */
348 /* word conditionals add 2 bytes to frag:
349 1 extra opcode byte, 1 extra displacement byte. */
352 /* COND_JUMP86 states. */
353 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
354 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
355 /* dword conditionals adds 4 bytes to frag:
356 1 extra opcode byte, 3 extra displacement bytes. */
358 /* word conditionals add 3 bytes to frag:
359 1 extra opcode byte, 2 extra displacement bytes. */
363 static const arch_entry cpu_arch
[] = {
365 {"i186", Cpu086
|Cpu186
},
366 {"i286", Cpu086
|Cpu186
|Cpu286
},
367 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
368 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
369 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
370 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
371 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
372 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
373 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
374 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
375 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
376 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
381 i386_align_code (fragP
, count
)
385 /* Various efficient no-op patterns for aligning code labels.
386 Note: Don't try to assemble the instructions in the comments.
387 0L and 0w are not legal. */
388 static const char f32_1
[] =
390 static const char f32_2
[] =
391 {0x89,0xf6}; /* movl %esi,%esi */
392 static const char f32_3
[] =
393 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
394 static const char f32_4
[] =
395 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_5
[] =
398 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
399 static const char f32_6
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
401 static const char f32_7
[] =
402 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_8
[] =
405 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
406 static const char f32_9
[] =
407 {0x89,0xf6, /* movl %esi,%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_10
[] =
410 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_11
[] =
413 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
414 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
415 static const char f32_12
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
418 static const char f32_13
[] =
419 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_14
[] =
422 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
423 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
424 static const char f32_15
[] =
425 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
426 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
427 static const char f16_3
[] =
428 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
429 static const char f16_4
[] =
430 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_5
[] =
433 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
434 static const char f16_6
[] =
435 {0x89,0xf6, /* mov %si,%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_7
[] =
438 {0x8d,0x74,0x00, /* lea 0(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char f16_8
[] =
441 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
442 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
443 static const char *const f32_patt
[] = {
444 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
445 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
447 static const char *const f16_patt
[] = {
448 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
449 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
452 /* ??? We can't use these fillers for x86_64, since they often kills the
453 upper halves. Solve later. */
454 if (flag_code
== CODE_64BIT
)
457 if (count
> 0 && count
<= 15)
459 if (flag_code
== CODE_16BIT
)
461 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
462 f16_patt
[count
- 1], count
);
464 /* Adjust jump offset. */
465 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
468 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
469 f32_patt
[count
- 1], count
);
470 fragP
->fr_var
= count
;
474 static char *output_invalid
PARAMS ((int c
));
475 static int i386_operand
PARAMS ((char *operand_string
));
476 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
477 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
481 static void s_bss
PARAMS ((int));
484 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
486 static INLINE
unsigned int
487 mode_from_disp_size (t
)
490 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
494 fits_in_signed_byte (num
)
497 return (num
>= -128) && (num
<= 127);
501 fits_in_unsigned_byte (num
)
504 return (num
& 0xff) == num
;
508 fits_in_unsigned_word (num
)
511 return (num
& 0xffff) == num
;
515 fits_in_signed_word (num
)
518 return (-32768 <= num
) && (num
<= 32767);
521 fits_in_signed_long (num
)
522 offsetT num ATTRIBUTE_UNUSED
;
527 return (!(((offsetT
) -1 << 31) & num
)
528 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
530 } /* fits_in_signed_long() */
532 fits_in_unsigned_long (num
)
533 offsetT num ATTRIBUTE_UNUSED
;
538 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
540 } /* fits_in_unsigned_long() */
543 smallest_imm_type (num
)
546 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
547 && !(cpu_arch_flags
& (CpuUnknown
)))
549 /* This code is disabled on the 486 because all the Imm1 forms
550 in the opcode table are slower on the i486. They're the
551 versions with the implicitly specified single-position
552 displacement, which has another syntax if you really want to
555 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
557 return (fits_in_signed_byte (num
)
558 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
559 : fits_in_unsigned_byte (num
)
560 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
561 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
562 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
563 : fits_in_signed_long (num
)
564 ? (Imm32
| Imm32S
| Imm64
)
565 : fits_in_unsigned_long (num
)
571 offset_in_range (val
, size
)
579 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
580 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
581 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
583 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
588 /* If BFD64, sign extend val. */
589 if (!use_rela_relocations
)
590 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
591 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
593 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
595 char buf1
[40], buf2
[40];
597 sprint_value (buf1
, val
);
598 sprint_value (buf2
, val
& mask
);
599 as_warn (_("%s shortened to %s"), buf1
, buf2
);
604 /* Returns 0 if attempting to add a prefix where one from the same
605 class already exists, 1 if non rep/repne added, 2 if rep/repne
614 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
622 case CS_PREFIX_OPCODE
:
623 case DS_PREFIX_OPCODE
:
624 case ES_PREFIX_OPCODE
:
625 case FS_PREFIX_OPCODE
:
626 case GS_PREFIX_OPCODE
:
627 case SS_PREFIX_OPCODE
:
631 case REPNE_PREFIX_OPCODE
:
632 case REPE_PREFIX_OPCODE
:
635 case LOCK_PREFIX_OPCODE
:
643 case ADDR_PREFIX_OPCODE
:
647 case DATA_PREFIX_OPCODE
:
654 as_bad (_("same type of prefix used twice"));
659 i
.prefix
[q
] = prefix
;
664 set_code_flag (value
)
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
670 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
672 as_bad (_("64bit mode not supported on this CPU."));
674 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
676 as_bad (_("32bit mode not supported on this CPU."));
682 set_16bit_gcc_code_flag (new_code_flag
)
685 flag_code
= new_code_flag
;
686 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
687 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
692 set_intel_syntax (syntax_flag
)
695 /* Find out if register prefixing is specified. */
696 int ask_naked_reg
= 0;
699 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
701 char *string
= input_line_pointer
;
702 int e
= get_symbol_end ();
704 if (strcmp (string
, "prefix") == 0)
706 else if (strcmp (string
, "noprefix") == 0)
709 as_bad (_("bad argument to syntax directive."));
710 *input_line_pointer
= e
;
712 demand_empty_rest_of_line ();
714 intel_syntax
= syntax_flag
;
716 if (ask_naked_reg
== 0)
719 allow_naked_reg
= (intel_syntax
720 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
722 /* Conservative default. */
727 allow_naked_reg
= (ask_naked_reg
< 0);
732 int dummy ATTRIBUTE_UNUSED
;
736 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
738 char *string
= input_line_pointer
;
739 int e
= get_symbol_end ();
742 for (i
= 0; cpu_arch
[i
].name
; i
++)
744 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
746 cpu_arch_name
= cpu_arch
[i
].name
;
747 cpu_arch_flags
= (cpu_arch
[i
].flags
748 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
752 if (!cpu_arch
[i
].name
)
753 as_bad (_("no such architecture: `%s'"), string
);
755 *input_line_pointer
= e
;
758 as_bad (_("missing cpu architecture"));
760 no_cond_jump_promotion
= 0;
761 if (*input_line_pointer
== ','
762 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
764 char *string
= ++input_line_pointer
;
765 int e
= get_symbol_end ();
767 if (strcmp (string
, "nojumps") == 0)
768 no_cond_jump_promotion
= 1;
769 else if (strcmp (string
, "jumps") == 0)
772 as_bad (_("no such architecture modifier: `%s'"), string
);
774 *input_line_pointer
= e
;
777 demand_empty_rest_of_line ();
780 const pseudo_typeS md_pseudo_table
[] =
782 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
783 {"align", s_align_bytes
, 0},
785 {"align", s_align_ptwo
, 0},
787 {"arch", set_cpu_arch
, 0},
791 {"ffloat", float_cons
, 'f'},
792 {"dfloat", float_cons
, 'd'},
793 {"tfloat", float_cons
, 'x'},
795 {"noopt", s_ignore
, 0},
796 {"optim", s_ignore
, 0},
797 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
798 {"code16", set_code_flag
, CODE_16BIT
},
799 {"code32", set_code_flag
, CODE_32BIT
},
800 {"code64", set_code_flag
, CODE_64BIT
},
801 {"intel_syntax", set_intel_syntax
, 1},
802 {"att_syntax", set_intel_syntax
, 0},
803 {"file", dwarf2_directive_file
, 0},
804 {"loc", dwarf2_directive_loc
, 0},
808 /* For interface with expression (). */
809 extern char *input_line_pointer
;
811 /* Hash table for instruction mnemonic lookup. */
812 static struct hash_control
*op_hash
;
814 /* Hash table for register lookup. */
815 static struct hash_control
*reg_hash
;
821 if (!strcmp (default_arch
, "x86_64"))
822 return bfd_mach_x86_64
;
823 else if (!strcmp (default_arch
, "i386"))
824 return bfd_mach_i386_i386
;
826 as_fatal (_("Unknown architecture"));
833 const char *hash_err
;
835 /* Initialize op_hash hash table. */
836 op_hash
= hash_new ();
839 register const template *optab
;
840 register templates
*core_optab
;
842 /* Setup for loop. */
844 core_optab
= (templates
*) xmalloc (sizeof (templates
));
845 core_optab
->start
= optab
;
850 if (optab
->name
== NULL
851 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
853 /* different name --> ship out current template list;
854 add to hash table; & begin anew. */
855 core_optab
->end
= optab
;
856 hash_err
= hash_insert (op_hash
,
861 as_fatal (_("Internal Error: Can't hash %s: %s"),
865 if (optab
->name
== NULL
)
867 core_optab
= (templates
*) xmalloc (sizeof (templates
));
868 core_optab
->start
= optab
;
873 /* Initialize reg_hash hash table. */
874 reg_hash
= hash_new ();
876 register const reg_entry
*regtab
;
878 for (regtab
= i386_regtab
;
879 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
882 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
890 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
895 for (c
= 0; c
< 256; c
++)
900 mnemonic_chars
[c
] = c
;
901 register_chars
[c
] = c
;
902 operand_chars
[c
] = c
;
904 else if (islower (c
))
906 mnemonic_chars
[c
] = c
;
907 register_chars
[c
] = c
;
908 operand_chars
[c
] = c
;
910 else if (isupper (c
))
912 mnemonic_chars
[c
] = tolower (c
);
913 register_chars
[c
] = mnemonic_chars
[c
];
914 operand_chars
[c
] = c
;
917 if (isalpha (c
) || isdigit (c
))
918 identifier_chars
[c
] = c
;
921 identifier_chars
[c
] = c
;
922 operand_chars
[c
] = c
;
927 identifier_chars
['@'] = '@';
929 digit_chars
['-'] = '-';
930 identifier_chars
['_'] = '_';
931 identifier_chars
['.'] = '.';
933 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
934 operand_chars
[(unsigned char) *p
] = *p
;
937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
938 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
940 record_alignment (text_section
, 2);
941 record_alignment (data_section
, 2);
942 record_alignment (bss_section
, 2);
948 i386_print_statistics (file
)
951 hash_print_statistics (file
, "i386 opcode", op_hash
);
952 hash_print_statistics (file
, "i386 register", reg_hash
);
957 /* Debugging routines for md_assemble. */
958 static void pi
PARAMS ((char *, i386_insn
*));
959 static void pte
PARAMS ((template *));
960 static void pt
PARAMS ((unsigned int));
961 static void pe
PARAMS ((expressionS
*));
962 static void ps
PARAMS ((symbolS
*));
971 fprintf (stdout
, "%s: template ", line
);
973 fprintf (stdout
, " address: base %s index %s scale %x\n",
974 x
->base_reg
? x
->base_reg
->reg_name
: "none",
975 x
->index_reg
? x
->index_reg
->reg_name
: "none",
976 x
->log2_scale_factor
);
977 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
978 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
979 fprintf (stdout
, " sib: base %x index %x scale %x\n",
980 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
981 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
982 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
983 for (i
= 0; i
< x
->operands
; i
++)
985 fprintf (stdout
, " #%d: ", i
+ 1);
987 fprintf (stdout
, "\n");
989 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
990 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
991 if (x
->types
[i
] & Imm
)
993 if (x
->types
[i
] & Disp
)
1003 fprintf (stdout
, " %d operands ", t
->operands
);
1004 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1005 if (t
->extension_opcode
!= None
)
1006 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1007 if (t
->opcode_modifier
& D
)
1008 fprintf (stdout
, "D");
1009 if (t
->opcode_modifier
& W
)
1010 fprintf (stdout
, "W");
1011 fprintf (stdout
, "\n");
1012 for (i
= 0; i
< t
->operands
; i
++)
1014 fprintf (stdout
, " #%d type ", i
+ 1);
1015 pt (t
->operand_types
[i
]);
1016 fprintf (stdout
, "\n");
1024 fprintf (stdout
, " operation %d\n", e
->X_op
);
1025 fprintf (stdout
, " add_number %ld (%lx)\n",
1026 (long) e
->X_add_number
, (long) e
->X_add_number
);
1027 if (e
->X_add_symbol
)
1029 fprintf (stdout
, " add_symbol ");
1030 ps (e
->X_add_symbol
);
1031 fprintf (stdout
, "\n");
1035 fprintf (stdout
, " op_symbol ");
1036 ps (e
->X_op_symbol
);
1037 fprintf (stdout
, "\n");
1045 fprintf (stdout
, "%s type %s%s",
1047 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1048 segment_name (S_GET_SEGMENT (s
)));
1070 { BaseIndex
, "BaseIndex" },
1074 { Disp32S
, "d32s" },
1076 { InOutPortReg
, "InOutPortReg" },
1077 { ShiftCount
, "ShiftCount" },
1078 { Control
, "control reg" },
1079 { Test
, "test reg" },
1080 { Debug
, "debug reg" },
1081 { FloatReg
, "FReg" },
1082 { FloatAcc
, "FAcc" },
1086 { JumpAbsolute
, "Jump Absolute" },
1097 register struct type_name
*ty
;
1099 for (ty
= type_names
; ty
->mask
; ty
++)
1101 fprintf (stdout
, "%s, ", ty
->tname
);
1105 #endif /* DEBUG386 */
1108 tc_i386_force_relocation (fixp
)
1111 #ifdef BFD_ASSEMBLER
1112 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1113 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1118 return fixp
->fx_r_type
== 7;
1122 #ifdef BFD_ASSEMBLER
1124 static bfd_reloc_code_real_type
1125 reloc (size
, pcrel
, sign
, other
)
1129 bfd_reloc_code_real_type other
;
1131 if (other
!= NO_RELOC
)
1137 as_bad (_("There are no unsigned pc-relative relocations"));
1140 case 1: return BFD_RELOC_8_PCREL
;
1141 case 2: return BFD_RELOC_16_PCREL
;
1142 case 4: return BFD_RELOC_32_PCREL
;
1144 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1151 case 4: return BFD_RELOC_X86_64_32S
;
1156 case 1: return BFD_RELOC_8
;
1157 case 2: return BFD_RELOC_16
;
1158 case 4: return BFD_RELOC_32
;
1159 case 8: return BFD_RELOC_64
;
1161 as_bad (_("can not do %s %d byte relocation"),
1162 sign
? "signed" : "unsigned", size
);
1166 return BFD_RELOC_NONE
;
1169 /* Here we decide which fixups can be adjusted to make them relative to
1170 the beginning of the section instead of the symbol. Basically we need
1171 to make sure that the dynamic relocations are done correctly, so in
1172 some cases we force the original symbol to be used. */
1175 tc_i386_fix_adjustable (fixP
)
1178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1179 /* Prevent all adjustments to global symbols, or else dynamic
1180 linking will not work correctly. */
1181 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1182 || S_IS_WEAK (fixP
->fx_addsy
))
1185 /* adjust_reloc_syms doesn't know about the GOT. */
1186 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1187 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1188 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1189 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1190 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1191 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1192 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1193 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1198 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1199 #define BFD_RELOC_16 0
1200 #define BFD_RELOC_32 0
1201 #define BFD_RELOC_16_PCREL 0
1202 #define BFD_RELOC_32_PCREL 0
1203 #define BFD_RELOC_386_PLT32 0
1204 #define BFD_RELOC_386_GOT32 0
1205 #define BFD_RELOC_386_GOTOFF 0
1206 #define BFD_RELOC_X86_64_PLT32 0
1207 #define BFD_RELOC_X86_64_GOT32 0
1208 #define BFD_RELOC_X86_64_GOTPCREL 0
1211 static int intel_float_operand
PARAMS ((char *mnemonic
));
1214 intel_float_operand (mnemonic
)
1217 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1220 if (mnemonic
[0] == 'f')
1226 /* This is the guts of the machine-dependent assembler. LINE points to a
1227 machine dependent instruction. This function is supposed to emit
1228 the frags/bytes it assembles to. */
1234 /* Points to template once we've found it. */
1237 /* Count the size of the instruction generated. Does not include
1238 variable part of jump insns before relax. */
1243 char mnemonic
[MAX_MNEM_SIZE
];
1245 /* Initialize globals. */
1246 memset (&i
, '\0', sizeof (i
));
1247 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1248 i
.disp_reloc
[j
] = NO_RELOC
;
1249 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1250 memset (im_expressions
, '\0', sizeof (im_expressions
));
1251 save_stack_p
= save_stack
;
1253 /* First parse an instruction mnemonic & call i386_operand for the operands.
1254 We assume that the scrubber has arranged it so that line[0] is the valid
1255 start of a (possibly prefixed) mnemonic. */
1258 char *token_start
= l
;
1261 /* Non-zero if we found a prefix only acceptable with string insns. */
1262 const char *expecting_string_instruction
= NULL
;
1267 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1270 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1272 as_bad (_("no such instruction: `%s'"), token_start
);
1277 if (!is_space_char (*l
)
1278 && *l
!= END_OF_INSN
1279 && *l
!= PREFIX_SEPARATOR
)
1281 as_bad (_("invalid character %s in mnemonic"),
1282 output_invalid (*l
));
1285 if (token_start
== l
)
1287 if (*l
== PREFIX_SEPARATOR
)
1288 as_bad (_("expecting prefix; got nothing"));
1290 as_bad (_("expecting mnemonic; got nothing"));
1294 /* Look up instruction (or prefix) via hash table. */
1295 current_templates
= hash_find (op_hash
, mnemonic
);
1297 if (*l
!= END_OF_INSN
1298 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1299 && current_templates
1300 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1302 /* If we are in 16-bit mode, do not allow addr16 or data16.
1303 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1304 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1305 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1306 ^ (flag_code
== CODE_16BIT
)))
1308 as_bad (_("redundant %s prefix"),
1309 current_templates
->start
->name
);
1312 /* Add prefix, checking for repeated prefixes. */
1313 switch (add_prefix (current_templates
->start
->base_opcode
))
1318 expecting_string_instruction
= current_templates
->start
->name
;
1321 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1328 if (!current_templates
)
1330 /* See if we can get a match by trimming off a suffix. */
1333 case WORD_MNEM_SUFFIX
:
1334 case BYTE_MNEM_SUFFIX
:
1335 case QWORD_MNEM_SUFFIX
:
1336 i
.suffix
= mnem_p
[-1];
1338 current_templates
= hash_find (op_hash
, mnemonic
);
1340 case SHORT_MNEM_SUFFIX
:
1341 case LONG_MNEM_SUFFIX
:
1344 i
.suffix
= mnem_p
[-1];
1346 current_templates
= hash_find (op_hash
, mnemonic
);
1354 if (intel_float_operand (mnemonic
))
1355 i
.suffix
= SHORT_MNEM_SUFFIX
;
1357 i
.suffix
= LONG_MNEM_SUFFIX
;
1359 current_templates
= hash_find (op_hash
, mnemonic
);
1363 if (!current_templates
)
1365 as_bad (_("no such instruction: `%s'"), token_start
);
1370 /* Check if instruction is supported on specified architecture. */
1371 if (cpu_arch_flags
!= 0)
1373 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1374 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1376 as_warn (_("`%s' is not supported on `%s'"),
1377 current_templates
->start
->name
, cpu_arch_name
);
1379 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1381 as_warn (_("use .code16 to ensure correct addressing mode"));
1385 /* Check for rep/repne without a string instruction. */
1386 if (expecting_string_instruction
1387 && !(current_templates
->start
->opcode_modifier
& IsString
))
1389 as_bad (_("expecting string instruction after `%s'"),
1390 expecting_string_instruction
);
1394 /* There may be operands to parse. */
1395 if (*l
!= END_OF_INSN
)
1397 /* 1 if operand is pending after ','. */
1398 unsigned int expecting_operand
= 0;
1400 /* Non-zero if operand parens not balanced. */
1401 unsigned int paren_not_balanced
;
1405 /* Skip optional white space before operand. */
1406 if (is_space_char (*l
))
1408 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1410 as_bad (_("invalid character %s before operand %d"),
1411 output_invalid (*l
),
1415 token_start
= l
; /* after white space */
1416 paren_not_balanced
= 0;
1417 while (paren_not_balanced
|| *l
!= ',')
1419 if (*l
== END_OF_INSN
)
1421 if (paren_not_balanced
)
1424 as_bad (_("unbalanced parenthesis in operand %d."),
1427 as_bad (_("unbalanced brackets in operand %d."),
1432 break; /* we are done */
1434 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1436 as_bad (_("invalid character %s in operand %d"),
1437 output_invalid (*l
),
1444 ++paren_not_balanced
;
1446 --paren_not_balanced
;
1451 ++paren_not_balanced
;
1453 --paren_not_balanced
;
1457 if (l
!= token_start
)
1458 { /* Yes, we've read in another operand. */
1459 unsigned int operand_ok
;
1460 this_operand
= i
.operands
++;
1461 if (i
.operands
> MAX_OPERANDS
)
1463 as_bad (_("spurious operands; (%d operands/instruction max)"),
1467 /* Now parse operand adding info to 'i' as we go along. */
1468 END_STRING_AND_SAVE (l
);
1472 i386_intel_operand (token_start
,
1473 intel_float_operand (mnemonic
));
1475 operand_ok
= i386_operand (token_start
);
1477 RESTORE_END_STRING (l
);
1483 if (expecting_operand
)
1485 expecting_operand_after_comma
:
1486 as_bad (_("expecting operand after ','; got nothing"));
1491 as_bad (_("expecting operand before ','; got nothing"));
1496 /* Now *l must be either ',' or END_OF_INSN. */
1499 if (*++l
== END_OF_INSN
)
1501 /* Just skip it, if it's \n complain. */
1502 goto expecting_operand_after_comma
;
1504 expecting_operand
= 1;
1507 while (*l
!= END_OF_INSN
);
1511 /* Now we've parsed the mnemonic into a set of templates, and have the
1514 Next, we find a template that matches the given insn,
1515 making sure the overlap of the given operands types is consistent
1516 with the template operand types. */
1518 #define MATCH(overlap, given, template) \
1519 ((overlap & ~JumpAbsolute) \
1520 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1522 /* If given types r0 and r1 are registers they must be of the same type
1523 unless the expected operand type register overlap is null.
1524 Note that Acc in a template matches every size of reg. */
1525 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1526 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1527 ((g0) & Reg) == ((g1) & Reg) || \
1528 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1531 register unsigned int overlap0
, overlap1
;
1532 unsigned int overlap2
;
1533 unsigned int found_reverse_match
;
1536 /* All intel opcodes have reversed operands except for "bound" and
1537 "enter". We also don't reverse intersegment "jmp" and "call"
1538 instructions with 2 immediate operands so that the immediate segment
1539 precedes the offset, as it does when in AT&T mode. "enter" and the
1540 intersegment "jmp" and "call" instructions are the only ones that
1541 have two immediate operands. */
1542 if (intel_syntax
&& i
.operands
> 1
1543 && (strcmp (mnemonic
, "bound") != 0)
1544 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1546 union i386_op temp_op
;
1547 unsigned int temp_type
;
1548 #ifdef BFD_ASSEMBLER
1549 enum bfd_reloc_code_real temp_reloc
;
1556 if (i
.operands
== 2)
1561 else if (i
.operands
== 3)
1566 temp_type
= i
.types
[xchg2
];
1567 i
.types
[xchg2
] = i
.types
[xchg1
];
1568 i
.types
[xchg1
] = temp_type
;
1569 temp_op
= i
.op
[xchg2
];
1570 i
.op
[xchg2
] = i
.op
[xchg1
];
1571 i
.op
[xchg1
] = temp_op
;
1572 temp_reloc
= i
.disp_reloc
[xchg2
];
1573 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1574 i
.disp_reloc
[xchg1
] = temp_reloc
;
1576 if (i
.mem_operands
== 2)
1578 const seg_entry
*temp_seg
;
1579 temp_seg
= i
.seg
[0];
1580 i
.seg
[0] = i
.seg
[1];
1581 i
.seg
[1] = temp_seg
;
1587 /* Try to ensure constant immediates are represented in the smallest
1589 char guess_suffix
= 0;
1593 guess_suffix
= i
.suffix
;
1594 else if (i
.reg_operands
)
1596 /* Figure out a suffix from the last register operand specified.
1597 We can't do this properly yet, ie. excluding InOutPortReg,
1598 but the following works for instructions with immediates.
1599 In any case, we can't set i.suffix yet. */
1600 for (op
= i
.operands
; --op
>= 0;)
1601 if (i
.types
[op
] & Reg
)
1603 if (i
.types
[op
] & Reg8
)
1604 guess_suffix
= BYTE_MNEM_SUFFIX
;
1605 else if (i
.types
[op
] & Reg16
)
1606 guess_suffix
= WORD_MNEM_SUFFIX
;
1607 else if (i
.types
[op
] & Reg32
)
1608 guess_suffix
= LONG_MNEM_SUFFIX
;
1609 else if (i
.types
[op
] & Reg64
)
1610 guess_suffix
= QWORD_MNEM_SUFFIX
;
1614 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1615 guess_suffix
= WORD_MNEM_SUFFIX
;
1617 for (op
= i
.operands
; --op
>= 0;)
1618 if (i
.types
[op
] & Imm
)
1620 switch (i
.op
[op
].imms
->X_op
)
1623 /* If a suffix is given, this operand may be shortened. */
1624 switch (guess_suffix
)
1626 case LONG_MNEM_SUFFIX
:
1627 i
.types
[op
] |= Imm32
| Imm64
;
1629 case WORD_MNEM_SUFFIX
:
1630 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1632 case BYTE_MNEM_SUFFIX
:
1633 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1637 /* If this operand is at most 16 bits, convert it
1638 to a signed 16 bit number before trying to see
1639 whether it will fit in an even smaller size.
1640 This allows a 16-bit operand such as $0xffe0 to
1641 be recognised as within Imm8S range. */
1642 if ((i
.types
[op
] & Imm16
)
1643 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1645 i
.op
[op
].imms
->X_add_number
=
1646 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1648 if ((i
.types
[op
] & Imm32
)
1649 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1651 i
.op
[op
].imms
->X_add_number
=
1652 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1654 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1655 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1656 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1657 i
.types
[op
] &= ~Imm32
;
1662 /* Symbols and expressions. */
1664 /* Convert symbolic operand to proper sizes for matching. */
1665 switch (guess_suffix
)
1667 case QWORD_MNEM_SUFFIX
:
1668 i
.types
[op
] = Imm64
| Imm32S
;
1670 case LONG_MNEM_SUFFIX
:
1671 i
.types
[op
] = Imm32
| Imm64
;
1673 case WORD_MNEM_SUFFIX
:
1674 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1677 case BYTE_MNEM_SUFFIX
:
1678 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1687 if (i
.disp_operands
)
1689 /* Try to use the smallest displacement type too. */
1692 for (op
= i
.operands
; --op
>= 0;)
1693 if ((i
.types
[op
] & Disp
)
1694 && i
.op
[op
].imms
->X_op
== O_constant
)
1696 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1698 if (i
.types
[op
] & Disp16
)
1700 /* We know this operand is at most 16 bits, so
1701 convert to a signed 16 bit number before trying
1702 to see whether it will fit in an even smaller
1705 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1707 else if (i
.types
[op
] & Disp32
)
1709 /* We know this operand is at most 32 bits, so convert to a
1710 signed 32 bit number before trying to see whether it will
1711 fit in an even smaller size. */
1712 disp
&= (((offsetT
) 2 << 31) - 1);
1713 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1715 if (flag_code
== CODE_64BIT
)
1717 if (fits_in_signed_long (disp
))
1718 i
.types
[op
] |= Disp32S
;
1719 if (fits_in_unsigned_long (disp
))
1720 i
.types
[op
] |= Disp32
;
1722 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1723 && fits_in_signed_byte (disp
))
1724 i
.types
[op
] |= Disp8
;
1731 found_reverse_match
= 0;
1732 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1734 : (i
.suffix
== WORD_MNEM_SUFFIX
1736 : (i
.suffix
== SHORT_MNEM_SUFFIX
1738 : (i
.suffix
== LONG_MNEM_SUFFIX
1740 : (i
.suffix
== QWORD_MNEM_SUFFIX
1742 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1744 for (t
= current_templates
->start
;
1745 t
< current_templates
->end
;
1748 /* Must have right number of operands. */
1749 if (i
.operands
!= t
->operands
)
1752 /* Check the suffix, except for some instructions in intel mode. */
1753 if ((t
->opcode_modifier
& suffix_check
)
1755 && (t
->opcode_modifier
& IgnoreSize
))
1757 && t
->base_opcode
== 0xd9
1758 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1759 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1762 /* Do not verify operands when there are none. */
1763 else if (!t
->operands
)
1765 if (t
->cpu_flags
& ~cpu_arch_flags
)
1767 /* We've found a match; break out of loop. */
1771 overlap0
= i
.types
[0] & t
->operand_types
[0];
1772 switch (t
->operands
)
1775 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1780 overlap1
= i
.types
[1] & t
->operand_types
[1];
1781 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1782 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1783 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1784 t
->operand_types
[0],
1785 overlap1
, i
.types
[1],
1786 t
->operand_types
[1]))
1788 /* Check if other direction is valid ... */
1789 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1792 /* Try reversing direction of operands. */
1793 overlap0
= i
.types
[0] & t
->operand_types
[1];
1794 overlap1
= i
.types
[1] & t
->operand_types
[0];
1795 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1796 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1797 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1798 t
->operand_types
[1],
1799 overlap1
, i
.types
[1],
1800 t
->operand_types
[0]))
1802 /* Does not match either direction. */
1805 /* found_reverse_match holds which of D or FloatDR
1807 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1809 /* Found a forward 2 operand match here. */
1810 else if (t
->operands
== 3)
1812 /* Here we make use of the fact that there are no
1813 reverse match 3 operand instructions, and all 3
1814 operand instructions only need to be checked for
1815 register consistency between operands 2 and 3. */
1816 overlap2
= i
.types
[2] & t
->operand_types
[2];
1817 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1818 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1819 t
->operand_types
[1],
1820 overlap2
, i
.types
[2],
1821 t
->operand_types
[2]))
1825 /* Found either forward/reverse 2 or 3 operand match here:
1826 slip through to break. */
1828 if (t
->cpu_flags
& ~cpu_arch_flags
)
1830 found_reverse_match
= 0;
1833 /* We've found a match; break out of loop. */
1836 if (t
== current_templates
->end
)
1838 /* We found no match. */
1839 as_bad (_("suffix or operands invalid for `%s'"),
1840 current_templates
->start
->name
);
1844 if (!quiet_warnings
)
1847 && ((i
.types
[0] & JumpAbsolute
)
1848 != (t
->operand_types
[0] & JumpAbsolute
)))
1850 as_warn (_("indirect %s without `*'"), t
->name
);
1853 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1854 == (IsPrefix
|IgnoreSize
))
1856 /* Warn them that a data or address size prefix doesn't
1857 affect assembly of the next line of code. */
1858 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1862 /* Copy the template we found. */
1864 if (found_reverse_match
)
1866 /* If we found a reverse match we must alter the opcode
1867 direction bit. found_reverse_match holds bits to change
1868 (different for int & float insns). */
1870 i
.tm
.base_opcode
^= found_reverse_match
;
1872 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1873 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1876 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1879 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1880 i
.tm
.base_opcode
^= FloatR
;
1882 if (i
.tm
.opcode_modifier
& FWait
)
1883 if (! add_prefix (FWAIT_OPCODE
))
1886 /* Check string instruction segment overrides. */
1887 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1889 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1890 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1892 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1894 as_bad (_("`%s' operand %d must use `%%es' segment"),
1899 /* There's only ever one segment override allowed per instruction.
1900 This instruction possibly has a legal segment override on the
1901 second operand, so copy the segment to where non-string
1902 instructions store it, allowing common code. */
1903 i
.seg
[0] = i
.seg
[1];
1905 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1907 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1909 as_bad (_("`%s' operand %d must use `%%es' segment"),
1917 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1920 for (op
= i
.operands
; --op
>= 0;)
1921 if ((i
.types
[op
] & Reg
)
1922 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1924 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1925 i
.op
[op
].regs
->reg_name
);
1930 /* If matched instruction specifies an explicit instruction mnemonic
1932 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1934 if (i
.tm
.opcode_modifier
& Size16
)
1935 i
.suffix
= WORD_MNEM_SUFFIX
;
1936 else if (i
.tm
.opcode_modifier
& Size64
)
1937 i
.suffix
= QWORD_MNEM_SUFFIX
;
1939 i
.suffix
= LONG_MNEM_SUFFIX
;
1941 else if (i
.reg_operands
)
1943 /* If there's no instruction mnemonic suffix we try to invent one
1944 based on register operands. */
1947 /* We take i.suffix from the last register operand specified,
1948 Destination register type is more significant than source
1951 for (op
= i
.operands
; --op
>= 0;)
1952 if ((i
.types
[op
] & Reg
)
1953 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1955 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1956 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1957 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1962 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1965 for (op
= i
.operands
; --op
>= 0;)
1967 /* If this is an eight bit register, it's OK. If it's
1968 the 16 or 32 bit version of an eight bit register,
1969 we will just use the low portion, and that's OK too. */
1970 if (i
.types
[op
] & Reg8
)
1973 /* movzx and movsx should not generate this warning. */
1975 && (i
.tm
.base_opcode
== 0xfb7
1976 || i
.tm
.base_opcode
== 0xfb6
1977 || i
.tm
.base_opcode
== 0x63
1978 || i
.tm
.base_opcode
== 0xfbe
1979 || i
.tm
.base_opcode
== 0xfbf))
1982 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1984 /* Check that the template allows eight bit regs
1985 This kills insns such as `orb $1,%edx', which
1986 maybe should be allowed. */
1987 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1991 /* Prohibit these changes in the 64bit mode, since
1992 the lowering is more complicated. */
1993 if (flag_code
== CODE_64BIT
1994 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1995 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1996 i
.op
[op
].regs
->reg_name
,
1998 #if REGISTER_WARNINGS
2000 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2001 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2002 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
2003 i
.op
[op
].regs
->reg_name
,
2008 /* Any other register is bad. */
2009 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2011 | Control
| Debug
| Test
2012 | FloatReg
| FloatAcc
))
2014 as_bad (_("`%%%s' not allowed with `%s%c'"),
2015 i
.op
[op
].regs
->reg_name
,
2022 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2026 for (op
= i
.operands
; --op
>= 0;)
2027 /* Reject eight bit registers, except where the template
2028 requires them. (eg. movzb) */
2029 if ((i
.types
[op
] & Reg8
) != 0
2030 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2032 as_bad (_("`%%%s' not allowed with `%s%c'"),
2033 i
.op
[op
].regs
->reg_name
,
2038 /* Warn if the e prefix on a general reg is missing. */
2039 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2040 && (i
.types
[op
] & Reg16
) != 0
2041 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2043 /* Prohibit these changes in the 64bit mode, since
2044 the lowering is more complicated. */
2045 if (flag_code
== CODE_64BIT
)
2046 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2047 i
.op
[op
].regs
->reg_name
,
2049 #if REGISTER_WARNINGS
2051 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2052 (i
.op
[op
].regs
+ 8)->reg_name
,
2053 i
.op
[op
].regs
->reg_name
,
2057 /* Warn if the r prefix on a general reg is missing. */
2058 else if ((i
.types
[op
] & Reg64
) != 0
2059 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2061 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2062 i
.op
[op
].regs
->reg_name
,
2066 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2070 for (op
= i
.operands
; --op
>= 0; )
2071 /* Reject eight bit registers, except where the template
2072 requires them. (eg. movzb) */
2073 if ((i
.types
[op
] & Reg8
) != 0
2074 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2076 as_bad (_("`%%%s' not allowed with `%s%c'"),
2077 i
.op
[op
].regs
->reg_name
,
2082 /* Warn if the e prefix on a general reg is missing. */
2083 else if (((i
.types
[op
] & Reg16
) != 0
2084 || (i
.types
[op
] & Reg32
) != 0)
2085 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2087 /* Prohibit these changes in the 64bit mode, since
2088 the lowering is more complicated. */
2089 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2090 i
.op
[op
].regs
->reg_name
,
2094 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2097 for (op
= i
.operands
; --op
>= 0;)
2098 /* Reject eight bit registers, except where the template
2099 requires them. (eg. movzb) */
2100 if ((i
.types
[op
] & Reg8
) != 0
2101 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2103 as_bad (_("`%%%s' not allowed with `%s%c'"),
2104 i
.op
[op
].regs
->reg_name
,
2109 /* Warn if the e prefix on a general reg is present. */
2110 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2111 && (i
.types
[op
] & Reg32
) != 0
2112 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2114 /* Prohibit these changes in the 64bit mode, since
2115 the lowering is more complicated. */
2116 if (flag_code
== CODE_64BIT
)
2117 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2118 i
.op
[op
].regs
->reg_name
,
2121 #if REGISTER_WARNINGS
2122 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2123 (i
.op
[op
].regs
- 8)->reg_name
,
2124 i
.op
[op
].regs
->reg_name
,
2129 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2130 /* Do nothing if the instruction is going to ignore the prefix. */
2135 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2137 i
.suffix
= stackop_size
;
2139 /* Make still unresolved immediate matches conform to size of immediate
2140 given in i.suffix. Note: overlap2 cannot be an immediate! */
2141 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2142 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2143 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2144 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2148 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2149 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2150 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2152 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2153 || overlap0
== (Imm16
| Imm32
)
2154 || overlap0
== (Imm16
| Imm32S
))
2157 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2159 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2160 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2161 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2163 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2167 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2168 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2169 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2170 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2174 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2175 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2176 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2178 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2179 || overlap1
== (Imm16
| Imm32
)
2180 || overlap1
== (Imm16
| Imm32S
))
2183 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2185 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2186 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2187 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2189 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2193 assert ((overlap2
& Imm
) == 0);
2195 i
.types
[0] = overlap0
;
2196 if (overlap0
& ImplicitRegister
)
2198 if (overlap0
& Imm1
)
2199 i
.imm_operands
= 0; /* kludge for shift insns. */
2201 i
.types
[1] = overlap1
;
2202 if (overlap1
& ImplicitRegister
)
2205 i
.types
[2] = overlap2
;
2206 if (overlap2
& ImplicitRegister
)
2209 /* Finalize opcode. First, we change the opcode based on the operand
2210 size given by i.suffix: We need not change things for byte insns. */
2212 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2214 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2218 /* For movzx and movsx, need to check the register type. */
2220 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2221 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2223 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2225 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2226 if (!add_prefix (prefix
))
2230 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2232 /* It's not a byte, select word/dword operation. */
2233 if (i
.tm
.opcode_modifier
& W
)
2235 if (i
.tm
.opcode_modifier
& ShortForm
)
2236 i
.tm
.base_opcode
|= 8;
2238 i
.tm
.base_opcode
|= 1;
2240 /* Now select between word & dword operations via the operand
2241 size prefix, except for instructions that will ignore this
2243 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2244 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2245 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2247 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2248 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2249 prefix
= ADDR_PREFIX_OPCODE
;
2251 if (! add_prefix (prefix
))
2255 /* Set mode64 for an operand. */
2256 if (i
.suffix
== QWORD_MNEM_SUFFIX
2257 && !(i
.tm
.opcode_modifier
& NoRex64
))
2260 if (flag_code
< CODE_64BIT
)
2262 as_bad (_("64bit operations available only in 64bit modes."));
2267 /* Size floating point instruction. */
2268 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2270 if (i
.tm
.opcode_modifier
& FloatMF
)
2271 i
.tm
.base_opcode
^= 4;
2275 if (i
.tm
.opcode_modifier
& ImmExt
)
2277 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2278 opcode suffix which is coded in the same place as an 8-bit
2279 immediate field would be. Here we fake an 8-bit immediate
2280 operand from the opcode suffix stored in tm.extension_opcode. */
2284 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2286 exp
= &im_expressions
[i
.imm_operands
++];
2287 i
.op
[i
.operands
].imms
= exp
;
2288 i
.types
[i
.operands
++] = Imm8
;
2289 exp
->X_op
= O_constant
;
2290 exp
->X_add_number
= i
.tm
.extension_opcode
;
2291 i
.tm
.extension_opcode
= None
;
2294 /* For insns with operands there are more diddles to do to the opcode. */
2297 /* Default segment register this instruction will use
2298 for memory accesses. 0 means unknown.
2299 This is only for optimizing out unnecessary segment overrides. */
2300 const seg_entry
*default_seg
= 0;
2302 /* The imul $imm, %reg instruction is converted into
2303 imul $imm, %reg, %reg, and the clr %reg instruction
2304 is converted into xor %reg, %reg. */
2305 if (i
.tm
.opcode_modifier
& regKludge
)
2307 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2308 /* Pretend we saw the extra register operand. */
2309 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2310 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2311 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2315 if (i
.tm
.opcode_modifier
& ShortForm
)
2317 /* The register or float register operand is in operand 0 or 1. */
2318 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2319 /* Register goes in low 3 bits of opcode. */
2320 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2321 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2323 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2325 /* Warn about some common errors, but press on regardless.
2326 The first case can be generated by gcc (<= 2.8.1). */
2327 if (i
.operands
== 2)
2329 /* Reversed arguments on faddp, fsubp, etc. */
2330 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2331 i
.op
[1].regs
->reg_name
,
2332 i
.op
[0].regs
->reg_name
);
2336 /* Extraneous `l' suffix on fp insn. */
2337 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2338 i
.op
[0].regs
->reg_name
);
2342 else if (i
.tm
.opcode_modifier
& Modrm
)
2344 /* The opcode is completed (modulo i.tm.extension_opcode which
2345 must be put into the modrm byte).
2346 Now, we make the modrm & index base bytes based on all the
2347 info we've collected. */
2349 /* i.reg_operands MUST be the number of real register operands;
2350 implicit registers do not count. */
2351 if (i
.reg_operands
== 2)
2353 unsigned int source
, dest
;
2354 source
= ((i
.types
[0]
2355 & (Reg
| RegMMX
| RegXMM
2357 | Control
| Debug
| Test
))
2362 /* One of the register operands will be encoded in the
2363 i.tm.reg field, the other in the combined i.tm.mode
2364 and i.tm.regmem fields. If no form of this
2365 instruction supports a memory destination operand,
2366 then we assume the source operand may sometimes be
2367 a memory operand and so we need to store the
2368 destination in the i.rm.reg field. */
2369 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2371 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2372 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2373 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2375 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2380 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2381 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2382 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2384 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2389 { /* If it's not 2 reg operands... */
2392 unsigned int fake_zero_displacement
= 0;
2393 unsigned int op
= ((i
.types
[0] & AnyMem
)
2395 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2402 if (! i
.disp_operands
)
2403 fake_zero_displacement
= 1;
2406 /* Operand is just <disp> */
2407 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2409 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2410 i
.types
[op
] &= ~Disp
;
2411 i
.types
[op
] |= Disp16
;
2413 else if (flag_code
!= CODE_64BIT
)
2415 i
.rm
.regmem
= NO_BASE_REGISTER
;
2416 i
.types
[op
] &= ~Disp
;
2417 i
.types
[op
] |= Disp32
;
2421 /* 64bit mode overwrites the 32bit
2422 absolute addressing by RIP relative
2423 addressing and absolute addressing
2424 is encoded by one of the redundant
2427 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2428 i
.sib
.base
= NO_BASE_REGISTER
;
2429 i
.sib
.index
= NO_INDEX_REGISTER
;
2430 i
.types
[op
] &= ~Disp
;
2431 i
.types
[op
] |= Disp32S
;
2434 else /* ! i.base_reg && i.index_reg */
2436 i
.sib
.index
= i
.index_reg
->reg_num
;
2437 i
.sib
.base
= NO_BASE_REGISTER
;
2438 i
.sib
.scale
= i
.log2_scale_factor
;
2439 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2440 i
.types
[op
] &= ~Disp
;
2441 if (flag_code
!= CODE_64BIT
)
2442 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2444 i
.types
[op
] |= Disp32S
;
2445 if (i
.index_reg
->reg_flags
& RegRex
)
2449 /* RIP addressing for 64bit mode. */
2450 else if (i
.base_reg
->reg_type
== BaseIndex
)
2452 i
.rm
.regmem
= NO_BASE_REGISTER
;
2453 i
.types
[op
] &= ~Disp
;
2454 i
.types
[op
] |= Disp32S
;
2455 i
.flags
[op
] = Operand_PCrel
;
2457 else if (i
.base_reg
->reg_type
& Reg16
)
2459 switch (i
.base_reg
->reg_num
)
2464 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2465 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2472 if ((i
.types
[op
] & Disp
) == 0)
2474 /* fake (%bp) into 0(%bp) */
2475 i
.types
[op
] |= Disp8
;
2476 fake_zero_displacement
= 1;
2479 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2480 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2482 default: /* (%si) -> 4 or (%di) -> 5 */
2483 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2485 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2487 else /* i.base_reg and 32/64 bit mode */
2489 if (flag_code
== CODE_64BIT
2490 && (i
.types
[op
] & Disp
))
2492 if (i
.types
[op
] & Disp8
)
2493 i
.types
[op
] = Disp8
| Disp32S
;
2495 i
.types
[op
] = Disp32S
;
2497 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2498 if (i
.base_reg
->reg_flags
& RegRex
)
2500 i
.sib
.base
= i
.base_reg
->reg_num
;
2501 /* x86-64 ignores REX prefix bit here to avoid
2502 decoder complications. */
2503 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2506 if (i
.disp_operands
== 0)
2508 fake_zero_displacement
= 1;
2509 i
.types
[op
] |= Disp8
;
2512 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2516 i
.sib
.scale
= i
.log2_scale_factor
;
2519 /* <disp>(%esp) becomes two byte modrm
2520 with no index register. We've already
2521 stored the code for esp in i.rm.regmem
2522 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2523 base register besides %esp will not use
2524 the extra modrm byte. */
2525 i
.sib
.index
= NO_INDEX_REGISTER
;
2526 #if ! SCALE1_WHEN_NO_INDEX
2527 /* Another case where we force the second
2529 if (i
.log2_scale_factor
)
2530 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2535 i
.sib
.index
= i
.index_reg
->reg_num
;
2536 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2537 if (i
.index_reg
->reg_flags
& RegRex
)
2540 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2543 if (fake_zero_displacement
)
2545 /* Fakes a zero displacement assuming that i.types[op]
2546 holds the correct displacement size. */
2549 assert (i
.op
[op
].disps
== 0);
2550 exp
= &disp_expressions
[i
.disp_operands
++];
2551 i
.op
[op
].disps
= exp
;
2552 exp
->X_op
= O_constant
;
2553 exp
->X_add_number
= 0;
2554 exp
->X_add_symbol
= (symbolS
*) 0;
2555 exp
->X_op_symbol
= (symbolS
*) 0;
2559 /* Fill in i.rm.reg or i.rm.regmem field with register
2560 operand (if any) based on i.tm.extension_opcode.
2561 Again, we must be careful to make sure that
2562 segment/control/debug/test/MMX registers are coded
2563 into the i.rm.reg field. */
2568 & (Reg
| RegMMX
| RegXMM
2570 | Control
| Debug
| Test
))
2573 & (Reg
| RegMMX
| RegXMM
2575 | Control
| Debug
| Test
))
2578 /* If there is an extension opcode to put here, the
2579 register number must be put into the regmem field. */
2580 if (i
.tm
.extension_opcode
!= None
)
2582 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2583 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2588 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2589 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2593 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2594 we must set it to 3 to indicate this is a register
2595 operand in the regmem field. */
2596 if (!i
.mem_operands
)
2600 /* Fill in i.rm.reg field with extension opcode (if any). */
2601 if (i
.tm
.extension_opcode
!= None
)
2602 i
.rm
.reg
= i
.tm
.extension_opcode
;
2605 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2607 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2608 && i
.op
[0].regs
->reg_num
== 1)
2610 as_bad (_("you can't `pop %%cs'"));
2613 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2614 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2617 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2621 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2623 /* For the string instructions that allow a segment override
2624 on one of their operands, the default segment is ds. */
2628 /* If a segment was explicitly specified,
2629 and the specified segment is not the default,
2630 use an opcode prefix to select it.
2631 If we never figured out what the default segment is,
2632 then default_seg will be zero at this point,
2633 and the specified segment prefix will always be used. */
2634 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2636 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2640 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2642 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2643 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2647 /* Handle conversion of 'int $3' --> special int3 insn. */
2648 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2650 i
.tm
.base_opcode
= INT3_OPCODE
;
2654 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2655 && i
.op
[0].disps
->X_op
== O_constant
)
2657 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2658 the absolute address given by the constant. Since ix86 jumps and
2659 calls are pc relative, we need to generate a reloc. */
2660 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2661 i
.op
[0].disps
->X_op
= O_symbol
;
2664 if (i
.tm
.opcode_modifier
& Rex64
)
2667 /* For 8bit registers we would need an empty rex prefix.
2668 Also in the case instruction is already having prefix,
2669 we need to convert old registers to new ones. */
2671 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2672 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2673 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2674 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2678 for (x
= 0; x
< 2; x
++)
2680 /* Look for 8bit operand that does use old registers. */
2681 if (i
.types
[x
] & Reg8
2682 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2684 /* In case it is "hi" register, give up. */
2685 if (i
.op
[x
].regs
->reg_num
> 3)
2686 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2687 i
.op
[x
].regs
->reg_name
);
2689 /* Otherwise it is equivalent to the extended register.
2690 Since the encoding don't change this is merely cosmetical
2691 cleanup for debug output. */
2693 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2698 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2700 | (i
.rex
.mode64
? 8 : 0)
2701 | (i
.rex
.extX
? 4 : 0)
2702 | (i
.rex
.extY
? 2 : 0)
2703 | (i
.rex
.extZ
? 1 : 0));
2705 /* We are ready to output the insn. */
2710 if (i
.tm
.opcode_modifier
& Jump
)
2716 if (flag_code
== CODE_16BIT
)
2720 if (i
.prefix
[DATA_PREFIX
])
2726 if (i
.prefix
[REX_PREFIX
])
2732 if (i
.prefixes
!= 0 && !intel_syntax
)
2733 as_warn (_("skipping prefixes on this instruction"));
2735 /* It's always a symbol; End frag & setup for relax.
2736 Make sure there is enough room in this frag for the largest
2737 instruction we may generate in md_convert_frag. This is 2
2738 bytes for the opcode and room for the prefix and largest
2740 frag_grow (prefix
+ 2 + 4);
2741 insn_size
+= prefix
+ 1;
2742 /* Prefix and 1 opcode byte go in fr_fix. */
2743 p
= frag_more (prefix
+ 1);
2744 if (i
.prefix
[DATA_PREFIX
])
2745 *p
++ = DATA_PREFIX_OPCODE
;
2746 if (i
.prefix
[REX_PREFIX
])
2747 *p
++ = i
.prefix
[REX_PREFIX
];
2748 *p
= i
.tm
.base_opcode
;
2749 /* 1 possible extra opcode + displacement go in var part.
2750 Pass reloc in fr_var. */
2751 frag_var (rs_machine_dependent
,
2754 ((unsigned char) *p
== JUMP_PC_RELATIVE
2755 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2756 : ((cpu_arch_flags
& Cpu386
) != 0
2757 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2758 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2759 i
.op
[0].disps
->X_add_symbol
,
2760 i
.op
[0].disps
->X_add_number
,
2763 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2767 if (i
.tm
.opcode_modifier
& JumpByte
)
2769 /* This is a loop or jecxz type instruction. */
2771 if (i
.prefix
[ADDR_PREFIX
])
2774 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2783 if (flag_code
== CODE_16BIT
)
2786 if (i
.prefix
[DATA_PREFIX
])
2789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2799 if (i
.prefix
[REX_PREFIX
])
2801 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2806 if (i
.prefixes
!= 0 && !intel_syntax
)
2807 as_warn (_("skipping prefixes on this instruction"));
2809 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2811 insn_size
+= 1 + size
;
2812 p
= frag_more (1 + size
);
2816 /* Opcode can be at most two bytes. */
2817 insn_size
+= 2 + size
;
2818 p
= frag_more (2 + size
);
2819 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2821 *p
++ = i
.tm
.base_opcode
& 0xff;
2823 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2824 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2826 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2833 if (flag_code
== CODE_16BIT
)
2837 if (i
.prefix
[DATA_PREFIX
])
2843 if (i
.prefix
[REX_PREFIX
])
2853 if (i
.prefixes
!= 0 && !intel_syntax
)
2854 as_warn (_("skipping prefixes on this instruction"));
2856 /* 1 opcode; 2 segment; offset */
2857 insn_size
+= prefix
+ 1 + 2 + size
;
2858 p
= frag_more (prefix
+ 1 + 2 + size
);
2860 if (i
.prefix
[DATA_PREFIX
])
2861 *p
++ = DATA_PREFIX_OPCODE
;
2863 if (i
.prefix
[REX_PREFIX
])
2864 *p
++ = i
.prefix
[REX_PREFIX
];
2866 *p
++ = i
.tm
.base_opcode
;
2867 if (i
.op
[1].imms
->X_op
== O_constant
)
2869 offsetT n
= i
.op
[1].imms
->X_add_number
;
2872 && !fits_in_unsigned_word (n
)
2873 && !fits_in_signed_word (n
))
2875 as_bad (_("16-bit jump out of range"));
2878 md_number_to_chars (p
, n
, size
);
2881 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2882 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2883 if (i
.op
[0].imms
->X_op
!= O_constant
)
2884 as_bad (_("can't handle non absolute segment in `%s'"),
2886 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2890 /* Output normal instructions here. */
2893 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2894 byte for the SSE instructions to specify prefix they require. */
2895 if (i
.tm
.base_opcode
& 0xff0000)
2896 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2898 /* The prefix bytes. */
2900 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2907 md_number_to_chars (p
, (valueT
) *q
, 1);
2911 /* Now the opcode; be careful about word order here! */
2912 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2915 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2921 /* Put out high byte first: can't use md_number_to_chars! */
2922 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2923 *p
= i
.tm
.base_opcode
& 0xff;
2926 /* Now the modrm byte and sib byte (if present). */
2927 if (i
.tm
.opcode_modifier
& Modrm
)
2931 md_number_to_chars (p
,
2932 (valueT
) (i
.rm
.regmem
<< 0
2936 /* If i.rm.regmem == ESP (4)
2937 && i.rm.mode != (Register mode)
2939 ==> need second modrm byte. */
2940 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2942 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2946 md_number_to_chars (p
,
2947 (valueT
) (i
.sib
.base
<< 0
2949 | i
.sib
.scale
<< 6),
2954 if (i
.disp_operands
)
2956 register unsigned int n
;
2958 for (n
= 0; n
< i
.operands
; n
++)
2960 if (i
.types
[n
] & Disp
)
2962 if (i
.op
[n
].disps
->X_op
== O_constant
)
2968 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2971 if (i
.types
[n
] & Disp8
)
2973 if (i
.types
[n
] & Disp64
)
2976 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2979 p
= frag_more (size
);
2980 md_number_to_chars (p
, val
, size
);
2986 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2988 /* The PC relative address is computed relative
2989 to the instruction boundary, so in case immediate
2990 fields follows, we need to adjust the value. */
2991 if (pcrel
&& i
.imm_operands
)
2994 register unsigned int n1
;
2996 for (n1
= 0; n1
< i
.operands
; n1
++)
2997 if (i
.types
[n1
] & Imm
)
2999 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3002 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3004 if (i
.types
[n1
] & Imm64
)
3009 /* We should find the immediate. */
3010 if (n1
== i
.operands
)
3012 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3015 if (i
.types
[n
] & Disp32S
)
3018 if (i
.types
[n
] & (Disp16
| Disp64
))
3021 if (i
.types
[n
] & Disp64
)
3026 p
= frag_more (size
);
3027 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3028 i
.op
[n
].disps
, pcrel
,
3029 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
3035 /* Output immediate. */
3038 register unsigned int n
;
3040 for (n
= 0; n
< i
.operands
; n
++)
3042 if (i
.types
[n
] & Imm
)
3044 if (i
.op
[n
].imms
->X_op
== O_constant
)
3050 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3053 if (i
.types
[n
] & (Imm8
| Imm8S
))
3055 else if (i
.types
[n
] & Imm64
)
3058 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3061 p
= frag_more (size
);
3062 md_number_to_chars (p
, val
, size
);
3066 /* Not absolute_section.
3067 Need a 32-bit fixup (don't support 8bit
3068 non-absolute imms). Try to support other
3070 #ifdef BFD_ASSEMBLER
3071 enum bfd_reloc_code_real reloc_type
;
3078 if ((i
.types
[n
] & (Imm32S
))
3079 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3081 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3084 if (i
.types
[n
] & (Imm8
| Imm8S
))
3086 if (i
.types
[n
] & Imm64
)
3091 p
= frag_more (size
);
3092 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3093 #ifdef BFD_ASSEMBLER
3094 if (reloc_type
== BFD_RELOC_32
3096 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3097 && (i
.op
[n
].imms
->X_op
== O_symbol
3098 || (i
.op
[n
].imms
->X_op
== O_add
3099 && ((symbol_get_value_expression
3100 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3103 /* We don't support dynamic linking on x86-64 yet. */
3104 if (flag_code
== CODE_64BIT
)
3106 reloc_type
= BFD_RELOC_386_GOTPC
;
3107 i
.op
[n
].imms
->X_add_number
+= 3;
3110 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3111 i
.op
[n
].imms
, 0, reloc_type
);
3118 dwarf2_emit_insn (insn_size
);
3125 #endif /* DEBUG386 */
3129 static int i386_immediate
PARAMS ((char *));
3132 i386_immediate (imm_start
)
3135 char *save_input_line_pointer
;
3139 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3141 as_bad (_("only 1 or 2 immediate operands are allowed"));
3145 exp
= &im_expressions
[i
.imm_operands
++];
3146 i
.op
[this_operand
].imms
= exp
;
3148 if (is_space_char (*imm_start
))
3151 save_input_line_pointer
= input_line_pointer
;
3152 input_line_pointer
= imm_start
;
3156 /* We can have operands of the form
3157 <symbol>@GOTOFF+<nnn>
3158 Take the easy way out here and copy everything
3159 into a temporary buffer... */
3162 cp
= strchr (input_line_pointer
, '@');
3169 /* GOT relocations are not supported in 16 bit mode. */
3170 if (flag_code
== CODE_16BIT
)
3171 as_bad (_("GOT relocations not supported in 16 bit mode"));
3173 if (GOT_symbol
== NULL
)
3174 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3176 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3178 if (flag_code
== CODE_64BIT
)
3179 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3181 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3184 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3186 if (flag_code
== CODE_64BIT
)
3187 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3188 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3191 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3193 if (flag_code
== CODE_64BIT
)
3194 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3196 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3199 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3201 if (flag_code
== CODE_64BIT
)
3202 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3204 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3208 as_bad (_("bad reloc specifier in expression"));
3210 /* Replace the relocation token with ' ', so that errors like
3211 foo@GOTOFF1 will be detected. */
3212 first
= cp
- input_line_pointer
;
3213 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3214 memcpy (tmpbuf
, input_line_pointer
, first
);
3215 tmpbuf
[first
] = ' ';
3216 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3217 input_line_pointer
= tmpbuf
;
3222 exp_seg
= expression (exp
);
3225 if (*input_line_pointer
)
3226 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3228 input_line_pointer
= save_input_line_pointer
;
3230 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3232 /* Missing or bad expr becomes absolute 0. */
3233 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3235 exp
->X_op
= O_constant
;
3236 exp
->X_add_number
= 0;
3237 exp
->X_add_symbol
= (symbolS
*) 0;
3238 exp
->X_op_symbol
= (symbolS
*) 0;
3240 else if (exp
->X_op
== O_constant
)
3242 /* Size it properly later. */
3243 i
.types
[this_operand
] |= Imm64
;
3244 /* If BFD64, sign extend val. */
3245 if (!use_rela_relocations
)
3246 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3247 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3249 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3251 #ifdef BFD_ASSEMBLER
3252 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3254 && exp_seg
!= text_section
3255 && exp_seg
!= data_section
3256 && exp_seg
!= bss_section
3257 && exp_seg
!= undefined_section
3258 #ifdef BFD_ASSEMBLER
3259 && !bfd_is_com_section (exp_seg
)
3263 #ifdef BFD_ASSEMBLER
3264 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3266 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3273 /* This is an address. The size of the address will be
3274 determined later, depending on destination register,
3275 suffix, or the default for the section. */
3276 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3282 static int i386_scale
PARAMS ((char *));
3288 if (!isdigit (*scale
))
3295 i
.log2_scale_factor
= 0;
3298 i
.log2_scale_factor
= 1;
3301 i
.log2_scale_factor
= 2;
3304 i
.log2_scale_factor
= 3;
3308 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3312 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3314 as_warn (_("scale factor of %d without an index register"),
3315 1 << i
.log2_scale_factor
);
3316 #if SCALE1_WHEN_NO_INDEX
3317 i
.log2_scale_factor
= 0;
3323 static int i386_displacement
PARAMS ((char *, char *));
3326 i386_displacement (disp_start
, disp_end
)
3330 register expressionS
*exp
;
3332 char *save_input_line_pointer
;
3333 int bigdisp
= Disp32
;
3335 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3337 if (flag_code
== CODE_64BIT
)
3339 i
.types
[this_operand
] |= bigdisp
;
3341 exp
= &disp_expressions
[i
.disp_operands
];
3342 i
.op
[this_operand
].disps
= exp
;
3344 save_input_line_pointer
= input_line_pointer
;
3345 input_line_pointer
= disp_start
;
3346 END_STRING_AND_SAVE (disp_end
);
3348 #ifndef GCC_ASM_O_HACK
3349 #define GCC_ASM_O_HACK 0
3352 END_STRING_AND_SAVE (disp_end
+ 1);
3353 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3354 && displacement_string_end
[-1] == '+')
3356 /* This hack is to avoid a warning when using the "o"
3357 constraint within gcc asm statements.
3360 #define _set_tssldt_desc(n,addr,limit,type) \
3361 __asm__ __volatile__ ( \
3363 "movw %w1,2+%0\n\t" \
3365 "movb %b1,4+%0\n\t" \
3366 "movb %4,5+%0\n\t" \
3367 "movb $0,6+%0\n\t" \
3368 "movb %h1,7+%0\n\t" \
3370 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3372 This works great except that the output assembler ends
3373 up looking a bit weird if it turns out that there is
3374 no offset. You end up producing code that looks like:
3387 So here we provide the missing zero. */
3389 *displacement_string_end
= '0';
3394 /* We can have operands of the form
3395 <symbol>@GOTOFF+<nnn>
3396 Take the easy way out here and copy everything
3397 into a temporary buffer... */
3400 cp
= strchr (input_line_pointer
, '@');
3407 /* GOT relocations are not supported in 16 bit mode. */
3408 if (flag_code
== CODE_16BIT
)
3409 as_bad (_("GOT relocations not supported in 16 bit mode"));
3411 if (GOT_symbol
== NULL
)
3412 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3414 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3416 if (flag_code
== CODE_64BIT
)
3417 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3419 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3422 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3424 if (flag_code
== CODE_64BIT
)
3425 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3426 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3429 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3431 if (flag_code
!= CODE_64BIT
)
3432 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3433 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3436 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3438 if (flag_code
== CODE_64BIT
)
3439 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3441 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3445 as_bad (_("bad reloc specifier in expression"));
3447 /* Replace the relocation token with ' ', so that errors like
3448 foo@GOTOFF1 will be detected. */
3449 first
= cp
- input_line_pointer
;
3450 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3451 memcpy (tmpbuf
, input_line_pointer
, first
);
3452 tmpbuf
[first
] = ' ';
3453 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3454 input_line_pointer
= tmpbuf
;
3459 exp_seg
= expression (exp
);
3461 #ifdef BFD_ASSEMBLER
3462 /* We do this to make sure that the section symbol is in
3463 the symbol table. We will ultimately change the relocation
3464 to be relative to the beginning of the section. */
3465 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3466 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3468 if (S_IS_LOCAL (exp
->X_add_symbol
)
3469 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3470 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3471 assert (exp
->X_op
== O_symbol
);
3472 exp
->X_op
= O_subtract
;
3473 exp
->X_op_symbol
= GOT_symbol
;
3474 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3475 i
.disp_reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3477 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3482 if (*input_line_pointer
)
3483 as_bad (_("ignoring junk `%s' after expression"),
3484 input_line_pointer
);
3486 RESTORE_END_STRING (disp_end
+ 1);
3488 RESTORE_END_STRING (disp_end
);
3489 input_line_pointer
= save_input_line_pointer
;
3491 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3493 /* Missing or bad expr becomes absolute 0. */
3494 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3496 exp
->X_op
= O_constant
;
3497 exp
->X_add_number
= 0;
3498 exp
->X_add_symbol
= (symbolS
*) 0;
3499 exp
->X_op_symbol
= (symbolS
*) 0;
3502 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3503 if (exp
->X_op
!= O_constant
3504 #ifdef BFD_ASSEMBLER
3505 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3507 && exp_seg
!= text_section
3508 && exp_seg
!= data_section
3509 && exp_seg
!= bss_section
3510 && exp_seg
!= undefined_section
)
3512 #ifdef BFD_ASSEMBLER
3513 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3515 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3520 else if (flag_code
== CODE_64BIT
)
3521 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3525 static int i386_index_check
PARAMS ((const char *));
3527 /* Make sure the memory operand we've been dealt is valid.
3528 Return 1 on success, 0 on a failure. */
3531 i386_index_check (operand_string
)
3532 const char *operand_string
;
3535 #if INFER_ADDR_PREFIX
3541 if (flag_code
== CODE_64BIT
)
3545 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3546 && (i
.base_reg
->reg_type
!= BaseIndex
3549 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3550 != (Reg64
|BaseIndex
))))
3555 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3559 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3560 != (Reg16
|BaseIndex
)))
3562 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3563 != (Reg16
|BaseIndex
))
3565 && i
.base_reg
->reg_num
< 6
3566 && i
.index_reg
->reg_num
>= 6
3567 && i
.log2_scale_factor
== 0))))
3574 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3576 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3577 != (Reg32
|BaseIndex
))))
3583 #if INFER_ADDR_PREFIX
3584 if (flag_code
!= CODE_64BIT
3585 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3587 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3589 /* Change the size of any displacement too. At most one of
3590 Disp16 or Disp32 is set.
3591 FIXME. There doesn't seem to be any real need for separate
3592 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3593 Removing them would probably clean up the code quite a lot. */
3594 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3595 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3600 as_bad (_("`%s' is not a valid base/index expression"),
3604 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3606 flag_code_names
[flag_code
]);
3612 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3616 i386_operand (operand_string
)
3617 char *operand_string
;
3621 char *op_string
= operand_string
;
3623 if (is_space_char (*op_string
))
3626 /* We check for an absolute prefix (differentiating,
3627 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3628 if (*op_string
== ABSOLUTE_PREFIX
)
3631 if (is_space_char (*op_string
))
3633 i
.types
[this_operand
] |= JumpAbsolute
;
3636 /* Check if operand is a register. */
3637 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3638 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3640 /* Check for a segment override by searching for ':' after a
3641 segment register. */
3643 if (is_space_char (*op_string
))
3645 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3650 i
.seg
[i
.mem_operands
] = &es
;
3653 i
.seg
[i
.mem_operands
] = &cs
;
3656 i
.seg
[i
.mem_operands
] = &ss
;
3659 i
.seg
[i
.mem_operands
] = &ds
;
3662 i
.seg
[i
.mem_operands
] = &fs
;
3665 i
.seg
[i
.mem_operands
] = &gs
;
3669 /* Skip the ':' and whitespace. */
3671 if (is_space_char (*op_string
))
3674 if (!is_digit_char (*op_string
)
3675 && !is_identifier_char (*op_string
)
3676 && *op_string
!= '('
3677 && *op_string
!= ABSOLUTE_PREFIX
)
3679 as_bad (_("bad memory operand `%s'"), op_string
);
3682 /* Handle case of %es:*foo. */
3683 if (*op_string
== ABSOLUTE_PREFIX
)
3686 if (is_space_char (*op_string
))
3688 i
.types
[this_operand
] |= JumpAbsolute
;
3690 goto do_memory_reference
;
3694 as_bad (_("junk `%s' after register"), op_string
);
3697 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3698 i
.op
[this_operand
].regs
= r
;
3701 else if (*op_string
== REGISTER_PREFIX
)
3703 as_bad (_("bad register name `%s'"), op_string
);
3706 else if (*op_string
== IMMEDIATE_PREFIX
)
3709 if (i
.types
[this_operand
] & JumpAbsolute
)
3711 as_bad (_("immediate operand illegal with absolute jump"));
3714 if (!i386_immediate (op_string
))
3717 else if (is_digit_char (*op_string
)
3718 || is_identifier_char (*op_string
)
3719 || *op_string
== '(')
3721 /* This is a memory reference of some sort. */
3724 /* Start and end of displacement string expression (if found). */
3725 char *displacement_string_start
;
3726 char *displacement_string_end
;
3728 do_memory_reference
:
3729 if ((i
.mem_operands
== 1
3730 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3731 || i
.mem_operands
== 2)
3733 as_bad (_("too many memory references for `%s'"),
3734 current_templates
->start
->name
);
3738 /* Check for base index form. We detect the base index form by
3739 looking for an ')' at the end of the operand, searching
3740 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3742 base_string
= op_string
+ strlen (op_string
);
3745 if (is_space_char (*base_string
))
3748 /* If we only have a displacement, set-up for it to be parsed later. */
3749 displacement_string_start
= op_string
;
3750 displacement_string_end
= base_string
+ 1;
3752 if (*base_string
== ')')
3755 unsigned int parens_balanced
= 1;
3756 /* We've already checked that the number of left & right ()'s are
3757 equal, so this loop will not be infinite. */
3761 if (*base_string
== ')')
3763 if (*base_string
== '(')
3766 while (parens_balanced
);
3768 temp_string
= base_string
;
3770 /* Skip past '(' and whitespace. */
3772 if (is_space_char (*base_string
))
3775 if (*base_string
== ','
3776 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3777 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3779 displacement_string_end
= temp_string
;
3781 i
.types
[this_operand
] |= BaseIndex
;
3785 base_string
= end_op
;
3786 if (is_space_char (*base_string
))
3790 /* There may be an index reg or scale factor here. */
3791 if (*base_string
== ',')
3794 if (is_space_char (*base_string
))
3797 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3798 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3800 base_string
= end_op
;
3801 if (is_space_char (*base_string
))
3803 if (*base_string
== ',')
3806 if (is_space_char (*base_string
))
3809 else if (*base_string
!= ')')
3811 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3816 else if (*base_string
== REGISTER_PREFIX
)
3818 as_bad (_("bad register name `%s'"), base_string
);
3822 /* Check for scale factor. */
3823 if (isdigit ((unsigned char) *base_string
))
3825 if (!i386_scale (base_string
))
3829 if (is_space_char (*base_string
))
3831 if (*base_string
!= ')')
3833 as_bad (_("expecting `)' after scale factor in `%s'"),
3838 else if (!i
.index_reg
)
3840 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3845 else if (*base_string
!= ')')
3847 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3852 else if (*base_string
== REGISTER_PREFIX
)
3854 as_bad (_("bad register name `%s'"), base_string
);
3859 /* If there's an expression beginning the operand, parse it,
3860 assuming displacement_string_start and
3861 displacement_string_end are meaningful. */
3862 if (displacement_string_start
!= displacement_string_end
)
3864 if (!i386_displacement (displacement_string_start
,
3865 displacement_string_end
))
3869 /* Special case for (%dx) while doing input/output op. */
3871 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3873 && i
.log2_scale_factor
== 0
3874 && i
.seg
[i
.mem_operands
] == 0
3875 && (i
.types
[this_operand
] & Disp
) == 0)
3877 i
.types
[this_operand
] = InOutPortReg
;
3881 if (i386_index_check (operand_string
) == 0)
3887 /* It's not a memory operand; argh! */
3888 as_bad (_("invalid char %s beginning operand %d `%s'"),
3889 output_invalid (*op_string
),
3894 return 1; /* Normal return. */
3897 /* md_estimate_size_before_relax()
3899 Called just before relax() for rs_machine_dependent frags. The x86
3900 assembler uses these frags to handle variable size jump
3903 Any symbol that is now undefined will not become defined.
3904 Return the correct fr_subtype in the frag.
3905 Return the initial "guess for variable size of frag" to caller.
3906 The guess is actually the growth beyond the fixed part. Whatever
3907 we do to grow the fixed or variable part contributes to our
3911 md_estimate_size_before_relax (fragP
, segment
)
3912 register fragS
*fragP
;
3913 register segT segment
;
3915 /* We've already got fragP->fr_subtype right; all we have to do is
3916 check for un-relaxable symbols. On an ELF system, we can't relax
3917 an externally visible symbol, because it may be overridden by a
3919 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3920 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3921 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3922 || S_IS_WEAK (fragP
->fr_symbol
)
3926 /* Symbol is undefined in this segment, or we need to keep a
3927 reloc so that weak symbols can be overridden. */
3928 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3929 #ifdef BFD_ASSEMBLER
3930 enum bfd_reloc_code_real reloc_type
;
3934 unsigned char *opcode
;
3937 if (fragP
->fr_var
!= NO_RELOC
)
3938 reloc_type
= fragP
->fr_var
;
3940 reloc_type
= BFD_RELOC_16_PCREL
;
3942 reloc_type
= BFD_RELOC_32_PCREL
;
3944 old_fr_fix
= fragP
->fr_fix
;
3945 opcode
= (unsigned char *) fragP
->fr_opcode
;
3947 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3950 /* Make jmp (0xeb) a (d)word displacement jump. */
3952 fragP
->fr_fix
+= size
;
3953 fix_new (fragP
, old_fr_fix
, size
,
3955 fragP
->fr_offset
, 1,
3960 if (no_cond_jump_promotion
)
3964 /* Negate the condition, and branch past an
3965 unconditional jump. */
3968 /* Insert an unconditional jump. */
3970 /* We added two extra opcode bytes, and have a two byte
3972 fragP
->fr_fix
+= 2 + 2;
3973 fix_new (fragP
, old_fr_fix
+ 2, 2,
3975 fragP
->fr_offset
, 1,
3982 if (no_cond_jump_promotion
)
3984 /* This changes the byte-displacement jump 0x7N
3985 to the (d)word-displacement jump 0x0f,0x8N. */
3986 opcode
[1] = opcode
[0] + 0x10;
3987 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3988 /* We've added an opcode byte. */
3989 fragP
->fr_fix
+= 1 + size
;
3990 fix_new (fragP
, old_fr_fix
+ 1, size
,
3992 fragP
->fr_offset
, 1,
3997 BAD_CASE (fragP
->fr_subtype
);
4001 return fragP
->fr_fix
- old_fr_fix
;
4003 /* Guess a short jump. */
4007 /* Called after relax() is finished.
4009 In: Address of frag.
4010 fr_type == rs_machine_dependent.
4011 fr_subtype is what the address relaxed to.
4013 Out: Any fixSs and constants are set up.
4014 Caller will turn frag into a ".space 0". */
4016 #ifndef BFD_ASSEMBLER
4018 md_convert_frag (headers
, sec
, fragP
)
4019 object_headers
*headers ATTRIBUTE_UNUSED
;
4020 segT sec ATTRIBUTE_UNUSED
;
4021 register fragS
*fragP
;
4024 md_convert_frag (abfd
, sec
, fragP
)
4025 bfd
*abfd ATTRIBUTE_UNUSED
;
4026 segT sec ATTRIBUTE_UNUSED
;
4027 register fragS
*fragP
;
4030 register unsigned char *opcode
;
4031 unsigned char *where_to_put_displacement
= NULL
;
4032 offsetT target_address
;
4033 offsetT opcode_address
;
4034 unsigned int extension
= 0;
4035 offsetT displacement_from_opcode_start
;
4037 opcode
= (unsigned char *) fragP
->fr_opcode
;
4039 /* Address we want to reach in file space. */
4040 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4041 #ifdef BFD_ASSEMBLER
4042 /* Not needed otherwise? */
4043 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
4046 /* Address opcode resides at in file space. */
4047 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4049 /* Displacement from opcode start to fill into instruction. */
4050 displacement_from_opcode_start
= target_address
- opcode_address
;
4052 if ((fragP
->fr_subtype
& BIG
) == 0)
4054 /* Don't have to change opcode. */
4055 extension
= 1; /* 1 opcode + 1 displacement */
4056 where_to_put_displacement
= &opcode
[1];
4060 if (no_cond_jump_promotion
4061 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4062 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4064 switch (fragP
->fr_subtype
)
4066 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4067 extension
= 4; /* 1 opcode + 4 displacement */
4069 where_to_put_displacement
= &opcode
[1];
4072 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4073 extension
= 2; /* 1 opcode + 2 displacement */
4075 where_to_put_displacement
= &opcode
[1];
4078 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4079 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4080 extension
= 5; /* 2 opcode + 4 displacement */
4081 opcode
[1] = opcode
[0] + 0x10;
4082 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4083 where_to_put_displacement
= &opcode
[2];
4086 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4087 extension
= 3; /* 2 opcode + 2 displacement */
4088 opcode
[1] = opcode
[0] + 0x10;
4089 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4090 where_to_put_displacement
= &opcode
[2];
4093 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4098 where_to_put_displacement
= &opcode
[3];
4102 BAD_CASE (fragP
->fr_subtype
);
4107 /* Now put displacement after opcode. */
4108 md_number_to_chars ((char *) where_to_put_displacement
,
4109 (valueT
) (displacement_from_opcode_start
- extension
),
4110 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4111 fragP
->fr_fix
+= extension
;
4114 /* Size of byte displacement jmp. */
4115 int md_short_jump_size
= 2;
4117 /* Size of dword displacement jmp. */
4118 int md_long_jump_size
= 5;
4120 /* Size of relocation record. */
4121 const int md_reloc_size
= 8;
4124 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4126 addressT from_addr
, to_addr
;
4127 fragS
*frag ATTRIBUTE_UNUSED
;
4128 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4132 offset
= to_addr
- (from_addr
+ 2);
4133 /* Opcode for byte-disp jump. */
4134 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4135 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4139 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4141 addressT from_addr
, to_addr
;
4142 fragS
*frag ATTRIBUTE_UNUSED
;
4143 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4147 offset
= to_addr
- (from_addr
+ 5);
4148 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4149 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4152 /* Apply a fixup (fixS) to segment data, once it has been determined
4153 by our caller that we have all the info we need to fix it up.
4155 On the 386, immediates, displacements, and data pointers are all in
4156 the same (little-endian) format, so we don't need to care about which
4160 md_apply_fix3 (fixP
, valp
, seg
)
4161 /* The fix we're to put in. */
4164 /* Pointer to the value of the bits. */
4167 /* Segment fix is from. */
4168 segT seg ATTRIBUTE_UNUSED
;
4170 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4171 valueT value
= *valp
;
4173 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4176 switch (fixP
->fx_r_type
)
4182 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4185 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4188 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4193 /* This is a hack. There should be a better way to handle this.
4194 This covers for the fact that bfd_install_relocation will
4195 subtract the current location (for partial_inplace, PC relative
4196 relocations); see more below. */
4197 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4198 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4199 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4200 && fixP
->fx_addsy
&& !use_rela_relocations
)
4203 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4205 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4208 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4211 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4213 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4216 || (symbol_section_p (fixP
->fx_addsy
)
4217 && fseg
!= absolute_section
))
4218 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4219 && ! S_IS_WEAK (fixP
->fx_addsy
)
4220 && S_IS_DEFINED (fixP
->fx_addsy
)
4221 && ! S_IS_COMMON (fixP
->fx_addsy
))
4223 /* Yes, we add the values in twice. This is because
4224 bfd_perform_relocation subtracts them out again. I think
4225 bfd_perform_relocation is broken, but I don't dare change
4227 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4231 #if defined (OBJ_COFF) && defined (TE_PE)
4232 /* For some reason, the PE format does not store a section
4233 address offset for a PC relative symbol. */
4234 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4235 value
+= md_pcrel_from (fixP
);
4239 /* Fix a few things - the dynamic linker expects certain values here,
4240 and we must not dissappoint it. */
4241 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4242 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4244 switch (fixP
->fx_r_type
)
4246 case BFD_RELOC_386_PLT32
:
4247 case BFD_RELOC_X86_64_PLT32
:
4248 /* Make the jump instruction point to the address of the operand. At
4249 runtime we merely add the offset to the actual PLT entry. */
4252 case BFD_RELOC_386_GOTPC
:
4254 /* This is tough to explain. We end up with this one if we have
4255 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4256 * here is to obtain the absolute address of the GOT, and it is strongly
4257 * preferable from a performance point of view to avoid using a runtime
4258 * relocation for this. The actual sequence of instructions often look
4264 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4266 * The call and pop essentially return the absolute address of
4267 * the label .L66 and store it in %ebx. The linker itself will
4268 * ultimately change the first operand of the addl so that %ebx points to
4269 * the GOT, but to keep things simple, the .o file must have this operand
4270 * set so that it generates not the absolute address of .L66, but the
4271 * absolute address of itself. This allows the linker itself simply
4272 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4273 * added in, and the addend of the relocation is stored in the operand
4274 * field for the instruction itself.
4276 * Our job here is to fix the operand so that it would add the correct
4277 * offset so that %ebx would point to itself. The thing that is tricky is
4278 * that .-.L66 will point to the beginning of the instruction, so we need
4279 * to further modify the operand so that it will point to itself.
4280 * There are other cases where you have something like:
4282 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4284 * and here no correction would be required. Internally in the assembler
4285 * we treat operands of this form as not being pcrel since the '.' is
4286 * explicitly mentioned, and I wonder whether it would simplify matters
4287 * to do it this way. Who knows. In earlier versions of the PIC patches,
4288 * the pcrel_adjust field was used to store the correction, but since the
4289 * expression is not pcrel, I felt it would be confusing to do it this
4294 case BFD_RELOC_386_GOT32
:
4295 case BFD_RELOC_X86_64_GOT32
:
4296 value
= 0; /* Fully resolved at runtime. No addend. */
4298 case BFD_RELOC_386_GOTOFF
:
4299 case BFD_RELOC_X86_64_GOTPCREL
:
4302 case BFD_RELOC_VTABLE_INHERIT
:
4303 case BFD_RELOC_VTABLE_ENTRY
:
4310 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4312 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4314 #ifndef BFD_ASSEMBLER
4315 md_number_to_chars (p
, value
, fixP
->fx_size
);
4317 /* Are we finished with this relocation now? */
4318 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4320 else if (use_rela_relocations
)
4322 fixP
->fx_no_overflow
= 1;
4325 md_number_to_chars (p
, value
, fixP
->fx_size
);
4331 #define MAX_LITTLENUMS 6
4333 /* Turn the string pointed to by litP into a floating point constant
4334 of type TYPE, and emit the appropriate bytes. The number of
4335 LITTLENUMS emitted is stored in *SIZEP. An error message is
4336 returned, or NULL on OK. */
4339 md_atof (type
, litP
, sizeP
)
4345 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4346 LITTLENUM_TYPE
*wordP
;
4368 return _("Bad call to md_atof ()");
4370 t
= atof_ieee (input_line_pointer
, type
, words
);
4372 input_line_pointer
= t
;
4374 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4375 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4376 the bigendian 386. */
4377 for (wordP
= words
+ prec
- 1; prec
--;)
4379 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4380 litP
+= sizeof (LITTLENUM_TYPE
);
4385 char output_invalid_buf
[8];
4392 sprintf (output_invalid_buf
, "'%c'", c
);
4394 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4395 return output_invalid_buf
;
4398 /* REG_STRING starts *before* REGISTER_PREFIX. */
4400 static const reg_entry
*
4401 parse_register (reg_string
, end_op
)
4405 char *s
= reg_string
;
4407 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4410 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4411 if (*s
== REGISTER_PREFIX
)
4414 if (is_space_char (*s
))
4418 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4420 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4421 return (const reg_entry
*) NULL
;
4425 /* For naked regs, make sure that we are not dealing with an identifier.
4426 This prevents confusing an identifier like `eax_var' with register
4428 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4429 return (const reg_entry
*) NULL
;
4433 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4435 /* Handle floating point regs, allowing spaces in the (i) part. */
4436 if (r
== i386_regtab
/* %st is first entry of table */)
4438 if (is_space_char (*s
))
4443 if (is_space_char (*s
))
4445 if (*s
>= '0' && *s
<= '7')
4447 r
= &i386_float_regtab
[*s
- '0'];
4449 if (is_space_char (*s
))
4457 /* We have "%st(" then garbage. */
4458 return (const reg_entry
*) NULL
;
4465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4466 const char *md_shortopts
= "kVQ:sq";
4468 const char *md_shortopts
= "q";
4471 struct option md_longopts
[] = {
4472 #define OPTION_32 (OPTION_MD_BASE + 0)
4473 {"32", no_argument
, NULL
, OPTION_32
},
4474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4475 #define OPTION_64 (OPTION_MD_BASE + 1)
4476 {"64", no_argument
, NULL
, OPTION_64
},
4478 {NULL
, no_argument
, NULL
, 0}
4480 size_t md_longopts_size
= sizeof (md_longopts
);
4483 md_parse_option (c
, arg
)
4485 char *arg ATTRIBUTE_UNUSED
;
4493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4494 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4495 should be emitted or not. FIXME: Not implemented. */
4499 /* -V: SVR4 argument to print version ID. */
4501 print_version_id ();
4504 /* -k: Ignore for FreeBSD compatibility. */
4509 /* -s: On i386 Solaris, this tells the native assembler to use
4510 .stab instead of .stab.excl. We always use .stab anyhow. */
4515 const char **list
, **l
;
4517 list
= bfd_target_list ();
4518 for (l
= list
; *l
!= NULL
; l
++)
4519 if (strcmp (*l
, "elf64-x86-64") == 0)
4521 default_arch
= "x86_64";
4525 as_fatal (_("No compiled in support for x86_64"));
4532 default_arch
= "i386";
4542 md_show_usage (stream
)
4545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4546 fprintf (stream
, _("\
4548 -V print assembler version number\n\
4550 -q quieten some warnings\n\
4553 fprintf (stream
, _("\
4554 -q quieten some warnings\n"));
4558 #ifdef BFD_ASSEMBLER
4559 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4560 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4562 /* Pick the target format to use. */
4565 i386_target_format ()
4567 if (!strcmp (default_arch
, "x86_64"))
4568 set_code_flag (CODE_64BIT
);
4569 else if (!strcmp (default_arch
, "i386"))
4570 set_code_flag (CODE_32BIT
);
4572 as_fatal (_("Unknown architecture"));
4573 switch (OUTPUT_FLAVOR
)
4575 #ifdef OBJ_MAYBE_AOUT
4576 case bfd_target_aout_flavour
:
4577 return AOUT_TARGET_FORMAT
;
4579 #ifdef OBJ_MAYBE_COFF
4580 case bfd_target_coff_flavour
:
4583 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4584 case bfd_target_elf_flavour
:
4586 if (flag_code
== CODE_64BIT
)
4587 use_rela_relocations
= 1;
4588 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4597 #endif /* OBJ_MAYBE_ more than one */
4598 #endif /* BFD_ASSEMBLER */
4601 md_undefined_symbol (name
)
4604 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4605 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4606 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4607 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4611 if (symbol_find (name
))
4612 as_bad (_("GOT already in symbol table"));
4613 GOT_symbol
= symbol_new (name
, undefined_section
,
4614 (valueT
) 0, &zero_address_frag
);
4621 /* Round up a section size to the appropriate boundary. */
4624 md_section_align (segment
, size
)
4625 segT segment ATTRIBUTE_UNUSED
;
4628 #ifdef BFD_ASSEMBLER
4629 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4630 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4632 /* For a.out, force the section size to be aligned. If we don't do
4633 this, BFD will align it for us, but it will not write out the
4634 final bytes of the section. This may be a bug in BFD, but it is
4635 easier to fix it here since that is how the other a.out targets
4639 align
= bfd_get_section_alignment (stdoutput
, segment
);
4640 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4648 /* On the i386, PC-relative offsets are relative to the start of the
4649 next instruction. That is, the address of the offset, plus its
4650 size, since the offset is always the last part of the insn. */
4653 md_pcrel_from (fixP
)
4656 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4663 int ignore ATTRIBUTE_UNUSED
;
4667 temp
= get_absolute_expression ();
4668 subseg_set (bss_section
, (subsegT
) temp
);
4669 demand_empty_rest_of_line ();
4674 #ifdef BFD_ASSEMBLER
4677 i386_validate_fix (fixp
)
4680 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4682 /* GOTOFF relocation are nonsense in 64bit mode. */
4683 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4685 if (flag_code
!= CODE_64BIT
)
4687 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4691 if (flag_code
== CODE_64BIT
)
4693 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4700 tc_gen_reloc (section
, fixp
)
4701 asection
*section ATTRIBUTE_UNUSED
;
4705 bfd_reloc_code_real_type code
;
4707 switch (fixp
->fx_r_type
)
4709 case BFD_RELOC_X86_64_PLT32
:
4710 case BFD_RELOC_X86_64_GOT32
:
4711 case BFD_RELOC_X86_64_GOTPCREL
:
4712 case BFD_RELOC_386_PLT32
:
4713 case BFD_RELOC_386_GOT32
:
4714 case BFD_RELOC_386_GOTOFF
:
4715 case BFD_RELOC_386_GOTPC
:
4716 case BFD_RELOC_X86_64_32S
:
4718 case BFD_RELOC_VTABLE_ENTRY
:
4719 case BFD_RELOC_VTABLE_INHERIT
:
4720 code
= fixp
->fx_r_type
;
4725 switch (fixp
->fx_size
)
4728 as_bad (_("can not do %d byte pc-relative relocation"),
4730 code
= BFD_RELOC_32_PCREL
;
4732 case 1: code
= BFD_RELOC_8_PCREL
; break;
4733 case 2: code
= BFD_RELOC_16_PCREL
; break;
4734 case 4: code
= BFD_RELOC_32_PCREL
; break;
4739 switch (fixp
->fx_size
)
4742 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4743 code
= BFD_RELOC_32
;
4745 case 1: code
= BFD_RELOC_8
; break;
4746 case 2: code
= BFD_RELOC_16
; break;
4747 case 4: code
= BFD_RELOC_32
; break;
4748 case 8: code
= BFD_RELOC_64
; break;
4754 if (code
== BFD_RELOC_32
4756 && fixp
->fx_addsy
== GOT_symbol
)
4758 /* We don't support GOTPC on 64bit targets. */
4759 if (flag_code
== CODE_64BIT
)
4761 code
= BFD_RELOC_386_GOTPC
;
4764 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4765 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4766 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4768 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4769 if (!use_rela_relocations
)
4771 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4772 vtable entry to be used in the relocation's section offset. */
4773 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4774 rel
->address
= fixp
->fx_offset
;
4777 rel
->addend
= fixp
->fx_addnumber
;
4781 /* Use the rela in 64bit mode. */
4784 rel
->addend
= fixp
->fx_offset
;
4786 rel
->addend
-= fixp
->fx_size
;
4789 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4790 if (rel
->howto
== NULL
)
4792 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4793 _("cannot represent relocation type %s"),
4794 bfd_get_reloc_code_name (code
));
4795 /* Set howto to a garbage value so that we can keep going. */
4796 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4797 assert (rel
->howto
!= NULL
);
4803 #else /* ! BFD_ASSEMBLER */
4805 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4807 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4810 relax_addressT segment_address_in_file
;
4812 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4813 Out: GNU LD relocation length code: 0, 1, or 2. */
4815 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4818 know (fixP
->fx_addsy
!= NULL
);
4820 md_number_to_chars (where
,
4821 (valueT
) (fixP
->fx_frag
->fr_address
4822 + fixP
->fx_where
- segment_address_in_file
),
4825 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4826 ? S_GET_TYPE (fixP
->fx_addsy
)
4827 : fixP
->fx_addsy
->sy_number
);
4829 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4830 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4831 where
[4] = r_symbolnum
& 0x0ff;
4832 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4833 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4834 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4837 #endif /* OBJ_AOUT or OBJ_BOUT. */
4839 #if defined (I386COFF)
4842 tc_coff_fix2rtype (fixP
)
4845 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4848 return (fixP
->fx_pcrel
?
4849 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4850 fixP
->fx_size
== 2 ? R_PCRWORD
:
4852 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4853 fixP
->fx_size
== 2 ? R_RELWORD
:
4858 tc_coff_sizemachdep (frag
)
4862 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4867 #endif /* I386COFF */
4869 #endif /* ! BFD_ASSEMBLER */
4871 /* Parse operands using Intel syntax. This implements a recursive descent
4872 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4875 FIXME: We do not recognize the full operand grammar defined in the MASM
4876 documentation. In particular, all the structure/union and
4877 high-level macro operands are missing.
4879 Uppercase words are terminals, lower case words are non-terminals.
4880 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4881 bars '|' denote choices. Most grammar productions are implemented in
4882 functions called 'intel_<production>'.
4884 Initial production is 'expr'.
4890 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4892 constant digits [[ radixOverride ]]
4894 dataType BYTE | WORD | DWORD | QWORD | XWORD
4927 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4928 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4930 hexdigit a | b | c | d | e | f
4931 | A | B | C | D | E | F
4941 register specialRegister
4945 segmentRegister CS | DS | ES | FS | GS | SS
4947 specialRegister CR0 | CR2 | CR3
4948 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4949 | TR3 | TR4 | TR5 | TR6 | TR7
4951 We simplify the grammar in obvious places (e.g., register parsing is
4952 done by calling parse_register) and eliminate immediate left recursion
4953 to implement a recursive-descent parser.
4993 /* Parsing structure for the intel syntax parser. Used to implement the
4994 semantic actions for the operand grammar. */
4995 struct intel_parser_s
4997 char *op_string
; /* The string being parsed. */
4998 int got_a_float
; /* Whether the operand is a float. */
4999 int op_modifier
; /* Operand modifier. */
5000 int is_mem
; /* 1 if operand is memory reference. */
5001 const reg_entry
*reg
; /* Last register reference found. */
5002 char *disp
; /* Displacement string being built. */
5005 static struct intel_parser_s intel_parser
;
5007 /* Token structure for parsing intel syntax. */
5010 int code
; /* Token code. */
5011 const reg_entry
*reg
; /* Register entry for register tokens. */
5012 char *str
; /* String representation. */
5015 static struct intel_token cur_token
, prev_token
;
5017 /* Token codes for the intel parser. Since T_SHORT is already used
5018 by COFF, undefine it first to prevent a warning. */
5033 /* Prototypes for intel parser functions. */
5034 static int intel_match_token
PARAMS ((int code
));
5035 static void intel_get_token
PARAMS ((void));
5036 static void intel_putback_token
PARAMS ((void));
5037 static int intel_expr
PARAMS ((void));
5038 static int intel_e05
PARAMS ((void));
5039 static int intel_e05_1
PARAMS ((void));
5040 static int intel_e06
PARAMS ((void));
5041 static int intel_e06_1
PARAMS ((void));
5042 static int intel_e09
PARAMS ((void));
5043 static int intel_e09_1
PARAMS ((void));
5044 static int intel_e10
PARAMS ((void));
5045 static int intel_e10_1
PARAMS ((void));
5046 static int intel_e11
PARAMS ((void));
5049 i386_intel_operand (operand_string
, got_a_float
)
5050 char *operand_string
;
5056 /* Initialize token holders. */
5057 cur_token
.code
= prev_token
.code
= T_NIL
;
5058 cur_token
.reg
= prev_token
.reg
= NULL
;
5059 cur_token
.str
= prev_token
.str
= NULL
;
5061 /* Initialize parser structure. */
5062 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5065 strcpy (intel_parser
.op_string
, operand_string
);
5066 intel_parser
.got_a_float
= got_a_float
;
5067 intel_parser
.op_modifier
= -1;
5068 intel_parser
.is_mem
= 0;
5069 intel_parser
.reg
= NULL
;
5070 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5071 if (intel_parser
.disp
== NULL
)
5073 intel_parser
.disp
[0] = '\0';
5075 /* Read the first token and start the parser. */
5077 ret
= intel_expr ();
5081 /* If we found a memory reference, hand it over to i386_displacement
5082 to fill in the rest of the operand fields. */
5083 if (intel_parser
.is_mem
)
5085 if ((i
.mem_operands
== 1
5086 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5087 || i
.mem_operands
== 2)
5089 as_bad (_("too many memory references for '%s'"),
5090 current_templates
->start
->name
);
5095 char *s
= intel_parser
.disp
;
5098 /* Add the displacement expression. */
5100 ret
= i386_displacement (s
, s
+ strlen (s
))
5101 && i386_index_check (s
);
5105 /* Constant and OFFSET expressions are handled by i386_immediate. */
5106 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5107 || intel_parser
.reg
== NULL
)
5108 ret
= i386_immediate (intel_parser
.disp
);
5112 free (intel_parser
.disp
);
5122 /* expr SHORT e05 */
5123 if (cur_token
.code
== T_SHORT
)
5125 intel_parser
.op_modifier
= SHORT
;
5126 intel_match_token (T_SHORT
);
5128 return (intel_e05 ());
5133 return intel_e05 ();
5143 return (intel_e06 () && intel_e05_1 ());
5149 /* e05' addOp e06 e05' */
5150 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5152 strcat (intel_parser
.disp
, cur_token
.str
);
5153 intel_match_token (cur_token
.code
);
5155 return (intel_e06 () && intel_e05_1 ());
5170 return (intel_e09 () && intel_e06_1 ());
5176 /* e06' mulOp e09 e06' */
5177 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5179 strcat (intel_parser
.disp
, cur_token
.str
);
5180 intel_match_token (cur_token
.code
);
5182 return (intel_e09 () && intel_e06_1 ());
5190 /* e09 OFFSET e10 e09'
5199 /* e09 OFFSET e10 e09' */
5200 if (cur_token
.code
== T_OFFSET
)
5202 intel_parser
.is_mem
= 0;
5203 intel_parser
.op_modifier
= OFFSET_FLAT
;
5204 intel_match_token (T_OFFSET
);
5206 return (intel_e10 () && intel_e09_1 ());
5211 return (intel_e10 () && intel_e09_1 ());
5217 /* e09' PTR e10 e09' */
5218 if (cur_token
.code
== T_PTR
)
5220 if (prev_token
.code
== T_BYTE
)
5221 i
.suffix
= BYTE_MNEM_SUFFIX
;
5223 else if (prev_token
.code
== T_WORD
)
5225 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5226 i
.suffix
= SHORT_MNEM_SUFFIX
;
5228 i
.suffix
= WORD_MNEM_SUFFIX
;
5231 else if (prev_token
.code
== T_DWORD
)
5233 if (intel_parser
.got_a_float
== 1) /* "f..." */
5234 i
.suffix
= SHORT_MNEM_SUFFIX
;
5236 i
.suffix
= LONG_MNEM_SUFFIX
;
5239 else if (prev_token
.code
== T_QWORD
)
5241 if (intel_parser
.got_a_float
== 1) /* "f..." */
5242 i
.suffix
= LONG_MNEM_SUFFIX
;
5244 i
.suffix
= QWORD_MNEM_SUFFIX
;
5247 else if (prev_token
.code
== T_XWORD
)
5248 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5252 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5256 intel_match_token (T_PTR
);
5258 return (intel_e10 () && intel_e09_1 ());
5261 /* e09 : e10 e09' */
5262 else if (cur_token
.code
== ':')
5264 /* Mark as a memory operand only if it's not already known to be an
5265 offset expression. */
5266 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5267 intel_parser
.is_mem
= 1;
5269 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5284 return (intel_e11 () && intel_e10_1 ());
5290 /* e10' [ expr ] e10' */
5291 if (cur_token
.code
== '[')
5293 intel_match_token ('[');
5295 /* Mark as a memory operand only if it's not already known to be an
5296 offset expression. If it's an offset expression, we need to keep
5298 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5299 intel_parser
.is_mem
= 1;
5301 strcat (intel_parser
.disp
, "[");
5303 /* Add a '+' to the displacement string if necessary. */
5304 if (*intel_parser
.disp
!= '\0'
5305 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5306 strcat (intel_parser
.disp
, "+");
5308 if (intel_expr () && intel_match_token (']'))
5310 /* Preserve brackets when the operand is an offset expression. */
5311 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5312 strcat (intel_parser
.disp
, "]");
5314 return intel_e10_1 ();
5341 if (cur_token
.code
== '(')
5343 intel_match_token ('(');
5344 strcat (intel_parser
.disp
, "(");
5346 if (intel_expr () && intel_match_token (')'))
5348 strcat (intel_parser
.disp
, ")");
5356 else if (cur_token
.code
== '[')
5358 intel_match_token ('[');
5360 /* Mark as a memory operand only if it's not already known to be an
5361 offset expression. If it's an offset expression, we need to keep
5363 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5364 intel_parser
.is_mem
= 1;
5366 strcat (intel_parser
.disp
, "[");
5368 /* Operands for jump/call inside brackets denote absolute addresses. */
5369 if (current_templates
->start
->opcode_modifier
& Jump
5370 || current_templates
->start
->opcode_modifier
& JumpDword
5371 || current_templates
->start
->opcode_modifier
& JumpByte
5372 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5373 i
.types
[this_operand
] |= JumpAbsolute
;
5375 /* Add a '+' to the displacement string if necessary. */
5376 if (*intel_parser
.disp
!= '\0'
5377 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5378 strcat (intel_parser
.disp
, "+");
5380 if (intel_expr () && intel_match_token (']'))
5382 /* Preserve brackets when the operand is an offset expression. */
5383 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5384 strcat (intel_parser
.disp
, "]");
5397 else if (cur_token
.code
== T_BYTE
5398 || cur_token
.code
== T_WORD
5399 || cur_token
.code
== T_DWORD
5400 || cur_token
.code
== T_QWORD
5401 || cur_token
.code
== T_XWORD
)
5403 intel_match_token (cur_token
.code
);
5410 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5412 strcat (intel_parser
.disp
, cur_token
.str
);
5413 intel_match_token (cur_token
.code
);
5415 /* Mark as a memory operand only if it's not already known to be an
5416 offset expression. */
5417 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5418 intel_parser
.is_mem
= 1;
5424 else if (cur_token
.code
== T_REG
)
5426 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5428 intel_match_token (T_REG
);
5430 /* Check for segment change. */
5431 if (cur_token
.code
== ':')
5433 if (reg
->reg_type
& (SReg2
| SReg3
))
5435 switch (reg
->reg_num
)
5438 i
.seg
[i
.mem_operands
] = &es
;
5441 i
.seg
[i
.mem_operands
] = &cs
;
5444 i
.seg
[i
.mem_operands
] = &ss
;
5447 i
.seg
[i
.mem_operands
] = &ds
;
5450 i
.seg
[i
.mem_operands
] = &fs
;
5453 i
.seg
[i
.mem_operands
] = &gs
;
5459 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5464 /* Not a segment register. Check for register scaling. */
5465 else if (cur_token
.code
== '*')
5467 if (!intel_parser
.is_mem
)
5469 as_bad (_("Register scaling only allowed in memory operands."));
5473 /* What follows must be a valid scale. */
5474 if (intel_match_token ('*')
5475 && strchr ("01248", *cur_token
.str
))
5478 i
.types
[this_operand
] |= BaseIndex
;
5480 /* Set the scale after setting the register (otherwise,
5481 i386_scale will complain) */
5482 i386_scale (cur_token
.str
);
5483 intel_match_token (T_CONST
);
5487 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5493 /* No scaling. If this is a memory operand, the register is either a
5494 base register (first occurrence) or an index register (second
5496 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5498 if (i
.base_reg
&& i
.index_reg
)
5500 as_bad (_("Too many register references in memory operand.\n"));
5504 if (i
.base_reg
== NULL
)
5509 i
.types
[this_operand
] |= BaseIndex
;
5512 /* Offset modifier. Add the register to the displacement string to be
5513 parsed as an immediate expression after we're done. */
5514 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5515 strcat (intel_parser
.disp
, reg
->reg_name
);
5517 /* It's neither base nor index nor offset. */
5520 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5521 i
.op
[this_operand
].regs
= reg
;
5525 /* Since registers are not part of the displacement string (except
5526 when we're parsing offset operands), we may need to remove any
5527 preceding '+' from the displacement string. */
5528 if (*intel_parser
.disp
!= '\0'
5529 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5531 char *s
= intel_parser
.disp
;
5532 s
+= strlen (s
) - 1;
5541 else if (cur_token
.code
== T_ID
)
5543 /* Add the identifier to the displacement string. */
5544 strcat (intel_parser
.disp
, cur_token
.str
);
5545 intel_match_token (T_ID
);
5547 /* The identifier represents a memory reference only if it's not
5548 preceded by an offset modifier. */
5549 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5550 intel_parser
.is_mem
= 1;
5556 else if (cur_token
.code
== T_CONST
5557 || cur_token
.code
== '-'
5558 || cur_token
.code
== '+')
5562 /* Allow constants that start with `+' or `-'. */
5563 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5565 strcat (intel_parser
.disp
, cur_token
.str
);
5566 intel_match_token (cur_token
.code
);
5567 if (cur_token
.code
!= T_CONST
)
5569 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5575 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5576 if (save_str
== NULL
)
5578 strcpy (save_str
, cur_token
.str
);
5580 /* Get the next token to check for register scaling. */
5581 intel_match_token (cur_token
.code
);
5583 /* Check if this constant is a scaling factor for an index register. */
5584 if (cur_token
.code
== '*')
5586 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5588 if (!intel_parser
.is_mem
)
5590 as_bad (_("Register scaling only allowed in memory operands."));
5594 /* The constant is followed by `* reg', so it must be
5596 if (strchr ("01248", *save_str
))
5598 i
.index_reg
= cur_token
.reg
;
5599 i
.types
[this_operand
] |= BaseIndex
;
5601 /* Set the scale after setting the register (otherwise,
5602 i386_scale will complain) */
5603 i386_scale (save_str
);
5604 intel_match_token (T_REG
);
5606 /* Since registers are not part of the displacement
5607 string, we may need to remove any preceding '+' from
5608 the displacement string. */
5609 if (*intel_parser
.disp
!= '\0')
5611 char *s
= intel_parser
.disp
;
5612 s
+= strlen (s
) - 1;
5625 /* The constant was not used for register scaling. Since we have
5626 already consumed the token following `*' we now need to put it
5627 back in the stream. */
5629 intel_putback_token ();
5632 /* Add the constant to the displacement string. */
5633 strcat (intel_parser
.disp
, save_str
);
5639 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5643 /* Match the given token against cur_token. If they match, read the next
5644 token from the operand string. */
5646 intel_match_token (code
)
5649 if (cur_token
.code
== code
)
5656 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5661 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5666 const reg_entry
*reg
;
5667 struct intel_token new_token
;
5669 new_token
.code
= T_NIL
;
5670 new_token
.reg
= NULL
;
5671 new_token
.str
= NULL
;
5673 /* Free the memory allocated to the previous token and move
5674 cur_token to prev_token. */
5676 free (prev_token
.str
);
5678 prev_token
= cur_token
;
5680 /* Skip whitespace. */
5681 while (is_space_char (*intel_parser
.op_string
))
5682 intel_parser
.op_string
++;
5684 /* Return an empty token if we find nothing else on the line. */
5685 if (*intel_parser
.op_string
== '\0')
5687 cur_token
= new_token
;
5691 /* The new token cannot be larger than the remainder of the operand
5693 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5694 if (new_token
.str
== NULL
)
5696 new_token
.str
[0] = '\0';
5698 if (strchr ("0123456789", *intel_parser
.op_string
))
5700 char *p
= new_token
.str
;
5701 char *q
= intel_parser
.op_string
;
5702 new_token
.code
= T_CONST
;
5704 /* Allow any kind of identifier char to encompass floating point and
5705 hexadecimal numbers. */
5706 while (is_identifier_char (*q
))
5710 /* Recognize special symbol names [0-9][bf]. */
5711 if (strlen (intel_parser
.op_string
) == 2
5712 && (intel_parser
.op_string
[1] == 'b'
5713 || intel_parser
.op_string
[1] == 'f'))
5714 new_token
.code
= T_ID
;
5717 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5719 new_token
.code
= *intel_parser
.op_string
;
5720 new_token
.str
[0] = *intel_parser
.op_string
;
5721 new_token
.str
[1] = '\0';
5724 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5725 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5727 new_token
.code
= T_REG
;
5728 new_token
.reg
= reg
;
5730 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5732 new_token
.str
[0] = REGISTER_PREFIX
;
5733 new_token
.str
[1] = '\0';
5736 strcat (new_token
.str
, reg
->reg_name
);
5739 else if (is_identifier_char (*intel_parser
.op_string
))
5741 char *p
= new_token
.str
;
5742 char *q
= intel_parser
.op_string
;
5744 /* A '.' or '$' followed by an identifier char is an identifier.
5745 Otherwise, it's operator '.' followed by an expression. */
5746 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5748 new_token
.code
= *q
;
5749 new_token
.str
[0] = *q
;
5750 new_token
.str
[1] = '\0';
5754 while (is_identifier_char (*q
) || *q
== '@')
5758 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5759 new_token
.code
= T_BYTE
;
5761 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5762 new_token
.code
= T_WORD
;
5764 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5765 new_token
.code
= T_DWORD
;
5767 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5768 new_token
.code
= T_QWORD
;
5770 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5771 new_token
.code
= T_XWORD
;
5773 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5774 new_token
.code
= T_PTR
;
5776 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5777 new_token
.code
= T_SHORT
;
5779 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5781 new_token
.code
= T_OFFSET
;
5783 /* ??? This is not mentioned in the MASM grammar but gcc
5784 makes use of it with -mintel-syntax. OFFSET may be
5785 followed by FLAT: */
5786 if (strncasecmp (q
, " FLAT:", 6) == 0)
5787 strcat (new_token
.str
, " FLAT:");
5790 /* ??? This is not mentioned in the MASM grammar. */
5791 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5792 new_token
.code
= T_OFFSET
;
5795 new_token
.code
= T_ID
;
5800 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5802 intel_parser
.op_string
+= strlen (new_token
.str
);
5803 cur_token
= new_token
;
5806 /* Put cur_token back into the token stream and make cur_token point to
5809 intel_putback_token ()
5811 intel_parser
.op_string
-= strlen (cur_token
.str
);
5812 free (cur_token
.str
);
5813 cur_token
= prev_token
;
5815 /* Forget prev_token. */
5816 prev_token
.code
= T_NIL
;
5817 prev_token
.reg
= NULL
;
5818 prev_token
.str
= NULL
;