1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528 /* 1 if not generating code for a shared library. */
529 static int no_shared
= 0;
532 /* 1 for intel syntax,
534 static int intel_syntax
= 0;
536 /* 1 for intel mnemonic,
537 0 if att mnemonic. */
538 static int intel_mnemonic
= !SYSV386_COMPAT
;
540 /* 1 if support old (<= 2.8.1) versions of gcc. */
541 static int old_gcc
= OLDGCC_COMPAT
;
543 /* 1 if pseudo registers are permitted. */
544 static int allow_pseudo_reg
= 0;
546 /* 1 if register prefix % not required. */
547 static int allow_naked_reg
= 0;
549 /* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
552 static int add_bnd_prefix
= 0;
554 /* 1 if pseudo index register, eiz/riz, is allowed . */
555 static int allow_index_reg
= 0;
557 /* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559 static int omit_lock_prefix
= 0;
561 static enum check_kind
567 sse_check
, operand_check
= check_warning
;
569 /* Register prefix used for error message. */
570 static const char *register_prefix
= "%";
572 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575 static char stackop_size
= '\0';
577 /* Non-zero to optimize code alignment. */
578 int optimize_align_code
= 1;
580 /* Non-zero to quieten some warnings. */
581 static int quiet_warnings
= 0;
584 static const char *cpu_arch_name
= NULL
;
585 static char *cpu_sub_arch_name
= NULL
;
587 /* CPU feature flags. */
588 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
590 /* If we have selected a cpu we are generating instructions for. */
591 static int cpu_arch_tune_set
= 0;
593 /* Cpu we are generating instructions for. */
594 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of cpu we are generating instructions for. */
597 static i386_cpu_flags cpu_arch_tune_flags
;
599 /* CPU instruction set architecture used. */
600 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
602 /* CPU feature flags of instruction set architecture used. */
603 i386_cpu_flags cpu_arch_isa_flags
;
605 /* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607 static unsigned int no_cond_jump_promotion
= 0;
609 /* Encode SSE instructions with VEX prefix. */
610 static unsigned int sse2avx
;
612 /* Encode scalar AVX instructions with specific vector length. */
619 /* Encode scalar EVEX LIG instructions with specific vector length. */
627 /* Encode EVEX WIG instructions with specific evex.w. */
634 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
635 static enum rc_type evexrcig
= rne
;
637 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
638 static symbolS
*GOT_symbol
;
640 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
641 unsigned int x86_dwarf2_return_column
;
643 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644 int x86_cie_data_alignment
;
646 /* Interface to relax_segment.
647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
652 #define UNCOND_JUMP 0
654 #define COND_JUMP86 2
659 #define SMALL16 (SMALL | CODE16)
661 #define BIG16 (BIG | CODE16)
665 #define INLINE __inline__
671 #define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673 #define TYPE_FROM_RELAX_STATE(s) \
675 #define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
678 /* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
686 const relax_typeS md_relax_table
[] =
689 1) most positive reach of this state,
690 2) most negative reach of this state,
691 3) how many bytes this mode will have in the variable part of the frag
692 4) which index into the table to try if we can't fit into this one. */
694 /* UNCOND_JUMP states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
710 /* word conditionals add 3 bytes to frag:
711 1 extra opcode byte, 2 displacement bytes. */
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
725 static const arch_entry cpu_arch
[] =
727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
730 CPU_GENERIC32_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
732 CPU_GENERIC64_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
734 CPU_NONE_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
736 CPU_I186_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
738 CPU_I286_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
740 CPU_I386_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
742 CPU_I486_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
744 CPU_I586_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
746 CPU_I686_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
748 CPU_I586_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
750 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
752 CPU_P2_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
754 CPU_P3_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
756 CPU_P4_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
760 CPU_NOCONA_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
762 CPU_CORE_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
764 CPU_CORE_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
766 CPU_CORE2_FLAGS
, 1, 0 },
767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
768 CPU_CORE2_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
770 CPU_COREI7_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
772 CPU_L1OM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
774 CPU_K1OM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
776 CPU_IAMCU_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
778 CPU_K6_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
780 CPU_K6_2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
782 CPU_ATHLON_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
784 CPU_K8_FLAGS
, 1, 0 },
785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
786 CPU_K8_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
788 CPU_K8_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
790 CPU_AMDFAM10_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
792 CPU_BDVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
794 CPU_BDVER2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
796 CPU_BDVER3_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
798 CPU_BDVER4_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
800 CPU_ZNVER1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
802 CPU_BTVER1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
804 CPU_BTVER2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
806 CPU_8087_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
808 CPU_287_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
810 CPU_387_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
812 CPU_ANY87_FLAGS
, 0, 1 },
813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
814 CPU_MMX_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
816 CPU_3DNOWA_FLAGS
, 0, 1 },
817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
818 CPU_SSE_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
820 CPU_SSE2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
822 CPU_SSE3_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
824 CPU_SSSE3_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
826 CPU_SSE4_1_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
828 CPU_SSE4_2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
830 CPU_SSE4_2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
832 CPU_ANY_SSE_FLAGS
, 0, 1 },
833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
834 CPU_AVX_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
836 CPU_AVX2_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512F_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512CD_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512ER_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512PF_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
846 CPU_AVX512DQ_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
848 CPU_AVX512BW_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
850 CPU_AVX512VL_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
852 CPU_ANY_AVX_FLAGS
, 0, 1 },
853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
854 CPU_VMX_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
856 CPU_VMFUNC_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
858 CPU_SMX_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVE_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
862 CPU_XSAVEOPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
864 CPU_XSAVEC_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
866 CPU_XSAVES_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
868 CPU_AES_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
870 CPU_PCLMUL_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
872 CPU_PCLMUL_FLAGS
, 1, 0 },
873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
874 CPU_FSGSBASE_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
876 CPU_RDRND_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
878 CPU_F16C_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
880 CPU_BMI2_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
882 CPU_FMA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
884 CPU_FMA4_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
886 CPU_XOP_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
888 CPU_LWP_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
890 CPU_MOVBE_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
892 CPU_CX16_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
894 CPU_EPT_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
896 CPU_LZCNT_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
898 CPU_HLE_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
900 CPU_RTM_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
902 CPU_INVPCID_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
904 CPU_CLFLUSH_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
906 CPU_NOP_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
908 CPU_SYSCALL_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
910 CPU_RDTSCP_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
912 CPU_3DNOW_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
914 CPU_3DNOWA_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
916 CPU_PADLOCK_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
918 CPU_SVME_FLAGS
, 1, 0 },
919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
920 CPU_SVME_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4A_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
924 CPU_ABM_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
926 CPU_BMI_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
928 CPU_TBM_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
930 CPU_ADX_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
932 CPU_RDSEED_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
934 CPU_PRFCHW_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
936 CPU_SMAP_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
938 CPU_MPX_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
940 CPU_SHA_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
942 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
944 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
946 CPU_SE1_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
948 CPU_CLWB_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
950 CPU_PCOMMIT_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
952 CPU_AVX512IFMA_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
954 CPU_AVX512VBMI_FLAGS
, 0, 0 },
955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
956 CPU_CLZERO_FLAGS
, 0, 0 },
960 /* Like s_lcomm_internal in gas/read.c but the alignment string
961 is allowed to be optional. */
964 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
971 && *input_line_pointer
== ',')
973 align
= parse_align (needs_align
- 1);
975 if (align
== (addressT
) -1)
990 bss_alloc (symbolP
, size
, align
);
995 pe_lcomm (int needs_align
)
997 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1001 const pseudo_typeS md_pseudo_table
[] =
1003 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1004 {"align", s_align_bytes
, 0},
1006 {"align", s_align_ptwo
, 0},
1008 {"arch", set_cpu_arch
, 0},
1012 {"lcomm", pe_lcomm
, 1},
1014 {"ffloat", float_cons
, 'f'},
1015 {"dfloat", float_cons
, 'd'},
1016 {"tfloat", float_cons
, 'x'},
1018 {"slong", signed_cons
, 4},
1019 {"noopt", s_ignore
, 0},
1020 {"optim", s_ignore
, 0},
1021 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1022 {"code16", set_code_flag
, CODE_16BIT
},
1023 {"code32", set_code_flag
, CODE_32BIT
},
1024 {"code64", set_code_flag
, CODE_64BIT
},
1025 {"intel_syntax", set_intel_syntax
, 1},
1026 {"att_syntax", set_intel_syntax
, 0},
1027 {"intel_mnemonic", set_intel_mnemonic
, 1},
1028 {"att_mnemonic", set_intel_mnemonic
, 0},
1029 {"allow_index_reg", set_allow_index_reg
, 1},
1030 {"disallow_index_reg", set_allow_index_reg
, 0},
1031 {"sse_check", set_check
, 0},
1032 {"operand_check", set_check
, 1},
1033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1034 {"largecomm", handle_large_common
, 0},
1036 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1037 {"loc", dwarf2_directive_loc
, 0},
1038 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1041 {"secrel32", pe_directive_secrel
, 0},
1046 /* For interface with expression (). */
1047 extern char *input_line_pointer
;
1049 /* Hash table for instruction mnemonic lookup. */
1050 static struct hash_control
*op_hash
;
1052 /* Hash table for register lookup. */
1053 static struct hash_control
*reg_hash
;
1056 i386_align_code (fragS
*fragP
, int count
)
1058 /* Various efficient no-op patterns for aligning code labels.
1059 Note: Don't try to assemble the instructions in the comments.
1060 0L and 0w are not legal. */
1061 static const char f32_1
[] =
1063 static const char f32_2
[] =
1064 {0x66,0x90}; /* xchg %ax,%ax */
1065 static const char f32_3
[] =
1066 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1067 static const char f32_4
[] =
1068 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1069 static const char f32_5
[] =
1071 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1072 static const char f32_6
[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1074 static const char f32_7
[] =
1075 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1076 static const char f32_8
[] =
1078 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1079 static const char f32_9
[] =
1080 {0x89,0xf6, /* movl %esi,%esi */
1081 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1082 static const char f32_10
[] =
1083 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1084 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1085 static const char f32_11
[] =
1086 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1087 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1088 static const char f32_12
[] =
1089 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1090 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1091 static const char f32_13
[] =
1092 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1093 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1094 static const char f32_14
[] =
1095 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1096 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1097 static const char f16_3
[] =
1098 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1099 static const char f16_4
[] =
1100 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1101 static const char f16_5
[] =
1103 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1104 static const char f16_6
[] =
1105 {0x89,0xf6, /* mov %si,%si */
1106 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1107 static const char f16_7
[] =
1108 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1109 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1110 static const char f16_8
[] =
1111 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1112 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1113 static const char jump_31
[] =
1114 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1116 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1118 static const char *const f32_patt
[] = {
1119 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1120 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1122 static const char *const f16_patt
[] = {
1123 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1125 /* nopl (%[re]ax) */
1126 static const char alt_3
[] =
1128 /* nopl 0(%[re]ax) */
1129 static const char alt_4
[] =
1130 {0x0f,0x1f,0x40,0x00};
1131 /* nopl 0(%[re]ax,%[re]ax,1) */
1132 static const char alt_5
[] =
1133 {0x0f,0x1f,0x44,0x00,0x00};
1134 /* nopw 0(%[re]ax,%[re]ax,1) */
1135 static const char alt_6
[] =
1136 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1137 /* nopl 0L(%[re]ax) */
1138 static const char alt_7
[] =
1139 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1140 /* nopl 0L(%[re]ax,%[re]ax,1) */
1141 static const char alt_8
[] =
1142 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 /* nopw 0L(%[re]ax,%[re]ax,1) */
1144 static const char alt_9
[] =
1145 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1146 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_10
[] =
1148 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 static const char *const alt_patt
[] = {
1150 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1154 /* Only align for at least a positive non-zero boundary. */
1155 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1158 /* We need to decide which NOP sequence to use for 32bit and
1159 64bit. When -mtune= is used:
1161 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1162 PROCESSOR_GENERIC32, f32_patt will be used.
1163 2. For the rest, alt_patt will be used.
1165 When -mtune= isn't used, alt_patt will be used if
1166 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1169 When -march= or .arch is used, we can't use anything beyond
1170 cpu_arch_isa_flags. */
1172 if (flag_code
== CODE_16BIT
)
1176 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1178 /* Adjust jump offset. */
1179 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1182 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1183 f16_patt
[count
- 1], count
);
1187 const char *const *patt
= NULL
;
1189 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1191 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1192 switch (cpu_arch_tune
)
1194 case PROCESSOR_UNKNOWN
:
1195 /* We use cpu_arch_isa_flags to check if we SHOULD
1196 optimize with nops. */
1197 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1202 case PROCESSOR_PENTIUM4
:
1203 case PROCESSOR_NOCONA
:
1204 case PROCESSOR_CORE
:
1205 case PROCESSOR_CORE2
:
1206 case PROCESSOR_COREI7
:
1207 case PROCESSOR_L1OM
:
1208 case PROCESSOR_K1OM
:
1209 case PROCESSOR_GENERIC64
:
1211 case PROCESSOR_ATHLON
:
1213 case PROCESSOR_AMDFAM10
:
1215 case PROCESSOR_ZNVER
:
1219 case PROCESSOR_I386
:
1220 case PROCESSOR_I486
:
1221 case PROCESSOR_PENTIUM
:
1222 case PROCESSOR_PENTIUMPRO
:
1223 case PROCESSOR_IAMCU
:
1224 case PROCESSOR_GENERIC32
:
1231 switch (fragP
->tc_frag_data
.tune
)
1233 case PROCESSOR_UNKNOWN
:
1234 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1235 PROCESSOR_UNKNOWN. */
1239 case PROCESSOR_I386
:
1240 case PROCESSOR_I486
:
1241 case PROCESSOR_PENTIUM
:
1242 case PROCESSOR_IAMCU
:
1244 case PROCESSOR_ATHLON
:
1246 case PROCESSOR_AMDFAM10
:
1248 case PROCESSOR_ZNVER
:
1250 case PROCESSOR_GENERIC32
:
1251 /* We use cpu_arch_isa_flags to check if we CAN optimize
1253 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1258 case PROCESSOR_PENTIUMPRO
:
1259 case PROCESSOR_PENTIUM4
:
1260 case PROCESSOR_NOCONA
:
1261 case PROCESSOR_CORE
:
1262 case PROCESSOR_CORE2
:
1263 case PROCESSOR_COREI7
:
1264 case PROCESSOR_L1OM
:
1265 case PROCESSOR_K1OM
:
1266 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1271 case PROCESSOR_GENERIC64
:
1277 if (patt
== f32_patt
)
1279 /* If the padding is less than 15 bytes, we use the normal
1280 ones. Otherwise, we use a jump instruction and adjust
1284 /* For 64bit, the limit is 3 bytes. */
1285 if (flag_code
== CODE_64BIT
1286 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1291 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1292 patt
[count
- 1], count
);
1295 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1297 /* Adjust jump offset. */
1298 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1303 /* Maximum length of an instruction is 10 byte. If the
1304 padding is greater than 10 bytes and we don't use jump,
1305 we have to break it into smaller pieces. */
1306 int padding
= count
;
1307 while (padding
> 10)
1310 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1315 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1316 patt
[padding
- 1], padding
);
1319 fragP
->fr_var
= count
;
1323 operand_type_all_zero (const union i386_operand_type
*x
)
1325 switch (ARRAY_SIZE(x
->array
))
1334 return !x
->array
[0];
1341 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1343 switch (ARRAY_SIZE(x
->array
))
1358 operand_type_equal (const union i386_operand_type
*x
,
1359 const union i386_operand_type
*y
)
1361 switch (ARRAY_SIZE(x
->array
))
1364 if (x
->array
[2] != y
->array
[2])
1367 if (x
->array
[1] != y
->array
[1])
1370 return x
->array
[0] == y
->array
[0];
1378 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1380 switch (ARRAY_SIZE(x
->array
))
1389 return !x
->array
[0];
1396 cpu_flags_equal (const union i386_cpu_flags
*x
,
1397 const union i386_cpu_flags
*y
)
1399 switch (ARRAY_SIZE(x
->array
))
1402 if (x
->array
[2] != y
->array
[2])
1405 if (x
->array
[1] != y
->array
[1])
1408 return x
->array
[0] == y
->array
[0];
1416 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1418 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1419 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1422 static INLINE i386_cpu_flags
1423 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1425 switch (ARRAY_SIZE (x
.array
))
1428 x
.array
[2] &= y
.array
[2];
1430 x
.array
[1] &= y
.array
[1];
1432 x
.array
[0] &= y
.array
[0];
1440 static INLINE i386_cpu_flags
1441 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1443 switch (ARRAY_SIZE (x
.array
))
1446 x
.array
[2] |= y
.array
[2];
1448 x
.array
[1] |= y
.array
[1];
1450 x
.array
[0] |= y
.array
[0];
1458 static INLINE i386_cpu_flags
1459 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1461 switch (ARRAY_SIZE (x
.array
))
1464 x
.array
[2] &= ~y
.array
[2];
1466 x
.array
[1] &= ~y
.array
[1];
1468 x
.array
[0] &= ~y
.array
[0];
1477 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1479 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1481 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1482 i386_cpu_flags compat_flags
;
1483 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1484 return cpu_flags_all_zero (&compat_flags
);
1490 #define CPU_FLAGS_ARCH_MATCH 0x1
1491 #define CPU_FLAGS_64BIT_MATCH 0x2
1492 #define CPU_FLAGS_AES_MATCH 0x4
1493 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1494 #define CPU_FLAGS_AVX_MATCH 0x10
1496 #define CPU_FLAGS_32BIT_MATCH \
1497 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1498 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1499 #define CPU_FLAGS_PERFECT_MATCH \
1500 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1502 /* Return CPU flags match bits. */
1505 cpu_flags_match (const insn_template
*t
)
1507 i386_cpu_flags x
= t
->cpu_flags
;
1508 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1510 x
.bitfield
.cpu64
= 0;
1511 x
.bitfield
.cpuno64
= 0;
1513 if (cpu_flags_all_zero (&x
))
1515 /* This instruction is available on all archs. */
1516 match
|= CPU_FLAGS_32BIT_MATCH
;
1520 /* This instruction is available only on some archs. */
1521 i386_cpu_flags cpu
= cpu_arch_flags
;
1523 cpu
.bitfield
.cpu64
= 0;
1524 cpu
.bitfield
.cpuno64
= 0;
1525 cpu
= cpu_flags_and (x
, cpu
);
1526 if (!cpu_flags_all_zero (&cpu
))
1528 if (x
.bitfield
.cpuavx
)
1530 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1531 if (cpu
.bitfield
.cpuavx
)
1533 /* Check SSE2AVX. */
1534 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1536 match
|= (CPU_FLAGS_ARCH_MATCH
1537 | CPU_FLAGS_AVX_MATCH
);
1539 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1540 match
|= CPU_FLAGS_AES_MATCH
;
1542 if (!x
.bitfield
.cpupclmul
1543 || cpu
.bitfield
.cpupclmul
)
1544 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1548 match
|= CPU_FLAGS_ARCH_MATCH
;
1551 match
|= CPU_FLAGS_32BIT_MATCH
;
1557 static INLINE i386_operand_type
1558 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1560 switch (ARRAY_SIZE (x
.array
))
1563 x
.array
[2] &= y
.array
[2];
1565 x
.array
[1] &= y
.array
[1];
1567 x
.array
[0] &= y
.array
[0];
1575 static INLINE i386_operand_type
1576 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1578 switch (ARRAY_SIZE (x
.array
))
1581 x
.array
[2] |= y
.array
[2];
1583 x
.array
[1] |= y
.array
[1];
1585 x
.array
[0] |= y
.array
[0];
1593 static INLINE i386_operand_type
1594 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1596 switch (ARRAY_SIZE (x
.array
))
1599 x
.array
[2] ^= y
.array
[2];
1601 x
.array
[1] ^= y
.array
[1];
1603 x
.array
[0] ^= y
.array
[0];
1611 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1612 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1613 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1614 static const i386_operand_type inoutportreg
1615 = OPERAND_TYPE_INOUTPORTREG
;
1616 static const i386_operand_type reg16_inoutportreg
1617 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1618 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1619 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1620 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1621 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1622 static const i386_operand_type anydisp
1623 = OPERAND_TYPE_ANYDISP
;
1624 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1625 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1626 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1627 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1628 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1629 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1630 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1631 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1632 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1633 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1634 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1635 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1636 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1637 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1648 operand_type_check (i386_operand_type t
, enum operand_type c
)
1653 return (t
.bitfield
.reg8
1656 || t
.bitfield
.reg64
);
1659 return (t
.bitfield
.imm8
1663 || t
.bitfield
.imm32s
1664 || t
.bitfield
.imm64
);
1667 return (t
.bitfield
.disp8
1668 || t
.bitfield
.disp16
1669 || t
.bitfield
.disp32
1670 || t
.bitfield
.disp32s
1671 || t
.bitfield
.disp64
);
1674 return (t
.bitfield
.disp8
1675 || t
.bitfield
.disp16
1676 || t
.bitfield
.disp32
1677 || t
.bitfield
.disp32s
1678 || t
.bitfield
.disp64
1679 || t
.bitfield
.baseindex
);
1688 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1689 operand J for instruction template T. */
1692 match_reg_size (const insn_template
*t
, unsigned int j
)
1694 return !((i
.types
[j
].bitfield
.byte
1695 && !t
->operand_types
[j
].bitfield
.byte
)
1696 || (i
.types
[j
].bitfield
.word
1697 && !t
->operand_types
[j
].bitfield
.word
)
1698 || (i
.types
[j
].bitfield
.dword
1699 && !t
->operand_types
[j
].bitfield
.dword
)
1700 || (i
.types
[j
].bitfield
.qword
1701 && !t
->operand_types
[j
].bitfield
.qword
));
1704 /* Return 1 if there is no conflict in any size on operand J for
1705 instruction template T. */
1708 match_mem_size (const insn_template
*t
, unsigned int j
)
1710 return (match_reg_size (t
, j
)
1711 && !((i
.types
[j
].bitfield
.unspecified
1713 && !t
->operand_types
[j
].bitfield
.unspecified
)
1714 || (i
.types
[j
].bitfield
.fword
1715 && !t
->operand_types
[j
].bitfield
.fword
)
1716 || (i
.types
[j
].bitfield
.tbyte
1717 && !t
->operand_types
[j
].bitfield
.tbyte
)
1718 || (i
.types
[j
].bitfield
.xmmword
1719 && !t
->operand_types
[j
].bitfield
.xmmword
)
1720 || (i
.types
[j
].bitfield
.ymmword
1721 && !t
->operand_types
[j
].bitfield
.ymmword
)
1722 || (i
.types
[j
].bitfield
.zmmword
1723 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1726 /* Return 1 if there is no size conflict on any operands for
1727 instruction template T. */
1730 operand_size_match (const insn_template
*t
)
1735 /* Don't check jump instructions. */
1736 if (t
->opcode_modifier
.jump
1737 || t
->opcode_modifier
.jumpbyte
1738 || t
->opcode_modifier
.jumpdword
1739 || t
->opcode_modifier
.jumpintersegment
)
1742 /* Check memory and accumulator operand size. */
1743 for (j
= 0; j
< i
.operands
; j
++)
1745 if (t
->operand_types
[j
].bitfield
.anysize
)
1748 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1754 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1763 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1766 i
.error
= operand_size_mismatch
;
1770 /* Check reverse. */
1771 gas_assert (i
.operands
== 2);
1774 for (j
= 0; j
< 2; j
++)
1776 if (t
->operand_types
[j
].bitfield
.acc
1777 && !match_reg_size (t
, j
? 0 : 1))
1780 if (i
.types
[j
].bitfield
.mem
1781 && !match_mem_size (t
, j
? 0 : 1))
1789 operand_type_match (i386_operand_type overlap
,
1790 i386_operand_type given
)
1792 i386_operand_type temp
= overlap
;
1794 temp
.bitfield
.jumpabsolute
= 0;
1795 temp
.bitfield
.unspecified
= 0;
1796 temp
.bitfield
.byte
= 0;
1797 temp
.bitfield
.word
= 0;
1798 temp
.bitfield
.dword
= 0;
1799 temp
.bitfield
.fword
= 0;
1800 temp
.bitfield
.qword
= 0;
1801 temp
.bitfield
.tbyte
= 0;
1802 temp
.bitfield
.xmmword
= 0;
1803 temp
.bitfield
.ymmword
= 0;
1804 temp
.bitfield
.zmmword
= 0;
1805 if (operand_type_all_zero (&temp
))
1808 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1809 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1813 i
.error
= operand_type_mismatch
;
1817 /* If given types g0 and g1 are registers they must be of the same type
1818 unless the expected operand type register overlap is null.
1819 Note that Acc in a template matches every size of reg. */
1822 operand_type_register_match (i386_operand_type m0
,
1823 i386_operand_type g0
,
1824 i386_operand_type t0
,
1825 i386_operand_type m1
,
1826 i386_operand_type g1
,
1827 i386_operand_type t1
)
1829 if (!operand_type_check (g0
, reg
))
1832 if (!operand_type_check (g1
, reg
))
1835 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1836 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1837 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1838 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1841 if (m0
.bitfield
.acc
)
1843 t0
.bitfield
.reg8
= 1;
1844 t0
.bitfield
.reg16
= 1;
1845 t0
.bitfield
.reg32
= 1;
1846 t0
.bitfield
.reg64
= 1;
1849 if (m1
.bitfield
.acc
)
1851 t1
.bitfield
.reg8
= 1;
1852 t1
.bitfield
.reg16
= 1;
1853 t1
.bitfield
.reg32
= 1;
1854 t1
.bitfield
.reg64
= 1;
1857 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1858 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1859 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1860 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1863 i
.error
= register_type_mismatch
;
1868 static INLINE
unsigned int
1869 register_number (const reg_entry
*r
)
1871 unsigned int nr
= r
->reg_num
;
1873 if (r
->reg_flags
& RegRex
)
1879 static INLINE
unsigned int
1880 mode_from_disp_size (i386_operand_type t
)
1882 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1884 else if (t
.bitfield
.disp16
1885 || t
.bitfield
.disp32
1886 || t
.bitfield
.disp32s
)
1893 fits_in_signed_byte (addressT num
)
1895 return num
+ 0x80 <= 0xff;
1899 fits_in_unsigned_byte (addressT num
)
1905 fits_in_unsigned_word (addressT num
)
1907 return num
<= 0xffff;
1911 fits_in_signed_word (addressT num
)
1913 return num
+ 0x8000 <= 0xffff;
1917 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1922 return num
+ 0x80000000 <= 0xffffffff;
1924 } /* fits_in_signed_long() */
1927 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1932 return num
<= 0xffffffff;
1934 } /* fits_in_unsigned_long() */
1937 fits_in_vec_disp8 (offsetT num
)
1939 int shift
= i
.memshift
;
1945 mask
= (1 << shift
) - 1;
1947 /* Return 0 if NUM isn't properly aligned. */
1951 /* Check if NUM will fit in 8bit after shift. */
1952 return fits_in_signed_byte (num
>> shift
);
1956 fits_in_imm4 (offsetT num
)
1958 return (num
& 0xf) == num
;
1961 static i386_operand_type
1962 smallest_imm_type (offsetT num
)
1964 i386_operand_type t
;
1966 operand_type_set (&t
, 0);
1967 t
.bitfield
.imm64
= 1;
1969 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1971 /* This code is disabled on the 486 because all the Imm1 forms
1972 in the opcode table are slower on the i486. They're the
1973 versions with the implicitly specified single-position
1974 displacement, which has another syntax if you really want to
1976 t
.bitfield
.imm1
= 1;
1977 t
.bitfield
.imm8
= 1;
1978 t
.bitfield
.imm8s
= 1;
1979 t
.bitfield
.imm16
= 1;
1980 t
.bitfield
.imm32
= 1;
1981 t
.bitfield
.imm32s
= 1;
1983 else if (fits_in_signed_byte (num
))
1985 t
.bitfield
.imm8
= 1;
1986 t
.bitfield
.imm8s
= 1;
1987 t
.bitfield
.imm16
= 1;
1988 t
.bitfield
.imm32
= 1;
1989 t
.bitfield
.imm32s
= 1;
1991 else if (fits_in_unsigned_byte (num
))
1993 t
.bitfield
.imm8
= 1;
1994 t
.bitfield
.imm16
= 1;
1995 t
.bitfield
.imm32
= 1;
1996 t
.bitfield
.imm32s
= 1;
1998 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2000 t
.bitfield
.imm16
= 1;
2001 t
.bitfield
.imm32
= 1;
2002 t
.bitfield
.imm32s
= 1;
2004 else if (fits_in_signed_long (num
))
2006 t
.bitfield
.imm32
= 1;
2007 t
.bitfield
.imm32s
= 1;
2009 else if (fits_in_unsigned_long (num
))
2010 t
.bitfield
.imm32
= 1;
2016 offset_in_range (offsetT val
, int size
)
2022 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2023 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2024 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2026 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2032 /* If BFD64, sign extend val for 32bit address mode. */
2033 if (flag_code
!= CODE_64BIT
2034 || i
.prefix
[ADDR_PREFIX
])
2035 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2036 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2039 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2041 char buf1
[40], buf2
[40];
2043 sprint_value (buf1
, val
);
2044 sprint_value (buf2
, val
& mask
);
2045 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2059 a. PREFIX_EXIST if attempting to add a prefix where one from the
2060 same class already exists.
2061 b. PREFIX_LOCK if lock prefix is added.
2062 c. PREFIX_REP if rep/repne prefix is added.
2063 d. PREFIX_OTHER if other prefix is added.
2066 static enum PREFIX_GROUP
2067 add_prefix (unsigned int prefix
)
2069 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2072 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2073 && flag_code
== CODE_64BIT
)
2075 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2076 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2077 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2088 case CS_PREFIX_OPCODE
:
2089 case DS_PREFIX_OPCODE
:
2090 case ES_PREFIX_OPCODE
:
2091 case FS_PREFIX_OPCODE
:
2092 case GS_PREFIX_OPCODE
:
2093 case SS_PREFIX_OPCODE
:
2097 case REPNE_PREFIX_OPCODE
:
2098 case REPE_PREFIX_OPCODE
:
2103 case LOCK_PREFIX_OPCODE
:
2112 case ADDR_PREFIX_OPCODE
:
2116 case DATA_PREFIX_OPCODE
:
2120 if (i
.prefix
[q
] != 0)
2128 i
.prefix
[q
] |= prefix
;
2131 as_bad (_("same type of prefix used twice"));
2137 update_code_flag (int value
, int check
)
2139 PRINTF_LIKE ((*as_error
));
2141 flag_code
= (enum flag_code
) value
;
2142 if (flag_code
== CODE_64BIT
)
2144 cpu_arch_flags
.bitfield
.cpu64
= 1;
2145 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2149 cpu_arch_flags
.bitfield
.cpu64
= 0;
2150 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2152 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2155 as_error
= as_fatal
;
2158 (*as_error
) (_("64bit mode not supported on `%s'."),
2159 cpu_arch_name
? cpu_arch_name
: default_arch
);
2161 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2164 as_error
= as_fatal
;
2167 (*as_error
) (_("32bit mode not supported on `%s'."),
2168 cpu_arch_name
? cpu_arch_name
: default_arch
);
2170 stackop_size
= '\0';
2174 set_code_flag (int value
)
2176 update_code_flag (value
, 0);
2180 set_16bit_gcc_code_flag (int new_code_flag
)
2182 flag_code
= (enum flag_code
) new_code_flag
;
2183 if (flag_code
!= CODE_16BIT
)
2185 cpu_arch_flags
.bitfield
.cpu64
= 0;
2186 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2187 stackop_size
= LONG_MNEM_SUFFIX
;
2191 set_intel_syntax (int syntax_flag
)
2193 /* Find out if register prefixing is specified. */
2194 int ask_naked_reg
= 0;
2197 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2199 char *string
= input_line_pointer
;
2200 int e
= get_symbol_end ();
2202 if (strcmp (string
, "prefix") == 0)
2204 else if (strcmp (string
, "noprefix") == 0)
2207 as_bad (_("bad argument to syntax directive."));
2208 *input_line_pointer
= e
;
2210 demand_empty_rest_of_line ();
2212 intel_syntax
= syntax_flag
;
2214 if (ask_naked_reg
== 0)
2215 allow_naked_reg
= (intel_syntax
2216 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2218 allow_naked_reg
= (ask_naked_reg
< 0);
2220 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2222 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2223 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2224 register_prefix
= allow_naked_reg
? "" : "%";
2228 set_intel_mnemonic (int mnemonic_flag
)
2230 intel_mnemonic
= mnemonic_flag
;
2234 set_allow_index_reg (int flag
)
2236 allow_index_reg
= flag
;
2240 set_check (int what
)
2242 enum check_kind
*kind
;
2247 kind
= &operand_check
;
2258 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2260 char *string
= input_line_pointer
;
2261 int e
= get_symbol_end ();
2263 if (strcmp (string
, "none") == 0)
2265 else if (strcmp (string
, "warning") == 0)
2266 *kind
= check_warning
;
2267 else if (strcmp (string
, "error") == 0)
2268 *kind
= check_error
;
2270 as_bad (_("bad argument to %s_check directive."), str
);
2271 *input_line_pointer
= e
;
2274 as_bad (_("missing argument for %s_check directive"), str
);
2276 demand_empty_rest_of_line ();
2280 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2281 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2284 static const char *arch
;
2286 /* Intel LIOM is only supported on ELF. */
2292 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2293 use default_arch. */
2294 arch
= cpu_arch_name
;
2296 arch
= default_arch
;
2299 /* If we are targeting Intel MCU, we must enable it. */
2300 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2301 || new_flag
.bitfield
.cpuiamcu
)
2304 /* If we are targeting Intel L1OM, we must enable it. */
2305 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2306 || new_flag
.bitfield
.cpul1om
)
2309 /* If we are targeting Intel K1OM, we must enable it. */
2310 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2311 || new_flag
.bitfield
.cpuk1om
)
2314 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2319 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2323 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2325 char *string
= input_line_pointer
;
2326 int e
= get_symbol_end ();
2328 i386_cpu_flags flags
;
2330 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2332 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2334 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2338 cpu_arch_name
= cpu_arch
[j
].name
;
2339 cpu_sub_arch_name
= NULL
;
2340 cpu_arch_flags
= cpu_arch
[j
].flags
;
2341 if (flag_code
== CODE_64BIT
)
2343 cpu_arch_flags
.bitfield
.cpu64
= 1;
2344 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2348 cpu_arch_flags
.bitfield
.cpu64
= 0;
2349 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2351 cpu_arch_isa
= cpu_arch
[j
].type
;
2352 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2353 if (!cpu_arch_tune_set
)
2355 cpu_arch_tune
= cpu_arch_isa
;
2356 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2361 if (!cpu_arch
[j
].negated
)
2362 flags
= cpu_flags_or (cpu_arch_flags
,
2365 flags
= cpu_flags_and_not (cpu_arch_flags
,
2368 if (!valid_iamcu_cpu_flags (&flags
))
2369 as_fatal (_("`%s' isn't valid for Intel MCU"),
2371 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2373 if (cpu_sub_arch_name
)
2375 char *name
= cpu_sub_arch_name
;
2376 cpu_sub_arch_name
= concat (name
,
2378 (const char *) NULL
);
2382 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2383 cpu_arch_flags
= flags
;
2384 cpu_arch_isa_flags
= flags
;
2386 *input_line_pointer
= e
;
2387 demand_empty_rest_of_line ();
2391 if (j
>= ARRAY_SIZE (cpu_arch
))
2392 as_bad (_("no such architecture: `%s'"), string
);
2394 *input_line_pointer
= e
;
2397 as_bad (_("missing cpu architecture"));
2399 no_cond_jump_promotion
= 0;
2400 if (*input_line_pointer
== ','
2401 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2403 char *string
= ++input_line_pointer
;
2404 int e
= get_symbol_end ();
2406 if (strcmp (string
, "nojumps") == 0)
2407 no_cond_jump_promotion
= 1;
2408 else if (strcmp (string
, "jumps") == 0)
2411 as_bad (_("no such architecture modifier: `%s'"), string
);
2413 *input_line_pointer
= e
;
2416 demand_empty_rest_of_line ();
2419 enum bfd_architecture
2422 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2424 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2425 || flag_code
!= CODE_64BIT
)
2426 as_fatal (_("Intel L1OM is 64bit ELF only"));
2427 return bfd_arch_l1om
;
2429 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2431 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2432 || flag_code
!= CODE_64BIT
)
2433 as_fatal (_("Intel K1OM is 64bit ELF only"));
2434 return bfd_arch_k1om
;
2436 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2438 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2439 || flag_code
== CODE_64BIT
)
2440 as_fatal (_("Intel MCU is 32bit ELF only"));
2441 return bfd_arch_iamcu
;
2444 return bfd_arch_i386
;
2450 if (!strncmp (default_arch
, "x86_64", 6))
2452 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2455 || default_arch
[6] != '\0')
2456 as_fatal (_("Intel L1OM is 64bit ELF only"));
2457 return bfd_mach_l1om
;
2459 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2461 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2462 || default_arch
[6] != '\0')
2463 as_fatal (_("Intel K1OM is 64bit ELF only"));
2464 return bfd_mach_k1om
;
2466 else if (default_arch
[6] == '\0')
2467 return bfd_mach_x86_64
;
2469 return bfd_mach_x64_32
;
2471 else if (!strcmp (default_arch
, "i386"))
2473 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2475 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu
;
2480 return bfd_mach_i386_i386
;
2483 as_fatal (_("unknown architecture"));
2489 const char *hash_err
;
2491 /* Initialize op_hash hash table. */
2492 op_hash
= hash_new ();
2495 const insn_template
*optab
;
2496 templates
*core_optab
;
2498 /* Setup for loop. */
2500 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2501 core_optab
->start
= optab
;
2506 if (optab
->name
== NULL
2507 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2509 /* different name --> ship out current template list;
2510 add to hash table; & begin anew. */
2511 core_optab
->end
= optab
;
2512 hash_err
= hash_insert (op_hash
,
2514 (void *) core_optab
);
2517 as_fatal (_("can't hash %s: %s"),
2521 if (optab
->name
== NULL
)
2523 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2524 core_optab
->start
= optab
;
2529 /* Initialize reg_hash hash table. */
2530 reg_hash
= hash_new ();
2532 const reg_entry
*regtab
;
2533 unsigned int regtab_size
= i386_regtab_size
;
2535 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2537 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2539 as_fatal (_("can't hash %s: %s"),
2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2550 for (c
= 0; c
< 256; c
++)
2555 mnemonic_chars
[c
] = c
;
2556 register_chars
[c
] = c
;
2557 operand_chars
[c
] = c
;
2559 else if (ISLOWER (c
))
2561 mnemonic_chars
[c
] = c
;
2562 register_chars
[c
] = c
;
2563 operand_chars
[c
] = c
;
2565 else if (ISUPPER (c
))
2567 mnemonic_chars
[c
] = TOLOWER (c
);
2568 register_chars
[c
] = mnemonic_chars
[c
];
2569 operand_chars
[c
] = c
;
2571 else if (c
== '{' || c
== '}')
2572 operand_chars
[c
] = c
;
2574 if (ISALPHA (c
) || ISDIGIT (c
))
2575 identifier_chars
[c
] = c
;
2578 identifier_chars
[c
] = c
;
2579 operand_chars
[c
] = c
;
2584 identifier_chars
['@'] = '@';
2587 identifier_chars
['?'] = '?';
2588 operand_chars
['?'] = '?';
2590 digit_chars
['-'] = '-';
2591 mnemonic_chars
['_'] = '_';
2592 mnemonic_chars
['-'] = '-';
2593 mnemonic_chars
['.'] = '.';
2594 identifier_chars
['_'] = '_';
2595 identifier_chars
['.'] = '.';
2597 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2598 operand_chars
[(unsigned char) *p
] = *p
;
2601 if (flag_code
== CODE_64BIT
)
2603 #if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2607 x86_dwarf2_return_column
= 16;
2609 x86_cie_data_alignment
= -8;
2613 x86_dwarf2_return_column
= 8;
2614 x86_cie_data_alignment
= -4;
2619 i386_print_statistics (FILE *file
)
2621 hash_print_statistics (file
, "i386 opcode", op_hash
);
2622 hash_print_statistics (file
, "i386 register", reg_hash
);
2627 /* Debugging routines for md_assemble. */
2628 static void pte (insn_template
*);
2629 static void pt (i386_operand_type
);
2630 static void pe (expressionS
*);
2631 static void ps (symbolS
*);
2634 pi (char *line
, i386_insn
*x
)
2638 fprintf (stdout
, "%s: template ", line
);
2640 fprintf (stdout
, " address: base %s index %s scale %x\n",
2641 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2642 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2643 x
->log2_scale_factor
);
2644 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2645 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2646 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2647 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2648 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2649 (x
->rex
& REX_W
) != 0,
2650 (x
->rex
& REX_R
) != 0,
2651 (x
->rex
& REX_X
) != 0,
2652 (x
->rex
& REX_B
) != 0);
2653 for (j
= 0; j
< x
->operands
; j
++)
2655 fprintf (stdout
, " #%d: ", j
+ 1);
2657 fprintf (stdout
, "\n");
2658 if (x
->types
[j
].bitfield
.reg8
2659 || x
->types
[j
].bitfield
.reg16
2660 || x
->types
[j
].bitfield
.reg32
2661 || x
->types
[j
].bitfield
.reg64
2662 || x
->types
[j
].bitfield
.regmmx
2663 || x
->types
[j
].bitfield
.regxmm
2664 || x
->types
[j
].bitfield
.regymm
2665 || x
->types
[j
].bitfield
.regzmm
2666 || x
->types
[j
].bitfield
.sreg2
2667 || x
->types
[j
].bitfield
.sreg3
2668 || x
->types
[j
].bitfield
.control
2669 || x
->types
[j
].bitfield
.debug
2670 || x
->types
[j
].bitfield
.test
)
2671 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2672 if (operand_type_check (x
->types
[j
], imm
))
2674 if (operand_type_check (x
->types
[j
], disp
))
2675 pe (x
->op
[j
].disps
);
2680 pte (insn_template
*t
)
2683 fprintf (stdout
, " %d operands ", t
->operands
);
2684 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2685 if (t
->extension_opcode
!= None
)
2686 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2687 if (t
->opcode_modifier
.d
)
2688 fprintf (stdout
, "D");
2689 if (t
->opcode_modifier
.w
)
2690 fprintf (stdout
, "W");
2691 fprintf (stdout
, "\n");
2692 for (j
= 0; j
< t
->operands
; j
++)
2694 fprintf (stdout
, " #%d type ", j
+ 1);
2695 pt (t
->operand_types
[j
]);
2696 fprintf (stdout
, "\n");
2703 fprintf (stdout
, " operation %d\n", e
->X_op
);
2704 fprintf (stdout
, " add_number %ld (%lx)\n",
2705 (long) e
->X_add_number
, (long) e
->X_add_number
);
2706 if (e
->X_add_symbol
)
2708 fprintf (stdout
, " add_symbol ");
2709 ps (e
->X_add_symbol
);
2710 fprintf (stdout
, "\n");
2714 fprintf (stdout
, " op_symbol ");
2715 ps (e
->X_op_symbol
);
2716 fprintf (stdout
, "\n");
2723 fprintf (stdout
, "%s type %s%s",
2725 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s
)));
2729 static struct type_name
2731 i386_operand_type mask
;
2734 const type_names
[] =
2736 { OPERAND_TYPE_REG8
, "r8" },
2737 { OPERAND_TYPE_REG16
, "r16" },
2738 { OPERAND_TYPE_REG32
, "r32" },
2739 { OPERAND_TYPE_REG64
, "r64" },
2740 { OPERAND_TYPE_IMM8
, "i8" },
2741 { OPERAND_TYPE_IMM8
, "i8s" },
2742 { OPERAND_TYPE_IMM16
, "i16" },
2743 { OPERAND_TYPE_IMM32
, "i32" },
2744 { OPERAND_TYPE_IMM32S
, "i32s" },
2745 { OPERAND_TYPE_IMM64
, "i64" },
2746 { OPERAND_TYPE_IMM1
, "i1" },
2747 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8
, "d8" },
2749 { OPERAND_TYPE_DISP16
, "d16" },
2750 { OPERAND_TYPE_DISP32
, "d32" },
2751 { OPERAND_TYPE_DISP32S
, "d32s" },
2752 { OPERAND_TYPE_DISP64
, "d64" },
2753 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2754 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL
, "control reg" },
2757 { OPERAND_TYPE_TEST
, "test reg" },
2758 { OPERAND_TYPE_DEBUG
, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG
, "FReg" },
2760 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2761 { OPERAND_TYPE_SREG2
, "SReg2" },
2762 { OPERAND_TYPE_SREG3
, "SReg3" },
2763 { OPERAND_TYPE_ACC
, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX
, "rMMX" },
2766 { OPERAND_TYPE_REGXMM
, "rXMM" },
2767 { OPERAND_TYPE_REGYMM
, "rYMM" },
2768 { OPERAND_TYPE_REGZMM
, "rZMM" },
2769 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2770 { OPERAND_TYPE_ESSEG
, "es" },
2774 pt (i386_operand_type t
)
2777 i386_operand_type a
;
2779 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2781 a
= operand_type_and (t
, type_names
[j
].mask
);
2782 if (!operand_type_all_zero (&a
))
2783 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2788 #endif /* DEBUG386 */
2790 static bfd_reloc_code_real_type
2791 reloc (unsigned int size
,
2794 bfd_reloc_code_real_type other
)
2796 if (other
!= NO_RELOC
)
2798 reloc_howto_type
*rel
;
2803 case BFD_RELOC_X86_64_GOT32
:
2804 return BFD_RELOC_X86_64_GOT64
;
2806 case BFD_RELOC_X86_64_GOTPLT64
:
2807 return BFD_RELOC_X86_64_GOTPLT64
;
2809 case BFD_RELOC_X86_64_PLTOFF64
:
2810 return BFD_RELOC_X86_64_PLTOFF64
;
2812 case BFD_RELOC_X86_64_GOTPC32
:
2813 other
= BFD_RELOC_X86_64_GOTPC64
;
2815 case BFD_RELOC_X86_64_GOTPCREL
:
2816 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2818 case BFD_RELOC_X86_64_TPOFF32
:
2819 other
= BFD_RELOC_X86_64_TPOFF64
;
2821 case BFD_RELOC_X86_64_DTPOFF32
:
2822 other
= BFD_RELOC_X86_64_DTPOFF64
;
2828 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2829 if (other
== BFD_RELOC_SIZE32
)
2832 other
= BFD_RELOC_SIZE64
;
2835 as_bad (_("there are no pc-relative size relocations"));
2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2842 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2845 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2847 as_bad (_("unknown relocation (%u)"), other
);
2848 else if (size
!= bfd_get_reloc_size (rel
))
2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2850 bfd_get_reloc_size (rel
),
2852 else if (pcrel
&& !rel
->pc_relative
)
2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
2854 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2856 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2858 as_bad (_("relocated field and relocation type differ in signedness"));
2867 as_bad (_("there are no unsigned pc-relative relocations"));
2870 case 1: return BFD_RELOC_8_PCREL
;
2871 case 2: return BFD_RELOC_16_PCREL
;
2872 case 4: return BFD_RELOC_32_PCREL
;
2873 case 8: return BFD_RELOC_64_PCREL
;
2875 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2882 case 4: return BFD_RELOC_X86_64_32S
;
2887 case 1: return BFD_RELOC_8
;
2888 case 2: return BFD_RELOC_16
;
2889 case 4: return BFD_RELOC_32
;
2890 case 8: return BFD_RELOC_64
;
2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign
> 0 ? "signed" : "unsigned", size
);
2899 /* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2905 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2921 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2927 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2928 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2929 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2930 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2931 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2932 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2933 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2941 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2942 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2943 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2954 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2955 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2962 intel_float_operand (const char *mnemonic
)
2964 /* Note that the value returned is meaningful only for opcodes with (memory)
2965 operands, hence the code here is free to improperly handle opcodes that
2966 have no operands (for better performance and smaller code). */
2968 if (mnemonic
[0] != 'f')
2969 return 0; /* non-math */
2971 switch (mnemonic
[1])
2973 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2974 the fs segment override prefix not currently handled because no
2975 call path can make opcodes without operands get here */
2977 return 2 /* integer op */;
2979 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2980 return 3; /* fldcw/fldenv */
2983 if (mnemonic
[2] != 'o' /* fnop */)
2984 return 3; /* non-waiting control op */
2987 if (mnemonic
[2] == 's')
2988 return 3; /* frstor/frstpm */
2991 if (mnemonic
[2] == 'a')
2992 return 3; /* fsave */
2993 if (mnemonic
[2] == 't')
2995 switch (mnemonic
[3])
2997 case 'c': /* fstcw */
2998 case 'd': /* fstdw */
2999 case 'e': /* fstenv */
3000 case 's': /* fsts[gw] */
3006 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3007 return 0; /* fxsave/fxrstor are not really math ops */
3014 /* Build the VEX prefix. */
3017 build_vex_prefix (const insn_template
*t
)
3019 unsigned int register_specifier
;
3020 unsigned int implied_prefix
;
3021 unsigned int vector_length
;
3023 /* Check register specifier. */
3024 if (i
.vex
.register_specifier
)
3026 register_specifier
=
3027 ~register_number (i
.vex
.register_specifier
) & 0xf;
3028 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3031 register_specifier
= 0xf;
3033 /* Use 2-byte VEX prefix by swappping destination and source
3036 && i
.operands
== i
.reg_operands
3037 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3038 && i
.tm
.opcode_modifier
.s
3041 unsigned int xchg
= i
.operands
- 1;
3042 union i386_op temp_op
;
3043 i386_operand_type temp_type
;
3045 temp_type
= i
.types
[xchg
];
3046 i
.types
[xchg
] = i
.types
[0];
3047 i
.types
[0] = temp_type
;
3048 temp_op
= i
.op
[xchg
];
3049 i
.op
[xchg
] = i
.op
[0];
3052 gas_assert (i
.rm
.mode
== 3);
3056 i
.rm
.regmem
= i
.rm
.reg
;
3059 /* Use the next insn. */
3063 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3064 vector_length
= avxscalar
;
3066 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3068 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3073 case DATA_PREFIX_OPCODE
:
3076 case REPE_PREFIX_OPCODE
:
3079 case REPNE_PREFIX_OPCODE
:
3086 /* Use 2-byte VEX prefix if possible. */
3087 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3088 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3089 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3091 /* 2-byte VEX prefix. */
3095 i
.vex
.bytes
[0] = 0xc5;
3097 /* Check the REX.R bit. */
3098 r
= (i
.rex
& REX_R
) ? 0 : 1;
3099 i
.vex
.bytes
[1] = (r
<< 7
3100 | register_specifier
<< 3
3101 | vector_length
<< 2
3106 /* 3-byte VEX prefix. */
3111 switch (i
.tm
.opcode_modifier
.vexopcode
)
3115 i
.vex
.bytes
[0] = 0xc4;
3119 i
.vex
.bytes
[0] = 0xc4;
3123 i
.vex
.bytes
[0] = 0xc4;
3127 i
.vex
.bytes
[0] = 0x8f;
3131 i
.vex
.bytes
[0] = 0x8f;
3135 i
.vex
.bytes
[0] = 0x8f;
3141 /* The high 3 bits of the second VEX byte are 1's compliment
3142 of RXB bits from REX. */
3143 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3145 /* Check the REX.W bit. */
3146 w
= (i
.rex
& REX_W
) ? 1 : 0;
3147 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3150 i
.vex
.bytes
[2] = (w
<< 7
3151 | register_specifier
<< 3
3152 | vector_length
<< 2
3157 /* Build the EVEX prefix. */
3160 build_evex_prefix (void)
3162 unsigned int register_specifier
;
3163 unsigned int implied_prefix
;
3165 rex_byte vrex_used
= 0;
3167 /* Check register specifier. */
3168 if (i
.vex
.register_specifier
)
3170 gas_assert ((i
.vrex
& REX_X
) == 0);
3172 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3173 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3174 register_specifier
+= 8;
3175 /* The upper 16 registers are encoded in the fourth byte of the
3177 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3178 i
.vex
.bytes
[3] = 0x8;
3179 register_specifier
= ~register_specifier
& 0xf;
3183 register_specifier
= 0xf;
3185 /* Encode upper 16 vector index register in the fourth byte of
3187 if (!(i
.vrex
& REX_X
))
3188 i
.vex
.bytes
[3] = 0x8;
3193 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3198 case DATA_PREFIX_OPCODE
:
3201 case REPE_PREFIX_OPCODE
:
3204 case REPNE_PREFIX_OPCODE
:
3211 /* 4 byte EVEX prefix. */
3213 i
.vex
.bytes
[0] = 0x62;
3216 switch (i
.tm
.opcode_modifier
.vexopcode
)
3232 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3234 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3236 /* The fifth bit of the second EVEX byte is 1's compliment of the
3237 REX_R bit in VREX. */
3238 if (!(i
.vrex
& REX_R
))
3239 i
.vex
.bytes
[1] |= 0x10;
3243 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3245 /* When all operands are registers, the REX_X bit in REX is not
3246 used. We reuse it to encode the upper 16 registers, which is
3247 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3248 as 1's compliment. */
3249 if ((i
.vrex
& REX_B
))
3252 i
.vex
.bytes
[1] &= ~0x40;
3256 /* EVEX instructions shouldn't need the REX prefix. */
3257 i
.vrex
&= ~vrex_used
;
3258 gas_assert (i
.vrex
== 0);
3260 /* Check the REX.W bit. */
3261 w
= (i
.rex
& REX_W
) ? 1 : 0;
3262 if (i
.tm
.opcode_modifier
.vexw
)
3264 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3267 /* If w is not set it means we are dealing with WIG instruction. */
3270 if (evexwig
== evexw1
)
3274 /* Encode the U bit. */
3275 implied_prefix
|= 0x4;
3277 /* The third byte of the EVEX prefix. */
3278 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3280 /* The fourth byte of the EVEX prefix. */
3281 /* The zeroing-masking bit. */
3282 if (i
.mask
&& i
.mask
->zeroing
)
3283 i
.vex
.bytes
[3] |= 0x80;
3285 /* Don't always set the broadcast bit if there is no RC. */
3288 /* Encode the vector length. */
3289 unsigned int vec_length
;
3291 switch (i
.tm
.opcode_modifier
.evex
)
3293 case EVEXLIG
: /* LL' is ignored */
3294 vec_length
= evexlig
<< 5;
3297 vec_length
= 0 << 5;
3300 vec_length
= 1 << 5;
3303 vec_length
= 2 << 5;
3309 i
.vex
.bytes
[3] |= vec_length
;
3310 /* Encode the broadcast bit. */
3312 i
.vex
.bytes
[3] |= 0x10;
3316 if (i
.rounding
->type
!= saeonly
)
3317 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3319 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3322 if (i
.mask
&& i
.mask
->mask
)
3323 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3327 process_immext (void)
3331 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3334 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3335 with an opcode suffix which is coded in the same place as an
3336 8-bit immediate field would be.
3337 Here we check those operands and remove them afterwards. */
3340 for (x
= 0; x
< i
.operands
; x
++)
3341 if (register_number (i
.op
[x
].regs
) != x
)
3342 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3343 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3349 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3350 which is coded in the same place as an 8-bit immediate field
3351 would be. Here we fake an 8-bit immediate operand from the
3352 opcode suffix stored in tm.extension_opcode.
3354 AVX instructions also use this encoding, for some of
3355 3 argument instructions. */
3357 gas_assert (i
.imm_operands
<= 1
3359 || ((i
.tm
.opcode_modifier
.vex
3360 || i
.tm
.opcode_modifier
.evex
)
3361 && i
.operands
<= 4)));
3363 exp
= &im_expressions
[i
.imm_operands
++];
3364 i
.op
[i
.operands
].imms
= exp
;
3365 i
.types
[i
.operands
] = imm8
;
3367 exp
->X_op
= O_constant
;
3368 exp
->X_add_number
= i
.tm
.extension_opcode
;
3369 i
.tm
.extension_opcode
= None
;
3376 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3381 as_bad (_("invalid instruction `%s' after `%s'"),
3382 i
.tm
.name
, i
.hle_prefix
);
3385 if (i
.prefix
[LOCK_PREFIX
])
3387 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3391 case HLEPrefixRelease
:
3392 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3394 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3398 if (i
.mem_operands
== 0
3399 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3401 as_bad (_("memory destination needed for instruction `%s'"
3402 " after `xrelease'"), i
.tm
.name
);
3409 /* This is the guts of the machine-dependent assembler. LINE points to a
3410 machine dependent instruction. This function is supposed to emit
3411 the frags/bytes it assembles to. */
3414 md_assemble (char *line
)
3417 char mnemonic
[MAX_MNEM_SIZE
];
3418 const insn_template
*t
;
3420 /* Initialize globals. */
3421 memset (&i
, '\0', sizeof (i
));
3422 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3423 i
.reloc
[j
] = NO_RELOC
;
3424 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3425 memset (im_expressions
, '\0', sizeof (im_expressions
));
3426 save_stack_p
= save_stack
;
3428 /* First parse an instruction mnemonic & call i386_operand for the operands.
3429 We assume that the scrubber has arranged it so that line[0] is the valid
3430 start of a (possibly prefixed) mnemonic. */
3432 line
= parse_insn (line
, mnemonic
);
3436 line
= parse_operands (line
, mnemonic
);
3441 /* Now we've parsed the mnemonic into a set of templates, and have the
3442 operands at hand. */
3444 /* All intel opcodes have reversed operands except for "bound" and
3445 "enter". We also don't reverse intersegment "jmp" and "call"
3446 instructions with 2 immediate operands so that the immediate segment
3447 precedes the offset, as it does when in AT&T mode. */
3450 && (strcmp (mnemonic
, "bound") != 0)
3451 && (strcmp (mnemonic
, "invlpga") != 0)
3452 && !(operand_type_check (i
.types
[0], imm
)
3453 && operand_type_check (i
.types
[1], imm
)))
3456 /* The order of the immediates should be reversed
3457 for 2 immediates extrq and insertq instructions */
3458 if (i
.imm_operands
== 2
3459 && (strcmp (mnemonic
, "extrq") == 0
3460 || strcmp (mnemonic
, "insertq") == 0))
3461 swap_2_operands (0, 1);
3466 /* Don't optimize displacement for movabs since it only takes 64bit
3469 && i
.disp_encoding
!= disp_encoding_32bit
3470 && (flag_code
!= CODE_64BIT
3471 || strcmp (mnemonic
, "movabs") != 0))
3474 /* Next, we find a template that matches the given insn,
3475 making sure the overlap of the given operands types is consistent
3476 with the template operand types. */
3478 if (!(t
= match_template ()))
3481 if (sse_check
!= check_none
3482 && !i
.tm
.opcode_modifier
.noavx
3483 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3484 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3485 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3486 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3487 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3488 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3490 (sse_check
== check_warning
3492 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3495 /* Zap movzx and movsx suffix. The suffix has been set from
3496 "word ptr" or "byte ptr" on the source operand in Intel syntax
3497 or extracted from mnemonic in AT&T syntax. But we'll use
3498 the destination register to choose the suffix for encoding. */
3499 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3501 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3502 there is no suffix, the default will be byte extension. */
3503 if (i
.reg_operands
!= 2
3506 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3511 if (i
.tm
.opcode_modifier
.fwait
)
3512 if (!add_prefix (FWAIT_OPCODE
))
3515 /* Check if REP prefix is OK. */
3516 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3518 as_bad (_("invalid instruction `%s' after `%s'"),
3519 i
.tm
.name
, i
.rep_prefix
);
3523 /* Check for lock without a lockable instruction. Destination operand
3524 must be memory unless it is xchg (0x86). */
3525 if (i
.prefix
[LOCK_PREFIX
]
3526 && (!i
.tm
.opcode_modifier
.islockable
3527 || i
.mem_operands
== 0
3528 || (i
.tm
.base_opcode
!= 0x86
3529 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3531 as_bad (_("expecting lockable instruction after `lock'"));
3535 /* Check if HLE prefix is OK. */
3536 if (i
.hle_prefix
&& !check_hle ())
3539 /* Check BND prefix. */
3540 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3541 as_bad (_("expecting valid branch instruction after `bnd'"));
3543 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3544 && flag_code
== CODE_64BIT
3545 && i
.prefix
[ADDR_PREFIX
])
3546 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3548 /* Insert BND prefix. */
3550 && i
.tm
.opcode_modifier
.bndprefixok
3551 && !i
.prefix
[BND_PREFIX
])
3552 add_prefix (BND_PREFIX_OPCODE
);
3554 /* Check string instruction segment overrides. */
3555 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3557 if (!check_string ())
3559 i
.disp_operands
= 0;
3562 if (!process_suffix ())
3565 /* Update operand types. */
3566 for (j
= 0; j
< i
.operands
; j
++)
3567 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3569 /* Make still unresolved immediate matches conform to size of immediate
3570 given in i.suffix. */
3571 if (!finalize_imm ())
3574 if (i
.types
[0].bitfield
.imm1
)
3575 i
.imm_operands
= 0; /* kludge for shift insns. */
3577 /* We only need to check those implicit registers for instructions
3578 with 3 operands or less. */
3579 if (i
.operands
<= 3)
3580 for (j
= 0; j
< i
.operands
; j
++)
3581 if (i
.types
[j
].bitfield
.inoutportreg
3582 || i
.types
[j
].bitfield
.shiftcount
3583 || i
.types
[j
].bitfield
.acc
3584 || i
.types
[j
].bitfield
.floatacc
)
3587 /* ImmExt should be processed after SSE2AVX. */
3588 if (!i
.tm
.opcode_modifier
.sse2avx
3589 && i
.tm
.opcode_modifier
.immext
)
3592 /* For insns with operands there are more diddles to do to the opcode. */
3595 if (!process_operands ())
3598 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3600 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3601 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3604 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3606 if (flag_code
== CODE_16BIT
)
3608 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3613 if (i
.tm
.opcode_modifier
.vex
)
3614 build_vex_prefix (t
);
3616 build_evex_prefix ();
3619 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3620 instructions may define INT_OPCODE as well, so avoid this corner
3621 case for those instructions that use MODRM. */
3622 if (i
.tm
.base_opcode
== INT_OPCODE
3623 && !i
.tm
.opcode_modifier
.modrm
3624 && i
.op
[0].imms
->X_add_number
== 3)
3626 i
.tm
.base_opcode
= INT3_OPCODE
;
3630 if ((i
.tm
.opcode_modifier
.jump
3631 || i
.tm
.opcode_modifier
.jumpbyte
3632 || i
.tm
.opcode_modifier
.jumpdword
)
3633 && i
.op
[0].disps
->X_op
== O_constant
)
3635 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3636 the absolute address given by the constant. Since ix86 jumps and
3637 calls are pc relative, we need to generate a reloc. */
3638 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3639 i
.op
[0].disps
->X_op
= O_symbol
;
3642 if (i
.tm
.opcode_modifier
.rex64
)
3645 /* For 8 bit registers we need an empty rex prefix. Also if the
3646 instruction already has a prefix, we need to convert old
3647 registers to new ones. */
3649 if ((i
.types
[0].bitfield
.reg8
3650 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3651 || (i
.types
[1].bitfield
.reg8
3652 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3653 || ((i
.types
[0].bitfield
.reg8
3654 || i
.types
[1].bitfield
.reg8
)
3659 i
.rex
|= REX_OPCODE
;
3660 for (x
= 0; x
< 2; x
++)
3662 /* Look for 8 bit operand that uses old registers. */
3663 if (i
.types
[x
].bitfield
.reg8
3664 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3666 /* In case it is "hi" register, give up. */
3667 if (i
.op
[x
].regs
->reg_num
> 3)
3668 as_bad (_("can't encode register '%s%s' in an "
3669 "instruction requiring REX prefix."),
3670 register_prefix
, i
.op
[x
].regs
->reg_name
);
3672 /* Otherwise it is equivalent to the extended register.
3673 Since the encoding doesn't change this is merely
3674 cosmetic cleanup for debug output. */
3676 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3682 add_prefix (REX_OPCODE
| i
.rex
);
3684 /* We are ready to output the insn. */
3689 parse_insn (char *line
, char *mnemonic
)
3692 char *token_start
= l
;
3695 const insn_template
*t
;
3701 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3706 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3708 as_bad (_("no such instruction: `%s'"), token_start
);
3713 if (!is_space_char (*l
)
3714 && *l
!= END_OF_INSN
3716 || (*l
!= PREFIX_SEPARATOR
3719 as_bad (_("invalid character %s in mnemonic"),
3720 output_invalid (*l
));
3723 if (token_start
== l
)
3725 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3726 as_bad (_("expecting prefix; got nothing"));
3728 as_bad (_("expecting mnemonic; got nothing"));
3732 /* Look up instruction (or prefix) via hash table. */
3733 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3735 if (*l
!= END_OF_INSN
3736 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3737 && current_templates
3738 && current_templates
->start
->opcode_modifier
.isprefix
)
3740 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3742 as_bad ((flag_code
!= CODE_64BIT
3743 ? _("`%s' is only supported in 64-bit mode")
3744 : _("`%s' is not supported in 64-bit mode")),
3745 current_templates
->start
->name
);
3748 /* If we are in 16-bit mode, do not allow addr16 or data16.
3749 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3750 if ((current_templates
->start
->opcode_modifier
.size16
3751 || current_templates
->start
->opcode_modifier
.size32
)
3752 && flag_code
!= CODE_64BIT
3753 && (current_templates
->start
->opcode_modifier
.size32
3754 ^ (flag_code
== CODE_16BIT
)))
3756 as_bad (_("redundant %s prefix"),
3757 current_templates
->start
->name
);
3760 /* Add prefix, checking for repeated prefixes. */
3761 switch (add_prefix (current_templates
->start
->base_opcode
))
3766 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3767 i
.hle_prefix
= current_templates
->start
->name
;
3768 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3769 i
.bnd_prefix
= current_templates
->start
->name
;
3771 i
.rep_prefix
= current_templates
->start
->name
;
3776 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3783 if (!current_templates
)
3785 /* Check if we should swap operand or force 32bit displacement in
3787 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3789 else if (mnem_p
- 3 == dot_p
3792 i
.disp_encoding
= disp_encoding_8bit
;
3793 else if (mnem_p
- 4 == dot_p
3797 i
.disp_encoding
= disp_encoding_32bit
;
3802 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3805 if (!current_templates
)
3808 /* See if we can get a match by trimming off a suffix. */
3811 case WORD_MNEM_SUFFIX
:
3812 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3813 i
.suffix
= SHORT_MNEM_SUFFIX
;
3815 case BYTE_MNEM_SUFFIX
:
3816 case QWORD_MNEM_SUFFIX
:
3817 i
.suffix
= mnem_p
[-1];
3819 current_templates
= (const templates
*) hash_find (op_hash
,
3822 case SHORT_MNEM_SUFFIX
:
3823 case LONG_MNEM_SUFFIX
:
3826 i
.suffix
= mnem_p
[-1];
3828 current_templates
= (const templates
*) hash_find (op_hash
,
3837 if (intel_float_operand (mnemonic
) == 1)
3838 i
.suffix
= SHORT_MNEM_SUFFIX
;
3840 i
.suffix
= LONG_MNEM_SUFFIX
;
3842 current_templates
= (const templates
*) hash_find (op_hash
,
3847 if (!current_templates
)
3849 as_bad (_("no such instruction: `%s'"), token_start
);
3854 if (current_templates
->start
->opcode_modifier
.jump
3855 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3857 /* Check for a branch hint. We allow ",pt" and ",pn" for
3858 predict taken and predict not taken respectively.
3859 I'm not sure that branch hints actually do anything on loop
3860 and jcxz insns (JumpByte) for current Pentium4 chips. They
3861 may work in the future and it doesn't hurt to accept them
3863 if (l
[0] == ',' && l
[1] == 'p')
3867 if (!add_prefix (DS_PREFIX_OPCODE
))
3871 else if (l
[2] == 'n')
3873 if (!add_prefix (CS_PREFIX_OPCODE
))
3879 /* Any other comma loses. */
3882 as_bad (_("invalid character %s in mnemonic"),
3883 output_invalid (*l
));
3887 /* Check if instruction is supported on specified architecture. */
3889 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3891 supported
|= cpu_flags_match (t
);
3892 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3896 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3898 as_bad (flag_code
== CODE_64BIT
3899 ? _("`%s' is not supported in 64-bit mode")
3900 : _("`%s' is only supported in 64-bit mode"),
3901 current_templates
->start
->name
);
3904 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3906 as_bad (_("`%s' is not supported on `%s%s'"),
3907 current_templates
->start
->name
,
3908 cpu_arch_name
? cpu_arch_name
: default_arch
,
3909 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3914 if (!cpu_arch_flags
.bitfield
.cpui386
3915 && (flag_code
!= CODE_16BIT
))
3917 as_warn (_("use .code16 to ensure correct addressing mode"));
3924 parse_operands (char *l
, const char *mnemonic
)
3928 /* 1 if operand is pending after ','. */
3929 unsigned int expecting_operand
= 0;
3931 /* Non-zero if operand parens not balanced. */
3932 unsigned int paren_not_balanced
;
3934 while (*l
!= END_OF_INSN
)
3936 /* Skip optional white space before operand. */
3937 if (is_space_char (*l
))
3939 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3941 as_bad (_("invalid character %s before operand %d"),
3942 output_invalid (*l
),
3946 token_start
= l
; /* after white space */
3947 paren_not_balanced
= 0;
3948 while (paren_not_balanced
|| *l
!= ',')
3950 if (*l
== END_OF_INSN
)
3952 if (paren_not_balanced
)
3955 as_bad (_("unbalanced parenthesis in operand %d."),
3958 as_bad (_("unbalanced brackets in operand %d."),
3963 break; /* we are done */
3965 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3967 as_bad (_("invalid character %s in operand %d"),
3968 output_invalid (*l
),
3975 ++paren_not_balanced
;
3977 --paren_not_balanced
;
3982 ++paren_not_balanced
;
3984 --paren_not_balanced
;
3988 if (l
!= token_start
)
3989 { /* Yes, we've read in another operand. */
3990 unsigned int operand_ok
;
3991 this_operand
= i
.operands
++;
3992 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3993 if (i
.operands
> MAX_OPERANDS
)
3995 as_bad (_("spurious operands; (%d operands/instruction max)"),
3999 /* Now parse operand adding info to 'i' as we go along. */
4000 END_STRING_AND_SAVE (l
);
4004 i386_intel_operand (token_start
,
4005 intel_float_operand (mnemonic
));
4007 operand_ok
= i386_att_operand (token_start
);
4009 RESTORE_END_STRING (l
);
4015 if (expecting_operand
)
4017 expecting_operand_after_comma
:
4018 as_bad (_("expecting operand after ','; got nothing"));
4023 as_bad (_("expecting operand before ','; got nothing"));
4028 /* Now *l must be either ',' or END_OF_INSN. */
4031 if (*++l
== END_OF_INSN
)
4033 /* Just skip it, if it's \n complain. */
4034 goto expecting_operand_after_comma
;
4036 expecting_operand
= 1;
4043 swap_2_operands (int xchg1
, int xchg2
)
4045 union i386_op temp_op
;
4046 i386_operand_type temp_type
;
4047 enum bfd_reloc_code_real temp_reloc
;
4049 temp_type
= i
.types
[xchg2
];
4050 i
.types
[xchg2
] = i
.types
[xchg1
];
4051 i
.types
[xchg1
] = temp_type
;
4052 temp_op
= i
.op
[xchg2
];
4053 i
.op
[xchg2
] = i
.op
[xchg1
];
4054 i
.op
[xchg1
] = temp_op
;
4055 temp_reloc
= i
.reloc
[xchg2
];
4056 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4057 i
.reloc
[xchg1
] = temp_reloc
;
4061 if (i
.mask
->operand
== xchg1
)
4062 i
.mask
->operand
= xchg2
;
4063 else if (i
.mask
->operand
== xchg2
)
4064 i
.mask
->operand
= xchg1
;
4068 if (i
.broadcast
->operand
== xchg1
)
4069 i
.broadcast
->operand
= xchg2
;
4070 else if (i
.broadcast
->operand
== xchg2
)
4071 i
.broadcast
->operand
= xchg1
;
4075 if (i
.rounding
->operand
== xchg1
)
4076 i
.rounding
->operand
= xchg2
;
4077 else if (i
.rounding
->operand
== xchg2
)
4078 i
.rounding
->operand
= xchg1
;
4083 swap_operands (void)
4089 swap_2_operands (1, i
.operands
- 2);
4092 swap_2_operands (0, i
.operands
- 1);
4098 if (i
.mem_operands
== 2)
4100 const seg_entry
*temp_seg
;
4101 temp_seg
= i
.seg
[0];
4102 i
.seg
[0] = i
.seg
[1];
4103 i
.seg
[1] = temp_seg
;
4107 /* Try to ensure constant immediates are represented in the smallest
4112 char guess_suffix
= 0;
4116 guess_suffix
= i
.suffix
;
4117 else if (i
.reg_operands
)
4119 /* Figure out a suffix from the last register operand specified.
4120 We can't do this properly yet, ie. excluding InOutPortReg,
4121 but the following works for instructions with immediates.
4122 In any case, we can't set i.suffix yet. */
4123 for (op
= i
.operands
; --op
>= 0;)
4124 if (i
.types
[op
].bitfield
.reg8
)
4126 guess_suffix
= BYTE_MNEM_SUFFIX
;
4129 else if (i
.types
[op
].bitfield
.reg16
)
4131 guess_suffix
= WORD_MNEM_SUFFIX
;
4134 else if (i
.types
[op
].bitfield
.reg32
)
4136 guess_suffix
= LONG_MNEM_SUFFIX
;
4139 else if (i
.types
[op
].bitfield
.reg64
)
4141 guess_suffix
= QWORD_MNEM_SUFFIX
;
4145 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4146 guess_suffix
= WORD_MNEM_SUFFIX
;
4148 for (op
= i
.operands
; --op
>= 0;)
4149 if (operand_type_check (i
.types
[op
], imm
))
4151 switch (i
.op
[op
].imms
->X_op
)
4154 /* If a suffix is given, this operand may be shortened. */
4155 switch (guess_suffix
)
4157 case LONG_MNEM_SUFFIX
:
4158 i
.types
[op
].bitfield
.imm32
= 1;
4159 i
.types
[op
].bitfield
.imm64
= 1;
4161 case WORD_MNEM_SUFFIX
:
4162 i
.types
[op
].bitfield
.imm16
= 1;
4163 i
.types
[op
].bitfield
.imm32
= 1;
4164 i
.types
[op
].bitfield
.imm32s
= 1;
4165 i
.types
[op
].bitfield
.imm64
= 1;
4167 case BYTE_MNEM_SUFFIX
:
4168 i
.types
[op
].bitfield
.imm8
= 1;
4169 i
.types
[op
].bitfield
.imm8s
= 1;
4170 i
.types
[op
].bitfield
.imm16
= 1;
4171 i
.types
[op
].bitfield
.imm32
= 1;
4172 i
.types
[op
].bitfield
.imm32s
= 1;
4173 i
.types
[op
].bitfield
.imm64
= 1;
4177 /* If this operand is at most 16 bits, convert it
4178 to a signed 16 bit number before trying to see
4179 whether it will fit in an even smaller size.
4180 This allows a 16-bit operand such as $0xffe0 to
4181 be recognised as within Imm8S range. */
4182 if ((i
.types
[op
].bitfield
.imm16
)
4183 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4185 i
.op
[op
].imms
->X_add_number
=
4186 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4188 if ((i
.types
[op
].bitfield
.imm32
)
4189 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4192 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4193 ^ ((offsetT
) 1 << 31))
4194 - ((offsetT
) 1 << 31));
4197 = operand_type_or (i
.types
[op
],
4198 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4200 /* We must avoid matching of Imm32 templates when 64bit
4201 only immediate is available. */
4202 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4203 i
.types
[op
].bitfield
.imm32
= 0;
4210 /* Symbols and expressions. */
4212 /* Convert symbolic operand to proper sizes for matching, but don't
4213 prevent matching a set of insns that only supports sizes other
4214 than those matching the insn suffix. */
4216 i386_operand_type mask
, allowed
;
4217 const insn_template
*t
;
4219 operand_type_set (&mask
, 0);
4220 operand_type_set (&allowed
, 0);
4222 for (t
= current_templates
->start
;
4223 t
< current_templates
->end
;
4225 allowed
= operand_type_or (allowed
,
4226 t
->operand_types
[op
]);
4227 switch (guess_suffix
)
4229 case QWORD_MNEM_SUFFIX
:
4230 mask
.bitfield
.imm64
= 1;
4231 mask
.bitfield
.imm32s
= 1;
4233 case LONG_MNEM_SUFFIX
:
4234 mask
.bitfield
.imm32
= 1;
4236 case WORD_MNEM_SUFFIX
:
4237 mask
.bitfield
.imm16
= 1;
4239 case BYTE_MNEM_SUFFIX
:
4240 mask
.bitfield
.imm8
= 1;
4245 allowed
= operand_type_and (mask
, allowed
);
4246 if (!operand_type_all_zero (&allowed
))
4247 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4254 /* Try to use the smallest displacement type too. */
4256 optimize_disp (void)
4260 for (op
= i
.operands
; --op
>= 0;)
4261 if (operand_type_check (i
.types
[op
], disp
))
4263 if (i
.op
[op
].disps
->X_op
== O_constant
)
4265 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4267 if (i
.types
[op
].bitfield
.disp16
4268 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4270 /* If this operand is at most 16 bits, convert
4271 to a signed 16 bit number and don't use 64bit
4273 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4274 i
.types
[op
].bitfield
.disp64
= 0;
4276 if (i
.types
[op
].bitfield
.disp32
4277 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4279 /* If this operand is at most 32 bits, convert
4280 to a signed 32 bit number and don't use 64bit
4282 op_disp
&= (((offsetT
) 2 << 31) - 1);
4283 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4284 i
.types
[op
].bitfield
.disp64
= 0;
4286 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4288 i
.types
[op
].bitfield
.disp8
= 0;
4289 i
.types
[op
].bitfield
.disp16
= 0;
4290 i
.types
[op
].bitfield
.disp32
= 0;
4291 i
.types
[op
].bitfield
.disp32s
= 0;
4292 i
.types
[op
].bitfield
.disp64
= 0;
4296 else if (flag_code
== CODE_64BIT
)
4298 if (fits_in_signed_long (op_disp
))
4300 i
.types
[op
].bitfield
.disp64
= 0;
4301 i
.types
[op
].bitfield
.disp32s
= 1;
4303 if (i
.prefix
[ADDR_PREFIX
]
4304 && fits_in_unsigned_long (op_disp
))
4305 i
.types
[op
].bitfield
.disp32
= 1;
4307 if ((i
.types
[op
].bitfield
.disp32
4308 || i
.types
[op
].bitfield
.disp32s
4309 || i
.types
[op
].bitfield
.disp16
)
4310 && fits_in_signed_byte (op_disp
))
4311 i
.types
[op
].bitfield
.disp8
= 1;
4313 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4314 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4316 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4317 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4318 i
.types
[op
].bitfield
.disp8
= 0;
4319 i
.types
[op
].bitfield
.disp16
= 0;
4320 i
.types
[op
].bitfield
.disp32
= 0;
4321 i
.types
[op
].bitfield
.disp32s
= 0;
4322 i
.types
[op
].bitfield
.disp64
= 0;
4325 /* We only support 64bit displacement on constants. */
4326 i
.types
[op
].bitfield
.disp64
= 0;
4330 /* Check if operands are valid for the instruction. */
4333 check_VecOperands (const insn_template
*t
)
4337 /* Without VSIB byte, we can't have a vector register for index. */
4338 if (!t
->opcode_modifier
.vecsib
4340 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4341 || i
.index_reg
->reg_type
.bitfield
.regymm
4342 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4344 i
.error
= unsupported_vector_index_register
;
4348 /* Check if default mask is allowed. */
4349 if (t
->opcode_modifier
.nodefmask
4350 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4352 i
.error
= no_default_mask
;
4356 /* For VSIB byte, we need a vector register for index, and all vector
4357 registers must be distinct. */
4358 if (t
->opcode_modifier
.vecsib
)
4361 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4362 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4363 || (t
->opcode_modifier
.vecsib
== VecSIB256
4364 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4365 || (t
->opcode_modifier
.vecsib
== VecSIB512
4366 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4368 i
.error
= invalid_vsib_address
;
4372 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4373 if (i
.reg_operands
== 2 && !i
.mask
)
4375 gas_assert (i
.types
[0].bitfield
.regxmm
4376 || i
.types
[0].bitfield
.regymm
);
4377 gas_assert (i
.types
[2].bitfield
.regxmm
4378 || i
.types
[2].bitfield
.regymm
);
4379 if (operand_check
== check_none
)
4381 if (register_number (i
.op
[0].regs
)
4382 != register_number (i
.index_reg
)
4383 && register_number (i
.op
[2].regs
)
4384 != register_number (i
.index_reg
)
4385 && register_number (i
.op
[0].regs
)
4386 != register_number (i
.op
[2].regs
))
4388 if (operand_check
== check_error
)
4390 i
.error
= invalid_vector_register_set
;
4393 as_warn (_("mask, index, and destination registers should be distinct"));
4395 else if (i
.reg_operands
== 1 && i
.mask
)
4397 if ((i
.types
[1].bitfield
.regymm
4398 || i
.types
[1].bitfield
.regzmm
)
4399 && (register_number (i
.op
[1].regs
)
4400 == register_number (i
.index_reg
)))
4402 if (operand_check
== check_error
)
4404 i
.error
= invalid_vector_register_set
;
4407 if (operand_check
!= check_none
)
4408 as_warn (_("index and destination registers should be distinct"));
4413 /* Check if broadcast is supported by the instruction and is applied
4414 to the memory operand. */
4417 int broadcasted_opnd_size
;
4419 /* Check if specified broadcast is supported in this instruction,
4420 and it's applied to memory operand of DWORD or QWORD type,
4421 depending on VecESize. */
4422 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4423 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4424 || (t
->opcode_modifier
.vecesize
== 0
4425 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4426 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4427 || (t
->opcode_modifier
.vecesize
== 1
4428 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4429 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4432 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4433 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4434 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4435 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4436 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4437 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4438 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4439 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4440 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4444 if ((broadcasted_opnd_size
== 256
4445 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4446 || (broadcasted_opnd_size
== 512
4447 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4450 i
.error
= unsupported_broadcast
;
4454 /* If broadcast is supported in this instruction, we need to check if
4455 operand of one-element size isn't specified without broadcast. */
4456 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4458 /* Find memory operand. */
4459 for (op
= 0; op
< i
.operands
; op
++)
4460 if (operand_type_check (i
.types
[op
], anymem
))
4462 gas_assert (op
< i
.operands
);
4463 /* Check size of the memory operand. */
4464 if ((t
->opcode_modifier
.vecesize
== 0
4465 && i
.types
[op
].bitfield
.dword
)
4466 || (t
->opcode_modifier
.vecesize
== 1
4467 && i
.types
[op
].bitfield
.qword
))
4469 i
.error
= broadcast_needed
;
4474 /* Check if requested masking is supported. */
4476 && (!t
->opcode_modifier
.masking
4478 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4480 i
.error
= unsupported_masking
;
4484 /* Check if masking is applied to dest operand. */
4485 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4487 i
.error
= mask_not_on_destination
;
4494 if ((i
.rounding
->type
!= saeonly
4495 && !t
->opcode_modifier
.staticrounding
)
4496 || (i
.rounding
->type
== saeonly
4497 && (t
->opcode_modifier
.staticrounding
4498 || !t
->opcode_modifier
.sae
)))
4500 i
.error
= unsupported_rc_sae
;
4503 /* If the instruction has several immediate operands and one of
4504 them is rounding, the rounding operand should be the last
4505 immediate operand. */
4506 if (i
.imm_operands
> 1
4507 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4509 i
.error
= rc_sae_operand_not_last_imm
;
4514 /* Check vector Disp8 operand. */
4515 if (t
->opcode_modifier
.disp8memshift
)
4518 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4520 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4522 for (op
= 0; op
< i
.operands
; op
++)
4523 if (operand_type_check (i
.types
[op
], disp
)
4524 && i
.op
[op
].disps
->X_op
== O_constant
)
4526 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4527 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4528 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4531 i
.types
[op
].bitfield
.vec_disp8
= 1;
4534 /* Vector insn can only have Vec_Disp8/Disp32 in
4535 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4537 i
.types
[op
].bitfield
.disp8
= 0;
4538 if (flag_code
!= CODE_16BIT
)
4539 i
.types
[op
].bitfield
.disp16
= 0;
4542 else if (flag_code
!= CODE_16BIT
)
4544 /* One form of this instruction supports vector Disp8.
4545 Try vector Disp8 if we need to use Disp32. */
4546 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4548 i
.error
= try_vector_disp8
;
4560 /* Check if operands are valid for the instruction. Update VEX
4564 VEX_check_operands (const insn_template
*t
)
4566 /* VREX is only valid with EVEX prefix. */
4567 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4569 i
.error
= invalid_register_operand
;
4573 if (!t
->opcode_modifier
.vex
)
4576 /* Only check VEX_Imm4, which must be the first operand. */
4577 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4579 if (i
.op
[0].imms
->X_op
!= O_constant
4580 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4586 /* Turn off Imm8 so that update_imm won't complain. */
4587 i
.types
[0] = vec_imm4
;
4593 static const insn_template
*
4594 match_template (void)
4596 /* Points to template once we've found it. */
4597 const insn_template
*t
;
4598 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4599 i386_operand_type overlap4
;
4600 unsigned int found_reverse_match
;
4601 i386_opcode_modifier suffix_check
;
4602 i386_operand_type operand_types
[MAX_OPERANDS
];
4603 int addr_prefix_disp
;
4605 unsigned int found_cpu_match
;
4606 unsigned int check_register
;
4607 enum i386_error specific_error
= 0;
4609 #if MAX_OPERANDS != 5
4610 # error "MAX_OPERANDS must be 5."
4613 found_reverse_match
= 0;
4614 addr_prefix_disp
= -1;
4616 memset (&suffix_check
, 0, sizeof (suffix_check
));
4617 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4618 suffix_check
.no_bsuf
= 1;
4619 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4620 suffix_check
.no_wsuf
= 1;
4621 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4622 suffix_check
.no_ssuf
= 1;
4623 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4624 suffix_check
.no_lsuf
= 1;
4625 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4626 suffix_check
.no_qsuf
= 1;
4627 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4628 suffix_check
.no_ldsuf
= 1;
4630 /* Must have right number of operands. */
4631 i
.error
= number_of_operands_mismatch
;
4633 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4635 addr_prefix_disp
= -1;
4637 if (i
.operands
!= t
->operands
)
4640 /* Check processor support. */
4641 i
.error
= unsupported
;
4642 found_cpu_match
= (cpu_flags_match (t
)
4643 == CPU_FLAGS_PERFECT_MATCH
);
4644 if (!found_cpu_match
)
4647 /* Check old gcc support. */
4648 i
.error
= old_gcc_only
;
4649 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4652 /* Check AT&T mnemonic. */
4653 i
.error
= unsupported_with_intel_mnemonic
;
4654 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4657 /* Check AT&T/Intel syntax. */
4658 i
.error
= unsupported_syntax
;
4659 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4660 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4663 /* Check the suffix, except for some instructions in intel mode. */
4664 i
.error
= invalid_instruction_suffix
;
4665 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4666 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4667 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4668 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4669 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4670 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4671 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4674 if (!operand_size_match (t
))
4677 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4678 operand_types
[j
] = t
->operand_types
[j
];
4680 /* In general, don't allow 64-bit operands in 32-bit mode. */
4681 if (i
.suffix
== QWORD_MNEM_SUFFIX
4682 && flag_code
!= CODE_64BIT
4684 ? (!t
->opcode_modifier
.ignoresize
4685 && !intel_float_operand (t
->name
))
4686 : intel_float_operand (t
->name
) != 2)
4687 && ((!operand_types
[0].bitfield
.regmmx
4688 && !operand_types
[0].bitfield
.regxmm
4689 && !operand_types
[0].bitfield
.regymm
4690 && !operand_types
[0].bitfield
.regzmm
)
4691 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4692 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4693 && operand_types
[t
->operands
> 1].bitfield
.regymm
4694 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4695 && (t
->base_opcode
!= 0x0fc7
4696 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4699 /* In general, don't allow 32-bit operands on pre-386. */
4700 else if (i
.suffix
== LONG_MNEM_SUFFIX
4701 && !cpu_arch_flags
.bitfield
.cpui386
4703 ? (!t
->opcode_modifier
.ignoresize
4704 && !intel_float_operand (t
->name
))
4705 : intel_float_operand (t
->name
) != 2)
4706 && ((!operand_types
[0].bitfield
.regmmx
4707 && !operand_types
[0].bitfield
.regxmm
)
4708 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4709 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4712 /* Do not verify operands when there are none. */
4716 /* We've found a match; break out of loop. */
4720 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4721 into Disp32/Disp16/Disp32 operand. */
4722 if (i
.prefix
[ADDR_PREFIX
] != 0)
4724 /* There should be only one Disp operand. */
4728 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4730 if (operand_types
[j
].bitfield
.disp16
)
4732 addr_prefix_disp
= j
;
4733 operand_types
[j
].bitfield
.disp32
= 1;
4734 operand_types
[j
].bitfield
.disp16
= 0;
4740 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4742 if (operand_types
[j
].bitfield
.disp32
)
4744 addr_prefix_disp
= j
;
4745 operand_types
[j
].bitfield
.disp32
= 0;
4746 operand_types
[j
].bitfield
.disp16
= 1;
4752 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4754 if (operand_types
[j
].bitfield
.disp64
)
4756 addr_prefix_disp
= j
;
4757 operand_types
[j
].bitfield
.disp64
= 0;
4758 operand_types
[j
].bitfield
.disp32
= 1;
4766 /* We check register size if needed. */
4767 check_register
= t
->opcode_modifier
.checkregsize
;
4768 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4769 switch (t
->operands
)
4772 if (!operand_type_match (overlap0
, i
.types
[0]))
4776 /* xchg %eax, %eax is a special case. It is an aliase for nop
4777 only in 32bit mode and we can use opcode 0x90. In 64bit
4778 mode, we can't use 0x90 for xchg %eax, %eax since it should
4779 zero-extend %eax to %rax. */
4780 if (flag_code
== CODE_64BIT
4781 && t
->base_opcode
== 0x90
4782 && operand_type_equal (&i
.types
[0], &acc32
)
4783 && operand_type_equal (&i
.types
[1], &acc32
))
4787 /* If we swap operand in encoding, we either match
4788 the next one or reverse direction of operands. */
4789 if (t
->opcode_modifier
.s
)
4791 else if (t
->opcode_modifier
.d
)
4796 /* If we swap operand in encoding, we match the next one. */
4797 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4801 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4802 if (!operand_type_match (overlap0
, i
.types
[0])
4803 || !operand_type_match (overlap1
, i
.types
[1])
4805 && !operand_type_register_match (overlap0
, i
.types
[0],
4807 overlap1
, i
.types
[1],
4810 /* Check if other direction is valid ... */
4811 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4815 /* Try reversing direction of operands. */
4816 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4817 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4818 if (!operand_type_match (overlap0
, i
.types
[0])
4819 || !operand_type_match (overlap1
, i
.types
[1])
4821 && !operand_type_register_match (overlap0
,
4828 /* Does not match either direction. */
4831 /* found_reverse_match holds which of D or FloatDR
4833 if (t
->opcode_modifier
.d
)
4834 found_reverse_match
= Opcode_D
;
4835 else if (t
->opcode_modifier
.floatd
)
4836 found_reverse_match
= Opcode_FloatD
;
4838 found_reverse_match
= 0;
4839 if (t
->opcode_modifier
.floatr
)
4840 found_reverse_match
|= Opcode_FloatR
;
4844 /* Found a forward 2 operand match here. */
4845 switch (t
->operands
)
4848 overlap4
= operand_type_and (i
.types
[4],
4851 overlap3
= operand_type_and (i
.types
[3],
4854 overlap2
= operand_type_and (i
.types
[2],
4859 switch (t
->operands
)
4862 if (!operand_type_match (overlap4
, i
.types
[4])
4863 || !operand_type_register_match (overlap3
,
4871 if (!operand_type_match (overlap3
, i
.types
[3])
4873 && !operand_type_register_match (overlap2
,
4881 /* Here we make use of the fact that there are no
4882 reverse match 3 operand instructions, and all 3
4883 operand instructions only need to be checked for
4884 register consistency between operands 2 and 3. */
4885 if (!operand_type_match (overlap2
, i
.types
[2])
4887 && !operand_type_register_match (overlap1
,
4897 /* Found either forward/reverse 2, 3 or 4 operand match here:
4898 slip through to break. */
4900 if (!found_cpu_match
)
4902 found_reverse_match
= 0;
4906 /* Check if vector and VEX operands are valid. */
4907 if (check_VecOperands (t
) || VEX_check_operands (t
))
4909 specific_error
= i
.error
;
4913 /* We've found a match; break out of loop. */
4917 if (t
== current_templates
->end
)
4919 /* We found no match. */
4920 const char *err_msg
;
4921 switch (specific_error
? specific_error
: i
.error
)
4925 case operand_size_mismatch
:
4926 err_msg
= _("operand size mismatch");
4928 case operand_type_mismatch
:
4929 err_msg
= _("operand type mismatch");
4931 case register_type_mismatch
:
4932 err_msg
= _("register type mismatch");
4934 case number_of_operands_mismatch
:
4935 err_msg
= _("number of operands mismatch");
4937 case invalid_instruction_suffix
:
4938 err_msg
= _("invalid instruction suffix");
4941 err_msg
= _("constant doesn't fit in 4 bits");
4944 err_msg
= _("only supported with old gcc");
4946 case unsupported_with_intel_mnemonic
:
4947 err_msg
= _("unsupported with Intel mnemonic");
4949 case unsupported_syntax
:
4950 err_msg
= _("unsupported syntax");
4953 as_bad (_("unsupported instruction `%s'"),
4954 current_templates
->start
->name
);
4956 case invalid_vsib_address
:
4957 err_msg
= _("invalid VSIB address");
4959 case invalid_vector_register_set
:
4960 err_msg
= _("mask, index, and destination registers must be distinct");
4962 case unsupported_vector_index_register
:
4963 err_msg
= _("unsupported vector index register");
4965 case unsupported_broadcast
:
4966 err_msg
= _("unsupported broadcast");
4968 case broadcast_not_on_src_operand
:
4969 err_msg
= _("broadcast not on source memory operand");
4971 case broadcast_needed
:
4972 err_msg
= _("broadcast is needed for operand of such type");
4974 case unsupported_masking
:
4975 err_msg
= _("unsupported masking");
4977 case mask_not_on_destination
:
4978 err_msg
= _("mask not on destination operand");
4980 case no_default_mask
:
4981 err_msg
= _("default mask isn't allowed");
4983 case unsupported_rc_sae
:
4984 err_msg
= _("unsupported static rounding/sae");
4986 case rc_sae_operand_not_last_imm
:
4988 err_msg
= _("RC/SAE operand must precede immediate operands");
4990 err_msg
= _("RC/SAE operand must follow immediate operands");
4992 case invalid_register_operand
:
4993 err_msg
= _("invalid register operand");
4996 as_bad (_("%s for `%s'"), err_msg
,
4997 current_templates
->start
->name
);
5001 if (!quiet_warnings
)
5004 && (i
.types
[0].bitfield
.jumpabsolute
5005 != operand_types
[0].bitfield
.jumpabsolute
))
5007 as_warn (_("indirect %s without `*'"), t
->name
);
5010 if (t
->opcode_modifier
.isprefix
5011 && t
->opcode_modifier
.ignoresize
)
5013 /* Warn them that a data or address size prefix doesn't
5014 affect assembly of the next line of code. */
5015 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5019 /* Copy the template we found. */
5022 if (addr_prefix_disp
!= -1)
5023 i
.tm
.operand_types
[addr_prefix_disp
]
5024 = operand_types
[addr_prefix_disp
];
5026 if (found_reverse_match
)
5028 /* If we found a reverse match we must alter the opcode
5029 direction bit. found_reverse_match holds bits to change
5030 (different for int & float insns). */
5032 i
.tm
.base_opcode
^= found_reverse_match
;
5034 i
.tm
.operand_types
[0] = operand_types
[1];
5035 i
.tm
.operand_types
[1] = operand_types
[0];
5044 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5045 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5047 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5049 as_bad (_("`%s' operand %d must use `%ses' segment"),
5055 /* There's only ever one segment override allowed per instruction.
5056 This instruction possibly has a legal segment override on the
5057 second operand, so copy the segment to where non-string
5058 instructions store it, allowing common code. */
5059 i
.seg
[0] = i
.seg
[1];
5061 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5063 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5065 as_bad (_("`%s' operand %d must use `%ses' segment"),
5076 process_suffix (void)
5078 /* If matched instruction specifies an explicit instruction mnemonic
5080 if (i
.tm
.opcode_modifier
.size16
)
5081 i
.suffix
= WORD_MNEM_SUFFIX
;
5082 else if (i
.tm
.opcode_modifier
.size32
)
5083 i
.suffix
= LONG_MNEM_SUFFIX
;
5084 else if (i
.tm
.opcode_modifier
.size64
)
5085 i
.suffix
= QWORD_MNEM_SUFFIX
;
5086 else if (i
.reg_operands
)
5088 /* If there's no instruction mnemonic suffix we try to invent one
5089 based on register operands. */
5092 /* We take i.suffix from the last register operand specified,
5093 Destination register type is more significant than source
5094 register type. crc32 in SSE4.2 prefers source register
5096 if (i
.tm
.base_opcode
== 0xf20f38f1)
5098 if (i
.types
[0].bitfield
.reg16
)
5099 i
.suffix
= WORD_MNEM_SUFFIX
;
5100 else if (i
.types
[0].bitfield
.reg32
)
5101 i
.suffix
= LONG_MNEM_SUFFIX
;
5102 else if (i
.types
[0].bitfield
.reg64
)
5103 i
.suffix
= QWORD_MNEM_SUFFIX
;
5105 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5107 if (i
.types
[0].bitfield
.reg8
)
5108 i
.suffix
= BYTE_MNEM_SUFFIX
;
5115 if (i
.tm
.base_opcode
== 0xf20f38f1
5116 || i
.tm
.base_opcode
== 0xf20f38f0)
5118 /* We have to know the operand size for crc32. */
5119 as_bad (_("ambiguous memory operand size for `%s`"),
5124 for (op
= i
.operands
; --op
>= 0;)
5125 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5127 if (i
.types
[op
].bitfield
.reg8
)
5129 i
.suffix
= BYTE_MNEM_SUFFIX
;
5132 else if (i
.types
[op
].bitfield
.reg16
)
5134 i
.suffix
= WORD_MNEM_SUFFIX
;
5137 else if (i
.types
[op
].bitfield
.reg32
)
5139 i
.suffix
= LONG_MNEM_SUFFIX
;
5142 else if (i
.types
[op
].bitfield
.reg64
)
5144 i
.suffix
= QWORD_MNEM_SUFFIX
;
5150 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5153 && i
.tm
.opcode_modifier
.ignoresize
5154 && i
.tm
.opcode_modifier
.no_bsuf
)
5156 else if (!check_byte_reg ())
5159 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5162 && i
.tm
.opcode_modifier
.ignoresize
5163 && i
.tm
.opcode_modifier
.no_lsuf
)
5165 else if (!check_long_reg ())
5168 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5171 && i
.tm
.opcode_modifier
.ignoresize
5172 && i
.tm
.opcode_modifier
.no_qsuf
)
5174 else if (!check_qword_reg ())
5177 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5180 && i
.tm
.opcode_modifier
.ignoresize
5181 && i
.tm
.opcode_modifier
.no_wsuf
)
5183 else if (!check_word_reg ())
5186 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5187 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5188 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5190 /* Skip if the instruction has x/y/z suffix. match_template
5191 should check if it is a valid suffix. */
5193 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5194 /* Do nothing if the instruction is going to ignore the prefix. */
5199 else if (i
.tm
.opcode_modifier
.defaultsize
5201 /* exclude fldenv/frstor/fsave/fstenv */
5202 && i
.tm
.opcode_modifier
.no_ssuf
)
5204 i
.suffix
= stackop_size
;
5206 else if (intel_syntax
5208 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5209 || i
.tm
.opcode_modifier
.jumpbyte
5210 || i
.tm
.opcode_modifier
.jumpintersegment
5211 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5212 && i
.tm
.extension_opcode
<= 3)))
5217 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5219 i
.suffix
= QWORD_MNEM_SUFFIX
;
5223 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5224 i
.suffix
= LONG_MNEM_SUFFIX
;
5227 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5228 i
.suffix
= WORD_MNEM_SUFFIX
;
5237 if (i
.tm
.opcode_modifier
.w
)
5239 as_bad (_("no instruction mnemonic suffix given and "
5240 "no register operands; can't size instruction"));
5246 unsigned int suffixes
;
5248 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5249 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5251 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5253 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5255 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5257 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5260 /* There are more than suffix matches. */
5261 if (i
.tm
.opcode_modifier
.w
5262 || ((suffixes
& (suffixes
- 1))
5263 && !i
.tm
.opcode_modifier
.defaultsize
5264 && !i
.tm
.opcode_modifier
.ignoresize
))
5266 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5272 /* Change the opcode based on the operand size given by i.suffix;
5273 We don't need to change things for byte insns. */
5276 && i
.suffix
!= BYTE_MNEM_SUFFIX
5277 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5278 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5279 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5281 /* It's not a byte, select word/dword operation. */
5282 if (i
.tm
.opcode_modifier
.w
)
5284 if (i
.tm
.opcode_modifier
.shortform
)
5285 i
.tm
.base_opcode
|= 8;
5287 i
.tm
.base_opcode
|= 1;
5290 /* Now select between word & dword operations via the operand
5291 size prefix, except for instructions that will ignore this
5293 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5295 /* The address size override prefix changes the size of the
5297 if ((flag_code
== CODE_32BIT
5298 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5299 || (flag_code
!= CODE_32BIT
5300 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5301 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5304 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5305 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5306 && !i
.tm
.opcode_modifier
.ignoresize
5307 && !i
.tm
.opcode_modifier
.floatmf
5308 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5309 || (flag_code
== CODE_64BIT
5310 && i
.tm
.opcode_modifier
.jumpbyte
)))
5312 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5314 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5315 prefix
= ADDR_PREFIX_OPCODE
;
5317 if (!add_prefix (prefix
))
5321 /* Set mode64 for an operand. */
5322 if (i
.suffix
== QWORD_MNEM_SUFFIX
5323 && flag_code
== CODE_64BIT
5324 && !i
.tm
.opcode_modifier
.norex64
)
5326 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5327 need rex64. cmpxchg8b is also a special case. */
5328 if (! (i
.operands
== 2
5329 && i
.tm
.base_opcode
== 0x90
5330 && i
.tm
.extension_opcode
== None
5331 && operand_type_equal (&i
.types
[0], &acc64
)
5332 && operand_type_equal (&i
.types
[1], &acc64
))
5333 && ! (i
.operands
== 1
5334 && i
.tm
.base_opcode
== 0xfc7
5335 && i
.tm
.extension_opcode
== 1
5336 && !operand_type_check (i
.types
[0], reg
)
5337 && operand_type_check (i
.types
[0], anymem
)))
5341 /* Size floating point instruction. */
5342 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5343 if (i
.tm
.opcode_modifier
.floatmf
)
5344 i
.tm
.base_opcode
^= 4;
5351 check_byte_reg (void)
5355 for (op
= i
.operands
; --op
>= 0;)
5357 /* If this is an eight bit register, it's OK. If it's the 16 or
5358 32 bit version of an eight bit register, we will just use the
5359 low portion, and that's OK too. */
5360 if (i
.types
[op
].bitfield
.reg8
)
5363 /* I/O port address operands are OK too. */
5364 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5367 /* crc32 doesn't generate this warning. */
5368 if (i
.tm
.base_opcode
== 0xf20f38f0)
5371 if ((i
.types
[op
].bitfield
.reg16
5372 || i
.types
[op
].bitfield
.reg32
5373 || i
.types
[op
].bitfield
.reg64
)
5374 && i
.op
[op
].regs
->reg_num
< 4
5375 /* Prohibit these changes in 64bit mode, since the lowering
5376 would be more complicated. */
5377 && flag_code
!= CODE_64BIT
)
5379 #if REGISTER_WARNINGS
5380 if (!quiet_warnings
)
5381 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5383 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5384 ? REGNAM_AL
- REGNAM_AX
5385 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5387 i
.op
[op
].regs
->reg_name
,
5392 /* Any other register is bad. */
5393 if (i
.types
[op
].bitfield
.reg16
5394 || i
.types
[op
].bitfield
.reg32
5395 || i
.types
[op
].bitfield
.reg64
5396 || i
.types
[op
].bitfield
.regmmx
5397 || i
.types
[op
].bitfield
.regxmm
5398 || i
.types
[op
].bitfield
.regymm
5399 || i
.types
[op
].bitfield
.regzmm
5400 || i
.types
[op
].bitfield
.sreg2
5401 || i
.types
[op
].bitfield
.sreg3
5402 || i
.types
[op
].bitfield
.control
5403 || i
.types
[op
].bitfield
.debug
5404 || i
.types
[op
].bitfield
.test
5405 || i
.types
[op
].bitfield
.floatreg
5406 || i
.types
[op
].bitfield
.floatacc
)
5408 as_bad (_("`%s%s' not allowed with `%s%c'"),
5410 i
.op
[op
].regs
->reg_name
,
5420 check_long_reg (void)
5424 for (op
= i
.operands
; --op
>= 0;)
5425 /* Reject eight bit registers, except where the template requires
5426 them. (eg. movzb) */
5427 if (i
.types
[op
].bitfield
.reg8
5428 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5429 || i
.tm
.operand_types
[op
].bitfield
.reg32
5430 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5432 as_bad (_("`%s%s' not allowed with `%s%c'"),
5434 i
.op
[op
].regs
->reg_name
,
5439 /* Warn if the e prefix on a general reg is missing. */
5440 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5441 && i
.types
[op
].bitfield
.reg16
5442 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5443 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5445 /* Prohibit these changes in the 64bit mode, since the
5446 lowering is more complicated. */
5447 if (flag_code
== CODE_64BIT
)
5449 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5450 register_prefix
, i
.op
[op
].regs
->reg_name
,
5454 #if REGISTER_WARNINGS
5455 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5457 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5458 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5461 /* Warn if the r prefix on a general reg is present. */
5462 else if (i
.types
[op
].bitfield
.reg64
5463 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5464 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5467 && i
.tm
.opcode_modifier
.toqword
5468 && !i
.types
[0].bitfield
.regxmm
)
5470 /* Convert to QWORD. We want REX byte. */
5471 i
.suffix
= QWORD_MNEM_SUFFIX
;
5475 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5476 register_prefix
, i
.op
[op
].regs
->reg_name
,
5485 check_qword_reg (void)
5489 for (op
= i
.operands
; --op
>= 0; )
5490 /* Reject eight bit registers, except where the template requires
5491 them. (eg. movzb) */
5492 if (i
.types
[op
].bitfield
.reg8
5493 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5494 || i
.tm
.operand_types
[op
].bitfield
.reg32
5495 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5497 as_bad (_("`%s%s' not allowed with `%s%c'"),
5499 i
.op
[op
].regs
->reg_name
,
5504 /* Warn if the r prefix on a general reg is missing. */
5505 else if ((i
.types
[op
].bitfield
.reg16
5506 || i
.types
[op
].bitfield
.reg32
)
5507 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5508 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5510 /* Prohibit these changes in the 64bit mode, since the
5511 lowering is more complicated. */
5513 && i
.tm
.opcode_modifier
.todword
5514 && !i
.types
[0].bitfield
.regxmm
)
5516 /* Convert to DWORD. We don't want REX byte. */
5517 i
.suffix
= LONG_MNEM_SUFFIX
;
5521 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5522 register_prefix
, i
.op
[op
].regs
->reg_name
,
5531 check_word_reg (void)
5534 for (op
= i
.operands
; --op
>= 0;)
5535 /* Reject eight bit registers, except where the template requires
5536 them. (eg. movzb) */
5537 if (i
.types
[op
].bitfield
.reg8
5538 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5539 || i
.tm
.operand_types
[op
].bitfield
.reg32
5540 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5542 as_bad (_("`%s%s' not allowed with `%s%c'"),
5544 i
.op
[op
].regs
->reg_name
,
5549 /* Warn if the e or r prefix on a general reg is present. */
5550 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5551 && (i
.types
[op
].bitfield
.reg32
5552 || i
.types
[op
].bitfield
.reg64
)
5553 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5554 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5556 /* Prohibit these changes in the 64bit mode, since the
5557 lowering is more complicated. */
5558 if (flag_code
== CODE_64BIT
)
5560 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5561 register_prefix
, i
.op
[op
].regs
->reg_name
,
5565 #if REGISTER_WARNINGS
5566 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5568 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5569 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5576 update_imm (unsigned int j
)
5578 i386_operand_type overlap
= i
.types
[j
];
5579 if ((overlap
.bitfield
.imm8
5580 || overlap
.bitfield
.imm8s
5581 || overlap
.bitfield
.imm16
5582 || overlap
.bitfield
.imm32
5583 || overlap
.bitfield
.imm32s
5584 || overlap
.bitfield
.imm64
)
5585 && !operand_type_equal (&overlap
, &imm8
)
5586 && !operand_type_equal (&overlap
, &imm8s
)
5587 && !operand_type_equal (&overlap
, &imm16
)
5588 && !operand_type_equal (&overlap
, &imm32
)
5589 && !operand_type_equal (&overlap
, &imm32s
)
5590 && !operand_type_equal (&overlap
, &imm64
))
5594 i386_operand_type temp
;
5596 operand_type_set (&temp
, 0);
5597 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5599 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5600 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5602 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5603 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5604 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5606 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5607 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5610 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5613 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5614 || operand_type_equal (&overlap
, &imm16_32
)
5615 || operand_type_equal (&overlap
, &imm16_32s
))
5617 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5622 if (!operand_type_equal (&overlap
, &imm8
)
5623 && !operand_type_equal (&overlap
, &imm8s
)
5624 && !operand_type_equal (&overlap
, &imm16
)
5625 && !operand_type_equal (&overlap
, &imm32
)
5626 && !operand_type_equal (&overlap
, &imm32s
)
5627 && !operand_type_equal (&overlap
, &imm64
))
5629 as_bad (_("no instruction mnemonic suffix given; "
5630 "can't determine immediate size"));
5634 i
.types
[j
] = overlap
;
5644 /* Update the first 2 immediate operands. */
5645 n
= i
.operands
> 2 ? 2 : i
.operands
;
5648 for (j
= 0; j
< n
; j
++)
5649 if (update_imm (j
) == 0)
5652 /* The 3rd operand can't be immediate operand. */
5653 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5660 bad_implicit_operand (int xmm
)
5662 const char *ireg
= xmm
? "xmm0" : "ymm0";
5665 as_bad (_("the last operand of `%s' must be `%s%s'"),
5666 i
.tm
.name
, register_prefix
, ireg
);
5668 as_bad (_("the first operand of `%s' must be `%s%s'"),
5669 i
.tm
.name
, register_prefix
, ireg
);
5674 process_operands (void)
5676 /* Default segment register this instruction will use for memory
5677 accesses. 0 means unknown. This is only for optimizing out
5678 unnecessary segment overrides. */
5679 const seg_entry
*default_seg
= 0;
5681 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5683 unsigned int dupl
= i
.operands
;
5684 unsigned int dest
= dupl
- 1;
5687 /* The destination must be an xmm register. */
5688 gas_assert (i
.reg_operands
5689 && MAX_OPERANDS
> dupl
5690 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5692 if (i
.tm
.opcode_modifier
.firstxmm0
)
5694 /* The first operand is implicit and must be xmm0. */
5695 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5696 if (register_number (i
.op
[0].regs
) != 0)
5697 return bad_implicit_operand (1);
5699 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5701 /* Keep xmm0 for instructions with VEX prefix and 3
5707 /* We remove the first xmm0 and keep the number of
5708 operands unchanged, which in fact duplicates the
5710 for (j
= 1; j
< i
.operands
; j
++)
5712 i
.op
[j
- 1] = i
.op
[j
];
5713 i
.types
[j
- 1] = i
.types
[j
];
5714 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5718 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5720 gas_assert ((MAX_OPERANDS
- 1) > dupl
5721 && (i
.tm
.opcode_modifier
.vexsources
5724 /* Add the implicit xmm0 for instructions with VEX prefix
5726 for (j
= i
.operands
; j
> 0; j
--)
5728 i
.op
[j
] = i
.op
[j
- 1];
5729 i
.types
[j
] = i
.types
[j
- 1];
5730 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5733 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5734 i
.types
[0] = regxmm
;
5735 i
.tm
.operand_types
[0] = regxmm
;
5738 i
.reg_operands
+= 2;
5743 i
.op
[dupl
] = i
.op
[dest
];
5744 i
.types
[dupl
] = i
.types
[dest
];
5745 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5754 i
.op
[dupl
] = i
.op
[dest
];
5755 i
.types
[dupl
] = i
.types
[dest
];
5756 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5759 if (i
.tm
.opcode_modifier
.immext
)
5762 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5766 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5767 gas_assert (i
.reg_operands
5768 && (operand_type_equal (&i
.types
[0], ®xmm
)
5769 || operand_type_equal (&i
.types
[0], ®ymm
)
5770 || operand_type_equal (&i
.types
[0], ®zmm
)));
5771 if (register_number (i
.op
[0].regs
) != 0)
5772 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5774 for (j
= 1; j
< i
.operands
; j
++)
5776 i
.op
[j
- 1] = i
.op
[j
];
5777 i
.types
[j
- 1] = i
.types
[j
];
5779 /* We need to adjust fields in i.tm since they are used by
5780 build_modrm_byte. */
5781 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5788 else if (i
.tm
.opcode_modifier
.regkludge
)
5790 /* The imul $imm, %reg instruction is converted into
5791 imul $imm, %reg, %reg, and the clr %reg instruction
5792 is converted into xor %reg, %reg. */
5794 unsigned int first_reg_op
;
5796 if (operand_type_check (i
.types
[0], reg
))
5800 /* Pretend we saw the extra register operand. */
5801 gas_assert (i
.reg_operands
== 1
5802 && i
.op
[first_reg_op
+ 1].regs
== 0);
5803 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5804 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5809 if (i
.tm
.opcode_modifier
.shortform
)
5811 if (i
.types
[0].bitfield
.sreg2
5812 || i
.types
[0].bitfield
.sreg3
)
5814 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5815 && i
.op
[0].regs
->reg_num
== 1)
5817 as_bad (_("you can't `pop %scs'"), register_prefix
);
5820 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5821 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5826 /* The register or float register operand is in operand
5830 if (i
.types
[0].bitfield
.floatreg
5831 || operand_type_check (i
.types
[0], reg
))
5835 /* Register goes in low 3 bits of opcode. */
5836 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5837 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5839 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5841 /* Warn about some common errors, but press on regardless.
5842 The first case can be generated by gcc (<= 2.8.1). */
5843 if (i
.operands
== 2)
5845 /* Reversed arguments on faddp, fsubp, etc. */
5846 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5847 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5848 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5852 /* Extraneous `l' suffix on fp insn. */
5853 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5854 register_prefix
, i
.op
[0].regs
->reg_name
);
5859 else if (i
.tm
.opcode_modifier
.modrm
)
5861 /* The opcode is completed (modulo i.tm.extension_opcode which
5862 must be put into the modrm byte). Now, we make the modrm and
5863 index base bytes based on all the info we've collected. */
5865 default_seg
= build_modrm_byte ();
5867 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5871 else if (i
.tm
.opcode_modifier
.isstring
)
5873 /* For the string instructions that allow a segment override
5874 on one of their operands, the default segment is ds. */
5878 if (i
.tm
.base_opcode
== 0x8d /* lea */
5881 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5883 /* If a segment was explicitly specified, and the specified segment
5884 is not the default, use an opcode prefix to select it. If we
5885 never figured out what the default segment is, then default_seg
5886 will be zero at this point, and the specified segment prefix will
5888 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5890 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5896 static const seg_entry
*
5897 build_modrm_byte (void)
5899 const seg_entry
*default_seg
= 0;
5900 unsigned int source
, dest
;
5903 /* The first operand of instructions with VEX prefix and 3 sources
5904 must be VEX_Imm4. */
5905 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5908 unsigned int nds
, reg_slot
;
5911 if (i
.tm
.opcode_modifier
.veximmext
5912 && i
.tm
.opcode_modifier
.immext
)
5914 dest
= i
.operands
- 2;
5915 gas_assert (dest
== 3);
5918 dest
= i
.operands
- 1;
5921 /* There are 2 kinds of instructions:
5922 1. 5 operands: 4 register operands or 3 register operands
5923 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5924 VexW0 or VexW1. The destination must be either XMM, YMM or
5926 2. 4 operands: 4 register operands or 3 register operands
5927 plus 1 memory operand, VexXDS, and VexImmExt */
5928 gas_assert ((i
.reg_operands
== 4
5929 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5930 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5931 && (i
.tm
.opcode_modifier
.veximmext
5932 || (i
.imm_operands
== 1
5933 && i
.types
[0].bitfield
.vec_imm4
5934 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5935 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5936 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5937 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5938 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5940 if (i
.imm_operands
== 0)
5942 /* When there is no immediate operand, generate an 8bit
5943 immediate operand to encode the first operand. */
5944 exp
= &im_expressions
[i
.imm_operands
++];
5945 i
.op
[i
.operands
].imms
= exp
;
5946 i
.types
[i
.operands
] = imm8
;
5948 /* If VexW1 is set, the first operand is the source and
5949 the second operand is encoded in the immediate operand. */
5950 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5961 /* FMA swaps REG and NDS. */
5962 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5970 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5972 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5974 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5976 exp
->X_op
= O_constant
;
5977 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5978 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5982 unsigned int imm_slot
;
5984 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5986 /* If VexW0 is set, the third operand is the source and
5987 the second operand is encoded in the immediate
5994 /* VexW1 is set, the second operand is the source and
5995 the third operand is encoded in the immediate
6001 if (i
.tm
.opcode_modifier
.immext
)
6003 /* When ImmExt is set, the immdiate byte is the last
6005 imm_slot
= i
.operands
- 1;
6013 /* Turn on Imm8 so that output_imm will generate it. */
6014 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6017 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6019 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6021 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6023 i
.op
[imm_slot
].imms
->X_add_number
6024 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6025 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6028 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6029 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6031 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6033 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6038 /* i.reg_operands MUST be the number of real register operands;
6039 implicit registers do not count. If there are 3 register
6040 operands, it must be a instruction with VexNDS. For a
6041 instruction with VexNDD, the destination register is encoded
6042 in VEX prefix. If there are 4 register operands, it must be
6043 a instruction with VEX prefix and 3 sources. */
6044 if (i
.mem_operands
== 0
6045 && ((i
.reg_operands
== 2
6046 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6047 || (i
.reg_operands
== 3
6048 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6049 || (i
.reg_operands
== 4 && vex_3_sources
)))
6057 /* When there are 3 operands, one of them may be immediate,
6058 which may be the first or the last operand. Otherwise,
6059 the first operand must be shift count register (cl) or it
6060 is an instruction with VexNDS. */
6061 gas_assert (i
.imm_operands
== 1
6062 || (i
.imm_operands
== 0
6063 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6064 || i
.types
[0].bitfield
.shiftcount
)));
6065 if (operand_type_check (i
.types
[0], imm
)
6066 || i
.types
[0].bitfield
.shiftcount
)
6072 /* When there are 4 operands, the first two must be 8bit
6073 immediate operands. The source operand will be the 3rd
6076 For instructions with VexNDS, if the first operand
6077 an imm8, the source operand is the 2nd one. If the last
6078 operand is imm8, the source operand is the first one. */
6079 gas_assert ((i
.imm_operands
== 2
6080 && i
.types
[0].bitfield
.imm8
6081 && i
.types
[1].bitfield
.imm8
)
6082 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6083 && i
.imm_operands
== 1
6084 && (i
.types
[0].bitfield
.imm8
6085 || i
.types
[i
.operands
- 1].bitfield
.imm8
6087 if (i
.imm_operands
== 2)
6091 if (i
.types
[0].bitfield
.imm8
)
6098 if (i
.tm
.opcode_modifier
.evex
)
6100 /* For EVEX instructions, when there are 5 operands, the
6101 first one must be immediate operand. If the second one
6102 is immediate operand, the source operand is the 3th
6103 one. If the last one is immediate operand, the source
6104 operand is the 2nd one. */
6105 gas_assert (i
.imm_operands
== 2
6106 && i
.tm
.opcode_modifier
.sae
6107 && operand_type_check (i
.types
[0], imm
));
6108 if (operand_type_check (i
.types
[1], imm
))
6110 else if (operand_type_check (i
.types
[4], imm
))
6124 /* RC/SAE operand could be between DEST and SRC. That happens
6125 when one operand is GPR and the other one is XMM/YMM/ZMM
6127 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6130 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6132 /* For instructions with VexNDS, the register-only source
6133 operand must be 32/64bit integer, XMM, YMM or ZMM
6134 register. It is encoded in VEX prefix. We need to
6135 clear RegMem bit before calling operand_type_equal. */
6137 i386_operand_type op
;
6140 /* Check register-only source operand when two source
6141 operands are swapped. */
6142 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6143 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6151 op
= i
.tm
.operand_types
[vvvv
];
6152 op
.bitfield
.regmem
= 0;
6153 if ((dest
+ 1) >= i
.operands
6154 || (!op
.bitfield
.reg32
6155 && op
.bitfield
.reg64
6156 && !operand_type_equal (&op
, ®xmm
)
6157 && !operand_type_equal (&op
, ®ymm
)
6158 && !operand_type_equal (&op
, ®zmm
)
6159 && !operand_type_equal (&op
, ®mask
)))
6161 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6167 /* One of the register operands will be encoded in the i.tm.reg
6168 field, the other in the combined i.tm.mode and i.tm.regmem
6169 fields. If no form of this instruction supports a memory
6170 destination operand, then we assume the source operand may
6171 sometimes be a memory operand and so we need to store the
6172 destination in the i.rm.reg field. */
6173 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6174 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6176 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6177 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6178 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6180 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6182 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6184 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6189 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6190 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6191 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6193 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6195 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6197 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6200 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6202 if (!i
.types
[0].bitfield
.control
6203 && !i
.types
[1].bitfield
.control
)
6205 i
.rex
&= ~(REX_R
| REX_B
);
6206 add_prefix (LOCK_PREFIX_OPCODE
);
6210 { /* If it's not 2 reg operands... */
6215 unsigned int fake_zero_displacement
= 0;
6218 for (op
= 0; op
< i
.operands
; op
++)
6219 if (operand_type_check (i
.types
[op
], anymem
))
6221 gas_assert (op
< i
.operands
);
6223 if (i
.tm
.opcode_modifier
.vecsib
)
6225 if (i
.index_reg
->reg_num
== RegEiz
6226 || i
.index_reg
->reg_num
== RegRiz
)
6229 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6232 i
.sib
.base
= NO_BASE_REGISTER
;
6233 i
.sib
.scale
= i
.log2_scale_factor
;
6234 /* No Vec_Disp8 if there is no base. */
6235 i
.types
[op
].bitfield
.vec_disp8
= 0;
6236 i
.types
[op
].bitfield
.disp8
= 0;
6237 i
.types
[op
].bitfield
.disp16
= 0;
6238 i
.types
[op
].bitfield
.disp64
= 0;
6239 if (flag_code
!= CODE_64BIT
)
6241 /* Must be 32 bit */
6242 i
.types
[op
].bitfield
.disp32
= 1;
6243 i
.types
[op
].bitfield
.disp32s
= 0;
6247 i
.types
[op
].bitfield
.disp32
= 0;
6248 i
.types
[op
].bitfield
.disp32s
= 1;
6251 i
.sib
.index
= i
.index_reg
->reg_num
;
6252 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6254 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6260 if (i
.base_reg
== 0)
6263 if (!i
.disp_operands
)
6265 fake_zero_displacement
= 1;
6266 /* Instructions with VSIB byte need 32bit displacement
6267 if there is no base register. */
6268 if (i
.tm
.opcode_modifier
.vecsib
)
6269 i
.types
[op
].bitfield
.disp32
= 1;
6271 if (i
.index_reg
== 0)
6273 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6274 /* Operand is just <disp> */
6275 if (flag_code
== CODE_64BIT
)
6277 /* 64bit mode overwrites the 32bit absolute
6278 addressing by RIP relative addressing and
6279 absolute addressing is encoded by one of the
6280 redundant SIB forms. */
6281 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6282 i
.sib
.base
= NO_BASE_REGISTER
;
6283 i
.sib
.index
= NO_INDEX_REGISTER
;
6284 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6285 ? disp32s
: disp32
);
6287 else if ((flag_code
== CODE_16BIT
)
6288 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6290 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6291 i
.types
[op
] = disp16
;
6295 i
.rm
.regmem
= NO_BASE_REGISTER
;
6296 i
.types
[op
] = disp32
;
6299 else if (!i
.tm
.opcode_modifier
.vecsib
)
6301 /* !i.base_reg && i.index_reg */
6302 if (i
.index_reg
->reg_num
== RegEiz
6303 || i
.index_reg
->reg_num
== RegRiz
)
6304 i
.sib
.index
= NO_INDEX_REGISTER
;
6306 i
.sib
.index
= i
.index_reg
->reg_num
;
6307 i
.sib
.base
= NO_BASE_REGISTER
;
6308 i
.sib
.scale
= i
.log2_scale_factor
;
6309 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6310 /* No Vec_Disp8 if there is no base. */
6311 i
.types
[op
].bitfield
.vec_disp8
= 0;
6312 i
.types
[op
].bitfield
.disp8
= 0;
6313 i
.types
[op
].bitfield
.disp16
= 0;
6314 i
.types
[op
].bitfield
.disp64
= 0;
6315 if (flag_code
!= CODE_64BIT
)
6317 /* Must be 32 bit */
6318 i
.types
[op
].bitfield
.disp32
= 1;
6319 i
.types
[op
].bitfield
.disp32s
= 0;
6323 i
.types
[op
].bitfield
.disp32
= 0;
6324 i
.types
[op
].bitfield
.disp32s
= 1;
6326 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6330 /* RIP addressing for 64bit mode. */
6331 else if (i
.base_reg
->reg_num
== RegRip
||
6332 i
.base_reg
->reg_num
== RegEip
)
6334 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6335 i
.rm
.regmem
= NO_BASE_REGISTER
;
6336 i
.types
[op
].bitfield
.disp8
= 0;
6337 i
.types
[op
].bitfield
.disp16
= 0;
6338 i
.types
[op
].bitfield
.disp32
= 0;
6339 i
.types
[op
].bitfield
.disp32s
= 1;
6340 i
.types
[op
].bitfield
.disp64
= 0;
6341 i
.types
[op
].bitfield
.vec_disp8
= 0;
6342 i
.flags
[op
] |= Operand_PCrel
;
6343 if (! i
.disp_operands
)
6344 fake_zero_displacement
= 1;
6346 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6348 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6349 switch (i
.base_reg
->reg_num
)
6352 if (i
.index_reg
== 0)
6354 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6355 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6359 if (i
.index_reg
== 0)
6362 if (operand_type_check (i
.types
[op
], disp
) == 0)
6364 /* fake (%bp) into 0(%bp) */
6365 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6366 i
.types
[op
].bitfield
.vec_disp8
= 1;
6368 i
.types
[op
].bitfield
.disp8
= 1;
6369 fake_zero_displacement
= 1;
6372 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6373 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6375 default: /* (%si) -> 4 or (%di) -> 5 */
6376 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6378 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6380 else /* i.base_reg and 32/64 bit mode */
6382 if (flag_code
== CODE_64BIT
6383 && operand_type_check (i
.types
[op
], disp
))
6385 i386_operand_type temp
;
6386 operand_type_set (&temp
, 0);
6387 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6388 temp
.bitfield
.vec_disp8
6389 = i
.types
[op
].bitfield
.vec_disp8
;
6391 if (i
.prefix
[ADDR_PREFIX
] == 0)
6392 i
.types
[op
].bitfield
.disp32s
= 1;
6394 i
.types
[op
].bitfield
.disp32
= 1;
6397 if (!i
.tm
.opcode_modifier
.vecsib
)
6398 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6399 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6401 i
.sib
.base
= i
.base_reg
->reg_num
;
6402 /* x86-64 ignores REX prefix bit here to avoid decoder
6404 if (!(i
.base_reg
->reg_flags
& RegRex
)
6405 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6406 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6408 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6410 fake_zero_displacement
= 1;
6411 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6412 i
.types
[op
].bitfield
.vec_disp8
= 1;
6414 i
.types
[op
].bitfield
.disp8
= 1;
6416 i
.sib
.scale
= i
.log2_scale_factor
;
6417 if (i
.index_reg
== 0)
6419 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6420 /* <disp>(%esp) becomes two byte modrm with no index
6421 register. We've already stored the code for esp
6422 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6423 Any base register besides %esp will not use the
6424 extra modrm byte. */
6425 i
.sib
.index
= NO_INDEX_REGISTER
;
6427 else if (!i
.tm
.opcode_modifier
.vecsib
)
6429 if (i
.index_reg
->reg_num
== RegEiz
6430 || i
.index_reg
->reg_num
== RegRiz
)
6431 i
.sib
.index
= NO_INDEX_REGISTER
;
6433 i
.sib
.index
= i
.index_reg
->reg_num
;
6434 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6435 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6440 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6441 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6445 if (!fake_zero_displacement
6449 fake_zero_displacement
= 1;
6450 if (i
.disp_encoding
== disp_encoding_8bit
)
6451 i
.types
[op
].bitfield
.disp8
= 1;
6453 i
.types
[op
].bitfield
.disp32
= 1;
6455 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6459 if (fake_zero_displacement
)
6461 /* Fakes a zero displacement assuming that i.types[op]
6462 holds the correct displacement size. */
6465 gas_assert (i
.op
[op
].disps
== 0);
6466 exp
= &disp_expressions
[i
.disp_operands
++];
6467 i
.op
[op
].disps
= exp
;
6468 exp
->X_op
= O_constant
;
6469 exp
->X_add_number
= 0;
6470 exp
->X_add_symbol
= (symbolS
*) 0;
6471 exp
->X_op_symbol
= (symbolS
*) 0;
6479 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6481 if (operand_type_check (i
.types
[0], imm
))
6482 i
.vex
.register_specifier
= NULL
;
6485 /* VEX.vvvv encodes one of the sources when the first
6486 operand is not an immediate. */
6487 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6488 i
.vex
.register_specifier
= i
.op
[0].regs
;
6490 i
.vex
.register_specifier
= i
.op
[1].regs
;
6493 /* Destination is a XMM register encoded in the ModRM.reg
6495 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6496 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6499 /* ModRM.rm and VEX.B encodes the other source. */
6500 if (!i
.mem_operands
)
6504 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6505 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6507 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6509 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6513 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6515 i
.vex
.register_specifier
= i
.op
[2].regs
;
6516 if (!i
.mem_operands
)
6519 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6520 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6524 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6525 (if any) based on i.tm.extension_opcode. Again, we must be
6526 careful to make sure that segment/control/debug/test/MMX
6527 registers are coded into the i.rm.reg field. */
6528 else if (i
.reg_operands
)
6531 unsigned int vex_reg
= ~0;
6533 for (op
= 0; op
< i
.operands
; op
++)
6534 if (i
.types
[op
].bitfield
.reg8
6535 || i
.types
[op
].bitfield
.reg16
6536 || i
.types
[op
].bitfield
.reg32
6537 || i
.types
[op
].bitfield
.reg64
6538 || i
.types
[op
].bitfield
.regmmx
6539 || i
.types
[op
].bitfield
.regxmm
6540 || i
.types
[op
].bitfield
.regymm
6541 || i
.types
[op
].bitfield
.regbnd
6542 || i
.types
[op
].bitfield
.regzmm
6543 || i
.types
[op
].bitfield
.regmask
6544 || i
.types
[op
].bitfield
.sreg2
6545 || i
.types
[op
].bitfield
.sreg3
6546 || i
.types
[op
].bitfield
.control
6547 || i
.types
[op
].bitfield
.debug
6548 || i
.types
[op
].bitfield
.test
)
6553 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6555 /* For instructions with VexNDS, the register-only
6556 source operand is encoded in VEX prefix. */
6557 gas_assert (mem
!= (unsigned int) ~0);
6562 gas_assert (op
< i
.operands
);
6566 /* Check register-only source operand when two source
6567 operands are swapped. */
6568 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6569 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6573 gas_assert (mem
== (vex_reg
+ 1)
6574 && op
< i
.operands
);
6579 gas_assert (vex_reg
< i
.operands
);
6583 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6585 /* For instructions with VexNDD, the register destination
6586 is encoded in VEX prefix. */
6587 if (i
.mem_operands
== 0)
6589 /* There is no memory operand. */
6590 gas_assert ((op
+ 2) == i
.operands
);
6595 /* There are only 2 operands. */
6596 gas_assert (op
< 2 && i
.operands
== 2);
6601 gas_assert (op
< i
.operands
);
6603 if (vex_reg
!= (unsigned int) ~0)
6605 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6607 if (type
->bitfield
.reg32
!= 1
6608 && type
->bitfield
.reg64
!= 1
6609 && !operand_type_equal (type
, ®xmm
)
6610 && !operand_type_equal (type
, ®ymm
)
6611 && !operand_type_equal (type
, ®zmm
)
6612 && !operand_type_equal (type
, ®mask
))
6615 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6618 /* Don't set OP operand twice. */
6621 /* If there is an extension opcode to put here, the
6622 register number must be put into the regmem field. */
6623 if (i
.tm
.extension_opcode
!= None
)
6625 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6626 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6628 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6633 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6634 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6636 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6641 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6642 must set it to 3 to indicate this is a register operand
6643 in the regmem field. */
6644 if (!i
.mem_operands
)
6648 /* Fill in i.rm.reg field with extension opcode (if any). */
6649 if (i
.tm
.extension_opcode
!= None
)
6650 i
.rm
.reg
= i
.tm
.extension_opcode
;
6656 output_branch (void)
6662 relax_substateT subtype
;
6666 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6667 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6670 if (i
.prefix
[DATA_PREFIX
] != 0)
6676 /* Pentium4 branch hints. */
6677 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6678 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6683 if (i
.prefix
[REX_PREFIX
] != 0)
6689 /* BND prefixed jump. */
6690 if (i
.prefix
[BND_PREFIX
] != 0)
6692 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6696 if (i
.prefixes
!= 0 && !intel_syntax
)
6697 as_warn (_("skipping prefixes on this instruction"));
6699 /* It's always a symbol; End frag & setup for relax.
6700 Make sure there is enough room in this frag for the largest
6701 instruction we may generate in md_convert_frag. This is 2
6702 bytes for the opcode and room for the prefix and largest
6704 frag_grow (prefix
+ 2 + 4);
6705 /* Prefix and 1 opcode byte go in fr_fix. */
6706 p
= frag_more (prefix
+ 1);
6707 if (i
.prefix
[DATA_PREFIX
] != 0)
6708 *p
++ = DATA_PREFIX_OPCODE
;
6709 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6710 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6711 *p
++ = i
.prefix
[SEG_PREFIX
];
6712 if (i
.prefix
[REX_PREFIX
] != 0)
6713 *p
++ = i
.prefix
[REX_PREFIX
];
6714 *p
= i
.tm
.base_opcode
;
6716 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6717 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6718 else if (cpu_arch_flags
.bitfield
.cpui386
)
6719 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6721 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6724 sym
= i
.op
[0].disps
->X_add_symbol
;
6725 off
= i
.op
[0].disps
->X_add_number
;
6727 if (i
.op
[0].disps
->X_op
!= O_constant
6728 && i
.op
[0].disps
->X_op
!= O_symbol
)
6730 /* Handle complex expressions. */
6731 sym
= make_expr_symbol (i
.op
[0].disps
);
6735 /* 1 possible extra opcode + 4 byte displacement go in var part.
6736 Pass reloc in fr_var. */
6737 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6747 if (i
.tm
.opcode_modifier
.jumpbyte
)
6749 /* This is a loop or jecxz type instruction. */
6751 if (i
.prefix
[ADDR_PREFIX
] != 0)
6753 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6756 /* Pentium4 branch hints. */
6757 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6758 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6760 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6769 if (flag_code
== CODE_16BIT
)
6772 if (i
.prefix
[DATA_PREFIX
] != 0)
6774 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6784 if (i
.prefix
[REX_PREFIX
] != 0)
6786 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6790 /* BND prefixed jump. */
6791 if (i
.prefix
[BND_PREFIX
] != 0)
6793 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6797 if (i
.prefixes
!= 0 && !intel_syntax
)
6798 as_warn (_("skipping prefixes on this instruction"));
6800 p
= frag_more (i
.tm
.opcode_length
+ size
);
6801 switch (i
.tm
.opcode_length
)
6804 *p
++ = i
.tm
.base_opcode
>> 8;
6806 *p
++ = i
.tm
.base_opcode
;
6812 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6813 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6815 /* All jumps handled here are signed, but don't use a signed limit
6816 check for 32 and 16 bit jumps as we want to allow wrap around at
6817 4G and 64k respectively. */
6819 fixP
->fx_signed
= 1;
6823 output_interseg_jump (void)
6831 if (flag_code
== CODE_16BIT
)
6835 if (i
.prefix
[DATA_PREFIX
] != 0)
6841 if (i
.prefix
[REX_PREFIX
] != 0)
6851 if (i
.prefixes
!= 0 && !intel_syntax
)
6852 as_warn (_("skipping prefixes on this instruction"));
6854 /* 1 opcode; 2 segment; offset */
6855 p
= frag_more (prefix
+ 1 + 2 + size
);
6857 if (i
.prefix
[DATA_PREFIX
] != 0)
6858 *p
++ = DATA_PREFIX_OPCODE
;
6860 if (i
.prefix
[REX_PREFIX
] != 0)
6861 *p
++ = i
.prefix
[REX_PREFIX
];
6863 *p
++ = i
.tm
.base_opcode
;
6864 if (i
.op
[1].imms
->X_op
== O_constant
)
6866 offsetT n
= i
.op
[1].imms
->X_add_number
;
6869 && !fits_in_unsigned_word (n
)
6870 && !fits_in_signed_word (n
))
6872 as_bad (_("16-bit jump out of range"));
6875 md_number_to_chars (p
, n
, size
);
6878 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6879 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6880 if (i
.op
[0].imms
->X_op
!= O_constant
)
6881 as_bad (_("can't handle non absolute segment in `%s'"),
6883 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6889 fragS
*insn_start_frag
;
6890 offsetT insn_start_off
;
6892 /* Tie dwarf2 debug info to the address at the start of the insn.
6893 We can't do this after the insn has been output as the current
6894 frag may have been closed off. eg. by frag_var. */
6895 dwarf2_emit_insn (0);
6897 insn_start_frag
= frag_now
;
6898 insn_start_off
= frag_now_fix ();
6901 if (i
.tm
.opcode_modifier
.jump
)
6903 else if (i
.tm
.opcode_modifier
.jumpbyte
6904 || i
.tm
.opcode_modifier
.jumpdword
)
6906 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6907 output_interseg_jump ();
6910 /* Output normal instructions here. */
6914 unsigned int prefix
;
6916 /* Some processors fail on LOCK prefix. This options makes
6917 assembler ignore LOCK prefix and serves as a workaround. */
6918 if (omit_lock_prefix
)
6920 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6922 i
.prefix
[LOCK_PREFIX
] = 0;
6925 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6926 don't need the explicit prefix. */
6927 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6929 switch (i
.tm
.opcode_length
)
6932 if (i
.tm
.base_opcode
& 0xff000000)
6934 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6939 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6941 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6942 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6945 if (prefix
!= REPE_PREFIX_OPCODE
6946 || (i
.prefix
[REP_PREFIX
]
6947 != REPE_PREFIX_OPCODE
))
6948 add_prefix (prefix
);
6951 add_prefix (prefix
);
6960 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6961 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6962 R_X86_64_GOTTPOFF relocation so that linker can safely
6963 perform IE->LE optimization. */
6964 if (x86_elf_abi
== X86_64_X32_ABI
6966 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6967 && i
.prefix
[REX_PREFIX
] == 0)
6968 add_prefix (REX_OPCODE
);
6971 /* The prefix bytes. */
6972 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6974 FRAG_APPEND_1_CHAR (*q
);
6978 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6983 /* REX byte is encoded in VEX prefix. */
6987 FRAG_APPEND_1_CHAR (*q
);
6990 /* There should be no other prefixes for instructions
6995 /* For EVEX instructions i.vrex should become 0 after
6996 build_evex_prefix. For VEX instructions upper 16 registers
6997 aren't available, so VREX should be 0. */
7000 /* Now the VEX prefix. */
7001 p
= frag_more (i
.vex
.length
);
7002 for (j
= 0; j
< i
.vex
.length
; j
++)
7003 p
[j
] = i
.vex
.bytes
[j
];
7006 /* Now the opcode; be careful about word order here! */
7007 if (i
.tm
.opcode_length
== 1)
7009 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7013 switch (i
.tm
.opcode_length
)
7017 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7018 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7022 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7032 /* Put out high byte first: can't use md_number_to_chars! */
7033 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7034 *p
= i
.tm
.base_opcode
& 0xff;
7037 /* Now the modrm byte and sib byte (if present). */
7038 if (i
.tm
.opcode_modifier
.modrm
)
7040 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7043 /* If i.rm.regmem == ESP (4)
7044 && i.rm.mode != (Register mode)
7046 ==> need second modrm byte. */
7047 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7049 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7050 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7052 | i
.sib
.scale
<< 6));
7055 if (i
.disp_operands
)
7056 output_disp (insn_start_frag
, insn_start_off
);
7059 output_imm (insn_start_frag
, insn_start_off
);
7065 pi ("" /*line*/, &i
);
7067 #endif /* DEBUG386 */
7070 /* Return the size of the displacement operand N. */
7073 disp_size (unsigned int n
)
7077 /* Vec_Disp8 has to be 8bit. */
7078 if (i
.types
[n
].bitfield
.vec_disp8
)
7080 else if (i
.types
[n
].bitfield
.disp64
)
7082 else if (i
.types
[n
].bitfield
.disp8
)
7084 else if (i
.types
[n
].bitfield
.disp16
)
7089 /* Return the size of the immediate operand N. */
7092 imm_size (unsigned int n
)
7095 if (i
.types
[n
].bitfield
.imm64
)
7097 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7099 else if (i
.types
[n
].bitfield
.imm16
)
7105 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7110 for (n
= 0; n
< i
.operands
; n
++)
7112 if (i
.types
[n
].bitfield
.vec_disp8
7113 || operand_type_check (i
.types
[n
], disp
))
7115 if (i
.op
[n
].disps
->X_op
== O_constant
)
7117 int size
= disp_size (n
);
7118 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7120 if (i
.types
[n
].bitfield
.vec_disp8
)
7122 val
= offset_in_range (val
, size
);
7123 p
= frag_more (size
);
7124 md_number_to_chars (p
, val
, size
);
7128 enum bfd_reloc_code_real reloc_type
;
7129 int size
= disp_size (n
);
7130 int sign
= i
.types
[n
].bitfield
.disp32s
;
7131 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7133 /* We can't have 8 bit displacement here. */
7134 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7136 /* The PC relative address is computed relative
7137 to the instruction boundary, so in case immediate
7138 fields follows, we need to adjust the value. */
7139 if (pcrel
&& i
.imm_operands
)
7144 for (n1
= 0; n1
< i
.operands
; n1
++)
7145 if (operand_type_check (i
.types
[n1
], imm
))
7147 /* Only one immediate is allowed for PC
7148 relative address. */
7149 gas_assert (sz
== 0);
7151 i
.op
[n
].disps
->X_add_number
-= sz
;
7153 /* We should find the immediate. */
7154 gas_assert (sz
!= 0);
7157 p
= frag_more (size
);
7158 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7160 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7161 && (((reloc_type
== BFD_RELOC_32
7162 || reloc_type
== BFD_RELOC_X86_64_32S
7163 || (reloc_type
== BFD_RELOC_64
7165 && (i
.op
[n
].disps
->X_op
== O_symbol
7166 || (i
.op
[n
].disps
->X_op
== O_add
7167 && ((symbol_get_value_expression
7168 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7170 || reloc_type
== BFD_RELOC_32_PCREL
))
7174 if (insn_start_frag
== frag_now
)
7175 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7180 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7181 for (fr
= insn_start_frag
->fr_next
;
7182 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7184 add
+= p
- frag_now
->fr_literal
;
7189 reloc_type
= BFD_RELOC_386_GOTPC
;
7190 i
.op
[n
].imms
->X_add_number
+= add
;
7192 else if (reloc_type
== BFD_RELOC_64
)
7193 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7195 /* Don't do the adjustment for x86-64, as there
7196 the pcrel addressing is relative to the _next_
7197 insn, and that is taken care of in other code. */
7198 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7200 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7201 i
.op
[n
].disps
, pcrel
, reloc_type
);
7208 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7213 for (n
= 0; n
< i
.operands
; n
++)
7215 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7216 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7219 if (operand_type_check (i
.types
[n
], imm
))
7221 if (i
.op
[n
].imms
->X_op
== O_constant
)
7223 int size
= imm_size (n
);
7226 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7228 p
= frag_more (size
);
7229 md_number_to_chars (p
, val
, size
);
7233 /* Not absolute_section.
7234 Need a 32-bit fixup (don't support 8bit
7235 non-absolute imms). Try to support other
7237 enum bfd_reloc_code_real reloc_type
;
7238 int size
= imm_size (n
);
7241 if (i
.types
[n
].bitfield
.imm32s
7242 && (i
.suffix
== QWORD_MNEM_SUFFIX
7243 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7248 p
= frag_more (size
);
7249 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7251 /* This is tough to explain. We end up with this one if we
7252 * have operands that look like
7253 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7254 * obtain the absolute address of the GOT, and it is strongly
7255 * preferable from a performance point of view to avoid using
7256 * a runtime relocation for this. The actual sequence of
7257 * instructions often look something like:
7262 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7264 * The call and pop essentially return the absolute address
7265 * of the label .L66 and store it in %ebx. The linker itself
7266 * will ultimately change the first operand of the addl so
7267 * that %ebx points to the GOT, but to keep things simple, the
7268 * .o file must have this operand set so that it generates not
7269 * the absolute address of .L66, but the absolute address of
7270 * itself. This allows the linker itself simply treat a GOTPC
7271 * relocation as asking for a pcrel offset to the GOT to be
7272 * added in, and the addend of the relocation is stored in the
7273 * operand field for the instruction itself.
7275 * Our job here is to fix the operand so that it would add
7276 * the correct offset so that %ebx would point to itself. The
7277 * thing that is tricky is that .-.L66 will point to the
7278 * beginning of the instruction, so we need to further modify
7279 * the operand so that it will point to itself. There are
7280 * other cases where you have something like:
7282 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7284 * and here no correction would be required. Internally in
7285 * the assembler we treat operands of this form as not being
7286 * pcrel since the '.' is explicitly mentioned, and I wonder
7287 * whether it would simplify matters to do it this way. Who
7288 * knows. In earlier versions of the PIC patches, the
7289 * pcrel_adjust field was used to store the correction, but
7290 * since the expression is not pcrel, I felt it would be
7291 * confusing to do it this way. */
7293 if ((reloc_type
== BFD_RELOC_32
7294 || reloc_type
== BFD_RELOC_X86_64_32S
7295 || reloc_type
== BFD_RELOC_64
)
7297 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7298 && (i
.op
[n
].imms
->X_op
== O_symbol
7299 || (i
.op
[n
].imms
->X_op
== O_add
7300 && ((symbol_get_value_expression
7301 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7306 if (insn_start_frag
== frag_now
)
7307 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7312 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7313 for (fr
= insn_start_frag
->fr_next
;
7314 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7316 add
+= p
- frag_now
->fr_literal
;
7320 reloc_type
= BFD_RELOC_386_GOTPC
;
7322 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7324 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7325 i
.op
[n
].imms
->X_add_number
+= add
;
7327 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7328 i
.op
[n
].imms
, 0, reloc_type
);
7334 /* x86_cons_fix_new is called via the expression parsing code when a
7335 reloc is needed. We use this hook to get the correct .got reloc. */
7336 static int cons_sign
= -1;
7339 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7340 expressionS
*exp
, bfd_reloc_code_real_type r
)
7342 r
= reloc (len
, 0, cons_sign
, r
);
7345 if (exp
->X_op
== O_secrel
)
7347 exp
->X_op
= O_symbol
;
7348 r
= BFD_RELOC_32_SECREL
;
7352 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7355 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7356 purpose of the `.dc.a' internal pseudo-op. */
7359 x86_address_bytes (void)
7361 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7363 return stdoutput
->arch_info
->bits_per_address
/ 8;
7366 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7368 # define lex_got(reloc, adjust, types) NULL
7370 /* Parse operands of the form
7371 <symbol>@GOTOFF+<nnn>
7372 and similar .plt or .got references.
7374 If we find one, set up the correct relocation in RELOC and copy the
7375 input string, minus the `@GOTOFF' into a malloc'd buffer for
7376 parsing by the calling routine. Return this buffer, and if ADJUST
7377 is non-null set it to the length of the string we removed from the
7378 input line. Otherwise return NULL. */
7380 lex_got (enum bfd_reloc_code_real
*rel
,
7382 i386_operand_type
*types
)
7384 /* Some of the relocations depend on the size of what field is to
7385 be relocated. But in our callers i386_immediate and i386_displacement
7386 we don't yet know the operand size (this will be set by insn
7387 matching). Hence we record the word32 relocation here,
7388 and adjust the reloc according to the real size in reloc(). */
7389 static const struct {
7392 const enum bfd_reloc_code_real rel
[2];
7393 const i386_operand_type types64
;
7395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7396 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7398 OPERAND_TYPE_IMM32_64
},
7400 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7401 BFD_RELOC_X86_64_PLTOFF64
},
7402 OPERAND_TYPE_IMM64
},
7403 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7404 BFD_RELOC_X86_64_PLT32
},
7405 OPERAND_TYPE_IMM32_32S_DISP32
},
7406 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7407 BFD_RELOC_X86_64_GOTPLT64
},
7408 OPERAND_TYPE_IMM64_DISP64
},
7409 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7410 BFD_RELOC_X86_64_GOTOFF64
},
7411 OPERAND_TYPE_IMM64_DISP64
},
7412 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7413 BFD_RELOC_X86_64_GOTPCREL
},
7414 OPERAND_TYPE_IMM32_32S_DISP32
},
7415 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7416 BFD_RELOC_X86_64_TLSGD
},
7417 OPERAND_TYPE_IMM32_32S_DISP32
},
7418 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7419 _dummy_first_bfd_reloc_code_real
},
7420 OPERAND_TYPE_NONE
},
7421 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7422 BFD_RELOC_X86_64_TLSLD
},
7423 OPERAND_TYPE_IMM32_32S_DISP32
},
7424 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7425 BFD_RELOC_X86_64_GOTTPOFF
},
7426 OPERAND_TYPE_IMM32_32S_DISP32
},
7427 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7428 BFD_RELOC_X86_64_TPOFF32
},
7429 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7430 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7431 _dummy_first_bfd_reloc_code_real
},
7432 OPERAND_TYPE_NONE
},
7433 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7434 BFD_RELOC_X86_64_DTPOFF32
},
7435 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7436 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7437 _dummy_first_bfd_reloc_code_real
},
7438 OPERAND_TYPE_NONE
},
7439 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7440 _dummy_first_bfd_reloc_code_real
},
7441 OPERAND_TYPE_NONE
},
7442 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7443 BFD_RELOC_X86_64_GOT32
},
7444 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7445 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7446 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7447 OPERAND_TYPE_IMM32_32S_DISP32
},
7448 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7449 BFD_RELOC_X86_64_TLSDESC_CALL
},
7450 OPERAND_TYPE_IMM32_32S_DISP32
},
7455 #if defined (OBJ_MAYBE_ELF)
7460 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7461 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7464 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7466 int len
= gotrel
[j
].len
;
7467 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7469 if (gotrel
[j
].rel
[object_64bit
] != 0)
7472 char *tmpbuf
, *past_reloc
;
7474 *rel
= gotrel
[j
].rel
[object_64bit
];
7478 if (flag_code
!= CODE_64BIT
)
7480 types
->bitfield
.imm32
= 1;
7481 types
->bitfield
.disp32
= 1;
7484 *types
= gotrel
[j
].types64
;
7487 if (j
!= 0 && GOT_symbol
== NULL
)
7488 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7490 /* The length of the first part of our input line. */
7491 first
= cp
- input_line_pointer
;
7493 /* The second part goes from after the reloc token until
7494 (and including) an end_of_line char or comma. */
7495 past_reloc
= cp
+ 1 + len
;
7497 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7499 second
= cp
+ 1 - past_reloc
;
7501 /* Allocate and copy string. The trailing NUL shouldn't
7502 be necessary, but be safe. */
7503 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7504 memcpy (tmpbuf
, input_line_pointer
, first
);
7505 if (second
!= 0 && *past_reloc
!= ' ')
7506 /* Replace the relocation token with ' ', so that
7507 errors like foo@GOTOFF1 will be detected. */
7508 tmpbuf
[first
++] = ' ';
7510 /* Increment length by 1 if the relocation token is
7515 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7516 tmpbuf
[first
+ second
] = '\0';
7520 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7521 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7526 /* Might be a symbol version string. Don't as_bad here. */
7535 /* Parse operands of the form
7536 <symbol>@SECREL32+<nnn>
7538 If we find one, set up the correct relocation in RELOC and copy the
7539 input string, minus the `@SECREL32' into a malloc'd buffer for
7540 parsing by the calling routine. Return this buffer, and if ADJUST
7541 is non-null set it to the length of the string we removed from the
7542 input line. Otherwise return NULL.
7544 This function is copied from the ELF version above adjusted for PE targets. */
7547 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7548 int *adjust ATTRIBUTE_UNUSED
,
7549 i386_operand_type
*types
)
7555 const enum bfd_reloc_code_real rel
[2];
7556 const i386_operand_type types64
;
7560 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7561 BFD_RELOC_32_SECREL
},
7562 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7568 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7569 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7572 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7574 int len
= gotrel
[j
].len
;
7576 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7578 if (gotrel
[j
].rel
[object_64bit
] != 0)
7581 char *tmpbuf
, *past_reloc
;
7583 *rel
= gotrel
[j
].rel
[object_64bit
];
7589 if (flag_code
!= CODE_64BIT
)
7591 types
->bitfield
.imm32
= 1;
7592 types
->bitfield
.disp32
= 1;
7595 *types
= gotrel
[j
].types64
;
7598 /* The length of the first part of our input line. */
7599 first
= cp
- input_line_pointer
;
7601 /* The second part goes from after the reloc token until
7602 (and including) an end_of_line char or comma. */
7603 past_reloc
= cp
+ 1 + len
;
7605 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7607 second
= cp
+ 1 - past_reloc
;
7609 /* Allocate and copy string. The trailing NUL shouldn't
7610 be necessary, but be safe. */
7611 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7612 memcpy (tmpbuf
, input_line_pointer
, first
);
7613 if (second
!= 0 && *past_reloc
!= ' ')
7614 /* Replace the relocation token with ' ', so that
7615 errors like foo@SECLREL321 will be detected. */
7616 tmpbuf
[first
++] = ' ';
7617 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7618 tmpbuf
[first
+ second
] = '\0';
7622 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7623 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7628 /* Might be a symbol version string. Don't as_bad here. */
7634 bfd_reloc_code_real_type
7635 x86_cons (expressionS
*exp
, int size
)
7637 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7639 intel_syntax
= -intel_syntax
;
7642 if (size
== 4 || (object_64bit
&& size
== 8))
7644 /* Handle @GOTOFF and the like in an expression. */
7646 char *gotfree_input_line
;
7649 save
= input_line_pointer
;
7650 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7651 if (gotfree_input_line
)
7652 input_line_pointer
= gotfree_input_line
;
7656 if (gotfree_input_line
)
7658 /* expression () has merrily parsed up to the end of line,
7659 or a comma - in the wrong buffer. Transfer how far
7660 input_line_pointer has moved to the right buffer. */
7661 input_line_pointer
= (save
7662 + (input_line_pointer
- gotfree_input_line
)
7664 free (gotfree_input_line
);
7665 if (exp
->X_op
== O_constant
7666 || exp
->X_op
== O_absent
7667 || exp
->X_op
== O_illegal
7668 || exp
->X_op
== O_register
7669 || exp
->X_op
== O_big
)
7671 char c
= *input_line_pointer
;
7672 *input_line_pointer
= 0;
7673 as_bad (_("missing or invalid expression `%s'"), save
);
7674 *input_line_pointer
= c
;
7681 intel_syntax
= -intel_syntax
;
7684 i386_intel_simplify (exp
);
7690 signed_cons (int size
)
7692 if (flag_code
== CODE_64BIT
)
7700 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7707 if (exp
.X_op
== O_symbol
)
7708 exp
.X_op
= O_secrel
;
7710 emit_expr (&exp
, 4);
7712 while (*input_line_pointer
++ == ',');
7714 input_line_pointer
--;
7715 demand_empty_rest_of_line ();
7719 /* Handle Vector operations. */
7722 check_VecOperations (char *op_string
, char *op_end
)
7724 const reg_entry
*mask
;
7729 && (op_end
== NULL
|| op_string
< op_end
))
7732 if (*op_string
== '{')
7736 /* Check broadcasts. */
7737 if (strncmp (op_string
, "1to", 3) == 0)
7742 goto duplicated_vec_op
;
7745 if (*op_string
== '8')
7746 bcst_type
= BROADCAST_1TO8
;
7747 else if (*op_string
== '4')
7748 bcst_type
= BROADCAST_1TO4
;
7749 else if (*op_string
== '2')
7750 bcst_type
= BROADCAST_1TO2
;
7751 else if (*op_string
== '1'
7752 && *(op_string
+1) == '6')
7754 bcst_type
= BROADCAST_1TO16
;
7759 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7764 broadcast_op
.type
= bcst_type
;
7765 broadcast_op
.operand
= this_operand
;
7766 i
.broadcast
= &broadcast_op
;
7768 /* Check masking operation. */
7769 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7771 /* k0 can't be used for write mask. */
7772 if (mask
->reg_num
== 0)
7774 as_bad (_("`%s' can't be used for write mask"),
7781 mask_op
.mask
= mask
;
7782 mask_op
.zeroing
= 0;
7783 mask_op
.operand
= this_operand
;
7789 goto duplicated_vec_op
;
7791 i
.mask
->mask
= mask
;
7793 /* Only "{z}" is allowed here. No need to check
7794 zeroing mask explicitly. */
7795 if (i
.mask
->operand
!= this_operand
)
7797 as_bad (_("invalid write mask `%s'"), saved
);
7804 /* Check zeroing-flag for masking operation. */
7805 else if (*op_string
== 'z')
7809 mask_op
.mask
= NULL
;
7810 mask_op
.zeroing
= 1;
7811 mask_op
.operand
= this_operand
;
7816 if (i
.mask
->zeroing
)
7819 as_bad (_("duplicated `%s'"), saved
);
7823 i
.mask
->zeroing
= 1;
7825 /* Only "{%k}" is allowed here. No need to check mask
7826 register explicitly. */
7827 if (i
.mask
->operand
!= this_operand
)
7829 as_bad (_("invalid zeroing-masking `%s'"),
7838 goto unknown_vec_op
;
7840 if (*op_string
!= '}')
7842 as_bad (_("missing `}' in `%s'"), saved
);
7849 /* We don't know this one. */
7850 as_bad (_("unknown vector operation: `%s'"), saved
);
7858 i386_immediate (char *imm_start
)
7860 char *save_input_line_pointer
;
7861 char *gotfree_input_line
;
7864 i386_operand_type types
;
7866 operand_type_set (&types
, ~0);
7868 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7870 as_bad (_("at most %d immediate operands are allowed"),
7871 MAX_IMMEDIATE_OPERANDS
);
7875 exp
= &im_expressions
[i
.imm_operands
++];
7876 i
.op
[this_operand
].imms
= exp
;
7878 if (is_space_char (*imm_start
))
7881 save_input_line_pointer
= input_line_pointer
;
7882 input_line_pointer
= imm_start
;
7884 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7885 if (gotfree_input_line
)
7886 input_line_pointer
= gotfree_input_line
;
7888 exp_seg
= expression (exp
);
7892 /* Handle vector operations. */
7893 if (*input_line_pointer
== '{')
7895 input_line_pointer
= check_VecOperations (input_line_pointer
,
7897 if (input_line_pointer
== NULL
)
7901 if (*input_line_pointer
)
7902 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7904 input_line_pointer
= save_input_line_pointer
;
7905 if (gotfree_input_line
)
7907 free (gotfree_input_line
);
7909 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7910 exp
->X_op
= O_illegal
;
7913 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7917 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7918 i386_operand_type types
, const char *imm_start
)
7920 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7923 as_bad (_("missing or invalid immediate expression `%s'"),
7927 else if (exp
->X_op
== O_constant
)
7929 /* Size it properly later. */
7930 i
.types
[this_operand
].bitfield
.imm64
= 1;
7931 /* If not 64bit, sign extend val. */
7932 if (flag_code
!= CODE_64BIT
7933 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7935 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7937 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7938 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7939 && exp_seg
!= absolute_section
7940 && exp_seg
!= text_section
7941 && exp_seg
!= data_section
7942 && exp_seg
!= bss_section
7943 && exp_seg
!= undefined_section
7944 && !bfd_is_com_section (exp_seg
))
7946 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7950 else if (!intel_syntax
&& exp_seg
== reg_section
)
7953 as_bad (_("illegal immediate register operand %s"), imm_start
);
7958 /* This is an address. The size of the address will be
7959 determined later, depending on destination register,
7960 suffix, or the default for the section. */
7961 i
.types
[this_operand
].bitfield
.imm8
= 1;
7962 i
.types
[this_operand
].bitfield
.imm16
= 1;
7963 i
.types
[this_operand
].bitfield
.imm32
= 1;
7964 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7965 i
.types
[this_operand
].bitfield
.imm64
= 1;
7966 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7974 i386_scale (char *scale
)
7977 char *save
= input_line_pointer
;
7979 input_line_pointer
= scale
;
7980 val
= get_absolute_expression ();
7985 i
.log2_scale_factor
= 0;
7988 i
.log2_scale_factor
= 1;
7991 i
.log2_scale_factor
= 2;
7994 i
.log2_scale_factor
= 3;
7998 char sep
= *input_line_pointer
;
8000 *input_line_pointer
= '\0';
8001 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8003 *input_line_pointer
= sep
;
8004 input_line_pointer
= save
;
8008 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8010 as_warn (_("scale factor of %d without an index register"),
8011 1 << i
.log2_scale_factor
);
8012 i
.log2_scale_factor
= 0;
8014 scale
= input_line_pointer
;
8015 input_line_pointer
= save
;
8020 i386_displacement (char *disp_start
, char *disp_end
)
8024 char *save_input_line_pointer
;
8025 char *gotfree_input_line
;
8027 i386_operand_type bigdisp
, types
= anydisp
;
8030 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8032 as_bad (_("at most %d displacement operands are allowed"),
8033 MAX_MEMORY_OPERANDS
);
8037 operand_type_set (&bigdisp
, 0);
8038 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8039 || (!current_templates
->start
->opcode_modifier
.jump
8040 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8042 bigdisp
.bitfield
.disp32
= 1;
8043 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8044 if (flag_code
== CODE_64BIT
)
8048 bigdisp
.bitfield
.disp32s
= 1;
8049 bigdisp
.bitfield
.disp64
= 1;
8052 else if ((flag_code
== CODE_16BIT
) ^ override
)
8054 bigdisp
.bitfield
.disp32
= 0;
8055 bigdisp
.bitfield
.disp16
= 1;
8060 /* For PC-relative branches, the width of the displacement
8061 is dependent upon data size, not address size. */
8062 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8063 if (flag_code
== CODE_64BIT
)
8065 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8066 bigdisp
.bitfield
.disp16
= 1;
8069 bigdisp
.bitfield
.disp32
= 1;
8070 bigdisp
.bitfield
.disp32s
= 1;
8076 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8078 : LONG_MNEM_SUFFIX
));
8079 bigdisp
.bitfield
.disp32
= 1;
8080 if ((flag_code
== CODE_16BIT
) ^ override
)
8082 bigdisp
.bitfield
.disp32
= 0;
8083 bigdisp
.bitfield
.disp16
= 1;
8087 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8090 exp
= &disp_expressions
[i
.disp_operands
];
8091 i
.op
[this_operand
].disps
= exp
;
8093 save_input_line_pointer
= input_line_pointer
;
8094 input_line_pointer
= disp_start
;
8095 END_STRING_AND_SAVE (disp_end
);
8097 #ifndef GCC_ASM_O_HACK
8098 #define GCC_ASM_O_HACK 0
8101 END_STRING_AND_SAVE (disp_end
+ 1);
8102 if (i
.types
[this_operand
].bitfield
.baseIndex
8103 && displacement_string_end
[-1] == '+')
8105 /* This hack is to avoid a warning when using the "o"
8106 constraint within gcc asm statements.
8109 #define _set_tssldt_desc(n,addr,limit,type) \
8110 __asm__ __volatile__ ( \
8112 "movw %w1,2+%0\n\t" \
8114 "movb %b1,4+%0\n\t" \
8115 "movb %4,5+%0\n\t" \
8116 "movb $0,6+%0\n\t" \
8117 "movb %h1,7+%0\n\t" \
8119 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8121 This works great except that the output assembler ends
8122 up looking a bit weird if it turns out that there is
8123 no offset. You end up producing code that looks like:
8136 So here we provide the missing zero. */
8138 *displacement_string_end
= '0';
8141 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8142 if (gotfree_input_line
)
8143 input_line_pointer
= gotfree_input_line
;
8145 exp_seg
= expression (exp
);
8148 if (*input_line_pointer
)
8149 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8151 RESTORE_END_STRING (disp_end
+ 1);
8153 input_line_pointer
= save_input_line_pointer
;
8154 if (gotfree_input_line
)
8156 free (gotfree_input_line
);
8158 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8159 exp
->X_op
= O_illegal
;
8162 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8164 RESTORE_END_STRING (disp_end
);
8170 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8171 i386_operand_type types
, const char *disp_start
)
8173 i386_operand_type bigdisp
;
8176 /* We do this to make sure that the section symbol is in
8177 the symbol table. We will ultimately change the relocation
8178 to be relative to the beginning of the section. */
8179 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8180 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8181 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8183 if (exp
->X_op
!= O_symbol
)
8186 if (S_IS_LOCAL (exp
->X_add_symbol
)
8187 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8188 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8189 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8190 exp
->X_op
= O_subtract
;
8191 exp
->X_op_symbol
= GOT_symbol
;
8192 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8193 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8194 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8195 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8197 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8200 else if (exp
->X_op
== O_absent
8201 || exp
->X_op
== O_illegal
8202 || exp
->X_op
== O_big
)
8205 as_bad (_("missing or invalid displacement expression `%s'"),
8210 else if (flag_code
== CODE_64BIT
8211 && !i
.prefix
[ADDR_PREFIX
]
8212 && exp
->X_op
== O_constant
)
8214 /* Since displacement is signed extended to 64bit, don't allow
8215 disp32 and turn off disp32s if they are out of range. */
8216 i
.types
[this_operand
].bitfield
.disp32
= 0;
8217 if (!fits_in_signed_long (exp
->X_add_number
))
8219 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8220 if (i
.types
[this_operand
].bitfield
.baseindex
)
8222 as_bad (_("0x%lx out range of signed 32bit displacement"),
8223 (long) exp
->X_add_number
);
8229 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8230 else if (exp
->X_op
!= O_constant
8231 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8232 && exp_seg
!= absolute_section
8233 && exp_seg
!= text_section
8234 && exp_seg
!= data_section
8235 && exp_seg
!= bss_section
8236 && exp_seg
!= undefined_section
8237 && !bfd_is_com_section (exp_seg
))
8239 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8244 /* Check if this is a displacement only operand. */
8245 bigdisp
= i
.types
[this_operand
];
8246 bigdisp
.bitfield
.disp8
= 0;
8247 bigdisp
.bitfield
.disp16
= 0;
8248 bigdisp
.bitfield
.disp32
= 0;
8249 bigdisp
.bitfield
.disp32s
= 0;
8250 bigdisp
.bitfield
.disp64
= 0;
8251 if (operand_type_all_zero (&bigdisp
))
8252 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8258 /* Make sure the memory operand we've been dealt is valid.
8259 Return 1 on success, 0 on a failure. */
8262 i386_index_check (const char *operand_string
)
8264 const char *kind
= "base/index";
8265 enum flag_code addr_mode
;
8267 if (i
.prefix
[ADDR_PREFIX
])
8268 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8271 addr_mode
= flag_code
;
8273 #if INFER_ADDR_PREFIX
8274 if (i
.mem_operands
== 0)
8276 /* Infer address prefix from the first memory operand. */
8277 const reg_entry
*addr_reg
= i
.base_reg
;
8279 if (addr_reg
== NULL
)
8280 addr_reg
= i
.index_reg
;
8284 if (addr_reg
->reg_num
== RegEip
8285 || addr_reg
->reg_num
== RegEiz
8286 || addr_reg
->reg_type
.bitfield
.reg32
)
8287 addr_mode
= CODE_32BIT
;
8288 else if (flag_code
!= CODE_64BIT
8289 && addr_reg
->reg_type
.bitfield
.reg16
)
8290 addr_mode
= CODE_16BIT
;
8292 if (addr_mode
!= flag_code
)
8294 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8296 /* Change the size of any displacement too. At most one
8297 of Disp16 or Disp32 is set.
8298 FIXME. There doesn't seem to be any real need for
8299 separate Disp16 and Disp32 flags. The same goes for
8300 Imm16 and Imm32. Removing them would probably clean
8301 up the code quite a lot. */
8302 if (flag_code
!= CODE_64BIT
8303 && (i
.types
[this_operand
].bitfield
.disp16
8304 || i
.types
[this_operand
].bitfield
.disp32
))
8305 i
.types
[this_operand
]
8306 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8313 if (current_templates
->start
->opcode_modifier
.isstring
8314 && !current_templates
->start
->opcode_modifier
.immext
8315 && (current_templates
->end
[-1].opcode_modifier
.isstring
8318 /* Memory operands of string insns are special in that they only allow
8319 a single register (rDI, rSI, or rBX) as their memory address. */
8320 const reg_entry
*expected_reg
;
8321 static const char *di_si
[][2] =
8327 static const char *bx
[] = { "ebx", "bx", "rbx" };
8329 kind
= "string address";
8331 if (current_templates
->start
->opcode_modifier
.w
)
8333 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8335 if (!type
.bitfield
.baseindex
8336 || ((!i
.mem_operands
!= !intel_syntax
)
8337 && current_templates
->end
[-1].operand_types
[1]
8338 .bitfield
.baseindex
))
8339 type
= current_templates
->end
[-1].operand_types
[1];
8340 expected_reg
= hash_find (reg_hash
,
8341 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8345 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8347 if (i
.base_reg
!= expected_reg
8349 || operand_type_check (i
.types
[this_operand
], disp
))
8351 /* The second memory operand must have the same size as
8355 && !((addr_mode
== CODE_64BIT
8356 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8357 || (addr_mode
== CODE_32BIT
8358 ? i
.base_reg
->reg_type
.bitfield
.reg32
8359 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8362 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8364 intel_syntax
? '[' : '(',
8366 expected_reg
->reg_name
,
8367 intel_syntax
? ']' : ')');
8374 as_bad (_("`%s' is not a valid %s expression"),
8375 operand_string
, kind
);
8380 if (addr_mode
!= CODE_16BIT
)
8382 /* 32-bit/64-bit checks. */
8384 && (addr_mode
== CODE_64BIT
8385 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8386 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8388 || (i
.base_reg
->reg_num
8389 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8391 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8392 && !i
.index_reg
->reg_type
.bitfield
.regymm
8393 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8394 && ((addr_mode
== CODE_64BIT
8395 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8396 || i
.index_reg
->reg_num
== RegRiz
)
8397 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8398 || i
.index_reg
->reg_num
== RegEiz
))
8399 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8404 /* 16-bit checks. */
8406 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8407 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8409 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8410 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8412 && i
.base_reg
->reg_num
< 6
8413 && i
.index_reg
->reg_num
>= 6
8414 && i
.log2_scale_factor
== 0))))
8421 /* Handle vector immediates. */
8424 RC_SAE_immediate (const char *imm_start
)
8426 unsigned int match_found
, j
;
8427 const char *pstr
= imm_start
;
8435 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8437 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8441 rc_op
.type
= RC_NamesTable
[j
].type
;
8442 rc_op
.operand
= this_operand
;
8443 i
.rounding
= &rc_op
;
8447 as_bad (_("duplicated `%s'"), imm_start
);
8450 pstr
+= RC_NamesTable
[j
].len
;
8460 as_bad (_("Missing '}': '%s'"), imm_start
);
8463 /* RC/SAE immediate string should contain nothing more. */;
8466 as_bad (_("Junk after '}': '%s'"), imm_start
);
8470 exp
= &im_expressions
[i
.imm_operands
++];
8471 i
.op
[this_operand
].imms
= exp
;
8473 exp
->X_op
= O_constant
;
8474 exp
->X_add_number
= 0;
8475 exp
->X_add_symbol
= (symbolS
*) 0;
8476 exp
->X_op_symbol
= (symbolS
*) 0;
8478 i
.types
[this_operand
].bitfield
.imm8
= 1;
8482 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8486 i386_att_operand (char *operand_string
)
8490 char *op_string
= operand_string
;
8492 if (is_space_char (*op_string
))
8495 /* We check for an absolute prefix (differentiating,
8496 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8497 if (*op_string
== ABSOLUTE_PREFIX
)
8500 if (is_space_char (*op_string
))
8502 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8505 /* Check if operand is a register. */
8506 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8508 i386_operand_type temp
;
8510 /* Check for a segment override by searching for ':' after a
8511 segment register. */
8513 if (is_space_char (*op_string
))
8515 if (*op_string
== ':'
8516 && (r
->reg_type
.bitfield
.sreg2
8517 || r
->reg_type
.bitfield
.sreg3
))
8522 i
.seg
[i
.mem_operands
] = &es
;
8525 i
.seg
[i
.mem_operands
] = &cs
;
8528 i
.seg
[i
.mem_operands
] = &ss
;
8531 i
.seg
[i
.mem_operands
] = &ds
;
8534 i
.seg
[i
.mem_operands
] = &fs
;
8537 i
.seg
[i
.mem_operands
] = &gs
;
8541 /* Skip the ':' and whitespace. */
8543 if (is_space_char (*op_string
))
8546 if (!is_digit_char (*op_string
)
8547 && !is_identifier_char (*op_string
)
8548 && *op_string
!= '('
8549 && *op_string
!= ABSOLUTE_PREFIX
)
8551 as_bad (_("bad memory operand `%s'"), op_string
);
8554 /* Handle case of %es:*foo. */
8555 if (*op_string
== ABSOLUTE_PREFIX
)
8558 if (is_space_char (*op_string
))
8560 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8562 goto do_memory_reference
;
8565 /* Handle vector operations. */
8566 if (*op_string
== '{')
8568 op_string
= check_VecOperations (op_string
, NULL
);
8569 if (op_string
== NULL
)
8575 as_bad (_("junk `%s' after register"), op_string
);
8579 temp
.bitfield
.baseindex
= 0;
8580 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8582 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8583 i
.op
[this_operand
].regs
= r
;
8586 else if (*op_string
== REGISTER_PREFIX
)
8588 as_bad (_("bad register name `%s'"), op_string
);
8591 else if (*op_string
== IMMEDIATE_PREFIX
)
8594 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8596 as_bad (_("immediate operand illegal with absolute jump"));
8599 if (!i386_immediate (op_string
))
8602 else if (RC_SAE_immediate (operand_string
))
8604 /* If it is a RC or SAE immediate, do nothing. */
8607 else if (is_digit_char (*op_string
)
8608 || is_identifier_char (*op_string
)
8609 || *op_string
== '(')
8611 /* This is a memory reference of some sort. */
8614 /* Start and end of displacement string expression (if found). */
8615 char *displacement_string_start
;
8616 char *displacement_string_end
;
8619 do_memory_reference
:
8620 if ((i
.mem_operands
== 1
8621 && !current_templates
->start
->opcode_modifier
.isstring
)
8622 || i
.mem_operands
== 2)
8624 as_bad (_("too many memory references for `%s'"),
8625 current_templates
->start
->name
);
8629 /* Check for base index form. We detect the base index form by
8630 looking for an ')' at the end of the operand, searching
8631 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8633 base_string
= op_string
+ strlen (op_string
);
8635 /* Handle vector operations. */
8636 vop_start
= strchr (op_string
, '{');
8637 if (vop_start
&& vop_start
< base_string
)
8639 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8641 base_string
= vop_start
;
8645 if (is_space_char (*base_string
))
8648 /* If we only have a displacement, set-up for it to be parsed later. */
8649 displacement_string_start
= op_string
;
8650 displacement_string_end
= base_string
+ 1;
8652 if (*base_string
== ')')
8655 unsigned int parens_balanced
= 1;
8656 /* We've already checked that the number of left & right ()'s are
8657 equal, so this loop will not be infinite. */
8661 if (*base_string
== ')')
8663 if (*base_string
== '(')
8666 while (parens_balanced
);
8668 temp_string
= base_string
;
8670 /* Skip past '(' and whitespace. */
8672 if (is_space_char (*base_string
))
8675 if (*base_string
== ','
8676 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8679 displacement_string_end
= temp_string
;
8681 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8685 base_string
= end_op
;
8686 if (is_space_char (*base_string
))
8690 /* There may be an index reg or scale factor here. */
8691 if (*base_string
== ',')
8694 if (is_space_char (*base_string
))
8697 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8700 base_string
= end_op
;
8701 if (is_space_char (*base_string
))
8703 if (*base_string
== ',')
8706 if (is_space_char (*base_string
))
8709 else if (*base_string
!= ')')
8711 as_bad (_("expecting `,' or `)' "
8712 "after index register in `%s'"),
8717 else if (*base_string
== REGISTER_PREFIX
)
8719 end_op
= strchr (base_string
, ',');
8722 as_bad (_("bad register name `%s'"), base_string
);
8726 /* Check for scale factor. */
8727 if (*base_string
!= ')')
8729 char *end_scale
= i386_scale (base_string
);
8734 base_string
= end_scale
;
8735 if (is_space_char (*base_string
))
8737 if (*base_string
!= ')')
8739 as_bad (_("expecting `)' "
8740 "after scale factor in `%s'"),
8745 else if (!i
.index_reg
)
8747 as_bad (_("expecting index register or scale factor "
8748 "after `,'; got '%c'"),
8753 else if (*base_string
!= ')')
8755 as_bad (_("expecting `,' or `)' "
8756 "after base register in `%s'"),
8761 else if (*base_string
== REGISTER_PREFIX
)
8763 end_op
= strchr (base_string
, ',');
8766 as_bad (_("bad register name `%s'"), base_string
);
8771 /* If there's an expression beginning the operand, parse it,
8772 assuming displacement_string_start and
8773 displacement_string_end are meaningful. */
8774 if (displacement_string_start
!= displacement_string_end
)
8776 if (!i386_displacement (displacement_string_start
,
8777 displacement_string_end
))
8781 /* Special case for (%dx) while doing input/output op. */
8783 && operand_type_equal (&i
.base_reg
->reg_type
,
8784 ®16_inoutportreg
)
8786 && i
.log2_scale_factor
== 0
8787 && i
.seg
[i
.mem_operands
] == 0
8788 && !operand_type_check (i
.types
[this_operand
], disp
))
8790 i
.types
[this_operand
] = inoutportreg
;
8794 if (i386_index_check (operand_string
) == 0)
8796 i
.types
[this_operand
].bitfield
.mem
= 1;
8801 /* It's not a memory operand; argh! */
8802 as_bad (_("invalid char %s beginning operand %d `%s'"),
8803 output_invalid (*op_string
),
8808 return 1; /* Normal return. */
8811 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8812 that an rs_machine_dependent frag may reach. */
8815 i386_frag_max_var (fragS
*frag
)
8817 /* The only relaxable frags are for jumps.
8818 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8819 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8820 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8825 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
)
8827 /* STT_GNU_IFUNC symbol must go through PLT. */
8828 if ((symbol_get_bfdsym (fr_symbol
)->flags
8829 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8832 if (!S_IS_EXTERNAL (fr_symbol
))
8833 /* Symbol may be weak or local. */
8834 return !S_IS_WEAK (fr_symbol
);
8836 /* Non-weak symbols won't be preempted. */
8840 /* Global symbols with default visibility in a shared library may be
8841 preempted by another definition. */
8842 return ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
;
8846 /* md_estimate_size_before_relax()
8848 Called just before relax() for rs_machine_dependent frags. The x86
8849 assembler uses these frags to handle variable size jump
8852 Any symbol that is now undefined will not become defined.
8853 Return the correct fr_subtype in the frag.
8854 Return the initial "guess for variable size of frag" to caller.
8855 The guess is actually the growth beyond the fixed part. Whatever
8856 we do to grow the fixed or variable part contributes to our
8860 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8862 /* We've already got fragP->fr_subtype right; all we have to do is
8863 check for un-relaxable symbols. On an ELF system, we can't relax
8864 an externally visible symbol, because it may be overridden by a
8866 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8869 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
))
8871 #if defined (OBJ_COFF) && defined (TE_PE)
8872 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8873 && S_IS_WEAK (fragP
->fr_symbol
))
8877 /* Symbol is undefined in this segment, or we need to keep a
8878 reloc so that weak symbols can be overridden. */
8879 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8880 enum bfd_reloc_code_real reloc_type
;
8881 unsigned char *opcode
;
8884 if (fragP
->fr_var
!= NO_RELOC
)
8885 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8887 reloc_type
= BFD_RELOC_16_PCREL
;
8889 reloc_type
= BFD_RELOC_32_PCREL
;
8891 old_fr_fix
= fragP
->fr_fix
;
8892 opcode
= (unsigned char *) fragP
->fr_opcode
;
8894 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8897 /* Make jmp (0xeb) a (d)word displacement jump. */
8899 fragP
->fr_fix
+= size
;
8900 fix_new (fragP
, old_fr_fix
, size
,
8902 fragP
->fr_offset
, 1,
8908 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8910 /* Negate the condition, and branch past an
8911 unconditional jump. */
8914 /* Insert an unconditional jump. */
8916 /* We added two extra opcode bytes, and have a two byte
8918 fragP
->fr_fix
+= 2 + 2;
8919 fix_new (fragP
, old_fr_fix
+ 2, 2,
8921 fragP
->fr_offset
, 1,
8928 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8933 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8935 fragP
->fr_offset
, 1,
8937 fixP
->fx_signed
= 1;
8941 /* This changes the byte-displacement jump 0x7N
8942 to the (d)word-displacement jump 0x0f,0x8N. */
8943 opcode
[1] = opcode
[0] + 0x10;
8944 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8945 /* We've added an opcode byte. */
8946 fragP
->fr_fix
+= 1 + size
;
8947 fix_new (fragP
, old_fr_fix
+ 1, size
,
8949 fragP
->fr_offset
, 1,
8954 BAD_CASE (fragP
->fr_subtype
);
8958 return fragP
->fr_fix
- old_fr_fix
;
8961 /* Guess size depending on current relax state. Initially the relax
8962 state will correspond to a short jump and we return 1, because
8963 the variable part of the frag (the branch offset) is one byte
8964 long. However, we can relax a section more than once and in that
8965 case we must either set fr_subtype back to the unrelaxed state,
8966 or return the value for the appropriate branch. */
8967 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8970 /* Called after relax() is finished.
8972 In: Address of frag.
8973 fr_type == rs_machine_dependent.
8974 fr_subtype is what the address relaxed to.
8976 Out: Any fixSs and constants are set up.
8977 Caller will turn frag into a ".space 0". */
8980 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8983 unsigned char *opcode
;
8984 unsigned char *where_to_put_displacement
= NULL
;
8985 offsetT target_address
;
8986 offsetT opcode_address
;
8987 unsigned int extension
= 0;
8988 offsetT displacement_from_opcode_start
;
8990 opcode
= (unsigned char *) fragP
->fr_opcode
;
8992 /* Address we want to reach in file space. */
8993 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8995 /* Address opcode resides at in file space. */
8996 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8998 /* Displacement from opcode start to fill into instruction. */
8999 displacement_from_opcode_start
= target_address
- opcode_address
;
9001 if ((fragP
->fr_subtype
& BIG
) == 0)
9003 /* Don't have to change opcode. */
9004 extension
= 1; /* 1 opcode + 1 displacement */
9005 where_to_put_displacement
= &opcode
[1];
9009 if (no_cond_jump_promotion
9010 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9011 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9012 _("long jump required"));
9014 switch (fragP
->fr_subtype
)
9016 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9017 extension
= 4; /* 1 opcode + 4 displacement */
9019 where_to_put_displacement
= &opcode
[1];
9022 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9023 extension
= 2; /* 1 opcode + 2 displacement */
9025 where_to_put_displacement
= &opcode
[1];
9028 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9029 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9030 extension
= 5; /* 2 opcode + 4 displacement */
9031 opcode
[1] = opcode
[0] + 0x10;
9032 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9033 where_to_put_displacement
= &opcode
[2];
9036 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9037 extension
= 3; /* 2 opcode + 2 displacement */
9038 opcode
[1] = opcode
[0] + 0x10;
9039 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9040 where_to_put_displacement
= &opcode
[2];
9043 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9048 where_to_put_displacement
= &opcode
[3];
9052 BAD_CASE (fragP
->fr_subtype
);
9057 /* If size if less then four we are sure that the operand fits,
9058 but if it's 4, then it could be that the displacement is larger
9060 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9062 && ((addressT
) (displacement_from_opcode_start
- extension
9063 + ((addressT
) 1 << 31))
9064 > (((addressT
) 2 << 31) - 1)))
9066 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9067 _("jump target out of range"));
9068 /* Make us emit 0. */
9069 displacement_from_opcode_start
= extension
;
9071 /* Now put displacement after opcode. */
9072 md_number_to_chars ((char *) where_to_put_displacement
,
9073 (valueT
) (displacement_from_opcode_start
- extension
),
9074 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9075 fragP
->fr_fix
+= extension
;
9078 /* Apply a fixup (fixP) to segment data, once it has been determined
9079 by our caller that we have all the info we need to fix it up.
9081 Parameter valP is the pointer to the value of the bits.
9083 On the 386, immediates, displacements, and data pointers are all in
9084 the same (little-endian) format, so we don't need to care about which
9088 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9090 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9091 valueT value
= *valP
;
9093 #if !defined (TE_Mach)
9096 switch (fixP
->fx_r_type
)
9102 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9105 case BFD_RELOC_X86_64_32S
:
9106 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9109 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9112 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9117 if (fixP
->fx_addsy
!= NULL
9118 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9119 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9120 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9121 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9122 && !use_rela_relocations
)
9124 /* This is a hack. There should be a better way to handle this.
9125 This covers for the fact that bfd_install_relocation will
9126 subtract the current location (for partial_inplace, PC relative
9127 relocations); see more below. */
9131 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9134 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9136 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9139 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9142 || (symbol_section_p (fixP
->fx_addsy
)
9143 && sym_seg
!= absolute_section
))
9144 && !generic_force_reloc (fixP
))
9146 /* Yes, we add the values in twice. This is because
9147 bfd_install_relocation subtracts them out again. I think
9148 bfd_install_relocation is broken, but I don't dare change
9150 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9154 #if defined (OBJ_COFF) && defined (TE_PE)
9155 /* For some reason, the PE format does not store a
9156 section address offset for a PC relative symbol. */
9157 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9158 || S_IS_WEAK (fixP
->fx_addsy
))
9159 value
+= md_pcrel_from (fixP
);
9162 #if defined (OBJ_COFF) && defined (TE_PE)
9163 if (fixP
->fx_addsy
!= NULL
9164 && S_IS_WEAK (fixP
->fx_addsy
)
9165 /* PR 16858: Do not modify weak function references. */
9166 && ! fixP
->fx_pcrel
)
9168 #if !defined (TE_PEP)
9169 /* For x86 PE weak function symbols are neither PC-relative
9170 nor do they set S_IS_FUNCTION. So the only reliable way
9171 to detect them is to check the flags of their containing
9173 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9174 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9178 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9182 /* Fix a few things - the dynamic linker expects certain values here,
9183 and we must not disappoint it. */
9184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9185 if (IS_ELF
&& fixP
->fx_addsy
)
9186 switch (fixP
->fx_r_type
)
9188 case BFD_RELOC_386_PLT32
:
9189 case BFD_RELOC_X86_64_PLT32
:
9190 /* Make the jump instruction point to the address of the operand. At
9191 runtime we merely add the offset to the actual PLT entry. */
9195 case BFD_RELOC_386_TLS_GD
:
9196 case BFD_RELOC_386_TLS_LDM
:
9197 case BFD_RELOC_386_TLS_IE_32
:
9198 case BFD_RELOC_386_TLS_IE
:
9199 case BFD_RELOC_386_TLS_GOTIE
:
9200 case BFD_RELOC_386_TLS_GOTDESC
:
9201 case BFD_RELOC_X86_64_TLSGD
:
9202 case BFD_RELOC_X86_64_TLSLD
:
9203 case BFD_RELOC_X86_64_GOTTPOFF
:
9204 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9205 value
= 0; /* Fully resolved at runtime. No addend. */
9207 case BFD_RELOC_386_TLS_LE
:
9208 case BFD_RELOC_386_TLS_LDO_32
:
9209 case BFD_RELOC_386_TLS_LE_32
:
9210 case BFD_RELOC_X86_64_DTPOFF32
:
9211 case BFD_RELOC_X86_64_DTPOFF64
:
9212 case BFD_RELOC_X86_64_TPOFF32
:
9213 case BFD_RELOC_X86_64_TPOFF64
:
9214 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9217 case BFD_RELOC_386_TLS_DESC_CALL
:
9218 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9219 value
= 0; /* Fully resolved at runtime. No addend. */
9220 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9224 case BFD_RELOC_386_GOT32
:
9225 case BFD_RELOC_X86_64_GOT32
:
9226 value
= 0; /* Fully resolved at runtime. No addend. */
9229 case BFD_RELOC_VTABLE_INHERIT
:
9230 case BFD_RELOC_VTABLE_ENTRY
:
9237 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9239 #endif /* !defined (TE_Mach) */
9241 /* Are we finished with this relocation now? */
9242 if (fixP
->fx_addsy
== NULL
)
9244 #if defined (OBJ_COFF) && defined (TE_PE)
9245 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9248 /* Remember value for tc_gen_reloc. */
9249 fixP
->fx_addnumber
= value
;
9250 /* Clear out the frag for now. */
9254 else if (use_rela_relocations
)
9256 fixP
->fx_no_overflow
= 1;
9257 /* Remember value for tc_gen_reloc. */
9258 fixP
->fx_addnumber
= value
;
9262 md_number_to_chars (p
, value
, fixP
->fx_size
);
9266 md_atof (int type
, char *litP
, int *sizeP
)
9268 /* This outputs the LITTLENUMs in REVERSE order;
9269 in accord with the bigendian 386. */
9270 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9273 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9276 output_invalid (int c
)
9279 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9282 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9283 "(0x%x)", (unsigned char) c
);
9284 return output_invalid_buf
;
9287 /* REG_STRING starts *before* REGISTER_PREFIX. */
9289 static const reg_entry
*
9290 parse_real_register (char *reg_string
, char **end_op
)
9292 char *s
= reg_string
;
9294 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9297 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9298 if (*s
== REGISTER_PREFIX
)
9301 if (is_space_char (*s
))
9305 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9307 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9308 return (const reg_entry
*) NULL
;
9312 /* For naked regs, make sure that we are not dealing with an identifier.
9313 This prevents confusing an identifier like `eax_var' with register
9315 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9316 return (const reg_entry
*) NULL
;
9320 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9322 /* Handle floating point regs, allowing spaces in the (i) part. */
9323 if (r
== i386_regtab
/* %st is first entry of table */)
9325 if (is_space_char (*s
))
9330 if (is_space_char (*s
))
9332 if (*s
>= '0' && *s
<= '7')
9336 if (is_space_char (*s
))
9341 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9346 /* We have "%st(" then garbage. */
9347 return (const reg_entry
*) NULL
;
9351 if (r
== NULL
|| allow_pseudo_reg
)
9354 if (operand_type_all_zero (&r
->reg_type
))
9355 return (const reg_entry
*) NULL
;
9357 if ((r
->reg_type
.bitfield
.reg32
9358 || r
->reg_type
.bitfield
.sreg3
9359 || r
->reg_type
.bitfield
.control
9360 || r
->reg_type
.bitfield
.debug
9361 || r
->reg_type
.bitfield
.test
)
9362 && !cpu_arch_flags
.bitfield
.cpui386
)
9363 return (const reg_entry
*) NULL
;
9365 if (r
->reg_type
.bitfield
.floatreg
9366 && !cpu_arch_flags
.bitfield
.cpu8087
9367 && !cpu_arch_flags
.bitfield
.cpu287
9368 && !cpu_arch_flags
.bitfield
.cpu387
)
9369 return (const reg_entry
*) NULL
;
9371 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9372 return (const reg_entry
*) NULL
;
9374 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9375 return (const reg_entry
*) NULL
;
9377 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9378 return (const reg_entry
*) NULL
;
9380 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9381 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9382 return (const reg_entry
*) NULL
;
9384 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9385 if (!allow_index_reg
9386 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9387 return (const reg_entry
*) NULL
;
9389 /* Upper 16 vector register is only available with VREX in 64bit
9391 if ((r
->reg_flags
& RegVRex
))
9393 if (!cpu_arch_flags
.bitfield
.cpuvrex
9394 || flag_code
!= CODE_64BIT
)
9395 return (const reg_entry
*) NULL
;
9400 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9401 || r
->reg_type
.bitfield
.reg64
)
9402 && (!cpu_arch_flags
.bitfield
.cpulm
9403 || !operand_type_equal (&r
->reg_type
, &control
))
9404 && flag_code
!= CODE_64BIT
)
9405 return (const reg_entry
*) NULL
;
9407 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9408 return (const reg_entry
*) NULL
;
9413 /* REG_STRING starts *before* REGISTER_PREFIX. */
9415 static const reg_entry
*
9416 parse_register (char *reg_string
, char **end_op
)
9420 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9421 r
= parse_real_register (reg_string
, end_op
);
9426 char *save
= input_line_pointer
;
9430 input_line_pointer
= reg_string
;
9431 c
= get_symbol_end ();
9432 symbolP
= symbol_find (reg_string
);
9433 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9435 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9437 know (e
->X_op
== O_register
);
9438 know (e
->X_add_number
>= 0
9439 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9440 r
= i386_regtab
+ e
->X_add_number
;
9441 if ((r
->reg_flags
& RegVRex
))
9443 *end_op
= input_line_pointer
;
9445 *input_line_pointer
= c
;
9446 input_line_pointer
= save
;
9452 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9455 char *end
= input_line_pointer
;
9458 r
= parse_register (name
, &input_line_pointer
);
9459 if (r
&& end
<= input_line_pointer
)
9461 *nextcharP
= *input_line_pointer
;
9462 *input_line_pointer
= 0;
9463 e
->X_op
= O_register
;
9464 e
->X_add_number
= r
- i386_regtab
;
9467 input_line_pointer
= end
;
9469 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9473 md_operand (expressionS
*e
)
9478 switch (*input_line_pointer
)
9480 case REGISTER_PREFIX
:
9481 r
= parse_real_register (input_line_pointer
, &end
);
9484 e
->X_op
= O_register
;
9485 e
->X_add_number
= r
- i386_regtab
;
9486 input_line_pointer
= end
;
9491 gas_assert (intel_syntax
);
9492 end
= input_line_pointer
++;
9494 if (*input_line_pointer
== ']')
9496 ++input_line_pointer
;
9497 e
->X_op_symbol
= make_expr_symbol (e
);
9498 e
->X_add_symbol
= NULL
;
9499 e
->X_add_number
= 0;
9505 input_line_pointer
= end
;
9512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9513 const char *md_shortopts
= "kVQ:sqn";
9515 const char *md_shortopts
= "qn";
9518 #define OPTION_32 (OPTION_MD_BASE + 0)
9519 #define OPTION_64 (OPTION_MD_BASE + 1)
9520 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9521 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9522 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9523 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9524 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9525 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9526 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9527 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9528 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9529 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9530 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9531 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9532 #define OPTION_X32 (OPTION_MD_BASE + 14)
9533 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9534 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9535 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9536 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9537 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9538 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9539 #define OPTION_MNO_SHARED (OPTION_MD_BASE + 21)
9541 struct option md_longopts
[] =
9543 {"32", no_argument
, NULL
, OPTION_32
},
9544 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9545 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9546 {"64", no_argument
, NULL
, OPTION_64
},
9548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9549 {"x32", no_argument
, NULL
, OPTION_X32
},
9550 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
9552 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9553 {"march", required_argument
, NULL
, OPTION_MARCH
},
9554 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9555 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9556 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9557 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9558 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9559 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9560 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9561 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9562 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9563 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9564 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9565 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9566 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9567 # if defined (TE_PE) || defined (TE_PEP)
9568 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9570 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9571 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9572 {NULL
, no_argument
, NULL
, 0}
9574 size_t md_longopts_size
= sizeof (md_longopts
);
9577 md_parse_option (int c
, char *arg
)
9585 optimize_align_code
= 0;
9592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9593 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9594 should be emitted or not. FIXME: Not implemented. */
9598 /* -V: SVR4 argument to print version ID. */
9600 print_version_id ();
9603 /* -k: Ignore for FreeBSD compatibility. */
9608 /* -s: On i386 Solaris, this tells the native assembler to use
9609 .stab instead of .stab.excl. We always use .stab anyhow. */
9612 case OPTION_MNO_SHARED
:
9616 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9617 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9620 const char **list
, **l
;
9622 list
= bfd_target_list ();
9623 for (l
= list
; *l
!= NULL
; l
++)
9624 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9625 || strcmp (*l
, "coff-x86-64") == 0
9626 || strcmp (*l
, "pe-x86-64") == 0
9627 || strcmp (*l
, "pei-x86-64") == 0
9628 || strcmp (*l
, "mach-o-x86-64") == 0)
9630 default_arch
= "x86_64";
9634 as_fatal (_("no compiled in support for x86_64"));
9640 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9644 const char **list
, **l
;
9646 list
= bfd_target_list ();
9647 for (l
= list
; *l
!= NULL
; l
++)
9648 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9650 default_arch
= "x86_64:32";
9654 as_fatal (_("no compiled in support for 32bit x86_64"));
9658 as_fatal (_("32bit x86_64 is only supported for ELF"));
9663 default_arch
= "i386";
9667 #ifdef SVR4_COMMENT_CHARS
9672 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9674 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9678 i386_comment_chars
= n
;
9684 arch
= xstrdup (arg
);
9688 as_fatal (_("invalid -march= option: `%s'"), arg
);
9689 next
= strchr (arch
, '+');
9692 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9694 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9697 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9700 cpu_arch_name
= cpu_arch
[j
].name
;
9701 cpu_sub_arch_name
= NULL
;
9702 cpu_arch_flags
= cpu_arch
[j
].flags
;
9703 cpu_arch_isa
= cpu_arch
[j
].type
;
9704 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9705 if (!cpu_arch_tune_set
)
9707 cpu_arch_tune
= cpu_arch_isa
;
9708 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9712 else if (*cpu_arch
[j
].name
== '.'
9713 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9715 /* ISA entension. */
9716 i386_cpu_flags flags
;
9718 if (!cpu_arch
[j
].negated
)
9719 flags
= cpu_flags_or (cpu_arch_flags
,
9722 flags
= cpu_flags_and_not (cpu_arch_flags
,
9725 if (!valid_iamcu_cpu_flags (&flags
))
9726 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9727 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9729 if (cpu_sub_arch_name
)
9731 char *name
= cpu_sub_arch_name
;
9732 cpu_sub_arch_name
= concat (name
,
9734 (const char *) NULL
);
9738 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9739 cpu_arch_flags
= flags
;
9740 cpu_arch_isa_flags
= flags
;
9746 if (j
>= ARRAY_SIZE (cpu_arch
))
9747 as_fatal (_("invalid -march= option: `%s'"), arg
);
9751 while (next
!= NULL
);
9756 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9757 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9759 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9761 cpu_arch_tune_set
= 1;
9762 cpu_arch_tune
= cpu_arch
[j
].type
;
9763 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9767 if (j
>= ARRAY_SIZE (cpu_arch
))
9768 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9771 case OPTION_MMNEMONIC
:
9772 if (strcasecmp (arg
, "att") == 0)
9774 else if (strcasecmp (arg
, "intel") == 0)
9777 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9780 case OPTION_MSYNTAX
:
9781 if (strcasecmp (arg
, "att") == 0)
9783 else if (strcasecmp (arg
, "intel") == 0)
9786 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9789 case OPTION_MINDEX_REG
:
9790 allow_index_reg
= 1;
9793 case OPTION_MNAKED_REG
:
9794 allow_naked_reg
= 1;
9797 case OPTION_MOLD_GCC
:
9801 case OPTION_MSSE2AVX
:
9805 case OPTION_MSSE_CHECK
:
9806 if (strcasecmp (arg
, "error") == 0)
9807 sse_check
= check_error
;
9808 else if (strcasecmp (arg
, "warning") == 0)
9809 sse_check
= check_warning
;
9810 else if (strcasecmp (arg
, "none") == 0)
9811 sse_check
= check_none
;
9813 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9816 case OPTION_MOPERAND_CHECK
:
9817 if (strcasecmp (arg
, "error") == 0)
9818 operand_check
= check_error
;
9819 else if (strcasecmp (arg
, "warning") == 0)
9820 operand_check
= check_warning
;
9821 else if (strcasecmp (arg
, "none") == 0)
9822 operand_check
= check_none
;
9824 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9827 case OPTION_MAVXSCALAR
:
9828 if (strcasecmp (arg
, "128") == 0)
9830 else if (strcasecmp (arg
, "256") == 0)
9833 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9836 case OPTION_MADD_BND_PREFIX
:
9840 case OPTION_MEVEXLIG
:
9841 if (strcmp (arg
, "128") == 0)
9843 else if (strcmp (arg
, "256") == 0)
9845 else if (strcmp (arg
, "512") == 0)
9848 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9851 case OPTION_MEVEXRCIG
:
9852 if (strcmp (arg
, "rne") == 0)
9854 else if (strcmp (arg
, "rd") == 0)
9856 else if (strcmp (arg
, "ru") == 0)
9858 else if (strcmp (arg
, "rz") == 0)
9861 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9864 case OPTION_MEVEXWIG
:
9865 if (strcmp (arg
, "0") == 0)
9867 else if (strcmp (arg
, "1") == 0)
9870 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9873 # if defined (TE_PE) || defined (TE_PEP)
9874 case OPTION_MBIG_OBJ
:
9879 case OPTION_OMIT_LOCK_PREFIX
:
9880 if (strcasecmp (arg
, "yes") == 0)
9881 omit_lock_prefix
= 1;
9882 else if (strcasecmp (arg
, "no") == 0)
9883 omit_lock_prefix
= 0;
9885 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9894 #define MESSAGE_TEMPLATE \
9898 show_arch (FILE *stream
, int ext
, int check
)
9900 static char message
[] = MESSAGE_TEMPLATE
;
9901 char *start
= message
+ 27;
9903 int size
= sizeof (MESSAGE_TEMPLATE
);
9910 left
= size
- (start
- message
);
9911 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9913 /* Should it be skipped? */
9914 if (cpu_arch
[j
].skip
)
9917 name
= cpu_arch
[j
].name
;
9918 len
= cpu_arch
[j
].len
;
9921 /* It is an extension. Skip if we aren't asked to show it. */
9932 /* It is an processor. Skip if we show only extension. */
9935 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9937 /* It is an impossible processor - skip. */
9941 /* Reserve 2 spaces for ", " or ",\0" */
9944 /* Check if there is any room. */
9952 p
= mempcpy (p
, name
, len
);
9956 /* Output the current message now and start a new one. */
9959 fprintf (stream
, "%s\n", message
);
9961 left
= size
- (start
- message
) - len
- 2;
9963 gas_assert (left
>= 0);
9965 p
= mempcpy (p
, name
, len
);
9970 fprintf (stream
, "%s\n", message
);
9974 md_show_usage (FILE *stream
)
9976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9977 fprintf (stream
, _("\
9979 -V print assembler version number\n\
9982 fprintf (stream
, _("\
9983 -n Do not optimize code alignment\n\
9984 -q quieten some warnings\n"));
9985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9986 fprintf (stream
, _("\
9989 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9990 || defined (TE_PE) || defined (TE_PEP))
9991 fprintf (stream
, _("\
9992 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9994 #ifdef SVR4_COMMENT_CHARS
9995 fprintf (stream
, _("\
9996 --divide do not treat `/' as a comment character\n"));
9998 fprintf (stream
, _("\
9999 --divide ignored\n"));
10001 fprintf (stream
, _("\
10002 -march=CPU[,+EXTENSION...]\n\
10003 generate code for CPU and EXTENSION, CPU is one of:\n"));
10004 show_arch (stream
, 0, 1);
10005 fprintf (stream
, _("\
10006 EXTENSION is combination of:\n"));
10007 show_arch (stream
, 1, 0);
10008 fprintf (stream
, _("\
10009 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10010 show_arch (stream
, 0, 0);
10011 fprintf (stream
, _("\
10012 -msse2avx encode SSE instructions with VEX prefix\n"));
10013 fprintf (stream
, _("\
10014 -msse-check=[none|error|warning]\n\
10015 check SSE instructions\n"));
10016 fprintf (stream
, _("\
10017 -moperand-check=[none|error|warning]\n\
10018 check operand combinations for validity\n"));
10019 fprintf (stream
, _("\
10020 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10022 fprintf (stream
, _("\
10023 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10025 fprintf (stream
, _("\
10026 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10027 for EVEX.W bit ignored instructions\n"));
10028 fprintf (stream
, _("\
10029 -mevexrcig=[rne|rd|ru|rz]\n\
10030 encode EVEX instructions with specific EVEX.RC value\n\
10031 for SAE-only ignored instructions\n"));
10032 fprintf (stream
, _("\
10033 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10034 fprintf (stream
, _("\
10035 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10036 fprintf (stream
, _("\
10037 -mindex-reg support pseudo index registers\n"));
10038 fprintf (stream
, _("\
10039 -mnaked-reg don't require `%%' prefix for registers\n"));
10040 fprintf (stream
, _("\
10041 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10042 fprintf (stream
, _("\
10043 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10044 fprintf (stream
, _("\
10045 -mno-shared enable branch optimization for non shared code\n"));
10046 # if defined (TE_PE) || defined (TE_PEP)
10047 fprintf (stream
, _("\
10048 -mbig-obj generate big object files\n"));
10050 fprintf (stream
, _("\
10051 -momit-lock-prefix=[no|yes]\n\
10052 strip all lock prefixes\n"));
10055 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10056 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10057 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10059 /* Pick the target format to use. */
10062 i386_target_format (void)
10064 if (!strncmp (default_arch
, "x86_64", 6))
10066 update_code_flag (CODE_64BIT
, 1);
10067 if (default_arch
[6] == '\0')
10068 x86_elf_abi
= X86_64_ABI
;
10070 x86_elf_abi
= X86_64_X32_ABI
;
10072 else if (!strcmp (default_arch
, "i386"))
10073 update_code_flag (CODE_32BIT
, 1);
10075 as_fatal (_("unknown architecture"));
10077 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10078 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10079 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10080 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10082 switch (OUTPUT_FLAVOR
)
10084 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10085 case bfd_target_aout_flavour
:
10086 return AOUT_TARGET_FORMAT
;
10088 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10089 # if defined (TE_PE) || defined (TE_PEP)
10090 case bfd_target_coff_flavour
:
10091 if (flag_code
== CODE_64BIT
)
10092 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10095 # elif defined (TE_GO32)
10096 case bfd_target_coff_flavour
:
10097 return "coff-go32";
10099 case bfd_target_coff_flavour
:
10100 return "coff-i386";
10103 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10104 case bfd_target_elf_flavour
:
10106 const char *format
;
10108 switch (x86_elf_abi
)
10111 format
= ELF_TARGET_FORMAT
;
10114 use_rela_relocations
= 1;
10116 format
= ELF_TARGET_FORMAT64
;
10118 case X86_64_X32_ABI
:
10119 use_rela_relocations
= 1;
10121 disallow_64bit_reloc
= 1;
10122 format
= ELF_TARGET_FORMAT32
;
10125 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10127 if (x86_elf_abi
!= X86_64_ABI
)
10128 as_fatal (_("Intel L1OM is 64bit only"));
10129 return ELF_TARGET_L1OM_FORMAT
;
10131 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10133 if (x86_elf_abi
!= X86_64_ABI
)
10134 as_fatal (_("Intel K1OM is 64bit only"));
10135 return ELF_TARGET_K1OM_FORMAT
;
10137 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10139 if (x86_elf_abi
!= I386_ABI
)
10140 as_fatal (_("Intel MCU is 32bit only"));
10141 return ELF_TARGET_IAMCU_FORMAT
;
10147 #if defined (OBJ_MACH_O)
10148 case bfd_target_mach_o_flavour
:
10149 if (flag_code
== CODE_64BIT
)
10151 use_rela_relocations
= 1;
10153 return "mach-o-x86-64";
10156 return "mach-o-i386";
10164 #endif /* OBJ_MAYBE_ more than one */
10167 md_undefined_symbol (char *name
)
10169 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10170 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10171 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10172 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10176 if (symbol_find (name
))
10177 as_bad (_("GOT already in symbol table"));
10178 GOT_symbol
= symbol_new (name
, undefined_section
,
10179 (valueT
) 0, &zero_address_frag
);
10186 /* Round up a section size to the appropriate boundary. */
10189 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10191 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10192 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10194 /* For a.out, force the section size to be aligned. If we don't do
10195 this, BFD will align it for us, but it will not write out the
10196 final bytes of the section. This may be a bug in BFD, but it is
10197 easier to fix it here since that is how the other a.out targets
10201 align
= bfd_get_section_alignment (stdoutput
, segment
);
10202 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10209 /* On the i386, PC-relative offsets are relative to the start of the
10210 next instruction. That is, the address of the offset, plus its
10211 size, since the offset is always the last part of the insn. */
10214 md_pcrel_from (fixS
*fixP
)
10216 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10222 s_bss (int ignore ATTRIBUTE_UNUSED
)
10226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10228 obj_elf_section_change_hook ();
10230 temp
= get_absolute_expression ();
10231 subseg_set (bss_section
, (subsegT
) temp
);
10232 demand_empty_rest_of_line ();
10238 i386_validate_fix (fixS
*fixp
)
10240 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10242 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10246 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10251 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10253 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10255 fixp
->fx_subsy
= 0;
10260 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10263 bfd_reloc_code_real_type code
;
10265 switch (fixp
->fx_r_type
)
10267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10268 case BFD_RELOC_SIZE32
:
10269 case BFD_RELOC_SIZE64
:
10270 if (S_IS_DEFINED (fixp
->fx_addsy
)
10271 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10273 /* Resolve size relocation against local symbol to size of
10274 the symbol plus addend. */
10275 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10276 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10277 && !fits_in_unsigned_long (value
))
10278 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10279 _("symbol size computation overflow"));
10280 fixp
->fx_addsy
= NULL
;
10281 fixp
->fx_subsy
= NULL
;
10282 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10287 case BFD_RELOC_X86_64_PLT32
:
10288 case BFD_RELOC_X86_64_GOT32
:
10289 case BFD_RELOC_X86_64_GOTPCREL
:
10290 case BFD_RELOC_386_PLT32
:
10291 case BFD_RELOC_386_GOT32
:
10292 case BFD_RELOC_386_GOTOFF
:
10293 case BFD_RELOC_386_GOTPC
:
10294 case BFD_RELOC_386_TLS_GD
:
10295 case BFD_RELOC_386_TLS_LDM
:
10296 case BFD_RELOC_386_TLS_LDO_32
:
10297 case BFD_RELOC_386_TLS_IE_32
:
10298 case BFD_RELOC_386_TLS_IE
:
10299 case BFD_RELOC_386_TLS_GOTIE
:
10300 case BFD_RELOC_386_TLS_LE_32
:
10301 case BFD_RELOC_386_TLS_LE
:
10302 case BFD_RELOC_386_TLS_GOTDESC
:
10303 case BFD_RELOC_386_TLS_DESC_CALL
:
10304 case BFD_RELOC_X86_64_TLSGD
:
10305 case BFD_RELOC_X86_64_TLSLD
:
10306 case BFD_RELOC_X86_64_DTPOFF32
:
10307 case BFD_RELOC_X86_64_DTPOFF64
:
10308 case BFD_RELOC_X86_64_GOTTPOFF
:
10309 case BFD_RELOC_X86_64_TPOFF32
:
10310 case BFD_RELOC_X86_64_TPOFF64
:
10311 case BFD_RELOC_X86_64_GOTOFF64
:
10312 case BFD_RELOC_X86_64_GOTPC32
:
10313 case BFD_RELOC_X86_64_GOT64
:
10314 case BFD_RELOC_X86_64_GOTPCREL64
:
10315 case BFD_RELOC_X86_64_GOTPC64
:
10316 case BFD_RELOC_X86_64_GOTPLT64
:
10317 case BFD_RELOC_X86_64_PLTOFF64
:
10318 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10319 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10320 case BFD_RELOC_RVA
:
10321 case BFD_RELOC_VTABLE_ENTRY
:
10322 case BFD_RELOC_VTABLE_INHERIT
:
10324 case BFD_RELOC_32_SECREL
:
10326 code
= fixp
->fx_r_type
;
10328 case BFD_RELOC_X86_64_32S
:
10329 if (!fixp
->fx_pcrel
)
10331 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10332 code
= fixp
->fx_r_type
;
10336 if (fixp
->fx_pcrel
)
10338 switch (fixp
->fx_size
)
10341 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10342 _("can not do %d byte pc-relative relocation"),
10344 code
= BFD_RELOC_32_PCREL
;
10346 case 1: code
= BFD_RELOC_8_PCREL
; break;
10347 case 2: code
= BFD_RELOC_16_PCREL
; break;
10348 case 4: code
= BFD_RELOC_32_PCREL
; break;
10350 case 8: code
= BFD_RELOC_64_PCREL
; break;
10356 switch (fixp
->fx_size
)
10359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10360 _("can not do %d byte relocation"),
10362 code
= BFD_RELOC_32
;
10364 case 1: code
= BFD_RELOC_8
; break;
10365 case 2: code
= BFD_RELOC_16
; break;
10366 case 4: code
= BFD_RELOC_32
; break;
10368 case 8: code
= BFD_RELOC_64
; break;
10375 if ((code
== BFD_RELOC_32
10376 || code
== BFD_RELOC_32_PCREL
10377 || code
== BFD_RELOC_X86_64_32S
)
10379 && fixp
->fx_addsy
== GOT_symbol
)
10382 code
= BFD_RELOC_386_GOTPC
;
10384 code
= BFD_RELOC_X86_64_GOTPC32
;
10386 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10388 && fixp
->fx_addsy
== GOT_symbol
)
10390 code
= BFD_RELOC_X86_64_GOTPC64
;
10393 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10394 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10395 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10397 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10399 if (!use_rela_relocations
)
10401 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10402 vtable entry to be used in the relocation's section offset. */
10403 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10404 rel
->address
= fixp
->fx_offset
;
10405 #if defined (OBJ_COFF) && defined (TE_PE)
10406 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10407 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10412 /* Use the rela in 64bit mode. */
10415 if (disallow_64bit_reloc
)
10418 case BFD_RELOC_X86_64_DTPOFF64
:
10419 case BFD_RELOC_X86_64_TPOFF64
:
10420 case BFD_RELOC_64_PCREL
:
10421 case BFD_RELOC_X86_64_GOTOFF64
:
10422 case BFD_RELOC_X86_64_GOT64
:
10423 case BFD_RELOC_X86_64_GOTPCREL64
:
10424 case BFD_RELOC_X86_64_GOTPC64
:
10425 case BFD_RELOC_X86_64_GOTPLT64
:
10426 case BFD_RELOC_X86_64_PLTOFF64
:
10427 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10428 _("cannot represent relocation type %s in x32 mode"),
10429 bfd_get_reloc_code_name (code
));
10435 if (!fixp
->fx_pcrel
)
10436 rel
->addend
= fixp
->fx_offset
;
10440 case BFD_RELOC_X86_64_PLT32
:
10441 case BFD_RELOC_X86_64_GOT32
:
10442 case BFD_RELOC_X86_64_GOTPCREL
:
10443 case BFD_RELOC_X86_64_TLSGD
:
10444 case BFD_RELOC_X86_64_TLSLD
:
10445 case BFD_RELOC_X86_64_GOTTPOFF
:
10446 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10447 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10448 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10451 rel
->addend
= (section
->vma
10453 + fixp
->fx_addnumber
10454 + md_pcrel_from (fixp
));
10459 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10460 if (rel
->howto
== NULL
)
10462 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10463 _("cannot represent relocation type %s"),
10464 bfd_get_reloc_code_name (code
));
10465 /* Set howto to a garbage value so that we can keep going. */
10466 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10467 gas_assert (rel
->howto
!= NULL
);
10473 #include "tc-i386-intel.c"
10476 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10478 int saved_naked_reg
;
10479 char saved_register_dot
;
10481 saved_naked_reg
= allow_naked_reg
;
10482 allow_naked_reg
= 1;
10483 saved_register_dot
= register_chars
['.'];
10484 register_chars
['.'] = '.';
10485 allow_pseudo_reg
= 1;
10486 expression_and_evaluate (exp
);
10487 allow_pseudo_reg
= 0;
10488 register_chars
['.'] = saved_register_dot
;
10489 allow_naked_reg
= saved_naked_reg
;
10491 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10493 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10495 exp
->X_op
= O_constant
;
10496 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10497 .dw2_regnum
[flag_code
>> 1];
10500 exp
->X_op
= O_illegal
;
10505 tc_x86_frame_initial_instructions (void)
10507 static unsigned int sp_regno
[2];
10509 if (!sp_regno
[flag_code
>> 1])
10511 char *saved_input
= input_line_pointer
;
10512 char sp
[][4] = {"esp", "rsp"};
10515 input_line_pointer
= sp
[flag_code
>> 1];
10516 tc_x86_parse_to_dw2regnum (&exp
);
10517 gas_assert (exp
.X_op
== O_constant
);
10518 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10519 input_line_pointer
= saved_input
;
10522 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10523 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10527 x86_dwarf2_addr_size (void)
10529 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10530 if (x86_elf_abi
== X86_64_X32_ABI
)
10533 return bfd_arch_bits_per_address (stdoutput
) / 8;
10537 i386_elf_section_type (const char *str
, size_t len
)
10539 if (flag_code
== CODE_64BIT
10540 && len
== sizeof ("unwind") - 1
10541 && strncmp (str
, "unwind", 6) == 0)
10542 return SHT_X86_64_UNWIND
;
10549 i386_solaris_fix_up_eh_frame (segT sec
)
10551 if (flag_code
== CODE_64BIT
)
10552 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10558 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10562 exp
.X_op
= O_secrel
;
10563 exp
.X_add_symbol
= symbol
;
10564 exp
.X_add_number
= 0;
10565 emit_expr (&exp
, size
);
10569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10570 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10573 x86_64_section_letter (int letter
, char **ptr_msg
)
10575 if (flag_code
== CODE_64BIT
)
10578 return SHF_X86_64_LARGE
;
10580 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10583 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10588 x86_64_section_word (char *str
, size_t len
)
10590 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10591 return SHF_X86_64_LARGE
;
10597 handle_large_common (int small ATTRIBUTE_UNUSED
)
10599 if (flag_code
!= CODE_64BIT
)
10601 s_comm_internal (0, elf_common_parse
);
10602 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10606 static segT lbss_section
;
10607 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10608 asection
*saved_bss_section
= bss_section
;
10610 if (lbss_section
== NULL
)
10612 flagword applicable
;
10613 segT seg
= now_seg
;
10614 subsegT subseg
= now_subseg
;
10616 /* The .lbss section is for local .largecomm symbols. */
10617 lbss_section
= subseg_new (".lbss", 0);
10618 applicable
= bfd_applicable_section_flags (stdoutput
);
10619 bfd_set_section_flags (stdoutput
, lbss_section
,
10620 applicable
& SEC_ALLOC
);
10621 seg_info (lbss_section
)->bss
= 1;
10623 subseg_set (seg
, subseg
);
10626 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10627 bss_section
= lbss_section
;
10629 s_comm_internal (0, elf_common_parse
);
10631 elf_com_section_ptr
= saved_com_section_ptr
;
10632 bss_section
= saved_bss_section
;
10635 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */