1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 static enum check_kind
552 sse_check
, operand_check
= check_warning
;
554 /* Register prefix used for error message. */
555 static const char *register_prefix
= "%";
557 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560 static char stackop_size
= '\0';
562 /* Non-zero to optimize code alignment. */
563 int optimize_align_code
= 1;
565 /* Non-zero to quieten some warnings. */
566 static int quiet_warnings
= 0;
569 static const char *cpu_arch_name
= NULL
;
570 static char *cpu_sub_arch_name
= NULL
;
572 /* CPU feature flags. */
573 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
575 /* If we have selected a cpu we are generating instructions for. */
576 static int cpu_arch_tune_set
= 0;
578 /* Cpu we are generating instructions for. */
579 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
581 /* CPU feature flags of cpu we are generating instructions for. */
582 static i386_cpu_flags cpu_arch_tune_flags
;
584 /* CPU instruction set architecture used. */
585 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
587 /* CPU feature flags of instruction set architecture used. */
588 i386_cpu_flags cpu_arch_isa_flags
;
590 /* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592 static unsigned int no_cond_jump_promotion
= 0;
594 /* Encode SSE instructions with VEX prefix. */
595 static unsigned int sse2avx
;
597 /* Encode scalar AVX instructions with specific vector length. */
604 /* Encode scalar EVEX LIG instructions with specific vector length. */
612 /* Encode EVEX WIG instructions with specific evex.w. */
619 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
620 static symbolS
*GOT_symbol
;
622 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
623 unsigned int x86_dwarf2_return_column
;
625 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626 int x86_cie_data_alignment
;
628 /* Interface to relax_segment.
629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
634 #define UNCOND_JUMP 0
636 #define COND_JUMP86 2
641 #define SMALL16 (SMALL | CODE16)
643 #define BIG16 (BIG | CODE16)
647 #define INLINE __inline__
653 #define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655 #define TYPE_FROM_RELAX_STATE(s) \
657 #define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
660 /* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
668 const relax_typeS md_relax_table
[] =
671 1) most positive reach of this state,
672 2) most negative reach of this state,
673 3) how many bytes this mode will have in the variable part of the frag
674 4) which index into the table to try if we can't fit into this one. */
676 /* UNCOND_JUMP states. */
677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
692 /* word conditionals add 3 bytes to frag:
693 1 extra opcode byte, 2 displacement bytes. */
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
707 static const arch_entry cpu_arch
[] =
709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
712 CPU_GENERIC32_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
714 CPU_GENERIC64_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
716 CPU_NONE_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
718 CPU_I186_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
720 CPU_I286_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
722 CPU_I386_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
724 CPU_I486_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
726 CPU_I586_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
728 CPU_I686_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
730 CPU_I586_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
732 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
734 CPU_P2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
736 CPU_P3_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
738 CPU_P4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
740 CPU_CORE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
742 CPU_NOCONA_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 1, 0 },
745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
746 CPU_CORE_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 1, 0 },
749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
750 CPU_CORE2_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
752 CPU_COREI7_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
754 CPU_L1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
756 CPU_K1OM_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
758 CPU_K6_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
760 CPU_K6_2_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
762 CPU_ATHLON_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 1, 0 },
765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
768 CPU_K8_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
770 CPU_AMDFAM10_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
772 CPU_BDVER1_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
774 CPU_BDVER2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
776 CPU_BDVER3_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
778 CPU_BDVER4_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
780 CPU_BTVER1_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
782 CPU_BTVER2_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
784 CPU_8087_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
786 CPU_287_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
788 CPU_387_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
790 CPU_ANY87_FLAGS
, 0, 1 },
791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
792 CPU_MMX_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
794 CPU_3DNOWA_FLAGS
, 0, 1 },
795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
796 CPU_SSE_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
798 CPU_SSE2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
802 CPU_SSSE3_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_1_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
808 CPU_SSE4_2_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
810 CPU_ANY_SSE_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
812 CPU_AVX_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
814 CPU_AVX2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512F_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512CD_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512ER_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
822 CPU_AVX512PF_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
824 CPU_ANY_AVX_FLAGS
, 0, 1 },
825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
826 CPU_VMX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
828 CPU_VMFUNC_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
830 CPU_SMX_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVE_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
834 CPU_XSAVEOPT_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
836 CPU_AES_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
840 CPU_PCLMUL_FLAGS
, 1, 0 },
841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
842 CPU_FSGSBASE_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
844 CPU_RDRND_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
846 CPU_F16C_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
848 CPU_BMI2_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
850 CPU_FMA_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
852 CPU_FMA4_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
854 CPU_XOP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
856 CPU_LWP_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
858 CPU_MOVBE_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
860 CPU_CX16_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
862 CPU_EPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
864 CPU_LZCNT_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
866 CPU_HLE_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
868 CPU_RTM_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
870 CPU_INVPCID_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
872 CPU_CLFLUSH_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
874 CPU_NOP_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
876 CPU_SYSCALL_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
878 CPU_RDTSCP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOW_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
882 CPU_3DNOWA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
884 CPU_PADLOCK_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 1, 0 },
887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
888 CPU_SVME_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
890 CPU_SSE4A_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
892 CPU_ABM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
894 CPU_BMI_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
896 CPU_TBM_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
898 CPU_ADX_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
900 CPU_RDSEED_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
902 CPU_PRFCHW_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
904 CPU_SMAP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
906 CPU_MPX_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
908 CPU_SHA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
910 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVEC_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
914 CPU_XSAVES_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
916 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
918 CPU_SE1_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
920 CPU_AVX512DQ_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
922 CPU_AVX512BW_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
924 CPU_AVX512VL_FLAGS
, 0, 0 },
928 /* Like s_lcomm_internal in gas/read.c but the alignment string
929 is allowed to be optional. */
932 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
939 && *input_line_pointer
== ',')
941 align
= parse_align (needs_align
- 1);
943 if (align
== (addressT
) -1)
958 bss_alloc (symbolP
, size
, align
);
963 pe_lcomm (int needs_align
)
965 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
969 const pseudo_typeS md_pseudo_table
[] =
971 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
972 {"align", s_align_bytes
, 0},
974 {"align", s_align_ptwo
, 0},
976 {"arch", set_cpu_arch
, 0},
980 {"lcomm", pe_lcomm
, 1},
982 {"ffloat", float_cons
, 'f'},
983 {"dfloat", float_cons
, 'd'},
984 {"tfloat", float_cons
, 'x'},
986 {"slong", signed_cons
, 4},
987 {"noopt", s_ignore
, 0},
988 {"optim", s_ignore
, 0},
989 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
990 {"code16", set_code_flag
, CODE_16BIT
},
991 {"code32", set_code_flag
, CODE_32BIT
},
992 {"code64", set_code_flag
, CODE_64BIT
},
993 {"intel_syntax", set_intel_syntax
, 1},
994 {"att_syntax", set_intel_syntax
, 0},
995 {"intel_mnemonic", set_intel_mnemonic
, 1},
996 {"att_mnemonic", set_intel_mnemonic
, 0},
997 {"allow_index_reg", set_allow_index_reg
, 1},
998 {"disallow_index_reg", set_allow_index_reg
, 0},
999 {"sse_check", set_check
, 0},
1000 {"operand_check", set_check
, 1},
1001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1002 {"largecomm", handle_large_common
, 0},
1004 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1005 {"loc", dwarf2_directive_loc
, 0},
1006 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1009 {"secrel32", pe_directive_secrel
, 0},
1014 /* For interface with expression (). */
1015 extern char *input_line_pointer
;
1017 /* Hash table for instruction mnemonic lookup. */
1018 static struct hash_control
*op_hash
;
1020 /* Hash table for register lookup. */
1021 static struct hash_control
*reg_hash
;
1024 i386_align_code (fragS
*fragP
, int count
)
1026 /* Various efficient no-op patterns for aligning code labels.
1027 Note: Don't try to assemble the instructions in the comments.
1028 0L and 0w are not legal. */
1029 static const char f32_1
[] =
1031 static const char f32_2
[] =
1032 {0x66,0x90}; /* xchg %ax,%ax */
1033 static const char f32_3
[] =
1034 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1035 static const char f32_4
[] =
1036 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1037 static const char f32_5
[] =
1039 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1040 static const char f32_6
[] =
1041 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1042 static const char f32_7
[] =
1043 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1044 static const char f32_8
[] =
1046 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1047 static const char f32_9
[] =
1048 {0x89,0xf6, /* movl %esi,%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_10
[] =
1051 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1052 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1053 static const char f32_11
[] =
1054 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1055 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1056 static const char f32_12
[] =
1057 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1058 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1059 static const char f32_13
[] =
1060 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1061 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1062 static const char f32_14
[] =
1063 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f16_3
[] =
1066 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1067 static const char f16_4
[] =
1068 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1069 static const char f16_5
[] =
1071 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1072 static const char f16_6
[] =
1073 {0x89,0xf6, /* mov %si,%si */
1074 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1075 static const char f16_7
[] =
1076 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1077 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1078 static const char f16_8
[] =
1079 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1080 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1081 static const char jump_31
[] =
1082 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1083 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1084 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1085 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1086 static const char *const f32_patt
[] = {
1087 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1088 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1090 static const char *const f16_patt
[] = {
1091 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1093 /* nopl (%[re]ax) */
1094 static const char alt_3
[] =
1096 /* nopl 0(%[re]ax) */
1097 static const char alt_4
[] =
1098 {0x0f,0x1f,0x40,0x00};
1099 /* nopl 0(%[re]ax,%[re]ax,1) */
1100 static const char alt_5
[] =
1101 {0x0f,0x1f,0x44,0x00,0x00};
1102 /* nopw 0(%[re]ax,%[re]ax,1) */
1103 static const char alt_6
[] =
1104 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1105 /* nopl 0L(%[re]ax) */
1106 static const char alt_7
[] =
1107 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1108 /* nopl 0L(%[re]ax,%[re]ax,1) */
1109 static const char alt_8
[] =
1110 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* nopw 0L(%[re]ax,%[re]ax,1) */
1112 static const char alt_9
[] =
1113 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1114 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_10
[] =
1116 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_long_11
[] =
1121 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_12
[] =
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1133 static const char alt_long_13
[] =
1137 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_long_14
[] =
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1154 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1155 static const char alt_long_15
[] =
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1162 /* nopl 0(%[re]ax,%[re]ax,1)
1163 nopw 0(%[re]ax,%[re]ax,1) */
1164 static const char alt_short_11
[] =
1165 {0x0f,0x1f,0x44,0x00,0x00,
1166 0x66,0x0f,0x1f,0x44,0x00,0x00};
1167 /* nopw 0(%[re]ax,%[re]ax,1)
1168 nopw 0(%[re]ax,%[re]ax,1) */
1169 static const char alt_short_12
[] =
1170 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1171 0x66,0x0f,0x1f,0x44,0x00,0x00};
1172 /* nopw 0(%[re]ax,%[re]ax,1)
1174 static const char alt_short_13
[] =
1175 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1176 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1179 static const char alt_short_14
[] =
1180 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1181 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1183 nopl 0L(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_15
[] =
1185 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1186 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1187 static const char *const alt_short_patt
[] = {
1188 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1189 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1190 alt_short_14
, alt_short_15
1192 static const char *const alt_long_patt
[] = {
1193 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1194 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1195 alt_long_14
, alt_long_15
1198 /* Only align for at least a positive non-zero boundary. */
1199 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1202 /* We need to decide which NOP sequence to use for 32bit and
1203 64bit. When -mtune= is used:
1205 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1206 PROCESSOR_GENERIC32, f32_patt will be used.
1207 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1208 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1209 PROCESSOR_GENERIC64, alt_long_patt will be used.
1210 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1211 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1214 When -mtune= isn't used, alt_long_patt will be used if
1215 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1218 When -march= or .arch is used, we can't use anything beyond
1219 cpu_arch_isa_flags. */
1221 if (flag_code
== CODE_16BIT
)
1225 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1227 /* Adjust jump offset. */
1228 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1231 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1232 f16_patt
[count
- 1], count
);
1236 const char *const *patt
= NULL
;
1238 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1240 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1241 switch (cpu_arch_tune
)
1243 case PROCESSOR_UNKNOWN
:
1244 /* We use cpu_arch_isa_flags to check if we SHOULD
1245 optimize with nops. */
1246 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1247 patt
= alt_long_patt
;
1251 case PROCESSOR_PENTIUM4
:
1252 case PROCESSOR_NOCONA
:
1253 case PROCESSOR_CORE
:
1254 case PROCESSOR_CORE2
:
1255 case PROCESSOR_COREI7
:
1256 case PROCESSOR_L1OM
:
1257 case PROCESSOR_K1OM
:
1258 case PROCESSOR_GENERIC64
:
1259 patt
= alt_long_patt
;
1262 case PROCESSOR_ATHLON
:
1264 case PROCESSOR_AMDFAM10
:
1267 patt
= alt_short_patt
;
1269 case PROCESSOR_I386
:
1270 case PROCESSOR_I486
:
1271 case PROCESSOR_PENTIUM
:
1272 case PROCESSOR_PENTIUMPRO
:
1273 case PROCESSOR_GENERIC32
:
1280 switch (fragP
->tc_frag_data
.tune
)
1282 case PROCESSOR_UNKNOWN
:
1283 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1284 PROCESSOR_UNKNOWN. */
1288 case PROCESSOR_I386
:
1289 case PROCESSOR_I486
:
1290 case PROCESSOR_PENTIUM
:
1292 case PROCESSOR_ATHLON
:
1294 case PROCESSOR_AMDFAM10
:
1297 case PROCESSOR_GENERIC32
:
1298 /* We use cpu_arch_isa_flags to check if we CAN optimize
1300 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1301 patt
= alt_short_patt
;
1305 case PROCESSOR_PENTIUMPRO
:
1306 case PROCESSOR_PENTIUM4
:
1307 case PROCESSOR_NOCONA
:
1308 case PROCESSOR_CORE
:
1309 case PROCESSOR_CORE2
:
1310 case PROCESSOR_COREI7
:
1311 case PROCESSOR_L1OM
:
1312 case PROCESSOR_K1OM
:
1313 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1314 patt
= alt_long_patt
;
1318 case PROCESSOR_GENERIC64
:
1319 patt
= alt_long_patt
;
1324 if (patt
== f32_patt
)
1326 /* If the padding is less than 15 bytes, we use the normal
1327 ones. Otherwise, we use a jump instruction and adjust
1331 /* For 64bit, the limit is 3 bytes. */
1332 if (flag_code
== CODE_64BIT
1333 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1338 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1339 patt
[count
- 1], count
);
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1344 /* Adjust jump offset. */
1345 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1350 /* Maximum length of an instruction is 15 byte. If the
1351 padding is greater than 15 bytes and we don't use jump,
1352 we have to break it into smaller pieces. */
1353 int padding
= count
;
1354 while (padding
> 15)
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1362 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1363 patt
[padding
- 1], padding
);
1366 fragP
->fr_var
= count
;
1370 operand_type_all_zero (const union i386_operand_type
*x
)
1372 switch (ARRAY_SIZE(x
->array
))
1381 return !x
->array
[0];
1388 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1390 switch (ARRAY_SIZE(x
->array
))
1405 operand_type_equal (const union i386_operand_type
*x
,
1406 const union i386_operand_type
*y
)
1408 switch (ARRAY_SIZE(x
->array
))
1411 if (x
->array
[2] != y
->array
[2])
1414 if (x
->array
[1] != y
->array
[1])
1417 return x
->array
[0] == y
->array
[0];
1425 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1427 switch (ARRAY_SIZE(x
->array
))
1436 return !x
->array
[0];
1443 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1445 switch (ARRAY_SIZE(x
->array
))
1460 cpu_flags_equal (const union i386_cpu_flags
*x
,
1461 const union i386_cpu_flags
*y
)
1463 switch (ARRAY_SIZE(x
->array
))
1466 if (x
->array
[2] != y
->array
[2])
1469 if (x
->array
[1] != y
->array
[1])
1472 return x
->array
[0] == y
->array
[0];
1480 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1482 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1483 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1486 static INLINE i386_cpu_flags
1487 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1489 switch (ARRAY_SIZE (x
.array
))
1492 x
.array
[2] &= y
.array
[2];
1494 x
.array
[1] &= y
.array
[1];
1496 x
.array
[0] &= y
.array
[0];
1504 static INLINE i386_cpu_flags
1505 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1507 switch (ARRAY_SIZE (x
.array
))
1510 x
.array
[2] |= y
.array
[2];
1512 x
.array
[1] |= y
.array
[1];
1514 x
.array
[0] |= y
.array
[0];
1522 static INLINE i386_cpu_flags
1523 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1525 switch (ARRAY_SIZE (x
.array
))
1528 x
.array
[2] &= ~y
.array
[2];
1530 x
.array
[1] &= ~y
.array
[1];
1532 x
.array
[0] &= ~y
.array
[0];
1540 #define CPU_FLAGS_ARCH_MATCH 0x1
1541 #define CPU_FLAGS_64BIT_MATCH 0x2
1542 #define CPU_FLAGS_AES_MATCH 0x4
1543 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1544 #define CPU_FLAGS_AVX_MATCH 0x10
1546 #define CPU_FLAGS_32BIT_MATCH \
1547 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1548 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1549 #define CPU_FLAGS_PERFECT_MATCH \
1550 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1552 /* Return CPU flags match bits. */
1555 cpu_flags_match (const insn_template
*t
)
1557 i386_cpu_flags x
= t
->cpu_flags
;
1558 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1560 x
.bitfield
.cpu64
= 0;
1561 x
.bitfield
.cpuno64
= 0;
1563 if (cpu_flags_all_zero (&x
))
1565 /* This instruction is available on all archs. */
1566 match
|= CPU_FLAGS_32BIT_MATCH
;
1570 /* This instruction is available only on some archs. */
1571 i386_cpu_flags cpu
= cpu_arch_flags
;
1573 cpu
.bitfield
.cpu64
= 0;
1574 cpu
.bitfield
.cpuno64
= 0;
1575 cpu
= cpu_flags_and (x
, cpu
);
1576 if (!cpu_flags_all_zero (&cpu
))
1578 if (x
.bitfield
.cpuavx
)
1580 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1581 if (cpu
.bitfield
.cpuavx
)
1583 /* Check SSE2AVX. */
1584 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1586 match
|= (CPU_FLAGS_ARCH_MATCH
1587 | CPU_FLAGS_AVX_MATCH
);
1589 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1590 match
|= CPU_FLAGS_AES_MATCH
;
1592 if (!x
.bitfield
.cpupclmul
1593 || cpu
.bitfield
.cpupclmul
)
1594 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1598 match
|= CPU_FLAGS_ARCH_MATCH
;
1601 match
|= CPU_FLAGS_32BIT_MATCH
;
1607 static INLINE i386_operand_type
1608 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1610 switch (ARRAY_SIZE (x
.array
))
1613 x
.array
[2] &= y
.array
[2];
1615 x
.array
[1] &= y
.array
[1];
1617 x
.array
[0] &= y
.array
[0];
1625 static INLINE i386_operand_type
1626 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1628 switch (ARRAY_SIZE (x
.array
))
1631 x
.array
[2] |= y
.array
[2];
1633 x
.array
[1] |= y
.array
[1];
1635 x
.array
[0] |= y
.array
[0];
1643 static INLINE i386_operand_type
1644 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1646 switch (ARRAY_SIZE (x
.array
))
1649 x
.array
[2] ^= y
.array
[2];
1651 x
.array
[1] ^= y
.array
[1];
1653 x
.array
[0] ^= y
.array
[0];
1661 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1662 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1663 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1664 static const i386_operand_type inoutportreg
1665 = OPERAND_TYPE_INOUTPORTREG
;
1666 static const i386_operand_type reg16_inoutportreg
1667 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1668 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1669 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1670 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1671 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1672 static const i386_operand_type anydisp
1673 = OPERAND_TYPE_ANYDISP
;
1674 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1675 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1676 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1677 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1678 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1679 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1680 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1681 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1682 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1683 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1684 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1685 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1686 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1687 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1698 operand_type_check (i386_operand_type t
, enum operand_type c
)
1703 return (t
.bitfield
.reg8
1706 || t
.bitfield
.reg64
);
1709 return (t
.bitfield
.imm8
1713 || t
.bitfield
.imm32s
1714 || t
.bitfield
.imm64
);
1717 return (t
.bitfield
.disp8
1718 || t
.bitfield
.disp16
1719 || t
.bitfield
.disp32
1720 || t
.bitfield
.disp32s
1721 || t
.bitfield
.disp64
);
1724 return (t
.bitfield
.disp8
1725 || t
.bitfield
.disp16
1726 || t
.bitfield
.disp32
1727 || t
.bitfield
.disp32s
1728 || t
.bitfield
.disp64
1729 || t
.bitfield
.baseindex
);
1738 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1739 operand J for instruction template T. */
1742 match_reg_size (const insn_template
*t
, unsigned int j
)
1744 return !((i
.types
[j
].bitfield
.byte
1745 && !t
->operand_types
[j
].bitfield
.byte
)
1746 || (i
.types
[j
].bitfield
.word
1747 && !t
->operand_types
[j
].bitfield
.word
)
1748 || (i
.types
[j
].bitfield
.dword
1749 && !t
->operand_types
[j
].bitfield
.dword
)
1750 || (i
.types
[j
].bitfield
.qword
1751 && !t
->operand_types
[j
].bitfield
.qword
));
1754 /* Return 1 if there is no conflict in any size on operand J for
1755 instruction template T. */
1758 match_mem_size (const insn_template
*t
, unsigned int j
)
1760 return (match_reg_size (t
, j
)
1761 && !((i
.types
[j
].bitfield
.unspecified
1762 && !t
->operand_types
[j
].bitfield
.unspecified
)
1763 || (i
.types
[j
].bitfield
.fword
1764 && !t
->operand_types
[j
].bitfield
.fword
)
1765 || (i
.types
[j
].bitfield
.tbyte
1766 && !t
->operand_types
[j
].bitfield
.tbyte
)
1767 || (i
.types
[j
].bitfield
.xmmword
1768 && !t
->operand_types
[j
].bitfield
.xmmword
)
1769 || (i
.types
[j
].bitfield
.ymmword
1770 && !t
->operand_types
[j
].bitfield
.ymmword
)
1771 || (i
.types
[j
].bitfield
.zmmword
1772 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1775 /* Return 1 if there is no size conflict on any operands for
1776 instruction template T. */
1779 operand_size_match (const insn_template
*t
)
1784 /* Don't check jump instructions. */
1785 if (t
->opcode_modifier
.jump
1786 || t
->opcode_modifier
.jumpbyte
1787 || t
->opcode_modifier
.jumpdword
1788 || t
->opcode_modifier
.jumpintersegment
)
1791 /* Check memory and accumulator operand size. */
1792 for (j
= 0; j
< i
.operands
; j
++)
1794 if (t
->operand_types
[j
].bitfield
.anysize
)
1797 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1803 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1812 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1815 i
.error
= operand_size_mismatch
;
1819 /* Check reverse. */
1820 gas_assert (i
.operands
== 2);
1823 for (j
= 0; j
< 2; j
++)
1825 if (t
->operand_types
[j
].bitfield
.acc
1826 && !match_reg_size (t
, j
? 0 : 1))
1829 if (i
.types
[j
].bitfield
.mem
1830 && !match_mem_size (t
, j
? 0 : 1))
1838 operand_type_match (i386_operand_type overlap
,
1839 i386_operand_type given
)
1841 i386_operand_type temp
= overlap
;
1843 temp
.bitfield
.jumpabsolute
= 0;
1844 temp
.bitfield
.unspecified
= 0;
1845 temp
.bitfield
.byte
= 0;
1846 temp
.bitfield
.word
= 0;
1847 temp
.bitfield
.dword
= 0;
1848 temp
.bitfield
.fword
= 0;
1849 temp
.bitfield
.qword
= 0;
1850 temp
.bitfield
.tbyte
= 0;
1851 temp
.bitfield
.xmmword
= 0;
1852 temp
.bitfield
.ymmword
= 0;
1853 temp
.bitfield
.zmmword
= 0;
1854 if (operand_type_all_zero (&temp
))
1857 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1858 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1862 i
.error
= operand_type_mismatch
;
1866 /* If given types g0 and g1 are registers they must be of the same type
1867 unless the expected operand type register overlap is null.
1868 Note that Acc in a template matches every size of reg. */
1871 operand_type_register_match (i386_operand_type m0
,
1872 i386_operand_type g0
,
1873 i386_operand_type t0
,
1874 i386_operand_type m1
,
1875 i386_operand_type g1
,
1876 i386_operand_type t1
)
1878 if (!operand_type_check (g0
, reg
))
1881 if (!operand_type_check (g1
, reg
))
1884 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1885 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1886 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1887 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1890 if (m0
.bitfield
.acc
)
1892 t0
.bitfield
.reg8
= 1;
1893 t0
.bitfield
.reg16
= 1;
1894 t0
.bitfield
.reg32
= 1;
1895 t0
.bitfield
.reg64
= 1;
1898 if (m1
.bitfield
.acc
)
1900 t1
.bitfield
.reg8
= 1;
1901 t1
.bitfield
.reg16
= 1;
1902 t1
.bitfield
.reg32
= 1;
1903 t1
.bitfield
.reg64
= 1;
1906 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1907 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1908 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1909 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1912 i
.error
= register_type_mismatch
;
1917 static INLINE
unsigned int
1918 register_number (const reg_entry
*r
)
1920 unsigned int nr
= r
->reg_num
;
1922 if (r
->reg_flags
& RegRex
)
1928 static INLINE
unsigned int
1929 mode_from_disp_size (i386_operand_type t
)
1931 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1933 else if (t
.bitfield
.disp16
1934 || t
.bitfield
.disp32
1935 || t
.bitfield
.disp32s
)
1942 fits_in_signed_byte (offsetT num
)
1944 return (num
>= -128) && (num
<= 127);
1948 fits_in_unsigned_byte (offsetT num
)
1950 return (num
& 0xff) == num
;
1954 fits_in_unsigned_word (offsetT num
)
1956 return (num
& 0xffff) == num
;
1960 fits_in_signed_word (offsetT num
)
1962 return (-32768 <= num
) && (num
<= 32767);
1966 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1971 return (!(((offsetT
) -1 << 31) & num
)
1972 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1974 } /* fits_in_signed_long() */
1977 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1982 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1984 } /* fits_in_unsigned_long() */
1987 fits_in_vec_disp8 (offsetT num
)
1989 int shift
= i
.memshift
;
1995 mask
= (1 << shift
) - 1;
1997 /* Return 0 if NUM isn't properly aligned. */
2001 /* Check if NUM will fit in 8bit after shift. */
2002 return fits_in_signed_byte (num
>> shift
);
2006 fits_in_imm4 (offsetT num
)
2008 return (num
& 0xf) == num
;
2011 static i386_operand_type
2012 smallest_imm_type (offsetT num
)
2014 i386_operand_type t
;
2016 operand_type_set (&t
, 0);
2017 t
.bitfield
.imm64
= 1;
2019 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2021 /* This code is disabled on the 486 because all the Imm1 forms
2022 in the opcode table are slower on the i486. They're the
2023 versions with the implicitly specified single-position
2024 displacement, which has another syntax if you really want to
2026 t
.bitfield
.imm1
= 1;
2027 t
.bitfield
.imm8
= 1;
2028 t
.bitfield
.imm8s
= 1;
2029 t
.bitfield
.imm16
= 1;
2030 t
.bitfield
.imm32
= 1;
2031 t
.bitfield
.imm32s
= 1;
2033 else if (fits_in_signed_byte (num
))
2035 t
.bitfield
.imm8
= 1;
2036 t
.bitfield
.imm8s
= 1;
2037 t
.bitfield
.imm16
= 1;
2038 t
.bitfield
.imm32
= 1;
2039 t
.bitfield
.imm32s
= 1;
2041 else if (fits_in_unsigned_byte (num
))
2043 t
.bitfield
.imm8
= 1;
2044 t
.bitfield
.imm16
= 1;
2045 t
.bitfield
.imm32
= 1;
2046 t
.bitfield
.imm32s
= 1;
2048 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2050 t
.bitfield
.imm16
= 1;
2051 t
.bitfield
.imm32
= 1;
2052 t
.bitfield
.imm32s
= 1;
2054 else if (fits_in_signed_long (num
))
2056 t
.bitfield
.imm32
= 1;
2057 t
.bitfield
.imm32s
= 1;
2059 else if (fits_in_unsigned_long (num
))
2060 t
.bitfield
.imm32
= 1;
2066 offset_in_range (offsetT val
, int size
)
2072 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2073 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2074 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2076 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2082 /* If BFD64, sign extend val for 32bit address mode. */
2083 if (flag_code
!= CODE_64BIT
2084 || i
.prefix
[ADDR_PREFIX
])
2085 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2086 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2089 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2091 char buf1
[40], buf2
[40];
2093 sprint_value (buf1
, val
);
2094 sprint_value (buf2
, val
& mask
);
2095 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2109 a. PREFIX_EXIST if attempting to add a prefix where one from the
2110 same class already exists.
2111 b. PREFIX_LOCK if lock prefix is added.
2112 c. PREFIX_REP if rep/repne prefix is added.
2113 d. PREFIX_OTHER if other prefix is added.
2116 static enum PREFIX_GROUP
2117 add_prefix (unsigned int prefix
)
2119 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2122 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2123 && flag_code
== CODE_64BIT
)
2125 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2126 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2127 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2138 case CS_PREFIX_OPCODE
:
2139 case DS_PREFIX_OPCODE
:
2140 case ES_PREFIX_OPCODE
:
2141 case FS_PREFIX_OPCODE
:
2142 case GS_PREFIX_OPCODE
:
2143 case SS_PREFIX_OPCODE
:
2147 case REPNE_PREFIX_OPCODE
:
2148 case REPE_PREFIX_OPCODE
:
2153 case LOCK_PREFIX_OPCODE
:
2162 case ADDR_PREFIX_OPCODE
:
2166 case DATA_PREFIX_OPCODE
:
2170 if (i
.prefix
[q
] != 0)
2178 i
.prefix
[q
] |= prefix
;
2181 as_bad (_("same type of prefix used twice"));
2187 update_code_flag (int value
, int check
)
2189 PRINTF_LIKE ((*as_error
));
2191 flag_code
= (enum flag_code
) value
;
2192 if (flag_code
== CODE_64BIT
)
2194 cpu_arch_flags
.bitfield
.cpu64
= 1;
2195 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2199 cpu_arch_flags
.bitfield
.cpu64
= 0;
2200 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2202 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2205 as_error
= as_fatal
;
2208 (*as_error
) (_("64bit mode not supported on `%s'."),
2209 cpu_arch_name
? cpu_arch_name
: default_arch
);
2211 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2214 as_error
= as_fatal
;
2217 (*as_error
) (_("32bit mode not supported on `%s'."),
2218 cpu_arch_name
? cpu_arch_name
: default_arch
);
2220 stackop_size
= '\0';
2224 set_code_flag (int value
)
2226 update_code_flag (value
, 0);
2230 set_16bit_gcc_code_flag (int new_code_flag
)
2232 flag_code
= (enum flag_code
) new_code_flag
;
2233 if (flag_code
!= CODE_16BIT
)
2235 cpu_arch_flags
.bitfield
.cpu64
= 0;
2236 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2237 stackop_size
= LONG_MNEM_SUFFIX
;
2241 set_intel_syntax (int syntax_flag
)
2243 /* Find out if register prefixing is specified. */
2244 int ask_naked_reg
= 0;
2247 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2249 char *string
= input_line_pointer
;
2250 int e
= get_symbol_end ();
2252 if (strcmp (string
, "prefix") == 0)
2254 else if (strcmp (string
, "noprefix") == 0)
2257 as_bad (_("bad argument to syntax directive."));
2258 *input_line_pointer
= e
;
2260 demand_empty_rest_of_line ();
2262 intel_syntax
= syntax_flag
;
2264 if (ask_naked_reg
== 0)
2265 allow_naked_reg
= (intel_syntax
2266 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2268 allow_naked_reg
= (ask_naked_reg
< 0);
2270 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2272 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2273 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2274 register_prefix
= allow_naked_reg
? "" : "%";
2278 set_intel_mnemonic (int mnemonic_flag
)
2280 intel_mnemonic
= mnemonic_flag
;
2284 set_allow_index_reg (int flag
)
2286 allow_index_reg
= flag
;
2290 set_check (int what
)
2292 enum check_kind
*kind
;
2297 kind
= &operand_check
;
2308 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2310 char *string
= input_line_pointer
;
2311 int e
= get_symbol_end ();
2313 if (strcmp (string
, "none") == 0)
2315 else if (strcmp (string
, "warning") == 0)
2316 *kind
= check_warning
;
2317 else if (strcmp (string
, "error") == 0)
2318 *kind
= check_error
;
2320 as_bad (_("bad argument to %s_check directive."), str
);
2321 *input_line_pointer
= e
;
2324 as_bad (_("missing argument for %s_check directive"), str
);
2326 demand_empty_rest_of_line ();
2330 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2331 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2333 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2334 static const char *arch
;
2336 /* Intel LIOM is only supported on ELF. */
2342 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2343 use default_arch. */
2344 arch
= cpu_arch_name
;
2346 arch
= default_arch
;
2349 /* If we are targeting Intel L1OM, we must enable it. */
2350 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2351 || new_flag
.bitfield
.cpul1om
)
2354 /* If we are targeting Intel K1OM, we must enable it. */
2355 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2356 || new_flag
.bitfield
.cpuk1om
)
2359 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2364 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2368 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2370 char *string
= input_line_pointer
;
2371 int e
= get_symbol_end ();
2373 i386_cpu_flags flags
;
2375 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2377 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2379 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2383 cpu_arch_name
= cpu_arch
[j
].name
;
2384 cpu_sub_arch_name
= NULL
;
2385 cpu_arch_flags
= cpu_arch
[j
].flags
;
2386 if (flag_code
== CODE_64BIT
)
2388 cpu_arch_flags
.bitfield
.cpu64
= 1;
2389 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2393 cpu_arch_flags
.bitfield
.cpu64
= 0;
2394 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2396 cpu_arch_isa
= cpu_arch
[j
].type
;
2397 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2398 if (!cpu_arch_tune_set
)
2400 cpu_arch_tune
= cpu_arch_isa
;
2401 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2406 if (!cpu_arch
[j
].negated
)
2407 flags
= cpu_flags_or (cpu_arch_flags
,
2410 flags
= cpu_flags_and_not (cpu_arch_flags
,
2412 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2414 if (cpu_sub_arch_name
)
2416 char *name
= cpu_sub_arch_name
;
2417 cpu_sub_arch_name
= concat (name
,
2419 (const char *) NULL
);
2423 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2424 cpu_arch_flags
= flags
;
2425 cpu_arch_isa_flags
= flags
;
2427 *input_line_pointer
= e
;
2428 demand_empty_rest_of_line ();
2432 if (j
>= ARRAY_SIZE (cpu_arch
))
2433 as_bad (_("no such architecture: `%s'"), string
);
2435 *input_line_pointer
= e
;
2438 as_bad (_("missing cpu architecture"));
2440 no_cond_jump_promotion
= 0;
2441 if (*input_line_pointer
== ','
2442 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2444 char *string
= ++input_line_pointer
;
2445 int e
= get_symbol_end ();
2447 if (strcmp (string
, "nojumps") == 0)
2448 no_cond_jump_promotion
= 1;
2449 else if (strcmp (string
, "jumps") == 0)
2452 as_bad (_("no such architecture modifier: `%s'"), string
);
2454 *input_line_pointer
= e
;
2457 demand_empty_rest_of_line ();
2460 enum bfd_architecture
2463 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2465 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2466 || flag_code
!= CODE_64BIT
)
2467 as_fatal (_("Intel L1OM is 64bit ELF only"));
2468 return bfd_arch_l1om
;
2470 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2472 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2473 || flag_code
!= CODE_64BIT
)
2474 as_fatal (_("Intel K1OM is 64bit ELF only"));
2475 return bfd_arch_k1om
;
2478 return bfd_arch_i386
;
2484 if (!strncmp (default_arch
, "x86_64", 6))
2486 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2488 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2489 || default_arch
[6] != '\0')
2490 as_fatal (_("Intel L1OM is 64bit ELF only"));
2491 return bfd_mach_l1om
;
2493 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2495 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2496 || default_arch
[6] != '\0')
2497 as_fatal (_("Intel K1OM is 64bit ELF only"));
2498 return bfd_mach_k1om
;
2500 else if (default_arch
[6] == '\0')
2501 return bfd_mach_x86_64
;
2503 return bfd_mach_x64_32
;
2505 else if (!strcmp (default_arch
, "i386"))
2506 return bfd_mach_i386_i386
;
2508 as_fatal (_("unknown architecture"));
2514 const char *hash_err
;
2516 /* Initialize op_hash hash table. */
2517 op_hash
= hash_new ();
2520 const insn_template
*optab
;
2521 templates
*core_optab
;
2523 /* Setup for loop. */
2525 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2526 core_optab
->start
= optab
;
2531 if (optab
->name
== NULL
2532 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2534 /* different name --> ship out current template list;
2535 add to hash table; & begin anew. */
2536 core_optab
->end
= optab
;
2537 hash_err
= hash_insert (op_hash
,
2539 (void *) core_optab
);
2542 as_fatal (_("can't hash %s: %s"),
2546 if (optab
->name
== NULL
)
2548 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2549 core_optab
->start
= optab
;
2554 /* Initialize reg_hash hash table. */
2555 reg_hash
= hash_new ();
2557 const reg_entry
*regtab
;
2558 unsigned int regtab_size
= i386_regtab_size
;
2560 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2562 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2564 as_fatal (_("can't hash %s: %s"),
2570 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2575 for (c
= 0; c
< 256; c
++)
2580 mnemonic_chars
[c
] = c
;
2581 register_chars
[c
] = c
;
2582 operand_chars
[c
] = c
;
2584 else if (ISLOWER (c
))
2586 mnemonic_chars
[c
] = c
;
2587 register_chars
[c
] = c
;
2588 operand_chars
[c
] = c
;
2590 else if (ISUPPER (c
))
2592 mnemonic_chars
[c
] = TOLOWER (c
);
2593 register_chars
[c
] = mnemonic_chars
[c
];
2594 operand_chars
[c
] = c
;
2596 else if (c
== '{' || c
== '}')
2597 operand_chars
[c
] = c
;
2599 if (ISALPHA (c
) || ISDIGIT (c
))
2600 identifier_chars
[c
] = c
;
2603 identifier_chars
[c
] = c
;
2604 operand_chars
[c
] = c
;
2609 identifier_chars
['@'] = '@';
2612 identifier_chars
['?'] = '?';
2613 operand_chars
['?'] = '?';
2615 digit_chars
['-'] = '-';
2616 mnemonic_chars
['_'] = '_';
2617 mnemonic_chars
['-'] = '-';
2618 mnemonic_chars
['.'] = '.';
2619 identifier_chars
['_'] = '_';
2620 identifier_chars
['.'] = '.';
2622 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2623 operand_chars
[(unsigned char) *p
] = *p
;
2626 if (flag_code
== CODE_64BIT
)
2628 #if defined (OBJ_COFF) && defined (TE_PE)
2629 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2632 x86_dwarf2_return_column
= 16;
2634 x86_cie_data_alignment
= -8;
2638 x86_dwarf2_return_column
= 8;
2639 x86_cie_data_alignment
= -4;
2644 i386_print_statistics (FILE *file
)
2646 hash_print_statistics (file
, "i386 opcode", op_hash
);
2647 hash_print_statistics (file
, "i386 register", reg_hash
);
2652 /* Debugging routines for md_assemble. */
2653 static void pte (insn_template
*);
2654 static void pt (i386_operand_type
);
2655 static void pe (expressionS
*);
2656 static void ps (symbolS
*);
2659 pi (char *line
, i386_insn
*x
)
2663 fprintf (stdout
, "%s: template ", line
);
2665 fprintf (stdout
, " address: base %s index %s scale %x\n",
2666 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2667 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2668 x
->log2_scale_factor
);
2669 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2670 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2671 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2672 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2673 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2674 (x
->rex
& REX_W
) != 0,
2675 (x
->rex
& REX_R
) != 0,
2676 (x
->rex
& REX_X
) != 0,
2677 (x
->rex
& REX_B
) != 0);
2678 for (j
= 0; j
< x
->operands
; j
++)
2680 fprintf (stdout
, " #%d: ", j
+ 1);
2682 fprintf (stdout
, "\n");
2683 if (x
->types
[j
].bitfield
.reg8
2684 || x
->types
[j
].bitfield
.reg16
2685 || x
->types
[j
].bitfield
.reg32
2686 || x
->types
[j
].bitfield
.reg64
2687 || x
->types
[j
].bitfield
.regmmx
2688 || x
->types
[j
].bitfield
.regxmm
2689 || x
->types
[j
].bitfield
.regymm
2690 || x
->types
[j
].bitfield
.regzmm
2691 || x
->types
[j
].bitfield
.sreg2
2692 || x
->types
[j
].bitfield
.sreg3
2693 || x
->types
[j
].bitfield
.control
2694 || x
->types
[j
].bitfield
.debug
2695 || x
->types
[j
].bitfield
.test
)
2696 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2697 if (operand_type_check (x
->types
[j
], imm
))
2699 if (operand_type_check (x
->types
[j
], disp
))
2700 pe (x
->op
[j
].disps
);
2705 pte (insn_template
*t
)
2708 fprintf (stdout
, " %d operands ", t
->operands
);
2709 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2710 if (t
->extension_opcode
!= None
)
2711 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2712 if (t
->opcode_modifier
.d
)
2713 fprintf (stdout
, "D");
2714 if (t
->opcode_modifier
.w
)
2715 fprintf (stdout
, "W");
2716 fprintf (stdout
, "\n");
2717 for (j
= 0; j
< t
->operands
; j
++)
2719 fprintf (stdout
, " #%d type ", j
+ 1);
2720 pt (t
->operand_types
[j
]);
2721 fprintf (stdout
, "\n");
2728 fprintf (stdout
, " operation %d\n", e
->X_op
);
2729 fprintf (stdout
, " add_number %ld (%lx)\n",
2730 (long) e
->X_add_number
, (long) e
->X_add_number
);
2731 if (e
->X_add_symbol
)
2733 fprintf (stdout
, " add_symbol ");
2734 ps (e
->X_add_symbol
);
2735 fprintf (stdout
, "\n");
2739 fprintf (stdout
, " op_symbol ");
2740 ps (e
->X_op_symbol
);
2741 fprintf (stdout
, "\n");
2748 fprintf (stdout
, "%s type %s%s",
2750 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2751 segment_name (S_GET_SEGMENT (s
)));
2754 static struct type_name
2756 i386_operand_type mask
;
2759 const type_names
[] =
2761 { OPERAND_TYPE_REG8
, "r8" },
2762 { OPERAND_TYPE_REG16
, "r16" },
2763 { OPERAND_TYPE_REG32
, "r32" },
2764 { OPERAND_TYPE_REG64
, "r64" },
2765 { OPERAND_TYPE_IMM8
, "i8" },
2766 { OPERAND_TYPE_IMM8
, "i8s" },
2767 { OPERAND_TYPE_IMM16
, "i16" },
2768 { OPERAND_TYPE_IMM32
, "i32" },
2769 { OPERAND_TYPE_IMM32S
, "i32s" },
2770 { OPERAND_TYPE_IMM64
, "i64" },
2771 { OPERAND_TYPE_IMM1
, "i1" },
2772 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2773 { OPERAND_TYPE_DISP8
, "d8" },
2774 { OPERAND_TYPE_DISP16
, "d16" },
2775 { OPERAND_TYPE_DISP32
, "d32" },
2776 { OPERAND_TYPE_DISP32S
, "d32s" },
2777 { OPERAND_TYPE_DISP64
, "d64" },
2778 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2779 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2780 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2781 { OPERAND_TYPE_CONTROL
, "control reg" },
2782 { OPERAND_TYPE_TEST
, "test reg" },
2783 { OPERAND_TYPE_DEBUG
, "debug reg" },
2784 { OPERAND_TYPE_FLOATREG
, "FReg" },
2785 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2786 { OPERAND_TYPE_SREG2
, "SReg2" },
2787 { OPERAND_TYPE_SREG3
, "SReg3" },
2788 { OPERAND_TYPE_ACC
, "Acc" },
2789 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2790 { OPERAND_TYPE_REGMMX
, "rMMX" },
2791 { OPERAND_TYPE_REGXMM
, "rXMM" },
2792 { OPERAND_TYPE_REGYMM
, "rYMM" },
2793 { OPERAND_TYPE_REGZMM
, "rZMM" },
2794 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2795 { OPERAND_TYPE_ESSEG
, "es" },
2799 pt (i386_operand_type t
)
2802 i386_operand_type a
;
2804 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2806 a
= operand_type_and (t
, type_names
[j
].mask
);
2807 if (!operand_type_all_zero (&a
))
2808 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2813 #endif /* DEBUG386 */
2815 static bfd_reloc_code_real_type
2816 reloc (unsigned int size
,
2820 bfd_reloc_code_real_type other
)
2822 if (other
!= NO_RELOC
)
2824 reloc_howto_type
*rel
;
2829 case BFD_RELOC_X86_64_GOT32
:
2830 return BFD_RELOC_X86_64_GOT64
;
2832 case BFD_RELOC_X86_64_PLTOFF64
:
2833 return BFD_RELOC_X86_64_PLTOFF64
;
2835 case BFD_RELOC_X86_64_GOTPC32
:
2836 other
= BFD_RELOC_X86_64_GOTPC64
;
2838 case BFD_RELOC_X86_64_GOTPCREL
:
2839 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2841 case BFD_RELOC_X86_64_TPOFF32
:
2842 other
= BFD_RELOC_X86_64_TPOFF64
;
2844 case BFD_RELOC_X86_64_DTPOFF32
:
2845 other
= BFD_RELOC_X86_64_DTPOFF64
;
2851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2852 if (other
== BFD_RELOC_SIZE32
)
2855 other
= BFD_RELOC_SIZE64
;
2858 as_bad (_("there are no pc-relative size relocations"));
2864 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2865 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2868 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2870 as_bad (_("unknown relocation (%u)"), other
);
2871 else if (size
!= bfd_get_reloc_size (rel
))
2872 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2873 bfd_get_reloc_size (rel
),
2875 else if (pcrel
&& !rel
->pc_relative
)
2876 as_bad (_("non-pc-relative relocation for pc-relative field"));
2877 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2879 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2881 as_bad (_("relocated field and relocation type differ in signedness"));
2890 as_bad (_("there are no unsigned pc-relative relocations"));
2893 case 1: return BFD_RELOC_8_PCREL
;
2894 case 2: return BFD_RELOC_16_PCREL
;
2895 case 4: return (bnd_prefix
&& object_64bit
2896 ? BFD_RELOC_X86_64_PC32_BND
2897 : BFD_RELOC_32_PCREL
);
2898 case 8: return BFD_RELOC_64_PCREL
;
2900 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2907 case 4: return BFD_RELOC_X86_64_32S
;
2912 case 1: return BFD_RELOC_8
;
2913 case 2: return BFD_RELOC_16
;
2914 case 4: return BFD_RELOC_32
;
2915 case 8: return BFD_RELOC_64
;
2917 as_bad (_("cannot do %s %u byte relocation"),
2918 sign
> 0 ? "signed" : "unsigned", size
);
2924 /* Here we decide which fixups can be adjusted to make them relative to
2925 the beginning of the section instead of the symbol. Basically we need
2926 to make sure that the dynamic relocations are done correctly, so in
2927 some cases we force the original symbol to be used. */
2930 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2936 /* Don't adjust pc-relative references to merge sections in 64-bit
2938 if (use_rela_relocations
2939 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2943 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2944 and changed later by validate_fix. */
2945 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2946 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2949 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2950 for size relocations. */
2951 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2952 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2953 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2954 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2955 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2956 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2957 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2958 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2959 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2960 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2961 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2962 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2963 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2964 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2965 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2968 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2969 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2970 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2971 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2972 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2973 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2974 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2975 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2976 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2977 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2978 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2979 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2980 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2987 intel_float_operand (const char *mnemonic
)
2989 /* Note that the value returned is meaningful only for opcodes with (memory)
2990 operands, hence the code here is free to improperly handle opcodes that
2991 have no operands (for better performance and smaller code). */
2993 if (mnemonic
[0] != 'f')
2994 return 0; /* non-math */
2996 switch (mnemonic
[1])
2998 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2999 the fs segment override prefix not currently handled because no
3000 call path can make opcodes without operands get here */
3002 return 2 /* integer op */;
3004 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3005 return 3; /* fldcw/fldenv */
3008 if (mnemonic
[2] != 'o' /* fnop */)
3009 return 3; /* non-waiting control op */
3012 if (mnemonic
[2] == 's')
3013 return 3; /* frstor/frstpm */
3016 if (mnemonic
[2] == 'a')
3017 return 3; /* fsave */
3018 if (mnemonic
[2] == 't')
3020 switch (mnemonic
[3])
3022 case 'c': /* fstcw */
3023 case 'd': /* fstdw */
3024 case 'e': /* fstenv */
3025 case 's': /* fsts[gw] */
3031 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3032 return 0; /* fxsave/fxrstor are not really math ops */
3039 /* Build the VEX prefix. */
3042 build_vex_prefix (const insn_template
*t
)
3044 unsigned int register_specifier
;
3045 unsigned int implied_prefix
;
3046 unsigned int vector_length
;
3048 /* Check register specifier. */
3049 if (i
.vex
.register_specifier
)
3051 register_specifier
=
3052 ~register_number (i
.vex
.register_specifier
) & 0xf;
3053 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3056 register_specifier
= 0xf;
3058 /* Use 2-byte VEX prefix by swappping destination and source
3061 && i
.operands
== i
.reg_operands
3062 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3063 && i
.tm
.opcode_modifier
.s
3066 unsigned int xchg
= i
.operands
- 1;
3067 union i386_op temp_op
;
3068 i386_operand_type temp_type
;
3070 temp_type
= i
.types
[xchg
];
3071 i
.types
[xchg
] = i
.types
[0];
3072 i
.types
[0] = temp_type
;
3073 temp_op
= i
.op
[xchg
];
3074 i
.op
[xchg
] = i
.op
[0];
3077 gas_assert (i
.rm
.mode
== 3);
3081 i
.rm
.regmem
= i
.rm
.reg
;
3084 /* Use the next insn. */
3088 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3089 vector_length
= avxscalar
;
3091 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3093 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3098 case DATA_PREFIX_OPCODE
:
3101 case REPE_PREFIX_OPCODE
:
3104 case REPNE_PREFIX_OPCODE
:
3111 /* Use 2-byte VEX prefix if possible. */
3112 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3113 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3114 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3116 /* 2-byte VEX prefix. */
3120 i
.vex
.bytes
[0] = 0xc5;
3122 /* Check the REX.R bit. */
3123 r
= (i
.rex
& REX_R
) ? 0 : 1;
3124 i
.vex
.bytes
[1] = (r
<< 7
3125 | register_specifier
<< 3
3126 | vector_length
<< 2
3131 /* 3-byte VEX prefix. */
3136 switch (i
.tm
.opcode_modifier
.vexopcode
)
3140 i
.vex
.bytes
[0] = 0xc4;
3144 i
.vex
.bytes
[0] = 0xc4;
3148 i
.vex
.bytes
[0] = 0xc4;
3152 i
.vex
.bytes
[0] = 0x8f;
3156 i
.vex
.bytes
[0] = 0x8f;
3160 i
.vex
.bytes
[0] = 0x8f;
3166 /* The high 3 bits of the second VEX byte are 1's compliment
3167 of RXB bits from REX. */
3168 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3170 /* Check the REX.W bit. */
3171 w
= (i
.rex
& REX_W
) ? 1 : 0;
3172 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3175 i
.vex
.bytes
[2] = (w
<< 7
3176 | register_specifier
<< 3
3177 | vector_length
<< 2
3182 /* Build the EVEX prefix. */
3185 build_evex_prefix (void)
3187 unsigned int register_specifier
;
3188 unsigned int implied_prefix
;
3190 rex_byte vrex_used
= 0;
3192 /* Check register specifier. */
3193 if (i
.vex
.register_specifier
)
3195 gas_assert ((i
.vrex
& REX_X
) == 0);
3197 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3198 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3199 register_specifier
+= 8;
3200 /* The upper 16 registers are encoded in the fourth byte of the
3202 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3203 i
.vex
.bytes
[3] = 0x8;
3204 register_specifier
= ~register_specifier
& 0xf;
3208 register_specifier
= 0xf;
3210 /* Encode upper 16 vector index register in the fourth byte of
3212 if (!(i
.vrex
& REX_X
))
3213 i
.vex
.bytes
[3] = 0x8;
3218 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3223 case DATA_PREFIX_OPCODE
:
3226 case REPE_PREFIX_OPCODE
:
3229 case REPNE_PREFIX_OPCODE
:
3236 /* 4 byte EVEX prefix. */
3238 i
.vex
.bytes
[0] = 0x62;
3241 switch (i
.tm
.opcode_modifier
.vexopcode
)
3257 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3259 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3261 /* The fifth bit of the second EVEX byte is 1's compliment of the
3262 REX_R bit in VREX. */
3263 if (!(i
.vrex
& REX_R
))
3264 i
.vex
.bytes
[1] |= 0x10;
3268 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3270 /* When all operands are registers, the REX_X bit in REX is not
3271 used. We reuse it to encode the upper 16 registers, which is
3272 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3273 as 1's compliment. */
3274 if ((i
.vrex
& REX_B
))
3277 i
.vex
.bytes
[1] &= ~0x40;
3281 /* EVEX instructions shouldn't need the REX prefix. */
3282 i
.vrex
&= ~vrex_used
;
3283 gas_assert (i
.vrex
== 0);
3285 /* Check the REX.W bit. */
3286 w
= (i
.rex
& REX_W
) ? 1 : 0;
3287 if (i
.tm
.opcode_modifier
.vexw
)
3289 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3292 /* If w is not set it means we are dealing with WIG instruction. */
3295 if (evexwig
== evexw1
)
3299 /* Encode the U bit. */
3300 implied_prefix
|= 0x4;
3302 /* The third byte of the EVEX prefix. */
3303 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3305 /* The fourth byte of the EVEX prefix. */
3306 /* The zeroing-masking bit. */
3307 if (i
.mask
&& i
.mask
->zeroing
)
3308 i
.vex
.bytes
[3] |= 0x80;
3310 /* Don't always set the broadcast bit if there is no RC. */
3313 /* Encode the vector length. */
3314 unsigned int vec_length
;
3316 switch (i
.tm
.opcode_modifier
.evex
)
3318 case EVEXLIG
: /* LL' is ignored */
3319 vec_length
= evexlig
<< 5;
3322 vec_length
= 0 << 5;
3325 vec_length
= 1 << 5;
3328 vec_length
= 2 << 5;
3334 i
.vex
.bytes
[3] |= vec_length
;
3335 /* Encode the broadcast bit. */
3337 i
.vex
.bytes
[3] |= 0x10;
3341 if (i
.rounding
->type
!= saeonly
)
3342 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3344 i
.vex
.bytes
[3] |= 0x10;
3347 if (i
.mask
&& i
.mask
->mask
)
3348 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3352 process_immext (void)
3356 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3359 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3360 with an opcode suffix which is coded in the same place as an
3361 8-bit immediate field would be.
3362 Here we check those operands and remove them afterwards. */
3365 for (x
= 0; x
< i
.operands
; x
++)
3366 if (register_number (i
.op
[x
].regs
) != x
)
3367 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3368 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3374 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3375 which is coded in the same place as an 8-bit immediate field
3376 would be. Here we fake an 8-bit immediate operand from the
3377 opcode suffix stored in tm.extension_opcode.
3379 AVX instructions also use this encoding, for some of
3380 3 argument instructions. */
3382 gas_assert (i
.imm_operands
<= 1
3384 || ((i
.tm
.opcode_modifier
.vex
3385 || i
.tm
.opcode_modifier
.evex
)
3386 && i
.operands
<= 4)));
3388 exp
= &im_expressions
[i
.imm_operands
++];
3389 i
.op
[i
.operands
].imms
= exp
;
3390 i
.types
[i
.operands
] = imm8
;
3392 exp
->X_op
= O_constant
;
3393 exp
->X_add_number
= i
.tm
.extension_opcode
;
3394 i
.tm
.extension_opcode
= None
;
3401 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3406 as_bad (_("invalid instruction `%s' after `%s'"),
3407 i
.tm
.name
, i
.hle_prefix
);
3410 if (i
.prefix
[LOCK_PREFIX
])
3412 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3416 case HLEPrefixRelease
:
3417 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3419 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3423 if (i
.mem_operands
== 0
3424 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3426 as_bad (_("memory destination needed for instruction `%s'"
3427 " after `xrelease'"), i
.tm
.name
);
3434 /* This is the guts of the machine-dependent assembler. LINE points to a
3435 machine dependent instruction. This function is supposed to emit
3436 the frags/bytes it assembles to. */
3439 md_assemble (char *line
)
3442 char mnemonic
[MAX_MNEM_SIZE
];
3443 const insn_template
*t
;
3445 /* Initialize globals. */
3446 memset (&i
, '\0', sizeof (i
));
3447 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3448 i
.reloc
[j
] = NO_RELOC
;
3449 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3450 memset (im_expressions
, '\0', sizeof (im_expressions
));
3451 save_stack_p
= save_stack
;
3453 /* First parse an instruction mnemonic & call i386_operand for the operands.
3454 We assume that the scrubber has arranged it so that line[0] is the valid
3455 start of a (possibly prefixed) mnemonic. */
3457 line
= parse_insn (line
, mnemonic
);
3461 line
= parse_operands (line
, mnemonic
);
3466 /* Now we've parsed the mnemonic into a set of templates, and have the
3467 operands at hand. */
3469 /* All intel opcodes have reversed operands except for "bound" and
3470 "enter". We also don't reverse intersegment "jmp" and "call"
3471 instructions with 2 immediate operands so that the immediate segment
3472 precedes the offset, as it does when in AT&T mode. */
3475 && (strcmp (mnemonic
, "bound") != 0)
3476 && (strcmp (mnemonic
, "invlpga") != 0)
3477 && !(operand_type_check (i
.types
[0], imm
)
3478 && operand_type_check (i
.types
[1], imm
)))
3481 /* The order of the immediates should be reversed
3482 for 2 immediates extrq and insertq instructions */
3483 if (i
.imm_operands
== 2
3484 && (strcmp (mnemonic
, "extrq") == 0
3485 || strcmp (mnemonic
, "insertq") == 0))
3486 swap_2_operands (0, 1);
3491 /* Don't optimize displacement for movabs since it only takes 64bit
3494 && i
.disp_encoding
!= disp_encoding_32bit
3495 && (flag_code
!= CODE_64BIT
3496 || strcmp (mnemonic
, "movabs") != 0))
3499 /* Next, we find a template that matches the given insn,
3500 making sure the overlap of the given operands types is consistent
3501 with the template operand types. */
3503 if (!(t
= match_template ()))
3506 if (sse_check
!= check_none
3507 && !i
.tm
.opcode_modifier
.noavx
3508 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3509 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3510 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3511 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3512 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3513 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3515 (sse_check
== check_warning
3517 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3520 /* Zap movzx and movsx suffix. The suffix has been set from
3521 "word ptr" or "byte ptr" on the source operand in Intel syntax
3522 or extracted from mnemonic in AT&T syntax. But we'll use
3523 the destination register to choose the suffix for encoding. */
3524 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3526 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3527 there is no suffix, the default will be byte extension. */
3528 if (i
.reg_operands
!= 2
3531 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3536 if (i
.tm
.opcode_modifier
.fwait
)
3537 if (!add_prefix (FWAIT_OPCODE
))
3540 /* Check if REP prefix is OK. */
3541 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3543 as_bad (_("invalid instruction `%s' after `%s'"),
3544 i
.tm
.name
, i
.rep_prefix
);
3548 /* Check for lock without a lockable instruction. Destination operand
3549 must be memory unless it is xchg (0x86). */
3550 if (i
.prefix
[LOCK_PREFIX
]
3551 && (!i
.tm
.opcode_modifier
.islockable
3552 || i
.mem_operands
== 0
3553 || (i
.tm
.base_opcode
!= 0x86
3554 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3556 as_bad (_("expecting lockable instruction after `lock'"));
3560 /* Check if HLE prefix is OK. */
3561 if (i
.hle_prefix
&& !check_hle ())
3564 /* Check BND prefix. */
3565 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3566 as_bad (_("expecting valid branch instruction after `bnd'"));
3568 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3569 && flag_code
== CODE_64BIT
3570 && i
.prefix
[ADDR_PREFIX
])
3571 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3573 /* Insert BND prefix. */
3575 && i
.tm
.opcode_modifier
.bndprefixok
3576 && !i
.prefix
[BND_PREFIX
])
3577 add_prefix (BND_PREFIX_OPCODE
);
3579 /* Check string instruction segment overrides. */
3580 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3582 if (!check_string ())
3584 i
.disp_operands
= 0;
3587 if (!process_suffix ())
3590 /* Update operand types. */
3591 for (j
= 0; j
< i
.operands
; j
++)
3592 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3594 /* Make still unresolved immediate matches conform to size of immediate
3595 given in i.suffix. */
3596 if (!finalize_imm ())
3599 if (i
.types
[0].bitfield
.imm1
)
3600 i
.imm_operands
= 0; /* kludge for shift insns. */
3602 /* We only need to check those implicit registers for instructions
3603 with 3 operands or less. */
3604 if (i
.operands
<= 3)
3605 for (j
= 0; j
< i
.operands
; j
++)
3606 if (i
.types
[j
].bitfield
.inoutportreg
3607 || i
.types
[j
].bitfield
.shiftcount
3608 || i
.types
[j
].bitfield
.acc
3609 || i
.types
[j
].bitfield
.floatacc
)
3612 /* ImmExt should be processed after SSE2AVX. */
3613 if (!i
.tm
.opcode_modifier
.sse2avx
3614 && i
.tm
.opcode_modifier
.immext
)
3617 /* For insns with operands there are more diddles to do to the opcode. */
3620 if (!process_operands ())
3623 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3625 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3626 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3629 if (i
.tm
.opcode_modifier
.vex
)
3630 build_vex_prefix (t
);
3632 if (i
.tm
.opcode_modifier
.evex
)
3633 build_evex_prefix ();
3635 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3636 instructions may define INT_OPCODE as well, so avoid this corner
3637 case for those instructions that use MODRM. */
3638 if (i
.tm
.base_opcode
== INT_OPCODE
3639 && !i
.tm
.opcode_modifier
.modrm
3640 && i
.op
[0].imms
->X_add_number
== 3)
3642 i
.tm
.base_opcode
= INT3_OPCODE
;
3646 if ((i
.tm
.opcode_modifier
.jump
3647 || i
.tm
.opcode_modifier
.jumpbyte
3648 || i
.tm
.opcode_modifier
.jumpdword
)
3649 && i
.op
[0].disps
->X_op
== O_constant
)
3651 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3652 the absolute address given by the constant. Since ix86 jumps and
3653 calls are pc relative, we need to generate a reloc. */
3654 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3655 i
.op
[0].disps
->X_op
= O_symbol
;
3658 if (i
.tm
.opcode_modifier
.rex64
)
3661 /* For 8 bit registers we need an empty rex prefix. Also if the
3662 instruction already has a prefix, we need to convert old
3663 registers to new ones. */
3665 if ((i
.types
[0].bitfield
.reg8
3666 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3667 || (i
.types
[1].bitfield
.reg8
3668 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3669 || ((i
.types
[0].bitfield
.reg8
3670 || i
.types
[1].bitfield
.reg8
)
3675 i
.rex
|= REX_OPCODE
;
3676 for (x
= 0; x
< 2; x
++)
3678 /* Look for 8 bit operand that uses old registers. */
3679 if (i
.types
[x
].bitfield
.reg8
3680 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3682 /* In case it is "hi" register, give up. */
3683 if (i
.op
[x
].regs
->reg_num
> 3)
3684 as_bad (_("can't encode register '%s%s' in an "
3685 "instruction requiring REX prefix."),
3686 register_prefix
, i
.op
[x
].regs
->reg_name
);
3688 /* Otherwise it is equivalent to the extended register.
3689 Since the encoding doesn't change this is merely
3690 cosmetic cleanup for debug output. */
3692 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3698 add_prefix (REX_OPCODE
| i
.rex
);
3700 /* We are ready to output the insn. */
3705 parse_insn (char *line
, char *mnemonic
)
3708 char *token_start
= l
;
3711 const insn_template
*t
;
3717 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3722 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3724 as_bad (_("no such instruction: `%s'"), token_start
);
3729 if (!is_space_char (*l
)
3730 && *l
!= END_OF_INSN
3732 || (*l
!= PREFIX_SEPARATOR
3735 as_bad (_("invalid character %s in mnemonic"),
3736 output_invalid (*l
));
3739 if (token_start
== l
)
3741 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3742 as_bad (_("expecting prefix; got nothing"));
3744 as_bad (_("expecting mnemonic; got nothing"));
3748 /* Look up instruction (or prefix) via hash table. */
3749 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3751 if (*l
!= END_OF_INSN
3752 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3753 && current_templates
3754 && current_templates
->start
->opcode_modifier
.isprefix
)
3756 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3758 as_bad ((flag_code
!= CODE_64BIT
3759 ? _("`%s' is only supported in 64-bit mode")
3760 : _("`%s' is not supported in 64-bit mode")),
3761 current_templates
->start
->name
);
3764 /* If we are in 16-bit mode, do not allow addr16 or data16.
3765 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3766 if ((current_templates
->start
->opcode_modifier
.size16
3767 || current_templates
->start
->opcode_modifier
.size32
)
3768 && flag_code
!= CODE_64BIT
3769 && (current_templates
->start
->opcode_modifier
.size32
3770 ^ (flag_code
== CODE_16BIT
)))
3772 as_bad (_("redundant %s prefix"),
3773 current_templates
->start
->name
);
3776 /* Add prefix, checking for repeated prefixes. */
3777 switch (add_prefix (current_templates
->start
->base_opcode
))
3782 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3783 i
.hle_prefix
= current_templates
->start
->name
;
3784 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3785 i
.bnd_prefix
= current_templates
->start
->name
;
3787 i
.rep_prefix
= current_templates
->start
->name
;
3792 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3799 if (!current_templates
)
3801 /* Check if we should swap operand or force 32bit displacement in
3803 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3805 else if (mnem_p
- 3 == dot_p
3808 i
.disp_encoding
= disp_encoding_8bit
;
3809 else if (mnem_p
- 4 == dot_p
3813 i
.disp_encoding
= disp_encoding_32bit
;
3818 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3821 if (!current_templates
)
3824 /* See if we can get a match by trimming off a suffix. */
3827 case WORD_MNEM_SUFFIX
:
3828 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3829 i
.suffix
= SHORT_MNEM_SUFFIX
;
3831 case BYTE_MNEM_SUFFIX
:
3832 case QWORD_MNEM_SUFFIX
:
3833 i
.suffix
= mnem_p
[-1];
3835 current_templates
= (const templates
*) hash_find (op_hash
,
3838 case SHORT_MNEM_SUFFIX
:
3839 case LONG_MNEM_SUFFIX
:
3842 i
.suffix
= mnem_p
[-1];
3844 current_templates
= (const templates
*) hash_find (op_hash
,
3853 if (intel_float_operand (mnemonic
) == 1)
3854 i
.suffix
= SHORT_MNEM_SUFFIX
;
3856 i
.suffix
= LONG_MNEM_SUFFIX
;
3858 current_templates
= (const templates
*) hash_find (op_hash
,
3863 if (!current_templates
)
3865 as_bad (_("no such instruction: `%s'"), token_start
);
3870 if (current_templates
->start
->opcode_modifier
.jump
3871 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3873 /* Check for a branch hint. We allow ",pt" and ",pn" for
3874 predict taken and predict not taken respectively.
3875 I'm not sure that branch hints actually do anything on loop
3876 and jcxz insns (JumpByte) for current Pentium4 chips. They
3877 may work in the future and it doesn't hurt to accept them
3879 if (l
[0] == ',' && l
[1] == 'p')
3883 if (!add_prefix (DS_PREFIX_OPCODE
))
3887 else if (l
[2] == 'n')
3889 if (!add_prefix (CS_PREFIX_OPCODE
))
3895 /* Any other comma loses. */
3898 as_bad (_("invalid character %s in mnemonic"),
3899 output_invalid (*l
));
3903 /* Check if instruction is supported on specified architecture. */
3905 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3907 supported
|= cpu_flags_match (t
);
3908 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3912 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3914 as_bad (flag_code
== CODE_64BIT
3915 ? _("`%s' is not supported in 64-bit mode")
3916 : _("`%s' is only supported in 64-bit mode"),
3917 current_templates
->start
->name
);
3920 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3922 as_bad (_("`%s' is not supported on `%s%s'"),
3923 current_templates
->start
->name
,
3924 cpu_arch_name
? cpu_arch_name
: default_arch
,
3925 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3930 if (!cpu_arch_flags
.bitfield
.cpui386
3931 && (flag_code
!= CODE_16BIT
))
3933 as_warn (_("use .code16 to ensure correct addressing mode"));
3940 parse_operands (char *l
, const char *mnemonic
)
3944 /* 1 if operand is pending after ','. */
3945 unsigned int expecting_operand
= 0;
3947 /* Non-zero if operand parens not balanced. */
3948 unsigned int paren_not_balanced
;
3950 while (*l
!= END_OF_INSN
)
3952 /* Skip optional white space before operand. */
3953 if (is_space_char (*l
))
3955 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3957 as_bad (_("invalid character %s before operand %d"),
3958 output_invalid (*l
),
3962 token_start
= l
; /* after white space */
3963 paren_not_balanced
= 0;
3964 while (paren_not_balanced
|| *l
!= ',')
3966 if (*l
== END_OF_INSN
)
3968 if (paren_not_balanced
)
3971 as_bad (_("unbalanced parenthesis in operand %d."),
3974 as_bad (_("unbalanced brackets in operand %d."),
3979 break; /* we are done */
3981 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3983 as_bad (_("invalid character %s in operand %d"),
3984 output_invalid (*l
),
3991 ++paren_not_balanced
;
3993 --paren_not_balanced
;
3998 ++paren_not_balanced
;
4000 --paren_not_balanced
;
4004 if (l
!= token_start
)
4005 { /* Yes, we've read in another operand. */
4006 unsigned int operand_ok
;
4007 this_operand
= i
.operands
++;
4008 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4009 if (i
.operands
> MAX_OPERANDS
)
4011 as_bad (_("spurious operands; (%d operands/instruction max)"),
4015 /* Now parse operand adding info to 'i' as we go along. */
4016 END_STRING_AND_SAVE (l
);
4020 i386_intel_operand (token_start
,
4021 intel_float_operand (mnemonic
));
4023 operand_ok
= i386_att_operand (token_start
);
4025 RESTORE_END_STRING (l
);
4031 if (expecting_operand
)
4033 expecting_operand_after_comma
:
4034 as_bad (_("expecting operand after ','; got nothing"));
4039 as_bad (_("expecting operand before ','; got nothing"));
4044 /* Now *l must be either ',' or END_OF_INSN. */
4047 if (*++l
== END_OF_INSN
)
4049 /* Just skip it, if it's \n complain. */
4050 goto expecting_operand_after_comma
;
4052 expecting_operand
= 1;
4059 swap_2_operands (int xchg1
, int xchg2
)
4061 union i386_op temp_op
;
4062 i386_operand_type temp_type
;
4063 enum bfd_reloc_code_real temp_reloc
;
4065 temp_type
= i
.types
[xchg2
];
4066 i
.types
[xchg2
] = i
.types
[xchg1
];
4067 i
.types
[xchg1
] = temp_type
;
4068 temp_op
= i
.op
[xchg2
];
4069 i
.op
[xchg2
] = i
.op
[xchg1
];
4070 i
.op
[xchg1
] = temp_op
;
4071 temp_reloc
= i
.reloc
[xchg2
];
4072 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4073 i
.reloc
[xchg1
] = temp_reloc
;
4077 if (i
.mask
->operand
== xchg1
)
4078 i
.mask
->operand
= xchg2
;
4079 else if (i
.mask
->operand
== xchg2
)
4080 i
.mask
->operand
= xchg1
;
4084 if (i
.broadcast
->operand
== xchg1
)
4085 i
.broadcast
->operand
= xchg2
;
4086 else if (i
.broadcast
->operand
== xchg2
)
4087 i
.broadcast
->operand
= xchg1
;
4091 if (i
.rounding
->operand
== xchg1
)
4092 i
.rounding
->operand
= xchg2
;
4093 else if (i
.rounding
->operand
== xchg2
)
4094 i
.rounding
->operand
= xchg1
;
4099 swap_operands (void)
4105 swap_2_operands (1, i
.operands
- 2);
4108 swap_2_operands (0, i
.operands
- 1);
4114 if (i
.mem_operands
== 2)
4116 const seg_entry
*temp_seg
;
4117 temp_seg
= i
.seg
[0];
4118 i
.seg
[0] = i
.seg
[1];
4119 i
.seg
[1] = temp_seg
;
4123 /* Try to ensure constant immediates are represented in the smallest
4128 char guess_suffix
= 0;
4132 guess_suffix
= i
.suffix
;
4133 else if (i
.reg_operands
)
4135 /* Figure out a suffix from the last register operand specified.
4136 We can't do this properly yet, ie. excluding InOutPortReg,
4137 but the following works for instructions with immediates.
4138 In any case, we can't set i.suffix yet. */
4139 for (op
= i
.operands
; --op
>= 0;)
4140 if (i
.types
[op
].bitfield
.reg8
)
4142 guess_suffix
= BYTE_MNEM_SUFFIX
;
4145 else if (i
.types
[op
].bitfield
.reg16
)
4147 guess_suffix
= WORD_MNEM_SUFFIX
;
4150 else if (i
.types
[op
].bitfield
.reg32
)
4152 guess_suffix
= LONG_MNEM_SUFFIX
;
4155 else if (i
.types
[op
].bitfield
.reg64
)
4157 guess_suffix
= QWORD_MNEM_SUFFIX
;
4161 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4162 guess_suffix
= WORD_MNEM_SUFFIX
;
4164 for (op
= i
.operands
; --op
>= 0;)
4165 if (operand_type_check (i
.types
[op
], imm
))
4167 switch (i
.op
[op
].imms
->X_op
)
4170 /* If a suffix is given, this operand may be shortened. */
4171 switch (guess_suffix
)
4173 case LONG_MNEM_SUFFIX
:
4174 i
.types
[op
].bitfield
.imm32
= 1;
4175 i
.types
[op
].bitfield
.imm64
= 1;
4177 case WORD_MNEM_SUFFIX
:
4178 i
.types
[op
].bitfield
.imm16
= 1;
4179 i
.types
[op
].bitfield
.imm32
= 1;
4180 i
.types
[op
].bitfield
.imm32s
= 1;
4181 i
.types
[op
].bitfield
.imm64
= 1;
4183 case BYTE_MNEM_SUFFIX
:
4184 i
.types
[op
].bitfield
.imm8
= 1;
4185 i
.types
[op
].bitfield
.imm8s
= 1;
4186 i
.types
[op
].bitfield
.imm16
= 1;
4187 i
.types
[op
].bitfield
.imm32
= 1;
4188 i
.types
[op
].bitfield
.imm32s
= 1;
4189 i
.types
[op
].bitfield
.imm64
= 1;
4193 /* If this operand is at most 16 bits, convert it
4194 to a signed 16 bit number before trying to see
4195 whether it will fit in an even smaller size.
4196 This allows a 16-bit operand such as $0xffe0 to
4197 be recognised as within Imm8S range. */
4198 if ((i
.types
[op
].bitfield
.imm16
)
4199 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4201 i
.op
[op
].imms
->X_add_number
=
4202 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4204 if ((i
.types
[op
].bitfield
.imm32
)
4205 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4208 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4209 ^ ((offsetT
) 1 << 31))
4210 - ((offsetT
) 1 << 31));
4213 = operand_type_or (i
.types
[op
],
4214 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4216 /* We must avoid matching of Imm32 templates when 64bit
4217 only immediate is available. */
4218 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4219 i
.types
[op
].bitfield
.imm32
= 0;
4226 /* Symbols and expressions. */
4228 /* Convert symbolic operand to proper sizes for matching, but don't
4229 prevent matching a set of insns that only supports sizes other
4230 than those matching the insn suffix. */
4232 i386_operand_type mask
, allowed
;
4233 const insn_template
*t
;
4235 operand_type_set (&mask
, 0);
4236 operand_type_set (&allowed
, 0);
4238 for (t
= current_templates
->start
;
4239 t
< current_templates
->end
;
4241 allowed
= operand_type_or (allowed
,
4242 t
->operand_types
[op
]);
4243 switch (guess_suffix
)
4245 case QWORD_MNEM_SUFFIX
:
4246 mask
.bitfield
.imm64
= 1;
4247 mask
.bitfield
.imm32s
= 1;
4249 case LONG_MNEM_SUFFIX
:
4250 mask
.bitfield
.imm32
= 1;
4252 case WORD_MNEM_SUFFIX
:
4253 mask
.bitfield
.imm16
= 1;
4255 case BYTE_MNEM_SUFFIX
:
4256 mask
.bitfield
.imm8
= 1;
4261 allowed
= operand_type_and (mask
, allowed
);
4262 if (!operand_type_all_zero (&allowed
))
4263 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4270 /* Try to use the smallest displacement type too. */
4272 optimize_disp (void)
4276 for (op
= i
.operands
; --op
>= 0;)
4277 if (operand_type_check (i
.types
[op
], disp
))
4279 if (i
.op
[op
].disps
->X_op
== O_constant
)
4281 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4283 if (i
.types
[op
].bitfield
.disp16
4284 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4286 /* If this operand is at most 16 bits, convert
4287 to a signed 16 bit number and don't use 64bit
4289 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4290 i
.types
[op
].bitfield
.disp64
= 0;
4292 if (i
.types
[op
].bitfield
.disp32
4293 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4295 /* If this operand is at most 32 bits, convert
4296 to a signed 32 bit number and don't use 64bit
4298 op_disp
&= (((offsetT
) 2 << 31) - 1);
4299 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4300 i
.types
[op
].bitfield
.disp64
= 0;
4302 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4304 i
.types
[op
].bitfield
.disp8
= 0;
4305 i
.types
[op
].bitfield
.disp16
= 0;
4306 i
.types
[op
].bitfield
.disp32
= 0;
4307 i
.types
[op
].bitfield
.disp32s
= 0;
4308 i
.types
[op
].bitfield
.disp64
= 0;
4312 else if (flag_code
== CODE_64BIT
)
4314 if (fits_in_signed_long (op_disp
))
4316 i
.types
[op
].bitfield
.disp64
= 0;
4317 i
.types
[op
].bitfield
.disp32s
= 1;
4319 if (i
.prefix
[ADDR_PREFIX
]
4320 && fits_in_unsigned_long (op_disp
))
4321 i
.types
[op
].bitfield
.disp32
= 1;
4323 if ((i
.types
[op
].bitfield
.disp32
4324 || i
.types
[op
].bitfield
.disp32s
4325 || i
.types
[op
].bitfield
.disp16
)
4326 && fits_in_signed_byte (op_disp
))
4327 i
.types
[op
].bitfield
.disp8
= 1;
4329 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4330 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4332 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4333 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4334 i
.types
[op
].bitfield
.disp8
= 0;
4335 i
.types
[op
].bitfield
.disp16
= 0;
4336 i
.types
[op
].bitfield
.disp32
= 0;
4337 i
.types
[op
].bitfield
.disp32s
= 0;
4338 i
.types
[op
].bitfield
.disp64
= 0;
4341 /* We only support 64bit displacement on constants. */
4342 i
.types
[op
].bitfield
.disp64
= 0;
4346 /* Check if operands are valid for the instruction. */
4349 check_VecOperands (const insn_template
*t
)
4353 /* Without VSIB byte, we can't have a vector register for index. */
4354 if (!t
->opcode_modifier
.vecsib
4356 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4357 || i
.index_reg
->reg_type
.bitfield
.regymm
4358 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4360 i
.error
= unsupported_vector_index_register
;
4364 /* Check if default mask is allowed. */
4365 if (t
->opcode_modifier
.nodefmask
4366 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4368 i
.error
= no_default_mask
;
4372 /* For VSIB byte, we need a vector register for index, and all vector
4373 registers must be distinct. */
4374 if (t
->opcode_modifier
.vecsib
)
4377 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4378 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4379 || (t
->opcode_modifier
.vecsib
== VecSIB256
4380 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4381 || (t
->opcode_modifier
.vecsib
== VecSIB512
4382 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4384 i
.error
= invalid_vsib_address
;
4388 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4389 if (i
.reg_operands
== 2 && !i
.mask
)
4391 gas_assert (i
.types
[0].bitfield
.regxmm
4392 || i
.types
[0].bitfield
.regymm
);
4393 gas_assert (i
.types
[2].bitfield
.regxmm
4394 || i
.types
[2].bitfield
.regymm
);
4395 if (operand_check
== check_none
)
4397 if (register_number (i
.op
[0].regs
)
4398 != register_number (i
.index_reg
)
4399 && register_number (i
.op
[2].regs
)
4400 != register_number (i
.index_reg
)
4401 && register_number (i
.op
[0].regs
)
4402 != register_number (i
.op
[2].regs
))
4404 if (operand_check
== check_error
)
4406 i
.error
= invalid_vector_register_set
;
4409 as_warn (_("mask, index, and destination registers should be distinct"));
4411 else if (i
.reg_operands
== 1 && i
.mask
)
4413 if ((i
.types
[1].bitfield
.regymm
4414 || i
.types
[1].bitfield
.regzmm
)
4415 && (register_number (i
.op
[1].regs
)
4416 == register_number (i
.index_reg
)))
4418 if (operand_check
== check_error
)
4420 i
.error
= invalid_vector_register_set
;
4423 if (operand_check
!= check_none
)
4424 as_warn (_("index and destination registers should be distinct"));
4429 /* Check if broadcast is supported by the instruction and is applied
4430 to the memory operand. */
4433 int broadcasted_opnd_size
;
4435 /* Check if specified broadcast is supported in this instruction,
4436 and it's applied to memory operand of DWORD or QWORD type,
4437 depending on VecESize. */
4438 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4439 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4440 || (t
->opcode_modifier
.vecesize
== 0
4441 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4442 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4443 || (t
->opcode_modifier
.vecesize
== 1
4444 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4445 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4448 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4449 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4450 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4451 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4452 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4453 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4454 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4455 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4456 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4460 if ((broadcasted_opnd_size
== 256
4461 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4462 || (broadcasted_opnd_size
== 512
4463 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4466 i
.error
= unsupported_broadcast
;
4470 /* If broadcast is supported in this instruction, we need to check if
4471 operand of one-element size isn't specified without broadcast. */
4472 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4474 /* Find memory operand. */
4475 for (op
= 0; op
< i
.operands
; op
++)
4476 if (operand_type_check (i
.types
[op
], anymem
))
4478 gas_assert (op
< i
.operands
);
4479 /* Check size of the memory operand. */
4480 if ((t
->opcode_modifier
.vecesize
== 0
4481 && i
.types
[op
].bitfield
.dword
)
4482 || (t
->opcode_modifier
.vecesize
== 1
4483 && i
.types
[op
].bitfield
.qword
))
4485 i
.error
= broadcast_needed
;
4490 /* Check if requested masking is supported. */
4492 && (!t
->opcode_modifier
.masking
4494 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4496 i
.error
= unsupported_masking
;
4500 /* Check if masking is applied to dest operand. */
4501 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4503 i
.error
= mask_not_on_destination
;
4510 if ((i
.rounding
->type
!= saeonly
4511 && !t
->opcode_modifier
.staticrounding
)
4512 || (i
.rounding
->type
== saeonly
4513 && (t
->opcode_modifier
.staticrounding
4514 || !t
->opcode_modifier
.sae
)))
4516 i
.error
= unsupported_rc_sae
;
4519 /* If the instruction has several immediate operands and one of
4520 them is rounding, the rounding operand should be the last
4521 immediate operand. */
4522 if (i
.imm_operands
> 1
4523 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4525 i
.error
= rc_sae_operand_not_last_imm
;
4530 /* Check vector Disp8 operand. */
4531 if (t
->opcode_modifier
.disp8memshift
)
4534 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4536 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4538 for (op
= 0; op
< i
.operands
; op
++)
4539 if (operand_type_check (i
.types
[op
], disp
)
4540 && i
.op
[op
].disps
->X_op
== O_constant
)
4542 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4543 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4544 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4547 i
.types
[op
].bitfield
.vec_disp8
= 1;
4550 /* Vector insn can only have Vec_Disp8/Disp32 in
4551 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4553 i
.types
[op
].bitfield
.disp8
= 0;
4554 if (flag_code
!= CODE_16BIT
)
4555 i
.types
[op
].bitfield
.disp16
= 0;
4558 else if (flag_code
!= CODE_16BIT
)
4560 /* One form of this instruction supports vector Disp8.
4561 Try vector Disp8 if we need to use Disp32. */
4562 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4564 i
.error
= try_vector_disp8
;
4576 /* Check if operands are valid for the instruction. Update VEX
4580 VEX_check_operands (const insn_template
*t
)
4582 /* VREX is only valid with EVEX prefix. */
4583 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4585 i
.error
= invalid_register_operand
;
4589 if (!t
->opcode_modifier
.vex
)
4592 /* Only check VEX_Imm4, which must be the first operand. */
4593 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4595 if (i
.op
[0].imms
->X_op
!= O_constant
4596 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4602 /* Turn off Imm8 so that update_imm won't complain. */
4603 i
.types
[0] = vec_imm4
;
4609 static const insn_template
*
4610 match_template (void)
4612 /* Points to template once we've found it. */
4613 const insn_template
*t
;
4614 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4615 i386_operand_type overlap4
;
4616 unsigned int found_reverse_match
;
4617 i386_opcode_modifier suffix_check
;
4618 i386_operand_type operand_types
[MAX_OPERANDS
];
4619 int addr_prefix_disp
;
4621 unsigned int found_cpu_match
;
4622 unsigned int check_register
;
4623 enum i386_error specific_error
= 0;
4625 #if MAX_OPERANDS != 5
4626 # error "MAX_OPERANDS must be 5."
4629 found_reverse_match
= 0;
4630 addr_prefix_disp
= -1;
4632 memset (&suffix_check
, 0, sizeof (suffix_check
));
4633 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4634 suffix_check
.no_bsuf
= 1;
4635 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4636 suffix_check
.no_wsuf
= 1;
4637 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4638 suffix_check
.no_ssuf
= 1;
4639 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4640 suffix_check
.no_lsuf
= 1;
4641 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4642 suffix_check
.no_qsuf
= 1;
4643 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4644 suffix_check
.no_ldsuf
= 1;
4646 /* Must have right number of operands. */
4647 i
.error
= number_of_operands_mismatch
;
4649 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4651 addr_prefix_disp
= -1;
4653 if (i
.operands
!= t
->operands
)
4656 /* Check processor support. */
4657 i
.error
= unsupported
;
4658 found_cpu_match
= (cpu_flags_match (t
)
4659 == CPU_FLAGS_PERFECT_MATCH
);
4660 if (!found_cpu_match
)
4663 /* Check old gcc support. */
4664 i
.error
= old_gcc_only
;
4665 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4668 /* Check AT&T mnemonic. */
4669 i
.error
= unsupported_with_intel_mnemonic
;
4670 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4673 /* Check AT&T/Intel syntax. */
4674 i
.error
= unsupported_syntax
;
4675 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4676 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4679 /* Check the suffix, except for some instructions in intel mode. */
4680 i
.error
= invalid_instruction_suffix
;
4681 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4682 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4683 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4684 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4685 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4686 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4687 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4690 if (!operand_size_match (t
))
4693 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4694 operand_types
[j
] = t
->operand_types
[j
];
4696 /* In general, don't allow 64-bit operands in 32-bit mode. */
4697 if (i
.suffix
== QWORD_MNEM_SUFFIX
4698 && flag_code
!= CODE_64BIT
4700 ? (!t
->opcode_modifier
.ignoresize
4701 && !intel_float_operand (t
->name
))
4702 : intel_float_operand (t
->name
) != 2)
4703 && ((!operand_types
[0].bitfield
.regmmx
4704 && !operand_types
[0].bitfield
.regxmm
4705 && !operand_types
[0].bitfield
.regymm
4706 && !operand_types
[0].bitfield
.regzmm
)
4707 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4708 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4709 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4710 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4711 && (t
->base_opcode
!= 0x0fc7
4712 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4715 /* In general, don't allow 32-bit operands on pre-386. */
4716 else if (i
.suffix
== LONG_MNEM_SUFFIX
4717 && !cpu_arch_flags
.bitfield
.cpui386
4719 ? (!t
->opcode_modifier
.ignoresize
4720 && !intel_float_operand (t
->name
))
4721 : intel_float_operand (t
->name
) != 2)
4722 && ((!operand_types
[0].bitfield
.regmmx
4723 && !operand_types
[0].bitfield
.regxmm
)
4724 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4725 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4728 /* Do not verify operands when there are none. */
4732 /* We've found a match; break out of loop. */
4736 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4737 into Disp32/Disp16/Disp32 operand. */
4738 if (i
.prefix
[ADDR_PREFIX
] != 0)
4740 /* There should be only one Disp operand. */
4744 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4746 if (operand_types
[j
].bitfield
.disp16
)
4748 addr_prefix_disp
= j
;
4749 operand_types
[j
].bitfield
.disp32
= 1;
4750 operand_types
[j
].bitfield
.disp16
= 0;
4756 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4758 if (operand_types
[j
].bitfield
.disp32
)
4760 addr_prefix_disp
= j
;
4761 operand_types
[j
].bitfield
.disp32
= 0;
4762 operand_types
[j
].bitfield
.disp16
= 1;
4768 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4770 if (operand_types
[j
].bitfield
.disp64
)
4772 addr_prefix_disp
= j
;
4773 operand_types
[j
].bitfield
.disp64
= 0;
4774 operand_types
[j
].bitfield
.disp32
= 1;
4782 /* We check register size if needed. */
4783 check_register
= t
->opcode_modifier
.checkregsize
;
4784 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4785 switch (t
->operands
)
4788 if (!operand_type_match (overlap0
, i
.types
[0]))
4792 /* xchg %eax, %eax is a special case. It is an aliase for nop
4793 only in 32bit mode and we can use opcode 0x90. In 64bit
4794 mode, we can't use 0x90 for xchg %eax, %eax since it should
4795 zero-extend %eax to %rax. */
4796 if (flag_code
== CODE_64BIT
4797 && t
->base_opcode
== 0x90
4798 && operand_type_equal (&i
.types
[0], &acc32
)
4799 && operand_type_equal (&i
.types
[1], &acc32
))
4803 /* If we swap operand in encoding, we either match
4804 the next one or reverse direction of operands. */
4805 if (t
->opcode_modifier
.s
)
4807 else if (t
->opcode_modifier
.d
)
4812 /* If we swap operand in encoding, we match the next one. */
4813 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4817 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4818 if (!operand_type_match (overlap0
, i
.types
[0])
4819 || !operand_type_match (overlap1
, i
.types
[1])
4821 && !operand_type_register_match (overlap0
, i
.types
[0],
4823 overlap1
, i
.types
[1],
4826 /* Check if other direction is valid ... */
4827 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4831 /* Try reversing direction of operands. */
4832 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4833 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4834 if (!operand_type_match (overlap0
, i
.types
[0])
4835 || !operand_type_match (overlap1
, i
.types
[1])
4837 && !operand_type_register_match (overlap0
,
4844 /* Does not match either direction. */
4847 /* found_reverse_match holds which of D or FloatDR
4849 if (t
->opcode_modifier
.d
)
4850 found_reverse_match
= Opcode_D
;
4851 else if (t
->opcode_modifier
.floatd
)
4852 found_reverse_match
= Opcode_FloatD
;
4854 found_reverse_match
= 0;
4855 if (t
->opcode_modifier
.floatr
)
4856 found_reverse_match
|= Opcode_FloatR
;
4860 /* Found a forward 2 operand match here. */
4861 switch (t
->operands
)
4864 overlap4
= operand_type_and (i
.types
[4],
4867 overlap3
= operand_type_and (i
.types
[3],
4870 overlap2
= operand_type_and (i
.types
[2],
4875 switch (t
->operands
)
4878 if (!operand_type_match (overlap4
, i
.types
[4])
4879 || !operand_type_register_match (overlap3
,
4887 if (!operand_type_match (overlap3
, i
.types
[3])
4889 && !operand_type_register_match (overlap2
,
4897 /* Here we make use of the fact that there are no
4898 reverse match 3 operand instructions, and all 3
4899 operand instructions only need to be checked for
4900 register consistency between operands 2 and 3. */
4901 if (!operand_type_match (overlap2
, i
.types
[2])
4903 && !operand_type_register_match (overlap1
,
4913 /* Found either forward/reverse 2, 3 or 4 operand match here:
4914 slip through to break. */
4916 if (!found_cpu_match
)
4918 found_reverse_match
= 0;
4922 /* Check if vector and VEX operands are valid. */
4923 if (check_VecOperands (t
) || VEX_check_operands (t
))
4925 specific_error
= i
.error
;
4929 /* We've found a match; break out of loop. */
4933 if (t
== current_templates
->end
)
4935 /* We found no match. */
4936 const char *err_msg
;
4937 switch (specific_error
? specific_error
: i
.error
)
4941 case operand_size_mismatch
:
4942 err_msg
= _("operand size mismatch");
4944 case operand_type_mismatch
:
4945 err_msg
= _("operand type mismatch");
4947 case register_type_mismatch
:
4948 err_msg
= _("register type mismatch");
4950 case number_of_operands_mismatch
:
4951 err_msg
= _("number of operands mismatch");
4953 case invalid_instruction_suffix
:
4954 err_msg
= _("invalid instruction suffix");
4957 err_msg
= _("constant doesn't fit in 4 bits");
4960 err_msg
= _("only supported with old gcc");
4962 case unsupported_with_intel_mnemonic
:
4963 err_msg
= _("unsupported with Intel mnemonic");
4965 case unsupported_syntax
:
4966 err_msg
= _("unsupported syntax");
4969 as_bad (_("unsupported instruction `%s'"),
4970 current_templates
->start
->name
);
4972 case invalid_vsib_address
:
4973 err_msg
= _("invalid VSIB address");
4975 case invalid_vector_register_set
:
4976 err_msg
= _("mask, index, and destination registers must be distinct");
4978 case unsupported_vector_index_register
:
4979 err_msg
= _("unsupported vector index register");
4981 case unsupported_broadcast
:
4982 err_msg
= _("unsupported broadcast");
4984 case broadcast_not_on_src_operand
:
4985 err_msg
= _("broadcast not on source memory operand");
4987 case broadcast_needed
:
4988 err_msg
= _("broadcast is needed for operand of such type");
4990 case unsupported_masking
:
4991 err_msg
= _("unsupported masking");
4993 case mask_not_on_destination
:
4994 err_msg
= _("mask not on destination operand");
4996 case no_default_mask
:
4997 err_msg
= _("default mask isn't allowed");
4999 case unsupported_rc_sae
:
5000 err_msg
= _("unsupported static rounding/sae");
5002 case rc_sae_operand_not_last_imm
:
5004 err_msg
= _("RC/SAE operand must precede immediate operands");
5006 err_msg
= _("RC/SAE operand must follow immediate operands");
5008 case invalid_register_operand
:
5009 err_msg
= _("invalid register operand");
5012 as_bad (_("%s for `%s'"), err_msg
,
5013 current_templates
->start
->name
);
5017 if (!quiet_warnings
)
5020 && (i
.types
[0].bitfield
.jumpabsolute
5021 != operand_types
[0].bitfield
.jumpabsolute
))
5023 as_warn (_("indirect %s without `*'"), t
->name
);
5026 if (t
->opcode_modifier
.isprefix
5027 && t
->opcode_modifier
.ignoresize
)
5029 /* Warn them that a data or address size prefix doesn't
5030 affect assembly of the next line of code. */
5031 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5035 /* Copy the template we found. */
5038 if (addr_prefix_disp
!= -1)
5039 i
.tm
.operand_types
[addr_prefix_disp
]
5040 = operand_types
[addr_prefix_disp
];
5042 if (found_reverse_match
)
5044 /* If we found a reverse match we must alter the opcode
5045 direction bit. found_reverse_match holds bits to change
5046 (different for int & float insns). */
5048 i
.tm
.base_opcode
^= found_reverse_match
;
5050 i
.tm
.operand_types
[0] = operand_types
[1];
5051 i
.tm
.operand_types
[1] = operand_types
[0];
5060 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5061 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5063 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5065 as_bad (_("`%s' operand %d must use `%ses' segment"),
5071 /* There's only ever one segment override allowed per instruction.
5072 This instruction possibly has a legal segment override on the
5073 second operand, so copy the segment to where non-string
5074 instructions store it, allowing common code. */
5075 i
.seg
[0] = i
.seg
[1];
5077 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5079 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5081 as_bad (_("`%s' operand %d must use `%ses' segment"),
5092 process_suffix (void)
5094 /* If matched instruction specifies an explicit instruction mnemonic
5096 if (i
.tm
.opcode_modifier
.size16
)
5097 i
.suffix
= WORD_MNEM_SUFFIX
;
5098 else if (i
.tm
.opcode_modifier
.size32
)
5099 i
.suffix
= LONG_MNEM_SUFFIX
;
5100 else if (i
.tm
.opcode_modifier
.size64
)
5101 i
.suffix
= QWORD_MNEM_SUFFIX
;
5102 else if (i
.reg_operands
)
5104 /* If there's no instruction mnemonic suffix we try to invent one
5105 based on register operands. */
5108 /* We take i.suffix from the last register operand specified,
5109 Destination register type is more significant than source
5110 register type. crc32 in SSE4.2 prefers source register
5112 if (i
.tm
.base_opcode
== 0xf20f38f1)
5114 if (i
.types
[0].bitfield
.reg16
)
5115 i
.suffix
= WORD_MNEM_SUFFIX
;
5116 else if (i
.types
[0].bitfield
.reg32
)
5117 i
.suffix
= LONG_MNEM_SUFFIX
;
5118 else if (i
.types
[0].bitfield
.reg64
)
5119 i
.suffix
= QWORD_MNEM_SUFFIX
;
5121 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5123 if (i
.types
[0].bitfield
.reg8
)
5124 i
.suffix
= BYTE_MNEM_SUFFIX
;
5131 if (i
.tm
.base_opcode
== 0xf20f38f1
5132 || i
.tm
.base_opcode
== 0xf20f38f0)
5134 /* We have to know the operand size for crc32. */
5135 as_bad (_("ambiguous memory operand size for `%s`"),
5140 for (op
= i
.operands
; --op
>= 0;)
5141 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5143 if (i
.types
[op
].bitfield
.reg8
)
5145 i
.suffix
= BYTE_MNEM_SUFFIX
;
5148 else if (i
.types
[op
].bitfield
.reg16
)
5150 i
.suffix
= WORD_MNEM_SUFFIX
;
5153 else if (i
.types
[op
].bitfield
.reg32
)
5155 i
.suffix
= LONG_MNEM_SUFFIX
;
5158 else if (i
.types
[op
].bitfield
.reg64
)
5160 i
.suffix
= QWORD_MNEM_SUFFIX
;
5166 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5169 && i
.tm
.opcode_modifier
.ignoresize
5170 && i
.tm
.opcode_modifier
.no_bsuf
)
5172 else if (!check_byte_reg ())
5175 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5178 && i
.tm
.opcode_modifier
.ignoresize
5179 && i
.tm
.opcode_modifier
.no_lsuf
)
5181 else if (!check_long_reg ())
5184 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5187 && i
.tm
.opcode_modifier
.ignoresize
5188 && i
.tm
.opcode_modifier
.no_qsuf
)
5190 else if (!check_qword_reg ())
5193 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5196 && i
.tm
.opcode_modifier
.ignoresize
5197 && i
.tm
.opcode_modifier
.no_wsuf
)
5199 else if (!check_word_reg ())
5202 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5203 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5204 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5206 /* Skip if the instruction has x/y/z suffix. match_template
5207 should check if it is a valid suffix. */
5209 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5210 /* Do nothing if the instruction is going to ignore the prefix. */
5215 else if (i
.tm
.opcode_modifier
.defaultsize
5217 /* exclude fldenv/frstor/fsave/fstenv */
5218 && i
.tm
.opcode_modifier
.no_ssuf
)
5220 i
.suffix
= stackop_size
;
5222 else if (intel_syntax
5224 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5225 || i
.tm
.opcode_modifier
.jumpbyte
5226 || i
.tm
.opcode_modifier
.jumpintersegment
5227 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5228 && i
.tm
.extension_opcode
<= 3)))
5233 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5235 i
.suffix
= QWORD_MNEM_SUFFIX
;
5239 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5240 i
.suffix
= LONG_MNEM_SUFFIX
;
5243 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5244 i
.suffix
= WORD_MNEM_SUFFIX
;
5253 if (i
.tm
.opcode_modifier
.w
)
5255 as_bad (_("no instruction mnemonic suffix given and "
5256 "no register operands; can't size instruction"));
5262 unsigned int suffixes
;
5264 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5265 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5267 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5269 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5271 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5273 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5276 /* There are more than suffix matches. */
5277 if (i
.tm
.opcode_modifier
.w
5278 || ((suffixes
& (suffixes
- 1))
5279 && !i
.tm
.opcode_modifier
.defaultsize
5280 && !i
.tm
.opcode_modifier
.ignoresize
))
5282 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5288 /* Change the opcode based on the operand size given by i.suffix;
5289 We don't need to change things for byte insns. */
5292 && i
.suffix
!= BYTE_MNEM_SUFFIX
5293 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5294 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5295 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5297 /* It's not a byte, select word/dword operation. */
5298 if (i
.tm
.opcode_modifier
.w
)
5300 if (i
.tm
.opcode_modifier
.shortform
)
5301 i
.tm
.base_opcode
|= 8;
5303 i
.tm
.base_opcode
|= 1;
5306 /* Now select between word & dword operations via the operand
5307 size prefix, except for instructions that will ignore this
5309 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5311 /* The address size override prefix changes the size of the
5313 if ((flag_code
== CODE_32BIT
5314 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5315 || (flag_code
!= CODE_32BIT
5316 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5317 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5320 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5321 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5322 && !i
.tm
.opcode_modifier
.ignoresize
5323 && !i
.tm
.opcode_modifier
.floatmf
5324 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5325 || (flag_code
== CODE_64BIT
5326 && i
.tm
.opcode_modifier
.jumpbyte
)))
5328 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5330 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5331 prefix
= ADDR_PREFIX_OPCODE
;
5333 if (!add_prefix (prefix
))
5337 /* Set mode64 for an operand. */
5338 if (i
.suffix
== QWORD_MNEM_SUFFIX
5339 && flag_code
== CODE_64BIT
5340 && !i
.tm
.opcode_modifier
.norex64
)
5342 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5343 need rex64. cmpxchg8b is also a special case. */
5344 if (! (i
.operands
== 2
5345 && i
.tm
.base_opcode
== 0x90
5346 && i
.tm
.extension_opcode
== None
5347 && operand_type_equal (&i
.types
[0], &acc64
)
5348 && operand_type_equal (&i
.types
[1], &acc64
))
5349 && ! (i
.operands
== 1
5350 && i
.tm
.base_opcode
== 0xfc7
5351 && i
.tm
.extension_opcode
== 1
5352 && !operand_type_check (i
.types
[0], reg
)
5353 && operand_type_check (i
.types
[0], anymem
)))
5357 /* Size floating point instruction. */
5358 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5359 if (i
.tm
.opcode_modifier
.floatmf
)
5360 i
.tm
.base_opcode
^= 4;
5367 check_byte_reg (void)
5371 for (op
= i
.operands
; --op
>= 0;)
5373 /* If this is an eight bit register, it's OK. If it's the 16 or
5374 32 bit version of an eight bit register, we will just use the
5375 low portion, and that's OK too. */
5376 if (i
.types
[op
].bitfield
.reg8
)
5379 /* I/O port address operands are OK too. */
5380 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5383 /* crc32 doesn't generate this warning. */
5384 if (i
.tm
.base_opcode
== 0xf20f38f0)
5387 if ((i
.types
[op
].bitfield
.reg16
5388 || i
.types
[op
].bitfield
.reg32
5389 || i
.types
[op
].bitfield
.reg64
)
5390 && i
.op
[op
].regs
->reg_num
< 4
5391 /* Prohibit these changes in 64bit mode, since the lowering
5392 would be more complicated. */
5393 && flag_code
!= CODE_64BIT
)
5395 #if REGISTER_WARNINGS
5396 if (!quiet_warnings
)
5397 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5399 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5400 ? REGNAM_AL
- REGNAM_AX
5401 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5403 i
.op
[op
].regs
->reg_name
,
5408 /* Any other register is bad. */
5409 if (i
.types
[op
].bitfield
.reg16
5410 || i
.types
[op
].bitfield
.reg32
5411 || i
.types
[op
].bitfield
.reg64
5412 || i
.types
[op
].bitfield
.regmmx
5413 || i
.types
[op
].bitfield
.regxmm
5414 || i
.types
[op
].bitfield
.regymm
5415 || i
.types
[op
].bitfield
.regzmm
5416 || i
.types
[op
].bitfield
.sreg2
5417 || i
.types
[op
].bitfield
.sreg3
5418 || i
.types
[op
].bitfield
.control
5419 || i
.types
[op
].bitfield
.debug
5420 || i
.types
[op
].bitfield
.test
5421 || i
.types
[op
].bitfield
.floatreg
5422 || i
.types
[op
].bitfield
.floatacc
)
5424 as_bad (_("`%s%s' not allowed with `%s%c'"),
5426 i
.op
[op
].regs
->reg_name
,
5436 check_long_reg (void)
5440 for (op
= i
.operands
; --op
>= 0;)
5441 /* Reject eight bit registers, except where the template requires
5442 them. (eg. movzb) */
5443 if (i
.types
[op
].bitfield
.reg8
5444 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5445 || i
.tm
.operand_types
[op
].bitfield
.reg32
5446 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5448 as_bad (_("`%s%s' not allowed with `%s%c'"),
5450 i
.op
[op
].regs
->reg_name
,
5455 /* Warn if the e prefix on a general reg is missing. */
5456 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5457 && i
.types
[op
].bitfield
.reg16
5458 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5459 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5461 /* Prohibit these changes in the 64bit mode, since the
5462 lowering is more complicated. */
5463 if (flag_code
== CODE_64BIT
)
5465 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5466 register_prefix
, i
.op
[op
].regs
->reg_name
,
5470 #if REGISTER_WARNINGS
5471 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5473 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5474 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5477 /* Warn if the r prefix on a general reg is present. */
5478 else if (i
.types
[op
].bitfield
.reg64
5479 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5480 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5483 && i
.tm
.opcode_modifier
.toqword
5484 && !i
.types
[0].bitfield
.regxmm
)
5486 /* Convert to QWORD. We want REX byte. */
5487 i
.suffix
= QWORD_MNEM_SUFFIX
;
5491 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5492 register_prefix
, i
.op
[op
].regs
->reg_name
,
5501 check_qword_reg (void)
5505 for (op
= i
.operands
; --op
>= 0; )
5506 /* Reject eight bit registers, except where the template requires
5507 them. (eg. movzb) */
5508 if (i
.types
[op
].bitfield
.reg8
5509 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5510 || i
.tm
.operand_types
[op
].bitfield
.reg32
5511 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5513 as_bad (_("`%s%s' not allowed with `%s%c'"),
5515 i
.op
[op
].regs
->reg_name
,
5520 /* Warn if the r prefix on a general reg is missing. */
5521 else if ((i
.types
[op
].bitfield
.reg16
5522 || i
.types
[op
].bitfield
.reg32
)
5523 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5524 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5526 /* Prohibit these changes in the 64bit mode, since the
5527 lowering is more complicated. */
5529 && i
.tm
.opcode_modifier
.todword
5530 && !i
.types
[0].bitfield
.regxmm
)
5532 /* Convert to DWORD. We don't want REX byte. */
5533 i
.suffix
= LONG_MNEM_SUFFIX
;
5537 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5538 register_prefix
, i
.op
[op
].regs
->reg_name
,
5547 check_word_reg (void)
5550 for (op
= i
.operands
; --op
>= 0;)
5551 /* Reject eight bit registers, except where the template requires
5552 them. (eg. movzb) */
5553 if (i
.types
[op
].bitfield
.reg8
5554 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5555 || i
.tm
.operand_types
[op
].bitfield
.reg32
5556 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5558 as_bad (_("`%s%s' not allowed with `%s%c'"),
5560 i
.op
[op
].regs
->reg_name
,
5565 /* Warn if the e or r prefix on a general reg is present. */
5566 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5567 && (i
.types
[op
].bitfield
.reg32
5568 || i
.types
[op
].bitfield
.reg64
)
5569 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5570 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5572 /* Prohibit these changes in the 64bit mode, since the
5573 lowering is more complicated. */
5574 if (flag_code
== CODE_64BIT
)
5576 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5577 register_prefix
, i
.op
[op
].regs
->reg_name
,
5581 #if REGISTER_WARNINGS
5582 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5584 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5585 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5592 update_imm (unsigned int j
)
5594 i386_operand_type overlap
= i
.types
[j
];
5595 if ((overlap
.bitfield
.imm8
5596 || overlap
.bitfield
.imm8s
5597 || overlap
.bitfield
.imm16
5598 || overlap
.bitfield
.imm32
5599 || overlap
.bitfield
.imm32s
5600 || overlap
.bitfield
.imm64
)
5601 && !operand_type_equal (&overlap
, &imm8
)
5602 && !operand_type_equal (&overlap
, &imm8s
)
5603 && !operand_type_equal (&overlap
, &imm16
)
5604 && !operand_type_equal (&overlap
, &imm32
)
5605 && !operand_type_equal (&overlap
, &imm32s
)
5606 && !operand_type_equal (&overlap
, &imm64
))
5610 i386_operand_type temp
;
5612 operand_type_set (&temp
, 0);
5613 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5615 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5616 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5618 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5619 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5620 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5622 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5623 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5626 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5629 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5630 || operand_type_equal (&overlap
, &imm16_32
)
5631 || operand_type_equal (&overlap
, &imm16_32s
))
5633 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5638 if (!operand_type_equal (&overlap
, &imm8
)
5639 && !operand_type_equal (&overlap
, &imm8s
)
5640 && !operand_type_equal (&overlap
, &imm16
)
5641 && !operand_type_equal (&overlap
, &imm32
)
5642 && !operand_type_equal (&overlap
, &imm32s
)
5643 && !operand_type_equal (&overlap
, &imm64
))
5645 as_bad (_("no instruction mnemonic suffix given; "
5646 "can't determine immediate size"));
5650 i
.types
[j
] = overlap
;
5660 /* Update the first 2 immediate operands. */
5661 n
= i
.operands
> 2 ? 2 : i
.operands
;
5664 for (j
= 0; j
< n
; j
++)
5665 if (update_imm (j
) == 0)
5668 /* The 3rd operand can't be immediate operand. */
5669 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5676 bad_implicit_operand (int xmm
)
5678 const char *ireg
= xmm
? "xmm0" : "ymm0";
5681 as_bad (_("the last operand of `%s' must be `%s%s'"),
5682 i
.tm
.name
, register_prefix
, ireg
);
5684 as_bad (_("the first operand of `%s' must be `%s%s'"),
5685 i
.tm
.name
, register_prefix
, ireg
);
5690 process_operands (void)
5692 /* Default segment register this instruction will use for memory
5693 accesses. 0 means unknown. This is only for optimizing out
5694 unnecessary segment overrides. */
5695 const seg_entry
*default_seg
= 0;
5697 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5699 unsigned int dupl
= i
.operands
;
5700 unsigned int dest
= dupl
- 1;
5703 /* The destination must be an xmm register. */
5704 gas_assert (i
.reg_operands
5705 && MAX_OPERANDS
> dupl
5706 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5708 if (i
.tm
.opcode_modifier
.firstxmm0
)
5710 /* The first operand is implicit and must be xmm0. */
5711 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5712 if (register_number (i
.op
[0].regs
) != 0)
5713 return bad_implicit_operand (1);
5715 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5717 /* Keep xmm0 for instructions with VEX prefix and 3
5723 /* We remove the first xmm0 and keep the number of
5724 operands unchanged, which in fact duplicates the
5726 for (j
= 1; j
< i
.operands
; j
++)
5728 i
.op
[j
- 1] = i
.op
[j
];
5729 i
.types
[j
- 1] = i
.types
[j
];
5730 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5734 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5736 gas_assert ((MAX_OPERANDS
- 1) > dupl
5737 && (i
.tm
.opcode_modifier
.vexsources
5740 /* Add the implicit xmm0 for instructions with VEX prefix
5742 for (j
= i
.operands
; j
> 0; j
--)
5744 i
.op
[j
] = i
.op
[j
- 1];
5745 i
.types
[j
] = i
.types
[j
- 1];
5746 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5749 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5750 i
.types
[0] = regxmm
;
5751 i
.tm
.operand_types
[0] = regxmm
;
5754 i
.reg_operands
+= 2;
5759 i
.op
[dupl
] = i
.op
[dest
];
5760 i
.types
[dupl
] = i
.types
[dest
];
5761 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5770 i
.op
[dupl
] = i
.op
[dest
];
5771 i
.types
[dupl
] = i
.types
[dest
];
5772 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5775 if (i
.tm
.opcode_modifier
.immext
)
5778 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5782 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5783 gas_assert (i
.reg_operands
5784 && (operand_type_equal (&i
.types
[0], ®xmm
)
5785 || operand_type_equal (&i
.types
[0], ®ymm
)
5786 || operand_type_equal (&i
.types
[0], ®zmm
)));
5787 if (register_number (i
.op
[0].regs
) != 0)
5788 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5790 for (j
= 1; j
< i
.operands
; j
++)
5792 i
.op
[j
- 1] = i
.op
[j
];
5793 i
.types
[j
- 1] = i
.types
[j
];
5795 /* We need to adjust fields in i.tm since they are used by
5796 build_modrm_byte. */
5797 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5804 else if (i
.tm
.opcode_modifier
.regkludge
)
5806 /* The imul $imm, %reg instruction is converted into
5807 imul $imm, %reg, %reg, and the clr %reg instruction
5808 is converted into xor %reg, %reg. */
5810 unsigned int first_reg_op
;
5812 if (operand_type_check (i
.types
[0], reg
))
5816 /* Pretend we saw the extra register operand. */
5817 gas_assert (i
.reg_operands
== 1
5818 && i
.op
[first_reg_op
+ 1].regs
== 0);
5819 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5820 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5825 if (i
.tm
.opcode_modifier
.shortform
)
5827 if (i
.types
[0].bitfield
.sreg2
5828 || i
.types
[0].bitfield
.sreg3
)
5830 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5831 && i
.op
[0].regs
->reg_num
== 1)
5833 as_bad (_("you can't `pop %scs'"), register_prefix
);
5836 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5837 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5842 /* The register or float register operand is in operand
5846 if (i
.types
[0].bitfield
.floatreg
5847 || operand_type_check (i
.types
[0], reg
))
5851 /* Register goes in low 3 bits of opcode. */
5852 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5853 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5855 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5857 /* Warn about some common errors, but press on regardless.
5858 The first case can be generated by gcc (<= 2.8.1). */
5859 if (i
.operands
== 2)
5861 /* Reversed arguments on faddp, fsubp, etc. */
5862 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5863 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5864 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5868 /* Extraneous `l' suffix on fp insn. */
5869 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5870 register_prefix
, i
.op
[0].regs
->reg_name
);
5875 else if (i
.tm
.opcode_modifier
.modrm
)
5877 /* The opcode is completed (modulo i.tm.extension_opcode which
5878 must be put into the modrm byte). Now, we make the modrm and
5879 index base bytes based on all the info we've collected. */
5881 default_seg
= build_modrm_byte ();
5883 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5887 else if (i
.tm
.opcode_modifier
.isstring
)
5889 /* For the string instructions that allow a segment override
5890 on one of their operands, the default segment is ds. */
5894 if (i
.tm
.base_opcode
== 0x8d /* lea */
5897 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5899 /* If a segment was explicitly specified, and the specified segment
5900 is not the default, use an opcode prefix to select it. If we
5901 never figured out what the default segment is, then default_seg
5902 will be zero at this point, and the specified segment prefix will
5904 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5906 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5912 static const seg_entry
*
5913 build_modrm_byte (void)
5915 const seg_entry
*default_seg
= 0;
5916 unsigned int source
, dest
;
5919 /* The first operand of instructions with VEX prefix and 3 sources
5920 must be VEX_Imm4. */
5921 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5924 unsigned int nds
, reg_slot
;
5927 if (i
.tm
.opcode_modifier
.veximmext
5928 && i
.tm
.opcode_modifier
.immext
)
5930 dest
= i
.operands
- 2;
5931 gas_assert (dest
== 3);
5934 dest
= i
.operands
- 1;
5937 /* There are 2 kinds of instructions:
5938 1. 5 operands: 4 register operands or 3 register operands
5939 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5940 VexW0 or VexW1. The destination must be either XMM, YMM or
5942 2. 4 operands: 4 register operands or 3 register operands
5943 plus 1 memory operand, VexXDS, and VexImmExt */
5944 gas_assert ((i
.reg_operands
== 4
5945 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5946 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5947 && (i
.tm
.opcode_modifier
.veximmext
5948 || (i
.imm_operands
== 1
5949 && i
.types
[0].bitfield
.vec_imm4
5950 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5951 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5952 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5953 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5954 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5956 if (i
.imm_operands
== 0)
5958 /* When there is no immediate operand, generate an 8bit
5959 immediate operand to encode the first operand. */
5960 exp
= &im_expressions
[i
.imm_operands
++];
5961 i
.op
[i
.operands
].imms
= exp
;
5962 i
.types
[i
.operands
] = imm8
;
5964 /* If VexW1 is set, the first operand is the source and
5965 the second operand is encoded in the immediate operand. */
5966 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5977 /* FMA swaps REG and NDS. */
5978 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5986 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5988 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5990 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5992 exp
->X_op
= O_constant
;
5993 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5994 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5998 unsigned int imm_slot
;
6000 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6002 /* If VexW0 is set, the third operand is the source and
6003 the second operand is encoded in the immediate
6010 /* VexW1 is set, the second operand is the source and
6011 the third operand is encoded in the immediate
6017 if (i
.tm
.opcode_modifier
.immext
)
6019 /* When ImmExt is set, the immdiate byte is the last
6021 imm_slot
= i
.operands
- 1;
6029 /* Turn on Imm8 so that output_imm will generate it. */
6030 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6033 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6035 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6037 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6039 i
.op
[imm_slot
].imms
->X_add_number
6040 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6041 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6044 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6045 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6047 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6049 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6054 /* i.reg_operands MUST be the number of real register operands;
6055 implicit registers do not count. If there are 3 register
6056 operands, it must be a instruction with VexNDS. For a
6057 instruction with VexNDD, the destination register is encoded
6058 in VEX prefix. If there are 4 register operands, it must be
6059 a instruction with VEX prefix and 3 sources. */
6060 if (i
.mem_operands
== 0
6061 && ((i
.reg_operands
== 2
6062 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6063 || (i
.reg_operands
== 3
6064 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6065 || (i
.reg_operands
== 4 && vex_3_sources
)))
6073 /* When there are 3 operands, one of them may be immediate,
6074 which may be the first or the last operand. Otherwise,
6075 the first operand must be shift count register (cl) or it
6076 is an instruction with VexNDS. */
6077 gas_assert (i
.imm_operands
== 1
6078 || (i
.imm_operands
== 0
6079 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6080 || i
.types
[0].bitfield
.shiftcount
)));
6081 if (operand_type_check (i
.types
[0], imm
)
6082 || i
.types
[0].bitfield
.shiftcount
)
6088 /* When there are 4 operands, the first two must be 8bit
6089 immediate operands. The source operand will be the 3rd
6092 For instructions with VexNDS, if the first operand
6093 an imm8, the source operand is the 2nd one. If the last
6094 operand is imm8, the source operand is the first one. */
6095 gas_assert ((i
.imm_operands
== 2
6096 && i
.types
[0].bitfield
.imm8
6097 && i
.types
[1].bitfield
.imm8
)
6098 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6099 && i
.imm_operands
== 1
6100 && (i
.types
[0].bitfield
.imm8
6101 || i
.types
[i
.operands
- 1].bitfield
.imm8
6103 if (i
.imm_operands
== 2)
6107 if (i
.types
[0].bitfield
.imm8
)
6114 if (i
.tm
.opcode_modifier
.evex
)
6116 /* For EVEX instructions, when there are 5 operands, the
6117 first one must be immediate operand. If the second one
6118 is immediate operand, the source operand is the 3th
6119 one. If the last one is immediate operand, the source
6120 operand is the 2nd one. */
6121 gas_assert (i
.imm_operands
== 2
6122 && i
.tm
.opcode_modifier
.sae
6123 && operand_type_check (i
.types
[0], imm
));
6124 if (operand_type_check (i
.types
[1], imm
))
6126 else if (operand_type_check (i
.types
[4], imm
))
6140 /* RC/SAE operand could be between DEST and SRC. That happens
6141 when one operand is GPR and the other one is XMM/YMM/ZMM
6143 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6146 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6148 /* For instructions with VexNDS, the register-only source
6149 operand must be 32/64bit integer, XMM, YMM or ZMM
6150 register. It is encoded in VEX prefix. We need to
6151 clear RegMem bit before calling operand_type_equal. */
6153 i386_operand_type op
;
6156 /* Check register-only source operand when two source
6157 operands are swapped. */
6158 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6159 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6167 op
= i
.tm
.operand_types
[vvvv
];
6168 op
.bitfield
.regmem
= 0;
6169 if ((dest
+ 1) >= i
.operands
6170 || (op
.bitfield
.reg32
!= 1
6171 && !op
.bitfield
.reg64
!= 1
6172 && !operand_type_equal (&op
, ®xmm
)
6173 && !operand_type_equal (&op
, ®ymm
)
6174 && !operand_type_equal (&op
, ®zmm
)
6175 && !operand_type_equal (&op
, ®mask
)))
6177 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6183 /* One of the register operands will be encoded in the i.tm.reg
6184 field, the other in the combined i.tm.mode and i.tm.regmem
6185 fields. If no form of this instruction supports a memory
6186 destination operand, then we assume the source operand may
6187 sometimes be a memory operand and so we need to store the
6188 destination in the i.rm.reg field. */
6189 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6190 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6192 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6193 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6194 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6196 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6198 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6200 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6205 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6206 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6207 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6209 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6211 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6213 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6216 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6218 if (!i
.types
[0].bitfield
.control
6219 && !i
.types
[1].bitfield
.control
)
6221 i
.rex
&= ~(REX_R
| REX_B
);
6222 add_prefix (LOCK_PREFIX_OPCODE
);
6226 { /* If it's not 2 reg operands... */
6231 unsigned int fake_zero_displacement
= 0;
6234 for (op
= 0; op
< i
.operands
; op
++)
6235 if (operand_type_check (i
.types
[op
], anymem
))
6237 gas_assert (op
< i
.operands
);
6239 if (i
.tm
.opcode_modifier
.vecsib
)
6241 if (i
.index_reg
->reg_num
== RegEiz
6242 || i
.index_reg
->reg_num
== RegRiz
)
6245 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6248 i
.sib
.base
= NO_BASE_REGISTER
;
6249 i
.sib
.scale
= i
.log2_scale_factor
;
6250 /* No Vec_Disp8 if there is no base. */
6251 i
.types
[op
].bitfield
.vec_disp8
= 0;
6252 i
.types
[op
].bitfield
.disp8
= 0;
6253 i
.types
[op
].bitfield
.disp16
= 0;
6254 i
.types
[op
].bitfield
.disp64
= 0;
6255 if (flag_code
!= CODE_64BIT
)
6257 /* Must be 32 bit */
6258 i
.types
[op
].bitfield
.disp32
= 1;
6259 i
.types
[op
].bitfield
.disp32s
= 0;
6263 i
.types
[op
].bitfield
.disp32
= 0;
6264 i
.types
[op
].bitfield
.disp32s
= 1;
6267 i
.sib
.index
= i
.index_reg
->reg_num
;
6268 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6270 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6276 if (i
.base_reg
== 0)
6279 if (!i
.disp_operands
)
6281 fake_zero_displacement
= 1;
6282 /* Instructions with VSIB byte need 32bit displacement
6283 if there is no base register. */
6284 if (i
.tm
.opcode_modifier
.vecsib
)
6285 i
.types
[op
].bitfield
.disp32
= 1;
6287 if (i
.index_reg
== 0)
6289 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6290 /* Operand is just <disp> */
6291 if (flag_code
== CODE_64BIT
)
6293 /* 64bit mode overwrites the 32bit absolute
6294 addressing by RIP relative addressing and
6295 absolute addressing is encoded by one of the
6296 redundant SIB forms. */
6297 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6298 i
.sib
.base
= NO_BASE_REGISTER
;
6299 i
.sib
.index
= NO_INDEX_REGISTER
;
6300 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6301 ? disp32s
: disp32
);
6303 else if ((flag_code
== CODE_16BIT
)
6304 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6306 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6307 i
.types
[op
] = disp16
;
6311 i
.rm
.regmem
= NO_BASE_REGISTER
;
6312 i
.types
[op
] = disp32
;
6315 else if (!i
.tm
.opcode_modifier
.vecsib
)
6317 /* !i.base_reg && i.index_reg */
6318 if (i
.index_reg
->reg_num
== RegEiz
6319 || i
.index_reg
->reg_num
== RegRiz
)
6320 i
.sib
.index
= NO_INDEX_REGISTER
;
6322 i
.sib
.index
= i
.index_reg
->reg_num
;
6323 i
.sib
.base
= NO_BASE_REGISTER
;
6324 i
.sib
.scale
= i
.log2_scale_factor
;
6325 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6326 /* No Vec_Disp8 if there is no base. */
6327 i
.types
[op
].bitfield
.vec_disp8
= 0;
6328 i
.types
[op
].bitfield
.disp8
= 0;
6329 i
.types
[op
].bitfield
.disp16
= 0;
6330 i
.types
[op
].bitfield
.disp64
= 0;
6331 if (flag_code
!= CODE_64BIT
)
6333 /* Must be 32 bit */
6334 i
.types
[op
].bitfield
.disp32
= 1;
6335 i
.types
[op
].bitfield
.disp32s
= 0;
6339 i
.types
[op
].bitfield
.disp32
= 0;
6340 i
.types
[op
].bitfield
.disp32s
= 1;
6342 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6346 /* RIP addressing for 64bit mode. */
6347 else if (i
.base_reg
->reg_num
== RegRip
||
6348 i
.base_reg
->reg_num
== RegEip
)
6350 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6351 i
.rm
.regmem
= NO_BASE_REGISTER
;
6352 i
.types
[op
].bitfield
.disp8
= 0;
6353 i
.types
[op
].bitfield
.disp16
= 0;
6354 i
.types
[op
].bitfield
.disp32
= 0;
6355 i
.types
[op
].bitfield
.disp32s
= 1;
6356 i
.types
[op
].bitfield
.disp64
= 0;
6357 i
.types
[op
].bitfield
.vec_disp8
= 0;
6358 i
.flags
[op
] |= Operand_PCrel
;
6359 if (! i
.disp_operands
)
6360 fake_zero_displacement
= 1;
6362 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6364 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6365 switch (i
.base_reg
->reg_num
)
6368 if (i
.index_reg
== 0)
6370 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6371 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6375 if (i
.index_reg
== 0)
6378 if (operand_type_check (i
.types
[op
], disp
) == 0)
6380 /* fake (%bp) into 0(%bp) */
6381 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6382 i
.types
[op
].bitfield
.vec_disp8
= 1;
6384 i
.types
[op
].bitfield
.disp8
= 1;
6385 fake_zero_displacement
= 1;
6388 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6389 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6391 default: /* (%si) -> 4 or (%di) -> 5 */
6392 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6394 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6396 else /* i.base_reg and 32/64 bit mode */
6398 if (flag_code
== CODE_64BIT
6399 && operand_type_check (i
.types
[op
], disp
))
6401 i386_operand_type temp
;
6402 operand_type_set (&temp
, 0);
6403 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6404 temp
.bitfield
.vec_disp8
6405 = i
.types
[op
].bitfield
.vec_disp8
;
6407 if (i
.prefix
[ADDR_PREFIX
] == 0)
6408 i
.types
[op
].bitfield
.disp32s
= 1;
6410 i
.types
[op
].bitfield
.disp32
= 1;
6413 if (!i
.tm
.opcode_modifier
.vecsib
)
6414 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6415 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6417 i
.sib
.base
= i
.base_reg
->reg_num
;
6418 /* x86-64 ignores REX prefix bit here to avoid decoder
6420 if (!(i
.base_reg
->reg_flags
& RegRex
)
6421 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6422 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6424 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6426 fake_zero_displacement
= 1;
6427 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6428 i
.types
[op
].bitfield
.vec_disp8
= 1;
6430 i
.types
[op
].bitfield
.disp8
= 1;
6432 i
.sib
.scale
= i
.log2_scale_factor
;
6433 if (i
.index_reg
== 0)
6435 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6436 /* <disp>(%esp) becomes two byte modrm with no index
6437 register. We've already stored the code for esp
6438 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6439 Any base register besides %esp will not use the
6440 extra modrm byte. */
6441 i
.sib
.index
= NO_INDEX_REGISTER
;
6443 else if (!i
.tm
.opcode_modifier
.vecsib
)
6445 if (i
.index_reg
->reg_num
== RegEiz
6446 || i
.index_reg
->reg_num
== RegRiz
)
6447 i
.sib
.index
= NO_INDEX_REGISTER
;
6449 i
.sib
.index
= i
.index_reg
->reg_num
;
6450 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6451 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6456 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6457 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6461 if (!fake_zero_displacement
6465 fake_zero_displacement
= 1;
6466 if (i
.disp_encoding
== disp_encoding_8bit
)
6467 i
.types
[op
].bitfield
.disp8
= 1;
6469 i
.types
[op
].bitfield
.disp32
= 1;
6471 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6475 if (fake_zero_displacement
)
6477 /* Fakes a zero displacement assuming that i.types[op]
6478 holds the correct displacement size. */
6481 gas_assert (i
.op
[op
].disps
== 0);
6482 exp
= &disp_expressions
[i
.disp_operands
++];
6483 i
.op
[op
].disps
= exp
;
6484 exp
->X_op
= O_constant
;
6485 exp
->X_add_number
= 0;
6486 exp
->X_add_symbol
= (symbolS
*) 0;
6487 exp
->X_op_symbol
= (symbolS
*) 0;
6495 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6497 if (operand_type_check (i
.types
[0], imm
))
6498 i
.vex
.register_specifier
= NULL
;
6501 /* VEX.vvvv encodes one of the sources when the first
6502 operand is not an immediate. */
6503 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6504 i
.vex
.register_specifier
= i
.op
[0].regs
;
6506 i
.vex
.register_specifier
= i
.op
[1].regs
;
6509 /* Destination is a XMM register encoded in the ModRM.reg
6511 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6512 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6515 /* ModRM.rm and VEX.B encodes the other source. */
6516 if (!i
.mem_operands
)
6520 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6521 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6523 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6525 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6529 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6531 i
.vex
.register_specifier
= i
.op
[2].regs
;
6532 if (!i
.mem_operands
)
6535 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6536 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6540 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6541 (if any) based on i.tm.extension_opcode. Again, we must be
6542 careful to make sure that segment/control/debug/test/MMX
6543 registers are coded into the i.rm.reg field. */
6544 else if (i
.reg_operands
)
6547 unsigned int vex_reg
= ~0;
6549 for (op
= 0; op
< i
.operands
; op
++)
6550 if (i
.types
[op
].bitfield
.reg8
6551 || i
.types
[op
].bitfield
.reg16
6552 || i
.types
[op
].bitfield
.reg32
6553 || i
.types
[op
].bitfield
.reg64
6554 || i
.types
[op
].bitfield
.regmmx
6555 || i
.types
[op
].bitfield
.regxmm
6556 || i
.types
[op
].bitfield
.regymm
6557 || i
.types
[op
].bitfield
.regbnd
6558 || i
.types
[op
].bitfield
.regzmm
6559 || i
.types
[op
].bitfield
.regmask
6560 || i
.types
[op
].bitfield
.sreg2
6561 || i
.types
[op
].bitfield
.sreg3
6562 || i
.types
[op
].bitfield
.control
6563 || i
.types
[op
].bitfield
.debug
6564 || i
.types
[op
].bitfield
.test
)
6569 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6571 /* For instructions with VexNDS, the register-only
6572 source operand is encoded in VEX prefix. */
6573 gas_assert (mem
!= (unsigned int) ~0);
6578 gas_assert (op
< i
.operands
);
6582 /* Check register-only source operand when two source
6583 operands are swapped. */
6584 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6585 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6589 gas_assert (mem
== (vex_reg
+ 1)
6590 && op
< i
.operands
);
6595 gas_assert (vex_reg
< i
.operands
);
6599 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6601 /* For instructions with VexNDD, the register destination
6602 is encoded in VEX prefix. */
6603 if (i
.mem_operands
== 0)
6605 /* There is no memory operand. */
6606 gas_assert ((op
+ 2) == i
.operands
);
6611 /* There are only 2 operands. */
6612 gas_assert (op
< 2 && i
.operands
== 2);
6617 gas_assert (op
< i
.operands
);
6619 if (vex_reg
!= (unsigned int) ~0)
6621 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6623 if (type
->bitfield
.reg32
!= 1
6624 && type
->bitfield
.reg64
!= 1
6625 && !operand_type_equal (type
, ®xmm
)
6626 && !operand_type_equal (type
, ®ymm
)
6627 && !operand_type_equal (type
, ®zmm
)
6628 && !operand_type_equal (type
, ®mask
))
6631 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6634 /* Don't set OP operand twice. */
6637 /* If there is an extension opcode to put here, the
6638 register number must be put into the regmem field. */
6639 if (i
.tm
.extension_opcode
!= None
)
6641 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6642 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6644 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6649 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6650 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6652 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6657 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6658 must set it to 3 to indicate this is a register operand
6659 in the regmem field. */
6660 if (!i
.mem_operands
)
6664 /* Fill in i.rm.reg field with extension opcode (if any). */
6665 if (i
.tm
.extension_opcode
!= None
)
6666 i
.rm
.reg
= i
.tm
.extension_opcode
;
6672 output_branch (void)
6678 relax_substateT subtype
;
6682 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6683 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6686 if (i
.prefix
[DATA_PREFIX
] != 0)
6692 /* Pentium4 branch hints. */
6693 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6694 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6699 if (i
.prefix
[REX_PREFIX
] != 0)
6705 /* BND prefixed jump. */
6706 if (i
.prefix
[BND_PREFIX
] != 0)
6708 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6712 if (i
.prefixes
!= 0 && !intel_syntax
)
6713 as_warn (_("skipping prefixes on this instruction"));
6715 /* It's always a symbol; End frag & setup for relax.
6716 Make sure there is enough room in this frag for the largest
6717 instruction we may generate in md_convert_frag. This is 2
6718 bytes for the opcode and room for the prefix and largest
6720 frag_grow (prefix
+ 2 + 4);
6721 /* Prefix and 1 opcode byte go in fr_fix. */
6722 p
= frag_more (prefix
+ 1);
6723 if (i
.prefix
[DATA_PREFIX
] != 0)
6724 *p
++ = DATA_PREFIX_OPCODE
;
6725 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6726 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6727 *p
++ = i
.prefix
[SEG_PREFIX
];
6728 if (i
.prefix
[REX_PREFIX
] != 0)
6729 *p
++ = i
.prefix
[REX_PREFIX
];
6730 *p
= i
.tm
.base_opcode
;
6732 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6733 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6734 else if (cpu_arch_flags
.bitfield
.cpui386
)
6735 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6737 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6740 sym
= i
.op
[0].disps
->X_add_symbol
;
6741 off
= i
.op
[0].disps
->X_add_number
;
6743 if (i
.op
[0].disps
->X_op
!= O_constant
6744 && i
.op
[0].disps
->X_op
!= O_symbol
)
6746 /* Handle complex expressions. */
6747 sym
= make_expr_symbol (i
.op
[0].disps
);
6751 /* 1 possible extra opcode + 4 byte displacement go in var part.
6752 Pass reloc in fr_var. */
6753 frag_var (rs_machine_dependent
, 5,
6755 || i
.reloc
[0] != NO_RELOC
6756 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6758 : BFD_RELOC_X86_64_PC32_BND
),
6759 subtype
, sym
, off
, p
);
6769 if (i
.tm
.opcode_modifier
.jumpbyte
)
6771 /* This is a loop or jecxz type instruction. */
6773 if (i
.prefix
[ADDR_PREFIX
] != 0)
6775 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6778 /* Pentium4 branch hints. */
6779 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6780 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6782 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6791 if (flag_code
== CODE_16BIT
)
6794 if (i
.prefix
[DATA_PREFIX
] != 0)
6796 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6806 if (i
.prefix
[REX_PREFIX
] != 0)
6808 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6812 /* BND prefixed jump. */
6813 if (i
.prefix
[BND_PREFIX
] != 0)
6815 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6819 if (i
.prefixes
!= 0 && !intel_syntax
)
6820 as_warn (_("skipping prefixes on this instruction"));
6822 p
= frag_more (i
.tm
.opcode_length
+ size
);
6823 switch (i
.tm
.opcode_length
)
6826 *p
++ = i
.tm
.base_opcode
>> 8;
6828 *p
++ = i
.tm
.base_opcode
;
6834 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6835 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6836 (i
.bnd_prefix
!= NULL
6840 /* All jumps handled here are signed, but don't use a signed limit
6841 check for 32 and 16 bit jumps as we want to allow wrap around at
6842 4G and 64k respectively. */
6844 fixP
->fx_signed
= 1;
6848 output_interseg_jump (void)
6856 if (flag_code
== CODE_16BIT
)
6860 if (i
.prefix
[DATA_PREFIX
] != 0)
6866 if (i
.prefix
[REX_PREFIX
] != 0)
6876 if (i
.prefixes
!= 0 && !intel_syntax
)
6877 as_warn (_("skipping prefixes on this instruction"));
6879 /* 1 opcode; 2 segment; offset */
6880 p
= frag_more (prefix
+ 1 + 2 + size
);
6882 if (i
.prefix
[DATA_PREFIX
] != 0)
6883 *p
++ = DATA_PREFIX_OPCODE
;
6885 if (i
.prefix
[REX_PREFIX
] != 0)
6886 *p
++ = i
.prefix
[REX_PREFIX
];
6888 *p
++ = i
.tm
.base_opcode
;
6889 if (i
.op
[1].imms
->X_op
== O_constant
)
6891 offsetT n
= i
.op
[1].imms
->X_add_number
;
6894 && !fits_in_unsigned_word (n
)
6895 && !fits_in_signed_word (n
))
6897 as_bad (_("16-bit jump out of range"));
6900 md_number_to_chars (p
, n
, size
);
6903 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6904 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6905 if (i
.op
[0].imms
->X_op
!= O_constant
)
6906 as_bad (_("can't handle non absolute segment in `%s'"),
6908 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6914 fragS
*insn_start_frag
;
6915 offsetT insn_start_off
;
6917 /* Tie dwarf2 debug info to the address at the start of the insn.
6918 We can't do this after the insn has been output as the current
6919 frag may have been closed off. eg. by frag_var. */
6920 dwarf2_emit_insn (0);
6922 insn_start_frag
= frag_now
;
6923 insn_start_off
= frag_now_fix ();
6926 if (i
.tm
.opcode_modifier
.jump
)
6928 else if (i
.tm
.opcode_modifier
.jumpbyte
6929 || i
.tm
.opcode_modifier
.jumpdword
)
6931 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6932 output_interseg_jump ();
6935 /* Output normal instructions here. */
6939 unsigned int prefix
;
6941 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6942 don't need the explicit prefix. */
6943 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6945 switch (i
.tm
.opcode_length
)
6948 if (i
.tm
.base_opcode
& 0xff000000)
6950 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6955 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6957 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6958 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6961 if (prefix
!= REPE_PREFIX_OPCODE
6962 || (i
.prefix
[REP_PREFIX
]
6963 != REPE_PREFIX_OPCODE
))
6964 add_prefix (prefix
);
6967 add_prefix (prefix
);
6976 /* The prefix bytes. */
6977 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6979 FRAG_APPEND_1_CHAR (*q
);
6983 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6988 /* REX byte is encoded in VEX prefix. */
6992 FRAG_APPEND_1_CHAR (*q
);
6995 /* There should be no other prefixes for instructions
7000 /* For EVEX instructions i.vrex should become 0 after
7001 build_evex_prefix. For VEX instructions upper 16 registers
7002 aren't available, so VREX should be 0. */
7005 /* Now the VEX prefix. */
7006 p
= frag_more (i
.vex
.length
);
7007 for (j
= 0; j
< i
.vex
.length
; j
++)
7008 p
[j
] = i
.vex
.bytes
[j
];
7011 /* Now the opcode; be careful about word order here! */
7012 if (i
.tm
.opcode_length
== 1)
7014 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7018 switch (i
.tm
.opcode_length
)
7022 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7023 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7027 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7037 /* Put out high byte first: can't use md_number_to_chars! */
7038 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7039 *p
= i
.tm
.base_opcode
& 0xff;
7042 /* Now the modrm byte and sib byte (if present). */
7043 if (i
.tm
.opcode_modifier
.modrm
)
7045 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7048 /* If i.rm.regmem == ESP (4)
7049 && i.rm.mode != (Register mode)
7051 ==> need second modrm byte. */
7052 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7054 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7055 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7057 | i
.sib
.scale
<< 6));
7060 if (i
.disp_operands
)
7061 output_disp (insn_start_frag
, insn_start_off
);
7064 output_imm (insn_start_frag
, insn_start_off
);
7070 pi ("" /*line*/, &i
);
7072 #endif /* DEBUG386 */
7075 /* Return the size of the displacement operand N. */
7078 disp_size (unsigned int n
)
7082 /* Vec_Disp8 has to be 8bit. */
7083 if (i
.types
[n
].bitfield
.vec_disp8
)
7085 else if (i
.types
[n
].bitfield
.disp64
)
7087 else if (i
.types
[n
].bitfield
.disp8
)
7089 else if (i
.types
[n
].bitfield
.disp16
)
7094 /* Return the size of the immediate operand N. */
7097 imm_size (unsigned int n
)
7100 if (i
.types
[n
].bitfield
.imm64
)
7102 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7104 else if (i
.types
[n
].bitfield
.imm16
)
7110 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7115 for (n
= 0; n
< i
.operands
; n
++)
7117 if (i
.types
[n
].bitfield
.vec_disp8
7118 || operand_type_check (i
.types
[n
], disp
))
7120 if (i
.op
[n
].disps
->X_op
== O_constant
)
7122 int size
= disp_size (n
);
7123 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7125 if (i
.types
[n
].bitfield
.vec_disp8
)
7127 val
= offset_in_range (val
, size
);
7128 p
= frag_more (size
);
7129 md_number_to_chars (p
, val
, size
);
7133 enum bfd_reloc_code_real reloc_type
;
7134 int size
= disp_size (n
);
7135 int sign
= i
.types
[n
].bitfield
.disp32s
;
7136 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7138 /* We can't have 8 bit displacement here. */
7139 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7141 /* The PC relative address is computed relative
7142 to the instruction boundary, so in case immediate
7143 fields follows, we need to adjust the value. */
7144 if (pcrel
&& i
.imm_operands
)
7149 for (n1
= 0; n1
< i
.operands
; n1
++)
7150 if (operand_type_check (i
.types
[n1
], imm
))
7152 /* Only one immediate is allowed for PC
7153 relative address. */
7154 gas_assert (sz
== 0);
7156 i
.op
[n
].disps
->X_add_number
-= sz
;
7158 /* We should find the immediate. */
7159 gas_assert (sz
!= 0);
7162 p
= frag_more (size
);
7163 reloc_type
= reloc (size
, pcrel
, sign
,
7164 (i
.bnd_prefix
!= NULL
7168 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7169 && (((reloc_type
== BFD_RELOC_32
7170 || reloc_type
== BFD_RELOC_X86_64_32S
7171 || (reloc_type
== BFD_RELOC_64
7173 && (i
.op
[n
].disps
->X_op
== O_symbol
7174 || (i
.op
[n
].disps
->X_op
== O_add
7175 && ((symbol_get_value_expression
7176 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7178 || reloc_type
== BFD_RELOC_32_PCREL
))
7182 if (insn_start_frag
== frag_now
)
7183 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7188 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7189 for (fr
= insn_start_frag
->fr_next
;
7190 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7192 add
+= p
- frag_now
->fr_literal
;
7197 reloc_type
= BFD_RELOC_386_GOTPC
;
7198 i
.op
[n
].imms
->X_add_number
+= add
;
7200 else if (reloc_type
== BFD_RELOC_64
)
7201 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7203 /* Don't do the adjustment for x86-64, as there
7204 the pcrel addressing is relative to the _next_
7205 insn, and that is taken care of in other code. */
7206 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7208 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7209 i
.op
[n
].disps
, pcrel
, reloc_type
);
7216 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7221 for (n
= 0; n
< i
.operands
; n
++)
7223 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7224 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7227 if (operand_type_check (i
.types
[n
], imm
))
7229 if (i
.op
[n
].imms
->X_op
== O_constant
)
7231 int size
= imm_size (n
);
7234 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7236 p
= frag_more (size
);
7237 md_number_to_chars (p
, val
, size
);
7241 /* Not absolute_section.
7242 Need a 32-bit fixup (don't support 8bit
7243 non-absolute imms). Try to support other
7245 enum bfd_reloc_code_real reloc_type
;
7246 int size
= imm_size (n
);
7249 if (i
.types
[n
].bitfield
.imm32s
7250 && (i
.suffix
== QWORD_MNEM_SUFFIX
7251 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7256 p
= frag_more (size
);
7257 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7259 /* This is tough to explain. We end up with this one if we
7260 * have operands that look like
7261 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7262 * obtain the absolute address of the GOT, and it is strongly
7263 * preferable from a performance point of view to avoid using
7264 * a runtime relocation for this. The actual sequence of
7265 * instructions often look something like:
7270 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7272 * The call and pop essentially return the absolute address
7273 * of the label .L66 and store it in %ebx. The linker itself
7274 * will ultimately change the first operand of the addl so
7275 * that %ebx points to the GOT, but to keep things simple, the
7276 * .o file must have this operand set so that it generates not
7277 * the absolute address of .L66, but the absolute address of
7278 * itself. This allows the linker itself simply treat a GOTPC
7279 * relocation as asking for a pcrel offset to the GOT to be
7280 * added in, and the addend of the relocation is stored in the
7281 * operand field for the instruction itself.
7283 * Our job here is to fix the operand so that it would add
7284 * the correct offset so that %ebx would point to itself. The
7285 * thing that is tricky is that .-.L66 will point to the
7286 * beginning of the instruction, so we need to further modify
7287 * the operand so that it will point to itself. There are
7288 * other cases where you have something like:
7290 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7292 * and here no correction would be required. Internally in
7293 * the assembler we treat operands of this form as not being
7294 * pcrel since the '.' is explicitly mentioned, and I wonder
7295 * whether it would simplify matters to do it this way. Who
7296 * knows. In earlier versions of the PIC patches, the
7297 * pcrel_adjust field was used to store the correction, but
7298 * since the expression is not pcrel, I felt it would be
7299 * confusing to do it this way. */
7301 if ((reloc_type
== BFD_RELOC_32
7302 || reloc_type
== BFD_RELOC_X86_64_32S
7303 || reloc_type
== BFD_RELOC_64
)
7305 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7306 && (i
.op
[n
].imms
->X_op
== O_symbol
7307 || (i
.op
[n
].imms
->X_op
== O_add
7308 && ((symbol_get_value_expression
7309 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7314 if (insn_start_frag
== frag_now
)
7315 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7320 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7321 for (fr
= insn_start_frag
->fr_next
;
7322 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7324 add
+= p
- frag_now
->fr_literal
;
7328 reloc_type
= BFD_RELOC_386_GOTPC
;
7330 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7332 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7333 i
.op
[n
].imms
->X_add_number
+= add
;
7335 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7336 i
.op
[n
].imms
, 0, reloc_type
);
7342 /* x86_cons_fix_new is called via the expression parsing code when a
7343 reloc is needed. We use this hook to get the correct .got reloc. */
7344 static int cons_sign
= -1;
7347 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7348 expressionS
*exp
, bfd_reloc_code_real_type r
)
7350 r
= reloc (len
, 0, cons_sign
, 0, r
);
7353 if (exp
->X_op
== O_secrel
)
7355 exp
->X_op
= O_symbol
;
7356 r
= BFD_RELOC_32_SECREL
;
7360 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7363 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7364 purpose of the `.dc.a' internal pseudo-op. */
7367 x86_address_bytes (void)
7369 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7371 return stdoutput
->arch_info
->bits_per_address
/ 8;
7374 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7376 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7378 /* Parse operands of the form
7379 <symbol>@GOTOFF+<nnn>
7380 and similar .plt or .got references.
7382 If we find one, set up the correct relocation in RELOC and copy the
7383 input string, minus the `@GOTOFF' into a malloc'd buffer for
7384 parsing by the calling routine. Return this buffer, and if ADJUST
7385 is non-null set it to the length of the string we removed from the
7386 input line. Otherwise return NULL. */
7388 lex_got (enum bfd_reloc_code_real
*rel
,
7390 i386_operand_type
*types
,
7393 /* Some of the relocations depend on the size of what field is to
7394 be relocated. But in our callers i386_immediate and i386_displacement
7395 we don't yet know the operand size (this will be set by insn
7396 matching). Hence we record the word32 relocation here,
7397 and adjust the reloc according to the real size in reloc(). */
7398 static const struct {
7401 const enum bfd_reloc_code_real rel
[2];
7402 const i386_operand_type types64
;
7404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7405 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7407 OPERAND_TYPE_IMM32_64
},
7409 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7410 BFD_RELOC_X86_64_PLTOFF64
},
7411 OPERAND_TYPE_IMM64
},
7412 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7413 BFD_RELOC_X86_64_PLT32
},
7414 OPERAND_TYPE_IMM32_32S_DISP32
},
7415 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7416 BFD_RELOC_X86_64_GOTPLT64
},
7417 OPERAND_TYPE_IMM64_DISP64
},
7418 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7419 BFD_RELOC_X86_64_GOTOFF64
},
7420 OPERAND_TYPE_IMM64_DISP64
},
7421 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7422 BFD_RELOC_X86_64_GOTPCREL
},
7423 OPERAND_TYPE_IMM32_32S_DISP32
},
7424 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7425 BFD_RELOC_X86_64_TLSGD
},
7426 OPERAND_TYPE_IMM32_32S_DISP32
},
7427 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7428 _dummy_first_bfd_reloc_code_real
},
7429 OPERAND_TYPE_NONE
},
7430 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7431 BFD_RELOC_X86_64_TLSLD
},
7432 OPERAND_TYPE_IMM32_32S_DISP32
},
7433 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7434 BFD_RELOC_X86_64_GOTTPOFF
},
7435 OPERAND_TYPE_IMM32_32S_DISP32
},
7436 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7437 BFD_RELOC_X86_64_TPOFF32
},
7438 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7439 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7440 _dummy_first_bfd_reloc_code_real
},
7441 OPERAND_TYPE_NONE
},
7442 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7443 BFD_RELOC_X86_64_DTPOFF32
},
7444 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7445 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7446 _dummy_first_bfd_reloc_code_real
},
7447 OPERAND_TYPE_NONE
},
7448 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7449 _dummy_first_bfd_reloc_code_real
},
7450 OPERAND_TYPE_NONE
},
7451 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7452 BFD_RELOC_X86_64_GOT32
},
7453 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7454 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7455 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7456 OPERAND_TYPE_IMM32_32S_DISP32
},
7457 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7458 BFD_RELOC_X86_64_TLSDESC_CALL
},
7459 OPERAND_TYPE_IMM32_32S_DISP32
},
7464 #if defined (OBJ_MAYBE_ELF)
7469 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7470 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7473 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7475 int len
= gotrel
[j
].len
;
7476 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7478 if (gotrel
[j
].rel
[object_64bit
] != 0)
7481 char *tmpbuf
, *past_reloc
;
7483 *rel
= gotrel
[j
].rel
[object_64bit
];
7487 if (flag_code
!= CODE_64BIT
)
7489 types
->bitfield
.imm32
= 1;
7490 types
->bitfield
.disp32
= 1;
7493 *types
= gotrel
[j
].types64
;
7496 if (j
!= 0 && GOT_symbol
== NULL
)
7497 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7499 /* The length of the first part of our input line. */
7500 first
= cp
- input_line_pointer
;
7502 /* The second part goes from after the reloc token until
7503 (and including) an end_of_line char or comma. */
7504 past_reloc
= cp
+ 1 + len
;
7506 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7508 second
= cp
+ 1 - past_reloc
;
7510 /* Allocate and copy string. The trailing NUL shouldn't
7511 be necessary, but be safe. */
7512 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7513 memcpy (tmpbuf
, input_line_pointer
, first
);
7514 if (second
!= 0 && *past_reloc
!= ' ')
7515 /* Replace the relocation token with ' ', so that
7516 errors like foo@GOTOFF1 will be detected. */
7517 tmpbuf
[first
++] = ' ';
7519 /* Increment length by 1 if the relocation token is
7524 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7525 tmpbuf
[first
+ second
] = '\0';
7526 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7527 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7531 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7532 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7537 /* Might be a symbol version string. Don't as_bad here. */
7546 /* Parse operands of the form
7547 <symbol>@SECREL32+<nnn>
7549 If we find one, set up the correct relocation in RELOC and copy the
7550 input string, minus the `@SECREL32' into a malloc'd buffer for
7551 parsing by the calling routine. Return this buffer, and if ADJUST
7552 is non-null set it to the length of the string we removed from the
7553 input line. Otherwise return NULL.
7555 This function is copied from the ELF version above adjusted for PE targets. */
7558 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7559 int *adjust ATTRIBUTE_UNUSED
,
7560 i386_operand_type
*types
,
7561 int bnd_prefix ATTRIBUTE_UNUSED
)
7567 const enum bfd_reloc_code_real rel
[2];
7568 const i386_operand_type types64
;
7572 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7573 BFD_RELOC_32_SECREL
},
7574 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7580 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7581 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7584 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7586 int len
= gotrel
[j
].len
;
7588 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7590 if (gotrel
[j
].rel
[object_64bit
] != 0)
7593 char *tmpbuf
, *past_reloc
;
7595 *rel
= gotrel
[j
].rel
[object_64bit
];
7601 if (flag_code
!= CODE_64BIT
)
7603 types
->bitfield
.imm32
= 1;
7604 types
->bitfield
.disp32
= 1;
7607 *types
= gotrel
[j
].types64
;
7610 /* The length of the first part of our input line. */
7611 first
= cp
- input_line_pointer
;
7613 /* The second part goes from after the reloc token until
7614 (and including) an end_of_line char or comma. */
7615 past_reloc
= cp
+ 1 + len
;
7617 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7619 second
= cp
+ 1 - past_reloc
;
7621 /* Allocate and copy string. The trailing NUL shouldn't
7622 be necessary, but be safe. */
7623 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7624 memcpy (tmpbuf
, input_line_pointer
, first
);
7625 if (second
!= 0 && *past_reloc
!= ' ')
7626 /* Replace the relocation token with ' ', so that
7627 errors like foo@SECLREL321 will be detected. */
7628 tmpbuf
[first
++] = ' ';
7629 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7630 tmpbuf
[first
+ second
] = '\0';
7634 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7635 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7640 /* Might be a symbol version string. Don't as_bad here. */
7646 bfd_reloc_code_real_type
7647 x86_cons (expressionS
*exp
, int size
)
7649 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7651 intel_syntax
= -intel_syntax
;
7654 if (size
== 4 || (object_64bit
&& size
== 8))
7656 /* Handle @GOTOFF and the like in an expression. */
7658 char *gotfree_input_line
;
7661 save
= input_line_pointer
;
7662 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7663 if (gotfree_input_line
)
7664 input_line_pointer
= gotfree_input_line
;
7668 if (gotfree_input_line
)
7670 /* expression () has merrily parsed up to the end of line,
7671 or a comma - in the wrong buffer. Transfer how far
7672 input_line_pointer has moved to the right buffer. */
7673 input_line_pointer
= (save
7674 + (input_line_pointer
- gotfree_input_line
)
7676 free (gotfree_input_line
);
7677 if (exp
->X_op
== O_constant
7678 || exp
->X_op
== O_absent
7679 || exp
->X_op
== O_illegal
7680 || exp
->X_op
== O_register
7681 || exp
->X_op
== O_big
)
7683 char c
= *input_line_pointer
;
7684 *input_line_pointer
= 0;
7685 as_bad (_("missing or invalid expression `%s'"), save
);
7686 *input_line_pointer
= c
;
7693 intel_syntax
= -intel_syntax
;
7696 i386_intel_simplify (exp
);
7702 signed_cons (int size
)
7704 if (flag_code
== CODE_64BIT
)
7712 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7719 if (exp
.X_op
== O_symbol
)
7720 exp
.X_op
= O_secrel
;
7722 emit_expr (&exp
, 4);
7724 while (*input_line_pointer
++ == ',');
7726 input_line_pointer
--;
7727 demand_empty_rest_of_line ();
7731 /* Handle Vector operations. */
7734 check_VecOperations (char *op_string
, char *op_end
)
7736 const reg_entry
*mask
;
7741 && (op_end
== NULL
|| op_string
< op_end
))
7744 if (*op_string
== '{')
7748 /* Check broadcasts. */
7749 if (strncmp (op_string
, "1to", 3) == 0)
7754 goto duplicated_vec_op
;
7757 if (*op_string
== '8')
7758 bcst_type
= BROADCAST_1TO8
;
7759 else if (*op_string
== '4')
7760 bcst_type
= BROADCAST_1TO4
;
7761 else if (*op_string
== '2')
7762 bcst_type
= BROADCAST_1TO2
;
7763 else if (*op_string
== '1'
7764 && *(op_string
+1) == '6')
7766 bcst_type
= BROADCAST_1TO16
;
7771 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7776 broadcast_op
.type
= bcst_type
;
7777 broadcast_op
.operand
= this_operand
;
7778 i
.broadcast
= &broadcast_op
;
7780 /* Check masking operation. */
7781 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7783 /* k0 can't be used for write mask. */
7784 if (mask
->reg_num
== 0)
7786 as_bad (_("`%s' can't be used for write mask"),
7793 mask_op
.mask
= mask
;
7794 mask_op
.zeroing
= 0;
7795 mask_op
.operand
= this_operand
;
7801 goto duplicated_vec_op
;
7803 i
.mask
->mask
= mask
;
7805 /* Only "{z}" is allowed here. No need to check
7806 zeroing mask explicitly. */
7807 if (i
.mask
->operand
!= this_operand
)
7809 as_bad (_("invalid write mask `%s'"), saved
);
7816 /* Check zeroing-flag for masking operation. */
7817 else if (*op_string
== 'z')
7821 mask_op
.mask
= NULL
;
7822 mask_op
.zeroing
= 1;
7823 mask_op
.operand
= this_operand
;
7828 if (i
.mask
->zeroing
)
7831 as_bad (_("duplicated `%s'"), saved
);
7835 i
.mask
->zeroing
= 1;
7837 /* Only "{%k}" is allowed here. No need to check mask
7838 register explicitly. */
7839 if (i
.mask
->operand
!= this_operand
)
7841 as_bad (_("invalid zeroing-masking `%s'"),
7850 goto unknown_vec_op
;
7852 if (*op_string
!= '}')
7854 as_bad (_("missing `}' in `%s'"), saved
);
7861 /* We don't know this one. */
7862 as_bad (_("unknown vector operation: `%s'"), saved
);
7870 i386_immediate (char *imm_start
)
7872 char *save_input_line_pointer
;
7873 char *gotfree_input_line
;
7876 i386_operand_type types
;
7878 operand_type_set (&types
, ~0);
7880 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7882 as_bad (_("at most %d immediate operands are allowed"),
7883 MAX_IMMEDIATE_OPERANDS
);
7887 exp
= &im_expressions
[i
.imm_operands
++];
7888 i
.op
[this_operand
].imms
= exp
;
7890 if (is_space_char (*imm_start
))
7893 save_input_line_pointer
= input_line_pointer
;
7894 input_line_pointer
= imm_start
;
7896 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7897 (i
.bnd_prefix
!= NULL
7898 || add_bnd_prefix
));
7899 if (gotfree_input_line
)
7900 input_line_pointer
= gotfree_input_line
;
7902 exp_seg
= expression (exp
);
7906 /* Handle vector operations. */
7907 if (*input_line_pointer
== '{')
7909 input_line_pointer
= check_VecOperations (input_line_pointer
,
7911 if (input_line_pointer
== NULL
)
7915 if (*input_line_pointer
)
7916 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7918 input_line_pointer
= save_input_line_pointer
;
7919 if (gotfree_input_line
)
7921 free (gotfree_input_line
);
7923 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7924 exp
->X_op
= O_illegal
;
7927 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7931 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7932 i386_operand_type types
, const char *imm_start
)
7934 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7937 as_bad (_("missing or invalid immediate expression `%s'"),
7941 else if (exp
->X_op
== O_constant
)
7943 /* Size it properly later. */
7944 i
.types
[this_operand
].bitfield
.imm64
= 1;
7945 /* If not 64bit, sign extend val. */
7946 if (flag_code
!= CODE_64BIT
7947 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7949 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7951 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7952 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7953 && exp_seg
!= absolute_section
7954 && exp_seg
!= text_section
7955 && exp_seg
!= data_section
7956 && exp_seg
!= bss_section
7957 && exp_seg
!= undefined_section
7958 && !bfd_is_com_section (exp_seg
))
7960 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7964 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7967 as_bad (_("illegal immediate register operand %s"), imm_start
);
7972 /* This is an address. The size of the address will be
7973 determined later, depending on destination register,
7974 suffix, or the default for the section. */
7975 i
.types
[this_operand
].bitfield
.imm8
= 1;
7976 i
.types
[this_operand
].bitfield
.imm16
= 1;
7977 i
.types
[this_operand
].bitfield
.imm32
= 1;
7978 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7979 i
.types
[this_operand
].bitfield
.imm64
= 1;
7980 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7988 i386_scale (char *scale
)
7991 char *save
= input_line_pointer
;
7993 input_line_pointer
= scale
;
7994 val
= get_absolute_expression ();
7999 i
.log2_scale_factor
= 0;
8002 i
.log2_scale_factor
= 1;
8005 i
.log2_scale_factor
= 2;
8008 i
.log2_scale_factor
= 3;
8012 char sep
= *input_line_pointer
;
8014 *input_line_pointer
= '\0';
8015 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8017 *input_line_pointer
= sep
;
8018 input_line_pointer
= save
;
8022 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8024 as_warn (_("scale factor of %d without an index register"),
8025 1 << i
.log2_scale_factor
);
8026 i
.log2_scale_factor
= 0;
8028 scale
= input_line_pointer
;
8029 input_line_pointer
= save
;
8034 i386_displacement (char *disp_start
, char *disp_end
)
8038 char *save_input_line_pointer
;
8039 char *gotfree_input_line
;
8041 i386_operand_type bigdisp
, types
= anydisp
;
8044 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8046 as_bad (_("at most %d displacement operands are allowed"),
8047 MAX_MEMORY_OPERANDS
);
8051 operand_type_set (&bigdisp
, 0);
8052 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8053 || (!current_templates
->start
->opcode_modifier
.jump
8054 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8056 bigdisp
.bitfield
.disp32
= 1;
8057 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8058 if (flag_code
== CODE_64BIT
)
8062 bigdisp
.bitfield
.disp32s
= 1;
8063 bigdisp
.bitfield
.disp64
= 1;
8066 else if ((flag_code
== CODE_16BIT
) ^ override
)
8068 bigdisp
.bitfield
.disp32
= 0;
8069 bigdisp
.bitfield
.disp16
= 1;
8074 /* For PC-relative branches, the width of the displacement
8075 is dependent upon data size, not address size. */
8076 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8077 if (flag_code
== CODE_64BIT
)
8079 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8080 bigdisp
.bitfield
.disp16
= 1;
8083 bigdisp
.bitfield
.disp32
= 1;
8084 bigdisp
.bitfield
.disp32s
= 1;
8090 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8092 : LONG_MNEM_SUFFIX
));
8093 bigdisp
.bitfield
.disp32
= 1;
8094 if ((flag_code
== CODE_16BIT
) ^ override
)
8096 bigdisp
.bitfield
.disp32
= 0;
8097 bigdisp
.bitfield
.disp16
= 1;
8101 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8104 exp
= &disp_expressions
[i
.disp_operands
];
8105 i
.op
[this_operand
].disps
= exp
;
8107 save_input_line_pointer
= input_line_pointer
;
8108 input_line_pointer
= disp_start
;
8109 END_STRING_AND_SAVE (disp_end
);
8111 #ifndef GCC_ASM_O_HACK
8112 #define GCC_ASM_O_HACK 0
8115 END_STRING_AND_SAVE (disp_end
+ 1);
8116 if (i
.types
[this_operand
].bitfield
.baseIndex
8117 && displacement_string_end
[-1] == '+')
8119 /* This hack is to avoid a warning when using the "o"
8120 constraint within gcc asm statements.
8123 #define _set_tssldt_desc(n,addr,limit,type) \
8124 __asm__ __volatile__ ( \
8126 "movw %w1,2+%0\n\t" \
8128 "movb %b1,4+%0\n\t" \
8129 "movb %4,5+%0\n\t" \
8130 "movb $0,6+%0\n\t" \
8131 "movb %h1,7+%0\n\t" \
8133 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8135 This works great except that the output assembler ends
8136 up looking a bit weird if it turns out that there is
8137 no offset. You end up producing code that looks like:
8150 So here we provide the missing zero. */
8152 *displacement_string_end
= '0';
8155 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8156 (i
.bnd_prefix
!= NULL
8157 || add_bnd_prefix
));
8158 if (gotfree_input_line
)
8159 input_line_pointer
= gotfree_input_line
;
8161 exp_seg
= expression (exp
);
8164 if (*input_line_pointer
)
8165 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8167 RESTORE_END_STRING (disp_end
+ 1);
8169 input_line_pointer
= save_input_line_pointer
;
8170 if (gotfree_input_line
)
8172 free (gotfree_input_line
);
8174 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8175 exp
->X_op
= O_illegal
;
8178 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8180 RESTORE_END_STRING (disp_end
);
8186 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8187 i386_operand_type types
, const char *disp_start
)
8189 i386_operand_type bigdisp
;
8192 /* We do this to make sure that the section symbol is in
8193 the symbol table. We will ultimately change the relocation
8194 to be relative to the beginning of the section. */
8195 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8196 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8197 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8199 if (exp
->X_op
!= O_symbol
)
8202 if (S_IS_LOCAL (exp
->X_add_symbol
)
8203 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8204 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8205 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8206 exp
->X_op
= O_subtract
;
8207 exp
->X_op_symbol
= GOT_symbol
;
8208 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8209 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8210 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8211 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8213 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8216 else if (exp
->X_op
== O_absent
8217 || exp
->X_op
== O_illegal
8218 || exp
->X_op
== O_big
)
8221 as_bad (_("missing or invalid displacement expression `%s'"),
8226 else if (flag_code
== CODE_64BIT
8227 && !i
.prefix
[ADDR_PREFIX
]
8228 && exp
->X_op
== O_constant
)
8230 /* Since displacement is signed extended to 64bit, don't allow
8231 disp32 and turn off disp32s if they are out of range. */
8232 i
.types
[this_operand
].bitfield
.disp32
= 0;
8233 if (!fits_in_signed_long (exp
->X_add_number
))
8235 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8236 if (i
.types
[this_operand
].bitfield
.baseindex
)
8238 as_bad (_("0x%lx out range of signed 32bit displacement"),
8239 (long) exp
->X_add_number
);
8245 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8246 else if (exp
->X_op
!= O_constant
8247 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8248 && exp_seg
!= absolute_section
8249 && exp_seg
!= text_section
8250 && exp_seg
!= data_section
8251 && exp_seg
!= bss_section
8252 && exp_seg
!= undefined_section
8253 && !bfd_is_com_section (exp_seg
))
8255 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8260 /* Check if this is a displacement only operand. */
8261 bigdisp
= i
.types
[this_operand
];
8262 bigdisp
.bitfield
.disp8
= 0;
8263 bigdisp
.bitfield
.disp16
= 0;
8264 bigdisp
.bitfield
.disp32
= 0;
8265 bigdisp
.bitfield
.disp32s
= 0;
8266 bigdisp
.bitfield
.disp64
= 0;
8267 if (operand_type_all_zero (&bigdisp
))
8268 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8274 /* Make sure the memory operand we've been dealt is valid.
8275 Return 1 on success, 0 on a failure. */
8278 i386_index_check (const char *operand_string
)
8280 const char *kind
= "base/index";
8281 enum flag_code addr_mode
;
8283 if (i
.prefix
[ADDR_PREFIX
])
8284 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8287 addr_mode
= flag_code
;
8289 #if INFER_ADDR_PREFIX
8290 if (i
.mem_operands
== 0)
8292 /* Infer address prefix from the first memory operand. */
8293 const reg_entry
*addr_reg
= i
.base_reg
;
8295 if (addr_reg
== NULL
)
8296 addr_reg
= i
.index_reg
;
8300 if (addr_reg
->reg_num
== RegEip
8301 || addr_reg
->reg_num
== RegEiz
8302 || addr_reg
->reg_type
.bitfield
.reg32
)
8303 addr_mode
= CODE_32BIT
;
8304 else if (flag_code
!= CODE_64BIT
8305 && addr_reg
->reg_type
.bitfield
.reg16
)
8306 addr_mode
= CODE_16BIT
;
8308 if (addr_mode
!= flag_code
)
8310 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8312 /* Change the size of any displacement too. At most one
8313 of Disp16 or Disp32 is set.
8314 FIXME. There doesn't seem to be any real need for
8315 separate Disp16 and Disp32 flags. The same goes for
8316 Imm16 and Imm32. Removing them would probably clean
8317 up the code quite a lot. */
8318 if (flag_code
!= CODE_64BIT
8319 && (i
.types
[this_operand
].bitfield
.disp16
8320 || i
.types
[this_operand
].bitfield
.disp32
))
8321 i
.types
[this_operand
]
8322 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8329 if (current_templates
->start
->opcode_modifier
.isstring
8330 && !current_templates
->start
->opcode_modifier
.immext
8331 && (current_templates
->end
[-1].opcode_modifier
.isstring
8334 /* Memory operands of string insns are special in that they only allow
8335 a single register (rDI, rSI, or rBX) as their memory address. */
8336 const reg_entry
*expected_reg
;
8337 static const char *di_si
[][2] =
8343 static const char *bx
[] = { "ebx", "bx", "rbx" };
8345 kind
= "string address";
8347 if (current_templates
->start
->opcode_modifier
.w
)
8349 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8351 if (!type
.bitfield
.baseindex
8352 || ((!i
.mem_operands
!= !intel_syntax
)
8353 && current_templates
->end
[-1].operand_types
[1]
8354 .bitfield
.baseindex
))
8355 type
= current_templates
->end
[-1].operand_types
[1];
8356 expected_reg
= hash_find (reg_hash
,
8357 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8361 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8363 if (i
.base_reg
!= expected_reg
8365 || operand_type_check (i
.types
[this_operand
], disp
))
8367 /* The second memory operand must have the same size as
8371 && !((addr_mode
== CODE_64BIT
8372 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8373 || (addr_mode
== CODE_32BIT
8374 ? i
.base_reg
->reg_type
.bitfield
.reg32
8375 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8378 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8380 intel_syntax
? '[' : '(',
8382 expected_reg
->reg_name
,
8383 intel_syntax
? ']' : ')');
8390 as_bad (_("`%s' is not a valid %s expression"),
8391 operand_string
, kind
);
8396 if (addr_mode
!= CODE_16BIT
)
8398 /* 32-bit/64-bit checks. */
8400 && (addr_mode
== CODE_64BIT
8401 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8402 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8404 || (i
.base_reg
->reg_num
8405 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8407 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8408 && !i
.index_reg
->reg_type
.bitfield
.regymm
8409 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8410 && ((addr_mode
== CODE_64BIT
8411 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8412 || i
.index_reg
->reg_num
== RegRiz
)
8413 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8414 || i
.index_reg
->reg_num
== RegEiz
))
8415 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8420 /* 16-bit checks. */
8422 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8423 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8425 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8426 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8428 && i
.base_reg
->reg_num
< 6
8429 && i
.index_reg
->reg_num
>= 6
8430 && i
.log2_scale_factor
== 0))))
8437 /* Handle vector immediates. */
8440 RC_SAE_immediate (const char *imm_start
)
8442 unsigned int match_found
, j
;
8443 const char *pstr
= imm_start
;
8451 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8453 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8457 rc_op
.type
= RC_NamesTable
[j
].type
;
8458 rc_op
.operand
= this_operand
;
8459 i
.rounding
= &rc_op
;
8463 as_bad (_("duplicated `%s'"), imm_start
);
8466 pstr
+= RC_NamesTable
[j
].len
;
8476 as_bad (_("Missing '}': '%s'"), imm_start
);
8479 /* RC/SAE immediate string should contain nothing more. */;
8482 as_bad (_("Junk after '}': '%s'"), imm_start
);
8486 exp
= &im_expressions
[i
.imm_operands
++];
8487 i
.op
[this_operand
].imms
= exp
;
8489 exp
->X_op
= O_constant
;
8490 exp
->X_add_number
= 0;
8491 exp
->X_add_symbol
= (symbolS
*) 0;
8492 exp
->X_op_symbol
= (symbolS
*) 0;
8494 i
.types
[this_operand
].bitfield
.imm8
= 1;
8498 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8502 i386_att_operand (char *operand_string
)
8506 char *op_string
= operand_string
;
8508 if (is_space_char (*op_string
))
8511 /* We check for an absolute prefix (differentiating,
8512 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8513 if (*op_string
== ABSOLUTE_PREFIX
)
8516 if (is_space_char (*op_string
))
8518 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8521 /* Check if operand is a register. */
8522 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8524 i386_operand_type temp
;
8526 /* Check for a segment override by searching for ':' after a
8527 segment register. */
8529 if (is_space_char (*op_string
))
8531 if (*op_string
== ':'
8532 && (r
->reg_type
.bitfield
.sreg2
8533 || r
->reg_type
.bitfield
.sreg3
))
8538 i
.seg
[i
.mem_operands
] = &es
;
8541 i
.seg
[i
.mem_operands
] = &cs
;
8544 i
.seg
[i
.mem_operands
] = &ss
;
8547 i
.seg
[i
.mem_operands
] = &ds
;
8550 i
.seg
[i
.mem_operands
] = &fs
;
8553 i
.seg
[i
.mem_operands
] = &gs
;
8557 /* Skip the ':' and whitespace. */
8559 if (is_space_char (*op_string
))
8562 if (!is_digit_char (*op_string
)
8563 && !is_identifier_char (*op_string
)
8564 && *op_string
!= '('
8565 && *op_string
!= ABSOLUTE_PREFIX
)
8567 as_bad (_("bad memory operand `%s'"), op_string
);
8570 /* Handle case of %es:*foo. */
8571 if (*op_string
== ABSOLUTE_PREFIX
)
8574 if (is_space_char (*op_string
))
8576 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8578 goto do_memory_reference
;
8581 /* Handle vector operations. */
8582 if (*op_string
== '{')
8584 op_string
= check_VecOperations (op_string
, NULL
);
8585 if (op_string
== NULL
)
8591 as_bad (_("junk `%s' after register"), op_string
);
8595 temp
.bitfield
.baseindex
= 0;
8596 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8598 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8599 i
.op
[this_operand
].regs
= r
;
8602 else if (*op_string
== REGISTER_PREFIX
)
8604 as_bad (_("bad register name `%s'"), op_string
);
8607 else if (*op_string
== IMMEDIATE_PREFIX
)
8610 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8612 as_bad (_("immediate operand illegal with absolute jump"));
8615 if (!i386_immediate (op_string
))
8618 else if (RC_SAE_immediate (operand_string
))
8620 /* If it is a RC or SAE immediate, do nothing. */
8623 else if (is_digit_char (*op_string
)
8624 || is_identifier_char (*op_string
)
8625 || *op_string
== '(')
8627 /* This is a memory reference of some sort. */
8630 /* Start and end of displacement string expression (if found). */
8631 char *displacement_string_start
;
8632 char *displacement_string_end
;
8635 do_memory_reference
:
8636 if ((i
.mem_operands
== 1
8637 && !current_templates
->start
->opcode_modifier
.isstring
)
8638 || i
.mem_operands
== 2)
8640 as_bad (_("too many memory references for `%s'"),
8641 current_templates
->start
->name
);
8645 /* Check for base index form. We detect the base index form by
8646 looking for an ')' at the end of the operand, searching
8647 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8649 base_string
= op_string
+ strlen (op_string
);
8651 /* Handle vector operations. */
8652 vop_start
= strchr (op_string
, '{');
8653 if (vop_start
&& vop_start
< base_string
)
8655 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8657 base_string
= vop_start
;
8661 if (is_space_char (*base_string
))
8664 /* If we only have a displacement, set-up for it to be parsed later. */
8665 displacement_string_start
= op_string
;
8666 displacement_string_end
= base_string
+ 1;
8668 if (*base_string
== ')')
8671 unsigned int parens_balanced
= 1;
8672 /* We've already checked that the number of left & right ()'s are
8673 equal, so this loop will not be infinite. */
8677 if (*base_string
== ')')
8679 if (*base_string
== '(')
8682 while (parens_balanced
);
8684 temp_string
= base_string
;
8686 /* Skip past '(' and whitespace. */
8688 if (is_space_char (*base_string
))
8691 if (*base_string
== ','
8692 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8695 displacement_string_end
= temp_string
;
8697 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8701 base_string
= end_op
;
8702 if (is_space_char (*base_string
))
8706 /* There may be an index reg or scale factor here. */
8707 if (*base_string
== ',')
8710 if (is_space_char (*base_string
))
8713 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8716 base_string
= end_op
;
8717 if (is_space_char (*base_string
))
8719 if (*base_string
== ',')
8722 if (is_space_char (*base_string
))
8725 else if (*base_string
!= ')')
8727 as_bad (_("expecting `,' or `)' "
8728 "after index register in `%s'"),
8733 else if (*base_string
== REGISTER_PREFIX
)
8735 end_op
= strchr (base_string
, ',');
8738 as_bad (_("bad register name `%s'"), base_string
);
8742 /* Check for scale factor. */
8743 if (*base_string
!= ')')
8745 char *end_scale
= i386_scale (base_string
);
8750 base_string
= end_scale
;
8751 if (is_space_char (*base_string
))
8753 if (*base_string
!= ')')
8755 as_bad (_("expecting `)' "
8756 "after scale factor in `%s'"),
8761 else if (!i
.index_reg
)
8763 as_bad (_("expecting index register or scale factor "
8764 "after `,'; got '%c'"),
8769 else if (*base_string
!= ')')
8771 as_bad (_("expecting `,' or `)' "
8772 "after base register in `%s'"),
8777 else if (*base_string
== REGISTER_PREFIX
)
8779 end_op
= strchr (base_string
, ',');
8782 as_bad (_("bad register name `%s'"), base_string
);
8787 /* If there's an expression beginning the operand, parse it,
8788 assuming displacement_string_start and
8789 displacement_string_end are meaningful. */
8790 if (displacement_string_start
!= displacement_string_end
)
8792 if (!i386_displacement (displacement_string_start
,
8793 displacement_string_end
))
8797 /* Special case for (%dx) while doing input/output op. */
8799 && operand_type_equal (&i
.base_reg
->reg_type
,
8800 ®16_inoutportreg
)
8802 && i
.log2_scale_factor
== 0
8803 && i
.seg
[i
.mem_operands
] == 0
8804 && !operand_type_check (i
.types
[this_operand
], disp
))
8806 i
.types
[this_operand
] = inoutportreg
;
8810 if (i386_index_check (operand_string
) == 0)
8812 i
.types
[this_operand
].bitfield
.mem
= 1;
8817 /* It's not a memory operand; argh! */
8818 as_bad (_("invalid char %s beginning operand %d `%s'"),
8819 output_invalid (*op_string
),
8824 return 1; /* Normal return. */
8827 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8828 that an rs_machine_dependent frag may reach. */
8831 i386_frag_max_var (fragS
*frag
)
8833 /* The only relaxable frags are for jumps.
8834 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8835 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8836 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8839 /* md_estimate_size_before_relax()
8841 Called just before relax() for rs_machine_dependent frags. The x86
8842 assembler uses these frags to handle variable size jump
8845 Any symbol that is now undefined will not become defined.
8846 Return the correct fr_subtype in the frag.
8847 Return the initial "guess for variable size of frag" to caller.
8848 The guess is actually the growth beyond the fixed part. Whatever
8849 we do to grow the fixed or variable part contributes to our
8853 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8855 /* We've already got fragP->fr_subtype right; all we have to do is
8856 check for un-relaxable symbols. On an ELF system, we can't relax
8857 an externally visible symbol, because it may be overridden by a
8859 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8862 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8863 || S_IS_WEAK (fragP
->fr_symbol
)
8864 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8865 & BSF_GNU_INDIRECT_FUNCTION
))))
8867 #if defined (OBJ_COFF) && defined (TE_PE)
8868 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8869 && S_IS_WEAK (fragP
->fr_symbol
))
8873 /* Symbol is undefined in this segment, or we need to keep a
8874 reloc so that weak symbols can be overridden. */
8875 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8876 enum bfd_reloc_code_real reloc_type
;
8877 unsigned char *opcode
;
8880 if (fragP
->fr_var
!= NO_RELOC
)
8881 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8883 reloc_type
= BFD_RELOC_16_PCREL
;
8885 reloc_type
= BFD_RELOC_32_PCREL
;
8887 old_fr_fix
= fragP
->fr_fix
;
8888 opcode
= (unsigned char *) fragP
->fr_opcode
;
8890 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8893 /* Make jmp (0xeb) a (d)word displacement jump. */
8895 fragP
->fr_fix
+= size
;
8896 fix_new (fragP
, old_fr_fix
, size
,
8898 fragP
->fr_offset
, 1,
8904 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8906 /* Negate the condition, and branch past an
8907 unconditional jump. */
8910 /* Insert an unconditional jump. */
8912 /* We added two extra opcode bytes, and have a two byte
8914 fragP
->fr_fix
+= 2 + 2;
8915 fix_new (fragP
, old_fr_fix
+ 2, 2,
8917 fragP
->fr_offset
, 1,
8924 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8929 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8931 fragP
->fr_offset
, 1,
8933 fixP
->fx_signed
= 1;
8937 /* This changes the byte-displacement jump 0x7N
8938 to the (d)word-displacement jump 0x0f,0x8N. */
8939 opcode
[1] = opcode
[0] + 0x10;
8940 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8941 /* We've added an opcode byte. */
8942 fragP
->fr_fix
+= 1 + size
;
8943 fix_new (fragP
, old_fr_fix
+ 1, size
,
8945 fragP
->fr_offset
, 1,
8950 BAD_CASE (fragP
->fr_subtype
);
8954 return fragP
->fr_fix
- old_fr_fix
;
8957 /* Guess size depending on current relax state. Initially the relax
8958 state will correspond to a short jump and we return 1, because
8959 the variable part of the frag (the branch offset) is one byte
8960 long. However, we can relax a section more than once and in that
8961 case we must either set fr_subtype back to the unrelaxed state,
8962 or return the value for the appropriate branch. */
8963 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8966 /* Called after relax() is finished.
8968 In: Address of frag.
8969 fr_type == rs_machine_dependent.
8970 fr_subtype is what the address relaxed to.
8972 Out: Any fixSs and constants are set up.
8973 Caller will turn frag into a ".space 0". */
8976 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8979 unsigned char *opcode
;
8980 unsigned char *where_to_put_displacement
= NULL
;
8981 offsetT target_address
;
8982 offsetT opcode_address
;
8983 unsigned int extension
= 0;
8984 offsetT displacement_from_opcode_start
;
8986 opcode
= (unsigned char *) fragP
->fr_opcode
;
8988 /* Address we want to reach in file space. */
8989 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8991 /* Address opcode resides at in file space. */
8992 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8994 /* Displacement from opcode start to fill into instruction. */
8995 displacement_from_opcode_start
= target_address
- opcode_address
;
8997 if ((fragP
->fr_subtype
& BIG
) == 0)
8999 /* Don't have to change opcode. */
9000 extension
= 1; /* 1 opcode + 1 displacement */
9001 where_to_put_displacement
= &opcode
[1];
9005 if (no_cond_jump_promotion
9006 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9007 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9008 _("long jump required"));
9010 switch (fragP
->fr_subtype
)
9012 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9013 extension
= 4; /* 1 opcode + 4 displacement */
9015 where_to_put_displacement
= &opcode
[1];
9018 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9019 extension
= 2; /* 1 opcode + 2 displacement */
9021 where_to_put_displacement
= &opcode
[1];
9024 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9025 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9026 extension
= 5; /* 2 opcode + 4 displacement */
9027 opcode
[1] = opcode
[0] + 0x10;
9028 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9029 where_to_put_displacement
= &opcode
[2];
9032 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9033 extension
= 3; /* 2 opcode + 2 displacement */
9034 opcode
[1] = opcode
[0] + 0x10;
9035 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9036 where_to_put_displacement
= &opcode
[2];
9039 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9044 where_to_put_displacement
= &opcode
[3];
9048 BAD_CASE (fragP
->fr_subtype
);
9053 /* If size if less then four we are sure that the operand fits,
9054 but if it's 4, then it could be that the displacement is larger
9056 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9058 && ((addressT
) (displacement_from_opcode_start
- extension
9059 + ((addressT
) 1 << 31))
9060 > (((addressT
) 2 << 31) - 1)))
9062 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9063 _("jump target out of range"));
9064 /* Make us emit 0. */
9065 displacement_from_opcode_start
= extension
;
9067 /* Now put displacement after opcode. */
9068 md_number_to_chars ((char *) where_to_put_displacement
,
9069 (valueT
) (displacement_from_opcode_start
- extension
),
9070 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9071 fragP
->fr_fix
+= extension
;
9074 /* Apply a fixup (fixP) to segment data, once it has been determined
9075 by our caller that we have all the info we need to fix it up.
9077 Parameter valP is the pointer to the value of the bits.
9079 On the 386, immediates, displacements, and data pointers are all in
9080 the same (little-endian) format, so we don't need to care about which
9084 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9086 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9087 valueT value
= *valP
;
9089 #if !defined (TE_Mach)
9092 switch (fixP
->fx_r_type
)
9098 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9101 case BFD_RELOC_X86_64_32S
:
9102 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9105 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9108 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9113 if (fixP
->fx_addsy
!= NULL
9114 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9115 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9116 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9117 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9118 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9119 && !use_rela_relocations
)
9121 /* This is a hack. There should be a better way to handle this.
9122 This covers for the fact that bfd_install_relocation will
9123 subtract the current location (for partial_inplace, PC relative
9124 relocations); see more below. */
9128 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9131 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9136 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9139 || (symbol_section_p (fixP
->fx_addsy
)
9140 && sym_seg
!= absolute_section
))
9141 && !generic_force_reloc (fixP
))
9143 /* Yes, we add the values in twice. This is because
9144 bfd_install_relocation subtracts them out again. I think
9145 bfd_install_relocation is broken, but I don't dare change
9147 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9151 #if defined (OBJ_COFF) && defined (TE_PE)
9152 /* For some reason, the PE format does not store a
9153 section address offset for a PC relative symbol. */
9154 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9155 || S_IS_WEAK (fixP
->fx_addsy
))
9156 value
+= md_pcrel_from (fixP
);
9159 #if defined (OBJ_COFF) && defined (TE_PE)
9160 if (fixP
->fx_addsy
!= NULL
9161 && S_IS_WEAK (fixP
->fx_addsy
)
9162 /* PR 16858: Do not modify weak function references. */
9163 && ! fixP
->fx_pcrel
)
9165 #if !defined (TE_PEP)
9166 /* For x86 PE weak function symbols are neither PC-relative
9167 nor do they set S_IS_FUNCTION. So the only reliable way
9168 to detect them is to check the flags of their containing
9170 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9171 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9175 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9179 /* Fix a few things - the dynamic linker expects certain values here,
9180 and we must not disappoint it. */
9181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9182 if (IS_ELF
&& fixP
->fx_addsy
)
9183 switch (fixP
->fx_r_type
)
9185 case BFD_RELOC_386_PLT32
:
9186 case BFD_RELOC_X86_64_PLT32
:
9187 case BFD_RELOC_X86_64_PLT32_BND
:
9188 /* Make the jump instruction point to the address of the operand. At
9189 runtime we merely add the offset to the actual PLT entry. */
9193 case BFD_RELOC_386_TLS_GD
:
9194 case BFD_RELOC_386_TLS_LDM
:
9195 case BFD_RELOC_386_TLS_IE_32
:
9196 case BFD_RELOC_386_TLS_IE
:
9197 case BFD_RELOC_386_TLS_GOTIE
:
9198 case BFD_RELOC_386_TLS_GOTDESC
:
9199 case BFD_RELOC_X86_64_TLSGD
:
9200 case BFD_RELOC_X86_64_TLSLD
:
9201 case BFD_RELOC_X86_64_GOTTPOFF
:
9202 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9203 value
= 0; /* Fully resolved at runtime. No addend. */
9205 case BFD_RELOC_386_TLS_LE
:
9206 case BFD_RELOC_386_TLS_LDO_32
:
9207 case BFD_RELOC_386_TLS_LE_32
:
9208 case BFD_RELOC_X86_64_DTPOFF32
:
9209 case BFD_RELOC_X86_64_DTPOFF64
:
9210 case BFD_RELOC_X86_64_TPOFF32
:
9211 case BFD_RELOC_X86_64_TPOFF64
:
9212 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9215 case BFD_RELOC_386_TLS_DESC_CALL
:
9216 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9217 value
= 0; /* Fully resolved at runtime. No addend. */
9218 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9222 case BFD_RELOC_386_GOT32
:
9223 case BFD_RELOC_X86_64_GOT32
:
9224 value
= 0; /* Fully resolved at runtime. No addend. */
9227 case BFD_RELOC_VTABLE_INHERIT
:
9228 case BFD_RELOC_VTABLE_ENTRY
:
9235 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9237 #endif /* !defined (TE_Mach) */
9239 /* Are we finished with this relocation now? */
9240 if (fixP
->fx_addsy
== NULL
)
9242 #if defined (OBJ_COFF) && defined (TE_PE)
9243 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9246 /* Remember value for tc_gen_reloc. */
9247 fixP
->fx_addnumber
= value
;
9248 /* Clear out the frag for now. */
9252 else if (use_rela_relocations
)
9254 fixP
->fx_no_overflow
= 1;
9255 /* Remember value for tc_gen_reloc. */
9256 fixP
->fx_addnumber
= value
;
9260 md_number_to_chars (p
, value
, fixP
->fx_size
);
9264 md_atof (int type
, char *litP
, int *sizeP
)
9266 /* This outputs the LITTLENUMs in REVERSE order;
9267 in accord with the bigendian 386. */
9268 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9271 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9274 output_invalid (int c
)
9277 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9280 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9281 "(0x%x)", (unsigned char) c
);
9282 return output_invalid_buf
;
9285 /* REG_STRING starts *before* REGISTER_PREFIX. */
9287 static const reg_entry
*
9288 parse_real_register (char *reg_string
, char **end_op
)
9290 char *s
= reg_string
;
9292 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9295 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9296 if (*s
== REGISTER_PREFIX
)
9299 if (is_space_char (*s
))
9303 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9305 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9306 return (const reg_entry
*) NULL
;
9310 /* For naked regs, make sure that we are not dealing with an identifier.
9311 This prevents confusing an identifier like `eax_var' with register
9313 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9314 return (const reg_entry
*) NULL
;
9318 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9320 /* Handle floating point regs, allowing spaces in the (i) part. */
9321 if (r
== i386_regtab
/* %st is first entry of table */)
9323 if (is_space_char (*s
))
9328 if (is_space_char (*s
))
9330 if (*s
>= '0' && *s
<= '7')
9334 if (is_space_char (*s
))
9339 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9344 /* We have "%st(" then garbage. */
9345 return (const reg_entry
*) NULL
;
9349 if (r
== NULL
|| allow_pseudo_reg
)
9352 if (operand_type_all_zero (&r
->reg_type
))
9353 return (const reg_entry
*) NULL
;
9355 if ((r
->reg_type
.bitfield
.reg32
9356 || r
->reg_type
.bitfield
.sreg3
9357 || r
->reg_type
.bitfield
.control
9358 || r
->reg_type
.bitfield
.debug
9359 || r
->reg_type
.bitfield
.test
)
9360 && !cpu_arch_flags
.bitfield
.cpui386
)
9361 return (const reg_entry
*) NULL
;
9363 if (r
->reg_type
.bitfield
.floatreg
9364 && !cpu_arch_flags
.bitfield
.cpu8087
9365 && !cpu_arch_flags
.bitfield
.cpu287
9366 && !cpu_arch_flags
.bitfield
.cpu387
)
9367 return (const reg_entry
*) NULL
;
9369 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9370 return (const reg_entry
*) NULL
;
9372 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9373 return (const reg_entry
*) NULL
;
9375 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9376 return (const reg_entry
*) NULL
;
9378 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9379 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9380 return (const reg_entry
*) NULL
;
9382 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9383 if (!allow_index_reg
9384 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9385 return (const reg_entry
*) NULL
;
9387 /* Upper 16 vector register is only available with VREX in 64bit
9389 if ((r
->reg_flags
& RegVRex
))
9391 if (!cpu_arch_flags
.bitfield
.cpuvrex
9392 || flag_code
!= CODE_64BIT
)
9393 return (const reg_entry
*) NULL
;
9398 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9399 || r
->reg_type
.bitfield
.reg64
)
9400 && (!cpu_arch_flags
.bitfield
.cpulm
9401 || !operand_type_equal (&r
->reg_type
, &control
))
9402 && flag_code
!= CODE_64BIT
)
9403 return (const reg_entry
*) NULL
;
9405 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9406 return (const reg_entry
*) NULL
;
9411 /* REG_STRING starts *before* REGISTER_PREFIX. */
9413 static const reg_entry
*
9414 parse_register (char *reg_string
, char **end_op
)
9418 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9419 r
= parse_real_register (reg_string
, end_op
);
9424 char *save
= input_line_pointer
;
9428 input_line_pointer
= reg_string
;
9429 c
= get_symbol_end ();
9430 symbolP
= symbol_find (reg_string
);
9431 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9433 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9435 know (e
->X_op
== O_register
);
9436 know (e
->X_add_number
>= 0
9437 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9438 r
= i386_regtab
+ e
->X_add_number
;
9439 if ((r
->reg_flags
& RegVRex
))
9441 *end_op
= input_line_pointer
;
9443 *input_line_pointer
= c
;
9444 input_line_pointer
= save
;
9450 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9453 char *end
= input_line_pointer
;
9456 r
= parse_register (name
, &input_line_pointer
);
9457 if (r
&& end
<= input_line_pointer
)
9459 *nextcharP
= *input_line_pointer
;
9460 *input_line_pointer
= 0;
9461 e
->X_op
= O_register
;
9462 e
->X_add_number
= r
- i386_regtab
;
9465 input_line_pointer
= end
;
9467 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9471 md_operand (expressionS
*e
)
9476 switch (*input_line_pointer
)
9478 case REGISTER_PREFIX
:
9479 r
= parse_real_register (input_line_pointer
, &end
);
9482 e
->X_op
= O_register
;
9483 e
->X_add_number
= r
- i386_regtab
;
9484 input_line_pointer
= end
;
9489 gas_assert (intel_syntax
);
9490 end
= input_line_pointer
++;
9492 if (*input_line_pointer
== ']')
9494 ++input_line_pointer
;
9495 e
->X_op_symbol
= make_expr_symbol (e
);
9496 e
->X_add_symbol
= NULL
;
9497 e
->X_add_number
= 0;
9503 input_line_pointer
= end
;
9510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9511 const char *md_shortopts
= "kVQ:sqn";
9513 const char *md_shortopts
= "qn";
9516 #define OPTION_32 (OPTION_MD_BASE + 0)
9517 #define OPTION_64 (OPTION_MD_BASE + 1)
9518 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9519 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9520 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9521 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9522 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9523 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9524 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9525 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9526 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9527 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9528 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9529 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9530 #define OPTION_X32 (OPTION_MD_BASE + 14)
9531 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9532 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9533 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9534 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9536 struct option md_longopts
[] =
9538 {"32", no_argument
, NULL
, OPTION_32
},
9539 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9540 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9541 {"64", no_argument
, NULL
, OPTION_64
},
9543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9544 {"x32", no_argument
, NULL
, OPTION_X32
},
9546 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9547 {"march", required_argument
, NULL
, OPTION_MARCH
},
9548 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9549 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9550 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9551 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9552 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9553 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9554 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9555 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9556 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9557 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9558 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9559 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9560 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9561 # if defined (TE_PE) || defined (TE_PEP)
9562 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9564 {NULL
, no_argument
, NULL
, 0}
9566 size_t md_longopts_size
= sizeof (md_longopts
);
9569 md_parse_option (int c
, char *arg
)
9577 optimize_align_code
= 0;
9584 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9585 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9586 should be emitted or not. FIXME: Not implemented. */
9590 /* -V: SVR4 argument to print version ID. */
9592 print_version_id ();
9595 /* -k: Ignore for FreeBSD compatibility. */
9600 /* -s: On i386 Solaris, this tells the native assembler to use
9601 .stab instead of .stab.excl. We always use .stab anyhow. */
9604 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9605 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9608 const char **list
, **l
;
9610 list
= bfd_target_list ();
9611 for (l
= list
; *l
!= NULL
; l
++)
9612 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9613 || strcmp (*l
, "coff-x86-64") == 0
9614 || strcmp (*l
, "pe-x86-64") == 0
9615 || strcmp (*l
, "pei-x86-64") == 0
9616 || strcmp (*l
, "mach-o-x86-64") == 0)
9618 default_arch
= "x86_64";
9622 as_fatal (_("no compiled in support for x86_64"));
9628 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9632 const char **list
, **l
;
9634 list
= bfd_target_list ();
9635 for (l
= list
; *l
!= NULL
; l
++)
9636 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9638 default_arch
= "x86_64:32";
9642 as_fatal (_("no compiled in support for 32bit x86_64"));
9646 as_fatal (_("32bit x86_64 is only supported for ELF"));
9651 default_arch
= "i386";
9655 #ifdef SVR4_COMMENT_CHARS
9660 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9662 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9666 i386_comment_chars
= n
;
9672 arch
= xstrdup (arg
);
9676 as_fatal (_("invalid -march= option: `%s'"), arg
);
9677 next
= strchr (arch
, '+');
9680 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9682 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9685 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9688 cpu_arch_name
= cpu_arch
[j
].name
;
9689 cpu_sub_arch_name
= NULL
;
9690 cpu_arch_flags
= cpu_arch
[j
].flags
;
9691 cpu_arch_isa
= cpu_arch
[j
].type
;
9692 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9693 if (!cpu_arch_tune_set
)
9695 cpu_arch_tune
= cpu_arch_isa
;
9696 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9700 else if (*cpu_arch
[j
].name
== '.'
9701 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9703 /* ISA entension. */
9704 i386_cpu_flags flags
;
9706 if (!cpu_arch
[j
].negated
)
9707 flags
= cpu_flags_or (cpu_arch_flags
,
9710 flags
= cpu_flags_and_not (cpu_arch_flags
,
9712 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9714 if (cpu_sub_arch_name
)
9716 char *name
= cpu_sub_arch_name
;
9717 cpu_sub_arch_name
= concat (name
,
9719 (const char *) NULL
);
9723 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9724 cpu_arch_flags
= flags
;
9725 cpu_arch_isa_flags
= flags
;
9731 if (j
>= ARRAY_SIZE (cpu_arch
))
9732 as_fatal (_("invalid -march= option: `%s'"), arg
);
9736 while (next
!= NULL
);
9741 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9742 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9744 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9746 cpu_arch_tune_set
= 1;
9747 cpu_arch_tune
= cpu_arch
[j
].type
;
9748 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9752 if (j
>= ARRAY_SIZE (cpu_arch
))
9753 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9756 case OPTION_MMNEMONIC
:
9757 if (strcasecmp (arg
, "att") == 0)
9759 else if (strcasecmp (arg
, "intel") == 0)
9762 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9765 case OPTION_MSYNTAX
:
9766 if (strcasecmp (arg
, "att") == 0)
9768 else if (strcasecmp (arg
, "intel") == 0)
9771 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9774 case OPTION_MINDEX_REG
:
9775 allow_index_reg
= 1;
9778 case OPTION_MNAKED_REG
:
9779 allow_naked_reg
= 1;
9782 case OPTION_MOLD_GCC
:
9786 case OPTION_MSSE2AVX
:
9790 case OPTION_MSSE_CHECK
:
9791 if (strcasecmp (arg
, "error") == 0)
9792 sse_check
= check_error
;
9793 else if (strcasecmp (arg
, "warning") == 0)
9794 sse_check
= check_warning
;
9795 else if (strcasecmp (arg
, "none") == 0)
9796 sse_check
= check_none
;
9798 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9801 case OPTION_MOPERAND_CHECK
:
9802 if (strcasecmp (arg
, "error") == 0)
9803 operand_check
= check_error
;
9804 else if (strcasecmp (arg
, "warning") == 0)
9805 operand_check
= check_warning
;
9806 else if (strcasecmp (arg
, "none") == 0)
9807 operand_check
= check_none
;
9809 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9812 case OPTION_MAVXSCALAR
:
9813 if (strcasecmp (arg
, "128") == 0)
9815 else if (strcasecmp (arg
, "256") == 0)
9818 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9821 case OPTION_MADD_BND_PREFIX
:
9825 case OPTION_MEVEXLIG
:
9826 if (strcmp (arg
, "128") == 0)
9828 else if (strcmp (arg
, "256") == 0)
9830 else if (strcmp (arg
, "512") == 0)
9833 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9836 case OPTION_MEVEXWIG
:
9837 if (strcmp (arg
, "0") == 0)
9839 else if (strcmp (arg
, "1") == 0)
9842 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9845 # if defined (TE_PE) || defined (TE_PEP)
9846 case OPTION_MBIG_OBJ
:
9857 #define MESSAGE_TEMPLATE \
9861 show_arch (FILE *stream
, int ext
, int check
)
9863 static char message
[] = MESSAGE_TEMPLATE
;
9864 char *start
= message
+ 27;
9866 int size
= sizeof (MESSAGE_TEMPLATE
);
9873 left
= size
- (start
- message
);
9874 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9876 /* Should it be skipped? */
9877 if (cpu_arch
[j
].skip
)
9880 name
= cpu_arch
[j
].name
;
9881 len
= cpu_arch
[j
].len
;
9884 /* It is an extension. Skip if we aren't asked to show it. */
9895 /* It is an processor. Skip if we show only extension. */
9898 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9900 /* It is an impossible processor - skip. */
9904 /* Reserve 2 spaces for ", " or ",\0" */
9907 /* Check if there is any room. */
9915 p
= mempcpy (p
, name
, len
);
9919 /* Output the current message now and start a new one. */
9922 fprintf (stream
, "%s\n", message
);
9924 left
= size
- (start
- message
) - len
- 2;
9926 gas_assert (left
>= 0);
9928 p
= mempcpy (p
, name
, len
);
9933 fprintf (stream
, "%s\n", message
);
9937 md_show_usage (FILE *stream
)
9939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9940 fprintf (stream
, _("\
9942 -V print assembler version number\n\
9945 fprintf (stream
, _("\
9946 -n Do not optimize code alignment\n\
9947 -q quieten some warnings\n"));
9948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9949 fprintf (stream
, _("\
9952 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9953 || defined (TE_PE) || defined (TE_PEP))
9954 fprintf (stream
, _("\
9955 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9957 #ifdef SVR4_COMMENT_CHARS
9958 fprintf (stream
, _("\
9959 --divide do not treat `/' as a comment character\n"));
9961 fprintf (stream
, _("\
9962 --divide ignored\n"));
9964 fprintf (stream
, _("\
9965 -march=CPU[,+EXTENSION...]\n\
9966 generate code for CPU and EXTENSION, CPU is one of:\n"));
9967 show_arch (stream
, 0, 1);
9968 fprintf (stream
, _("\
9969 EXTENSION is combination of:\n"));
9970 show_arch (stream
, 1, 0);
9971 fprintf (stream
, _("\
9972 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9973 show_arch (stream
, 0, 0);
9974 fprintf (stream
, _("\
9975 -msse2avx encode SSE instructions with VEX prefix\n"));
9976 fprintf (stream
, _("\
9977 -msse-check=[none|error|warning]\n\
9978 check SSE instructions\n"));
9979 fprintf (stream
, _("\
9980 -moperand-check=[none|error|warning]\n\
9981 check operand combinations for validity\n"));
9982 fprintf (stream
, _("\
9983 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9985 fprintf (stream
, _("\
9986 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9988 fprintf (stream
, _("\
9989 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9990 for EVEX.W bit ignored instructions\n"));
9991 fprintf (stream
, _("\
9992 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9993 fprintf (stream
, _("\
9994 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9995 fprintf (stream
, _("\
9996 -mindex-reg support pseudo index registers\n"));
9997 fprintf (stream
, _("\
9998 -mnaked-reg don't require `%%' prefix for registers\n"));
9999 fprintf (stream
, _("\
10000 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10001 fprintf (stream
, _("\
10002 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10003 # if defined (TE_PE) || defined (TE_PEP)
10004 fprintf (stream
, _("\
10005 -mbig-obj generate big object files\n"));
10009 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10010 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10011 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10013 /* Pick the target format to use. */
10016 i386_target_format (void)
10018 if (!strncmp (default_arch
, "x86_64", 6))
10020 update_code_flag (CODE_64BIT
, 1);
10021 if (default_arch
[6] == '\0')
10022 x86_elf_abi
= X86_64_ABI
;
10024 x86_elf_abi
= X86_64_X32_ABI
;
10026 else if (!strcmp (default_arch
, "i386"))
10027 update_code_flag (CODE_32BIT
, 1);
10029 as_fatal (_("unknown architecture"));
10031 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10032 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10033 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10034 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10036 switch (OUTPUT_FLAVOR
)
10038 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10039 case bfd_target_aout_flavour
:
10040 return AOUT_TARGET_FORMAT
;
10042 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10043 # if defined (TE_PE) || defined (TE_PEP)
10044 case bfd_target_coff_flavour
:
10045 if (flag_code
== CODE_64BIT
)
10046 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10049 # elif defined (TE_GO32)
10050 case bfd_target_coff_flavour
:
10051 return "coff-go32";
10053 case bfd_target_coff_flavour
:
10054 return "coff-i386";
10057 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10058 case bfd_target_elf_flavour
:
10060 const char *format
;
10062 switch (x86_elf_abi
)
10065 format
= ELF_TARGET_FORMAT
;
10068 use_rela_relocations
= 1;
10070 format
= ELF_TARGET_FORMAT64
;
10072 case X86_64_X32_ABI
:
10073 use_rela_relocations
= 1;
10075 disallow_64bit_reloc
= 1;
10076 format
= ELF_TARGET_FORMAT32
;
10079 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10081 if (x86_elf_abi
!= X86_64_ABI
)
10082 as_fatal (_("Intel L1OM is 64bit only"));
10083 return ELF_TARGET_L1OM_FORMAT
;
10085 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10087 if (x86_elf_abi
!= X86_64_ABI
)
10088 as_fatal (_("Intel K1OM is 64bit only"));
10089 return ELF_TARGET_K1OM_FORMAT
;
10095 #if defined (OBJ_MACH_O)
10096 case bfd_target_mach_o_flavour
:
10097 if (flag_code
== CODE_64BIT
)
10099 use_rela_relocations
= 1;
10101 return "mach-o-x86-64";
10104 return "mach-o-i386";
10112 #endif /* OBJ_MAYBE_ more than one */
10114 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10116 i386_elf_emit_arch_note (void)
10118 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10121 asection
*seg
= now_seg
;
10122 subsegT subseg
= now_subseg
;
10123 Elf_Internal_Note i_note
;
10124 Elf_External_Note e_note
;
10125 asection
*note_secp
;
10128 /* Create the .note section. */
10129 note_secp
= subseg_new (".note", 0);
10130 bfd_set_section_flags (stdoutput
,
10132 SEC_HAS_CONTENTS
| SEC_READONLY
);
10134 /* Process the arch string. */
10135 len
= strlen (cpu_arch_name
);
10137 i_note
.namesz
= len
+ 1;
10139 i_note
.type
= NT_ARCH
;
10140 p
= frag_more (sizeof (e_note
.namesz
));
10141 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10142 p
= frag_more (sizeof (e_note
.descsz
));
10143 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10144 p
= frag_more (sizeof (e_note
.type
));
10145 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10146 p
= frag_more (len
+ 1);
10147 strcpy (p
, cpu_arch_name
);
10149 frag_align (2, 0, 0);
10151 subseg_set (seg
, subseg
);
10157 md_undefined_symbol (char *name
)
10159 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10160 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10161 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10162 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10166 if (symbol_find (name
))
10167 as_bad (_("GOT already in symbol table"));
10168 GOT_symbol
= symbol_new (name
, undefined_section
,
10169 (valueT
) 0, &zero_address_frag
);
10176 /* Round up a section size to the appropriate boundary. */
10179 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10181 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10182 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10184 /* For a.out, force the section size to be aligned. If we don't do
10185 this, BFD will align it for us, but it will not write out the
10186 final bytes of the section. This may be a bug in BFD, but it is
10187 easier to fix it here since that is how the other a.out targets
10191 align
= bfd_get_section_alignment (stdoutput
, segment
);
10192 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10199 /* On the i386, PC-relative offsets are relative to the start of the
10200 next instruction. That is, the address of the offset, plus its
10201 size, since the offset is always the last part of the insn. */
10204 md_pcrel_from (fixS
*fixP
)
10206 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10212 s_bss (int ignore ATTRIBUTE_UNUSED
)
10216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10218 obj_elf_section_change_hook ();
10220 temp
= get_absolute_expression ();
10221 subseg_set (bss_section
, (subsegT
) temp
);
10222 demand_empty_rest_of_line ();
10228 i386_validate_fix (fixS
*fixp
)
10230 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10232 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10236 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10241 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10243 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10245 fixp
->fx_subsy
= 0;
10250 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10253 bfd_reloc_code_real_type code
;
10255 switch (fixp
->fx_r_type
)
10257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10258 case BFD_RELOC_SIZE32
:
10259 case BFD_RELOC_SIZE64
:
10260 if (S_IS_DEFINED (fixp
->fx_addsy
)
10261 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10263 /* Resolve size relocation against local symbol to size of
10264 the symbol plus addend. */
10265 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10266 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10267 && !fits_in_unsigned_long (value
))
10268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10269 _("symbol size computation overflow"));
10270 fixp
->fx_addsy
= NULL
;
10271 fixp
->fx_subsy
= NULL
;
10272 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10277 case BFD_RELOC_X86_64_PLT32
:
10278 case BFD_RELOC_X86_64_PLT32_BND
:
10279 case BFD_RELOC_X86_64_GOT32
:
10280 case BFD_RELOC_X86_64_GOTPCREL
:
10281 case BFD_RELOC_386_PLT32
:
10282 case BFD_RELOC_386_GOT32
:
10283 case BFD_RELOC_386_GOTOFF
:
10284 case BFD_RELOC_386_GOTPC
:
10285 case BFD_RELOC_386_TLS_GD
:
10286 case BFD_RELOC_386_TLS_LDM
:
10287 case BFD_RELOC_386_TLS_LDO_32
:
10288 case BFD_RELOC_386_TLS_IE_32
:
10289 case BFD_RELOC_386_TLS_IE
:
10290 case BFD_RELOC_386_TLS_GOTIE
:
10291 case BFD_RELOC_386_TLS_LE_32
:
10292 case BFD_RELOC_386_TLS_LE
:
10293 case BFD_RELOC_386_TLS_GOTDESC
:
10294 case BFD_RELOC_386_TLS_DESC_CALL
:
10295 case BFD_RELOC_X86_64_TLSGD
:
10296 case BFD_RELOC_X86_64_TLSLD
:
10297 case BFD_RELOC_X86_64_DTPOFF32
:
10298 case BFD_RELOC_X86_64_DTPOFF64
:
10299 case BFD_RELOC_X86_64_GOTTPOFF
:
10300 case BFD_RELOC_X86_64_TPOFF32
:
10301 case BFD_RELOC_X86_64_TPOFF64
:
10302 case BFD_RELOC_X86_64_GOTOFF64
:
10303 case BFD_RELOC_X86_64_GOTPC32
:
10304 case BFD_RELOC_X86_64_GOT64
:
10305 case BFD_RELOC_X86_64_GOTPCREL64
:
10306 case BFD_RELOC_X86_64_GOTPC64
:
10307 case BFD_RELOC_X86_64_GOTPLT64
:
10308 case BFD_RELOC_X86_64_PLTOFF64
:
10309 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10310 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10311 case BFD_RELOC_RVA
:
10312 case BFD_RELOC_VTABLE_ENTRY
:
10313 case BFD_RELOC_VTABLE_INHERIT
:
10315 case BFD_RELOC_32_SECREL
:
10317 code
= fixp
->fx_r_type
;
10319 case BFD_RELOC_X86_64_32S
:
10320 if (!fixp
->fx_pcrel
)
10322 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10323 code
= fixp
->fx_r_type
;
10327 if (fixp
->fx_pcrel
)
10329 switch (fixp
->fx_size
)
10332 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10333 _("can not do %d byte pc-relative relocation"),
10335 code
= BFD_RELOC_32_PCREL
;
10337 case 1: code
= BFD_RELOC_8_PCREL
; break;
10338 case 2: code
= BFD_RELOC_16_PCREL
; break;
10340 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10341 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10344 case 8: code
= BFD_RELOC_64_PCREL
; break;
10350 switch (fixp
->fx_size
)
10353 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10354 _("can not do %d byte relocation"),
10356 code
= BFD_RELOC_32
;
10358 case 1: code
= BFD_RELOC_8
; break;
10359 case 2: code
= BFD_RELOC_16
; break;
10360 case 4: code
= BFD_RELOC_32
; break;
10362 case 8: code
= BFD_RELOC_64
; break;
10369 if ((code
== BFD_RELOC_32
10370 || code
== BFD_RELOC_32_PCREL
10371 || code
== BFD_RELOC_X86_64_32S
)
10373 && fixp
->fx_addsy
== GOT_symbol
)
10376 code
= BFD_RELOC_386_GOTPC
;
10378 code
= BFD_RELOC_X86_64_GOTPC32
;
10380 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10382 && fixp
->fx_addsy
== GOT_symbol
)
10384 code
= BFD_RELOC_X86_64_GOTPC64
;
10387 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10388 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10389 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10391 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10393 if (!use_rela_relocations
)
10395 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10396 vtable entry to be used in the relocation's section offset. */
10397 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10398 rel
->address
= fixp
->fx_offset
;
10399 #if defined (OBJ_COFF) && defined (TE_PE)
10400 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10401 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10406 /* Use the rela in 64bit mode. */
10409 if (disallow_64bit_reloc
)
10412 case BFD_RELOC_X86_64_DTPOFF64
:
10413 case BFD_RELOC_X86_64_TPOFF64
:
10414 case BFD_RELOC_64_PCREL
:
10415 case BFD_RELOC_X86_64_GOTOFF64
:
10416 case BFD_RELOC_X86_64_GOT64
:
10417 case BFD_RELOC_X86_64_GOTPCREL64
:
10418 case BFD_RELOC_X86_64_GOTPC64
:
10419 case BFD_RELOC_X86_64_GOTPLT64
:
10420 case BFD_RELOC_X86_64_PLTOFF64
:
10421 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10422 _("cannot represent relocation type %s in x32 mode"),
10423 bfd_get_reloc_code_name (code
));
10429 if (!fixp
->fx_pcrel
)
10430 rel
->addend
= fixp
->fx_offset
;
10434 case BFD_RELOC_X86_64_PLT32
:
10435 case BFD_RELOC_X86_64_PLT32_BND
:
10436 case BFD_RELOC_X86_64_GOT32
:
10437 case BFD_RELOC_X86_64_GOTPCREL
:
10438 case BFD_RELOC_X86_64_TLSGD
:
10439 case BFD_RELOC_X86_64_TLSLD
:
10440 case BFD_RELOC_X86_64_GOTTPOFF
:
10441 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10442 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10443 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10446 rel
->addend
= (section
->vma
10448 + fixp
->fx_addnumber
10449 + md_pcrel_from (fixp
));
10454 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10455 if (rel
->howto
== NULL
)
10457 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10458 _("cannot represent relocation type %s"),
10459 bfd_get_reloc_code_name (code
));
10460 /* Set howto to a garbage value so that we can keep going. */
10461 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10462 gas_assert (rel
->howto
!= NULL
);
10468 #include "tc-i386-intel.c"
10471 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10473 int saved_naked_reg
;
10474 char saved_register_dot
;
10476 saved_naked_reg
= allow_naked_reg
;
10477 allow_naked_reg
= 1;
10478 saved_register_dot
= register_chars
['.'];
10479 register_chars
['.'] = '.';
10480 allow_pseudo_reg
= 1;
10481 expression_and_evaluate (exp
);
10482 allow_pseudo_reg
= 0;
10483 register_chars
['.'] = saved_register_dot
;
10484 allow_naked_reg
= saved_naked_reg
;
10486 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10488 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10490 exp
->X_op
= O_constant
;
10491 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10492 .dw2_regnum
[flag_code
>> 1];
10495 exp
->X_op
= O_illegal
;
10500 tc_x86_frame_initial_instructions (void)
10502 static unsigned int sp_regno
[2];
10504 if (!sp_regno
[flag_code
>> 1])
10506 char *saved_input
= input_line_pointer
;
10507 char sp
[][4] = {"esp", "rsp"};
10510 input_line_pointer
= sp
[flag_code
>> 1];
10511 tc_x86_parse_to_dw2regnum (&exp
);
10512 gas_assert (exp
.X_op
== O_constant
);
10513 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10514 input_line_pointer
= saved_input
;
10517 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10518 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10522 x86_dwarf2_addr_size (void)
10524 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10525 if (x86_elf_abi
== X86_64_X32_ABI
)
10528 return bfd_arch_bits_per_address (stdoutput
) / 8;
10532 i386_elf_section_type (const char *str
, size_t len
)
10534 if (flag_code
== CODE_64BIT
10535 && len
== sizeof ("unwind") - 1
10536 && strncmp (str
, "unwind", 6) == 0)
10537 return SHT_X86_64_UNWIND
;
10544 i386_solaris_fix_up_eh_frame (segT sec
)
10546 if (flag_code
== CODE_64BIT
)
10547 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10553 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10557 exp
.X_op
= O_secrel
;
10558 exp
.X_add_symbol
= symbol
;
10559 exp
.X_add_number
= 0;
10560 emit_expr (&exp
, size
);
10564 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10565 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10568 x86_64_section_letter (int letter
, char **ptr_msg
)
10570 if (flag_code
== CODE_64BIT
)
10573 return SHF_X86_64_LARGE
;
10575 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10578 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10583 x86_64_section_word (char *str
, size_t len
)
10585 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10586 return SHF_X86_64_LARGE
;
10592 handle_large_common (int small ATTRIBUTE_UNUSED
)
10594 if (flag_code
!= CODE_64BIT
)
10596 s_comm_internal (0, elf_common_parse
);
10597 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10601 static segT lbss_section
;
10602 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10603 asection
*saved_bss_section
= bss_section
;
10605 if (lbss_section
== NULL
)
10607 flagword applicable
;
10608 segT seg
= now_seg
;
10609 subsegT subseg
= now_subseg
;
10611 /* The .lbss section is for local .largecomm symbols. */
10612 lbss_section
= subseg_new (".lbss", 0);
10613 applicable
= bfd_applicable_section_flags (stdoutput
);
10614 bfd_set_section_flags (stdoutput
, lbss_section
,
10615 applicable
& SEC_ALLOC
);
10616 seg_info (lbss_section
)->bss
= 1;
10618 subseg_set (seg
, subseg
);
10621 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10622 bss_section
= lbss_section
;
10624 s_comm_internal (0, elf_common_parse
);
10626 elf_com_section_ptr
= saved_com_section_ptr
;
10627 bss_section
= saved_bss_section
;
10630 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */