1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for intel mnemonic,
539 0 if att mnemonic. */
540 static int intel_mnemonic
= !SYSV386_COMPAT
;
542 /* 1 if support old (<= 2.8.1) versions of gcc. */
543 static int old_gcc
= OLDGCC_COMPAT
;
545 /* 1 if pseudo registers are permitted. */
546 static int allow_pseudo_reg
= 0;
548 /* 1 if register prefix % not required. */
549 static int allow_naked_reg
= 0;
551 /* 1 if the assembler should add BND prefix for all control-tranferring
552 instructions supporting it, even if this prefix wasn't specified
554 static int add_bnd_prefix
= 0;
556 /* 1 if pseudo index register, eiz/riz, is allowed . */
557 static int allow_index_reg
= 0;
559 /* 1 if the assembler should ignore LOCK prefix, even if it was
560 specified explicitly. */
561 static int omit_lock_prefix
= 0;
563 /* 1 if the assembler should encode lfence, mfence, and sfence as
564 "lock addl $0, (%{re}sp)". */
565 static int avoid_fence
= 0;
567 /* 1 if the assembler should generate relax relocations. */
569 static int generate_relax_relocations
570 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
572 static enum check_kind
578 sse_check
, operand_check
= check_warning
;
580 /* Register prefix used for error message. */
581 static const char *register_prefix
= "%";
583 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
584 leave, push, and pop instructions so that gcc has the same stack
585 frame as in 32 bit mode. */
586 static char stackop_size
= '\0';
588 /* Non-zero to optimize code alignment. */
589 int optimize_align_code
= 1;
591 /* Non-zero to quieten some warnings. */
592 static int quiet_warnings
= 0;
595 static const char *cpu_arch_name
= NULL
;
596 static char *cpu_sub_arch_name
= NULL
;
598 /* CPU feature flags. */
599 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
601 /* If we have selected a cpu we are generating instructions for. */
602 static int cpu_arch_tune_set
= 0;
604 /* Cpu we are generating instructions for. */
605 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
607 /* CPU feature flags of cpu we are generating instructions for. */
608 static i386_cpu_flags cpu_arch_tune_flags
;
610 /* CPU instruction set architecture used. */
611 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
613 /* CPU feature flags of instruction set architecture used. */
614 i386_cpu_flags cpu_arch_isa_flags
;
616 /* If set, conditional jumps are not automatically promoted to handle
617 larger than a byte offset. */
618 static unsigned int no_cond_jump_promotion
= 0;
620 /* Encode SSE instructions with VEX prefix. */
621 static unsigned int sse2avx
;
623 /* Encode scalar AVX instructions with specific vector length. */
630 /* Encode scalar EVEX LIG instructions with specific vector length. */
638 /* Encode EVEX WIG instructions with specific evex.w. */
645 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
646 static enum rc_type evexrcig
= rne
;
648 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
649 static symbolS
*GOT_symbol
;
651 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
652 unsigned int x86_dwarf2_return_column
;
654 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
655 int x86_cie_data_alignment
;
657 /* Interface to relax_segment.
658 There are 3 major relax states for 386 jump insns because the
659 different types of jumps add different sizes to frags when we're
660 figuring out what sort of jump to choose to reach a given label. */
663 #define UNCOND_JUMP 0
665 #define COND_JUMP86 2
670 #define SMALL16 (SMALL | CODE16)
672 #define BIG16 (BIG | CODE16)
676 #define INLINE __inline__
682 #define ENCODE_RELAX_STATE(type, size) \
683 ((relax_substateT) (((type) << 2) | (size)))
684 #define TYPE_FROM_RELAX_STATE(s) \
686 #define DISP_SIZE_FROM_RELAX_STATE(s) \
687 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
689 /* This table is used by relax_frag to promote short jumps to long
690 ones where necessary. SMALL (short) jumps may be promoted to BIG
691 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
692 don't allow a short jump in a 32 bit code segment to be promoted to
693 a 16 bit offset jump because it's slower (requires data size
694 prefix), and doesn't work, unless the destination is in the bottom
695 64k of the code segment (The top 16 bits of eip are zeroed). */
697 const relax_typeS md_relax_table
[] =
700 1) most positive reach of this state,
701 2) most negative reach of this state,
702 3) how many bytes this mode will have in the variable part of the frag
703 4) which index into the table to try if we can't fit into this one. */
705 /* UNCOND_JUMP states. */
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
707 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
708 /* dword jmp adds 4 bytes to frag:
709 0 extra opcode bytes, 4 displacement bytes. */
711 /* word jmp adds 2 byte2 to frag:
712 0 extra opcode bytes, 2 displacement bytes. */
715 /* COND_JUMP states. */
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
717 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
718 /* dword conditionals adds 5 bytes to frag:
719 1 extra opcode byte, 4 displacement bytes. */
721 /* word conditionals add 3 bytes to frag:
722 1 extra opcode byte, 2 displacement bytes. */
725 /* COND_JUMP86 states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
728 /* dword conditionals adds 5 bytes to frag:
729 1 extra opcode byte, 4 displacement bytes. */
731 /* word conditionals add 4 bytes to frag:
732 1 displacement byte and a 3 byte long branch insn. */
736 static const arch_entry cpu_arch
[] =
738 /* Do not replace the first two entries - i386_target_format()
739 relies on them being there in this order. */
740 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
741 CPU_GENERIC32_FLAGS
, 0 },
742 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
743 CPU_GENERIC64_FLAGS
, 0 },
744 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
746 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
748 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
752 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
754 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
756 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
758 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
761 CPU_PENTIUMPRO_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
764 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
766 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
768 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
770 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
771 CPU_NOCONA_FLAGS
, 0 },
772 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
774 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
776 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
777 CPU_CORE2_FLAGS
, 1 },
778 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
779 CPU_CORE2_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
781 CPU_COREI7_FLAGS
, 0 },
782 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
784 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
786 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
787 CPU_IAMCU_FLAGS
, 0 },
788 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
790 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
792 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
793 CPU_ATHLON_FLAGS
, 0 },
794 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
796 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
798 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
801 CPU_AMDFAM10_FLAGS
, 0 },
802 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
803 CPU_BDVER1_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
805 CPU_BDVER2_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
807 CPU_BDVER3_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
809 CPU_BDVER4_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
811 CPU_ZNVER1_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
813 CPU_BTVER1_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
815 CPU_BTVER2_FLAGS
, 0 },
816 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
818 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
820 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
831 CPU_SSSE3_FLAGS
, 0 },
832 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
833 CPU_SSE4_1_FLAGS
, 0 },
834 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
835 CPU_SSE4_2_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
837 CPU_SSE4_2_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512F_FLAGS
, 0 },
844 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512CD_FLAGS
, 0 },
846 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512ER_FLAGS
, 0 },
848 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512PF_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512DQ_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512BW_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512VL_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
859 CPU_VMFUNC_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
863 CPU_XSAVE_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
865 CPU_XSAVEOPT_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVEC_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVES_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
873 CPU_PCLMUL_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
875 CPU_PCLMUL_FLAGS
, 1 },
876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
877 CPU_FSGSBASE_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
879 CPU_RDRND_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
893 CPU_MOVBE_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
899 CPU_LZCNT_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
905 CPU_INVPCID_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
907 CPU_CLFLUSH_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
911 CPU_SYSCALL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
913 CPU_RDTSCP_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
915 CPU_3DNOW_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
917 CPU_3DNOWA_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
919 CPU_PADLOCK_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
925 CPU_SSE4A_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
935 CPU_RDSEED_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
937 CPU_PRFCHW_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSHOPT_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
947 CPU_PREFETCHWT1_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
953 CPU_PCOMMIT_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
955 CPU_AVX512IFMA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
957 CPU_AVX512VBMI_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
959 CPU_CLZERO_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
961 CPU_MWAITX_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
963 CPU_OSPKE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
965 CPU_RDPID_FLAGS
, 0 },
968 static const noarch_entry cpu_noarch
[] =
970 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
971 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
972 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
973 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
977 /* Like s_lcomm_internal in gas/read.c but the alignment string
978 is allowed to be optional. */
981 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
988 && *input_line_pointer
== ',')
990 align
= parse_align (needs_align
- 1);
992 if (align
== (addressT
) -1)
1007 bss_alloc (symbolP
, size
, align
);
1012 pe_lcomm (int needs_align
)
1014 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1018 const pseudo_typeS md_pseudo_table
[] =
1020 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1021 {"align", s_align_bytes
, 0},
1023 {"align", s_align_ptwo
, 0},
1025 {"arch", set_cpu_arch
, 0},
1029 {"lcomm", pe_lcomm
, 1},
1031 {"ffloat", float_cons
, 'f'},
1032 {"dfloat", float_cons
, 'd'},
1033 {"tfloat", float_cons
, 'x'},
1035 {"slong", signed_cons
, 4},
1036 {"noopt", s_ignore
, 0},
1037 {"optim", s_ignore
, 0},
1038 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1039 {"code16", set_code_flag
, CODE_16BIT
},
1040 {"code32", set_code_flag
, CODE_32BIT
},
1041 {"code64", set_code_flag
, CODE_64BIT
},
1042 {"intel_syntax", set_intel_syntax
, 1},
1043 {"att_syntax", set_intel_syntax
, 0},
1044 {"intel_mnemonic", set_intel_mnemonic
, 1},
1045 {"att_mnemonic", set_intel_mnemonic
, 0},
1046 {"allow_index_reg", set_allow_index_reg
, 1},
1047 {"disallow_index_reg", set_allow_index_reg
, 0},
1048 {"sse_check", set_check
, 0},
1049 {"operand_check", set_check
, 1},
1050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1051 {"largecomm", handle_large_common
, 0},
1053 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1054 {"loc", dwarf2_directive_loc
, 0},
1055 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1058 {"secrel32", pe_directive_secrel
, 0},
1063 /* For interface with expression (). */
1064 extern char *input_line_pointer
;
1066 /* Hash table for instruction mnemonic lookup. */
1067 static struct hash_control
*op_hash
;
1069 /* Hash table for register lookup. */
1070 static struct hash_control
*reg_hash
;
1073 i386_align_code (fragS
*fragP
, int count
)
1075 /* Various efficient no-op patterns for aligning code labels.
1076 Note: Don't try to assemble the instructions in the comments.
1077 0L and 0w are not legal. */
1078 static const unsigned char f32_1
[] =
1080 static const unsigned char f32_2
[] =
1081 {0x66,0x90}; /* xchg %ax,%ax */
1082 static const unsigned char f32_3
[] =
1083 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1084 static const unsigned char f32_4
[] =
1085 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1086 static const unsigned char f32_5
[] =
1088 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1089 static const unsigned char f32_6
[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1091 static const unsigned char f32_7
[] =
1092 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1093 static const unsigned char f32_8
[] =
1095 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1096 static const unsigned char f32_9
[] =
1097 {0x89,0xf6, /* movl %esi,%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const unsigned char f32_10
[] =
1100 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1101 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1102 static const unsigned char f32_11
[] =
1103 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1104 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1105 static const unsigned char f32_12
[] =
1106 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1107 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1108 static const unsigned char f32_13
[] =
1109 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1110 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1111 static const unsigned char f32_14
[] =
1112 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1113 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1114 static const unsigned char f16_3
[] =
1115 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1116 static const unsigned char f16_4
[] =
1117 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1118 static const unsigned char f16_5
[] =
1120 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1121 static const unsigned char f16_6
[] =
1122 {0x89,0xf6, /* mov %si,%si */
1123 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1124 static const unsigned char f16_7
[] =
1125 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1126 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1127 static const unsigned char f16_8
[] =
1128 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1129 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1130 static const unsigned char jump_31
[] =
1131 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1132 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1133 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1134 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1135 static const unsigned char *const f32_patt
[] = {
1136 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1137 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1139 static const unsigned char *const f16_patt
[] = {
1140 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1142 /* nopl (%[re]ax) */
1143 static const unsigned char alt_3
[] =
1145 /* nopl 0(%[re]ax) */
1146 static const unsigned char alt_4
[] =
1147 {0x0f,0x1f,0x40,0x00};
1148 /* nopl 0(%[re]ax,%[re]ax,1) */
1149 static const unsigned char alt_5
[] =
1150 {0x0f,0x1f,0x44,0x00,0x00};
1151 /* nopw 0(%[re]ax,%[re]ax,1) */
1152 static const unsigned char alt_6
[] =
1153 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopl 0L(%[re]ax) */
1155 static const unsigned char alt_7
[] =
1156 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1157 /* nopl 0L(%[re]ax,%[re]ax,1) */
1158 static const unsigned char alt_8
[] =
1159 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopw 0L(%[re]ax,%[re]ax,1) */
1161 static const unsigned char alt_9
[] =
1162 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1163 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1164 static const unsigned char alt_10
[] =
1165 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 static const unsigned char *const alt_patt
[] = {
1167 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1171 /* Only align for at least a positive non-zero boundary. */
1172 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1175 /* We need to decide which NOP sequence to use for 32bit and
1176 64bit. When -mtune= is used:
1178 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1179 PROCESSOR_GENERIC32, f32_patt will be used.
1180 2. For the rest, alt_patt will be used.
1182 When -mtune= isn't used, alt_patt will be used if
1183 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1186 When -march= or .arch is used, we can't use anything beyond
1187 cpu_arch_isa_flags. */
1189 if (flag_code
== CODE_16BIT
)
1193 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1195 /* Adjust jump offset. */
1196 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1199 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1200 f16_patt
[count
- 1], count
);
1204 const unsigned char *const *patt
= NULL
;
1206 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1208 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1209 switch (cpu_arch_tune
)
1211 case PROCESSOR_UNKNOWN
:
1212 /* We use cpu_arch_isa_flags to check if we SHOULD
1213 optimize with nops. */
1214 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1219 case PROCESSOR_PENTIUM4
:
1220 case PROCESSOR_NOCONA
:
1221 case PROCESSOR_CORE
:
1222 case PROCESSOR_CORE2
:
1223 case PROCESSOR_COREI7
:
1224 case PROCESSOR_L1OM
:
1225 case PROCESSOR_K1OM
:
1226 case PROCESSOR_GENERIC64
:
1228 case PROCESSOR_ATHLON
:
1230 case PROCESSOR_AMDFAM10
:
1232 case PROCESSOR_ZNVER
:
1236 case PROCESSOR_I386
:
1237 case PROCESSOR_I486
:
1238 case PROCESSOR_PENTIUM
:
1239 case PROCESSOR_PENTIUMPRO
:
1240 case PROCESSOR_IAMCU
:
1241 case PROCESSOR_GENERIC32
:
1248 switch (fragP
->tc_frag_data
.tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1252 PROCESSOR_UNKNOWN. */
1256 case PROCESSOR_I386
:
1257 case PROCESSOR_I486
:
1258 case PROCESSOR_PENTIUM
:
1259 case PROCESSOR_IAMCU
:
1261 case PROCESSOR_ATHLON
:
1263 case PROCESSOR_AMDFAM10
:
1265 case PROCESSOR_ZNVER
:
1267 case PROCESSOR_GENERIC32
:
1268 /* We use cpu_arch_isa_flags to check if we CAN optimize
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1275 case PROCESSOR_PENTIUMPRO
:
1276 case PROCESSOR_PENTIUM4
:
1277 case PROCESSOR_NOCONA
:
1278 case PROCESSOR_CORE
:
1279 case PROCESSOR_CORE2
:
1280 case PROCESSOR_COREI7
:
1281 case PROCESSOR_L1OM
:
1282 case PROCESSOR_K1OM
:
1283 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 case PROCESSOR_GENERIC64
:
1294 if (patt
== f32_patt
)
1296 /* If the padding is less than 15 bytes, we use the normal
1297 ones. Otherwise, we use a jump instruction and adjust
1301 /* For 64bit, the limit is 3 bytes. */
1302 if (flag_code
== CODE_64BIT
1303 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1308 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1309 patt
[count
- 1], count
);
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1314 /* Adjust jump offset. */
1315 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1320 /* Maximum length of an instruction is 10 byte. If the
1321 padding is greater than 10 bytes and we don't use jump,
1322 we have to break it into smaller pieces. */
1323 int padding
= count
;
1324 while (padding
> 10)
1327 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1332 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1333 patt
[padding
- 1], padding
);
1336 fragP
->fr_var
= count
;
1340 operand_type_all_zero (const union i386_operand_type
*x
)
1342 switch (ARRAY_SIZE(x
->array
))
1351 return !x
->array
[0];
1358 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1360 switch (ARRAY_SIZE(x
->array
))
1375 operand_type_equal (const union i386_operand_type
*x
,
1376 const union i386_operand_type
*y
)
1378 switch (ARRAY_SIZE(x
->array
))
1381 if (x
->array
[2] != y
->array
[2])
1384 if (x
->array
[1] != y
->array
[1])
1387 return x
->array
[0] == y
->array
[0];
1395 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1397 switch (ARRAY_SIZE(x
->array
))
1406 return !x
->array
[0];
1413 cpu_flags_equal (const union i386_cpu_flags
*x
,
1414 const union i386_cpu_flags
*y
)
1416 switch (ARRAY_SIZE(x
->array
))
1419 if (x
->array
[2] != y
->array
[2])
1422 if (x
->array
[1] != y
->array
[1])
1425 return x
->array
[0] == y
->array
[0];
1433 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1435 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1436 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1439 static INLINE i386_cpu_flags
1440 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1442 switch (ARRAY_SIZE (x
.array
))
1445 x
.array
[2] &= y
.array
[2];
1447 x
.array
[1] &= y
.array
[1];
1449 x
.array
[0] &= y
.array
[0];
1457 static INLINE i386_cpu_flags
1458 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1460 switch (ARRAY_SIZE (x
.array
))
1463 x
.array
[2] |= y
.array
[2];
1465 x
.array
[1] |= y
.array
[1];
1467 x
.array
[0] |= y
.array
[0];
1475 static INLINE i386_cpu_flags
1476 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1478 switch (ARRAY_SIZE (x
.array
))
1481 x
.array
[2] &= ~y
.array
[2];
1483 x
.array
[1] &= ~y
.array
[1];
1485 x
.array
[0] &= ~y
.array
[0];
1494 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1496 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1498 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1499 i386_cpu_flags compat_flags
;
1500 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1501 return cpu_flags_all_zero (&compat_flags
);
1507 #define CPU_FLAGS_ARCH_MATCH 0x1
1508 #define CPU_FLAGS_64BIT_MATCH 0x2
1509 #define CPU_FLAGS_AES_MATCH 0x4
1510 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1511 #define CPU_FLAGS_AVX_MATCH 0x10
1513 #define CPU_FLAGS_32BIT_MATCH \
1514 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1515 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1516 #define CPU_FLAGS_PERFECT_MATCH \
1517 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1519 /* Return CPU flags match bits. */
1522 cpu_flags_match (const insn_template
*t
)
1524 i386_cpu_flags x
= t
->cpu_flags
;
1525 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1527 x
.bitfield
.cpu64
= 0;
1528 x
.bitfield
.cpuno64
= 0;
1530 if (cpu_flags_all_zero (&x
))
1532 /* This instruction is available on all archs. */
1533 match
|= CPU_FLAGS_32BIT_MATCH
;
1537 /* This instruction is available only on some archs. */
1538 i386_cpu_flags cpu
= cpu_arch_flags
;
1540 cpu
= cpu_flags_and (x
, cpu
);
1541 if (!cpu_flags_all_zero (&cpu
))
1543 if (x
.bitfield
.cpuavx
)
1545 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1546 if (cpu
.bitfield
.cpuavx
)
1548 /* Check SSE2AVX. */
1549 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1551 match
|= (CPU_FLAGS_ARCH_MATCH
1552 | CPU_FLAGS_AVX_MATCH
);
1554 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1555 match
|= CPU_FLAGS_AES_MATCH
;
1557 if (!x
.bitfield
.cpupclmul
1558 || cpu
.bitfield
.cpupclmul
)
1559 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1563 match
|= CPU_FLAGS_ARCH_MATCH
;
1565 else if (x
.bitfield
.cpuavx512vl
)
1567 /* Match AVX512VL. */
1568 if (cpu
.bitfield
.cpuavx512vl
)
1570 /* Need another match. */
1571 cpu
.bitfield
.cpuavx512vl
= 0;
1572 if (!cpu_flags_all_zero (&cpu
))
1573 match
|= CPU_FLAGS_32BIT_MATCH
;
1575 match
|= CPU_FLAGS_ARCH_MATCH
;
1578 match
|= CPU_FLAGS_ARCH_MATCH
;
1581 match
|= CPU_FLAGS_32BIT_MATCH
;
1587 static INLINE i386_operand_type
1588 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1590 switch (ARRAY_SIZE (x
.array
))
1593 x
.array
[2] &= y
.array
[2];
1595 x
.array
[1] &= y
.array
[1];
1597 x
.array
[0] &= y
.array
[0];
1605 static INLINE i386_operand_type
1606 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1608 switch (ARRAY_SIZE (x
.array
))
1611 x
.array
[2] |= y
.array
[2];
1613 x
.array
[1] |= y
.array
[1];
1615 x
.array
[0] |= y
.array
[0];
1623 static INLINE i386_operand_type
1624 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[2] ^= y
.array
[2];
1631 x
.array
[1] ^= y
.array
[1];
1633 x
.array
[0] ^= y
.array
[0];
1641 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1642 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1643 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1644 static const i386_operand_type inoutportreg
1645 = OPERAND_TYPE_INOUTPORTREG
;
1646 static const i386_operand_type reg16_inoutportreg
1647 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1648 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1649 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1650 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1651 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1652 static const i386_operand_type anydisp
1653 = OPERAND_TYPE_ANYDISP
;
1654 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1655 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1656 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1657 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1658 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1659 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1660 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1661 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1662 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1663 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1664 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1665 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1666 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1667 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1678 operand_type_check (i386_operand_type t
, enum operand_type c
)
1683 return (t
.bitfield
.reg8
1686 || t
.bitfield
.reg64
);
1689 return (t
.bitfield
.imm8
1693 || t
.bitfield
.imm32s
1694 || t
.bitfield
.imm64
);
1697 return (t
.bitfield
.disp8
1698 || t
.bitfield
.disp16
1699 || t
.bitfield
.disp32
1700 || t
.bitfield
.disp32s
1701 || t
.bitfield
.disp64
);
1704 return (t
.bitfield
.disp8
1705 || t
.bitfield
.disp16
1706 || t
.bitfield
.disp32
1707 || t
.bitfield
.disp32s
1708 || t
.bitfield
.disp64
1709 || t
.bitfield
.baseindex
);
1718 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1719 operand J for instruction template T. */
1722 match_reg_size (const insn_template
*t
, unsigned int j
)
1724 return !((i
.types
[j
].bitfield
.byte
1725 && !t
->operand_types
[j
].bitfield
.byte
)
1726 || (i
.types
[j
].bitfield
.word
1727 && !t
->operand_types
[j
].bitfield
.word
)
1728 || (i
.types
[j
].bitfield
.dword
1729 && !t
->operand_types
[j
].bitfield
.dword
)
1730 || (i
.types
[j
].bitfield
.qword
1731 && !t
->operand_types
[j
].bitfield
.qword
));
1734 /* Return 1 if there is no conflict in any size on operand J for
1735 instruction template T. */
1738 match_mem_size (const insn_template
*t
, unsigned int j
)
1740 return (match_reg_size (t
, j
)
1741 && !((i
.types
[j
].bitfield
.unspecified
1743 && !t
->operand_types
[j
].bitfield
.unspecified
)
1744 || (i
.types
[j
].bitfield
.fword
1745 && !t
->operand_types
[j
].bitfield
.fword
)
1746 || (i
.types
[j
].bitfield
.tbyte
1747 && !t
->operand_types
[j
].bitfield
.tbyte
)
1748 || (i
.types
[j
].bitfield
.xmmword
1749 && !t
->operand_types
[j
].bitfield
.xmmword
)
1750 || (i
.types
[j
].bitfield
.ymmword
1751 && !t
->operand_types
[j
].bitfield
.ymmword
)
1752 || (i
.types
[j
].bitfield
.zmmword
1753 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1756 /* Return 1 if there is no size conflict on any operands for
1757 instruction template T. */
1760 operand_size_match (const insn_template
*t
)
1765 /* Don't check jump instructions. */
1766 if (t
->opcode_modifier
.jump
1767 || t
->opcode_modifier
.jumpbyte
1768 || t
->opcode_modifier
.jumpdword
1769 || t
->opcode_modifier
.jumpintersegment
)
1772 /* Check memory and accumulator operand size. */
1773 for (j
= 0; j
< i
.operands
; j
++)
1775 if (t
->operand_types
[j
].bitfield
.anysize
)
1778 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1784 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1793 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1796 i
.error
= operand_size_mismatch
;
1800 /* Check reverse. */
1801 gas_assert (i
.operands
== 2);
1804 for (j
= 0; j
< 2; j
++)
1806 if (t
->operand_types
[j
].bitfield
.acc
1807 && !match_reg_size (t
, j
? 0 : 1))
1810 if (i
.types
[j
].bitfield
.mem
1811 && !match_mem_size (t
, j
? 0 : 1))
1819 operand_type_match (i386_operand_type overlap
,
1820 i386_operand_type given
)
1822 i386_operand_type temp
= overlap
;
1824 temp
.bitfield
.jumpabsolute
= 0;
1825 temp
.bitfield
.unspecified
= 0;
1826 temp
.bitfield
.byte
= 0;
1827 temp
.bitfield
.word
= 0;
1828 temp
.bitfield
.dword
= 0;
1829 temp
.bitfield
.fword
= 0;
1830 temp
.bitfield
.qword
= 0;
1831 temp
.bitfield
.tbyte
= 0;
1832 temp
.bitfield
.xmmword
= 0;
1833 temp
.bitfield
.ymmword
= 0;
1834 temp
.bitfield
.zmmword
= 0;
1835 if (operand_type_all_zero (&temp
))
1838 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1839 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1843 i
.error
= operand_type_mismatch
;
1847 /* If given types g0 and g1 are registers they must be of the same type
1848 unless the expected operand type register overlap is null.
1849 Note that Acc in a template matches every size of reg. */
1852 operand_type_register_match (i386_operand_type m0
,
1853 i386_operand_type g0
,
1854 i386_operand_type t0
,
1855 i386_operand_type m1
,
1856 i386_operand_type g1
,
1857 i386_operand_type t1
)
1859 if (!operand_type_check (g0
, reg
))
1862 if (!operand_type_check (g1
, reg
))
1865 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1866 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1867 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1868 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1871 if (m0
.bitfield
.acc
)
1873 t0
.bitfield
.reg8
= 1;
1874 t0
.bitfield
.reg16
= 1;
1875 t0
.bitfield
.reg32
= 1;
1876 t0
.bitfield
.reg64
= 1;
1879 if (m1
.bitfield
.acc
)
1881 t1
.bitfield
.reg8
= 1;
1882 t1
.bitfield
.reg16
= 1;
1883 t1
.bitfield
.reg32
= 1;
1884 t1
.bitfield
.reg64
= 1;
1887 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1888 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1889 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1890 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1893 i
.error
= register_type_mismatch
;
1898 static INLINE
unsigned int
1899 register_number (const reg_entry
*r
)
1901 unsigned int nr
= r
->reg_num
;
1903 if (r
->reg_flags
& RegRex
)
1906 if (r
->reg_flags
& RegVRex
)
1912 static INLINE
unsigned int
1913 mode_from_disp_size (i386_operand_type t
)
1915 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1917 else if (t
.bitfield
.disp16
1918 || t
.bitfield
.disp32
1919 || t
.bitfield
.disp32s
)
1926 fits_in_signed_byte (addressT num
)
1928 return num
+ 0x80 <= 0xff;
1932 fits_in_unsigned_byte (addressT num
)
1938 fits_in_unsigned_word (addressT num
)
1940 return num
<= 0xffff;
1944 fits_in_signed_word (addressT num
)
1946 return num
+ 0x8000 <= 0xffff;
1950 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1955 return num
+ 0x80000000 <= 0xffffffff;
1957 } /* fits_in_signed_long() */
1960 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1965 return num
<= 0xffffffff;
1967 } /* fits_in_unsigned_long() */
1970 fits_in_vec_disp8 (offsetT num
)
1972 int shift
= i
.memshift
;
1978 mask
= (1 << shift
) - 1;
1980 /* Return 0 if NUM isn't properly aligned. */
1984 /* Check if NUM will fit in 8bit after shift. */
1985 return fits_in_signed_byte (num
>> shift
);
1989 fits_in_imm4 (offsetT num
)
1991 return (num
& 0xf) == num
;
1994 static i386_operand_type
1995 smallest_imm_type (offsetT num
)
1997 i386_operand_type t
;
1999 operand_type_set (&t
, 0);
2000 t
.bitfield
.imm64
= 1;
2002 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2004 /* This code is disabled on the 486 because all the Imm1 forms
2005 in the opcode table are slower on the i486. They're the
2006 versions with the implicitly specified single-position
2007 displacement, which has another syntax if you really want to
2009 t
.bitfield
.imm1
= 1;
2010 t
.bitfield
.imm8
= 1;
2011 t
.bitfield
.imm8s
= 1;
2012 t
.bitfield
.imm16
= 1;
2013 t
.bitfield
.imm32
= 1;
2014 t
.bitfield
.imm32s
= 1;
2016 else if (fits_in_signed_byte (num
))
2018 t
.bitfield
.imm8
= 1;
2019 t
.bitfield
.imm8s
= 1;
2020 t
.bitfield
.imm16
= 1;
2021 t
.bitfield
.imm32
= 1;
2022 t
.bitfield
.imm32s
= 1;
2024 else if (fits_in_unsigned_byte (num
))
2026 t
.bitfield
.imm8
= 1;
2027 t
.bitfield
.imm16
= 1;
2028 t
.bitfield
.imm32
= 1;
2029 t
.bitfield
.imm32s
= 1;
2031 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2033 t
.bitfield
.imm16
= 1;
2034 t
.bitfield
.imm32
= 1;
2035 t
.bitfield
.imm32s
= 1;
2037 else if (fits_in_signed_long (num
))
2039 t
.bitfield
.imm32
= 1;
2040 t
.bitfield
.imm32s
= 1;
2042 else if (fits_in_unsigned_long (num
))
2043 t
.bitfield
.imm32
= 1;
2049 offset_in_range (offsetT val
, int size
)
2055 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2056 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2057 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2059 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2065 /* If BFD64, sign extend val for 32bit address mode. */
2066 if (flag_code
!= CODE_64BIT
2067 || i
.prefix
[ADDR_PREFIX
])
2068 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2069 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2072 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2074 char buf1
[40], buf2
[40];
2076 sprint_value (buf1
, val
);
2077 sprint_value (buf2
, val
& mask
);
2078 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2092 a. PREFIX_EXIST if attempting to add a prefix where one from the
2093 same class already exists.
2094 b. PREFIX_LOCK if lock prefix is added.
2095 c. PREFIX_REP if rep/repne prefix is added.
2096 d. PREFIX_OTHER if other prefix is added.
2099 static enum PREFIX_GROUP
2100 add_prefix (unsigned int prefix
)
2102 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2105 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2106 && flag_code
== CODE_64BIT
)
2108 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2109 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2110 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2121 case CS_PREFIX_OPCODE
:
2122 case DS_PREFIX_OPCODE
:
2123 case ES_PREFIX_OPCODE
:
2124 case FS_PREFIX_OPCODE
:
2125 case GS_PREFIX_OPCODE
:
2126 case SS_PREFIX_OPCODE
:
2130 case REPNE_PREFIX_OPCODE
:
2131 case REPE_PREFIX_OPCODE
:
2136 case LOCK_PREFIX_OPCODE
:
2145 case ADDR_PREFIX_OPCODE
:
2149 case DATA_PREFIX_OPCODE
:
2153 if (i
.prefix
[q
] != 0)
2161 i
.prefix
[q
] |= prefix
;
2164 as_bad (_("same type of prefix used twice"));
2170 update_code_flag (int value
, int check
)
2172 PRINTF_LIKE ((*as_error
));
2174 flag_code
= (enum flag_code
) value
;
2175 if (flag_code
== CODE_64BIT
)
2177 cpu_arch_flags
.bitfield
.cpu64
= 1;
2178 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2182 cpu_arch_flags
.bitfield
.cpu64
= 0;
2183 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2185 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2188 as_error
= as_fatal
;
2191 (*as_error
) (_("64bit mode not supported on `%s'."),
2192 cpu_arch_name
? cpu_arch_name
: default_arch
);
2194 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2197 as_error
= as_fatal
;
2200 (*as_error
) (_("32bit mode not supported on `%s'."),
2201 cpu_arch_name
? cpu_arch_name
: default_arch
);
2203 stackop_size
= '\0';
2207 set_code_flag (int value
)
2209 update_code_flag (value
, 0);
2213 set_16bit_gcc_code_flag (int new_code_flag
)
2215 flag_code
= (enum flag_code
) new_code_flag
;
2216 if (flag_code
!= CODE_16BIT
)
2218 cpu_arch_flags
.bitfield
.cpu64
= 0;
2219 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2220 stackop_size
= LONG_MNEM_SUFFIX
;
2224 set_intel_syntax (int syntax_flag
)
2226 /* Find out if register prefixing is specified. */
2227 int ask_naked_reg
= 0;
2230 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2233 int e
= get_symbol_name (&string
);
2235 if (strcmp (string
, "prefix") == 0)
2237 else if (strcmp (string
, "noprefix") == 0)
2240 as_bad (_("bad argument to syntax directive."));
2241 (void) restore_line_pointer (e
);
2243 demand_empty_rest_of_line ();
2245 intel_syntax
= syntax_flag
;
2247 if (ask_naked_reg
== 0)
2248 allow_naked_reg
= (intel_syntax
2249 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2251 allow_naked_reg
= (ask_naked_reg
< 0);
2253 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2255 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2256 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2257 register_prefix
= allow_naked_reg
? "" : "%";
2261 set_intel_mnemonic (int mnemonic_flag
)
2263 intel_mnemonic
= mnemonic_flag
;
2267 set_allow_index_reg (int flag
)
2269 allow_index_reg
= flag
;
2273 set_check (int what
)
2275 enum check_kind
*kind
;
2280 kind
= &operand_check
;
2291 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2294 int e
= get_symbol_name (&string
);
2296 if (strcmp (string
, "none") == 0)
2298 else if (strcmp (string
, "warning") == 0)
2299 *kind
= check_warning
;
2300 else if (strcmp (string
, "error") == 0)
2301 *kind
= check_error
;
2303 as_bad (_("bad argument to %s_check directive."), str
);
2304 (void) restore_line_pointer (e
);
2307 as_bad (_("missing argument for %s_check directive"), str
);
2309 demand_empty_rest_of_line ();
2313 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2314 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2317 static const char *arch
;
2319 /* Intel LIOM is only supported on ELF. */
2325 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2326 use default_arch. */
2327 arch
= cpu_arch_name
;
2329 arch
= default_arch
;
2332 /* If we are targeting Intel MCU, we must enable it. */
2333 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2334 || new_flag
.bitfield
.cpuiamcu
)
2337 /* If we are targeting Intel L1OM, we must enable it. */
2338 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2339 || new_flag
.bitfield
.cpul1om
)
2342 /* If we are targeting Intel K1OM, we must enable it. */
2343 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2344 || new_flag
.bitfield
.cpuk1om
)
2347 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2352 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2356 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2359 int e
= get_symbol_name (&string
);
2361 i386_cpu_flags flags
;
2363 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2365 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2367 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2371 cpu_arch_name
= cpu_arch
[j
].name
;
2372 cpu_sub_arch_name
= NULL
;
2373 cpu_arch_flags
= cpu_arch
[j
].flags
;
2374 if (flag_code
== CODE_64BIT
)
2376 cpu_arch_flags
.bitfield
.cpu64
= 1;
2377 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2381 cpu_arch_flags
.bitfield
.cpu64
= 0;
2382 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2384 cpu_arch_isa
= cpu_arch
[j
].type
;
2385 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2386 if (!cpu_arch_tune_set
)
2388 cpu_arch_tune
= cpu_arch_isa
;
2389 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2394 flags
= cpu_flags_or (cpu_arch_flags
,
2397 if (!valid_iamcu_cpu_flags (&flags
))
2398 as_fatal (_("`%s' isn't valid for Intel MCU"),
2400 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2402 if (cpu_sub_arch_name
)
2404 char *name
= cpu_sub_arch_name
;
2405 cpu_sub_arch_name
= concat (name
,
2407 (const char *) NULL
);
2411 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2412 cpu_arch_flags
= flags
;
2413 cpu_arch_isa_flags
= flags
;
2415 (void) restore_line_pointer (e
);
2416 demand_empty_rest_of_line ();
2421 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2423 /* Disable an ISA entension. */
2424 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2425 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2427 flags
= cpu_flags_and_not (cpu_arch_flags
,
2428 cpu_noarch
[j
].flags
);
2429 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2431 if (cpu_sub_arch_name
)
2433 char *name
= cpu_sub_arch_name
;
2434 cpu_sub_arch_name
= concat (name
, string
,
2435 (const char *) NULL
);
2439 cpu_sub_arch_name
= xstrdup (string
);
2440 cpu_arch_flags
= flags
;
2441 cpu_arch_isa_flags
= flags
;
2443 (void) restore_line_pointer (e
);
2444 demand_empty_rest_of_line ();
2448 j
= ARRAY_SIZE (cpu_arch
);
2451 if (j
>= ARRAY_SIZE (cpu_arch
))
2452 as_bad (_("no such architecture: `%s'"), string
);
2454 *input_line_pointer
= e
;
2457 as_bad (_("missing cpu architecture"));
2459 no_cond_jump_promotion
= 0;
2460 if (*input_line_pointer
== ','
2461 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2466 ++input_line_pointer
;
2467 e
= get_symbol_name (&string
);
2469 if (strcmp (string
, "nojumps") == 0)
2470 no_cond_jump_promotion
= 1;
2471 else if (strcmp (string
, "jumps") == 0)
2474 as_bad (_("no such architecture modifier: `%s'"), string
);
2476 (void) restore_line_pointer (e
);
2479 demand_empty_rest_of_line ();
2482 enum bfd_architecture
2485 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2487 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2488 || flag_code
!= CODE_64BIT
)
2489 as_fatal (_("Intel L1OM is 64bit ELF only"));
2490 return bfd_arch_l1om
;
2492 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2494 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2495 || flag_code
!= CODE_64BIT
)
2496 as_fatal (_("Intel K1OM is 64bit ELF only"));
2497 return bfd_arch_k1om
;
2499 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2501 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2502 || flag_code
== CODE_64BIT
)
2503 as_fatal (_("Intel MCU is 32bit ELF only"));
2504 return bfd_arch_iamcu
;
2507 return bfd_arch_i386
;
2513 if (!strncmp (default_arch
, "x86_64", 6))
2515 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2517 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2518 || default_arch
[6] != '\0')
2519 as_fatal (_("Intel L1OM is 64bit ELF only"));
2520 return bfd_mach_l1om
;
2522 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2524 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2525 || default_arch
[6] != '\0')
2526 as_fatal (_("Intel K1OM is 64bit ELF only"));
2527 return bfd_mach_k1om
;
2529 else if (default_arch
[6] == '\0')
2530 return bfd_mach_x86_64
;
2532 return bfd_mach_x64_32
;
2534 else if (!strcmp (default_arch
, "i386")
2535 || !strcmp (default_arch
, "iamcu"))
2537 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2539 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2540 as_fatal (_("Intel MCU is 32bit ELF only"));
2541 return bfd_mach_i386_iamcu
;
2544 return bfd_mach_i386_i386
;
2547 as_fatal (_("unknown architecture"));
2553 const char *hash_err
;
2555 /* Initialize op_hash hash table. */
2556 op_hash
= hash_new ();
2559 const insn_template
*optab
;
2560 templates
*core_optab
;
2562 /* Setup for loop. */
2564 core_optab
= XNEW (templates
);
2565 core_optab
->start
= optab
;
2570 if (optab
->name
== NULL
2571 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2573 /* different name --> ship out current template list;
2574 add to hash table; & begin anew. */
2575 core_optab
->end
= optab
;
2576 hash_err
= hash_insert (op_hash
,
2578 (void *) core_optab
);
2581 as_fatal (_("can't hash %s: %s"),
2585 if (optab
->name
== NULL
)
2587 core_optab
= XNEW (templates
);
2588 core_optab
->start
= optab
;
2593 /* Initialize reg_hash hash table. */
2594 reg_hash
= hash_new ();
2596 const reg_entry
*regtab
;
2597 unsigned int regtab_size
= i386_regtab_size
;
2599 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2601 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2603 as_fatal (_("can't hash %s: %s"),
2609 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2614 for (c
= 0; c
< 256; c
++)
2619 mnemonic_chars
[c
] = c
;
2620 register_chars
[c
] = c
;
2621 operand_chars
[c
] = c
;
2623 else if (ISLOWER (c
))
2625 mnemonic_chars
[c
] = c
;
2626 register_chars
[c
] = c
;
2627 operand_chars
[c
] = c
;
2629 else if (ISUPPER (c
))
2631 mnemonic_chars
[c
] = TOLOWER (c
);
2632 register_chars
[c
] = mnemonic_chars
[c
];
2633 operand_chars
[c
] = c
;
2635 else if (c
== '{' || c
== '}')
2636 operand_chars
[c
] = c
;
2638 if (ISALPHA (c
) || ISDIGIT (c
))
2639 identifier_chars
[c
] = c
;
2642 identifier_chars
[c
] = c
;
2643 operand_chars
[c
] = c
;
2648 identifier_chars
['@'] = '@';
2651 identifier_chars
['?'] = '?';
2652 operand_chars
['?'] = '?';
2654 digit_chars
['-'] = '-';
2655 mnemonic_chars
['_'] = '_';
2656 mnemonic_chars
['-'] = '-';
2657 mnemonic_chars
['.'] = '.';
2658 identifier_chars
['_'] = '_';
2659 identifier_chars
['.'] = '.';
2661 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2662 operand_chars
[(unsigned char) *p
] = *p
;
2665 if (flag_code
== CODE_64BIT
)
2667 #if defined (OBJ_COFF) && defined (TE_PE)
2668 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2671 x86_dwarf2_return_column
= 16;
2673 x86_cie_data_alignment
= -8;
2677 x86_dwarf2_return_column
= 8;
2678 x86_cie_data_alignment
= -4;
2683 i386_print_statistics (FILE *file
)
2685 hash_print_statistics (file
, "i386 opcode", op_hash
);
2686 hash_print_statistics (file
, "i386 register", reg_hash
);
2691 /* Debugging routines for md_assemble. */
2692 static void pte (insn_template
*);
2693 static void pt (i386_operand_type
);
2694 static void pe (expressionS
*);
2695 static void ps (symbolS
*);
2698 pi (char *line
, i386_insn
*x
)
2702 fprintf (stdout
, "%s: template ", line
);
2704 fprintf (stdout
, " address: base %s index %s scale %x\n",
2705 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2706 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2707 x
->log2_scale_factor
);
2708 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2709 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2710 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2711 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2712 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2713 (x
->rex
& REX_W
) != 0,
2714 (x
->rex
& REX_R
) != 0,
2715 (x
->rex
& REX_X
) != 0,
2716 (x
->rex
& REX_B
) != 0);
2717 for (j
= 0; j
< x
->operands
; j
++)
2719 fprintf (stdout
, " #%d: ", j
+ 1);
2721 fprintf (stdout
, "\n");
2722 if (x
->types
[j
].bitfield
.reg8
2723 || x
->types
[j
].bitfield
.reg16
2724 || x
->types
[j
].bitfield
.reg32
2725 || x
->types
[j
].bitfield
.reg64
2726 || x
->types
[j
].bitfield
.regmmx
2727 || x
->types
[j
].bitfield
.regxmm
2728 || x
->types
[j
].bitfield
.regymm
2729 || x
->types
[j
].bitfield
.regzmm
2730 || x
->types
[j
].bitfield
.sreg2
2731 || x
->types
[j
].bitfield
.sreg3
2732 || x
->types
[j
].bitfield
.control
2733 || x
->types
[j
].bitfield
.debug
2734 || x
->types
[j
].bitfield
.test
)
2735 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2736 if (operand_type_check (x
->types
[j
], imm
))
2738 if (operand_type_check (x
->types
[j
], disp
))
2739 pe (x
->op
[j
].disps
);
2744 pte (insn_template
*t
)
2747 fprintf (stdout
, " %d operands ", t
->operands
);
2748 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2749 if (t
->extension_opcode
!= None
)
2750 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2751 if (t
->opcode_modifier
.d
)
2752 fprintf (stdout
, "D");
2753 if (t
->opcode_modifier
.w
)
2754 fprintf (stdout
, "W");
2755 fprintf (stdout
, "\n");
2756 for (j
= 0; j
< t
->operands
; j
++)
2758 fprintf (stdout
, " #%d type ", j
+ 1);
2759 pt (t
->operand_types
[j
]);
2760 fprintf (stdout
, "\n");
2767 fprintf (stdout
, " operation %d\n", e
->X_op
);
2768 fprintf (stdout
, " add_number %ld (%lx)\n",
2769 (long) e
->X_add_number
, (long) e
->X_add_number
);
2770 if (e
->X_add_symbol
)
2772 fprintf (stdout
, " add_symbol ");
2773 ps (e
->X_add_symbol
);
2774 fprintf (stdout
, "\n");
2778 fprintf (stdout
, " op_symbol ");
2779 ps (e
->X_op_symbol
);
2780 fprintf (stdout
, "\n");
2787 fprintf (stdout
, "%s type %s%s",
2789 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2790 segment_name (S_GET_SEGMENT (s
)));
2793 static struct type_name
2795 i386_operand_type mask
;
2798 const type_names
[] =
2800 { OPERAND_TYPE_REG8
, "r8" },
2801 { OPERAND_TYPE_REG16
, "r16" },
2802 { OPERAND_TYPE_REG32
, "r32" },
2803 { OPERAND_TYPE_REG64
, "r64" },
2804 { OPERAND_TYPE_IMM8
, "i8" },
2805 { OPERAND_TYPE_IMM8
, "i8s" },
2806 { OPERAND_TYPE_IMM16
, "i16" },
2807 { OPERAND_TYPE_IMM32
, "i32" },
2808 { OPERAND_TYPE_IMM32S
, "i32s" },
2809 { OPERAND_TYPE_IMM64
, "i64" },
2810 { OPERAND_TYPE_IMM1
, "i1" },
2811 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2812 { OPERAND_TYPE_DISP8
, "d8" },
2813 { OPERAND_TYPE_DISP16
, "d16" },
2814 { OPERAND_TYPE_DISP32
, "d32" },
2815 { OPERAND_TYPE_DISP32S
, "d32s" },
2816 { OPERAND_TYPE_DISP64
, "d64" },
2817 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2818 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2819 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2820 { OPERAND_TYPE_CONTROL
, "control reg" },
2821 { OPERAND_TYPE_TEST
, "test reg" },
2822 { OPERAND_TYPE_DEBUG
, "debug reg" },
2823 { OPERAND_TYPE_FLOATREG
, "FReg" },
2824 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2825 { OPERAND_TYPE_SREG2
, "SReg2" },
2826 { OPERAND_TYPE_SREG3
, "SReg3" },
2827 { OPERAND_TYPE_ACC
, "Acc" },
2828 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2829 { OPERAND_TYPE_REGMMX
, "rMMX" },
2830 { OPERAND_TYPE_REGXMM
, "rXMM" },
2831 { OPERAND_TYPE_REGYMM
, "rYMM" },
2832 { OPERAND_TYPE_REGZMM
, "rZMM" },
2833 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2834 { OPERAND_TYPE_ESSEG
, "es" },
2838 pt (i386_operand_type t
)
2841 i386_operand_type a
;
2843 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2845 a
= operand_type_and (t
, type_names
[j
].mask
);
2846 if (!operand_type_all_zero (&a
))
2847 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2852 #endif /* DEBUG386 */
2854 static bfd_reloc_code_real_type
2855 reloc (unsigned int size
,
2858 bfd_reloc_code_real_type other
)
2860 if (other
!= NO_RELOC
)
2862 reloc_howto_type
*rel
;
2867 case BFD_RELOC_X86_64_GOT32
:
2868 return BFD_RELOC_X86_64_GOT64
;
2870 case BFD_RELOC_X86_64_GOTPLT64
:
2871 return BFD_RELOC_X86_64_GOTPLT64
;
2873 case BFD_RELOC_X86_64_PLTOFF64
:
2874 return BFD_RELOC_X86_64_PLTOFF64
;
2876 case BFD_RELOC_X86_64_GOTPC32
:
2877 other
= BFD_RELOC_X86_64_GOTPC64
;
2879 case BFD_RELOC_X86_64_GOTPCREL
:
2880 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2882 case BFD_RELOC_X86_64_TPOFF32
:
2883 other
= BFD_RELOC_X86_64_TPOFF64
;
2885 case BFD_RELOC_X86_64_DTPOFF32
:
2886 other
= BFD_RELOC_X86_64_DTPOFF64
;
2892 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2893 if (other
== BFD_RELOC_SIZE32
)
2896 other
= BFD_RELOC_SIZE64
;
2899 as_bad (_("there are no pc-relative size relocations"));
2905 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2906 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2909 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2911 as_bad (_("unknown relocation (%u)"), other
);
2912 else if (size
!= bfd_get_reloc_size (rel
))
2913 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2914 bfd_get_reloc_size (rel
),
2916 else if (pcrel
&& !rel
->pc_relative
)
2917 as_bad (_("non-pc-relative relocation for pc-relative field"));
2918 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2920 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2922 as_bad (_("relocated field and relocation type differ in signedness"));
2931 as_bad (_("there are no unsigned pc-relative relocations"));
2934 case 1: return BFD_RELOC_8_PCREL
;
2935 case 2: return BFD_RELOC_16_PCREL
;
2936 case 4: return BFD_RELOC_32_PCREL
;
2937 case 8: return BFD_RELOC_64_PCREL
;
2939 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2946 case 4: return BFD_RELOC_X86_64_32S
;
2951 case 1: return BFD_RELOC_8
;
2952 case 2: return BFD_RELOC_16
;
2953 case 4: return BFD_RELOC_32
;
2954 case 8: return BFD_RELOC_64
;
2956 as_bad (_("cannot do %s %u byte relocation"),
2957 sign
> 0 ? "signed" : "unsigned", size
);
2963 /* Here we decide which fixups can be adjusted to make them relative to
2964 the beginning of the section instead of the symbol. Basically we need
2965 to make sure that the dynamic relocations are done correctly, so in
2966 some cases we force the original symbol to be used. */
2969 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2975 /* Don't adjust pc-relative references to merge sections in 64-bit
2977 if (use_rela_relocations
2978 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2982 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2983 and changed later by validate_fix. */
2984 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2985 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2988 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2989 for size relocations. */
2990 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2991 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2992 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2993 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2994 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2995 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2996 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2997 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2998 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2999 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3000 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3001 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3002 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3003 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3004 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3005 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3006 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3007 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3008 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3009 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3010 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3011 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3012 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3013 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3014 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3015 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3016 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3017 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3018 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3019 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3020 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3021 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3022 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3029 intel_float_operand (const char *mnemonic
)
3031 /* Note that the value returned is meaningful only for opcodes with (memory)
3032 operands, hence the code here is free to improperly handle opcodes that
3033 have no operands (for better performance and smaller code). */
3035 if (mnemonic
[0] != 'f')
3036 return 0; /* non-math */
3038 switch (mnemonic
[1])
3040 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3041 the fs segment override prefix not currently handled because no
3042 call path can make opcodes without operands get here */
3044 return 2 /* integer op */;
3046 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3047 return 3; /* fldcw/fldenv */
3050 if (mnemonic
[2] != 'o' /* fnop */)
3051 return 3; /* non-waiting control op */
3054 if (mnemonic
[2] == 's')
3055 return 3; /* frstor/frstpm */
3058 if (mnemonic
[2] == 'a')
3059 return 3; /* fsave */
3060 if (mnemonic
[2] == 't')
3062 switch (mnemonic
[3])
3064 case 'c': /* fstcw */
3065 case 'd': /* fstdw */
3066 case 'e': /* fstenv */
3067 case 's': /* fsts[gw] */
3073 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3074 return 0; /* fxsave/fxrstor are not really math ops */
3081 /* Build the VEX prefix. */
3084 build_vex_prefix (const insn_template
*t
)
3086 unsigned int register_specifier
;
3087 unsigned int implied_prefix
;
3088 unsigned int vector_length
;
3090 /* Check register specifier. */
3091 if (i
.vex
.register_specifier
)
3093 register_specifier
=
3094 ~register_number (i
.vex
.register_specifier
) & 0xf;
3095 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3098 register_specifier
= 0xf;
3100 /* Use 2-byte VEX prefix by swappping destination and source
3103 && i
.operands
== i
.reg_operands
3104 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3105 && i
.tm
.opcode_modifier
.s
3108 unsigned int xchg
= i
.operands
- 1;
3109 union i386_op temp_op
;
3110 i386_operand_type temp_type
;
3112 temp_type
= i
.types
[xchg
];
3113 i
.types
[xchg
] = i
.types
[0];
3114 i
.types
[0] = temp_type
;
3115 temp_op
= i
.op
[xchg
];
3116 i
.op
[xchg
] = i
.op
[0];
3119 gas_assert (i
.rm
.mode
== 3);
3123 i
.rm
.regmem
= i
.rm
.reg
;
3126 /* Use the next insn. */
3130 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3131 vector_length
= avxscalar
;
3133 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3135 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3140 case DATA_PREFIX_OPCODE
:
3143 case REPE_PREFIX_OPCODE
:
3146 case REPNE_PREFIX_OPCODE
:
3153 /* Use 2-byte VEX prefix if possible. */
3154 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3155 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3156 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3158 /* 2-byte VEX prefix. */
3162 i
.vex
.bytes
[0] = 0xc5;
3164 /* Check the REX.R bit. */
3165 r
= (i
.rex
& REX_R
) ? 0 : 1;
3166 i
.vex
.bytes
[1] = (r
<< 7
3167 | register_specifier
<< 3
3168 | vector_length
<< 2
3173 /* 3-byte VEX prefix. */
3178 switch (i
.tm
.opcode_modifier
.vexopcode
)
3182 i
.vex
.bytes
[0] = 0xc4;
3186 i
.vex
.bytes
[0] = 0xc4;
3190 i
.vex
.bytes
[0] = 0xc4;
3194 i
.vex
.bytes
[0] = 0x8f;
3198 i
.vex
.bytes
[0] = 0x8f;
3202 i
.vex
.bytes
[0] = 0x8f;
3208 /* The high 3 bits of the second VEX byte are 1's compliment
3209 of RXB bits from REX. */
3210 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3212 /* Check the REX.W bit. */
3213 w
= (i
.rex
& REX_W
) ? 1 : 0;
3214 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3217 i
.vex
.bytes
[2] = (w
<< 7
3218 | register_specifier
<< 3
3219 | vector_length
<< 2
3224 /* Build the EVEX prefix. */
3227 build_evex_prefix (void)
3229 unsigned int register_specifier
;
3230 unsigned int implied_prefix
;
3232 rex_byte vrex_used
= 0;
3234 /* Check register specifier. */
3235 if (i
.vex
.register_specifier
)
3237 gas_assert ((i
.vrex
& REX_X
) == 0);
3239 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3240 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3241 register_specifier
+= 8;
3242 /* The upper 16 registers are encoded in the fourth byte of the
3244 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3245 i
.vex
.bytes
[3] = 0x8;
3246 register_specifier
= ~register_specifier
& 0xf;
3250 register_specifier
= 0xf;
3252 /* Encode upper 16 vector index register in the fourth byte of
3254 if (!(i
.vrex
& REX_X
))
3255 i
.vex
.bytes
[3] = 0x8;
3260 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3265 case DATA_PREFIX_OPCODE
:
3268 case REPE_PREFIX_OPCODE
:
3271 case REPNE_PREFIX_OPCODE
:
3278 /* 4 byte EVEX prefix. */
3280 i
.vex
.bytes
[0] = 0x62;
3283 switch (i
.tm
.opcode_modifier
.vexopcode
)
3299 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3301 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3303 /* The fifth bit of the second EVEX byte is 1's compliment of the
3304 REX_R bit in VREX. */
3305 if (!(i
.vrex
& REX_R
))
3306 i
.vex
.bytes
[1] |= 0x10;
3310 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3312 /* When all operands are registers, the REX_X bit in REX is not
3313 used. We reuse it to encode the upper 16 registers, which is
3314 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3315 as 1's compliment. */
3316 if ((i
.vrex
& REX_B
))
3319 i
.vex
.bytes
[1] &= ~0x40;
3323 /* EVEX instructions shouldn't need the REX prefix. */
3324 i
.vrex
&= ~vrex_used
;
3325 gas_assert (i
.vrex
== 0);
3327 /* Check the REX.W bit. */
3328 w
= (i
.rex
& REX_W
) ? 1 : 0;
3329 if (i
.tm
.opcode_modifier
.vexw
)
3331 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3334 /* If w is not set it means we are dealing with WIG instruction. */
3337 if (evexwig
== evexw1
)
3341 /* Encode the U bit. */
3342 implied_prefix
|= 0x4;
3344 /* The third byte of the EVEX prefix. */
3345 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3347 /* The fourth byte of the EVEX prefix. */
3348 /* The zeroing-masking bit. */
3349 if (i
.mask
&& i
.mask
->zeroing
)
3350 i
.vex
.bytes
[3] |= 0x80;
3352 /* Don't always set the broadcast bit if there is no RC. */
3355 /* Encode the vector length. */
3356 unsigned int vec_length
;
3358 switch (i
.tm
.opcode_modifier
.evex
)
3360 case EVEXLIG
: /* LL' is ignored */
3361 vec_length
= evexlig
<< 5;
3364 vec_length
= 0 << 5;
3367 vec_length
= 1 << 5;
3370 vec_length
= 2 << 5;
3376 i
.vex
.bytes
[3] |= vec_length
;
3377 /* Encode the broadcast bit. */
3379 i
.vex
.bytes
[3] |= 0x10;
3383 if (i
.rounding
->type
!= saeonly
)
3384 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3386 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3389 if (i
.mask
&& i
.mask
->mask
)
3390 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3394 process_immext (void)
3398 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3401 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3402 with an opcode suffix which is coded in the same place as an
3403 8-bit immediate field would be.
3404 Here we check those operands and remove them afterwards. */
3407 for (x
= 0; x
< i
.operands
; x
++)
3408 if (register_number (i
.op
[x
].regs
) != x
)
3409 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3410 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3416 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3418 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3419 suffix which is coded in the same place as an 8-bit immediate
3421 Here we check those operands and remove them afterwards. */
3424 if (i
.operands
!= 3)
3427 for (x
= 0; x
< 2; x
++)
3428 if (register_number (i
.op
[x
].regs
) != x
)
3429 goto bad_register_operand
;
3431 /* Check for third operand for mwaitx/monitorx insn. */
3432 if (register_number (i
.op
[x
].regs
)
3433 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3435 bad_register_operand
:
3436 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3437 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3444 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3445 which is coded in the same place as an 8-bit immediate field
3446 would be. Here we fake an 8-bit immediate operand from the
3447 opcode suffix stored in tm.extension_opcode.
3449 AVX instructions also use this encoding, for some of
3450 3 argument instructions. */
3452 gas_assert (i
.imm_operands
<= 1
3454 || ((i
.tm
.opcode_modifier
.vex
3455 || i
.tm
.opcode_modifier
.evex
)
3456 && i
.operands
<= 4)));
3458 exp
= &im_expressions
[i
.imm_operands
++];
3459 i
.op
[i
.operands
].imms
= exp
;
3460 i
.types
[i
.operands
] = imm8
;
3462 exp
->X_op
= O_constant
;
3463 exp
->X_add_number
= i
.tm
.extension_opcode
;
3464 i
.tm
.extension_opcode
= None
;
3471 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3476 as_bad (_("invalid instruction `%s' after `%s'"),
3477 i
.tm
.name
, i
.hle_prefix
);
3480 if (i
.prefix
[LOCK_PREFIX
])
3482 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3486 case HLEPrefixRelease
:
3487 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3489 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3493 if (i
.mem_operands
== 0
3494 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3496 as_bad (_("memory destination needed for instruction `%s'"
3497 " after `xrelease'"), i
.tm
.name
);
3504 /* This is the guts of the machine-dependent assembler. LINE points to a
3505 machine dependent instruction. This function is supposed to emit
3506 the frags/bytes it assembles to. */
3509 md_assemble (char *line
)
3512 char mnemonic
[MAX_MNEM_SIZE
];
3513 const insn_template
*t
;
3515 /* Initialize globals. */
3516 memset (&i
, '\0', sizeof (i
));
3517 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3518 i
.reloc
[j
] = NO_RELOC
;
3519 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3520 memset (im_expressions
, '\0', sizeof (im_expressions
));
3521 save_stack_p
= save_stack
;
3523 /* First parse an instruction mnemonic & call i386_operand for the operands.
3524 We assume that the scrubber has arranged it so that line[0] is the valid
3525 start of a (possibly prefixed) mnemonic. */
3527 line
= parse_insn (line
, mnemonic
);
3531 line
= parse_operands (line
, mnemonic
);
3536 /* Now we've parsed the mnemonic into a set of templates, and have the
3537 operands at hand. */
3539 /* All intel opcodes have reversed operands except for "bound" and
3540 "enter". We also don't reverse intersegment "jmp" and "call"
3541 instructions with 2 immediate operands so that the immediate segment
3542 precedes the offset, as it does when in AT&T mode. */
3545 && (strcmp (mnemonic
, "bound") != 0)
3546 && (strcmp (mnemonic
, "invlpga") != 0)
3547 && !(operand_type_check (i
.types
[0], imm
)
3548 && operand_type_check (i
.types
[1], imm
)))
3551 /* The order of the immediates should be reversed
3552 for 2 immediates extrq and insertq instructions */
3553 if (i
.imm_operands
== 2
3554 && (strcmp (mnemonic
, "extrq") == 0
3555 || strcmp (mnemonic
, "insertq") == 0))
3556 swap_2_operands (0, 1);
3561 /* Don't optimize displacement for movabs since it only takes 64bit
3564 && i
.disp_encoding
!= disp_encoding_32bit
3565 && (flag_code
!= CODE_64BIT
3566 || strcmp (mnemonic
, "movabs") != 0))
3569 /* Next, we find a template that matches the given insn,
3570 making sure the overlap of the given operands types is consistent
3571 with the template operand types. */
3573 if (!(t
= match_template ()))
3576 if (sse_check
!= check_none
3577 && !i
.tm
.opcode_modifier
.noavx
3578 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3579 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3580 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3581 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3582 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3583 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3585 (sse_check
== check_warning
3587 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3590 /* Zap movzx and movsx suffix. The suffix has been set from
3591 "word ptr" or "byte ptr" on the source operand in Intel syntax
3592 or extracted from mnemonic in AT&T syntax. But we'll use
3593 the destination register to choose the suffix for encoding. */
3594 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3596 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3597 there is no suffix, the default will be byte extension. */
3598 if (i
.reg_operands
!= 2
3601 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3606 if (i
.tm
.opcode_modifier
.fwait
)
3607 if (!add_prefix (FWAIT_OPCODE
))
3610 /* Check if REP prefix is OK. */
3611 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3613 as_bad (_("invalid instruction `%s' after `%s'"),
3614 i
.tm
.name
, i
.rep_prefix
);
3618 /* Check for lock without a lockable instruction. Destination operand
3619 must be memory unless it is xchg (0x86). */
3620 if (i
.prefix
[LOCK_PREFIX
]
3621 && (!i
.tm
.opcode_modifier
.islockable
3622 || i
.mem_operands
== 0
3623 || (i
.tm
.base_opcode
!= 0x86
3624 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3626 as_bad (_("expecting lockable instruction after `lock'"));
3630 /* Check if HLE prefix is OK. */
3631 if (i
.hle_prefix
&& !check_hle ())
3634 /* Check BND prefix. */
3635 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3636 as_bad (_("expecting valid branch instruction after `bnd'"));
3638 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3639 && flag_code
== CODE_64BIT
3640 && i
.prefix
[ADDR_PREFIX
])
3641 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3643 /* Insert BND prefix. */
3645 && i
.tm
.opcode_modifier
.bndprefixok
3646 && !i
.prefix
[BND_PREFIX
])
3647 add_prefix (BND_PREFIX_OPCODE
);
3649 /* Check string instruction segment overrides. */
3650 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3652 if (!check_string ())
3654 i
.disp_operands
= 0;
3657 if (!process_suffix ())
3660 /* Update operand types. */
3661 for (j
= 0; j
< i
.operands
; j
++)
3662 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3664 /* Make still unresolved immediate matches conform to size of immediate
3665 given in i.suffix. */
3666 if (!finalize_imm ())
3669 if (i
.types
[0].bitfield
.imm1
)
3670 i
.imm_operands
= 0; /* kludge for shift insns. */
3672 /* We only need to check those implicit registers for instructions
3673 with 3 operands or less. */
3674 if (i
.operands
<= 3)
3675 for (j
= 0; j
< i
.operands
; j
++)
3676 if (i
.types
[j
].bitfield
.inoutportreg
3677 || i
.types
[j
].bitfield
.shiftcount
3678 || i
.types
[j
].bitfield
.acc
3679 || i
.types
[j
].bitfield
.floatacc
)
3682 /* ImmExt should be processed after SSE2AVX. */
3683 if (!i
.tm
.opcode_modifier
.sse2avx
3684 && i
.tm
.opcode_modifier
.immext
)
3687 /* For insns with operands there are more diddles to do to the opcode. */
3690 if (!process_operands ())
3693 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3695 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3696 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3699 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3701 if (flag_code
== CODE_16BIT
)
3703 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3708 if (i
.tm
.opcode_modifier
.vex
)
3709 build_vex_prefix (t
);
3711 build_evex_prefix ();
3714 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3715 instructions may define INT_OPCODE as well, so avoid this corner
3716 case for those instructions that use MODRM. */
3717 if (i
.tm
.base_opcode
== INT_OPCODE
3718 && !i
.tm
.opcode_modifier
.modrm
3719 && i
.op
[0].imms
->X_add_number
== 3)
3721 i
.tm
.base_opcode
= INT3_OPCODE
;
3725 if ((i
.tm
.opcode_modifier
.jump
3726 || i
.tm
.opcode_modifier
.jumpbyte
3727 || i
.tm
.opcode_modifier
.jumpdword
)
3728 && i
.op
[0].disps
->X_op
== O_constant
)
3730 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3731 the absolute address given by the constant. Since ix86 jumps and
3732 calls are pc relative, we need to generate a reloc. */
3733 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3734 i
.op
[0].disps
->X_op
= O_symbol
;
3737 if (i
.tm
.opcode_modifier
.rex64
)
3740 /* For 8 bit registers we need an empty rex prefix. Also if the
3741 instruction already has a prefix, we need to convert old
3742 registers to new ones. */
3744 if ((i
.types
[0].bitfield
.reg8
3745 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3746 || (i
.types
[1].bitfield
.reg8
3747 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3748 || ((i
.types
[0].bitfield
.reg8
3749 || i
.types
[1].bitfield
.reg8
)
3754 i
.rex
|= REX_OPCODE
;
3755 for (x
= 0; x
< 2; x
++)
3757 /* Look for 8 bit operand that uses old registers. */
3758 if (i
.types
[x
].bitfield
.reg8
3759 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3761 /* In case it is "hi" register, give up. */
3762 if (i
.op
[x
].regs
->reg_num
> 3)
3763 as_bad (_("can't encode register '%s%s' in an "
3764 "instruction requiring REX prefix."),
3765 register_prefix
, i
.op
[x
].regs
->reg_name
);
3767 /* Otherwise it is equivalent to the extended register.
3768 Since the encoding doesn't change this is merely
3769 cosmetic cleanup for debug output. */
3771 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3777 add_prefix (REX_OPCODE
| i
.rex
);
3779 /* We are ready to output the insn. */
3784 parse_insn (char *line
, char *mnemonic
)
3787 char *token_start
= l
;
3790 const insn_template
*t
;
3796 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3801 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3803 as_bad (_("no such instruction: `%s'"), token_start
);
3808 if (!is_space_char (*l
)
3809 && *l
!= END_OF_INSN
3811 || (*l
!= PREFIX_SEPARATOR
3814 as_bad (_("invalid character %s in mnemonic"),
3815 output_invalid (*l
));
3818 if (token_start
== l
)
3820 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3821 as_bad (_("expecting prefix; got nothing"));
3823 as_bad (_("expecting mnemonic; got nothing"));
3827 /* Look up instruction (or prefix) via hash table. */
3828 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3830 if (*l
!= END_OF_INSN
3831 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3832 && current_templates
3833 && current_templates
->start
->opcode_modifier
.isprefix
)
3835 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3837 as_bad ((flag_code
!= CODE_64BIT
3838 ? _("`%s' is only supported in 64-bit mode")
3839 : _("`%s' is not supported in 64-bit mode")),
3840 current_templates
->start
->name
);
3843 /* If we are in 16-bit mode, do not allow addr16 or data16.
3844 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3845 if ((current_templates
->start
->opcode_modifier
.size16
3846 || current_templates
->start
->opcode_modifier
.size32
)
3847 && flag_code
!= CODE_64BIT
3848 && (current_templates
->start
->opcode_modifier
.size32
3849 ^ (flag_code
== CODE_16BIT
)))
3851 as_bad (_("redundant %s prefix"),
3852 current_templates
->start
->name
);
3855 /* Add prefix, checking for repeated prefixes. */
3856 switch (add_prefix (current_templates
->start
->base_opcode
))
3861 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3862 i
.hle_prefix
= current_templates
->start
->name
;
3863 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3864 i
.bnd_prefix
= current_templates
->start
->name
;
3866 i
.rep_prefix
= current_templates
->start
->name
;
3871 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3878 if (!current_templates
)
3880 /* Check if we should swap operand or force 32bit displacement in
3882 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3884 else if (mnem_p
- 3 == dot_p
3887 i
.disp_encoding
= disp_encoding_8bit
;
3888 else if (mnem_p
- 4 == dot_p
3892 i
.disp_encoding
= disp_encoding_32bit
;
3897 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3900 if (!current_templates
)
3903 /* See if we can get a match by trimming off a suffix. */
3906 case WORD_MNEM_SUFFIX
:
3907 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3908 i
.suffix
= SHORT_MNEM_SUFFIX
;
3910 case BYTE_MNEM_SUFFIX
:
3911 case QWORD_MNEM_SUFFIX
:
3912 i
.suffix
= mnem_p
[-1];
3914 current_templates
= (const templates
*) hash_find (op_hash
,
3917 case SHORT_MNEM_SUFFIX
:
3918 case LONG_MNEM_SUFFIX
:
3921 i
.suffix
= mnem_p
[-1];
3923 current_templates
= (const templates
*) hash_find (op_hash
,
3932 if (intel_float_operand (mnemonic
) == 1)
3933 i
.suffix
= SHORT_MNEM_SUFFIX
;
3935 i
.suffix
= LONG_MNEM_SUFFIX
;
3937 current_templates
= (const templates
*) hash_find (op_hash
,
3942 if (!current_templates
)
3944 as_bad (_("no such instruction: `%s'"), token_start
);
3949 if (current_templates
->start
->opcode_modifier
.jump
3950 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3952 /* Check for a branch hint. We allow ",pt" and ",pn" for
3953 predict taken and predict not taken respectively.
3954 I'm not sure that branch hints actually do anything on loop
3955 and jcxz insns (JumpByte) for current Pentium4 chips. They
3956 may work in the future and it doesn't hurt to accept them
3958 if (l
[0] == ',' && l
[1] == 'p')
3962 if (!add_prefix (DS_PREFIX_OPCODE
))
3966 else if (l
[2] == 'n')
3968 if (!add_prefix (CS_PREFIX_OPCODE
))
3974 /* Any other comma loses. */
3977 as_bad (_("invalid character %s in mnemonic"),
3978 output_invalid (*l
));
3982 /* Check if instruction is supported on specified architecture. */
3984 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3986 supported
|= cpu_flags_match (t
);
3987 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3991 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3993 as_bad (flag_code
== CODE_64BIT
3994 ? _("`%s' is not supported in 64-bit mode")
3995 : _("`%s' is only supported in 64-bit mode"),
3996 current_templates
->start
->name
);
3999 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4001 as_bad (_("`%s' is not supported on `%s%s'"),
4002 current_templates
->start
->name
,
4003 cpu_arch_name
? cpu_arch_name
: default_arch
,
4004 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4009 if (!cpu_arch_flags
.bitfield
.cpui386
4010 && (flag_code
!= CODE_16BIT
))
4012 as_warn (_("use .code16 to ensure correct addressing mode"));
4019 parse_operands (char *l
, const char *mnemonic
)
4023 /* 1 if operand is pending after ','. */
4024 unsigned int expecting_operand
= 0;
4026 /* Non-zero if operand parens not balanced. */
4027 unsigned int paren_not_balanced
;
4029 while (*l
!= END_OF_INSN
)
4031 /* Skip optional white space before operand. */
4032 if (is_space_char (*l
))
4034 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4036 as_bad (_("invalid character %s before operand %d"),
4037 output_invalid (*l
),
4041 token_start
= l
; /* After white space. */
4042 paren_not_balanced
= 0;
4043 while (paren_not_balanced
|| *l
!= ',')
4045 if (*l
== END_OF_INSN
)
4047 if (paren_not_balanced
)
4050 as_bad (_("unbalanced parenthesis in operand %d."),
4053 as_bad (_("unbalanced brackets in operand %d."),
4058 break; /* we are done */
4060 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4062 as_bad (_("invalid character %s in operand %d"),
4063 output_invalid (*l
),
4070 ++paren_not_balanced
;
4072 --paren_not_balanced
;
4077 ++paren_not_balanced
;
4079 --paren_not_balanced
;
4083 if (l
!= token_start
)
4084 { /* Yes, we've read in another operand. */
4085 unsigned int operand_ok
;
4086 this_operand
= i
.operands
++;
4087 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4088 if (i
.operands
> MAX_OPERANDS
)
4090 as_bad (_("spurious operands; (%d operands/instruction max)"),
4094 /* Now parse operand adding info to 'i' as we go along. */
4095 END_STRING_AND_SAVE (l
);
4099 i386_intel_operand (token_start
,
4100 intel_float_operand (mnemonic
));
4102 operand_ok
= i386_att_operand (token_start
);
4104 RESTORE_END_STRING (l
);
4110 if (expecting_operand
)
4112 expecting_operand_after_comma
:
4113 as_bad (_("expecting operand after ','; got nothing"));
4118 as_bad (_("expecting operand before ','; got nothing"));
4123 /* Now *l must be either ',' or END_OF_INSN. */
4126 if (*++l
== END_OF_INSN
)
4128 /* Just skip it, if it's \n complain. */
4129 goto expecting_operand_after_comma
;
4131 expecting_operand
= 1;
4138 swap_2_operands (int xchg1
, int xchg2
)
4140 union i386_op temp_op
;
4141 i386_operand_type temp_type
;
4142 enum bfd_reloc_code_real temp_reloc
;
4144 temp_type
= i
.types
[xchg2
];
4145 i
.types
[xchg2
] = i
.types
[xchg1
];
4146 i
.types
[xchg1
] = temp_type
;
4147 temp_op
= i
.op
[xchg2
];
4148 i
.op
[xchg2
] = i
.op
[xchg1
];
4149 i
.op
[xchg1
] = temp_op
;
4150 temp_reloc
= i
.reloc
[xchg2
];
4151 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4152 i
.reloc
[xchg1
] = temp_reloc
;
4156 if (i
.mask
->operand
== xchg1
)
4157 i
.mask
->operand
= xchg2
;
4158 else if (i
.mask
->operand
== xchg2
)
4159 i
.mask
->operand
= xchg1
;
4163 if (i
.broadcast
->operand
== xchg1
)
4164 i
.broadcast
->operand
= xchg2
;
4165 else if (i
.broadcast
->operand
== xchg2
)
4166 i
.broadcast
->operand
= xchg1
;
4170 if (i
.rounding
->operand
== xchg1
)
4171 i
.rounding
->operand
= xchg2
;
4172 else if (i
.rounding
->operand
== xchg2
)
4173 i
.rounding
->operand
= xchg1
;
4178 swap_operands (void)
4184 swap_2_operands (1, i
.operands
- 2);
4187 swap_2_operands (0, i
.operands
- 1);
4193 if (i
.mem_operands
== 2)
4195 const seg_entry
*temp_seg
;
4196 temp_seg
= i
.seg
[0];
4197 i
.seg
[0] = i
.seg
[1];
4198 i
.seg
[1] = temp_seg
;
4202 /* Try to ensure constant immediates are represented in the smallest
4207 char guess_suffix
= 0;
4211 guess_suffix
= i
.suffix
;
4212 else if (i
.reg_operands
)
4214 /* Figure out a suffix from the last register operand specified.
4215 We can't do this properly yet, ie. excluding InOutPortReg,
4216 but the following works for instructions with immediates.
4217 In any case, we can't set i.suffix yet. */
4218 for (op
= i
.operands
; --op
>= 0;)
4219 if (i
.types
[op
].bitfield
.reg8
)
4221 guess_suffix
= BYTE_MNEM_SUFFIX
;
4224 else if (i
.types
[op
].bitfield
.reg16
)
4226 guess_suffix
= WORD_MNEM_SUFFIX
;
4229 else if (i
.types
[op
].bitfield
.reg32
)
4231 guess_suffix
= LONG_MNEM_SUFFIX
;
4234 else if (i
.types
[op
].bitfield
.reg64
)
4236 guess_suffix
= QWORD_MNEM_SUFFIX
;
4240 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4241 guess_suffix
= WORD_MNEM_SUFFIX
;
4243 for (op
= i
.operands
; --op
>= 0;)
4244 if (operand_type_check (i
.types
[op
], imm
))
4246 switch (i
.op
[op
].imms
->X_op
)
4249 /* If a suffix is given, this operand may be shortened. */
4250 switch (guess_suffix
)
4252 case LONG_MNEM_SUFFIX
:
4253 i
.types
[op
].bitfield
.imm32
= 1;
4254 i
.types
[op
].bitfield
.imm64
= 1;
4256 case WORD_MNEM_SUFFIX
:
4257 i
.types
[op
].bitfield
.imm16
= 1;
4258 i
.types
[op
].bitfield
.imm32
= 1;
4259 i
.types
[op
].bitfield
.imm32s
= 1;
4260 i
.types
[op
].bitfield
.imm64
= 1;
4262 case BYTE_MNEM_SUFFIX
:
4263 i
.types
[op
].bitfield
.imm8
= 1;
4264 i
.types
[op
].bitfield
.imm8s
= 1;
4265 i
.types
[op
].bitfield
.imm16
= 1;
4266 i
.types
[op
].bitfield
.imm32
= 1;
4267 i
.types
[op
].bitfield
.imm32s
= 1;
4268 i
.types
[op
].bitfield
.imm64
= 1;
4272 /* If this operand is at most 16 bits, convert it
4273 to a signed 16 bit number before trying to see
4274 whether it will fit in an even smaller size.
4275 This allows a 16-bit operand such as $0xffe0 to
4276 be recognised as within Imm8S range. */
4277 if ((i
.types
[op
].bitfield
.imm16
)
4278 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4280 i
.op
[op
].imms
->X_add_number
=
4281 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4284 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4285 if ((i
.types
[op
].bitfield
.imm32
)
4286 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4289 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4290 ^ ((offsetT
) 1 << 31))
4291 - ((offsetT
) 1 << 31));
4295 = operand_type_or (i
.types
[op
],
4296 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4298 /* We must avoid matching of Imm32 templates when 64bit
4299 only immediate is available. */
4300 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4301 i
.types
[op
].bitfield
.imm32
= 0;
4308 /* Symbols and expressions. */
4310 /* Convert symbolic operand to proper sizes for matching, but don't
4311 prevent matching a set of insns that only supports sizes other
4312 than those matching the insn suffix. */
4314 i386_operand_type mask
, allowed
;
4315 const insn_template
*t
;
4317 operand_type_set (&mask
, 0);
4318 operand_type_set (&allowed
, 0);
4320 for (t
= current_templates
->start
;
4321 t
< current_templates
->end
;
4323 allowed
= operand_type_or (allowed
,
4324 t
->operand_types
[op
]);
4325 switch (guess_suffix
)
4327 case QWORD_MNEM_SUFFIX
:
4328 mask
.bitfield
.imm64
= 1;
4329 mask
.bitfield
.imm32s
= 1;
4331 case LONG_MNEM_SUFFIX
:
4332 mask
.bitfield
.imm32
= 1;
4334 case WORD_MNEM_SUFFIX
:
4335 mask
.bitfield
.imm16
= 1;
4337 case BYTE_MNEM_SUFFIX
:
4338 mask
.bitfield
.imm8
= 1;
4343 allowed
= operand_type_and (mask
, allowed
);
4344 if (!operand_type_all_zero (&allowed
))
4345 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4352 /* Try to use the smallest displacement type too. */
4354 optimize_disp (void)
4358 for (op
= i
.operands
; --op
>= 0;)
4359 if (operand_type_check (i
.types
[op
], disp
))
4361 if (i
.op
[op
].disps
->X_op
== O_constant
)
4363 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4365 if (i
.types
[op
].bitfield
.disp16
4366 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4368 /* If this operand is at most 16 bits, convert
4369 to a signed 16 bit number and don't use 64bit
4371 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4372 i
.types
[op
].bitfield
.disp64
= 0;
4375 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4376 if (i
.types
[op
].bitfield
.disp32
4377 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4379 /* If this operand is at most 32 bits, convert
4380 to a signed 32 bit number and don't use 64bit
4382 op_disp
&= (((offsetT
) 2 << 31) - 1);
4383 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4384 i
.types
[op
].bitfield
.disp64
= 0;
4387 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4389 i
.types
[op
].bitfield
.disp8
= 0;
4390 i
.types
[op
].bitfield
.disp16
= 0;
4391 i
.types
[op
].bitfield
.disp32
= 0;
4392 i
.types
[op
].bitfield
.disp32s
= 0;
4393 i
.types
[op
].bitfield
.disp64
= 0;
4397 else if (flag_code
== CODE_64BIT
)
4399 if (fits_in_signed_long (op_disp
))
4401 i
.types
[op
].bitfield
.disp64
= 0;
4402 i
.types
[op
].bitfield
.disp32s
= 1;
4404 if (i
.prefix
[ADDR_PREFIX
]
4405 && fits_in_unsigned_long (op_disp
))
4406 i
.types
[op
].bitfield
.disp32
= 1;
4408 if ((i
.types
[op
].bitfield
.disp32
4409 || i
.types
[op
].bitfield
.disp32s
4410 || i
.types
[op
].bitfield
.disp16
)
4411 && fits_in_signed_byte (op_disp
))
4412 i
.types
[op
].bitfield
.disp8
= 1;
4414 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4415 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4417 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4418 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4419 i
.types
[op
].bitfield
.disp8
= 0;
4420 i
.types
[op
].bitfield
.disp16
= 0;
4421 i
.types
[op
].bitfield
.disp32
= 0;
4422 i
.types
[op
].bitfield
.disp32s
= 0;
4423 i
.types
[op
].bitfield
.disp64
= 0;
4426 /* We only support 64bit displacement on constants. */
4427 i
.types
[op
].bitfield
.disp64
= 0;
4431 /* Check if operands are valid for the instruction. */
4434 check_VecOperands (const insn_template
*t
)
4438 /* Without VSIB byte, we can't have a vector register for index. */
4439 if (!t
->opcode_modifier
.vecsib
4441 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4442 || i
.index_reg
->reg_type
.bitfield
.regymm
4443 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4445 i
.error
= unsupported_vector_index_register
;
4449 /* Check if default mask is allowed. */
4450 if (t
->opcode_modifier
.nodefmask
4451 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4453 i
.error
= no_default_mask
;
4457 /* For VSIB byte, we need a vector register for index, and all vector
4458 registers must be distinct. */
4459 if (t
->opcode_modifier
.vecsib
)
4462 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4463 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4464 || (t
->opcode_modifier
.vecsib
== VecSIB256
4465 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4466 || (t
->opcode_modifier
.vecsib
== VecSIB512
4467 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4469 i
.error
= invalid_vsib_address
;
4473 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4474 if (i
.reg_operands
== 2 && !i
.mask
)
4476 gas_assert (i
.types
[0].bitfield
.regxmm
4477 || i
.types
[0].bitfield
.regymm
);
4478 gas_assert (i
.types
[2].bitfield
.regxmm
4479 || i
.types
[2].bitfield
.regymm
);
4480 if (operand_check
== check_none
)
4482 if (register_number (i
.op
[0].regs
)
4483 != register_number (i
.index_reg
)
4484 && register_number (i
.op
[2].regs
)
4485 != register_number (i
.index_reg
)
4486 && register_number (i
.op
[0].regs
)
4487 != register_number (i
.op
[2].regs
))
4489 if (operand_check
== check_error
)
4491 i
.error
= invalid_vector_register_set
;
4494 as_warn (_("mask, index, and destination registers should be distinct"));
4496 else if (i
.reg_operands
== 1 && i
.mask
)
4498 if ((i
.types
[1].bitfield
.regymm
4499 || i
.types
[1].bitfield
.regzmm
)
4500 && (register_number (i
.op
[1].regs
)
4501 == register_number (i
.index_reg
)))
4503 if (operand_check
== check_error
)
4505 i
.error
= invalid_vector_register_set
;
4508 if (operand_check
!= check_none
)
4509 as_warn (_("index and destination registers should be distinct"));
4514 /* Check if broadcast is supported by the instruction and is applied
4515 to the memory operand. */
4518 int broadcasted_opnd_size
;
4520 /* Check if specified broadcast is supported in this instruction,
4521 and it's applied to memory operand of DWORD or QWORD type,
4522 depending on VecESize. */
4523 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4524 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4525 || (t
->opcode_modifier
.vecesize
== 0
4526 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4527 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4528 || (t
->opcode_modifier
.vecesize
== 1
4529 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4530 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4533 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4534 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4535 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4536 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4537 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4538 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4539 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4540 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4541 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4545 if ((broadcasted_opnd_size
== 256
4546 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4547 || (broadcasted_opnd_size
== 512
4548 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4551 i
.error
= unsupported_broadcast
;
4555 /* If broadcast is supported in this instruction, we need to check if
4556 operand of one-element size isn't specified without broadcast. */
4557 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4559 /* Find memory operand. */
4560 for (op
= 0; op
< i
.operands
; op
++)
4561 if (operand_type_check (i
.types
[op
], anymem
))
4563 gas_assert (op
< i
.operands
);
4564 /* Check size of the memory operand. */
4565 if ((t
->opcode_modifier
.vecesize
== 0
4566 && i
.types
[op
].bitfield
.dword
)
4567 || (t
->opcode_modifier
.vecesize
== 1
4568 && i
.types
[op
].bitfield
.qword
))
4570 i
.error
= broadcast_needed
;
4575 /* Check if requested masking is supported. */
4577 && (!t
->opcode_modifier
.masking
4579 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4581 i
.error
= unsupported_masking
;
4585 /* Check if masking is applied to dest operand. */
4586 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4588 i
.error
= mask_not_on_destination
;
4595 if ((i
.rounding
->type
!= saeonly
4596 && !t
->opcode_modifier
.staticrounding
)
4597 || (i
.rounding
->type
== saeonly
4598 && (t
->opcode_modifier
.staticrounding
4599 || !t
->opcode_modifier
.sae
)))
4601 i
.error
= unsupported_rc_sae
;
4604 /* If the instruction has several immediate operands and one of
4605 them is rounding, the rounding operand should be the last
4606 immediate operand. */
4607 if (i
.imm_operands
> 1
4608 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4610 i
.error
= rc_sae_operand_not_last_imm
;
4615 /* Check vector Disp8 operand. */
4616 if (t
->opcode_modifier
.disp8memshift
)
4619 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4621 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4623 for (op
= 0; op
< i
.operands
; op
++)
4624 if (operand_type_check (i
.types
[op
], disp
)
4625 && i
.op
[op
].disps
->X_op
== O_constant
)
4627 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4629 = (i
.disp_encoding
!= disp_encoding_32bit
4630 && fits_in_vec_disp8 (value
));
4631 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4634 i
.types
[op
].bitfield
.vec_disp8
= 1;
4637 /* Vector insn can only have Vec_Disp8/Disp32 in
4638 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4640 i
.types
[op
].bitfield
.disp8
= 0;
4641 if (flag_code
!= CODE_16BIT
)
4642 i
.types
[op
].bitfield
.disp16
= 0;
4645 else if (flag_code
!= CODE_16BIT
)
4647 /* One form of this instruction supports vector Disp8.
4648 Try vector Disp8 if we need to use Disp32. */
4649 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4651 i
.error
= try_vector_disp8
;
4663 /* Check if operands are valid for the instruction. Update VEX
4667 VEX_check_operands (const insn_template
*t
)
4669 /* VREX is only valid with EVEX prefix. */
4670 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4672 i
.error
= invalid_register_operand
;
4676 if (!t
->opcode_modifier
.vex
)
4679 /* Only check VEX_Imm4, which must be the first operand. */
4680 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4682 if (i
.op
[0].imms
->X_op
!= O_constant
4683 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4689 /* Turn off Imm8 so that update_imm won't complain. */
4690 i
.types
[0] = vec_imm4
;
4696 static const insn_template
*
4697 match_template (void)
4699 /* Points to template once we've found it. */
4700 const insn_template
*t
;
4701 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4702 i386_operand_type overlap4
;
4703 unsigned int found_reverse_match
;
4704 i386_opcode_modifier suffix_check
;
4705 i386_operand_type operand_types
[MAX_OPERANDS
];
4706 int addr_prefix_disp
;
4708 unsigned int found_cpu_match
;
4709 unsigned int check_register
;
4710 enum i386_error specific_error
= 0;
4712 #if MAX_OPERANDS != 5
4713 # error "MAX_OPERANDS must be 5."
4716 found_reverse_match
= 0;
4717 addr_prefix_disp
= -1;
4719 memset (&suffix_check
, 0, sizeof (suffix_check
));
4720 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4721 suffix_check
.no_bsuf
= 1;
4722 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4723 suffix_check
.no_wsuf
= 1;
4724 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4725 suffix_check
.no_ssuf
= 1;
4726 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4727 suffix_check
.no_lsuf
= 1;
4728 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4729 suffix_check
.no_qsuf
= 1;
4730 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4731 suffix_check
.no_ldsuf
= 1;
4733 /* Must have right number of operands. */
4734 i
.error
= number_of_operands_mismatch
;
4736 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4738 addr_prefix_disp
= -1;
4740 if (i
.operands
!= t
->operands
)
4743 /* Check processor support. */
4744 i
.error
= unsupported
;
4745 found_cpu_match
= (cpu_flags_match (t
)
4746 == CPU_FLAGS_PERFECT_MATCH
);
4747 if (!found_cpu_match
)
4750 /* Check old gcc support. */
4751 i
.error
= old_gcc_only
;
4752 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4755 /* Check AT&T mnemonic. */
4756 i
.error
= unsupported_with_intel_mnemonic
;
4757 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4760 /* Check AT&T/Intel syntax. */
4761 i
.error
= unsupported_syntax
;
4762 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4763 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4766 /* Check the suffix, except for some instructions in intel mode. */
4767 i
.error
= invalid_instruction_suffix
;
4768 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4769 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4770 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4771 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4772 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4773 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4774 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4777 if (!operand_size_match (t
))
4780 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4781 operand_types
[j
] = t
->operand_types
[j
];
4783 /* In general, don't allow 64-bit operands in 32-bit mode. */
4784 if (i
.suffix
== QWORD_MNEM_SUFFIX
4785 && flag_code
!= CODE_64BIT
4787 ? (!t
->opcode_modifier
.ignoresize
4788 && !intel_float_operand (t
->name
))
4789 : intel_float_operand (t
->name
) != 2)
4790 && ((!operand_types
[0].bitfield
.regmmx
4791 && !operand_types
[0].bitfield
.regxmm
4792 && !operand_types
[0].bitfield
.regymm
4793 && !operand_types
[0].bitfield
.regzmm
)
4794 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4795 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4796 && operand_types
[t
->operands
> 1].bitfield
.regymm
4797 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4798 && (t
->base_opcode
!= 0x0fc7
4799 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4802 /* In general, don't allow 32-bit operands on pre-386. */
4803 else if (i
.suffix
== LONG_MNEM_SUFFIX
4804 && !cpu_arch_flags
.bitfield
.cpui386
4806 ? (!t
->opcode_modifier
.ignoresize
4807 && !intel_float_operand (t
->name
))
4808 : intel_float_operand (t
->name
) != 2)
4809 && ((!operand_types
[0].bitfield
.regmmx
4810 && !operand_types
[0].bitfield
.regxmm
)
4811 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4812 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4815 /* Do not verify operands when there are none. */
4819 /* We've found a match; break out of loop. */
4823 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4824 into Disp32/Disp16/Disp32 operand. */
4825 if (i
.prefix
[ADDR_PREFIX
] != 0)
4827 /* There should be only one Disp operand. */
4831 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4833 if (operand_types
[j
].bitfield
.disp16
)
4835 addr_prefix_disp
= j
;
4836 operand_types
[j
].bitfield
.disp32
= 1;
4837 operand_types
[j
].bitfield
.disp16
= 0;
4843 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4845 if (operand_types
[j
].bitfield
.disp32
)
4847 addr_prefix_disp
= j
;
4848 operand_types
[j
].bitfield
.disp32
= 0;
4849 operand_types
[j
].bitfield
.disp16
= 1;
4855 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4857 if (operand_types
[j
].bitfield
.disp64
)
4859 addr_prefix_disp
= j
;
4860 operand_types
[j
].bitfield
.disp64
= 0;
4861 operand_types
[j
].bitfield
.disp32
= 1;
4869 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4870 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4873 /* We check register size if needed. */
4874 check_register
= t
->opcode_modifier
.checkregsize
;
4875 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4876 switch (t
->operands
)
4879 if (!operand_type_match (overlap0
, i
.types
[0]))
4883 /* xchg %eax, %eax is a special case. It is an aliase for nop
4884 only in 32bit mode and we can use opcode 0x90. In 64bit
4885 mode, we can't use 0x90 for xchg %eax, %eax since it should
4886 zero-extend %eax to %rax. */
4887 if (flag_code
== CODE_64BIT
4888 && t
->base_opcode
== 0x90
4889 && operand_type_equal (&i
.types
[0], &acc32
)
4890 && operand_type_equal (&i
.types
[1], &acc32
))
4894 /* If we swap operand in encoding, we either match
4895 the next one or reverse direction of operands. */
4896 if (t
->opcode_modifier
.s
)
4898 else if (t
->opcode_modifier
.d
)
4903 /* If we swap operand in encoding, we match the next one. */
4904 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4908 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4909 if (!operand_type_match (overlap0
, i
.types
[0])
4910 || !operand_type_match (overlap1
, i
.types
[1])
4912 && !operand_type_register_match (overlap0
, i
.types
[0],
4914 overlap1
, i
.types
[1],
4917 /* Check if other direction is valid ... */
4918 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4922 /* Try reversing direction of operands. */
4923 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4924 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4925 if (!operand_type_match (overlap0
, i
.types
[0])
4926 || !operand_type_match (overlap1
, i
.types
[1])
4928 && !operand_type_register_match (overlap0
,
4935 /* Does not match either direction. */
4938 /* found_reverse_match holds which of D or FloatDR
4940 if (t
->opcode_modifier
.d
)
4941 found_reverse_match
= Opcode_D
;
4942 else if (t
->opcode_modifier
.floatd
)
4943 found_reverse_match
= Opcode_FloatD
;
4945 found_reverse_match
= 0;
4946 if (t
->opcode_modifier
.floatr
)
4947 found_reverse_match
|= Opcode_FloatR
;
4951 /* Found a forward 2 operand match here. */
4952 switch (t
->operands
)
4955 overlap4
= operand_type_and (i
.types
[4],
4958 overlap3
= operand_type_and (i
.types
[3],
4961 overlap2
= operand_type_and (i
.types
[2],
4966 switch (t
->operands
)
4969 if (!operand_type_match (overlap4
, i
.types
[4])
4970 || !operand_type_register_match (overlap3
,
4978 if (!operand_type_match (overlap3
, i
.types
[3])
4980 && !operand_type_register_match (overlap2
,
4988 /* Here we make use of the fact that there are no
4989 reverse match 3 operand instructions, and all 3
4990 operand instructions only need to be checked for
4991 register consistency between operands 2 and 3. */
4992 if (!operand_type_match (overlap2
, i
.types
[2])
4994 && !operand_type_register_match (overlap1
,
5004 /* Found either forward/reverse 2, 3 or 4 operand match here:
5005 slip through to break. */
5007 if (!found_cpu_match
)
5009 found_reverse_match
= 0;
5013 /* Check if vector and VEX operands are valid. */
5014 if (check_VecOperands (t
) || VEX_check_operands (t
))
5016 specific_error
= i
.error
;
5020 /* We've found a match; break out of loop. */
5024 if (t
== current_templates
->end
)
5026 /* We found no match. */
5027 const char *err_msg
;
5028 switch (specific_error
? specific_error
: i
.error
)
5032 case operand_size_mismatch
:
5033 err_msg
= _("operand size mismatch");
5035 case operand_type_mismatch
:
5036 err_msg
= _("operand type mismatch");
5038 case register_type_mismatch
:
5039 err_msg
= _("register type mismatch");
5041 case number_of_operands_mismatch
:
5042 err_msg
= _("number of operands mismatch");
5044 case invalid_instruction_suffix
:
5045 err_msg
= _("invalid instruction suffix");
5048 err_msg
= _("constant doesn't fit in 4 bits");
5051 err_msg
= _("only supported with old gcc");
5053 case unsupported_with_intel_mnemonic
:
5054 err_msg
= _("unsupported with Intel mnemonic");
5056 case unsupported_syntax
:
5057 err_msg
= _("unsupported syntax");
5060 as_bad (_("unsupported instruction `%s'"),
5061 current_templates
->start
->name
);
5063 case invalid_vsib_address
:
5064 err_msg
= _("invalid VSIB address");
5066 case invalid_vector_register_set
:
5067 err_msg
= _("mask, index, and destination registers must be distinct");
5069 case unsupported_vector_index_register
:
5070 err_msg
= _("unsupported vector index register");
5072 case unsupported_broadcast
:
5073 err_msg
= _("unsupported broadcast");
5075 case broadcast_not_on_src_operand
:
5076 err_msg
= _("broadcast not on source memory operand");
5078 case broadcast_needed
:
5079 err_msg
= _("broadcast is needed for operand of such type");
5081 case unsupported_masking
:
5082 err_msg
= _("unsupported masking");
5084 case mask_not_on_destination
:
5085 err_msg
= _("mask not on destination operand");
5087 case no_default_mask
:
5088 err_msg
= _("default mask isn't allowed");
5090 case unsupported_rc_sae
:
5091 err_msg
= _("unsupported static rounding/sae");
5093 case rc_sae_operand_not_last_imm
:
5095 err_msg
= _("RC/SAE operand must precede immediate operands");
5097 err_msg
= _("RC/SAE operand must follow immediate operands");
5099 case invalid_register_operand
:
5100 err_msg
= _("invalid register operand");
5103 as_bad (_("%s for `%s'"), err_msg
,
5104 current_templates
->start
->name
);
5108 if (!quiet_warnings
)
5111 && (i
.types
[0].bitfield
.jumpabsolute
5112 != operand_types
[0].bitfield
.jumpabsolute
))
5114 as_warn (_("indirect %s without `*'"), t
->name
);
5117 if (t
->opcode_modifier
.isprefix
5118 && t
->opcode_modifier
.ignoresize
)
5120 /* Warn them that a data or address size prefix doesn't
5121 affect assembly of the next line of code. */
5122 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5126 /* Copy the template we found. */
5129 if (addr_prefix_disp
!= -1)
5130 i
.tm
.operand_types
[addr_prefix_disp
]
5131 = operand_types
[addr_prefix_disp
];
5133 if (found_reverse_match
)
5135 /* If we found a reverse match we must alter the opcode
5136 direction bit. found_reverse_match holds bits to change
5137 (different for int & float insns). */
5139 i
.tm
.base_opcode
^= found_reverse_match
;
5141 i
.tm
.operand_types
[0] = operand_types
[1];
5142 i
.tm
.operand_types
[1] = operand_types
[0];
5151 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5152 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5154 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5156 as_bad (_("`%s' operand %d must use `%ses' segment"),
5162 /* There's only ever one segment override allowed per instruction.
5163 This instruction possibly has a legal segment override on the
5164 second operand, so copy the segment to where non-string
5165 instructions store it, allowing common code. */
5166 i
.seg
[0] = i
.seg
[1];
5168 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5170 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5172 as_bad (_("`%s' operand %d must use `%ses' segment"),
5183 process_suffix (void)
5185 /* If matched instruction specifies an explicit instruction mnemonic
5187 if (i
.tm
.opcode_modifier
.size16
)
5188 i
.suffix
= WORD_MNEM_SUFFIX
;
5189 else if (i
.tm
.opcode_modifier
.size32
)
5190 i
.suffix
= LONG_MNEM_SUFFIX
;
5191 else if (i
.tm
.opcode_modifier
.size64
)
5192 i
.suffix
= QWORD_MNEM_SUFFIX
;
5193 else if (i
.reg_operands
)
5195 /* If there's no instruction mnemonic suffix we try to invent one
5196 based on register operands. */
5199 /* We take i.suffix from the last register operand specified,
5200 Destination register type is more significant than source
5201 register type. crc32 in SSE4.2 prefers source register
5203 if (i
.tm
.base_opcode
== 0xf20f38f1)
5205 if (i
.types
[0].bitfield
.reg16
)
5206 i
.suffix
= WORD_MNEM_SUFFIX
;
5207 else if (i
.types
[0].bitfield
.reg32
)
5208 i
.suffix
= LONG_MNEM_SUFFIX
;
5209 else if (i
.types
[0].bitfield
.reg64
)
5210 i
.suffix
= QWORD_MNEM_SUFFIX
;
5212 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5214 if (i
.types
[0].bitfield
.reg8
)
5215 i
.suffix
= BYTE_MNEM_SUFFIX
;
5222 if (i
.tm
.base_opcode
== 0xf20f38f1
5223 || i
.tm
.base_opcode
== 0xf20f38f0)
5225 /* We have to know the operand size for crc32. */
5226 as_bad (_("ambiguous memory operand size for `%s`"),
5231 for (op
= i
.operands
; --op
>= 0;)
5232 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5234 if (i
.types
[op
].bitfield
.reg8
)
5236 i
.suffix
= BYTE_MNEM_SUFFIX
;
5239 else if (i
.types
[op
].bitfield
.reg16
)
5241 i
.suffix
= WORD_MNEM_SUFFIX
;
5244 else if (i
.types
[op
].bitfield
.reg32
)
5246 i
.suffix
= LONG_MNEM_SUFFIX
;
5249 else if (i
.types
[op
].bitfield
.reg64
)
5251 i
.suffix
= QWORD_MNEM_SUFFIX
;
5257 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5260 && i
.tm
.opcode_modifier
.ignoresize
5261 && i
.tm
.opcode_modifier
.no_bsuf
)
5263 else if (!check_byte_reg ())
5266 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5269 && i
.tm
.opcode_modifier
.ignoresize
5270 && i
.tm
.opcode_modifier
.no_lsuf
)
5272 else if (!check_long_reg ())
5275 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5278 && i
.tm
.opcode_modifier
.ignoresize
5279 && i
.tm
.opcode_modifier
.no_qsuf
)
5281 else if (!check_qword_reg ())
5284 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5287 && i
.tm
.opcode_modifier
.ignoresize
5288 && i
.tm
.opcode_modifier
.no_wsuf
)
5290 else if (!check_word_reg ())
5293 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5294 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5295 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5297 /* Skip if the instruction has x/y/z suffix. match_template
5298 should check if it is a valid suffix. */
5300 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5301 /* Do nothing if the instruction is going to ignore the prefix. */
5306 else if (i
.tm
.opcode_modifier
.defaultsize
5308 /* exclude fldenv/frstor/fsave/fstenv */
5309 && i
.tm
.opcode_modifier
.no_ssuf
)
5311 i
.suffix
= stackop_size
;
5313 else if (intel_syntax
5315 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5316 || i
.tm
.opcode_modifier
.jumpbyte
5317 || i
.tm
.opcode_modifier
.jumpintersegment
5318 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5319 && i
.tm
.extension_opcode
<= 3)))
5324 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5326 i
.suffix
= QWORD_MNEM_SUFFIX
;
5330 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5331 i
.suffix
= LONG_MNEM_SUFFIX
;
5334 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5335 i
.suffix
= WORD_MNEM_SUFFIX
;
5344 if (i
.tm
.opcode_modifier
.w
)
5346 as_bad (_("no instruction mnemonic suffix given and "
5347 "no register operands; can't size instruction"));
5353 unsigned int suffixes
;
5355 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5356 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5358 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5360 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5362 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5364 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5367 /* There are more than suffix matches. */
5368 if (i
.tm
.opcode_modifier
.w
5369 || ((suffixes
& (suffixes
- 1))
5370 && !i
.tm
.opcode_modifier
.defaultsize
5371 && !i
.tm
.opcode_modifier
.ignoresize
))
5373 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5379 /* Change the opcode based on the operand size given by i.suffix;
5380 We don't need to change things for byte insns. */
5383 && i
.suffix
!= BYTE_MNEM_SUFFIX
5384 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5385 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5386 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5388 /* It's not a byte, select word/dword operation. */
5389 if (i
.tm
.opcode_modifier
.w
)
5391 if (i
.tm
.opcode_modifier
.shortform
)
5392 i
.tm
.base_opcode
|= 8;
5394 i
.tm
.base_opcode
|= 1;
5397 /* Now select between word & dword operations via the operand
5398 size prefix, except for instructions that will ignore this
5400 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5402 /* The address size override prefix changes the size of the
5404 if ((flag_code
== CODE_32BIT
5405 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5406 || (flag_code
!= CODE_32BIT
5407 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5408 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5411 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5412 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5413 && !i
.tm
.opcode_modifier
.ignoresize
5414 && !i
.tm
.opcode_modifier
.floatmf
5415 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5416 || (flag_code
== CODE_64BIT
5417 && i
.tm
.opcode_modifier
.jumpbyte
)))
5419 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5421 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5422 prefix
= ADDR_PREFIX_OPCODE
;
5424 if (!add_prefix (prefix
))
5428 /* Set mode64 for an operand. */
5429 if (i
.suffix
== QWORD_MNEM_SUFFIX
5430 && flag_code
== CODE_64BIT
5431 && !i
.tm
.opcode_modifier
.norex64
)
5433 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5434 need rex64. cmpxchg8b is also a special case. */
5435 if (! (i
.operands
== 2
5436 && i
.tm
.base_opcode
== 0x90
5437 && i
.tm
.extension_opcode
== None
5438 && operand_type_equal (&i
.types
[0], &acc64
)
5439 && operand_type_equal (&i
.types
[1], &acc64
))
5440 && ! (i
.operands
== 1
5441 && i
.tm
.base_opcode
== 0xfc7
5442 && i
.tm
.extension_opcode
== 1
5443 && !operand_type_check (i
.types
[0], reg
)
5444 && operand_type_check (i
.types
[0], anymem
)))
5448 /* Size floating point instruction. */
5449 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5450 if (i
.tm
.opcode_modifier
.floatmf
)
5451 i
.tm
.base_opcode
^= 4;
5458 check_byte_reg (void)
5462 for (op
= i
.operands
; --op
>= 0;)
5464 /* If this is an eight bit register, it's OK. If it's the 16 or
5465 32 bit version of an eight bit register, we will just use the
5466 low portion, and that's OK too. */
5467 if (i
.types
[op
].bitfield
.reg8
)
5470 /* I/O port address operands are OK too. */
5471 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5474 /* crc32 doesn't generate this warning. */
5475 if (i
.tm
.base_opcode
== 0xf20f38f0)
5478 if ((i
.types
[op
].bitfield
.reg16
5479 || i
.types
[op
].bitfield
.reg32
5480 || i
.types
[op
].bitfield
.reg64
)
5481 && i
.op
[op
].regs
->reg_num
< 4
5482 /* Prohibit these changes in 64bit mode, since the lowering
5483 would be more complicated. */
5484 && flag_code
!= CODE_64BIT
)
5486 #if REGISTER_WARNINGS
5487 if (!quiet_warnings
)
5488 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5490 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5491 ? REGNAM_AL
- REGNAM_AX
5492 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5494 i
.op
[op
].regs
->reg_name
,
5499 /* Any other register is bad. */
5500 if (i
.types
[op
].bitfield
.reg16
5501 || i
.types
[op
].bitfield
.reg32
5502 || i
.types
[op
].bitfield
.reg64
5503 || i
.types
[op
].bitfield
.regmmx
5504 || i
.types
[op
].bitfield
.regxmm
5505 || i
.types
[op
].bitfield
.regymm
5506 || i
.types
[op
].bitfield
.regzmm
5507 || i
.types
[op
].bitfield
.sreg2
5508 || i
.types
[op
].bitfield
.sreg3
5509 || i
.types
[op
].bitfield
.control
5510 || i
.types
[op
].bitfield
.debug
5511 || i
.types
[op
].bitfield
.test
5512 || i
.types
[op
].bitfield
.floatreg
5513 || i
.types
[op
].bitfield
.floatacc
)
5515 as_bad (_("`%s%s' not allowed with `%s%c'"),
5517 i
.op
[op
].regs
->reg_name
,
5527 check_long_reg (void)
5531 for (op
= i
.operands
; --op
>= 0;)
5532 /* Reject eight bit registers, except where the template requires
5533 them. (eg. movzb) */
5534 if (i
.types
[op
].bitfield
.reg8
5535 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5536 || i
.tm
.operand_types
[op
].bitfield
.reg32
5537 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5539 as_bad (_("`%s%s' not allowed with `%s%c'"),
5541 i
.op
[op
].regs
->reg_name
,
5546 /* Warn if the e prefix on a general reg is missing. */
5547 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5548 && i
.types
[op
].bitfield
.reg16
5549 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5550 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5552 /* Prohibit these changes in the 64bit mode, since the
5553 lowering is more complicated. */
5554 if (flag_code
== CODE_64BIT
)
5556 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5557 register_prefix
, i
.op
[op
].regs
->reg_name
,
5561 #if REGISTER_WARNINGS
5562 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5564 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5565 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5568 /* Warn if the r prefix on a general reg is present. */
5569 else if (i
.types
[op
].bitfield
.reg64
5570 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5571 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5574 && i
.tm
.opcode_modifier
.toqword
5575 && !i
.types
[0].bitfield
.regxmm
)
5577 /* Convert to QWORD. We want REX byte. */
5578 i
.suffix
= QWORD_MNEM_SUFFIX
;
5582 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5583 register_prefix
, i
.op
[op
].regs
->reg_name
,
5592 check_qword_reg (void)
5596 for (op
= i
.operands
; --op
>= 0; )
5597 /* Reject eight bit registers, except where the template requires
5598 them. (eg. movzb) */
5599 if (i
.types
[op
].bitfield
.reg8
5600 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5601 || i
.tm
.operand_types
[op
].bitfield
.reg32
5602 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5604 as_bad (_("`%s%s' not allowed with `%s%c'"),
5606 i
.op
[op
].regs
->reg_name
,
5611 /* Warn if the r prefix on a general reg is missing. */
5612 else if ((i
.types
[op
].bitfield
.reg16
5613 || i
.types
[op
].bitfield
.reg32
)
5614 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5615 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5617 /* Prohibit these changes in the 64bit mode, since the
5618 lowering is more complicated. */
5620 && i
.tm
.opcode_modifier
.todword
5621 && !i
.types
[0].bitfield
.regxmm
)
5623 /* Convert to DWORD. We don't want REX byte. */
5624 i
.suffix
= LONG_MNEM_SUFFIX
;
5628 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5629 register_prefix
, i
.op
[op
].regs
->reg_name
,
5638 check_word_reg (void)
5641 for (op
= i
.operands
; --op
>= 0;)
5642 /* Reject eight bit registers, except where the template requires
5643 them. (eg. movzb) */
5644 if (i
.types
[op
].bitfield
.reg8
5645 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5646 || i
.tm
.operand_types
[op
].bitfield
.reg32
5647 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5649 as_bad (_("`%s%s' not allowed with `%s%c'"),
5651 i
.op
[op
].regs
->reg_name
,
5656 /* Warn if the e or r prefix on a general reg is present. */
5657 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5658 && (i
.types
[op
].bitfield
.reg32
5659 || i
.types
[op
].bitfield
.reg64
)
5660 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5661 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5663 /* Prohibit these changes in the 64bit mode, since the
5664 lowering is more complicated. */
5665 if (flag_code
== CODE_64BIT
)
5667 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5668 register_prefix
, i
.op
[op
].regs
->reg_name
,
5672 #if REGISTER_WARNINGS
5673 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5675 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5676 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5683 update_imm (unsigned int j
)
5685 i386_operand_type overlap
= i
.types
[j
];
5686 if ((overlap
.bitfield
.imm8
5687 || overlap
.bitfield
.imm8s
5688 || overlap
.bitfield
.imm16
5689 || overlap
.bitfield
.imm32
5690 || overlap
.bitfield
.imm32s
5691 || overlap
.bitfield
.imm64
)
5692 && !operand_type_equal (&overlap
, &imm8
)
5693 && !operand_type_equal (&overlap
, &imm8s
)
5694 && !operand_type_equal (&overlap
, &imm16
)
5695 && !operand_type_equal (&overlap
, &imm32
)
5696 && !operand_type_equal (&overlap
, &imm32s
)
5697 && !operand_type_equal (&overlap
, &imm64
))
5701 i386_operand_type temp
;
5703 operand_type_set (&temp
, 0);
5704 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5706 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5707 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5709 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5710 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5711 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5713 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5714 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5717 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5720 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5721 || operand_type_equal (&overlap
, &imm16_32
)
5722 || operand_type_equal (&overlap
, &imm16_32s
))
5724 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5729 if (!operand_type_equal (&overlap
, &imm8
)
5730 && !operand_type_equal (&overlap
, &imm8s
)
5731 && !operand_type_equal (&overlap
, &imm16
)
5732 && !operand_type_equal (&overlap
, &imm32
)
5733 && !operand_type_equal (&overlap
, &imm32s
)
5734 && !operand_type_equal (&overlap
, &imm64
))
5736 as_bad (_("no instruction mnemonic suffix given; "
5737 "can't determine immediate size"));
5741 i
.types
[j
] = overlap
;
5751 /* Update the first 2 immediate operands. */
5752 n
= i
.operands
> 2 ? 2 : i
.operands
;
5755 for (j
= 0; j
< n
; j
++)
5756 if (update_imm (j
) == 0)
5759 /* The 3rd operand can't be immediate operand. */
5760 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5767 bad_implicit_operand (int xmm
)
5769 const char *ireg
= xmm
? "xmm0" : "ymm0";
5772 as_bad (_("the last operand of `%s' must be `%s%s'"),
5773 i
.tm
.name
, register_prefix
, ireg
);
5775 as_bad (_("the first operand of `%s' must be `%s%s'"),
5776 i
.tm
.name
, register_prefix
, ireg
);
5781 process_operands (void)
5783 /* Default segment register this instruction will use for memory
5784 accesses. 0 means unknown. This is only for optimizing out
5785 unnecessary segment overrides. */
5786 const seg_entry
*default_seg
= 0;
5788 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5790 unsigned int dupl
= i
.operands
;
5791 unsigned int dest
= dupl
- 1;
5794 /* The destination must be an xmm register. */
5795 gas_assert (i
.reg_operands
5796 && MAX_OPERANDS
> dupl
5797 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5799 if (i
.tm
.opcode_modifier
.firstxmm0
)
5801 /* The first operand is implicit and must be xmm0. */
5802 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5803 if (register_number (i
.op
[0].regs
) != 0)
5804 return bad_implicit_operand (1);
5806 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5808 /* Keep xmm0 for instructions with VEX prefix and 3
5814 /* We remove the first xmm0 and keep the number of
5815 operands unchanged, which in fact duplicates the
5817 for (j
= 1; j
< i
.operands
; j
++)
5819 i
.op
[j
- 1] = i
.op
[j
];
5820 i
.types
[j
- 1] = i
.types
[j
];
5821 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5825 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5827 gas_assert ((MAX_OPERANDS
- 1) > dupl
5828 && (i
.tm
.opcode_modifier
.vexsources
5831 /* Add the implicit xmm0 for instructions with VEX prefix
5833 for (j
= i
.operands
; j
> 0; j
--)
5835 i
.op
[j
] = i
.op
[j
- 1];
5836 i
.types
[j
] = i
.types
[j
- 1];
5837 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5840 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5841 i
.types
[0] = regxmm
;
5842 i
.tm
.operand_types
[0] = regxmm
;
5845 i
.reg_operands
+= 2;
5850 i
.op
[dupl
] = i
.op
[dest
];
5851 i
.types
[dupl
] = i
.types
[dest
];
5852 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5861 i
.op
[dupl
] = i
.op
[dest
];
5862 i
.types
[dupl
] = i
.types
[dest
];
5863 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5866 if (i
.tm
.opcode_modifier
.immext
)
5869 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5873 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5874 gas_assert (i
.reg_operands
5875 && (operand_type_equal (&i
.types
[0], ®xmm
)
5876 || operand_type_equal (&i
.types
[0], ®ymm
)
5877 || operand_type_equal (&i
.types
[0], ®zmm
)));
5878 if (register_number (i
.op
[0].regs
) != 0)
5879 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5881 for (j
= 1; j
< i
.operands
; j
++)
5883 i
.op
[j
- 1] = i
.op
[j
];
5884 i
.types
[j
- 1] = i
.types
[j
];
5886 /* We need to adjust fields in i.tm since they are used by
5887 build_modrm_byte. */
5888 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5895 else if (i
.tm
.opcode_modifier
.regkludge
)
5897 /* The imul $imm, %reg instruction is converted into
5898 imul $imm, %reg, %reg, and the clr %reg instruction
5899 is converted into xor %reg, %reg. */
5901 unsigned int first_reg_op
;
5903 if (operand_type_check (i
.types
[0], reg
))
5907 /* Pretend we saw the extra register operand. */
5908 gas_assert (i
.reg_operands
== 1
5909 && i
.op
[first_reg_op
+ 1].regs
== 0);
5910 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5911 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5916 if (i
.tm
.opcode_modifier
.shortform
)
5918 if (i
.types
[0].bitfield
.sreg2
5919 || i
.types
[0].bitfield
.sreg3
)
5921 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5922 && i
.op
[0].regs
->reg_num
== 1)
5924 as_bad (_("you can't `pop %scs'"), register_prefix
);
5927 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5928 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5933 /* The register or float register operand is in operand
5937 if (i
.types
[0].bitfield
.floatreg
5938 || operand_type_check (i
.types
[0], reg
))
5942 /* Register goes in low 3 bits of opcode. */
5943 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5944 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5946 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5948 /* Warn about some common errors, but press on regardless.
5949 The first case can be generated by gcc (<= 2.8.1). */
5950 if (i
.operands
== 2)
5952 /* Reversed arguments on faddp, fsubp, etc. */
5953 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5954 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5955 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5959 /* Extraneous `l' suffix on fp insn. */
5960 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5961 register_prefix
, i
.op
[0].regs
->reg_name
);
5966 else if (i
.tm
.opcode_modifier
.modrm
)
5968 /* The opcode is completed (modulo i.tm.extension_opcode which
5969 must be put into the modrm byte). Now, we make the modrm and
5970 index base bytes based on all the info we've collected. */
5972 default_seg
= build_modrm_byte ();
5974 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5978 else if (i
.tm
.opcode_modifier
.isstring
)
5980 /* For the string instructions that allow a segment override
5981 on one of their operands, the default segment is ds. */
5985 if (i
.tm
.base_opcode
== 0x8d /* lea */
5988 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5990 /* If a segment was explicitly specified, and the specified segment
5991 is not the default, use an opcode prefix to select it. If we
5992 never figured out what the default segment is, then default_seg
5993 will be zero at this point, and the specified segment prefix will
5995 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5997 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6003 static const seg_entry
*
6004 build_modrm_byte (void)
6006 const seg_entry
*default_seg
= 0;
6007 unsigned int source
, dest
;
6010 /* The first operand of instructions with VEX prefix and 3 sources
6011 must be VEX_Imm4. */
6012 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6015 unsigned int nds
, reg_slot
;
6018 if (i
.tm
.opcode_modifier
.veximmext
6019 && i
.tm
.opcode_modifier
.immext
)
6021 dest
= i
.operands
- 2;
6022 gas_assert (dest
== 3);
6025 dest
= i
.operands
- 1;
6028 /* There are 2 kinds of instructions:
6029 1. 5 operands: 4 register operands or 3 register operands
6030 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6031 VexW0 or VexW1. The destination must be either XMM, YMM or
6033 2. 4 operands: 4 register operands or 3 register operands
6034 plus 1 memory operand, VexXDS, and VexImmExt */
6035 gas_assert ((i
.reg_operands
== 4
6036 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6037 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6038 && (i
.tm
.opcode_modifier
.veximmext
6039 || (i
.imm_operands
== 1
6040 && i
.types
[0].bitfield
.vec_imm4
6041 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6042 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6043 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6044 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6045 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6047 if (i
.imm_operands
== 0)
6049 /* When there is no immediate operand, generate an 8bit
6050 immediate operand to encode the first operand. */
6051 exp
= &im_expressions
[i
.imm_operands
++];
6052 i
.op
[i
.operands
].imms
= exp
;
6053 i
.types
[i
.operands
] = imm8
;
6055 /* If VexW1 is set, the first operand is the source and
6056 the second operand is encoded in the immediate operand. */
6057 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6068 /* FMA swaps REG and NDS. */
6069 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6077 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6079 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6081 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6083 exp
->X_op
= O_constant
;
6084 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6085 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6089 unsigned int imm_slot
;
6091 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6093 /* If VexW0 is set, the third operand is the source and
6094 the second operand is encoded in the immediate
6101 /* VexW1 is set, the second operand is the source and
6102 the third operand is encoded in the immediate
6108 if (i
.tm
.opcode_modifier
.immext
)
6110 /* When ImmExt is set, the immdiate byte is the last
6112 imm_slot
= i
.operands
- 1;
6120 /* Turn on Imm8 so that output_imm will generate it. */
6121 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6124 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6126 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6128 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6130 i
.op
[imm_slot
].imms
->X_add_number
6131 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6132 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6135 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6136 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6138 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6140 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6145 /* i.reg_operands MUST be the number of real register operands;
6146 implicit registers do not count. If there are 3 register
6147 operands, it must be a instruction with VexNDS. For a
6148 instruction with VexNDD, the destination register is encoded
6149 in VEX prefix. If there are 4 register operands, it must be
6150 a instruction with VEX prefix and 3 sources. */
6151 if (i
.mem_operands
== 0
6152 && ((i
.reg_operands
== 2
6153 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6154 || (i
.reg_operands
== 3
6155 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6156 || (i
.reg_operands
== 4 && vex_3_sources
)))
6164 /* When there are 3 operands, one of them may be immediate,
6165 which may be the first or the last operand. Otherwise,
6166 the first operand must be shift count register (cl) or it
6167 is an instruction with VexNDS. */
6168 gas_assert (i
.imm_operands
== 1
6169 || (i
.imm_operands
== 0
6170 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6171 || i
.types
[0].bitfield
.shiftcount
)));
6172 if (operand_type_check (i
.types
[0], imm
)
6173 || i
.types
[0].bitfield
.shiftcount
)
6179 /* When there are 4 operands, the first two must be 8bit
6180 immediate operands. The source operand will be the 3rd
6183 For instructions with VexNDS, if the first operand
6184 an imm8, the source operand is the 2nd one. If the last
6185 operand is imm8, the source operand is the first one. */
6186 gas_assert ((i
.imm_operands
== 2
6187 && i
.types
[0].bitfield
.imm8
6188 && i
.types
[1].bitfield
.imm8
)
6189 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6190 && i
.imm_operands
== 1
6191 && (i
.types
[0].bitfield
.imm8
6192 || i
.types
[i
.operands
- 1].bitfield
.imm8
6194 if (i
.imm_operands
== 2)
6198 if (i
.types
[0].bitfield
.imm8
)
6205 if (i
.tm
.opcode_modifier
.evex
)
6207 /* For EVEX instructions, when there are 5 operands, the
6208 first one must be immediate operand. If the second one
6209 is immediate operand, the source operand is the 3th
6210 one. If the last one is immediate operand, the source
6211 operand is the 2nd one. */
6212 gas_assert (i
.imm_operands
== 2
6213 && i
.tm
.opcode_modifier
.sae
6214 && operand_type_check (i
.types
[0], imm
));
6215 if (operand_type_check (i
.types
[1], imm
))
6217 else if (operand_type_check (i
.types
[4], imm
))
6231 /* RC/SAE operand could be between DEST and SRC. That happens
6232 when one operand is GPR and the other one is XMM/YMM/ZMM
6234 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6237 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6239 /* For instructions with VexNDS, the register-only source
6240 operand must be 32/64bit integer, XMM, YMM or ZMM
6241 register. It is encoded in VEX prefix. We need to
6242 clear RegMem bit before calling operand_type_equal. */
6244 i386_operand_type op
;
6247 /* Check register-only source operand when two source
6248 operands are swapped. */
6249 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6250 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6258 op
= i
.tm
.operand_types
[vvvv
];
6259 op
.bitfield
.regmem
= 0;
6260 if ((dest
+ 1) >= i
.operands
6261 || (!op
.bitfield
.reg32
6262 && op
.bitfield
.reg64
6263 && !operand_type_equal (&op
, ®xmm
)
6264 && !operand_type_equal (&op
, ®ymm
)
6265 && !operand_type_equal (&op
, ®zmm
)
6266 && !operand_type_equal (&op
, ®mask
)))
6268 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6274 /* One of the register operands will be encoded in the i.tm.reg
6275 field, the other in the combined i.tm.mode and i.tm.regmem
6276 fields. If no form of this instruction supports a memory
6277 destination operand, then we assume the source operand may
6278 sometimes be a memory operand and so we need to store the
6279 destination in the i.rm.reg field. */
6280 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6281 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6283 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6284 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6285 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6287 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6289 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6291 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6296 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6297 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6298 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6300 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6302 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6304 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6307 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6309 if (!i
.types
[0].bitfield
.control
6310 && !i
.types
[1].bitfield
.control
)
6312 i
.rex
&= ~(REX_R
| REX_B
);
6313 add_prefix (LOCK_PREFIX_OPCODE
);
6317 { /* If it's not 2 reg operands... */
6322 unsigned int fake_zero_displacement
= 0;
6325 for (op
= 0; op
< i
.operands
; op
++)
6326 if (operand_type_check (i
.types
[op
], anymem
))
6328 gas_assert (op
< i
.operands
);
6330 if (i
.tm
.opcode_modifier
.vecsib
)
6332 if (i
.index_reg
->reg_num
== RegEiz
6333 || i
.index_reg
->reg_num
== RegRiz
)
6336 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6339 i
.sib
.base
= NO_BASE_REGISTER
;
6340 i
.sib
.scale
= i
.log2_scale_factor
;
6341 /* No Vec_Disp8 if there is no base. */
6342 i
.types
[op
].bitfield
.vec_disp8
= 0;
6343 i
.types
[op
].bitfield
.disp8
= 0;
6344 i
.types
[op
].bitfield
.disp16
= 0;
6345 i
.types
[op
].bitfield
.disp64
= 0;
6346 if (flag_code
!= CODE_64BIT
)
6348 /* Must be 32 bit */
6349 i
.types
[op
].bitfield
.disp32
= 1;
6350 i
.types
[op
].bitfield
.disp32s
= 0;
6354 i
.types
[op
].bitfield
.disp32
= 0;
6355 i
.types
[op
].bitfield
.disp32s
= 1;
6358 i
.sib
.index
= i
.index_reg
->reg_num
;
6359 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6361 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6367 if (i
.base_reg
== 0)
6370 if (!i
.disp_operands
)
6372 fake_zero_displacement
= 1;
6373 /* Instructions with VSIB byte need 32bit displacement
6374 if there is no base register. */
6375 if (i
.tm
.opcode_modifier
.vecsib
)
6376 i
.types
[op
].bitfield
.disp32
= 1;
6378 if (i
.index_reg
== 0)
6380 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6381 /* Operand is just <disp> */
6382 if (flag_code
== CODE_64BIT
)
6384 /* 64bit mode overwrites the 32bit absolute
6385 addressing by RIP relative addressing and
6386 absolute addressing is encoded by one of the
6387 redundant SIB forms. */
6388 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6389 i
.sib
.base
= NO_BASE_REGISTER
;
6390 i
.sib
.index
= NO_INDEX_REGISTER
;
6391 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6392 ? disp32s
: disp32
);
6394 else if ((flag_code
== CODE_16BIT
)
6395 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6397 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6398 i
.types
[op
] = disp16
;
6402 i
.rm
.regmem
= NO_BASE_REGISTER
;
6403 i
.types
[op
] = disp32
;
6406 else if (!i
.tm
.opcode_modifier
.vecsib
)
6408 /* !i.base_reg && i.index_reg */
6409 if (i
.index_reg
->reg_num
== RegEiz
6410 || i
.index_reg
->reg_num
== RegRiz
)
6411 i
.sib
.index
= NO_INDEX_REGISTER
;
6413 i
.sib
.index
= i
.index_reg
->reg_num
;
6414 i
.sib
.base
= NO_BASE_REGISTER
;
6415 i
.sib
.scale
= i
.log2_scale_factor
;
6416 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6417 /* No Vec_Disp8 if there is no base. */
6418 i
.types
[op
].bitfield
.vec_disp8
= 0;
6419 i
.types
[op
].bitfield
.disp8
= 0;
6420 i
.types
[op
].bitfield
.disp16
= 0;
6421 i
.types
[op
].bitfield
.disp64
= 0;
6422 if (flag_code
!= CODE_64BIT
)
6424 /* Must be 32 bit */
6425 i
.types
[op
].bitfield
.disp32
= 1;
6426 i
.types
[op
].bitfield
.disp32s
= 0;
6430 i
.types
[op
].bitfield
.disp32
= 0;
6431 i
.types
[op
].bitfield
.disp32s
= 1;
6433 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6437 /* RIP addressing for 64bit mode. */
6438 else if (i
.base_reg
->reg_num
== RegRip
||
6439 i
.base_reg
->reg_num
== RegEip
)
6441 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6442 i
.rm
.regmem
= NO_BASE_REGISTER
;
6443 i
.types
[op
].bitfield
.disp8
= 0;
6444 i
.types
[op
].bitfield
.disp16
= 0;
6445 i
.types
[op
].bitfield
.disp32
= 0;
6446 i
.types
[op
].bitfield
.disp32s
= 1;
6447 i
.types
[op
].bitfield
.disp64
= 0;
6448 i
.types
[op
].bitfield
.vec_disp8
= 0;
6449 i
.flags
[op
] |= Operand_PCrel
;
6450 if (! i
.disp_operands
)
6451 fake_zero_displacement
= 1;
6453 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6455 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6456 switch (i
.base_reg
->reg_num
)
6459 if (i
.index_reg
== 0)
6461 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6462 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6466 if (i
.index_reg
== 0)
6469 if (operand_type_check (i
.types
[op
], disp
) == 0)
6471 /* fake (%bp) into 0(%bp) */
6472 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6473 i
.types
[op
].bitfield
.vec_disp8
= 1;
6475 i
.types
[op
].bitfield
.disp8
= 1;
6476 fake_zero_displacement
= 1;
6479 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6480 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6482 default: /* (%si) -> 4 or (%di) -> 5 */
6483 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6485 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6487 else /* i.base_reg and 32/64 bit mode */
6489 if (flag_code
== CODE_64BIT
6490 && operand_type_check (i
.types
[op
], disp
))
6492 i386_operand_type temp
;
6493 operand_type_set (&temp
, 0);
6494 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6495 temp
.bitfield
.vec_disp8
6496 = i
.types
[op
].bitfield
.vec_disp8
;
6498 if (i
.prefix
[ADDR_PREFIX
] == 0)
6499 i
.types
[op
].bitfield
.disp32s
= 1;
6501 i
.types
[op
].bitfield
.disp32
= 1;
6504 if (!i
.tm
.opcode_modifier
.vecsib
)
6505 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6506 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6508 i
.sib
.base
= i
.base_reg
->reg_num
;
6509 /* x86-64 ignores REX prefix bit here to avoid decoder
6511 if (!(i
.base_reg
->reg_flags
& RegRex
)
6512 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6513 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6515 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6517 fake_zero_displacement
= 1;
6518 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6519 i
.types
[op
].bitfield
.vec_disp8
= 1;
6521 i
.types
[op
].bitfield
.disp8
= 1;
6523 i
.sib
.scale
= i
.log2_scale_factor
;
6524 if (i
.index_reg
== 0)
6526 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6527 /* <disp>(%esp) becomes two byte modrm with no index
6528 register. We've already stored the code for esp
6529 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6530 Any base register besides %esp will not use the
6531 extra modrm byte. */
6532 i
.sib
.index
= NO_INDEX_REGISTER
;
6534 else if (!i
.tm
.opcode_modifier
.vecsib
)
6536 if (i
.index_reg
->reg_num
== RegEiz
6537 || i
.index_reg
->reg_num
== RegRiz
)
6538 i
.sib
.index
= NO_INDEX_REGISTER
;
6540 i
.sib
.index
= i
.index_reg
->reg_num
;
6541 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6542 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6547 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6548 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6552 if (!fake_zero_displacement
6556 fake_zero_displacement
= 1;
6557 if (i
.disp_encoding
== disp_encoding_8bit
)
6558 i
.types
[op
].bitfield
.disp8
= 1;
6560 i
.types
[op
].bitfield
.disp32
= 1;
6562 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6566 if (fake_zero_displacement
)
6568 /* Fakes a zero displacement assuming that i.types[op]
6569 holds the correct displacement size. */
6572 gas_assert (i
.op
[op
].disps
== 0);
6573 exp
= &disp_expressions
[i
.disp_operands
++];
6574 i
.op
[op
].disps
= exp
;
6575 exp
->X_op
= O_constant
;
6576 exp
->X_add_number
= 0;
6577 exp
->X_add_symbol
= (symbolS
*) 0;
6578 exp
->X_op_symbol
= (symbolS
*) 0;
6586 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6588 if (operand_type_check (i
.types
[0], imm
))
6589 i
.vex
.register_specifier
= NULL
;
6592 /* VEX.vvvv encodes one of the sources when the first
6593 operand is not an immediate. */
6594 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6595 i
.vex
.register_specifier
= i
.op
[0].regs
;
6597 i
.vex
.register_specifier
= i
.op
[1].regs
;
6600 /* Destination is a XMM register encoded in the ModRM.reg
6602 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6603 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6606 /* ModRM.rm and VEX.B encodes the other source. */
6607 if (!i
.mem_operands
)
6611 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6612 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6614 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6616 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6620 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6622 i
.vex
.register_specifier
= i
.op
[2].regs
;
6623 if (!i
.mem_operands
)
6626 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6627 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6631 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6632 (if any) based on i.tm.extension_opcode. Again, we must be
6633 careful to make sure that segment/control/debug/test/MMX
6634 registers are coded into the i.rm.reg field. */
6635 else if (i
.reg_operands
)
6638 unsigned int vex_reg
= ~0;
6640 for (op
= 0; op
< i
.operands
; op
++)
6641 if (i
.types
[op
].bitfield
.reg8
6642 || i
.types
[op
].bitfield
.reg16
6643 || i
.types
[op
].bitfield
.reg32
6644 || i
.types
[op
].bitfield
.reg64
6645 || i
.types
[op
].bitfield
.regmmx
6646 || i
.types
[op
].bitfield
.regxmm
6647 || i
.types
[op
].bitfield
.regymm
6648 || i
.types
[op
].bitfield
.regbnd
6649 || i
.types
[op
].bitfield
.regzmm
6650 || i
.types
[op
].bitfield
.regmask
6651 || i
.types
[op
].bitfield
.sreg2
6652 || i
.types
[op
].bitfield
.sreg3
6653 || i
.types
[op
].bitfield
.control
6654 || i
.types
[op
].bitfield
.debug
6655 || i
.types
[op
].bitfield
.test
)
6660 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6662 /* For instructions with VexNDS, the register-only
6663 source operand is encoded in VEX prefix. */
6664 gas_assert (mem
!= (unsigned int) ~0);
6669 gas_assert (op
< i
.operands
);
6673 /* Check register-only source operand when two source
6674 operands are swapped. */
6675 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6676 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6680 gas_assert (mem
== (vex_reg
+ 1)
6681 && op
< i
.operands
);
6686 gas_assert (vex_reg
< i
.operands
);
6690 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6692 /* For instructions with VexNDD, the register destination
6693 is encoded in VEX prefix. */
6694 if (i
.mem_operands
== 0)
6696 /* There is no memory operand. */
6697 gas_assert ((op
+ 2) == i
.operands
);
6702 /* There are only 2 operands. */
6703 gas_assert (op
< 2 && i
.operands
== 2);
6708 gas_assert (op
< i
.operands
);
6710 if (vex_reg
!= (unsigned int) ~0)
6712 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6714 if (type
->bitfield
.reg32
!= 1
6715 && type
->bitfield
.reg64
!= 1
6716 && !operand_type_equal (type
, ®xmm
)
6717 && !operand_type_equal (type
, ®ymm
)
6718 && !operand_type_equal (type
, ®zmm
)
6719 && !operand_type_equal (type
, ®mask
))
6722 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6725 /* Don't set OP operand twice. */
6728 /* If there is an extension opcode to put here, the
6729 register number must be put into the regmem field. */
6730 if (i
.tm
.extension_opcode
!= None
)
6732 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6733 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6735 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6740 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6741 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6743 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6748 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6749 must set it to 3 to indicate this is a register operand
6750 in the regmem field. */
6751 if (!i
.mem_operands
)
6755 /* Fill in i.rm.reg field with extension opcode (if any). */
6756 if (i
.tm
.extension_opcode
!= None
)
6757 i
.rm
.reg
= i
.tm
.extension_opcode
;
6763 output_branch (void)
6769 relax_substateT subtype
;
6773 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6774 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6777 if (i
.prefix
[DATA_PREFIX
] != 0)
6783 /* Pentium4 branch hints. */
6784 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6785 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6790 if (i
.prefix
[REX_PREFIX
] != 0)
6796 /* BND prefixed jump. */
6797 if (i
.prefix
[BND_PREFIX
] != 0)
6799 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6803 if (i
.prefixes
!= 0 && !intel_syntax
)
6804 as_warn (_("skipping prefixes on this instruction"));
6806 /* It's always a symbol; End frag & setup for relax.
6807 Make sure there is enough room in this frag for the largest
6808 instruction we may generate in md_convert_frag. This is 2
6809 bytes for the opcode and room for the prefix and largest
6811 frag_grow (prefix
+ 2 + 4);
6812 /* Prefix and 1 opcode byte go in fr_fix. */
6813 p
= frag_more (prefix
+ 1);
6814 if (i
.prefix
[DATA_PREFIX
] != 0)
6815 *p
++ = DATA_PREFIX_OPCODE
;
6816 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6817 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6818 *p
++ = i
.prefix
[SEG_PREFIX
];
6819 if (i
.prefix
[REX_PREFIX
] != 0)
6820 *p
++ = i
.prefix
[REX_PREFIX
];
6821 *p
= i
.tm
.base_opcode
;
6823 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6824 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6825 else if (cpu_arch_flags
.bitfield
.cpui386
)
6826 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6828 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6831 sym
= i
.op
[0].disps
->X_add_symbol
;
6832 off
= i
.op
[0].disps
->X_add_number
;
6834 if (i
.op
[0].disps
->X_op
!= O_constant
6835 && i
.op
[0].disps
->X_op
!= O_symbol
)
6837 /* Handle complex expressions. */
6838 sym
= make_expr_symbol (i
.op
[0].disps
);
6842 /* 1 possible extra opcode + 4 byte displacement go in var part.
6843 Pass reloc in fr_var. */
6844 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6854 if (i
.tm
.opcode_modifier
.jumpbyte
)
6856 /* This is a loop or jecxz type instruction. */
6858 if (i
.prefix
[ADDR_PREFIX
] != 0)
6860 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6863 /* Pentium4 branch hints. */
6864 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6865 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6867 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6876 if (flag_code
== CODE_16BIT
)
6879 if (i
.prefix
[DATA_PREFIX
] != 0)
6881 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6891 if (i
.prefix
[REX_PREFIX
] != 0)
6893 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6897 /* BND prefixed jump. */
6898 if (i
.prefix
[BND_PREFIX
] != 0)
6900 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6904 if (i
.prefixes
!= 0 && !intel_syntax
)
6905 as_warn (_("skipping prefixes on this instruction"));
6907 p
= frag_more (i
.tm
.opcode_length
+ size
);
6908 switch (i
.tm
.opcode_length
)
6911 *p
++ = i
.tm
.base_opcode
>> 8;
6913 *p
++ = i
.tm
.base_opcode
;
6919 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6920 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6922 /* All jumps handled here are signed, but don't use a signed limit
6923 check for 32 and 16 bit jumps as we want to allow wrap around at
6924 4G and 64k respectively. */
6926 fixP
->fx_signed
= 1;
6930 output_interseg_jump (void)
6938 if (flag_code
== CODE_16BIT
)
6942 if (i
.prefix
[DATA_PREFIX
] != 0)
6948 if (i
.prefix
[REX_PREFIX
] != 0)
6958 if (i
.prefixes
!= 0 && !intel_syntax
)
6959 as_warn (_("skipping prefixes on this instruction"));
6961 /* 1 opcode; 2 segment; offset */
6962 p
= frag_more (prefix
+ 1 + 2 + size
);
6964 if (i
.prefix
[DATA_PREFIX
] != 0)
6965 *p
++ = DATA_PREFIX_OPCODE
;
6967 if (i
.prefix
[REX_PREFIX
] != 0)
6968 *p
++ = i
.prefix
[REX_PREFIX
];
6970 *p
++ = i
.tm
.base_opcode
;
6971 if (i
.op
[1].imms
->X_op
== O_constant
)
6973 offsetT n
= i
.op
[1].imms
->X_add_number
;
6976 && !fits_in_unsigned_word (n
)
6977 && !fits_in_signed_word (n
))
6979 as_bad (_("16-bit jump out of range"));
6982 md_number_to_chars (p
, n
, size
);
6985 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6986 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6987 if (i
.op
[0].imms
->X_op
!= O_constant
)
6988 as_bad (_("can't handle non absolute segment in `%s'"),
6990 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6996 fragS
*insn_start_frag
;
6997 offsetT insn_start_off
;
6999 /* Tie dwarf2 debug info to the address at the start of the insn.
7000 We can't do this after the insn has been output as the current
7001 frag may have been closed off. eg. by frag_var. */
7002 dwarf2_emit_insn (0);
7004 insn_start_frag
= frag_now
;
7005 insn_start_off
= frag_now_fix ();
7008 if (i
.tm
.opcode_modifier
.jump
)
7010 else if (i
.tm
.opcode_modifier
.jumpbyte
7011 || i
.tm
.opcode_modifier
.jumpdword
)
7013 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7014 output_interseg_jump ();
7017 /* Output normal instructions here. */
7021 unsigned int prefix
;
7024 && i
.tm
.base_opcode
== 0xfae
7026 && i
.imm_operands
== 1
7027 && (i
.op
[0].imms
->X_add_number
== 0xe8
7028 || i
.op
[0].imms
->X_add_number
== 0xf0
7029 || i
.op
[0].imms
->X_add_number
== 0xf8))
7031 /* Encode lfence, mfence, and sfence as
7032 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7033 offsetT val
= 0x240483f0ULL
;
7035 md_number_to_chars (p
, val
, 5);
7039 /* Some processors fail on LOCK prefix. This options makes
7040 assembler ignore LOCK prefix and serves as a workaround. */
7041 if (omit_lock_prefix
)
7043 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7045 i
.prefix
[LOCK_PREFIX
] = 0;
7048 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7049 don't need the explicit prefix. */
7050 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7052 switch (i
.tm
.opcode_length
)
7055 if (i
.tm
.base_opcode
& 0xff000000)
7057 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7062 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7064 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7065 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7068 if (prefix
!= REPE_PREFIX_OPCODE
7069 || (i
.prefix
[REP_PREFIX
]
7070 != REPE_PREFIX_OPCODE
))
7071 add_prefix (prefix
);
7074 add_prefix (prefix
);
7083 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7084 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7085 R_X86_64_GOTTPOFF relocation so that linker can safely
7086 perform IE->LE optimization. */
7087 if (x86_elf_abi
== X86_64_X32_ABI
7089 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7090 && i
.prefix
[REX_PREFIX
] == 0)
7091 add_prefix (REX_OPCODE
);
7094 /* The prefix bytes. */
7095 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7097 FRAG_APPEND_1_CHAR (*q
);
7101 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7106 /* REX byte is encoded in VEX prefix. */
7110 FRAG_APPEND_1_CHAR (*q
);
7113 /* There should be no other prefixes for instructions
7118 /* For EVEX instructions i.vrex should become 0 after
7119 build_evex_prefix. For VEX instructions upper 16 registers
7120 aren't available, so VREX should be 0. */
7123 /* Now the VEX prefix. */
7124 p
= frag_more (i
.vex
.length
);
7125 for (j
= 0; j
< i
.vex
.length
; j
++)
7126 p
[j
] = i
.vex
.bytes
[j
];
7129 /* Now the opcode; be careful about word order here! */
7130 if (i
.tm
.opcode_length
== 1)
7132 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7136 switch (i
.tm
.opcode_length
)
7140 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7141 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7145 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7155 /* Put out high byte first: can't use md_number_to_chars! */
7156 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7157 *p
= i
.tm
.base_opcode
& 0xff;
7160 /* Now the modrm byte and sib byte (if present). */
7161 if (i
.tm
.opcode_modifier
.modrm
)
7163 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7166 /* If i.rm.regmem == ESP (4)
7167 && i.rm.mode != (Register mode)
7169 ==> need second modrm byte. */
7170 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7172 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7173 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7175 | i
.sib
.scale
<< 6));
7178 if (i
.disp_operands
)
7179 output_disp (insn_start_frag
, insn_start_off
);
7182 output_imm (insn_start_frag
, insn_start_off
);
7188 pi ("" /*line*/, &i
);
7190 #endif /* DEBUG386 */
7193 /* Return the size of the displacement operand N. */
7196 disp_size (unsigned int n
)
7200 /* Vec_Disp8 has to be 8bit. */
7201 if (i
.types
[n
].bitfield
.vec_disp8
)
7203 else if (i
.types
[n
].bitfield
.disp64
)
7205 else if (i
.types
[n
].bitfield
.disp8
)
7207 else if (i
.types
[n
].bitfield
.disp16
)
7212 /* Return the size of the immediate operand N. */
7215 imm_size (unsigned int n
)
7218 if (i
.types
[n
].bitfield
.imm64
)
7220 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7222 else if (i
.types
[n
].bitfield
.imm16
)
7228 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7233 for (n
= 0; n
< i
.operands
; n
++)
7235 if (i
.types
[n
].bitfield
.vec_disp8
7236 || operand_type_check (i
.types
[n
], disp
))
7238 if (i
.op
[n
].disps
->X_op
== O_constant
)
7240 int size
= disp_size (n
);
7241 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7243 if (i
.types
[n
].bitfield
.vec_disp8
)
7245 val
= offset_in_range (val
, size
);
7246 p
= frag_more (size
);
7247 md_number_to_chars (p
, val
, size
);
7251 enum bfd_reloc_code_real reloc_type
;
7252 int size
= disp_size (n
);
7253 int sign
= i
.types
[n
].bitfield
.disp32s
;
7254 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7257 /* We can't have 8 bit displacement here. */
7258 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7260 /* The PC relative address is computed relative
7261 to the instruction boundary, so in case immediate
7262 fields follows, we need to adjust the value. */
7263 if (pcrel
&& i
.imm_operands
)
7268 for (n1
= 0; n1
< i
.operands
; n1
++)
7269 if (operand_type_check (i
.types
[n1
], imm
))
7271 /* Only one immediate is allowed for PC
7272 relative address. */
7273 gas_assert (sz
== 0);
7275 i
.op
[n
].disps
->X_add_number
-= sz
;
7277 /* We should find the immediate. */
7278 gas_assert (sz
!= 0);
7281 p
= frag_more (size
);
7282 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7284 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7285 && (((reloc_type
== BFD_RELOC_32
7286 || reloc_type
== BFD_RELOC_X86_64_32S
7287 || (reloc_type
== BFD_RELOC_64
7289 && (i
.op
[n
].disps
->X_op
== O_symbol
7290 || (i
.op
[n
].disps
->X_op
== O_add
7291 && ((symbol_get_value_expression
7292 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7294 || reloc_type
== BFD_RELOC_32_PCREL
))
7298 if (insn_start_frag
== frag_now
)
7299 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7304 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7305 for (fr
= insn_start_frag
->fr_next
;
7306 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7308 add
+= p
- frag_now
->fr_literal
;
7313 reloc_type
= BFD_RELOC_386_GOTPC
;
7314 i
.op
[n
].imms
->X_add_number
+= add
;
7316 else if (reloc_type
== BFD_RELOC_64
)
7317 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7319 /* Don't do the adjustment for x86-64, as there
7320 the pcrel addressing is relative to the _next_
7321 insn, and that is taken care of in other code. */
7322 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7324 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7325 size
, i
.op
[n
].disps
, pcrel
,
7327 /* Check for "call/jmp *mem", "mov mem, %reg",
7328 "test %reg, mem" and "binop mem, %reg" where binop
7329 is one of adc, add, and, cmp, or, sbb, sub, xor
7330 instructions. Always generate R_386_GOT32X for
7331 "sym*GOT" operand in 32-bit mode. */
7332 if ((generate_relax_relocations
7335 && i
.rm
.regmem
== 5))
7337 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7338 && ((i
.operands
== 1
7339 && i
.tm
.base_opcode
== 0xff
7340 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7342 && (i
.tm
.base_opcode
== 0x8b
7343 || i
.tm
.base_opcode
== 0x85
7344 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7348 fixP
->fx_tcbit
= i
.rex
!= 0;
7350 && (i
.base_reg
->reg_num
== RegRip
7351 || i
.base_reg
->reg_num
== RegEip
))
7352 fixP
->fx_tcbit2
= 1;
7355 fixP
->fx_tcbit2
= 1;
7363 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7368 for (n
= 0; n
< i
.operands
; n
++)
7370 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7371 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7374 if (operand_type_check (i
.types
[n
], imm
))
7376 if (i
.op
[n
].imms
->X_op
== O_constant
)
7378 int size
= imm_size (n
);
7381 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7383 p
= frag_more (size
);
7384 md_number_to_chars (p
, val
, size
);
7388 /* Not absolute_section.
7389 Need a 32-bit fixup (don't support 8bit
7390 non-absolute imms). Try to support other
7392 enum bfd_reloc_code_real reloc_type
;
7393 int size
= imm_size (n
);
7396 if (i
.types
[n
].bitfield
.imm32s
7397 && (i
.suffix
== QWORD_MNEM_SUFFIX
7398 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7403 p
= frag_more (size
);
7404 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7406 /* This is tough to explain. We end up with this one if we
7407 * have operands that look like
7408 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7409 * obtain the absolute address of the GOT, and it is strongly
7410 * preferable from a performance point of view to avoid using
7411 * a runtime relocation for this. The actual sequence of
7412 * instructions often look something like:
7417 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7419 * The call and pop essentially return the absolute address
7420 * of the label .L66 and store it in %ebx. The linker itself
7421 * will ultimately change the first operand of the addl so
7422 * that %ebx points to the GOT, but to keep things simple, the
7423 * .o file must have this operand set so that it generates not
7424 * the absolute address of .L66, but the absolute address of
7425 * itself. This allows the linker itself simply treat a GOTPC
7426 * relocation as asking for a pcrel offset to the GOT to be
7427 * added in, and the addend of the relocation is stored in the
7428 * operand field for the instruction itself.
7430 * Our job here is to fix the operand so that it would add
7431 * the correct offset so that %ebx would point to itself. The
7432 * thing that is tricky is that .-.L66 will point to the
7433 * beginning of the instruction, so we need to further modify
7434 * the operand so that it will point to itself. There are
7435 * other cases where you have something like:
7437 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7439 * and here no correction would be required. Internally in
7440 * the assembler we treat operands of this form as not being
7441 * pcrel since the '.' is explicitly mentioned, and I wonder
7442 * whether it would simplify matters to do it this way. Who
7443 * knows. In earlier versions of the PIC patches, the
7444 * pcrel_adjust field was used to store the correction, but
7445 * since the expression is not pcrel, I felt it would be
7446 * confusing to do it this way. */
7448 if ((reloc_type
== BFD_RELOC_32
7449 || reloc_type
== BFD_RELOC_X86_64_32S
7450 || reloc_type
== BFD_RELOC_64
)
7452 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7453 && (i
.op
[n
].imms
->X_op
== O_symbol
7454 || (i
.op
[n
].imms
->X_op
== O_add
7455 && ((symbol_get_value_expression
7456 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7461 if (insn_start_frag
== frag_now
)
7462 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7467 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7468 for (fr
= insn_start_frag
->fr_next
;
7469 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7471 add
+= p
- frag_now
->fr_literal
;
7475 reloc_type
= BFD_RELOC_386_GOTPC
;
7477 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7479 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7480 i
.op
[n
].imms
->X_add_number
+= add
;
7482 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7483 i
.op
[n
].imms
, 0, reloc_type
);
7489 /* x86_cons_fix_new is called via the expression parsing code when a
7490 reloc is needed. We use this hook to get the correct .got reloc. */
7491 static int cons_sign
= -1;
7494 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7495 expressionS
*exp
, bfd_reloc_code_real_type r
)
7497 r
= reloc (len
, 0, cons_sign
, r
);
7500 if (exp
->X_op
== O_secrel
)
7502 exp
->X_op
= O_symbol
;
7503 r
= BFD_RELOC_32_SECREL
;
7507 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7510 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7511 purpose of the `.dc.a' internal pseudo-op. */
7514 x86_address_bytes (void)
7516 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7518 return stdoutput
->arch_info
->bits_per_address
/ 8;
7521 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7523 # define lex_got(reloc, adjust, types) NULL
7525 /* Parse operands of the form
7526 <symbol>@GOTOFF+<nnn>
7527 and similar .plt or .got references.
7529 If we find one, set up the correct relocation in RELOC and copy the
7530 input string, minus the `@GOTOFF' into a malloc'd buffer for
7531 parsing by the calling routine. Return this buffer, and if ADJUST
7532 is non-null set it to the length of the string we removed from the
7533 input line. Otherwise return NULL. */
7535 lex_got (enum bfd_reloc_code_real
*rel
,
7537 i386_operand_type
*types
)
7539 /* Some of the relocations depend on the size of what field is to
7540 be relocated. But in our callers i386_immediate and i386_displacement
7541 we don't yet know the operand size (this will be set by insn
7542 matching). Hence we record the word32 relocation here,
7543 and adjust the reloc according to the real size in reloc(). */
7544 static const struct {
7547 const enum bfd_reloc_code_real rel
[2];
7548 const i386_operand_type types64
;
7550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7551 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7553 OPERAND_TYPE_IMM32_64
},
7555 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7556 BFD_RELOC_X86_64_PLTOFF64
},
7557 OPERAND_TYPE_IMM64
},
7558 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7559 BFD_RELOC_X86_64_PLT32
},
7560 OPERAND_TYPE_IMM32_32S_DISP32
},
7561 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7562 BFD_RELOC_X86_64_GOTPLT64
},
7563 OPERAND_TYPE_IMM64_DISP64
},
7564 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7565 BFD_RELOC_X86_64_GOTOFF64
},
7566 OPERAND_TYPE_IMM64_DISP64
},
7567 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7568 BFD_RELOC_X86_64_GOTPCREL
},
7569 OPERAND_TYPE_IMM32_32S_DISP32
},
7570 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7571 BFD_RELOC_X86_64_TLSGD
},
7572 OPERAND_TYPE_IMM32_32S_DISP32
},
7573 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7574 _dummy_first_bfd_reloc_code_real
},
7575 OPERAND_TYPE_NONE
},
7576 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7577 BFD_RELOC_X86_64_TLSLD
},
7578 OPERAND_TYPE_IMM32_32S_DISP32
},
7579 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7580 BFD_RELOC_X86_64_GOTTPOFF
},
7581 OPERAND_TYPE_IMM32_32S_DISP32
},
7582 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7583 BFD_RELOC_X86_64_TPOFF32
},
7584 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7585 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7586 _dummy_first_bfd_reloc_code_real
},
7587 OPERAND_TYPE_NONE
},
7588 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7589 BFD_RELOC_X86_64_DTPOFF32
},
7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7591 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7592 _dummy_first_bfd_reloc_code_real
},
7593 OPERAND_TYPE_NONE
},
7594 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7595 _dummy_first_bfd_reloc_code_real
},
7596 OPERAND_TYPE_NONE
},
7597 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7598 BFD_RELOC_X86_64_GOT32
},
7599 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7600 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7601 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7602 OPERAND_TYPE_IMM32_32S_DISP32
},
7603 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7604 BFD_RELOC_X86_64_TLSDESC_CALL
},
7605 OPERAND_TYPE_IMM32_32S_DISP32
},
7610 #if defined (OBJ_MAYBE_ELF)
7615 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7616 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7619 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7621 int len
= gotrel
[j
].len
;
7622 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7624 if (gotrel
[j
].rel
[object_64bit
] != 0)
7627 char *tmpbuf
, *past_reloc
;
7629 *rel
= gotrel
[j
].rel
[object_64bit
];
7633 if (flag_code
!= CODE_64BIT
)
7635 types
->bitfield
.imm32
= 1;
7636 types
->bitfield
.disp32
= 1;
7639 *types
= gotrel
[j
].types64
;
7642 if (j
!= 0 && GOT_symbol
== NULL
)
7643 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7645 /* The length of the first part of our input line. */
7646 first
= cp
- input_line_pointer
;
7648 /* The second part goes from after the reloc token until
7649 (and including) an end_of_line char or comma. */
7650 past_reloc
= cp
+ 1 + len
;
7652 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7654 second
= cp
+ 1 - past_reloc
;
7656 /* Allocate and copy string. The trailing NUL shouldn't
7657 be necessary, but be safe. */
7658 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7659 memcpy (tmpbuf
, input_line_pointer
, first
);
7660 if (second
!= 0 && *past_reloc
!= ' ')
7661 /* Replace the relocation token with ' ', so that
7662 errors like foo@GOTOFF1 will be detected. */
7663 tmpbuf
[first
++] = ' ';
7665 /* Increment length by 1 if the relocation token is
7670 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7671 tmpbuf
[first
+ second
] = '\0';
7675 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7676 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7681 /* Might be a symbol version string. Don't as_bad here. */
7690 /* Parse operands of the form
7691 <symbol>@SECREL32+<nnn>
7693 If we find one, set up the correct relocation in RELOC and copy the
7694 input string, minus the `@SECREL32' into a malloc'd buffer for
7695 parsing by the calling routine. Return this buffer, and if ADJUST
7696 is non-null set it to the length of the string we removed from the
7697 input line. Otherwise return NULL.
7699 This function is copied from the ELF version above adjusted for PE targets. */
7702 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7703 int *adjust ATTRIBUTE_UNUSED
,
7704 i386_operand_type
*types
)
7710 const enum bfd_reloc_code_real rel
[2];
7711 const i386_operand_type types64
;
7715 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7716 BFD_RELOC_32_SECREL
},
7717 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7723 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7724 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7727 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7729 int len
= gotrel
[j
].len
;
7731 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7733 if (gotrel
[j
].rel
[object_64bit
] != 0)
7736 char *tmpbuf
, *past_reloc
;
7738 *rel
= gotrel
[j
].rel
[object_64bit
];
7744 if (flag_code
!= CODE_64BIT
)
7746 types
->bitfield
.imm32
= 1;
7747 types
->bitfield
.disp32
= 1;
7750 *types
= gotrel
[j
].types64
;
7753 /* The length of the first part of our input line. */
7754 first
= cp
- input_line_pointer
;
7756 /* The second part goes from after the reloc token until
7757 (and including) an end_of_line char or comma. */
7758 past_reloc
= cp
+ 1 + len
;
7760 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7762 second
= cp
+ 1 - past_reloc
;
7764 /* Allocate and copy string. The trailing NUL shouldn't
7765 be necessary, but be safe. */
7766 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7767 memcpy (tmpbuf
, input_line_pointer
, first
);
7768 if (second
!= 0 && *past_reloc
!= ' ')
7769 /* Replace the relocation token with ' ', so that
7770 errors like foo@SECLREL321 will be detected. */
7771 tmpbuf
[first
++] = ' ';
7772 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7773 tmpbuf
[first
+ second
] = '\0';
7777 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7778 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7783 /* Might be a symbol version string. Don't as_bad here. */
7789 bfd_reloc_code_real_type
7790 x86_cons (expressionS
*exp
, int size
)
7792 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7794 intel_syntax
= -intel_syntax
;
7797 if (size
== 4 || (object_64bit
&& size
== 8))
7799 /* Handle @GOTOFF and the like in an expression. */
7801 char *gotfree_input_line
;
7804 save
= input_line_pointer
;
7805 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7806 if (gotfree_input_line
)
7807 input_line_pointer
= gotfree_input_line
;
7811 if (gotfree_input_line
)
7813 /* expression () has merrily parsed up to the end of line,
7814 or a comma - in the wrong buffer. Transfer how far
7815 input_line_pointer has moved to the right buffer. */
7816 input_line_pointer
= (save
7817 + (input_line_pointer
- gotfree_input_line
)
7819 free (gotfree_input_line
);
7820 if (exp
->X_op
== O_constant
7821 || exp
->X_op
== O_absent
7822 || exp
->X_op
== O_illegal
7823 || exp
->X_op
== O_register
7824 || exp
->X_op
== O_big
)
7826 char c
= *input_line_pointer
;
7827 *input_line_pointer
= 0;
7828 as_bad (_("missing or invalid expression `%s'"), save
);
7829 *input_line_pointer
= c
;
7836 intel_syntax
= -intel_syntax
;
7839 i386_intel_simplify (exp
);
7845 signed_cons (int size
)
7847 if (flag_code
== CODE_64BIT
)
7855 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7862 if (exp
.X_op
== O_symbol
)
7863 exp
.X_op
= O_secrel
;
7865 emit_expr (&exp
, 4);
7867 while (*input_line_pointer
++ == ',');
7869 input_line_pointer
--;
7870 demand_empty_rest_of_line ();
7874 /* Handle Vector operations. */
7877 check_VecOperations (char *op_string
, char *op_end
)
7879 const reg_entry
*mask
;
7884 && (op_end
== NULL
|| op_string
< op_end
))
7887 if (*op_string
== '{')
7891 /* Check broadcasts. */
7892 if (strncmp (op_string
, "1to", 3) == 0)
7897 goto duplicated_vec_op
;
7900 if (*op_string
== '8')
7901 bcst_type
= BROADCAST_1TO8
;
7902 else if (*op_string
== '4')
7903 bcst_type
= BROADCAST_1TO4
;
7904 else if (*op_string
== '2')
7905 bcst_type
= BROADCAST_1TO2
;
7906 else if (*op_string
== '1'
7907 && *(op_string
+1) == '6')
7909 bcst_type
= BROADCAST_1TO16
;
7914 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7919 broadcast_op
.type
= bcst_type
;
7920 broadcast_op
.operand
= this_operand
;
7921 i
.broadcast
= &broadcast_op
;
7923 /* Check masking operation. */
7924 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7926 /* k0 can't be used for write mask. */
7927 if (mask
->reg_num
== 0)
7929 as_bad (_("`%s' can't be used for write mask"),
7936 mask_op
.mask
= mask
;
7937 mask_op
.zeroing
= 0;
7938 mask_op
.operand
= this_operand
;
7944 goto duplicated_vec_op
;
7946 i
.mask
->mask
= mask
;
7948 /* Only "{z}" is allowed here. No need to check
7949 zeroing mask explicitly. */
7950 if (i
.mask
->operand
!= this_operand
)
7952 as_bad (_("invalid write mask `%s'"), saved
);
7959 /* Check zeroing-flag for masking operation. */
7960 else if (*op_string
== 'z')
7964 mask_op
.mask
= NULL
;
7965 mask_op
.zeroing
= 1;
7966 mask_op
.operand
= this_operand
;
7971 if (i
.mask
->zeroing
)
7974 as_bad (_("duplicated `%s'"), saved
);
7978 i
.mask
->zeroing
= 1;
7980 /* Only "{%k}" is allowed here. No need to check mask
7981 register explicitly. */
7982 if (i
.mask
->operand
!= this_operand
)
7984 as_bad (_("invalid zeroing-masking `%s'"),
7993 goto unknown_vec_op
;
7995 if (*op_string
!= '}')
7997 as_bad (_("missing `}' in `%s'"), saved
);
8004 /* We don't know this one. */
8005 as_bad (_("unknown vector operation: `%s'"), saved
);
8013 i386_immediate (char *imm_start
)
8015 char *save_input_line_pointer
;
8016 char *gotfree_input_line
;
8019 i386_operand_type types
;
8021 operand_type_set (&types
, ~0);
8023 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8025 as_bad (_("at most %d immediate operands are allowed"),
8026 MAX_IMMEDIATE_OPERANDS
);
8030 exp
= &im_expressions
[i
.imm_operands
++];
8031 i
.op
[this_operand
].imms
= exp
;
8033 if (is_space_char (*imm_start
))
8036 save_input_line_pointer
= input_line_pointer
;
8037 input_line_pointer
= imm_start
;
8039 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8040 if (gotfree_input_line
)
8041 input_line_pointer
= gotfree_input_line
;
8043 exp_seg
= expression (exp
);
8047 /* Handle vector operations. */
8048 if (*input_line_pointer
== '{')
8050 input_line_pointer
= check_VecOperations (input_line_pointer
,
8052 if (input_line_pointer
== NULL
)
8056 if (*input_line_pointer
)
8057 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8059 input_line_pointer
= save_input_line_pointer
;
8060 if (gotfree_input_line
)
8062 free (gotfree_input_line
);
8064 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8065 exp
->X_op
= O_illegal
;
8068 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8072 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8073 i386_operand_type types
, const char *imm_start
)
8075 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8078 as_bad (_("missing or invalid immediate expression `%s'"),
8082 else if (exp
->X_op
== O_constant
)
8084 /* Size it properly later. */
8085 i
.types
[this_operand
].bitfield
.imm64
= 1;
8086 /* If not 64bit, sign extend val. */
8087 if (flag_code
!= CODE_64BIT
8088 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8090 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8092 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8093 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8094 && exp_seg
!= absolute_section
8095 && exp_seg
!= text_section
8096 && exp_seg
!= data_section
8097 && exp_seg
!= bss_section
8098 && exp_seg
!= undefined_section
8099 && !bfd_is_com_section (exp_seg
))
8101 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8105 else if (!intel_syntax
&& exp_seg
== reg_section
)
8108 as_bad (_("illegal immediate register operand %s"), imm_start
);
8113 /* This is an address. The size of the address will be
8114 determined later, depending on destination register,
8115 suffix, or the default for the section. */
8116 i
.types
[this_operand
].bitfield
.imm8
= 1;
8117 i
.types
[this_operand
].bitfield
.imm16
= 1;
8118 i
.types
[this_operand
].bitfield
.imm32
= 1;
8119 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8120 i
.types
[this_operand
].bitfield
.imm64
= 1;
8121 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8129 i386_scale (char *scale
)
8132 char *save
= input_line_pointer
;
8134 input_line_pointer
= scale
;
8135 val
= get_absolute_expression ();
8140 i
.log2_scale_factor
= 0;
8143 i
.log2_scale_factor
= 1;
8146 i
.log2_scale_factor
= 2;
8149 i
.log2_scale_factor
= 3;
8153 char sep
= *input_line_pointer
;
8155 *input_line_pointer
= '\0';
8156 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8158 *input_line_pointer
= sep
;
8159 input_line_pointer
= save
;
8163 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8165 as_warn (_("scale factor of %d without an index register"),
8166 1 << i
.log2_scale_factor
);
8167 i
.log2_scale_factor
= 0;
8169 scale
= input_line_pointer
;
8170 input_line_pointer
= save
;
8175 i386_displacement (char *disp_start
, char *disp_end
)
8179 char *save_input_line_pointer
;
8180 char *gotfree_input_line
;
8182 i386_operand_type bigdisp
, types
= anydisp
;
8185 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8187 as_bad (_("at most %d displacement operands are allowed"),
8188 MAX_MEMORY_OPERANDS
);
8192 operand_type_set (&bigdisp
, 0);
8193 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8194 || (!current_templates
->start
->opcode_modifier
.jump
8195 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8197 bigdisp
.bitfield
.disp32
= 1;
8198 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8199 if (flag_code
== CODE_64BIT
)
8203 bigdisp
.bitfield
.disp32s
= 1;
8204 bigdisp
.bitfield
.disp64
= 1;
8207 else if ((flag_code
== CODE_16BIT
) ^ override
)
8209 bigdisp
.bitfield
.disp32
= 0;
8210 bigdisp
.bitfield
.disp16
= 1;
8215 /* For PC-relative branches, the width of the displacement
8216 is dependent upon data size, not address size. */
8217 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8218 if (flag_code
== CODE_64BIT
)
8220 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8221 bigdisp
.bitfield
.disp16
= 1;
8224 bigdisp
.bitfield
.disp32
= 1;
8225 bigdisp
.bitfield
.disp32s
= 1;
8231 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8233 : LONG_MNEM_SUFFIX
));
8234 bigdisp
.bitfield
.disp32
= 1;
8235 if ((flag_code
== CODE_16BIT
) ^ override
)
8237 bigdisp
.bitfield
.disp32
= 0;
8238 bigdisp
.bitfield
.disp16
= 1;
8242 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8245 exp
= &disp_expressions
[i
.disp_operands
];
8246 i
.op
[this_operand
].disps
= exp
;
8248 save_input_line_pointer
= input_line_pointer
;
8249 input_line_pointer
= disp_start
;
8250 END_STRING_AND_SAVE (disp_end
);
8252 #ifndef GCC_ASM_O_HACK
8253 #define GCC_ASM_O_HACK 0
8256 END_STRING_AND_SAVE (disp_end
+ 1);
8257 if (i
.types
[this_operand
].bitfield
.baseIndex
8258 && displacement_string_end
[-1] == '+')
8260 /* This hack is to avoid a warning when using the "o"
8261 constraint within gcc asm statements.
8264 #define _set_tssldt_desc(n,addr,limit,type) \
8265 __asm__ __volatile__ ( \
8267 "movw %w1,2+%0\n\t" \
8269 "movb %b1,4+%0\n\t" \
8270 "movb %4,5+%0\n\t" \
8271 "movb $0,6+%0\n\t" \
8272 "movb %h1,7+%0\n\t" \
8274 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8276 This works great except that the output assembler ends
8277 up looking a bit weird if it turns out that there is
8278 no offset. You end up producing code that looks like:
8291 So here we provide the missing zero. */
8293 *displacement_string_end
= '0';
8296 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8297 if (gotfree_input_line
)
8298 input_line_pointer
= gotfree_input_line
;
8300 exp_seg
= expression (exp
);
8303 if (*input_line_pointer
)
8304 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8306 RESTORE_END_STRING (disp_end
+ 1);
8308 input_line_pointer
= save_input_line_pointer
;
8309 if (gotfree_input_line
)
8311 free (gotfree_input_line
);
8313 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8314 exp
->X_op
= O_illegal
;
8317 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8319 RESTORE_END_STRING (disp_end
);
8325 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8326 i386_operand_type types
, const char *disp_start
)
8328 i386_operand_type bigdisp
;
8331 /* We do this to make sure that the section symbol is in
8332 the symbol table. We will ultimately change the relocation
8333 to be relative to the beginning of the section. */
8334 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8335 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8336 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8338 if (exp
->X_op
!= O_symbol
)
8341 if (S_IS_LOCAL (exp
->X_add_symbol
)
8342 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8343 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8344 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8345 exp
->X_op
= O_subtract
;
8346 exp
->X_op_symbol
= GOT_symbol
;
8347 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8348 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8349 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8350 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8352 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8355 else if (exp
->X_op
== O_absent
8356 || exp
->X_op
== O_illegal
8357 || exp
->X_op
== O_big
)
8360 as_bad (_("missing or invalid displacement expression `%s'"),
8365 else if (flag_code
== CODE_64BIT
8366 && !i
.prefix
[ADDR_PREFIX
]
8367 && exp
->X_op
== O_constant
)
8369 /* Since displacement is signed extended to 64bit, don't allow
8370 disp32 and turn off disp32s if they are out of range. */
8371 i
.types
[this_operand
].bitfield
.disp32
= 0;
8372 if (!fits_in_signed_long (exp
->X_add_number
))
8374 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8375 if (i
.types
[this_operand
].bitfield
.baseindex
)
8377 as_bad (_("0x%lx out range of signed 32bit displacement"),
8378 (long) exp
->X_add_number
);
8384 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8385 else if (exp
->X_op
!= O_constant
8386 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8387 && exp_seg
!= absolute_section
8388 && exp_seg
!= text_section
8389 && exp_seg
!= data_section
8390 && exp_seg
!= bss_section
8391 && exp_seg
!= undefined_section
8392 && !bfd_is_com_section (exp_seg
))
8394 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8399 /* Check if this is a displacement only operand. */
8400 bigdisp
= i
.types
[this_operand
];
8401 bigdisp
.bitfield
.disp8
= 0;
8402 bigdisp
.bitfield
.disp16
= 0;
8403 bigdisp
.bitfield
.disp32
= 0;
8404 bigdisp
.bitfield
.disp32s
= 0;
8405 bigdisp
.bitfield
.disp64
= 0;
8406 if (operand_type_all_zero (&bigdisp
))
8407 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8413 /* Make sure the memory operand we've been dealt is valid.
8414 Return 1 on success, 0 on a failure. */
8417 i386_index_check (const char *operand_string
)
8419 const char *kind
= "base/index";
8420 enum flag_code addr_mode
;
8422 if (i
.prefix
[ADDR_PREFIX
])
8423 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8426 addr_mode
= flag_code
;
8428 #if INFER_ADDR_PREFIX
8429 if (i
.mem_operands
== 0)
8431 /* Infer address prefix from the first memory operand. */
8432 const reg_entry
*addr_reg
= i
.base_reg
;
8434 if (addr_reg
== NULL
)
8435 addr_reg
= i
.index_reg
;
8439 if (addr_reg
->reg_num
== RegEip
8440 || addr_reg
->reg_num
== RegEiz
8441 || addr_reg
->reg_type
.bitfield
.reg32
)
8442 addr_mode
= CODE_32BIT
;
8443 else if (flag_code
!= CODE_64BIT
8444 && addr_reg
->reg_type
.bitfield
.reg16
)
8445 addr_mode
= CODE_16BIT
;
8447 if (addr_mode
!= flag_code
)
8449 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8451 /* Change the size of any displacement too. At most one
8452 of Disp16 or Disp32 is set.
8453 FIXME. There doesn't seem to be any real need for
8454 separate Disp16 and Disp32 flags. The same goes for
8455 Imm16 and Imm32. Removing them would probably clean
8456 up the code quite a lot. */
8457 if (flag_code
!= CODE_64BIT
8458 && (i
.types
[this_operand
].bitfield
.disp16
8459 || i
.types
[this_operand
].bitfield
.disp32
))
8460 i
.types
[this_operand
]
8461 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8468 if (current_templates
->start
->opcode_modifier
.isstring
8469 && !current_templates
->start
->opcode_modifier
.immext
8470 && (current_templates
->end
[-1].opcode_modifier
.isstring
8473 /* Memory operands of string insns are special in that they only allow
8474 a single register (rDI, rSI, or rBX) as their memory address. */
8475 const reg_entry
*expected_reg
;
8476 static const char *di_si
[][2] =
8482 static const char *bx
[] = { "ebx", "bx", "rbx" };
8484 kind
= "string address";
8486 if (current_templates
->start
->opcode_modifier
.w
)
8488 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8490 if (!type
.bitfield
.baseindex
8491 || ((!i
.mem_operands
!= !intel_syntax
)
8492 && current_templates
->end
[-1].operand_types
[1]
8493 .bitfield
.baseindex
))
8494 type
= current_templates
->end
[-1].operand_types
[1];
8495 expected_reg
= hash_find (reg_hash
,
8496 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8500 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8502 if (i
.base_reg
!= expected_reg
8504 || operand_type_check (i
.types
[this_operand
], disp
))
8506 /* The second memory operand must have the same size as
8510 && !((addr_mode
== CODE_64BIT
8511 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8512 || (addr_mode
== CODE_32BIT
8513 ? i
.base_reg
->reg_type
.bitfield
.reg32
8514 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8517 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8519 intel_syntax
? '[' : '(',
8521 expected_reg
->reg_name
,
8522 intel_syntax
? ']' : ')');
8529 as_bad (_("`%s' is not a valid %s expression"),
8530 operand_string
, kind
);
8535 if (addr_mode
!= CODE_16BIT
)
8537 /* 32-bit/64-bit checks. */
8539 && (addr_mode
== CODE_64BIT
8540 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8541 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8543 || (i
.base_reg
->reg_num
8544 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8546 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8547 && !i
.index_reg
->reg_type
.bitfield
.regymm
8548 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8549 && ((addr_mode
== CODE_64BIT
8550 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8551 || i
.index_reg
->reg_num
== RegRiz
)
8552 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8553 || i
.index_reg
->reg_num
== RegEiz
))
8554 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8559 /* 16-bit checks. */
8561 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8562 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8564 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8565 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8567 && i
.base_reg
->reg_num
< 6
8568 && i
.index_reg
->reg_num
>= 6
8569 && i
.log2_scale_factor
== 0))))
8576 /* Handle vector immediates. */
8579 RC_SAE_immediate (const char *imm_start
)
8581 unsigned int match_found
, j
;
8582 const char *pstr
= imm_start
;
8590 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8592 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8596 rc_op
.type
= RC_NamesTable
[j
].type
;
8597 rc_op
.operand
= this_operand
;
8598 i
.rounding
= &rc_op
;
8602 as_bad (_("duplicated `%s'"), imm_start
);
8605 pstr
+= RC_NamesTable
[j
].len
;
8615 as_bad (_("Missing '}': '%s'"), imm_start
);
8618 /* RC/SAE immediate string should contain nothing more. */;
8621 as_bad (_("Junk after '}': '%s'"), imm_start
);
8625 exp
= &im_expressions
[i
.imm_operands
++];
8626 i
.op
[this_operand
].imms
= exp
;
8628 exp
->X_op
= O_constant
;
8629 exp
->X_add_number
= 0;
8630 exp
->X_add_symbol
= (symbolS
*) 0;
8631 exp
->X_op_symbol
= (symbolS
*) 0;
8633 i
.types
[this_operand
].bitfield
.imm8
= 1;
8637 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8641 i386_att_operand (char *operand_string
)
8645 char *op_string
= operand_string
;
8647 if (is_space_char (*op_string
))
8650 /* We check for an absolute prefix (differentiating,
8651 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8652 if (*op_string
== ABSOLUTE_PREFIX
)
8655 if (is_space_char (*op_string
))
8657 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8660 /* Check if operand is a register. */
8661 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8663 i386_operand_type temp
;
8665 /* Check for a segment override by searching for ':' after a
8666 segment register. */
8668 if (is_space_char (*op_string
))
8670 if (*op_string
== ':'
8671 && (r
->reg_type
.bitfield
.sreg2
8672 || r
->reg_type
.bitfield
.sreg3
))
8677 i
.seg
[i
.mem_operands
] = &es
;
8680 i
.seg
[i
.mem_operands
] = &cs
;
8683 i
.seg
[i
.mem_operands
] = &ss
;
8686 i
.seg
[i
.mem_operands
] = &ds
;
8689 i
.seg
[i
.mem_operands
] = &fs
;
8692 i
.seg
[i
.mem_operands
] = &gs
;
8696 /* Skip the ':' and whitespace. */
8698 if (is_space_char (*op_string
))
8701 if (!is_digit_char (*op_string
)
8702 && !is_identifier_char (*op_string
)
8703 && *op_string
!= '('
8704 && *op_string
!= ABSOLUTE_PREFIX
)
8706 as_bad (_("bad memory operand `%s'"), op_string
);
8709 /* Handle case of %es:*foo. */
8710 if (*op_string
== ABSOLUTE_PREFIX
)
8713 if (is_space_char (*op_string
))
8715 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8717 goto do_memory_reference
;
8720 /* Handle vector operations. */
8721 if (*op_string
== '{')
8723 op_string
= check_VecOperations (op_string
, NULL
);
8724 if (op_string
== NULL
)
8730 as_bad (_("junk `%s' after register"), op_string
);
8734 temp
.bitfield
.baseindex
= 0;
8735 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8737 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8738 i
.op
[this_operand
].regs
= r
;
8741 else if (*op_string
== REGISTER_PREFIX
)
8743 as_bad (_("bad register name `%s'"), op_string
);
8746 else if (*op_string
== IMMEDIATE_PREFIX
)
8749 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8751 as_bad (_("immediate operand illegal with absolute jump"));
8754 if (!i386_immediate (op_string
))
8757 else if (RC_SAE_immediate (operand_string
))
8759 /* If it is a RC or SAE immediate, do nothing. */
8762 else if (is_digit_char (*op_string
)
8763 || is_identifier_char (*op_string
)
8764 || *op_string
== '"'
8765 || *op_string
== '(')
8767 /* This is a memory reference of some sort. */
8770 /* Start and end of displacement string expression (if found). */
8771 char *displacement_string_start
;
8772 char *displacement_string_end
;
8775 do_memory_reference
:
8776 if ((i
.mem_operands
== 1
8777 && !current_templates
->start
->opcode_modifier
.isstring
)
8778 || i
.mem_operands
== 2)
8780 as_bad (_("too many memory references for `%s'"),
8781 current_templates
->start
->name
);
8785 /* Check for base index form. We detect the base index form by
8786 looking for an ')' at the end of the operand, searching
8787 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8789 base_string
= op_string
+ strlen (op_string
);
8791 /* Handle vector operations. */
8792 vop_start
= strchr (op_string
, '{');
8793 if (vop_start
&& vop_start
< base_string
)
8795 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8797 base_string
= vop_start
;
8801 if (is_space_char (*base_string
))
8804 /* If we only have a displacement, set-up for it to be parsed later. */
8805 displacement_string_start
= op_string
;
8806 displacement_string_end
= base_string
+ 1;
8808 if (*base_string
== ')')
8811 unsigned int parens_balanced
= 1;
8812 /* We've already checked that the number of left & right ()'s are
8813 equal, so this loop will not be infinite. */
8817 if (*base_string
== ')')
8819 if (*base_string
== '(')
8822 while (parens_balanced
);
8824 temp_string
= base_string
;
8826 /* Skip past '(' and whitespace. */
8828 if (is_space_char (*base_string
))
8831 if (*base_string
== ','
8832 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8835 displacement_string_end
= temp_string
;
8837 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8841 base_string
= end_op
;
8842 if (is_space_char (*base_string
))
8846 /* There may be an index reg or scale factor here. */
8847 if (*base_string
== ',')
8850 if (is_space_char (*base_string
))
8853 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8856 base_string
= end_op
;
8857 if (is_space_char (*base_string
))
8859 if (*base_string
== ',')
8862 if (is_space_char (*base_string
))
8865 else if (*base_string
!= ')')
8867 as_bad (_("expecting `,' or `)' "
8868 "after index register in `%s'"),
8873 else if (*base_string
== REGISTER_PREFIX
)
8875 end_op
= strchr (base_string
, ',');
8878 as_bad (_("bad register name `%s'"), base_string
);
8882 /* Check for scale factor. */
8883 if (*base_string
!= ')')
8885 char *end_scale
= i386_scale (base_string
);
8890 base_string
= end_scale
;
8891 if (is_space_char (*base_string
))
8893 if (*base_string
!= ')')
8895 as_bad (_("expecting `)' "
8896 "after scale factor in `%s'"),
8901 else if (!i
.index_reg
)
8903 as_bad (_("expecting index register or scale factor "
8904 "after `,'; got '%c'"),
8909 else if (*base_string
!= ')')
8911 as_bad (_("expecting `,' or `)' "
8912 "after base register in `%s'"),
8917 else if (*base_string
== REGISTER_PREFIX
)
8919 end_op
= strchr (base_string
, ',');
8922 as_bad (_("bad register name `%s'"), base_string
);
8927 /* If there's an expression beginning the operand, parse it,
8928 assuming displacement_string_start and
8929 displacement_string_end are meaningful. */
8930 if (displacement_string_start
!= displacement_string_end
)
8932 if (!i386_displacement (displacement_string_start
,
8933 displacement_string_end
))
8937 /* Special case for (%dx) while doing input/output op. */
8939 && operand_type_equal (&i
.base_reg
->reg_type
,
8940 ®16_inoutportreg
)
8942 && i
.log2_scale_factor
== 0
8943 && i
.seg
[i
.mem_operands
] == 0
8944 && !operand_type_check (i
.types
[this_operand
], disp
))
8946 i
.types
[this_operand
] = inoutportreg
;
8950 if (i386_index_check (operand_string
) == 0)
8952 i
.types
[this_operand
].bitfield
.mem
= 1;
8957 /* It's not a memory operand; argh! */
8958 as_bad (_("invalid char %s beginning operand %d `%s'"),
8959 output_invalid (*op_string
),
8964 return 1; /* Normal return. */
8967 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8968 that an rs_machine_dependent frag may reach. */
8971 i386_frag_max_var (fragS
*frag
)
8973 /* The only relaxable frags are for jumps.
8974 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8975 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8976 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8981 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8983 /* STT_GNU_IFUNC symbol must go through PLT. */
8984 if ((symbol_get_bfdsym (fr_symbol
)->flags
8985 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8988 if (!S_IS_EXTERNAL (fr_symbol
))
8989 /* Symbol may be weak or local. */
8990 return !S_IS_WEAK (fr_symbol
);
8992 /* Global symbols with non-default visibility can't be preempted. */
8993 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8996 if (fr_var
!= NO_RELOC
)
8997 switch ((enum bfd_reloc_code_real
) fr_var
)
8999 case BFD_RELOC_386_PLT32
:
9000 case BFD_RELOC_X86_64_PLT32
:
9001 /* Symbol with PLT relocatin may be preempted. */
9007 /* Global symbols with default visibility in a shared library may be
9008 preempted by another definition. */
9013 /* md_estimate_size_before_relax()
9015 Called just before relax() for rs_machine_dependent frags. The x86
9016 assembler uses these frags to handle variable size jump
9019 Any symbol that is now undefined will not become defined.
9020 Return the correct fr_subtype in the frag.
9021 Return the initial "guess for variable size of frag" to caller.
9022 The guess is actually the growth beyond the fixed part. Whatever
9023 we do to grow the fixed or variable part contributes to our
9027 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9029 /* We've already got fragP->fr_subtype right; all we have to do is
9030 check for un-relaxable symbols. On an ELF system, we can't relax
9031 an externally visible symbol, because it may be overridden by a
9033 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9036 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9039 #if defined (OBJ_COFF) && defined (TE_PE)
9040 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9041 && S_IS_WEAK (fragP
->fr_symbol
))
9045 /* Symbol is undefined in this segment, or we need to keep a
9046 reloc so that weak symbols can be overridden. */
9047 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9048 enum bfd_reloc_code_real reloc_type
;
9049 unsigned char *opcode
;
9052 if (fragP
->fr_var
!= NO_RELOC
)
9053 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9055 reloc_type
= BFD_RELOC_16_PCREL
;
9057 reloc_type
= BFD_RELOC_32_PCREL
;
9059 old_fr_fix
= fragP
->fr_fix
;
9060 opcode
= (unsigned char *) fragP
->fr_opcode
;
9062 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9065 /* Make jmp (0xeb) a (d)word displacement jump. */
9067 fragP
->fr_fix
+= size
;
9068 fix_new (fragP
, old_fr_fix
, size
,
9070 fragP
->fr_offset
, 1,
9076 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9078 /* Negate the condition, and branch past an
9079 unconditional jump. */
9082 /* Insert an unconditional jump. */
9084 /* We added two extra opcode bytes, and have a two byte
9086 fragP
->fr_fix
+= 2 + 2;
9087 fix_new (fragP
, old_fr_fix
+ 2, 2,
9089 fragP
->fr_offset
, 1,
9096 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9101 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9103 fragP
->fr_offset
, 1,
9105 fixP
->fx_signed
= 1;
9109 /* This changes the byte-displacement jump 0x7N
9110 to the (d)word-displacement jump 0x0f,0x8N. */
9111 opcode
[1] = opcode
[0] + 0x10;
9112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9113 /* We've added an opcode byte. */
9114 fragP
->fr_fix
+= 1 + size
;
9115 fix_new (fragP
, old_fr_fix
+ 1, size
,
9117 fragP
->fr_offset
, 1,
9122 BAD_CASE (fragP
->fr_subtype
);
9126 return fragP
->fr_fix
- old_fr_fix
;
9129 /* Guess size depending on current relax state. Initially the relax
9130 state will correspond to a short jump and we return 1, because
9131 the variable part of the frag (the branch offset) is one byte
9132 long. However, we can relax a section more than once and in that
9133 case we must either set fr_subtype back to the unrelaxed state,
9134 or return the value for the appropriate branch. */
9135 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9138 /* Called after relax() is finished.
9140 In: Address of frag.
9141 fr_type == rs_machine_dependent.
9142 fr_subtype is what the address relaxed to.
9144 Out: Any fixSs and constants are set up.
9145 Caller will turn frag into a ".space 0". */
9148 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9151 unsigned char *opcode
;
9152 unsigned char *where_to_put_displacement
= NULL
;
9153 offsetT target_address
;
9154 offsetT opcode_address
;
9155 unsigned int extension
= 0;
9156 offsetT displacement_from_opcode_start
;
9158 opcode
= (unsigned char *) fragP
->fr_opcode
;
9160 /* Address we want to reach in file space. */
9161 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9163 /* Address opcode resides at in file space. */
9164 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9166 /* Displacement from opcode start to fill into instruction. */
9167 displacement_from_opcode_start
= target_address
- opcode_address
;
9169 if ((fragP
->fr_subtype
& BIG
) == 0)
9171 /* Don't have to change opcode. */
9172 extension
= 1; /* 1 opcode + 1 displacement */
9173 where_to_put_displacement
= &opcode
[1];
9177 if (no_cond_jump_promotion
9178 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9179 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9180 _("long jump required"));
9182 switch (fragP
->fr_subtype
)
9184 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9185 extension
= 4; /* 1 opcode + 4 displacement */
9187 where_to_put_displacement
= &opcode
[1];
9190 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9191 extension
= 2; /* 1 opcode + 2 displacement */
9193 where_to_put_displacement
= &opcode
[1];
9196 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9197 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9198 extension
= 5; /* 2 opcode + 4 displacement */
9199 opcode
[1] = opcode
[0] + 0x10;
9200 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9201 where_to_put_displacement
= &opcode
[2];
9204 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9205 extension
= 3; /* 2 opcode + 2 displacement */
9206 opcode
[1] = opcode
[0] + 0x10;
9207 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9208 where_to_put_displacement
= &opcode
[2];
9211 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9216 where_to_put_displacement
= &opcode
[3];
9220 BAD_CASE (fragP
->fr_subtype
);
9225 /* If size if less then four we are sure that the operand fits,
9226 but if it's 4, then it could be that the displacement is larger
9228 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9230 && ((addressT
) (displacement_from_opcode_start
- extension
9231 + ((addressT
) 1 << 31))
9232 > (((addressT
) 2 << 31) - 1)))
9234 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9235 _("jump target out of range"));
9236 /* Make us emit 0. */
9237 displacement_from_opcode_start
= extension
;
9239 /* Now put displacement after opcode. */
9240 md_number_to_chars ((char *) where_to_put_displacement
,
9241 (valueT
) (displacement_from_opcode_start
- extension
),
9242 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9243 fragP
->fr_fix
+= extension
;
9246 /* Apply a fixup (fixP) to segment data, once it has been determined
9247 by our caller that we have all the info we need to fix it up.
9249 Parameter valP is the pointer to the value of the bits.
9251 On the 386, immediates, displacements, and data pointers are all in
9252 the same (little-endian) format, so we don't need to care about which
9256 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9258 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9259 valueT value
= *valP
;
9261 #if !defined (TE_Mach)
9264 switch (fixP
->fx_r_type
)
9270 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9273 case BFD_RELOC_X86_64_32S
:
9274 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9277 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9280 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9285 if (fixP
->fx_addsy
!= NULL
9286 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9287 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9288 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9289 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9290 && !use_rela_relocations
)
9292 /* This is a hack. There should be a better way to handle this.
9293 This covers for the fact that bfd_install_relocation will
9294 subtract the current location (for partial_inplace, PC relative
9295 relocations); see more below. */
9299 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9302 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9307 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9310 || (symbol_section_p (fixP
->fx_addsy
)
9311 && sym_seg
!= absolute_section
))
9312 && !generic_force_reloc (fixP
))
9314 /* Yes, we add the values in twice. This is because
9315 bfd_install_relocation subtracts them out again. I think
9316 bfd_install_relocation is broken, but I don't dare change
9318 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9322 #if defined (OBJ_COFF) && defined (TE_PE)
9323 /* For some reason, the PE format does not store a
9324 section address offset for a PC relative symbol. */
9325 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9326 || S_IS_WEAK (fixP
->fx_addsy
))
9327 value
+= md_pcrel_from (fixP
);
9330 #if defined (OBJ_COFF) && defined (TE_PE)
9331 if (fixP
->fx_addsy
!= NULL
9332 && S_IS_WEAK (fixP
->fx_addsy
)
9333 /* PR 16858: Do not modify weak function references. */
9334 && ! fixP
->fx_pcrel
)
9336 #if !defined (TE_PEP)
9337 /* For x86 PE weak function symbols are neither PC-relative
9338 nor do they set S_IS_FUNCTION. So the only reliable way
9339 to detect them is to check the flags of their containing
9341 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9342 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9346 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9350 /* Fix a few things - the dynamic linker expects certain values here,
9351 and we must not disappoint it. */
9352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9353 if (IS_ELF
&& fixP
->fx_addsy
)
9354 switch (fixP
->fx_r_type
)
9356 case BFD_RELOC_386_PLT32
:
9357 case BFD_RELOC_X86_64_PLT32
:
9358 /* Make the jump instruction point to the address of the operand. At
9359 runtime we merely add the offset to the actual PLT entry. */
9363 case BFD_RELOC_386_TLS_GD
:
9364 case BFD_RELOC_386_TLS_LDM
:
9365 case BFD_RELOC_386_TLS_IE_32
:
9366 case BFD_RELOC_386_TLS_IE
:
9367 case BFD_RELOC_386_TLS_GOTIE
:
9368 case BFD_RELOC_386_TLS_GOTDESC
:
9369 case BFD_RELOC_X86_64_TLSGD
:
9370 case BFD_RELOC_X86_64_TLSLD
:
9371 case BFD_RELOC_X86_64_GOTTPOFF
:
9372 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9373 value
= 0; /* Fully resolved at runtime. No addend. */
9375 case BFD_RELOC_386_TLS_LE
:
9376 case BFD_RELOC_386_TLS_LDO_32
:
9377 case BFD_RELOC_386_TLS_LE_32
:
9378 case BFD_RELOC_X86_64_DTPOFF32
:
9379 case BFD_RELOC_X86_64_DTPOFF64
:
9380 case BFD_RELOC_X86_64_TPOFF32
:
9381 case BFD_RELOC_X86_64_TPOFF64
:
9382 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9385 case BFD_RELOC_386_TLS_DESC_CALL
:
9386 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9387 value
= 0; /* Fully resolved at runtime. No addend. */
9388 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9392 case BFD_RELOC_VTABLE_INHERIT
:
9393 case BFD_RELOC_VTABLE_ENTRY
:
9400 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9402 #endif /* !defined (TE_Mach) */
9404 /* Are we finished with this relocation now? */
9405 if (fixP
->fx_addsy
== NULL
)
9407 #if defined (OBJ_COFF) && defined (TE_PE)
9408 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9411 /* Remember value for tc_gen_reloc. */
9412 fixP
->fx_addnumber
= value
;
9413 /* Clear out the frag for now. */
9417 else if (use_rela_relocations
)
9419 fixP
->fx_no_overflow
= 1;
9420 /* Remember value for tc_gen_reloc. */
9421 fixP
->fx_addnumber
= value
;
9425 md_number_to_chars (p
, value
, fixP
->fx_size
);
9429 md_atof (int type
, char *litP
, int *sizeP
)
9431 /* This outputs the LITTLENUMs in REVERSE order;
9432 in accord with the bigendian 386. */
9433 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9436 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9439 output_invalid (int c
)
9442 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9445 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9446 "(0x%x)", (unsigned char) c
);
9447 return output_invalid_buf
;
9450 /* REG_STRING starts *before* REGISTER_PREFIX. */
9452 static const reg_entry
*
9453 parse_real_register (char *reg_string
, char **end_op
)
9455 char *s
= reg_string
;
9457 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9460 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9461 if (*s
== REGISTER_PREFIX
)
9464 if (is_space_char (*s
))
9468 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9470 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9471 return (const reg_entry
*) NULL
;
9475 /* For naked regs, make sure that we are not dealing with an identifier.
9476 This prevents confusing an identifier like `eax_var' with register
9478 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9479 return (const reg_entry
*) NULL
;
9483 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9485 /* Handle floating point regs, allowing spaces in the (i) part. */
9486 if (r
== i386_regtab
/* %st is first entry of table */)
9488 if (is_space_char (*s
))
9493 if (is_space_char (*s
))
9495 if (*s
>= '0' && *s
<= '7')
9499 if (is_space_char (*s
))
9504 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9509 /* We have "%st(" then garbage. */
9510 return (const reg_entry
*) NULL
;
9514 if (r
== NULL
|| allow_pseudo_reg
)
9517 if (operand_type_all_zero (&r
->reg_type
))
9518 return (const reg_entry
*) NULL
;
9520 if ((r
->reg_type
.bitfield
.reg32
9521 || r
->reg_type
.bitfield
.sreg3
9522 || r
->reg_type
.bitfield
.control
9523 || r
->reg_type
.bitfield
.debug
9524 || r
->reg_type
.bitfield
.test
)
9525 && !cpu_arch_flags
.bitfield
.cpui386
)
9526 return (const reg_entry
*) NULL
;
9528 if (r
->reg_type
.bitfield
.floatreg
9529 && !cpu_arch_flags
.bitfield
.cpu8087
9530 && !cpu_arch_flags
.bitfield
.cpu287
9531 && !cpu_arch_flags
.bitfield
.cpu387
)
9532 return (const reg_entry
*) NULL
;
9534 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9535 return (const reg_entry
*) NULL
;
9537 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9538 return (const reg_entry
*) NULL
;
9540 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9541 return (const reg_entry
*) NULL
;
9543 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9544 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9545 return (const reg_entry
*) NULL
;
9547 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9548 if (!allow_index_reg
9549 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9550 return (const reg_entry
*) NULL
;
9552 /* Upper 16 vector register is only available with VREX in 64bit
9554 if ((r
->reg_flags
& RegVRex
))
9556 if (!cpu_arch_flags
.bitfield
.cpuvrex
9557 || flag_code
!= CODE_64BIT
)
9558 return (const reg_entry
*) NULL
;
9563 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9564 || r
->reg_type
.bitfield
.reg64
)
9565 && (!cpu_arch_flags
.bitfield
.cpulm
9566 || !operand_type_equal (&r
->reg_type
, &control
))
9567 && flag_code
!= CODE_64BIT
)
9568 return (const reg_entry
*) NULL
;
9570 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9571 return (const reg_entry
*) NULL
;
9576 /* REG_STRING starts *before* REGISTER_PREFIX. */
9578 static const reg_entry
*
9579 parse_register (char *reg_string
, char **end_op
)
9583 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9584 r
= parse_real_register (reg_string
, end_op
);
9589 char *save
= input_line_pointer
;
9593 input_line_pointer
= reg_string
;
9594 c
= get_symbol_name (®_string
);
9595 symbolP
= symbol_find (reg_string
);
9596 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9598 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9600 know (e
->X_op
== O_register
);
9601 know (e
->X_add_number
>= 0
9602 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9603 r
= i386_regtab
+ e
->X_add_number
;
9604 if ((r
->reg_flags
& RegVRex
))
9606 *end_op
= input_line_pointer
;
9608 *input_line_pointer
= c
;
9609 input_line_pointer
= save
;
9615 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9618 char *end
= input_line_pointer
;
9621 r
= parse_register (name
, &input_line_pointer
);
9622 if (r
&& end
<= input_line_pointer
)
9624 *nextcharP
= *input_line_pointer
;
9625 *input_line_pointer
= 0;
9626 e
->X_op
= O_register
;
9627 e
->X_add_number
= r
- i386_regtab
;
9630 input_line_pointer
= end
;
9632 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9636 md_operand (expressionS
*e
)
9641 switch (*input_line_pointer
)
9643 case REGISTER_PREFIX
:
9644 r
= parse_real_register (input_line_pointer
, &end
);
9647 e
->X_op
= O_register
;
9648 e
->X_add_number
= r
- i386_regtab
;
9649 input_line_pointer
= end
;
9654 gas_assert (intel_syntax
);
9655 end
= input_line_pointer
++;
9657 if (*input_line_pointer
== ']')
9659 ++input_line_pointer
;
9660 e
->X_op_symbol
= make_expr_symbol (e
);
9661 e
->X_add_symbol
= NULL
;
9662 e
->X_add_number
= 0;
9668 input_line_pointer
= end
;
9675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9676 const char *md_shortopts
= "kVQ:sqn";
9678 const char *md_shortopts
= "qn";
9681 #define OPTION_32 (OPTION_MD_BASE + 0)
9682 #define OPTION_64 (OPTION_MD_BASE + 1)
9683 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9684 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9685 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9686 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9687 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9688 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9689 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9690 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9691 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9692 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9693 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9694 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9695 #define OPTION_X32 (OPTION_MD_BASE + 14)
9696 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9697 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9698 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9699 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9700 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9701 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9702 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9703 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9704 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9705 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9706 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9708 struct option md_longopts
[] =
9710 {"32", no_argument
, NULL
, OPTION_32
},
9711 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9712 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9713 {"64", no_argument
, NULL
, OPTION_64
},
9715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9716 {"x32", no_argument
, NULL
, OPTION_X32
},
9717 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9719 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9720 {"march", required_argument
, NULL
, OPTION_MARCH
},
9721 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9722 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9723 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9724 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9725 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9726 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9727 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9728 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9729 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9730 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9731 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9732 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9733 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9734 # if defined (TE_PE) || defined (TE_PEP)
9735 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9737 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9738 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9739 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9740 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9741 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9742 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9743 {NULL
, no_argument
, NULL
, 0}
9745 size_t md_longopts_size
= sizeof (md_longopts
);
9748 md_parse_option (int c
, const char *arg
)
9751 char *arch
, *next
, *saved
;
9756 optimize_align_code
= 0;
9763 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9764 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9765 should be emitted or not. FIXME: Not implemented. */
9769 /* -V: SVR4 argument to print version ID. */
9771 print_version_id ();
9774 /* -k: Ignore for FreeBSD compatibility. */
9779 /* -s: On i386 Solaris, this tells the native assembler to use
9780 .stab instead of .stab.excl. We always use .stab anyhow. */
9783 case OPTION_MSHARED
:
9787 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9788 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9791 const char **list
, **l
;
9793 list
= bfd_target_list ();
9794 for (l
= list
; *l
!= NULL
; l
++)
9795 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9796 || strcmp (*l
, "coff-x86-64") == 0
9797 || strcmp (*l
, "pe-x86-64") == 0
9798 || strcmp (*l
, "pei-x86-64") == 0
9799 || strcmp (*l
, "mach-o-x86-64") == 0)
9801 default_arch
= "x86_64";
9805 as_fatal (_("no compiled in support for x86_64"));
9811 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9815 const char **list
, **l
;
9817 list
= bfd_target_list ();
9818 for (l
= list
; *l
!= NULL
; l
++)
9819 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9821 default_arch
= "x86_64:32";
9825 as_fatal (_("no compiled in support for 32bit x86_64"));
9829 as_fatal (_("32bit x86_64 is only supported for ELF"));
9834 default_arch
= "i386";
9838 #ifdef SVR4_COMMENT_CHARS
9843 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9845 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9849 i386_comment_chars
= n
;
9855 saved
= xstrdup (arg
);
9857 /* Allow -march=+nosse. */
9863 as_fatal (_("invalid -march= option: `%s'"), arg
);
9864 next
= strchr (arch
, '+');
9867 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9869 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9872 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9875 cpu_arch_name
= cpu_arch
[j
].name
;
9876 cpu_sub_arch_name
= NULL
;
9877 cpu_arch_flags
= cpu_arch
[j
].flags
;
9878 cpu_arch_isa
= cpu_arch
[j
].type
;
9879 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9880 if (!cpu_arch_tune_set
)
9882 cpu_arch_tune
= cpu_arch_isa
;
9883 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9887 else if (*cpu_arch
[j
].name
== '.'
9888 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9890 /* ISA entension. */
9891 i386_cpu_flags flags
;
9893 flags
= cpu_flags_or (cpu_arch_flags
,
9896 if (!valid_iamcu_cpu_flags (&flags
))
9897 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9898 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9900 if (cpu_sub_arch_name
)
9902 char *name
= cpu_sub_arch_name
;
9903 cpu_sub_arch_name
= concat (name
,
9905 (const char *) NULL
);
9909 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9910 cpu_arch_flags
= flags
;
9911 cpu_arch_isa_flags
= flags
;
9917 if (j
>= ARRAY_SIZE (cpu_arch
))
9919 /* Disable an ISA entension. */
9920 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9921 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9923 i386_cpu_flags flags
;
9925 flags
= cpu_flags_and_not (cpu_arch_flags
,
9926 cpu_noarch
[j
].flags
);
9927 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9929 if (cpu_sub_arch_name
)
9931 char *name
= cpu_sub_arch_name
;
9932 cpu_sub_arch_name
= concat (arch
,
9933 (const char *) NULL
);
9937 cpu_sub_arch_name
= xstrdup (arch
);
9938 cpu_arch_flags
= flags
;
9939 cpu_arch_isa_flags
= flags
;
9944 if (j
>= ARRAY_SIZE (cpu_noarch
))
9945 j
= ARRAY_SIZE (cpu_arch
);
9948 if (j
>= ARRAY_SIZE (cpu_arch
))
9949 as_fatal (_("invalid -march= option: `%s'"), arg
);
9953 while (next
!= NULL
);
9959 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9960 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9962 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9964 cpu_arch_tune_set
= 1;
9965 cpu_arch_tune
= cpu_arch
[j
].type
;
9966 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9970 if (j
>= ARRAY_SIZE (cpu_arch
))
9971 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9974 case OPTION_MMNEMONIC
:
9975 if (strcasecmp (arg
, "att") == 0)
9977 else if (strcasecmp (arg
, "intel") == 0)
9980 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9983 case OPTION_MSYNTAX
:
9984 if (strcasecmp (arg
, "att") == 0)
9986 else if (strcasecmp (arg
, "intel") == 0)
9989 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9992 case OPTION_MINDEX_REG
:
9993 allow_index_reg
= 1;
9996 case OPTION_MNAKED_REG
:
9997 allow_naked_reg
= 1;
10000 case OPTION_MOLD_GCC
:
10004 case OPTION_MSSE2AVX
:
10008 case OPTION_MSSE_CHECK
:
10009 if (strcasecmp (arg
, "error") == 0)
10010 sse_check
= check_error
;
10011 else if (strcasecmp (arg
, "warning") == 0)
10012 sse_check
= check_warning
;
10013 else if (strcasecmp (arg
, "none") == 0)
10014 sse_check
= check_none
;
10016 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10019 case OPTION_MOPERAND_CHECK
:
10020 if (strcasecmp (arg
, "error") == 0)
10021 operand_check
= check_error
;
10022 else if (strcasecmp (arg
, "warning") == 0)
10023 operand_check
= check_warning
;
10024 else if (strcasecmp (arg
, "none") == 0)
10025 operand_check
= check_none
;
10027 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10030 case OPTION_MAVXSCALAR
:
10031 if (strcasecmp (arg
, "128") == 0)
10032 avxscalar
= vex128
;
10033 else if (strcasecmp (arg
, "256") == 0)
10034 avxscalar
= vex256
;
10036 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10039 case OPTION_MADD_BND_PREFIX
:
10040 add_bnd_prefix
= 1;
10043 case OPTION_MEVEXLIG
:
10044 if (strcmp (arg
, "128") == 0)
10045 evexlig
= evexl128
;
10046 else if (strcmp (arg
, "256") == 0)
10047 evexlig
= evexl256
;
10048 else if (strcmp (arg
, "512") == 0)
10049 evexlig
= evexl512
;
10051 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10054 case OPTION_MEVEXRCIG
:
10055 if (strcmp (arg
, "rne") == 0)
10057 else if (strcmp (arg
, "rd") == 0)
10059 else if (strcmp (arg
, "ru") == 0)
10061 else if (strcmp (arg
, "rz") == 0)
10064 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10067 case OPTION_MEVEXWIG
:
10068 if (strcmp (arg
, "0") == 0)
10070 else if (strcmp (arg
, "1") == 0)
10073 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10076 # if defined (TE_PE) || defined (TE_PEP)
10077 case OPTION_MBIG_OBJ
:
10082 case OPTION_MOMIT_LOCK_PREFIX
:
10083 if (strcasecmp (arg
, "yes") == 0)
10084 omit_lock_prefix
= 1;
10085 else if (strcasecmp (arg
, "no") == 0)
10086 omit_lock_prefix
= 0;
10088 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10091 case OPTION_MFENCE_AS_LOCK_ADD
:
10092 if (strcasecmp (arg
, "yes") == 0)
10094 else if (strcasecmp (arg
, "no") == 0)
10097 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10100 case OPTION_MRELAX_RELOCATIONS
:
10101 if (strcasecmp (arg
, "yes") == 0)
10102 generate_relax_relocations
= 1;
10103 else if (strcasecmp (arg
, "no") == 0)
10104 generate_relax_relocations
= 0;
10106 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10109 case OPTION_MAMD64
:
10110 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10111 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10112 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10113 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10116 case OPTION_MINTEL64
:
10117 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10118 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10119 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10120 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10129 #define MESSAGE_TEMPLATE \
10133 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10134 int *left_p
, const char *name
, int len
)
10136 int size
= sizeof (MESSAGE_TEMPLATE
);
10137 int left
= *left_p
;
10139 /* Reserve 2 spaces for ", " or ",\0" */
10142 /* Check if there is any room. */
10150 p
= mempcpy (p
, name
, len
);
10154 /* Output the current message now and start a new one. */
10157 fprintf (stream
, "%s\n", message
);
10159 left
= size
- (start
- message
) - len
- 2;
10161 gas_assert (left
>= 0);
10163 p
= mempcpy (p
, name
, len
);
10171 show_arch (FILE *stream
, int ext
, int check
)
10173 static char message
[] = MESSAGE_TEMPLATE
;
10174 char *start
= message
+ 27;
10176 int size
= sizeof (MESSAGE_TEMPLATE
);
10183 left
= size
- (start
- message
);
10184 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10186 /* Should it be skipped? */
10187 if (cpu_arch
[j
].skip
)
10190 name
= cpu_arch
[j
].name
;
10191 len
= cpu_arch
[j
].len
;
10194 /* It is an extension. Skip if we aren't asked to show it. */
10205 /* It is an processor. Skip if we show only extension. */
10208 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10210 /* It is an impossible processor - skip. */
10214 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10217 /* Display disabled extensions. */
10219 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10221 name
= cpu_noarch
[j
].name
;
10222 len
= cpu_noarch
[j
].len
;
10223 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10228 fprintf (stream
, "%s\n", message
);
10232 md_show_usage (FILE *stream
)
10234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10235 fprintf (stream
, _("\
10237 -V print assembler version number\n\
10240 fprintf (stream
, _("\
10241 -n Do not optimize code alignment\n\
10242 -q quieten some warnings\n"));
10243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10244 fprintf (stream
, _("\
10247 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10248 || defined (TE_PE) || defined (TE_PEP))
10249 fprintf (stream
, _("\
10250 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10252 #ifdef SVR4_COMMENT_CHARS
10253 fprintf (stream
, _("\
10254 --divide do not treat `/' as a comment character\n"));
10256 fprintf (stream
, _("\
10257 --divide ignored\n"));
10259 fprintf (stream
, _("\
10260 -march=CPU[,+EXTENSION...]\n\
10261 generate code for CPU and EXTENSION, CPU is one of:\n"));
10262 show_arch (stream
, 0, 1);
10263 fprintf (stream
, _("\
10264 EXTENSION is combination of:\n"));
10265 show_arch (stream
, 1, 0);
10266 fprintf (stream
, _("\
10267 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10268 show_arch (stream
, 0, 0);
10269 fprintf (stream
, _("\
10270 -msse2avx encode SSE instructions with VEX prefix\n"));
10271 fprintf (stream
, _("\
10272 -msse-check=[none|error|warning]\n\
10273 check SSE instructions\n"));
10274 fprintf (stream
, _("\
10275 -moperand-check=[none|error|warning]\n\
10276 check operand combinations for validity\n"));
10277 fprintf (stream
, _("\
10278 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10280 fprintf (stream
, _("\
10281 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10283 fprintf (stream
, _("\
10284 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10285 for EVEX.W bit ignored instructions\n"));
10286 fprintf (stream
, _("\
10287 -mevexrcig=[rne|rd|ru|rz]\n\
10288 encode EVEX instructions with specific EVEX.RC value\n\
10289 for SAE-only ignored instructions\n"));
10290 fprintf (stream
, _("\
10291 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10292 fprintf (stream
, _("\
10293 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10294 fprintf (stream
, _("\
10295 -mindex-reg support pseudo index registers\n"));
10296 fprintf (stream
, _("\
10297 -mnaked-reg don't require `%%' prefix for registers\n"));
10298 fprintf (stream
, _("\
10299 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10300 fprintf (stream
, _("\
10301 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10302 fprintf (stream
, _("\
10303 -mshared disable branch optimization for shared code\n"));
10304 # if defined (TE_PE) || defined (TE_PEP)
10305 fprintf (stream
, _("\
10306 -mbig-obj generate big object files\n"));
10308 fprintf (stream
, _("\
10309 -momit-lock-prefix=[no|yes]\n\
10310 strip all lock prefixes\n"));
10311 fprintf (stream
, _("\
10312 -mfence-as-lock-add=[no|yes]\n\
10313 encode lfence, mfence and sfence as\n\
10314 lock addl $0x0, (%%{re}sp)\n"));
10315 fprintf (stream
, _("\
10316 -mrelax-relocations=[no|yes]\n\
10317 generate relax relocations\n"));
10318 fprintf (stream
, _("\
10319 -mamd64 accept only AMD64 ISA\n"));
10320 fprintf (stream
, _("\
10321 -mintel64 accept only Intel64 ISA\n"));
10324 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10325 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10326 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10328 /* Pick the target format to use. */
10331 i386_target_format (void)
10333 if (!strncmp (default_arch
, "x86_64", 6))
10335 update_code_flag (CODE_64BIT
, 1);
10336 if (default_arch
[6] == '\0')
10337 x86_elf_abi
= X86_64_ABI
;
10339 x86_elf_abi
= X86_64_X32_ABI
;
10341 else if (!strcmp (default_arch
, "i386"))
10342 update_code_flag (CODE_32BIT
, 1);
10343 else if (!strcmp (default_arch
, "iamcu"))
10345 update_code_flag (CODE_32BIT
, 1);
10346 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10348 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10349 cpu_arch_name
= "iamcu";
10350 cpu_sub_arch_name
= NULL
;
10351 cpu_arch_flags
= iamcu_flags
;
10352 cpu_arch_isa
= PROCESSOR_IAMCU
;
10353 cpu_arch_isa_flags
= iamcu_flags
;
10354 if (!cpu_arch_tune_set
)
10356 cpu_arch_tune
= cpu_arch_isa
;
10357 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10361 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10365 as_fatal (_("unknown architecture"));
10367 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10368 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10369 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10370 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10372 switch (OUTPUT_FLAVOR
)
10374 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10375 case bfd_target_aout_flavour
:
10376 return AOUT_TARGET_FORMAT
;
10378 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10379 # if defined (TE_PE) || defined (TE_PEP)
10380 case bfd_target_coff_flavour
:
10381 if (flag_code
== CODE_64BIT
)
10382 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10385 # elif defined (TE_GO32)
10386 case bfd_target_coff_flavour
:
10387 return "coff-go32";
10389 case bfd_target_coff_flavour
:
10390 return "coff-i386";
10393 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10394 case bfd_target_elf_flavour
:
10396 const char *format
;
10398 switch (x86_elf_abi
)
10401 format
= ELF_TARGET_FORMAT
;
10404 use_rela_relocations
= 1;
10406 format
= ELF_TARGET_FORMAT64
;
10408 case X86_64_X32_ABI
:
10409 use_rela_relocations
= 1;
10411 disallow_64bit_reloc
= 1;
10412 format
= ELF_TARGET_FORMAT32
;
10415 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10417 if (x86_elf_abi
!= X86_64_ABI
)
10418 as_fatal (_("Intel L1OM is 64bit only"));
10419 return ELF_TARGET_L1OM_FORMAT
;
10421 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10423 if (x86_elf_abi
!= X86_64_ABI
)
10424 as_fatal (_("Intel K1OM is 64bit only"));
10425 return ELF_TARGET_K1OM_FORMAT
;
10427 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10429 if (x86_elf_abi
!= I386_ABI
)
10430 as_fatal (_("Intel MCU is 32bit only"));
10431 return ELF_TARGET_IAMCU_FORMAT
;
10437 #if defined (OBJ_MACH_O)
10438 case bfd_target_mach_o_flavour
:
10439 if (flag_code
== CODE_64BIT
)
10441 use_rela_relocations
= 1;
10443 return "mach-o-x86-64";
10446 return "mach-o-i386";
10454 #endif /* OBJ_MAYBE_ more than one */
10457 md_undefined_symbol (char *name
)
10459 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10460 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10461 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10462 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10466 if (symbol_find (name
))
10467 as_bad (_("GOT already in symbol table"));
10468 GOT_symbol
= symbol_new (name
, undefined_section
,
10469 (valueT
) 0, &zero_address_frag
);
10476 /* Round up a section size to the appropriate boundary. */
10479 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10481 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10482 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10484 /* For a.out, force the section size to be aligned. If we don't do
10485 this, BFD will align it for us, but it will not write out the
10486 final bytes of the section. This may be a bug in BFD, but it is
10487 easier to fix it here since that is how the other a.out targets
10491 align
= bfd_get_section_alignment (stdoutput
, segment
);
10492 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10499 /* On the i386, PC-relative offsets are relative to the start of the
10500 next instruction. That is, the address of the offset, plus its
10501 size, since the offset is always the last part of the insn. */
10504 md_pcrel_from (fixS
*fixP
)
10506 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10512 s_bss (int ignore ATTRIBUTE_UNUSED
)
10516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10518 obj_elf_section_change_hook ();
10520 temp
= get_absolute_expression ();
10521 subseg_set (bss_section
, (subsegT
) temp
);
10522 demand_empty_rest_of_line ();
10528 i386_validate_fix (fixS
*fixp
)
10530 if (fixp
->fx_subsy
)
10532 if (fixp
->fx_subsy
== GOT_symbol
)
10534 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10539 if (fixp
->fx_tcbit2
)
10540 fixp
->fx_r_type
= (fixp
->fx_tcbit
10541 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10542 : BFD_RELOC_X86_64_GOTPCRELX
);
10545 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10550 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10552 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10554 fixp
->fx_subsy
= 0;
10557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10558 else if (!object_64bit
)
10560 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10561 && fixp
->fx_tcbit2
)
10562 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10568 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10571 bfd_reloc_code_real_type code
;
10573 switch (fixp
->fx_r_type
)
10575 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10576 case BFD_RELOC_SIZE32
:
10577 case BFD_RELOC_SIZE64
:
10578 if (S_IS_DEFINED (fixp
->fx_addsy
)
10579 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10581 /* Resolve size relocation against local symbol to size of
10582 the symbol plus addend. */
10583 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10584 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10585 && !fits_in_unsigned_long (value
))
10586 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10587 _("symbol size computation overflow"));
10588 fixp
->fx_addsy
= NULL
;
10589 fixp
->fx_subsy
= NULL
;
10590 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10595 case BFD_RELOC_X86_64_PLT32
:
10596 case BFD_RELOC_X86_64_GOT32
:
10597 case BFD_RELOC_X86_64_GOTPCREL
:
10598 case BFD_RELOC_X86_64_GOTPCRELX
:
10599 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10600 case BFD_RELOC_386_PLT32
:
10601 case BFD_RELOC_386_GOT32
:
10602 case BFD_RELOC_386_GOT32X
:
10603 case BFD_RELOC_386_GOTOFF
:
10604 case BFD_RELOC_386_GOTPC
:
10605 case BFD_RELOC_386_TLS_GD
:
10606 case BFD_RELOC_386_TLS_LDM
:
10607 case BFD_RELOC_386_TLS_LDO_32
:
10608 case BFD_RELOC_386_TLS_IE_32
:
10609 case BFD_RELOC_386_TLS_IE
:
10610 case BFD_RELOC_386_TLS_GOTIE
:
10611 case BFD_RELOC_386_TLS_LE_32
:
10612 case BFD_RELOC_386_TLS_LE
:
10613 case BFD_RELOC_386_TLS_GOTDESC
:
10614 case BFD_RELOC_386_TLS_DESC_CALL
:
10615 case BFD_RELOC_X86_64_TLSGD
:
10616 case BFD_RELOC_X86_64_TLSLD
:
10617 case BFD_RELOC_X86_64_DTPOFF32
:
10618 case BFD_RELOC_X86_64_DTPOFF64
:
10619 case BFD_RELOC_X86_64_GOTTPOFF
:
10620 case BFD_RELOC_X86_64_TPOFF32
:
10621 case BFD_RELOC_X86_64_TPOFF64
:
10622 case BFD_RELOC_X86_64_GOTOFF64
:
10623 case BFD_RELOC_X86_64_GOTPC32
:
10624 case BFD_RELOC_X86_64_GOT64
:
10625 case BFD_RELOC_X86_64_GOTPCREL64
:
10626 case BFD_RELOC_X86_64_GOTPC64
:
10627 case BFD_RELOC_X86_64_GOTPLT64
:
10628 case BFD_RELOC_X86_64_PLTOFF64
:
10629 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10630 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10631 case BFD_RELOC_RVA
:
10632 case BFD_RELOC_VTABLE_ENTRY
:
10633 case BFD_RELOC_VTABLE_INHERIT
:
10635 case BFD_RELOC_32_SECREL
:
10637 code
= fixp
->fx_r_type
;
10639 case BFD_RELOC_X86_64_32S
:
10640 if (!fixp
->fx_pcrel
)
10642 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10643 code
= fixp
->fx_r_type
;
10647 if (fixp
->fx_pcrel
)
10649 switch (fixp
->fx_size
)
10652 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10653 _("can not do %d byte pc-relative relocation"),
10655 code
= BFD_RELOC_32_PCREL
;
10657 case 1: code
= BFD_RELOC_8_PCREL
; break;
10658 case 2: code
= BFD_RELOC_16_PCREL
; break;
10659 case 4: code
= BFD_RELOC_32_PCREL
; break;
10661 case 8: code
= BFD_RELOC_64_PCREL
; break;
10667 switch (fixp
->fx_size
)
10670 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10671 _("can not do %d byte relocation"),
10673 code
= BFD_RELOC_32
;
10675 case 1: code
= BFD_RELOC_8
; break;
10676 case 2: code
= BFD_RELOC_16
; break;
10677 case 4: code
= BFD_RELOC_32
; break;
10679 case 8: code
= BFD_RELOC_64
; break;
10686 if ((code
== BFD_RELOC_32
10687 || code
== BFD_RELOC_32_PCREL
10688 || code
== BFD_RELOC_X86_64_32S
)
10690 && fixp
->fx_addsy
== GOT_symbol
)
10693 code
= BFD_RELOC_386_GOTPC
;
10695 code
= BFD_RELOC_X86_64_GOTPC32
;
10697 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10699 && fixp
->fx_addsy
== GOT_symbol
)
10701 code
= BFD_RELOC_X86_64_GOTPC64
;
10704 rel
= XNEW (arelent
);
10705 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10706 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10708 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10710 if (!use_rela_relocations
)
10712 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10713 vtable entry to be used in the relocation's section offset. */
10714 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10715 rel
->address
= fixp
->fx_offset
;
10716 #if defined (OBJ_COFF) && defined (TE_PE)
10717 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10718 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10723 /* Use the rela in 64bit mode. */
10726 if (disallow_64bit_reloc
)
10729 case BFD_RELOC_X86_64_DTPOFF64
:
10730 case BFD_RELOC_X86_64_TPOFF64
:
10731 case BFD_RELOC_64_PCREL
:
10732 case BFD_RELOC_X86_64_GOTOFF64
:
10733 case BFD_RELOC_X86_64_GOT64
:
10734 case BFD_RELOC_X86_64_GOTPCREL64
:
10735 case BFD_RELOC_X86_64_GOTPC64
:
10736 case BFD_RELOC_X86_64_GOTPLT64
:
10737 case BFD_RELOC_X86_64_PLTOFF64
:
10738 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10739 _("cannot represent relocation type %s in x32 mode"),
10740 bfd_get_reloc_code_name (code
));
10746 if (!fixp
->fx_pcrel
)
10747 rel
->addend
= fixp
->fx_offset
;
10751 case BFD_RELOC_X86_64_PLT32
:
10752 case BFD_RELOC_X86_64_GOT32
:
10753 case BFD_RELOC_X86_64_GOTPCREL
:
10754 case BFD_RELOC_X86_64_GOTPCRELX
:
10755 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10756 case BFD_RELOC_X86_64_TLSGD
:
10757 case BFD_RELOC_X86_64_TLSLD
:
10758 case BFD_RELOC_X86_64_GOTTPOFF
:
10759 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10760 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10761 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10764 rel
->addend
= (section
->vma
10766 + fixp
->fx_addnumber
10767 + md_pcrel_from (fixp
));
10772 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10773 if (rel
->howto
== NULL
)
10775 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10776 _("cannot represent relocation type %s"),
10777 bfd_get_reloc_code_name (code
));
10778 /* Set howto to a garbage value so that we can keep going. */
10779 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10780 gas_assert (rel
->howto
!= NULL
);
10786 #include "tc-i386-intel.c"
10789 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10791 int saved_naked_reg
;
10792 char saved_register_dot
;
10794 saved_naked_reg
= allow_naked_reg
;
10795 allow_naked_reg
= 1;
10796 saved_register_dot
= register_chars
['.'];
10797 register_chars
['.'] = '.';
10798 allow_pseudo_reg
= 1;
10799 expression_and_evaluate (exp
);
10800 allow_pseudo_reg
= 0;
10801 register_chars
['.'] = saved_register_dot
;
10802 allow_naked_reg
= saved_naked_reg
;
10804 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10806 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10808 exp
->X_op
= O_constant
;
10809 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10810 .dw2_regnum
[flag_code
>> 1];
10813 exp
->X_op
= O_illegal
;
10818 tc_x86_frame_initial_instructions (void)
10820 static unsigned int sp_regno
[2];
10822 if (!sp_regno
[flag_code
>> 1])
10824 char *saved_input
= input_line_pointer
;
10825 char sp
[][4] = {"esp", "rsp"};
10828 input_line_pointer
= sp
[flag_code
>> 1];
10829 tc_x86_parse_to_dw2regnum (&exp
);
10830 gas_assert (exp
.X_op
== O_constant
);
10831 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10832 input_line_pointer
= saved_input
;
10835 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10836 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10840 x86_dwarf2_addr_size (void)
10842 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10843 if (x86_elf_abi
== X86_64_X32_ABI
)
10846 return bfd_arch_bits_per_address (stdoutput
) / 8;
10850 i386_elf_section_type (const char *str
, size_t len
)
10852 if (flag_code
== CODE_64BIT
10853 && len
== sizeof ("unwind") - 1
10854 && strncmp (str
, "unwind", 6) == 0)
10855 return SHT_X86_64_UNWIND
;
10862 i386_solaris_fix_up_eh_frame (segT sec
)
10864 if (flag_code
== CODE_64BIT
)
10865 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10871 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10875 exp
.X_op
= O_secrel
;
10876 exp
.X_add_symbol
= symbol
;
10877 exp
.X_add_number
= 0;
10878 emit_expr (&exp
, size
);
10882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10886 x86_64_section_letter (int letter
, const char **ptr_msg
)
10888 if (flag_code
== CODE_64BIT
)
10891 return SHF_X86_64_LARGE
;
10893 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10896 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10901 x86_64_section_word (char *str
, size_t len
)
10903 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10904 return SHF_X86_64_LARGE
;
10910 handle_large_common (int small ATTRIBUTE_UNUSED
)
10912 if (flag_code
!= CODE_64BIT
)
10914 s_comm_internal (0, elf_common_parse
);
10915 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10919 static segT lbss_section
;
10920 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10921 asection
*saved_bss_section
= bss_section
;
10923 if (lbss_section
== NULL
)
10925 flagword applicable
;
10926 segT seg
= now_seg
;
10927 subsegT subseg
= now_subseg
;
10929 /* The .lbss section is for local .largecomm symbols. */
10930 lbss_section
= subseg_new (".lbss", 0);
10931 applicable
= bfd_applicable_section_flags (stdoutput
);
10932 bfd_set_section_flags (stdoutput
, lbss_section
,
10933 applicable
& SEC_ALLOC
);
10934 seg_info (lbss_section
)->bss
= 1;
10936 subseg_set (seg
, subseg
);
10939 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10940 bss_section
= lbss_section
;
10942 s_comm_internal (0, elf_common_parse
);
10944 elf_com_section_ptr
= saved_com_section_ptr
;
10945 bss_section
= saved_bss_section
;
10948 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */