1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
53 #define RELOC_ENUM enum bfd_reloc_code_real
55 #define RELOC_ENUM int
59 #define DEFAULT_ARCH "i386"
64 #define INLINE __inline__
70 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
71 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
73 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
75 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
76 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
77 static int smallest_imm_type
PARAMS ((offsetT
));
78 static offsetT offset_in_range
PARAMS ((offsetT
, int));
79 static int add_prefix
PARAMS ((unsigned int));
80 static void set_code_flag
PARAMS ((int));
81 static void set_16bit_gcc_code_flag
PARAMS ((int));
82 static void set_intel_syntax
PARAMS ((int));
83 static void set_cpu_arch
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void optimize_imm
PARAMS ((void));
93 static void optimize_disp
PARAMS ((void));
94 static int match_template
PARAMS ((void));
95 static int check_string
PARAMS ((void));
96 static int process_suffix
PARAMS ((void));
97 static int check_byte_reg
PARAMS ((void));
98 static int check_long_reg
PARAMS ((void));
99 static int check_qword_reg
PARAMS ((void));
100 static int check_word_reg
PARAMS ((void));
101 static int finalize_imm
PARAMS ((void));
102 static int process_operands
PARAMS ((void));
103 static const seg_entry
*build_modrm_byte
PARAMS ((void));
104 static void output_insn
PARAMS ((void));
105 static void output_branch
PARAMS ((void));
106 static void output_jump
PARAMS ((void));
107 static void output_interseg_jump
PARAMS ((void));
108 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
110 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
111 offsetT insn_start_off
));
113 static void s_bss
PARAMS ((int));
116 static const char *default_arch
= DEFAULT_ARCH
;
118 /* 'md_assemble ()' gathers together information and puts it into a
125 const reg_entry
*regs
;
130 /* TM holds the template for the insn were currently assembling. */
133 /* SUFFIX holds the instruction mnemonic suffix if given.
134 (e.g. 'l' for 'movl') */
137 /* OPERANDS gives the number of given operands. */
138 unsigned int operands
;
140 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
141 of given register, displacement, memory operands and immediate
143 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
145 /* TYPES [i] is the type (see above #defines) which tells us how to
146 use OP[i] for the corresponding operand. */
147 unsigned int types
[MAX_OPERANDS
];
149 /* Displacement expression, immediate expression, or register for each
151 union i386_op op
[MAX_OPERANDS
];
153 /* Flags for operands. */
154 unsigned int flags
[MAX_OPERANDS
];
155 #define Operand_PCrel 1
157 /* Relocation type for operand */
158 RELOC_ENUM reloc
[MAX_OPERANDS
];
160 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
161 the base index byte below. */
162 const reg_entry
*base_reg
;
163 const reg_entry
*index_reg
;
164 unsigned int log2_scale_factor
;
166 /* SEG gives the seg_entries of this insn. They are zero unless
167 explicit segment overrides are given. */
168 const seg_entry
*seg
[2];
170 /* PREFIX holds all the given prefix opcodes (usually null).
171 PREFIXES is the number of prefix opcodes. */
172 unsigned int prefixes
;
173 unsigned char prefix
[MAX_PREFIXES
];
175 /* RM and SIB are the modrm byte and the sib byte where the
176 addressing modes of this insn are encoded. */
183 typedef struct _i386_insn i386_insn
;
185 /* List of chars besides those in app.c:symbol_chars that can start an
186 operand. Used to prevent the scrubber eating vital white-space. */
188 const char extra_symbol_chars
[] = "*%-(@[";
190 const char extra_symbol_chars
[] = "*%-([";
193 #if (defined (TE_I386AIX) \
194 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
195 && !defined (TE_LINUX) \
196 && !defined (TE_FreeBSD) \
197 && !defined (TE_NetBSD)))
198 /* This array holds the chars that always start a comment. If the
199 pre-processor is disabled, these aren't very useful. */
200 const char comment_chars
[] = "#/";
201 #define PREFIX_SEPARATOR '\\'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars
[] = "#";
214 /* Putting '/' here makes it impossible to use the divide operator.
215 However, we need it for compatibility with SVR4 systems. */
216 const char comment_chars
[] = "#";
217 #define PREFIX_SEPARATOR '/'
219 const char line_comment_chars
[] = "/#";
222 const char line_separator_chars
[] = ";";
224 /* Chars that can be used to separate mant from exp in floating point
226 const char EXP_CHARS
[] = "eE";
228 /* Chars that mean this number is a floating point constant
231 const char FLT_CHARS
[] = "fFdDxX";
233 /* Tables for lexical analysis. */
234 static char mnemonic_chars
[256];
235 static char register_chars
[256];
236 static char operand_chars
[256];
237 static char identifier_chars
[256];
238 static char digit_chars
[256];
240 /* Lexical macros. */
241 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
242 #define is_operand_char(x) (operand_chars[(unsigned char) x])
243 #define is_register_char(x) (register_chars[(unsigned char) x])
244 #define is_space_char(x) ((x) == ' ')
245 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
246 #define is_digit_char(x) (digit_chars[(unsigned char) x])
248 /* All non-digit non-letter charcters that may occur in an operand. */
249 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
251 /* md_assemble() always leaves the strings it's passed unaltered. To
252 effect this we maintain a stack of saved characters that we've smashed
253 with '\0's (indicating end of strings for various sub-fields of the
254 assembler instruction). */
255 static char save_stack
[32];
256 static char *save_stack_p
;
257 #define END_STRING_AND_SAVE(s) \
258 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
259 #define RESTORE_END_STRING(s) \
260 do { *(s) = *--save_stack_p; } while (0)
262 /* The instruction we're assembling. */
265 /* Possible templates for current insn. */
266 static const templates
*current_templates
;
268 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
269 static expressionS disp_expressions
[2], im_expressions
[2];
271 /* Current operand we are working on. */
272 static int this_operand
;
274 /* We support four different modes. FLAG_CODE variable is used to distinguish
281 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
283 static enum flag_code flag_code
;
284 static int use_rela_relocations
= 0;
286 /* The names used to print error messages. */
287 static const char *flag_code_names
[] =
294 /* 1 for intel syntax,
296 static int intel_syntax
= 0;
298 /* 1 if register prefix % not required. */
299 static int allow_naked_reg
= 0;
301 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
302 leave, push, and pop instructions so that gcc has the same stack
303 frame as in 32 bit mode. */
304 static char stackop_size
= '\0';
306 /* Non-zero to quieten some warnings. */
307 static int quiet_warnings
= 0;
310 static const char *cpu_arch_name
= NULL
;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
315 /* If set, conditional jumps are not automatically promoted to handle
316 larger than a byte offset. */
317 static unsigned int no_cond_jump_promotion
= 0;
319 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
322 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
323 unsigned int x86_dwarf2_return_column
;
325 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
326 int x86_cie_data_alignment
;
328 /* Interface to relax_segment.
329 There are 3 major relax states for 386 jump insns because the
330 different types of jumps add different sizes to frags when we're
331 figuring out what sort of jump to choose to reach a given label. */
334 #define UNCOND_JUMP 0
336 #define COND_JUMP86 2
341 #define SMALL16 (SMALL | CODE16)
343 #define BIG16 (BIG | CODE16)
347 #define INLINE __inline__
353 #define ENCODE_RELAX_STATE(type, size) \
354 ((relax_substateT) (((type) << 2) | (size)))
355 #define TYPE_FROM_RELAX_STATE(s) \
357 #define DISP_SIZE_FROM_RELAX_STATE(s) \
358 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
360 /* This table is used by relax_frag to promote short jumps to long
361 ones where necessary. SMALL (short) jumps may be promoted to BIG
362 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
363 don't allow a short jump in a 32 bit code segment to be promoted to
364 a 16 bit offset jump because it's slower (requires data size
365 prefix), and doesn't work, unless the destination is in the bottom
366 64k of the code segment (The top 16 bits of eip are zeroed). */
368 const relax_typeS md_relax_table
[] =
371 1) most positive reach of this state,
372 2) most negative reach of this state,
373 3) how many bytes this mode will have in the variable part of the frag
374 4) which index into the table to try if we can't fit into this one. */
376 /* UNCOND_JUMP states. */
377 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
379 /* dword jmp adds 4 bytes to frag:
380 0 extra opcode bytes, 4 displacement bytes. */
382 /* word jmp adds 2 byte2 to frag:
383 0 extra opcode bytes, 2 displacement bytes. */
386 /* COND_JUMP states. */
387 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
389 /* dword conditionals adds 5 bytes to frag:
390 1 extra opcode byte, 4 displacement bytes. */
392 /* word conditionals add 3 bytes to frag:
393 1 extra opcode byte, 2 displacement bytes. */
396 /* COND_JUMP86 states. */
397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
399 /* dword conditionals adds 5 bytes to frag:
400 1 extra opcode byte, 4 displacement bytes. */
402 /* word conditionals add 4 bytes to frag:
403 1 displacement byte and a 3 byte long branch insn. */
407 static const arch_entry cpu_arch
[] = {
409 {"i186", Cpu086
|Cpu186
},
410 {"i286", Cpu086
|Cpu186
|Cpu286
},
411 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
412 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
413 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
414 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
415 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
416 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
417 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
418 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
419 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
420 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
424 const pseudo_typeS md_pseudo_table
[] =
426 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
427 {"align", s_align_bytes
, 0},
429 {"align", s_align_ptwo
, 0},
431 {"arch", set_cpu_arch
, 0},
435 {"ffloat", float_cons
, 'f'},
436 {"dfloat", float_cons
, 'd'},
437 {"tfloat", float_cons
, 'x'},
439 {"noopt", s_ignore
, 0},
440 {"optim", s_ignore
, 0},
441 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
442 {"code16", set_code_flag
, CODE_16BIT
},
443 {"code32", set_code_flag
, CODE_32BIT
},
444 {"code64", set_code_flag
, CODE_64BIT
},
445 {"intel_syntax", set_intel_syntax
, 1},
446 {"att_syntax", set_intel_syntax
, 0},
447 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
448 {"loc", dwarf2_directive_loc
, 0},
452 /* For interface with expression (). */
453 extern char *input_line_pointer
;
455 /* Hash table for instruction mnemonic lookup. */
456 static struct hash_control
*op_hash
;
458 /* Hash table for register lookup. */
459 static struct hash_control
*reg_hash
;
462 i386_align_code (fragP
, count
)
466 /* Various efficient no-op patterns for aligning code labels.
467 Note: Don't try to assemble the instructions in the comments.
468 0L and 0w are not legal. */
469 static const char f32_1
[] =
471 static const char f32_2
[] =
472 {0x89,0xf6}; /* movl %esi,%esi */
473 static const char f32_3
[] =
474 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
475 static const char f32_4
[] =
476 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
477 static const char f32_5
[] =
479 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
480 static const char f32_6
[] =
481 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
482 static const char f32_7
[] =
483 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
484 static const char f32_8
[] =
486 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
487 static const char f32_9
[] =
488 {0x89,0xf6, /* movl %esi,%esi */
489 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
490 static const char f32_10
[] =
491 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_11
[] =
494 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_12
[] =
497 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
498 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
499 static const char f32_13
[] =
500 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
501 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
502 static const char f32_14
[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
504 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
505 static const char f32_15
[] =
506 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
507 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
508 static const char f16_3
[] =
509 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
510 static const char f16_4
[] =
511 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
512 static const char f16_5
[] =
514 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
515 static const char f16_6
[] =
516 {0x89,0xf6, /* mov %si,%si */
517 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
518 static const char f16_7
[] =
519 {0x8d,0x74,0x00, /* lea 0(%si),%si */
520 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
521 static const char f16_8
[] =
522 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
523 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
524 static const char *const f32_patt
[] = {
525 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
526 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
528 static const char *const f16_patt
[] = {
529 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
530 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
533 if (count
<= 0 || count
> 15)
536 /* The recommended way to pad 64bit code is to use NOPs preceded by
537 maximally four 0x66 prefixes. Balance the size of nops. */
538 if (flag_code
== CODE_64BIT
)
541 int nnops
= (count
+ 3) / 4;
542 int len
= count
/ nnops
;
543 int remains
= count
- nnops
* len
;
546 for (i
= 0; i
< remains
; i
++)
548 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
549 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
552 for (; i
< nnops
; i
++)
554 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
555 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
560 if (flag_code
== CODE_16BIT
)
562 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
563 f16_patt
[count
- 1], count
);
565 /* Adjust jump offset. */
566 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
569 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
570 f32_patt
[count
- 1], count
);
571 fragP
->fr_var
= count
;
574 static INLINE
unsigned int
575 mode_from_disp_size (t
)
578 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
582 fits_in_signed_byte (num
)
585 return (num
>= -128) && (num
<= 127);
589 fits_in_unsigned_byte (num
)
592 return (num
& 0xff) == num
;
596 fits_in_unsigned_word (num
)
599 return (num
& 0xffff) == num
;
603 fits_in_signed_word (num
)
606 return (-32768 <= num
) && (num
<= 32767);
609 fits_in_signed_long (num
)
610 offsetT num ATTRIBUTE_UNUSED
;
615 return (!(((offsetT
) -1 << 31) & num
)
616 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
618 } /* fits_in_signed_long() */
620 fits_in_unsigned_long (num
)
621 offsetT num ATTRIBUTE_UNUSED
;
626 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
628 } /* fits_in_unsigned_long() */
631 smallest_imm_type (num
)
634 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
636 /* This code is disabled on the 486 because all the Imm1 forms
637 in the opcode table are slower on the i486. They're the
638 versions with the implicitly specified single-position
639 displacement, which has another syntax if you really want to
642 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
644 return (fits_in_signed_byte (num
)
645 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
646 : fits_in_unsigned_byte (num
)
647 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
648 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
649 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
650 : fits_in_signed_long (num
)
651 ? (Imm32
| Imm32S
| Imm64
)
652 : fits_in_unsigned_long (num
)
658 offset_in_range (val
, size
)
666 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
667 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
668 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
670 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
675 /* If BFD64, sign extend val. */
676 if (!use_rela_relocations
)
677 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
678 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
680 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
682 char buf1
[40], buf2
[40];
684 sprint_value (buf1
, val
);
685 sprint_value (buf2
, val
& mask
);
686 as_warn (_("%s shortened to %s"), buf1
, buf2
);
691 /* Returns 0 if attempting to add a prefix where one from the same
692 class already exists, 1 if non rep/repne added, 2 if rep/repne
701 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
702 && flag_code
== CODE_64BIT
)
710 case CS_PREFIX_OPCODE
:
711 case DS_PREFIX_OPCODE
:
712 case ES_PREFIX_OPCODE
:
713 case FS_PREFIX_OPCODE
:
714 case GS_PREFIX_OPCODE
:
715 case SS_PREFIX_OPCODE
:
719 case REPNE_PREFIX_OPCODE
:
720 case REPE_PREFIX_OPCODE
:
723 case LOCK_PREFIX_OPCODE
:
731 case ADDR_PREFIX_OPCODE
:
735 case DATA_PREFIX_OPCODE
:
740 if (i
.prefix
[q
] != 0)
742 as_bad (_("same type of prefix used twice"));
747 i
.prefix
[q
] = prefix
;
752 set_code_flag (value
)
756 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
757 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
758 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
760 as_bad (_("64bit mode not supported on this CPU."));
762 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
764 as_bad (_("32bit mode not supported on this CPU."));
770 set_16bit_gcc_code_flag (new_code_flag
)
773 flag_code
= new_code_flag
;
774 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
775 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
780 set_intel_syntax (syntax_flag
)
783 /* Find out if register prefixing is specified. */
784 int ask_naked_reg
= 0;
787 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
789 char *string
= input_line_pointer
;
790 int e
= get_symbol_end ();
792 if (strcmp (string
, "prefix") == 0)
794 else if (strcmp (string
, "noprefix") == 0)
797 as_bad (_("bad argument to syntax directive."));
798 *input_line_pointer
= e
;
800 demand_empty_rest_of_line ();
802 intel_syntax
= syntax_flag
;
804 if (ask_naked_reg
== 0)
807 allow_naked_reg
= (intel_syntax
808 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
810 /* Conservative default. */
815 allow_naked_reg
= (ask_naked_reg
< 0);
820 int dummy ATTRIBUTE_UNUSED
;
824 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
826 char *string
= input_line_pointer
;
827 int e
= get_symbol_end ();
830 for (i
= 0; cpu_arch
[i
].name
; i
++)
832 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
834 cpu_arch_name
= cpu_arch
[i
].name
;
835 cpu_arch_flags
= (cpu_arch
[i
].flags
836 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
840 if (!cpu_arch
[i
].name
)
841 as_bad (_("no such architecture: `%s'"), string
);
843 *input_line_pointer
= e
;
846 as_bad (_("missing cpu architecture"));
848 no_cond_jump_promotion
= 0;
849 if (*input_line_pointer
== ','
850 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
852 char *string
= ++input_line_pointer
;
853 int e
= get_symbol_end ();
855 if (strcmp (string
, "nojumps") == 0)
856 no_cond_jump_promotion
= 1;
857 else if (strcmp (string
, "jumps") == 0)
860 as_bad (_("no such architecture modifier: `%s'"), string
);
862 *input_line_pointer
= e
;
865 demand_empty_rest_of_line ();
872 if (!strcmp (default_arch
, "x86_64"))
873 return bfd_mach_x86_64
;
874 else if (!strcmp (default_arch
, "i386"))
875 return bfd_mach_i386_i386
;
877 as_fatal (_("Unknown architecture"));
884 const char *hash_err
;
886 /* Initialize op_hash hash table. */
887 op_hash
= hash_new ();
890 const template *optab
;
891 templates
*core_optab
;
893 /* Setup for loop. */
895 core_optab
= (templates
*) xmalloc (sizeof (templates
));
896 core_optab
->start
= optab
;
901 if (optab
->name
== NULL
902 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
904 /* different name --> ship out current template list;
905 add to hash table; & begin anew. */
906 core_optab
->end
= optab
;
907 hash_err
= hash_insert (op_hash
,
912 as_fatal (_("Internal Error: Can't hash %s: %s"),
916 if (optab
->name
== NULL
)
918 core_optab
= (templates
*) xmalloc (sizeof (templates
));
919 core_optab
->start
= optab
;
924 /* Initialize reg_hash hash table. */
925 reg_hash
= hash_new ();
927 const reg_entry
*regtab
;
929 for (regtab
= i386_regtab
;
930 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
933 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
935 as_fatal (_("Internal Error: Can't hash %s: %s"),
941 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
946 for (c
= 0; c
< 256; c
++)
951 mnemonic_chars
[c
] = c
;
952 register_chars
[c
] = c
;
953 operand_chars
[c
] = c
;
955 else if (ISLOWER (c
))
957 mnemonic_chars
[c
] = c
;
958 register_chars
[c
] = c
;
959 operand_chars
[c
] = c
;
961 else if (ISUPPER (c
))
963 mnemonic_chars
[c
] = TOLOWER (c
);
964 register_chars
[c
] = mnemonic_chars
[c
];
965 operand_chars
[c
] = c
;
968 if (ISALPHA (c
) || ISDIGIT (c
))
969 identifier_chars
[c
] = c
;
972 identifier_chars
[c
] = c
;
973 operand_chars
[c
] = c
;
978 identifier_chars
['@'] = '@';
980 digit_chars
['-'] = '-';
981 identifier_chars
['_'] = '_';
982 identifier_chars
['.'] = '.';
984 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
985 operand_chars
[(unsigned char) *p
] = *p
;
988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
989 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
991 record_alignment (text_section
, 2);
992 record_alignment (data_section
, 2);
993 record_alignment (bss_section
, 2);
997 if (flag_code
== CODE_64BIT
)
999 x86_dwarf2_return_column
= 16;
1000 x86_cie_data_alignment
= -8;
1004 x86_dwarf2_return_column
= 8;
1005 x86_cie_data_alignment
= -4;
1010 i386_print_statistics (file
)
1013 hash_print_statistics (file
, "i386 opcode", op_hash
);
1014 hash_print_statistics (file
, "i386 register", reg_hash
);
1019 /* Debugging routines for md_assemble. */
1020 static void pi
PARAMS ((char *, i386_insn
*));
1021 static void pte
PARAMS ((template *));
1022 static void pt
PARAMS ((unsigned int));
1023 static void pe
PARAMS ((expressionS
*));
1024 static void ps
PARAMS ((symbolS
*));
1033 fprintf (stdout
, "%s: template ", line
);
1035 fprintf (stdout
, " address: base %s index %s scale %x\n",
1036 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1037 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1038 x
->log2_scale_factor
);
1039 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1040 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1041 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1042 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1043 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1044 (x
->rex
& REX_MODE64
) != 0,
1045 (x
->rex
& REX_EXTX
) != 0,
1046 (x
->rex
& REX_EXTY
) != 0,
1047 (x
->rex
& REX_EXTZ
) != 0);
1048 for (i
= 0; i
< x
->operands
; i
++)
1050 fprintf (stdout
, " #%d: ", i
+ 1);
1052 fprintf (stdout
, "\n");
1054 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1055 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1056 if (x
->types
[i
] & Imm
)
1058 if (x
->types
[i
] & Disp
)
1059 pe (x
->op
[i
].disps
);
1068 fprintf (stdout
, " %d operands ", t
->operands
);
1069 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1070 if (t
->extension_opcode
!= None
)
1071 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1072 if (t
->opcode_modifier
& D
)
1073 fprintf (stdout
, "D");
1074 if (t
->opcode_modifier
& W
)
1075 fprintf (stdout
, "W");
1076 fprintf (stdout
, "\n");
1077 for (i
= 0; i
< t
->operands
; i
++)
1079 fprintf (stdout
, " #%d type ", i
+ 1);
1080 pt (t
->operand_types
[i
]);
1081 fprintf (stdout
, "\n");
1089 fprintf (stdout
, " operation %d\n", e
->X_op
);
1090 fprintf (stdout
, " add_number %ld (%lx)\n",
1091 (long) e
->X_add_number
, (long) e
->X_add_number
);
1092 if (e
->X_add_symbol
)
1094 fprintf (stdout
, " add_symbol ");
1095 ps (e
->X_add_symbol
);
1096 fprintf (stdout
, "\n");
1100 fprintf (stdout
, " op_symbol ");
1101 ps (e
->X_op_symbol
);
1102 fprintf (stdout
, "\n");
1110 fprintf (stdout
, "%s type %s%s",
1112 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1113 segment_name (S_GET_SEGMENT (s
)));
1122 static const type_names
[] =
1135 { BaseIndex
, "BaseIndex" },
1139 { Disp32S
, "d32s" },
1141 { InOutPortReg
, "InOutPortReg" },
1142 { ShiftCount
, "ShiftCount" },
1143 { Control
, "control reg" },
1144 { Test
, "test reg" },
1145 { Debug
, "debug reg" },
1146 { FloatReg
, "FReg" },
1147 { FloatAcc
, "FAcc" },
1151 { JumpAbsolute
, "Jump Absolute" },
1162 const struct type_name
*ty
;
1164 for (ty
= type_names
; ty
->mask
; ty
++)
1166 fprintf (stdout
, "%s, ", ty
->tname
);
1170 #endif /* DEBUG386 */
1172 #ifdef BFD_ASSEMBLER
1173 static bfd_reloc_code_real_type reloc
1174 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1176 static bfd_reloc_code_real_type
1177 reloc (size
, pcrel
, sign
, other
)
1181 bfd_reloc_code_real_type other
;
1183 if (other
!= NO_RELOC
)
1189 as_bad (_("There are no unsigned pc-relative relocations"));
1192 case 1: return BFD_RELOC_8_PCREL
;
1193 case 2: return BFD_RELOC_16_PCREL
;
1194 case 4: return BFD_RELOC_32_PCREL
;
1196 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1203 case 4: return BFD_RELOC_X86_64_32S
;
1208 case 1: return BFD_RELOC_8
;
1209 case 2: return BFD_RELOC_16
;
1210 case 4: return BFD_RELOC_32
;
1211 case 8: return BFD_RELOC_64
;
1213 as_bad (_("can not do %s %d byte relocation"),
1214 sign
? "signed" : "unsigned", size
);
1218 return BFD_RELOC_NONE
;
1221 /* Here we decide which fixups can be adjusted to make them relative to
1222 the beginning of the section instead of the symbol. Basically we need
1223 to make sure that the dynamic relocations are done correctly, so in
1224 some cases we force the original symbol to be used. */
1227 tc_i386_fix_adjustable (fixP
)
1228 fixS
*fixP ATTRIBUTE_UNUSED
;
1230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1231 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1234 /* Don't adjust pc-relative references to merge sections in 64-bit
1236 if (use_rela_relocations
1237 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1241 /* adjust_reloc_syms doesn't know about the GOT. */
1242 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1243 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1244 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1245 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1246 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1247 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1248 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1249 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1250 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1251 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1252 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1253 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1254 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1255 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1256 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1257 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1258 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1259 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1260 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1261 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1262 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1268 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1269 #define BFD_RELOC_8 0
1270 #define BFD_RELOC_16 0
1271 #define BFD_RELOC_32 0
1272 #define BFD_RELOC_8_PCREL 0
1273 #define BFD_RELOC_16_PCREL 0
1274 #define BFD_RELOC_32_PCREL 0
1275 #define BFD_RELOC_386_PLT32 0
1276 #define BFD_RELOC_386_GOT32 0
1277 #define BFD_RELOC_386_GOTOFF 0
1278 #define BFD_RELOC_386_TLS_GD 0
1279 #define BFD_RELOC_386_TLS_LDM 0
1280 #define BFD_RELOC_386_TLS_LDO_32 0
1281 #define BFD_RELOC_386_TLS_IE_32 0
1282 #define BFD_RELOC_386_TLS_IE 0
1283 #define BFD_RELOC_386_TLS_GOTIE 0
1284 #define BFD_RELOC_386_TLS_LE_32 0
1285 #define BFD_RELOC_386_TLS_LE 0
1286 #define BFD_RELOC_X86_64_PLT32 0
1287 #define BFD_RELOC_X86_64_GOT32 0
1288 #define BFD_RELOC_X86_64_GOTPCREL 0
1289 #define BFD_RELOC_X86_64_TLSGD 0
1290 #define BFD_RELOC_X86_64_TLSLD 0
1291 #define BFD_RELOC_X86_64_DTPOFF32 0
1292 #define BFD_RELOC_X86_64_GOTTPOFF 0
1293 #define BFD_RELOC_X86_64_TPOFF32 0
1296 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1299 intel_float_operand (mnemonic
)
1300 const char *mnemonic
;
1302 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1305 if (mnemonic
[0] == 'f')
1311 /* This is the guts of the machine-dependent assembler. LINE points to a
1312 machine dependent instruction. This function is supposed to emit
1313 the frags/bytes it assembles to. */
1320 char mnemonic
[MAX_MNEM_SIZE
];
1322 /* Initialize globals. */
1323 memset (&i
, '\0', sizeof (i
));
1324 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1325 i
.reloc
[j
] = NO_RELOC
;
1326 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1327 memset (im_expressions
, '\0', sizeof (im_expressions
));
1328 save_stack_p
= save_stack
;
1330 /* First parse an instruction mnemonic & call i386_operand for the operands.
1331 We assume that the scrubber has arranged it so that line[0] is the valid
1332 start of a (possibly prefixed) mnemonic. */
1334 line
= parse_insn (line
, mnemonic
);
1338 line
= parse_operands (line
, mnemonic
);
1342 /* Now we've parsed the mnemonic into a set of templates, and have the
1343 operands at hand. */
1345 /* All intel opcodes have reversed operands except for "bound" and
1346 "enter". We also don't reverse intersegment "jmp" and "call"
1347 instructions with 2 immediate operands so that the immediate segment
1348 precedes the offset, as it does when in AT&T mode. "enter" and the
1349 intersegment "jmp" and "call" instructions are the only ones that
1350 have two immediate operands. */
1351 if (intel_syntax
&& i
.operands
> 1
1352 && (strcmp (mnemonic
, "bound") != 0)
1353 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1359 if (i
.disp_operands
)
1362 /* Next, we find a template that matches the given insn,
1363 making sure the overlap of the given operands types is consistent
1364 with the template operand types. */
1366 if (!match_template ())
1371 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1373 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1374 i
.tm
.base_opcode
^= FloatR
;
1376 /* Zap movzx and movsx suffix. The suffix may have been set from
1377 "word ptr" or "byte ptr" on the source operand, but we'll use
1378 the suffix later to choose the destination register. */
1379 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1383 if (i
.tm
.opcode_modifier
& FWait
)
1384 if (!add_prefix (FWAIT_OPCODE
))
1387 /* Check string instruction segment overrides. */
1388 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1390 if (!check_string ())
1394 if (!process_suffix ())
1397 /* Make still unresolved immediate matches conform to size of immediate
1398 given in i.suffix. */
1399 if (!finalize_imm ())
1402 if (i
.types
[0] & Imm1
)
1403 i
.imm_operands
= 0; /* kludge for shift insns. */
1404 if (i
.types
[0] & ImplicitRegister
)
1406 if (i
.types
[1] & ImplicitRegister
)
1408 if (i
.types
[2] & ImplicitRegister
)
1411 if (i
.tm
.opcode_modifier
& ImmExt
)
1413 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1414 opcode suffix which is coded in the same place as an 8-bit
1415 immediate field would be. Here we fake an 8-bit immediate
1416 operand from the opcode suffix stored in tm.extension_opcode. */
1420 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1422 exp
= &im_expressions
[i
.imm_operands
++];
1423 i
.op
[i
.operands
].imms
= exp
;
1424 i
.types
[i
.operands
++] = Imm8
;
1425 exp
->X_op
= O_constant
;
1426 exp
->X_add_number
= i
.tm
.extension_opcode
;
1427 i
.tm
.extension_opcode
= None
;
1430 /* For insns with operands there are more diddles to do to the opcode. */
1433 if (!process_operands ())
1436 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1438 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1439 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1442 /* Handle conversion of 'int $3' --> special int3 insn. */
1443 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1445 i
.tm
.base_opcode
= INT3_OPCODE
;
1449 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1450 && i
.op
[0].disps
->X_op
== O_constant
)
1452 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1453 the absolute address given by the constant. Since ix86 jumps and
1454 calls are pc relative, we need to generate a reloc. */
1455 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1456 i
.op
[0].disps
->X_op
= O_symbol
;
1459 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1460 i
.rex
|= REX_MODE64
;
1462 /* For 8 bit registers we need an empty rex prefix. Also if the
1463 instruction already has a prefix, we need to convert old
1464 registers to new ones. */
1466 if (((i
.types
[0] & Reg8
) != 0
1467 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1468 || ((i
.types
[1] & Reg8
) != 0
1469 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1470 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1475 i
.rex
|= REX_OPCODE
;
1476 for (x
= 0; x
< 2; x
++)
1478 /* Look for 8 bit operand that uses old registers. */
1479 if ((i
.types
[x
] & Reg8
) != 0
1480 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1482 /* In case it is "hi" register, give up. */
1483 if (i
.op
[x
].regs
->reg_num
> 3)
1484 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1485 i
.op
[x
].regs
->reg_name
);
1487 /* Otherwise it is equivalent to the extended register.
1488 Since the encoding doesn't change this is merely
1489 cosmetic cleanup for debug output. */
1491 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1497 add_prefix (REX_OPCODE
| i
.rex
);
1499 /* We are ready to output the insn. */
1504 parse_insn (line
, mnemonic
)
1509 char *token_start
= l
;
1512 /* Non-zero if we found a prefix only acceptable with string insns. */
1513 const char *expecting_string_instruction
= NULL
;
1518 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1521 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1523 as_bad (_("no such instruction: `%s'"), token_start
);
1528 if (!is_space_char (*l
)
1529 && *l
!= END_OF_INSN
1530 && *l
!= PREFIX_SEPARATOR
1533 as_bad (_("invalid character %s in mnemonic"),
1534 output_invalid (*l
));
1537 if (token_start
== l
)
1539 if (*l
== PREFIX_SEPARATOR
)
1540 as_bad (_("expecting prefix; got nothing"));
1542 as_bad (_("expecting mnemonic; got nothing"));
1546 /* Look up instruction (or prefix) via hash table. */
1547 current_templates
= hash_find (op_hash
, mnemonic
);
1549 if (*l
!= END_OF_INSN
1550 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1551 && current_templates
1552 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1554 /* If we are in 16-bit mode, do not allow addr16 or data16.
1555 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1556 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1557 && flag_code
!= CODE_64BIT
1558 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1559 ^ (flag_code
== CODE_16BIT
)))
1561 as_bad (_("redundant %s prefix"),
1562 current_templates
->start
->name
);
1565 /* Add prefix, checking for repeated prefixes. */
1566 switch (add_prefix (current_templates
->start
->base_opcode
))
1571 expecting_string_instruction
= current_templates
->start
->name
;
1574 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1581 if (!current_templates
)
1583 /* See if we can get a match by trimming off a suffix. */
1586 case WORD_MNEM_SUFFIX
:
1587 case BYTE_MNEM_SUFFIX
:
1588 case QWORD_MNEM_SUFFIX
:
1589 i
.suffix
= mnem_p
[-1];
1591 current_templates
= hash_find (op_hash
, mnemonic
);
1593 case SHORT_MNEM_SUFFIX
:
1594 case LONG_MNEM_SUFFIX
:
1597 i
.suffix
= mnem_p
[-1];
1599 current_templates
= hash_find (op_hash
, mnemonic
);
1607 if (intel_float_operand (mnemonic
))
1608 i
.suffix
= SHORT_MNEM_SUFFIX
;
1610 i
.suffix
= LONG_MNEM_SUFFIX
;
1612 current_templates
= hash_find (op_hash
, mnemonic
);
1616 if (!current_templates
)
1618 as_bad (_("no such instruction: `%s'"), token_start
);
1623 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1625 /* Check for a branch hint. We allow ",pt" and ",pn" for
1626 predict taken and predict not taken respectively.
1627 I'm not sure that branch hints actually do anything on loop
1628 and jcxz insns (JumpByte) for current Pentium4 chips. They
1629 may work in the future and it doesn't hurt to accept them
1631 if (l
[0] == ',' && l
[1] == 'p')
1635 if (!add_prefix (DS_PREFIX_OPCODE
))
1639 else if (l
[2] == 'n')
1641 if (!add_prefix (CS_PREFIX_OPCODE
))
1647 /* Any other comma loses. */
1650 as_bad (_("invalid character %s in mnemonic"),
1651 output_invalid (*l
));
1655 /* Check if instruction is supported on specified architecture. */
1656 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1657 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1659 as_warn (_("`%s' is not supported on `%s'"),
1660 current_templates
->start
->name
, cpu_arch_name
);
1662 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1664 as_warn (_("use .code16 to ensure correct addressing mode"));
1667 /* Check for rep/repne without a string instruction. */
1668 if (expecting_string_instruction
1669 && !(current_templates
->start
->opcode_modifier
& IsString
))
1671 as_bad (_("expecting string instruction after `%s'"),
1672 expecting_string_instruction
);
1680 parse_operands (l
, mnemonic
)
1682 const char *mnemonic
;
1686 /* 1 if operand is pending after ','. */
1687 unsigned int expecting_operand
= 0;
1689 /* Non-zero if operand parens not balanced. */
1690 unsigned int paren_not_balanced
;
1692 while (*l
!= END_OF_INSN
)
1694 /* Skip optional white space before operand. */
1695 if (is_space_char (*l
))
1697 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1699 as_bad (_("invalid character %s before operand %d"),
1700 output_invalid (*l
),
1704 token_start
= l
; /* after white space */
1705 paren_not_balanced
= 0;
1706 while (paren_not_balanced
|| *l
!= ',')
1708 if (*l
== END_OF_INSN
)
1710 if (paren_not_balanced
)
1713 as_bad (_("unbalanced parenthesis in operand %d."),
1716 as_bad (_("unbalanced brackets in operand %d."),
1721 break; /* we are done */
1723 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1725 as_bad (_("invalid character %s in operand %d"),
1726 output_invalid (*l
),
1733 ++paren_not_balanced
;
1735 --paren_not_balanced
;
1740 ++paren_not_balanced
;
1742 --paren_not_balanced
;
1746 if (l
!= token_start
)
1747 { /* Yes, we've read in another operand. */
1748 unsigned int operand_ok
;
1749 this_operand
= i
.operands
++;
1750 if (i
.operands
> MAX_OPERANDS
)
1752 as_bad (_("spurious operands; (%d operands/instruction max)"),
1756 /* Now parse operand adding info to 'i' as we go along. */
1757 END_STRING_AND_SAVE (l
);
1761 i386_intel_operand (token_start
,
1762 intel_float_operand (mnemonic
));
1764 operand_ok
= i386_operand (token_start
);
1766 RESTORE_END_STRING (l
);
1772 if (expecting_operand
)
1774 expecting_operand_after_comma
:
1775 as_bad (_("expecting operand after ','; got nothing"));
1780 as_bad (_("expecting operand before ','; got nothing"));
1785 /* Now *l must be either ',' or END_OF_INSN. */
1788 if (*++l
== END_OF_INSN
)
1790 /* Just skip it, if it's \n complain. */
1791 goto expecting_operand_after_comma
;
1793 expecting_operand
= 1;
1802 union i386_op temp_op
;
1803 unsigned int temp_type
;
1804 RELOC_ENUM temp_reloc
;
1808 if (i
.operands
== 2)
1813 else if (i
.operands
== 3)
1818 temp_type
= i
.types
[xchg2
];
1819 i
.types
[xchg2
] = i
.types
[xchg1
];
1820 i
.types
[xchg1
] = temp_type
;
1821 temp_op
= i
.op
[xchg2
];
1822 i
.op
[xchg2
] = i
.op
[xchg1
];
1823 i
.op
[xchg1
] = temp_op
;
1824 temp_reloc
= i
.reloc
[xchg2
];
1825 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1826 i
.reloc
[xchg1
] = temp_reloc
;
1828 if (i
.mem_operands
== 2)
1830 const seg_entry
*temp_seg
;
1831 temp_seg
= i
.seg
[0];
1832 i
.seg
[0] = i
.seg
[1];
1833 i
.seg
[1] = temp_seg
;
1837 /* Try to ensure constant immediates are represented in the smallest
1842 char guess_suffix
= 0;
1846 guess_suffix
= i
.suffix
;
1847 else if (i
.reg_operands
)
1849 /* Figure out a suffix from the last register operand specified.
1850 We can't do this properly yet, ie. excluding InOutPortReg,
1851 but the following works for instructions with immediates.
1852 In any case, we can't set i.suffix yet. */
1853 for (op
= i
.operands
; --op
>= 0;)
1854 if (i
.types
[op
] & Reg
)
1856 if (i
.types
[op
] & Reg8
)
1857 guess_suffix
= BYTE_MNEM_SUFFIX
;
1858 else if (i
.types
[op
] & Reg16
)
1859 guess_suffix
= WORD_MNEM_SUFFIX
;
1860 else if (i
.types
[op
] & Reg32
)
1861 guess_suffix
= LONG_MNEM_SUFFIX
;
1862 else if (i
.types
[op
] & Reg64
)
1863 guess_suffix
= QWORD_MNEM_SUFFIX
;
1867 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1868 guess_suffix
= WORD_MNEM_SUFFIX
;
1870 for (op
= i
.operands
; --op
>= 0;)
1871 if (i
.types
[op
] & Imm
)
1873 switch (i
.op
[op
].imms
->X_op
)
1876 /* If a suffix is given, this operand may be shortened. */
1877 switch (guess_suffix
)
1879 case LONG_MNEM_SUFFIX
:
1880 i
.types
[op
] |= Imm32
| Imm64
;
1882 case WORD_MNEM_SUFFIX
:
1883 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1885 case BYTE_MNEM_SUFFIX
:
1886 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1890 /* If this operand is at most 16 bits, convert it
1891 to a signed 16 bit number before trying to see
1892 whether it will fit in an even smaller size.
1893 This allows a 16-bit operand such as $0xffe0 to
1894 be recognised as within Imm8S range. */
1895 if ((i
.types
[op
] & Imm16
)
1896 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1898 i
.op
[op
].imms
->X_add_number
=
1899 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1901 if ((i
.types
[op
] & Imm32
)
1902 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1905 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1906 ^ ((offsetT
) 1 << 31))
1907 - ((offsetT
) 1 << 31));
1909 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1911 /* We must avoid matching of Imm32 templates when 64bit
1912 only immediate is available. */
1913 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1914 i
.types
[op
] &= ~Imm32
;
1921 /* Symbols and expressions. */
1923 /* Convert symbolic operand to proper sizes for matching. */
1924 switch (guess_suffix
)
1926 case QWORD_MNEM_SUFFIX
:
1927 i
.types
[op
] = Imm64
| Imm32S
;
1929 case LONG_MNEM_SUFFIX
:
1930 i
.types
[op
] = Imm32
| Imm64
;
1932 case WORD_MNEM_SUFFIX
:
1933 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1936 case BYTE_MNEM_SUFFIX
:
1937 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1946 /* Try to use the smallest displacement type too. */
1952 for (op
= i
.operands
; --op
>= 0;)
1953 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1955 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1957 if (i
.types
[op
] & Disp16
)
1959 /* We know this operand is at most 16 bits, so
1960 convert to a signed 16 bit number before trying
1961 to see whether it will fit in an even smaller
1964 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1966 else if (i
.types
[op
] & Disp32
)
1968 /* We know this operand is at most 32 bits, so convert to a
1969 signed 32 bit number before trying to see whether it will
1970 fit in an even smaller size. */
1971 disp
&= (((offsetT
) 2 << 31) - 1);
1972 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1974 if (flag_code
== CODE_64BIT
)
1976 if (fits_in_signed_long (disp
))
1977 i
.types
[op
] |= Disp32S
;
1978 if (fits_in_unsigned_long (disp
))
1979 i
.types
[op
] |= Disp32
;
1981 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1982 && fits_in_signed_byte (disp
))
1983 i
.types
[op
] |= Disp8
;
1990 /* Points to template once we've found it. */
1992 unsigned int overlap0
, overlap1
, overlap2
;
1993 unsigned int found_reverse_match
;
1996 #define MATCH(overlap, given, template) \
1997 ((overlap & ~JumpAbsolute) \
1998 && (((given) & (BaseIndex | JumpAbsolute)) \
1999 == ((overlap) & (BaseIndex | JumpAbsolute))))
2001 /* If given types r0 and r1 are registers they must be of the same type
2002 unless the expected operand type register overlap is null.
2003 Note that Acc in a template matches every size of reg. */
2004 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2005 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2006 || ((g0) & Reg) == ((g1) & Reg) \
2007 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2012 found_reverse_match
= 0;
2013 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2015 : (i
.suffix
== WORD_MNEM_SUFFIX
2017 : (i
.suffix
== SHORT_MNEM_SUFFIX
2019 : (i
.suffix
== LONG_MNEM_SUFFIX
2021 : (i
.suffix
== QWORD_MNEM_SUFFIX
2023 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2024 ? No_xSuf
: 0))))));
2026 for (t
= current_templates
->start
;
2027 t
< current_templates
->end
;
2030 /* Must have right number of operands. */
2031 if (i
.operands
!= t
->operands
)
2034 /* Check the suffix, except for some instructions in intel mode. */
2035 if ((t
->opcode_modifier
& suffix_check
)
2037 && (t
->opcode_modifier
& IgnoreSize
))
2039 && t
->base_opcode
== 0xd9
2040 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2041 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2044 /* Do not verify operands when there are none. */
2045 else if (!t
->operands
)
2047 if (t
->cpu_flags
& ~cpu_arch_flags
)
2049 /* We've found a match; break out of loop. */
2053 overlap0
= i
.types
[0] & t
->operand_types
[0];
2054 switch (t
->operands
)
2057 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2062 overlap1
= i
.types
[1] & t
->operand_types
[1];
2063 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2064 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2065 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2066 t
->operand_types
[0],
2067 overlap1
, i
.types
[1],
2068 t
->operand_types
[1]))
2070 /* Check if other direction is valid ... */
2071 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2074 /* Try reversing direction of operands. */
2075 overlap0
= i
.types
[0] & t
->operand_types
[1];
2076 overlap1
= i
.types
[1] & t
->operand_types
[0];
2077 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2078 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2079 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2080 t
->operand_types
[1],
2081 overlap1
, i
.types
[1],
2082 t
->operand_types
[0]))
2084 /* Does not match either direction. */
2087 /* found_reverse_match holds which of D or FloatDR
2089 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2091 /* Found a forward 2 operand match here. */
2092 else if (t
->operands
== 3)
2094 /* Here we make use of the fact that there are no
2095 reverse match 3 operand instructions, and all 3
2096 operand instructions only need to be checked for
2097 register consistency between operands 2 and 3. */
2098 overlap2
= i
.types
[2] & t
->operand_types
[2];
2099 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2100 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2101 t
->operand_types
[1],
2102 overlap2
, i
.types
[2],
2103 t
->operand_types
[2]))
2107 /* Found either forward/reverse 2 or 3 operand match here:
2108 slip through to break. */
2110 if (t
->cpu_flags
& ~cpu_arch_flags
)
2112 found_reverse_match
= 0;
2115 /* We've found a match; break out of loop. */
2119 if (t
== current_templates
->end
)
2121 /* We found no match. */
2122 as_bad (_("suffix or operands invalid for `%s'"),
2123 current_templates
->start
->name
);
2127 if (!quiet_warnings
)
2130 && ((i
.types
[0] & JumpAbsolute
)
2131 != (t
->operand_types
[0] & JumpAbsolute
)))
2133 as_warn (_("indirect %s without `*'"), t
->name
);
2136 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2137 == (IsPrefix
| IgnoreSize
))
2139 /* Warn them that a data or address size prefix doesn't
2140 affect assembly of the next line of code. */
2141 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2145 /* Copy the template we found. */
2147 if (found_reverse_match
)
2149 /* If we found a reverse match we must alter the opcode
2150 direction bit. found_reverse_match holds bits to change
2151 (different for int & float insns). */
2153 i
.tm
.base_opcode
^= found_reverse_match
;
2155 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2156 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2165 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2166 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2168 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2170 as_bad (_("`%s' operand %d must use `%%es' segment"),
2175 /* There's only ever one segment override allowed per instruction.
2176 This instruction possibly has a legal segment override on the
2177 second operand, so copy the segment to where non-string
2178 instructions store it, allowing common code. */
2179 i
.seg
[0] = i
.seg
[1];
2181 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2183 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2185 as_bad (_("`%s' operand %d must use `%%es' segment"),
2197 /* If matched instruction specifies an explicit instruction mnemonic
2199 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2201 if (i
.tm
.opcode_modifier
& Size16
)
2202 i
.suffix
= WORD_MNEM_SUFFIX
;
2203 else if (i
.tm
.opcode_modifier
& Size64
)
2204 i
.suffix
= QWORD_MNEM_SUFFIX
;
2206 i
.suffix
= LONG_MNEM_SUFFIX
;
2208 else if (i
.reg_operands
)
2210 /* If there's no instruction mnemonic suffix we try to invent one
2211 based on register operands. */
2214 /* We take i.suffix from the last register operand specified,
2215 Destination register type is more significant than source
2218 for (op
= i
.operands
; --op
>= 0;)
2219 if ((i
.types
[op
] & Reg
)
2220 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2222 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2223 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2224 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2229 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2231 if (!check_byte_reg ())
2234 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2236 if (!check_long_reg ())
2239 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2241 if (!check_qword_reg ())
2244 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2246 if (!check_word_reg ())
2249 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2250 /* Do nothing if the instruction is going to ignore the prefix. */
2255 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2257 i
.suffix
= stackop_size
;
2260 /* Change the opcode based on the operand size given by i.suffix;
2261 We need not change things for byte insns. */
2263 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2265 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2269 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2271 /* It's not a byte, select word/dword operation. */
2272 if (i
.tm
.opcode_modifier
& W
)
2274 if (i
.tm
.opcode_modifier
& ShortForm
)
2275 i
.tm
.base_opcode
|= 8;
2277 i
.tm
.base_opcode
|= 1;
2280 /* Now select between word & dword operations via the operand
2281 size prefix, except for instructions that will ignore this
2283 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2284 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2285 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2286 || (flag_code
== CODE_64BIT
2287 && (i
.tm
.opcode_modifier
& JumpByte
))))
2289 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2290 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2291 prefix
= ADDR_PREFIX_OPCODE
;
2293 if (!add_prefix (prefix
))
2297 /* Set mode64 for an operand. */
2298 if (i
.suffix
== QWORD_MNEM_SUFFIX
2299 && flag_code
== CODE_64BIT
2300 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2301 i
.rex
|= REX_MODE64
;
2303 /* Size floating point instruction. */
2304 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2306 if (i
.tm
.opcode_modifier
& FloatMF
)
2307 i
.tm
.base_opcode
^= 4;
2318 for (op
= i
.operands
; --op
>= 0;)
2320 /* If this is an eight bit register, it's OK. If it's the 16 or
2321 32 bit version of an eight bit register, we will just use the
2322 low portion, and that's OK too. */
2323 if (i
.types
[op
] & Reg8
)
2326 /* movzx and movsx should not generate this warning. */
2328 && (i
.tm
.base_opcode
== 0xfb7
2329 || i
.tm
.base_opcode
== 0xfb6
2330 || i
.tm
.base_opcode
== 0x63
2331 || i
.tm
.base_opcode
== 0xfbe
2332 || i
.tm
.base_opcode
== 0xfbf))
2335 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2337 /* Check that the template allows eight bit regs. This
2338 kills insns such as `orb $1,%edx', which maybe should be
2340 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2344 /* Prohibit these changes in the 64bit mode, since the
2345 lowering is more complicated. */
2346 if (flag_code
== CODE_64BIT
2347 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2349 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2350 i
.op
[op
].regs
->reg_name
,
2354 #if REGISTER_WARNINGS
2356 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2357 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2358 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2359 ? REGNAM_AL
- REGNAM_AX
2360 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2361 i
.op
[op
].regs
->reg_name
,
2366 /* Any other register is bad. */
2367 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2369 | Control
| Debug
| Test
2370 | FloatReg
| FloatAcc
))
2372 as_bad (_("`%%%s' not allowed with `%s%c'"),
2373 i
.op
[op
].regs
->reg_name
,
2387 for (op
= i
.operands
; --op
>= 0;)
2388 /* Reject eight bit registers, except where the template requires
2389 them. (eg. movzb) */
2390 if ((i
.types
[op
] & Reg8
) != 0
2391 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2393 as_bad (_("`%%%s' not allowed with `%s%c'"),
2394 i
.op
[op
].regs
->reg_name
,
2399 /* Warn if the e prefix on a general reg is missing. */
2400 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2401 && (i
.types
[op
] & Reg16
) != 0
2402 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2404 /* Prohibit these changes in the 64bit mode, since the
2405 lowering is more complicated. */
2406 if (flag_code
== CODE_64BIT
)
2408 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2409 i
.op
[op
].regs
->reg_name
,
2413 #if REGISTER_WARNINGS
2415 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2416 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2417 i
.op
[op
].regs
->reg_name
,
2421 /* Warn if the r prefix on a general reg is missing. */
2422 else if ((i
.types
[op
] & Reg64
) != 0
2423 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2425 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2426 i
.op
[op
].regs
->reg_name
,
2438 for (op
= i
.operands
; --op
>= 0; )
2439 /* Reject eight bit registers, except where the template requires
2440 them. (eg. movzb) */
2441 if ((i
.types
[op
] & Reg8
) != 0
2442 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2444 as_bad (_("`%%%s' not allowed with `%s%c'"),
2445 i
.op
[op
].regs
->reg_name
,
2450 /* Warn if the e prefix on a general reg is missing. */
2451 else if (((i
.types
[op
] & Reg16
) != 0
2452 || (i
.types
[op
] & Reg32
) != 0)
2453 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2455 /* Prohibit these changes in the 64bit mode, since the
2456 lowering is more complicated. */
2457 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2458 i
.op
[op
].regs
->reg_name
,
2469 for (op
= i
.operands
; --op
>= 0;)
2470 /* Reject eight bit registers, except where the template requires
2471 them. (eg. movzb) */
2472 if ((i
.types
[op
] & Reg8
) != 0
2473 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2475 as_bad (_("`%%%s' not allowed with `%s%c'"),
2476 i
.op
[op
].regs
->reg_name
,
2481 /* Warn if the e prefix on a general reg is present. */
2482 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2483 && (i
.types
[op
] & Reg32
) != 0
2484 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2486 /* Prohibit these changes in the 64bit mode, since the
2487 lowering is more complicated. */
2488 if (flag_code
== CODE_64BIT
)
2490 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2491 i
.op
[op
].regs
->reg_name
,
2496 #if REGISTER_WARNINGS
2497 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2498 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2499 i
.op
[op
].regs
->reg_name
,
2509 unsigned int overlap0
, overlap1
, overlap2
;
2511 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2512 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2513 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2514 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2515 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2519 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2521 : (i
.suffix
== WORD_MNEM_SUFFIX
2523 : (i
.suffix
== QWORD_MNEM_SUFFIX
2527 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2528 || overlap0
== (Imm16
| Imm32
)
2529 || overlap0
== (Imm16
| Imm32S
))
2531 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2534 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2535 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2536 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2538 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2542 i
.types
[0] = overlap0
;
2544 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2545 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2546 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2547 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2548 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2552 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2554 : (i
.suffix
== WORD_MNEM_SUFFIX
2556 : (i
.suffix
== QWORD_MNEM_SUFFIX
2560 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2561 || overlap1
== (Imm16
| Imm32
)
2562 || overlap1
== (Imm16
| Imm32S
))
2564 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2567 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2568 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2569 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2571 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2575 i
.types
[1] = overlap1
;
2577 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2578 assert ((overlap2
& Imm
) == 0);
2579 i
.types
[2] = overlap2
;
2587 /* Default segment register this instruction will use for memory
2588 accesses. 0 means unknown. This is only for optimizing out
2589 unnecessary segment overrides. */
2590 const seg_entry
*default_seg
= 0;
2592 /* The imul $imm, %reg instruction is converted into
2593 imul $imm, %reg, %reg, and the clr %reg instruction
2594 is converted into xor %reg, %reg. */
2595 if (i
.tm
.opcode_modifier
& regKludge
)
2597 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2598 /* Pretend we saw the extra register operand. */
2599 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2600 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2601 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2605 if (i
.tm
.opcode_modifier
& ShortForm
)
2607 /* The register or float register operand is in operand 0 or 1. */
2608 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2609 /* Register goes in low 3 bits of opcode. */
2610 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2611 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2613 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2615 /* Warn about some common errors, but press on regardless.
2616 The first case can be generated by gcc (<= 2.8.1). */
2617 if (i
.operands
== 2)
2619 /* Reversed arguments on faddp, fsubp, etc. */
2620 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2621 i
.op
[1].regs
->reg_name
,
2622 i
.op
[0].regs
->reg_name
);
2626 /* Extraneous `l' suffix on fp insn. */
2627 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2628 i
.op
[0].regs
->reg_name
);
2632 else if (i
.tm
.opcode_modifier
& Modrm
)
2634 /* The opcode is completed (modulo i.tm.extension_opcode which
2635 must be put into the modrm byte). Now, we make the modrm and
2636 index base bytes based on all the info we've collected. */
2638 default_seg
= build_modrm_byte ();
2640 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2642 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2643 && i
.op
[0].regs
->reg_num
== 1)
2645 as_bad (_("you can't `pop %%cs'"));
2648 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2649 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2652 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2656 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2658 /* For the string instructions that allow a segment override
2659 on one of their operands, the default segment is ds. */
2663 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2664 as_warn (_("segment override on `lea' is ineffectual"));
2666 /* If a segment was explicitly specified, and the specified segment
2667 is not the default, use an opcode prefix to select it. If we
2668 never figured out what the default segment is, then default_seg
2669 will be zero at this point, and the specified segment prefix will
2671 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2673 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2679 static const seg_entry
*
2682 const seg_entry
*default_seg
= 0;
2684 /* i.reg_operands MUST be the number of real register operands;
2685 implicit registers do not count. */
2686 if (i
.reg_operands
== 2)
2688 unsigned int source
, dest
;
2689 source
= ((i
.types
[0]
2690 & (Reg
| RegMMX
| RegXMM
2692 | Control
| Debug
| Test
))
2697 /* One of the register operands will be encoded in the i.tm.reg
2698 field, the other in the combined i.tm.mode and i.tm.regmem
2699 fields. If no form of this instruction supports a memory
2700 destination operand, then we assume the source operand may
2701 sometimes be a memory operand and so we need to store the
2702 destination in the i.rm.reg field. */
2703 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2705 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2706 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2707 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2709 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2714 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2715 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2716 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2718 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2723 { /* If it's not 2 reg operands... */
2726 unsigned int fake_zero_displacement
= 0;
2727 unsigned int op
= ((i
.types
[0] & AnyMem
)
2729 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2733 if (i
.base_reg
== 0)
2736 if (!i
.disp_operands
)
2737 fake_zero_displacement
= 1;
2738 if (i
.index_reg
== 0)
2740 /* Operand is just <disp> */
2741 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2742 && (flag_code
!= CODE_64BIT
))
2744 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2745 i
.types
[op
] &= ~Disp
;
2746 i
.types
[op
] |= Disp16
;
2748 else if (flag_code
!= CODE_64BIT
2749 || (i
.prefix
[ADDR_PREFIX
] != 0))
2751 i
.rm
.regmem
= NO_BASE_REGISTER
;
2752 i
.types
[op
] &= ~Disp
;
2753 i
.types
[op
] |= Disp32
;
2757 /* 64bit mode overwrites the 32bit absolute
2758 addressing by RIP relative addressing and
2759 absolute addressing is encoded by one of the
2760 redundant SIB forms. */
2761 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2762 i
.sib
.base
= NO_BASE_REGISTER
;
2763 i
.sib
.index
= NO_INDEX_REGISTER
;
2764 i
.types
[op
] &= ~Disp
;
2765 i
.types
[op
] |= Disp32S
;
2768 else /* !i.base_reg && i.index_reg */
2770 i
.sib
.index
= i
.index_reg
->reg_num
;
2771 i
.sib
.base
= NO_BASE_REGISTER
;
2772 i
.sib
.scale
= i
.log2_scale_factor
;
2773 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2774 i
.types
[op
] &= ~Disp
;
2775 if (flag_code
!= CODE_64BIT
)
2776 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2778 i
.types
[op
] |= Disp32S
;
2779 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2783 /* RIP addressing for 64bit mode. */
2784 else if (i
.base_reg
->reg_type
== BaseIndex
)
2786 i
.rm
.regmem
= NO_BASE_REGISTER
;
2787 i
.types
[op
] &= ~Disp
;
2788 i
.types
[op
] |= Disp32S
;
2789 i
.flags
[op
] = Operand_PCrel
;
2791 else if (i
.base_reg
->reg_type
& Reg16
)
2793 switch (i
.base_reg
->reg_num
)
2796 if (i
.index_reg
== 0)
2798 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2799 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2803 if (i
.index_reg
== 0)
2806 if ((i
.types
[op
] & Disp
) == 0)
2808 /* fake (%bp) into 0(%bp) */
2809 i
.types
[op
] |= Disp8
;
2810 fake_zero_displacement
= 1;
2813 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2814 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2816 default: /* (%si) -> 4 or (%di) -> 5 */
2817 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2819 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2821 else /* i.base_reg and 32/64 bit mode */
2823 if (flag_code
== CODE_64BIT
2824 && (i
.types
[op
] & Disp
))
2826 if (i
.types
[op
] & Disp8
)
2827 i
.types
[op
] = Disp8
| Disp32S
;
2829 i
.types
[op
] = Disp32S
;
2831 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2832 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2834 i
.sib
.base
= i
.base_reg
->reg_num
;
2835 /* x86-64 ignores REX prefix bit here to avoid decoder
2837 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2840 if (i
.disp_operands
== 0)
2842 fake_zero_displacement
= 1;
2843 i
.types
[op
] |= Disp8
;
2846 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2850 i
.sib
.scale
= i
.log2_scale_factor
;
2851 if (i
.index_reg
== 0)
2853 /* <disp>(%esp) becomes two byte modrm with no index
2854 register. We've already stored the code for esp
2855 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2856 Any base register besides %esp will not use the
2857 extra modrm byte. */
2858 i
.sib
.index
= NO_INDEX_REGISTER
;
2859 #if !SCALE1_WHEN_NO_INDEX
2860 /* Another case where we force the second modrm byte. */
2861 if (i
.log2_scale_factor
)
2862 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2867 i
.sib
.index
= i
.index_reg
->reg_num
;
2868 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2869 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2872 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2875 if (fake_zero_displacement
)
2877 /* Fakes a zero displacement assuming that i.types[op]
2878 holds the correct displacement size. */
2881 assert (i
.op
[op
].disps
== 0);
2882 exp
= &disp_expressions
[i
.disp_operands
++];
2883 i
.op
[op
].disps
= exp
;
2884 exp
->X_op
= O_constant
;
2885 exp
->X_add_number
= 0;
2886 exp
->X_add_symbol
= (symbolS
*) 0;
2887 exp
->X_op_symbol
= (symbolS
*) 0;
2891 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2892 (if any) based on i.tm.extension_opcode. Again, we must be
2893 careful to make sure that segment/control/debug/test/MMX
2894 registers are coded into the i.rm.reg field. */
2899 & (Reg
| RegMMX
| RegXMM
2901 | Control
| Debug
| Test
))
2904 & (Reg
| RegMMX
| RegXMM
2906 | Control
| Debug
| Test
))
2909 /* If there is an extension opcode to put here, the register
2910 number must be put into the regmem field. */
2911 if (i
.tm
.extension_opcode
!= None
)
2913 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2914 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2919 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2920 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2924 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2925 must set it to 3 to indicate this is a register operand
2926 in the regmem field. */
2927 if (!i
.mem_operands
)
2931 /* Fill in i.rm.reg field with extension opcode (if any). */
2932 if (i
.tm
.extension_opcode
!= None
)
2933 i
.rm
.reg
= i
.tm
.extension_opcode
;
2944 relax_substateT subtype
;
2949 if (flag_code
== CODE_16BIT
)
2953 if (i
.prefix
[DATA_PREFIX
] != 0)
2959 /* Pentium4 branch hints. */
2960 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2961 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2966 if (i
.prefix
[REX_PREFIX
] != 0)
2972 if (i
.prefixes
!= 0 && !intel_syntax
)
2973 as_warn (_("skipping prefixes on this instruction"));
2975 /* It's always a symbol; End frag & setup for relax.
2976 Make sure there is enough room in this frag for the largest
2977 instruction we may generate in md_convert_frag. This is 2
2978 bytes for the opcode and room for the prefix and largest
2980 frag_grow (prefix
+ 2 + 4);
2981 /* Prefix and 1 opcode byte go in fr_fix. */
2982 p
= frag_more (prefix
+ 1);
2983 if (i
.prefix
[DATA_PREFIX
] != 0)
2984 *p
++ = DATA_PREFIX_OPCODE
;
2985 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2986 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2987 *p
++ = i
.prefix
[SEG_PREFIX
];
2988 if (i
.prefix
[REX_PREFIX
] != 0)
2989 *p
++ = i
.prefix
[REX_PREFIX
];
2990 *p
= i
.tm
.base_opcode
;
2992 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2993 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2994 else if ((cpu_arch_flags
& Cpu386
) != 0)
2995 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2997 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3000 sym
= i
.op
[0].disps
->X_add_symbol
;
3001 off
= i
.op
[0].disps
->X_add_number
;
3003 if (i
.op
[0].disps
->X_op
!= O_constant
3004 && i
.op
[0].disps
->X_op
!= O_symbol
)
3006 /* Handle complex expressions. */
3007 sym
= make_expr_symbol (i
.op
[0].disps
);
3011 /* 1 possible extra opcode + 4 byte displacement go in var part.
3012 Pass reloc in fr_var. */
3013 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3023 if (i
.tm
.opcode_modifier
& JumpByte
)
3025 /* This is a loop or jecxz type instruction. */
3027 if (i
.prefix
[ADDR_PREFIX
] != 0)
3029 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3032 /* Pentium4 branch hints. */
3033 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3034 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3036 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3045 if (flag_code
== CODE_16BIT
)
3048 if (i
.prefix
[DATA_PREFIX
] != 0)
3050 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3060 if (i
.prefix
[REX_PREFIX
] != 0)
3062 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3066 if (i
.prefixes
!= 0 && !intel_syntax
)
3067 as_warn (_("skipping prefixes on this instruction"));
3069 p
= frag_more (1 + size
);
3070 *p
++ = i
.tm
.base_opcode
;
3072 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3073 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3075 /* All jumps handled here are signed, but don't use a signed limit
3076 check for 32 and 16 bit jumps as we want to allow wrap around at
3077 4G and 64k respectively. */
3079 fixP
->fx_signed
= 1;
3083 output_interseg_jump ()
3091 if (flag_code
== CODE_16BIT
)
3095 if (i
.prefix
[DATA_PREFIX
] != 0)
3101 if (i
.prefix
[REX_PREFIX
] != 0)
3111 if (i
.prefixes
!= 0 && !intel_syntax
)
3112 as_warn (_("skipping prefixes on this instruction"));
3114 /* 1 opcode; 2 segment; offset */
3115 p
= frag_more (prefix
+ 1 + 2 + size
);
3117 if (i
.prefix
[DATA_PREFIX
] != 0)
3118 *p
++ = DATA_PREFIX_OPCODE
;
3120 if (i
.prefix
[REX_PREFIX
] != 0)
3121 *p
++ = i
.prefix
[REX_PREFIX
];
3123 *p
++ = i
.tm
.base_opcode
;
3124 if (i
.op
[1].imms
->X_op
== O_constant
)
3126 offsetT n
= i
.op
[1].imms
->X_add_number
;
3129 && !fits_in_unsigned_word (n
)
3130 && !fits_in_signed_word (n
))
3132 as_bad (_("16-bit jump out of range"));
3135 md_number_to_chars (p
, n
, size
);
3138 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3139 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3140 if (i
.op
[0].imms
->X_op
!= O_constant
)
3141 as_bad (_("can't handle non absolute segment in `%s'"),
3143 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3150 fragS
*insn_start_frag
;
3151 offsetT insn_start_off
;
3153 /* Tie dwarf2 debug info to the address at the start of the insn.
3154 We can't do this after the insn has been output as the current
3155 frag may have been closed off. eg. by frag_var. */
3156 dwarf2_emit_insn (0);
3158 insn_start_frag
= frag_now
;
3159 insn_start_off
= frag_now_fix ();
3162 if (i
.tm
.opcode_modifier
& Jump
)
3164 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3166 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3167 output_interseg_jump ();
3170 /* Output normal instructions here. */
3174 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3175 byte for the SSE instructions to specify a prefix they require. */
3176 if (i
.tm
.base_opcode
& 0xff0000)
3177 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3179 /* The prefix bytes. */
3181 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3187 md_number_to_chars (p
, (valueT
) *q
, 1);
3191 /* Now the opcode; be careful about word order here! */
3192 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3194 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3199 /* Put out high byte first: can't use md_number_to_chars! */
3200 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3201 *p
= i
.tm
.base_opcode
& 0xff;
3204 /* Now the modrm byte and sib byte (if present). */
3205 if (i
.tm
.opcode_modifier
& Modrm
)
3208 md_number_to_chars (p
,
3209 (valueT
) (i
.rm
.regmem
<< 0
3213 /* If i.rm.regmem == ESP (4)
3214 && i.rm.mode != (Register mode)
3216 ==> need second modrm byte. */
3217 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3219 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3222 md_number_to_chars (p
,
3223 (valueT
) (i
.sib
.base
<< 0
3225 | i
.sib
.scale
<< 6),
3230 if (i
.disp_operands
)
3231 output_disp (insn_start_frag
, insn_start_off
);
3234 output_imm (insn_start_frag
, insn_start_off
);
3242 #endif /* DEBUG386 */
3246 output_disp (insn_start_frag
, insn_start_off
)
3247 fragS
*insn_start_frag
;
3248 offsetT insn_start_off
;
3253 for (n
= 0; n
< i
.operands
; n
++)
3255 if (i
.types
[n
] & Disp
)
3257 if (i
.op
[n
].disps
->X_op
== O_constant
)
3263 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3266 if (i
.types
[n
] & Disp8
)
3268 if (i
.types
[n
] & Disp64
)
3271 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3273 p
= frag_more (size
);
3274 md_number_to_chars (p
, val
, size
);
3278 RELOC_ENUM reloc_type
;
3281 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3283 /* The PC relative address is computed relative
3284 to the instruction boundary, so in case immediate
3285 fields follows, we need to adjust the value. */
3286 if (pcrel
&& i
.imm_operands
)
3291 for (n1
= 0; n1
< i
.operands
; n1
++)
3292 if (i
.types
[n1
] & Imm
)
3294 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3297 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3299 if (i
.types
[n1
] & Imm64
)
3304 /* We should find the immediate. */
3305 if (n1
== i
.operands
)
3307 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3310 if (i
.types
[n
] & Disp32S
)
3313 if (i
.types
[n
] & (Disp16
| Disp64
))
3316 if (i
.types
[n
] & Disp64
)
3320 p
= frag_more (size
);
3321 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3322 #ifdef BFD_ASSEMBLER
3323 if (reloc_type
== BFD_RELOC_32
3325 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3326 && (i
.op
[n
].disps
->X_op
== O_symbol
3327 || (i
.op
[n
].disps
->X_op
== O_add
3328 && ((symbol_get_value_expression
3329 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3334 if (insn_start_frag
== frag_now
)
3335 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3340 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3341 for (fr
= insn_start_frag
->fr_next
;
3342 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3344 add
+= p
- frag_now
->fr_literal
;
3347 /* We don't support dynamic linking on x86-64 yet. */
3348 if (flag_code
== CODE_64BIT
)
3350 reloc_type
= BFD_RELOC_386_GOTPC
;
3351 i
.op
[n
].disps
->X_add_number
+= add
;
3354 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3355 i
.op
[n
].disps
, pcrel
, reloc_type
);
3362 output_imm (insn_start_frag
, insn_start_off
)
3363 fragS
*insn_start_frag
;
3364 offsetT insn_start_off
;
3369 for (n
= 0; n
< i
.operands
; n
++)
3371 if (i
.types
[n
] & Imm
)
3373 if (i
.op
[n
].imms
->X_op
== O_constant
)
3379 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3382 if (i
.types
[n
] & (Imm8
| Imm8S
))
3384 else if (i
.types
[n
] & Imm64
)
3387 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3389 p
= frag_more (size
);
3390 md_number_to_chars (p
, val
, size
);
3394 /* Not absolute_section.
3395 Need a 32-bit fixup (don't support 8bit
3396 non-absolute imms). Try to support other
3398 RELOC_ENUM reloc_type
;
3402 if ((i
.types
[n
] & (Imm32S
))
3403 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3405 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3408 if (i
.types
[n
] & (Imm8
| Imm8S
))
3410 if (i
.types
[n
] & Imm64
)
3414 p
= frag_more (size
);
3415 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3416 #ifdef BFD_ASSEMBLER
3417 /* This is tough to explain. We end up with this one if we
3418 * have operands that look like
3419 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3420 * obtain the absolute address of the GOT, and it is strongly
3421 * preferable from a performance point of view to avoid using
3422 * a runtime relocation for this. The actual sequence of
3423 * instructions often look something like:
3428 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3430 * The call and pop essentially return the absolute address
3431 * of the label .L66 and store it in %ebx. The linker itself
3432 * will ultimately change the first operand of the addl so
3433 * that %ebx points to the GOT, but to keep things simple, the
3434 * .o file must have this operand set so that it generates not
3435 * the absolute address of .L66, but the absolute address of
3436 * itself. This allows the linker itself simply treat a GOTPC
3437 * relocation as asking for a pcrel offset to the GOT to be
3438 * added in, and the addend of the relocation is stored in the
3439 * operand field for the instruction itself.
3441 * Our job here is to fix the operand so that it would add
3442 * the correct offset so that %ebx would point to itself. The
3443 * thing that is tricky is that .-.L66 will point to the
3444 * beginning of the instruction, so we need to further modify
3445 * the operand so that it will point to itself. There are
3446 * other cases where you have something like:
3448 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3450 * and here no correction would be required. Internally in
3451 * the assembler we treat operands of this form as not being
3452 * pcrel since the '.' is explicitly mentioned, and I wonder
3453 * whether it would simplify matters to do it this way. Who
3454 * knows. In earlier versions of the PIC patches, the
3455 * pcrel_adjust field was used to store the correction, but
3456 * since the expression is not pcrel, I felt it would be
3457 * confusing to do it this way. */
3459 if (reloc_type
== BFD_RELOC_32
3461 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3462 && (i
.op
[n
].imms
->X_op
== O_symbol
3463 || (i
.op
[n
].imms
->X_op
== O_add
3464 && ((symbol_get_value_expression
3465 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3470 if (insn_start_frag
== frag_now
)
3471 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3476 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3477 for (fr
= insn_start_frag
->fr_next
;
3478 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3480 add
+= p
- frag_now
->fr_literal
;
3483 /* We don't support dynamic linking on x86-64 yet. */
3484 if (flag_code
== CODE_64BIT
)
3486 reloc_type
= BFD_RELOC_386_GOTPC
;
3487 i
.op
[n
].imms
->X_add_number
+= add
;
3490 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3491 i
.op
[n
].imms
, 0, reloc_type
);
3498 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3500 /* Parse operands of the form
3501 <symbol>@GOTOFF+<nnn>
3502 and similar .plt or .got references.
3504 If we find one, set up the correct relocation in RELOC and copy the
3505 input string, minus the `@GOTOFF' into a malloc'd buffer for
3506 parsing by the calling routine. Return this buffer, and if ADJUST
3507 is non-null set it to the length of the string we removed from the
3508 input line. Otherwise return NULL. */
3510 lex_got (reloc
, adjust
)
3514 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3515 static const struct {
3517 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3519 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3520 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3521 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3522 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3523 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3524 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3525 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3526 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3527 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3528 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3529 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3530 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3531 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3536 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3537 if (is_end_of_line
[(unsigned char) *cp
])
3540 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3544 len
= strlen (gotrel
[j
].str
);
3545 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3547 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3550 char *tmpbuf
, *past_reloc
;
3552 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3556 if (GOT_symbol
== NULL
)
3557 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3559 /* Replace the relocation token with ' ', so that
3560 errors like foo@GOTOFF1 will be detected. */
3562 /* The length of the first part of our input line. */
3563 first
= cp
- input_line_pointer
;
3565 /* The second part goes from after the reloc token until
3566 (and including) an end_of_line char. Don't use strlen
3567 here as the end_of_line char may not be a NUL. */
3568 past_reloc
= cp
+ 1 + len
;
3569 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3571 second
= cp
- past_reloc
;
3573 /* Allocate and copy string. The trailing NUL shouldn't
3574 be necessary, but be safe. */
3575 tmpbuf
= xmalloc (first
+ second
+ 2);
3576 memcpy (tmpbuf
, input_line_pointer
, first
);
3577 tmpbuf
[first
] = ' ';
3578 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3579 tmpbuf
[first
+ second
+ 1] = '\0';
3583 as_bad (_("@%s reloc is not supported in %s bit mode"),
3584 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3589 /* Might be a symbol version string. Don't as_bad here. */
3593 /* x86_cons_fix_new is called via the expression parsing code when a
3594 reloc is needed. We use this hook to get the correct .got reloc. */
3595 static RELOC_ENUM got_reloc
= NO_RELOC
;
3598 x86_cons_fix_new (frag
, off
, len
, exp
)
3604 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3605 got_reloc
= NO_RELOC
;
3606 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3610 x86_cons (exp
, size
)
3616 /* Handle @GOTOFF and the like in an expression. */
3618 char *gotfree_input_line
;
3621 save
= input_line_pointer
;
3622 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3623 if (gotfree_input_line
)
3624 input_line_pointer
= gotfree_input_line
;
3628 if (gotfree_input_line
)
3630 /* expression () has merrily parsed up to the end of line,
3631 or a comma - in the wrong buffer. Transfer how far
3632 input_line_pointer has moved to the right buffer. */
3633 input_line_pointer
= (save
3634 + (input_line_pointer
- gotfree_input_line
)
3636 free (gotfree_input_line
);
3644 static int i386_immediate
PARAMS ((char *));
3647 i386_immediate (imm_start
)
3650 char *save_input_line_pointer
;
3652 char *gotfree_input_line
;
3657 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3659 as_bad (_("only 1 or 2 immediate operands are allowed"));
3663 exp
= &im_expressions
[i
.imm_operands
++];
3664 i
.op
[this_operand
].imms
= exp
;
3666 if (is_space_char (*imm_start
))
3669 save_input_line_pointer
= input_line_pointer
;
3670 input_line_pointer
= imm_start
;
3673 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3674 if (gotfree_input_line
)
3675 input_line_pointer
= gotfree_input_line
;
3678 exp_seg
= expression (exp
);
3681 if (*input_line_pointer
)
3682 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3684 input_line_pointer
= save_input_line_pointer
;
3686 if (gotfree_input_line
)
3687 free (gotfree_input_line
);
3690 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3692 /* Missing or bad expr becomes absolute 0. */
3693 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3695 exp
->X_op
= O_constant
;
3696 exp
->X_add_number
= 0;
3697 exp
->X_add_symbol
= (symbolS
*) 0;
3698 exp
->X_op_symbol
= (symbolS
*) 0;
3700 else if (exp
->X_op
== O_constant
)
3702 /* Size it properly later. */
3703 i
.types
[this_operand
] |= Imm64
;
3704 /* If BFD64, sign extend val. */
3705 if (!use_rela_relocations
)
3706 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3707 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3709 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3711 #ifdef BFD_ASSEMBLER
3712 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3714 && exp_seg
!= absolute_section
3715 && exp_seg
!= text_section
3716 && exp_seg
!= data_section
3717 && exp_seg
!= bss_section
3718 && exp_seg
!= undefined_section
3719 #ifdef BFD_ASSEMBLER
3720 && !bfd_is_com_section (exp_seg
)
3724 #ifdef BFD_ASSEMBLER
3725 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3727 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3734 /* This is an address. The size of the address will be
3735 determined later, depending on destination register,
3736 suffix, or the default for the section. */
3737 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3743 static char *i386_scale
PARAMS ((char *));
3750 char *save
= input_line_pointer
;
3752 input_line_pointer
= scale
;
3753 val
= get_absolute_expression ();
3759 i
.log2_scale_factor
= 0;
3762 i
.log2_scale_factor
= 1;
3765 i
.log2_scale_factor
= 2;
3768 i
.log2_scale_factor
= 3;
3771 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3773 input_line_pointer
= save
;
3776 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3778 as_warn (_("scale factor of %d without an index register"),
3779 1 << i
.log2_scale_factor
);
3780 #if SCALE1_WHEN_NO_INDEX
3781 i
.log2_scale_factor
= 0;
3784 scale
= input_line_pointer
;
3785 input_line_pointer
= save
;
3789 static int i386_displacement
PARAMS ((char *, char *));
3792 i386_displacement (disp_start
, disp_end
)
3798 char *save_input_line_pointer
;
3800 char *gotfree_input_line
;
3802 int bigdisp
= Disp32
;
3804 if (flag_code
== CODE_64BIT
)
3806 if (i
.prefix
[ADDR_PREFIX
] == 0)
3809 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3811 i
.types
[this_operand
] |= bigdisp
;
3813 exp
= &disp_expressions
[i
.disp_operands
];
3814 i
.op
[this_operand
].disps
= exp
;
3816 save_input_line_pointer
= input_line_pointer
;
3817 input_line_pointer
= disp_start
;
3818 END_STRING_AND_SAVE (disp_end
);
3820 #ifndef GCC_ASM_O_HACK
3821 #define GCC_ASM_O_HACK 0
3824 END_STRING_AND_SAVE (disp_end
+ 1);
3825 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3826 && displacement_string_end
[-1] == '+')
3828 /* This hack is to avoid a warning when using the "o"
3829 constraint within gcc asm statements.
3832 #define _set_tssldt_desc(n,addr,limit,type) \
3833 __asm__ __volatile__ ( \
3835 "movw %w1,2+%0\n\t" \
3837 "movb %b1,4+%0\n\t" \
3838 "movb %4,5+%0\n\t" \
3839 "movb $0,6+%0\n\t" \
3840 "movb %h1,7+%0\n\t" \
3842 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3844 This works great except that the output assembler ends
3845 up looking a bit weird if it turns out that there is
3846 no offset. You end up producing code that looks like:
3859 So here we provide the missing zero. */
3861 *displacement_string_end
= '0';
3865 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3866 if (gotfree_input_line
)
3867 input_line_pointer
= gotfree_input_line
;
3870 exp_seg
= expression (exp
);
3873 if (*input_line_pointer
)
3874 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3876 RESTORE_END_STRING (disp_end
+ 1);
3878 RESTORE_END_STRING (disp_end
);
3879 input_line_pointer
= save_input_line_pointer
;
3881 if (gotfree_input_line
)
3882 free (gotfree_input_line
);
3885 #ifdef BFD_ASSEMBLER
3886 /* We do this to make sure that the section symbol is in
3887 the symbol table. We will ultimately change the relocation
3888 to be relative to the beginning of the section. */
3889 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3890 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3892 if (exp
->X_op
!= O_symbol
)
3894 as_bad (_("bad expression used with @%s"),
3895 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3901 if (S_IS_LOCAL (exp
->X_add_symbol
)
3902 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3903 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3904 exp
->X_op
= O_subtract
;
3905 exp
->X_op_symbol
= GOT_symbol
;
3906 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3907 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3909 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3913 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3915 /* Missing or bad expr becomes absolute 0. */
3916 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3918 exp
->X_op
= O_constant
;
3919 exp
->X_add_number
= 0;
3920 exp
->X_add_symbol
= (symbolS
*) 0;
3921 exp
->X_op_symbol
= (symbolS
*) 0;
3924 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3925 if (exp
->X_op
!= O_constant
3926 #ifdef BFD_ASSEMBLER
3927 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3929 && exp_seg
!= absolute_section
3930 && exp_seg
!= text_section
3931 && exp_seg
!= data_section
3932 && exp_seg
!= bss_section
3933 && exp_seg
!= undefined_section
3934 #ifdef BFD_ASSEMBLER
3935 && !bfd_is_com_section (exp_seg
)
3939 #ifdef BFD_ASSEMBLER
3940 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3942 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3947 else if (flag_code
== CODE_64BIT
)
3948 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3952 static int i386_index_check
PARAMS ((const char *));
3954 /* Make sure the memory operand we've been dealt is valid.
3955 Return 1 on success, 0 on a failure. */
3958 i386_index_check (operand_string
)
3959 const char *operand_string
;
3962 #if INFER_ADDR_PREFIX
3968 if (flag_code
== CODE_64BIT
)
3970 if (i
.prefix
[ADDR_PREFIX
] == 0)
3974 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3975 && (i
.base_reg
->reg_type
!= BaseIndex
3978 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3979 != (Reg64
| BaseIndex
))))
3986 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3988 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3989 != (Reg32
| BaseIndex
))))
3995 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3999 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4000 != (Reg16
| BaseIndex
)))
4002 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4003 != (Reg16
| BaseIndex
))
4005 && i
.base_reg
->reg_num
< 6
4006 && i
.index_reg
->reg_num
>= 6
4007 && i
.log2_scale_factor
== 0))))
4014 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4016 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4017 != (Reg32
| BaseIndex
))))
4023 #if INFER_ADDR_PREFIX
4024 if (flag_code
!= CODE_64BIT
4025 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
4027 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4029 /* Change the size of any displacement too. At most one of
4030 Disp16 or Disp32 is set.
4031 FIXME. There doesn't seem to be any real need for separate
4032 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4033 Removing them would probably clean up the code quite a lot. */
4034 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
4035 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4040 as_bad (_("`%s' is not a valid base/index expression"),
4044 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4046 flag_code_names
[flag_code
]);
4052 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4056 i386_operand (operand_string
)
4057 char *operand_string
;
4061 char *op_string
= operand_string
;
4063 if (is_space_char (*op_string
))
4066 /* We check for an absolute prefix (differentiating,
4067 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4068 if (*op_string
== ABSOLUTE_PREFIX
)
4071 if (is_space_char (*op_string
))
4073 i
.types
[this_operand
] |= JumpAbsolute
;
4076 /* Check if operand is a register. */
4077 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4078 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4080 /* Check for a segment override by searching for ':' after a
4081 segment register. */
4083 if (is_space_char (*op_string
))
4085 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4090 i
.seg
[i
.mem_operands
] = &es
;
4093 i
.seg
[i
.mem_operands
] = &cs
;
4096 i
.seg
[i
.mem_operands
] = &ss
;
4099 i
.seg
[i
.mem_operands
] = &ds
;
4102 i
.seg
[i
.mem_operands
] = &fs
;
4105 i
.seg
[i
.mem_operands
] = &gs
;
4109 /* Skip the ':' and whitespace. */
4111 if (is_space_char (*op_string
))
4114 if (!is_digit_char (*op_string
)
4115 && !is_identifier_char (*op_string
)
4116 && *op_string
!= '('
4117 && *op_string
!= ABSOLUTE_PREFIX
)
4119 as_bad (_("bad memory operand `%s'"), op_string
);
4122 /* Handle case of %es:*foo. */
4123 if (*op_string
== ABSOLUTE_PREFIX
)
4126 if (is_space_char (*op_string
))
4128 i
.types
[this_operand
] |= JumpAbsolute
;
4130 goto do_memory_reference
;
4134 as_bad (_("junk `%s' after register"), op_string
);
4137 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4138 i
.op
[this_operand
].regs
= r
;
4141 else if (*op_string
== REGISTER_PREFIX
)
4143 as_bad (_("bad register name `%s'"), op_string
);
4146 else if (*op_string
== IMMEDIATE_PREFIX
)
4149 if (i
.types
[this_operand
] & JumpAbsolute
)
4151 as_bad (_("immediate operand illegal with absolute jump"));
4154 if (!i386_immediate (op_string
))
4157 else if (is_digit_char (*op_string
)
4158 || is_identifier_char (*op_string
)
4159 || *op_string
== '(')
4161 /* This is a memory reference of some sort. */
4164 /* Start and end of displacement string expression (if found). */
4165 char *displacement_string_start
;
4166 char *displacement_string_end
;
4168 do_memory_reference
:
4169 if ((i
.mem_operands
== 1
4170 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4171 || i
.mem_operands
== 2)
4173 as_bad (_("too many memory references for `%s'"),
4174 current_templates
->start
->name
);
4178 /* Check for base index form. We detect the base index form by
4179 looking for an ')' at the end of the operand, searching
4180 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4182 base_string
= op_string
+ strlen (op_string
);
4185 if (is_space_char (*base_string
))
4188 /* If we only have a displacement, set-up for it to be parsed later. */
4189 displacement_string_start
= op_string
;
4190 displacement_string_end
= base_string
+ 1;
4192 if (*base_string
== ')')
4195 unsigned int parens_balanced
= 1;
4196 /* We've already checked that the number of left & right ()'s are
4197 equal, so this loop will not be infinite. */
4201 if (*base_string
== ')')
4203 if (*base_string
== '(')
4206 while (parens_balanced
);
4208 temp_string
= base_string
;
4210 /* Skip past '(' and whitespace. */
4212 if (is_space_char (*base_string
))
4215 if (*base_string
== ','
4216 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4217 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4219 displacement_string_end
= temp_string
;
4221 i
.types
[this_operand
] |= BaseIndex
;
4225 base_string
= end_op
;
4226 if (is_space_char (*base_string
))
4230 /* There may be an index reg or scale factor here. */
4231 if (*base_string
== ',')
4234 if (is_space_char (*base_string
))
4237 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4238 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4240 base_string
= end_op
;
4241 if (is_space_char (*base_string
))
4243 if (*base_string
== ',')
4246 if (is_space_char (*base_string
))
4249 else if (*base_string
!= ')')
4251 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4256 else if (*base_string
== REGISTER_PREFIX
)
4258 as_bad (_("bad register name `%s'"), base_string
);
4262 /* Check for scale factor. */
4263 if (*base_string
!= ')')
4265 char *end_scale
= i386_scale (base_string
);
4270 base_string
= end_scale
;
4271 if (is_space_char (*base_string
))
4273 if (*base_string
!= ')')
4275 as_bad (_("expecting `)' after scale factor in `%s'"),
4280 else if (!i
.index_reg
)
4282 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4287 else if (*base_string
!= ')')
4289 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4294 else if (*base_string
== REGISTER_PREFIX
)
4296 as_bad (_("bad register name `%s'"), base_string
);
4301 /* If there's an expression beginning the operand, parse it,
4302 assuming displacement_string_start and
4303 displacement_string_end are meaningful. */
4304 if (displacement_string_start
!= displacement_string_end
)
4306 if (!i386_displacement (displacement_string_start
,
4307 displacement_string_end
))
4311 /* Special case for (%dx) while doing input/output op. */
4313 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4315 && i
.log2_scale_factor
== 0
4316 && i
.seg
[i
.mem_operands
] == 0
4317 && (i
.types
[this_operand
] & Disp
) == 0)
4319 i
.types
[this_operand
] = InOutPortReg
;
4323 if (i386_index_check (operand_string
) == 0)
4329 /* It's not a memory operand; argh! */
4330 as_bad (_("invalid char %s beginning operand %d `%s'"),
4331 output_invalid (*op_string
),
4336 return 1; /* Normal return. */
4339 /* md_estimate_size_before_relax()
4341 Called just before relax() for rs_machine_dependent frags. The x86
4342 assembler uses these frags to handle variable size jump
4345 Any symbol that is now undefined will not become defined.
4346 Return the correct fr_subtype in the frag.
4347 Return the initial "guess for variable size of frag" to caller.
4348 The guess is actually the growth beyond the fixed part. Whatever
4349 we do to grow the fixed or variable part contributes to our
4353 md_estimate_size_before_relax (fragP
, segment
)
4357 /* We've already got fragP->fr_subtype right; all we have to do is
4358 check for un-relaxable symbols. On an ELF system, we can't relax
4359 an externally visible symbol, because it may be overridden by a
4361 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4363 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4364 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4365 || S_IS_WEAK (fragP
->fr_symbol
)))
4369 /* Symbol is undefined in this segment, or we need to keep a
4370 reloc so that weak symbols can be overridden. */
4371 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4372 RELOC_ENUM reloc_type
;
4373 unsigned char *opcode
;
4376 if (fragP
->fr_var
!= NO_RELOC
)
4377 reloc_type
= fragP
->fr_var
;
4379 reloc_type
= BFD_RELOC_16_PCREL
;
4381 reloc_type
= BFD_RELOC_32_PCREL
;
4383 old_fr_fix
= fragP
->fr_fix
;
4384 opcode
= (unsigned char *) fragP
->fr_opcode
;
4386 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4389 /* Make jmp (0xeb) a (d)word displacement jump. */
4391 fragP
->fr_fix
+= size
;
4392 fix_new (fragP
, old_fr_fix
, size
,
4394 fragP
->fr_offset
, 1,
4400 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4402 /* Negate the condition, and branch past an
4403 unconditional jump. */
4406 /* Insert an unconditional jump. */
4408 /* We added two extra opcode bytes, and have a two byte
4410 fragP
->fr_fix
+= 2 + 2;
4411 fix_new (fragP
, old_fr_fix
+ 2, 2,
4413 fragP
->fr_offset
, 1,
4420 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4425 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4427 fragP
->fr_offset
, 1,
4429 fixP
->fx_signed
= 1;
4433 /* This changes the byte-displacement jump 0x7N
4434 to the (d)word-displacement jump 0x0f,0x8N. */
4435 opcode
[1] = opcode
[0] + 0x10;
4436 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4437 /* We've added an opcode byte. */
4438 fragP
->fr_fix
+= 1 + size
;
4439 fix_new (fragP
, old_fr_fix
+ 1, size
,
4441 fragP
->fr_offset
, 1,
4446 BAD_CASE (fragP
->fr_subtype
);
4450 return fragP
->fr_fix
- old_fr_fix
;
4453 /* Guess size depending on current relax state. Initially the relax
4454 state will correspond to a short jump and we return 1, because
4455 the variable part of the frag (the branch offset) is one byte
4456 long. However, we can relax a section more than once and in that
4457 case we must either set fr_subtype back to the unrelaxed state,
4458 or return the value for the appropriate branch. */
4459 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4462 /* Called after relax() is finished.
4464 In: Address of frag.
4465 fr_type == rs_machine_dependent.
4466 fr_subtype is what the address relaxed to.
4468 Out: Any fixSs and constants are set up.
4469 Caller will turn frag into a ".space 0". */
4471 #ifndef BFD_ASSEMBLER
4473 md_convert_frag (headers
, sec
, fragP
)
4474 object_headers
*headers ATTRIBUTE_UNUSED
;
4475 segT sec ATTRIBUTE_UNUSED
;
4479 md_convert_frag (abfd
, sec
, fragP
)
4480 bfd
*abfd ATTRIBUTE_UNUSED
;
4481 segT sec ATTRIBUTE_UNUSED
;
4485 unsigned char *opcode
;
4486 unsigned char *where_to_put_displacement
= NULL
;
4487 offsetT target_address
;
4488 offsetT opcode_address
;
4489 unsigned int extension
= 0;
4490 offsetT displacement_from_opcode_start
;
4492 opcode
= (unsigned char *) fragP
->fr_opcode
;
4494 /* Address we want to reach in file space. */
4495 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4497 /* Address opcode resides at in file space. */
4498 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4500 /* Displacement from opcode start to fill into instruction. */
4501 displacement_from_opcode_start
= target_address
- opcode_address
;
4503 if ((fragP
->fr_subtype
& BIG
) == 0)
4505 /* Don't have to change opcode. */
4506 extension
= 1; /* 1 opcode + 1 displacement */
4507 where_to_put_displacement
= &opcode
[1];
4511 if (no_cond_jump_promotion
4512 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4513 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4515 switch (fragP
->fr_subtype
)
4517 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4518 extension
= 4; /* 1 opcode + 4 displacement */
4520 where_to_put_displacement
= &opcode
[1];
4523 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4524 extension
= 2; /* 1 opcode + 2 displacement */
4526 where_to_put_displacement
= &opcode
[1];
4529 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4530 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4531 extension
= 5; /* 2 opcode + 4 displacement */
4532 opcode
[1] = opcode
[0] + 0x10;
4533 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4534 where_to_put_displacement
= &opcode
[2];
4537 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4538 extension
= 3; /* 2 opcode + 2 displacement */
4539 opcode
[1] = opcode
[0] + 0x10;
4540 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4541 where_to_put_displacement
= &opcode
[2];
4544 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4549 where_to_put_displacement
= &opcode
[3];
4553 BAD_CASE (fragP
->fr_subtype
);
4558 /* Now put displacement after opcode. */
4559 md_number_to_chars ((char *) where_to_put_displacement
,
4560 (valueT
) (displacement_from_opcode_start
- extension
),
4561 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4562 fragP
->fr_fix
+= extension
;
4565 /* Size of byte displacement jmp. */
4566 int md_short_jump_size
= 2;
4568 /* Size of dword displacement jmp. */
4569 int md_long_jump_size
= 5;
4571 /* Size of relocation record. */
4572 const int md_reloc_size
= 8;
4575 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4577 addressT from_addr
, to_addr
;
4578 fragS
*frag ATTRIBUTE_UNUSED
;
4579 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4583 offset
= to_addr
- (from_addr
+ 2);
4584 /* Opcode for byte-disp jump. */
4585 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4586 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4590 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4592 addressT from_addr
, to_addr
;
4593 fragS
*frag ATTRIBUTE_UNUSED
;
4594 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4598 offset
= to_addr
- (from_addr
+ 5);
4599 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4600 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4603 /* Apply a fixup (fixS) to segment data, once it has been determined
4604 by our caller that we have all the info we need to fix it up.
4606 On the 386, immediates, displacements, and data pointers are all in
4607 the same (little-endian) format, so we don't need to care about which
4611 md_apply_fix3 (fixP
, valP
, seg
)
4612 /* The fix we're to put in. */
4614 /* Pointer to the value of the bits. */
4616 /* Segment fix is from. */
4617 segT seg ATTRIBUTE_UNUSED
;
4619 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4620 valueT value
= *valP
;
4622 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4625 switch (fixP
->fx_r_type
)
4631 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4634 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4637 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4642 if (fixP
->fx_addsy
!= NULL
4643 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4644 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4645 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4646 && !use_rela_relocations
)
4648 /* This is a hack. There should be a better way to handle this.
4649 This covers for the fact that bfd_install_relocation will
4650 subtract the current location (for partial_inplace, PC relative
4651 relocations); see more below. */
4653 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4655 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4658 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4661 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4663 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4666 || (symbol_section_p (fixP
->fx_addsy
)
4667 && sym_seg
!= absolute_section
))
4668 && !generic_force_reloc (fixP
))
4670 /* Yes, we add the values in twice. This is because
4671 bfd_install_relocation subtracts them out again. I think
4672 bfd_install_relocation is broken, but I don't dare change
4674 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4678 #if defined (OBJ_COFF) && defined (TE_PE)
4679 /* For some reason, the PE format does not store a section
4680 address offset for a PC relative symbol. */
4681 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4682 value
+= md_pcrel_from (fixP
);
4686 /* Fix a few things - the dynamic linker expects certain values here,
4687 and we must not dissappoint it. */
4688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4689 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4691 switch (fixP
->fx_r_type
)
4693 case BFD_RELOC_386_PLT32
:
4694 case BFD_RELOC_X86_64_PLT32
:
4695 /* Make the jump instruction point to the address of the operand. At
4696 runtime we merely add the offset to the actual PLT entry. */
4700 case BFD_RELOC_386_TLS_GD
:
4701 case BFD_RELOC_386_TLS_LDM
:
4702 case BFD_RELOC_386_TLS_IE_32
:
4703 case BFD_RELOC_386_TLS_IE
:
4704 case BFD_RELOC_386_TLS_GOTIE
:
4705 case BFD_RELOC_X86_64_TLSGD
:
4706 case BFD_RELOC_X86_64_TLSLD
:
4707 case BFD_RELOC_X86_64_GOTTPOFF
:
4708 value
= 0; /* Fully resolved at runtime. No addend. */
4710 case BFD_RELOC_386_TLS_LE
:
4711 case BFD_RELOC_386_TLS_LDO_32
:
4712 case BFD_RELOC_386_TLS_LE_32
:
4713 case BFD_RELOC_X86_64_DTPOFF32
:
4714 case BFD_RELOC_X86_64_TPOFF32
:
4715 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4718 case BFD_RELOC_386_GOT32
:
4719 case BFD_RELOC_X86_64_GOT32
:
4720 value
= 0; /* Fully resolved at runtime. No addend. */
4723 case BFD_RELOC_VTABLE_INHERIT
:
4724 case BFD_RELOC_VTABLE_ENTRY
:
4731 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4733 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4735 /* Are we finished with this relocation now? */
4736 if (fixP
->fx_addsy
== NULL
)
4738 #ifdef BFD_ASSEMBLER
4739 else if (use_rela_relocations
)
4741 fixP
->fx_no_overflow
= 1;
4742 /* Remember value for tc_gen_reloc. */
4743 fixP
->fx_addnumber
= value
;
4747 md_number_to_chars (p
, value
, fixP
->fx_size
);
4750 #define MAX_LITTLENUMS 6
4752 /* Turn the string pointed to by litP into a floating point constant
4753 of type TYPE, and emit the appropriate bytes. The number of
4754 LITTLENUMS emitted is stored in *SIZEP. An error message is
4755 returned, or NULL on OK. */
4758 md_atof (type
, litP
, sizeP
)
4764 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4765 LITTLENUM_TYPE
*wordP
;
4787 return _("Bad call to md_atof ()");
4789 t
= atof_ieee (input_line_pointer
, type
, words
);
4791 input_line_pointer
= t
;
4793 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4794 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4795 the bigendian 386. */
4796 for (wordP
= words
+ prec
- 1; prec
--;)
4798 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4799 litP
+= sizeof (LITTLENUM_TYPE
);
4804 char output_invalid_buf
[8];
4811 sprintf (output_invalid_buf
, "'%c'", c
);
4813 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4814 return output_invalid_buf
;
4817 /* REG_STRING starts *before* REGISTER_PREFIX. */
4819 static const reg_entry
*
4820 parse_register (reg_string
, end_op
)
4824 char *s
= reg_string
;
4826 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4829 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4830 if (*s
== REGISTER_PREFIX
)
4833 if (is_space_char (*s
))
4837 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4839 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4840 return (const reg_entry
*) NULL
;
4844 /* For naked regs, make sure that we are not dealing with an identifier.
4845 This prevents confusing an identifier like `eax_var' with register
4847 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4848 return (const reg_entry
*) NULL
;
4852 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4854 /* Handle floating point regs, allowing spaces in the (i) part. */
4855 if (r
== i386_regtab
/* %st is first entry of table */)
4857 if (is_space_char (*s
))
4862 if (is_space_char (*s
))
4864 if (*s
>= '0' && *s
<= '7')
4866 r
= &i386_float_regtab
[*s
- '0'];
4868 if (is_space_char (*s
))
4876 /* We have "%st(" then garbage. */
4877 return (const reg_entry
*) NULL
;
4882 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4883 && flag_code
!= CODE_64BIT
)
4885 return (const reg_entry
*) NULL
;
4891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4892 const char *md_shortopts
= "kVQ:sq";
4894 const char *md_shortopts
= "q";
4897 struct option md_longopts
[] = {
4898 #define OPTION_32 (OPTION_MD_BASE + 0)
4899 {"32", no_argument
, NULL
, OPTION_32
},
4900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4901 #define OPTION_64 (OPTION_MD_BASE + 1)
4902 {"64", no_argument
, NULL
, OPTION_64
},
4904 {NULL
, no_argument
, NULL
, 0}
4906 size_t md_longopts_size
= sizeof (md_longopts
);
4909 md_parse_option (c
, arg
)
4911 char *arg ATTRIBUTE_UNUSED
;
4919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4920 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4921 should be emitted or not. FIXME: Not implemented. */
4925 /* -V: SVR4 argument to print version ID. */
4927 print_version_id ();
4930 /* -k: Ignore for FreeBSD compatibility. */
4935 /* -s: On i386 Solaris, this tells the native assembler to use
4936 .stab instead of .stab.excl. We always use .stab anyhow. */
4941 const char **list
, **l
;
4943 list
= bfd_target_list ();
4944 for (l
= list
; *l
!= NULL
; l
++)
4945 if (strcmp (*l
, "elf64-x86-64") == 0)
4947 default_arch
= "x86_64";
4951 as_fatal (_("No compiled in support for x86_64"));
4958 default_arch
= "i386";
4968 md_show_usage (stream
)
4971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4972 fprintf (stream
, _("\
4974 -V print assembler version number\n\
4976 -q quieten some warnings\n\
4979 fprintf (stream
, _("\
4980 -q quieten some warnings\n"));
4984 #ifdef BFD_ASSEMBLER
4985 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4986 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4988 /* Pick the target format to use. */
4991 i386_target_format ()
4993 if (!strcmp (default_arch
, "x86_64"))
4994 set_code_flag (CODE_64BIT
);
4995 else if (!strcmp (default_arch
, "i386"))
4996 set_code_flag (CODE_32BIT
);
4998 as_fatal (_("Unknown architecture"));
4999 switch (OUTPUT_FLAVOR
)
5001 #ifdef OBJ_MAYBE_AOUT
5002 case bfd_target_aout_flavour
:
5003 return AOUT_TARGET_FORMAT
;
5005 #ifdef OBJ_MAYBE_COFF
5006 case bfd_target_coff_flavour
:
5009 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5010 case bfd_target_elf_flavour
:
5012 if (flag_code
== CODE_64BIT
)
5013 use_rela_relocations
= 1;
5014 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5023 #endif /* OBJ_MAYBE_ more than one */
5025 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5026 void i386_elf_emit_arch_note ()
5028 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5029 && cpu_arch_name
!= NULL
)
5032 asection
*seg
= now_seg
;
5033 subsegT subseg
= now_subseg
;
5034 Elf_Internal_Note i_note
;
5035 Elf_External_Note e_note
;
5036 asection
*note_secp
;
5039 /* Create the .note section. */
5040 note_secp
= subseg_new (".note", 0);
5041 bfd_set_section_flags (stdoutput
,
5043 SEC_HAS_CONTENTS
| SEC_READONLY
);
5045 /* Process the arch string. */
5046 len
= strlen (cpu_arch_name
);
5048 i_note
.namesz
= len
+ 1;
5050 i_note
.type
= NT_ARCH
;
5051 p
= frag_more (sizeof (e_note
.namesz
));
5052 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5053 p
= frag_more (sizeof (e_note
.descsz
));
5054 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5055 p
= frag_more (sizeof (e_note
.type
));
5056 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5057 p
= frag_more (len
+ 1);
5058 strcpy (p
, cpu_arch_name
);
5060 frag_align (2, 0, 0);
5062 subseg_set (seg
, subseg
);
5066 #endif /* BFD_ASSEMBLER */
5069 md_undefined_symbol (name
)
5072 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5073 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5074 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5075 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5079 if (symbol_find (name
))
5080 as_bad (_("GOT already in symbol table"));
5081 GOT_symbol
= symbol_new (name
, undefined_section
,
5082 (valueT
) 0, &zero_address_frag
);
5089 /* Round up a section size to the appropriate boundary. */
5092 md_section_align (segment
, size
)
5093 segT segment ATTRIBUTE_UNUSED
;
5096 #ifdef BFD_ASSEMBLER
5097 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5098 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5100 /* For a.out, force the section size to be aligned. If we don't do
5101 this, BFD will align it for us, but it will not write out the
5102 final bytes of the section. This may be a bug in BFD, but it is
5103 easier to fix it here since that is how the other a.out targets
5107 align
= bfd_get_section_alignment (stdoutput
, segment
);
5108 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5116 /* On the i386, PC-relative offsets are relative to the start of the
5117 next instruction. That is, the address of the offset, plus its
5118 size, since the offset is always the last part of the insn. */
5121 md_pcrel_from (fixP
)
5124 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5131 int ignore ATTRIBUTE_UNUSED
;
5135 temp
= get_absolute_expression ();
5136 subseg_set (bss_section
, (subsegT
) temp
);
5137 demand_empty_rest_of_line ();
5142 #ifdef BFD_ASSEMBLER
5145 i386_validate_fix (fixp
)
5148 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5150 /* GOTOFF relocation are nonsense in 64bit mode. */
5151 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5153 if (flag_code
!= CODE_64BIT
)
5155 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5159 if (flag_code
== CODE_64BIT
)
5161 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5168 tc_gen_reloc (section
, fixp
)
5169 asection
*section ATTRIBUTE_UNUSED
;
5173 bfd_reloc_code_real_type code
;
5175 switch (fixp
->fx_r_type
)
5177 case BFD_RELOC_X86_64_PLT32
:
5178 case BFD_RELOC_X86_64_GOT32
:
5179 case BFD_RELOC_X86_64_GOTPCREL
:
5180 case BFD_RELOC_386_PLT32
:
5181 case BFD_RELOC_386_GOT32
:
5182 case BFD_RELOC_386_GOTOFF
:
5183 case BFD_RELOC_386_GOTPC
:
5184 case BFD_RELOC_386_TLS_GD
:
5185 case BFD_RELOC_386_TLS_LDM
:
5186 case BFD_RELOC_386_TLS_LDO_32
:
5187 case BFD_RELOC_386_TLS_IE_32
:
5188 case BFD_RELOC_386_TLS_IE
:
5189 case BFD_RELOC_386_TLS_GOTIE
:
5190 case BFD_RELOC_386_TLS_LE_32
:
5191 case BFD_RELOC_386_TLS_LE
:
5192 case BFD_RELOC_X86_64_32S
:
5193 case BFD_RELOC_X86_64_TLSGD
:
5194 case BFD_RELOC_X86_64_TLSLD
:
5195 case BFD_RELOC_X86_64_DTPOFF32
:
5196 case BFD_RELOC_X86_64_GOTTPOFF
:
5197 case BFD_RELOC_X86_64_TPOFF32
:
5199 case BFD_RELOC_VTABLE_ENTRY
:
5200 case BFD_RELOC_VTABLE_INHERIT
:
5201 code
= fixp
->fx_r_type
;
5206 switch (fixp
->fx_size
)
5209 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5210 _("can not do %d byte pc-relative relocation"),
5212 code
= BFD_RELOC_32_PCREL
;
5214 case 1: code
= BFD_RELOC_8_PCREL
; break;
5215 case 2: code
= BFD_RELOC_16_PCREL
; break;
5216 case 4: code
= BFD_RELOC_32_PCREL
; break;
5221 switch (fixp
->fx_size
)
5224 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5225 _("can not do %d byte relocation"),
5227 code
= BFD_RELOC_32
;
5229 case 1: code
= BFD_RELOC_8
; break;
5230 case 2: code
= BFD_RELOC_16
; break;
5231 case 4: code
= BFD_RELOC_32
; break;
5233 case 8: code
= BFD_RELOC_64
; break;
5240 if (code
== BFD_RELOC_32
5242 && fixp
->fx_addsy
== GOT_symbol
)
5244 /* We don't support GOTPC on 64bit targets. */
5245 if (flag_code
== CODE_64BIT
)
5247 code
= BFD_RELOC_386_GOTPC
;
5250 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5251 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5252 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5254 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5255 if (!use_rela_relocations
)
5257 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5258 vtable entry to be used in the relocation's section offset. */
5259 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5260 rel
->address
= fixp
->fx_offset
;
5264 /* Use the rela in 64bit mode. */
5267 if (!fixp
->fx_pcrel
)
5268 rel
->addend
= fixp
->fx_offset
;
5272 case BFD_RELOC_X86_64_PLT32
:
5273 case BFD_RELOC_X86_64_GOT32
:
5274 case BFD_RELOC_X86_64_GOTPCREL
:
5275 case BFD_RELOC_X86_64_TLSGD
:
5276 case BFD_RELOC_X86_64_TLSLD
:
5277 case BFD_RELOC_X86_64_GOTTPOFF
:
5278 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5281 rel
->addend
= (section
->vma
5283 + fixp
->fx_addnumber
5284 + md_pcrel_from (fixp
));
5289 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5290 if (rel
->howto
== NULL
)
5292 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5293 _("cannot represent relocation type %s"),
5294 bfd_get_reloc_code_name (code
));
5295 /* Set howto to a garbage value so that we can keep going. */
5296 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5297 assert (rel
->howto
!= NULL
);
5303 #else /* !BFD_ASSEMBLER */
5305 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5307 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5310 relax_addressT segment_address_in_file
;
5312 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5313 Out: GNU LD relocation length code: 0, 1, or 2. */
5315 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5318 know (fixP
->fx_addsy
!= NULL
);
5320 md_number_to_chars (where
,
5321 (valueT
) (fixP
->fx_frag
->fr_address
5322 + fixP
->fx_where
- segment_address_in_file
),
5325 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5326 ? S_GET_TYPE (fixP
->fx_addsy
)
5327 : fixP
->fx_addsy
->sy_number
);
5329 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5330 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5331 where
[4] = r_symbolnum
& 0x0ff;
5332 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5333 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5334 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5337 #endif /* OBJ_AOUT or OBJ_BOUT. */
5339 #if defined (I386COFF)
5342 tc_coff_fix2rtype (fixP
)
5345 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5348 return (fixP
->fx_pcrel
?
5349 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5350 fixP
->fx_size
== 2 ? R_PCRWORD
:
5352 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5353 fixP
->fx_size
== 2 ? R_RELWORD
:
5358 tc_coff_sizemachdep (frag
)
5362 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5367 #endif /* I386COFF */
5369 #endif /* !BFD_ASSEMBLER */
5371 /* Parse operands using Intel syntax. This implements a recursive descent
5372 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5375 FIXME: We do not recognize the full operand grammar defined in the MASM
5376 documentation. In particular, all the structure/union and
5377 high-level macro operands are missing.
5379 Uppercase words are terminals, lower case words are non-terminals.
5380 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5381 bars '|' denote choices. Most grammar productions are implemented in
5382 functions called 'intel_<production>'.
5384 Initial production is 'expr'.
5390 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5392 constant digits [[ radixOverride ]]
5394 dataType BYTE | WORD | DWORD | QWORD | XWORD
5427 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5428 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5430 hexdigit a | b | c | d | e | f
5431 | A | B | C | D | E | F
5441 register specialRegister
5445 segmentRegister CS | DS | ES | FS | GS | SS
5447 specialRegister CR0 | CR2 | CR3
5448 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5449 | TR3 | TR4 | TR5 | TR6 | TR7
5451 We simplify the grammar in obvious places (e.g., register parsing is
5452 done by calling parse_register) and eliminate immediate left recursion
5453 to implement a recursive-descent parser.
5493 /* Parsing structure for the intel syntax parser. Used to implement the
5494 semantic actions for the operand grammar. */
5495 struct intel_parser_s
5497 char *op_string
; /* The string being parsed. */
5498 int got_a_float
; /* Whether the operand is a float. */
5499 int op_modifier
; /* Operand modifier. */
5500 int is_mem
; /* 1 if operand is memory reference. */
5501 const reg_entry
*reg
; /* Last register reference found. */
5502 char *disp
; /* Displacement string being built. */
5505 static struct intel_parser_s intel_parser
;
5507 /* Token structure for parsing intel syntax. */
5510 int code
; /* Token code. */
5511 const reg_entry
*reg
; /* Register entry for register tokens. */
5512 char *str
; /* String representation. */
5515 static struct intel_token cur_token
, prev_token
;
5517 /* Token codes for the intel parser. Since T_SHORT is already used
5518 by COFF, undefine it first to prevent a warning. */
5533 /* Prototypes for intel parser functions. */
5534 static int intel_match_token
PARAMS ((int code
));
5535 static void intel_get_token
PARAMS ((void));
5536 static void intel_putback_token
PARAMS ((void));
5537 static int intel_expr
PARAMS ((void));
5538 static int intel_e05
PARAMS ((void));
5539 static int intel_e05_1
PARAMS ((void));
5540 static int intel_e06
PARAMS ((void));
5541 static int intel_e06_1
PARAMS ((void));
5542 static int intel_e09
PARAMS ((void));
5543 static int intel_e09_1
PARAMS ((void));
5544 static int intel_e10
PARAMS ((void));
5545 static int intel_e10_1
PARAMS ((void));
5546 static int intel_e11
PARAMS ((void));
5549 i386_intel_operand (operand_string
, got_a_float
)
5550 char *operand_string
;
5556 /* Initialize token holders. */
5557 cur_token
.code
= prev_token
.code
= T_NIL
;
5558 cur_token
.reg
= prev_token
.reg
= NULL
;
5559 cur_token
.str
= prev_token
.str
= NULL
;
5561 /* Initialize parser structure. */
5562 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5565 strcpy (intel_parser
.op_string
, operand_string
);
5566 intel_parser
.got_a_float
= got_a_float
;
5567 intel_parser
.op_modifier
= -1;
5568 intel_parser
.is_mem
= 0;
5569 intel_parser
.reg
= NULL
;
5570 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5571 if (intel_parser
.disp
== NULL
)
5573 intel_parser
.disp
[0] = '\0';
5575 /* Read the first token and start the parser. */
5577 ret
= intel_expr ();
5581 /* If we found a memory reference, hand it over to i386_displacement
5582 to fill in the rest of the operand fields. */
5583 if (intel_parser
.is_mem
)
5585 if ((i
.mem_operands
== 1
5586 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5587 || i
.mem_operands
== 2)
5589 as_bad (_("too many memory references for '%s'"),
5590 current_templates
->start
->name
);
5595 char *s
= intel_parser
.disp
;
5598 /* Add the displacement expression. */
5600 ret
= i386_displacement (s
, s
+ strlen (s
))
5601 && i386_index_check (s
);
5605 /* Constant and OFFSET expressions are handled by i386_immediate. */
5606 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5607 || intel_parser
.reg
== NULL
)
5608 ret
= i386_immediate (intel_parser
.disp
);
5612 free (intel_parser
.disp
);
5622 /* expr SHORT e05 */
5623 if (cur_token
.code
== T_SHORT
)
5625 intel_parser
.op_modifier
= SHORT
;
5626 intel_match_token (T_SHORT
);
5628 return (intel_e05 ());
5633 return intel_e05 ();
5643 return (intel_e06 () && intel_e05_1 ());
5649 /* e05' addOp e06 e05' */
5650 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5652 strcat (intel_parser
.disp
, cur_token
.str
);
5653 intel_match_token (cur_token
.code
);
5655 return (intel_e06 () && intel_e05_1 ());
5670 return (intel_e09 () && intel_e06_1 ());
5676 /* e06' mulOp e09 e06' */
5677 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5679 strcat (intel_parser
.disp
, cur_token
.str
);
5680 intel_match_token (cur_token
.code
);
5682 return (intel_e09 () && intel_e06_1 ());
5690 /* e09 OFFSET e10 e09'
5699 /* e09 OFFSET e10 e09' */
5700 if (cur_token
.code
== T_OFFSET
)
5702 intel_parser
.is_mem
= 0;
5703 intel_parser
.op_modifier
= OFFSET_FLAT
;
5704 intel_match_token (T_OFFSET
);
5706 return (intel_e10 () && intel_e09_1 ());
5711 return (intel_e10 () && intel_e09_1 ());
5717 /* e09' PTR e10 e09' */
5718 if (cur_token
.code
== T_PTR
)
5720 if (prev_token
.code
== T_BYTE
)
5721 i
.suffix
= BYTE_MNEM_SUFFIX
;
5723 else if (prev_token
.code
== T_WORD
)
5725 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5726 i
.suffix
= SHORT_MNEM_SUFFIX
;
5728 i
.suffix
= WORD_MNEM_SUFFIX
;
5731 else if (prev_token
.code
== T_DWORD
)
5733 if (intel_parser
.got_a_float
== 1) /* "f..." */
5734 i
.suffix
= SHORT_MNEM_SUFFIX
;
5736 i
.suffix
= LONG_MNEM_SUFFIX
;
5739 else if (prev_token
.code
== T_QWORD
)
5741 if (intel_parser
.got_a_float
== 1) /* "f..." */
5742 i
.suffix
= LONG_MNEM_SUFFIX
;
5744 i
.suffix
= QWORD_MNEM_SUFFIX
;
5747 else if (prev_token
.code
== T_XWORD
)
5748 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5752 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5756 intel_match_token (T_PTR
);
5758 return (intel_e10 () && intel_e09_1 ());
5761 /* e09 : e10 e09' */
5762 else if (cur_token
.code
== ':')
5764 /* Mark as a memory operand only if it's not already known to be an
5765 offset expression. */
5766 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5767 intel_parser
.is_mem
= 1;
5769 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5784 return (intel_e11 () && intel_e10_1 ());
5790 /* e10' [ expr ] e10' */
5791 if (cur_token
.code
== '[')
5793 intel_match_token ('[');
5795 /* Mark as a memory operand only if it's not already known to be an
5796 offset expression. If it's an offset expression, we need to keep
5798 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5799 intel_parser
.is_mem
= 1;
5801 strcat (intel_parser
.disp
, "[");
5803 /* Add a '+' to the displacement string if necessary. */
5804 if (*intel_parser
.disp
!= '\0'
5805 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5806 strcat (intel_parser
.disp
, "+");
5808 if (intel_expr () && intel_match_token (']'))
5810 /* Preserve brackets when the operand is an offset expression. */
5811 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5812 strcat (intel_parser
.disp
, "]");
5814 return intel_e10_1 ();
5841 if (cur_token
.code
== '(')
5843 intel_match_token ('(');
5844 strcat (intel_parser
.disp
, "(");
5846 if (intel_expr () && intel_match_token (')'))
5848 strcat (intel_parser
.disp
, ")");
5856 else if (cur_token
.code
== '[')
5858 intel_match_token ('[');
5860 /* Mark as a memory operand only if it's not already known to be an
5861 offset expression. If it's an offset expression, we need to keep
5863 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5864 intel_parser
.is_mem
= 1;
5866 strcat (intel_parser
.disp
, "[");
5868 /* Operands for jump/call inside brackets denote absolute addresses. */
5869 if (current_templates
->start
->opcode_modifier
& Jump
5870 || current_templates
->start
->opcode_modifier
& JumpDword
5871 || current_templates
->start
->opcode_modifier
& JumpByte
5872 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5873 i
.types
[this_operand
] |= JumpAbsolute
;
5875 /* Add a '+' to the displacement string if necessary. */
5876 if (*intel_parser
.disp
!= '\0'
5877 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5878 strcat (intel_parser
.disp
, "+");
5880 if (intel_expr () && intel_match_token (']'))
5882 /* Preserve brackets when the operand is an offset expression. */
5883 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5884 strcat (intel_parser
.disp
, "]");
5897 else if (cur_token
.code
== T_BYTE
5898 || cur_token
.code
== T_WORD
5899 || cur_token
.code
== T_DWORD
5900 || cur_token
.code
== T_QWORD
5901 || cur_token
.code
== T_XWORD
)
5903 intel_match_token (cur_token
.code
);
5910 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5912 strcat (intel_parser
.disp
, cur_token
.str
);
5913 intel_match_token (cur_token
.code
);
5915 /* Mark as a memory operand only if it's not already known to be an
5916 offset expression. */
5917 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5918 intel_parser
.is_mem
= 1;
5924 else if (cur_token
.code
== T_REG
)
5926 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5928 intel_match_token (T_REG
);
5930 /* Check for segment change. */
5931 if (cur_token
.code
== ':')
5933 if (reg
->reg_type
& (SReg2
| SReg3
))
5935 switch (reg
->reg_num
)
5938 i
.seg
[i
.mem_operands
] = &es
;
5941 i
.seg
[i
.mem_operands
] = &cs
;
5944 i
.seg
[i
.mem_operands
] = &ss
;
5947 i
.seg
[i
.mem_operands
] = &ds
;
5950 i
.seg
[i
.mem_operands
] = &fs
;
5953 i
.seg
[i
.mem_operands
] = &gs
;
5959 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5964 /* Not a segment register. Check for register scaling. */
5965 else if (cur_token
.code
== '*')
5967 if (!intel_parser
.is_mem
)
5969 as_bad (_("Register scaling only allowed in memory operands."));
5973 /* What follows must be a valid scale. */
5974 if (intel_match_token ('*')
5975 && strchr ("01248", *cur_token
.str
))
5978 i
.types
[this_operand
] |= BaseIndex
;
5980 /* Set the scale after setting the register (otherwise,
5981 i386_scale will complain) */
5982 i386_scale (cur_token
.str
);
5983 intel_match_token (T_CONST
);
5987 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5993 /* No scaling. If this is a memory operand, the register is either a
5994 base register (first occurrence) or an index register (second
5996 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5998 if (i
.base_reg
&& i
.index_reg
)
6000 as_bad (_("Too many register references in memory operand.\n"));
6004 if (i
.base_reg
== NULL
)
6009 i
.types
[this_operand
] |= BaseIndex
;
6012 /* Offset modifier. Add the register to the displacement string to be
6013 parsed as an immediate expression after we're done. */
6014 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
6015 strcat (intel_parser
.disp
, reg
->reg_name
);
6017 /* It's neither base nor index nor offset. */
6020 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6021 i
.op
[this_operand
].regs
= reg
;
6025 /* Since registers are not part of the displacement string (except
6026 when we're parsing offset operands), we may need to remove any
6027 preceding '+' from the displacement string. */
6028 if (*intel_parser
.disp
!= '\0'
6029 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
6031 char *s
= intel_parser
.disp
;
6032 s
+= strlen (s
) - 1;
6041 else if (cur_token
.code
== T_ID
)
6043 /* Add the identifier to the displacement string. */
6044 strcat (intel_parser
.disp
, cur_token
.str
);
6045 intel_match_token (T_ID
);
6047 /* The identifier represents a memory reference only if it's not
6048 preceded by an offset modifier. */
6049 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6050 intel_parser
.is_mem
= 1;
6056 else if (cur_token
.code
== T_CONST
6057 || cur_token
.code
== '-'
6058 || cur_token
.code
== '+')
6062 /* Allow constants that start with `+' or `-'. */
6063 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6065 strcat (intel_parser
.disp
, cur_token
.str
);
6066 intel_match_token (cur_token
.code
);
6067 if (cur_token
.code
!= T_CONST
)
6069 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6075 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6076 if (save_str
== NULL
)
6078 strcpy (save_str
, cur_token
.str
);
6080 /* Get the next token to check for register scaling. */
6081 intel_match_token (cur_token
.code
);
6083 /* Check if this constant is a scaling factor for an index register. */
6084 if (cur_token
.code
== '*')
6086 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6088 if (!intel_parser
.is_mem
)
6090 as_bad (_("Register scaling only allowed in memory operands."));
6094 /* The constant is followed by `* reg', so it must be
6096 if (strchr ("01248", *save_str
))
6098 i
.index_reg
= cur_token
.reg
;
6099 i
.types
[this_operand
] |= BaseIndex
;
6101 /* Set the scale after setting the register (otherwise,
6102 i386_scale will complain) */
6103 i386_scale (save_str
);
6104 intel_match_token (T_REG
);
6106 /* Since registers are not part of the displacement
6107 string, we may need to remove any preceding '+' from
6108 the displacement string. */
6109 if (*intel_parser
.disp
!= '\0')
6111 char *s
= intel_parser
.disp
;
6112 s
+= strlen (s
) - 1;
6125 /* The constant was not used for register scaling. Since we have
6126 already consumed the token following `*' we now need to put it
6127 back in the stream. */
6129 intel_putback_token ();
6132 /* Add the constant to the displacement string. */
6133 strcat (intel_parser
.disp
, save_str
);
6139 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6143 /* Match the given token against cur_token. If they match, read the next
6144 token from the operand string. */
6146 intel_match_token (code
)
6149 if (cur_token
.code
== code
)
6156 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6161 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6166 const reg_entry
*reg
;
6167 struct intel_token new_token
;
6169 new_token
.code
= T_NIL
;
6170 new_token
.reg
= NULL
;
6171 new_token
.str
= NULL
;
6173 /* Free the memory allocated to the previous token and move
6174 cur_token to prev_token. */
6176 free (prev_token
.str
);
6178 prev_token
= cur_token
;
6180 /* Skip whitespace. */
6181 while (is_space_char (*intel_parser
.op_string
))
6182 intel_parser
.op_string
++;
6184 /* Return an empty token if we find nothing else on the line. */
6185 if (*intel_parser
.op_string
== '\0')
6187 cur_token
= new_token
;
6191 /* The new token cannot be larger than the remainder of the operand
6193 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6194 if (new_token
.str
== NULL
)
6196 new_token
.str
[0] = '\0';
6198 if (strchr ("0123456789", *intel_parser
.op_string
))
6200 char *p
= new_token
.str
;
6201 char *q
= intel_parser
.op_string
;
6202 new_token
.code
= T_CONST
;
6204 /* Allow any kind of identifier char to encompass floating point and
6205 hexadecimal numbers. */
6206 while (is_identifier_char (*q
))
6210 /* Recognize special symbol names [0-9][bf]. */
6211 if (strlen (intel_parser
.op_string
) == 2
6212 && (intel_parser
.op_string
[1] == 'b'
6213 || intel_parser
.op_string
[1] == 'f'))
6214 new_token
.code
= T_ID
;
6217 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6219 new_token
.code
= *intel_parser
.op_string
;
6220 new_token
.str
[0] = *intel_parser
.op_string
;
6221 new_token
.str
[1] = '\0';
6224 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6225 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6227 new_token
.code
= T_REG
;
6228 new_token
.reg
= reg
;
6230 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6232 new_token
.str
[0] = REGISTER_PREFIX
;
6233 new_token
.str
[1] = '\0';
6236 strcat (new_token
.str
, reg
->reg_name
);
6239 else if (is_identifier_char (*intel_parser
.op_string
))
6241 char *p
= new_token
.str
;
6242 char *q
= intel_parser
.op_string
;
6244 /* A '.' or '$' followed by an identifier char is an identifier.
6245 Otherwise, it's operator '.' followed by an expression. */
6246 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6248 new_token
.code
= *q
;
6249 new_token
.str
[0] = *q
;
6250 new_token
.str
[1] = '\0';
6254 while (is_identifier_char (*q
) || *q
== '@')
6258 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6259 new_token
.code
= T_BYTE
;
6261 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6262 new_token
.code
= T_WORD
;
6264 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6265 new_token
.code
= T_DWORD
;
6267 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6268 new_token
.code
= T_QWORD
;
6270 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6271 new_token
.code
= T_XWORD
;
6273 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6274 new_token
.code
= T_PTR
;
6276 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6277 new_token
.code
= T_SHORT
;
6279 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6281 new_token
.code
= T_OFFSET
;
6283 /* ??? This is not mentioned in the MASM grammar but gcc
6284 makes use of it with -mintel-syntax. OFFSET may be
6285 followed by FLAT: */
6286 if (strncasecmp (q
, " FLAT:", 6) == 0)
6287 strcat (new_token
.str
, " FLAT:");
6290 /* ??? This is not mentioned in the MASM grammar. */
6291 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6292 new_token
.code
= T_OFFSET
;
6295 new_token
.code
= T_ID
;
6300 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6302 intel_parser
.op_string
+= strlen (new_token
.str
);
6303 cur_token
= new_token
;
6306 /* Put cur_token back into the token stream and make cur_token point to
6309 intel_putback_token ()
6311 intel_parser
.op_string
-= strlen (cur_token
.str
);
6312 free (cur_token
.str
);
6313 cur_token
= prev_token
;
6315 /* Forget prev_token. */
6316 prev_token
.code
= T_NIL
;
6317 prev_token
.reg
= NULL
;
6318 prev_token
.str
= NULL
;
6322 tc_x86_regname_to_dw2regnum (const char *regname
)
6324 unsigned int regnum
;
6325 unsigned int regnames_count
;
6326 char *regnames_32
[] =
6328 "eax", "ecx", "edx", "ebx",
6329 "esp", "ebp", "esi", "edi",
6332 char *regnames_64
[] =
6334 "rax", "rbx", "rcx", "rdx",
6335 "rdi", "rsi", "rbp", "rsp",
6336 "r8", "r9", "r10", "r11",
6337 "r12", "r13", "r14", "r15",
6342 if (flag_code
== CODE_64BIT
)
6344 regnames
= regnames_64
;
6345 regnames_count
= sizeof (regnames_64
);
6349 regnames
= regnames_32
;
6350 regnames_count
= sizeof (regnames_32
);
6353 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6354 if (strcmp (regname
, regnames
[regnum
]) == 0)
6361 tc_x86_frame_initial_instructions (void)
6363 static unsigned int sp_regno
;
6366 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6369 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6370 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);