1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags enable
; /* cpu feature enable flags */
135 i386_cpu_flags disable
; /* cpu feature disable flags */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
149 static void pe_directive_secidx (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static const char *parse_insn (const char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (unsigned int, unsigned int);
166 static enum flag_code
i386_addressing_mode (void);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (char);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const reg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 /* GNU_PROPERTY_X86_ISA_1_USED. */
189 static unsigned int x86_isa_1_used
;
190 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
191 static unsigned int x86_feature_2_used
;
192 /* Generate x86 used ISA and feature properties. */
193 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* parse_register() returns this when a register alias cannot be used. */
199 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
200 { Dw2Inval
, Dw2Inval
} };
202 static const reg_entry
*reg_eax
;
203 static const reg_entry
*reg_ds
;
204 static const reg_entry
*reg_es
;
205 static const reg_entry
*reg_ss
;
206 static const reg_entry
*reg_st0
;
207 static const reg_entry
*reg_k0
;
212 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
213 unsigned char bytes
[4];
215 /* Destination or source register specifier. */
216 const reg_entry
*register_specifier
;
219 /* 'md_assemble ()' gathers together information and puts it into a
226 const reg_entry
*regs
;
231 no_error
, /* Must be first. */
232 operand_size_mismatch
,
233 operand_type_mismatch
,
234 register_type_mismatch
,
235 number_of_operands_mismatch
,
236 invalid_instruction_suffix
,
238 unsupported_with_intel_mnemonic
,
244 invalid_vsib_address
,
245 invalid_vector_register_set
,
246 invalid_tmm_register_set
,
247 invalid_dest_and_src_register_set
,
248 unsupported_vector_index_register
,
249 unsupported_broadcast
,
252 mask_not_on_destination
,
255 invalid_register_operand
,
260 /* TM holds the template for the insn were currently assembling. */
263 /* SUFFIX holds the instruction size suffix for byte, word, dword
264 or qword, if given. */
267 /* OPCODE_LENGTH holds the number of base opcode bytes. */
268 unsigned char opcode_length
;
270 /* OPERANDS gives the number of given operands. */
271 unsigned int operands
;
273 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
274 of given register, displacement, memory operands and immediate
276 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
278 /* TYPES [i] is the type (see above #defines) which tells us how to
279 use OP[i] for the corresponding operand. */
280 i386_operand_type types
[MAX_OPERANDS
];
282 /* Displacement expression, immediate expression, or register for each
284 union i386_op op
[MAX_OPERANDS
];
286 /* Flags for operands. */
287 unsigned int flags
[MAX_OPERANDS
];
288 #define Operand_PCrel 1
289 #define Operand_Mem 2
291 /* Relocation type for operand */
292 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
294 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
295 the base index byte below. */
296 const reg_entry
*base_reg
;
297 const reg_entry
*index_reg
;
298 unsigned int log2_scale_factor
;
300 /* SEG gives the seg_entries of this insn. They are zero unless
301 explicit segment overrides are given. */
302 const reg_entry
*seg
[2];
304 /* PREFIX holds all the given prefix opcodes (usually null).
305 PREFIXES is the number of prefix opcodes. */
306 unsigned int prefixes
;
307 unsigned char prefix
[MAX_PREFIXES
];
309 /* Register is in low 3 bits of opcode. */
312 /* The operand to a branch insn indicates an absolute branch. */
315 /* The operand to a branch insn indicates a far branch. */
318 /* There is a memory operand of (%dx) which should be only used
319 with input/output instructions. */
320 bool input_output_operand
;
322 /* Extended states. */
330 xstate_ymm
= 1 << 2 | xstate_xmm
,
332 xstate_zmm
= 1 << 3 | xstate_ymm
,
335 /* Use MASK state. */
339 /* Has GOTPC or TLS relocation. */
340 bool has_gotpc_tls_reloc
;
342 /* RM and SIB are the modrm byte and the sib byte where the
343 addressing modes of this insn are encoded. */
350 /* Masking attributes.
352 The struct describes masking, applied to OPERAND in the instruction.
353 REG is a pointer to the corresponding mask register. ZEROING tells
354 whether merging or zeroing mask is used. */
355 struct Mask_Operation
357 const reg_entry
*reg
;
358 unsigned int zeroing
;
359 /* The operand where this operation is associated. */
360 unsigned int operand
;
363 /* Rounding control and SAE attributes. */
375 /* In Intel syntax the operand modifier form is supposed to be used, but
376 we continue to accept the immediate forms as well. */
380 /* Broadcasting attributes.
382 The struct describes broadcasting, applied to OPERAND. TYPE is
383 expresses the broadcast factor. */
384 struct Broadcast_Operation
386 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
389 /* Index of broadcasted operand. */
390 unsigned int operand
;
392 /* Number of bytes to broadcast. */
396 /* Compressed disp8*N attribute. */
397 unsigned int memshift
;
399 /* Prefer load or store in encoding. */
402 dir_encoding_default
= 0,
408 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
411 disp_encoding_default
= 0,
417 /* Prefer the REX byte in encoding. */
420 /* Disable instruction size optimization. */
423 /* How to encode vector instructions. */
426 vex_encoding_default
= 0,
434 const char *rep_prefix
;
437 const char *hle_prefix
;
439 /* Have BND prefix. */
440 const char *bnd_prefix
;
442 /* Have NOTRACK prefix. */
443 const char *notrack_prefix
;
446 enum i386_error error
;
449 typedef struct _i386_insn i386_insn
;
451 /* Link RC type with corresponding string, that'll be looked for in
460 static const struct RC_name RC_NamesTable
[] =
462 { rne
, STRING_COMMA_LEN ("rn-sae") },
463 { rd
, STRING_COMMA_LEN ("rd-sae") },
464 { ru
, STRING_COMMA_LEN ("ru-sae") },
465 { rz
, STRING_COMMA_LEN ("rz-sae") },
466 { saeonly
, STRING_COMMA_LEN ("sae") },
469 /* To be indexed by segment register number. */
470 static const unsigned char i386_seg_prefixes
[] = {
479 /* List of chars besides those in app.c:symbol_chars that can start an
480 operand. Used to prevent the scrubber eating vital white-space. */
481 const char extra_symbol_chars
[] = "*%-([{}"
490 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
491 && !defined (TE_GNU) \
492 && !defined (TE_LINUX) \
493 && !defined (TE_Haiku) \
494 && !defined (TE_FreeBSD) \
495 && !defined (TE_DragonFly) \
496 && !defined (TE_NetBSD))
497 /* This array holds the chars that always start a comment. If the
498 pre-processor is disabled, these aren't very useful. The option
499 --divide will remove '/' from this list. */
500 const char *i386_comment_chars
= "#/";
501 #define SVR4_COMMENT_CHARS 1
502 #define PREFIX_SEPARATOR '\\'
505 const char *i386_comment_chars
= "#";
506 #define PREFIX_SEPARATOR '/'
509 /* This array holds the chars that only start a comment at the beginning of
510 a line. If the line seems to have the form '# 123 filename'
511 .line and .file directives will appear in the pre-processed output.
512 Note that input_file.c hand checks for '#' at the beginning of the
513 first line of the input file. This is because the compiler outputs
514 #NO_APP at the beginning of its output.
515 Also note that comments started like this one will always work if
516 '/' isn't otherwise defined. */
517 const char line_comment_chars
[] = "#/";
519 const char line_separator_chars
[] = ";";
521 /* Chars that can be used to separate mant from exp in floating point
523 const char EXP_CHARS
[] = "eE";
525 /* Chars that mean this number is a floating point constant
528 const char FLT_CHARS
[] = "fFdDxXhHbB";
530 /* Tables for lexical analysis. */
531 static char mnemonic_chars
[256];
532 static char register_chars
[256];
533 static char operand_chars
[256];
534 static char identifier_chars
[256];
536 /* Lexical macros. */
537 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
538 #define is_operand_char(x) (operand_chars[(unsigned char) x])
539 #define is_register_char(x) (register_chars[(unsigned char) x])
540 #define is_space_char(x) ((x) == ' ')
541 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
543 /* All non-digit non-letter characters that may occur in an operand. */
544 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
546 /* md_assemble() always leaves the strings it's passed unaltered. To
547 effect this we maintain a stack of saved characters that we've smashed
548 with '\0's (indicating end of strings for various sub-fields of the
549 assembler instruction). */
550 static char save_stack
[32];
551 static char *save_stack_p
;
552 #define END_STRING_AND_SAVE(s) \
553 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
554 #define RESTORE_END_STRING(s) \
555 do { *(s) = *--save_stack_p; } while (0)
557 /* The instruction we're assembling. */
560 /* Possible templates for current insn. */
561 static const templates
*current_templates
;
563 /* Per instruction expressionS buffers: max displacements & immediates. */
564 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
565 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
567 /* Current operand we are working on. */
568 static int this_operand
= -1;
570 /* We support four different modes. FLAG_CODE variable is used to distinguish
578 static enum flag_code flag_code
;
579 static unsigned int object_64bit
;
580 static unsigned int disallow_64bit_reloc
;
581 static int use_rela_relocations
= 0;
582 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
583 static const char *tls_get_addr
;
585 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
586 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
587 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
589 /* The ELF ABI to use. */
597 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
600 #if defined (TE_PE) || defined (TE_PEP)
601 /* Use big object file format. */
602 static int use_big_obj
= 0;
605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
606 /* 1 if generating code for a shared library. */
607 static int shared
= 0;
609 unsigned int x86_sframe_cfa_sp_reg
;
610 /* The other CFA base register for SFrame stack trace info. */
611 unsigned int x86_sframe_cfa_fp_reg
;
612 unsigned int x86_sframe_cfa_ra_reg
;
616 /* 1 for intel syntax,
618 static int intel_syntax
= 0;
620 static enum x86_64_isa
622 amd64
= 1, /* AMD64 ISA. */
623 intel64
/* Intel64 ISA. */
626 /* 1 for intel mnemonic,
627 0 if att mnemonic. */
628 static int intel_mnemonic
= !SYSV386_COMPAT
;
630 /* 1 if pseudo registers are permitted. */
631 static int allow_pseudo_reg
= 0;
633 /* 1 if register prefix % not required. */
634 static int allow_naked_reg
= 0;
636 /* 1 if the assembler should add BND prefix for all control-transferring
637 instructions supporting it, even if this prefix wasn't specified
639 static int add_bnd_prefix
= 0;
641 /* 1 if pseudo index register, eiz/riz, is allowed . */
642 static int allow_index_reg
= 0;
644 /* 1 if the assembler should ignore LOCK prefix, even if it was
645 specified explicitly. */
646 static int omit_lock_prefix
= 0;
648 /* 1 if the assembler should encode lfence, mfence, and sfence as
649 "lock addl $0, (%{re}sp)". */
650 static int avoid_fence
= 0;
652 /* 1 if lfence should be inserted after every load. */
653 static int lfence_after_load
= 0;
655 /* Non-zero if lfence should be inserted before indirect branch. */
656 static enum lfence_before_indirect_branch_kind
658 lfence_branch_none
= 0,
659 lfence_branch_register
,
660 lfence_branch_memory
,
663 lfence_before_indirect_branch
;
665 /* Non-zero if lfence should be inserted before ret. */
666 static enum lfence_before_ret_kind
668 lfence_before_ret_none
= 0,
669 lfence_before_ret_not
,
670 lfence_before_ret_or
,
671 lfence_before_ret_shl
675 /* Types of previous instruction is .byte or prefix. */
690 /* 1 if the assembler should generate relax relocations. */
692 static int generate_relax_relocations
693 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
695 static enum check_kind
701 sse_check
, operand_check
= check_warning
;
703 /* Non-zero if branches should be aligned within power of 2 boundary. */
704 static int align_branch_power
= 0;
706 /* Types of branches to align. */
707 enum align_branch_kind
709 align_branch_none
= 0,
710 align_branch_jcc
= 1,
711 align_branch_fused
= 2,
712 align_branch_jmp
= 3,
713 align_branch_call
= 4,
714 align_branch_indirect
= 5,
718 /* Type bits of branches to align. */
719 enum align_branch_bit
721 align_branch_jcc_bit
= 1 << align_branch_jcc
,
722 align_branch_fused_bit
= 1 << align_branch_fused
,
723 align_branch_jmp_bit
= 1 << align_branch_jmp
,
724 align_branch_call_bit
= 1 << align_branch_call
,
725 align_branch_indirect_bit
= 1 << align_branch_indirect
,
726 align_branch_ret_bit
= 1 << align_branch_ret
729 static unsigned int align_branch
= (align_branch_jcc_bit
730 | align_branch_fused_bit
731 | align_branch_jmp_bit
);
733 /* Types of condition jump used by macro-fusion. */
736 mf_jcc_jo
= 0, /* base opcode 0x70 */
737 mf_jcc_jc
, /* base opcode 0x72 */
738 mf_jcc_je
, /* base opcode 0x74 */
739 mf_jcc_jna
, /* base opcode 0x76 */
740 mf_jcc_js
, /* base opcode 0x78 */
741 mf_jcc_jp
, /* base opcode 0x7a */
742 mf_jcc_jl
, /* base opcode 0x7c */
743 mf_jcc_jle
, /* base opcode 0x7e */
746 /* Types of compare flag-modifying insntructions used by macro-fusion. */
749 mf_cmp_test_and
, /* test/cmp */
750 mf_cmp_alu_cmp
, /* add/sub/cmp */
751 mf_cmp_incdec
/* inc/dec */
754 /* The maximum padding size for fused jcc. CMP like instruction can
755 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
757 #define MAX_FUSED_JCC_PADDING_SIZE 20
759 /* The maximum number of prefixes added for an instruction. */
760 static unsigned int align_branch_prefix_size
= 5;
763 1. Clear the REX_W bit with register operand if possible.
764 2. Above plus use 128bit vector instruction to clear the full vector
767 static int optimize
= 0;
770 1. Clear the REX_W bit with register operand if possible.
771 2. Above plus use 128bit vector instruction to clear the full vector
773 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
776 static int optimize_for_space
= 0;
778 /* Register prefix used for error message. */
779 static const char *register_prefix
= "%";
781 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
782 leave, push, and pop instructions so that gcc has the same stack
783 frame as in 32 bit mode. */
784 static char stackop_size
= '\0';
786 /* Non-zero to optimize code alignment. */
787 int optimize_align_code
= 1;
789 /* Non-zero to quieten some warnings. */
790 static int quiet_warnings
= 0;
792 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
793 static bool pre_386_16bit_warned
;
796 static const char *cpu_arch_name
= NULL
;
797 static char *cpu_sub_arch_name
= NULL
;
799 /* CPU feature flags. */
800 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
802 /* If we have selected a cpu we are generating instructions for. */
803 static int cpu_arch_tune_set
= 0;
805 /* Cpu we are generating instructions for. */
806 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
808 /* CPU feature flags of cpu we are generating instructions for. */
809 static i386_cpu_flags cpu_arch_tune_flags
;
811 /* CPU instruction set architecture used. */
812 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
814 /* CPU feature flags of instruction set architecture used. */
815 i386_cpu_flags cpu_arch_isa_flags
;
817 /* If set, conditional jumps are not automatically promoted to handle
818 larger than a byte offset. */
819 static bool no_cond_jump_promotion
= false;
821 /* Encode SSE instructions with VEX prefix. */
822 static unsigned int sse2avx
;
824 /* Encode aligned vector move as unaligned vector move. */
825 static unsigned int use_unaligned_vector_move
;
827 /* Encode scalar AVX instructions with specific vector length. */
834 /* Encode VEX WIG instructions with specific vex.w. */
841 /* Encode scalar EVEX LIG instructions with specific vector length. */
849 /* Encode EVEX WIG instructions with specific evex.w. */
856 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
857 static enum rc_type evexrcig
= rne
;
859 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
860 static symbolS
*GOT_symbol
;
862 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
863 unsigned int x86_dwarf2_return_column
;
865 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
866 int x86_cie_data_alignment
;
868 /* Interface to relax_segment.
869 There are 3 major relax states for 386 jump insns because the
870 different types of jumps add different sizes to frags when we're
871 figuring out what sort of jump to choose to reach a given label.
873 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
874 branches which are handled by md_estimate_size_before_relax() and
875 i386_generic_table_relax_frag(). */
878 #define UNCOND_JUMP 0
880 #define COND_JUMP86 2
881 #define BRANCH_PADDING 3
882 #define BRANCH_PREFIX 4
883 #define FUSED_JCC_PADDING 5
888 #define SMALL16 (SMALL | CODE16)
890 #define BIG16 (BIG | CODE16)
894 #define INLINE __inline__
900 #define ENCODE_RELAX_STATE(type, size) \
901 ((relax_substateT) (((type) << 2) | (size)))
902 #define TYPE_FROM_RELAX_STATE(s) \
904 #define DISP_SIZE_FROM_RELAX_STATE(s) \
905 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
907 /* This table is used by relax_frag to promote short jumps to long
908 ones where necessary. SMALL (short) jumps may be promoted to BIG
909 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
910 don't allow a short jump in a 32 bit code segment to be promoted to
911 a 16 bit offset jump because it's slower (requires data size
912 prefix), and doesn't work, unless the destination is in the bottom
913 64k of the code segment (The top 16 bits of eip are zeroed). */
915 const relax_typeS md_relax_table
[] =
918 1) most positive reach of this state,
919 2) most negative reach of this state,
920 3) how many bytes this mode will have in the variable part of the frag
921 4) which index into the table to try if we can't fit into this one. */
923 /* UNCOND_JUMP states. */
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
925 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
926 /* dword jmp adds 4 bytes to frag:
927 0 extra opcode bytes, 4 displacement bytes. */
929 /* word jmp adds 2 byte2 to frag:
930 0 extra opcode bytes, 2 displacement bytes. */
933 /* COND_JUMP states. */
934 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
935 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
936 /* dword conditionals adds 5 bytes to frag:
937 1 extra opcode byte, 4 displacement bytes. */
939 /* word conditionals add 3 bytes to frag:
940 1 extra opcode byte, 2 displacement bytes. */
943 /* COND_JUMP86 states. */
944 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
945 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
946 /* dword conditionals adds 5 bytes to frag:
947 1 extra opcode byte, 4 displacement bytes. */
949 /* word conditionals add 4 bytes to frag:
950 1 displacement byte and a 3 byte long branch insn. */
954 #define ARCH(n, t, f, s) \
955 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \
957 #define SUBARCH(n, e, d, s) \
958 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \
959 CPU_ ## d ## _FLAGS }
961 static const arch_entry cpu_arch
[] =
963 /* Do not replace the first two entries - i386_target_format() and
964 set_cpu_arch() rely on them being there in this order. */
965 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
966 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
967 ARCH (i8086
, UNKNOWN
, NONE
, false),
968 ARCH (i186
, UNKNOWN
, 186, false),
969 ARCH (i286
, UNKNOWN
, 286, false),
970 ARCH (i386
, I386
, 386, false),
971 ARCH (i486
, I486
, 486, false),
972 ARCH (i586
, PENTIUM
, 586, false),
973 ARCH (i686
, PENTIUMPRO
, 686, false),
974 ARCH (pentium
, PENTIUM
, 586, false),
975 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
976 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
977 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
978 ARCH (pentium4
, PENTIUM4
, P4
, false),
979 ARCH (prescott
, NOCONA
, CORE
, false),
980 ARCH (nocona
, NOCONA
, NOCONA
, false),
981 ARCH (yonah
, CORE
, CORE
, true),
982 ARCH (core
, CORE
, CORE
, false),
983 ARCH (merom
, CORE2
, CORE2
, true),
984 ARCH (core2
, CORE2
, CORE2
, false),
985 ARCH (corei7
, COREI7
, COREI7
, false),
986 ARCH (iamcu
, IAMCU
, IAMCU
, false),
987 ARCH (k6
, K6
, K6
, false),
988 ARCH (k6_2
, K6
, K6_2
, false),
989 ARCH (athlon
, ATHLON
, ATHLON
, false),
990 ARCH (sledgehammer
, K8
, K8
, true),
991 ARCH (opteron
, K8
, K8
, false),
992 ARCH (k8
, K8
, K8
, false),
993 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
994 ARCH (bdver1
, BD
, BDVER1
, false),
995 ARCH (bdver2
, BD
, BDVER2
, false),
996 ARCH (bdver3
, BD
, BDVER3
, false),
997 ARCH (bdver4
, BD
, BDVER4
, false),
998 ARCH (znver1
, ZNVER
, ZNVER1
, false),
999 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1000 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1001 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1002 ARCH (btver1
, BT
, BTVER1
, false),
1003 ARCH (btver2
, BT
, BTVER2
, false),
1005 SUBARCH (8087, 8087, ANY_8087
, false),
1006 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1007 SUBARCH (287, 287, ANY_287
, false),
1008 SUBARCH (387, 387, ANY_387
, false),
1009 SUBARCH (687, 687, ANY_687
, false),
1010 SUBARCH (cmov
, CMOV
, CMOV
, false),
1011 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1012 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1013 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1014 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1015 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1016 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1017 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1018 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1019 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1020 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1021 SUBARCH (avx
, AVX
, ANY_AVX
, false),
1022 SUBARCH (avx2
, AVX2
, ANY_AVX2
, false),
1023 SUBARCH (avx512f
, AVX512F
, ANY_AVX512F
, false),
1024 SUBARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, false),
1025 SUBARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, false),
1026 SUBARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, false),
1027 SUBARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, false),
1028 SUBARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, false),
1029 SUBARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, false),
1030 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1031 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1032 SUBARCH (smx
, SMX
, SMX
, false),
1033 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1034 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1035 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1036 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1037 SUBARCH (aes
, AES
, ANY_AES
, false),
1038 SUBARCH (pclmul
, PCLMUL
, ANY_PCLMUL
, false),
1039 SUBARCH (clmul
, PCLMUL
, ANY_PCLMUL
, true),
1040 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1041 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1042 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1043 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1044 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1045 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1046 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1047 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1048 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1049 SUBARCH (cx16
, CX16
, CX16
, false),
1050 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1051 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1052 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1053 SUBARCH (hle
, HLE
, HLE
, false),
1054 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1055 SUBARCH (tsx
, TSX
, TSX
, false),
1056 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1057 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1058 SUBARCH (nop
, NOP
, NOP
, false),
1059 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1060 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1061 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1062 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1063 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1064 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1065 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1066 SUBARCH (abm
, ABM
, ABM
, false),
1067 SUBARCH (bmi
, BMI
, BMI
, false),
1068 SUBARCH (tbm
, TBM
, TBM
, false),
1069 SUBARCH (adx
, ADX
, ADX
, false),
1070 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1071 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1072 SUBARCH (smap
, SMAP
, SMAP
, false),
1073 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1074 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1075 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1076 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1077 SUBARCH (se1
, SE1
, SE1
, false),
1078 SUBARCH (clwb
, CLWB
, CLWB
, false),
1079 SUBARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, false),
1080 SUBARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, false),
1081 SUBARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, false),
1082 SUBARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, false),
1083 SUBARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, false),
1084 SUBARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, false),
1085 SUBARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, false),
1086 SUBARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, false),
1087 SUBARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, false),
1088 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1089 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1090 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1091 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1092 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1093 SUBARCH (ibt
, IBT
, IBT
, false),
1094 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1095 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1096 SUBARCH (vaes
, VAES
, ANY_VAES
, false),
1097 SUBARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, false),
1098 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1099 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1100 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1101 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1102 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1103 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1104 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1105 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1106 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1107 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1108 SUBARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, false),
1109 SUBARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1110 ANY_AVX512_VP2INTERSECT
, false),
1111 SUBARCH (tdx
, TDX
, TDX
, false),
1112 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1113 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1114 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1115 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1116 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1117 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1118 SUBARCH (kl
, KL
, ANY_KL
, false),
1119 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1120 SUBARCH (uintr
, UINTR
, UINTR
, false),
1121 SUBARCH (hreset
, HRESET
, HRESET
, false),
1122 SUBARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, false),
1123 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1124 SUBARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, false),
1125 SUBARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, false),
1126 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1127 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1128 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1129 SUBARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, false),
1130 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1131 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1138 /* Like s_lcomm_internal in gas/read.c but the alignment string
1139 is allowed to be optional. */
1142 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1149 && *input_line_pointer
== ',')
1151 align
= parse_align (needs_align
- 1);
1153 if (align
== (addressT
) -1)
1168 bss_alloc (symbolP
, size
, align
);
1173 pe_lcomm (int needs_align
)
1175 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1179 const pseudo_typeS md_pseudo_table
[] =
1181 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1182 {"align", s_align_bytes
, 0},
1184 {"align", s_align_ptwo
, 0},
1186 {"arch", set_cpu_arch
, 0},
1190 {"lcomm", pe_lcomm
, 1},
1192 {"ffloat", float_cons
, 'f'},
1193 {"dfloat", float_cons
, 'd'},
1194 {"tfloat", float_cons
, 'x'},
1195 {"hfloat", float_cons
, 'h'},
1196 {"bfloat16", float_cons
, 'b'},
1198 {"slong", signed_cons
, 4},
1199 {"noopt", s_ignore
, 0},
1200 {"optim", s_ignore
, 0},
1201 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1202 {"code16", set_code_flag
, CODE_16BIT
},
1203 {"code32", set_code_flag
, CODE_32BIT
},
1205 {"code64", set_code_flag
, CODE_64BIT
},
1207 {"intel_syntax", set_intel_syntax
, 1},
1208 {"att_syntax", set_intel_syntax
, 0},
1209 {"intel_mnemonic", set_intel_mnemonic
, 1},
1210 {"att_mnemonic", set_intel_mnemonic
, 0},
1211 {"allow_index_reg", set_allow_index_reg
, 1},
1212 {"disallow_index_reg", set_allow_index_reg
, 0},
1213 {"sse_check", set_check
, 0},
1214 {"operand_check", set_check
, 1},
1215 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1216 {"largecomm", handle_large_common
, 0},
1218 {"file", dwarf2_directive_file
, 0},
1219 {"loc", dwarf2_directive_loc
, 0},
1220 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1223 {"secrel32", pe_directive_secrel
, 0},
1224 {"secidx", pe_directive_secidx
, 0},
1229 /* For interface with expression (). */
1230 extern char *input_line_pointer
;
1232 /* Hash table for instruction mnemonic lookup. */
1233 static htab_t op_hash
;
1235 /* Hash table for register lookup. */
1236 static htab_t reg_hash
;
1238 /* Various efficient no-op patterns for aligning code labels.
1239 Note: Don't try to assemble the instructions in the comments.
1240 0L and 0w are not legal. */
1241 static const unsigned char f32_1
[] =
1243 static const unsigned char f32_2
[] =
1244 {0x66,0x90}; /* xchg %ax,%ax */
1245 static const unsigned char f32_3
[] =
1246 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1247 static const unsigned char f32_4
[] =
1248 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1249 static const unsigned char f32_6
[] =
1250 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1251 static const unsigned char f32_7
[] =
1252 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1253 static const unsigned char f16_3
[] =
1254 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1255 static const unsigned char f16_4
[] =
1256 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1257 static const unsigned char jump_disp8
[] =
1258 {0xeb}; /* jmp disp8 */
1259 static const unsigned char jump32_disp32
[] =
1260 {0xe9}; /* jmp disp32 */
1261 static const unsigned char jump16_disp32
[] =
1262 {0x66,0xe9}; /* jmp disp32 */
1263 /* 32-bit NOPs patterns. */
1264 static const unsigned char *const f32_patt
[] = {
1265 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1267 /* 16-bit NOPs patterns. */
1268 static const unsigned char *const f16_patt
[] = {
1269 f32_1
, f32_2
, f16_3
, f16_4
1271 /* nopl (%[re]ax) */
1272 static const unsigned char alt_3
[] =
1274 /* nopl 0(%[re]ax) */
1275 static const unsigned char alt_4
[] =
1276 {0x0f,0x1f,0x40,0x00};
1277 /* nopl 0(%[re]ax,%[re]ax,1) */
1278 static const unsigned char alt_5
[] =
1279 {0x0f,0x1f,0x44,0x00,0x00};
1280 /* nopw 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_6
[] =
1282 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopl 0L(%[re]ax) */
1284 static const unsigned char alt_7
[] =
1285 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1286 /* nopl 0L(%[re]ax,%[re]ax,1) */
1287 static const unsigned char alt_8
[] =
1288 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1289 /* nopw 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_9
[] =
1291 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_10
[] =
1294 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* data16 nopw %cs:0L(%eax,%eax,1) */
1296 static const unsigned char alt_11
[] =
1297 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* 32-bit and 64-bit NOPs patterns. */
1299 static const unsigned char *const alt_patt
[] = {
1300 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1301 alt_9
, alt_10
, alt_11
1304 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1305 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1308 i386_output_nops (char *where
, const unsigned char *const *patt
,
1309 int count
, int max_single_nop_size
)
1312 /* Place the longer NOP first. */
1315 const unsigned char *nops
;
1317 if (max_single_nop_size
< 1)
1319 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1320 max_single_nop_size
);
1324 nops
= patt
[max_single_nop_size
- 1];
1326 /* Use the smaller one if the requsted one isn't available. */
1329 max_single_nop_size
--;
1330 nops
= patt
[max_single_nop_size
- 1];
1333 last
= count
% max_single_nop_size
;
1336 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1337 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1341 nops
= patt
[last
- 1];
1344 /* Use the smaller one plus one-byte NOP if the needed one
1347 nops
= patt
[last
- 1];
1348 memcpy (where
+ offset
, nops
, last
);
1349 where
[offset
+ last
] = *patt
[0];
1352 memcpy (where
+ offset
, nops
, last
);
1357 fits_in_imm7 (offsetT num
)
1359 return (num
& 0x7f) == num
;
1363 fits_in_imm31 (offsetT num
)
1365 return (num
& 0x7fffffff) == num
;
1368 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1369 single NOP instruction LIMIT. */
1372 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1374 const unsigned char *const *patt
= NULL
;
1375 int max_single_nop_size
;
1376 /* Maximum number of NOPs before switching to jump over NOPs. */
1377 int max_number_of_nops
;
1379 switch (fragP
->fr_type
)
1384 case rs_machine_dependent
:
1385 /* Allow NOP padding for jumps and calls. */
1386 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1387 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1394 /* We need to decide which NOP sequence to use for 32bit and
1395 64bit. When -mtune= is used:
1397 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1398 PROCESSOR_GENERIC32, f32_patt will be used.
1399 2. For the rest, alt_patt will be used.
1401 When -mtune= isn't used, alt_patt will be used if
1402 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1405 When -march= or .arch is used, we can't use anything beyond
1406 cpu_arch_isa_flags. */
1408 if (flag_code
== CODE_16BIT
)
1411 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1412 /* Limit number of NOPs to 2 in 16-bit mode. */
1413 max_number_of_nops
= 2;
1417 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1419 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1420 switch (cpu_arch_tune
)
1422 case PROCESSOR_UNKNOWN
:
1423 /* We use cpu_arch_isa_flags to check if we SHOULD
1424 optimize with nops. */
1425 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1430 case PROCESSOR_PENTIUM4
:
1431 case PROCESSOR_NOCONA
:
1432 case PROCESSOR_CORE
:
1433 case PROCESSOR_CORE2
:
1434 case PROCESSOR_COREI7
:
1435 case PROCESSOR_GENERIC64
:
1437 case PROCESSOR_ATHLON
:
1439 case PROCESSOR_AMDFAM10
:
1441 case PROCESSOR_ZNVER
:
1445 case PROCESSOR_I386
:
1446 case PROCESSOR_I486
:
1447 case PROCESSOR_PENTIUM
:
1448 case PROCESSOR_PENTIUMPRO
:
1449 case PROCESSOR_IAMCU
:
1450 case PROCESSOR_GENERIC32
:
1453 case PROCESSOR_NONE
:
1459 switch (fragP
->tc_frag_data
.tune
)
1461 case PROCESSOR_UNKNOWN
:
1462 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1463 PROCESSOR_UNKNOWN. */
1467 case PROCESSOR_I386
:
1468 case PROCESSOR_I486
:
1469 case PROCESSOR_PENTIUM
:
1470 case PROCESSOR_IAMCU
:
1472 case PROCESSOR_ATHLON
:
1474 case PROCESSOR_AMDFAM10
:
1476 case PROCESSOR_ZNVER
:
1478 case PROCESSOR_GENERIC32
:
1479 /* We use cpu_arch_isa_flags to check if we CAN optimize
1481 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1486 case PROCESSOR_PENTIUMPRO
:
1487 case PROCESSOR_PENTIUM4
:
1488 case PROCESSOR_NOCONA
:
1489 case PROCESSOR_CORE
:
1490 case PROCESSOR_CORE2
:
1491 case PROCESSOR_COREI7
:
1492 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1497 case PROCESSOR_GENERIC64
:
1500 case PROCESSOR_NONE
:
1505 if (patt
== f32_patt
)
1507 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1508 /* Limit number of NOPs to 2 for older processors. */
1509 max_number_of_nops
= 2;
1513 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1514 /* Limit number of NOPs to 7 for newer processors. */
1515 max_number_of_nops
= 7;
1520 limit
= max_single_nop_size
;
1522 if (fragP
->fr_type
== rs_fill_nop
)
1524 /* Output NOPs for .nop directive. */
1525 if (limit
> max_single_nop_size
)
1527 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1528 _("invalid single nop size: %d "
1529 "(expect within [0, %d])"),
1530 limit
, max_single_nop_size
);
1534 else if (fragP
->fr_type
!= rs_machine_dependent
)
1535 fragP
->fr_var
= count
;
1537 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1539 /* Generate jump over NOPs. */
1540 offsetT disp
= count
- 2;
1541 if (fits_in_imm7 (disp
))
1543 /* Use "jmp disp8" if possible. */
1545 where
[0] = jump_disp8
[0];
1551 unsigned int size_of_jump
;
1553 if (flag_code
== CODE_16BIT
)
1555 where
[0] = jump16_disp32
[0];
1556 where
[1] = jump16_disp32
[1];
1561 where
[0] = jump32_disp32
[0];
1565 count
-= size_of_jump
+ 4;
1566 if (!fits_in_imm31 (count
))
1568 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1569 _("jump over nop padding out of range"));
1573 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1574 where
+= size_of_jump
+ 4;
1578 /* Generate multiple NOPs. */
1579 i386_output_nops (where
, patt
, count
, limit
);
1583 operand_type_all_zero (const union i386_operand_type
*x
)
1585 switch (ARRAY_SIZE(x
->array
))
1596 return !x
->array
[0];
1603 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1605 switch (ARRAY_SIZE(x
->array
))
1621 x
->bitfield
.class = ClassNone
;
1622 x
->bitfield
.instance
= InstanceNone
;
1626 operand_type_equal (const union i386_operand_type
*x
,
1627 const union i386_operand_type
*y
)
1629 switch (ARRAY_SIZE(x
->array
))
1632 if (x
->array
[2] != y
->array
[2])
1636 if (x
->array
[1] != y
->array
[1])
1640 return x
->array
[0] == y
->array
[0];
1648 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1650 switch (ARRAY_SIZE(x
->array
))
1669 return !x
->array
[0];
1676 cpu_flags_equal (const union i386_cpu_flags
*x
,
1677 const union i386_cpu_flags
*y
)
1679 switch (ARRAY_SIZE(x
->array
))
1682 if (x
->array
[4] != y
->array
[4])
1686 if (x
->array
[3] != y
->array
[3])
1690 if (x
->array
[2] != y
->array
[2])
1694 if (x
->array
[1] != y
->array
[1])
1698 return x
->array
[0] == y
->array
[0];
1706 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1708 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1709 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1712 static INLINE i386_cpu_flags
1713 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1715 switch (ARRAY_SIZE (x
.array
))
1718 x
.array
[4] &= y
.array
[4];
1721 x
.array
[3] &= y
.array
[3];
1724 x
.array
[2] &= y
.array
[2];
1727 x
.array
[1] &= y
.array
[1];
1730 x
.array
[0] &= y
.array
[0];
1738 static INLINE i386_cpu_flags
1739 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1741 switch (ARRAY_SIZE (x
.array
))
1744 x
.array
[4] |= y
.array
[4];
1747 x
.array
[3] |= y
.array
[3];
1750 x
.array
[2] |= y
.array
[2];
1753 x
.array
[1] |= y
.array
[1];
1756 x
.array
[0] |= y
.array
[0];
1764 static INLINE i386_cpu_flags
1765 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1767 switch (ARRAY_SIZE (x
.array
))
1770 x
.array
[4] &= ~y
.array
[4];
1773 x
.array
[3] &= ~y
.array
[3];
1776 x
.array
[2] &= ~y
.array
[2];
1779 x
.array
[1] &= ~y
.array
[1];
1782 x
.array
[0] &= ~y
.array
[0];
1790 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1792 #define CPU_FLAGS_ARCH_MATCH 0x1
1793 #define CPU_FLAGS_64BIT_MATCH 0x2
1795 #define CPU_FLAGS_PERFECT_MATCH \
1796 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1798 /* Return CPU flags match bits. */
1801 cpu_flags_match (const insn_template
*t
)
1803 i386_cpu_flags x
= t
->cpu_flags
;
1804 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1806 x
.bitfield
.cpu64
= 0;
1807 x
.bitfield
.cpuno64
= 0;
1809 if (cpu_flags_all_zero (&x
))
1811 /* This instruction is available on all archs. */
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1816 /* This instruction is available only on some archs. */
1817 i386_cpu_flags cpu
= cpu_arch_flags
;
1819 /* AVX512VL is no standalone feature - match it and then strip it. */
1820 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1822 x
.bitfield
.cpuavx512vl
= 0;
1824 /* AVX and AVX2 present at the same time express an operand size
1825 dependency - strip AVX2 for the purposes here. The operand size
1826 dependent check occurs in check_vecOperands(). */
1827 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1828 x
.bitfield
.cpuavx2
= 0;
1830 cpu
= cpu_flags_and (x
, cpu
);
1831 if (!cpu_flags_all_zero (&cpu
))
1833 if (x
.bitfield
.cpuavx
)
1835 /* We need to check a few extra flags with AVX. */
1836 if (cpu
.bitfield
.cpuavx
1837 && (!t
->opcode_modifier
.sse2avx
1838 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1839 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1840 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1841 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1842 match
|= CPU_FLAGS_ARCH_MATCH
;
1844 else if (x
.bitfield
.cpuavx512f
)
1846 /* We need to check a few extra flags with AVX512F. */
1847 if (cpu
.bitfield
.cpuavx512f
1848 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1849 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1850 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1851 match
|= CPU_FLAGS_ARCH_MATCH
;
1854 match
|= CPU_FLAGS_ARCH_MATCH
;
1860 static INLINE i386_operand_type
1861 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1863 if (x
.bitfield
.class != y
.bitfield
.class)
1864 x
.bitfield
.class = ClassNone
;
1865 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1866 x
.bitfield
.instance
= InstanceNone
;
1868 switch (ARRAY_SIZE (x
.array
))
1871 x
.array
[2] &= y
.array
[2];
1874 x
.array
[1] &= y
.array
[1];
1877 x
.array
[0] &= y
.array
[0];
1885 static INLINE i386_operand_type
1886 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1888 gas_assert (y
.bitfield
.class == ClassNone
);
1889 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1891 switch (ARRAY_SIZE (x
.array
))
1894 x
.array
[2] &= ~y
.array
[2];
1897 x
.array
[1] &= ~y
.array
[1];
1900 x
.array
[0] &= ~y
.array
[0];
1908 static INLINE i386_operand_type
1909 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1911 gas_assert (x
.bitfield
.class == ClassNone
||
1912 y
.bitfield
.class == ClassNone
||
1913 x
.bitfield
.class == y
.bitfield
.class);
1914 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1915 y
.bitfield
.instance
== InstanceNone
||
1916 x
.bitfield
.instance
== y
.bitfield
.instance
);
1918 switch (ARRAY_SIZE (x
.array
))
1921 x
.array
[2] |= y
.array
[2];
1924 x
.array
[1] |= y
.array
[1];
1927 x
.array
[0] |= y
.array
[0];
1935 static INLINE i386_operand_type
1936 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1938 gas_assert (y
.bitfield
.class == ClassNone
);
1939 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1941 switch (ARRAY_SIZE (x
.array
))
1944 x
.array
[2] ^= y
.array
[2];
1947 x
.array
[1] ^= y
.array
[1];
1950 x
.array
[0] ^= y
.array
[0];
1958 static const i386_operand_type anydisp
= {
1959 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
1971 operand_type_check (i386_operand_type t
, enum operand_type c
)
1976 return t
.bitfield
.class == Reg
;
1979 return (t
.bitfield
.imm8
1983 || t
.bitfield
.imm32s
1984 || t
.bitfield
.imm64
);
1987 return (t
.bitfield
.disp8
1988 || t
.bitfield
.disp16
1989 || t
.bitfield
.disp32
1990 || t
.bitfield
.disp64
);
1993 return (t
.bitfield
.disp8
1994 || t
.bitfield
.disp16
1995 || t
.bitfield
.disp32
1996 || t
.bitfield
.disp64
1997 || t
.bitfield
.baseindex
);
2006 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2007 between operand GIVEN and opeand WANTED for instruction template T. */
2010 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2013 return !((i
.types
[given
].bitfield
.byte
2014 && !t
->operand_types
[wanted
].bitfield
.byte
)
2015 || (i
.types
[given
].bitfield
.word
2016 && !t
->operand_types
[wanted
].bitfield
.word
)
2017 || (i
.types
[given
].bitfield
.dword
2018 && !t
->operand_types
[wanted
].bitfield
.dword
)
2019 || (i
.types
[given
].bitfield
.qword
2020 && (!t
->operand_types
[wanted
].bitfield
.qword
2021 /* Don't allow 64-bit (memory) operands outside of 64-bit
2022 mode, when they're used where a 64-bit GPR could also
2023 be used. Checking is needed for Intel Syntax only. */
2025 && flag_code
!= CODE_64BIT
2026 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2027 || t
->operand_types
[wanted
].bitfield
.class == Accum
2028 || t
->opcode_modifier
.isstring
))))
2029 || (i
.types
[given
].bitfield
.tbyte
2030 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2033 /* Return 1 if there is no conflict in SIMD register between operand
2034 GIVEN and opeand WANTED for instruction template T. */
2037 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2040 return !((i
.types
[given
].bitfield
.xmmword
2041 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2042 || (i
.types
[given
].bitfield
.ymmword
2043 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2044 || (i
.types
[given
].bitfield
.zmmword
2045 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2046 || (i
.types
[given
].bitfield
.tmmword
2047 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2050 /* Return 1 if there is no conflict in any size between operand GIVEN
2051 and opeand WANTED for instruction template T. */
2054 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2057 return (match_operand_size (t
, wanted
, given
)
2058 && !((i
.types
[given
].bitfield
.unspecified
2059 && !i
.broadcast
.type
2060 && !i
.broadcast
.bytes
2061 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2062 || (i
.types
[given
].bitfield
.fword
2063 && !t
->operand_types
[wanted
].bitfield
.fword
)
2064 /* For scalar opcode templates to allow register and memory
2065 operands at the same time, some special casing is needed
2066 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2067 down-conversion vpmov*. */
2068 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2069 && t
->operand_types
[wanted
].bitfield
.byte
2070 + t
->operand_types
[wanted
].bitfield
.word
2071 + t
->operand_types
[wanted
].bitfield
.dword
2072 + t
->operand_types
[wanted
].bitfield
.qword
2073 > !!t
->opcode_modifier
.broadcast
)
2074 ? (i
.types
[given
].bitfield
.xmmword
2075 || i
.types
[given
].bitfield
.ymmword
2076 || i
.types
[given
].bitfield
.zmmword
)
2077 : !match_simd_size(t
, wanted
, given
))));
2080 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2081 operands for instruction template T, and it has MATCH_REVERSE set if there
2082 is no size conflict on any operands for the template with operands reversed
2083 (and the template allows for reversing in the first place). */
2085 #define MATCH_STRAIGHT 1
2086 #define MATCH_REVERSE 2
2088 static INLINE
unsigned int
2089 operand_size_match (const insn_template
*t
)
2091 unsigned int j
, match
= MATCH_STRAIGHT
;
2093 /* Don't check non-absolute jump instructions. */
2094 if (t
->opcode_modifier
.jump
2095 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2098 /* Check memory and accumulator operand size. */
2099 for (j
= 0; j
< i
.operands
; j
++)
2101 if (i
.types
[j
].bitfield
.class != Reg
2102 && i
.types
[j
].bitfield
.class != RegSIMD
2103 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2106 if (t
->operand_types
[j
].bitfield
.class == Reg
2107 && !match_operand_size (t
, j
, j
))
2113 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2114 && !match_simd_size (t
, j
, j
))
2120 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2121 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2127 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2134 if (!t
->opcode_modifier
.d
)
2137 /* Check reverse. */
2138 gas_assert ((i
.operands
>= 2 && i
.operands
<= 3)
2139 || t
->opcode_modifier
.vexsources
);
2141 for (j
= 0; j
< i
.operands
; j
++)
2143 unsigned int given
= i
.operands
- j
- 1;
2145 /* For 4- and 5-operand insns VEX.W controls just the first two
2146 register operands. */
2147 if (t
->opcode_modifier
.vexsources
)
2148 given
= j
< 2 ? 1 - j
: j
;
2150 if (t
->operand_types
[j
].bitfield
.class == Reg
2151 && !match_operand_size (t
, j
, given
))
2154 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2155 && !match_simd_size (t
, j
, given
))
2158 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2159 && (!match_operand_size (t
, j
, given
)
2160 || !match_simd_size (t
, j
, given
)))
2163 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2167 return match
| MATCH_REVERSE
;
2171 operand_type_match (i386_operand_type overlap
,
2172 i386_operand_type given
)
2174 i386_operand_type temp
= overlap
;
2176 temp
.bitfield
.unspecified
= 0;
2177 temp
.bitfield
.byte
= 0;
2178 temp
.bitfield
.word
= 0;
2179 temp
.bitfield
.dword
= 0;
2180 temp
.bitfield
.fword
= 0;
2181 temp
.bitfield
.qword
= 0;
2182 temp
.bitfield
.tbyte
= 0;
2183 temp
.bitfield
.xmmword
= 0;
2184 temp
.bitfield
.ymmword
= 0;
2185 temp
.bitfield
.zmmword
= 0;
2186 temp
.bitfield
.tmmword
= 0;
2187 if (operand_type_all_zero (&temp
))
2190 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2194 i
.error
= operand_type_mismatch
;
2198 /* If given types g0 and g1 are registers they must be of the same type
2199 unless the expected operand type register overlap is null.
2200 Intel syntax sized memory operands are also checked here. */
2203 operand_type_register_match (i386_operand_type g0
,
2204 i386_operand_type t0
,
2205 i386_operand_type g1
,
2206 i386_operand_type t1
)
2208 if (g0
.bitfield
.class != Reg
2209 && g0
.bitfield
.class != RegSIMD
2210 && (g0
.bitfield
.unspecified
2211 || !operand_type_check (g0
, anymem
)))
2214 if (g1
.bitfield
.class != Reg
2215 && g1
.bitfield
.class != RegSIMD
2216 && (g1
.bitfield
.unspecified
2217 || !operand_type_check (g1
, anymem
)))
2220 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2221 && g0
.bitfield
.word
== g1
.bitfield
.word
2222 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2223 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2224 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2225 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2226 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2229 /* If expectations overlap in no more than a single size, all is fine. */
2230 g0
= operand_type_and (t0
, t1
);
2231 if (g0
.bitfield
.byte
2235 + g0
.bitfield
.xmmword
2236 + g0
.bitfield
.ymmword
2237 + g0
.bitfield
.zmmword
<= 1)
2240 i
.error
= register_type_mismatch
;
2245 static INLINE
unsigned int
2246 register_number (const reg_entry
*r
)
2248 unsigned int nr
= r
->reg_num
;
2250 if (r
->reg_flags
& RegRex
)
2253 if (r
->reg_flags
& RegVRex
)
2259 static INLINE
unsigned int
2260 mode_from_disp_size (i386_operand_type t
)
2262 if (t
.bitfield
.disp8
)
2264 else if (t
.bitfield
.disp16
2265 || t
.bitfield
.disp32
)
2272 fits_in_signed_byte (addressT num
)
2274 return num
+ 0x80 <= 0xff;
2278 fits_in_unsigned_byte (addressT num
)
2284 fits_in_unsigned_word (addressT num
)
2286 return num
<= 0xffff;
2290 fits_in_signed_word (addressT num
)
2292 return num
+ 0x8000 <= 0xffff;
2296 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2301 return num
+ 0x80000000 <= 0xffffffff;
2303 } /* fits_in_signed_long() */
2306 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2311 return num
<= 0xffffffff;
2313 } /* fits_in_unsigned_long() */
2315 static INLINE valueT
extend_to_32bit_address (addressT num
)
2318 if (fits_in_unsigned_long(num
))
2319 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2321 if (!fits_in_signed_long (num
))
2322 return num
& 0xffffffff;
2329 fits_in_disp8 (offsetT num
)
2331 int shift
= i
.memshift
;
2337 mask
= (1 << shift
) - 1;
2339 /* Return 0 if NUM isn't properly aligned. */
2343 /* Check if NUM will fit in 8bit after shift. */
2344 return fits_in_signed_byte (num
>> shift
);
2348 fits_in_imm4 (offsetT num
)
2350 return (num
& 0xf) == num
;
2353 static i386_operand_type
2354 smallest_imm_type (offsetT num
)
2356 i386_operand_type t
;
2358 operand_type_set (&t
, 0);
2359 t
.bitfield
.imm64
= 1;
2361 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2363 /* This code is disabled on the 486 because all the Imm1 forms
2364 in the opcode table are slower on the i486. They're the
2365 versions with the implicitly specified single-position
2366 displacement, which has another syntax if you really want to
2368 t
.bitfield
.imm1
= 1;
2369 t
.bitfield
.imm8
= 1;
2370 t
.bitfield
.imm8s
= 1;
2371 t
.bitfield
.imm16
= 1;
2372 t
.bitfield
.imm32
= 1;
2373 t
.bitfield
.imm32s
= 1;
2375 else if (fits_in_signed_byte (num
))
2377 t
.bitfield
.imm8
= 1;
2378 t
.bitfield
.imm8s
= 1;
2379 t
.bitfield
.imm16
= 1;
2380 t
.bitfield
.imm32
= 1;
2381 t
.bitfield
.imm32s
= 1;
2383 else if (fits_in_unsigned_byte (num
))
2385 t
.bitfield
.imm8
= 1;
2386 t
.bitfield
.imm16
= 1;
2387 t
.bitfield
.imm32
= 1;
2388 t
.bitfield
.imm32s
= 1;
2390 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2392 t
.bitfield
.imm16
= 1;
2393 t
.bitfield
.imm32
= 1;
2394 t
.bitfield
.imm32s
= 1;
2396 else if (fits_in_signed_long (num
))
2398 t
.bitfield
.imm32
= 1;
2399 t
.bitfield
.imm32s
= 1;
2401 else if (fits_in_unsigned_long (num
))
2402 t
.bitfield
.imm32
= 1;
2408 offset_in_range (offsetT val
, int size
)
2414 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2415 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2417 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2419 case sizeof (val
): return val
;
2423 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2424 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2425 (uint64_t) val
, (uint64_t) (val
& mask
));
2430 static INLINE
const char *insn_name (const insn_template
*t
)
2432 return &i386_mnemonics
[t
->mnem_off
];
2445 a. PREFIX_EXIST if attempting to add a prefix where one from the
2446 same class already exists.
2447 b. PREFIX_LOCK if lock prefix is added.
2448 c. PREFIX_REP if rep/repne prefix is added.
2449 d. PREFIX_DS if ds prefix is added.
2450 e. PREFIX_OTHER if other prefix is added.
2453 static enum PREFIX_GROUP
2454 add_prefix (unsigned int prefix
)
2456 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2459 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2460 && flag_code
== CODE_64BIT
)
2462 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2463 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2464 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2465 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2476 case DS_PREFIX_OPCODE
:
2479 case CS_PREFIX_OPCODE
:
2480 case ES_PREFIX_OPCODE
:
2481 case FS_PREFIX_OPCODE
:
2482 case GS_PREFIX_OPCODE
:
2483 case SS_PREFIX_OPCODE
:
2487 case REPNE_PREFIX_OPCODE
:
2488 case REPE_PREFIX_OPCODE
:
2493 case LOCK_PREFIX_OPCODE
:
2502 case ADDR_PREFIX_OPCODE
:
2506 case DATA_PREFIX_OPCODE
:
2510 if (i
.prefix
[q
] != 0)
2518 i
.prefix
[q
] |= prefix
;
2521 as_bad (_("same type of prefix used twice"));
2527 update_code_flag (int value
, int check
)
2529 PRINTF_LIKE ((*as_error
));
2531 flag_code
= (enum flag_code
) value
;
2532 if (flag_code
== CODE_64BIT
)
2534 cpu_arch_flags
.bitfield
.cpu64
= 1;
2535 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2539 cpu_arch_flags
.bitfield
.cpu64
= 0;
2540 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2542 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2545 as_error
= as_fatal
;
2548 (*as_error
) (_("64bit mode not supported on `%s'."),
2549 cpu_arch_name
? cpu_arch_name
: default_arch
);
2551 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2554 as_error
= as_fatal
;
2557 (*as_error
) (_("32bit mode not supported on `%s'."),
2558 cpu_arch_name
? cpu_arch_name
: default_arch
);
2560 stackop_size
= '\0';
2564 set_code_flag (int value
)
2566 update_code_flag (value
, 0);
2570 set_16bit_gcc_code_flag (int new_code_flag
)
2572 flag_code
= (enum flag_code
) new_code_flag
;
2573 if (flag_code
!= CODE_16BIT
)
2575 cpu_arch_flags
.bitfield
.cpu64
= 0;
2576 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2577 stackop_size
= LONG_MNEM_SUFFIX
;
2581 set_intel_syntax (int syntax_flag
)
2583 /* Find out if register prefixing is specified. */
2584 int ask_naked_reg
= 0;
2587 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2590 int e
= get_symbol_name (&string
);
2592 if (strcmp (string
, "prefix") == 0)
2594 else if (strcmp (string
, "noprefix") == 0)
2597 as_bad (_("bad argument to syntax directive."));
2598 (void) restore_line_pointer (e
);
2600 demand_empty_rest_of_line ();
2602 intel_syntax
= syntax_flag
;
2604 if (ask_naked_reg
== 0)
2605 allow_naked_reg
= (intel_syntax
2606 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2608 allow_naked_reg
= (ask_naked_reg
< 0);
2610 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2612 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2613 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2614 register_prefix
= allow_naked_reg
? "" : "%";
2618 set_intel_mnemonic (int mnemonic_flag
)
2620 intel_mnemonic
= mnemonic_flag
;
2624 set_allow_index_reg (int flag
)
2626 allow_index_reg
= flag
;
2630 set_check (int what
)
2632 enum check_kind
*kind
;
2637 kind
= &operand_check
;
2648 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2651 int e
= get_symbol_name (&string
);
2653 if (strcmp (string
, "none") == 0)
2655 else if (strcmp (string
, "warning") == 0)
2656 *kind
= check_warning
;
2657 else if (strcmp (string
, "error") == 0)
2658 *kind
= check_error
;
2660 as_bad (_("bad argument to %s_check directive."), str
);
2661 (void) restore_line_pointer (e
);
2664 as_bad (_("missing argument for %s_check directive"), str
);
2666 demand_empty_rest_of_line ();
2670 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2671 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2674 static const char *arch
;
2676 /* Intel MCU is only supported on ELF. */
2682 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2683 use default_arch. */
2684 arch
= cpu_arch_name
;
2686 arch
= default_arch
;
2689 /* If we are targeting Intel MCU, we must enable it. */
2690 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2691 == new_flag
.bitfield
.cpuiamcu
)
2694 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2699 extend_cpu_sub_arch_name (const char *name
)
2701 if (cpu_sub_arch_name
)
2702 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2703 ".", name
, (const char *) NULL
);
2705 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2709 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2711 typedef struct arch_stack_entry
2713 const struct arch_stack_entry
*prev
;
2716 i386_cpu_flags flags
;
2717 i386_cpu_flags isa_flags
;
2718 enum processor_type isa
;
2719 enum flag_code flag_code
;
2721 bool no_cond_jump_promotion
;
2723 static const arch_stack_entry
*arch_stack_top
;
2727 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2730 int e
= get_symbol_name (&s
);
2731 const char *string
= s
;
2733 i386_cpu_flags flags
;
2735 if (strcmp (string
, "default") == 0)
2737 if (strcmp (default_arch
, "iamcu") == 0)
2738 string
= default_arch
;
2741 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2743 cpu_arch_name
= NULL
;
2744 free (cpu_sub_arch_name
);
2745 cpu_sub_arch_name
= NULL
;
2746 cpu_arch_flags
= cpu_unknown_flags
;
2747 if (flag_code
== CODE_64BIT
)
2749 cpu_arch_flags
.bitfield
.cpu64
= 1;
2750 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2754 cpu_arch_flags
.bitfield
.cpu64
= 0;
2755 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2757 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2758 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2759 if (!cpu_arch_tune_set
)
2761 cpu_arch_tune
= cpu_arch_isa
;
2762 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2765 j
= ARRAY_SIZE (cpu_arch
) + 1;
2768 else if (strcmp (string
, "push") == 0)
2770 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2772 top
->name
= cpu_arch_name
;
2773 if (cpu_sub_arch_name
)
2774 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2776 top
->sub_name
= NULL
;
2777 top
->flags
= cpu_arch_flags
;
2778 top
->isa
= cpu_arch_isa
;
2779 top
->isa_flags
= cpu_arch_isa_flags
;
2780 top
->flag_code
= flag_code
;
2781 top
->stackop_size
= stackop_size
;
2782 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2784 top
->prev
= arch_stack_top
;
2785 arch_stack_top
= top
;
2787 (void) restore_line_pointer (e
);
2788 demand_empty_rest_of_line ();
2791 else if (strcmp (string
, "pop") == 0)
2793 const arch_stack_entry
*top
= arch_stack_top
;
2796 as_bad (_(".arch stack is empty"));
2797 else if (top
->flag_code
!= flag_code
2798 || top
->stackop_size
!= stackop_size
)
2800 static const unsigned int bits
[] = {
2806 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2807 bits
[top
->flag_code
],
2808 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2812 arch_stack_top
= top
->prev
;
2814 cpu_arch_name
= top
->name
;
2815 free (cpu_sub_arch_name
);
2816 cpu_sub_arch_name
= top
->sub_name
;
2817 cpu_arch_flags
= top
->flags
;
2818 cpu_arch_isa
= top
->isa
;
2819 cpu_arch_isa_flags
= top
->isa_flags
;
2820 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2825 (void) restore_line_pointer (e
);
2826 demand_empty_rest_of_line ();
2830 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2832 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2833 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2837 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2839 cpu_arch_name
= cpu_arch
[j
].name
;
2840 free (cpu_sub_arch_name
);
2841 cpu_sub_arch_name
= NULL
;
2842 cpu_arch_flags
= cpu_arch
[j
].enable
;
2843 if (flag_code
== CODE_64BIT
)
2845 cpu_arch_flags
.bitfield
.cpu64
= 1;
2846 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2850 cpu_arch_flags
.bitfield
.cpu64
= 0;
2851 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2853 cpu_arch_isa
= cpu_arch
[j
].type
;
2854 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2855 if (!cpu_arch_tune_set
)
2857 cpu_arch_tune
= cpu_arch_isa
;
2858 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2860 pre_386_16bit_warned
= false;
2864 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2867 flags
= cpu_flags_or (cpu_arch_flags
,
2868 cpu_arch
[j
].enable
);
2870 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2872 extend_cpu_sub_arch_name (string
+ 1);
2873 cpu_arch_flags
= flags
;
2874 cpu_arch_isa_flags
= flags
;
2878 = cpu_flags_or (cpu_arch_isa_flags
,
2879 cpu_arch
[j
].enable
);
2880 (void) restore_line_pointer (e
);
2881 demand_empty_rest_of_line ();
2886 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
2888 /* Disable an ISA extension. */
2889 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2890 if (cpu_arch
[j
].type
== PROCESSOR_NONE
2891 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
2893 flags
= cpu_flags_and_not (cpu_arch_flags
,
2894 cpu_arch
[j
].disable
);
2895 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2897 extend_cpu_sub_arch_name (string
+ 1);
2898 cpu_arch_flags
= flags
;
2899 cpu_arch_isa_flags
= flags
;
2901 (void) restore_line_pointer (e
);
2902 demand_empty_rest_of_line ();
2907 if (j
== ARRAY_SIZE (cpu_arch
))
2908 as_bad (_("no such architecture: `%s'"), string
);
2910 *input_line_pointer
= e
;
2913 as_bad (_("missing cpu architecture"));
2915 no_cond_jump_promotion
= 0;
2916 if (*input_line_pointer
== ','
2917 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2922 ++input_line_pointer
;
2923 e
= get_symbol_name (&string
);
2925 if (strcmp (string
, "nojumps") == 0)
2926 no_cond_jump_promotion
= 1;
2927 else if (strcmp (string
, "jumps") == 0)
2930 as_bad (_("no such architecture modifier: `%s'"), string
);
2932 (void) restore_line_pointer (e
);
2935 demand_empty_rest_of_line ();
2938 enum bfd_architecture
2941 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2943 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2944 || flag_code
== CODE_64BIT
)
2945 as_fatal (_("Intel MCU is 32bit ELF only"));
2946 return bfd_arch_iamcu
;
2949 return bfd_arch_i386
;
2955 if (startswith (default_arch
, "x86_64"))
2957 if (default_arch
[6] == '\0')
2958 return bfd_mach_x86_64
;
2960 return bfd_mach_x64_32
;
2962 else if (!strcmp (default_arch
, "i386")
2963 || !strcmp (default_arch
, "iamcu"))
2965 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2967 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2968 as_fatal (_("Intel MCU is 32bit ELF only"));
2969 return bfd_mach_i386_iamcu
;
2972 return bfd_mach_i386_i386
;
2975 as_fatal (_("unknown architecture"));
2978 #include "opcodes/i386-tbl.h"
2983 /* Support pseudo prefixes like {disp32}. */
2984 lex_type
['{'] = LEX_BEGIN_NAME
;
2986 /* Initialize op_hash hash table. */
2987 op_hash
= str_htab_create ();
2990 const insn_template
*const *sets
= i386_op_sets
;
2991 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
2993 /* Type checks to compensate for the conversion through void * which
2994 occurs during hash table insertion / lookup. */
2995 (void) sizeof (sets
== ¤t_templates
->start
);
2996 (void) sizeof (end
== ¤t_templates
->end
);
2997 for (; sets
< end
; ++sets
)
2998 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
2999 as_fatal (_("duplicate %s"), insn_name (*sets
));
3002 /* Initialize reg_hash hash table. */
3003 reg_hash
= str_htab_create ();
3005 const reg_entry
*regtab
;
3006 unsigned int regtab_size
= i386_regtab_size
;
3008 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3010 switch (regtab
->reg_type
.bitfield
.class)
3013 if (regtab
->reg_type
.bitfield
.dword
)
3015 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3018 else if (regtab
->reg_type
.bitfield
.tbyte
)
3020 /* There's no point inserting st(<N>) in the hash table, as
3021 parentheses aren't included in register_chars[] anyway. */
3022 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3029 switch (regtab
->reg_num
)
3031 case 0: reg_es
= regtab
; break;
3032 case 2: reg_ss
= regtab
; break;
3033 case 3: reg_ds
= regtab
; break;
3038 if (!regtab
->reg_num
)
3043 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3044 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3048 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3053 for (c
= 0; c
< 256; c
++)
3055 if (ISDIGIT (c
) || ISLOWER (c
))
3057 mnemonic_chars
[c
] = c
;
3058 register_chars
[c
] = c
;
3059 operand_chars
[c
] = c
;
3061 else if (ISUPPER (c
))
3063 mnemonic_chars
[c
] = TOLOWER (c
);
3064 register_chars
[c
] = mnemonic_chars
[c
];
3065 operand_chars
[c
] = c
;
3067 else if (c
== '{' || c
== '}')
3069 mnemonic_chars
[c
] = c
;
3070 operand_chars
[c
] = c
;
3072 #ifdef SVR4_COMMENT_CHARS
3073 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3074 operand_chars
[c
] = c
;
3077 if (ISALPHA (c
) || ISDIGIT (c
))
3078 identifier_chars
[c
] = c
;
3081 identifier_chars
[c
] = c
;
3082 operand_chars
[c
] = c
;
3087 identifier_chars
['@'] = '@';
3090 identifier_chars
['?'] = '?';
3091 operand_chars
['?'] = '?';
3093 mnemonic_chars
['_'] = '_';
3094 mnemonic_chars
['-'] = '-';
3095 mnemonic_chars
['.'] = '.';
3096 identifier_chars
['_'] = '_';
3097 identifier_chars
['.'] = '.';
3099 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3100 operand_chars
[(unsigned char) *p
] = *p
;
3103 if (flag_code
== CODE_64BIT
)
3105 #if defined (OBJ_COFF) && defined (TE_PE)
3106 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3109 x86_dwarf2_return_column
= 16;
3111 x86_cie_data_alignment
= -8;
3112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3113 x86_sframe_cfa_sp_reg
= 7;
3114 x86_sframe_cfa_fp_reg
= 6;
3119 x86_dwarf2_return_column
= 8;
3120 x86_cie_data_alignment
= -4;
3123 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3124 can be turned into BRANCH_PREFIX frag. */
3125 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3130 i386_print_statistics (FILE *file
)
3132 htab_print_statistics (file
, "i386 opcode", op_hash
);
3133 htab_print_statistics (file
, "i386 register", reg_hash
);
3139 htab_delete (op_hash
);
3140 htab_delete (reg_hash
);
3145 /* Debugging routines for md_assemble. */
3146 static void pte (insn_template
*);
3147 static void pt (i386_operand_type
);
3148 static void pe (expressionS
*);
3149 static void ps (symbolS
*);
3152 pi (const char *line
, i386_insn
*x
)
3156 fprintf (stdout
, "%s: template ", line
);
3158 fprintf (stdout
, " address: base %s index %s scale %x\n",
3159 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3160 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3161 x
->log2_scale_factor
);
3162 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3163 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3164 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3165 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3166 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3167 (x
->rex
& REX_W
) != 0,
3168 (x
->rex
& REX_R
) != 0,
3169 (x
->rex
& REX_X
) != 0,
3170 (x
->rex
& REX_B
) != 0);
3171 for (j
= 0; j
< x
->operands
; j
++)
3173 fprintf (stdout
, " #%d: ", j
+ 1);
3175 fprintf (stdout
, "\n");
3176 if (x
->types
[j
].bitfield
.class == Reg
3177 || x
->types
[j
].bitfield
.class == RegMMX
3178 || x
->types
[j
].bitfield
.class == RegSIMD
3179 || x
->types
[j
].bitfield
.class == RegMask
3180 || x
->types
[j
].bitfield
.class == SReg
3181 || x
->types
[j
].bitfield
.class == RegCR
3182 || x
->types
[j
].bitfield
.class == RegDR
3183 || x
->types
[j
].bitfield
.class == RegTR
3184 || x
->types
[j
].bitfield
.class == RegBND
)
3185 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3186 if (operand_type_check (x
->types
[j
], imm
))
3188 if (operand_type_check (x
->types
[j
], disp
))
3189 pe (x
->op
[j
].disps
);
3194 pte (insn_template
*t
)
3196 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3197 static const char *const opc_spc
[] = {
3198 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3199 "XOP08", "XOP09", "XOP0A",
3203 fprintf (stdout
, " %d operands ", t
->operands
);
3204 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3205 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3206 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3207 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3208 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3209 if (t
->extension_opcode
!= None
)
3210 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3211 if (t
->opcode_modifier
.d
)
3212 fprintf (stdout
, "D");
3213 if (t
->opcode_modifier
.w
)
3214 fprintf (stdout
, "W");
3215 fprintf (stdout
, "\n");
3216 for (j
= 0; j
< t
->operands
; j
++)
3218 fprintf (stdout
, " #%d type ", j
+ 1);
3219 pt (t
->operand_types
[j
]);
3220 fprintf (stdout
, "\n");
3227 fprintf (stdout
, " operation %d\n", e
->X_op
);
3228 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3229 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3230 if (e
->X_add_symbol
)
3232 fprintf (stdout
, " add_symbol ");
3233 ps (e
->X_add_symbol
);
3234 fprintf (stdout
, "\n");
3238 fprintf (stdout
, " op_symbol ");
3239 ps (e
->X_op_symbol
);
3240 fprintf (stdout
, "\n");
3247 fprintf (stdout
, "%s type %s%s",
3249 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3250 segment_name (S_GET_SEGMENT (s
)));
3253 static struct type_name
3255 i386_operand_type mask
;
3258 const type_names
[] =
3260 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3261 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3262 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3263 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3264 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3265 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3266 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3267 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3268 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3269 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3270 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3271 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3272 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3273 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3274 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3275 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3276 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3277 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3278 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3279 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3280 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3281 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3282 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3283 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3284 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3285 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3286 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3287 { { .bitfield
= { .class = SReg
} }, "SReg" },
3288 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3289 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3290 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3291 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3292 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3293 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3297 pt (i386_operand_type t
)
3300 i386_operand_type a
;
3302 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3304 a
= operand_type_and (t
, type_names
[j
].mask
);
3305 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3306 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3311 #endif /* DEBUG386 */
3313 static bfd_reloc_code_real_type
3314 reloc (unsigned int size
,
3317 bfd_reloc_code_real_type other
)
3319 if (other
!= NO_RELOC
)
3321 reloc_howto_type
*rel
;
3326 case BFD_RELOC_X86_64_GOT32
:
3327 return BFD_RELOC_X86_64_GOT64
;
3329 case BFD_RELOC_X86_64_GOTPLT64
:
3330 return BFD_RELOC_X86_64_GOTPLT64
;
3332 case BFD_RELOC_X86_64_PLTOFF64
:
3333 return BFD_RELOC_X86_64_PLTOFF64
;
3335 case BFD_RELOC_X86_64_GOTPC32
:
3336 other
= BFD_RELOC_X86_64_GOTPC64
;
3338 case BFD_RELOC_X86_64_GOTPCREL
:
3339 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3341 case BFD_RELOC_X86_64_TPOFF32
:
3342 other
= BFD_RELOC_X86_64_TPOFF64
;
3344 case BFD_RELOC_X86_64_DTPOFF32
:
3345 other
= BFD_RELOC_X86_64_DTPOFF64
;
3351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3352 if (other
== BFD_RELOC_SIZE32
)
3355 other
= BFD_RELOC_SIZE64
;
3358 as_bad (_("there are no pc-relative size relocations"));
3364 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3365 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3368 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3370 as_bad (_("unknown relocation (%u)"), other
);
3371 else if (size
!= bfd_get_reloc_size (rel
))
3372 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3373 bfd_get_reloc_size (rel
),
3375 else if (pcrel
&& !rel
->pc_relative
)
3376 as_bad (_("non-pc-relative relocation for pc-relative field"));
3377 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3379 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3381 as_bad (_("relocated field and relocation type differ in signedness"));
3390 as_bad (_("there are no unsigned pc-relative relocations"));
3393 case 1: return BFD_RELOC_8_PCREL
;
3394 case 2: return BFD_RELOC_16_PCREL
;
3395 case 4: return BFD_RELOC_32_PCREL
;
3396 case 8: return BFD_RELOC_64_PCREL
;
3398 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3405 case 4: return BFD_RELOC_X86_64_32S
;
3410 case 1: return BFD_RELOC_8
;
3411 case 2: return BFD_RELOC_16
;
3412 case 4: return BFD_RELOC_32
;
3413 case 8: return BFD_RELOC_64
;
3415 as_bad (_("cannot do %s %u byte relocation"),
3416 sign
> 0 ? "signed" : "unsigned", size
);
3422 /* Here we decide which fixups can be adjusted to make them relative to
3423 the beginning of the section instead of the symbol. Basically we need
3424 to make sure that the dynamic relocations are done correctly, so in
3425 some cases we force the original symbol to be used. */
3428 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3434 /* Don't adjust pc-relative references to merge sections in 64-bit
3436 if (use_rela_relocations
3437 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3441 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3442 and changed later by validate_fix. */
3443 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3444 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3447 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3448 for size relocations. */
3449 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3450 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3451 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3452 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3453 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3454 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3455 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3456 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3457 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3458 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3459 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3461 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3464 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3465 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3466 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3467 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3468 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3469 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3478 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3479 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3486 want_disp32 (const insn_template
*t
)
3488 return flag_code
!= CODE_64BIT
3489 || i
.prefix
[ADDR_PREFIX
]
3490 || (t
->mnem_off
== MN_lea
3491 && (!i
.types
[1].bitfield
.qword
3492 || t
->opcode_modifier
.size
== SIZE32
));
3496 intel_float_operand (const char *mnemonic
)
3498 /* Note that the value returned is meaningful only for opcodes with (memory)
3499 operands, hence the code here is free to improperly handle opcodes that
3500 have no operands (for better performance and smaller code). */
3502 if (mnemonic
[0] != 'f')
3503 return 0; /* non-math */
3505 switch (mnemonic
[1])
3507 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3508 the fs segment override prefix not currently handled because no
3509 call path can make opcodes without operands get here */
3511 return 2 /* integer op */;
3513 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3514 return 3; /* fldcw/fldenv */
3517 if (mnemonic
[2] != 'o' /* fnop */)
3518 return 3; /* non-waiting control op */
3521 if (mnemonic
[2] == 's')
3522 return 3; /* frstor/frstpm */
3525 if (mnemonic
[2] == 'a')
3526 return 3; /* fsave */
3527 if (mnemonic
[2] == 't')
3529 switch (mnemonic
[3])
3531 case 'c': /* fstcw */
3532 case 'd': /* fstdw */
3533 case 'e': /* fstenv */
3534 case 's': /* fsts[gw] */
3540 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3541 return 0; /* fxsave/fxrstor are not really math ops */
3549 install_template (const insn_template
*t
)
3555 /* Note that for pseudo prefixes this produces a length of 1. But for them
3556 the length isn't interesting at all. */
3557 for (l
= 1; l
< 4; ++l
)
3558 if (!(t
->base_opcode
>> (8 * l
)))
3561 i
.opcode_length
= l
;
3564 /* Build the VEX prefix. */
3567 build_vex_prefix (const insn_template
*t
)
3569 unsigned int register_specifier
;
3570 unsigned int vector_length
;
3573 /* Check register specifier. */
3574 if (i
.vex
.register_specifier
)
3576 register_specifier
=
3577 ~register_number (i
.vex
.register_specifier
) & 0xf;
3578 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3581 register_specifier
= 0xf;
3583 /* Use 2-byte VEX prefix by swapping destination and source operand
3584 if there are more than 1 register operand. */
3585 if (i
.reg_operands
> 1
3586 && i
.vec_encoding
!= vex_encoding_vex3
3587 && i
.dir_encoding
== dir_encoding_default
3588 && i
.operands
== i
.reg_operands
3589 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3590 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3591 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3594 unsigned int xchg
= i
.operands
- 1;
3595 union i386_op temp_op
;
3596 i386_operand_type temp_type
;
3598 temp_type
= i
.types
[xchg
];
3599 i
.types
[xchg
] = i
.types
[0];
3600 i
.types
[0] = temp_type
;
3601 temp_op
= i
.op
[xchg
];
3602 i
.op
[xchg
] = i
.op
[0];
3605 gas_assert (i
.rm
.mode
== 3);
3609 i
.rm
.regmem
= i
.rm
.reg
;
3612 if (i
.tm
.opcode_modifier
.d
)
3613 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3614 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3615 else /* Use the next insn. */
3616 install_template (&t
[1]);
3619 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3620 are no memory operands and at least 3 register ones. */
3621 if (i
.reg_operands
>= 3
3622 && i
.vec_encoding
!= vex_encoding_vex3
3623 && i
.reg_operands
== i
.operands
- i
.imm_operands
3624 && i
.tm
.opcode_modifier
.vex
3625 && i
.tm
.opcode_modifier
.commutative
3626 && (i
.tm
.opcode_modifier
.sse2avx
3627 || (optimize
> 1 && !i
.no_optimize
))
3629 && i
.vex
.register_specifier
3630 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3632 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3633 union i386_op temp_op
;
3634 i386_operand_type temp_type
;
3636 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3637 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3638 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3639 &i
.types
[i
.operands
- 3]));
3640 gas_assert (i
.rm
.mode
== 3);
3642 temp_type
= i
.types
[xchg
];
3643 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3644 i
.types
[xchg
+ 1] = temp_type
;
3645 temp_op
= i
.op
[xchg
];
3646 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3647 i
.op
[xchg
+ 1] = temp_op
;
3650 xchg
= i
.rm
.regmem
| 8;
3651 i
.rm
.regmem
= ~register_specifier
& 0xf;
3652 gas_assert (!(i
.rm
.regmem
& 8));
3653 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3654 register_specifier
= ~xchg
& 0xf;
3657 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3658 vector_length
= avxscalar
;
3659 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3665 /* Determine vector length from the last multi-length vector
3668 for (op
= t
->operands
; op
--;)
3669 if (t
->operand_types
[op
].bitfield
.xmmword
3670 && t
->operand_types
[op
].bitfield
.ymmword
3671 && i
.types
[op
].bitfield
.ymmword
)
3678 /* Check the REX.W bit and VEXW. */
3679 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3680 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3681 else if (i
.tm
.opcode_modifier
.vexw
)
3682 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3684 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3686 /* Use 2-byte VEX prefix if possible. */
3688 && i
.vec_encoding
!= vex_encoding_vex3
3689 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3690 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3692 /* 2-byte VEX prefix. */
3696 i
.vex
.bytes
[0] = 0xc5;
3698 /* Check the REX.R bit. */
3699 r
= (i
.rex
& REX_R
) ? 0 : 1;
3700 i
.vex
.bytes
[1] = (r
<< 7
3701 | register_specifier
<< 3
3702 | vector_length
<< 2
3703 | i
.tm
.opcode_modifier
.opcodeprefix
);
3707 /* 3-byte VEX prefix. */
3710 switch (i
.tm
.opcode_modifier
.opcodespace
)
3715 i
.vex
.bytes
[0] = 0xc4;
3720 i
.vex
.bytes
[0] = 0x8f;
3726 /* The high 3 bits of the second VEX byte are 1's compliment
3727 of RXB bits from REX. */
3728 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3730 i
.vex
.bytes
[2] = (w
<< 7
3731 | register_specifier
<< 3
3732 | vector_length
<< 2
3733 | i
.tm
.opcode_modifier
.opcodeprefix
);
3738 is_evex_encoding (const insn_template
*t
)
3740 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3741 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3742 || t
->opcode_modifier
.sae
;
3746 is_any_vex_encoding (const insn_template
*t
)
3748 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3752 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3754 unsigned int op
, bytes
;
3755 const i386_operand_type
*types
;
3757 if (i
.broadcast
.type
)
3758 return i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
3759 * i
.broadcast
.type
);
3761 gas_assert (intel_syntax
);
3763 for (op
= 0; op
< t
->operands
; ++op
)
3764 if (t
->operand_types
[op
].bitfield
.baseindex
)
3767 gas_assert (op
< t
->operands
);
3769 if (t
->opcode_modifier
.evex
3770 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3771 switch (i
.broadcast
.bytes
)
3774 if (t
->operand_types
[op
].bitfield
.word
)
3778 if (t
->operand_types
[op
].bitfield
.dword
)
3782 if (t
->operand_types
[op
].bitfield
.qword
)
3786 if (t
->operand_types
[op
].bitfield
.xmmword
)
3788 if (t
->operand_types
[op
].bitfield
.ymmword
)
3790 if (t
->operand_types
[op
].bitfield
.zmmword
)
3797 gas_assert (op
+ 1 < t
->operands
);
3799 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3800 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3801 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3803 types
= &i
.types
[op
+ 1];
3806 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3807 types
= &t
->operand_types
[op
];
3809 if (types
->bitfield
.zmmword
)
3811 else if (types
->bitfield
.ymmword
)
3817 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3818 insn_name (t
), bytes
* 8);
3823 /* Build the EVEX prefix. */
3826 build_evex_prefix (void)
3828 unsigned int register_specifier
, w
;
3829 rex_byte vrex_used
= 0;
3831 /* Check register specifier. */
3832 if (i
.vex
.register_specifier
)
3834 gas_assert ((i
.vrex
& REX_X
) == 0);
3836 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3837 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3838 register_specifier
+= 8;
3839 /* The upper 16 registers are encoded in the fourth byte of the
3841 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3842 i
.vex
.bytes
[3] = 0x8;
3843 register_specifier
= ~register_specifier
& 0xf;
3847 register_specifier
= 0xf;
3849 /* Encode upper 16 vector index register in the fourth byte of
3851 if (!(i
.vrex
& REX_X
))
3852 i
.vex
.bytes
[3] = 0x8;
3857 /* 4 byte EVEX prefix. */
3859 i
.vex
.bytes
[0] = 0x62;
3861 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3863 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3864 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_EVEXMAP6
);
3865 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3867 /* The fifth bit of the second EVEX byte is 1's compliment of the
3868 REX_R bit in VREX. */
3869 if (!(i
.vrex
& REX_R
))
3870 i
.vex
.bytes
[1] |= 0x10;
3874 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3876 /* When all operands are registers, the REX_X bit in REX is not
3877 used. We reuse it to encode the upper 16 registers, which is
3878 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3879 as 1's compliment. */
3880 if ((i
.vrex
& REX_B
))
3883 i
.vex
.bytes
[1] &= ~0x40;
3887 /* EVEX instructions shouldn't need the REX prefix. */
3888 i
.vrex
&= ~vrex_used
;
3889 gas_assert (i
.vrex
== 0);
3891 /* Check the REX.W bit and VEXW. */
3892 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3893 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3894 else if (i
.tm
.opcode_modifier
.vexw
)
3895 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3897 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3899 /* The third byte of the EVEX prefix. */
3900 i
.vex
.bytes
[2] = ((w
<< 7)
3901 | (register_specifier
<< 3)
3902 | 4 /* Encode the U bit. */
3903 | i
.tm
.opcode_modifier
.opcodeprefix
);
3905 /* The fourth byte of the EVEX prefix. */
3906 /* The zeroing-masking bit. */
3907 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3908 i
.vex
.bytes
[3] |= 0x80;
3910 /* Don't always set the broadcast bit if there is no RC. */
3911 if (i
.rounding
.type
== rc_none
)
3913 /* Encode the vector length. */
3914 unsigned int vec_length
;
3916 if (!i
.tm
.opcode_modifier
.evex
3917 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3921 /* Determine vector length from the last multi-length vector
3923 for (op
= i
.operands
; op
--;)
3924 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3925 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3926 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3928 if (i
.types
[op
].bitfield
.zmmword
)
3930 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3933 else if (i
.types
[op
].bitfield
.ymmword
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3938 else if (i
.types
[op
].bitfield
.xmmword
)
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3943 else if (i
.broadcast
.bytes
&& op
== i
.broadcast
.operand
)
3945 switch (get_broadcast_bytes (&i
.tm
, true))
3948 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3951 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3954 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3963 if (op
>= MAX_OPERANDS
)
3967 switch (i
.tm
.opcode_modifier
.evex
)
3969 case EVEXLIG
: /* LL' is ignored */
3970 vec_length
= evexlig
<< 5;
3973 vec_length
= 0 << 5;
3976 vec_length
= 1 << 5;
3979 vec_length
= 2 << 5;
3985 i
.vex
.bytes
[3] |= vec_length
;
3986 /* Encode the broadcast bit. */
3987 if (i
.broadcast
.bytes
)
3988 i
.vex
.bytes
[3] |= 0x10;
3990 else if (i
.rounding
.type
!= saeonly
)
3991 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3993 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3996 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4000 process_immext (void)
4004 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4005 which is coded in the same place as an 8-bit immediate field
4006 would be. Here we fake an 8-bit immediate operand from the
4007 opcode suffix stored in tm.extension_opcode.
4009 AVX instructions also use this encoding, for some of
4010 3 argument instructions. */
4012 gas_assert (i
.imm_operands
<= 1
4014 || (is_any_vex_encoding (&i
.tm
)
4015 && i
.operands
<= 4)));
4017 exp
= &im_expressions
[i
.imm_operands
++];
4018 i
.op
[i
.operands
].imms
= exp
;
4019 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4021 exp
->X_op
= O_constant
;
4022 exp
->X_add_number
= i
.tm
.extension_opcode
;
4023 i
.tm
.extension_opcode
= None
;
4030 switch (i
.tm
.opcode_modifier
.prefixok
)
4038 as_bad (_("invalid instruction `%s' after `%s'"),
4039 insn_name (&i
.tm
), i
.hle_prefix
);
4042 if (i
.prefix
[LOCK_PREFIX
])
4044 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4048 case PrefixHLERelease
:
4049 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4051 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4055 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4057 as_bad (_("memory destination needed for instruction `%s'"
4058 " after `xrelease'"), insn_name (&i
.tm
));
4065 /* Encode aligned vector move as unaligned vector move. */
4068 encode_with_unaligned_vector_move (void)
4070 switch (i
.tm
.base_opcode
)
4072 case 0x28: /* Load instructions. */
4073 case 0x29: /* Store instructions. */
4074 /* movaps/movapd/vmovaps/vmovapd. */
4075 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4076 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4077 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4079 case 0x6f: /* Load instructions. */
4080 case 0x7f: /* Store instructions. */
4081 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4082 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4083 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4084 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4091 /* Try the shortest encoding by shortening operand size. */
4094 optimize_encoding (void)
4098 if (i
.tm
.mnem_off
== MN_lea
)
4101 lea symbol, %rN -> mov $symbol, %rN
4102 lea (%rM), %rN -> mov %rM, %rN
4103 lea (,%rM,1), %rN -> mov %rM, %rN
4105 and in 32-bit mode for 16-bit addressing
4107 lea (%rM), %rN -> movzx %rM, %rN
4109 and in 64-bit mode zap 32-bit addressing in favor of using a
4110 32-bit (or less) destination.
4112 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4114 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4115 i
.tm
.opcode_modifier
.size
= SIZE32
;
4116 i
.prefix
[ADDR_PREFIX
] = 0;
4119 if (!i
.index_reg
&& !i
.base_reg
)
4122 lea symbol, %rN -> mov $symbol, %rN
4124 if (flag_code
== CODE_64BIT
)
4126 /* Don't transform a relocation to a 16-bit one. */
4128 && i
.op
[0].disps
->X_op
!= O_constant
4129 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4132 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4133 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4135 i
.tm
.base_opcode
= 0xb8;
4136 i
.tm
.opcode_modifier
.modrm
= 0;
4137 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4138 i
.types
[0].bitfield
.imm32
= 1;
4141 i
.tm
.opcode_modifier
.size
= SIZE16
;
4142 i
.types
[0].bitfield
.imm16
= 1;
4147 /* Subject to further optimization below. */
4148 i
.tm
.base_opcode
= 0xc7;
4149 i
.tm
.extension_opcode
= 0;
4150 i
.types
[0].bitfield
.imm32s
= 1;
4151 i
.types
[0].bitfield
.baseindex
= 0;
4154 /* Outside of 64-bit mode address and operand sizes have to match if
4155 a relocation is involved, as otherwise we wouldn't (currently) or
4156 even couldn't express the relocation correctly. */
4157 else if (i
.op
[0].disps
4158 && i
.op
[0].disps
->X_op
!= O_constant
4159 && ((!i
.prefix
[ADDR_PREFIX
])
4160 != (flag_code
== CODE_32BIT
4161 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4162 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4164 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4165 destination is going to grow encoding size. */
4166 else if (flag_code
== CODE_16BIT
4167 && (optimize
<= 1 || optimize_for_space
)
4168 && !i
.prefix
[ADDR_PREFIX
]
4169 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4173 i
.tm
.base_opcode
= 0xb8;
4174 i
.tm
.opcode_modifier
.modrm
= 0;
4175 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4176 i
.types
[0].bitfield
.imm32
= 1;
4178 i
.types
[0].bitfield
.imm16
= 1;
4181 && i
.op
[0].disps
->X_op
== O_constant
4182 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4183 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4185 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4186 i
.op
[0].disps
->X_add_number
&= 0xffff;
4189 i
.tm
.operand_types
[0] = i
.types
[0];
4193 i
.op
[0].imms
= &im_expressions
[0];
4194 i
.op
[0].imms
->X_op
= O_absent
;
4197 else if (i
.op
[0].disps
4198 && (i
.op
[0].disps
->X_op
!= O_constant
4199 || i
.op
[0].disps
->X_add_number
))
4204 lea (%rM), %rN -> mov %rM, %rN
4205 lea (,%rM,1), %rN -> mov %rM, %rN
4206 lea (%rM), %rN -> movzx %rM, %rN
4208 const reg_entry
*addr_reg
;
4210 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4211 addr_reg
= i
.base_reg
;
4212 else if (!i
.base_reg
4213 && i
.index_reg
->reg_num
!= RegIZ
4214 && !i
.log2_scale_factor
)
4215 addr_reg
= i
.index_reg
;
4219 if (addr_reg
->reg_type
.bitfield
.word
4220 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4222 if (flag_code
!= CODE_32BIT
)
4224 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4225 i
.tm
.base_opcode
= 0xb7;
4228 i
.tm
.base_opcode
= 0x8b;
4230 if (addr_reg
->reg_type
.bitfield
.dword
4231 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4232 i
.tm
.opcode_modifier
.size
= SIZE32
;
4234 i
.op
[0].regs
= addr_reg
;
4239 i
.disp_operands
= 0;
4240 i
.prefix
[ADDR_PREFIX
] = 0;
4241 i
.prefix
[SEG_PREFIX
] = 0;
4245 if (optimize_for_space
4246 && i
.tm
.mnem_off
== MN_test
4247 && i
.reg_operands
== 1
4248 && i
.imm_operands
== 1
4249 && !i
.types
[1].bitfield
.byte
4250 && i
.op
[0].imms
->X_op
== O_constant
4251 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4254 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4256 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4257 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4259 i
.types
[1].bitfield
.byte
= 1;
4260 /* Ignore the suffix. */
4262 /* Convert to byte registers. */
4263 if (i
.types
[1].bitfield
.word
)
4265 else if (i
.types
[1].bitfield
.dword
)
4269 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4274 else if (flag_code
== CODE_64BIT
4275 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4276 && ((i
.types
[1].bitfield
.qword
4277 && i
.reg_operands
== 1
4278 && i
.imm_operands
== 1
4279 && i
.op
[0].imms
->X_op
== O_constant
4280 && ((i
.tm
.base_opcode
== 0xb8
4281 && i
.tm
.extension_opcode
== None
4282 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4283 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4284 && (i
.tm
.base_opcode
== 0x24
4285 || (i
.tm
.base_opcode
== 0x80
4286 && i
.tm
.extension_opcode
== 0x4)
4287 || i
.tm
.mnem_off
== MN_test
4288 || ((i
.tm
.base_opcode
| 1) == 0xc7
4289 && i
.tm
.extension_opcode
== 0x0)))
4290 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4291 && i
.tm
.base_opcode
== 0x83
4292 && i
.tm
.extension_opcode
== 0x4)))
4293 || (i
.types
[0].bitfield
.qword
4294 && ((i
.reg_operands
== 2
4295 && i
.op
[0].regs
== i
.op
[1].regs
4296 && (i
.tm
.mnem_off
== MN_xor
4297 || i
.tm
.mnem_off
== MN_sub
))
4298 || i
.tm
.mnem_off
== MN_clr
))))
4301 andq $imm31, %r64 -> andl $imm31, %r32
4302 andq $imm7, %r64 -> andl $imm7, %r32
4303 testq $imm31, %r64 -> testl $imm31, %r32
4304 xorq %r64, %r64 -> xorl %r32, %r32
4305 subq %r64, %r64 -> subl %r32, %r32
4306 movq $imm31, %r64 -> movl $imm31, %r32
4307 movq $imm32, %r64 -> movl $imm32, %r32
4309 i
.tm
.opcode_modifier
.size
= SIZE32
;
4312 i
.types
[0].bitfield
.imm32
= 1;
4313 i
.types
[0].bitfield
.imm32s
= 0;
4314 i
.types
[0].bitfield
.imm64
= 0;
4318 i
.types
[0].bitfield
.dword
= 1;
4319 i
.types
[0].bitfield
.qword
= 0;
4321 i
.types
[1].bitfield
.dword
= 1;
4322 i
.types
[1].bitfield
.qword
= 0;
4323 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4326 movq $imm31, %r64 -> movl $imm31, %r32
4327 movq $imm32, %r64 -> movl $imm32, %r32
4329 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4330 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4331 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4332 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4335 movq $imm31, %r64 -> movl $imm31, %r32
4337 i
.tm
.base_opcode
= 0xb8;
4338 i
.tm
.extension_opcode
= None
;
4339 i
.tm
.opcode_modifier
.w
= 0;
4340 i
.tm
.opcode_modifier
.modrm
= 0;
4344 else if (optimize
> 1
4345 && !optimize_for_space
4346 && i
.reg_operands
== 2
4347 && i
.op
[0].regs
== i
.op
[1].regs
4348 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4349 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4352 andb %rN, %rN -> testb %rN, %rN
4353 andw %rN, %rN -> testw %rN, %rN
4354 andq %rN, %rN -> testq %rN, %rN
4355 orb %rN, %rN -> testb %rN, %rN
4356 orw %rN, %rN -> testw %rN, %rN
4357 orq %rN, %rN -> testq %rN, %rN
4359 and outside of 64-bit mode
4361 andl %rN, %rN -> testl %rN, %rN
4362 orl %rN, %rN -> testl %rN, %rN
4364 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4366 else if (i
.reg_operands
== 3
4367 && i
.op
[0].regs
== i
.op
[1].regs
4368 && !i
.types
[2].bitfield
.xmmword
4369 && (i
.tm
.opcode_modifier
.vex
4370 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4371 && is_evex_encoding (&i
.tm
)
4372 && (i
.vec_encoding
!= vex_encoding_evex
4373 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4374 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4375 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4376 && i
.types
[2].bitfield
.ymmword
))))
4377 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4378 && ((i
.tm
.base_opcode
| 2) == 0x57
4379 || i
.tm
.base_opcode
== 0xdf
4380 || i
.tm
.base_opcode
== 0xef
4381 || (i
.tm
.base_opcode
| 3) == 0xfb
4382 || i
.tm
.base_opcode
== 0x42
4383 || i
.tm
.base_opcode
== 0x47))
4386 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4388 EVEX VOP %zmmM, %zmmM, %zmmN
4389 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4390 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4391 EVEX VOP %ymmM, %ymmM, %ymmN
4392 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4393 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4394 VEX VOP %ymmM, %ymmM, %ymmN
4395 -> VEX VOP %xmmM, %xmmM, %xmmN
4396 VOP, one of vpandn and vpxor:
4397 VEX VOP %ymmM, %ymmM, %ymmN
4398 -> VEX VOP %xmmM, %xmmM, %xmmN
4399 VOP, one of vpandnd and vpandnq:
4400 EVEX VOP %zmmM, %zmmM, %zmmN
4401 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4402 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4403 EVEX VOP %ymmM, %ymmM, %ymmN
4404 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4405 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4406 VOP, one of vpxord and vpxorq:
4407 EVEX VOP %zmmM, %zmmM, %zmmN
4408 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4409 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4410 EVEX VOP %ymmM, %ymmM, %ymmN
4411 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4412 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4413 VOP, one of kxord and kxorq:
4414 VEX VOP %kM, %kM, %kN
4415 -> VEX kxorw %kM, %kM, %kN
4416 VOP, one of kandnd and kandnq:
4417 VEX VOP %kM, %kM, %kN
4418 -> VEX kandnw %kM, %kM, %kN
4420 if (is_evex_encoding (&i
.tm
))
4422 if (i
.vec_encoding
!= vex_encoding_evex
)
4424 i
.tm
.opcode_modifier
.vex
= VEX128
;
4425 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4426 i
.tm
.opcode_modifier
.evex
= 0;
4428 else if (optimize
> 1)
4429 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4433 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4435 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4436 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4439 i
.tm
.opcode_modifier
.vex
= VEX128
;
4441 if (i
.tm
.opcode_modifier
.vex
)
4442 for (j
= 0; j
< 3; j
++)
4444 i
.types
[j
].bitfield
.xmmword
= 1;
4445 i
.types
[j
].bitfield
.ymmword
= 0;
4448 else if (i
.vec_encoding
!= vex_encoding_evex
4449 && !i
.types
[0].bitfield
.zmmword
4450 && !i
.types
[1].bitfield
.zmmword
4452 && !i
.broadcast
.bytes
4453 && is_evex_encoding (&i
.tm
)
4454 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4455 || (i
.tm
.base_opcode
& ~4) == 0xdb
4456 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4457 && i
.tm
.extension_opcode
== None
)
4460 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4461 vmovdqu32 and vmovdqu64:
4462 EVEX VOP %xmmM, %xmmN
4463 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4464 EVEX VOP %ymmM, %ymmN
4465 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4467 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4469 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4471 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4473 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4474 VOP, one of vpand, vpandn, vpor, vpxor:
4475 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4476 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4477 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4478 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4479 EVEX VOP{d,q} mem, %xmmM, %xmmN
4480 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4481 EVEX VOP{d,q} mem, %ymmM, %ymmN
4482 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4484 for (j
= 0; j
< i
.operands
; j
++)
4485 if (operand_type_check (i
.types
[j
], disp
)
4486 && i
.op
[j
].disps
->X_op
== O_constant
)
4488 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4489 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4490 bytes, we choose EVEX Disp8 over VEX Disp32. */
4491 int evex_disp8
, vex_disp8
;
4492 unsigned int memshift
= i
.memshift
;
4493 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4495 evex_disp8
= fits_in_disp8 (n
);
4497 vex_disp8
= fits_in_disp8 (n
);
4498 if (evex_disp8
!= vex_disp8
)
4500 i
.memshift
= memshift
;
4504 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4507 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4508 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4509 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4510 i
.tm
.opcode_modifier
.vex
4511 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4512 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4513 /* VPAND, VPOR, and VPXOR are commutative. */
4514 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4515 i
.tm
.opcode_modifier
.commutative
= 1;
4516 i
.tm
.opcode_modifier
.evex
= 0;
4517 i
.tm
.opcode_modifier
.masking
= 0;
4518 i
.tm
.opcode_modifier
.broadcast
= 0;
4519 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4522 i
.types
[j
].bitfield
.disp8
4523 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4527 /* Return non-zero for load instruction. */
4533 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4534 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4538 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4539 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4540 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4544 if (i
.tm
.mnem_off
== MN_pop
)
4548 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4551 if (i
.tm
.base_opcode
== 0x9d
4552 || i
.tm
.base_opcode
== 0x61)
4555 /* movs, cmps, lods, scas. */
4556 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4560 if (base_opcode
== 0x6f
4561 || i
.tm
.base_opcode
== 0xd7)
4563 /* NB: For AMD-specific insns with implicit memory operands,
4564 they're intentionally not covered. */
4567 /* No memory operand. */
4568 if (!i
.mem_operands
)
4573 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4576 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4578 /* test, not, neg, mul, imul, div, idiv. */
4579 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4583 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4586 /* add, or, adc, sbb, and, sub, xor, cmp. */
4587 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4590 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4591 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4592 && i
.tm
.extension_opcode
!= 6)
4595 /* Check for x87 instructions. */
4596 if ((base_opcode
| 6) == 0xdf)
4598 /* Skip fst, fstp, fstenv, fstcw. */
4599 if (i
.tm
.base_opcode
== 0xd9
4600 && (i
.tm
.extension_opcode
== 2
4601 || i
.tm
.extension_opcode
== 3
4602 || i
.tm
.extension_opcode
== 6
4603 || i
.tm
.extension_opcode
== 7))
4606 /* Skip fisttp, fist, fistp, fstp. */
4607 if (i
.tm
.base_opcode
== 0xdb
4608 && (i
.tm
.extension_opcode
== 1
4609 || i
.tm
.extension_opcode
== 2
4610 || i
.tm
.extension_opcode
== 3
4611 || i
.tm
.extension_opcode
== 7))
4614 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4615 if (i
.tm
.base_opcode
== 0xdd
4616 && (i
.tm
.extension_opcode
== 1
4617 || i
.tm
.extension_opcode
== 2
4618 || i
.tm
.extension_opcode
== 3
4619 || i
.tm
.extension_opcode
== 6
4620 || i
.tm
.extension_opcode
== 7))
4623 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4624 if (i
.tm
.base_opcode
== 0xdf
4625 && (i
.tm
.extension_opcode
== 1
4626 || i
.tm
.extension_opcode
== 2
4627 || i
.tm
.extension_opcode
== 3
4628 || i
.tm
.extension_opcode
== 6
4629 || i
.tm
.extension_opcode
== 7))
4635 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4637 /* bt, bts, btr, btc. */
4638 if (i
.tm
.base_opcode
== 0xba
4639 && (i
.tm
.extension_opcode
| 3) == 7)
4642 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4643 if (i
.tm
.base_opcode
== 0xc7
4644 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4645 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4646 || i
.tm
.extension_opcode
== 6))
4649 /* fxrstor, ldmxcsr, xrstor. */
4650 if (i
.tm
.base_opcode
== 0xae
4651 && (i
.tm
.extension_opcode
== 1
4652 || i
.tm
.extension_opcode
== 2
4653 || i
.tm
.extension_opcode
== 5))
4656 /* lgdt, lidt, lmsw. */
4657 if (i
.tm
.base_opcode
== 0x01
4658 && (i
.tm
.extension_opcode
== 2
4659 || i
.tm
.extension_opcode
== 3
4660 || i
.tm
.extension_opcode
== 6))
4664 dest
= i
.operands
- 1;
4666 /* Check fake imm8 operand and 3 source operands. */
4667 if ((i
.tm
.opcode_modifier
.immext
4668 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4669 && i
.types
[dest
].bitfield
.imm8
)
4672 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4673 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4674 && ((base_opcode
| 0x38) == 0x39
4675 || (base_opcode
| 2) == 0x87))
4678 if (i
.tm
.mnem_off
== MN_xadd
)
4681 /* Check for load instruction. */
4682 return (i
.types
[dest
].bitfield
.class != ClassNone
4683 || i
.types
[dest
].bitfield
.instance
== Accum
);
4686 /* Output lfence, 0xfaee8, after instruction. */
4689 insert_lfence_after (void)
4691 if (lfence_after_load
&& load_insn_p ())
4693 /* There are also two REP string instructions that require
4694 special treatment. Specifically, the compare string (CMPS)
4695 and scan string (SCAS) instructions set EFLAGS in a manner
4696 that depends on the data being compared/scanned. When used
4697 with a REP prefix, the number of iterations may therefore
4698 vary depending on this data. If the data is a program secret
4699 chosen by the adversary using an LVI method,
4700 then this data-dependent behavior may leak some aspect
4702 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4703 && i
.prefix
[REP_PREFIX
])
4705 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4708 char *p
= frag_more (3);
4715 /* Output lfence, 0xfaee8, before instruction. */
4718 insert_lfence_before (void)
4722 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4725 if (i
.tm
.base_opcode
== 0xff
4726 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4728 /* Insert lfence before indirect branch if needed. */
4730 if (lfence_before_indirect_branch
== lfence_branch_none
)
4733 if (i
.operands
!= 1)
4736 if (i
.reg_operands
== 1)
4738 /* Indirect branch via register. Don't insert lfence with
4739 -mlfence-after-load=yes. */
4740 if (lfence_after_load
4741 || lfence_before_indirect_branch
== lfence_branch_memory
)
4744 else if (i
.mem_operands
== 1
4745 && lfence_before_indirect_branch
!= lfence_branch_register
)
4747 as_warn (_("indirect `%s` with memory operand should be avoided"),
4754 if (last_insn
.kind
!= last_insn_other
4755 && last_insn
.seg
== now_seg
)
4757 as_warn_where (last_insn
.file
, last_insn
.line
,
4758 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4759 last_insn
.name
, insn_name (&i
.tm
));
4770 /* Output or/not/shl and lfence before near ret. */
4771 if (lfence_before_ret
!= lfence_before_ret_none
4772 && (i
.tm
.base_opcode
| 1) == 0xc3)
4774 if (last_insn
.kind
!= last_insn_other
4775 && last_insn
.seg
== now_seg
)
4777 as_warn_where (last_insn
.file
, last_insn
.line
,
4778 _("`%s` skips -mlfence-before-ret on `%s`"),
4779 last_insn
.name
, insn_name (&i
.tm
));
4783 /* Near ret ingore operand size override under CPU64. */
4784 char prefix
= flag_code
== CODE_64BIT
4786 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4788 if (lfence_before_ret
== lfence_before_ret_not
)
4790 /* not: 0xf71424, may add prefix
4791 for operand size override or 64-bit code. */
4792 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4806 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4809 if (lfence_before_ret
== lfence_before_ret_or
)
4811 /* or: 0x830c2400, may add prefix
4812 for operand size override or 64-bit code. */
4818 /* shl: 0xc1242400, may add prefix
4819 for operand size override or 64-bit code. */
4834 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
4835 parsing pass. Instead of introducing a rarely use new insn attribute this
4836 utilizes a common pattern between affected templates. It is deemed
4837 acceptable that this will lead to unnecessary pass 2 preparations in a
4838 limited set of cases. */
4839 static INLINE
bool may_need_pass2 (const insn_template
*t
)
4841 return t
->opcode_modifier
.sse2avx
4842 /* Note that all SSE2AVX templates have at least one operand. */
4843 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
4844 : (t
->opcode_modifier
.opcodespace
== SPACE_0F
4845 && (t
->base_opcode
| 1) == 0xbf)
4846 || (t
->opcode_modifier
.opcodespace
== SPACE_BASE
4847 && t
->base_opcode
== 0x63);
4850 /* This is the guts of the machine-dependent assembler. LINE points to a
4851 machine dependent instruction. This function is supposed to emit
4852 the frags/bytes it assembles to. */
4855 md_assemble (char *line
)
4858 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
4859 const char *end
, *pass1_mnem
= NULL
;
4860 enum i386_error pass1_err
= 0;
4861 const insn_template
*t
;
4863 /* Initialize globals. */
4864 current_templates
= NULL
;
4866 memset (&i
, '\0', sizeof (i
));
4867 i
.rounding
.type
= rc_none
;
4868 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4869 i
.reloc
[j
] = NO_RELOC
;
4870 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4871 memset (im_expressions
, '\0', sizeof (im_expressions
));
4872 save_stack_p
= save_stack
;
4874 /* First parse an instruction mnemonic & call i386_operand for the operands.
4875 We assume that the scrubber has arranged it so that line[0] is the valid
4876 start of a (possibly prefixed) mnemonic. */
4878 end
= parse_insn (line
, mnemonic
);
4881 if (pass1_mnem
!= NULL
)
4883 if (i
.error
!= no_error
)
4885 gas_assert (current_templates
!= NULL
);
4886 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
4888 /* No point in trying a 2nd pass - it'll only find the same suffix
4890 mnem_suffix
= i
.suffix
;
4895 t
= current_templates
->start
;
4896 if (may_need_pass2 (t
))
4898 /* Make a copy of the full line in case we need to retry. */
4899 copy
= xstrdup (line
);
4902 mnem_suffix
= i
.suffix
;
4904 line
= parse_operands (line
, mnemonic
);
4912 /* Now we've parsed the mnemonic into a set of templates, and have the
4913 operands at hand. */
4915 /* All Intel opcodes have reversed operands except for "bound", "enter",
4916 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4917 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
4918 intersegment "jmp" and "call" instructions with 2 immediate operands so
4919 that the immediate segment precedes the offset consistently in Intel and
4923 && (t
->mnem_off
!= MN_bound
)
4924 && !startswith (mnemonic
, "invlpg")
4925 && !startswith (mnemonic
, "monitor")
4926 && !startswith (mnemonic
, "mwait")
4927 && (t
->mnem_off
!= MN_pvalidate
)
4928 && !startswith (mnemonic
, "rmp")
4929 && (t
->mnem_off
!= MN_tpause
)
4930 && (t
->mnem_off
!= MN_umwait
)
4931 && !(i
.operands
== 2
4932 && operand_type_check (i
.types
[0], imm
)
4933 && operand_type_check (i
.types
[1], imm
)))
4936 /* The order of the immediates should be reversed
4937 for 2 immediates extrq and insertq instructions */
4938 if (i
.imm_operands
== 2
4939 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
4940 swap_2_operands (0, 1);
4945 if (i
.disp_operands
&& !want_disp32 (t
)
4946 && (!t
->opcode_modifier
.jump
4947 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
4949 for (j
= 0; j
< i
.operands
; ++j
)
4951 const expressionS
*exp
= i
.op
[j
].disps
;
4953 if (!operand_type_check (i
.types
[j
], disp
))
4956 if (exp
->X_op
!= O_constant
)
4959 /* Since displacement is signed extended to 64bit, don't allow
4960 disp32 if it is out of range. */
4961 if (fits_in_signed_long (exp
->X_add_number
))
4964 i
.types
[j
].bitfield
.disp32
= 0;
4965 if (i
.types
[j
].bitfield
.baseindex
)
4967 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
4968 (uint64_t) exp
->X_add_number
);
4974 /* Don't optimize displacement for movabs since it only takes 64bit
4977 && i
.disp_encoding
<= disp_encoding_8bit
4978 && (flag_code
!= CODE_64BIT
4979 || strcmp (mnemonic
, "movabs") != 0))
4982 /* Next, we find a template that matches the given insn,
4983 making sure the overlap of the given operands types is consistent
4984 with the template operand types. */
4986 if (!(t
= match_template (mnem_suffix
)))
4988 const char *err_msg
;
4990 if (copy
&& !mnem_suffix
)
4995 pass1_err
= i
.error
;
4996 pass1_mnem
= insn_name (current_templates
->start
);
5000 /* If a non-/only-64bit template (group) was found in pass 1, and if
5001 _some_ template (group) was found in pass 2, squash pass 1's
5003 if (pass1_err
== unsupported_64bit
)
5009 switch (pass1_mnem
? pass1_err
: i
.error
)
5013 case operand_size_mismatch
:
5014 err_msg
= _("operand size mismatch");
5016 case operand_type_mismatch
:
5017 err_msg
= _("operand type mismatch");
5019 case register_type_mismatch
:
5020 err_msg
= _("register type mismatch");
5022 case number_of_operands_mismatch
:
5023 err_msg
= _("number of operands mismatch");
5025 case invalid_instruction_suffix
:
5026 err_msg
= _("invalid instruction suffix");
5029 err_msg
= _("constant doesn't fit in 4 bits");
5031 case unsupported_with_intel_mnemonic
:
5032 err_msg
= _("unsupported with Intel mnemonic");
5034 case unsupported_syntax
:
5035 err_msg
= _("unsupported syntax");
5038 as_bad (_("unsupported instruction `%s'"),
5039 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5041 case unsupported_on_arch
:
5042 as_bad (_("`%s' is not supported on `%s%s'"),
5043 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5044 cpu_arch_name
? cpu_arch_name
: default_arch
,
5045 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5047 case unsupported_64bit
:
5048 if (ISLOWER (mnem_suffix
))
5050 if (flag_code
== CODE_64BIT
)
5051 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5052 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5055 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5056 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5061 if (flag_code
== CODE_64BIT
)
5062 as_bad (_("`%s' is not supported in 64-bit mode"),
5063 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5065 as_bad (_("`%s' is only supported in 64-bit mode"),
5066 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5069 case invalid_sib_address
:
5070 err_msg
= _("invalid SIB address");
5072 case invalid_vsib_address
:
5073 err_msg
= _("invalid VSIB address");
5075 case invalid_vector_register_set
:
5076 err_msg
= _("mask, index, and destination registers must be distinct");
5078 case invalid_tmm_register_set
:
5079 err_msg
= _("all tmm registers must be distinct");
5081 case invalid_dest_and_src_register_set
:
5082 err_msg
= _("destination and source registers must be distinct");
5084 case unsupported_vector_index_register
:
5085 err_msg
= _("unsupported vector index register");
5087 case unsupported_broadcast
:
5088 err_msg
= _("unsupported broadcast");
5090 case broadcast_needed
:
5091 err_msg
= _("broadcast is needed for operand of such type");
5093 case unsupported_masking
:
5094 err_msg
= _("unsupported masking");
5096 case mask_not_on_destination
:
5097 err_msg
= _("mask not on destination operand");
5099 case no_default_mask
:
5100 err_msg
= _("default mask isn't allowed");
5102 case unsupported_rc_sae
:
5103 err_msg
= _("unsupported static rounding/sae");
5105 case invalid_register_operand
:
5106 err_msg
= _("invalid register operand");
5109 as_bad (_("%s for `%s'"), err_msg
,
5110 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5116 if (sse_check
!= check_none
5117 /* The opcode space check isn't strictly needed; it's there only to
5118 bypass the logic below when easily possible. */
5119 && t
->opcode_modifier
.opcodespace
>= SPACE_0F
5120 && t
->opcode_modifier
.opcodespace
<= SPACE_0F3A
5121 && !i
.tm
.cpu_flags
.bitfield
.cpusse4a
5122 && !is_any_vex_encoding (t
))
5126 for (j
= 0; j
< t
->operands
; ++j
)
5128 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5130 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5134 if (j
>= t
->operands
&& simd
)
5135 (sse_check
== check_warning
5137 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5140 if (i
.tm
.opcode_modifier
.fwait
)
5141 if (!add_prefix (FWAIT_OPCODE
))
5144 /* Check if REP prefix is OK. */
5145 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5147 as_bad (_("invalid instruction `%s' after `%s'"),
5148 insn_name (&i
.tm
), i
.rep_prefix
);
5152 /* Check for lock without a lockable instruction. Destination operand
5153 must be memory unless it is xchg (0x86). */
5154 if (i
.prefix
[LOCK_PREFIX
])
5156 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5157 || i
.mem_operands
== 0
5158 || (i
.tm
.base_opcode
!= 0x86
5159 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5161 as_bad (_("expecting lockable instruction after `lock'"));
5165 /* Zap the redundant prefix from XCHG when optimizing. */
5166 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5167 i
.prefix
[LOCK_PREFIX
] = 0;
5170 if (is_any_vex_encoding (&i
.tm
)
5171 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5172 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5174 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5175 if (i
.prefix
[DATA_PREFIX
])
5177 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5181 /* Don't allow e.g. KMOV in TLS code sequences. */
5182 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5185 case BFD_RELOC_386_TLS_GOTIE
:
5186 case BFD_RELOC_386_TLS_LE_32
:
5187 case BFD_RELOC_X86_64_GOTTPOFF
:
5188 case BFD_RELOC_X86_64_TLSLD
:
5189 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5196 /* Check if HLE prefix is OK. */
5197 if (i
.hle_prefix
&& !check_hle ())
5200 /* Check BND prefix. */
5201 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5202 as_bad (_("expecting valid branch instruction after `bnd'"));
5204 /* Check NOTRACK prefix. */
5205 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5206 as_bad (_("expecting indirect branch instruction after `notrack'"));
5208 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5210 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5211 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5212 else if (flag_code
!= CODE_16BIT
5213 ? i
.prefix
[ADDR_PREFIX
]
5214 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5215 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5218 /* Insert BND prefix. */
5219 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5221 if (!i
.prefix
[BND_PREFIX
])
5222 add_prefix (BND_PREFIX_OPCODE
);
5223 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5225 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5226 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5230 /* Check string instruction segment overrides. */
5231 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5233 gas_assert (i
.mem_operands
);
5234 if (!check_string ())
5236 i
.disp_operands
= 0;
5239 /* The memory operand of (%dx) should be only used with input/output
5240 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5241 if (i
.input_output_operand
5242 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5243 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
))
5245 as_bad (_("input/output port address isn't allowed with `%s'"),
5250 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5251 optimize_encoding ();
5253 if (use_unaligned_vector_move
)
5254 encode_with_unaligned_vector_move ();
5256 if (!process_suffix ())
5259 /* Check if IP-relative addressing requirements can be satisfied. */
5260 if (i
.tm
.cpu_flags
.bitfield
.cpuprefetchi
5261 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5262 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5264 /* Update operand types and check extended states. */
5265 for (j
= 0; j
< i
.operands
; j
++)
5267 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5268 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5273 i
.xstate
|= xstate_mmx
;
5276 i
.xstate
|= xstate_mask
;
5279 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5280 i
.xstate
|= xstate_tmm
;
5281 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5282 i
.xstate
|= xstate_zmm
;
5283 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5284 i
.xstate
|= xstate_ymm
;
5285 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5286 i
.xstate
|= xstate_xmm
;
5291 /* Make still unresolved immediate matches conform to size of immediate
5292 given in i.suffix. */
5293 if (!finalize_imm ())
5296 if (i
.types
[0].bitfield
.imm1
)
5297 i
.imm_operands
= 0; /* kludge for shift insns. */
5299 /* For insns with operands there are more diddles to do to the opcode. */
5302 if (!process_operands ())
5305 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5307 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5308 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5311 if (is_any_vex_encoding (&i
.tm
))
5313 if (!cpu_arch_flags
.bitfield
.cpui286
)
5315 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5320 /* Check for explicit REX prefix. */
5321 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5323 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5327 if (i
.tm
.opcode_modifier
.vex
)
5328 build_vex_prefix (t
);
5330 build_evex_prefix ();
5332 /* The individual REX.RXBW bits got consumed. */
5333 i
.rex
&= REX_OPCODE
;
5336 /* Handle conversion of 'int $3' --> special int3 insn. */
5337 if (i
.tm
.mnem_off
== MN_int
5338 && i
.op
[0].imms
->X_add_number
== 3)
5340 i
.tm
.base_opcode
= INT3_OPCODE
;
5344 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5345 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5346 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5347 && i
.op
[0].disps
->X_op
== O_constant
)
5349 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5350 the absolute address given by the constant. Since ix86 jumps and
5351 calls are pc relative, we need to generate a reloc. */
5352 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5353 i
.op
[0].disps
->X_op
= O_symbol
;
5356 /* For 8 bit registers we need an empty rex prefix. Also if the
5357 instruction already has a prefix, we need to convert old
5358 registers to new ones. */
5360 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5361 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5362 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5363 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5364 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5365 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5370 i
.rex
|= REX_OPCODE
;
5371 for (x
= 0; x
< 2; x
++)
5373 /* Look for 8 bit operand that uses old registers. */
5374 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5375 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5377 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5378 /* In case it is "hi" register, give up. */
5379 if (i
.op
[x
].regs
->reg_num
> 3)
5380 as_bad (_("can't encode register '%s%s' in an "
5381 "instruction requiring REX prefix."),
5382 register_prefix
, i
.op
[x
].regs
->reg_name
);
5384 /* Otherwise it is equivalent to the extended register.
5385 Since the encoding doesn't change this is merely
5386 cosmetic cleanup for debug output. */
5388 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5393 if (i
.rex
== 0 && i
.rex_encoding
)
5395 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5396 that uses legacy register. If it is "hi" register, don't add
5397 the REX_OPCODE byte. */
5399 for (x
= 0; x
< 2; x
++)
5400 if (i
.types
[x
].bitfield
.class == Reg
5401 && i
.types
[x
].bitfield
.byte
5402 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5403 && i
.op
[x
].regs
->reg_num
> 3)
5405 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5406 i
.rex_encoding
= false;
5415 add_prefix (REX_OPCODE
| i
.rex
);
5417 insert_lfence_before ();
5419 /* We are ready to output the insn. */
5422 insert_lfence_after ();
5424 last_insn
.seg
= now_seg
;
5426 if (i
.tm
.opcode_modifier
.isprefix
)
5428 last_insn
.kind
= last_insn_prefix
;
5429 last_insn
.name
= insn_name (&i
.tm
);
5430 last_insn
.file
= as_where (&last_insn
.line
);
5433 last_insn
.kind
= last_insn_other
;
5436 /* The Q suffix is generally valid only in 64-bit mode, with very few
5437 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5438 and fisttp only one of their two templates is matched below: That's
5439 sufficient since other relevant attributes are the same between both
5440 respective templates. */
5441 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5443 return flag_code
== CODE_64BIT
5444 || (t
->opcode_modifier
.opcodespace
== SPACE_BASE
5445 && t
->base_opcode
== 0xdf
5446 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5447 || t
->mnem_off
== MN_cmpxchg8b
;
5451 parse_insn (const char *line
, char *mnemonic
)
5453 const char *l
= line
, *token_start
= l
;
5455 bool pass1
= !current_templates
;
5457 const insn_template
*t
;
5463 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5468 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5470 as_bad (_("no such instruction: `%s'"), token_start
);
5475 if (!is_space_char (*l
)
5476 && *l
!= END_OF_INSN
5478 || (*l
!= PREFIX_SEPARATOR
5481 as_bad (_("invalid character %s in mnemonic"),
5482 output_invalid (*l
));
5485 if (token_start
== l
)
5487 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5488 as_bad (_("expecting prefix; got nothing"));
5490 as_bad (_("expecting mnemonic; got nothing"));
5494 /* Look up instruction (or prefix) via hash table. */
5495 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5497 if (*l
!= END_OF_INSN
5498 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5499 && current_templates
5500 && current_templates
->start
->opcode_modifier
.isprefix
)
5502 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5504 as_bad ((flag_code
!= CODE_64BIT
5505 ? _("`%s' is only supported in 64-bit mode")
5506 : _("`%s' is not supported in 64-bit mode")),
5507 insn_name (current_templates
->start
));
5510 /* If we are in 16-bit mode, do not allow addr16 or data16.
5511 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5512 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5513 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5514 && flag_code
!= CODE_64BIT
5515 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5516 ^ (flag_code
== CODE_16BIT
)))
5518 as_bad (_("redundant %s prefix"),
5519 insn_name (current_templates
->start
));
5523 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5525 /* Handle pseudo prefixes. */
5526 switch (current_templates
->start
->extension_opcode
)
5530 i
.disp_encoding
= disp_encoding_8bit
;
5534 i
.disp_encoding
= disp_encoding_16bit
;
5538 i
.disp_encoding
= disp_encoding_32bit
;
5542 i
.dir_encoding
= dir_encoding_load
;
5546 i
.dir_encoding
= dir_encoding_store
;
5550 i
.vec_encoding
= vex_encoding_vex
;
5554 i
.vec_encoding
= vex_encoding_vex3
;
5558 i
.vec_encoding
= vex_encoding_evex
;
5562 i
.rex_encoding
= true;
5564 case Prefix_NoOptimize
:
5566 i
.no_optimize
= true;
5574 /* Add prefix, checking for repeated prefixes. */
5575 switch (add_prefix (current_templates
->start
->base_opcode
))
5580 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5581 i
.notrack_prefix
= insn_name (current_templates
->start
);
5584 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5585 i
.hle_prefix
= insn_name (current_templates
->start
);
5586 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5587 i
.bnd_prefix
= insn_name (current_templates
->start
);
5589 i
.rep_prefix
= insn_name (current_templates
->start
);
5595 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5602 if (!current_templates
)
5604 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5605 Check if we should swap operand or force 32bit displacement in
5607 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5608 i
.dir_encoding
= dir_encoding_swap
;
5609 else if (mnem_p
- 3 == dot_p
5612 i
.disp_encoding
= disp_encoding_8bit
;
5613 else if (mnem_p
- 4 == dot_p
5617 i
.disp_encoding
= disp_encoding_32bit
;
5622 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5625 if (!current_templates
|| !pass1
)
5627 current_templates
= NULL
;
5630 if (mnem_p
> mnemonic
)
5632 /* See if we can get a match by trimming off a suffix. */
5635 case WORD_MNEM_SUFFIX
:
5636 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5637 i
.suffix
= SHORT_MNEM_SUFFIX
;
5640 case BYTE_MNEM_SUFFIX
:
5641 case QWORD_MNEM_SUFFIX
:
5642 i
.suffix
= mnem_p
[-1];
5645 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5647 case SHORT_MNEM_SUFFIX
:
5648 case LONG_MNEM_SUFFIX
:
5651 i
.suffix
= mnem_p
[-1];
5654 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5662 if (intel_float_operand (mnemonic
) == 1)
5663 i
.suffix
= SHORT_MNEM_SUFFIX
;
5665 i
.suffix
= LONG_MNEM_SUFFIX
;
5668 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5670 /* For compatibility reasons accept MOVSD and CMPSD without
5671 operands even in AT&T mode. */
5672 else if (*l
== END_OF_INSN
5673 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5677 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5678 if (current_templates
!= NULL
5680 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5681 && current_templates
->start
->opcode_modifier
.opcodespace
5683 && mnem_p
[-2] == 's')
5685 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5686 mnemonic
, mnemonic
);
5687 i
.suffix
= LONG_MNEM_SUFFIX
;
5691 current_templates
= NULL
;
5699 if (!current_templates
)
5702 as_bad (_("no such instruction: `%s'"), token_start
);
5707 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5708 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5710 /* Check for a branch hint. We allow ",pt" and ",pn" for
5711 predict taken and predict not taken respectively.
5712 I'm not sure that branch hints actually do anything on loop
5713 and jcxz insns (JumpByte) for current Pentium4 chips. They
5714 may work in the future and it doesn't hurt to accept them
5716 if (l
[0] == ',' && l
[1] == 'p')
5720 if (!add_prefix (DS_PREFIX_OPCODE
))
5724 else if (l
[2] == 'n')
5726 if (!add_prefix (CS_PREFIX_OPCODE
))
5732 /* Any other comma loses. */
5735 as_bad (_("invalid character %s in mnemonic"),
5736 output_invalid (*l
));
5740 /* Check if instruction is supported on specified architecture. */
5742 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5744 supported
|= cpu_flags_match (t
);
5746 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5747 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5749 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5755 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5756 i
.error
= unsupported_on_arch
;
5758 i
.error
= unsupported_64bit
;
5765 parse_operands (char *l
, const char *mnemonic
)
5769 /* 1 if operand is pending after ','. */
5770 unsigned int expecting_operand
= 0;
5772 while (*l
!= END_OF_INSN
)
5774 /* Non-zero if operand parens not balanced. */
5775 unsigned int paren_not_balanced
= 0;
5776 /* True if inside double quotes. */
5777 bool in_quotes
= false;
5779 /* Skip optional white space before operand. */
5780 if (is_space_char (*l
))
5782 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5784 as_bad (_("invalid character %s before operand %d"),
5785 output_invalid (*l
),
5789 token_start
= l
; /* After white space. */
5790 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5792 if (*l
== END_OF_INSN
)
5796 as_bad (_("unbalanced double quotes in operand %d."),
5800 if (paren_not_balanced
)
5802 know (!intel_syntax
);
5803 as_bad (_("unbalanced parenthesis in operand %d."),
5808 break; /* we are done */
5810 else if (*l
== '\\' && l
[1] == '"')
5813 in_quotes
= !in_quotes
;
5814 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5816 as_bad (_("invalid character %s in operand %d"),
5817 output_invalid (*l
),
5821 if (!intel_syntax
&& !in_quotes
)
5824 ++paren_not_balanced
;
5826 --paren_not_balanced
;
5830 if (l
!= token_start
)
5831 { /* Yes, we've read in another operand. */
5832 unsigned int operand_ok
;
5833 this_operand
= i
.operands
++;
5834 if (i
.operands
> MAX_OPERANDS
)
5836 as_bad (_("spurious operands; (%d operands/instruction max)"),
5840 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5841 /* Now parse operand adding info to 'i' as we go along. */
5842 END_STRING_AND_SAVE (l
);
5844 if (i
.mem_operands
> 1)
5846 as_bad (_("too many memory references for `%s'"),
5853 i386_intel_operand (token_start
,
5854 intel_float_operand (mnemonic
));
5856 operand_ok
= i386_att_operand (token_start
);
5858 RESTORE_END_STRING (l
);
5864 if (expecting_operand
)
5866 expecting_operand_after_comma
:
5867 as_bad (_("expecting operand after ','; got nothing"));
5872 as_bad (_("expecting operand before ','; got nothing"));
5877 /* Now *l must be either ',' or END_OF_INSN. */
5880 if (*++l
== END_OF_INSN
)
5882 /* Just skip it, if it's \n complain. */
5883 goto expecting_operand_after_comma
;
5885 expecting_operand
= 1;
5892 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5894 union i386_op temp_op
;
5895 i386_operand_type temp_type
;
5896 unsigned int temp_flags
;
5897 enum bfd_reloc_code_real temp_reloc
;
5899 temp_type
= i
.types
[xchg2
];
5900 i
.types
[xchg2
] = i
.types
[xchg1
];
5901 i
.types
[xchg1
] = temp_type
;
5903 temp_flags
= i
.flags
[xchg2
];
5904 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5905 i
.flags
[xchg1
] = temp_flags
;
5907 temp_op
= i
.op
[xchg2
];
5908 i
.op
[xchg2
] = i
.op
[xchg1
];
5909 i
.op
[xchg1
] = temp_op
;
5911 temp_reloc
= i
.reloc
[xchg2
];
5912 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5913 i
.reloc
[xchg1
] = temp_reloc
;
5917 if (i
.mask
.operand
== xchg1
)
5918 i
.mask
.operand
= xchg2
;
5919 else if (i
.mask
.operand
== xchg2
)
5920 i
.mask
.operand
= xchg1
;
5922 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
5924 if (i
.broadcast
.operand
== xchg1
)
5925 i
.broadcast
.operand
= xchg2
;
5926 else if (i
.broadcast
.operand
== xchg2
)
5927 i
.broadcast
.operand
= xchg1
;
5932 swap_operands (void)
5938 swap_2_operands (1, i
.operands
- 2);
5942 swap_2_operands (0, i
.operands
- 1);
5948 if (i
.mem_operands
== 2)
5950 const reg_entry
*temp_seg
;
5951 temp_seg
= i
.seg
[0];
5952 i
.seg
[0] = i
.seg
[1];
5953 i
.seg
[1] = temp_seg
;
5957 /* Try to ensure constant immediates are represented in the smallest
5962 char guess_suffix
= 0;
5966 guess_suffix
= i
.suffix
;
5967 else if (i
.reg_operands
)
5969 /* Figure out a suffix from the last register operand specified.
5970 We can't do this properly yet, i.e. excluding special register
5971 instances, but the following works for instructions with
5972 immediates. In any case, we can't set i.suffix yet. */
5973 for (op
= i
.operands
; --op
>= 0;)
5974 if (i
.types
[op
].bitfield
.class != Reg
)
5976 else if (i
.types
[op
].bitfield
.byte
)
5978 guess_suffix
= BYTE_MNEM_SUFFIX
;
5981 else if (i
.types
[op
].bitfield
.word
)
5983 guess_suffix
= WORD_MNEM_SUFFIX
;
5986 else if (i
.types
[op
].bitfield
.dword
)
5988 guess_suffix
= LONG_MNEM_SUFFIX
;
5991 else if (i
.types
[op
].bitfield
.qword
)
5993 guess_suffix
= QWORD_MNEM_SUFFIX
;
5997 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5998 guess_suffix
= WORD_MNEM_SUFFIX
;
6000 for (op
= i
.operands
; --op
>= 0;)
6001 if (operand_type_check (i
.types
[op
], imm
))
6003 switch (i
.op
[op
].imms
->X_op
)
6006 /* If a suffix is given, this operand may be shortened. */
6007 switch (guess_suffix
)
6009 case LONG_MNEM_SUFFIX
:
6010 i
.types
[op
].bitfield
.imm32
= 1;
6011 i
.types
[op
].bitfield
.imm64
= 1;
6013 case WORD_MNEM_SUFFIX
:
6014 i
.types
[op
].bitfield
.imm16
= 1;
6015 i
.types
[op
].bitfield
.imm32
= 1;
6016 i
.types
[op
].bitfield
.imm32s
= 1;
6017 i
.types
[op
].bitfield
.imm64
= 1;
6019 case BYTE_MNEM_SUFFIX
:
6020 i
.types
[op
].bitfield
.imm8
= 1;
6021 i
.types
[op
].bitfield
.imm8s
= 1;
6022 i
.types
[op
].bitfield
.imm16
= 1;
6023 i
.types
[op
].bitfield
.imm32
= 1;
6024 i
.types
[op
].bitfield
.imm32s
= 1;
6025 i
.types
[op
].bitfield
.imm64
= 1;
6029 /* If this operand is at most 16 bits, convert it
6030 to a signed 16 bit number before trying to see
6031 whether it will fit in an even smaller size.
6032 This allows a 16-bit operand such as $0xffe0 to
6033 be recognised as within Imm8S range. */
6034 if ((i
.types
[op
].bitfield
.imm16
)
6035 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6037 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6038 ^ 0x8000) - 0x8000);
6041 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6042 if ((i
.types
[op
].bitfield
.imm32
)
6043 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6045 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6046 ^ ((offsetT
) 1 << 31))
6047 - ((offsetT
) 1 << 31));
6051 = operand_type_or (i
.types
[op
],
6052 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6054 /* We must avoid matching of Imm32 templates when 64bit
6055 only immediate is available. */
6056 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6057 i
.types
[op
].bitfield
.imm32
= 0;
6064 /* Symbols and expressions. */
6066 /* Convert symbolic operand to proper sizes for matching, but don't
6067 prevent matching a set of insns that only supports sizes other
6068 than those matching the insn suffix. */
6070 i386_operand_type mask
, allowed
;
6071 const insn_template
*t
= current_templates
->start
;
6073 operand_type_set (&mask
, 0);
6074 switch (guess_suffix
)
6076 case QWORD_MNEM_SUFFIX
:
6077 mask
.bitfield
.imm64
= 1;
6078 mask
.bitfield
.imm32s
= 1;
6080 case LONG_MNEM_SUFFIX
:
6081 mask
.bitfield
.imm32
= 1;
6083 case WORD_MNEM_SUFFIX
:
6084 mask
.bitfield
.imm16
= 1;
6086 case BYTE_MNEM_SUFFIX
:
6087 mask
.bitfield
.imm8
= 1;
6093 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6094 while (++t
< current_templates
->end
)
6096 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6097 allowed
= operand_type_and (allowed
, mask
);
6100 if (!operand_type_all_zero (&allowed
))
6101 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6108 /* Try to use the smallest displacement type too. */
6110 optimize_disp (void)
6114 for (op
= i
.operands
; --op
>= 0;)
6115 if (operand_type_check (i
.types
[op
], disp
))
6117 if (i
.op
[op
].disps
->X_op
== O_constant
)
6119 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6121 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6123 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6124 i
.op
[op
].disps
= NULL
;
6129 if (i
.types
[op
].bitfield
.disp16
6130 && fits_in_unsigned_word (op_disp
))
6132 /* If this operand is at most 16 bits, convert
6133 to a signed 16 bit number and don't use 64bit
6135 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6136 i
.types
[op
].bitfield
.disp64
= 0;
6140 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6141 if ((flag_code
!= CODE_64BIT
6142 ? i
.types
[op
].bitfield
.disp32
6143 : want_disp32 (current_templates
->start
)
6144 && (!current_templates
->start
->opcode_modifier
.jump
6145 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6146 && fits_in_unsigned_long (op_disp
))
6148 /* If this operand is at most 32 bits, convert
6149 to a signed 32 bit number and don't use 64bit
6151 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6152 i
.types
[op
].bitfield
.disp64
= 0;
6153 i
.types
[op
].bitfield
.disp32
= 1;
6156 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6158 i
.types
[op
].bitfield
.disp64
= 0;
6159 i
.types
[op
].bitfield
.disp32
= 1;
6162 if ((i
.types
[op
].bitfield
.disp32
6163 || i
.types
[op
].bitfield
.disp16
)
6164 && fits_in_disp8 (op_disp
))
6165 i
.types
[op
].bitfield
.disp8
= 1;
6167 i
.op
[op
].disps
->X_add_number
= op_disp
;
6169 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6170 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6172 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6173 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6174 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6177 /* We only support 64bit displacement on constants. */
6178 i
.types
[op
].bitfield
.disp64
= 0;
6182 /* Return 1 if there is a match in broadcast bytes between operand
6183 GIVEN and instruction template T. */
6186 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6188 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6189 && i
.types
[given
].bitfield
.byte
)
6190 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6191 && i
.types
[given
].bitfield
.word
)
6192 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6193 && i
.types
[given
].bitfield
.dword
)
6194 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6195 && i
.types
[given
].bitfield
.qword
));
6198 /* Check if operands are valid for the instruction. */
6201 check_VecOperands (const insn_template
*t
)
6206 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6207 any one operand are implicity requiring AVX512VL support if the actual
6208 operand size is YMMword or XMMword. Since this function runs after
6209 template matching, there's no need to check for YMMword/XMMword in
6211 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
6212 if (!cpu_flags_all_zero (&cpu
)
6213 && !t
->cpu_flags
.bitfield
.cpuavx512vl
6214 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6216 for (op
= 0; op
< t
->operands
; ++op
)
6218 if (t
->operand_types
[op
].bitfield
.zmmword
6219 && (i
.types
[op
].bitfield
.ymmword
6220 || i
.types
[op
].bitfield
.xmmword
))
6222 i
.error
= unsupported
;
6228 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6229 requiring AVX2 support if the actual operand size is YMMword. */
6230 if (t
->cpu_flags
.bitfield
.cpuavx
6231 && t
->cpu_flags
.bitfield
.cpuavx2
6232 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6234 for (op
= 0; op
< t
->operands
; ++op
)
6236 if (t
->operand_types
[op
].bitfield
.xmmword
6237 && i
.types
[op
].bitfield
.ymmword
)
6239 i
.error
= unsupported
;
6245 /* Without VSIB byte, we can't have a vector register for index. */
6246 if (!t
->opcode_modifier
.sib
6248 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6249 || i
.index_reg
->reg_type
.bitfield
.ymmword
6250 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6252 i
.error
= unsupported_vector_index_register
;
6256 /* Check if default mask is allowed. */
6257 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6258 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6260 i
.error
= no_default_mask
;
6264 /* For VSIB byte, we need a vector register for index, and all vector
6265 registers must be distinct. */
6266 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6269 || !((t
->opcode_modifier
.sib
== VECSIB128
6270 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6271 || (t
->opcode_modifier
.sib
== VECSIB256
6272 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6273 || (t
->opcode_modifier
.sib
== VECSIB512
6274 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6276 i
.error
= invalid_vsib_address
;
6280 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6281 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6283 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6284 gas_assert (i
.types
[0].bitfield
.xmmword
6285 || i
.types
[0].bitfield
.ymmword
);
6286 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6287 gas_assert (i
.types
[2].bitfield
.xmmword
6288 || i
.types
[2].bitfield
.ymmword
);
6289 if (operand_check
== check_none
)
6291 if (register_number (i
.op
[0].regs
)
6292 != register_number (i
.index_reg
)
6293 && register_number (i
.op
[2].regs
)
6294 != register_number (i
.index_reg
)
6295 && register_number (i
.op
[0].regs
)
6296 != register_number (i
.op
[2].regs
))
6298 if (operand_check
== check_error
)
6300 i
.error
= invalid_vector_register_set
;
6303 as_warn (_("mask, index, and destination registers should be distinct"));
6305 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6307 if (i
.types
[1].bitfield
.class == RegSIMD
6308 && (i
.types
[1].bitfield
.xmmword
6309 || i
.types
[1].bitfield
.ymmword
6310 || i
.types
[1].bitfield
.zmmword
)
6311 && (register_number (i
.op
[1].regs
)
6312 == register_number (i
.index_reg
)))
6314 if (operand_check
== check_error
)
6316 i
.error
= invalid_vector_register_set
;
6319 if (operand_check
!= check_none
)
6320 as_warn (_("index and destination registers should be distinct"));
6325 /* For AMX instructions with 3 TMM register operands, all operands
6326 must be distinct. */
6327 if (i
.reg_operands
== 3
6328 && t
->operand_types
[0].bitfield
.tmmword
6329 && (i
.op
[0].regs
== i
.op
[1].regs
6330 || i
.op
[0].regs
== i
.op
[2].regs
6331 || i
.op
[1].regs
== i
.op
[2].regs
))
6333 i
.error
= invalid_tmm_register_set
;
6337 /* For some special instructions require that destination must be distinct
6338 from source registers. */
6339 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6341 unsigned int dest_reg
= i
.operands
- 1;
6343 know (i
.operands
>= 3);
6345 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6346 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6347 || (i
.reg_operands
> 2
6348 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6350 i
.error
= invalid_dest_and_src_register_set
;
6355 /* Check if broadcast is supported by the instruction and is applied
6356 to the memory operand. */
6357 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6359 i386_operand_type type
, overlap
;
6361 /* Check if specified broadcast is supported in this instruction,
6362 and its broadcast bytes match the memory operand. */
6363 op
= i
.broadcast
.operand
;
6364 if (!t
->opcode_modifier
.broadcast
6365 || !(i
.flags
[op
] & Operand_Mem
)
6366 || (!i
.types
[op
].bitfield
.unspecified
6367 && !match_broadcast_size (t
, op
)))
6370 i
.error
= unsupported_broadcast
;
6374 if (i
.broadcast
.type
)
6375 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6376 * i
.broadcast
.type
);
6377 operand_type_set (&type
, 0);
6378 switch (get_broadcast_bytes (t
, false))
6381 type
.bitfield
.word
= 1;
6384 type
.bitfield
.dword
= 1;
6387 type
.bitfield
.qword
= 1;
6390 type
.bitfield
.xmmword
= 1;
6393 type
.bitfield
.ymmword
= 1;
6396 type
.bitfield
.zmmword
= 1;
6402 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6403 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6404 && t
->operand_types
[op
].bitfield
.byte
6405 + t
->operand_types
[op
].bitfield
.word
6406 + t
->operand_types
[op
].bitfield
.dword
6407 + t
->operand_types
[op
].bitfield
.qword
> 1)
6409 overlap
.bitfield
.xmmword
= 0;
6410 overlap
.bitfield
.ymmword
= 0;
6411 overlap
.bitfield
.zmmword
= 0;
6413 if (operand_type_all_zero (&overlap
))
6416 if (t
->opcode_modifier
.checkoperandsize
)
6420 type
.bitfield
.baseindex
= 1;
6421 for (j
= 0; j
< i
.operands
; ++j
)
6424 && !operand_type_register_match(i
.types
[j
],
6425 t
->operand_types
[j
],
6427 t
->operand_types
[op
]))
6432 /* If broadcast is supported in this instruction, we need to check if
6433 operand of one-element size isn't specified without broadcast. */
6434 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6436 /* Find memory operand. */
6437 for (op
= 0; op
< i
.operands
; op
++)
6438 if (i
.flags
[op
] & Operand_Mem
)
6440 gas_assert (op
< i
.operands
);
6441 /* Check size of the memory operand. */
6442 if (match_broadcast_size (t
, op
))
6444 i
.error
= broadcast_needed
;
6449 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6451 /* Check if requested masking is supported. */
6454 switch (t
->opcode_modifier
.masking
)
6458 case MERGING_MASKING
:
6462 i
.error
= unsupported_masking
;
6466 case DYNAMIC_MASKING
:
6467 /* Memory destinations allow only merging masking. */
6468 if (i
.mask
.zeroing
&& i
.mem_operands
)
6470 /* Find memory operand. */
6471 for (op
= 0; op
< i
.operands
; op
++)
6472 if (i
.flags
[op
] & Operand_Mem
)
6474 gas_assert (op
< i
.operands
);
6475 if (op
== i
.operands
- 1)
6477 i
.error
= unsupported_masking
;
6487 /* Check if masking is applied to dest operand. */
6488 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6490 i
.error
= mask_not_on_destination
;
6495 if (i
.rounding
.type
!= rc_none
)
6497 if (!t
->opcode_modifier
.sae
6498 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6501 i
.error
= unsupported_rc_sae
;
6505 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6507 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6509 for (op
= 0; op
< t
->operands
; ++op
)
6510 if (i
.types
[op
].bitfield
.zmmword
)
6512 if (op
>= t
->operands
)
6514 i
.error
= operand_size_mismatch
;
6520 /* Check the special Imm4 cases; must be the first operand. */
6521 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6523 if (i
.op
[0].imms
->X_op
!= O_constant
6524 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6530 /* Turn off Imm<N> so that update_imm won't complain. */
6531 operand_type_set (&i
.types
[0], 0);
6534 /* Check vector Disp8 operand. */
6535 if (t
->opcode_modifier
.disp8memshift
6536 && i
.disp_encoding
<= disp_encoding_8bit
)
6538 if (i
.broadcast
.bytes
)
6539 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6540 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6541 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6544 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6547 for (op
= 0; op
< i
.operands
; op
++)
6548 if (i
.flags
[op
] & Operand_Mem
)
6550 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6551 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6552 else if (t
->operand_types
[op
].bitfield
.xmmword
6553 + t
->operand_types
[op
].bitfield
.ymmword
6554 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6555 type
= &t
->operand_types
[op
];
6556 else if (!i
.types
[op
].bitfield
.unspecified
)
6557 type
= &i
.types
[op
];
6558 else /* Ambiguities get resolved elsewhere. */
6559 fallback
= &t
->operand_types
[op
];
6561 else if (i
.types
[op
].bitfield
.class == RegSIMD
6562 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6564 if (i
.types
[op
].bitfield
.zmmword
)
6566 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6568 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6572 if (!type
&& !i
.memshift
)
6576 if (type
->bitfield
.zmmword
)
6578 else if (type
->bitfield
.ymmword
)
6580 else if (type
->bitfield
.xmmword
)
6584 /* For the check in fits_in_disp8(). */
6585 if (i
.memshift
== 0)
6589 for (op
= 0; op
< i
.operands
; op
++)
6590 if (operand_type_check (i
.types
[op
], disp
)
6591 && i
.op
[op
].disps
->X_op
== O_constant
)
6593 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6595 i
.types
[op
].bitfield
.disp8
= 1;
6598 i
.types
[op
].bitfield
.disp8
= 0;
6607 /* Check if encoding requirements are met by the instruction. */
6610 VEX_check_encoding (const insn_template
*t
)
6612 if (i
.vec_encoding
== vex_encoding_error
)
6614 i
.error
= unsupported
;
6618 if (i
.vec_encoding
== vex_encoding_evex
)
6620 /* This instruction must be encoded with EVEX prefix. */
6621 if (!is_evex_encoding (t
))
6623 i
.error
= unsupported
;
6629 if (!t
->opcode_modifier
.vex
)
6631 /* This instruction template doesn't have VEX prefix. */
6632 if (i
.vec_encoding
!= vex_encoding_default
)
6634 i
.error
= unsupported
;
6643 /* Helper function for the progress() macro in match_template(). */
6644 static INLINE
enum i386_error
progress (enum i386_error
new,
6645 enum i386_error last
,
6646 unsigned int line
, unsigned int *line_p
)
6648 if (line
<= *line_p
)
6654 static const insn_template
*
6655 match_template (char mnem_suffix
)
6657 /* Points to template once we've found it. */
6658 const insn_template
*t
;
6659 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6660 i386_operand_type overlap4
;
6661 unsigned int found_reverse_match
;
6662 i386_operand_type operand_types
[MAX_OPERANDS
];
6663 int addr_prefix_disp
;
6664 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6665 enum i386_error specific_error
= number_of_operands_mismatch
;
6666 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6668 #if MAX_OPERANDS != 5
6669 # error "MAX_OPERANDS must be 5."
6672 found_reverse_match
= 0;
6673 addr_prefix_disp
= -1;
6675 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6677 addr_prefix_disp
= -1;
6678 found_reverse_match
= 0;
6680 /* Must have right number of operands. */
6681 if (i
.operands
!= t
->operands
)
6684 /* Check processor support. */
6685 specific_error
= progress (unsupported
);
6686 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6689 /* Check AT&T mnemonic. */
6690 specific_error
= progress (unsupported_with_intel_mnemonic
);
6691 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6694 /* Check AT&T/Intel syntax. */
6695 specific_error
= progress (unsupported_syntax
);
6696 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6697 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6700 /* Check Intel64/AMD64 ISA. */
6704 /* Default: Don't accept Intel64. */
6705 if (t
->opcode_modifier
.isa64
== INTEL64
)
6709 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6710 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6714 /* -mintel64: Don't accept AMD64. */
6715 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6720 /* Check the suffix. */
6721 specific_error
= progress (invalid_instruction_suffix
);
6722 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6723 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6724 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6725 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6726 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6729 specific_error
= progress (operand_size_mismatch
);
6730 size_match
= operand_size_match (t
);
6734 /* This is intentionally not
6736 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6738 as the case of a missing * on the operand is accepted (perhaps with
6739 a warning, issued further down). */
6740 specific_error
= progress (operand_type_mismatch
);
6741 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6744 /* In Intel syntax, normally we can check for memory operand size when
6745 there is no mnemonic suffix. But jmp and call have 2 different
6746 encodings with Dword memory operand size. Skip the "near" one
6747 (permitting a register operand) when "far" was requested. */
6749 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
6750 && t
->operand_types
[0].bitfield
.class == Reg
)
6753 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6754 operand_types
[j
] = t
->operand_types
[j
];
6756 /* In general, don't allow 32-bit operands on pre-386. */
6757 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
6758 : operand_size_mismatch
);
6759 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6760 if (i
.suffix
== LONG_MNEM_SUFFIX
6761 && !cpu_arch_flags
.bitfield
.cpui386
6763 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6764 && !intel_float_operand (insn_name (t
)))
6765 : intel_float_operand (insn_name (t
)) != 2)
6766 && (t
->operands
== i
.imm_operands
6767 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6768 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6769 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6770 || (operand_types
[j
].bitfield
.class != RegMMX
6771 && operand_types
[j
].bitfield
.class != RegSIMD
6772 && operand_types
[j
].bitfield
.class != RegMask
))
6773 && !t
->opcode_modifier
.sib
)
6776 /* Do not verify operands when there are none. */
6779 if (VEX_check_encoding (t
))
6781 specific_error
= progress (i
.error
);
6785 /* We've found a match; break out of loop. */
6789 if (!t
->opcode_modifier
.jump
6790 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6792 /* There should be only one Disp operand. */
6793 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6794 if (operand_type_check (operand_types
[j
], disp
))
6796 if (j
< MAX_OPERANDS
)
6798 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6800 addr_prefix_disp
= j
;
6802 /* Address size prefix will turn Disp64 operand into Disp32 and
6803 Disp32/Disp16 one into Disp16/Disp32 respectively. */
6807 override
= !override
;
6810 if (operand_types
[j
].bitfield
.disp32
6811 && operand_types
[j
].bitfield
.disp16
)
6813 operand_types
[j
].bitfield
.disp16
= override
;
6814 operand_types
[j
].bitfield
.disp32
= !override
;
6816 gas_assert (!operand_types
[j
].bitfield
.disp64
);
6820 if (operand_types
[j
].bitfield
.disp64
)
6822 gas_assert (!operand_types
[j
].bitfield
.disp32
);
6823 operand_types
[j
].bitfield
.disp32
= override
;
6824 operand_types
[j
].bitfield
.disp64
= !override
;
6826 operand_types
[j
].bitfield
.disp16
= 0;
6832 /* We check register size if needed. */
6833 if (t
->opcode_modifier
.checkoperandsize
)
6835 check_register
= (1 << t
->operands
) - 1;
6836 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6837 check_register
&= ~(1 << i
.broadcast
.operand
);
6842 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6843 switch (t
->operands
)
6846 if (!operand_type_match (overlap0
, i
.types
[0]))
6850 /* xchg %eax, %eax is a special case. It is an alias for nop
6851 only in 32bit mode and we can use opcode 0x90. In 64bit
6852 mode, we can't use 0x90 for xchg %eax, %eax since it should
6853 zero-extend %eax to %rax. */
6854 if (flag_code
== CODE_64BIT
6855 && t
->base_opcode
== 0x90
6856 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6857 && i
.types
[0].bitfield
.instance
== Accum
6858 && i
.types
[0].bitfield
.dword
6859 && i
.types
[1].bitfield
.instance
== Accum
)
6862 if (t
->base_opcode
== MOV_AX_DISP32
6863 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6864 && t
->mnem_off
!= MN_movabs
)
6866 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6867 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
6870 /* xrelease mov %eax, <disp> is another special case. It must not
6871 match the accumulator-only encoding of mov. */
6878 if (!(size_match
& MATCH_STRAIGHT
))
6880 /* Reverse direction of operands if swapping is possible in the first
6881 place (operands need to be symmetric) and
6882 - the load form is requested, and the template is a store form,
6883 - the store form is requested, and the template is a load form,
6884 - the non-default (swapped) form is requested. */
6885 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6886 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6887 && !operand_type_all_zero (&overlap1
))
6888 switch (i
.dir_encoding
)
6890 case dir_encoding_load
:
6891 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6892 || t
->opcode_modifier
.regmem
)
6896 case dir_encoding_store
:
6897 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6898 && !t
->opcode_modifier
.regmem
)
6902 case dir_encoding_swap
:
6905 case dir_encoding_default
:
6908 /* If we want store form, we skip the current load. */
6909 if ((i
.dir_encoding
== dir_encoding_store
6910 || i
.dir_encoding
== dir_encoding_swap
)
6911 && i
.mem_operands
== 0
6912 && t
->opcode_modifier
.load
)
6917 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6918 if (!operand_type_match (overlap0
, i
.types
[0])
6919 || !operand_type_match (overlap1
, i
.types
[1])
6920 || ((check_register
& 3) == 3
6921 && !operand_type_register_match (i
.types
[0],
6926 specific_error
= progress (i
.error
);
6928 /* Check if other direction is valid ... */
6929 if (!t
->opcode_modifier
.d
)
6933 if (!(size_match
& MATCH_REVERSE
))
6935 /* Try reversing direction of operands. */
6936 j
= t
->opcode_modifier
.vexsources
? 1 : i
.operands
- 1;
6937 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
6938 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
6939 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
6940 gas_assert (t
->operands
!= 3 || !check_register
);
6941 if (!operand_type_match (overlap0
, i
.types
[0])
6942 || !operand_type_match (overlap1
, i
.types
[j
])
6943 || (t
->operands
== 3
6944 && !operand_type_match (overlap2
, i
.types
[1]))
6946 && !operand_type_register_match (i
.types
[0],
6951 /* Does not match either direction. */
6952 specific_error
= progress (i
.error
);
6955 /* found_reverse_match holds which variant of D
6957 if (!t
->opcode_modifier
.d
)
6958 found_reverse_match
= 0;
6959 else if (operand_types
[0].bitfield
.tbyte
)
6961 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
6962 found_reverse_match
= Opcode_FloatD
;
6964 found_reverse_match
= ~0;
6965 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
6966 if ((t
->extension_opcode
& 4)
6967 && (intel_syntax
|| intel_mnemonic
))
6968 found_reverse_match
|= Opcode_FloatR
;
6970 else if (t
->opcode_modifier
.vexsources
)
6972 found_reverse_match
= Opcode_VexW
;
6973 goto check_operands_345
;
6975 else if (t
->opcode_modifier
.opcodespace
!= SPACE_BASE
6976 && (t
->opcode_modifier
.opcodespace
!= SPACE_0F
6977 /* MOV to/from CR/DR/TR, as an exception, follow
6978 the base opcode space encoding model. */
6979 || (t
->base_opcode
| 7) != 0x27))
6980 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6981 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
6982 else if (!t
->opcode_modifier
.commutative
)
6983 found_reverse_match
= Opcode_D
;
6985 found_reverse_match
= ~0;
6989 /* Found a forward 2 operand match here. */
6991 switch (t
->operands
)
6994 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
6995 if (!operand_type_match (overlap4
, i
.types
[4])
6996 || !operand_type_register_match (i
.types
[3],
7001 specific_error
= progress (i
.error
);
7006 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7007 if (!operand_type_match (overlap3
, i
.types
[3])
7008 || ((check_register
& 0xa) == 0xa
7009 && !operand_type_register_match (i
.types
[1],
7013 || ((check_register
& 0xc) == 0xc
7014 && !operand_type_register_match (i
.types
[2],
7019 specific_error
= progress (i
.error
);
7024 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7025 if (!operand_type_match (overlap2
, i
.types
[2])
7026 || ((check_register
& 5) == 5
7027 && !operand_type_register_match (i
.types
[0],
7031 || ((check_register
& 6) == 6
7032 && !operand_type_register_match (i
.types
[1],
7037 specific_error
= progress (i
.error
);
7043 /* Found either forward/reverse 2, 3 or 4 operand match here:
7044 slip through to break. */
7047 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7048 if (VEX_check_encoding (t
))
7050 specific_error
= progress (i
.error
);
7054 /* Check if vector operands are valid. */
7055 if (check_VecOperands (t
))
7057 specific_error
= progress (i
.error
);
7061 /* We've found a match; break out of loop. */
7067 if (t
== current_templates
->end
)
7069 /* We found no match. */
7070 i
.error
= specific_error
;
7074 if (!quiet_warnings
)
7077 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7078 as_warn (_("indirect %s without `*'"), insn_name (t
));
7080 if (t
->opcode_modifier
.isprefix
7081 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7083 /* Warn them that a data or address size prefix doesn't
7084 affect assembly of the next line of code. */
7085 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7089 /* Copy the template we found. */
7090 install_template (t
);
7092 if (addr_prefix_disp
!= -1)
7093 i
.tm
.operand_types
[addr_prefix_disp
]
7094 = operand_types
[addr_prefix_disp
];
7096 switch (found_reverse_match
)
7102 case Opcode_FloatR
| Opcode_FloatD
:
7103 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7104 found_reverse_match
&= Opcode_FloatD
;
7108 /* If we found a reverse match we must alter the opcode direction
7109 bit and clear/flip the regmem modifier one. found_reverse_match
7110 holds bits to change (different for int & float insns). */
7112 i
.tm
.base_opcode
^= found_reverse_match
;
7114 /* Certain SIMD insns have their load forms specified in the opcode
7115 table, and hence we need to _set_ RegMem instead of clearing it.
7116 We need to avoid setting the bit though on insns like KMOVW. */
7117 i
.tm
.opcode_modifier
.regmem
7118 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7119 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7120 && !i
.tm
.opcode_modifier
.regmem
;
7124 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7125 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7129 /* Only the first two register operands need reversing, alongside
7131 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7133 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7134 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7135 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7145 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7146 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7148 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7150 as_bad (_("`%s' operand %u must use `%ses' segment"),
7152 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7157 /* There's only ever one segment override allowed per instruction.
7158 This instruction possibly has a legal segment override on the
7159 second operand, so copy the segment to where non-string
7160 instructions store it, allowing common code. */
7161 i
.seg
[op
] = i
.seg
[1];
7167 process_suffix (void)
7169 bool is_movx
= false;
7171 /* If matched instruction specifies an explicit instruction mnemonic
7173 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7174 i
.suffix
= WORD_MNEM_SUFFIX
;
7175 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7176 i
.suffix
= LONG_MNEM_SUFFIX
;
7177 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7178 i
.suffix
= QWORD_MNEM_SUFFIX
;
7179 else if (i
.reg_operands
7180 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7181 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7183 unsigned int numop
= i
.operands
;
7186 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7187 && (i
.tm
.base_opcode
| 8) == 0xbe)
7188 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7189 && i
.tm
.base_opcode
== 0x63
7190 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
7192 /* movsx/movzx want only their source operand considered here, for the
7193 ambiguity checking below. The suffix will be replaced afterwards
7194 to represent the destination (register). */
7195 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7198 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7199 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7202 /* If there's no instruction mnemonic suffix we try to invent one
7203 based on GPR operands. */
7206 /* We take i.suffix from the last register operand specified,
7207 Destination register type is more significant than source
7208 register type. crc32 in SSE4.2 prefers source register
7210 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7213 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7214 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7216 if (i
.types
[op
].bitfield
.class != Reg
)
7218 if (i
.types
[op
].bitfield
.byte
)
7219 i
.suffix
= BYTE_MNEM_SUFFIX
;
7220 else if (i
.types
[op
].bitfield
.word
)
7221 i
.suffix
= WORD_MNEM_SUFFIX
;
7222 else if (i
.types
[op
].bitfield
.dword
)
7223 i
.suffix
= LONG_MNEM_SUFFIX
;
7224 else if (i
.types
[op
].bitfield
.qword
)
7225 i
.suffix
= QWORD_MNEM_SUFFIX
;
7231 /* As an exception, movsx/movzx silently default to a byte source
7233 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7234 i
.suffix
= BYTE_MNEM_SUFFIX
;
7236 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7238 if (!check_byte_reg ())
7241 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7243 if (!check_long_reg ())
7246 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7248 if (!check_qword_reg ())
7251 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7253 if (!check_word_reg ())
7256 else if (intel_syntax
7257 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7258 /* Do nothing if the instruction is going to ignore the prefix. */
7263 /* Undo the movsx/movzx change done above. */
7266 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7269 i
.suffix
= stackop_size
;
7270 if (stackop_size
== LONG_MNEM_SUFFIX
)
7272 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7273 .code16gcc directive to support 16-bit mode with
7274 32-bit address. For IRET without a suffix, generate
7275 16-bit IRET (opcode 0xcf) to return from an interrupt
7277 if (i
.tm
.base_opcode
== 0xcf)
7279 i
.suffix
= WORD_MNEM_SUFFIX
;
7280 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7282 /* Warn about changed behavior for segment register push/pop. */
7283 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7284 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7289 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7290 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7291 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7292 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7293 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7294 && i
.tm
.extension_opcode
<= 3)))
7299 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7301 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7302 || i
.tm
.opcode_modifier
.no_lsuf
)
7303 i
.suffix
= QWORD_MNEM_SUFFIX
;
7308 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7309 i
.suffix
= LONG_MNEM_SUFFIX
;
7312 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7313 i
.suffix
= WORD_MNEM_SUFFIX
;
7319 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7320 /* Also cover lret/retf/iret in 64-bit mode. */
7321 || (flag_code
== CODE_64BIT
7322 && !i
.tm
.opcode_modifier
.no_lsuf
7323 && !i
.tm
.opcode_modifier
.no_qsuf
))
7324 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7325 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7326 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7327 /* Accept FLDENV et al without suffix. */
7328 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7330 unsigned int suffixes
, evex
= 0;
7332 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7333 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7335 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7337 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7339 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7342 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7343 also suitable for AT&T syntax mode, it was requested that this be
7344 restricted to just Intel syntax. */
7345 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7346 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7350 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7352 if (is_evex_encoding (&i
.tm
)
7353 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7355 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7356 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7357 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7358 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7359 if (!i
.tm
.opcode_modifier
.evex
7360 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7361 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7364 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7365 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7366 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7369 /* Any properly sized operand disambiguates the insn. */
7370 if (i
.types
[op
].bitfield
.xmmword
7371 || i
.types
[op
].bitfield
.ymmword
7372 || i
.types
[op
].bitfield
.zmmword
)
7374 suffixes
&= ~(7 << 6);
7379 if ((i
.flags
[op
] & Operand_Mem
)
7380 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7382 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7384 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7386 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7388 if (is_evex_encoding (&i
.tm
))
7394 /* Are multiple suffixes / operand sizes allowed? */
7395 if (suffixes
& (suffixes
- 1))
7398 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7399 || operand_check
== check_error
))
7401 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7404 if (operand_check
== check_error
)
7406 as_bad (_("no instruction mnemonic suffix given and "
7407 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7410 if (operand_check
== check_warning
)
7411 as_warn (_("%s; using default for `%s'"),
7413 ? _("ambiguous operand size")
7414 : _("no instruction mnemonic suffix given and "
7415 "no register operands"),
7418 if (i
.tm
.opcode_modifier
.floatmf
)
7419 i
.suffix
= SHORT_MNEM_SUFFIX
;
7421 /* handled below */;
7423 i
.tm
.opcode_modifier
.evex
= evex
;
7424 else if (flag_code
== CODE_16BIT
)
7425 i
.suffix
= WORD_MNEM_SUFFIX
;
7426 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7427 i
.suffix
= LONG_MNEM_SUFFIX
;
7429 i
.suffix
= QWORD_MNEM_SUFFIX
;
7435 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7436 In AT&T syntax, if there is no suffix (warned about above), the default
7437 will be byte extension. */
7438 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7439 i
.tm
.base_opcode
|= 1;
7441 /* For further processing, the suffix should represent the destination
7442 (register). This is already the case when one was used with
7443 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7444 no suffix to begin with. */
7445 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7447 if (i
.types
[1].bitfield
.word
)
7448 i
.suffix
= WORD_MNEM_SUFFIX
;
7449 else if (i
.types
[1].bitfield
.qword
)
7450 i
.suffix
= QWORD_MNEM_SUFFIX
;
7452 i
.suffix
= LONG_MNEM_SUFFIX
;
7454 i
.tm
.opcode_modifier
.w
= 0;
7458 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7459 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7460 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7462 /* Change the opcode based on the operand size given by i.suffix. */
7465 /* Size floating point instruction. */
7466 case LONG_MNEM_SUFFIX
:
7467 if (i
.tm
.opcode_modifier
.floatmf
)
7469 i
.tm
.base_opcode
^= 4;
7473 case WORD_MNEM_SUFFIX
:
7474 case QWORD_MNEM_SUFFIX
:
7475 /* It's not a byte, select word/dword operation. */
7476 if (i
.tm
.opcode_modifier
.w
)
7479 i
.tm
.base_opcode
|= 8;
7481 i
.tm
.base_opcode
|= 1;
7484 case SHORT_MNEM_SUFFIX
:
7485 /* Now select between word & dword operations via the operand
7486 size prefix, except for instructions that will ignore this
7488 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7489 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7490 && !i
.tm
.opcode_modifier
.floatmf
7491 && !is_any_vex_encoding (&i
.tm
)
7492 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7493 || (flag_code
== CODE_64BIT
7494 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7496 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7498 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7499 prefix
= ADDR_PREFIX_OPCODE
;
7501 if (!add_prefix (prefix
))
7505 /* Set mode64 for an operand. */
7506 if (i
.suffix
== QWORD_MNEM_SUFFIX
7507 && flag_code
== CODE_64BIT
7508 && !i
.tm
.opcode_modifier
.norex64
7509 && !i
.tm
.opcode_modifier
.vexw
7510 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7512 && ! (i
.operands
== 2
7513 && i
.tm
.base_opcode
== 0x90
7514 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7515 && i
.types
[0].bitfield
.instance
== Accum
7516 && i
.types
[0].bitfield
.qword
7517 && i
.types
[1].bitfield
.instance
== Accum
))
7523 /* Select word/dword/qword operation with explicit data sizing prefix
7524 when there are no suitable register operands. */
7525 if (i
.tm
.opcode_modifier
.w
7526 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7528 || (i
.reg_operands
== 1
7530 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7532 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7533 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7534 || i
.tm
.mnem_off
== MN_crc32
))))
7535 i
.tm
.base_opcode
|= 1;
7539 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7541 gas_assert (!i
.suffix
);
7542 gas_assert (i
.reg_operands
);
7544 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7547 /* The address size override prefix changes the size of the
7549 if (flag_code
== CODE_64BIT
7550 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7552 as_bad (_("16-bit addressing unavailable for `%s'"),
7557 if ((flag_code
== CODE_32BIT
7558 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7559 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7560 && !add_prefix (ADDR_PREFIX_OPCODE
))
7565 /* Check invalid register operand when the address size override
7566 prefix changes the size of register operands. */
7568 enum { need_word
, need_dword
, need_qword
} need
;
7570 /* Check the register operand for the address size prefix if
7571 the memory operand has no real registers, like symbol, DISP
7572 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7573 if (i
.mem_operands
== 1
7574 && i
.reg_operands
== 1
7576 && i
.types
[1].bitfield
.class == Reg
7577 && (flag_code
== CODE_32BIT
7578 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7579 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7580 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7581 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7582 || (x86_elf_abi
== X86_64_X32_ABI
7584 && i
.base_reg
->reg_num
== RegIP
7585 && i
.base_reg
->reg_type
.bitfield
.qword
))
7589 && !add_prefix (ADDR_PREFIX_OPCODE
))
7592 if (flag_code
== CODE_32BIT
)
7593 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7594 else if (i
.prefix
[ADDR_PREFIX
])
7597 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7599 for (op
= 0; op
< i
.operands
; op
++)
7601 if (i
.types
[op
].bitfield
.class != Reg
)
7607 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7611 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7615 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7620 as_bad (_("invalid register operand size for `%s'"),
7631 check_byte_reg (void)
7635 for (op
= i
.operands
; --op
>= 0;)
7637 /* Skip non-register operands. */
7638 if (i
.types
[op
].bitfield
.class != Reg
)
7641 /* If this is an eight bit register, it's OK. If it's the 16 or
7642 32 bit version of an eight bit register, we will just use the
7643 low portion, and that's OK too. */
7644 if (i
.types
[op
].bitfield
.byte
)
7647 /* I/O port address operands are OK too. */
7648 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7649 && i
.tm
.operand_types
[op
].bitfield
.word
)
7652 /* crc32 only wants its source operand checked here. */
7653 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
7656 /* Any other register is bad. */
7657 as_bad (_("`%s%s' not allowed with `%s%c'"),
7658 register_prefix
, i
.op
[op
].regs
->reg_name
,
7659 insn_name (&i
.tm
), i
.suffix
);
7666 check_long_reg (void)
7670 for (op
= i
.operands
; --op
>= 0;)
7671 /* Skip non-register operands. */
7672 if (i
.types
[op
].bitfield
.class != Reg
)
7674 /* Reject eight bit registers, except where the template requires
7675 them. (eg. movzb) */
7676 else if (i
.types
[op
].bitfield
.byte
7677 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7678 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7679 && (i
.tm
.operand_types
[op
].bitfield
.word
7680 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7682 as_bad (_("`%s%s' not allowed with `%s%c'"),
7684 i
.op
[op
].regs
->reg_name
,
7689 /* Error if the e prefix on a general reg is missing. */
7690 else if (i
.types
[op
].bitfield
.word
7691 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7692 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7693 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7695 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7696 register_prefix
, i
.op
[op
].regs
->reg_name
,
7700 /* Warn if the r prefix on a general reg is present. */
7701 else if (i
.types
[op
].bitfield
.qword
7702 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7703 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7704 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7706 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7707 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7714 check_qword_reg (void)
7718 for (op
= i
.operands
; --op
>= 0; )
7719 /* Skip non-register operands. */
7720 if (i
.types
[op
].bitfield
.class != Reg
)
7722 /* Reject eight bit registers, except where the template requires
7723 them. (eg. movzb) */
7724 else if (i
.types
[op
].bitfield
.byte
7725 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7726 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7727 && (i
.tm
.operand_types
[op
].bitfield
.word
7728 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7730 as_bad (_("`%s%s' not allowed with `%s%c'"),
7732 i
.op
[op
].regs
->reg_name
,
7737 /* Warn if the r prefix on a general reg is missing. */
7738 else if ((i
.types
[op
].bitfield
.word
7739 || i
.types
[op
].bitfield
.dword
)
7740 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7741 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7742 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7744 /* Prohibit these changes in the 64bit mode, since the
7745 lowering is more complicated. */
7746 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7747 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7754 check_word_reg (void)
7757 for (op
= i
.operands
; --op
>= 0;)
7758 /* Skip non-register operands. */
7759 if (i
.types
[op
].bitfield
.class != Reg
)
7761 /* Reject eight bit registers, except where the template requires
7762 them. (eg. movzb) */
7763 else if (i
.types
[op
].bitfield
.byte
7764 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7765 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7766 && (i
.tm
.operand_types
[op
].bitfield
.word
7767 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7769 as_bad (_("`%s%s' not allowed with `%s%c'"),
7771 i
.op
[op
].regs
->reg_name
,
7776 /* Error if the e or r prefix on a general reg is present. */
7777 else if ((i
.types
[op
].bitfield
.dword
7778 || i
.types
[op
].bitfield
.qword
)
7779 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7780 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7781 && i
.tm
.operand_types
[op
].bitfield
.word
)
7783 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7784 register_prefix
, i
.op
[op
].regs
->reg_name
,
7792 update_imm (unsigned int j
)
7794 i386_operand_type overlap
= i
.types
[j
];
7795 if (overlap
.bitfield
.imm8
7796 + overlap
.bitfield
.imm8s
7797 + overlap
.bitfield
.imm16
7798 + overlap
.bitfield
.imm32
7799 + overlap
.bitfield
.imm32s
7800 + overlap
.bitfield
.imm64
> 1)
7802 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
7803 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
7804 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
7805 static const i386_operand_type imm16_32
= { .bitfield
=
7806 { .imm16
= 1, .imm32
= 1 }
7808 static const i386_operand_type imm16_32s
= { .bitfield
=
7809 { .imm16
= 1, .imm32s
= 1 }
7811 static const i386_operand_type imm16_32_32s
= { .bitfield
=
7812 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
7817 i386_operand_type temp
;
7819 operand_type_set (&temp
, 0);
7820 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7822 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7823 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7825 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7826 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7827 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7829 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7830 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7833 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7836 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7837 || operand_type_equal (&overlap
, &imm16_32
)
7838 || operand_type_equal (&overlap
, &imm16_32s
))
7840 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7845 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7846 overlap
= operand_type_and (overlap
, imm32s
);
7847 else if (i
.prefix
[DATA_PREFIX
])
7848 overlap
= operand_type_and (overlap
,
7849 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7850 if (overlap
.bitfield
.imm8
7851 + overlap
.bitfield
.imm8s
7852 + overlap
.bitfield
.imm16
7853 + overlap
.bitfield
.imm32
7854 + overlap
.bitfield
.imm32s
7855 + overlap
.bitfield
.imm64
!= 1)
7857 as_bad (_("no instruction mnemonic suffix given; "
7858 "can't determine immediate size"));
7862 i
.types
[j
] = overlap
;
7872 /* Update the first 2 immediate operands. */
7873 n
= i
.operands
> 2 ? 2 : i
.operands
;
7876 for (j
= 0; j
< n
; j
++)
7877 if (update_imm (j
) == 0)
7880 /* The 3rd operand can't be immediate operand. */
7881 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7888 process_operands (void)
7890 /* Default segment register this instruction will use for memory
7891 accesses. 0 means unknown. This is only for optimizing out
7892 unnecessary segment overrides. */
7893 const reg_entry
*default_seg
= NULL
;
7895 /* We only need to check those implicit registers for instructions
7896 with 3 operands or less. */
7897 if (i
.operands
<= 3)
7898 for (unsigned int j
= 0; j
< i
.operands
; j
++)
7899 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
7902 if (i
.tm
.opcode_modifier
.sse2avx
)
7904 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7906 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7907 i
.prefix
[REX_PREFIX
] = 0;
7910 /* ImmExt should be processed after SSE2AVX. */
7911 else if (i
.tm
.opcode_modifier
.immext
)
7914 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7916 static const i386_operand_type regxmm
= {
7917 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
7919 unsigned int dupl
= i
.operands
;
7920 unsigned int dest
= dupl
- 1;
7923 /* The destination must be an xmm register. */
7924 gas_assert (i
.reg_operands
7925 && MAX_OPERANDS
> dupl
7926 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7928 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7929 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7931 gas_assert (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
);
7932 /* Keep xmm0 for instructions with VEX prefix and 3
7934 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7935 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7940 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
7942 gas_assert ((MAX_OPERANDS
- 1) > dupl
7943 && (i
.tm
.opcode_modifier
.vexsources
7946 /* Add the implicit xmm0 for instructions with VEX prefix
7948 for (j
= i
.operands
; j
> 0; j
--)
7950 i
.op
[j
] = i
.op
[j
- 1];
7951 i
.types
[j
] = i
.types
[j
- 1];
7952 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7953 i
.flags
[j
] = i
.flags
[j
- 1];
7956 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7957 i
.types
[0] = regxmm
;
7958 i
.tm
.operand_types
[0] = regxmm
;
7961 i
.reg_operands
+= 2;
7966 i
.op
[dupl
] = i
.op
[dest
];
7967 i
.types
[dupl
] = i
.types
[dest
];
7968 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7969 i
.flags
[dupl
] = i
.flags
[dest
];
7978 i
.op
[dupl
] = i
.op
[dest
];
7979 i
.types
[dupl
] = i
.types
[dest
];
7980 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7981 i
.flags
[dupl
] = i
.flags
[dest
];
7984 if (i
.tm
.opcode_modifier
.immext
)
7987 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7988 && i
.tm
.opcode_modifier
.modrm
)
7992 for (j
= 1; j
< i
.operands
; j
++)
7994 i
.op
[j
- 1] = i
.op
[j
];
7995 i
.types
[j
- 1] = i
.types
[j
];
7997 /* We need to adjust fields in i.tm since they are used by
7998 build_modrm_byte. */
7999 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8001 i
.flags
[j
- 1] = i
.flags
[j
];
8004 /* No adjustment to i.reg_operands: This was already done at the top
8009 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8011 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8013 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8014 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8015 regnum
= register_number (i
.op
[1].regs
);
8016 first_reg_in_group
= regnum
& ~3;
8017 last_reg_in_group
= first_reg_in_group
+ 3;
8018 if (regnum
!= first_reg_in_group
)
8019 as_warn (_("source register `%s%s' implicitly denotes"
8020 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8021 register_prefix
, i
.op
[1].regs
->reg_name
,
8022 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8023 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8026 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8028 /* The imul $imm, %reg instruction is converted into
8029 imul $imm, %reg, %reg, and the clr %reg instruction
8030 is converted into xor %reg, %reg. */
8032 unsigned int first_reg_op
;
8034 if (operand_type_check (i
.types
[0], reg
))
8038 /* Pretend we saw the extra register operand. */
8039 gas_assert (i
.reg_operands
== 1
8040 && i
.op
[first_reg_op
+ 1].regs
== 0);
8041 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8042 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8047 if (i
.tm
.opcode_modifier
.modrm
)
8049 /* The opcode is completed (modulo i.tm.extension_opcode which
8050 must be put into the modrm byte). Now, we make the modrm and
8051 index base bytes based on all the info we've collected. */
8053 default_seg
= build_modrm_byte ();
8055 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8057 /* Warn about some common errors, but press on regardless. */
8058 if (i
.operands
== 2)
8060 /* Reversed arguments on faddp or fmulp. */
8061 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8062 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8063 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8065 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8067 /* Extraneous `l' suffix on fp insn. */
8068 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8069 register_prefix
, i
.op
[0].regs
->reg_name
);
8073 else if (i
.types
[0].bitfield
.class == SReg
)
8075 if (flag_code
!= CODE_64BIT
8076 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8077 && i
.op
[0].regs
->reg_num
== 1
8078 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8079 && i
.op
[0].regs
->reg_num
< 4)
8081 as_bad (_("you can't `%s %s%s'"),
8082 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8085 if (i
.op
[0].regs
->reg_num
> 3
8086 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
8088 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8089 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
8091 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8093 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
8094 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8096 default_seg
= reg_ds
;
8098 else if (i
.tm
.opcode_modifier
.isstring
)
8100 /* For the string instructions that allow a segment override
8101 on one of their operands, the default segment is ds. */
8102 default_seg
= reg_ds
;
8104 else if (i
.short_form
)
8106 /* The register operand is in operand 0 or 1. */
8107 const reg_entry
*r
= i
.op
[0].regs
;
8110 || (r
->reg_type
.bitfield
.instance
== Accum
&& i
.op
[1].regs
))
8112 /* Register goes in low 3 bits of opcode. */
8113 i
.tm
.base_opcode
|= r
->reg_num
;
8114 if ((r
->reg_flags
& RegRex
) != 0)
8118 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8119 && i
.tm
.mnem_off
== MN_lea
)
8121 if (!quiet_warnings
)
8122 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8123 if (optimize
&& !i
.no_optimize
)
8126 i
.prefix
[SEG_PREFIX
] = 0;
8130 /* If a segment was explicitly specified, and the specified segment
8131 is neither the default nor the one already recorded from a prefix,
8132 use an opcode prefix to select it. If we never figured out what
8133 the default segment is, then default_seg will be zero at this
8134 point, and the specified segment prefix will always be used. */
8136 && i
.seg
[0] != default_seg
8137 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8139 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8145 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8148 if (r
->reg_flags
& RegRex
)
8150 if (i
.rex
& rex_bit
)
8151 as_bad (_("same type of prefix used twice"));
8154 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8156 gas_assert (i
.vex
.register_specifier
== r
);
8157 i
.vex
.register_specifier
+= 8;
8160 if (r
->reg_flags
& RegVRex
)
8164 static const reg_entry
*
8165 build_modrm_byte (void)
8167 const reg_entry
*default_seg
= NULL
;
8168 unsigned int source
, dest
;
8171 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8174 unsigned int nds
, reg_slot
;
8177 dest
= i
.operands
- 1;
8180 /* There are 2 kinds of instructions:
8181 1. 5 operands: 4 register operands or 3 register operands
8182 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8183 VexW0 or VexW1. The destination must be either XMM, YMM or
8185 2. 4 operands: 4 register operands or 3 register operands
8186 plus 1 memory operand, with VexXDS. */
8187 gas_assert ((i
.reg_operands
== 4
8188 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8189 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8190 && i
.tm
.opcode_modifier
.vexw
8191 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8193 /* If VexW1 is set, the first non-immediate operand is the source and
8194 the second non-immediate one is encoded in the immediate operand. */
8195 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8197 source
= i
.imm_operands
;
8198 reg_slot
= i
.imm_operands
+ 1;
8202 source
= i
.imm_operands
+ 1;
8203 reg_slot
= i
.imm_operands
;
8206 if (i
.imm_operands
== 0)
8208 /* When there is no immediate operand, generate an 8bit
8209 immediate operand to encode the first operand. */
8210 exp
= &im_expressions
[i
.imm_operands
++];
8211 i
.op
[i
.operands
].imms
= exp
;
8212 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8215 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8216 exp
->X_op
= O_constant
;
8217 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8218 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8222 gas_assert (i
.imm_operands
== 1);
8223 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8224 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8226 /* Turn on Imm8 again so that output_imm will generate it. */
8227 i
.types
[0].bitfield
.imm8
= 1;
8229 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8230 i
.op
[0].imms
->X_add_number
8231 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8232 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8235 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8236 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8241 /* i.reg_operands MUST be the number of real register operands;
8242 implicit registers do not count. If there are 3 register
8243 operands, it must be a instruction with VexNDS. For a
8244 instruction with VexNDD, the destination register is encoded
8245 in VEX prefix. If there are 4 register operands, it must be
8246 a instruction with VEX prefix and 3 sources. */
8247 if (i
.mem_operands
== 0
8248 && ((i
.reg_operands
== 2
8249 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8250 || (i
.reg_operands
== 3
8251 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8252 || (i
.reg_operands
== 4 && vex_3_sources
)))
8260 /* When there are 3 operands, one of them may be immediate,
8261 which may be the first or the last operand. Otherwise,
8262 the first operand must be shift count register (cl) or it
8263 is an instruction with VexNDS. */
8264 gas_assert (i
.imm_operands
== 1
8265 || (i
.imm_operands
== 0
8266 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8267 || (i
.types
[0].bitfield
.instance
== RegC
8268 && i
.types
[0].bitfield
.byte
))));
8269 if (operand_type_check (i
.types
[0], imm
)
8270 || (i
.types
[0].bitfield
.instance
== RegC
8271 && i
.types
[0].bitfield
.byte
))
8277 /* When there are 4 operands, the first two must be 8bit
8278 immediate operands. The source operand will be the 3rd
8281 For instructions with VexNDS, if the first operand
8282 an imm8, the source operand is the 2nd one. If the last
8283 operand is imm8, the source operand is the first one. */
8284 gas_assert ((i
.imm_operands
== 2
8285 && i
.types
[0].bitfield
.imm8
8286 && i
.types
[1].bitfield
.imm8
)
8287 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8288 && i
.imm_operands
== 1
8289 && (i
.types
[0].bitfield
.imm8
8290 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
8291 if (i
.imm_operands
== 2)
8295 if (i
.types
[0].bitfield
.imm8
)
8302 gas_assert (!is_evex_encoding (&i
.tm
));
8303 gas_assert (i
.imm_operands
== 1 && vex_3_sources
);
8313 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8315 /* For instructions with VexNDS, the register-only source
8316 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8317 register. It is encoded in VEX prefix. */
8319 i386_operand_type op
;
8322 /* Swap two source operands if needed. */
8323 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
)
8331 op
= i
.tm
.operand_types
[vvvv
];
8332 if ((dest
+ 1) >= i
.operands
8333 || ((op
.bitfield
.class != Reg
8334 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8335 && op
.bitfield
.class != RegSIMD
8336 && op
.bitfield
.class != RegMask
))
8338 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8344 /* One of the register operands will be encoded in the i.rm.reg
8345 field, the other in the combined i.rm.mode and i.rm.regmem
8346 fields. If no form of this instruction supports a memory
8347 destination operand, then we assume the source operand may
8348 sometimes be a memory operand and so we need to store the
8349 destination in the i.rm.reg field. */
8350 if (!i
.tm
.opcode_modifier
.regmem
8351 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8353 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8354 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8355 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8356 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8360 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8361 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8362 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8363 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8365 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8367 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8370 add_prefix (LOCK_PREFIX_OPCODE
);
8374 { /* If it's not 2 reg operands... */
8379 unsigned int fake_zero_displacement
= 0;
8382 for (op
= 0; op
< i
.operands
; op
++)
8383 if (i
.flags
[op
] & Operand_Mem
)
8385 gas_assert (op
< i
.operands
);
8387 if (i
.tm
.opcode_modifier
.sib
)
8389 /* The index register of VSIB shouldn't be RegIZ. */
8390 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8391 && i
.index_reg
->reg_num
== RegIZ
)
8394 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8397 i
.sib
.base
= NO_BASE_REGISTER
;
8398 i
.sib
.scale
= i
.log2_scale_factor
;
8399 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8400 i
.types
[op
].bitfield
.disp32
= 1;
8403 /* Since the mandatory SIB always has index register, so
8404 the code logic remains unchanged. The non-mandatory SIB
8405 without index register is allowed and will be handled
8409 if (i
.index_reg
->reg_num
== RegIZ
)
8410 i
.sib
.index
= NO_INDEX_REGISTER
;
8412 i
.sib
.index
= i
.index_reg
->reg_num
;
8413 set_rex_vrex (i
.index_reg
, REX_X
, false);
8417 default_seg
= reg_ds
;
8419 if (i
.base_reg
== 0)
8422 if (!i
.disp_operands
)
8423 fake_zero_displacement
= 1;
8424 if (i
.index_reg
== 0)
8426 /* Both check for VSIB and mandatory non-vector SIB. */
8427 gas_assert (!i
.tm
.opcode_modifier
.sib
8428 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8429 /* Operand is just <disp> */
8430 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8431 if (flag_code
== CODE_64BIT
)
8433 /* 64bit mode overwrites the 32bit absolute
8434 addressing by RIP relative addressing and
8435 absolute addressing is encoded by one of the
8436 redundant SIB forms. */
8437 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8438 i
.sib
.base
= NO_BASE_REGISTER
;
8439 i
.sib
.index
= NO_INDEX_REGISTER
;
8440 i
.types
[op
].bitfield
.disp32
= 1;
8442 else if ((flag_code
== CODE_16BIT
)
8443 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8445 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8446 i
.types
[op
].bitfield
.disp16
= 1;
8450 i
.rm
.regmem
= NO_BASE_REGISTER
;
8451 i
.types
[op
].bitfield
.disp32
= 1;
8454 else if (!i
.tm
.opcode_modifier
.sib
)
8456 /* !i.base_reg && i.index_reg */
8457 if (i
.index_reg
->reg_num
== RegIZ
)
8458 i
.sib
.index
= NO_INDEX_REGISTER
;
8460 i
.sib
.index
= i
.index_reg
->reg_num
;
8461 i
.sib
.base
= NO_BASE_REGISTER
;
8462 i
.sib
.scale
= i
.log2_scale_factor
;
8463 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8464 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8465 i
.types
[op
].bitfield
.disp32
= 1;
8466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8470 /* RIP addressing for 64bit mode. */
8471 else if (i
.base_reg
->reg_num
== RegIP
)
8473 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8474 i
.rm
.regmem
= NO_BASE_REGISTER
;
8475 i
.types
[op
].bitfield
.disp8
= 0;
8476 i
.types
[op
].bitfield
.disp16
= 0;
8477 i
.types
[op
].bitfield
.disp32
= 1;
8478 i
.types
[op
].bitfield
.disp64
= 0;
8479 i
.flags
[op
] |= Operand_PCrel
;
8480 if (! i
.disp_operands
)
8481 fake_zero_displacement
= 1;
8483 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8485 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8486 switch (i
.base_reg
->reg_num
)
8489 if (i
.index_reg
== 0)
8491 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8492 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8495 default_seg
= reg_ss
;
8496 if (i
.index_reg
== 0)
8499 if (operand_type_check (i
.types
[op
], disp
) == 0)
8501 /* fake (%bp) into 0(%bp) */
8502 if (i
.disp_encoding
== disp_encoding_16bit
)
8503 i
.types
[op
].bitfield
.disp16
= 1;
8505 i
.types
[op
].bitfield
.disp8
= 1;
8506 fake_zero_displacement
= 1;
8509 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8510 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8512 default: /* (%si) -> 4 or (%di) -> 5 */
8513 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8515 if (!fake_zero_displacement
8519 fake_zero_displacement
= 1;
8520 if (i
.disp_encoding
== disp_encoding_8bit
)
8521 i
.types
[op
].bitfield
.disp8
= 1;
8523 i
.types
[op
].bitfield
.disp16
= 1;
8525 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8527 else /* i.base_reg and 32/64 bit mode */
8529 if (operand_type_check (i
.types
[op
], disp
))
8531 i
.types
[op
].bitfield
.disp16
= 0;
8532 i
.types
[op
].bitfield
.disp64
= 0;
8533 i
.types
[op
].bitfield
.disp32
= 1;
8536 if (!i
.tm
.opcode_modifier
.sib
)
8537 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8538 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8540 i
.sib
.base
= i
.base_reg
->reg_num
;
8541 /* x86-64 ignores REX prefix bit here to avoid decoder
8543 if (!(i
.base_reg
->reg_flags
& RegRex
)
8544 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8545 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8546 default_seg
= reg_ss
;
8547 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8549 fake_zero_displacement
= 1;
8550 if (i
.disp_encoding
== disp_encoding_32bit
)
8551 i
.types
[op
].bitfield
.disp32
= 1;
8553 i
.types
[op
].bitfield
.disp8
= 1;
8555 i
.sib
.scale
= i
.log2_scale_factor
;
8556 if (i
.index_reg
== 0)
8558 /* Only check for VSIB. */
8559 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8560 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8561 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8563 /* <disp>(%esp) becomes two byte modrm with no index
8564 register. We've already stored the code for esp
8565 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8566 Any base register besides %esp will not use the
8567 extra modrm byte. */
8568 i
.sib
.index
= NO_INDEX_REGISTER
;
8570 else if (!i
.tm
.opcode_modifier
.sib
)
8572 if (i
.index_reg
->reg_num
== RegIZ
)
8573 i
.sib
.index
= NO_INDEX_REGISTER
;
8575 i
.sib
.index
= i
.index_reg
->reg_num
;
8576 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8577 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8582 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8583 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8587 if (!fake_zero_displacement
8591 fake_zero_displacement
= 1;
8592 if (i
.disp_encoding
== disp_encoding_8bit
)
8593 i
.types
[op
].bitfield
.disp8
= 1;
8595 i
.types
[op
].bitfield
.disp32
= 1;
8597 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8601 if (fake_zero_displacement
)
8603 /* Fakes a zero displacement assuming that i.types[op]
8604 holds the correct displacement size. */
8607 gas_assert (i
.op
[op
].disps
== 0);
8608 exp
= &disp_expressions
[i
.disp_operands
++];
8609 i
.op
[op
].disps
= exp
;
8610 exp
->X_op
= O_constant
;
8611 exp
->X_add_number
= 0;
8612 exp
->X_add_symbol
= (symbolS
*) 0;
8613 exp
->X_op_symbol
= (symbolS
*) 0;
8621 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8623 if (operand_type_check (i
.types
[0], imm
))
8624 i
.vex
.register_specifier
= NULL
;
8627 /* VEX.vvvv encodes one of the sources when the first
8628 operand is not an immediate. */
8629 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8630 i
.vex
.register_specifier
= i
.op
[0].regs
;
8632 i
.vex
.register_specifier
= i
.op
[1].regs
;
8635 /* Destination is a XMM register encoded in the ModRM.reg
8637 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8638 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8641 /* ModRM.rm and VEX.B encodes the other source. */
8642 if (!i
.mem_operands
)
8646 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8647 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8649 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8651 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8655 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8657 i
.vex
.register_specifier
= i
.op
[2].regs
;
8658 if (!i
.mem_operands
)
8661 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8662 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8666 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8667 (if any) based on i.tm.extension_opcode. Again, we must be
8668 careful to make sure that segment/control/debug/test/MMX
8669 registers are coded into the i.rm.reg field. */
8670 else if (i
.reg_operands
)
8673 unsigned int vex_reg
= ~0;
8675 for (op
= 0; op
< i
.operands
; op
++)
8676 if (i
.types
[op
].bitfield
.class == Reg
8677 || i
.types
[op
].bitfield
.class == RegBND
8678 || i
.types
[op
].bitfield
.class == RegMask
8679 || i
.types
[op
].bitfield
.class == SReg
8680 || i
.types
[op
].bitfield
.class == RegCR
8681 || i
.types
[op
].bitfield
.class == RegDR
8682 || i
.types
[op
].bitfield
.class == RegTR
8683 || i
.types
[op
].bitfield
.class == RegSIMD
8684 || i
.types
[op
].bitfield
.class == RegMMX
)
8689 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8691 /* For instructions with VexNDS, the register-only
8692 source operand is encoded in VEX prefix. */
8693 gas_assert (mem
!= (unsigned int) ~0);
8695 if (op
> mem
|| i
.tm
.cpu_flags
.bitfield
.cpucmpccxadd
)
8698 gas_assert (op
< i
.operands
);
8702 /* Check register-only source operand when two source
8703 operands are swapped. */
8704 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8705 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8709 gas_assert (mem
== (vex_reg
+ 1)
8710 && op
< i
.operands
);
8715 gas_assert (vex_reg
< i
.operands
);
8719 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8721 /* For instructions with VexNDD, the register destination
8722 is encoded in VEX prefix. */
8723 if (i
.mem_operands
== 0)
8725 /* There is no memory operand. */
8726 gas_assert ((op
+ 2) == i
.operands
);
8731 /* There are only 2 non-immediate operands. */
8732 gas_assert (op
< i
.imm_operands
+ 2
8733 && i
.operands
== i
.imm_operands
+ 2);
8734 vex_reg
= i
.imm_operands
+ 1;
8738 gas_assert (op
< i
.operands
);
8740 if (vex_reg
!= (unsigned int) ~0)
8742 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8744 if ((type
->bitfield
.class != Reg
8745 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8746 && type
->bitfield
.class != RegSIMD
8747 && type
->bitfield
.class != RegMask
)
8750 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8753 /* Don't set OP operand twice. */
8756 /* If there is an extension opcode to put here, the
8757 register number must be put into the regmem field. */
8758 if (i
.tm
.extension_opcode
!= None
)
8760 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8761 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8762 i
.tm
.opcode_modifier
.sse2avx
);
8766 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8767 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8768 i
.tm
.opcode_modifier
.sse2avx
);
8772 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8773 must set it to 3 to indicate this is a register operand
8774 in the regmem field. */
8775 if (!i
.mem_operands
)
8779 /* Fill in i.rm.reg field with extension opcode (if any). */
8780 if (i
.tm
.extension_opcode
!= None
)
8781 i
.rm
.reg
= i
.tm
.extension_opcode
;
8787 frag_opcode_byte (unsigned char byte
)
8789 if (now_seg
!= absolute_section
)
8790 FRAG_APPEND_1_CHAR (byte
);
8792 ++abs_section_offset
;
8796 flip_code16 (unsigned int code16
)
8798 gas_assert (i
.tm
.operands
== 1);
8800 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8801 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8802 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8807 output_branch (void)
8813 relax_substateT subtype
;
8817 if (now_seg
== absolute_section
)
8819 as_bad (_("relaxable branches not supported in absolute section"));
8823 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8824 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8827 if (i
.prefix
[DATA_PREFIX
] != 0)
8831 code16
^= flip_code16(code16
);
8833 /* Pentium4 branch hints. */
8834 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8835 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8840 if (i
.prefix
[REX_PREFIX
] != 0)
8846 /* BND prefixed jump. */
8847 if (i
.prefix
[BND_PREFIX
] != 0)
8853 if (i
.prefixes
!= 0)
8854 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8856 /* It's always a symbol; End frag & setup for relax.
8857 Make sure there is enough room in this frag for the largest
8858 instruction we may generate in md_convert_frag. This is 2
8859 bytes for the opcode and room for the prefix and largest
8861 frag_grow (prefix
+ 2 + 4);
8862 /* Prefix and 1 opcode byte go in fr_fix. */
8863 p
= frag_more (prefix
+ 1);
8864 if (i
.prefix
[DATA_PREFIX
] != 0)
8865 *p
++ = DATA_PREFIX_OPCODE
;
8866 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8867 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8868 *p
++ = i
.prefix
[SEG_PREFIX
];
8869 if (i
.prefix
[BND_PREFIX
] != 0)
8870 *p
++ = BND_PREFIX_OPCODE
;
8871 if (i
.prefix
[REX_PREFIX
] != 0)
8872 *p
++ = i
.prefix
[REX_PREFIX
];
8873 *p
= i
.tm
.base_opcode
;
8875 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8876 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8877 else if (cpu_arch_flags
.bitfield
.cpui386
)
8878 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8880 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8883 sym
= i
.op
[0].disps
->X_add_symbol
;
8884 off
= i
.op
[0].disps
->X_add_number
;
8886 if (i
.op
[0].disps
->X_op
!= O_constant
8887 && i
.op
[0].disps
->X_op
!= O_symbol
)
8889 /* Handle complex expressions. */
8890 sym
= make_expr_symbol (i
.op
[0].disps
);
8894 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
8896 /* 1 possible extra opcode + 4 byte displacement go in var part.
8897 Pass reloc in fr_var. */
8898 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8902 /* Return TRUE iff PLT32 relocation should be used for branching to
8906 need_plt32_p (symbolS
*s
)
8908 /* PLT32 relocation is ELF only. */
8913 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8914 krtld support it. */
8918 /* Since there is no need to prepare for PLT branch on x86-64, we
8919 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8920 be used as a marker for 32-bit PC-relative branches. */
8927 /* Weak or undefined symbol need PLT32 relocation. */
8928 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8931 /* Non-global symbol doesn't need PLT32 relocation. */
8932 if (! S_IS_EXTERNAL (s
))
8935 /* Other global symbols need PLT32 relocation. NB: Symbol with
8936 non-default visibilities are treated as normal global symbol
8937 so that PLT32 relocation can be used as a marker for 32-bit
8938 PC-relative branches. It is useful for linker relaxation. */
8949 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8951 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8953 /* This is a loop or jecxz type instruction. */
8955 if (i
.prefix
[ADDR_PREFIX
] != 0)
8957 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8960 /* Pentium4 branch hints. */
8961 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8962 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8964 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8973 if (flag_code
== CODE_16BIT
)
8976 if (i
.prefix
[DATA_PREFIX
] != 0)
8978 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8980 code16
^= flip_code16(code16
);
8988 /* BND prefixed jump. */
8989 if (i
.prefix
[BND_PREFIX
] != 0)
8991 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8995 if (i
.prefix
[REX_PREFIX
] != 0)
8997 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9001 if (i
.prefixes
!= 0)
9002 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9004 if (now_seg
== absolute_section
)
9006 abs_section_offset
+= i
.opcode_length
+ size
;
9010 p
= frag_more (i
.opcode_length
+ size
);
9011 switch (i
.opcode_length
)
9014 *p
++ = i
.tm
.base_opcode
>> 8;
9017 *p
++ = i
.tm
.base_opcode
;
9023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9024 if (flag_code
== CODE_64BIT
&& size
== 4
9025 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9026 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9027 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9030 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9032 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9033 i
.op
[0].disps
, 1, jump_reloc
);
9035 /* All jumps handled here are signed, but don't unconditionally use a
9036 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9037 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9042 fixP
->fx_signed
= 1;
9046 if (i
.tm
.mnem_off
== MN_xbegin
)
9047 fixP
->fx_signed
= 1;
9051 if (flag_code
== CODE_64BIT
)
9052 fixP
->fx_signed
= 1;
9058 output_interseg_jump (void)
9066 if (flag_code
== CODE_16BIT
)
9070 if (i
.prefix
[DATA_PREFIX
] != 0)
9077 gas_assert (!i
.prefix
[REX_PREFIX
]);
9083 if (i
.prefixes
!= 0)
9084 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9086 if (now_seg
== absolute_section
)
9088 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9092 /* 1 opcode; 2 segment; offset */
9093 p
= frag_more (prefix
+ 1 + 2 + size
);
9095 if (i
.prefix
[DATA_PREFIX
] != 0)
9096 *p
++ = DATA_PREFIX_OPCODE
;
9098 if (i
.prefix
[REX_PREFIX
] != 0)
9099 *p
++ = i
.prefix
[REX_PREFIX
];
9101 *p
++ = i
.tm
.base_opcode
;
9102 if (i
.op
[1].imms
->X_op
== O_constant
)
9104 offsetT n
= i
.op
[1].imms
->X_add_number
;
9107 && !fits_in_unsigned_word (n
)
9108 && !fits_in_signed_word (n
))
9110 as_bad (_("16-bit jump out of range"));
9113 md_number_to_chars (p
, n
, size
);
9116 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9117 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9120 if (i
.op
[0].imms
->X_op
== O_constant
)
9121 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9123 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9124 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9132 asection
*seg
= now_seg
;
9133 subsegT subseg
= now_subseg
;
9135 unsigned int alignment
, align_size_1
;
9136 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9137 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9138 unsigned int padding
;
9140 if (!IS_ELF
|| !x86_used_note
)
9143 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9145 /* The .note.gnu.property section layout:
9147 Field Length Contents
9150 n_descsz 4 The note descriptor size
9151 n_type 4 NT_GNU_PROPERTY_TYPE_0
9153 n_desc n_descsz The program property array
9157 /* Create the .note.gnu.property section. */
9158 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9159 bfd_set_section_flags (sec
,
9166 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9177 bfd_set_section_alignment (sec
, alignment
);
9178 elf_section_type (sec
) = SHT_NOTE
;
9180 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9182 isa_1_descsz_raw
= 4 + 4 + 4;
9183 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9184 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9186 feature_2_descsz_raw
= isa_1_descsz
;
9187 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9189 feature_2_descsz_raw
+= 4 + 4 + 4;
9190 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9191 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9194 descsz
= feature_2_descsz
;
9195 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9196 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9198 /* Write n_namsz. */
9199 md_number_to_chars (p
, (valueT
) 4, 4);
9201 /* Write n_descsz. */
9202 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9205 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9208 memcpy (p
+ 4 * 3, "GNU", 4);
9210 /* Write 4-byte type. */
9211 md_number_to_chars (p
+ 4 * 4,
9212 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9214 /* Write 4-byte data size. */
9215 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9217 /* Write 4-byte data. */
9218 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9220 /* Zero out paddings. */
9221 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9223 memset (p
+ 4 * 7, 0, padding
);
9225 /* Write 4-byte type. */
9226 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9227 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9229 /* Write 4-byte data size. */
9230 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9232 /* Write 4-byte data. */
9233 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9234 (valueT
) x86_feature_2_used
, 4);
9236 /* Zero out paddings. */
9237 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9239 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9241 /* We probably can't restore the current segment, for there likely
9244 subseg_set (seg
, subseg
);
9248 x86_support_sframe_p (void)
9250 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9251 return (x86_elf_abi
== X86_64_ABI
);
9255 x86_sframe_ra_tracking_p (void)
9257 /* In AMD64, return address is always stored on the stack at a fixed offset
9258 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9259 Do not track explicitly via an SFrame Frame Row Entry. */
9264 x86_sframe_cfa_ra_offset (void)
9266 gas_assert (x86_elf_abi
== X86_64_ABI
);
9267 return (offsetT
) -8;
9271 x86_sframe_get_abi_arch (void)
9273 unsigned char sframe_abi_arch
= 0;
9275 if (x86_support_sframe_p ())
9277 gas_assert (!target_big_endian
);
9278 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9281 return sframe_abi_arch
;
9287 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9288 const char *frag_now_ptr
)
9290 unsigned int len
= 0;
9292 if (start_frag
!= frag_now
)
9294 const fragS
*fr
= start_frag
;
9299 } while (fr
&& fr
!= frag_now
);
9302 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9305 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9306 be macro-fused with conditional jumps.
9307 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9308 or is one of the following format:
9321 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9323 /* No RIP address. */
9324 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9327 /* No opcodes outside of base encoding space. */
9328 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9331 /* add, sub without add/sub m, imm. */
9332 if (i
.tm
.base_opcode
<= 5
9333 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9334 || ((i
.tm
.base_opcode
| 3) == 0x83
9335 && (i
.tm
.extension_opcode
== 0x5
9336 || i
.tm
.extension_opcode
== 0x0)))
9338 *mf_cmp_p
= mf_cmp_alu_cmp
;
9339 return !(i
.mem_operands
&& i
.imm_operands
);
9342 /* and without and m, imm. */
9343 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9344 || ((i
.tm
.base_opcode
| 3) == 0x83
9345 && i
.tm
.extension_opcode
== 0x4))
9347 *mf_cmp_p
= mf_cmp_test_and
;
9348 return !(i
.mem_operands
&& i
.imm_operands
);
9351 /* test without test m imm. */
9352 if ((i
.tm
.base_opcode
| 1) == 0x85
9353 || (i
.tm
.base_opcode
| 1) == 0xa9
9354 || ((i
.tm
.base_opcode
| 1) == 0xf7
9355 && i
.tm
.extension_opcode
== 0))
9357 *mf_cmp_p
= mf_cmp_test_and
;
9358 return !(i
.mem_operands
&& i
.imm_operands
);
9361 /* cmp without cmp m, imm. */
9362 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9363 || ((i
.tm
.base_opcode
| 3) == 0x83
9364 && (i
.tm
.extension_opcode
== 0x7)))
9366 *mf_cmp_p
= mf_cmp_alu_cmp
;
9367 return !(i
.mem_operands
&& i
.imm_operands
);
9370 /* inc, dec without inc/dec m. */
9371 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9372 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9373 || ((i
.tm
.base_opcode
| 1) == 0xff
9374 && i
.tm
.extension_opcode
<= 0x1))
9376 *mf_cmp_p
= mf_cmp_incdec
;
9377 return !i
.mem_operands
;
9383 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9386 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9388 /* NB: Don't work with COND_JUMP86 without i386. */
9389 if (!align_branch_power
9390 || now_seg
== absolute_section
9391 || !cpu_arch_flags
.bitfield
.cpui386
9392 || !(align_branch
& align_branch_fused_bit
))
9395 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9397 if (last_insn
.kind
== last_insn_other
9398 || last_insn
.seg
!= now_seg
)
9401 as_warn_where (last_insn
.file
, last_insn
.line
,
9402 _("`%s` skips -malign-branch-boundary on `%s`"),
9403 last_insn
.name
, insn_name (&i
.tm
));
9409 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9412 add_branch_prefix_frag_p (void)
9414 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9415 to PadLock instructions since they include prefixes in opcode. */
9416 if (!align_branch_power
9417 || !align_branch_prefix_size
9418 || now_seg
== absolute_section
9419 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9420 || !cpu_arch_flags
.bitfield
.cpui386
)
9423 /* Don't add prefix if it is a prefix or there is no operand in case
9424 that segment prefix is special. */
9425 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9428 if (last_insn
.kind
== last_insn_other
9429 || last_insn
.seg
!= now_seg
)
9433 as_warn_where (last_insn
.file
, last_insn
.line
,
9434 _("`%s` skips -malign-branch-boundary on `%s`"),
9435 last_insn
.name
, insn_name (&i
.tm
));
9440 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9443 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9444 enum mf_jcc_kind
*mf_jcc_p
)
9448 /* NB: Don't work with COND_JUMP86 without i386. */
9449 if (!align_branch_power
9450 || now_seg
== absolute_section
9451 || !cpu_arch_flags
.bitfield
.cpui386
9452 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9457 /* Check for jcc and direct jmp. */
9458 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9460 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9462 *branch_p
= align_branch_jmp
;
9463 add_padding
= align_branch
& align_branch_jmp_bit
;
9467 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9468 igore the lowest bit. */
9469 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9470 *branch_p
= align_branch_jcc
;
9471 if ((align_branch
& align_branch_jcc_bit
))
9475 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9478 *branch_p
= align_branch_ret
;
9479 if ((align_branch
& align_branch_ret_bit
))
9484 /* Check for indirect jmp, direct and indirect calls. */
9485 if (i
.tm
.base_opcode
== 0xe8)
9488 *branch_p
= align_branch_call
;
9489 if ((align_branch
& align_branch_call_bit
))
9492 else if (i
.tm
.base_opcode
== 0xff
9493 && (i
.tm
.extension_opcode
== 2
9494 || i
.tm
.extension_opcode
== 4))
9496 /* Indirect call and jmp. */
9497 *branch_p
= align_branch_indirect
;
9498 if ((align_branch
& align_branch_indirect_bit
))
9505 && (i
.op
[0].disps
->X_op
== O_symbol
9506 || (i
.op
[0].disps
->X_op
== O_subtract
9507 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9509 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9510 /* No padding to call to global or undefined tls_get_addr. */
9511 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9512 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9518 && last_insn
.kind
!= last_insn_other
9519 && last_insn
.seg
== now_seg
)
9522 as_warn_where (last_insn
.file
, last_insn
.line
,
9523 _("`%s` skips -malign-branch-boundary on `%s`"),
9524 last_insn
.name
, insn_name (&i
.tm
));
9534 fragS
*insn_start_frag
;
9535 offsetT insn_start_off
;
9536 fragS
*fragP
= NULL
;
9537 enum align_branch_kind branch
= align_branch_none
;
9538 /* The initializer is arbitrary just to avoid uninitialized error.
9539 it's actually either assigned in add_branch_padding_frag_p
9540 or never be used. */
9541 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9544 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9546 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9547 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9548 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9550 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9551 || i
.tm
.cpu_flags
.bitfield
.cpu287
9552 || i
.tm
.cpu_flags
.bitfield
.cpu387
9553 || i
.tm
.cpu_flags
.bitfield
.cpu687
9554 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9555 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9557 if ((i
.xstate
& xstate_mmx
)
9558 || i
.tm
.mnem_off
== MN_emms
9559 || i
.tm
.mnem_off
== MN_femms
)
9560 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9564 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9565 i
.xstate
|= xstate_zmm
;
9566 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9567 i
.xstate
|= xstate_ymm
;
9568 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9569 i
.xstate
|= xstate_xmm
;
9572 /* vzeroall / vzeroupper */
9573 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9574 i
.xstate
|= xstate_ymm
;
9576 if ((i
.xstate
& xstate_xmm
)
9577 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9578 || (i
.tm
.base_opcode
== 0xae
9579 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9580 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9581 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9582 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9583 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9585 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9586 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9587 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9588 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9589 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9590 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9591 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9592 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9593 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9594 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9595 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9596 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9597 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9598 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9600 if (x86_feature_2_used
9601 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9602 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9603 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9604 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9605 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9606 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9607 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9608 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9609 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9610 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9611 /* LAHF-SAHF insns in 64-bit mode. */
9612 || (flag_code
== CODE_64BIT
9613 && (i
.tm
.base_opcode
| 1) == 0x9f
9614 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9615 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9616 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9617 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9618 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9619 XOP, FMA4, LPW, TBM, and AMX. */
9620 || (i
.tm
.opcode_modifier
.vex
9621 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9622 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9623 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9624 && !i
.tm
.cpu_flags
.bitfield
.cpuxop
9625 && !i
.tm
.cpu_flags
.bitfield
.cpufma4
9626 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9627 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9628 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9629 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9630 || i
.tm
.cpu_flags
.bitfield
.cpufma
9631 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9632 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9633 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9634 || (x86_feature_2_used
9635 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9636 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9637 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9638 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9639 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9640 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9641 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9642 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9643 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9644 AVX512-4FMAPS, and AVX512-4VNNIW. */
9645 || (i
.tm
.opcode_modifier
.evex
9646 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9647 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9648 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
9649 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9650 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9654 /* Tie dwarf2 debug info to the address at the start of the insn.
9655 We can't do this after the insn has been output as the current
9656 frag may have been closed off. eg. by frag_var. */
9657 dwarf2_emit_insn (0);
9659 insn_start_frag
= frag_now
;
9660 insn_start_off
= frag_now_fix ();
9662 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9665 /* Branch can be 8 bytes. Leave some room for prefixes. */
9666 unsigned int max_branch_padding_size
= 14;
9668 /* Align section to boundary. */
9669 record_alignment (now_seg
, align_branch_power
);
9671 /* Make room for padding. */
9672 frag_grow (max_branch_padding_size
);
9674 /* Start of the padding. */
9679 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9680 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9683 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9684 fragP
->tc_frag_data
.branch_type
= branch
;
9685 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9688 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9689 && !pre_386_16bit_warned
)
9691 as_warn (_("use .code16 to ensure correct addressing mode"));
9692 pre_386_16bit_warned
= true;
9696 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9698 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9699 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9701 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9702 output_interseg_jump ();
9705 /* Output normal instructions here. */
9709 enum mf_cmp_kind mf_cmp
;
9712 && (i
.tm
.base_opcode
== 0xaee8
9713 || i
.tm
.base_opcode
== 0xaef0
9714 || i
.tm
.base_opcode
== 0xaef8))
9716 /* Encode lfence, mfence, and sfence as
9717 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9718 if (flag_code
== CODE_16BIT
)
9719 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9720 else if (omit_lock_prefix
)
9721 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9723 else if (now_seg
!= absolute_section
)
9725 offsetT val
= 0x240483f0ULL
;
9728 md_number_to_chars (p
, val
, 5);
9731 abs_section_offset
+= 5;
9735 /* Some processors fail on LOCK prefix. This options makes
9736 assembler ignore LOCK prefix and serves as a workaround. */
9737 if (omit_lock_prefix
)
9739 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9740 && i
.tm
.opcode_modifier
.isprefix
)
9742 i
.prefix
[LOCK_PREFIX
] = 0;
9746 /* Skip if this is a branch. */
9748 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9750 /* Make room for padding. */
9751 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9756 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9757 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9760 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9761 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9762 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9764 else if (add_branch_prefix_frag_p ())
9766 unsigned int max_prefix_size
= align_branch_prefix_size
;
9768 /* Make room for padding. */
9769 frag_grow (max_prefix_size
);
9774 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9775 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9778 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9781 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9782 don't need the explicit prefix. */
9783 if (!is_any_vex_encoding (&i
.tm
))
9785 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9794 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9795 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9799 switch (i
.opcode_length
)
9804 /* Check for pseudo prefixes. */
9805 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9807 as_bad_where (insn_start_frag
->fr_file
,
9808 insn_start_frag
->fr_line
,
9809 _("pseudo prefix without instruction"));
9819 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9820 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9821 R_X86_64_GOTTPOFF relocation so that linker can safely
9822 perform IE->LE optimization. A dummy REX_OPCODE prefix
9823 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9824 relocation for GDesc -> IE/LE optimization. */
9825 if (x86_elf_abi
== X86_64_X32_ABI
9827 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9828 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9829 && i
.prefix
[REX_PREFIX
] == 0)
9830 add_prefix (REX_OPCODE
);
9833 /* The prefix bytes. */
9834 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9836 frag_opcode_byte (*q
);
9840 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9846 frag_opcode_byte (*q
);
9849 /* There should be no other prefixes for instructions
9854 /* For EVEX instructions i.vrex should become 0 after
9855 build_evex_prefix. For VEX instructions upper 16 registers
9856 aren't available, so VREX should be 0. */
9859 /* Now the VEX prefix. */
9860 if (now_seg
!= absolute_section
)
9862 p
= frag_more (i
.vex
.length
);
9863 for (j
= 0; j
< i
.vex
.length
; j
++)
9864 p
[j
] = i
.vex
.bytes
[j
];
9867 abs_section_offset
+= i
.vex
.length
;
9870 /* Now the opcode; be careful about word order here! */
9871 j
= i
.opcode_length
;
9873 switch (i
.tm
.opcode_modifier
.opcodespace
)
9888 if (now_seg
== absolute_section
)
9889 abs_section_offset
+= j
;
9892 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9898 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9901 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9902 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9906 switch (i
.opcode_length
)
9909 /* Put out high byte first: can't use md_number_to_chars! */
9910 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9913 *p
= i
.tm
.base_opcode
& 0xff;
9922 /* Now the modrm byte and sib byte (if present). */
9923 if (i
.tm
.opcode_modifier
.modrm
)
9925 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9927 | (i
.rm
.mode
<< 6));
9928 /* If i.rm.regmem == ESP (4)
9929 && i.rm.mode != (Register mode)
9931 ==> need second modrm byte. */
9932 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9934 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9935 frag_opcode_byte ((i
.sib
.base
<< 0)
9936 | (i
.sib
.index
<< 3)
9937 | (i
.sib
.scale
<< 6));
9940 if (i
.disp_operands
)
9941 output_disp (insn_start_frag
, insn_start_off
);
9944 output_imm (insn_start_frag
, insn_start_off
);
9947 * frag_now_fix () returning plain abs_section_offset when we're in the
9948 * absolute section, and abs_section_offset not getting updated as data
9949 * gets added to the frag breaks the logic below.
9951 if (now_seg
!= absolute_section
)
9953 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9955 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9959 /* NB: Don't add prefix with GOTPC relocation since
9960 output_disp() above depends on the fixed encoding
9961 length. Can't add prefix with TLS relocation since
9962 it breaks TLS linker optimization. */
9963 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9964 /* Prefix count on the current instruction. */
9965 unsigned int count
= i
.vex
.length
;
9967 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9968 /* REX byte is encoded in VEX/EVEX prefix. */
9969 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9972 /* Count prefixes for extended opcode maps. */
9974 switch (i
.tm
.opcode_modifier
.opcodespace
)
9989 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9992 /* Set the maximum prefix size in BRANCH_PREFIX
9994 if (fragP
->tc_frag_data
.max_bytes
> max
)
9995 fragP
->tc_frag_data
.max_bytes
= max
;
9996 if (fragP
->tc_frag_data
.max_bytes
> count
)
9997 fragP
->tc_frag_data
.max_bytes
-= count
;
9999 fragP
->tc_frag_data
.max_bytes
= 0;
10003 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10005 unsigned int max_prefix_size
;
10006 if (align_branch_prefix_size
> max
)
10007 max_prefix_size
= max
;
10009 max_prefix_size
= align_branch_prefix_size
;
10010 if (max_prefix_size
> count
)
10011 fragP
->tc_frag_data
.max_prefix_length
10012 = max_prefix_size
- count
;
10015 /* Use existing segment prefix if possible. Use CS
10016 segment prefix in 64-bit mode. In 32-bit mode, use SS
10017 segment prefix with ESP/EBP base register and use DS
10018 segment prefix without ESP/EBP base register. */
10019 if (i
.prefix
[SEG_PREFIX
])
10020 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10021 else if (flag_code
== CODE_64BIT
)
10022 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10023 else if (i
.base_reg
10024 && (i
.base_reg
->reg_num
== 4
10025 || i
.base_reg
->reg_num
== 5))
10026 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10028 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10033 /* NB: Don't work with COND_JUMP86 without i386. */
10034 if (align_branch_power
10035 && now_seg
!= absolute_section
10036 && cpu_arch_flags
.bitfield
.cpui386
)
10038 /* Terminate each frag so that we can add prefix and check for
10040 frag_wane (frag_now
);
10047 pi ("" /*line*/, &i
);
10049 #endif /* DEBUG386 */
10052 /* Return the size of the displacement operand N. */
10055 disp_size (unsigned int n
)
10059 if (i
.types
[n
].bitfield
.disp64
)
10061 else if (i
.types
[n
].bitfield
.disp8
)
10063 else if (i
.types
[n
].bitfield
.disp16
)
10068 /* Return the size of the immediate operand N. */
10071 imm_size (unsigned int n
)
10074 if (i
.types
[n
].bitfield
.imm64
)
10076 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10078 else if (i
.types
[n
].bitfield
.imm16
)
10084 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10089 for (n
= 0; n
< i
.operands
; n
++)
10091 if (operand_type_check (i
.types
[n
], disp
))
10093 int size
= disp_size (n
);
10095 if (now_seg
== absolute_section
)
10096 abs_section_offset
+= size
;
10097 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10099 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10101 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10103 p
= frag_more (size
);
10104 md_number_to_chars (p
, val
, size
);
10108 enum bfd_reloc_code_real reloc_type
;
10109 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10110 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10111 && (!want_disp32 (&i
.tm
)
10112 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10113 && !i
.types
[n
].bitfield
.baseindex
)))
10117 /* We can't have 8 bit displacement here. */
10118 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10120 /* The PC relative address is computed relative
10121 to the instruction boundary, so in case immediate
10122 fields follows, we need to adjust the value. */
10123 if (pcrel
&& i
.imm_operands
)
10128 for (n1
= 0; n1
< i
.operands
; n1
++)
10129 if (operand_type_check (i
.types
[n1
], imm
))
10131 /* Only one immediate is allowed for PC
10132 relative address. */
10133 gas_assert (sz
== 0);
10134 sz
= imm_size (n1
);
10135 i
.op
[n
].disps
->X_add_number
-= sz
;
10137 /* We should find the immediate. */
10138 gas_assert (sz
!= 0);
10141 p
= frag_more (size
);
10142 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10144 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10145 && (((reloc_type
== BFD_RELOC_32
10146 || reloc_type
== BFD_RELOC_X86_64_32S
10147 || (reloc_type
== BFD_RELOC_64
10149 && (i
.op
[n
].disps
->X_op
== O_symbol
10150 || (i
.op
[n
].disps
->X_op
== O_add
10151 && ((symbol_get_value_expression
10152 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10154 || reloc_type
== BFD_RELOC_32_PCREL
))
10158 reloc_type
= BFD_RELOC_386_GOTPC
;
10159 i
.has_gotpc_tls_reloc
= true;
10160 i
.op
[n
].disps
->X_add_number
+=
10161 encoding_length (insn_start_frag
, insn_start_off
, p
);
10163 else if (reloc_type
== BFD_RELOC_64
)
10164 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10166 /* Don't do the adjustment for x86-64, as there
10167 the pcrel addressing is relative to the _next_
10168 insn, and that is taken care of in other code. */
10169 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10171 else if (align_branch_power
)
10173 switch (reloc_type
)
10175 case BFD_RELOC_386_TLS_GD
:
10176 case BFD_RELOC_386_TLS_LDM
:
10177 case BFD_RELOC_386_TLS_IE
:
10178 case BFD_RELOC_386_TLS_IE_32
:
10179 case BFD_RELOC_386_TLS_GOTIE
:
10180 case BFD_RELOC_386_TLS_GOTDESC
:
10181 case BFD_RELOC_386_TLS_DESC_CALL
:
10182 case BFD_RELOC_X86_64_TLSGD
:
10183 case BFD_RELOC_X86_64_TLSLD
:
10184 case BFD_RELOC_X86_64_GOTTPOFF
:
10185 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10186 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10187 i
.has_gotpc_tls_reloc
= true;
10192 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10193 size
, i
.op
[n
].disps
, pcrel
,
10196 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10197 && !i
.prefix
[ADDR_PREFIX
])
10198 fixP
->fx_signed
= 1;
10200 /* Check for "call/jmp *mem", "mov mem, %reg",
10201 "test %reg, mem" and "binop mem, %reg" where binop
10202 is one of adc, add, and, cmp, or, sbb, sub, xor
10203 instructions without data prefix. Always generate
10204 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10205 if (i
.prefix
[DATA_PREFIX
] == 0
10206 && (generate_relax_relocations
10209 && i
.rm
.regmem
== 5))
10211 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10212 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10213 && ((i
.operands
== 1
10214 && i
.tm
.base_opcode
== 0xff
10215 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10216 || (i
.operands
== 2
10217 && (i
.tm
.base_opcode
== 0x8b
10218 || i
.tm
.base_opcode
== 0x85
10219 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10223 fixP
->fx_tcbit
= i
.rex
!= 0;
10225 && (i
.base_reg
->reg_num
== RegIP
))
10226 fixP
->fx_tcbit2
= 1;
10229 fixP
->fx_tcbit2
= 1;
10237 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10242 for (n
= 0; n
< i
.operands
; n
++)
10244 if (operand_type_check (i
.types
[n
], imm
))
10246 int size
= imm_size (n
);
10248 if (now_seg
== absolute_section
)
10249 abs_section_offset
+= size
;
10250 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10254 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10256 p
= frag_more (size
);
10257 md_number_to_chars (p
, val
, size
);
10261 /* Not absolute_section.
10262 Need a 32-bit fixup (don't support 8bit
10263 non-absolute imms). Try to support other
10265 enum bfd_reloc_code_real reloc_type
;
10268 if (i
.types
[n
].bitfield
.imm32s
10269 && (i
.suffix
== QWORD_MNEM_SUFFIX
10270 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10275 p
= frag_more (size
);
10276 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10278 /* This is tough to explain. We end up with this one if we
10279 * have operands that look like
10280 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10281 * obtain the absolute address of the GOT, and it is strongly
10282 * preferable from a performance point of view to avoid using
10283 * a runtime relocation for this. The actual sequence of
10284 * instructions often look something like:
10289 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10291 * The call and pop essentially return the absolute address
10292 * of the label .L66 and store it in %ebx. The linker itself
10293 * will ultimately change the first operand of the addl so
10294 * that %ebx points to the GOT, but to keep things simple, the
10295 * .o file must have this operand set so that it generates not
10296 * the absolute address of .L66, but the absolute address of
10297 * itself. This allows the linker itself simply treat a GOTPC
10298 * relocation as asking for a pcrel offset to the GOT to be
10299 * added in, and the addend of the relocation is stored in the
10300 * operand field for the instruction itself.
10302 * Our job here is to fix the operand so that it would add
10303 * the correct offset so that %ebx would point to itself. The
10304 * thing that is tricky is that .-.L66 will point to the
10305 * beginning of the instruction, so we need to further modify
10306 * the operand so that it will point to itself. There are
10307 * other cases where you have something like:
10309 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10311 * and here no correction would be required. Internally in
10312 * the assembler we treat operands of this form as not being
10313 * pcrel since the '.' is explicitly mentioned, and I wonder
10314 * whether it would simplify matters to do it this way. Who
10315 * knows. In earlier versions of the PIC patches, the
10316 * pcrel_adjust field was used to store the correction, but
10317 * since the expression is not pcrel, I felt it would be
10318 * confusing to do it this way. */
10320 if ((reloc_type
== BFD_RELOC_32
10321 || reloc_type
== BFD_RELOC_X86_64_32S
10322 || reloc_type
== BFD_RELOC_64
)
10324 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10325 && (i
.op
[n
].imms
->X_op
== O_symbol
10326 || (i
.op
[n
].imms
->X_op
== O_add
10327 && ((symbol_get_value_expression
10328 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10332 reloc_type
= BFD_RELOC_386_GOTPC
;
10333 else if (size
== 4)
10334 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10335 else if (size
== 8)
10336 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10337 i
.has_gotpc_tls_reloc
= true;
10338 i
.op
[n
].imms
->X_add_number
+=
10339 encoding_length (insn_start_frag
, insn_start_off
, p
);
10341 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10342 i
.op
[n
].imms
, 0, reloc_type
);
10348 /* x86_cons_fix_new is called via the expression parsing code when a
10349 reloc is needed. We use this hook to get the correct .got reloc. */
10350 static int cons_sign
= -1;
10353 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10354 expressionS
*exp
, bfd_reloc_code_real_type r
)
10356 r
= reloc (len
, 0, cons_sign
, r
);
10359 if (exp
->X_op
== O_secrel
)
10361 exp
->X_op
= O_symbol
;
10362 r
= BFD_RELOC_32_SECREL
;
10364 else if (exp
->X_op
== O_secidx
)
10365 r
= BFD_RELOC_16_SECIDX
;
10368 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10371 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10372 purpose of the `.dc.a' internal pseudo-op. */
10375 x86_address_bytes (void)
10377 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10379 return stdoutput
->arch_info
->bits_per_address
/ 8;
10382 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10383 || defined (LEX_AT)) && !defined (TE_PE)
10384 # define lex_got(reloc, adjust, types) NULL
10386 /* Parse operands of the form
10387 <symbol>@GOTOFF+<nnn>
10388 and similar .plt or .got references.
10390 If we find one, set up the correct relocation in RELOC and copy the
10391 input string, minus the `@GOTOFF' into a malloc'd buffer for
10392 parsing by the calling routine. Return this buffer, and if ADJUST
10393 is non-null set it to the length of the string we removed from the
10394 input line. Otherwise return NULL. */
10396 lex_got (enum bfd_reloc_code_real
*rel
,
10398 i386_operand_type
*types
)
10400 /* Some of the relocations depend on the size of what field is to
10401 be relocated. But in our callers i386_immediate and i386_displacement
10402 we don't yet know the operand size (this will be set by insn
10403 matching). Hence we record the word32 relocation here,
10404 and adjust the reloc according to the real size in reloc(). */
10405 static const struct
10409 const enum bfd_reloc_code_real rel
[2];
10410 const i386_operand_type types64
;
10411 bool need_GOT_symbol
;
10416 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10417 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10418 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10419 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10420 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10421 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10422 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10423 { .imm64 = 1, .disp64 = 1 } }
10426 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10427 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10428 BFD_RELOC_SIZE32
},
10429 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10431 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10432 BFD_RELOC_X86_64_PLTOFF64
},
10433 { .bitfield
= { .imm64
= 1 } }, true },
10434 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10435 BFD_RELOC_X86_64_PLT32
},
10436 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10437 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10438 BFD_RELOC_X86_64_GOTPLT64
},
10439 OPERAND_TYPE_IMM64_DISP64
, true },
10440 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10441 BFD_RELOC_X86_64_GOTOFF64
},
10442 OPERAND_TYPE_IMM64_DISP64
, true },
10443 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10444 BFD_RELOC_X86_64_GOTPCREL
},
10445 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10446 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10447 BFD_RELOC_X86_64_TLSGD
},
10448 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10449 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10450 _dummy_first_bfd_reloc_code_real
},
10451 OPERAND_TYPE_NONE
, true },
10452 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10453 BFD_RELOC_X86_64_TLSLD
},
10454 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10455 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10456 BFD_RELOC_X86_64_GOTTPOFF
},
10457 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10458 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10459 BFD_RELOC_X86_64_TPOFF32
},
10460 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10461 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10462 _dummy_first_bfd_reloc_code_real
},
10463 OPERAND_TYPE_NONE
, true },
10464 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10465 BFD_RELOC_X86_64_DTPOFF32
},
10466 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10467 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10468 _dummy_first_bfd_reloc_code_real
},
10469 OPERAND_TYPE_NONE
, true },
10470 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10471 _dummy_first_bfd_reloc_code_real
},
10472 OPERAND_TYPE_NONE
, true },
10473 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10474 BFD_RELOC_X86_64_GOT32
},
10475 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10476 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10477 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10478 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10479 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10480 BFD_RELOC_X86_64_TLSDESC_CALL
},
10481 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10483 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10484 BFD_RELOC_32_SECREL
},
10485 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10488 #undef OPERAND_TYPE_IMM32_32S_DISP32
10489 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10490 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10491 #undef OPERAND_TYPE_IMM64_DISP64
10497 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10502 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10503 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10506 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10508 int len
= gotrel
[j
].len
;
10509 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10511 if (gotrel
[j
].rel
[object_64bit
] != 0)
10514 char *tmpbuf
, *past_reloc
;
10516 *rel
= gotrel
[j
].rel
[object_64bit
];
10520 if (flag_code
!= CODE_64BIT
)
10522 types
->bitfield
.imm32
= 1;
10523 types
->bitfield
.disp32
= 1;
10526 *types
= gotrel
[j
].types64
;
10529 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10530 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10532 /* The length of the first part of our input line. */
10533 first
= cp
- input_line_pointer
;
10535 /* The second part goes from after the reloc token until
10536 (and including) an end_of_line char or comma. */
10537 past_reloc
= cp
+ 1 + len
;
10539 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10541 second
= cp
+ 1 - past_reloc
;
10543 /* Allocate and copy string. The trailing NUL shouldn't
10544 be necessary, but be safe. */
10545 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10546 memcpy (tmpbuf
, input_line_pointer
, first
);
10547 if (second
!= 0 && *past_reloc
!= ' ')
10548 /* Replace the relocation token with ' ', so that
10549 errors like foo@GOTOFF1 will be detected. */
10550 tmpbuf
[first
++] = ' ';
10552 /* Increment length by 1 if the relocation token is
10557 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10558 tmpbuf
[first
+ second
] = '\0';
10562 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10563 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10568 /* Might be a symbol version string. Don't as_bad here. */
10573 bfd_reloc_code_real_type
10574 x86_cons (expressionS
*exp
, int size
)
10576 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10578 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10579 && !defined (LEX_AT)) \
10581 intel_syntax
= -intel_syntax
;
10584 if (size
== 4 || (object_64bit
&& size
== 8))
10586 /* Handle @GOTOFF and the like in an expression. */
10588 char *gotfree_input_line
;
10591 save
= input_line_pointer
;
10592 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10593 if (gotfree_input_line
)
10594 input_line_pointer
= gotfree_input_line
;
10598 if (gotfree_input_line
)
10600 /* expression () has merrily parsed up to the end of line,
10601 or a comma - in the wrong buffer. Transfer how far
10602 input_line_pointer has moved to the right buffer. */
10603 input_line_pointer
= (save
10604 + (input_line_pointer
- gotfree_input_line
)
10606 free (gotfree_input_line
);
10607 if (exp
->X_op
== O_constant
10608 || exp
->X_op
== O_absent
10609 || exp
->X_op
== O_illegal
10610 || exp
->X_op
== O_register
10611 || exp
->X_op
== O_big
)
10613 char c
= *input_line_pointer
;
10614 *input_line_pointer
= 0;
10615 as_bad (_("missing or invalid expression `%s'"), save
);
10616 *input_line_pointer
= c
;
10618 else if ((got_reloc
== BFD_RELOC_386_PLT32
10619 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10620 && exp
->X_op
!= O_symbol
)
10622 char c
= *input_line_pointer
;
10623 *input_line_pointer
= 0;
10624 as_bad (_("invalid PLT expression `%s'"), save
);
10625 *input_line_pointer
= c
;
10632 intel_syntax
= -intel_syntax
;
10635 i386_intel_simplify (exp
);
10640 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10641 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10642 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10648 signed_cons (int size
)
10658 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10665 if (exp
.X_op
== O_symbol
)
10666 exp
.X_op
= O_secrel
;
10668 emit_expr (&exp
, 4);
10670 while (*input_line_pointer
++ == ',');
10672 input_line_pointer
--;
10673 demand_empty_rest_of_line ();
10677 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
10684 if (exp
.X_op
== O_symbol
)
10685 exp
.X_op
= O_secidx
;
10687 emit_expr (&exp
, 2);
10689 while (*input_line_pointer
++ == ',');
10691 input_line_pointer
--;
10692 demand_empty_rest_of_line ();
10696 /* Handle Rounding Control / SAE specifiers. */
10699 RC_SAE_specifier (const char *pstr
)
10703 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10705 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10707 if (i
.rounding
.type
!= rc_none
)
10709 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
10713 i
.rounding
.type
= RC_NamesTable
[j
].type
;
10715 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
10722 /* Handle Vector operations. */
10725 check_VecOperations (char *op_string
)
10727 const reg_entry
*mask
;
10734 if (*op_string
== '{')
10738 /* Check broadcasts. */
10739 if (startswith (op_string
, "1to"))
10741 unsigned int bcst_type
;
10743 if (i
.broadcast
.type
)
10744 goto duplicated_vec_op
;
10747 if (*op_string
== '8')
10749 else if (*op_string
== '4')
10751 else if (*op_string
== '2')
10753 else if (*op_string
== '1'
10754 && *(op_string
+1) == '6')
10759 else if (*op_string
== '3'
10760 && *(op_string
+1) == '2')
10767 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10772 i
.broadcast
.type
= bcst_type
;
10773 i
.broadcast
.operand
= this_operand
;
10775 /* Check masking operation. */
10776 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10778 if (mask
== &bad_reg
)
10781 /* k0 can't be used for write mask. */
10782 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10784 as_bad (_("`%s%s' can't be used for write mask"),
10785 register_prefix
, mask
->reg_name
);
10792 i
.mask
.operand
= this_operand
;
10794 else if (i
.mask
.reg
->reg_num
)
10795 goto duplicated_vec_op
;
10800 /* Only "{z}" is allowed here. No need to check
10801 zeroing mask explicitly. */
10802 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10804 as_bad (_("invalid write mask `%s'"), saved
);
10809 op_string
= end_op
;
10811 /* Check zeroing-flag for masking operation. */
10812 else if (*op_string
== 'z')
10816 i
.mask
.reg
= reg_k0
;
10817 i
.mask
.zeroing
= 1;
10818 i
.mask
.operand
= this_operand
;
10822 if (i
.mask
.zeroing
)
10825 as_bad (_("duplicated `%s'"), saved
);
10829 i
.mask
.zeroing
= 1;
10831 /* Only "{%k}" is allowed here. No need to check mask
10832 register explicitly. */
10833 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10835 as_bad (_("invalid zeroing-masking `%s'"),
10843 else if (intel_syntax
10844 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
10845 i
.rounding
.modifier
= true;
10847 goto unknown_vec_op
;
10849 if (*op_string
!= '}')
10851 as_bad (_("missing `}' in `%s'"), saved
);
10856 /* Strip whitespace since the addition of pseudo prefixes
10857 changed how the scrubber treats '{'. */
10858 if (is_space_char (*op_string
))
10864 /* We don't know this one. */
10865 as_bad (_("unknown vector operation: `%s'"), saved
);
10869 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10871 as_bad (_("zeroing-masking only allowed with write mask"));
10879 i386_immediate (char *imm_start
)
10881 char *save_input_line_pointer
;
10882 char *gotfree_input_line
;
10885 i386_operand_type types
;
10887 operand_type_set (&types
, ~0);
10889 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10891 as_bad (_("at most %d immediate operands are allowed"),
10892 MAX_IMMEDIATE_OPERANDS
);
10896 exp
= &im_expressions
[i
.imm_operands
++];
10897 i
.op
[this_operand
].imms
= exp
;
10899 if (is_space_char (*imm_start
))
10902 save_input_line_pointer
= input_line_pointer
;
10903 input_line_pointer
= imm_start
;
10905 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10906 if (gotfree_input_line
)
10907 input_line_pointer
= gotfree_input_line
;
10909 exp_seg
= expression (exp
);
10911 SKIP_WHITESPACE ();
10912 if (*input_line_pointer
)
10913 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10915 input_line_pointer
= save_input_line_pointer
;
10916 if (gotfree_input_line
)
10918 free (gotfree_input_line
);
10920 if (exp
->X_op
== O_constant
)
10921 exp
->X_op
= O_illegal
;
10924 if (exp_seg
== reg_section
)
10926 as_bad (_("illegal immediate register operand %s"), imm_start
);
10930 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10934 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10935 i386_operand_type types
, const char *imm_start
)
10937 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10940 as_bad (_("missing or invalid immediate expression `%s'"),
10944 else if (exp
->X_op
== O_constant
)
10946 /* Size it properly later. */
10947 i
.types
[this_operand
].bitfield
.imm64
= 1;
10949 /* If not 64bit, sign/zero extend val, to account for wraparound
10951 if (flag_code
!= CODE_64BIT
)
10952 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10954 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10955 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10956 && exp_seg
!= absolute_section
10957 && exp_seg
!= text_section
10958 && exp_seg
!= data_section
10959 && exp_seg
!= bss_section
10960 && exp_seg
!= undefined_section
10961 && !bfd_is_com_section (exp_seg
))
10963 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10969 /* This is an address. The size of the address will be
10970 determined later, depending on destination register,
10971 suffix, or the default for the section. */
10972 i
.types
[this_operand
].bitfield
.imm8
= 1;
10973 i
.types
[this_operand
].bitfield
.imm16
= 1;
10974 i
.types
[this_operand
].bitfield
.imm32
= 1;
10975 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10976 i
.types
[this_operand
].bitfield
.imm64
= 1;
10977 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10985 i386_scale (char *scale
)
10988 char *save
= input_line_pointer
;
10990 input_line_pointer
= scale
;
10991 val
= get_absolute_expression ();
10996 i
.log2_scale_factor
= 0;
10999 i
.log2_scale_factor
= 1;
11002 i
.log2_scale_factor
= 2;
11005 i
.log2_scale_factor
= 3;
11009 char sep
= *input_line_pointer
;
11011 *input_line_pointer
= '\0';
11012 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
11014 *input_line_pointer
= sep
;
11015 input_line_pointer
= save
;
11019 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
11021 as_warn (_("scale factor of %d without an index register"),
11022 1 << i
.log2_scale_factor
);
11023 i
.log2_scale_factor
= 0;
11025 scale
= input_line_pointer
;
11026 input_line_pointer
= save
;
11031 i386_displacement (char *disp_start
, char *disp_end
)
11035 char *save_input_line_pointer
;
11036 char *gotfree_input_line
;
11038 i386_operand_type bigdisp
, types
= anydisp
;
11041 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
11043 as_bad (_("at most %d displacement operands are allowed"),
11044 MAX_MEMORY_OPERANDS
);
11048 operand_type_set (&bigdisp
, 0);
11050 || i
.types
[this_operand
].bitfield
.baseindex
11051 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
11052 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
11054 i386_addressing_mode ();
11055 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
11056 if (flag_code
== CODE_64BIT
)
11058 bigdisp
.bitfield
.disp32
= 1;
11060 bigdisp
.bitfield
.disp64
= 1;
11062 else if ((flag_code
== CODE_16BIT
) ^ override
)
11063 bigdisp
.bitfield
.disp16
= 1;
11065 bigdisp
.bitfield
.disp32
= 1;
11069 /* For PC-relative branches, the width of the displacement may be
11070 dependent upon data size, but is never dependent upon address size.
11071 Also make sure to not unintentionally match against a non-PC-relative
11072 branch template. */
11073 static templates aux_templates
;
11074 const insn_template
*t
= current_templates
->start
;
11075 bool has_intel64
= false;
11077 aux_templates
.start
= t
;
11078 while (++t
< current_templates
->end
)
11080 if (t
->opcode_modifier
.jump
11081 != current_templates
->start
->opcode_modifier
.jump
)
11083 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
11084 has_intel64
= true;
11086 if (t
< current_templates
->end
)
11088 aux_templates
.end
= t
;
11089 current_templates
= &aux_templates
;
11092 override
= (i
.prefix
[DATA_PREFIX
] != 0);
11093 if (flag_code
== CODE_64BIT
)
11095 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
11096 && (!intel64
|| !has_intel64
))
11097 bigdisp
.bitfield
.disp16
= 1;
11099 bigdisp
.bitfield
.disp32
= 1;
11104 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
11106 : LONG_MNEM_SUFFIX
));
11107 bigdisp
.bitfield
.disp32
= 1;
11108 if ((flag_code
== CODE_16BIT
) ^ override
)
11110 bigdisp
.bitfield
.disp32
= 0;
11111 bigdisp
.bitfield
.disp16
= 1;
11115 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11118 exp
= &disp_expressions
[i
.disp_operands
];
11119 i
.op
[this_operand
].disps
= exp
;
11121 save_input_line_pointer
= input_line_pointer
;
11122 input_line_pointer
= disp_start
;
11123 END_STRING_AND_SAVE (disp_end
);
11125 #ifndef GCC_ASM_O_HACK
11126 #define GCC_ASM_O_HACK 0
11129 END_STRING_AND_SAVE (disp_end
+ 1);
11130 if (i
.types
[this_operand
].bitfield
.baseIndex
11131 && displacement_string_end
[-1] == '+')
11133 /* This hack is to avoid a warning when using the "o"
11134 constraint within gcc asm statements.
11137 #define _set_tssldt_desc(n,addr,limit,type) \
11138 __asm__ __volatile__ ( \
11139 "movw %w2,%0\n\t" \
11140 "movw %w1,2+%0\n\t" \
11141 "rorl $16,%1\n\t" \
11142 "movb %b1,4+%0\n\t" \
11143 "movb %4,5+%0\n\t" \
11144 "movb $0,6+%0\n\t" \
11145 "movb %h1,7+%0\n\t" \
11147 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
11149 This works great except that the output assembler ends
11150 up looking a bit weird if it turns out that there is
11151 no offset. You end up producing code that looks like:
11164 So here we provide the missing zero. */
11166 *displacement_string_end
= '0';
11169 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11170 if (gotfree_input_line
)
11171 input_line_pointer
= gotfree_input_line
;
11173 exp_seg
= expression (exp
);
11175 SKIP_WHITESPACE ();
11176 if (*input_line_pointer
)
11177 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11179 RESTORE_END_STRING (disp_end
+ 1);
11181 input_line_pointer
= save_input_line_pointer
;
11182 if (gotfree_input_line
)
11184 free (gotfree_input_line
);
11186 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
11187 exp
->X_op
= O_illegal
;
11190 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
11192 RESTORE_END_STRING (disp_end
);
11198 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11199 i386_operand_type types
, const char *disp_start
)
11203 /* We do this to make sure that the section symbol is in
11204 the symbol table. We will ultimately change the relocation
11205 to be relative to the beginning of the section. */
11206 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
11207 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
11208 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11210 if (exp
->X_op
!= O_symbol
)
11213 if (S_IS_LOCAL (exp
->X_add_symbol
)
11214 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
11215 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
11216 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
11217 exp
->X_op
= O_subtract
;
11218 exp
->X_op_symbol
= GOT_symbol
;
11219 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
11220 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
11221 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11222 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11224 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11227 else if (exp
->X_op
== O_absent
11228 || exp
->X_op
== O_illegal
11229 || exp
->X_op
== O_big
)
11232 as_bad (_("missing or invalid displacement expression `%s'"),
11237 else if (exp
->X_op
== O_constant
)
11239 /* Sizing gets taken care of by optimize_disp().
11241 If not 64bit, sign/zero extend val, to account for wraparound
11243 if (flag_code
!= CODE_64BIT
)
11244 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11247 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11248 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11249 && exp_seg
!= absolute_section
11250 && exp_seg
!= text_section
11251 && exp_seg
!= data_section
11252 && exp_seg
!= bss_section
11253 && exp_seg
!= undefined_section
11254 && !bfd_is_com_section (exp_seg
))
11256 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11261 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
11262 i
.types
[this_operand
].bitfield
.disp8
= 1;
11264 /* Check if this is a displacement only operand. */
11265 if (!i
.types
[this_operand
].bitfield
.baseindex
)
11266 i
.types
[this_operand
] =
11267 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
11268 operand_type_and (i
.types
[this_operand
], types
));
11273 /* Return the active addressing mode, taking address override and
11274 registers forming the address into consideration. Update the
11275 address override prefix if necessary. */
11277 static enum flag_code
11278 i386_addressing_mode (void)
11280 enum flag_code addr_mode
;
11282 if (i
.prefix
[ADDR_PREFIX
])
11283 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11284 else if (flag_code
== CODE_16BIT
11285 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11286 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11287 from md_assemble() by "is not a valid base/index expression"
11288 when there is a base and/or index. */
11289 && !i
.types
[this_operand
].bitfield
.baseindex
)
11291 /* MPX insn memory operands with neither base nor index must be forced
11292 to use 32-bit addressing in 16-bit mode. */
11293 addr_mode
= CODE_32BIT
;
11294 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11296 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11297 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11301 addr_mode
= flag_code
;
11303 #if INFER_ADDR_PREFIX
11304 if (i
.mem_operands
== 0)
11306 /* Infer address prefix from the first memory operand. */
11307 const reg_entry
*addr_reg
= i
.base_reg
;
11309 if (addr_reg
== NULL
)
11310 addr_reg
= i
.index_reg
;
11314 if (addr_reg
->reg_type
.bitfield
.dword
)
11315 addr_mode
= CODE_32BIT
;
11316 else if (flag_code
!= CODE_64BIT
11317 && addr_reg
->reg_type
.bitfield
.word
)
11318 addr_mode
= CODE_16BIT
;
11320 if (addr_mode
!= flag_code
)
11322 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11324 /* Change the size of any displacement too. At most one
11325 of Disp16 or Disp32 is set.
11326 FIXME. There doesn't seem to be any real need for
11327 separate Disp16 and Disp32 flags. The same goes for
11328 Imm16 and Imm32. Removing them would probably clean
11329 up the code quite a lot. */
11330 if (flag_code
!= CODE_64BIT
11331 && (i
.types
[this_operand
].bitfield
.disp16
11332 || i
.types
[this_operand
].bitfield
.disp32
))
11334 static const i386_operand_type disp16_32
= {
11335 .bitfield
= { .disp16
= 1, .disp32
= 1 }
11338 i
.types
[this_operand
]
11339 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11350 /* Make sure the memory operand we've been dealt is valid.
11351 Return 1 on success, 0 on a failure. */
11354 i386_index_check (const char *operand_string
)
11356 const char *kind
= "base/index";
11357 enum flag_code addr_mode
= i386_addressing_mode ();
11358 const insn_template
*t
= current_templates
->end
- 1;
11360 if (t
->opcode_modifier
.isstring
)
11362 /* Memory operands of string insns are special in that they only allow
11363 a single register (rDI, rSI, or rBX) as their memory address. */
11364 const reg_entry
*expected_reg
;
11365 static const char *di_si
[][2] =
11371 static const char *bx
[] = { "ebx", "bx", "rbx" };
11373 kind
= "string address";
11375 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11377 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
11380 if (!t
->operand_types
[0].bitfield
.baseindex
11381 || ((!i
.mem_operands
!= !intel_syntax
)
11382 && t
->operand_types
[1].bitfield
.baseindex
))
11385 = (const reg_entry
*) str_hash_find (reg_hash
,
11386 di_si
[addr_mode
][op
== es_op
]);
11390 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11392 if (i
.base_reg
!= expected_reg
11394 || operand_type_check (i
.types
[this_operand
], disp
))
11396 /* The second memory operand must have the same size as
11400 && !((addr_mode
== CODE_64BIT
11401 && i
.base_reg
->reg_type
.bitfield
.qword
)
11402 || (addr_mode
== CODE_32BIT
11403 ? i
.base_reg
->reg_type
.bitfield
.dword
11404 : i
.base_reg
->reg_type
.bitfield
.word
)))
11407 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11409 intel_syntax
? '[' : '(',
11411 expected_reg
->reg_name
,
11412 intel_syntax
? ']' : ')');
11419 as_bad (_("`%s' is not a valid %s expression"),
11420 operand_string
, kind
);
11425 t
= current_templates
->start
;
11427 if (addr_mode
!= CODE_16BIT
)
11429 /* 32-bit/64-bit checks. */
11430 if (i
.disp_encoding
== disp_encoding_16bit
)
11433 as_bad (_("invalid `%s' prefix"),
11434 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11439 && ((addr_mode
== CODE_64BIT
11440 ? !i
.base_reg
->reg_type
.bitfield
.qword
11441 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11442 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11443 || i
.base_reg
->reg_num
== RegIZ
))
11445 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11446 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11447 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11448 && ((addr_mode
== CODE_64BIT
11449 ? !i
.index_reg
->reg_type
.bitfield
.qword
11450 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11451 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11454 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11455 if (t
->mnem_off
== MN_bndmk
11456 || t
->mnem_off
== MN_bndldx
11457 || t
->mnem_off
== MN_bndstx
11458 || t
->opcode_modifier
.sib
== SIBMEM
)
11460 /* They cannot use RIP-relative addressing. */
11461 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11463 as_bad (_("`%s' cannot be used here"), operand_string
);
11467 /* bndldx and bndstx ignore their scale factor. */
11468 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
11469 && i
.log2_scale_factor
)
11470 as_warn (_("register scaling is being ignored here"));
11475 /* 16-bit checks. */
11476 if (i
.disp_encoding
== disp_encoding_32bit
)
11480 && (!i
.base_reg
->reg_type
.bitfield
.word
11481 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11483 && (!i
.index_reg
->reg_type
.bitfield
.word
11484 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11486 && i
.base_reg
->reg_num
< 6
11487 && i
.index_reg
->reg_num
>= 6
11488 && i
.log2_scale_factor
== 0))))
11495 /* Handle vector immediates. */
11498 RC_SAE_immediate (const char *imm_start
)
11500 const char *pstr
= imm_start
;
11505 pstr
= RC_SAE_specifier (pstr
+ 1);
11509 if (*pstr
++ != '}')
11511 as_bad (_("Missing '}': '%s'"), imm_start
);
11514 /* RC/SAE immediate string should contain nothing more. */;
11517 as_bad (_("Junk after '}': '%s'"), imm_start
);
11521 /* Internally this doesn't count as an operand. */
11527 static INLINE
bool starts_memory_operand (char c
)
11530 || is_identifier_char (c
)
11531 || strchr ("([\"+-!~", c
);
11534 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11538 i386_att_operand (char *operand_string
)
11540 const reg_entry
*r
;
11542 char *op_string
= operand_string
;
11544 if (is_space_char (*op_string
))
11547 /* We check for an absolute prefix (differentiating,
11548 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11549 if (*op_string
== ABSOLUTE_PREFIX
)
11552 if (is_space_char (*op_string
))
11554 i
.jumpabsolute
= true;
11557 /* Check if operand is a register. */
11558 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11560 i386_operand_type temp
;
11565 /* Check for a segment override by searching for ':' after a
11566 segment register. */
11567 op_string
= end_op
;
11568 if (is_space_char (*op_string
))
11570 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11572 i
.seg
[i
.mem_operands
] = r
;
11574 /* Skip the ':' and whitespace. */
11576 if (is_space_char (*op_string
))
11579 /* Handle case of %es:*foo. */
11580 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
)
11583 if (is_space_char (*op_string
))
11585 i
.jumpabsolute
= true;
11588 if (!starts_memory_operand (*op_string
))
11590 as_bad (_("bad memory operand `%s'"), op_string
);
11593 goto do_memory_reference
;
11596 /* Handle vector operations. */
11597 if (*op_string
== '{')
11599 op_string
= check_VecOperations (op_string
);
11600 if (op_string
== NULL
)
11606 as_bad (_("junk `%s' after register"), op_string
);
11609 temp
= r
->reg_type
;
11610 temp
.bitfield
.baseindex
= 0;
11611 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11613 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11614 i
.op
[this_operand
].regs
= r
;
11617 /* A GPR may follow an RC or SAE immediate only if a (vector) register
11618 operand was also present earlier on. */
11619 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
11620 && i
.reg_operands
== 1)
11624 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
11625 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
11627 as_bad (_("`%s': misplaced `{%s}'"),
11628 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
11632 else if (*op_string
== REGISTER_PREFIX
)
11634 as_bad (_("bad register name `%s'"), op_string
);
11637 else if (*op_string
== IMMEDIATE_PREFIX
)
11640 if (i
.jumpabsolute
)
11642 as_bad (_("immediate operand illegal with absolute jump"));
11645 if (!i386_immediate (op_string
))
11647 if (i
.rounding
.type
!= rc_none
)
11649 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
11650 insn_name (current_templates
->start
));
11654 else if (RC_SAE_immediate (operand_string
))
11656 /* If it is a RC or SAE immediate, do the necessary placement check:
11657 Only another immediate or a GPR may precede it. */
11658 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
11659 || (i
.reg_operands
== 1
11660 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
11662 as_bad (_("`%s': misplaced `%s'"),
11663 insn_name (current_templates
->start
), operand_string
);
11667 else if (starts_memory_operand (*op_string
))
11669 /* This is a memory reference of some sort. */
11672 /* Start and end of displacement string expression (if found). */
11673 char *displacement_string_start
;
11674 char *displacement_string_end
;
11676 do_memory_reference
:
11677 /* Check for base index form. We detect the base index form by
11678 looking for an ')' at the end of the operand, searching
11679 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11681 base_string
= op_string
+ strlen (op_string
);
11683 /* Handle vector operations. */
11685 if (is_space_char (*base_string
))
11688 if (*base_string
== '}')
11690 char *vop_start
= NULL
;
11692 while (base_string
-- > op_string
)
11694 if (*base_string
== '"')
11696 if (*base_string
!= '{')
11699 vop_start
= base_string
;
11702 if (is_space_char (*base_string
))
11705 if (*base_string
!= '}')
11713 as_bad (_("unbalanced figure braces"));
11717 if (check_VecOperations (vop_start
) == NULL
)
11721 /* If we only have a displacement, set-up for it to be parsed later. */
11722 displacement_string_start
= op_string
;
11723 displacement_string_end
= base_string
+ 1;
11725 if (*base_string
== ')')
11728 unsigned int parens_not_balanced
= 0;
11729 bool in_quotes
= false;
11731 /* We've already checked that the number of left & right ()'s are
11732 equal, and that there's a matching set of double quotes. */
11733 end_op
= base_string
;
11734 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
11736 if (*temp_string
== '\\' && temp_string
[1] == '"')
11738 else if (*temp_string
== '"')
11739 in_quotes
= !in_quotes
;
11740 else if (!in_quotes
)
11742 if (*temp_string
== '(' && !parens_not_balanced
++)
11743 base_string
= temp_string
;
11744 if (*temp_string
== ')')
11745 --parens_not_balanced
;
11749 temp_string
= base_string
;
11751 /* Skip past '(' and whitespace. */
11752 gas_assert (*base_string
== '(');
11754 if (is_space_char (*base_string
))
11757 if (*base_string
== ','
11758 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11761 displacement_string_end
= temp_string
;
11763 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11767 if (i
.base_reg
== &bad_reg
)
11769 base_string
= end_op
;
11770 if (is_space_char (*base_string
))
11774 /* There may be an index reg or scale factor here. */
11775 if (*base_string
== ',')
11778 if (is_space_char (*base_string
))
11781 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11784 if (i
.index_reg
== &bad_reg
)
11786 base_string
= end_op
;
11787 if (is_space_char (*base_string
))
11789 if (*base_string
== ',')
11792 if (is_space_char (*base_string
))
11795 else if (*base_string
!= ')')
11797 as_bad (_("expecting `,' or `)' "
11798 "after index register in `%s'"),
11803 else if (*base_string
== REGISTER_PREFIX
)
11805 end_op
= strchr (base_string
, ',');
11808 as_bad (_("bad register name `%s'"), base_string
);
11812 /* Check for scale factor. */
11813 if (*base_string
!= ')')
11815 char *end_scale
= i386_scale (base_string
);
11820 base_string
= end_scale
;
11821 if (is_space_char (*base_string
))
11823 if (*base_string
!= ')')
11825 as_bad (_("expecting `)' "
11826 "after scale factor in `%s'"),
11831 else if (!i
.index_reg
)
11833 as_bad (_("expecting index register or scale factor "
11834 "after `,'; got '%c'"),
11839 else if (*base_string
!= ')')
11841 as_bad (_("expecting `,' or `)' "
11842 "after base register in `%s'"),
11847 else if (*base_string
== REGISTER_PREFIX
)
11849 end_op
= strchr (base_string
, ',');
11852 as_bad (_("bad register name `%s'"), base_string
);
11857 /* If there's an expression beginning the operand, parse it,
11858 assuming displacement_string_start and
11859 displacement_string_end are meaningful. */
11860 if (displacement_string_start
!= displacement_string_end
)
11862 if (!i386_displacement (displacement_string_start
,
11863 displacement_string_end
))
11867 /* Special case for (%dx) while doing input/output op. */
11869 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11870 && i
.base_reg
->reg_type
.bitfield
.word
11871 && i
.index_reg
== 0
11872 && i
.log2_scale_factor
== 0
11873 && i
.seg
[i
.mem_operands
] == 0
11874 && !operand_type_check (i
.types
[this_operand
], disp
))
11876 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11877 i
.input_output_operand
= true;
11881 if (i386_index_check (operand_string
) == 0)
11883 i
.flags
[this_operand
] |= Operand_Mem
;
11888 /* It's not a memory operand; argh! */
11889 as_bad (_("invalid char %s beginning operand %d `%s'"),
11890 output_invalid (*op_string
),
11895 return 1; /* Normal return. */
11898 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11899 that an rs_machine_dependent frag may reach. */
11902 i386_frag_max_var (fragS
*frag
)
11904 /* The only relaxable frags are for jumps.
11905 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11906 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11907 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11910 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11912 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11914 /* STT_GNU_IFUNC symbol must go through PLT. */
11915 if ((symbol_get_bfdsym (fr_symbol
)->flags
11916 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11919 if (!S_IS_EXTERNAL (fr_symbol
))
11920 /* Symbol may be weak or local. */
11921 return !S_IS_WEAK (fr_symbol
);
11923 /* Global symbols with non-default visibility can't be preempted. */
11924 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11927 if (fr_var
!= NO_RELOC
)
11928 switch ((enum bfd_reloc_code_real
) fr_var
)
11930 case BFD_RELOC_386_PLT32
:
11931 case BFD_RELOC_X86_64_PLT32
:
11932 /* Symbol with PLT relocation may be preempted. */
11938 /* Global symbols with default visibility in a shared library may be
11939 preempted by another definition. */
11944 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11945 Note also work for Skylake and Cascadelake.
11946 ---------------------------------------------------------------------
11947 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11948 | ------ | ----------- | ------- | -------- |
11950 | Jno | N | N | Y |
11951 | Jc/Jb | Y | N | Y |
11952 | Jae/Jnb | Y | N | Y |
11953 | Je/Jz | Y | Y | Y |
11954 | Jne/Jnz | Y | Y | Y |
11955 | Jna/Jbe | Y | N | Y |
11956 | Ja/Jnbe | Y | N | Y |
11958 | Jns | N | N | Y |
11959 | Jp/Jpe | N | N | Y |
11960 | Jnp/Jpo | N | N | Y |
11961 | Jl/Jnge | Y | Y | Y |
11962 | Jge/Jnl | Y | Y | Y |
11963 | Jle/Jng | Y | Y | Y |
11964 | Jg/Jnle | Y | Y | Y |
11965 --------------------------------------------------------------------- */
11967 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11969 if (mf_cmp
== mf_cmp_alu_cmp
)
11970 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11971 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11972 if (mf_cmp
== mf_cmp_incdec
)
11973 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11974 || mf_jcc
== mf_jcc_jle
);
11975 if (mf_cmp
== mf_cmp_test_and
)
11980 /* Return the next non-empty frag. */
11983 i386_next_non_empty_frag (fragS
*fragP
)
11985 /* There may be a frag with a ".fill 0" when there is no room in
11986 the current frag for frag_grow in output_insn. */
11987 for (fragP
= fragP
->fr_next
;
11989 && fragP
->fr_type
== rs_fill
11990 && fragP
->fr_fix
== 0);
11991 fragP
= fragP
->fr_next
)
11996 /* Return the next jcc frag after BRANCH_PADDING. */
11999 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
12001 fragS
*branch_fragP
;
12005 if (pad_fragP
->fr_type
== rs_machine_dependent
12006 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
12007 == BRANCH_PADDING
))
12009 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
12010 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
12012 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
12013 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
12014 pad_fragP
->tc_frag_data
.mf_type
))
12015 return branch_fragP
;
12021 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
12024 i386_classify_machine_dependent_frag (fragS
*fragP
)
12028 fragS
*branch_fragP
;
12030 unsigned int max_prefix_length
;
12032 if (fragP
->tc_frag_data
.classified
)
12035 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
12036 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
12037 for (next_fragP
= fragP
;
12038 next_fragP
!= NULL
;
12039 next_fragP
= next_fragP
->fr_next
)
12041 next_fragP
->tc_frag_data
.classified
= 1;
12042 if (next_fragP
->fr_type
== rs_machine_dependent
)
12043 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
12045 case BRANCH_PADDING
:
12046 /* The BRANCH_PADDING frag must be followed by a branch
12048 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
12049 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12051 case FUSED_JCC_PADDING
:
12052 /* Check if this is a fused jcc:
12054 CMP like instruction
12058 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
12059 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
12060 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
12063 /* The BRANCH_PADDING frag is merged with the
12064 FUSED_JCC_PADDING frag. */
12065 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12066 /* CMP like instruction size. */
12067 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
12068 frag_wane (pad_fragP
);
12069 /* Skip to branch_fragP. */
12070 next_fragP
= branch_fragP
;
12072 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
12074 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
12076 next_fragP
->fr_subtype
12077 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
12078 next_fragP
->tc_frag_data
.max_bytes
12079 = next_fragP
->tc_frag_data
.max_prefix_length
;
12080 /* This will be updated in the BRANCH_PREFIX scan. */
12081 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
12084 frag_wane (next_fragP
);
12089 /* Stop if there is no BRANCH_PREFIX. */
12090 if (!align_branch_prefix_size
)
12093 /* Scan for BRANCH_PREFIX. */
12094 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
12096 if (fragP
->fr_type
!= rs_machine_dependent
12097 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12101 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
12102 COND_JUMP_PREFIX. */
12103 max_prefix_length
= 0;
12104 for (next_fragP
= fragP
;
12105 next_fragP
!= NULL
;
12106 next_fragP
= next_fragP
->fr_next
)
12108 if (next_fragP
->fr_type
== rs_fill
)
12109 /* Skip rs_fill frags. */
12111 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
12112 /* Stop for all other frags. */
12115 /* rs_machine_dependent frags. */
12116 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12119 /* Count BRANCH_PREFIX frags. */
12120 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
12122 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
12123 frag_wane (next_fragP
);
12127 += next_fragP
->tc_frag_data
.max_bytes
;
12129 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12131 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12132 == FUSED_JCC_PADDING
))
12134 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
12135 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
12139 /* Stop for other rs_machine_dependent frags. */
12143 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
12145 /* Skip to the next frag. */
12146 fragP
= next_fragP
;
12150 /* Compute padding size for
12153 CMP like instruction
12155 COND_JUMP/UNCOND_JUMP
12160 COND_JUMP/UNCOND_JUMP
12164 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
12166 unsigned int offset
, size
, padding_size
;
12167 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
12169 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
12171 address
= fragP
->fr_address
;
12172 address
+= fragP
->fr_fix
;
12174 /* CMP like instrunction size. */
12175 size
= fragP
->tc_frag_data
.cmp_size
;
12177 /* The base size of the branch frag. */
12178 size
+= branch_fragP
->fr_fix
;
12180 /* Add opcode and displacement bytes for the rs_machine_dependent
12182 if (branch_fragP
->fr_type
== rs_machine_dependent
)
12183 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
12185 /* Check if branch is within boundary and doesn't end at the last
12187 offset
= address
& ((1U << align_branch_power
) - 1);
12188 if ((offset
+ size
) >= (1U << align_branch_power
))
12189 /* Padding needed to avoid crossing boundary. */
12190 padding_size
= (1U << align_branch_power
) - offset
;
12192 /* No padding needed. */
12195 /* The return value may be saved in tc_frag_data.length which is
12197 if (!fits_in_unsigned_byte (padding_size
))
12200 return padding_size
;
12203 /* i386_generic_table_relax_frag()
12205 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12206 grow/shrink padding to align branch frags. Hand others to
12210 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12212 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12213 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12215 long padding_size
= i386_branch_padding_size (fragP
, 0);
12216 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12218 /* When the BRANCH_PREFIX frag is used, the computed address
12219 must match the actual address and there should be no padding. */
12220 if (fragP
->tc_frag_data
.padding_address
12221 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12225 /* Update the padding size. */
12227 fragP
->tc_frag_data
.length
= padding_size
;
12231 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12233 fragS
*padding_fragP
, *next_fragP
;
12234 long padding_size
, left_size
, last_size
;
12236 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12237 if (!padding_fragP
)
12238 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12239 return (fragP
->tc_frag_data
.length
12240 - fragP
->tc_frag_data
.last_length
);
12242 /* Compute the relative address of the padding frag in the very
12243 first time where the BRANCH_PREFIX frag sizes are zero. */
12244 if (!fragP
->tc_frag_data
.padding_address
)
12245 fragP
->tc_frag_data
.padding_address
12246 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12248 /* First update the last length from the previous interation. */
12249 left_size
= fragP
->tc_frag_data
.prefix_length
;
12250 for (next_fragP
= fragP
;
12251 next_fragP
!= padding_fragP
;
12252 next_fragP
= next_fragP
->fr_next
)
12253 if (next_fragP
->fr_type
== rs_machine_dependent
12254 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12259 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12263 if (max
> left_size
)
12268 next_fragP
->tc_frag_data
.last_length
= size
;
12272 next_fragP
->tc_frag_data
.last_length
= 0;
12275 /* Check the padding size for the padding frag. */
12276 padding_size
= i386_branch_padding_size
12277 (padding_fragP
, (fragP
->fr_address
12278 + fragP
->tc_frag_data
.padding_address
));
12280 last_size
= fragP
->tc_frag_data
.prefix_length
;
12281 /* Check if there is change from the last interation. */
12282 if (padding_size
== last_size
)
12284 /* Update the expected address of the padding frag. */
12285 padding_fragP
->tc_frag_data
.padding_address
12286 = (fragP
->fr_address
+ padding_size
12287 + fragP
->tc_frag_data
.padding_address
);
12291 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12293 /* No padding if there is no sufficient room. Clear the
12294 expected address of the padding frag. */
12295 padding_fragP
->tc_frag_data
.padding_address
= 0;
12299 /* Store the expected address of the padding frag. */
12300 padding_fragP
->tc_frag_data
.padding_address
12301 = (fragP
->fr_address
+ padding_size
12302 + fragP
->tc_frag_data
.padding_address
);
12304 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12306 /* Update the length for the current interation. */
12307 left_size
= padding_size
;
12308 for (next_fragP
= fragP
;
12309 next_fragP
!= padding_fragP
;
12310 next_fragP
= next_fragP
->fr_next
)
12311 if (next_fragP
->fr_type
== rs_machine_dependent
12312 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12317 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12321 if (max
> left_size
)
12326 next_fragP
->tc_frag_data
.length
= size
;
12330 next_fragP
->tc_frag_data
.length
= 0;
12333 return (fragP
->tc_frag_data
.length
12334 - fragP
->tc_frag_data
.last_length
);
12336 return relax_frag (segment
, fragP
, stretch
);
12339 /* md_estimate_size_before_relax()
12341 Called just before relax() for rs_machine_dependent frags. The x86
12342 assembler uses these frags to handle variable size jump
12345 Any symbol that is now undefined will not become defined.
12346 Return the correct fr_subtype in the frag.
12347 Return the initial "guess for variable size of frag" to caller.
12348 The guess is actually the growth beyond the fixed part. Whatever
12349 we do to grow the fixed or variable part contributes to our
12353 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12355 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12356 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12357 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12359 i386_classify_machine_dependent_frag (fragP
);
12360 return fragP
->tc_frag_data
.length
;
12363 /* We've already got fragP->fr_subtype right; all we have to do is
12364 check for un-relaxable symbols. On an ELF system, we can't relax
12365 an externally visible symbol, because it may be overridden by a
12367 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12370 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12373 #if defined (OBJ_COFF) && defined (TE_PE)
12374 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12375 && S_IS_WEAK (fragP
->fr_symbol
))
12379 /* Symbol is undefined in this segment, or we need to keep a
12380 reloc so that weak symbols can be overridden. */
12381 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12382 enum bfd_reloc_code_real reloc_type
;
12383 unsigned char *opcode
;
12387 if (fragP
->fr_var
!= NO_RELOC
)
12388 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12389 else if (size
== 2)
12390 reloc_type
= BFD_RELOC_16_PCREL
;
12391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12392 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
12393 && need_plt32_p (fragP
->fr_symbol
))
12394 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12397 reloc_type
= BFD_RELOC_32_PCREL
;
12399 old_fr_fix
= fragP
->fr_fix
;
12400 opcode
= (unsigned char *) fragP
->fr_opcode
;
12402 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12405 /* Make jmp (0xeb) a (d)word displacement jump. */
12407 fragP
->fr_fix
+= size
;
12408 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12410 fragP
->fr_offset
, 1,
12416 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12418 /* Negate the condition, and branch past an
12419 unconditional jump. */
12422 /* Insert an unconditional jump. */
12424 /* We added two extra opcode bytes, and have a two byte
12426 fragP
->fr_fix
+= 2 + 2;
12427 fix_new (fragP
, old_fr_fix
+ 2, 2,
12429 fragP
->fr_offset
, 1,
12433 /* Fall through. */
12436 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12438 fragP
->fr_fix
+= 1;
12439 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12441 fragP
->fr_offset
, 1,
12442 BFD_RELOC_8_PCREL
);
12443 fixP
->fx_signed
= 1;
12447 /* This changes the byte-displacement jump 0x7N
12448 to the (d)word-displacement jump 0x0f,0x8N. */
12449 opcode
[1] = opcode
[0] + 0x10;
12450 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12451 /* We've added an opcode byte. */
12452 fragP
->fr_fix
+= 1 + size
;
12453 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12455 fragP
->fr_offset
, 1,
12460 BAD_CASE (fragP
->fr_subtype
);
12464 /* All jumps handled here are signed, but don't unconditionally use a
12465 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12466 around at 4G (outside of 64-bit mode) and 64k. */
12467 if (size
== 4 && flag_code
== CODE_64BIT
)
12468 fixP
->fx_signed
= 1;
12471 return fragP
->fr_fix
- old_fr_fix
;
12474 /* Guess size depending on current relax state. Initially the relax
12475 state will correspond to a short jump and we return 1, because
12476 the variable part of the frag (the branch offset) is one byte
12477 long. However, we can relax a section more than once and in that
12478 case we must either set fr_subtype back to the unrelaxed state,
12479 or return the value for the appropriate branch. */
12480 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12483 /* Called after relax() is finished.
12485 In: Address of frag.
12486 fr_type == rs_machine_dependent.
12487 fr_subtype is what the address relaxed to.
12489 Out: Any fixSs and constants are set up.
12490 Caller will turn frag into a ".space 0". */
12493 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12496 unsigned char *opcode
;
12497 unsigned char *where_to_put_displacement
= NULL
;
12498 offsetT target_address
;
12499 offsetT opcode_address
;
12500 unsigned int extension
= 0;
12501 offsetT displacement_from_opcode_start
;
12503 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12504 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12505 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12507 /* Generate nop padding. */
12508 unsigned int size
= fragP
->tc_frag_data
.length
;
12511 if (size
> fragP
->tc_frag_data
.max_bytes
)
12517 const char *branch
= "branch";
12518 const char *prefix
= "";
12519 fragS
*padding_fragP
;
12520 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12523 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12524 switch (fragP
->tc_frag_data
.default_prefix
)
12529 case CS_PREFIX_OPCODE
:
12532 case DS_PREFIX_OPCODE
:
12535 case ES_PREFIX_OPCODE
:
12538 case FS_PREFIX_OPCODE
:
12541 case GS_PREFIX_OPCODE
:
12544 case SS_PREFIX_OPCODE
:
12549 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12550 "%s within %d-byte boundary\n");
12552 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12553 "align %s within %d-byte boundary\n");
12557 padding_fragP
= fragP
;
12558 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12559 "%s within %d-byte boundary\n");
12563 switch (padding_fragP
->tc_frag_data
.branch_type
)
12565 case align_branch_jcc
:
12568 case align_branch_fused
:
12569 branch
= "fused jcc";
12571 case align_branch_jmp
:
12574 case align_branch_call
:
12577 case align_branch_indirect
:
12578 branch
= "indiret branch";
12580 case align_branch_ret
:
12587 fprintf (stdout
, msg
,
12588 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12589 (long long) fragP
->fr_address
, branch
,
12590 1 << align_branch_power
);
12592 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12593 memset (fragP
->fr_opcode
,
12594 fragP
->tc_frag_data
.default_prefix
, size
);
12596 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12598 fragP
->fr_fix
+= size
;
12603 opcode
= (unsigned char *) fragP
->fr_opcode
;
12605 /* Address we want to reach in file space. */
12606 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12608 /* Address opcode resides at in file space. */
12609 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12611 /* Displacement from opcode start to fill into instruction. */
12612 displacement_from_opcode_start
= target_address
- opcode_address
;
12614 if ((fragP
->fr_subtype
& BIG
) == 0)
12616 /* Don't have to change opcode. */
12617 extension
= 1; /* 1 opcode + 1 displacement */
12618 where_to_put_displacement
= &opcode
[1];
12622 if (no_cond_jump_promotion
12623 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12624 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12625 _("long jump required"));
12627 switch (fragP
->fr_subtype
)
12629 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12630 extension
= 4; /* 1 opcode + 4 displacement */
12632 where_to_put_displacement
= &opcode
[1];
12635 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12636 extension
= 2; /* 1 opcode + 2 displacement */
12638 where_to_put_displacement
= &opcode
[1];
12641 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12642 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12643 extension
= 5; /* 2 opcode + 4 displacement */
12644 opcode
[1] = opcode
[0] + 0x10;
12645 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12646 where_to_put_displacement
= &opcode
[2];
12649 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12650 extension
= 3; /* 2 opcode + 2 displacement */
12651 opcode
[1] = opcode
[0] + 0x10;
12652 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12653 where_to_put_displacement
= &opcode
[2];
12656 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12661 where_to_put_displacement
= &opcode
[3];
12665 BAD_CASE (fragP
->fr_subtype
);
12670 /* If size if less then four we are sure that the operand fits,
12671 but if it's 4, then it could be that the displacement is larger
12673 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12675 && ((addressT
) (displacement_from_opcode_start
- extension
12676 + ((addressT
) 1 << 31))
12677 > (((addressT
) 2 << 31) - 1)))
12679 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12680 _("jump target out of range"));
12681 /* Make us emit 0. */
12682 displacement_from_opcode_start
= extension
;
12684 /* Now put displacement after opcode. */
12685 md_number_to_chars ((char *) where_to_put_displacement
,
12686 (valueT
) (displacement_from_opcode_start
- extension
),
12687 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12688 fragP
->fr_fix
+= extension
;
12691 /* Apply a fixup (fixP) to segment data, once it has been determined
12692 by our caller that we have all the info we need to fix it up.
12694 Parameter valP is the pointer to the value of the bits.
12696 On the 386, immediates, displacements, and data pointers are all in
12697 the same (little-endian) format, so we don't need to care about which
12698 we are handling. */
12701 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12703 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12704 valueT value
= *valP
;
12706 #if !defined (TE_Mach)
12707 if (fixP
->fx_pcrel
)
12709 switch (fixP
->fx_r_type
)
12715 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12718 case BFD_RELOC_X86_64_32S
:
12719 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12722 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12725 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12730 if (fixP
->fx_addsy
!= NULL
12731 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12732 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12733 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12734 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12735 && !use_rela_relocations
)
12737 /* This is a hack. There should be a better way to handle this.
12738 This covers for the fact that bfd_install_relocation will
12739 subtract the current location (for partial_inplace, PC relative
12740 relocations); see more below. */
12744 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12747 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12752 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12754 if ((sym_seg
== seg
12755 || (symbol_section_p (fixP
->fx_addsy
)
12756 && sym_seg
!= absolute_section
))
12757 && !generic_force_reloc (fixP
))
12759 /* Yes, we add the values in twice. This is because
12760 bfd_install_relocation subtracts them out again. I think
12761 bfd_install_relocation is broken, but I don't dare change
12763 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12767 #if defined (OBJ_COFF) && defined (TE_PE)
12768 /* For some reason, the PE format does not store a
12769 section address offset for a PC relative symbol. */
12770 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12771 || S_IS_WEAK (fixP
->fx_addsy
))
12772 value
+= md_pcrel_from (fixP
);
12775 #if defined (OBJ_COFF) && defined (TE_PE)
12776 if (fixP
->fx_addsy
!= NULL
12777 && S_IS_WEAK (fixP
->fx_addsy
)
12778 /* PR 16858: Do not modify weak function references. */
12779 && ! fixP
->fx_pcrel
)
12781 #if !defined (TE_PEP)
12782 /* For x86 PE weak function symbols are neither PC-relative
12783 nor do they set S_IS_FUNCTION. So the only reliable way
12784 to detect them is to check the flags of their containing
12786 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12787 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12791 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12795 /* Fix a few things - the dynamic linker expects certain values here,
12796 and we must not disappoint it. */
12797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12798 if (IS_ELF
&& fixP
->fx_addsy
)
12799 switch (fixP
->fx_r_type
)
12801 case BFD_RELOC_386_PLT32
:
12802 case BFD_RELOC_X86_64_PLT32
:
12803 /* Make the jump instruction point to the address of the operand.
12804 At runtime we merely add the offset to the actual PLT entry.
12805 NB: Subtract the offset size only for jump instructions. */
12806 if (fixP
->fx_pcrel
)
12810 case BFD_RELOC_386_TLS_GD
:
12811 case BFD_RELOC_386_TLS_LDM
:
12812 case BFD_RELOC_386_TLS_IE_32
:
12813 case BFD_RELOC_386_TLS_IE
:
12814 case BFD_RELOC_386_TLS_GOTIE
:
12815 case BFD_RELOC_386_TLS_GOTDESC
:
12816 case BFD_RELOC_X86_64_TLSGD
:
12817 case BFD_RELOC_X86_64_TLSLD
:
12818 case BFD_RELOC_X86_64_GOTTPOFF
:
12819 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12820 value
= 0; /* Fully resolved at runtime. No addend. */
12822 case BFD_RELOC_386_TLS_LE
:
12823 case BFD_RELOC_386_TLS_LDO_32
:
12824 case BFD_RELOC_386_TLS_LE_32
:
12825 case BFD_RELOC_X86_64_DTPOFF32
:
12826 case BFD_RELOC_X86_64_DTPOFF64
:
12827 case BFD_RELOC_X86_64_TPOFF32
:
12828 case BFD_RELOC_X86_64_TPOFF64
:
12829 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12832 case BFD_RELOC_386_TLS_DESC_CALL
:
12833 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12834 value
= 0; /* Fully resolved at runtime. No addend. */
12835 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12839 case BFD_RELOC_VTABLE_INHERIT
:
12840 case BFD_RELOC_VTABLE_ENTRY
:
12847 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12849 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12851 value
= extend_to_32bit_address (value
);
12854 #endif /* !defined (TE_Mach) */
12856 /* Are we finished with this relocation now? */
12857 if (fixP
->fx_addsy
== NULL
)
12860 switch (fixP
->fx_r_type
)
12862 case BFD_RELOC_X86_64_32S
:
12863 fixP
->fx_signed
= 1;
12870 #if defined (OBJ_COFF) && defined (TE_PE)
12871 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12874 /* Remember value for tc_gen_reloc. */
12875 fixP
->fx_addnumber
= value
;
12876 /* Clear out the frag for now. */
12880 else if (use_rela_relocations
)
12882 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
12883 fixP
->fx_no_overflow
= 1;
12884 /* Remember value for tc_gen_reloc. */
12885 fixP
->fx_addnumber
= value
;
12889 md_number_to_chars (p
, value
, fixP
->fx_size
);
12893 md_atof (int type
, char *litP
, int *sizeP
)
12895 /* This outputs the LITTLENUMs in REVERSE order;
12896 in accord with the bigendian 386. */
12897 return ieee_md_atof (type
, litP
, sizeP
, false);
12900 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12903 output_invalid (int c
)
12906 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12909 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12910 "(0x%x)", (unsigned char) c
);
12911 return output_invalid_buf
;
12914 /* Verify that @r can be used in the current context. */
12916 static bool check_register (const reg_entry
*r
)
12918 if (allow_pseudo_reg
)
12921 if (operand_type_all_zero (&r
->reg_type
))
12924 if ((r
->reg_type
.bitfield
.dword
12925 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12926 || r
->reg_type
.bitfield
.class == RegCR
12927 || r
->reg_type
.bitfield
.class == RegDR
)
12928 && !cpu_arch_flags
.bitfield
.cpui386
)
12931 if (r
->reg_type
.bitfield
.class == RegTR
12932 && (flag_code
== CODE_64BIT
12933 || !cpu_arch_flags
.bitfield
.cpui386
12934 || cpu_arch_isa_flags
.bitfield
.cpui586
12935 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12938 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12941 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12943 if (r
->reg_type
.bitfield
.zmmword
12944 || r
->reg_type
.bitfield
.class == RegMask
)
12947 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12949 if (r
->reg_type
.bitfield
.ymmword
)
12952 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12957 if (r
->reg_type
.bitfield
.tmmword
12958 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12959 || flag_code
!= CODE_64BIT
))
12962 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12965 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12966 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12969 /* Upper 16 vector registers are only available with VREX in 64bit
12970 mode, and require EVEX encoding. */
12971 if (r
->reg_flags
& RegVRex
)
12973 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12974 || flag_code
!= CODE_64BIT
)
12977 if (i
.vec_encoding
== vex_encoding_default
)
12978 i
.vec_encoding
= vex_encoding_evex
;
12979 else if (i
.vec_encoding
!= vex_encoding_evex
)
12980 i
.vec_encoding
= vex_encoding_error
;
12983 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12984 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12985 && flag_code
!= CODE_64BIT
)
12988 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12995 /* REG_STRING starts *before* REGISTER_PREFIX. */
12997 static const reg_entry
*
12998 parse_real_register (char *reg_string
, char **end_op
)
13000 char *s
= reg_string
;
13002 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
13003 const reg_entry
*r
;
13005 /* Skip possible REGISTER_PREFIX and possible whitespace. */
13006 if (*s
== REGISTER_PREFIX
)
13009 if (is_space_char (*s
))
13012 p
= reg_name_given
;
13013 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
13015 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
13016 return (const reg_entry
*) NULL
;
13020 /* For naked regs, make sure that we are not dealing with an identifier.
13021 This prevents confusing an identifier like `eax_var' with register
13023 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
13024 return (const reg_entry
*) NULL
;
13028 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
13030 /* Handle floating point regs, allowing spaces in the (i) part. */
13033 if (!cpu_arch_flags
.bitfield
.cpu8087
13034 && !cpu_arch_flags
.bitfield
.cpu287
13035 && !cpu_arch_flags
.bitfield
.cpu387
13036 && !allow_pseudo_reg
)
13037 return (const reg_entry
*) NULL
;
13039 if (is_space_char (*s
))
13044 if (is_space_char (*s
))
13046 if (*s
>= '0' && *s
<= '7')
13048 int fpr
= *s
- '0';
13050 if (is_space_char (*s
))
13055 know (r
[fpr
].reg_num
== fpr
);
13059 /* We have "%st(" then garbage. */
13060 return (const reg_entry
*) NULL
;
13064 return r
&& check_register (r
) ? r
: NULL
;
13067 /* REG_STRING starts *before* REGISTER_PREFIX. */
13069 static const reg_entry
*
13070 parse_register (char *reg_string
, char **end_op
)
13072 const reg_entry
*r
;
13074 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
13075 r
= parse_real_register (reg_string
, end_op
);
13080 char *save
= input_line_pointer
;
13084 input_line_pointer
= reg_string
;
13085 c
= get_symbol_name (®_string
);
13086 symbolP
= symbol_find (reg_string
);
13087 while (symbolP
&& S_GET_SEGMENT (symbolP
) != reg_section
)
13089 const expressionS
*e
= symbol_get_value_expression(symbolP
);
13091 if (e
->X_op
!= O_symbol
|| e
->X_add_number
)
13093 symbolP
= e
->X_add_symbol
;
13095 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
13097 const expressionS
*e
= symbol_get_value_expression (symbolP
);
13099 know (e
->X_op
== O_register
);
13100 know (e
->X_add_number
>= 0
13101 && (valueT
) e
->X_add_number
< i386_regtab_size
);
13102 r
= i386_regtab
+ e
->X_add_number
;
13103 if (!check_register (r
))
13105 as_bad (_("register '%s%s' cannot be used here"),
13106 register_prefix
, r
->reg_name
);
13109 *end_op
= input_line_pointer
;
13111 *input_line_pointer
= c
;
13112 input_line_pointer
= save
;
13118 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
13120 const reg_entry
*r
= NULL
;
13121 char *end
= input_line_pointer
;
13124 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
13125 r
= parse_real_register (name
, &input_line_pointer
);
13126 if (r
&& end
<= input_line_pointer
)
13128 *nextcharP
= *input_line_pointer
;
13129 *input_line_pointer
= 0;
13132 e
->X_op
= O_register
;
13133 e
->X_add_number
= r
- i386_regtab
;
13136 e
->X_op
= O_illegal
;
13139 input_line_pointer
= end
;
13141 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
13145 md_operand (expressionS
*e
)
13148 const reg_entry
*r
;
13150 switch (*input_line_pointer
)
13152 case REGISTER_PREFIX
:
13153 r
= parse_real_register (input_line_pointer
, &end
);
13156 e
->X_op
= O_register
;
13157 e
->X_add_number
= r
- i386_regtab
;
13158 input_line_pointer
= end
;
13163 gas_assert (intel_syntax
);
13164 end
= input_line_pointer
++;
13166 if (*input_line_pointer
== ']')
13168 ++input_line_pointer
;
13169 e
->X_op_symbol
= make_expr_symbol (e
);
13170 e
->X_add_symbol
= NULL
;
13171 e
->X_add_number
= 0;
13176 e
->X_op
= O_absent
;
13177 input_line_pointer
= end
;
13184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13185 const char *md_shortopts
= "kVQ:sqnO::";
13187 const char *md_shortopts
= "qnO::";
13190 #define OPTION_32 (OPTION_MD_BASE + 0)
13191 #define OPTION_64 (OPTION_MD_BASE + 1)
13192 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
13193 #define OPTION_MARCH (OPTION_MD_BASE + 3)
13194 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
13195 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
13196 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
13197 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13198 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13199 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13200 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13201 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13202 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13203 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13204 #define OPTION_X32 (OPTION_MD_BASE + 14)
13205 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
13206 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
13207 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
13208 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13209 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13210 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13211 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13212 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13213 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13214 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13215 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13216 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13217 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13218 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13219 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13220 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13221 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13222 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13223 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13224 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
13226 struct option md_longopts
[] =
13228 {"32", no_argument
, NULL
, OPTION_32
},
13229 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13230 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13231 {"64", no_argument
, NULL
, OPTION_64
},
13233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13234 {"x32", no_argument
, NULL
, OPTION_X32
},
13235 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13236 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13238 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13239 {"march", required_argument
, NULL
, OPTION_MARCH
},
13240 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13241 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13242 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13243 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13244 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13245 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13246 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
13247 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13248 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13249 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13250 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13251 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13252 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13253 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13254 # if defined (TE_PE) || defined (TE_PEP)
13255 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13257 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13258 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13259 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13260 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13261 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13262 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13263 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13264 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13265 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13266 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13267 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13268 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13269 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13270 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13271 {NULL
, no_argument
, NULL
, 0}
13273 size_t md_longopts_size
= sizeof (md_longopts
);
13276 md_parse_option (int c
, const char *arg
)
13279 char *arch
, *next
, *saved
, *type
;
13284 optimize_align_code
= 0;
13288 quiet_warnings
= 1;
13291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13292 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13293 should be emitted or not. FIXME: Not implemented. */
13295 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13299 /* -V: SVR4 argument to print version ID. */
13301 print_version_id ();
13304 /* -k: Ignore for FreeBSD compatibility. */
13309 /* -s: On i386 Solaris, this tells the native assembler to use
13310 .stab instead of .stab.excl. We always use .stab anyhow. */
13313 case OPTION_MSHARED
:
13317 case OPTION_X86_USED_NOTE
:
13318 if (strcasecmp (arg
, "yes") == 0)
13320 else if (strcasecmp (arg
, "no") == 0)
13323 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13328 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13329 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13332 const char **list
, **l
;
13334 list
= bfd_target_list ();
13335 for (l
= list
; *l
!= NULL
; l
++)
13336 if (startswith (*l
, "elf64-x86-64")
13337 || strcmp (*l
, "coff-x86-64") == 0
13338 || strcmp (*l
, "pe-x86-64") == 0
13339 || strcmp (*l
, "pei-x86-64") == 0
13340 || strcmp (*l
, "mach-o-x86-64") == 0)
13342 default_arch
= "x86_64";
13346 as_fatal (_("no compiled in support for x86_64"));
13352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13356 const char **list
, **l
;
13358 list
= bfd_target_list ();
13359 for (l
= list
; *l
!= NULL
; l
++)
13360 if (startswith (*l
, "elf32-x86-64"))
13362 default_arch
= "x86_64:32";
13366 as_fatal (_("no compiled in support for 32bit x86_64"));
13370 as_fatal (_("32bit x86_64 is only supported for ELF"));
13375 default_arch
= "i386";
13378 case OPTION_DIVIDE
:
13379 #ifdef SVR4_COMMENT_CHARS
13384 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13386 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13390 i386_comment_chars
= n
;
13396 saved
= xstrdup (arg
);
13398 /* Allow -march=+nosse. */
13404 as_fatal (_("invalid -march= option: `%s'"), arg
);
13405 next
= strchr (arch
, '+');
13408 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13410 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
13411 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
13414 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
13417 cpu_arch_name
= cpu_arch
[j
].name
;
13418 free (cpu_sub_arch_name
);
13419 cpu_sub_arch_name
= NULL
;
13420 cpu_arch_flags
= cpu_arch
[j
].enable
;
13421 cpu_arch_isa
= cpu_arch
[j
].type
;
13422 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
13423 if (!cpu_arch_tune_set
)
13425 cpu_arch_tune
= cpu_arch_isa
;
13426 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13430 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
13431 && strcmp (arch
, cpu_arch
[j
].name
) == 0
13432 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13434 /* ISA extension. */
13435 i386_cpu_flags flags
;
13437 flags
= cpu_flags_or (cpu_arch_flags
,
13438 cpu_arch
[j
].enable
);
13440 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13442 extend_cpu_sub_arch_name (arch
);
13443 cpu_arch_flags
= flags
;
13444 cpu_arch_isa_flags
= flags
;
13448 = cpu_flags_or (cpu_arch_isa_flags
,
13449 cpu_arch
[j
].enable
);
13454 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
13456 /* Disable an ISA extension. */
13457 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13458 if (cpu_arch
[j
].type
== PROCESSOR_NONE
13459 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
13461 i386_cpu_flags flags
;
13463 flags
= cpu_flags_and_not (cpu_arch_flags
,
13464 cpu_arch
[j
].disable
);
13465 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13467 extend_cpu_sub_arch_name (arch
);
13468 cpu_arch_flags
= flags
;
13469 cpu_arch_isa_flags
= flags
;
13475 if (j
>= ARRAY_SIZE (cpu_arch
))
13476 as_fatal (_("invalid -march= option: `%s'"), arg
);
13480 while (next
!= NULL
);
13486 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13487 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13489 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
13490 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
13492 cpu_arch_tune_set
= 1;
13493 cpu_arch_tune
= cpu_arch
[j
].type
;
13494 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
13498 if (j
>= ARRAY_SIZE (cpu_arch
))
13499 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13502 case OPTION_MMNEMONIC
:
13503 if (strcasecmp (arg
, "att") == 0)
13504 intel_mnemonic
= 0;
13505 else if (strcasecmp (arg
, "intel") == 0)
13506 intel_mnemonic
= 1;
13508 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13511 case OPTION_MSYNTAX
:
13512 if (strcasecmp (arg
, "att") == 0)
13514 else if (strcasecmp (arg
, "intel") == 0)
13517 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13520 case OPTION_MINDEX_REG
:
13521 allow_index_reg
= 1;
13524 case OPTION_MNAKED_REG
:
13525 allow_naked_reg
= 1;
13528 case OPTION_MSSE2AVX
:
13532 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
13533 use_unaligned_vector_move
= 1;
13536 case OPTION_MSSE_CHECK
:
13537 if (strcasecmp (arg
, "error") == 0)
13538 sse_check
= check_error
;
13539 else if (strcasecmp (arg
, "warning") == 0)
13540 sse_check
= check_warning
;
13541 else if (strcasecmp (arg
, "none") == 0)
13542 sse_check
= check_none
;
13544 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13547 case OPTION_MOPERAND_CHECK
:
13548 if (strcasecmp (arg
, "error") == 0)
13549 operand_check
= check_error
;
13550 else if (strcasecmp (arg
, "warning") == 0)
13551 operand_check
= check_warning
;
13552 else if (strcasecmp (arg
, "none") == 0)
13553 operand_check
= check_none
;
13555 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13558 case OPTION_MAVXSCALAR
:
13559 if (strcasecmp (arg
, "128") == 0)
13560 avxscalar
= vex128
;
13561 else if (strcasecmp (arg
, "256") == 0)
13562 avxscalar
= vex256
;
13564 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13567 case OPTION_MVEXWIG
:
13568 if (strcmp (arg
, "0") == 0)
13570 else if (strcmp (arg
, "1") == 0)
13573 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13576 case OPTION_MADD_BND_PREFIX
:
13577 add_bnd_prefix
= 1;
13580 case OPTION_MEVEXLIG
:
13581 if (strcmp (arg
, "128") == 0)
13582 evexlig
= evexl128
;
13583 else if (strcmp (arg
, "256") == 0)
13584 evexlig
= evexl256
;
13585 else if (strcmp (arg
, "512") == 0)
13586 evexlig
= evexl512
;
13588 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13591 case OPTION_MEVEXRCIG
:
13592 if (strcmp (arg
, "rne") == 0)
13594 else if (strcmp (arg
, "rd") == 0)
13596 else if (strcmp (arg
, "ru") == 0)
13598 else if (strcmp (arg
, "rz") == 0)
13601 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13604 case OPTION_MEVEXWIG
:
13605 if (strcmp (arg
, "0") == 0)
13607 else if (strcmp (arg
, "1") == 0)
13610 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13613 # if defined (TE_PE) || defined (TE_PEP)
13614 case OPTION_MBIG_OBJ
:
13619 case OPTION_MOMIT_LOCK_PREFIX
:
13620 if (strcasecmp (arg
, "yes") == 0)
13621 omit_lock_prefix
= 1;
13622 else if (strcasecmp (arg
, "no") == 0)
13623 omit_lock_prefix
= 0;
13625 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13628 case OPTION_MFENCE_AS_LOCK_ADD
:
13629 if (strcasecmp (arg
, "yes") == 0)
13631 else if (strcasecmp (arg
, "no") == 0)
13634 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13637 case OPTION_MLFENCE_AFTER_LOAD
:
13638 if (strcasecmp (arg
, "yes") == 0)
13639 lfence_after_load
= 1;
13640 else if (strcasecmp (arg
, "no") == 0)
13641 lfence_after_load
= 0;
13643 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13646 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13647 if (strcasecmp (arg
, "all") == 0)
13649 lfence_before_indirect_branch
= lfence_branch_all
;
13650 if (lfence_before_ret
== lfence_before_ret_none
)
13651 lfence_before_ret
= lfence_before_ret_shl
;
13653 else if (strcasecmp (arg
, "memory") == 0)
13654 lfence_before_indirect_branch
= lfence_branch_memory
;
13655 else if (strcasecmp (arg
, "register") == 0)
13656 lfence_before_indirect_branch
= lfence_branch_register
;
13657 else if (strcasecmp (arg
, "none") == 0)
13658 lfence_before_indirect_branch
= lfence_branch_none
;
13660 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13664 case OPTION_MLFENCE_BEFORE_RET
:
13665 if (strcasecmp (arg
, "or") == 0)
13666 lfence_before_ret
= lfence_before_ret_or
;
13667 else if (strcasecmp (arg
, "not") == 0)
13668 lfence_before_ret
= lfence_before_ret_not
;
13669 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13670 lfence_before_ret
= lfence_before_ret_shl
;
13671 else if (strcasecmp (arg
, "none") == 0)
13672 lfence_before_ret
= lfence_before_ret_none
;
13674 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13678 case OPTION_MRELAX_RELOCATIONS
:
13679 if (strcasecmp (arg
, "yes") == 0)
13680 generate_relax_relocations
= 1;
13681 else if (strcasecmp (arg
, "no") == 0)
13682 generate_relax_relocations
= 0;
13684 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13687 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13690 long int align
= strtoul (arg
, &end
, 0);
13695 align_branch_power
= 0;
13698 else if (align
>= 16)
13701 for (align_power
= 0;
13703 align
>>= 1, align_power
++)
13705 /* Limit alignment power to 31. */
13706 if (align
== 1 && align_power
< 32)
13708 align_branch_power
= align_power
;
13713 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13717 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13720 int align
= strtoul (arg
, &end
, 0);
13721 /* Some processors only support 5 prefixes. */
13722 if (*end
== '\0' && align
>= 0 && align
< 6)
13724 align_branch_prefix_size
= align
;
13727 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13732 case OPTION_MALIGN_BRANCH
:
13734 saved
= xstrdup (arg
);
13738 next
= strchr (type
, '+');
13741 if (strcasecmp (type
, "jcc") == 0)
13742 align_branch
|= align_branch_jcc_bit
;
13743 else if (strcasecmp (type
, "fused") == 0)
13744 align_branch
|= align_branch_fused_bit
;
13745 else if (strcasecmp (type
, "jmp") == 0)
13746 align_branch
|= align_branch_jmp_bit
;
13747 else if (strcasecmp (type
, "call") == 0)
13748 align_branch
|= align_branch_call_bit
;
13749 else if (strcasecmp (type
, "ret") == 0)
13750 align_branch
|= align_branch_ret_bit
;
13751 else if (strcasecmp (type
, "indirect") == 0)
13752 align_branch
|= align_branch_indirect_bit
;
13754 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13757 while (next
!= NULL
);
13761 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13762 align_branch_power
= 5;
13763 align_branch_prefix_size
= 5;
13764 align_branch
= (align_branch_jcc_bit
13765 | align_branch_fused_bit
13766 | align_branch_jmp_bit
);
13769 case OPTION_MAMD64
:
13773 case OPTION_MINTEL64
:
13781 /* Turn off -Os. */
13782 optimize_for_space
= 0;
13784 else if (*arg
== 's')
13786 optimize_for_space
= 1;
13787 /* Turn on all encoding optimizations. */
13788 optimize
= INT_MAX
;
13792 optimize
= atoi (arg
);
13793 /* Turn off -Os. */
13794 optimize_for_space
= 0;
13804 #define MESSAGE_TEMPLATE \
13808 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13809 int *left_p
, const char *name
, int len
)
13811 int size
= sizeof (MESSAGE_TEMPLATE
);
13812 int left
= *left_p
;
13814 /* Reserve 2 spaces for ", " or ",\0" */
13817 /* Check if there is any room. */
13825 p
= mempcpy (p
, name
, len
);
13829 /* Output the current message now and start a new one. */
13832 fprintf (stream
, "%s\n", message
);
13834 left
= size
- (start
- message
) - len
- 2;
13836 gas_assert (left
>= 0);
13838 p
= mempcpy (p
, name
, len
);
13846 show_arch (FILE *stream
, int ext
, int check
)
13848 static char message
[] = MESSAGE_TEMPLATE
;
13849 char *start
= message
+ 27;
13851 int size
= sizeof (MESSAGE_TEMPLATE
);
13858 left
= size
- (start
- message
);
13862 p
= output_message (stream
, p
, message
, start
, &left
,
13863 STRING_COMMA_LEN ("default"));
13864 p
= output_message (stream
, p
, message
, start
, &left
,
13865 STRING_COMMA_LEN ("push"));
13866 p
= output_message (stream
, p
, message
, start
, &left
,
13867 STRING_COMMA_LEN ("pop"));
13870 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13872 /* Should it be skipped? */
13873 if (cpu_arch
[j
].skip
)
13876 name
= cpu_arch
[j
].name
;
13877 len
= cpu_arch
[j
].len
;
13878 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
13880 /* It is an extension. Skip if we aren't asked to show it. */
13881 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13886 /* It is an processor. Skip if we show only extension. */
13889 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
13891 /* It is an impossible processor - skip. */
13895 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13898 /* Display disabled extensions. */
13900 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13904 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
13905 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13907 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
13908 p
= output_message (stream
, p
, message
, start
, &left
, str
,
13914 fprintf (stream
, "%s\n", message
);
13918 md_show_usage (FILE *stream
)
13920 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13921 fprintf (stream
, _("\
13922 -Qy, -Qn ignored\n\
13923 -V print assembler version number\n\
13926 fprintf (stream
, _("\
13927 -n do not optimize code alignment\n\
13928 -O{012s} attempt some code optimizations\n\
13929 -q quieten some warnings\n"));
13930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13931 fprintf (stream
, _("\
13935 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13936 fprintf (stream
, _("\
13937 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
13938 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
13939 fprintf (stream
, _("\
13940 --32/--64 generate 32bit/64bit object\n"));
13943 #ifdef SVR4_COMMENT_CHARS
13944 fprintf (stream
, _("\
13945 --divide do not treat `/' as a comment character\n"));
13947 fprintf (stream
, _("\
13948 --divide ignored\n"));
13950 fprintf (stream
, _("\
13951 -march=CPU[,+EXTENSION...]\n\
13952 generate code for CPU and EXTENSION, CPU is one of:\n"));
13953 show_arch (stream
, 0, 1);
13954 fprintf (stream
, _("\
13955 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
13956 show_arch (stream
, 1, 0);
13957 fprintf (stream
, _("\
13958 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13959 show_arch (stream
, 0, 0);
13960 fprintf (stream
, _("\
13961 -msse2avx encode SSE instructions with VEX prefix\n"));
13962 fprintf (stream
, _("\
13963 -muse-unaligned-vector-move\n\
13964 encode aligned vector move as unaligned vector move\n"));
13965 fprintf (stream
, _("\
13966 -msse-check=[none|error|warning] (default: warning)\n\
13967 check SSE instructions\n"));
13968 fprintf (stream
, _("\
13969 -moperand-check=[none|error|warning] (default: warning)\n\
13970 check operand combinations for validity\n"));
13971 fprintf (stream
, _("\
13972 -mavxscalar=[128|256] (default: 128)\n\
13973 encode scalar AVX instructions with specific vector\n\
13975 fprintf (stream
, _("\
13976 -mvexwig=[0|1] (default: 0)\n\
13977 encode VEX instructions with specific VEX.W value\n\
13978 for VEX.W bit ignored instructions\n"));
13979 fprintf (stream
, _("\
13980 -mevexlig=[128|256|512] (default: 128)\n\
13981 encode scalar EVEX instructions with specific vector\n\
13983 fprintf (stream
, _("\
13984 -mevexwig=[0|1] (default: 0)\n\
13985 encode EVEX instructions with specific EVEX.W value\n\
13986 for EVEX.W bit ignored instructions\n"));
13987 fprintf (stream
, _("\
13988 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13989 encode EVEX instructions with specific EVEX.RC value\n\
13990 for SAE-only ignored instructions\n"));
13991 fprintf (stream
, _("\
13992 -mmnemonic=[att|intel] "));
13993 if (SYSV386_COMPAT
)
13994 fprintf (stream
, _("(default: att)\n"));
13996 fprintf (stream
, _("(default: intel)\n"));
13997 fprintf (stream
, _("\
13998 use AT&T/Intel mnemonic\n"));
13999 fprintf (stream
, _("\
14000 -msyntax=[att|intel] (default: att)\n\
14001 use AT&T/Intel syntax\n"));
14002 fprintf (stream
, _("\
14003 -mindex-reg support pseudo index registers\n"));
14004 fprintf (stream
, _("\
14005 -mnaked-reg don't require `%%' prefix for registers\n"));
14006 fprintf (stream
, _("\
14007 -madd-bnd-prefix add BND prefix for all valid branches\n"));
14008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14009 fprintf (stream
, _("\
14010 -mshared disable branch optimization for shared code\n"));
14011 fprintf (stream
, _("\
14012 -mx86-used-note=[no|yes] "));
14013 if (DEFAULT_X86_USED_NOTE
)
14014 fprintf (stream
, _("(default: yes)\n"));
14016 fprintf (stream
, _("(default: no)\n"));
14017 fprintf (stream
, _("\
14018 generate x86 used ISA and feature properties\n"));
14020 #if defined (TE_PE) || defined (TE_PEP)
14021 fprintf (stream
, _("\
14022 -mbig-obj generate big object files\n"));
14024 fprintf (stream
, _("\
14025 -momit-lock-prefix=[no|yes] (default: no)\n\
14026 strip all lock prefixes\n"));
14027 fprintf (stream
, _("\
14028 -mfence-as-lock-add=[no|yes] (default: no)\n\
14029 encode lfence, mfence and sfence as\n\
14030 lock addl $0x0, (%%{re}sp)\n"));
14031 fprintf (stream
, _("\
14032 -mrelax-relocations=[no|yes] "));
14033 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
14034 fprintf (stream
, _("(default: yes)\n"));
14036 fprintf (stream
, _("(default: no)\n"));
14037 fprintf (stream
, _("\
14038 generate relax relocations\n"));
14039 fprintf (stream
, _("\
14040 -malign-branch-boundary=NUM (default: 0)\n\
14041 align branches within NUM byte boundary\n"));
14042 fprintf (stream
, _("\
14043 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
14044 TYPE is combination of jcc, fused, jmp, call, ret,\n\
14046 specify types of branches to align\n"));
14047 fprintf (stream
, _("\
14048 -malign-branch-prefix-size=NUM (default: 5)\n\
14049 align branches with NUM prefixes per instruction\n"));
14050 fprintf (stream
, _("\
14051 -mbranches-within-32B-boundaries\n\
14052 align branches within 32 byte boundary\n"));
14053 fprintf (stream
, _("\
14054 -mlfence-after-load=[no|yes] (default: no)\n\
14055 generate lfence after load\n"));
14056 fprintf (stream
, _("\
14057 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
14058 generate lfence before indirect near branch\n"));
14059 fprintf (stream
, _("\
14060 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
14061 generate lfence before ret\n"));
14062 fprintf (stream
, _("\
14063 -mamd64 accept only AMD64 ISA [default]\n"));
14064 fprintf (stream
, _("\
14065 -mintel64 accept only Intel64 ISA\n"));
14068 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
14069 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14070 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14072 /* Pick the target format to use. */
14075 i386_target_format (void)
14077 if (startswith (default_arch
, "x86_64"))
14079 update_code_flag (CODE_64BIT
, 1);
14080 if (default_arch
[6] == '\0')
14081 x86_elf_abi
= X86_64_ABI
;
14083 x86_elf_abi
= X86_64_X32_ABI
;
14085 else if (!strcmp (default_arch
, "i386"))
14086 update_code_flag (CODE_32BIT
, 1);
14087 else if (!strcmp (default_arch
, "iamcu"))
14089 update_code_flag (CODE_32BIT
, 1);
14090 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
14092 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
14093 cpu_arch_name
= "iamcu";
14094 free (cpu_sub_arch_name
);
14095 cpu_sub_arch_name
= NULL
;
14096 cpu_arch_flags
= iamcu_flags
;
14097 cpu_arch_isa
= PROCESSOR_IAMCU
;
14098 cpu_arch_isa_flags
= iamcu_flags
;
14099 if (!cpu_arch_tune_set
)
14101 cpu_arch_tune
= cpu_arch_isa
;
14102 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14105 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
14106 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
14110 as_fatal (_("unknown architecture"));
14112 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
14113 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14114 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
14115 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14117 switch (OUTPUT_FLAVOR
)
14119 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
14120 case bfd_target_aout_flavour
:
14121 return AOUT_TARGET_FORMAT
;
14123 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
14124 # if defined (TE_PE) || defined (TE_PEP)
14125 case bfd_target_coff_flavour
:
14126 if (flag_code
== CODE_64BIT
)
14129 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
14131 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
14132 # elif defined (TE_GO32)
14133 case bfd_target_coff_flavour
:
14134 return "coff-go32";
14136 case bfd_target_coff_flavour
:
14137 return "coff-i386";
14140 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14141 case bfd_target_elf_flavour
:
14143 const char *format
;
14145 switch (x86_elf_abi
)
14148 format
= ELF_TARGET_FORMAT
;
14150 tls_get_addr
= "___tls_get_addr";
14154 use_rela_relocations
= 1;
14157 tls_get_addr
= "__tls_get_addr";
14159 format
= ELF_TARGET_FORMAT64
;
14161 case X86_64_X32_ABI
:
14162 use_rela_relocations
= 1;
14165 tls_get_addr
= "__tls_get_addr";
14167 disallow_64bit_reloc
= 1;
14168 format
= ELF_TARGET_FORMAT32
;
14171 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
14173 if (x86_elf_abi
!= I386_ABI
)
14174 as_fatal (_("Intel MCU is 32bit only"));
14175 return ELF_TARGET_IAMCU_FORMAT
;
14181 #if defined (OBJ_MACH_O)
14182 case bfd_target_mach_o_flavour
:
14183 if (flag_code
== CODE_64BIT
)
14185 use_rela_relocations
= 1;
14187 return "mach-o-x86-64";
14190 return "mach-o-i386";
14198 #endif /* OBJ_MAYBE_ more than one */
14201 md_undefined_symbol (char *name
)
14203 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14204 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14205 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
14206 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14210 if (symbol_find (name
))
14211 as_bad (_("GOT already in symbol table"));
14212 GOT_symbol
= symbol_new (name
, undefined_section
,
14213 &zero_address_frag
, 0);
14220 /* Round up a section size to the appropriate boundary. */
14223 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14225 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14226 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14228 /* For a.out, force the section size to be aligned. If we don't do
14229 this, BFD will align it for us, but it will not write out the
14230 final bytes of the section. This may be a bug in BFD, but it is
14231 easier to fix it here since that is how the other a.out targets
14235 align
= bfd_section_alignment (segment
);
14236 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14243 /* On the i386, PC-relative offsets are relative to the start of the
14244 next instruction. That is, the address of the offset, plus its
14245 size, since the offset is always the last part of the insn. */
14248 md_pcrel_from (fixS
*fixP
)
14250 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14256 s_bss (int ignore ATTRIBUTE_UNUSED
)
14260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14262 obj_elf_section_change_hook ();
14264 temp
= get_absolute_expression ();
14265 subseg_set (bss_section
, (subsegT
) temp
);
14266 demand_empty_rest_of_line ();
14271 /* Remember constant directive. */
14274 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14276 if (last_insn
.kind
!= last_insn_directive
14277 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14279 last_insn
.seg
= now_seg
;
14280 last_insn
.kind
= last_insn_directive
;
14281 last_insn
.name
= "constant directive";
14282 last_insn
.file
= as_where (&last_insn
.line
);
14283 if (lfence_before_ret
!= lfence_before_ret_none
)
14285 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14286 as_warn (_("constant directive skips -mlfence-before-ret "
14287 "and -mlfence-before-indirect-branch"));
14289 as_warn (_("constant directive skips -mlfence-before-ret"));
14291 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14292 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14297 i386_validate_fix (fixS
*fixp
)
14299 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
14301 reloc_howto_type
*howto
;
14303 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
14304 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14305 _("invalid %s relocation against register"),
14306 howto
? howto
->name
: "<unknown>");
14310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14311 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14312 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14313 return IS_ELF
&& fixp
->fx_addsy
14314 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14315 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14318 if (fixp
->fx_subsy
)
14320 if (fixp
->fx_subsy
== GOT_symbol
)
14322 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14326 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14327 if (fixp
->fx_tcbit2
)
14328 fixp
->fx_r_type
= (fixp
->fx_tcbit
14329 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14330 : BFD_RELOC_X86_64_GOTPCRELX
);
14333 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14338 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14340 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14342 fixp
->fx_subsy
= 0;
14345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14348 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14349 to section. Since PLT32 relocation must be against symbols,
14350 turn such PLT32 relocation into PC32 relocation. */
14352 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14353 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14354 && symbol_section_p (fixp
->fx_addsy
))
14355 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14358 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14359 && fixp
->fx_tcbit2
)
14360 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14369 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14372 bfd_reloc_code_real_type code
;
14374 switch (fixp
->fx_r_type
)
14376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14379 case BFD_RELOC_SIZE32
:
14380 case BFD_RELOC_SIZE64
:
14382 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14383 && (!fixp
->fx_subsy
14384 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14385 sym
= fixp
->fx_addsy
;
14386 else if (fixp
->fx_subsy
14387 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14388 && (!fixp
->fx_addsy
14389 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14390 sym
= fixp
->fx_subsy
;
14393 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14395 /* Resolve size relocation against local symbol to size of
14396 the symbol plus addend. */
14397 valueT value
= S_GET_SIZE (sym
);
14399 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14400 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14401 if (sym
== fixp
->fx_subsy
)
14404 if (fixp
->fx_addsy
)
14405 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14407 else if (fixp
->fx_subsy
)
14408 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14409 value
+= fixp
->fx_offset
;
14410 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14412 && !fits_in_unsigned_long (value
))
14413 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14414 _("symbol size computation overflow"));
14415 fixp
->fx_addsy
= NULL
;
14416 fixp
->fx_subsy
= NULL
;
14417 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14420 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14422 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14423 "unsupported expression involving @size");
14427 /* Fall through. */
14429 case BFD_RELOC_X86_64_PLT32
:
14430 case BFD_RELOC_X86_64_GOT32
:
14431 case BFD_RELOC_X86_64_GOTPCREL
:
14432 case BFD_RELOC_X86_64_GOTPCRELX
:
14433 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14434 case BFD_RELOC_386_PLT32
:
14435 case BFD_RELOC_386_GOT32
:
14436 case BFD_RELOC_386_GOT32X
:
14437 case BFD_RELOC_386_GOTOFF
:
14438 case BFD_RELOC_386_GOTPC
:
14439 case BFD_RELOC_386_TLS_GD
:
14440 case BFD_RELOC_386_TLS_LDM
:
14441 case BFD_RELOC_386_TLS_LDO_32
:
14442 case BFD_RELOC_386_TLS_IE_32
:
14443 case BFD_RELOC_386_TLS_IE
:
14444 case BFD_RELOC_386_TLS_GOTIE
:
14445 case BFD_RELOC_386_TLS_LE_32
:
14446 case BFD_RELOC_386_TLS_LE
:
14447 case BFD_RELOC_386_TLS_GOTDESC
:
14448 case BFD_RELOC_386_TLS_DESC_CALL
:
14449 case BFD_RELOC_X86_64_TLSGD
:
14450 case BFD_RELOC_X86_64_TLSLD
:
14451 case BFD_RELOC_X86_64_DTPOFF32
:
14452 case BFD_RELOC_X86_64_DTPOFF64
:
14453 case BFD_RELOC_X86_64_GOTTPOFF
:
14454 case BFD_RELOC_X86_64_TPOFF32
:
14455 case BFD_RELOC_X86_64_TPOFF64
:
14456 case BFD_RELOC_X86_64_GOTOFF64
:
14457 case BFD_RELOC_X86_64_GOTPC32
:
14458 case BFD_RELOC_X86_64_GOT64
:
14459 case BFD_RELOC_X86_64_GOTPCREL64
:
14460 case BFD_RELOC_X86_64_GOTPC64
:
14461 case BFD_RELOC_X86_64_GOTPLT64
:
14462 case BFD_RELOC_X86_64_PLTOFF64
:
14463 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14464 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14465 case BFD_RELOC_RVA
:
14466 case BFD_RELOC_VTABLE_ENTRY
:
14467 case BFD_RELOC_VTABLE_INHERIT
:
14469 case BFD_RELOC_32_SECREL
:
14470 case BFD_RELOC_16_SECIDX
:
14472 code
= fixp
->fx_r_type
;
14474 case BFD_RELOC_X86_64_32S
:
14475 if (!fixp
->fx_pcrel
)
14477 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14478 code
= fixp
->fx_r_type
;
14481 /* Fall through. */
14483 if (fixp
->fx_pcrel
)
14485 switch (fixp
->fx_size
)
14488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14489 _("can not do %d byte pc-relative relocation"),
14491 code
= BFD_RELOC_32_PCREL
;
14493 case 1: code
= BFD_RELOC_8_PCREL
; break;
14494 case 2: code
= BFD_RELOC_16_PCREL
; break;
14495 case 4: code
= BFD_RELOC_32_PCREL
; break;
14497 case 8: code
= BFD_RELOC_64_PCREL
; break;
14503 switch (fixp
->fx_size
)
14506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14507 _("can not do %d byte relocation"),
14509 code
= BFD_RELOC_32
;
14511 case 1: code
= BFD_RELOC_8
; break;
14512 case 2: code
= BFD_RELOC_16
; break;
14513 case 4: code
= BFD_RELOC_32
; break;
14515 case 8: code
= BFD_RELOC_64
; break;
14522 if ((code
== BFD_RELOC_32
14523 || code
== BFD_RELOC_32_PCREL
14524 || code
== BFD_RELOC_X86_64_32S
)
14526 && fixp
->fx_addsy
== GOT_symbol
)
14529 code
= BFD_RELOC_386_GOTPC
;
14531 code
= BFD_RELOC_X86_64_GOTPC32
;
14533 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14535 && fixp
->fx_addsy
== GOT_symbol
)
14537 code
= BFD_RELOC_X86_64_GOTPC64
;
14540 rel
= XNEW (arelent
);
14541 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14542 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14544 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14546 if (!use_rela_relocations
)
14548 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14549 vtable entry to be used in the relocation's section offset. */
14550 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14551 rel
->address
= fixp
->fx_offset
;
14552 #if defined (OBJ_COFF) && defined (TE_PE)
14553 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14554 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14559 /* Use the rela in 64bit mode. */
14562 if (disallow_64bit_reloc
)
14565 case BFD_RELOC_X86_64_DTPOFF64
:
14566 case BFD_RELOC_X86_64_TPOFF64
:
14567 case BFD_RELOC_64_PCREL
:
14568 case BFD_RELOC_X86_64_GOTOFF64
:
14569 case BFD_RELOC_X86_64_GOT64
:
14570 case BFD_RELOC_X86_64_GOTPCREL64
:
14571 case BFD_RELOC_X86_64_GOTPC64
:
14572 case BFD_RELOC_X86_64_GOTPLT64
:
14573 case BFD_RELOC_X86_64_PLTOFF64
:
14574 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14575 _("cannot represent relocation type %s in x32 mode"),
14576 bfd_get_reloc_code_name (code
));
14582 if (!fixp
->fx_pcrel
)
14583 rel
->addend
= fixp
->fx_offset
;
14587 case BFD_RELOC_X86_64_PLT32
:
14588 case BFD_RELOC_X86_64_GOT32
:
14589 case BFD_RELOC_X86_64_GOTPCREL
:
14590 case BFD_RELOC_X86_64_GOTPCRELX
:
14591 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14592 case BFD_RELOC_X86_64_TLSGD
:
14593 case BFD_RELOC_X86_64_TLSLD
:
14594 case BFD_RELOC_X86_64_GOTTPOFF
:
14595 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14596 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14597 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14600 rel
->addend
= (section
->vma
14602 + fixp
->fx_addnumber
14603 + md_pcrel_from (fixp
));
14608 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14609 if (rel
->howto
== NULL
)
14611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14612 _("cannot represent relocation type %s"),
14613 bfd_get_reloc_code_name (code
));
14614 /* Set howto to a garbage value so that we can keep going. */
14615 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14616 gas_assert (rel
->howto
!= NULL
);
14622 #include "tc-i386-intel.c"
14625 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14627 int saved_naked_reg
;
14628 char saved_register_dot
;
14630 saved_naked_reg
= allow_naked_reg
;
14631 allow_naked_reg
= 1;
14632 saved_register_dot
= register_chars
['.'];
14633 register_chars
['.'] = '.';
14634 allow_pseudo_reg
= 1;
14635 expression_and_evaluate (exp
);
14636 allow_pseudo_reg
= 0;
14637 register_chars
['.'] = saved_register_dot
;
14638 allow_naked_reg
= saved_naked_reg
;
14640 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14642 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14644 exp
->X_op
= O_constant
;
14645 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14646 .dw2_regnum
[flag_code
>> 1];
14649 exp
->X_op
= O_illegal
;
14654 tc_x86_frame_initial_instructions (void)
14656 static unsigned int sp_regno
[2];
14658 if (!sp_regno
[flag_code
>> 1])
14660 char *saved_input
= input_line_pointer
;
14661 char sp
[][4] = {"esp", "rsp"};
14664 input_line_pointer
= sp
[flag_code
>> 1];
14665 tc_x86_parse_to_dw2regnum (&exp
);
14666 gas_assert (exp
.X_op
== O_constant
);
14667 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14668 input_line_pointer
= saved_input
;
14671 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14672 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14676 x86_dwarf2_addr_size (void)
14678 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14679 if (x86_elf_abi
== X86_64_X32_ABI
)
14682 return bfd_arch_bits_per_address (stdoutput
) / 8;
14686 i386_elf_section_type (const char *str
, size_t len
)
14688 if (flag_code
== CODE_64BIT
14689 && len
== sizeof ("unwind") - 1
14690 && startswith (str
, "unwind"))
14691 return SHT_X86_64_UNWIND
;
14698 i386_solaris_fix_up_eh_frame (segT sec
)
14700 if (flag_code
== CODE_64BIT
)
14701 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14707 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14711 exp
.X_op
= O_secrel
;
14712 exp
.X_add_symbol
= symbol
;
14713 exp
.X_add_number
= 0;
14714 emit_expr (&exp
, size
);
14718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14719 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14722 x86_64_section_letter (int letter
, const char **ptr_msg
)
14724 if (flag_code
== CODE_64BIT
)
14727 return SHF_X86_64_LARGE
;
14729 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14732 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14737 x86_64_section_word (char *str
, size_t len
)
14739 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14740 return SHF_X86_64_LARGE
;
14746 handle_large_common (int small ATTRIBUTE_UNUSED
)
14748 if (flag_code
!= CODE_64BIT
)
14750 s_comm_internal (0, elf_common_parse
);
14751 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14755 static segT lbss_section
;
14756 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14757 asection
*saved_bss_section
= bss_section
;
14759 if (lbss_section
== NULL
)
14761 flagword applicable
;
14762 segT seg
= now_seg
;
14763 subsegT subseg
= now_subseg
;
14765 /* The .lbss section is for local .largecomm symbols. */
14766 lbss_section
= subseg_new (".lbss", 0);
14767 applicable
= bfd_applicable_section_flags (stdoutput
);
14768 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14769 seg_info (lbss_section
)->bss
= 1;
14771 subseg_set (seg
, subseg
);
14774 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14775 bss_section
= lbss_section
;
14777 s_comm_internal (0, elf_common_parse
);
14779 elf_com_section_ptr
= saved_com_section_ptr
;
14780 bss_section
= saved_bss_section
;
14783 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */