1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
292 #define Operand_Signed 4 /* .insn only */
294 /* Relocation type for operand */
295 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
297 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
298 the base index byte below. */
299 const reg_entry
*base_reg
;
300 const reg_entry
*index_reg
;
301 unsigned int log2_scale_factor
;
303 /* SEG gives the seg_entries of this insn. They are zero unless
304 explicit segment overrides are given. */
305 const reg_entry
*seg
[2];
307 /* PREFIX holds all the given prefix opcodes (usually null).
308 PREFIXES is the number of prefix opcodes. */
309 unsigned int prefixes
;
310 unsigned char prefix
[MAX_PREFIXES
];
312 /* .insn allows for reserved opcode spaces. */
313 unsigned char insn_opcode_space
;
315 /* .insn also allows (requires) specifying immediate size. */
316 unsigned char imm_bits
[MAX_OPERANDS
];
318 /* Register is in low 3 bits of opcode. */
321 /* The operand to a branch insn indicates an absolute branch. */
324 /* The operand to a branch insn indicates a far branch. */
327 /* There is a memory operand of (%dx) which should be only used
328 with input/output instructions. */
329 bool input_output_operand
;
331 /* Extended states. */
339 xstate_ymm
= 1 << 2 | xstate_xmm
,
341 xstate_zmm
= 1 << 3 | xstate_ymm
,
344 /* Use MASK state. */
348 /* Has GOTPC or TLS relocation. */
349 bool has_gotpc_tls_reloc
;
351 /* RM and SIB are the modrm byte and the sib byte where the
352 addressing modes of this insn are encoded. */
359 /* Masking attributes.
361 The struct describes masking, applied to OPERAND in the instruction.
362 REG is a pointer to the corresponding mask register. ZEROING tells
363 whether merging or zeroing mask is used. */
364 struct Mask_Operation
366 const reg_entry
*reg
;
367 unsigned int zeroing
;
368 /* The operand where this operation is associated. */
369 unsigned int operand
;
372 /* Rounding control and SAE attributes. */
384 /* In Intel syntax the operand modifier form is supposed to be used, but
385 we continue to accept the immediate forms as well. */
389 /* Broadcasting attributes.
391 The struct describes broadcasting, applied to OPERAND. TYPE is
392 expresses the broadcast factor. */
393 struct Broadcast_Operation
395 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
398 /* Index of broadcasted operand. */
399 unsigned int operand
;
401 /* Number of bytes to broadcast. */
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
429 /* Disable instruction size optimization. */
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
439 vex_encoding_evex512
,
444 const char *rep_prefix
;
447 const char *hle_prefix
;
449 /* Have BND prefix. */
450 const char *bnd_prefix
;
452 /* Have NOTRACK prefix. */
453 const char *notrack_prefix
;
456 enum i386_error error
;
459 typedef struct _i386_insn i386_insn
;
461 /* Link RC type with corresponding string, that'll be looked for in
470 static const struct RC_name RC_NamesTable
[] =
472 { rne
, STRING_COMMA_LEN ("rn-sae") },
473 { rd
, STRING_COMMA_LEN ("rd-sae") },
474 { ru
, STRING_COMMA_LEN ("ru-sae") },
475 { rz
, STRING_COMMA_LEN ("rz-sae") },
476 { saeonly
, STRING_COMMA_LEN ("sae") },
479 /* To be indexed by segment register number. */
480 static const unsigned char i386_seg_prefixes
[] = {
489 /* List of chars besides those in app.c:symbol_chars that can start an
490 operand. Used to prevent the scrubber eating vital white-space. */
491 const char extra_symbol_chars
[] = "*%-([{}"
500 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
501 && !defined (TE_GNU) \
502 && !defined (TE_LINUX) \
503 && !defined (TE_Haiku) \
504 && !defined (TE_FreeBSD) \
505 && !defined (TE_DragonFly) \
506 && !defined (TE_NetBSD))
507 /* This array holds the chars that always start a comment. If the
508 pre-processor is disabled, these aren't very useful. The option
509 --divide will remove '/' from this list. */
510 const char *i386_comment_chars
= "#/";
511 #define SVR4_COMMENT_CHARS 1
512 #define PREFIX_SEPARATOR '\\'
515 const char *i386_comment_chars
= "#";
516 #define PREFIX_SEPARATOR '/'
519 /* This array holds the chars that only start a comment at the beginning of
520 a line. If the line seems to have the form '# 123 filename'
521 .line and .file directives will appear in the pre-processed output.
522 Note that input_file.c hand checks for '#' at the beginning of the
523 first line of the input file. This is because the compiler outputs
524 #NO_APP at the beginning of its output.
525 Also note that comments started like this one will always work if
526 '/' isn't otherwise defined. */
527 const char line_comment_chars
[] = "#/";
529 const char line_separator_chars
[] = ";";
531 /* Chars that can be used to separate mant from exp in floating point
533 const char EXP_CHARS
[] = "eE";
535 /* Chars that mean this number is a floating point constant
538 const char FLT_CHARS
[] = "fFdDxXhHbB";
540 /* Tables for lexical analysis. */
541 static char mnemonic_chars
[256];
542 static char register_chars
[256];
543 static char operand_chars
[256];
545 /* Lexical macros. */
546 #define is_operand_char(x) (operand_chars[(unsigned char) x])
547 #define is_register_char(x) (register_chars[(unsigned char) x])
548 #define is_space_char(x) ((x) == ' ')
550 /* All non-digit non-letter characters that may occur in an operand and
551 which aren't already in extra_symbol_chars[]. */
552 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
554 /* md_assemble() always leaves the strings it's passed unaltered. To
555 effect this we maintain a stack of saved characters that we've smashed
556 with '\0's (indicating end of strings for various sub-fields of the
557 assembler instruction). */
558 static char save_stack
[32];
559 static char *save_stack_p
;
560 #define END_STRING_AND_SAVE(s) \
561 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
562 #define RESTORE_END_STRING(s) \
563 do { *(s) = *--save_stack_p; } while (0)
565 /* The instruction we're assembling. */
568 /* Possible templates for current insn. */
569 static const templates
*current_templates
;
571 /* Per instruction expressionS buffers: max displacements & immediates. */
572 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
573 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
575 /* Current operand we are working on. */
576 static int this_operand
= -1;
578 /* Are we processing a .insn directive? */
579 #define dot_insn() (i.tm.mnem_off == MN__insn)
581 /* We support four different modes. FLAG_CODE variable is used to distinguish
589 static enum flag_code flag_code
;
590 static unsigned int object_64bit
;
591 static unsigned int disallow_64bit_reloc
;
592 static int use_rela_relocations
= 0;
593 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
594 static const char *tls_get_addr
;
596 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
597 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
598 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
600 /* The ELF ABI to use. */
608 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
611 #if defined (TE_PE) || defined (TE_PEP)
612 /* Use big object file format. */
613 static int use_big_obj
= 0;
616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
617 /* 1 if generating code for a shared library. */
618 static int shared
= 0;
620 unsigned int x86_sframe_cfa_sp_reg
;
621 /* The other CFA base register for SFrame stack trace info. */
622 unsigned int x86_sframe_cfa_fp_reg
;
623 unsigned int x86_sframe_cfa_ra_reg
;
627 /* 1 for intel syntax,
629 static int intel_syntax
= 0;
631 static enum x86_64_isa
633 amd64
= 1, /* AMD64 ISA. */
634 intel64
/* Intel64 ISA. */
637 /* 1 for intel mnemonic,
638 0 if att mnemonic. */
639 static int intel_mnemonic
= !SYSV386_COMPAT
;
641 /* 1 if pseudo registers are permitted. */
642 static int allow_pseudo_reg
= 0;
644 /* 1 if register prefix % not required. */
645 static int allow_naked_reg
= 0;
647 /* 1 if the assembler should add BND prefix for all control-transferring
648 instructions supporting it, even if this prefix wasn't specified
650 static int add_bnd_prefix
= 0;
652 /* 1 if pseudo index register, eiz/riz, is allowed . */
653 static int allow_index_reg
= 0;
655 /* 1 if the assembler should ignore LOCK prefix, even if it was
656 specified explicitly. */
657 static int omit_lock_prefix
= 0;
659 /* 1 if the assembler should encode lfence, mfence, and sfence as
660 "lock addl $0, (%{re}sp)". */
661 static int avoid_fence
= 0;
663 /* 1 if lfence should be inserted after every load. */
664 static int lfence_after_load
= 0;
666 /* Non-zero if lfence should be inserted before indirect branch. */
667 static enum lfence_before_indirect_branch_kind
669 lfence_branch_none
= 0,
670 lfence_branch_register
,
671 lfence_branch_memory
,
674 lfence_before_indirect_branch
;
676 /* Non-zero if lfence should be inserted before ret. */
677 static enum lfence_before_ret_kind
679 lfence_before_ret_none
= 0,
680 lfence_before_ret_not
,
681 lfence_before_ret_or
,
682 lfence_before_ret_shl
686 /* Types of previous instruction is .byte or prefix. */
701 /* 1 if the assembler should generate relax relocations. */
703 static int generate_relax_relocations
704 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
706 static enum check_kind
712 sse_check
, operand_check
= check_warning
;
714 /* Non-zero if branches should be aligned within power of 2 boundary. */
715 static int align_branch_power
= 0;
717 /* Types of branches to align. */
718 enum align_branch_kind
720 align_branch_none
= 0,
721 align_branch_jcc
= 1,
722 align_branch_fused
= 2,
723 align_branch_jmp
= 3,
724 align_branch_call
= 4,
725 align_branch_indirect
= 5,
729 /* Type bits of branches to align. */
730 enum align_branch_bit
732 align_branch_jcc_bit
= 1 << align_branch_jcc
,
733 align_branch_fused_bit
= 1 << align_branch_fused
,
734 align_branch_jmp_bit
= 1 << align_branch_jmp
,
735 align_branch_call_bit
= 1 << align_branch_call
,
736 align_branch_indirect_bit
= 1 << align_branch_indirect
,
737 align_branch_ret_bit
= 1 << align_branch_ret
740 static unsigned int align_branch
= (align_branch_jcc_bit
741 | align_branch_fused_bit
742 | align_branch_jmp_bit
);
744 /* Types of condition jump used by macro-fusion. */
747 mf_jcc_jo
= 0, /* base opcode 0x70 */
748 mf_jcc_jc
, /* base opcode 0x72 */
749 mf_jcc_je
, /* base opcode 0x74 */
750 mf_jcc_jna
, /* base opcode 0x76 */
751 mf_jcc_js
, /* base opcode 0x78 */
752 mf_jcc_jp
, /* base opcode 0x7a */
753 mf_jcc_jl
, /* base opcode 0x7c */
754 mf_jcc_jle
, /* base opcode 0x7e */
757 /* Types of compare flag-modifying insntructions used by macro-fusion. */
760 mf_cmp_test_and
, /* test/cmp */
761 mf_cmp_alu_cmp
, /* add/sub/cmp */
762 mf_cmp_incdec
/* inc/dec */
765 /* The maximum padding size for fused jcc. CMP like instruction can
766 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
768 #define MAX_FUSED_JCC_PADDING_SIZE 20
770 /* The maximum number of prefixes added for an instruction. */
771 static unsigned int align_branch_prefix_size
= 5;
774 1. Clear the REX_W bit with register operand if possible.
775 2. Above plus use 128bit vector instruction to clear the full vector
778 static int optimize
= 0;
781 1. Clear the REX_W bit with register operand if possible.
782 2. Above plus use 128bit vector instruction to clear the full vector
784 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
787 static int optimize_for_space
= 0;
789 /* Register prefix used for error message. */
790 static const char *register_prefix
= "%";
792 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
793 leave, push, and pop instructions so that gcc has the same stack
794 frame as in 32 bit mode. */
795 static char stackop_size
= '\0';
797 /* Non-zero to optimize code alignment. */
798 int optimize_align_code
= 1;
800 /* Non-zero to quieten some warnings. */
801 static int quiet_warnings
= 0;
803 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
804 static bool pre_386_16bit_warned
;
807 static const char *cpu_arch_name
= NULL
;
808 static char *cpu_sub_arch_name
= NULL
;
810 /* CPU feature flags. */
811 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
813 /* If we have selected a cpu we are generating instructions for. */
814 static int cpu_arch_tune_set
= 0;
816 /* Cpu we are generating instructions for. */
817 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of cpu we are generating instructions for. */
820 static i386_cpu_flags cpu_arch_tune_flags
;
822 /* CPU instruction set architecture used. */
823 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
825 /* CPU feature flags of instruction set architecture used. */
826 i386_cpu_flags cpu_arch_isa_flags
;
828 /* If set, conditional jumps are not automatically promoted to handle
829 larger than a byte offset. */
830 static bool no_cond_jump_promotion
= false;
832 /* This will be set from an expression parser hook if there's any
833 applicable operator involved in an expression. */
836 expr_operator_present
,
840 /* Encode SSE instructions with VEX prefix. */
841 static unsigned int sse2avx
;
843 /* Encode aligned vector move as unaligned vector move. */
844 static unsigned int use_unaligned_vector_move
;
846 /* Maximum permitted vector size. */
847 #define VSZ_DEFAULT VSZ512
848 static unsigned int vector_size
= VSZ_DEFAULT
;
850 /* Encode scalar AVX instructions with specific vector length. */
857 /* Encode VEX WIG instructions with specific vex.w. */
864 /* Encode scalar EVEX LIG instructions with specific vector length. */
872 /* Encode EVEX WIG instructions with specific evex.w. */
879 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
880 static enum rc_type evexrcig
= rne
;
882 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
883 static symbolS
*GOT_symbol
;
885 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
886 unsigned int x86_dwarf2_return_column
;
888 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
889 int x86_cie_data_alignment
;
891 /* Interface to relax_segment.
892 There are 3 major relax states for 386 jump insns because the
893 different types of jumps add different sizes to frags when we're
894 figuring out what sort of jump to choose to reach a given label.
896 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
897 branches which are handled by md_estimate_size_before_relax() and
898 i386_generic_table_relax_frag(). */
901 #define UNCOND_JUMP 0
903 #define COND_JUMP86 2
904 #define BRANCH_PADDING 3
905 #define BRANCH_PREFIX 4
906 #define FUSED_JCC_PADDING 5
911 #define SMALL16 (SMALL | CODE16)
913 #define BIG16 (BIG | CODE16)
917 #define INLINE __inline__
923 #define ENCODE_RELAX_STATE(type, size) \
924 ((relax_substateT) (((type) << 2) | (size)))
925 #define TYPE_FROM_RELAX_STATE(s) \
927 #define DISP_SIZE_FROM_RELAX_STATE(s) \
928 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
930 /* This table is used by relax_frag to promote short jumps to long
931 ones where necessary. SMALL (short) jumps may be promoted to BIG
932 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
933 don't allow a short jump in a 32 bit code segment to be promoted to
934 a 16 bit offset jump because it's slower (requires data size
935 prefix), and doesn't work, unless the destination is in the bottom
936 64k of the code segment (The top 16 bits of eip are zeroed). */
938 const relax_typeS md_relax_table
[] =
941 1) most positive reach of this state,
942 2) most negative reach of this state,
943 3) how many bytes this mode will have in the variable part of the frag
944 4) which index into the table to try if we can't fit into this one. */
946 /* UNCOND_JUMP states. */
947 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
948 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
949 /* dword jmp adds 4 bytes to frag:
950 0 extra opcode bytes, 4 displacement bytes. */
952 /* word jmp adds 2 byte2 to frag:
953 0 extra opcode bytes, 2 displacement bytes. */
956 /* COND_JUMP states. */
957 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
958 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
959 /* dword conditionals adds 5 bytes to frag:
960 1 extra opcode byte, 4 displacement bytes. */
962 /* word conditionals add 3 bytes to frag:
963 1 extra opcode byte, 2 displacement bytes. */
966 /* COND_JUMP86 states. */
967 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
968 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
969 /* dword conditionals adds 5 bytes to frag:
970 1 extra opcode byte, 4 displacement bytes. */
972 /* word conditionals add 4 bytes to frag:
973 1 displacement byte and a 3 byte long branch insn. */
977 #define ARCH(n, t, f, s) \
978 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
980 #define SUBARCH(n, e, d, s) \
981 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
982 CPU_ ## d ## _FLAGS }
983 #define VECARCH(n, e, d, v) \
984 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
985 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
987 static const arch_entry cpu_arch
[] =
989 /* Do not replace the first two entries - i386_target_format() and
990 set_cpu_arch() rely on them being there in this order. */
991 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
992 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
993 ARCH (i8086
, UNKNOWN
, NONE
, false),
994 ARCH (i186
, UNKNOWN
, 186, false),
995 ARCH (i286
, UNKNOWN
, 286, false),
996 ARCH (i386
, I386
, 386, false),
997 ARCH (i486
, I486
, 486, false),
998 ARCH (i586
, PENTIUM
, 586, false),
999 ARCH (i686
, PENTIUMPRO
, 686, false),
1000 ARCH (pentium
, PENTIUM
, 586, false),
1001 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
1002 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
1003 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
1004 ARCH (pentium4
, PENTIUM4
, P4
, false),
1005 ARCH (prescott
, NOCONA
, CORE
, false),
1006 ARCH (nocona
, NOCONA
, NOCONA
, false),
1007 ARCH (yonah
, CORE
, CORE
, true),
1008 ARCH (core
, CORE
, CORE
, false),
1009 ARCH (merom
, CORE2
, CORE2
, true),
1010 ARCH (core2
, CORE2
, CORE2
, false),
1011 ARCH (corei7
, COREI7
, COREI7
, false),
1012 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1013 ARCH (k6
, K6
, K6
, false),
1014 ARCH (k6_2
, K6
, K6_2
, false),
1015 ARCH (athlon
, ATHLON
, ATHLON
, false),
1016 ARCH (sledgehammer
, K8
, K8
, true),
1017 ARCH (opteron
, K8
, K8
, false),
1018 ARCH (k8
, K8
, K8
, false),
1019 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1020 ARCH (bdver1
, BD
, BDVER1
, false),
1021 ARCH (bdver2
, BD
, BDVER2
, false),
1022 ARCH (bdver3
, BD
, BDVER3
, false),
1023 ARCH (bdver4
, BD
, BDVER4
, false),
1024 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1025 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1026 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1027 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1028 ARCH (btver1
, BT
, BTVER1
, false),
1029 ARCH (btver2
, BT
, BTVER2
, false),
1031 SUBARCH (8087, 8087, ANY_8087
, false),
1032 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1033 SUBARCH (287, 287, ANY_287
, false),
1034 SUBARCH (387, 387, ANY_387
, false),
1035 SUBARCH (687, 687, ANY_687
, false),
1036 SUBARCH (cmov
, CMOV
, CMOV
, false),
1037 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1038 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1039 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1040 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1041 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1042 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1043 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1044 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1045 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1046 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1047 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1048 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1049 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1050 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1051 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1052 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1053 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1054 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1055 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1056 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1057 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1058 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1059 SUBARCH (smx
, SMX
, SMX
, false),
1060 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1061 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1062 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1063 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1064 SUBARCH (aes
, AES
, ANY_AES
, false),
1065 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1066 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1067 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1068 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1069 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1070 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1071 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1072 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1073 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1074 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1075 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1076 SUBARCH (cx16
, CX16
, CX16
, false),
1077 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1078 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1079 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1080 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1081 SUBARCH (hle
, HLE
, HLE
, false),
1082 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1083 SUBARCH (tsx
, TSX
, TSX
, false),
1084 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1085 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1086 SUBARCH (nop
, NOP
, NOP
, false),
1087 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1088 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1089 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1090 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1091 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1092 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1093 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1094 SUBARCH (abm
, ABM
, ABM
, false),
1095 SUBARCH (bmi
, BMI
, BMI
, false),
1096 SUBARCH (tbm
, TBM
, TBM
, false),
1097 SUBARCH (adx
, ADX
, ADX
, false),
1098 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1099 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1100 SUBARCH (smap
, SMAP
, SMAP
, false),
1101 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1102 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1103 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1104 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1105 SUBARCH (se1
, SE1
, SE1
, false),
1106 SUBARCH (clwb
, CLWB
, CLWB
, false),
1107 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1108 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1109 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1110 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1111 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1112 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1113 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1114 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1115 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1116 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1117 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1118 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1119 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1120 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1121 SUBARCH (ibt
, IBT
, IBT
, false),
1122 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1123 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1124 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1125 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1126 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1127 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1128 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1129 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1130 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1131 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1132 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1133 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1134 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1135 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1136 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1137 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1138 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1139 ANY_AVX512_VP2INTERSECT
, reset
),
1140 SUBARCH (tdx
, TDX
, TDX
, false),
1141 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1142 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1143 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1144 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1145 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1146 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1147 SUBARCH (kl
, KL
, ANY_KL
, false),
1148 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1149 SUBARCH (uintr
, UINTR
, UINTR
, false),
1150 SUBARCH (hreset
, HRESET
, HRESET
, false),
1151 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1152 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1153 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1154 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1155 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1156 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1157 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1158 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1159 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1160 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1161 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1162 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1163 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1164 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1165 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1166 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1167 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1168 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1175 /* Like s_lcomm_internal in gas/read.c but the alignment string
1176 is allowed to be optional. */
1179 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1186 && *input_line_pointer
== ',')
1188 align
= parse_align (needs_align
- 1);
1190 if (align
== (addressT
) -1)
1205 bss_alloc (symbolP
, size
, align
);
1210 pe_lcomm (int needs_align
)
1212 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1216 const pseudo_typeS md_pseudo_table
[] =
1218 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1219 {"align", s_align_bytes
, 0},
1221 {"align", s_align_ptwo
, 0},
1223 {"arch", set_cpu_arch
, 0},
1227 {"lcomm", pe_lcomm
, 1},
1229 {"ffloat", float_cons
, 'f'},
1230 {"dfloat", float_cons
, 'd'},
1231 {"tfloat", float_cons
, 'x'},
1232 {"hfloat", float_cons
, 'h'},
1233 {"bfloat16", float_cons
, 'b'},
1235 {"slong", signed_cons
, 4},
1236 {"insn", s_insn
, 0},
1237 {"noopt", s_ignore
, 0},
1238 {"optim", s_ignore
, 0},
1239 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1240 {"code16", set_code_flag
, CODE_16BIT
},
1241 {"code32", set_code_flag
, CODE_32BIT
},
1243 {"code64", set_code_flag
, CODE_64BIT
},
1245 {"intel_syntax", set_intel_syntax
, 1},
1246 {"att_syntax", set_intel_syntax
, 0},
1247 {"intel_mnemonic", set_intel_mnemonic
, 1},
1248 {"att_mnemonic", set_intel_mnemonic
, 0},
1249 {"allow_index_reg", set_allow_index_reg
, 1},
1250 {"disallow_index_reg", set_allow_index_reg
, 0},
1251 {"sse_check", set_check
, 0},
1252 {"operand_check", set_check
, 1},
1253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1254 {"largecomm", handle_large_common
, 0},
1256 {"file", dwarf2_directive_file
, 0},
1257 {"loc", dwarf2_directive_loc
, 0},
1258 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1261 {"secrel32", pe_directive_secrel
, 0},
1262 {"secidx", pe_directive_secidx
, 0},
1267 /* For interface with expression (). */
1268 extern char *input_line_pointer
;
1270 /* Hash table for instruction mnemonic lookup. */
1271 static htab_t op_hash
;
1273 /* Hash table for register lookup. */
1274 static htab_t reg_hash
;
1276 /* Various efficient no-op patterns for aligning code labels.
1277 Note: Don't try to assemble the instructions in the comments.
1278 0L and 0w are not legal. */
1279 static const unsigned char f32_1
[] =
1281 static const unsigned char f32_2
[] =
1282 {0x66,0x90}; /* xchg %ax,%ax */
1283 static const unsigned char f32_3
[] =
1284 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1285 static const unsigned char f32_4
[] =
1286 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1287 static const unsigned char f32_6
[] =
1288 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1289 static const unsigned char f32_7
[] =
1290 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1291 static const unsigned char f16_3
[] =
1292 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1293 static const unsigned char f16_4
[] =
1294 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1295 static const unsigned char jump_disp8
[] =
1296 {0xeb}; /* jmp disp8 */
1297 static const unsigned char jump32_disp32
[] =
1298 {0xe9}; /* jmp disp32 */
1299 static const unsigned char jump16_disp32
[] =
1300 {0x66,0xe9}; /* jmp disp32 */
1301 /* 32-bit NOPs patterns. */
1302 static const unsigned char *const f32_patt
[] = {
1303 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1305 /* 16-bit NOPs patterns. */
1306 static const unsigned char *const f16_patt
[] = {
1307 f32_1
, f32_2
, f16_3
, f16_4
1309 /* nopl (%[re]ax) */
1310 static const unsigned char alt_3
[] =
1312 /* nopl 0(%[re]ax) */
1313 static const unsigned char alt_4
[] =
1314 {0x0f,0x1f,0x40,0x00};
1315 /* nopl 0(%[re]ax,%[re]ax,1) */
1316 static const unsigned char alt_5
[] =
1317 {0x0f,0x1f,0x44,0x00,0x00};
1318 /* nopw 0(%[re]ax,%[re]ax,1) */
1319 static const unsigned char alt_6
[] =
1320 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1321 /* nopl 0L(%[re]ax) */
1322 static const unsigned char alt_7
[] =
1323 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1324 /* nopl 0L(%[re]ax,%[re]ax,1) */
1325 static const unsigned char alt_8
[] =
1326 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1327 /* nopw 0L(%[re]ax,%[re]ax,1) */
1328 static const unsigned char alt_9
[] =
1329 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1330 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1331 static const unsigned char alt_10
[] =
1332 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1333 /* data16 nopw %cs:0L(%eax,%eax,1) */
1334 static const unsigned char alt_11
[] =
1335 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1336 /* 32-bit and 64-bit NOPs patterns. */
1337 static const unsigned char *const alt_patt
[] = {
1338 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1339 alt_9
, alt_10
, alt_11
1342 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1343 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1346 i386_output_nops (char *where
, const unsigned char *const *patt
,
1347 int count
, int max_single_nop_size
)
1350 /* Place the longer NOP first. */
1353 const unsigned char *nops
;
1355 if (max_single_nop_size
< 1)
1357 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1358 max_single_nop_size
);
1362 nops
= patt
[max_single_nop_size
- 1];
1364 /* Use the smaller one if the requsted one isn't available. */
1367 max_single_nop_size
--;
1368 nops
= patt
[max_single_nop_size
- 1];
1371 last
= count
% max_single_nop_size
;
1374 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1375 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1379 nops
= patt
[last
- 1];
1382 /* Use the smaller one plus one-byte NOP if the needed one
1385 nops
= patt
[last
- 1];
1386 memcpy (where
+ offset
, nops
, last
);
1387 where
[offset
+ last
] = *patt
[0];
1390 memcpy (where
+ offset
, nops
, last
);
1395 fits_in_imm7 (offsetT num
)
1397 return (num
& 0x7f) == num
;
1401 fits_in_imm31 (offsetT num
)
1403 return (num
& 0x7fffffff) == num
;
1406 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1407 single NOP instruction LIMIT. */
1410 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1412 const unsigned char *const *patt
= NULL
;
1413 int max_single_nop_size
;
1414 /* Maximum number of NOPs before switching to jump over NOPs. */
1415 int max_number_of_nops
;
1417 switch (fragP
->fr_type
)
1422 case rs_machine_dependent
:
1423 /* Allow NOP padding for jumps and calls. */
1424 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1425 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1432 /* We need to decide which NOP sequence to use for 32bit and
1433 64bit. When -mtune= is used:
1435 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1436 PROCESSOR_GENERIC32, f32_patt will be used.
1437 2. For the rest, alt_patt will be used.
1439 When -mtune= isn't used, alt_patt will be used if
1440 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1443 When -march= or .arch is used, we can't use anything beyond
1444 cpu_arch_isa_flags. */
1446 if (flag_code
== CODE_16BIT
)
1449 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1450 /* Limit number of NOPs to 2 in 16-bit mode. */
1451 max_number_of_nops
= 2;
1455 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1457 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1458 switch (cpu_arch_tune
)
1460 case PROCESSOR_UNKNOWN
:
1461 /* We use cpu_arch_isa_flags to check if we SHOULD
1462 optimize with nops. */
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_PENTIUM4
:
1469 case PROCESSOR_NOCONA
:
1470 case PROCESSOR_CORE
:
1471 case PROCESSOR_CORE2
:
1472 case PROCESSOR_COREI7
:
1473 case PROCESSOR_GENERIC64
:
1475 case PROCESSOR_ATHLON
:
1477 case PROCESSOR_AMDFAM10
:
1479 case PROCESSOR_ZNVER
:
1483 case PROCESSOR_I386
:
1484 case PROCESSOR_I486
:
1485 case PROCESSOR_PENTIUM
:
1486 case PROCESSOR_PENTIUMPRO
:
1487 case PROCESSOR_IAMCU
:
1488 case PROCESSOR_GENERIC32
:
1491 case PROCESSOR_NONE
:
1497 switch (fragP
->tc_frag_data
.tune
)
1499 case PROCESSOR_UNKNOWN
:
1500 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1501 PROCESSOR_UNKNOWN. */
1505 case PROCESSOR_I386
:
1506 case PROCESSOR_I486
:
1507 case PROCESSOR_PENTIUM
:
1508 case PROCESSOR_IAMCU
:
1510 case PROCESSOR_ATHLON
:
1512 case PROCESSOR_AMDFAM10
:
1514 case PROCESSOR_ZNVER
:
1516 case PROCESSOR_GENERIC32
:
1517 /* We use cpu_arch_isa_flags to check if we CAN optimize
1519 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1524 case PROCESSOR_PENTIUMPRO
:
1525 case PROCESSOR_PENTIUM4
:
1526 case PROCESSOR_NOCONA
:
1527 case PROCESSOR_CORE
:
1528 case PROCESSOR_CORE2
:
1529 case PROCESSOR_COREI7
:
1530 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1535 case PROCESSOR_GENERIC64
:
1538 case PROCESSOR_NONE
:
1543 if (patt
== f32_patt
)
1545 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1546 /* Limit number of NOPs to 2 for older processors. */
1547 max_number_of_nops
= 2;
1551 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1552 /* Limit number of NOPs to 7 for newer processors. */
1553 max_number_of_nops
= 7;
1558 limit
= max_single_nop_size
;
1560 if (fragP
->fr_type
== rs_fill_nop
)
1562 /* Output NOPs for .nop directive. */
1563 if (limit
> max_single_nop_size
)
1565 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1566 _("invalid single nop size: %d "
1567 "(expect within [0, %d])"),
1568 limit
, max_single_nop_size
);
1572 else if (fragP
->fr_type
!= rs_machine_dependent
)
1573 fragP
->fr_var
= count
;
1575 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1577 /* Generate jump over NOPs. */
1578 offsetT disp
= count
- 2;
1579 if (fits_in_imm7 (disp
))
1581 /* Use "jmp disp8" if possible. */
1583 where
[0] = jump_disp8
[0];
1589 unsigned int size_of_jump
;
1591 if (flag_code
== CODE_16BIT
)
1593 where
[0] = jump16_disp32
[0];
1594 where
[1] = jump16_disp32
[1];
1599 where
[0] = jump32_disp32
[0];
1603 count
-= size_of_jump
+ 4;
1604 if (!fits_in_imm31 (count
))
1606 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1607 _("jump over nop padding out of range"));
1611 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1612 where
+= size_of_jump
+ 4;
1616 /* Generate multiple NOPs. */
1617 i386_output_nops (where
, patt
, count
, limit
);
1621 operand_type_all_zero (const union i386_operand_type
*x
)
1623 switch (ARRAY_SIZE(x
->array
))
1634 return !x
->array
[0];
1641 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1643 switch (ARRAY_SIZE(x
->array
))
1659 x
->bitfield
.class = ClassNone
;
1660 x
->bitfield
.instance
= InstanceNone
;
1664 operand_type_equal (const union i386_operand_type
*x
,
1665 const union i386_operand_type
*y
)
1667 switch (ARRAY_SIZE(x
->array
))
1670 if (x
->array
[2] != y
->array
[2])
1674 if (x
->array
[1] != y
->array
[1])
1678 return x
->array
[0] == y
->array
[0];
1686 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1690 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1691 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1692 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1693 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1694 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1695 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1696 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1697 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1698 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1699 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1701 gas_assert (cpu
< CpuAttrEnums
);
1703 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1706 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1708 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1709 i386_cpu_flags f
= { .array
[0] = 0 };
1711 switch (ARRAY_SIZE(a
.array
))
1714 f
.array
[CpuAttrEnums
/ bps
]
1715 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1716 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1717 f
.array
[CpuAttrEnums
/ bps
+ 1]
1718 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1725 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1731 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1733 switch (ARRAY_SIZE(x
->array
))
1752 return !x
->array
[0];
1759 cpu_flags_equal (const union i386_cpu_flags
*x
,
1760 const union i386_cpu_flags
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[4] != y
->array
[4])
1769 if (x
->array
[3] != y
->array
[3])
1773 if (x
->array
[2] != y
->array
[2])
1777 if (x
->array
[1] != y
->array
[1])
1781 return x
->array
[0] == y
->array
[0];
1789 cpu_flags_check_cpu64 (const insn_template
*t
)
1791 return flag_code
== CODE_64BIT
1792 ? !t
->cpu
.bitfield
.cpuno64
1793 : !t
->cpu
.bitfield
.cpu64
;
1796 static INLINE i386_cpu_flags
1797 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[4] &= y
.array
[4];
1805 x
.array
[3] &= y
.array
[3];
1808 x
.array
[2] &= y
.array
[2];
1811 x
.array
[1] &= y
.array
[1];
1814 x
.array
[0] &= y
.array
[0];
1822 static INLINE i386_cpu_flags
1823 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1825 switch (ARRAY_SIZE (x
.array
))
1828 x
.array
[4] |= y
.array
[4];
1831 x
.array
[3] |= y
.array
[3];
1834 x
.array
[2] |= y
.array
[2];
1837 x
.array
[1] |= y
.array
[1];
1840 x
.array
[0] |= y
.array
[0];
1848 static INLINE i386_cpu_flags
1849 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1851 switch (ARRAY_SIZE (x
.array
))
1854 x
.array
[4] &= ~y
.array
[4];
1857 x
.array
[3] &= ~y
.array
[3];
1860 x
.array
[2] &= ~y
.array
[2];
1863 x
.array
[1] &= ~y
.array
[1];
1866 x
.array
[0] &= ~y
.array
[0];
1874 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1876 static INLINE
bool need_evex_encoding (void)
1878 return i
.vec_encoding
== vex_encoding_evex
1879 || i
.vec_encoding
== vex_encoding_evex512
1883 #define CPU_FLAGS_ARCH_MATCH 0x1
1884 #define CPU_FLAGS_64BIT_MATCH 0x2
1886 #define CPU_FLAGS_PERFECT_MATCH \
1887 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1889 /* Return CPU flags match bits. */
1892 cpu_flags_match (const insn_template
*t
)
1894 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1895 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1897 x
.bitfield
.cpu64
= 0;
1898 x
.bitfield
.cpuno64
= 0;
1900 if (cpu_flags_all_zero (&x
))
1902 /* This instruction is available on all archs. */
1903 match
|= CPU_FLAGS_ARCH_MATCH
;
1907 /* This instruction is available only on some archs. */
1908 i386_cpu_flags cpu
= cpu_arch_flags
;
1910 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1911 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1913 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1914 know that EVEX encoding will be needed. */
1915 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1916 && x
.bitfield
.cpuavx512f
)
1918 if (need_evex_encoding ())
1920 x
.bitfield
.cpuavx
= 0;
1921 x
.bitfield
.cpuavx2
= 0;
1923 /* need_evex_encoding() isn't reliable before operands were
1925 else if (i
.operands
)
1927 x
.bitfield
.cpuavx512f
= 0;
1928 x
.bitfield
.cpuavx512vl
= 0;
1929 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1930 x
.bitfield
.cpuavx
= 0;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 /* AVX and AVX2 present at the same time express an operand size
1941 dependency - strip AVX2 for the purposes here. The operand size
1942 dependent check occurs in check_vecOperands(). */
1943 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1944 x
.bitfield
.cpuavx2
= 0;
1946 cpu
= cpu_flags_and (x
, cpu
);
1947 if (!cpu_flags_all_zero (&cpu
))
1949 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1951 if ((need_evex_encoding ()
1952 ? cpu
.bitfield
.cpuavx512f
1953 : cpu
.bitfield
.cpuavx
)
1954 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1955 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1956 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1957 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1958 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1959 match
|= CPU_FLAGS_ARCH_MATCH
;
1961 else if (x
.bitfield
.cpuavx
)
1963 /* We need to check a few extra flags with AVX. */
1964 if (cpu
.bitfield
.cpuavx
1965 && (!t
->opcode_modifier
.sse2avx
1966 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1967 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1968 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1969 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1970 match
|= CPU_FLAGS_ARCH_MATCH
;
1972 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1973 match
|= CPU_FLAGS_ARCH_MATCH
;
1974 else if (x
.bitfield
.cpuavx512f
)
1976 /* We need to check a few extra flags with AVX512F. */
1977 if (cpu
.bitfield
.cpuavx512f
1978 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1979 match
|= CPU_FLAGS_ARCH_MATCH
;
1982 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 static INLINE i386_operand_type
1989 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1991 if (x
.bitfield
.class != y
.bitfield
.class)
1992 x
.bitfield
.class = ClassNone
;
1993 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1994 x
.bitfield
.instance
= InstanceNone
;
1996 switch (ARRAY_SIZE (x
.array
))
1999 x
.array
[2] &= y
.array
[2];
2002 x
.array
[1] &= y
.array
[1];
2005 x
.array
[0] &= y
.array
[0];
2013 static INLINE i386_operand_type
2014 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2016 gas_assert (y
.bitfield
.class == ClassNone
);
2017 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2019 switch (ARRAY_SIZE (x
.array
))
2022 x
.array
[2] &= ~y
.array
[2];
2025 x
.array
[1] &= ~y
.array
[1];
2028 x
.array
[0] &= ~y
.array
[0];
2036 static INLINE i386_operand_type
2037 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2039 gas_assert (x
.bitfield
.class == ClassNone
||
2040 y
.bitfield
.class == ClassNone
||
2041 x
.bitfield
.class == y
.bitfield
.class);
2042 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2043 y
.bitfield
.instance
== InstanceNone
||
2044 x
.bitfield
.instance
== y
.bitfield
.instance
);
2046 switch (ARRAY_SIZE (x
.array
))
2049 x
.array
[2] |= y
.array
[2];
2052 x
.array
[1] |= y
.array
[1];
2055 x
.array
[0] |= y
.array
[0];
2063 static INLINE i386_operand_type
2064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2066 gas_assert (y
.bitfield
.class == ClassNone
);
2067 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2069 switch (ARRAY_SIZE (x
.array
))
2072 x
.array
[2] ^= y
.array
[2];
2075 x
.array
[1] ^= y
.array
[1];
2078 x
.array
[0] ^= y
.array
[0];
2086 static const i386_operand_type anydisp
= {
2087 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2099 operand_type_check (i386_operand_type t
, enum operand_type c
)
2104 return t
.bitfield
.class == Reg
;
2107 return (t
.bitfield
.imm8
2111 || t
.bitfield
.imm32s
2112 || t
.bitfield
.imm64
);
2115 return (t
.bitfield
.disp8
2116 || t
.bitfield
.disp16
2117 || t
.bitfield
.disp32
2118 || t
.bitfield
.disp64
);
2121 return (t
.bitfield
.disp8
2122 || t
.bitfield
.disp16
2123 || t
.bitfield
.disp32
2124 || t
.bitfield
.disp64
2125 || t
.bitfield
.baseindex
);
2134 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2135 between operand GIVEN and opeand WANTED for instruction template T. */
2138 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2141 return !((i
.types
[given
].bitfield
.byte
2142 && !t
->operand_types
[wanted
].bitfield
.byte
)
2143 || (i
.types
[given
].bitfield
.word
2144 && !t
->operand_types
[wanted
].bitfield
.word
)
2145 || (i
.types
[given
].bitfield
.dword
2146 && !t
->operand_types
[wanted
].bitfield
.dword
)
2147 || (i
.types
[given
].bitfield
.qword
2148 && (!t
->operand_types
[wanted
].bitfield
.qword
2149 /* Don't allow 64-bit (memory) operands outside of 64-bit
2150 mode, when they're used where a 64-bit GPR could also
2151 be used. Checking is needed for Intel Syntax only. */
2153 && flag_code
!= CODE_64BIT
2154 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2155 || t
->operand_types
[wanted
].bitfield
.class == Accum
2156 || t
->opcode_modifier
.isstring
))))
2157 || (i
.types
[given
].bitfield
.tbyte
2158 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2161 /* Return 1 if there is no conflict in SIMD register between operand
2162 GIVEN and opeand WANTED for instruction template T. */
2165 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2168 return !((i
.types
[given
].bitfield
.xmmword
2169 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2170 || (i
.types
[given
].bitfield
.ymmword
2171 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2172 || (i
.types
[given
].bitfield
.zmmword
2173 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2174 || (i
.types
[given
].bitfield
.tmmword
2175 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2178 /* Return 1 if there is no conflict in any size between operand GIVEN
2179 and opeand WANTED for instruction template T. */
2182 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2185 return (match_operand_size (t
, wanted
, given
)
2186 && !((i
.types
[given
].bitfield
.unspecified
2187 && !i
.broadcast
.type
2188 && !i
.broadcast
.bytes
2189 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2190 || (i
.types
[given
].bitfield
.fword
2191 && !t
->operand_types
[wanted
].bitfield
.fword
)
2192 /* For scalar opcode templates to allow register and memory
2193 operands at the same time, some special casing is needed
2194 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2195 down-conversion vpmov*. */
2196 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2197 && t
->operand_types
[wanted
].bitfield
.byte
2198 + t
->operand_types
[wanted
].bitfield
.word
2199 + t
->operand_types
[wanted
].bitfield
.dword
2200 + t
->operand_types
[wanted
].bitfield
.qword
2201 > !!t
->opcode_modifier
.broadcast
)
2202 ? (i
.types
[given
].bitfield
.xmmword
2203 || i
.types
[given
].bitfield
.ymmword
2204 || i
.types
[given
].bitfield
.zmmword
)
2205 : !match_simd_size(t
, wanted
, given
))));
2208 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2209 operands for instruction template T, and it has MATCH_REVERSE set if there
2210 is no size conflict on any operands for the template with operands reversed
2211 (and the template allows for reversing in the first place). */
2213 #define MATCH_STRAIGHT 1
2214 #define MATCH_REVERSE 2
2216 static INLINE
unsigned int
2217 operand_size_match (const insn_template
*t
)
2219 unsigned int j
, match
= MATCH_STRAIGHT
;
2221 /* Don't check non-absolute jump instructions. */
2222 if (t
->opcode_modifier
.jump
2223 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2226 /* Check memory and accumulator operand size. */
2227 for (j
= 0; j
< i
.operands
; j
++)
2229 if (i
.types
[j
].bitfield
.class != Reg
2230 && i
.types
[j
].bitfield
.class != RegSIMD
2231 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2234 if (t
->operand_types
[j
].bitfield
.class == Reg
2235 && !match_operand_size (t
, j
, j
))
2241 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2242 && !match_simd_size (t
, j
, j
))
2248 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2249 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2255 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2262 if (!t
->opcode_modifier
.d
)
2265 /* Check reverse. */
2266 gas_assert (i
.operands
>= 2);
2268 for (j
= 0; j
< i
.operands
; j
++)
2270 unsigned int given
= i
.operands
- j
- 1;
2272 /* For FMA4 and XOP insns VEX.W controls just the first two
2273 register operands. */
2274 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2275 given
= j
< 2 ? 1 - j
: j
;
2277 if (t
->operand_types
[j
].bitfield
.class == Reg
2278 && !match_operand_size (t
, j
, given
))
2281 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2282 && !match_simd_size (t
, j
, given
))
2285 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2286 && (!match_operand_size (t
, j
, given
)
2287 || !match_simd_size (t
, j
, given
)))
2290 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2294 return match
| MATCH_REVERSE
;
2298 operand_type_match (i386_operand_type overlap
,
2299 i386_operand_type given
)
2301 i386_operand_type temp
= overlap
;
2303 temp
.bitfield
.unspecified
= 0;
2304 temp
.bitfield
.byte
= 0;
2305 temp
.bitfield
.word
= 0;
2306 temp
.bitfield
.dword
= 0;
2307 temp
.bitfield
.fword
= 0;
2308 temp
.bitfield
.qword
= 0;
2309 temp
.bitfield
.tbyte
= 0;
2310 temp
.bitfield
.xmmword
= 0;
2311 temp
.bitfield
.ymmword
= 0;
2312 temp
.bitfield
.zmmword
= 0;
2313 temp
.bitfield
.tmmword
= 0;
2314 if (operand_type_all_zero (&temp
))
2317 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2321 i
.error
= operand_type_mismatch
;
2325 /* If given types g0 and g1 are registers they must be of the same type
2326 unless the expected operand type register overlap is null.
2327 Intel syntax sized memory operands are also checked here. */
2330 operand_type_register_match (i386_operand_type g0
,
2331 i386_operand_type t0
,
2332 i386_operand_type g1
,
2333 i386_operand_type t1
)
2335 if (g0
.bitfield
.class != Reg
2336 && g0
.bitfield
.class != RegSIMD
2337 && (g0
.bitfield
.unspecified
2338 || !operand_type_check (g0
, anymem
)))
2341 if (g1
.bitfield
.class != Reg
2342 && g1
.bitfield
.class != RegSIMD
2343 && (g1
.bitfield
.unspecified
2344 || !operand_type_check (g1
, anymem
)))
2347 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2348 && g0
.bitfield
.word
== g1
.bitfield
.word
2349 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2350 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2351 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2352 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2353 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2356 /* If expectations overlap in no more than a single size, all is fine. */
2357 g0
= operand_type_and (t0
, t1
);
2358 if (g0
.bitfield
.byte
2362 + g0
.bitfield
.xmmword
2363 + g0
.bitfield
.ymmword
2364 + g0
.bitfield
.zmmword
<= 1)
2367 i
.error
= register_type_mismatch
;
2372 static INLINE
unsigned int
2373 register_number (const reg_entry
*r
)
2375 unsigned int nr
= r
->reg_num
;
2377 if (r
->reg_flags
& RegRex
)
2380 if (r
->reg_flags
& RegVRex
)
2386 static INLINE
unsigned int
2387 mode_from_disp_size (i386_operand_type t
)
2389 if (t
.bitfield
.disp8
)
2391 else if (t
.bitfield
.disp16
2392 || t
.bitfield
.disp32
)
2399 fits_in_signed_byte (addressT num
)
2401 return num
+ 0x80 <= 0xff;
2405 fits_in_unsigned_byte (addressT num
)
2411 fits_in_unsigned_word (addressT num
)
2413 return num
<= 0xffff;
2417 fits_in_signed_word (addressT num
)
2419 return num
+ 0x8000 <= 0xffff;
2423 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2428 return num
+ 0x80000000 <= 0xffffffff;
2430 } /* fits_in_signed_long() */
2433 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2438 return num
<= 0xffffffff;
2440 } /* fits_in_unsigned_long() */
2442 static INLINE valueT
extend_to_32bit_address (addressT num
)
2445 if (fits_in_unsigned_long(num
))
2446 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2448 if (!fits_in_signed_long (num
))
2449 return num
& 0xffffffff;
2456 fits_in_disp8 (offsetT num
)
2458 int shift
= i
.memshift
;
2464 mask
= (1 << shift
) - 1;
2466 /* Return 0 if NUM isn't properly aligned. */
2470 /* Check if NUM will fit in 8bit after shift. */
2471 return fits_in_signed_byte (num
>> shift
);
2475 fits_in_imm4 (offsetT num
)
2477 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2478 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2481 static i386_operand_type
2482 smallest_imm_type (offsetT num
)
2484 i386_operand_type t
;
2486 operand_type_set (&t
, 0);
2487 t
.bitfield
.imm64
= 1;
2489 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2491 /* This code is disabled on the 486 because all the Imm1 forms
2492 in the opcode table are slower on the i486. They're the
2493 versions with the implicitly specified single-position
2494 displacement, which has another syntax if you really want to
2496 t
.bitfield
.imm1
= 1;
2497 t
.bitfield
.imm8
= 1;
2498 t
.bitfield
.imm8s
= 1;
2499 t
.bitfield
.imm16
= 1;
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_signed_byte (num
))
2505 if (fits_in_unsigned_byte (num
))
2506 t
.bitfield
.imm8
= 1;
2507 t
.bitfield
.imm8s
= 1;
2508 t
.bitfield
.imm16
= 1;
2509 t
.bitfield
.imm32
= 1;
2510 t
.bitfield
.imm32s
= 1;
2512 else if (fits_in_unsigned_byte (num
))
2514 t
.bitfield
.imm8
= 1;
2515 t
.bitfield
.imm16
= 1;
2516 t
.bitfield
.imm32
= 1;
2517 t
.bitfield
.imm32s
= 1;
2519 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2521 t
.bitfield
.imm16
= 1;
2522 t
.bitfield
.imm32
= 1;
2523 t
.bitfield
.imm32s
= 1;
2525 else if (fits_in_signed_long (num
))
2527 t
.bitfield
.imm32
= 1;
2528 t
.bitfield
.imm32s
= 1;
2530 else if (fits_in_unsigned_long (num
))
2531 t
.bitfield
.imm32
= 1;
2537 offset_in_range (offsetT val
, int size
)
2543 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2544 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2546 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2548 case sizeof (val
): return val
;
2552 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2553 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2554 (uint64_t) val
, (uint64_t) (val
& mask
));
2559 static INLINE
const char *insn_name (const insn_template
*t
)
2561 return &i386_mnemonics
[t
->mnem_off
];
2574 a. PREFIX_EXIST if attempting to add a prefix where one from the
2575 same class already exists.
2576 b. PREFIX_LOCK if lock prefix is added.
2577 c. PREFIX_REP if rep/repne prefix is added.
2578 d. PREFIX_DS if ds prefix is added.
2579 e. PREFIX_OTHER if other prefix is added.
2582 static enum PREFIX_GROUP
2583 add_prefix (unsigned int prefix
)
2585 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2588 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2589 && flag_code
== CODE_64BIT
)
2591 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2592 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2593 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2594 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2605 case DS_PREFIX_OPCODE
:
2608 case CS_PREFIX_OPCODE
:
2609 case ES_PREFIX_OPCODE
:
2610 case FS_PREFIX_OPCODE
:
2611 case GS_PREFIX_OPCODE
:
2612 case SS_PREFIX_OPCODE
:
2616 case REPNE_PREFIX_OPCODE
:
2617 case REPE_PREFIX_OPCODE
:
2622 case LOCK_PREFIX_OPCODE
:
2631 case ADDR_PREFIX_OPCODE
:
2635 case DATA_PREFIX_OPCODE
:
2639 if (i
.prefix
[q
] != 0)
2647 i
.prefix
[q
] |= prefix
;
2650 as_bad (_("same type of prefix used twice"));
2656 update_code_flag (int value
, int check
)
2658 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2660 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2662 as_error (_("64bit mode not supported on `%s'."),
2663 cpu_arch_name
? cpu_arch_name
: default_arch
);
2667 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2669 as_error (_("32bit mode not supported on `%s'."),
2670 cpu_arch_name
? cpu_arch_name
: default_arch
);
2674 flag_code
= (enum flag_code
) value
;
2676 stackop_size
= '\0';
2680 set_code_flag (int value
)
2682 update_code_flag (value
, 0);
2686 set_16bit_gcc_code_flag (int new_code_flag
)
2688 flag_code
= (enum flag_code
) new_code_flag
;
2689 if (flag_code
!= CODE_16BIT
)
2691 stackop_size
= LONG_MNEM_SUFFIX
;
2695 set_intel_syntax (int syntax_flag
)
2697 /* Find out if register prefixing is specified. */
2698 int ask_naked_reg
= 0;
2701 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2704 int e
= get_symbol_name (&string
);
2706 if (strcmp (string
, "prefix") == 0)
2708 else if (strcmp (string
, "noprefix") == 0)
2711 as_bad (_("bad argument to syntax directive."));
2712 (void) restore_line_pointer (e
);
2714 demand_empty_rest_of_line ();
2716 intel_syntax
= syntax_flag
;
2718 if (ask_naked_reg
== 0)
2719 allow_naked_reg
= (intel_syntax
2720 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2722 allow_naked_reg
= (ask_naked_reg
< 0);
2724 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2726 register_prefix
= allow_naked_reg
? "" : "%";
2730 set_intel_mnemonic (int mnemonic_flag
)
2732 intel_mnemonic
= mnemonic_flag
;
2736 set_allow_index_reg (int flag
)
2738 allow_index_reg
= flag
;
2742 set_check (int what
)
2744 enum check_kind
*kind
;
2749 kind
= &operand_check
;
2760 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2763 int e
= get_symbol_name (&string
);
2765 if (strcmp (string
, "none") == 0)
2767 else if (strcmp (string
, "warning") == 0)
2768 *kind
= check_warning
;
2769 else if (strcmp (string
, "error") == 0)
2770 *kind
= check_error
;
2772 as_bad (_("bad argument to %s_check directive."), str
);
2773 (void) restore_line_pointer (e
);
2776 as_bad (_("missing argument for %s_check directive"), str
);
2778 demand_empty_rest_of_line ();
2782 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2783 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2786 static const char *arch
;
2788 /* Intel MCU is only supported on ELF. */
2794 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2795 use default_arch. */
2796 arch
= cpu_arch_name
;
2798 arch
= default_arch
;
2801 /* If we are targeting Intel MCU, we must enable it. */
2802 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2803 == new_flag
.bitfield
.cpuiamcu
)
2806 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2811 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2813 if (cpu_sub_arch_name
)
2814 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2815 pfx
, name
, (const char *) NULL
);
2817 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2820 static void isa_enable (unsigned int idx
)
2822 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2824 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2826 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2827 cpu_arch_flags
= flags
;
2830 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2833 static void isa_disable (unsigned int idx
)
2835 i386_cpu_flags flags
2836 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2838 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2840 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2841 cpu_arch_flags
= flags
;
2845 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2849 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2851 typedef struct arch_stack_entry
2853 const struct arch_stack_entry
*prev
;
2856 i386_cpu_flags flags
;
2857 i386_cpu_flags isa_flags
;
2858 enum processor_type isa
;
2859 enum flag_code flag_code
;
2860 unsigned int vector_size
;
2862 bool no_cond_jump_promotion
;
2864 static const arch_stack_entry
*arch_stack_top
;
2872 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2874 as_bad (_("missing cpu architecture"));
2875 input_line_pointer
++;
2879 e
= get_symbol_name (&s
);
2882 if (strcmp (string
, "push") == 0)
2884 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2886 top
->name
= cpu_arch_name
;
2887 if (cpu_sub_arch_name
)
2888 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2890 top
->sub_name
= NULL
;
2891 top
->flags
= cpu_arch_flags
;
2892 top
->isa
= cpu_arch_isa
;
2893 top
->isa_flags
= cpu_arch_isa_flags
;
2894 top
->flag_code
= flag_code
;
2895 top
->vector_size
= vector_size
;
2896 top
->stackop_size
= stackop_size
;
2897 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2899 top
->prev
= arch_stack_top
;
2900 arch_stack_top
= top
;
2902 (void) restore_line_pointer (e
);
2903 demand_empty_rest_of_line ();
2907 if (strcmp (string
, "pop") == 0)
2909 const arch_stack_entry
*top
= arch_stack_top
;
2912 as_bad (_(".arch stack is empty"));
2913 else if (top
->flag_code
!= flag_code
2914 || top
->stackop_size
!= stackop_size
)
2916 static const unsigned int bits
[] = {
2922 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2923 bits
[top
->flag_code
],
2924 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2928 arch_stack_top
= top
->prev
;
2930 cpu_arch_name
= top
->name
;
2931 free (cpu_sub_arch_name
);
2932 cpu_sub_arch_name
= top
->sub_name
;
2933 cpu_arch_flags
= top
->flags
;
2934 cpu_arch_isa
= top
->isa
;
2935 cpu_arch_isa_flags
= top
->isa_flags
;
2936 vector_size
= top
->vector_size
;
2937 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2942 (void) restore_line_pointer (e
);
2943 demand_empty_rest_of_line ();
2947 if (strcmp (string
, "default") == 0)
2949 if (strcmp (default_arch
, "iamcu") == 0)
2950 string
= default_arch
;
2953 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2955 cpu_arch_name
= NULL
;
2956 free (cpu_sub_arch_name
);
2957 cpu_sub_arch_name
= NULL
;
2958 cpu_arch_flags
= cpu_unknown_flags
;
2959 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2960 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2961 if (!cpu_arch_tune_set
)
2963 cpu_arch_tune
= cpu_arch_isa
;
2964 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2967 vector_size
= VSZ_DEFAULT
;
2969 j
= ARRAY_SIZE (cpu_arch
) + 1;
2973 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2975 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2976 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2980 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2982 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2984 as_bad (_("64bit mode not supported on `%s'."),
2986 (void) restore_line_pointer (e
);
2987 ignore_rest_of_line ();
2991 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2993 as_bad (_("32bit mode not supported on `%s'."),
2995 (void) restore_line_pointer (e
);
2996 ignore_rest_of_line ();
3000 cpu_arch_name
= cpu_arch
[j
].name
;
3001 free (cpu_sub_arch_name
);
3002 cpu_sub_arch_name
= NULL
;
3003 cpu_arch_flags
= cpu_arch
[j
].enable
;
3004 cpu_arch_isa
= cpu_arch
[j
].type
;
3005 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
3006 if (!cpu_arch_tune_set
)
3008 cpu_arch_tune
= cpu_arch_isa
;
3009 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
3012 vector_size
= VSZ_DEFAULT
;
3014 pre_386_16bit_warned
= false;
3018 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
3023 (void) restore_line_pointer (e
);
3025 switch (cpu_arch
[j
].vsz
)
3031 #ifdef SVR4_COMMENT_CHARS
3032 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3034 if (*input_line_pointer
== '/')
3037 ++input_line_pointer
;
3038 switch (get_absolute_expression ())
3040 case 512: vector_size
= VSZ512
; break;
3041 case 256: vector_size
= VSZ256
; break;
3042 case 128: vector_size
= VSZ128
; break;
3044 as_bad (_("Unrecognized vector size specifier"));
3045 ignore_rest_of_line ();
3052 vector_size
= VSZ_DEFAULT
;
3056 demand_empty_rest_of_line ();
3061 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3063 /* Disable an ISA extension. */
3064 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3065 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3066 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3070 if (cpu_arch
[j
].vsz
== vsz_set
)
3071 vector_size
= VSZ_DEFAULT
;
3073 (void) restore_line_pointer (e
);
3074 demand_empty_rest_of_line ();
3079 if (j
== ARRAY_SIZE (cpu_arch
))
3080 as_bad (_("no such architecture: `%s'"), string
);
3082 *input_line_pointer
= e
;
3084 no_cond_jump_promotion
= 0;
3085 if (*input_line_pointer
== ','
3086 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3088 ++input_line_pointer
;
3089 e
= get_symbol_name (&s
);
3092 if (strcmp (string
, "nojumps") == 0)
3093 no_cond_jump_promotion
= 1;
3094 else if (strcmp (string
, "jumps") == 0)
3097 as_bad (_("no such architecture modifier: `%s'"), string
);
3099 (void) restore_line_pointer (e
);
3102 demand_empty_rest_of_line ();
3105 enum bfd_architecture
3108 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3110 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3111 || flag_code
== CODE_64BIT
)
3112 as_fatal (_("Intel MCU is 32bit ELF only"));
3113 return bfd_arch_iamcu
;
3116 return bfd_arch_i386
;
3122 if (startswith (default_arch
, "x86_64"))
3124 if (default_arch
[6] == '\0')
3125 return bfd_mach_x86_64
;
3127 return bfd_mach_x64_32
;
3129 else if (!strcmp (default_arch
, "i386")
3130 || !strcmp (default_arch
, "iamcu"))
3132 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3134 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3135 as_fatal (_("Intel MCU is 32bit ELF only"));
3136 return bfd_mach_i386_iamcu
;
3139 return bfd_mach_i386_i386
;
3142 as_fatal (_("unknown architecture"));
3145 #include "opcodes/i386-tbl.h"
3150 /* Support pseudo prefixes like {disp32}. */
3151 lex_type
['{'] = LEX_BEGIN_NAME
;
3153 /* Initialize op_hash hash table. */
3154 op_hash
= str_htab_create ();
3157 const insn_template
*const *sets
= i386_op_sets
;
3158 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3160 /* Type checks to compensate for the conversion through void * which
3161 occurs during hash table insertion / lookup. */
3162 (void) sizeof (sets
== ¤t_templates
->start
);
3163 (void) sizeof (end
== ¤t_templates
->end
);
3164 for (; sets
< end
; ++sets
)
3165 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3166 as_fatal (_("duplicate %s"), insn_name (*sets
));
3169 /* Initialize reg_hash hash table. */
3170 reg_hash
= str_htab_create ();
3172 const reg_entry
*regtab
;
3173 unsigned int regtab_size
= i386_regtab_size
;
3175 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3177 switch (regtab
->reg_type
.bitfield
.class)
3180 if (regtab
->reg_type
.bitfield
.dword
)
3182 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3185 else if (regtab
->reg_type
.bitfield
.tbyte
)
3187 /* There's no point inserting st(<N>) in the hash table, as
3188 parentheses aren't included in register_chars[] anyway. */
3189 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3196 switch (regtab
->reg_num
)
3198 case 0: reg_es
= regtab
; break;
3199 case 2: reg_ss
= regtab
; break;
3200 case 3: reg_ds
= regtab
; break;
3205 if (!regtab
->reg_num
)
3210 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3211 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3215 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3220 for (c
= 0; c
< 256; c
++)
3222 if (ISDIGIT (c
) || ISLOWER (c
))
3224 mnemonic_chars
[c
] = c
;
3225 register_chars
[c
] = c
;
3226 operand_chars
[c
] = c
;
3228 else if (ISUPPER (c
))
3230 mnemonic_chars
[c
] = TOLOWER (c
);
3231 register_chars
[c
] = mnemonic_chars
[c
];
3232 operand_chars
[c
] = c
;
3234 #ifdef SVR4_COMMENT_CHARS
3235 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3236 operand_chars
[c
] = c
;
3240 operand_chars
[c
] = c
;
3243 mnemonic_chars
['_'] = '_';
3244 mnemonic_chars
['-'] = '-';
3245 mnemonic_chars
['.'] = '.';
3247 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3248 operand_chars
[(unsigned char) *p
] = *p
;
3249 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3250 operand_chars
[(unsigned char) *p
] = *p
;
3253 if (flag_code
== CODE_64BIT
)
3255 #if defined (OBJ_COFF) && defined (TE_PE)
3256 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3259 x86_dwarf2_return_column
= 16;
3261 x86_cie_data_alignment
= -8;
3262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3263 x86_sframe_cfa_sp_reg
= 7;
3264 x86_sframe_cfa_fp_reg
= 6;
3269 x86_dwarf2_return_column
= 8;
3270 x86_cie_data_alignment
= -4;
3273 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3274 can be turned into BRANCH_PREFIX frag. */
3275 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3280 i386_print_statistics (FILE *file
)
3282 htab_print_statistics (file
, "i386 opcode", op_hash
);
3283 htab_print_statistics (file
, "i386 register", reg_hash
);
3289 htab_delete (op_hash
);
3290 htab_delete (reg_hash
);
3295 /* Debugging routines for md_assemble. */
3296 static void pte (insn_template
*);
3297 static void pt (i386_operand_type
);
3298 static void pe (expressionS
*);
3299 static void ps (symbolS
*);
3302 pi (const char *line
, i386_insn
*x
)
3306 fprintf (stdout
, "%s: template ", line
);
3308 fprintf (stdout
, " address: base %s index %s scale %x\n",
3309 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3310 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3311 x
->log2_scale_factor
);
3312 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3313 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3314 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3315 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3316 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3317 (x
->rex
& REX_W
) != 0,
3318 (x
->rex
& REX_R
) != 0,
3319 (x
->rex
& REX_X
) != 0,
3320 (x
->rex
& REX_B
) != 0);
3321 for (j
= 0; j
< x
->operands
; j
++)
3323 fprintf (stdout
, " #%d: ", j
+ 1);
3325 fprintf (stdout
, "\n");
3326 if (x
->types
[j
].bitfield
.class == Reg
3327 || x
->types
[j
].bitfield
.class == RegMMX
3328 || x
->types
[j
].bitfield
.class == RegSIMD
3329 || x
->types
[j
].bitfield
.class == RegMask
3330 || x
->types
[j
].bitfield
.class == SReg
3331 || x
->types
[j
].bitfield
.class == RegCR
3332 || x
->types
[j
].bitfield
.class == RegDR
3333 || x
->types
[j
].bitfield
.class == RegTR
3334 || x
->types
[j
].bitfield
.class == RegBND
)
3335 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3336 if (operand_type_check (x
->types
[j
], imm
))
3338 if (operand_type_check (x
->types
[j
], disp
))
3339 pe (x
->op
[j
].disps
);
3344 pte (insn_template
*t
)
3346 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3347 static const char *const opc_spc
[] = {
3348 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3349 "XOP08", "XOP09", "XOP0A",
3353 fprintf (stdout
, " %d operands ", t
->operands
);
3354 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3355 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3356 if (opc_spc
[t
->opcode_space
])
3357 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3358 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3359 if (t
->extension_opcode
!= None
)
3360 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3361 if (t
->opcode_modifier
.d
)
3362 fprintf (stdout
, "D");
3363 if (t
->opcode_modifier
.w
)
3364 fprintf (stdout
, "W");
3365 fprintf (stdout
, "\n");
3366 for (j
= 0; j
< t
->operands
; j
++)
3368 fprintf (stdout
, " #%d type ", j
+ 1);
3369 pt (t
->operand_types
[j
]);
3370 fprintf (stdout
, "\n");
3377 fprintf (stdout
, " operation %d\n", e
->X_op
);
3378 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3379 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3380 if (e
->X_add_symbol
)
3382 fprintf (stdout
, " add_symbol ");
3383 ps (e
->X_add_symbol
);
3384 fprintf (stdout
, "\n");
3388 fprintf (stdout
, " op_symbol ");
3389 ps (e
->X_op_symbol
);
3390 fprintf (stdout
, "\n");
3397 fprintf (stdout
, "%s type %s%s",
3399 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3400 segment_name (S_GET_SEGMENT (s
)));
3403 static struct type_name
3405 i386_operand_type mask
;
3408 const type_names
[] =
3410 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3411 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3412 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3413 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3414 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3415 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3416 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3417 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3418 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3419 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3420 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3421 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3422 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3423 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3424 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3425 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3426 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3427 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3428 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3429 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3430 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3431 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3432 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3433 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3434 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3435 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3436 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3437 { { .bitfield
= { .class = SReg
} }, "SReg" },
3438 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3439 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3440 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3441 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3442 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3443 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3447 pt (i386_operand_type t
)
3450 i386_operand_type a
;
3452 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3454 a
= operand_type_and (t
, type_names
[j
].mask
);
3455 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3456 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3461 #endif /* DEBUG386 */
3463 static bfd_reloc_code_real_type
3464 reloc (unsigned int size
,
3467 bfd_reloc_code_real_type other
)
3469 if (other
!= NO_RELOC
)
3471 reloc_howto_type
*rel
;
3476 case BFD_RELOC_X86_64_GOT32
:
3477 return BFD_RELOC_X86_64_GOT64
;
3479 case BFD_RELOC_X86_64_GOTPLT64
:
3480 return BFD_RELOC_X86_64_GOTPLT64
;
3482 case BFD_RELOC_X86_64_PLTOFF64
:
3483 return BFD_RELOC_X86_64_PLTOFF64
;
3485 case BFD_RELOC_X86_64_GOTPC32
:
3486 other
= BFD_RELOC_X86_64_GOTPC64
;
3488 case BFD_RELOC_X86_64_GOTPCREL
:
3489 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3491 case BFD_RELOC_X86_64_TPOFF32
:
3492 other
= BFD_RELOC_X86_64_TPOFF64
;
3494 case BFD_RELOC_X86_64_DTPOFF32
:
3495 other
= BFD_RELOC_X86_64_DTPOFF64
;
3501 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3502 if (other
== BFD_RELOC_SIZE32
)
3505 other
= BFD_RELOC_SIZE64
;
3508 as_bad (_("there are no pc-relative size relocations"));
3514 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3515 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3518 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3520 as_bad (_("unknown relocation (%u)"), other
);
3521 else if (size
!= bfd_get_reloc_size (rel
))
3522 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3523 bfd_get_reloc_size (rel
),
3525 else if (pcrel
&& !rel
->pc_relative
)
3526 as_bad (_("non-pc-relative relocation for pc-relative field"));
3527 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3529 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3531 as_bad (_("relocated field and relocation type differ in signedness"));
3540 as_bad (_("there are no unsigned pc-relative relocations"));
3543 case 1: return BFD_RELOC_8_PCREL
;
3544 case 2: return BFD_RELOC_16_PCREL
;
3545 case 4: return BFD_RELOC_32_PCREL
;
3546 case 8: return BFD_RELOC_64_PCREL
;
3548 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3555 case 4: return BFD_RELOC_X86_64_32S
;
3560 case 1: return BFD_RELOC_8
;
3561 case 2: return BFD_RELOC_16
;
3562 case 4: return BFD_RELOC_32
;
3563 case 8: return BFD_RELOC_64
;
3565 as_bad (_("cannot do %s %u byte relocation"),
3566 sign
> 0 ? "signed" : "unsigned", size
);
3572 /* Here we decide which fixups can be adjusted to make them relative to
3573 the beginning of the section instead of the symbol. Basically we need
3574 to make sure that the dynamic relocations are done correctly, so in
3575 some cases we force the original symbol to be used. */
3578 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3584 /* Don't adjust pc-relative references to merge sections in 64-bit
3586 if (use_rela_relocations
3587 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3591 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3592 and changed later by validate_fix. */
3593 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3594 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3597 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3598 for size relocations. */
3599 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3600 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3601 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3602 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3603 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3604 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3606 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3607 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3608 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3609 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3612 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3613 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3625 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3626 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3627 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3628 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3629 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3636 want_disp32 (const insn_template
*t
)
3638 return flag_code
!= CODE_64BIT
3639 || i
.prefix
[ADDR_PREFIX
]
3640 || (t
->mnem_off
== MN_lea
3641 && (!i
.types
[1].bitfield
.qword
3642 || t
->opcode_modifier
.size
== SIZE32
));
3646 intel_float_operand (const char *mnemonic
)
3648 /* Note that the value returned is meaningful only for opcodes with (memory)
3649 operands, hence the code here is free to improperly handle opcodes that
3650 have no operands (for better performance and smaller code). */
3652 if (mnemonic
[0] != 'f')
3653 return 0; /* non-math */
3655 switch (mnemonic
[1])
3657 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3658 the fs segment override prefix not currently handled because no
3659 call path can make opcodes without operands get here */
3661 return 2 /* integer op */;
3663 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3664 return 3; /* fldcw/fldenv */
3667 if (mnemonic
[2] != 'o' /* fnop */)
3668 return 3; /* non-waiting control op */
3671 if (mnemonic
[2] == 's')
3672 return 3; /* frstor/frstpm */
3675 if (mnemonic
[2] == 'a')
3676 return 3; /* fsave */
3677 if (mnemonic
[2] == 't')
3679 switch (mnemonic
[3])
3681 case 'c': /* fstcw */
3682 case 'd': /* fstdw */
3683 case 'e': /* fstenv */
3684 case 's': /* fsts[gw] */
3690 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3691 return 0; /* fxsave/fxrstor are not really math ops */
3699 install_template (const insn_template
*t
)
3705 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3706 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3708 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3709 && is_cpu (t
, CpuAVX512F
))
3711 if (need_evex_encoding ())
3713 i
.tm
.opcode_modifier
.vex
= 0;
3714 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3715 if (is_cpu (&i
.tm
, CpuAVX2
))
3716 i
.tm
.cpu
.bitfield
.isa
= 0;
3720 i
.tm
.opcode_modifier
.evex
= 0;
3721 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3726 /* Note that for pseudo prefixes this produces a length of 1. But for them
3727 the length isn't interesting at all. */
3728 for (l
= 1; l
< 4; ++l
)
3729 if (!(t
->base_opcode
>> (8 * l
)))
3732 i
.opcode_length
= l
;
3735 /* Build the VEX prefix. */
3738 build_vex_prefix (const insn_template
*t
)
3740 unsigned int register_specifier
;
3741 unsigned int vector_length
;
3744 /* Check register specifier. */
3745 if (i
.vex
.register_specifier
)
3747 register_specifier
=
3748 ~register_number (i
.vex
.register_specifier
) & 0xf;
3749 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3752 register_specifier
= 0xf;
3754 /* Use 2-byte VEX prefix by swapping destination and source operand
3755 if there are more than 1 register operand. */
3756 if (i
.reg_operands
> 1
3757 && i
.vec_encoding
!= vex_encoding_vex3
3758 && i
.dir_encoding
== dir_encoding_default
3759 && i
.operands
== i
.reg_operands
3760 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3761 && i
.tm
.opcode_space
== SPACE_0F
3762 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3767 swap_2_operands (0, i
.operands
- 1);
3769 gas_assert (i
.rm
.mode
== 3);
3773 i
.rm
.regmem
= i
.rm
.reg
;
3776 if (i
.tm
.opcode_modifier
.d
)
3777 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3778 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3779 else /* Use the next insn. */
3780 install_template (&t
[1]);
3783 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3784 are no memory operands and at least 3 register ones. */
3785 if (i
.reg_operands
>= 3
3786 && i
.vec_encoding
!= vex_encoding_vex3
3787 && i
.reg_operands
== i
.operands
- i
.imm_operands
3788 && i
.tm
.opcode_modifier
.vex
3789 && i
.tm
.opcode_modifier
.commutative
3790 && (i
.tm
.opcode_modifier
.sse2avx
3791 || (optimize
> 1 && !i
.no_optimize
))
3793 && i
.vex
.register_specifier
3794 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3796 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3798 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3799 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3800 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3801 &i
.types
[i
.operands
- 3]));
3802 gas_assert (i
.rm
.mode
== 3);
3804 swap_2_operands (xchg
, xchg
+ 1);
3807 xchg
= i
.rm
.regmem
| 8;
3808 i
.rm
.regmem
= ~register_specifier
& 0xf;
3809 gas_assert (!(i
.rm
.regmem
& 8));
3810 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3811 register_specifier
= ~xchg
& 0xf;
3814 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3815 vector_length
= avxscalar
;
3816 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3818 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3824 /* Determine vector length from the last multi-length vector
3827 for (op
= t
->operands
; op
--;)
3828 if (t
->operand_types
[op
].bitfield
.xmmword
3829 && t
->operand_types
[op
].bitfield
.ymmword
3830 && i
.types
[op
].bitfield
.ymmword
)
3837 /* Check the REX.W bit and VEXW. */
3838 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3839 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3840 else if (i
.tm
.opcode_modifier
.vexw
)
3841 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3843 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3845 /* Use 2-byte VEX prefix if possible. */
3847 && i
.vec_encoding
!= vex_encoding_vex3
3848 && i
.tm
.opcode_space
== SPACE_0F
3849 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3851 /* 2-byte VEX prefix. */
3855 i
.vex
.bytes
[0] = 0xc5;
3857 /* Check the REX.R bit. */
3858 r
= (i
.rex
& REX_R
) ? 0 : 1;
3859 i
.vex
.bytes
[1] = (r
<< 7
3860 | register_specifier
<< 3
3861 | vector_length
<< 2
3862 | i
.tm
.opcode_modifier
.opcodeprefix
);
3866 /* 3-byte VEX prefix. */
3869 switch (i
.tm
.opcode_space
)
3874 i
.vex
.bytes
[0] = 0xc4;
3879 i
.vex
.bytes
[0] = 0x8f;
3885 /* The high 3 bits of the second VEX byte are 1's compliment
3886 of RXB bits from REX. */
3887 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3888 | (!dot_insn () ? i
.tm
.opcode_space
3889 : i
.insn_opcode_space
);
3891 i
.vex
.bytes
[2] = (w
<< 7
3892 | register_specifier
<< 3
3893 | vector_length
<< 2
3894 | i
.tm
.opcode_modifier
.opcodeprefix
);
3899 is_evex_encoding (const insn_template
*t
)
3901 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3902 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3903 || t
->opcode_modifier
.sae
;
3907 is_any_vex_encoding (const insn_template
*t
)
3909 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3913 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3915 unsigned int op
, bytes
;
3916 const i386_operand_type
*types
;
3918 if (i
.broadcast
.type
)
3919 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3921 gas_assert (intel_syntax
);
3923 for (op
= 0; op
< t
->operands
; ++op
)
3924 if (t
->operand_types
[op
].bitfield
.baseindex
)
3927 gas_assert (op
< t
->operands
);
3929 if (t
->opcode_modifier
.evex
3930 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3931 switch (i
.broadcast
.bytes
)
3934 if (t
->operand_types
[op
].bitfield
.word
)
3938 if (t
->operand_types
[op
].bitfield
.dword
)
3942 if (t
->operand_types
[op
].bitfield
.qword
)
3946 if (t
->operand_types
[op
].bitfield
.xmmword
)
3948 if (t
->operand_types
[op
].bitfield
.ymmword
)
3950 if (t
->operand_types
[op
].bitfield
.zmmword
)
3957 gas_assert (op
+ 1 < t
->operands
);
3959 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3960 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3961 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3963 types
= &i
.types
[op
+ 1];
3966 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3967 types
= &t
->operand_types
[op
];
3969 if (types
->bitfield
.zmmword
)
3971 else if (types
->bitfield
.ymmword
)
3977 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3978 insn_name (t
), bytes
* 8);
3983 /* Build the EVEX prefix. */
3986 build_evex_prefix (void)
3988 unsigned int register_specifier
, w
;
3989 rex_byte vrex_used
= 0;
3991 /* Check register specifier. */
3992 if (i
.vex
.register_specifier
)
3994 gas_assert ((i
.vrex
& REX_X
) == 0);
3996 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3997 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3998 register_specifier
+= 8;
3999 /* The upper 16 registers are encoded in the fourth byte of the
4001 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
4002 i
.vex
.bytes
[3] = 0x8;
4003 register_specifier
= ~register_specifier
& 0xf;
4007 register_specifier
= 0xf;
4009 /* Encode upper 16 vector index register in the fourth byte of
4011 if (!(i
.vrex
& REX_X
))
4012 i
.vex
.bytes
[3] = 0x8;
4017 /* 4 byte EVEX prefix. */
4019 i
.vex
.bytes
[0] = 0x62;
4021 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4023 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
4024 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
4025 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4026 | (!dot_insn () ? i
.tm
.opcode_space
4027 : i
.insn_opcode_space
);
4029 /* The fifth bit of the second EVEX byte is 1's compliment of the
4030 REX_R bit in VREX. */
4031 if (!(i
.vrex
& REX_R
))
4032 i
.vex
.bytes
[1] |= 0x10;
4036 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4038 /* When all operands are registers, the REX_X bit in REX is not
4039 used. We reuse it to encode the upper 16 registers, which is
4040 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4041 as 1's compliment. */
4042 if ((i
.vrex
& REX_B
))
4045 i
.vex
.bytes
[1] &= ~0x40;
4049 /* EVEX instructions shouldn't need the REX prefix. */
4050 i
.vrex
&= ~vrex_used
;
4051 gas_assert (i
.vrex
== 0);
4053 /* Check the REX.W bit and VEXW. */
4054 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4055 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4056 else if (i
.tm
.opcode_modifier
.vexw
)
4057 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4059 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4061 /* The third byte of the EVEX prefix. */
4062 i
.vex
.bytes
[2] = ((w
<< 7)
4063 | (register_specifier
<< 3)
4064 | 4 /* Encode the U bit. */
4065 | i
.tm
.opcode_modifier
.opcodeprefix
);
4067 /* The fourth byte of the EVEX prefix. */
4068 /* The zeroing-masking bit. */
4069 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4070 i
.vex
.bytes
[3] |= 0x80;
4072 /* Don't always set the broadcast bit if there is no RC. */
4073 if (i
.rounding
.type
== rc_none
)
4075 /* Encode the vector length. */
4076 unsigned int vec_length
;
4078 if (!i
.tm
.opcode_modifier
.evex
4079 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4083 /* Determine vector length from the last multi-length vector
4085 for (op
= i
.operands
; op
--;)
4086 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4087 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4088 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4090 if (i
.types
[op
].bitfield
.zmmword
)
4092 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4095 else if (i
.types
[op
].bitfield
.ymmword
)
4097 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4100 else if (i
.types
[op
].bitfield
.xmmword
)
4102 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4105 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4106 && op
== i
.broadcast
.operand
)
4108 switch (get_broadcast_bytes (&i
.tm
, true))
4111 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4114 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4117 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4126 if (op
>= MAX_OPERANDS
)
4130 switch (i
.tm
.opcode_modifier
.evex
)
4132 case EVEXLIG
: /* LL' is ignored */
4133 vec_length
= evexlig
<< 5;
4136 vec_length
= 0 << 5;
4139 vec_length
= 1 << 5;
4142 vec_length
= 2 << 5;
4147 vec_length
= 3 << 5;
4155 i
.vex
.bytes
[3] |= vec_length
;
4156 /* Encode the broadcast bit. */
4157 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4158 i
.vex
.bytes
[3] |= 0x10;
4160 else if (i
.rounding
.type
!= saeonly
)
4161 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4163 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4166 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4170 process_immext (void)
4174 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4175 which is coded in the same place as an 8-bit immediate field
4176 would be. Here we fake an 8-bit immediate operand from the
4177 opcode suffix stored in tm.extension_opcode.
4179 AVX instructions also use this encoding, for some of
4180 3 argument instructions. */
4182 gas_assert (i
.imm_operands
<= 1
4184 || (is_any_vex_encoding (&i
.tm
)
4185 && i
.operands
<= 4)));
4187 exp
= &im_expressions
[i
.imm_operands
++];
4188 i
.op
[i
.operands
].imms
= exp
;
4189 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4191 exp
->X_op
= O_constant
;
4192 exp
->X_add_number
= i
.tm
.extension_opcode
;
4193 i
.tm
.extension_opcode
= None
;
4200 switch (i
.tm
.opcode_modifier
.prefixok
)
4208 as_bad (_("invalid instruction `%s' after `%s'"),
4209 insn_name (&i
.tm
), i
.hle_prefix
);
4212 if (i
.prefix
[LOCK_PREFIX
])
4214 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4218 case PrefixHLERelease
:
4219 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4221 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4225 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4227 as_bad (_("memory destination needed for instruction `%s'"
4228 " after `xrelease'"), insn_name (&i
.tm
));
4235 /* Encode aligned vector move as unaligned vector move. */
4238 encode_with_unaligned_vector_move (void)
4240 switch (i
.tm
.base_opcode
)
4242 case 0x28: /* Load instructions. */
4243 case 0x29: /* Store instructions. */
4244 /* movaps/movapd/vmovaps/vmovapd. */
4245 if (i
.tm
.opcode_space
== SPACE_0F
4246 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4247 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4249 case 0x6f: /* Load instructions. */
4250 case 0x7f: /* Store instructions. */
4251 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4252 if (i
.tm
.opcode_space
== SPACE_0F
4253 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4254 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4261 /* Try the shortest encoding by shortening operand size. */
4264 optimize_encoding (void)
4268 if (i
.tm
.mnem_off
== MN_lea
)
4271 lea symbol, %rN -> mov $symbol, %rN
4272 lea (%rM), %rN -> mov %rM, %rN
4273 lea (,%rM,1), %rN -> mov %rM, %rN
4275 and in 32-bit mode for 16-bit addressing
4277 lea (%rM), %rN -> movzx %rM, %rN
4279 and in 64-bit mode zap 32-bit addressing in favor of using a
4280 32-bit (or less) destination.
4282 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4284 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4285 i
.tm
.opcode_modifier
.size
= SIZE32
;
4286 i
.prefix
[ADDR_PREFIX
] = 0;
4289 if (!i
.index_reg
&& !i
.base_reg
)
4292 lea symbol, %rN -> mov $symbol, %rN
4294 if (flag_code
== CODE_64BIT
)
4296 /* Don't transform a relocation to a 16-bit one. */
4298 && i
.op
[0].disps
->X_op
!= O_constant
4299 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4302 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4303 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4305 i
.tm
.base_opcode
= 0xb8;
4306 i
.tm
.opcode_modifier
.modrm
= 0;
4307 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4308 i
.types
[0].bitfield
.imm32
= 1;
4311 i
.tm
.opcode_modifier
.size
= SIZE16
;
4312 i
.types
[0].bitfield
.imm16
= 1;
4317 /* Subject to further optimization below. */
4318 i
.tm
.base_opcode
= 0xc7;
4319 i
.tm
.extension_opcode
= 0;
4320 i
.types
[0].bitfield
.imm32s
= 1;
4321 i
.types
[0].bitfield
.baseindex
= 0;
4324 /* Outside of 64-bit mode address and operand sizes have to match if
4325 a relocation is involved, as otherwise we wouldn't (currently) or
4326 even couldn't express the relocation correctly. */
4327 else if (i
.op
[0].disps
4328 && i
.op
[0].disps
->X_op
!= O_constant
4329 && ((!i
.prefix
[ADDR_PREFIX
])
4330 != (flag_code
== CODE_32BIT
4331 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4332 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4334 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4335 destination is going to grow encoding size. */
4336 else if (flag_code
== CODE_16BIT
4337 && (optimize
<= 1 || optimize_for_space
)
4338 && !i
.prefix
[ADDR_PREFIX
]
4339 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4343 i
.tm
.base_opcode
= 0xb8;
4344 i
.tm
.opcode_modifier
.modrm
= 0;
4345 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4346 i
.types
[0].bitfield
.imm32
= 1;
4348 i
.types
[0].bitfield
.imm16
= 1;
4351 && i
.op
[0].disps
->X_op
== O_constant
4352 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4353 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4355 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4356 i
.op
[0].disps
->X_add_number
&= 0xffff;
4359 i
.tm
.operand_types
[0] = i
.types
[0];
4363 i
.op
[0].imms
= &im_expressions
[0];
4364 i
.op
[0].imms
->X_op
= O_absent
;
4367 else if (i
.op
[0].disps
4368 && (i
.op
[0].disps
->X_op
!= O_constant
4369 || i
.op
[0].disps
->X_add_number
))
4374 lea (%rM), %rN -> mov %rM, %rN
4375 lea (,%rM,1), %rN -> mov %rM, %rN
4376 lea (%rM), %rN -> movzx %rM, %rN
4378 const reg_entry
*addr_reg
;
4380 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4381 addr_reg
= i
.base_reg
;
4382 else if (!i
.base_reg
4383 && i
.index_reg
->reg_num
!= RegIZ
4384 && !i
.log2_scale_factor
)
4385 addr_reg
= i
.index_reg
;
4389 if (addr_reg
->reg_type
.bitfield
.word
4390 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4392 if (flag_code
!= CODE_32BIT
)
4394 i
.tm
.opcode_space
= SPACE_0F
;
4395 i
.tm
.base_opcode
= 0xb7;
4398 i
.tm
.base_opcode
= 0x8b;
4400 if (addr_reg
->reg_type
.bitfield
.dword
4401 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4402 i
.tm
.opcode_modifier
.size
= SIZE32
;
4404 i
.op
[0].regs
= addr_reg
;
4409 i
.disp_operands
= 0;
4410 i
.prefix
[ADDR_PREFIX
] = 0;
4411 i
.prefix
[SEG_PREFIX
] = 0;
4415 if (optimize_for_space
4416 && i
.tm
.mnem_off
== MN_test
4417 && i
.reg_operands
== 1
4418 && i
.imm_operands
== 1
4419 && !i
.types
[1].bitfield
.byte
4420 && i
.op
[0].imms
->X_op
== O_constant
4421 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4424 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4426 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4427 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4429 i
.types
[1].bitfield
.byte
= 1;
4430 /* Ignore the suffix. */
4432 /* Convert to byte registers. */
4433 if (i
.types
[1].bitfield
.word
)
4435 else if (i
.types
[1].bitfield
.dword
)
4439 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4444 else if (flag_code
== CODE_64BIT
4445 && i
.tm
.opcode_space
== SPACE_BASE
4446 && ((i
.types
[1].bitfield
.qword
4447 && i
.reg_operands
== 1
4448 && i
.imm_operands
== 1
4449 && i
.op
[0].imms
->X_op
== O_constant
4450 && ((i
.tm
.base_opcode
== 0xb8
4451 && i
.tm
.extension_opcode
== None
4452 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4453 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4454 && (i
.tm
.base_opcode
== 0x24
4455 || (i
.tm
.base_opcode
== 0x80
4456 && i
.tm
.extension_opcode
== 0x4)
4457 || i
.tm
.mnem_off
== MN_test
4458 || ((i
.tm
.base_opcode
| 1) == 0xc7
4459 && i
.tm
.extension_opcode
== 0x0)))
4460 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4461 && i
.tm
.base_opcode
== 0x83
4462 && i
.tm
.extension_opcode
== 0x4)))
4463 || (i
.types
[0].bitfield
.qword
4464 && ((i
.reg_operands
== 2
4465 && i
.op
[0].regs
== i
.op
[1].regs
4466 && (i
.tm
.mnem_off
== MN_xor
4467 || i
.tm
.mnem_off
== MN_sub
))
4468 || i
.tm
.mnem_off
== MN_clr
))))
4471 andq $imm31, %r64 -> andl $imm31, %r32
4472 andq $imm7, %r64 -> andl $imm7, %r32
4473 testq $imm31, %r64 -> testl $imm31, %r32
4474 xorq %r64, %r64 -> xorl %r32, %r32
4475 subq %r64, %r64 -> subl %r32, %r32
4476 movq $imm31, %r64 -> movl $imm31, %r32
4477 movq $imm32, %r64 -> movl $imm32, %r32
4479 i
.tm
.opcode_modifier
.size
= SIZE32
;
4482 i
.types
[0].bitfield
.imm32
= 1;
4483 i
.types
[0].bitfield
.imm32s
= 0;
4484 i
.types
[0].bitfield
.imm64
= 0;
4488 i
.types
[0].bitfield
.dword
= 1;
4489 i
.types
[0].bitfield
.qword
= 0;
4491 i
.types
[1].bitfield
.dword
= 1;
4492 i
.types
[1].bitfield
.qword
= 0;
4493 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4496 movq $imm31, %r64 -> movl $imm31, %r32
4497 movq $imm32, %r64 -> movl $imm32, %r32
4499 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4500 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4501 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4502 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4505 movq $imm31, %r64 -> movl $imm31, %r32
4507 i
.tm
.base_opcode
= 0xb8;
4508 i
.tm
.extension_opcode
= None
;
4509 i
.tm
.opcode_modifier
.w
= 0;
4510 i
.tm
.opcode_modifier
.modrm
= 0;
4514 else if (optimize
> 1
4515 && !optimize_for_space
4516 && i
.reg_operands
== 2
4517 && i
.op
[0].regs
== i
.op
[1].regs
4518 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4519 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4522 andb %rN, %rN -> testb %rN, %rN
4523 andw %rN, %rN -> testw %rN, %rN
4524 andq %rN, %rN -> testq %rN, %rN
4525 orb %rN, %rN -> testb %rN, %rN
4526 orw %rN, %rN -> testw %rN, %rN
4527 orq %rN, %rN -> testq %rN, %rN
4529 and outside of 64-bit mode
4531 andl %rN, %rN -> testl %rN, %rN
4532 orl %rN, %rN -> testl %rN, %rN
4534 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4536 else if (i
.tm
.base_opcode
== 0xba
4537 && i
.tm
.opcode_space
== SPACE_0F
4538 && i
.reg_operands
== 1
4539 && i
.op
[0].imms
->X_op
== O_constant
4540 && i
.op
[0].imms
->X_add_number
>= 0)
4543 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4544 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4545 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4547 With <BT> one of bts, btr, and bts also:
4548 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4549 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4554 if (i
.tm
.extension_opcode
!= 4)
4556 if (i
.types
[1].bitfield
.qword
4557 && i
.op
[0].imms
->X_add_number
< 32
4558 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4559 i
.tm
.opcode_modifier
.size
= SIZE32
;
4562 if (i
.types
[1].bitfield
.word
4563 && i
.op
[0].imms
->X_add_number
< 16)
4564 i
.tm
.opcode_modifier
.size
= SIZE32
;
4567 if (i
.op
[0].imms
->X_add_number
< 16)
4568 i
.tm
.opcode_modifier
.size
= SIZE16
;
4572 else if (i
.reg_operands
== 3
4573 && i
.op
[0].regs
== i
.op
[1].regs
4574 && !i
.types
[2].bitfield
.xmmword
4575 && (i
.tm
.opcode_modifier
.vex
4576 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4577 && is_evex_encoding (&i
.tm
)
4578 && (i
.vec_encoding
!= vex_encoding_evex
4579 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4580 || is_cpu (&i
.tm
, CpuAVX512VL
)
4581 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4582 && i
.types
[2].bitfield
.ymmword
))))
4583 && i
.tm
.opcode_space
== SPACE_0F
4584 && ((i
.tm
.base_opcode
| 2) == 0x57
4585 || i
.tm
.base_opcode
== 0xdf
4586 || i
.tm
.base_opcode
== 0xef
4587 || (i
.tm
.base_opcode
| 3) == 0xfb
4588 || i
.tm
.base_opcode
== 0x42
4589 || i
.tm
.base_opcode
== 0x47))
4592 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4594 EVEX VOP %zmmM, %zmmM, %zmmN
4595 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4596 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4597 EVEX VOP %ymmM, %ymmM, %ymmN
4598 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4599 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4600 VEX VOP %ymmM, %ymmM, %ymmN
4601 -> VEX VOP %xmmM, %xmmM, %xmmN
4602 VOP, one of vpandn and vpxor:
4603 VEX VOP %ymmM, %ymmM, %ymmN
4604 -> VEX VOP %xmmM, %xmmM, %xmmN
4605 VOP, one of vpandnd and vpandnq:
4606 EVEX VOP %zmmM, %zmmM, %zmmN
4607 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4608 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4609 EVEX VOP %ymmM, %ymmM, %ymmN
4610 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4611 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4612 VOP, one of vpxord and vpxorq:
4613 EVEX VOP %zmmM, %zmmM, %zmmN
4614 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4615 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4616 EVEX VOP %ymmM, %ymmM, %ymmN
4617 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4618 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4619 VOP, one of kxord and kxorq:
4620 VEX VOP %kM, %kM, %kN
4621 -> VEX kxorw %kM, %kM, %kN
4622 VOP, one of kandnd and kandnq:
4623 VEX VOP %kM, %kM, %kN
4624 -> VEX kandnw %kM, %kM, %kN
4626 if (is_evex_encoding (&i
.tm
))
4628 if (i
.vec_encoding
!= vex_encoding_evex
)
4630 i
.tm
.opcode_modifier
.vex
= VEX128
;
4631 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4632 i
.tm
.opcode_modifier
.evex
= 0;
4633 i
.vec_encoding
= vex_encoding_vex
;
4636 else if (optimize
> 1)
4637 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4641 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4643 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4644 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4647 i
.tm
.opcode_modifier
.vex
= VEX128
;
4649 if (i
.tm
.opcode_modifier
.vex
)
4650 for (j
= 0; j
< 3; j
++)
4652 i
.types
[j
].bitfield
.xmmword
= 1;
4653 i
.types
[j
].bitfield
.ymmword
= 0;
4656 else if (i
.vec_encoding
!= vex_encoding_evex
4657 && !i
.types
[0].bitfield
.zmmword
4658 && !i
.types
[1].bitfield
.zmmword
4660 && !i
.broadcast
.type
4661 && !i
.broadcast
.bytes
4662 && is_evex_encoding (&i
.tm
)
4663 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4664 || (i
.tm
.base_opcode
& ~4) == 0xdb
4665 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4666 && i
.tm
.extension_opcode
== None
)
4669 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4670 vmovdqu32 and vmovdqu64:
4671 EVEX VOP %xmmM, %xmmN
4672 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4673 EVEX VOP %ymmM, %ymmN
4674 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4676 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4678 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4680 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4682 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4683 VOP, one of vpand, vpandn, vpor, vpxor:
4684 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4685 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4686 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4687 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4688 EVEX VOP{d,q} mem, %xmmM, %xmmN
4689 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4690 EVEX VOP{d,q} mem, %ymmM, %ymmN
4691 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4693 for (j
= 0; j
< i
.operands
; j
++)
4694 if (operand_type_check (i
.types
[j
], disp
)
4695 && i
.op
[j
].disps
->X_op
== O_constant
)
4697 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4698 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4699 bytes, we choose EVEX Disp8 over VEX Disp32. */
4700 int evex_disp8
, vex_disp8
;
4701 unsigned int memshift
= i
.memshift
;
4702 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4704 evex_disp8
= fits_in_disp8 (n
);
4706 vex_disp8
= fits_in_disp8 (n
);
4707 if (evex_disp8
!= vex_disp8
)
4709 i
.memshift
= memshift
;
4713 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4716 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4717 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4718 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4719 i
.tm
.opcode_modifier
.vex
4720 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4721 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4722 /* VPAND, VPOR, and VPXOR are commutative. */
4723 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4724 i
.tm
.opcode_modifier
.commutative
= 1;
4725 i
.tm
.opcode_modifier
.evex
= 0;
4726 i
.tm
.opcode_modifier
.masking
= 0;
4727 i
.tm
.opcode_modifier
.broadcast
= 0;
4728 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4731 i
.types
[j
].bitfield
.disp8
4732 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4734 else if (optimize_for_space
4735 && i
.tm
.base_opcode
== 0x29
4736 && i
.tm
.opcode_space
== SPACE_0F38
4737 && i
.operands
== i
.reg_operands
4738 && i
.op
[0].regs
== i
.op
[1].regs
4739 && (!i
.tm
.opcode_modifier
.vex
4740 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4741 && !is_evex_encoding (&i
.tm
))
4744 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4745 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4746 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4748 i
.tm
.opcode_space
= SPACE_0F
;
4749 i
.tm
.base_opcode
= 0x76;
4751 else if (((i
.tm
.base_opcode
>= 0x64
4752 && i
.tm
.base_opcode
<= 0x66
4753 && i
.tm
.opcode_space
== SPACE_0F
)
4754 || (i
.tm
.base_opcode
== 0x37
4755 && i
.tm
.opcode_space
== SPACE_0F38
))
4756 && i
.operands
== i
.reg_operands
4757 && i
.op
[0].regs
== i
.op
[1].regs
4758 && !is_evex_encoding (&i
.tm
))
4761 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4762 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4763 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4764 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4765 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4766 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4768 i
.tm
.opcode_space
= SPACE_0F
;
4769 i
.tm
.base_opcode
= 0xef;
4770 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4772 if (i
.operands
== 2)
4774 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4780 i
.op
[2].regs
= i
.op
[0].regs
;
4781 i
.types
[2] = i
.types
[0];
4782 i
.flags
[2] = i
.flags
[0];
4783 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4785 i
.tm
.opcode_modifier
.sse2avx
= 0;
4787 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4788 i
.op
[1].regs
= i
.op
[0].regs
;
4791 else if (optimize_for_space
4792 && i
.tm
.base_opcode
== 0x59
4793 && i
.tm
.opcode_space
== SPACE_0F38
4794 && i
.operands
== i
.reg_operands
4795 && i
.tm
.opcode_modifier
.vex
4796 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4797 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4798 && i
.vec_encoding
!= vex_encoding_vex3
)
4801 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4803 i
.tm
.opcode_space
= SPACE_0F
;
4804 i
.tm
.base_opcode
= 0x6c;
4805 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4811 i
.op
[2].regs
= i
.op
[0].regs
;
4812 i
.types
[2] = i
.types
[0];
4813 i
.flags
[2] = i
.flags
[0];
4814 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4816 swap_2_operands (1, 2);
4820 /* Return non-zero for load instruction. */
4826 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4827 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4831 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4832 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4833 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4837 if (i
.tm
.mnem_off
== MN_pop
)
4841 if (i
.tm
.opcode_space
== SPACE_BASE
)
4844 if (i
.tm
.base_opcode
== 0x9d
4845 || i
.tm
.base_opcode
== 0x61)
4848 /* movs, cmps, lods, scas. */
4849 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4853 if (base_opcode
== 0x6f
4854 || i
.tm
.base_opcode
== 0xd7)
4856 /* NB: For AMD-specific insns with implicit memory operands,
4857 they're intentionally not covered. */
4860 /* No memory operand. */
4861 if (!i
.mem_operands
)
4866 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4869 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4871 /* test, not, neg, mul, imul, div, idiv. */
4872 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4876 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4879 /* add, or, adc, sbb, and, sub, xor, cmp. */
4880 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4883 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4884 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4885 && i
.tm
.extension_opcode
!= 6)
4888 /* Check for x87 instructions. */
4889 if ((base_opcode
| 6) == 0xdf)
4891 /* Skip fst, fstp, fstenv, fstcw. */
4892 if (i
.tm
.base_opcode
== 0xd9
4893 && (i
.tm
.extension_opcode
== 2
4894 || i
.tm
.extension_opcode
== 3
4895 || i
.tm
.extension_opcode
== 6
4896 || i
.tm
.extension_opcode
== 7))
4899 /* Skip fisttp, fist, fistp, fstp. */
4900 if (i
.tm
.base_opcode
== 0xdb
4901 && (i
.tm
.extension_opcode
== 1
4902 || i
.tm
.extension_opcode
== 2
4903 || i
.tm
.extension_opcode
== 3
4904 || i
.tm
.extension_opcode
== 7))
4907 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4908 if (i
.tm
.base_opcode
== 0xdd
4909 && (i
.tm
.extension_opcode
== 1
4910 || i
.tm
.extension_opcode
== 2
4911 || i
.tm
.extension_opcode
== 3
4912 || i
.tm
.extension_opcode
== 6
4913 || i
.tm
.extension_opcode
== 7))
4916 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4917 if (i
.tm
.base_opcode
== 0xdf
4918 && (i
.tm
.extension_opcode
== 1
4919 || i
.tm
.extension_opcode
== 2
4920 || i
.tm
.extension_opcode
== 3
4921 || i
.tm
.extension_opcode
== 6
4922 || i
.tm
.extension_opcode
== 7))
4928 else if (i
.tm
.opcode_space
== SPACE_0F
)
4930 /* bt, bts, btr, btc. */
4931 if (i
.tm
.base_opcode
== 0xba
4932 && (i
.tm
.extension_opcode
| 3) == 7)
4935 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4936 if (i
.tm
.base_opcode
== 0xc7
4937 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4938 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4939 || i
.tm
.extension_opcode
== 6))
4942 /* fxrstor, ldmxcsr, xrstor. */
4943 if (i
.tm
.base_opcode
== 0xae
4944 && (i
.tm
.extension_opcode
== 1
4945 || i
.tm
.extension_opcode
== 2
4946 || i
.tm
.extension_opcode
== 5))
4949 /* lgdt, lidt, lmsw. */
4950 if (i
.tm
.base_opcode
== 0x01
4951 && (i
.tm
.extension_opcode
== 2
4952 || i
.tm
.extension_opcode
== 3
4953 || i
.tm
.extension_opcode
== 6))
4957 dest
= i
.operands
- 1;
4959 /* Check fake imm8 operand and 3 source operands. */
4960 if ((i
.tm
.opcode_modifier
.immext
4961 || i
.reg_operands
+ i
.mem_operands
== 4)
4962 && i
.types
[dest
].bitfield
.imm8
)
4965 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4966 if (i
.tm
.opcode_space
== SPACE_BASE
4967 && ((base_opcode
| 0x38) == 0x39
4968 || (base_opcode
| 2) == 0x87))
4971 if (i
.tm
.mnem_off
== MN_xadd
)
4974 /* Check for load instruction. */
4975 return (i
.types
[dest
].bitfield
.class != ClassNone
4976 || i
.types
[dest
].bitfield
.instance
== Accum
);
4979 /* Output lfence, 0xfaee8, after instruction. */
4982 insert_lfence_after (void)
4984 if (lfence_after_load
&& load_insn_p ())
4986 /* There are also two REP string instructions that require
4987 special treatment. Specifically, the compare string (CMPS)
4988 and scan string (SCAS) instructions set EFLAGS in a manner
4989 that depends on the data being compared/scanned. When used
4990 with a REP prefix, the number of iterations may therefore
4991 vary depending on this data. If the data is a program secret
4992 chosen by the adversary using an LVI method,
4993 then this data-dependent behavior may leak some aspect
4995 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4996 && i
.prefix
[REP_PREFIX
])
4998 as_warn (_("`%s` changes flags which would affect control flow behavior"),
5001 char *p
= frag_more (3);
5008 /* Output lfence, 0xfaee8, before instruction. */
5011 insert_lfence_before (void)
5015 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5018 if (i
.tm
.base_opcode
== 0xff
5019 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
5021 /* Insert lfence before indirect branch if needed. */
5023 if (lfence_before_indirect_branch
== lfence_branch_none
)
5026 if (i
.operands
!= 1)
5029 if (i
.reg_operands
== 1)
5031 /* Indirect branch via register. Don't insert lfence with
5032 -mlfence-after-load=yes. */
5033 if (lfence_after_load
5034 || lfence_before_indirect_branch
== lfence_branch_memory
)
5037 else if (i
.mem_operands
== 1
5038 && lfence_before_indirect_branch
!= lfence_branch_register
)
5040 as_warn (_("indirect `%s` with memory operand should be avoided"),
5047 if (last_insn
.kind
!= last_insn_other
5048 && last_insn
.seg
== now_seg
)
5050 as_warn_where (last_insn
.file
, last_insn
.line
,
5051 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5052 last_insn
.name
, insn_name (&i
.tm
));
5063 /* Output or/not/shl and lfence before near ret. */
5064 if (lfence_before_ret
!= lfence_before_ret_none
5065 && (i
.tm
.base_opcode
| 1) == 0xc3)
5067 if (last_insn
.kind
!= last_insn_other
5068 && last_insn
.seg
== now_seg
)
5070 as_warn_where (last_insn
.file
, last_insn
.line
,
5071 _("`%s` skips -mlfence-before-ret on `%s`"),
5072 last_insn
.name
, insn_name (&i
.tm
));
5076 /* Near ret ingore operand size override under CPU64. */
5077 char prefix
= flag_code
== CODE_64BIT
5079 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5081 if (lfence_before_ret
== lfence_before_ret_not
)
5083 /* not: 0xf71424, may add prefix
5084 for operand size override or 64-bit code. */
5085 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5099 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5102 if (lfence_before_ret
== lfence_before_ret_or
)
5104 /* or: 0x830c2400, may add prefix
5105 for operand size override or 64-bit code. */
5111 /* shl: 0xc1242400, may add prefix
5112 for operand size override or 64-bit code. */
5127 /* Shared helper for md_assemble() and s_insn(). */
5128 static void init_globals (void)
5132 memset (&i
, '\0', sizeof (i
));
5133 i
.rounding
.type
= rc_none
;
5134 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5135 i
.reloc
[j
] = NO_RELOC
;
5136 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5137 memset (im_expressions
, '\0', sizeof (im_expressions
));
5138 save_stack_p
= save_stack
;
5141 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5142 parsing pass. Instead of introducing a rarely use new insn attribute this
5143 utilizes a common pattern between affected templates. It is deemed
5144 acceptable that this will lead to unnecessary pass 2 preparations in a
5145 limited set of cases. */
5146 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5148 return t
->opcode_modifier
.sse2avx
5149 /* Note that all SSE2AVX templates have at least one operand. */
5150 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5151 : (t
->opcode_space
== SPACE_0F
5152 && (t
->base_opcode
| 1) == 0xbf)
5153 || (t
->opcode_space
== SPACE_BASE
5154 && t
->base_opcode
== 0x63);
5157 /* This is the guts of the machine-dependent assembler. LINE points to a
5158 machine dependent instruction. This function is supposed to emit
5159 the frags/bytes it assembles to. */
5162 md_assemble (char *line
)
5165 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5166 const char *end
, *pass1_mnem
= NULL
;
5167 enum i386_error pass1_err
= 0;
5168 const insn_template
*t
;
5170 /* Initialize globals. */
5171 current_templates
= NULL
;
5175 /* First parse an instruction mnemonic & call i386_operand for the operands.
5176 We assume that the scrubber has arranged it so that line[0] is the valid
5177 start of a (possibly prefixed) mnemonic. */
5179 end
= parse_insn (line
, mnemonic
, false);
5182 if (pass1_mnem
!= NULL
)
5184 if (i
.error
!= no_error
)
5186 gas_assert (current_templates
!= NULL
);
5187 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5189 /* No point in trying a 2nd pass - it'll only find the same suffix
5191 mnem_suffix
= i
.suffix
;
5196 t
= current_templates
->start
;
5197 if (may_need_pass2 (t
))
5199 /* Make a copy of the full line in case we need to retry. */
5200 copy
= xstrdup (line
);
5203 mnem_suffix
= i
.suffix
;
5205 line
= parse_operands (line
, mnemonic
);
5213 /* Now we've parsed the mnemonic into a set of templates, and have the
5214 operands at hand. */
5216 /* All Intel opcodes have reversed operands except for "bound", "enter",
5217 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5218 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5219 intersegment "jmp" and "call" instructions with 2 immediate operands so
5220 that the immediate segment precedes the offset consistently in Intel and
5224 && (t
->mnem_off
!= MN_bound
)
5225 && !startswith (mnemonic
, "invlpg")
5226 && !startswith (mnemonic
, "monitor")
5227 && !startswith (mnemonic
, "mwait")
5228 && (t
->mnem_off
!= MN_pvalidate
)
5229 && !startswith (mnemonic
, "rmp")
5230 && (t
->mnem_off
!= MN_tpause
)
5231 && (t
->mnem_off
!= MN_umwait
)
5232 && !(i
.operands
== 2
5233 && operand_type_check (i
.types
[0], imm
)
5234 && operand_type_check (i
.types
[1], imm
)))
5237 /* The order of the immediates should be reversed
5238 for 2 immediates extrq and insertq instructions */
5239 if (i
.imm_operands
== 2
5240 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5241 swap_2_operands (0, 1);
5246 if (i
.disp_operands
&& !optimize_disp (t
))
5249 /* Next, we find a template that matches the given insn,
5250 making sure the overlap of the given operands types is consistent
5251 with the template operand types. */
5253 if (!(t
= match_template (mnem_suffix
)))
5255 const char *err_msg
;
5257 if (copy
&& !mnem_suffix
)
5262 pass1_err
= i
.error
;
5263 pass1_mnem
= insn_name (current_templates
->start
);
5267 /* If a non-/only-64bit template (group) was found in pass 1, and if
5268 _some_ template (group) was found in pass 2, squash pass 1's
5270 if (pass1_err
== unsupported_64bit
)
5276 switch (pass1_mnem
? pass1_err
: i
.error
)
5280 case operand_size_mismatch
:
5281 err_msg
= _("operand size mismatch");
5283 case operand_type_mismatch
:
5284 err_msg
= _("operand type mismatch");
5286 case register_type_mismatch
:
5287 err_msg
= _("register type mismatch");
5289 case number_of_operands_mismatch
:
5290 err_msg
= _("number of operands mismatch");
5292 case invalid_instruction_suffix
:
5293 err_msg
= _("invalid instruction suffix");
5296 err_msg
= _("constant doesn't fit in 4 bits");
5298 case unsupported_with_intel_mnemonic
:
5299 err_msg
= _("unsupported with Intel mnemonic");
5301 case unsupported_syntax
:
5302 err_msg
= _("unsupported syntax");
5305 as_bad (_("unsupported instruction `%s'"),
5306 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5308 case unsupported_on_arch
:
5309 as_bad (_("`%s' is not supported on `%s%s'"),
5310 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5311 cpu_arch_name
? cpu_arch_name
: default_arch
,
5312 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5314 case unsupported_64bit
:
5315 if (ISLOWER (mnem_suffix
))
5317 if (flag_code
== CODE_64BIT
)
5318 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5319 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5322 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5323 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5328 if (flag_code
== CODE_64BIT
)
5329 as_bad (_("`%s' is not supported in 64-bit mode"),
5330 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5332 as_bad (_("`%s' is only supported in 64-bit mode"),
5333 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5336 case invalid_sib_address
:
5337 err_msg
= _("invalid SIB address");
5339 case invalid_vsib_address
:
5340 err_msg
= _("invalid VSIB address");
5342 case invalid_vector_register_set
:
5343 err_msg
= _("mask, index, and destination registers must be distinct");
5345 case invalid_tmm_register_set
:
5346 err_msg
= _("all tmm registers must be distinct");
5348 case invalid_dest_and_src_register_set
:
5349 err_msg
= _("destination and source registers must be distinct");
5351 case unsupported_vector_index_register
:
5352 err_msg
= _("unsupported vector index register");
5354 case unsupported_broadcast
:
5355 err_msg
= _("unsupported broadcast");
5357 case broadcast_needed
:
5358 err_msg
= _("broadcast is needed for operand of such type");
5360 case unsupported_masking
:
5361 err_msg
= _("unsupported masking");
5363 case mask_not_on_destination
:
5364 err_msg
= _("mask not on destination operand");
5366 case no_default_mask
:
5367 err_msg
= _("default mask isn't allowed");
5369 case unsupported_rc_sae
:
5370 err_msg
= _("unsupported static rounding/sae");
5372 case invalid_register_operand
:
5373 err_msg
= _("invalid register operand");
5376 as_bad (_("%s for `%s'"), err_msg
,
5377 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5383 if (sse_check
!= check_none
5384 /* The opcode space check isn't strictly needed; it's there only to
5385 bypass the logic below when easily possible. */
5386 && t
->opcode_space
>= SPACE_0F
5387 && t
->opcode_space
<= SPACE_0F3A
5388 && !is_cpu (&i
.tm
, CpuSSE4a
)
5389 && !is_any_vex_encoding (t
))
5393 for (j
= 0; j
< t
->operands
; ++j
)
5395 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5397 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5401 if (j
>= t
->operands
&& simd
)
5402 (sse_check
== check_warning
5404 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5407 if (i
.tm
.opcode_modifier
.fwait
)
5408 if (!add_prefix (FWAIT_OPCODE
))
5411 /* Check if REP prefix is OK. */
5412 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5414 as_bad (_("invalid instruction `%s' after `%s'"),
5415 insn_name (&i
.tm
), i
.rep_prefix
);
5419 /* Check for lock without a lockable instruction. Destination operand
5420 must be memory unless it is xchg (0x86). */
5421 if (i
.prefix
[LOCK_PREFIX
])
5423 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5424 || i
.mem_operands
== 0
5425 || (i
.tm
.base_opcode
!= 0x86
5426 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5428 as_bad (_("expecting lockable instruction after `lock'"));
5432 /* Zap the redundant prefix from XCHG when optimizing. */
5433 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5434 i
.prefix
[LOCK_PREFIX
] = 0;
5437 if (is_any_vex_encoding (&i
.tm
)
5438 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5439 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5441 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5442 if (i
.prefix
[DATA_PREFIX
])
5444 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5448 /* Don't allow e.g. KMOV in TLS code sequences. */
5449 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5452 case BFD_RELOC_386_TLS_GOTIE
:
5453 case BFD_RELOC_386_TLS_LE_32
:
5454 case BFD_RELOC_X86_64_GOTTPOFF
:
5455 case BFD_RELOC_X86_64_TLSLD
:
5456 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5463 /* Check if HLE prefix is OK. */
5464 if (i
.hle_prefix
&& !check_hle ())
5467 /* Check BND prefix. */
5468 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5469 as_bad (_("expecting valid branch instruction after `bnd'"));
5471 /* Check NOTRACK prefix. */
5472 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5473 as_bad (_("expecting indirect branch instruction after `notrack'"));
5475 if (is_cpu (&i
.tm
, CpuMPX
))
5477 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5478 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5479 else if (flag_code
!= CODE_16BIT
5480 ? i
.prefix
[ADDR_PREFIX
]
5481 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5482 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5485 /* Insert BND prefix. */
5486 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5488 if (!i
.prefix
[BND_PREFIX
])
5489 add_prefix (BND_PREFIX_OPCODE
);
5490 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5492 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5493 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5497 /* Check string instruction segment overrides. */
5498 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5500 gas_assert (i
.mem_operands
);
5501 if (!check_string ())
5503 i
.disp_operands
= 0;
5506 /* The memory operand of (%dx) should be only used with input/output
5507 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5508 if (i
.input_output_operand
5509 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5510 || i
.tm
.opcode_space
!= SPACE_BASE
))
5512 as_bad (_("input/output port address isn't allowed with `%s'"),
5517 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5518 optimize_encoding ();
5520 /* Past optimization there's no need to distinguish vex_encoding_evex and
5521 vex_encoding_evex512 anymore. */
5522 if (i
.vec_encoding
== vex_encoding_evex512
)
5523 i
.vec_encoding
= vex_encoding_evex
;
5525 if (use_unaligned_vector_move
)
5526 encode_with_unaligned_vector_move ();
5528 if (!process_suffix ())
5531 /* Check if IP-relative addressing requirements can be satisfied. */
5532 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5533 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5534 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5536 /* Update operand types and check extended states. */
5537 for (j
= 0; j
< i
.operands
; j
++)
5539 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5540 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5545 i
.xstate
|= xstate_mmx
;
5548 i
.xstate
|= xstate_mask
;
5551 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5552 i
.xstate
|= xstate_tmm
;
5553 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5554 && !i
.tm
.opcode_modifier
.vex
5555 && vector_size
>= VSZ512
)
5556 i
.xstate
|= xstate_zmm
;
5557 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5558 && vector_size
>= VSZ256
)
5559 i
.xstate
|= xstate_ymm
;
5560 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5561 i
.xstate
|= xstate_xmm
;
5566 /* Make still unresolved immediate matches conform to size of immediate
5567 given in i.suffix. */
5568 if (!finalize_imm ())
5571 if (i
.types
[0].bitfield
.imm1
)
5572 i
.imm_operands
= 0; /* kludge for shift insns. */
5574 /* For insns with operands there are more diddles to do to the opcode. */
5577 if (!process_operands ())
5580 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5582 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5583 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5586 if (is_any_vex_encoding (&i
.tm
))
5588 if (!cpu_arch_flags
.bitfield
.cpui286
)
5590 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5595 /* Check for explicit REX prefix. */
5596 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5598 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5602 if (i
.tm
.opcode_modifier
.vex
)
5603 build_vex_prefix (t
);
5605 build_evex_prefix ();
5607 /* The individual REX.RXBW bits got consumed. */
5608 i
.rex
&= REX_OPCODE
;
5611 /* Handle conversion of 'int $3' --> special int3 insn. */
5612 if (i
.tm
.mnem_off
== MN_int
5613 && i
.op
[0].imms
->X_add_number
== 3)
5615 i
.tm
.base_opcode
= INT3_OPCODE
;
5619 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5620 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5621 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5622 && i
.op
[0].disps
->X_op
== O_constant
)
5624 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5625 the absolute address given by the constant. Since ix86 jumps and
5626 calls are pc relative, we need to generate a reloc. */
5627 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5628 i
.op
[0].disps
->X_op
= O_symbol
;
5631 /* For 8 bit registers we need an empty rex prefix. Also if the
5632 instruction already has a prefix, we need to convert old
5633 registers to new ones. */
5635 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5636 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5637 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5638 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5639 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5640 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5645 i
.rex
|= REX_OPCODE
;
5646 for (x
= 0; x
< 2; x
++)
5648 /* Look for 8 bit operand that uses old registers. */
5649 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5650 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5652 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5653 /* In case it is "hi" register, give up. */
5654 if (i
.op
[x
].regs
->reg_num
> 3)
5655 as_bad (_("can't encode register '%s%s' in an "
5656 "instruction requiring REX prefix."),
5657 register_prefix
, i
.op
[x
].regs
->reg_name
);
5659 /* Otherwise it is equivalent to the extended register.
5660 Since the encoding doesn't change this is merely
5661 cosmetic cleanup for debug output. */
5663 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5668 if (i
.rex
== 0 && i
.rex_encoding
)
5670 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5671 that uses legacy register. If it is "hi" register, don't add
5672 the REX_OPCODE byte. */
5674 for (x
= 0; x
< 2; x
++)
5675 if (i
.types
[x
].bitfield
.class == Reg
5676 && i
.types
[x
].bitfield
.byte
5677 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5678 && i
.op
[x
].regs
->reg_num
> 3)
5680 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5681 i
.rex_encoding
= false;
5690 add_prefix (REX_OPCODE
| i
.rex
);
5692 insert_lfence_before ();
5694 /* We are ready to output the insn. */
5697 insert_lfence_after ();
5699 last_insn
.seg
= now_seg
;
5701 if (i
.tm
.opcode_modifier
.isprefix
)
5703 last_insn
.kind
= last_insn_prefix
;
5704 last_insn
.name
= insn_name (&i
.tm
);
5705 last_insn
.file
= as_where (&last_insn
.line
);
5708 last_insn
.kind
= last_insn_other
;
5711 /* The Q suffix is generally valid only in 64-bit mode, with very few
5712 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5713 and fisttp only one of their two templates is matched below: That's
5714 sufficient since other relevant attributes are the same between both
5715 respective templates. */
5716 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5718 return flag_code
== CODE_64BIT
5719 || (t
->opcode_space
== SPACE_BASE
5720 && t
->base_opcode
== 0xdf
5721 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5722 || t
->mnem_off
== MN_cmpxchg8b
;
5726 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5728 const char *l
= line
, *token_start
= l
;
5730 bool pass1
= !current_templates
;
5732 const insn_template
*t
;
5738 /* Pseudo-prefixes start with an opening figure brace. */
5739 if ((*mnem_p
= *l
) == '{')
5744 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5749 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5752 as_bad (_("no such instruction: `%s'"), token_start
);
5757 /* Pseudo-prefixes end with a closing figure brace. */
5758 if (*mnemonic
== '{' && *l
== '}')
5761 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5765 /* Point l at the closing brace if there's no other separator. */
5766 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5767 && *l
!= PREFIX_SEPARATOR
)
5770 else if (!is_space_char (*l
)
5771 && *l
!= END_OF_INSN
5773 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5777 as_bad (_("invalid character %s in mnemonic"),
5778 output_invalid (*l
));
5781 if (token_start
== l
)
5783 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5784 as_bad (_("expecting prefix; got nothing"));
5786 as_bad (_("expecting mnemonic; got nothing"));
5790 /* Look up instruction (or prefix) via hash table. */
5791 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5793 if (*l
!= END_OF_INSN
5794 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5795 && current_templates
5796 && current_templates
->start
->opcode_modifier
.isprefix
)
5798 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5800 as_bad ((flag_code
!= CODE_64BIT
5801 ? _("`%s' is only supported in 64-bit mode")
5802 : _("`%s' is not supported in 64-bit mode")),
5803 insn_name (current_templates
->start
));
5806 /* If we are in 16-bit mode, do not allow addr16 or data16.
5807 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5808 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5809 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5810 && flag_code
!= CODE_64BIT
5811 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5812 ^ (flag_code
== CODE_16BIT
)))
5814 as_bad (_("redundant %s prefix"),
5815 insn_name (current_templates
->start
));
5819 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5821 /* Handle pseudo prefixes. */
5822 switch (current_templates
->start
->extension_opcode
)
5826 i
.disp_encoding
= disp_encoding_8bit
;
5830 i
.disp_encoding
= disp_encoding_16bit
;
5834 i
.disp_encoding
= disp_encoding_32bit
;
5838 i
.dir_encoding
= dir_encoding_load
;
5842 i
.dir_encoding
= dir_encoding_store
;
5846 i
.vec_encoding
= vex_encoding_vex
;
5850 i
.vec_encoding
= vex_encoding_vex3
;
5854 i
.vec_encoding
= vex_encoding_evex
;
5858 i
.rex_encoding
= true;
5860 case Prefix_NoOptimize
:
5862 i
.no_optimize
= true;
5870 /* Add prefix, checking for repeated prefixes. */
5871 switch (add_prefix (current_templates
->start
->base_opcode
))
5876 if (is_cpu (current_templates
->start
, CpuIBT
))
5877 i
.notrack_prefix
= insn_name (current_templates
->start
);
5880 if (is_cpu (current_templates
->start
, CpuHLE
))
5881 i
.hle_prefix
= insn_name (current_templates
->start
);
5882 else if (is_cpu (current_templates
->start
, CpuMPX
))
5883 i
.bnd_prefix
= insn_name (current_templates
->start
);
5885 i
.rep_prefix
= insn_name (current_templates
->start
);
5891 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5901 if (!current_templates
)
5903 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5904 Check if we should swap operand or force 32bit displacement in
5906 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5907 i
.dir_encoding
= dir_encoding_swap
;
5908 else if (mnem_p
- 3 == dot_p
5911 i
.disp_encoding
= disp_encoding_8bit
;
5912 else if (mnem_p
- 4 == dot_p
5916 i
.disp_encoding
= disp_encoding_32bit
;
5921 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5924 if (!current_templates
|| !pass1
)
5926 current_templates
= NULL
;
5929 if (mnem_p
> mnemonic
)
5931 /* See if we can get a match by trimming off a suffix. */
5934 case WORD_MNEM_SUFFIX
:
5935 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5936 i
.suffix
= SHORT_MNEM_SUFFIX
;
5939 case BYTE_MNEM_SUFFIX
:
5940 case QWORD_MNEM_SUFFIX
:
5941 i
.suffix
= mnem_p
[-1];
5944 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5946 case SHORT_MNEM_SUFFIX
:
5947 case LONG_MNEM_SUFFIX
:
5950 i
.suffix
= mnem_p
[-1];
5953 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5961 if (intel_float_operand (mnemonic
) == 1)
5962 i
.suffix
= SHORT_MNEM_SUFFIX
;
5964 i
.suffix
= LONG_MNEM_SUFFIX
;
5967 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5969 /* For compatibility reasons accept MOVSD and CMPSD without
5970 operands even in AT&T mode. */
5971 else if (*l
== END_OF_INSN
5972 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5976 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5977 if (current_templates
!= NULL
5979 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5980 && current_templates
->start
->opcode_space
5982 && mnem_p
[-2] == 's')
5984 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5985 mnemonic
, mnemonic
);
5986 i
.suffix
= LONG_MNEM_SUFFIX
;
5990 current_templates
= NULL
;
5998 if (!current_templates
)
6001 as_bad (_("no such instruction: `%s'"), token_start
);
6006 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
6007 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
6009 /* Check for a branch hint. We allow ",pt" and ",pn" for
6010 predict taken and predict not taken respectively.
6011 I'm not sure that branch hints actually do anything on loop
6012 and jcxz insns (JumpByte) for current Pentium4 chips. They
6013 may work in the future and it doesn't hurt to accept them
6015 if (l
[0] == ',' && l
[1] == 'p')
6019 if (!add_prefix (DS_PREFIX_OPCODE
))
6023 else if (l
[2] == 'n')
6025 if (!add_prefix (CS_PREFIX_OPCODE
))
6031 /* Any other comma loses. */
6034 as_bad (_("invalid character %s in mnemonic"),
6035 output_invalid (*l
));
6039 /* Check if instruction is supported on specified architecture. */
6041 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6043 supported
|= cpu_flags_match (t
);
6045 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6046 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6048 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6054 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6055 i
.error
= unsupported_on_arch
;
6057 i
.error
= unsupported_64bit
;
6064 parse_operands (char *l
, const char *mnemonic
)
6068 /* 1 if operand is pending after ','. */
6069 unsigned int expecting_operand
= 0;
6071 while (*l
!= END_OF_INSN
)
6073 /* Non-zero if operand parens not balanced. */
6074 unsigned int paren_not_balanced
= 0;
6075 /* True if inside double quotes. */
6076 bool in_quotes
= false;
6078 /* Skip optional white space before operand. */
6079 if (is_space_char (*l
))
6081 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6083 as_bad (_("invalid character %s before operand %d"),
6084 output_invalid (*l
),
6088 token_start
= l
; /* After white space. */
6089 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6091 if (*l
== END_OF_INSN
)
6095 as_bad (_("unbalanced double quotes in operand %d."),
6099 if (paren_not_balanced
)
6101 know (!intel_syntax
);
6102 as_bad (_("unbalanced parenthesis in operand %d."),
6107 break; /* we are done */
6109 else if (*l
== '\\' && l
[1] == '"')
6112 in_quotes
= !in_quotes
;
6113 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6115 as_bad (_("invalid character %s in operand %d"),
6116 output_invalid (*l
),
6120 if (!intel_syntax
&& !in_quotes
)
6123 ++paren_not_balanced
;
6125 --paren_not_balanced
;
6129 if (l
!= token_start
)
6130 { /* Yes, we've read in another operand. */
6131 unsigned int operand_ok
;
6132 this_operand
= i
.operands
++;
6133 if (i
.operands
> MAX_OPERANDS
)
6135 as_bad (_("spurious operands; (%d operands/instruction max)"),
6139 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6140 /* Now parse operand adding info to 'i' as we go along. */
6141 END_STRING_AND_SAVE (l
);
6143 if (i
.mem_operands
> 1)
6145 as_bad (_("too many memory references for `%s'"),
6152 i386_intel_operand (token_start
,
6153 intel_float_operand (mnemonic
));
6155 operand_ok
= i386_att_operand (token_start
);
6157 RESTORE_END_STRING (l
);
6163 if (expecting_operand
)
6165 expecting_operand_after_comma
:
6166 as_bad (_("expecting operand after ','; got nothing"));
6171 as_bad (_("expecting operand before ','; got nothing"));
6176 /* Now *l must be either ',' or END_OF_INSN. */
6179 if (*++l
== END_OF_INSN
)
6181 /* Just skip it, if it's \n complain. */
6182 goto expecting_operand_after_comma
;
6184 expecting_operand
= 1;
6191 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6193 union i386_op temp_op
;
6194 i386_operand_type temp_type
;
6195 unsigned int temp_flags
;
6196 enum bfd_reloc_code_real temp_reloc
;
6198 temp_type
= i
.types
[xchg2
];
6199 i
.types
[xchg2
] = i
.types
[xchg1
];
6200 i
.types
[xchg1
] = temp_type
;
6202 temp_flags
= i
.flags
[xchg2
];
6203 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6204 i
.flags
[xchg1
] = temp_flags
;
6206 temp_op
= i
.op
[xchg2
];
6207 i
.op
[xchg2
] = i
.op
[xchg1
];
6208 i
.op
[xchg1
] = temp_op
;
6210 temp_reloc
= i
.reloc
[xchg2
];
6211 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6212 i
.reloc
[xchg1
] = temp_reloc
;
6214 temp_flags
= i
.imm_bits
[xchg2
];
6215 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6216 i
.imm_bits
[xchg1
] = temp_flags
;
6220 if (i
.mask
.operand
== xchg1
)
6221 i
.mask
.operand
= xchg2
;
6222 else if (i
.mask
.operand
== xchg2
)
6223 i
.mask
.operand
= xchg1
;
6225 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6227 if (i
.broadcast
.operand
== xchg1
)
6228 i
.broadcast
.operand
= xchg2
;
6229 else if (i
.broadcast
.operand
== xchg2
)
6230 i
.broadcast
.operand
= xchg1
;
6235 swap_operands (void)
6241 swap_2_operands (1, i
.operands
- 2);
6245 swap_2_operands (0, i
.operands
- 1);
6251 if (i
.mem_operands
== 2)
6253 const reg_entry
*temp_seg
;
6254 temp_seg
= i
.seg
[0];
6255 i
.seg
[0] = i
.seg
[1];
6256 i
.seg
[1] = temp_seg
;
6260 /* Try to ensure constant immediates are represented in the smallest
6265 char guess_suffix
= 0;
6269 guess_suffix
= i
.suffix
;
6270 else if (i
.reg_operands
)
6272 /* Figure out a suffix from the last register operand specified.
6273 We can't do this properly yet, i.e. excluding special register
6274 instances, but the following works for instructions with
6275 immediates. In any case, we can't set i.suffix yet. */
6276 for (op
= i
.operands
; --op
>= 0;)
6277 if (i
.types
[op
].bitfield
.class != Reg
)
6279 else if (i
.types
[op
].bitfield
.byte
)
6281 guess_suffix
= BYTE_MNEM_SUFFIX
;
6284 else if (i
.types
[op
].bitfield
.word
)
6286 guess_suffix
= WORD_MNEM_SUFFIX
;
6289 else if (i
.types
[op
].bitfield
.dword
)
6291 guess_suffix
= LONG_MNEM_SUFFIX
;
6294 else if (i
.types
[op
].bitfield
.qword
)
6296 guess_suffix
= QWORD_MNEM_SUFFIX
;
6300 else if ((flag_code
== CODE_16BIT
)
6301 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6302 guess_suffix
= WORD_MNEM_SUFFIX
;
6303 else if (flag_code
!= CODE_64BIT
6304 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6305 /* A more generic (but also more involved) way of dealing
6306 with the special case(s) would be to go look for
6307 DefaultSize attributes on any of the templates. */
6308 && current_templates
->start
->mnem_off
!= MN_push
))
6309 guess_suffix
= LONG_MNEM_SUFFIX
;
6311 for (op
= i
.operands
; --op
>= 0;)
6312 if (operand_type_check (i
.types
[op
], imm
))
6314 switch (i
.op
[op
].imms
->X_op
)
6317 /* If a suffix is given, this operand may be shortened. */
6318 switch (guess_suffix
)
6320 case LONG_MNEM_SUFFIX
:
6321 i
.types
[op
].bitfield
.imm32
= 1;
6322 i
.types
[op
].bitfield
.imm64
= 1;
6324 case WORD_MNEM_SUFFIX
:
6325 i
.types
[op
].bitfield
.imm16
= 1;
6326 i
.types
[op
].bitfield
.imm32
= 1;
6327 i
.types
[op
].bitfield
.imm32s
= 1;
6328 i
.types
[op
].bitfield
.imm64
= 1;
6330 case BYTE_MNEM_SUFFIX
:
6331 i
.types
[op
].bitfield
.imm8
= 1;
6332 i
.types
[op
].bitfield
.imm8s
= 1;
6333 i
.types
[op
].bitfield
.imm16
= 1;
6334 i
.types
[op
].bitfield
.imm32
= 1;
6335 i
.types
[op
].bitfield
.imm32s
= 1;
6336 i
.types
[op
].bitfield
.imm64
= 1;
6340 /* If this operand is at most 16 bits, convert it
6341 to a signed 16 bit number before trying to see
6342 whether it will fit in an even smaller size.
6343 This allows a 16-bit operand such as $0xffe0 to
6344 be recognised as within Imm8S range. */
6345 if ((i
.types
[op
].bitfield
.imm16
)
6346 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6348 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6349 ^ 0x8000) - 0x8000);
6352 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6353 if ((i
.types
[op
].bitfield
.imm32
)
6354 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6356 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6357 ^ ((offsetT
) 1 << 31))
6358 - ((offsetT
) 1 << 31));
6362 = operand_type_or (i
.types
[op
],
6363 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6365 /* We must avoid matching of Imm32 templates when 64bit
6366 only immediate is available. */
6367 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6368 i
.types
[op
].bitfield
.imm32
= 0;
6375 /* Symbols and expressions. */
6377 /* Convert symbolic operand to proper sizes for matching, but don't
6378 prevent matching a set of insns that only supports sizes other
6379 than those matching the insn suffix. */
6381 i386_operand_type mask
, allowed
;
6382 const insn_template
*t
= current_templates
->start
;
6384 operand_type_set (&mask
, 0);
6385 switch (guess_suffix
)
6387 case QWORD_MNEM_SUFFIX
:
6388 mask
.bitfield
.imm64
= 1;
6389 mask
.bitfield
.imm32s
= 1;
6391 case LONG_MNEM_SUFFIX
:
6392 mask
.bitfield
.imm32
= 1;
6394 case WORD_MNEM_SUFFIX
:
6395 mask
.bitfield
.imm16
= 1;
6397 case BYTE_MNEM_SUFFIX
:
6398 mask
.bitfield
.imm8
= 1;
6404 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6405 while (++t
< current_templates
->end
)
6407 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6408 allowed
= operand_type_and (allowed
, mask
);
6411 if (!operand_type_all_zero (&allowed
))
6412 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6419 /* Try to use the smallest displacement type too. */
6421 optimize_disp (const insn_template
*t
)
6425 if (!want_disp32 (t
)
6426 && (!t
->opcode_modifier
.jump
6427 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6429 for (op
= 0; op
< i
.operands
; ++op
)
6431 const expressionS
*exp
= i
.op
[op
].disps
;
6433 if (!operand_type_check (i
.types
[op
], disp
))
6436 if (exp
->X_op
!= O_constant
)
6439 /* Since displacement is signed extended to 64bit, don't allow
6440 disp32 if it is out of range. */
6441 if (fits_in_signed_long (exp
->X_add_number
))
6444 i
.types
[op
].bitfield
.disp32
= 0;
6445 if (i
.types
[op
].bitfield
.baseindex
)
6447 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6448 (uint64_t) exp
->X_add_number
);
6454 /* Don't optimize displacement for movabs since it only takes 64bit
6456 if (i
.disp_encoding
> disp_encoding_8bit
6457 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6460 for (op
= i
.operands
; op
-- > 0;)
6461 if (operand_type_check (i
.types
[op
], disp
))
6463 if (i
.op
[op
].disps
->X_op
== O_constant
)
6465 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6467 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6469 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6470 i
.op
[op
].disps
= NULL
;
6475 if (i
.types
[op
].bitfield
.disp16
6476 && fits_in_unsigned_word (op_disp
))
6478 /* If this operand is at most 16 bits, convert
6479 to a signed 16 bit number and don't use 64bit
6481 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6482 i
.types
[op
].bitfield
.disp64
= 0;
6486 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6487 if ((flag_code
!= CODE_64BIT
6488 ? i
.types
[op
].bitfield
.disp32
6490 && (!t
->opcode_modifier
.jump
6491 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6492 && fits_in_unsigned_long (op_disp
))
6494 /* If this operand is at most 32 bits, convert
6495 to a signed 32 bit number and don't use 64bit
6497 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6498 i
.types
[op
].bitfield
.disp64
= 0;
6499 i
.types
[op
].bitfield
.disp32
= 1;
6502 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6504 i
.types
[op
].bitfield
.disp64
= 0;
6505 i
.types
[op
].bitfield
.disp32
= 1;
6508 if ((i
.types
[op
].bitfield
.disp32
6509 || i
.types
[op
].bitfield
.disp16
)
6510 && fits_in_disp8 (op_disp
))
6511 i
.types
[op
].bitfield
.disp8
= 1;
6513 i
.op
[op
].disps
->X_add_number
= op_disp
;
6515 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6516 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6518 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6519 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6520 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6523 /* We only support 64bit displacement on constants. */
6524 i
.types
[op
].bitfield
.disp64
= 0;
6530 /* Return 1 if there is a match in broadcast bytes between operand
6531 GIVEN and instruction template T. */
6534 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6536 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6537 && i
.types
[given
].bitfield
.byte
)
6538 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6539 && i
.types
[given
].bitfield
.word
)
6540 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6541 && i
.types
[given
].bitfield
.dword
)
6542 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6543 && i
.types
[given
].bitfield
.qword
));
6546 /* Check if operands are valid for the instruction. */
6549 check_VecOperands (const insn_template
*t
)
6554 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6555 any one operand are implicity requiring AVX512VL support if the actual
6556 operand size is YMMword or XMMword. Since this function runs after
6557 template matching, there's no need to check for YMMword/XMMword in
6559 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6560 if (!cpu_flags_all_zero (&cpu
)
6561 && !is_cpu (t
, CpuAVX512VL
)
6562 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6563 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6565 for (op
= 0; op
< t
->operands
; ++op
)
6567 if (t
->operand_types
[op
].bitfield
.zmmword
6568 && (i
.types
[op
].bitfield
.ymmword
6569 || i
.types
[op
].bitfield
.xmmword
))
6571 i
.error
= unsupported
;
6577 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6578 requiring AVX2 support if the actual operand size is YMMword. */
6579 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6580 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6582 for (op
= 0; op
< t
->operands
; ++op
)
6584 if (t
->operand_types
[op
].bitfield
.xmmword
6585 && i
.types
[op
].bitfield
.ymmword
)
6587 i
.error
= unsupported
;
6593 /* Without VSIB byte, we can't have a vector register for index. */
6594 if (!t
->opcode_modifier
.sib
6596 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6597 || i
.index_reg
->reg_type
.bitfield
.ymmword
6598 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6600 i
.error
= unsupported_vector_index_register
;
6604 /* Check if default mask is allowed. */
6605 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6606 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6608 i
.error
= no_default_mask
;
6612 /* For VSIB byte, we need a vector register for index, and all vector
6613 registers must be distinct. */
6614 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6617 || !((t
->opcode_modifier
.sib
== VECSIB128
6618 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6619 || (t
->opcode_modifier
.sib
== VECSIB256
6620 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6621 || (t
->opcode_modifier
.sib
== VECSIB512
6622 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6624 i
.error
= invalid_vsib_address
;
6628 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6629 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6631 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6632 gas_assert (i
.types
[0].bitfield
.xmmword
6633 || i
.types
[0].bitfield
.ymmword
);
6634 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6635 gas_assert (i
.types
[2].bitfield
.xmmword
6636 || i
.types
[2].bitfield
.ymmword
);
6637 if (operand_check
== check_none
)
6639 if (register_number (i
.op
[0].regs
)
6640 != register_number (i
.index_reg
)
6641 && register_number (i
.op
[2].regs
)
6642 != register_number (i
.index_reg
)
6643 && register_number (i
.op
[0].regs
)
6644 != register_number (i
.op
[2].regs
))
6646 if (operand_check
== check_error
)
6648 i
.error
= invalid_vector_register_set
;
6651 as_warn (_("mask, index, and destination registers should be distinct"));
6653 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6655 if (i
.types
[1].bitfield
.class == RegSIMD
6656 && (i
.types
[1].bitfield
.xmmword
6657 || i
.types
[1].bitfield
.ymmword
6658 || i
.types
[1].bitfield
.zmmword
)
6659 && (register_number (i
.op
[1].regs
)
6660 == register_number (i
.index_reg
)))
6662 if (operand_check
== check_error
)
6664 i
.error
= invalid_vector_register_set
;
6667 if (operand_check
!= check_none
)
6668 as_warn (_("index and destination registers should be distinct"));
6673 /* For AMX instructions with 3 TMM register operands, all operands
6674 must be distinct. */
6675 if (i
.reg_operands
== 3
6676 && t
->operand_types
[0].bitfield
.tmmword
6677 && (i
.op
[0].regs
== i
.op
[1].regs
6678 || i
.op
[0].regs
== i
.op
[2].regs
6679 || i
.op
[1].regs
== i
.op
[2].regs
))
6681 i
.error
= invalid_tmm_register_set
;
6685 /* For some special instructions require that destination must be distinct
6686 from source registers. */
6687 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6689 unsigned int dest_reg
= i
.operands
- 1;
6691 know (i
.operands
>= 3);
6693 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6694 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6695 || (i
.reg_operands
> 2
6696 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6698 i
.error
= invalid_dest_and_src_register_set
;
6703 /* Check if broadcast is supported by the instruction and is applied
6704 to the memory operand. */
6705 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6707 i386_operand_type type
, overlap
;
6709 /* Check if specified broadcast is supported in this instruction,
6710 and its broadcast bytes match the memory operand. */
6711 op
= i
.broadcast
.operand
;
6712 if (!t
->opcode_modifier
.broadcast
6713 || !(i
.flags
[op
] & Operand_Mem
)
6714 || (!i
.types
[op
].bitfield
.unspecified
6715 && !match_broadcast_size (t
, op
)))
6718 i
.error
= unsupported_broadcast
;
6722 operand_type_set (&type
, 0);
6723 switch (get_broadcast_bytes (t
, false))
6726 type
.bitfield
.word
= 1;
6729 type
.bitfield
.dword
= 1;
6732 type
.bitfield
.qword
= 1;
6735 type
.bitfield
.xmmword
= 1;
6738 if (vector_size
< VSZ256
)
6740 type
.bitfield
.ymmword
= 1;
6743 if (vector_size
< VSZ512
)
6745 type
.bitfield
.zmmword
= 1;
6751 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6752 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6753 && t
->operand_types
[op
].bitfield
.byte
6754 + t
->operand_types
[op
].bitfield
.word
6755 + t
->operand_types
[op
].bitfield
.dword
6756 + t
->operand_types
[op
].bitfield
.qword
> 1)
6758 overlap
.bitfield
.xmmword
= 0;
6759 overlap
.bitfield
.ymmword
= 0;
6760 overlap
.bitfield
.zmmword
= 0;
6762 if (operand_type_all_zero (&overlap
))
6765 if (t
->opcode_modifier
.checkoperandsize
)
6769 type
.bitfield
.baseindex
= 1;
6770 for (j
= 0; j
< i
.operands
; ++j
)
6773 && !operand_type_register_match(i
.types
[j
],
6774 t
->operand_types
[j
],
6776 t
->operand_types
[op
]))
6781 /* If broadcast is supported in this instruction, we need to check if
6782 operand of one-element size isn't specified without broadcast. */
6783 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6785 /* Find memory operand. */
6786 for (op
= 0; op
< i
.operands
; op
++)
6787 if (i
.flags
[op
] & Operand_Mem
)
6789 gas_assert (op
< i
.operands
);
6790 /* Check size of the memory operand. */
6791 if (match_broadcast_size (t
, op
))
6793 i
.error
= broadcast_needed
;
6798 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6800 /* Check if requested masking is supported. */
6803 if (!t
->opcode_modifier
.masking
)
6805 i
.error
= unsupported_masking
;
6809 /* Common rules for masking:
6810 - mask register destinations permit only zeroing-masking, without
6811 that actually being expressed by a {z} operand suffix or EVEX.z,
6812 - memory destinations allow only merging-masking,
6813 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6816 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6817 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6818 || t
->opcode_modifier
.sib
))
6820 i
.error
= unsupported_masking
;
6825 /* Check if masking is applied to dest operand. */
6826 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6828 i
.error
= mask_not_on_destination
;
6833 if (i
.rounding
.type
!= rc_none
)
6835 if (!t
->opcode_modifier
.sae
6836 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6839 i
.error
= unsupported_rc_sae
;
6843 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6845 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6847 for (op
= 0; op
< t
->operands
; ++op
)
6848 if (i
.types
[op
].bitfield
.zmmword
)
6850 if (op
>= t
->operands
)
6852 i
.error
= operand_size_mismatch
;
6858 /* Check the special Imm4 cases; must be the first operand. */
6859 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6861 if (i
.op
[0].imms
->X_op
!= O_constant
6862 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6868 /* Turn off Imm<N> so that update_imm won't complain. */
6869 operand_type_set (&i
.types
[0], 0);
6872 /* Check vector Disp8 operand. */
6873 if (t
->opcode_modifier
.disp8memshift
6874 && (!t
->opcode_modifier
.vex
6875 || need_evex_encoding ())
6876 && i
.disp_encoding
<= disp_encoding_8bit
)
6878 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6879 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6880 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6881 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6884 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6887 for (op
= 0; op
< i
.operands
; op
++)
6888 if (i
.flags
[op
] & Operand_Mem
)
6890 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6891 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6892 else if (t
->operand_types
[op
].bitfield
.xmmword
6893 + t
->operand_types
[op
].bitfield
.ymmword
6894 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6895 type
= &t
->operand_types
[op
];
6896 else if (!i
.types
[op
].bitfield
.unspecified
)
6897 type
= &i
.types
[op
];
6898 else /* Ambiguities get resolved elsewhere. */
6899 fallback
= &t
->operand_types
[op
];
6901 else if (i
.types
[op
].bitfield
.class == RegSIMD
6902 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6904 if (i
.types
[op
].bitfield
.zmmword
)
6906 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6908 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6912 if (!type
&& !i
.memshift
)
6916 if (type
->bitfield
.zmmword
)
6918 else if (type
->bitfield
.ymmword
)
6920 else if (type
->bitfield
.xmmword
)
6924 /* For the check in fits_in_disp8(). */
6925 if (i
.memshift
== 0)
6929 for (op
= 0; op
< i
.operands
; op
++)
6930 if (operand_type_check (i
.types
[op
], disp
)
6931 && i
.op
[op
].disps
->X_op
== O_constant
)
6933 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6935 i
.types
[op
].bitfield
.disp8
= 1;
6938 i
.types
[op
].bitfield
.disp8
= 0;
6947 /* Check if encoding requirements are met by the instruction. */
6950 VEX_check_encoding (const insn_template
*t
)
6952 if (i
.vec_encoding
== vex_encoding_error
)
6954 i
.error
= unsupported
;
6958 /* Vector size restrictions. */
6959 if ((vector_size
< VSZ512
6960 && (t
->opcode_modifier
.evex
== EVEX512
6961 || t
->opcode_modifier
.vsz
>= VSZ512
))
6962 || (vector_size
< VSZ256
6963 && (t
->opcode_modifier
.evex
== EVEX256
6964 || t
->opcode_modifier
.vex
== VEX256
6965 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6967 i
.error
= unsupported
;
6971 if (i
.vec_encoding
== vex_encoding_evex
6972 || i
.vec_encoding
== vex_encoding_evex512
)
6974 /* This instruction must be encoded with EVEX prefix. */
6975 if (!is_evex_encoding (t
))
6977 i
.error
= unsupported
;
6983 if (!t
->opcode_modifier
.vex
)
6985 /* This instruction template doesn't have VEX prefix. */
6986 if (i
.vec_encoding
!= vex_encoding_default
)
6988 i
.error
= unsupported
;
6997 /* Helper function for the progress() macro in match_template(). */
6998 static INLINE
enum i386_error
progress (enum i386_error
new,
6999 enum i386_error last
,
7000 unsigned int line
, unsigned int *line_p
)
7002 if (line
<= *line_p
)
7008 static const insn_template
*
7009 match_template (char mnem_suffix
)
7011 /* Points to template once we've found it. */
7012 const insn_template
*t
;
7013 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
7014 i386_operand_type overlap4
;
7015 unsigned int found_reverse_match
;
7016 i386_operand_type operand_types
[MAX_OPERANDS
];
7017 int addr_prefix_disp
;
7018 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7019 enum i386_error specific_error
= number_of_operands_mismatch
;
7020 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7022 #if MAX_OPERANDS != 5
7023 # error "MAX_OPERANDS must be 5."
7026 found_reverse_match
= 0;
7027 addr_prefix_disp
= -1;
7029 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7031 addr_prefix_disp
= -1;
7032 found_reverse_match
= 0;
7034 /* Must have right number of operands. */
7035 if (i
.operands
!= t
->operands
)
7038 /* Check processor support. */
7039 specific_error
= progress (unsupported
);
7040 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7043 /* Check AT&T mnemonic. */
7044 specific_error
= progress (unsupported_with_intel_mnemonic
);
7045 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7048 /* Check AT&T/Intel syntax. */
7049 specific_error
= progress (unsupported_syntax
);
7050 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7051 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7054 /* Check Intel64/AMD64 ISA. */
7058 /* Default: Don't accept Intel64. */
7059 if (t
->opcode_modifier
.isa64
== INTEL64
)
7063 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7064 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7068 /* -mintel64: Don't accept AMD64. */
7069 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7074 /* Check the suffix. */
7075 specific_error
= progress (invalid_instruction_suffix
);
7076 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7077 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7078 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7079 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7080 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7083 specific_error
= progress (operand_size_mismatch
);
7084 size_match
= operand_size_match (t
);
7088 /* This is intentionally not
7090 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7092 as the case of a missing * on the operand is accepted (perhaps with
7093 a warning, issued further down). */
7094 specific_error
= progress (operand_type_mismatch
);
7095 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7098 /* In Intel syntax, normally we can check for memory operand size when
7099 there is no mnemonic suffix. But jmp and call have 2 different
7100 encodings with Dword memory operand size. Skip the "near" one
7101 (permitting a register operand) when "far" was requested. */
7103 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7104 && t
->operand_types
[0].bitfield
.class == Reg
)
7107 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7108 operand_types
[j
] = t
->operand_types
[j
];
7110 /* In general, don't allow 32-bit operands on pre-386. */
7111 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7112 : operand_size_mismatch
);
7113 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7114 if (i
.suffix
== LONG_MNEM_SUFFIX
7115 && !cpu_arch_flags
.bitfield
.cpui386
7117 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7118 && !intel_float_operand (insn_name (t
)))
7119 : intel_float_operand (insn_name (t
)) != 2)
7120 && (t
->operands
== i
.imm_operands
7121 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7122 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7123 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7124 || (operand_types
[j
].bitfield
.class != RegMMX
7125 && operand_types
[j
].bitfield
.class != RegSIMD
7126 && operand_types
[j
].bitfield
.class != RegMask
))
7127 && !t
->opcode_modifier
.sib
)
7130 /* Do not verify operands when there are none. */
7133 if (VEX_check_encoding (t
))
7135 specific_error
= progress (i
.error
);
7139 /* We've found a match; break out of loop. */
7143 if (!t
->opcode_modifier
.jump
7144 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7146 /* There should be only one Disp operand. */
7147 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7148 if (operand_type_check (operand_types
[j
], disp
))
7150 if (j
< MAX_OPERANDS
)
7152 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7154 addr_prefix_disp
= j
;
7156 /* Address size prefix will turn Disp64 operand into Disp32 and
7157 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7161 override
= !override
;
7164 if (operand_types
[j
].bitfield
.disp32
7165 && operand_types
[j
].bitfield
.disp16
)
7167 operand_types
[j
].bitfield
.disp16
= override
;
7168 operand_types
[j
].bitfield
.disp32
= !override
;
7170 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7174 if (operand_types
[j
].bitfield
.disp64
)
7176 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7177 operand_types
[j
].bitfield
.disp32
= override
;
7178 operand_types
[j
].bitfield
.disp64
= !override
;
7180 operand_types
[j
].bitfield
.disp16
= 0;
7186 /* We check register size if needed. */
7187 if (t
->opcode_modifier
.checkoperandsize
)
7189 check_register
= (1 << t
->operands
) - 1;
7190 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7191 check_register
&= ~(1 << i
.broadcast
.operand
);
7196 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7197 switch (t
->operands
)
7200 if (!operand_type_match (overlap0
, i
.types
[0]))
7203 /* Allow the ModR/M encoding to be requested by using the {load} or
7204 {store} pseudo prefix on an applicable insn. */
7205 if (!t
->opcode_modifier
.modrm
7206 && i
.reg_operands
== 1
7207 && ((i
.dir_encoding
== dir_encoding_load
7208 && t
->mnem_off
!= MN_pop
)
7209 || (i
.dir_encoding
== dir_encoding_store
7210 && t
->mnem_off
!= MN_push
))
7212 && t
->mnem_off
!= MN_bswap
)
7217 /* xchg %eax, %eax is a special case. It is an alias for nop
7218 only in 32bit mode and we can use opcode 0x90. In 64bit
7219 mode, we can't use 0x90 for xchg %eax, %eax since it should
7220 zero-extend %eax to %rax. */
7221 if (t
->base_opcode
== 0x90
7222 && t
->opcode_space
== SPACE_BASE
)
7224 if (flag_code
== CODE_64BIT
7225 && i
.types
[0].bitfield
.instance
== Accum
7226 && i
.types
[0].bitfield
.dword
7227 && i
.types
[1].bitfield
.instance
== Accum
)
7230 /* Allow the ModR/M encoding to be requested by using the
7231 {load} or {store} pseudo prefix. */
7232 if (i
.dir_encoding
== dir_encoding_load
7233 || i
.dir_encoding
== dir_encoding_store
)
7237 if (t
->base_opcode
== MOV_AX_DISP32
7238 && t
->opcode_space
== SPACE_BASE
7239 && t
->mnem_off
!= MN_movabs
)
7241 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7242 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7245 /* xrelease mov %eax, <disp> is another special case. It must not
7246 match the accumulator-only encoding of mov. */
7250 /* Allow the ModR/M encoding to be requested by using a suitable
7251 {load} or {store} pseudo prefix. */
7252 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7253 ? dir_encoding_store
7254 : dir_encoding_load
)
7255 && !i
.types
[0].bitfield
.disp64
7256 && !i
.types
[1].bitfield
.disp64
)
7260 /* Allow the ModR/M encoding to be requested by using the {load} or
7261 {store} pseudo prefix on an applicable insn. */
7262 if (!t
->opcode_modifier
.modrm
7263 && i
.reg_operands
== 1
7264 && i
.imm_operands
== 1
7265 && (i
.dir_encoding
== dir_encoding_load
7266 || i
.dir_encoding
== dir_encoding_store
)
7267 && t
->opcode_space
== SPACE_BASE
)
7269 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7270 && i
.dir_encoding
== dir_encoding_store
)
7273 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7274 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7275 || i
.dir_encoding
== dir_encoding_load
))
7278 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7279 && i
.dir_encoding
== dir_encoding_load
)
7285 if (!(size_match
& MATCH_STRAIGHT
))
7287 /* Reverse direction of operands if swapping is possible in the first
7288 place (operands need to be symmetric) and
7289 - the load form is requested, and the template is a store form,
7290 - the store form is requested, and the template is a load form,
7291 - the non-default (swapped) form is requested. */
7292 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7293 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7294 && !operand_type_all_zero (&overlap1
))
7295 switch (i
.dir_encoding
)
7297 case dir_encoding_load
:
7298 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7299 || t
->opcode_modifier
.regmem
)
7303 case dir_encoding_store
:
7304 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7305 && !t
->opcode_modifier
.regmem
)
7309 case dir_encoding_swap
:
7312 case dir_encoding_default
:
7315 /* If we want store form, we skip the current load. */
7316 if ((i
.dir_encoding
== dir_encoding_store
7317 || i
.dir_encoding
== dir_encoding_swap
)
7318 && i
.mem_operands
== 0
7319 && t
->opcode_modifier
.load
)
7324 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7325 if (!operand_type_match (overlap0
, i
.types
[0])
7326 || !operand_type_match (overlap1
, i
.types
[1])
7327 || ((check_register
& 3) == 3
7328 && !operand_type_register_match (i
.types
[0],
7333 specific_error
= progress (i
.error
);
7335 /* Check if other direction is valid ... */
7336 if (!t
->opcode_modifier
.d
)
7340 if (!(size_match
& MATCH_REVERSE
))
7342 /* Try reversing direction of operands. */
7343 j
= is_cpu (t
, CpuFMA4
)
7344 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7345 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7346 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7347 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7348 gas_assert (t
->operands
!= 3 || !check_register
);
7349 if (!operand_type_match (overlap0
, i
.types
[0])
7350 || !operand_type_match (overlap1
, i
.types
[j
])
7351 || (t
->operands
== 3
7352 && !operand_type_match (overlap2
, i
.types
[1]))
7354 && !operand_type_register_match (i
.types
[0],
7359 /* Does not match either direction. */
7360 specific_error
= progress (i
.error
);
7363 /* found_reverse_match holds which variant of D
7365 if (!t
->opcode_modifier
.d
)
7366 found_reverse_match
= 0;
7367 else if (operand_types
[0].bitfield
.tbyte
)
7369 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7370 found_reverse_match
= Opcode_FloatD
;
7372 found_reverse_match
= ~0;
7373 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7374 if ((t
->extension_opcode
& 4)
7375 && (intel_syntax
|| intel_mnemonic
))
7376 found_reverse_match
|= Opcode_FloatR
;
7378 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7380 found_reverse_match
= Opcode_VexW
;
7381 goto check_operands_345
;
7383 else if (t
->opcode_space
!= SPACE_BASE
7384 && (t
->opcode_space
!= SPACE_0F
7385 /* MOV to/from CR/DR/TR, as an exception, follow
7386 the base opcode space encoding model. */
7387 || (t
->base_opcode
| 7) != 0x27))
7388 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7389 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7390 else if (!t
->opcode_modifier
.commutative
)
7391 found_reverse_match
= Opcode_D
;
7393 found_reverse_match
= ~0;
7397 /* Found a forward 2 operand match here. */
7399 switch (t
->operands
)
7402 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7403 if (!operand_type_match (overlap4
, i
.types
[4])
7404 || !operand_type_register_match (i
.types
[3],
7409 specific_error
= progress (i
.error
);
7414 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7415 if (!operand_type_match (overlap3
, i
.types
[3])
7416 || ((check_register
& 0xa) == 0xa
7417 && !operand_type_register_match (i
.types
[1],
7421 || ((check_register
& 0xc) == 0xc
7422 && !operand_type_register_match (i
.types
[2],
7427 specific_error
= progress (i
.error
);
7432 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7433 if (!operand_type_match (overlap2
, i
.types
[2])
7434 || ((check_register
& 5) == 5
7435 && !operand_type_register_match (i
.types
[0],
7439 || ((check_register
& 6) == 6
7440 && !operand_type_register_match (i
.types
[1],
7445 specific_error
= progress (i
.error
);
7451 /* Found either forward/reverse 2, 3 or 4 operand match here:
7452 slip through to break. */
7455 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7456 if (VEX_check_encoding (t
))
7458 specific_error
= progress (i
.error
);
7462 /* Check if vector operands are valid. */
7463 if (check_VecOperands (t
))
7465 specific_error
= progress (i
.error
);
7469 /* We've found a match; break out of loop. */
7475 if (t
== current_templates
->end
)
7477 /* We found no match. */
7478 i
.error
= specific_error
;
7482 if (!quiet_warnings
)
7485 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7486 as_warn (_("indirect %s without `*'"), insn_name (t
));
7488 if (t
->opcode_modifier
.isprefix
7489 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7491 /* Warn them that a data or address size prefix doesn't
7492 affect assembly of the next line of code. */
7493 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7497 /* Copy the template we found. */
7498 install_template (t
);
7500 if (addr_prefix_disp
!= -1)
7501 i
.tm
.operand_types
[addr_prefix_disp
]
7502 = operand_types
[addr_prefix_disp
];
7504 switch (found_reverse_match
)
7510 case Opcode_FloatR
| Opcode_FloatD
:
7511 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7512 found_reverse_match
&= Opcode_FloatD
;
7516 /* If we found a reverse match we must alter the opcode direction
7517 bit and clear/flip the regmem modifier one. found_reverse_match
7518 holds bits to change (different for int & float insns). */
7520 i
.tm
.base_opcode
^= found_reverse_match
;
7522 /* Certain SIMD insns have their load forms specified in the opcode
7523 table, and hence we need to _set_ RegMem instead of clearing it.
7524 We need to avoid setting the bit though on insns like KMOVW. */
7525 i
.tm
.opcode_modifier
.regmem
7526 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7527 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7528 && !i
.tm
.opcode_modifier
.regmem
;
7532 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7533 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7537 /* Only the first two register operands need reversing, alongside
7539 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7541 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7542 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7543 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7553 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7554 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7556 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7558 as_bad (_("`%s' operand %u must use `%ses' segment"),
7560 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7565 /* There's only ever one segment override allowed per instruction.
7566 This instruction possibly has a legal segment override on the
7567 second operand, so copy the segment to where non-string
7568 instructions store it, allowing common code. */
7569 i
.seg
[op
] = i
.seg
[1];
7575 process_suffix (void)
7577 bool is_movx
= false;
7579 /* If matched instruction specifies an explicit instruction mnemonic
7581 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7582 i
.suffix
= WORD_MNEM_SUFFIX
;
7583 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7584 i
.suffix
= LONG_MNEM_SUFFIX
;
7585 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7586 i
.suffix
= QWORD_MNEM_SUFFIX
;
7587 else if (i
.reg_operands
7588 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7589 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7591 unsigned int numop
= i
.operands
;
7594 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7595 && (i
.tm
.base_opcode
| 8) == 0xbe)
7596 || (i
.tm
.opcode_space
== SPACE_BASE
7597 && i
.tm
.base_opcode
== 0x63
7598 && is_cpu (&i
.tm
, Cpu64
));
7600 /* movsx/movzx want only their source operand considered here, for the
7601 ambiguity checking below. The suffix will be replaced afterwards
7602 to represent the destination (register). */
7603 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7606 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7607 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7610 /* If there's no instruction mnemonic suffix we try to invent one
7611 based on GPR operands. */
7614 /* We take i.suffix from the last register operand specified,
7615 Destination register type is more significant than source
7616 register type. crc32 in SSE4.2 prefers source register
7618 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7621 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7622 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7624 if (i
.types
[op
].bitfield
.class != Reg
)
7626 if (i
.types
[op
].bitfield
.byte
)
7627 i
.suffix
= BYTE_MNEM_SUFFIX
;
7628 else if (i
.types
[op
].bitfield
.word
)
7629 i
.suffix
= WORD_MNEM_SUFFIX
;
7630 else if (i
.types
[op
].bitfield
.dword
)
7631 i
.suffix
= LONG_MNEM_SUFFIX
;
7632 else if (i
.types
[op
].bitfield
.qword
)
7633 i
.suffix
= QWORD_MNEM_SUFFIX
;
7639 /* As an exception, movsx/movzx silently default to a byte source
7641 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7642 i
.suffix
= BYTE_MNEM_SUFFIX
;
7644 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7646 if (!check_byte_reg ())
7649 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7651 if (!check_long_reg ())
7654 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7656 if (!check_qword_reg ())
7659 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7661 if (!check_word_reg ())
7664 else if (intel_syntax
7665 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7666 /* Do nothing if the instruction is going to ignore the prefix. */
7671 /* Undo the movsx/movzx change done above. */
7674 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7677 i
.suffix
= stackop_size
;
7678 if (stackop_size
== LONG_MNEM_SUFFIX
)
7680 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7681 .code16gcc directive to support 16-bit mode with
7682 32-bit address. For IRET without a suffix, generate
7683 16-bit IRET (opcode 0xcf) to return from an interrupt
7685 if (i
.tm
.base_opcode
== 0xcf)
7687 i
.suffix
= WORD_MNEM_SUFFIX
;
7688 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7690 /* Warn about changed behavior for segment register push/pop. */
7691 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7692 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7697 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7698 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7699 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7700 || (i
.tm
.opcode_space
== SPACE_0F
7701 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7702 && i
.tm
.extension_opcode
<= 3)))
7707 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7709 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7710 || i
.tm
.opcode_modifier
.no_lsuf
)
7711 i
.suffix
= QWORD_MNEM_SUFFIX
;
7716 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7717 i
.suffix
= LONG_MNEM_SUFFIX
;
7720 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7721 i
.suffix
= WORD_MNEM_SUFFIX
;
7727 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7728 /* Also cover lret/retf/iret in 64-bit mode. */
7729 || (flag_code
== CODE_64BIT
7730 && !i
.tm
.opcode_modifier
.no_lsuf
7731 && !i
.tm
.opcode_modifier
.no_qsuf
))
7732 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7733 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7734 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7735 /* Accept FLDENV et al without suffix. */
7736 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7738 unsigned int suffixes
, evex
= 0;
7740 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7741 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7743 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7745 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7747 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7750 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7751 also suitable for AT&T syntax mode, it was requested that this be
7752 restricted to just Intel syntax. */
7753 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7754 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7758 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7760 if (vector_size
< VSZ512
)
7762 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7763 if (vector_size
< VSZ256
)
7765 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7766 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7767 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7768 || (!i
.tm
.opcode_modifier
.evex
7769 && is_evex_encoding (&i
.tm
))))
7770 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7772 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7773 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7774 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7775 || (!i
.tm
.opcode_modifier
.evex
7776 && is_evex_encoding (&i
.tm
))))
7777 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7779 else if (is_evex_encoding (&i
.tm
)
7780 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7782 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7783 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7784 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7785 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7786 if (!i
.tm
.opcode_modifier
.evex
7787 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7788 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7791 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7792 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7793 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7796 /* Any properly sized operand disambiguates the insn. */
7797 if (i
.types
[op
].bitfield
.xmmword
7798 || i
.types
[op
].bitfield
.ymmword
7799 || i
.types
[op
].bitfield
.zmmword
)
7801 suffixes
&= ~(7 << 6);
7806 if ((i
.flags
[op
] & Operand_Mem
)
7807 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7809 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7811 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7813 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7815 if (is_evex_encoding (&i
.tm
))
7821 /* Are multiple suffixes / operand sizes allowed? */
7822 if (suffixes
& (suffixes
- 1))
7825 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7826 || operand_check
== check_error
))
7828 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7831 if (operand_check
== check_error
)
7833 as_bad (_("no instruction mnemonic suffix given and "
7834 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7837 if (operand_check
== check_warning
)
7838 as_warn (_("%s; using default for `%s'"),
7840 ? _("ambiguous operand size")
7841 : _("no instruction mnemonic suffix given and "
7842 "no register operands"),
7845 if (i
.tm
.opcode_modifier
.floatmf
)
7846 i
.suffix
= SHORT_MNEM_SUFFIX
;
7848 /* handled below */;
7850 i
.tm
.opcode_modifier
.evex
= evex
;
7851 else if (flag_code
== CODE_16BIT
)
7852 i
.suffix
= WORD_MNEM_SUFFIX
;
7853 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7854 i
.suffix
= LONG_MNEM_SUFFIX
;
7856 i
.suffix
= QWORD_MNEM_SUFFIX
;
7862 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7863 In AT&T syntax, if there is no suffix (warned about above), the default
7864 will be byte extension. */
7865 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7866 i
.tm
.base_opcode
|= 1;
7868 /* For further processing, the suffix should represent the destination
7869 (register). This is already the case when one was used with
7870 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7871 no suffix to begin with. */
7872 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7874 if (i
.types
[1].bitfield
.word
)
7875 i
.suffix
= WORD_MNEM_SUFFIX
;
7876 else if (i
.types
[1].bitfield
.qword
)
7877 i
.suffix
= QWORD_MNEM_SUFFIX
;
7879 i
.suffix
= LONG_MNEM_SUFFIX
;
7881 i
.tm
.opcode_modifier
.w
= 0;
7885 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7886 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7887 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7889 /* Change the opcode based on the operand size given by i.suffix. */
7892 /* Size floating point instruction. */
7893 case LONG_MNEM_SUFFIX
:
7894 if (i
.tm
.opcode_modifier
.floatmf
)
7896 i
.tm
.base_opcode
^= 4;
7900 case WORD_MNEM_SUFFIX
:
7901 case QWORD_MNEM_SUFFIX
:
7902 /* It's not a byte, select word/dword operation. */
7903 if (i
.tm
.opcode_modifier
.w
)
7906 i
.tm
.base_opcode
|= 8;
7908 i
.tm
.base_opcode
|= 1;
7911 case SHORT_MNEM_SUFFIX
:
7912 /* Now select between word & dword operations via the operand
7913 size prefix, except for instructions that will ignore this
7915 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7916 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7917 && !i
.tm
.opcode_modifier
.floatmf
7918 && !is_any_vex_encoding (&i
.tm
)
7919 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7920 || (flag_code
== CODE_64BIT
7921 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7923 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7925 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7926 prefix
= ADDR_PREFIX_OPCODE
;
7928 if (!add_prefix (prefix
))
7932 /* Set mode64 for an operand. */
7933 if (i
.suffix
== QWORD_MNEM_SUFFIX
7934 && flag_code
== CODE_64BIT
7935 && !i
.tm
.opcode_modifier
.norex64
7936 && !i
.tm
.opcode_modifier
.vexw
7937 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7939 && ! (i
.operands
== 2
7940 && i
.tm
.base_opcode
== 0x90
7941 && i
.tm
.opcode_space
== SPACE_BASE
7942 && i
.types
[0].bitfield
.instance
== Accum
7943 && i
.types
[0].bitfield
.qword
7944 && i
.types
[1].bitfield
.instance
== Accum
))
7950 /* Select word/dword/qword operation with explicit data sizing prefix
7951 when there are no suitable register operands. */
7952 if (i
.tm
.opcode_modifier
.w
7953 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7955 || (i
.reg_operands
== 1
7957 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7959 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7960 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7961 || i
.tm
.mnem_off
== MN_crc32
))))
7962 i
.tm
.base_opcode
|= 1;
7966 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7968 gas_assert (!i
.suffix
);
7969 gas_assert (i
.reg_operands
);
7971 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7974 /* The address size override prefix changes the size of the
7976 if (flag_code
== CODE_64BIT
7977 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7979 as_bad (_("16-bit addressing unavailable for `%s'"),
7984 if ((flag_code
== CODE_32BIT
7985 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7986 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7987 && !add_prefix (ADDR_PREFIX_OPCODE
))
7992 /* Check invalid register operand when the address size override
7993 prefix changes the size of register operands. */
7995 enum { need_word
, need_dword
, need_qword
} need
;
7997 /* Check the register operand for the address size prefix if
7998 the memory operand has no real registers, like symbol, DISP
7999 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8000 if (i
.mem_operands
== 1
8001 && i
.reg_operands
== 1
8003 && i
.types
[1].bitfield
.class == Reg
8004 && (flag_code
== CODE_32BIT
8005 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8006 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8007 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8008 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8009 || (x86_elf_abi
== X86_64_X32_ABI
8011 && i
.base_reg
->reg_num
== RegIP
8012 && i
.base_reg
->reg_type
.bitfield
.qword
))
8016 && !add_prefix (ADDR_PREFIX_OPCODE
))
8019 if (flag_code
== CODE_32BIT
)
8020 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8021 else if (i
.prefix
[ADDR_PREFIX
])
8024 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8026 for (op
= 0; op
< i
.operands
; op
++)
8028 if (i
.types
[op
].bitfield
.class != Reg
)
8034 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8038 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8042 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8047 as_bad (_("invalid register operand size for `%s'"),
8058 check_byte_reg (void)
8062 for (op
= i
.operands
; --op
>= 0;)
8064 /* Skip non-register operands. */
8065 if (i
.types
[op
].bitfield
.class != Reg
)
8068 /* If this is an eight bit register, it's OK. If it's the 16 or
8069 32 bit version of an eight bit register, we will just use the
8070 low portion, and that's OK too. */
8071 if (i
.types
[op
].bitfield
.byte
)
8074 /* I/O port address operands are OK too. */
8075 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8076 && i
.tm
.operand_types
[op
].bitfield
.word
)
8079 /* crc32 only wants its source operand checked here. */
8080 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8083 /* Any other register is bad. */
8084 as_bad (_("`%s%s' not allowed with `%s%c'"),
8085 register_prefix
, i
.op
[op
].regs
->reg_name
,
8086 insn_name (&i
.tm
), i
.suffix
);
8093 check_long_reg (void)
8097 for (op
= i
.operands
; --op
>= 0;)
8098 /* Skip non-register operands. */
8099 if (i
.types
[op
].bitfield
.class != Reg
)
8101 /* Reject eight bit registers, except where the template requires
8102 them. (eg. movzb) */
8103 else if (i
.types
[op
].bitfield
.byte
8104 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8105 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8106 && (i
.tm
.operand_types
[op
].bitfield
.word
8107 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8109 as_bad (_("`%s%s' not allowed with `%s%c'"),
8111 i
.op
[op
].regs
->reg_name
,
8116 /* Error if the e prefix on a general reg is missing. */
8117 else if (i
.types
[op
].bitfield
.word
8118 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8119 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8120 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8122 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8123 register_prefix
, i
.op
[op
].regs
->reg_name
,
8127 /* Warn if the r prefix on a general reg is present. */
8128 else if (i
.types
[op
].bitfield
.qword
8129 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8130 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8131 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8133 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8134 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8141 check_qword_reg (void)
8145 for (op
= i
.operands
; --op
>= 0; )
8146 /* Skip non-register operands. */
8147 if (i
.types
[op
].bitfield
.class != Reg
)
8149 /* Reject eight bit registers, except where the template requires
8150 them. (eg. movzb) */
8151 else if (i
.types
[op
].bitfield
.byte
8152 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8153 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8154 && (i
.tm
.operand_types
[op
].bitfield
.word
8155 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8157 as_bad (_("`%s%s' not allowed with `%s%c'"),
8159 i
.op
[op
].regs
->reg_name
,
8164 /* Warn if the r prefix on a general reg is missing. */
8165 else if ((i
.types
[op
].bitfield
.word
8166 || i
.types
[op
].bitfield
.dword
)
8167 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8168 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8169 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8171 /* Prohibit these changes in the 64bit mode, since the
8172 lowering is more complicated. */
8173 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8174 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8181 check_word_reg (void)
8184 for (op
= i
.operands
; --op
>= 0;)
8185 /* Skip non-register operands. */
8186 if (i
.types
[op
].bitfield
.class != Reg
)
8188 /* Reject eight bit registers, except where the template requires
8189 them. (eg. movzb) */
8190 else if (i
.types
[op
].bitfield
.byte
8191 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8192 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8193 && (i
.tm
.operand_types
[op
].bitfield
.word
8194 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8196 as_bad (_("`%s%s' not allowed with `%s%c'"),
8198 i
.op
[op
].regs
->reg_name
,
8203 /* Error if the e or r prefix on a general reg is present. */
8204 else if ((i
.types
[op
].bitfield
.dword
8205 || i
.types
[op
].bitfield
.qword
)
8206 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8207 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8208 && i
.tm
.operand_types
[op
].bitfield
.word
)
8210 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8211 register_prefix
, i
.op
[op
].regs
->reg_name
,
8219 update_imm (unsigned int j
)
8221 i386_operand_type overlap
= i
.types
[j
];
8223 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8224 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8225 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8227 /* This combination is used on 8-bit immediates where e.g. $~0 is
8228 desirable to permit. We're past operand type matching, so simply
8229 put things back in the shape they were before introducing the
8230 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8231 overlap
.bitfield
.imm8s
= 0;
8234 if (overlap
.bitfield
.imm8
8235 + overlap
.bitfield
.imm8s
8236 + overlap
.bitfield
.imm16
8237 + overlap
.bitfield
.imm32
8238 + overlap
.bitfield
.imm32s
8239 + overlap
.bitfield
.imm64
> 1)
8241 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8242 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8243 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8244 static const i386_operand_type imm16_32
= { .bitfield
=
8245 { .imm16
= 1, .imm32
= 1 }
8247 static const i386_operand_type imm16_32s
= { .bitfield
=
8248 { .imm16
= 1, .imm32s
= 1 }
8250 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8251 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8256 i386_operand_type temp
;
8258 operand_type_set (&temp
, 0);
8259 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8261 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8262 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8264 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8265 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8266 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8268 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8269 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8272 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8275 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8276 || operand_type_equal (&overlap
, &imm16_32
)
8277 || operand_type_equal (&overlap
, &imm16_32s
))
8279 if ((flag_code
== CODE_16BIT
)
8280 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8285 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8286 overlap
= operand_type_and (overlap
, imm32s
);
8287 else if (i
.prefix
[DATA_PREFIX
])
8288 overlap
= operand_type_and (overlap
,
8289 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8290 if (overlap
.bitfield
.imm8
8291 + overlap
.bitfield
.imm8s
8292 + overlap
.bitfield
.imm16
8293 + overlap
.bitfield
.imm32
8294 + overlap
.bitfield
.imm32s
8295 + overlap
.bitfield
.imm64
!= 1)
8297 as_bad (_("no instruction mnemonic suffix given; "
8298 "can't determine immediate size"));
8302 i
.types
[j
] = overlap
;
8312 /* Update the first 2 immediate operands. */
8313 n
= i
.operands
> 2 ? 2 : i
.operands
;
8316 for (j
= 0; j
< n
; j
++)
8317 if (update_imm (j
) == 0)
8320 /* The 3rd operand can't be immediate operand. */
8321 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8327 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8330 if (r
->reg_flags
& RegRex
)
8332 if (i
.rex
& rex_bit
)
8333 as_bad (_("same type of prefix used twice"));
8336 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8338 gas_assert (i
.vex
.register_specifier
== r
);
8339 i
.vex
.register_specifier
+= 8;
8342 if (r
->reg_flags
& RegVRex
)
8347 process_operands (void)
8349 /* Default segment register this instruction will use for memory
8350 accesses. 0 means unknown. This is only for optimizing out
8351 unnecessary segment overrides. */
8352 const reg_entry
*default_seg
= NULL
;
8354 /* We only need to check those implicit registers for instructions
8355 with 3 operands or less. */
8356 if (i
.operands
<= 3)
8357 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8358 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8361 if (i
.tm
.opcode_modifier
.sse2avx
)
8363 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8365 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8366 i
.prefix
[REX_PREFIX
] = 0;
8369 /* ImmExt should be processed after SSE2AVX. */
8370 else if (i
.tm
.opcode_modifier
.immext
)
8373 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8374 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8375 new destination operand here, while converting the source one to register
8377 if (i
.tm
.mnem_off
== MN_tilezero
)
8379 i
.op
[1].regs
= i
.op
[0].regs
;
8380 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8381 i
.types
[1] = i
.types
[0];
8382 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8383 i
.flags
[1] = i
.flags
[0];
8389 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8391 static const i386_operand_type regxmm
= {
8392 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8394 unsigned int dupl
= i
.operands
;
8395 unsigned int dest
= dupl
- 1;
8398 /* The destination must be an xmm register. */
8399 gas_assert (i
.reg_operands
8400 && MAX_OPERANDS
> dupl
8401 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8403 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8404 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8406 /* Keep xmm0 for instructions with VEX prefix and 3
8408 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8409 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8414 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8416 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8418 /* Add the implicit xmm0 for instructions with VEX prefix
8420 for (j
= i
.operands
; j
> 0; j
--)
8422 i
.op
[j
] = i
.op
[j
- 1];
8423 i
.types
[j
] = i
.types
[j
- 1];
8424 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8425 i
.flags
[j
] = i
.flags
[j
- 1];
8428 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8429 i
.types
[0] = regxmm
;
8430 i
.tm
.operand_types
[0] = regxmm
;
8433 i
.reg_operands
+= 2;
8438 i
.op
[dupl
] = i
.op
[dest
];
8439 i
.types
[dupl
] = i
.types
[dest
];
8440 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8441 i
.flags
[dupl
] = i
.flags
[dest
];
8450 i
.op
[dupl
] = i
.op
[dest
];
8451 i
.types
[dupl
] = i
.types
[dest
];
8452 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8453 i
.flags
[dupl
] = i
.flags
[dest
];
8456 if (i
.tm
.opcode_modifier
.immext
)
8459 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8460 && i
.tm
.opcode_modifier
.modrm
)
8464 for (j
= 1; j
< i
.operands
; j
++)
8466 i
.op
[j
- 1] = i
.op
[j
];
8467 i
.types
[j
- 1] = i
.types
[j
];
8469 /* We need to adjust fields in i.tm since they are used by
8470 build_modrm_byte. */
8471 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8473 i
.flags
[j
- 1] = i
.flags
[j
];
8476 /* No adjustment to i.reg_operands: This was already done at the top
8481 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8483 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8485 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8486 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8487 regnum
= register_number (i
.op
[1].regs
);
8488 first_reg_in_group
= regnum
& ~3;
8489 last_reg_in_group
= first_reg_in_group
+ 3;
8490 if (regnum
!= first_reg_in_group
)
8491 as_warn (_("source register `%s%s' implicitly denotes"
8492 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8493 register_prefix
, i
.op
[1].regs
->reg_name
,
8494 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8495 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8498 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8500 /* The imul $imm, %reg instruction is converted into
8501 imul $imm, %reg, %reg, and the clr %reg instruction
8502 is converted into xor %reg, %reg. */
8504 unsigned int first_reg_op
;
8506 if (operand_type_check (i
.types
[0], reg
))
8510 /* Pretend we saw the extra register operand. */
8511 gas_assert (i
.reg_operands
== 1
8512 && i
.op
[first_reg_op
+ 1].regs
== 0);
8513 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8514 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8519 if (i
.tm
.opcode_modifier
.modrm
)
8521 /* The opcode is completed (modulo i.tm.extension_opcode which
8522 must be put into the modrm byte). Now, we make the modrm and
8523 index base bytes based on all the info we've collected. */
8525 default_seg
= build_modrm_byte ();
8527 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8529 /* Warn about some common errors, but press on regardless. */
8530 if (i
.operands
== 2)
8532 /* Reversed arguments on faddp or fmulp. */
8533 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8534 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8535 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8537 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8539 /* Extraneous `l' suffix on fp insn. */
8540 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8541 register_prefix
, i
.op
[0].regs
->reg_name
);
8545 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8547 if (flag_code
!= CODE_64BIT
8548 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8549 && i
.op
[0].regs
->reg_num
== 1
8550 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8551 && i
.op
[0].regs
->reg_num
< 4)
8553 as_bad (_("you can't `%s %s%s'"),
8554 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8557 if (i
.op
[0].regs
->reg_num
> 3
8558 && i
.tm
.opcode_space
== SPACE_BASE
)
8560 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8561 i
.tm
.opcode_space
= SPACE_0F
;
8563 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8565 else if (i
.tm
.opcode_space
== SPACE_BASE
8566 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8568 default_seg
= reg_ds
;
8570 else if (i
.tm
.opcode_modifier
.isstring
)
8572 /* For the string instructions that allow a segment override
8573 on one of their operands, the default segment is ds. */
8574 default_seg
= reg_ds
;
8576 else if (i
.short_form
)
8578 /* The register operand is in the 1st or 2nd non-immediate operand. */
8579 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8582 && r
->reg_type
.bitfield
.instance
== Accum
8583 && i
.op
[i
.imm_operands
+ 1].regs
)
8584 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8585 /* Register goes in low 3 bits of opcode. */
8586 i
.tm
.base_opcode
|= r
->reg_num
;
8587 set_rex_vrex (r
, REX_B
, false);
8589 if (dot_insn () && i
.reg_operands
== 2)
8591 gas_assert (is_any_vex_encoding (&i
.tm
)
8592 || i
.vec_encoding
!= vex_encoding_default
);
8593 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8596 else if (i
.reg_operands
== 1
8597 && !i
.flags
[i
.operands
- 1]
8598 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8601 gas_assert (is_any_vex_encoding (&i
.tm
)
8602 || i
.vec_encoding
!= vex_encoding_default
);
8603 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8606 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8607 && i
.tm
.mnem_off
== MN_lea
)
8609 if (!quiet_warnings
)
8610 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8611 if (optimize
&& !i
.no_optimize
)
8614 i
.prefix
[SEG_PREFIX
] = 0;
8618 /* If a segment was explicitly specified, and the specified segment
8619 is neither the default nor the one already recorded from a prefix,
8620 use an opcode prefix to select it. If we never figured out what
8621 the default segment is, then default_seg will be zero at this
8622 point, and the specified segment prefix will always be used. */
8624 && i
.seg
[0] != default_seg
8625 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8627 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8633 static const reg_entry
*
8634 build_modrm_byte (void)
8636 const reg_entry
*default_seg
= NULL
;
8637 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8638 /* Compensate for kludge in md_assemble(). */
8639 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8640 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8641 unsigned int v
, op
, reg_slot
= ~0;
8643 /* Accumulator (in particular %st), shift count (%cl), and alike need
8644 to be skipped just like immediate operands do. */
8645 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8647 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8650 for (op
= source
; op
< i
.operands
; ++op
)
8651 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8654 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8658 /* There are 2 kinds of instructions:
8659 1. 5 operands: 4 register operands or 3 register operands
8660 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8661 VexW0 or VexW1. The destination must be either XMM, YMM or
8663 2. 4 operands: 4 register operands or 3 register operands
8664 plus 1 memory operand, with VexXDS.
8665 3. Other equivalent combinations when coming from s_insn(). */
8666 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8667 && i
.tm
.opcode_modifier
.vexw
);
8668 gas_assert (dot_insn ()
8669 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8671 /* Of the first two non-immediate operands the one with the template
8672 not allowing for a memory one is encoded in the immediate operand. */
8674 reg_slot
= source
+ 1;
8676 reg_slot
= source
++;
8680 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8681 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8684 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8686 if (i
.imm_operands
== 0)
8688 /* When there is no immediate operand, generate an 8bit
8689 immediate operand to encode the first operand. */
8690 exp
= &im_expressions
[i
.imm_operands
++];
8691 i
.op
[i
.operands
].imms
= exp
;
8692 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8695 exp
->X_op
= O_constant
;
8699 gas_assert (i
.imm_operands
== 1);
8700 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8701 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8703 /* Turn on Imm8 again so that output_imm will generate it. */
8704 i
.types
[0].bitfield
.imm8
= 1;
8708 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8709 << (3 + !(is_evex_encoding (&i
.tm
)
8710 || i
.vec_encoding
== vex_encoding_evex
));
8713 for (v
= source
+ 1; v
< dest
; ++v
)
8718 if (i
.tm
.extension_opcode
!= None
)
8724 gas_assert (source
< dest
);
8725 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8728 unsigned int tmp
= source
;
8734 if (v
< MAX_OPERANDS
)
8736 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8737 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8740 if (op
< i
.operands
)
8744 unsigned int fake_zero_displacement
= 0;
8746 gas_assert (i
.flags
[op
] & Operand_Mem
);
8748 if (i
.tm
.opcode_modifier
.sib
)
8750 /* The index register of VSIB shouldn't be RegIZ. */
8751 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8752 && i
.index_reg
->reg_num
== RegIZ
)
8755 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8758 i
.sib
.base
= NO_BASE_REGISTER
;
8759 i
.sib
.scale
= i
.log2_scale_factor
;
8760 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8761 i
.types
[op
].bitfield
.disp32
= 1;
8764 /* Since the mandatory SIB always has index register, so
8765 the code logic remains unchanged. The non-mandatory SIB
8766 without index register is allowed and will be handled
8770 if (i
.index_reg
->reg_num
== RegIZ
)
8771 i
.sib
.index
= NO_INDEX_REGISTER
;
8773 i
.sib
.index
= i
.index_reg
->reg_num
;
8774 set_rex_vrex (i
.index_reg
, REX_X
, false);
8778 default_seg
= reg_ds
;
8780 if (i
.base_reg
== 0)
8783 if (!i
.disp_operands
)
8784 fake_zero_displacement
= 1;
8785 if (i
.index_reg
== 0)
8787 /* Both check for VSIB and mandatory non-vector SIB. */
8788 gas_assert (!i
.tm
.opcode_modifier
.sib
8789 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8790 /* Operand is just <disp> */
8791 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8792 if (flag_code
== CODE_64BIT
)
8794 /* 64bit mode overwrites the 32bit absolute
8795 addressing by RIP relative addressing and
8796 absolute addressing is encoded by one of the
8797 redundant SIB forms. */
8798 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8799 i
.sib
.base
= NO_BASE_REGISTER
;
8800 i
.sib
.index
= NO_INDEX_REGISTER
;
8801 i
.types
[op
].bitfield
.disp32
= 1;
8803 else if ((flag_code
== CODE_16BIT
)
8804 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8806 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8807 i
.types
[op
].bitfield
.disp16
= 1;
8811 i
.rm
.regmem
= NO_BASE_REGISTER
;
8812 i
.types
[op
].bitfield
.disp32
= 1;
8815 else if (!i
.tm
.opcode_modifier
.sib
)
8817 /* !i.base_reg && i.index_reg */
8818 if (i
.index_reg
->reg_num
== RegIZ
)
8819 i
.sib
.index
= NO_INDEX_REGISTER
;
8821 i
.sib
.index
= i
.index_reg
->reg_num
;
8822 i
.sib
.base
= NO_BASE_REGISTER
;
8823 i
.sib
.scale
= i
.log2_scale_factor
;
8824 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8825 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8826 i
.types
[op
].bitfield
.disp32
= 1;
8827 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8831 /* RIP addressing for 64bit mode. */
8832 else if (i
.base_reg
->reg_num
== RegIP
)
8834 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8835 i
.rm
.regmem
= NO_BASE_REGISTER
;
8836 i
.types
[op
].bitfield
.disp8
= 0;
8837 i
.types
[op
].bitfield
.disp16
= 0;
8838 i
.types
[op
].bitfield
.disp32
= 1;
8839 i
.types
[op
].bitfield
.disp64
= 0;
8840 i
.flags
[op
] |= Operand_PCrel
;
8841 if (! i
.disp_operands
)
8842 fake_zero_displacement
= 1;
8844 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8846 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8847 switch (i
.base_reg
->reg_num
)
8850 if (i
.index_reg
== 0)
8852 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8853 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8856 default_seg
= reg_ss
;
8857 if (i
.index_reg
== 0)
8860 if (operand_type_check (i
.types
[op
], disp
) == 0)
8862 /* fake (%bp) into 0(%bp) */
8863 if (i
.disp_encoding
== disp_encoding_16bit
)
8864 i
.types
[op
].bitfield
.disp16
= 1;
8866 i
.types
[op
].bitfield
.disp8
= 1;
8867 fake_zero_displacement
= 1;
8870 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8871 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8873 default: /* (%si) -> 4 or (%di) -> 5 */
8874 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8876 if (!fake_zero_displacement
8880 fake_zero_displacement
= 1;
8881 if (i
.disp_encoding
== disp_encoding_8bit
)
8882 i
.types
[op
].bitfield
.disp8
= 1;
8884 i
.types
[op
].bitfield
.disp16
= 1;
8886 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8888 else /* i.base_reg and 32/64 bit mode */
8890 if (operand_type_check (i
.types
[op
], disp
))
8892 i
.types
[op
].bitfield
.disp16
= 0;
8893 i
.types
[op
].bitfield
.disp64
= 0;
8894 i
.types
[op
].bitfield
.disp32
= 1;
8897 if (!i
.tm
.opcode_modifier
.sib
)
8898 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8899 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8901 i
.sib
.base
= i
.base_reg
->reg_num
;
8902 /* x86-64 ignores REX prefix bit here to avoid decoder
8904 if (!(i
.base_reg
->reg_flags
& RegRex
)
8905 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8906 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8907 default_seg
= reg_ss
;
8908 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8910 fake_zero_displacement
= 1;
8911 if (i
.disp_encoding
== disp_encoding_32bit
)
8912 i
.types
[op
].bitfield
.disp32
= 1;
8914 i
.types
[op
].bitfield
.disp8
= 1;
8916 i
.sib
.scale
= i
.log2_scale_factor
;
8917 if (i
.index_reg
== 0)
8919 /* Only check for VSIB. */
8920 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8921 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8922 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8924 /* <disp>(%esp) becomes two byte modrm with no index
8925 register. We've already stored the code for esp
8926 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8927 Any base register besides %esp will not use the
8928 extra modrm byte. */
8929 i
.sib
.index
= NO_INDEX_REGISTER
;
8931 else if (!i
.tm
.opcode_modifier
.sib
)
8933 if (i
.index_reg
->reg_num
== RegIZ
)
8934 i
.sib
.index
= NO_INDEX_REGISTER
;
8936 i
.sib
.index
= i
.index_reg
->reg_num
;
8937 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8938 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8943 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8944 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8948 if (!fake_zero_displacement
8952 fake_zero_displacement
= 1;
8953 if (i
.disp_encoding
== disp_encoding_8bit
)
8954 i
.types
[op
].bitfield
.disp8
= 1;
8956 i
.types
[op
].bitfield
.disp32
= 1;
8958 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8962 if (fake_zero_displacement
)
8964 /* Fakes a zero displacement assuming that i.types[op]
8965 holds the correct displacement size. */
8968 gas_assert (i
.op
[op
].disps
== 0);
8969 exp
= &disp_expressions
[i
.disp_operands
++];
8970 i
.op
[op
].disps
= exp
;
8971 exp
->X_op
= O_constant
;
8972 exp
->X_add_number
= 0;
8973 exp
->X_add_symbol
= (symbolS
*) 0;
8974 exp
->X_op_symbol
= (symbolS
*) 0;
8980 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8981 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8992 if (!i
.tm
.opcode_modifier
.regmem
)
8994 gas_assert (source
< MAX_OPERANDS
);
8995 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8996 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8997 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9002 gas_assert (dest
< MAX_OPERANDS
);
9003 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9004 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9009 /* Fill in i.rm.reg field with extension opcode (if any) or the
9010 appropriate register. */
9011 if (i
.tm
.extension_opcode
!= None
)
9012 i
.rm
.reg
= i
.tm
.extension_opcode
;
9013 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9015 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9016 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9020 gas_assert (source
< MAX_OPERANDS
);
9021 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9022 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9025 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9027 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9029 add_prefix (LOCK_PREFIX_OPCODE
);
9036 frag_opcode_byte (unsigned char byte
)
9038 if (now_seg
!= absolute_section
)
9039 FRAG_APPEND_1_CHAR (byte
);
9041 ++abs_section_offset
;
9045 flip_code16 (unsigned int code16
)
9047 gas_assert (i
.tm
.operands
== 1);
9049 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9050 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9051 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9056 output_branch (void)
9062 relax_substateT subtype
;
9066 if (now_seg
== absolute_section
)
9068 as_bad (_("relaxable branches not supported in absolute section"));
9072 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9073 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9076 if (i
.prefix
[DATA_PREFIX
] != 0)
9080 code16
^= flip_code16(code16
);
9082 /* Pentium4 branch hints. */
9083 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9084 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9089 if (i
.prefix
[REX_PREFIX
] != 0)
9095 /* BND prefixed jump. */
9096 if (i
.prefix
[BND_PREFIX
] != 0)
9102 if (i
.prefixes
!= 0)
9103 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9105 /* It's always a symbol; End frag & setup for relax.
9106 Make sure there is enough room in this frag for the largest
9107 instruction we may generate in md_convert_frag. This is 2
9108 bytes for the opcode and room for the prefix and largest
9110 frag_grow (prefix
+ 2 + 4);
9111 /* Prefix and 1 opcode byte go in fr_fix. */
9112 p
= frag_more (prefix
+ 1);
9113 if (i
.prefix
[DATA_PREFIX
] != 0)
9114 *p
++ = DATA_PREFIX_OPCODE
;
9115 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9116 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9117 *p
++ = i
.prefix
[SEG_PREFIX
];
9118 if (i
.prefix
[BND_PREFIX
] != 0)
9119 *p
++ = BND_PREFIX_OPCODE
;
9120 if (i
.prefix
[REX_PREFIX
] != 0)
9121 *p
++ = i
.prefix
[REX_PREFIX
];
9122 *p
= i
.tm
.base_opcode
;
9124 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9125 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9126 else if (cpu_arch_flags
.bitfield
.cpui386
)
9127 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9129 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9132 sym
= i
.op
[0].disps
->X_add_symbol
;
9133 off
= i
.op
[0].disps
->X_add_number
;
9135 if (i
.op
[0].disps
->X_op
!= O_constant
9136 && i
.op
[0].disps
->X_op
!= O_symbol
)
9138 /* Handle complex expressions. */
9139 sym
= make_expr_symbol (i
.op
[0].disps
);
9143 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
9145 /* 1 possible extra opcode + 4 byte displacement go in var part.
9146 Pass reloc in fr_var. */
9147 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9151 /* Return TRUE iff PLT32 relocation should be used for branching to
9155 need_plt32_p (symbolS
*s
)
9157 /* PLT32 relocation is ELF only. */
9162 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9163 krtld support it. */
9167 /* Since there is no need to prepare for PLT branch on x86-64, we
9168 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9169 be used as a marker for 32-bit PC-relative branches. */
9176 /* Weak or undefined symbol need PLT32 relocation. */
9177 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9180 /* Non-global symbol doesn't need PLT32 relocation. */
9181 if (! S_IS_EXTERNAL (s
))
9184 /* Other global symbols need PLT32 relocation. NB: Symbol with
9185 non-default visibilities are treated as normal global symbol
9186 so that PLT32 relocation can be used as a marker for 32-bit
9187 PC-relative branches. It is useful for linker relaxation. */
9198 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9200 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9202 /* This is a loop or jecxz type instruction. */
9204 if (i
.prefix
[ADDR_PREFIX
] != 0)
9206 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9209 /* Pentium4 branch hints. */
9210 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9211 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9213 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9222 if (flag_code
== CODE_16BIT
)
9225 if (i
.prefix
[DATA_PREFIX
] != 0)
9227 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9229 code16
^= flip_code16(code16
);
9237 /* BND prefixed jump. */
9238 if (i
.prefix
[BND_PREFIX
] != 0)
9240 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9244 if (i
.prefix
[REX_PREFIX
] != 0)
9246 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9250 if (i
.prefixes
!= 0)
9251 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9253 if (now_seg
== absolute_section
)
9255 abs_section_offset
+= i
.opcode_length
+ size
;
9259 p
= frag_more (i
.opcode_length
+ size
);
9260 switch (i
.opcode_length
)
9263 *p
++ = i
.tm
.base_opcode
>> 8;
9266 *p
++ = i
.tm
.base_opcode
;
9272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9273 if (flag_code
== CODE_64BIT
&& size
== 4
9274 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9275 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9276 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9279 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9281 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9282 i
.op
[0].disps
, 1, jump_reloc
);
9284 /* All jumps handled here are signed, but don't unconditionally use a
9285 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9286 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9291 fixP
->fx_signed
= 1;
9295 if (i
.tm
.mnem_off
== MN_xbegin
)
9296 fixP
->fx_signed
= 1;
9300 if (flag_code
== CODE_64BIT
)
9301 fixP
->fx_signed
= 1;
9307 output_interseg_jump (void)
9315 if (flag_code
== CODE_16BIT
)
9319 if (i
.prefix
[DATA_PREFIX
] != 0)
9326 gas_assert (!i
.prefix
[REX_PREFIX
]);
9332 if (i
.prefixes
!= 0)
9333 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9335 if (now_seg
== absolute_section
)
9337 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9341 /* 1 opcode; 2 segment; offset */
9342 p
= frag_more (prefix
+ 1 + 2 + size
);
9344 if (i
.prefix
[DATA_PREFIX
] != 0)
9345 *p
++ = DATA_PREFIX_OPCODE
;
9347 if (i
.prefix
[REX_PREFIX
] != 0)
9348 *p
++ = i
.prefix
[REX_PREFIX
];
9350 *p
++ = i
.tm
.base_opcode
;
9351 if (i
.op
[1].imms
->X_op
== O_constant
)
9353 offsetT n
= i
.op
[1].imms
->X_add_number
;
9356 && !fits_in_unsigned_word (n
)
9357 && !fits_in_signed_word (n
))
9359 as_bad (_("16-bit jump out of range"));
9362 md_number_to_chars (p
, n
, size
);
9365 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9366 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9369 if (i
.op
[0].imms
->X_op
== O_constant
)
9370 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9372 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9373 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9381 asection
*seg
= now_seg
;
9382 subsegT subseg
= now_subseg
;
9384 unsigned int alignment
, align_size_1
;
9385 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9386 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9387 unsigned int padding
;
9389 if (!IS_ELF
|| !x86_used_note
)
9392 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9394 /* The .note.gnu.property section layout:
9396 Field Length Contents
9399 n_descsz 4 The note descriptor size
9400 n_type 4 NT_GNU_PROPERTY_TYPE_0
9402 n_desc n_descsz The program property array
9406 /* Create the .note.gnu.property section. */
9407 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9408 bfd_set_section_flags (sec
,
9415 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9426 bfd_set_section_alignment (sec
, alignment
);
9427 elf_section_type (sec
) = SHT_NOTE
;
9429 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9431 isa_1_descsz_raw
= 4 + 4 + 4;
9432 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9433 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9435 feature_2_descsz_raw
= isa_1_descsz
;
9436 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9438 feature_2_descsz_raw
+= 4 + 4 + 4;
9439 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9440 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9443 descsz
= feature_2_descsz
;
9444 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9445 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9447 /* Write n_namsz. */
9448 md_number_to_chars (p
, (valueT
) 4, 4);
9450 /* Write n_descsz. */
9451 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9454 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9457 memcpy (p
+ 4 * 3, "GNU", 4);
9459 /* Write 4-byte type. */
9460 md_number_to_chars (p
+ 4 * 4,
9461 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9463 /* Write 4-byte data size. */
9464 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9466 /* Write 4-byte data. */
9467 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9469 /* Zero out paddings. */
9470 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9472 memset (p
+ 4 * 7, 0, padding
);
9474 /* Write 4-byte type. */
9475 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9476 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9478 /* Write 4-byte data size. */
9479 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9481 /* Write 4-byte data. */
9482 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9483 (valueT
) x86_feature_2_used
, 4);
9485 /* Zero out paddings. */
9486 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9488 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9490 /* We probably can't restore the current segment, for there likely
9493 subseg_set (seg
, subseg
);
9497 x86_support_sframe_p (void)
9499 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9500 return (x86_elf_abi
== X86_64_ABI
);
9504 x86_sframe_ra_tracking_p (void)
9506 /* In AMD64, return address is always stored on the stack at a fixed offset
9507 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9508 Do not track explicitly via an SFrame Frame Row Entry. */
9513 x86_sframe_cfa_ra_offset (void)
9515 gas_assert (x86_elf_abi
== X86_64_ABI
);
9516 return (offsetT
) -8;
9520 x86_sframe_get_abi_arch (void)
9522 unsigned char sframe_abi_arch
= 0;
9524 if (x86_support_sframe_p ())
9526 gas_assert (!target_big_endian
);
9527 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9530 return sframe_abi_arch
;
9536 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9537 const char *frag_now_ptr
)
9539 unsigned int len
= 0;
9541 if (start_frag
!= frag_now
)
9543 const fragS
*fr
= start_frag
;
9548 } while (fr
&& fr
!= frag_now
);
9551 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9554 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9555 be macro-fused with conditional jumps.
9556 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9557 or is one of the following format:
9570 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9572 /* No RIP address. */
9573 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9576 /* No opcodes outside of base encoding space. */
9577 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9580 /* add, sub without add/sub m, imm. */
9581 if (i
.tm
.base_opcode
<= 5
9582 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9583 || ((i
.tm
.base_opcode
| 3) == 0x83
9584 && (i
.tm
.extension_opcode
== 0x5
9585 || i
.tm
.extension_opcode
== 0x0)))
9587 *mf_cmp_p
= mf_cmp_alu_cmp
;
9588 return !(i
.mem_operands
&& i
.imm_operands
);
9591 /* and without and m, imm. */
9592 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9593 || ((i
.tm
.base_opcode
| 3) == 0x83
9594 && i
.tm
.extension_opcode
== 0x4))
9596 *mf_cmp_p
= mf_cmp_test_and
;
9597 return !(i
.mem_operands
&& i
.imm_operands
);
9600 /* test without test m imm. */
9601 if ((i
.tm
.base_opcode
| 1) == 0x85
9602 || (i
.tm
.base_opcode
| 1) == 0xa9
9603 || ((i
.tm
.base_opcode
| 1) == 0xf7
9604 && i
.tm
.extension_opcode
== 0))
9606 *mf_cmp_p
= mf_cmp_test_and
;
9607 return !(i
.mem_operands
&& i
.imm_operands
);
9610 /* cmp without cmp m, imm. */
9611 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9612 || ((i
.tm
.base_opcode
| 3) == 0x83
9613 && (i
.tm
.extension_opcode
== 0x7)))
9615 *mf_cmp_p
= mf_cmp_alu_cmp
;
9616 return !(i
.mem_operands
&& i
.imm_operands
);
9619 /* inc, dec without inc/dec m. */
9620 if ((is_cpu (&i
.tm
, CpuNo64
)
9621 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9622 || ((i
.tm
.base_opcode
| 1) == 0xff
9623 && i
.tm
.extension_opcode
<= 0x1))
9625 *mf_cmp_p
= mf_cmp_incdec
;
9626 return !i
.mem_operands
;
9632 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9635 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9637 /* NB: Don't work with COND_JUMP86 without i386. */
9638 if (!align_branch_power
9639 || now_seg
== absolute_section
9640 || !cpu_arch_flags
.bitfield
.cpui386
9641 || !(align_branch
& align_branch_fused_bit
))
9644 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9646 if (last_insn
.kind
== last_insn_other
9647 || last_insn
.seg
!= now_seg
)
9650 as_warn_where (last_insn
.file
, last_insn
.line
,
9651 _("`%s` skips -malign-branch-boundary on `%s`"),
9652 last_insn
.name
, insn_name (&i
.tm
));
9658 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9661 add_branch_prefix_frag_p (void)
9663 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9664 to PadLock instructions since they include prefixes in opcode. */
9665 if (!align_branch_power
9666 || !align_branch_prefix_size
9667 || now_seg
== absolute_section
9668 || is_cpu (&i
.tm
, CpuPadLock
)
9669 || !cpu_arch_flags
.bitfield
.cpui386
)
9672 /* Don't add prefix if it is a prefix or there is no operand in case
9673 that segment prefix is special. */
9674 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9677 if (last_insn
.kind
== last_insn_other
9678 || last_insn
.seg
!= now_seg
)
9682 as_warn_where (last_insn
.file
, last_insn
.line
,
9683 _("`%s` skips -malign-branch-boundary on `%s`"),
9684 last_insn
.name
, insn_name (&i
.tm
));
9689 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9692 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9693 enum mf_jcc_kind
*mf_jcc_p
)
9697 /* NB: Don't work with COND_JUMP86 without i386. */
9698 if (!align_branch_power
9699 || now_seg
== absolute_section
9700 || !cpu_arch_flags
.bitfield
.cpui386
9701 || i
.tm
.opcode_space
!= SPACE_BASE
)
9706 /* Check for jcc and direct jmp. */
9707 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9709 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9711 *branch_p
= align_branch_jmp
;
9712 add_padding
= align_branch
& align_branch_jmp_bit
;
9716 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9717 igore the lowest bit. */
9718 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9719 *branch_p
= align_branch_jcc
;
9720 if ((align_branch
& align_branch_jcc_bit
))
9724 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9727 *branch_p
= align_branch_ret
;
9728 if ((align_branch
& align_branch_ret_bit
))
9733 /* Check for indirect jmp, direct and indirect calls. */
9734 if (i
.tm
.base_opcode
== 0xe8)
9737 *branch_p
= align_branch_call
;
9738 if ((align_branch
& align_branch_call_bit
))
9741 else if (i
.tm
.base_opcode
== 0xff
9742 && (i
.tm
.extension_opcode
== 2
9743 || i
.tm
.extension_opcode
== 4))
9745 /* Indirect call and jmp. */
9746 *branch_p
= align_branch_indirect
;
9747 if ((align_branch
& align_branch_indirect_bit
))
9754 && (i
.op
[0].disps
->X_op
== O_symbol
9755 || (i
.op
[0].disps
->X_op
== O_subtract
9756 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9758 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9759 /* No padding to call to global or undefined tls_get_addr. */
9760 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9761 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9767 && last_insn
.kind
!= last_insn_other
9768 && last_insn
.seg
== now_seg
)
9771 as_warn_where (last_insn
.file
, last_insn
.line
,
9772 _("`%s` skips -malign-branch-boundary on `%s`"),
9773 last_insn
.name
, insn_name (&i
.tm
));
9783 fragS
*insn_start_frag
;
9784 offsetT insn_start_off
;
9785 fragS
*fragP
= NULL
;
9786 enum align_branch_kind branch
= align_branch_none
;
9787 /* The initializer is arbitrary just to avoid uninitialized error.
9788 it's actually either assigned in add_branch_padding_frag_p
9789 or never be used. */
9790 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9792 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9793 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9795 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9796 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9797 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9799 if (is_cpu (&i
.tm
, Cpu8087
)
9800 || is_cpu (&i
.tm
, Cpu287
)
9801 || is_cpu (&i
.tm
, Cpu387
)
9802 || is_cpu (&i
.tm
, Cpu687
)
9803 || is_cpu (&i
.tm
, CpuFISTTP
))
9804 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9806 if ((i
.xstate
& xstate_mmx
)
9807 || i
.tm
.mnem_off
== MN_emms
9808 || i
.tm
.mnem_off
== MN_femms
)
9809 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9813 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9814 i
.xstate
|= xstate_zmm
;
9815 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9816 i
.xstate
|= xstate_ymm
;
9817 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9818 i
.xstate
|= xstate_xmm
;
9821 /* vzeroall / vzeroupper */
9822 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9823 i
.xstate
|= xstate_ymm
;
9825 if ((i
.xstate
& xstate_xmm
)
9826 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9827 || (i
.tm
.base_opcode
== 0xae
9828 && (is_cpu (&i
.tm
, CpuSSE
)
9829 || is_cpu (&i
.tm
, CpuAVX
)))
9830 || is_cpu (&i
.tm
, CpuWideKL
)
9831 || is_cpu (&i
.tm
, CpuKL
))
9832 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9834 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9835 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9836 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9837 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9838 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9839 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9840 if (is_cpu (&i
.tm
, CpuFXSR
))
9841 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9842 if (is_cpu (&i
.tm
, CpuXsave
))
9843 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9844 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9845 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9846 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9847 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9849 if (x86_feature_2_used
9850 || is_cpu (&i
.tm
, CpuCMOV
)
9851 || is_cpu (&i
.tm
, CpuSYSCALL
)
9852 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9853 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9854 if (is_cpu (&i
.tm
, CpuSSE3
)
9855 || is_cpu (&i
.tm
, CpuSSSE3
)
9856 || is_cpu (&i
.tm
, CpuSSE4_1
)
9857 || is_cpu (&i
.tm
, CpuSSE4_2
)
9858 || is_cpu (&i
.tm
, CpuCX16
)
9859 || is_cpu (&i
.tm
, CpuPOPCNT
)
9860 /* LAHF-SAHF insns in 64-bit mode. */
9861 || (flag_code
== CODE_64BIT
9862 && (i
.tm
.base_opcode
| 1) == 0x9f
9863 && i
.tm
.opcode_space
== SPACE_BASE
))
9864 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9865 if (is_cpu (&i
.tm
, CpuAVX
)
9866 || is_cpu (&i
.tm
, CpuAVX2
)
9867 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9868 XOP, FMA4, LPW, TBM, and AMX. */
9869 || (i
.tm
.opcode_modifier
.vex
9870 && !is_cpu (&i
.tm
, CpuAVX512F
)
9871 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9872 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9873 && !is_cpu (&i
.tm
, CpuXOP
)
9874 && !is_cpu (&i
.tm
, CpuFMA4
)
9875 && !is_cpu (&i
.tm
, CpuLWP
)
9876 && !is_cpu (&i
.tm
, CpuTBM
)
9877 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9878 || is_cpu (&i
.tm
, CpuF16C
)
9879 || is_cpu (&i
.tm
, CpuFMA
)
9880 || is_cpu (&i
.tm
, CpuLZCNT
)
9881 || is_cpu (&i
.tm
, CpuMovbe
)
9882 || is_cpu (&i
.tm
, CpuXSAVES
)
9883 || (x86_feature_2_used
9884 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9885 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9886 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9887 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9888 if (is_cpu (&i
.tm
, CpuAVX512F
)
9889 || is_cpu (&i
.tm
, CpuAVX512BW
)
9890 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9891 || is_cpu (&i
.tm
, CpuAVX512VL
)
9892 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9893 AVX512-4FMAPS, and AVX512-4VNNIW. */
9894 || (i
.tm
.opcode_modifier
.evex
9895 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9896 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9897 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9898 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9899 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9903 /* Tie dwarf2 debug info to the address at the start of the insn.
9904 We can't do this after the insn has been output as the current
9905 frag may have been closed off. eg. by frag_var. */
9906 dwarf2_emit_insn (0);
9908 insn_start_frag
= frag_now
;
9909 insn_start_off
= frag_now_fix ();
9911 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9914 /* Branch can be 8 bytes. Leave some room for prefixes. */
9915 unsigned int max_branch_padding_size
= 14;
9917 /* Align section to boundary. */
9918 record_alignment (now_seg
, align_branch_power
);
9920 /* Make room for padding. */
9921 frag_grow (max_branch_padding_size
);
9923 /* Start of the padding. */
9928 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9929 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9932 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9933 fragP
->tc_frag_data
.branch_type
= branch
;
9934 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9937 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9938 && !pre_386_16bit_warned
)
9940 as_warn (_("use .code16 to ensure correct addressing mode"));
9941 pre_386_16bit_warned
= true;
9945 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9947 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9948 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9950 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9951 output_interseg_jump ();
9954 /* Output normal instructions here. */
9958 enum mf_cmp_kind mf_cmp
;
9961 && (i
.tm
.base_opcode
== 0xaee8
9962 || i
.tm
.base_opcode
== 0xaef0
9963 || i
.tm
.base_opcode
== 0xaef8))
9965 /* Encode lfence, mfence, and sfence as
9966 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9967 if (flag_code
== CODE_16BIT
)
9968 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9969 else if (omit_lock_prefix
)
9970 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9972 else if (now_seg
!= absolute_section
)
9974 offsetT val
= 0x240483f0ULL
;
9977 md_number_to_chars (p
, val
, 5);
9980 abs_section_offset
+= 5;
9984 /* Some processors fail on LOCK prefix. This options makes
9985 assembler ignore LOCK prefix and serves as a workaround. */
9986 if (omit_lock_prefix
)
9988 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9989 && i
.tm
.opcode_modifier
.isprefix
)
9991 i
.prefix
[LOCK_PREFIX
] = 0;
9995 /* Skip if this is a branch. */
9997 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9999 /* Make room for padding. */
10000 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10005 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10006 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10009 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10010 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10011 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10013 else if (add_branch_prefix_frag_p ())
10015 unsigned int max_prefix_size
= align_branch_prefix_size
;
10017 /* Make room for padding. */
10018 frag_grow (max_prefix_size
);
10023 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10024 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10027 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10030 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10031 don't need the explicit prefix. */
10032 if (!is_any_vex_encoding (&i
.tm
))
10034 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10043 if (!is_cpu (&i
.tm
, CpuPadLock
)
10044 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10048 switch (i
.opcode_length
)
10053 /* Check for pseudo prefixes. */
10054 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10056 as_bad_where (insn_start_frag
->fr_file
,
10057 insn_start_frag
->fr_line
,
10058 _("pseudo prefix without instruction"));
10068 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10069 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10070 R_X86_64_GOTTPOFF relocation so that linker can safely
10071 perform IE->LE optimization. A dummy REX_OPCODE prefix
10072 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10073 relocation for GDesc -> IE/LE optimization. */
10074 if (x86_elf_abi
== X86_64_X32_ABI
10076 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10077 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10078 && i
.prefix
[REX_PREFIX
] == 0)
10079 add_prefix (REX_OPCODE
);
10082 /* The prefix bytes. */
10083 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10085 frag_opcode_byte (*q
);
10089 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10095 frag_opcode_byte (*q
);
10098 /* There should be no other prefixes for instructions
10099 with VEX prefix. */
10103 /* For EVEX instructions i.vrex should become 0 after
10104 build_evex_prefix. For VEX instructions upper 16 registers
10105 aren't available, so VREX should be 0. */
10108 /* Now the VEX prefix. */
10109 if (now_seg
!= absolute_section
)
10111 p
= frag_more (i
.vex
.length
);
10112 for (j
= 0; j
< i
.vex
.length
; j
++)
10113 p
[j
] = i
.vex
.bytes
[j
];
10116 abs_section_offset
+= i
.vex
.length
;
10119 /* Now the opcode; be careful about word order here! */
10120 j
= i
.opcode_length
;
10122 switch (i
.tm
.opcode_space
)
10137 if (now_seg
== absolute_section
)
10138 abs_section_offset
+= j
;
10141 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10147 && i
.tm
.opcode_space
!= SPACE_BASE
)
10150 if (i
.tm
.opcode_space
!= SPACE_0F
)
10151 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10155 switch (i
.opcode_length
)
10158 /* Put out high byte first: can't use md_number_to_chars! */
10159 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10160 /* Fall through. */
10162 *p
= i
.tm
.base_opcode
& 0xff;
10171 /* Now the modrm byte and sib byte (if present). */
10172 if (i
.tm
.opcode_modifier
.modrm
)
10174 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10176 | (i
.rm
.mode
<< 6));
10177 /* If i.rm.regmem == ESP (4)
10178 && i.rm.mode != (Register mode)
10180 ==> need second modrm byte. */
10181 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10183 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10184 frag_opcode_byte ((i
.sib
.base
<< 0)
10185 | (i
.sib
.index
<< 3)
10186 | (i
.sib
.scale
<< 6));
10189 if (i
.disp_operands
)
10190 output_disp (insn_start_frag
, insn_start_off
);
10192 if (i
.imm_operands
)
10193 output_imm (insn_start_frag
, insn_start_off
);
10196 * frag_now_fix () returning plain abs_section_offset when we're in the
10197 * absolute section, and abs_section_offset not getting updated as data
10198 * gets added to the frag breaks the logic below.
10200 if (now_seg
!= absolute_section
)
10202 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10204 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10208 /* NB: Don't add prefix with GOTPC relocation since
10209 output_disp() above depends on the fixed encoding
10210 length. Can't add prefix with TLS relocation since
10211 it breaks TLS linker optimization. */
10212 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10213 /* Prefix count on the current instruction. */
10214 unsigned int count
= i
.vex
.length
;
10216 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10217 /* REX byte is encoded in VEX/EVEX prefix. */
10218 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10221 /* Count prefixes for extended opcode maps. */
10223 switch (i
.tm
.opcode_space
)
10238 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10241 /* Set the maximum prefix size in BRANCH_PREFIX
10243 if (fragP
->tc_frag_data
.max_bytes
> max
)
10244 fragP
->tc_frag_data
.max_bytes
= max
;
10245 if (fragP
->tc_frag_data
.max_bytes
> count
)
10246 fragP
->tc_frag_data
.max_bytes
-= count
;
10248 fragP
->tc_frag_data
.max_bytes
= 0;
10252 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10254 unsigned int max_prefix_size
;
10255 if (align_branch_prefix_size
> max
)
10256 max_prefix_size
= max
;
10258 max_prefix_size
= align_branch_prefix_size
;
10259 if (max_prefix_size
> count
)
10260 fragP
->tc_frag_data
.max_prefix_length
10261 = max_prefix_size
- count
;
10264 /* Use existing segment prefix if possible. Use CS
10265 segment prefix in 64-bit mode. In 32-bit mode, use SS
10266 segment prefix with ESP/EBP base register and use DS
10267 segment prefix without ESP/EBP base register. */
10268 if (i
.prefix
[SEG_PREFIX
])
10269 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10270 else if (flag_code
== CODE_64BIT
)
10271 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10272 else if (i
.base_reg
10273 && (i
.base_reg
->reg_num
== 4
10274 || i
.base_reg
->reg_num
== 5))
10275 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10277 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10282 /* NB: Don't work with COND_JUMP86 without i386. */
10283 if (align_branch_power
10284 && now_seg
!= absolute_section
10285 && cpu_arch_flags
.bitfield
.cpui386
)
10287 /* Terminate each frag so that we can add prefix and check for
10289 frag_wane (frag_now
);
10296 pi ("" /*line*/, &i
);
10298 #endif /* DEBUG386 */
10301 /* Return the size of the displacement operand N. */
10304 disp_size (unsigned int n
)
10308 if (i
.types
[n
].bitfield
.disp64
)
10310 else if (i
.types
[n
].bitfield
.disp8
)
10312 else if (i
.types
[n
].bitfield
.disp16
)
10317 /* Return the size of the immediate operand N. */
10320 imm_size (unsigned int n
)
10323 if (i
.types
[n
].bitfield
.imm64
)
10325 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10327 else if (i
.types
[n
].bitfield
.imm16
)
10333 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10338 for (n
= 0; n
< i
.operands
; n
++)
10340 if (operand_type_check (i
.types
[n
], disp
))
10342 int size
= disp_size (n
);
10344 if (now_seg
== absolute_section
)
10345 abs_section_offset
+= size
;
10346 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10348 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10350 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10352 p
= frag_more (size
);
10353 md_number_to_chars (p
, val
, size
);
10357 enum bfd_reloc_code_real reloc_type
;
10358 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10359 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10360 && (!want_disp32 (&i
.tm
)
10361 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10362 && !i
.types
[n
].bitfield
.baseindex
)))
10366 /* We can't have 8 bit displacement here. */
10367 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10369 /* The PC relative address is computed relative
10370 to the instruction boundary, so in case immediate
10371 fields follows, we need to adjust the value. */
10372 if (pcrel
&& i
.imm_operands
)
10377 for (n1
= 0; n1
< i
.operands
; n1
++)
10378 if (operand_type_check (i
.types
[n1
], imm
))
10380 /* Only one immediate is allowed for PC
10381 relative address, except with .insn. */
10382 gas_assert (sz
== 0 || dot_insn ());
10383 sz
+= imm_size (n1
);
10385 /* We should find at least one immediate. */
10386 gas_assert (sz
!= 0);
10387 i
.op
[n
].disps
->X_add_number
-= sz
;
10390 p
= frag_more (size
);
10391 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10393 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10394 && (((reloc_type
== BFD_RELOC_32
10395 || reloc_type
== BFD_RELOC_X86_64_32S
10396 || (reloc_type
== BFD_RELOC_64
10398 && (i
.op
[n
].disps
->X_op
== O_symbol
10399 || (i
.op
[n
].disps
->X_op
== O_add
10400 && ((symbol_get_value_expression
10401 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10403 || reloc_type
== BFD_RELOC_32_PCREL
))
10407 reloc_type
= BFD_RELOC_386_GOTPC
;
10408 i
.has_gotpc_tls_reloc
= true;
10409 i
.op
[n
].disps
->X_add_number
+=
10410 encoding_length (insn_start_frag
, insn_start_off
, p
);
10412 else if (reloc_type
== BFD_RELOC_64
)
10413 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10415 /* Don't do the adjustment for x86-64, as there
10416 the pcrel addressing is relative to the _next_
10417 insn, and that is taken care of in other code. */
10418 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10420 else if (align_branch_power
)
10422 switch (reloc_type
)
10424 case BFD_RELOC_386_TLS_GD
:
10425 case BFD_RELOC_386_TLS_LDM
:
10426 case BFD_RELOC_386_TLS_IE
:
10427 case BFD_RELOC_386_TLS_IE_32
:
10428 case BFD_RELOC_386_TLS_GOTIE
:
10429 case BFD_RELOC_386_TLS_GOTDESC
:
10430 case BFD_RELOC_386_TLS_DESC_CALL
:
10431 case BFD_RELOC_X86_64_TLSGD
:
10432 case BFD_RELOC_X86_64_TLSLD
:
10433 case BFD_RELOC_X86_64_GOTTPOFF
:
10434 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10435 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10436 i
.has_gotpc_tls_reloc
= true;
10441 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10442 size
, i
.op
[n
].disps
, pcrel
,
10445 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10446 && !i
.prefix
[ADDR_PREFIX
])
10447 fixP
->fx_signed
= 1;
10449 /* Check for "call/jmp *mem", "mov mem, %reg",
10450 "test %reg, mem" and "binop mem, %reg" where binop
10451 is one of adc, add, and, cmp, or, sbb, sub, xor
10452 instructions without data prefix. Always generate
10453 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10454 if (i
.prefix
[DATA_PREFIX
] == 0
10455 && (generate_relax_relocations
10458 && i
.rm
.regmem
== 5))
10460 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10461 && i
.tm
.opcode_space
== SPACE_BASE
10462 && ((i
.operands
== 1
10463 && i
.tm
.base_opcode
== 0xff
10464 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10465 || (i
.operands
== 2
10466 && (i
.tm
.base_opcode
== 0x8b
10467 || i
.tm
.base_opcode
== 0x85
10468 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10472 fixP
->fx_tcbit
= i
.rex
!= 0;
10474 && (i
.base_reg
->reg_num
== RegIP
))
10475 fixP
->fx_tcbit2
= 1;
10478 fixP
->fx_tcbit2
= 1;
10486 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10491 for (n
= 0; n
< i
.operands
; n
++)
10493 if (operand_type_check (i
.types
[n
], imm
))
10495 int size
= imm_size (n
);
10497 if (now_seg
== absolute_section
)
10498 abs_section_offset
+= size
;
10499 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10503 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10505 p
= frag_more (size
);
10506 md_number_to_chars (p
, val
, size
);
10510 /* Not absolute_section.
10511 Need a 32-bit fixup (don't support 8bit
10512 non-absolute imms). Try to support other
10514 enum bfd_reloc_code_real reloc_type
;
10517 if (i
.types
[n
].bitfield
.imm32s
10518 && (i
.suffix
== QWORD_MNEM_SUFFIX
10519 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10520 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10526 p
= frag_more (size
);
10527 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10529 /* This is tough to explain. We end up with this one if we
10530 * have operands that look like
10531 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10532 * obtain the absolute address of the GOT, and it is strongly
10533 * preferable from a performance point of view to avoid using
10534 * a runtime relocation for this. The actual sequence of
10535 * instructions often look something like:
10540 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10542 * The call and pop essentially return the absolute address
10543 * of the label .L66 and store it in %ebx. The linker itself
10544 * will ultimately change the first operand of the addl so
10545 * that %ebx points to the GOT, but to keep things simple, the
10546 * .o file must have this operand set so that it generates not
10547 * the absolute address of .L66, but the absolute address of
10548 * itself. This allows the linker itself simply treat a GOTPC
10549 * relocation as asking for a pcrel offset to the GOT to be
10550 * added in, and the addend of the relocation is stored in the
10551 * operand field for the instruction itself.
10553 * Our job here is to fix the operand so that it would add
10554 * the correct offset so that %ebx would point to itself. The
10555 * thing that is tricky is that .-.L66 will point to the
10556 * beginning of the instruction, so we need to further modify
10557 * the operand so that it will point to itself. There are
10558 * other cases where you have something like:
10560 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10562 * and here no correction would be required. Internally in
10563 * the assembler we treat operands of this form as not being
10564 * pcrel since the '.' is explicitly mentioned, and I wonder
10565 * whether it would simplify matters to do it this way. Who
10566 * knows. In earlier versions of the PIC patches, the
10567 * pcrel_adjust field was used to store the correction, but
10568 * since the expression is not pcrel, I felt it would be
10569 * confusing to do it this way. */
10571 if ((reloc_type
== BFD_RELOC_32
10572 || reloc_type
== BFD_RELOC_X86_64_32S
10573 || reloc_type
== BFD_RELOC_64
)
10575 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10576 && (i
.op
[n
].imms
->X_op
== O_symbol
10577 || (i
.op
[n
].imms
->X_op
== O_add
10578 && ((symbol_get_value_expression
10579 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10583 reloc_type
= BFD_RELOC_386_GOTPC
;
10584 else if (size
== 4)
10585 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10586 else if (size
== 8)
10587 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10588 i
.has_gotpc_tls_reloc
= true;
10589 i
.op
[n
].imms
->X_add_number
+=
10590 encoding_length (insn_start_frag
, insn_start_off
, p
);
10592 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10593 i
.op
[n
].imms
, 0, reloc_type
);
10599 /* x86_cons_fix_new is called via the expression parsing code when a
10600 reloc is needed. We use this hook to get the correct .got reloc. */
10601 static int cons_sign
= -1;
10604 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10605 expressionS
*exp
, bfd_reloc_code_real_type r
)
10607 r
= reloc (len
, 0, cons_sign
, r
);
10610 if (exp
->X_op
== O_secrel
)
10612 exp
->X_op
= O_symbol
;
10613 r
= BFD_RELOC_32_SECREL
;
10615 else if (exp
->X_op
== O_secidx
)
10616 r
= BFD_RELOC_16_SECIDX
;
10619 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10622 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10623 purpose of the `.dc.a' internal pseudo-op. */
10626 x86_address_bytes (void)
10628 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10630 return stdoutput
->arch_info
->bits_per_address
/ 8;
10633 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10634 || defined (LEX_AT)) && !defined (TE_PE)
10635 # define lex_got(reloc, adjust, types) NULL
10637 /* Parse operands of the form
10638 <symbol>@GOTOFF+<nnn>
10639 and similar .plt or .got references.
10641 If we find one, set up the correct relocation in RELOC and copy the
10642 input string, minus the `@GOTOFF' into a malloc'd buffer for
10643 parsing by the calling routine. Return this buffer, and if ADJUST
10644 is non-null set it to the length of the string we removed from the
10645 input line. Otherwise return NULL. */
10647 lex_got (enum bfd_reloc_code_real
*rel
,
10649 i386_operand_type
*types
)
10651 /* Some of the relocations depend on the size of what field is to
10652 be relocated. But in our callers i386_immediate and i386_displacement
10653 we don't yet know the operand size (this will be set by insn
10654 matching). Hence we record the word32 relocation here,
10655 and adjust the reloc according to the real size in reloc(). */
10656 static const struct
10660 const enum bfd_reloc_code_real rel
[2];
10661 const i386_operand_type types64
;
10662 bool need_GOT_symbol
;
10667 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10668 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10669 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10670 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10671 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10672 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10673 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10674 { .imm64 = 1, .disp64 = 1 } }
10677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10678 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10679 BFD_RELOC_SIZE32
},
10680 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10682 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10683 BFD_RELOC_X86_64_PLTOFF64
},
10684 { .bitfield
= { .imm64
= 1 } }, true },
10685 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10686 BFD_RELOC_X86_64_PLT32
},
10687 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10688 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10689 BFD_RELOC_X86_64_GOTPLT64
},
10690 OPERAND_TYPE_IMM64_DISP64
, true },
10691 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10692 BFD_RELOC_X86_64_GOTOFF64
},
10693 OPERAND_TYPE_IMM64_DISP64
, true },
10694 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10695 BFD_RELOC_X86_64_GOTPCREL
},
10696 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10697 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10698 BFD_RELOC_X86_64_TLSGD
},
10699 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10700 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10701 _dummy_first_bfd_reloc_code_real
},
10702 OPERAND_TYPE_NONE
, true },
10703 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10704 BFD_RELOC_X86_64_TLSLD
},
10705 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10706 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10707 BFD_RELOC_X86_64_GOTTPOFF
},
10708 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10709 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10710 BFD_RELOC_X86_64_TPOFF32
},
10711 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10712 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10713 _dummy_first_bfd_reloc_code_real
},
10714 OPERAND_TYPE_NONE
, true },
10715 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10716 BFD_RELOC_X86_64_DTPOFF32
},
10717 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10718 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10719 _dummy_first_bfd_reloc_code_real
},
10720 OPERAND_TYPE_NONE
, true },
10721 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10722 _dummy_first_bfd_reloc_code_real
},
10723 OPERAND_TYPE_NONE
, true },
10724 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10725 BFD_RELOC_X86_64_GOT32
},
10726 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10727 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10728 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10729 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10730 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10731 BFD_RELOC_X86_64_TLSDESC_CALL
},
10732 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10734 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10735 BFD_RELOC_32_SECREL
},
10736 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10739 #undef OPERAND_TYPE_IMM32_32S_DISP32
10740 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10741 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10742 #undef OPERAND_TYPE_IMM64_DISP64
10748 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10753 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10754 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10757 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10759 int len
= gotrel
[j
].len
;
10760 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10762 if (gotrel
[j
].rel
[object_64bit
] != 0)
10765 char *tmpbuf
, *past_reloc
;
10767 *rel
= gotrel
[j
].rel
[object_64bit
];
10771 if (flag_code
!= CODE_64BIT
)
10773 types
->bitfield
.imm32
= 1;
10774 types
->bitfield
.disp32
= 1;
10777 *types
= gotrel
[j
].types64
;
10780 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10781 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10783 /* The length of the first part of our input line. */
10784 first
= cp
- input_line_pointer
;
10786 /* The second part goes from after the reloc token until
10787 (and including) an end_of_line char or comma. */
10788 past_reloc
= cp
+ 1 + len
;
10790 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10792 second
= cp
+ 1 - past_reloc
;
10794 /* Allocate and copy string. The trailing NUL shouldn't
10795 be necessary, but be safe. */
10796 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10797 memcpy (tmpbuf
, input_line_pointer
, first
);
10798 if (second
!= 0 && *past_reloc
!= ' ')
10799 /* Replace the relocation token with ' ', so that
10800 errors like foo@GOTOFF1 will be detected. */
10801 tmpbuf
[first
++] = ' ';
10803 /* Increment length by 1 if the relocation token is
10808 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10809 tmpbuf
[first
+ second
] = '\0';
10813 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10814 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10819 /* Might be a symbol version string. Don't as_bad here. */
10824 bfd_reloc_code_real_type
10825 x86_cons (expressionS
*exp
, int size
)
10827 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10829 intel_syntax
= -intel_syntax
;
10831 expr_mode
= expr_operator_none
;
10833 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10834 && !defined (LEX_AT)) \
10836 if (size
== 4 || (object_64bit
&& size
== 8))
10838 /* Handle @GOTOFF and the like in an expression. */
10840 char *gotfree_input_line
;
10843 save
= input_line_pointer
;
10844 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10845 if (gotfree_input_line
)
10846 input_line_pointer
= gotfree_input_line
;
10850 if (gotfree_input_line
)
10852 /* expression () has merrily parsed up to the end of line,
10853 or a comma - in the wrong buffer. Transfer how far
10854 input_line_pointer has moved to the right buffer. */
10855 input_line_pointer
= (save
10856 + (input_line_pointer
- gotfree_input_line
)
10858 free (gotfree_input_line
);
10859 if (exp
->X_op
== O_constant
10860 || exp
->X_op
== O_absent
10861 || exp
->X_op
== O_illegal
10862 || exp
->X_op
== O_register
10863 || exp
->X_op
== O_big
)
10865 char c
= *input_line_pointer
;
10866 *input_line_pointer
= 0;
10867 as_bad (_("missing or invalid expression `%s'"), save
);
10868 *input_line_pointer
= c
;
10870 else if ((got_reloc
== BFD_RELOC_386_PLT32
10871 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10872 && exp
->X_op
!= O_symbol
)
10874 char c
= *input_line_pointer
;
10875 *input_line_pointer
= 0;
10876 as_bad (_("invalid PLT expression `%s'"), save
);
10877 *input_line_pointer
= c
;
10885 intel_syntax
= -intel_syntax
;
10888 i386_intel_simplify (exp
);
10890 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10891 if (size
<= 4 && expr_mode
== expr_operator_present
10892 && exp
->X_op
== O_constant
&& !object_64bit
)
10893 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10899 signed_cons (int size
)
10908 s_insn (int dummy ATTRIBUTE_UNUSED
)
10910 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10911 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10915 bool vex
= false, xop
= false, evex
= false;
10916 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10920 saved_char
= *saved_ilp
;
10923 end
= parse_insn (line
, mnemonic
, true);
10927 *saved_ilp
= saved_char
;
10928 ignore_rest_of_line ();
10932 line
+= end
- line
;
10934 current_templates
= &tt
;
10935 i
.tm
.mnem_off
= MN__insn
;
10936 i
.tm
.extension_opcode
= None
;
10938 if (startswith (line
, "VEX")
10939 && (line
[3] == '.' || is_space_char (line
[3])))
10944 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10947 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10949 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10950 && (*e
== '.' || is_space_char (*e
)))
10953 /* Arrange for build_vex_prefix() to emit 0x8f. */
10954 i
.tm
.opcode_space
= SPACE_XOP08
;
10955 i
.insn_opcode_space
= n
;
10959 else if (startswith (line
, "EVEX")
10960 && (line
[4] == '.' || is_space_char (line
[4])))
10967 ? i
.vec_encoding
== vex_encoding_evex
10969 ? i
.vec_encoding
== vex_encoding_vex
10970 || i
.vec_encoding
== vex_encoding_vex3
10971 : i
.vec_encoding
!= vex_encoding_default
)
10973 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10977 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10978 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10980 if (i
.vec_encoding
!= vex_encoding_default
)
10982 /* Only address size and segment override prefixes are permitted with
10983 VEX/XOP/EVEX encodings. */
10984 const unsigned char *p
= i
.prefix
;
10986 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10997 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11003 if (line
> end
&& *line
== '.')
11005 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11013 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11015 i
.tm
.opcode_modifier
.vex
= VEX128
;
11020 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11022 i
.tm
.opcode_modifier
.vex
= VEX256
;
11027 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11032 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11036 if (line
[3] == 'G')
11039 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11041 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11047 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11052 if (line
[2] == '2' && line
[3] == '8')
11055 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11057 i
.tm
.opcode_modifier
.vex
= VEX128
;
11063 if (line
[2] == '5' && line
[3] == '6')
11066 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11068 i
.tm
.opcode_modifier
.vex
= VEX256
;
11074 if (evex
&& line
[2] == '1' && line
[3] == '2')
11076 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11083 if (line
> end
&& *line
== '.')
11085 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11089 if (line
[2] == 'P')
11094 if (line
[2] == '6')
11096 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11101 case 'F': case 'f':
11102 if (line
[2] == '3')
11104 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11107 else if (line
[2] == '2')
11109 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11116 if (line
> end
&& !xop
&& *line
== '.')
11118 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11122 if (TOUPPER (line
[2]) != 'F')
11124 if (line
[3] == '.' || is_space_char (line
[3]))
11126 i
.insn_opcode_space
= SPACE_0F
;
11129 else if (line
[3] == '3'
11130 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11131 && (line
[5] == '.' || is_space_char (line
[5])))
11133 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11139 if (ISDIGIT (line
[2]) && line
[2] != '0')
11142 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11144 if (n
<= (evex
? 15 : 31)
11145 && (*e
== '.' || is_space_char (*e
)))
11147 i
.insn_opcode_space
= n
;
11155 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11157 /* VEX.W, XOP.W, EVEX.W */
11161 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11165 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11169 if (line
[3] == 'G')
11171 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11177 if (i
.tm
.opcode_modifier
.vexw
)
11181 if (line
> end
&& *line
&& !is_space_char (*line
))
11183 /* Improve diagnostic a little. */
11184 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11189 /* Before processing the opcode expression, find trailing "+r" or
11190 "/<digit>" specifiers. */
11191 for (ptr
= line
; ; ++ptr
)
11196 ptr
= strpbrk (ptr
, "+/,");
11197 if (ptr
== NULL
|| *ptr
== ',')
11200 if (*ptr
== '+' && ptr
[1] == 'r'
11201 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11205 i
.short_form
= true;
11209 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11210 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11212 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11216 i
.tm
.extension_opcode
= n
;
11217 i
.tm
.opcode_modifier
.modrm
= 1;
11222 input_line_pointer
= line
;
11223 val
= get_absolute_expression ();
11224 line
= input_line_pointer
;
11226 if (i
.short_form
&& (val
& 7))
11227 as_warn ("`+r' assumes low three opcode bits to be clear");
11229 for (j
= 1; j
< sizeof(val
); ++j
)
11230 if (!(val
>> (j
* 8)))
11233 /* Trim off a prefix if present. */
11234 if (j
> 1 && !vex
&& !xop
&& !evex
)
11236 uint8_t byte
= val
>> ((j
- 1) * 8);
11240 case DATA_PREFIX_OPCODE
:
11241 case REPE_PREFIX_OPCODE
:
11242 case REPNE_PREFIX_OPCODE
:
11243 if (!add_prefix (byte
))
11245 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11250 /* Trim off encoding space. */
11251 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11253 uint8_t byte
= val
>> ((--j
- 1) * 8);
11255 i
.insn_opcode_space
= SPACE_0F
;
11256 switch (byte
& -(j
> 1))
11259 i
.insn_opcode_space
= SPACE_0F38
;
11263 i
.insn_opcode_space
= SPACE_0F3A
;
11267 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11268 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11270 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11271 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11272 Also avoid hitting abort() there or in build_evex_prefix(). */
11273 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11278 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11281 i
.opcode_length
= j
;
11283 /* Handle operands, if any. */
11286 i386_operand_type combined
;
11287 expressionS
*disp_exp
= NULL
;
11292 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11300 as_bad (_("expecting operand after ','; got nothing"));
11304 if (i
.mem_operands
> 1)
11306 as_bad (_("too many memory references for `%s'"),
11307 &i386_mnemonics
[MN__insn
]);
11311 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11312 if (i
.vec_encoding
== vex_encoding_evex512
)
11313 i
.vec_encoding
= vex_encoding_evex
;
11315 /* Are we to emit ModR/M encoding? */
11318 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11319 || i
.tm
.extension_opcode
!= None
))
11320 i
.tm
.opcode_modifier
.modrm
= 1;
11322 if (!i
.tm
.opcode_modifier
.modrm
11324 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11325 || i
.mem_operands
))
11327 as_bad (_("too many register/memory operands"));
11331 /* Enforce certain constraints on operands. */
11332 switch (i
.reg_operands
+ i
.mem_operands
11333 + (i
.tm
.extension_opcode
!= None
))
11338 as_bad (_("too few register/memory operands"));
11341 /* Fall through. */
11343 if (i
.tm
.opcode_modifier
.modrm
)
11345 as_bad (_("too few register/memory operands"));
11355 && (i
.op
[0].imms
->X_op
!= O_constant
11356 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11358 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11361 /* Fall through. */
11363 if (i
.vec_encoding
!= vex_encoding_default
)
11365 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11368 /* Fall through. */
11370 as_bad (_("too many register/memory operands"));
11374 /* Bring operands into canonical order (imm, mem, reg). */
11379 for (j
= 1; j
< i
.operands
; ++j
)
11381 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11382 && operand_type_check (i
.types
[j
], imm
))
11383 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11384 && i
.types
[j
].bitfield
.class == ClassNone
))
11386 swap_2_operands (j
- 1, j
);
11393 /* For Intel syntax swap the order of register operands. */
11395 switch (i
.reg_operands
)
11402 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11403 /* Fall through. */
11406 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11413 /* Enforce constraints when using VSIB. */
11415 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11416 || i
.index_reg
->reg_type
.bitfield
.ymmword
11417 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11419 if (i
.vec_encoding
== vex_encoding_default
)
11421 as_bad (_("VSIB unavailable with legacy encoding"));
11425 if (i
.vec_encoding
== vex_encoding_evex
11426 && i
.reg_operands
> 1)
11428 /* We could allow two register operands, encoding the 2nd one in
11429 an 8-bit immediate like for 4-register-operand insns, but that
11430 would require ugly fiddling with process_operands() and/or
11431 build_modrm_byte(). */
11432 as_bad (_("too many register operands with VSIB"));
11436 i
.tm
.opcode_modifier
.sib
= 1;
11439 /* Establish operand size encoding. */
11440 operand_type_set (&combined
, 0);
11442 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11444 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11446 if (operand_type_check (i
.types
[j
], disp
))
11448 i
.types
[j
].bitfield
.baseindex
= 1;
11449 disp_exp
= i
.op
[j
].disps
;
11452 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11454 unsigned int n
= i
.memshift
;
11456 if (i
.types
[j
].bitfield
.byte
)
11458 else if (i
.types
[j
].bitfield
.word
)
11460 else if (i
.types
[j
].bitfield
.dword
)
11462 else if (i
.types
[j
].bitfield
.qword
)
11464 else if (i
.types
[j
].bitfield
.xmmword
)
11466 else if (i
.types
[j
].bitfield
.ymmword
)
11468 else if (i
.types
[j
].bitfield
.zmmword
)
11471 if (i
.memshift
< 32 && n
!= i
.memshift
)
11472 as_warn ("conflicting memory operand size specifiers");
11476 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11477 && j
== i
.broadcast
.operand
)
11480 combined
= operand_type_or (combined
, i
.types
[j
]);
11481 combined
.bitfield
.class = ClassNone
;
11484 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11485 << (i
.memshift
< 32 ? i
.memshift
: 0))
11487 case 64: combined
.bitfield
.zmmword
= 1; break;
11488 case 32: combined
.bitfield
.ymmword
= 1; break;
11489 case 16: combined
.bitfield
.xmmword
= 1; break;
11490 case 8: combined
.bitfield
.qword
= 1; break;
11491 case 4: combined
.bitfield
.dword
= 1; break;
11494 if (i
.vec_encoding
== vex_encoding_default
)
11496 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11498 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11499 : combined
.bitfield
.word
)
11500 && !add_prefix (DATA_PREFIX_OPCODE
))
11503 else if (!i
.tm
.opcode_modifier
.vexw
)
11505 if (flag_code
== CODE_64BIT
)
11507 if (combined
.bitfield
.qword
)
11508 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11509 else if (combined
.bitfield
.dword
)
11510 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11513 if (!i
.tm
.opcode_modifier
.vexw
)
11514 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11519 if (!i
.tm
.opcode_modifier
.vex
)
11521 if (combined
.bitfield
.ymmword
)
11522 i
.tm
.opcode_modifier
.vex
= VEX256
;
11523 else if (combined
.bitfield
.xmmword
)
11524 i
.tm
.opcode_modifier
.vex
= VEX128
;
11529 if (!i
.tm
.opcode_modifier
.evex
)
11531 /* Do _not_ consider AVX512VL here. */
11532 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11533 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11534 else if (combined
.bitfield
.ymmword
)
11535 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11536 else if (combined
.bitfield
.xmmword
)
11537 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11540 if (i
.memshift
>= 32)
11542 unsigned int n
= 0;
11544 switch (i
.tm
.opcode_modifier
.evex
)
11546 case EVEX512
: n
= 64; break;
11547 case EVEX256
: n
= 32; break;
11548 case EVEX128
: n
= 16; break;
11551 if (i
.broadcast
.type
)
11552 n
/= i
.broadcast
.type
;
11555 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11557 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11558 && disp_exp
->X_add_number
!= 0
11559 && i
.disp_encoding
!= disp_encoding_32bit
)
11561 if (!quiet_warnings
)
11562 as_warn ("cannot determine memory operand size");
11563 i
.disp_encoding
= disp_encoding_32bit
;
11568 if (i
.memshift
>= 32)
11571 i
.vec_encoding
= vex_encoding_error
;
11573 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11576 /* Establish size for immediate operands. */
11577 for (j
= 0; j
< i
.imm_operands
; ++j
)
11579 expressionS
*expP
= i
.op
[j
].imms
;
11581 gas_assert (operand_type_check (i
.types
[j
], imm
));
11582 operand_type_set (&i
.types
[j
], 0);
11584 if (i
.imm_bits
[j
] > 32)
11585 i
.types
[j
].bitfield
.imm64
= 1;
11586 else if (i
.imm_bits
[j
] > 16)
11588 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11589 i
.types
[j
].bitfield
.imm32s
= 1;
11591 i
.types
[j
].bitfield
.imm32
= 1;
11593 else if (i
.imm_bits
[j
] > 8)
11594 i
.types
[j
].bitfield
.imm16
= 1;
11595 else if (i
.imm_bits
[j
] > 0)
11597 if (i
.flags
[j
] & Operand_Signed
)
11598 i
.types
[j
].bitfield
.imm8s
= 1;
11600 i
.types
[j
].bitfield
.imm8
= 1;
11602 else if (expP
->X_op
== O_constant
)
11604 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11605 i
.types
[j
].bitfield
.imm1
= 0;
11606 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11607 zapping since smallest_imm_type() sets it unconditionally. */
11608 if (flag_code
!= CODE_64BIT
)
11610 i
.types
[j
].bitfield
.imm64
= 0;
11611 i
.types
[j
].bitfield
.imm32s
= 0;
11612 i
.types
[j
].bitfield
.imm32
= 1;
11614 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11615 i
.types
[j
].bitfield
.imm64
= 0;
11618 /* Non-constant expressions are sized heuristically. */
11621 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11622 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11623 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11627 for (j
= 0; j
< i
.operands
; ++j
)
11628 i
.tm
.operand_types
[j
] = i
.types
[j
];
11630 process_operands ();
11633 /* Don't set opcode until after processing operands, to avoid any
11634 potential special casing there. */
11635 i
.tm
.base_opcode
|= val
;
11637 if (i
.vec_encoding
== vex_encoding_error
11638 || (i
.vec_encoding
!= vex_encoding_evex
11639 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11640 || i
.rounding
.type
!= rc_none
11642 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11643 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11644 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11646 as_bad (_("conflicting .insn operands"));
11652 if (!i
.tm
.opcode_modifier
.vex
)
11653 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11655 build_vex_prefix (NULL
);
11656 i
.rex
&= REX_OPCODE
;
11660 if (!i
.tm
.opcode_modifier
.evex
)
11661 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11663 build_evex_prefix ();
11664 i
.rex
&= REX_OPCODE
;
11666 else if (i
.rex
!= 0)
11667 add_prefix (REX_OPCODE
| i
.rex
);
11672 *saved_ilp
= saved_char
;
11673 input_line_pointer
= line
;
11675 demand_empty_rest_of_line ();
11677 /* Make sure dot_insn() won't yield "true" anymore. */
11683 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11690 if (exp
.X_op
== O_symbol
)
11691 exp
.X_op
= O_secrel
;
11693 emit_expr (&exp
, 4);
11695 while (*input_line_pointer
++ == ',');
11697 input_line_pointer
--;
11698 demand_empty_rest_of_line ();
11702 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11709 if (exp
.X_op
== O_symbol
)
11710 exp
.X_op
= O_secidx
;
11712 emit_expr (&exp
, 2);
11714 while (*input_line_pointer
++ == ',');
11716 input_line_pointer
--;
11717 demand_empty_rest_of_line ();
11721 /* Handle Rounding Control / SAE specifiers. */
11724 RC_SAE_specifier (const char *pstr
)
11728 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11730 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11732 if (i
.rounding
.type
!= rc_none
)
11734 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11738 if (i
.vec_encoding
== vex_encoding_default
)
11739 i
.vec_encoding
= vex_encoding_evex512
;
11740 else if (i
.vec_encoding
!= vex_encoding_evex
11741 && i
.vec_encoding
!= vex_encoding_evex512
)
11744 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11746 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11753 /* Handle Vector operations. */
11756 check_VecOperations (char *op_string
)
11758 const reg_entry
*mask
;
11765 if (*op_string
== '{')
11769 /* Check broadcasts. */
11770 if (startswith (op_string
, "1to"))
11772 unsigned int bcst_type
;
11774 if (i
.broadcast
.type
)
11775 goto duplicated_vec_op
;
11778 if (*op_string
== '8')
11780 else if (*op_string
== '4')
11782 else if (*op_string
== '2')
11784 else if (*op_string
== '1'
11785 && *(op_string
+1) == '6')
11790 else if (*op_string
== '3'
11791 && *(op_string
+1) == '2')
11798 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11803 if (i
.vec_encoding
== vex_encoding_default
)
11804 i
.vec_encoding
= vex_encoding_evex
;
11805 else if (i
.vec_encoding
!= vex_encoding_evex
11806 && i
.vec_encoding
!= vex_encoding_evex512
)
11807 goto unknown_vec_op
;
11809 i
.broadcast
.type
= bcst_type
;
11810 i
.broadcast
.operand
= this_operand
;
11812 /* For .insn a data size specifier may be appended. */
11813 if (dot_insn () && *op_string
== ':')
11814 goto dot_insn_modifier
;
11816 /* Check .insn special cases. */
11817 else if (dot_insn () && *op_string
== ':')
11820 switch (op_string
[1])
11825 if (i
.memshift
< 32)
11826 goto duplicated_vec_op
;
11828 n
= strtoul (op_string
+ 2, &end_op
, 0);
11830 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11832 if (i
.memshift
< 32 && n
== 1)
11833 op_string
= end_op
;
11836 case 's': case 'u':
11837 /* This isn't really a "vector" operation, but a sign/size
11838 specifier for immediate operands of .insn. Note that AT&T
11839 syntax handles the same in i386_immediate(). */
11843 if (i
.imm_bits
[this_operand
])
11844 goto duplicated_vec_op
;
11846 n
= strtoul (op_string
+ 2, &end_op
, 0);
11847 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11849 i
.imm_bits
[this_operand
] = n
;
11850 if (op_string
[1] == 's')
11851 i
.flags
[this_operand
] |= Operand_Signed
;
11852 op_string
= end_op
;
11857 /* Check masking operation. */
11858 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11860 if (mask
== &bad_reg
)
11863 /* k0 can't be used for write mask. */
11864 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11866 as_bad (_("`%s%s' can't be used for write mask"),
11867 register_prefix
, mask
->reg_name
);
11874 i
.mask
.operand
= this_operand
;
11876 else if (i
.mask
.reg
->reg_num
)
11877 goto duplicated_vec_op
;
11882 /* Only "{z}" is allowed here. No need to check
11883 zeroing mask explicitly. */
11884 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11886 as_bad (_("invalid write mask `%s'"), saved
);
11891 op_string
= end_op
;
11893 /* Check zeroing-flag for masking operation. */
11894 else if (*op_string
== 'z')
11898 i
.mask
.reg
= reg_k0
;
11899 i
.mask
.zeroing
= 1;
11900 i
.mask
.operand
= this_operand
;
11904 if (i
.mask
.zeroing
)
11907 as_bad (_("duplicated `%s'"), saved
);
11911 i
.mask
.zeroing
= 1;
11913 /* Only "{%k}" is allowed here. No need to check mask
11914 register explicitly. */
11915 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11917 as_bad (_("invalid zeroing-masking `%s'"),
11925 else if (intel_syntax
11926 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11927 i
.rounding
.modifier
= true;
11929 goto unknown_vec_op
;
11931 if (*op_string
!= '}')
11933 as_bad (_("missing `}' in `%s'"), saved
);
11938 /* Strip whitespace since the addition of pseudo prefixes
11939 changed how the scrubber treats '{'. */
11940 if (is_space_char (*op_string
))
11946 /* We don't know this one. */
11947 as_bad (_("unknown vector operation: `%s'"), saved
);
11951 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11953 as_bad (_("zeroing-masking only allowed with write mask"));
11961 i386_immediate (char *imm_start
)
11963 char *save_input_line_pointer
;
11964 char *gotfree_input_line
;
11967 i386_operand_type types
;
11969 operand_type_set (&types
, ~0);
11971 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11973 as_bad (_("at most %d immediate operands are allowed"),
11974 MAX_IMMEDIATE_OPERANDS
);
11978 exp
= &im_expressions
[i
.imm_operands
++];
11979 i
.op
[this_operand
].imms
= exp
;
11981 if (is_space_char (*imm_start
))
11984 save_input_line_pointer
= input_line_pointer
;
11985 input_line_pointer
= imm_start
;
11987 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11988 if (gotfree_input_line
)
11989 input_line_pointer
= gotfree_input_line
;
11991 expr_mode
= expr_operator_none
;
11992 exp_seg
= expression (exp
);
11994 /* For .insn immediates there may be a size specifier. */
11995 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11996 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11999 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12001 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12003 i
.imm_bits
[this_operand
] = n
;
12004 if (input_line_pointer
[2] == 's')
12005 i
.flags
[this_operand
] |= Operand_Signed
;
12006 input_line_pointer
= e
+ 1;
12010 SKIP_WHITESPACE ();
12011 if (*input_line_pointer
)
12012 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12014 input_line_pointer
= save_input_line_pointer
;
12015 if (gotfree_input_line
)
12017 free (gotfree_input_line
);
12019 if (exp
->X_op
== O_constant
)
12020 exp
->X_op
= O_illegal
;
12023 if (exp_seg
== reg_section
)
12025 as_bad (_("illegal immediate register operand %s"), imm_start
);
12029 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12033 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12034 i386_operand_type types
, const char *imm_start
)
12036 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12039 as_bad (_("missing or invalid immediate expression `%s'"),
12043 else if (exp
->X_op
== O_constant
)
12045 /* Size it properly later. */
12046 i
.types
[this_operand
].bitfield
.imm64
= 1;
12048 /* If not 64bit, sign/zero extend val, to account for wraparound
12050 if (expr_mode
== expr_operator_present
12051 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12052 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12054 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12055 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12056 && exp_seg
!= absolute_section
12057 && exp_seg
!= text_section
12058 && exp_seg
!= data_section
12059 && exp_seg
!= bss_section
12060 && exp_seg
!= undefined_section
12061 && !bfd_is_com_section (exp_seg
))
12063 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12069 /* This is an address. The size of the address will be
12070 determined later, depending on destination register,
12071 suffix, or the default for the section. */
12072 i
.types
[this_operand
].bitfield
.imm8
= 1;
12073 i
.types
[this_operand
].bitfield
.imm16
= 1;
12074 i
.types
[this_operand
].bitfield
.imm32
= 1;
12075 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12076 i
.types
[this_operand
].bitfield
.imm64
= 1;
12077 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12085 i386_scale (char *scale
)
12088 char *save
= input_line_pointer
;
12090 input_line_pointer
= scale
;
12091 val
= get_absolute_expression ();
12096 i
.log2_scale_factor
= 0;
12099 i
.log2_scale_factor
= 1;
12102 i
.log2_scale_factor
= 2;
12105 i
.log2_scale_factor
= 3;
12109 char sep
= *input_line_pointer
;
12111 *input_line_pointer
= '\0';
12112 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12114 *input_line_pointer
= sep
;
12115 input_line_pointer
= save
;
12119 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12121 as_warn (_("scale factor of %d without an index register"),
12122 1 << i
.log2_scale_factor
);
12123 i
.log2_scale_factor
= 0;
12125 scale
= input_line_pointer
;
12126 input_line_pointer
= save
;
12131 i386_displacement (char *disp_start
, char *disp_end
)
12135 char *save_input_line_pointer
;
12136 char *gotfree_input_line
;
12138 i386_operand_type bigdisp
, types
= anydisp
;
12141 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12143 as_bad (_("at most %d displacement operands are allowed"),
12144 MAX_MEMORY_OPERANDS
);
12148 operand_type_set (&bigdisp
, 0);
12150 || i
.types
[this_operand
].bitfield
.baseindex
12151 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12152 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12154 i386_addressing_mode ();
12155 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12156 if (flag_code
== CODE_64BIT
)
12158 bigdisp
.bitfield
.disp32
= 1;
12160 bigdisp
.bitfield
.disp64
= 1;
12162 else if ((flag_code
== CODE_16BIT
) ^ override
)
12163 bigdisp
.bitfield
.disp16
= 1;
12165 bigdisp
.bitfield
.disp32
= 1;
12169 /* For PC-relative branches, the width of the displacement may be
12170 dependent upon data size, but is never dependent upon address size.
12171 Also make sure to not unintentionally match against a non-PC-relative
12172 branch template. */
12173 static templates aux_templates
;
12174 const insn_template
*t
= current_templates
->start
;
12175 bool has_intel64
= false;
12177 aux_templates
.start
= t
;
12178 while (++t
< current_templates
->end
)
12180 if (t
->opcode_modifier
.jump
12181 != current_templates
->start
->opcode_modifier
.jump
)
12183 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12184 has_intel64
= true;
12186 if (t
< current_templates
->end
)
12188 aux_templates
.end
= t
;
12189 current_templates
= &aux_templates
;
12192 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12193 if (flag_code
== CODE_64BIT
)
12195 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12196 && (!intel64
|| !has_intel64
))
12197 bigdisp
.bitfield
.disp16
= 1;
12199 bigdisp
.bitfield
.disp32
= 1;
12204 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12206 : LONG_MNEM_SUFFIX
));
12207 bigdisp
.bitfield
.disp32
= 1;
12208 if ((flag_code
== CODE_16BIT
) ^ override
)
12210 bigdisp
.bitfield
.disp32
= 0;
12211 bigdisp
.bitfield
.disp16
= 1;
12215 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12218 exp
= &disp_expressions
[i
.disp_operands
];
12219 i
.op
[this_operand
].disps
= exp
;
12221 save_input_line_pointer
= input_line_pointer
;
12222 input_line_pointer
= disp_start
;
12223 END_STRING_AND_SAVE (disp_end
);
12225 #ifndef GCC_ASM_O_HACK
12226 #define GCC_ASM_O_HACK 0
12229 END_STRING_AND_SAVE (disp_end
+ 1);
12230 if (i
.types
[this_operand
].bitfield
.baseIndex
12231 && displacement_string_end
[-1] == '+')
12233 /* This hack is to avoid a warning when using the "o"
12234 constraint within gcc asm statements.
12237 #define _set_tssldt_desc(n,addr,limit,type) \
12238 __asm__ __volatile__ ( \
12239 "movw %w2,%0\n\t" \
12240 "movw %w1,2+%0\n\t" \
12241 "rorl $16,%1\n\t" \
12242 "movb %b1,4+%0\n\t" \
12243 "movb %4,5+%0\n\t" \
12244 "movb $0,6+%0\n\t" \
12245 "movb %h1,7+%0\n\t" \
12247 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12249 This works great except that the output assembler ends
12250 up looking a bit weird if it turns out that there is
12251 no offset. You end up producing code that looks like:
12264 So here we provide the missing zero. */
12266 *displacement_string_end
= '0';
12269 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12270 if (gotfree_input_line
)
12271 input_line_pointer
= gotfree_input_line
;
12273 expr_mode
= expr_operator_none
;
12274 exp_seg
= expression (exp
);
12276 SKIP_WHITESPACE ();
12277 if (*input_line_pointer
)
12278 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12280 RESTORE_END_STRING (disp_end
+ 1);
12282 input_line_pointer
= save_input_line_pointer
;
12283 if (gotfree_input_line
)
12285 free (gotfree_input_line
);
12287 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12288 exp
->X_op
= O_illegal
;
12291 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12293 RESTORE_END_STRING (disp_end
);
12299 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12300 i386_operand_type types
, const char *disp_start
)
12304 /* We do this to make sure that the section symbol is in
12305 the symbol table. We will ultimately change the relocation
12306 to be relative to the beginning of the section. */
12307 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12308 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12309 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12311 if (exp
->X_op
!= O_symbol
)
12314 if (S_IS_LOCAL (exp
->X_add_symbol
)
12315 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12316 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12317 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12318 exp
->X_op
= O_subtract
;
12319 exp
->X_op_symbol
= GOT_symbol
;
12320 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12321 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12322 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12323 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12325 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12328 else if (exp
->X_op
== O_absent
12329 || exp
->X_op
== O_illegal
12330 || exp
->X_op
== O_big
)
12333 as_bad (_("missing or invalid displacement expression `%s'"),
12338 else if (exp
->X_op
== O_constant
)
12340 /* Sizing gets taken care of by optimize_disp().
12342 If not 64bit, sign/zero extend val, to account for wraparound
12344 if (expr_mode
== expr_operator_present
12345 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12346 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12349 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12350 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12351 && exp_seg
!= absolute_section
12352 && exp_seg
!= text_section
12353 && exp_seg
!= data_section
12354 && exp_seg
!= bss_section
12355 && exp_seg
!= undefined_section
12356 && !bfd_is_com_section (exp_seg
))
12358 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12363 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12364 i
.types
[this_operand
].bitfield
.disp8
= 1;
12366 /* Check if this is a displacement only operand. */
12367 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12368 i
.types
[this_operand
] =
12369 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12370 operand_type_and (i
.types
[this_operand
], types
));
12375 /* Return the active addressing mode, taking address override and
12376 registers forming the address into consideration. Update the
12377 address override prefix if necessary. */
12379 static enum flag_code
12380 i386_addressing_mode (void)
12382 enum flag_code addr_mode
;
12384 if (i
.prefix
[ADDR_PREFIX
])
12385 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12386 else if (flag_code
== CODE_16BIT
12387 && is_cpu (current_templates
->start
, CpuMPX
)
12388 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12389 from md_assemble() by "is not a valid base/index expression"
12390 when there is a base and/or index. */
12391 && !i
.types
[this_operand
].bitfield
.baseindex
)
12393 /* MPX insn memory operands with neither base nor index must be forced
12394 to use 32-bit addressing in 16-bit mode. */
12395 addr_mode
= CODE_32BIT
;
12396 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12398 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12399 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12403 addr_mode
= flag_code
;
12405 #if INFER_ADDR_PREFIX
12406 if (i
.mem_operands
== 0)
12408 /* Infer address prefix from the first memory operand. */
12409 const reg_entry
*addr_reg
= i
.base_reg
;
12411 if (addr_reg
== NULL
)
12412 addr_reg
= i
.index_reg
;
12416 if (addr_reg
->reg_type
.bitfield
.dword
)
12417 addr_mode
= CODE_32BIT
;
12418 else if (flag_code
!= CODE_64BIT
12419 && addr_reg
->reg_type
.bitfield
.word
)
12420 addr_mode
= CODE_16BIT
;
12422 if (addr_mode
!= flag_code
)
12424 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12426 /* Change the size of any displacement too. At most one
12427 of Disp16 or Disp32 is set.
12428 FIXME. There doesn't seem to be any real need for
12429 separate Disp16 and Disp32 flags. The same goes for
12430 Imm16 and Imm32. Removing them would probably clean
12431 up the code quite a lot. */
12432 if (flag_code
!= CODE_64BIT
12433 && (i
.types
[this_operand
].bitfield
.disp16
12434 || i
.types
[this_operand
].bitfield
.disp32
))
12436 static const i386_operand_type disp16_32
= {
12437 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12440 i
.types
[this_operand
]
12441 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12452 /* Make sure the memory operand we've been dealt is valid.
12453 Return 1 on success, 0 on a failure. */
12456 i386_index_check (const char *operand_string
)
12458 const char *kind
= "base/index";
12459 enum flag_code addr_mode
= i386_addressing_mode ();
12460 const insn_template
*t
= current_templates
->end
- 1;
12462 if (t
->opcode_modifier
.isstring
)
12464 /* Memory operands of string insns are special in that they only allow
12465 a single register (rDI, rSI, or rBX) as their memory address. */
12466 const reg_entry
*expected_reg
;
12467 static const char di_si
[][2][4] =
12473 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12475 kind
= "string address";
12477 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12479 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12482 if (!t
->operand_types
[0].bitfield
.baseindex
12483 || ((!i
.mem_operands
!= !intel_syntax
)
12484 && t
->operand_types
[1].bitfield
.baseindex
))
12487 = (const reg_entry
*) str_hash_find (reg_hash
,
12488 di_si
[addr_mode
][op
== es_op
]);
12492 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12494 if (i
.base_reg
!= expected_reg
12496 || operand_type_check (i
.types
[this_operand
], disp
))
12498 /* The second memory operand must have the same size as
12502 && !((addr_mode
== CODE_64BIT
12503 && i
.base_reg
->reg_type
.bitfield
.qword
)
12504 || (addr_mode
== CODE_32BIT
12505 ? i
.base_reg
->reg_type
.bitfield
.dword
12506 : i
.base_reg
->reg_type
.bitfield
.word
)))
12509 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12511 intel_syntax
? '[' : '(',
12513 expected_reg
->reg_name
,
12514 intel_syntax
? ']' : ')');
12521 as_bad (_("`%s' is not a valid %s expression"),
12522 operand_string
, kind
);
12527 t
= current_templates
->start
;
12529 if (addr_mode
!= CODE_16BIT
)
12531 /* 32-bit/64-bit checks. */
12532 if (i
.disp_encoding
== disp_encoding_16bit
)
12535 as_bad (_("invalid `%s' prefix"),
12536 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12541 && ((addr_mode
== CODE_64BIT
12542 ? !i
.base_reg
->reg_type
.bitfield
.qword
12543 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12544 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12545 || i
.base_reg
->reg_num
== RegIZ
))
12547 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12548 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12549 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12550 && ((addr_mode
== CODE_64BIT
12551 ? !i
.index_reg
->reg_type
.bitfield
.qword
12552 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12553 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12556 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12557 if (t
->mnem_off
== MN_bndmk
12558 || t
->mnem_off
== MN_bndldx
12559 || t
->mnem_off
== MN_bndstx
12560 || t
->opcode_modifier
.sib
== SIBMEM
)
12562 /* They cannot use RIP-relative addressing. */
12563 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12565 as_bad (_("`%s' cannot be used here"), operand_string
);
12569 /* bndldx and bndstx ignore their scale factor. */
12570 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12571 && i
.log2_scale_factor
)
12572 as_warn (_("register scaling is being ignored here"));
12577 /* 16-bit checks. */
12578 if (i
.disp_encoding
== disp_encoding_32bit
)
12582 && (!i
.base_reg
->reg_type
.bitfield
.word
12583 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12585 && (!i
.index_reg
->reg_type
.bitfield
.word
12586 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12588 && i
.base_reg
->reg_num
< 6
12589 && i
.index_reg
->reg_num
>= 6
12590 && i
.log2_scale_factor
== 0))))
12597 /* Handle vector immediates. */
12600 RC_SAE_immediate (const char *imm_start
)
12602 const char *pstr
= imm_start
;
12607 pstr
= RC_SAE_specifier (pstr
+ 1);
12611 if (*pstr
++ != '}')
12613 as_bad (_("Missing '}': '%s'"), imm_start
);
12616 /* RC/SAE immediate string should contain nothing more. */;
12619 as_bad (_("Junk after '}': '%s'"), imm_start
);
12623 /* Internally this doesn't count as an operand. */
12629 static INLINE
bool starts_memory_operand (char c
)
12632 || is_name_beginner (c
)
12633 || strchr ("([\"+-!~", c
);
12636 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12640 i386_att_operand (char *operand_string
)
12642 const reg_entry
*r
;
12644 char *op_string
= operand_string
;
12646 if (is_space_char (*op_string
))
12649 /* We check for an absolute prefix (differentiating,
12650 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12651 if (*op_string
== ABSOLUTE_PREFIX
12652 && current_templates
->start
->opcode_modifier
.jump
)
12655 if (is_space_char (*op_string
))
12657 i
.jumpabsolute
= true;
12660 /* Check if operand is a register. */
12661 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12663 i386_operand_type temp
;
12668 /* Check for a segment override by searching for ':' after a
12669 segment register. */
12670 op_string
= end_op
;
12671 if (is_space_char (*op_string
))
12673 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12675 i
.seg
[i
.mem_operands
] = r
;
12677 /* Skip the ':' and whitespace. */
12679 if (is_space_char (*op_string
))
12682 /* Handle case of %es:*foo. */
12683 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12684 && current_templates
->start
->opcode_modifier
.jump
)
12687 if (is_space_char (*op_string
))
12689 i
.jumpabsolute
= true;
12692 if (!starts_memory_operand (*op_string
))
12694 as_bad (_("bad memory operand `%s'"), op_string
);
12697 goto do_memory_reference
;
12700 /* Handle vector operations. */
12701 if (*op_string
== '{')
12703 op_string
= check_VecOperations (op_string
);
12704 if (op_string
== NULL
)
12710 as_bad (_("junk `%s' after register"), op_string
);
12714 /* Reject pseudo registers for .insn. */
12715 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12717 as_bad (_("`%s%s' cannot be used here"),
12718 register_prefix
, r
->reg_name
);
12722 temp
= r
->reg_type
;
12723 temp
.bitfield
.baseindex
= 0;
12724 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12726 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12727 i
.op
[this_operand
].regs
= r
;
12730 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12731 operand was also present earlier on. */
12732 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12733 && i
.reg_operands
== 1)
12737 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12738 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12740 as_bad (_("`%s': misplaced `{%s}'"),
12741 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12745 else if (*op_string
== REGISTER_PREFIX
)
12747 as_bad (_("bad register name `%s'"), op_string
);
12750 else if (*op_string
== IMMEDIATE_PREFIX
)
12753 if (i
.jumpabsolute
)
12755 as_bad (_("immediate operand illegal with absolute jump"));
12758 if (!i386_immediate (op_string
))
12760 if (i
.rounding
.type
!= rc_none
)
12762 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12763 insn_name (current_templates
->start
));
12767 else if (RC_SAE_immediate (operand_string
))
12769 /* If it is a RC or SAE immediate, do the necessary placement check:
12770 Only another immediate or a GPR may precede it. */
12771 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12772 || (i
.reg_operands
== 1
12773 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12775 as_bad (_("`%s': misplaced `%s'"),
12776 insn_name (current_templates
->start
), operand_string
);
12780 else if (starts_memory_operand (*op_string
))
12782 /* This is a memory reference of some sort. */
12785 /* Start and end of displacement string expression (if found). */
12786 char *displacement_string_start
;
12787 char *displacement_string_end
;
12789 do_memory_reference
:
12790 /* Check for base index form. We detect the base index form by
12791 looking for an ')' at the end of the operand, searching
12792 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12794 base_string
= op_string
+ strlen (op_string
);
12796 /* Handle vector operations. */
12798 if (is_space_char (*base_string
))
12801 if (*base_string
== '}')
12803 char *vop_start
= NULL
;
12805 while (base_string
-- > op_string
)
12807 if (*base_string
== '"')
12809 if (*base_string
!= '{')
12812 vop_start
= base_string
;
12815 if (is_space_char (*base_string
))
12818 if (*base_string
!= '}')
12826 as_bad (_("unbalanced figure braces"));
12830 if (check_VecOperations (vop_start
) == NULL
)
12834 /* If we only have a displacement, set-up for it to be parsed later. */
12835 displacement_string_start
= op_string
;
12836 displacement_string_end
= base_string
+ 1;
12838 if (*base_string
== ')')
12841 unsigned int parens_not_balanced
= 0;
12842 bool in_quotes
= false;
12844 /* We've already checked that the number of left & right ()'s are
12845 equal, and that there's a matching set of double quotes. */
12846 end_op
= base_string
;
12847 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12849 if (*temp_string
== '\\' && temp_string
[1] == '"')
12851 else if (*temp_string
== '"')
12852 in_quotes
= !in_quotes
;
12853 else if (!in_quotes
)
12855 if (*temp_string
== '(' && !parens_not_balanced
++)
12856 base_string
= temp_string
;
12857 if (*temp_string
== ')')
12858 --parens_not_balanced
;
12862 temp_string
= base_string
;
12864 /* Skip past '(' and whitespace. */
12865 gas_assert (*base_string
== '(');
12867 if (is_space_char (*base_string
))
12870 if (*base_string
== ','
12871 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12874 displacement_string_end
= temp_string
;
12876 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12880 if (i
.base_reg
== &bad_reg
)
12882 base_string
= end_op
;
12883 if (is_space_char (*base_string
))
12887 /* There may be an index reg or scale factor here. */
12888 if (*base_string
== ',')
12891 if (is_space_char (*base_string
))
12894 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12897 if (i
.index_reg
== &bad_reg
)
12899 base_string
= end_op
;
12900 if (is_space_char (*base_string
))
12902 if (*base_string
== ',')
12905 if (is_space_char (*base_string
))
12908 else if (*base_string
!= ')')
12910 as_bad (_("expecting `,' or `)' "
12911 "after index register in `%s'"),
12916 else if (*base_string
== REGISTER_PREFIX
)
12918 end_op
= strchr (base_string
, ',');
12921 as_bad (_("bad register name `%s'"), base_string
);
12925 /* Check for scale factor. */
12926 if (*base_string
!= ')')
12928 char *end_scale
= i386_scale (base_string
);
12933 base_string
= end_scale
;
12934 if (is_space_char (*base_string
))
12936 if (*base_string
!= ')')
12938 as_bad (_("expecting `)' "
12939 "after scale factor in `%s'"),
12944 else if (!i
.index_reg
)
12946 as_bad (_("expecting index register or scale factor "
12947 "after `,'; got '%c'"),
12952 else if (*base_string
!= ')')
12954 as_bad (_("expecting `,' or `)' "
12955 "after base register in `%s'"),
12960 else if (*base_string
== REGISTER_PREFIX
)
12962 end_op
= strchr (base_string
, ',');
12965 as_bad (_("bad register name `%s'"), base_string
);
12970 /* If there's an expression beginning the operand, parse it,
12971 assuming displacement_string_start and
12972 displacement_string_end are meaningful. */
12973 if (displacement_string_start
!= displacement_string_end
)
12975 if (!i386_displacement (displacement_string_start
,
12976 displacement_string_end
))
12980 /* Special case for (%dx) while doing input/output op. */
12982 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12983 && i
.base_reg
->reg_type
.bitfield
.word
12984 && i
.index_reg
== 0
12985 && i
.log2_scale_factor
== 0
12986 && i
.seg
[i
.mem_operands
] == 0
12987 && !operand_type_check (i
.types
[this_operand
], disp
))
12989 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12990 i
.input_output_operand
= true;
12994 if (i386_index_check (operand_string
) == 0)
12996 i
.flags
[this_operand
] |= Operand_Mem
;
13001 /* It's not a memory operand; argh! */
13002 as_bad (_("invalid char %s beginning operand %d `%s'"),
13003 output_invalid (*op_string
),
13008 return 1; /* Normal return. */
13011 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13012 that an rs_machine_dependent frag may reach. */
13015 i386_frag_max_var (fragS
*frag
)
13017 /* The only relaxable frags are for jumps.
13018 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13019 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13020 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13025 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13027 /* STT_GNU_IFUNC symbol must go through PLT. */
13028 if ((symbol_get_bfdsym (fr_symbol
)->flags
13029 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13032 if (!S_IS_EXTERNAL (fr_symbol
))
13033 /* Symbol may be weak or local. */
13034 return !S_IS_WEAK (fr_symbol
);
13036 /* Global symbols with non-default visibility can't be preempted. */
13037 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13040 if (fr_var
!= NO_RELOC
)
13041 switch ((enum bfd_reloc_code_real
) fr_var
)
13043 case BFD_RELOC_386_PLT32
:
13044 case BFD_RELOC_X86_64_PLT32
:
13045 /* Symbol with PLT relocation may be preempted. */
13051 /* Global symbols with default visibility in a shared library may be
13052 preempted by another definition. */
13057 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13058 Note also work for Skylake and Cascadelake.
13059 ---------------------------------------------------------------------
13060 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13061 | ------ | ----------- | ------- | -------- |
13063 | Jno | N | N | Y |
13064 | Jc/Jb | Y | N | Y |
13065 | Jae/Jnb | Y | N | Y |
13066 | Je/Jz | Y | Y | Y |
13067 | Jne/Jnz | Y | Y | Y |
13068 | Jna/Jbe | Y | N | Y |
13069 | Ja/Jnbe | Y | N | Y |
13071 | Jns | N | N | Y |
13072 | Jp/Jpe | N | N | Y |
13073 | Jnp/Jpo | N | N | Y |
13074 | Jl/Jnge | Y | Y | Y |
13075 | Jge/Jnl | Y | Y | Y |
13076 | Jle/Jng | Y | Y | Y |
13077 | Jg/Jnle | Y | Y | Y |
13078 --------------------------------------------------------------------- */
13080 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13082 if (mf_cmp
== mf_cmp_alu_cmp
)
13083 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13084 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13085 if (mf_cmp
== mf_cmp_incdec
)
13086 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13087 || mf_jcc
== mf_jcc_jle
);
13088 if (mf_cmp
== mf_cmp_test_and
)
13093 /* Return the next non-empty frag. */
13096 i386_next_non_empty_frag (fragS
*fragP
)
13098 /* There may be a frag with a ".fill 0" when there is no room in
13099 the current frag for frag_grow in output_insn. */
13100 for (fragP
= fragP
->fr_next
;
13102 && fragP
->fr_type
== rs_fill
13103 && fragP
->fr_fix
== 0);
13104 fragP
= fragP
->fr_next
)
13109 /* Return the next jcc frag after BRANCH_PADDING. */
13112 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13114 fragS
*branch_fragP
;
13118 if (pad_fragP
->fr_type
== rs_machine_dependent
13119 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13120 == BRANCH_PADDING
))
13122 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13123 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13125 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13126 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13127 pad_fragP
->tc_frag_data
.mf_type
))
13128 return branch_fragP
;
13134 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13137 i386_classify_machine_dependent_frag (fragS
*fragP
)
13141 fragS
*branch_fragP
;
13143 unsigned int max_prefix_length
;
13145 if (fragP
->tc_frag_data
.classified
)
13148 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13149 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13150 for (next_fragP
= fragP
;
13151 next_fragP
!= NULL
;
13152 next_fragP
= next_fragP
->fr_next
)
13154 next_fragP
->tc_frag_data
.classified
= 1;
13155 if (next_fragP
->fr_type
== rs_machine_dependent
)
13156 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13158 case BRANCH_PADDING
:
13159 /* The BRANCH_PADDING frag must be followed by a branch
13161 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13162 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13164 case FUSED_JCC_PADDING
:
13165 /* Check if this is a fused jcc:
13167 CMP like instruction
13171 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13172 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13173 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13176 /* The BRANCH_PADDING frag is merged with the
13177 FUSED_JCC_PADDING frag. */
13178 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13179 /* CMP like instruction size. */
13180 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13181 frag_wane (pad_fragP
);
13182 /* Skip to branch_fragP. */
13183 next_fragP
= branch_fragP
;
13185 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13187 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13189 next_fragP
->fr_subtype
13190 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13191 next_fragP
->tc_frag_data
.max_bytes
13192 = next_fragP
->tc_frag_data
.max_prefix_length
;
13193 /* This will be updated in the BRANCH_PREFIX scan. */
13194 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13197 frag_wane (next_fragP
);
13202 /* Stop if there is no BRANCH_PREFIX. */
13203 if (!align_branch_prefix_size
)
13206 /* Scan for BRANCH_PREFIX. */
13207 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13209 if (fragP
->fr_type
!= rs_machine_dependent
13210 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13214 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13215 COND_JUMP_PREFIX. */
13216 max_prefix_length
= 0;
13217 for (next_fragP
= fragP
;
13218 next_fragP
!= NULL
;
13219 next_fragP
= next_fragP
->fr_next
)
13221 if (next_fragP
->fr_type
== rs_fill
)
13222 /* Skip rs_fill frags. */
13224 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13225 /* Stop for all other frags. */
13228 /* rs_machine_dependent frags. */
13229 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13232 /* Count BRANCH_PREFIX frags. */
13233 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13235 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13236 frag_wane (next_fragP
);
13240 += next_fragP
->tc_frag_data
.max_bytes
;
13242 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13244 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13245 == FUSED_JCC_PADDING
))
13247 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13248 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13252 /* Stop for other rs_machine_dependent frags. */
13256 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13258 /* Skip to the next frag. */
13259 fragP
= next_fragP
;
13263 /* Compute padding size for
13266 CMP like instruction
13268 COND_JUMP/UNCOND_JUMP
13273 COND_JUMP/UNCOND_JUMP
13277 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13279 unsigned int offset
, size
, padding_size
;
13280 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13282 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13284 address
= fragP
->fr_address
;
13285 address
+= fragP
->fr_fix
;
13287 /* CMP like instrunction size. */
13288 size
= fragP
->tc_frag_data
.cmp_size
;
13290 /* The base size of the branch frag. */
13291 size
+= branch_fragP
->fr_fix
;
13293 /* Add opcode and displacement bytes for the rs_machine_dependent
13295 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13296 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13298 /* Check if branch is within boundary and doesn't end at the last
13300 offset
= address
& ((1U << align_branch_power
) - 1);
13301 if ((offset
+ size
) >= (1U << align_branch_power
))
13302 /* Padding needed to avoid crossing boundary. */
13303 padding_size
= (1U << align_branch_power
) - offset
;
13305 /* No padding needed. */
13308 /* The return value may be saved in tc_frag_data.length which is
13310 if (!fits_in_unsigned_byte (padding_size
))
13313 return padding_size
;
13316 /* i386_generic_table_relax_frag()
13318 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13319 grow/shrink padding to align branch frags. Hand others to
13323 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13325 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13326 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13328 long padding_size
= i386_branch_padding_size (fragP
, 0);
13329 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13331 /* When the BRANCH_PREFIX frag is used, the computed address
13332 must match the actual address and there should be no padding. */
13333 if (fragP
->tc_frag_data
.padding_address
13334 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13338 /* Update the padding size. */
13340 fragP
->tc_frag_data
.length
= padding_size
;
13344 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13346 fragS
*padding_fragP
, *next_fragP
;
13347 long padding_size
, left_size
, last_size
;
13349 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13350 if (!padding_fragP
)
13351 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13352 return (fragP
->tc_frag_data
.length
13353 - fragP
->tc_frag_data
.last_length
);
13355 /* Compute the relative address of the padding frag in the very
13356 first time where the BRANCH_PREFIX frag sizes are zero. */
13357 if (!fragP
->tc_frag_data
.padding_address
)
13358 fragP
->tc_frag_data
.padding_address
13359 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13361 /* First update the last length from the previous interation. */
13362 left_size
= fragP
->tc_frag_data
.prefix_length
;
13363 for (next_fragP
= fragP
;
13364 next_fragP
!= padding_fragP
;
13365 next_fragP
= next_fragP
->fr_next
)
13366 if (next_fragP
->fr_type
== rs_machine_dependent
13367 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13372 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13376 if (max
> left_size
)
13381 next_fragP
->tc_frag_data
.last_length
= size
;
13385 next_fragP
->tc_frag_data
.last_length
= 0;
13388 /* Check the padding size for the padding frag. */
13389 padding_size
= i386_branch_padding_size
13390 (padding_fragP
, (fragP
->fr_address
13391 + fragP
->tc_frag_data
.padding_address
));
13393 last_size
= fragP
->tc_frag_data
.prefix_length
;
13394 /* Check if there is change from the last interation. */
13395 if (padding_size
== last_size
)
13397 /* Update the expected address of the padding frag. */
13398 padding_fragP
->tc_frag_data
.padding_address
13399 = (fragP
->fr_address
+ padding_size
13400 + fragP
->tc_frag_data
.padding_address
);
13404 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13406 /* No padding if there is no sufficient room. Clear the
13407 expected address of the padding frag. */
13408 padding_fragP
->tc_frag_data
.padding_address
= 0;
13412 /* Store the expected address of the padding frag. */
13413 padding_fragP
->tc_frag_data
.padding_address
13414 = (fragP
->fr_address
+ padding_size
13415 + fragP
->tc_frag_data
.padding_address
);
13417 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13419 /* Update the length for the current interation. */
13420 left_size
= padding_size
;
13421 for (next_fragP
= fragP
;
13422 next_fragP
!= padding_fragP
;
13423 next_fragP
= next_fragP
->fr_next
)
13424 if (next_fragP
->fr_type
== rs_machine_dependent
13425 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13430 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13434 if (max
> left_size
)
13439 next_fragP
->tc_frag_data
.length
= size
;
13443 next_fragP
->tc_frag_data
.length
= 0;
13446 return (fragP
->tc_frag_data
.length
13447 - fragP
->tc_frag_data
.last_length
);
13449 return relax_frag (segment
, fragP
, stretch
);
13452 /* md_estimate_size_before_relax()
13454 Called just before relax() for rs_machine_dependent frags. The x86
13455 assembler uses these frags to handle variable size jump
13458 Any symbol that is now undefined will not become defined.
13459 Return the correct fr_subtype in the frag.
13460 Return the initial "guess for variable size of frag" to caller.
13461 The guess is actually the growth beyond the fixed part. Whatever
13462 we do to grow the fixed or variable part contributes to our
13466 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13468 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13469 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13470 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13472 i386_classify_machine_dependent_frag (fragP
);
13473 return fragP
->tc_frag_data
.length
;
13476 /* We've already got fragP->fr_subtype right; all we have to do is
13477 check for un-relaxable symbols. On an ELF system, we can't relax
13478 an externally visible symbol, because it may be overridden by a
13480 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13481 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13483 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13486 #if defined (OBJ_COFF) && defined (TE_PE)
13487 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13488 && S_IS_WEAK (fragP
->fr_symbol
))
13492 /* Symbol is undefined in this segment, or we need to keep a
13493 reloc so that weak symbols can be overridden. */
13494 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13495 enum bfd_reloc_code_real reloc_type
;
13496 unsigned char *opcode
;
13500 if (fragP
->fr_var
!= NO_RELOC
)
13501 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13502 else if (size
== 2)
13503 reloc_type
= BFD_RELOC_16_PCREL
;
13504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13505 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13506 && need_plt32_p (fragP
->fr_symbol
))
13507 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13510 reloc_type
= BFD_RELOC_32_PCREL
;
13512 old_fr_fix
= fragP
->fr_fix
;
13513 opcode
= (unsigned char *) fragP
->fr_opcode
;
13515 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13518 /* Make jmp (0xeb) a (d)word displacement jump. */
13520 fragP
->fr_fix
+= size
;
13521 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13523 fragP
->fr_offset
, 1,
13529 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13531 /* Negate the condition, and branch past an
13532 unconditional jump. */
13535 /* Insert an unconditional jump. */
13537 /* We added two extra opcode bytes, and have a two byte
13539 fragP
->fr_fix
+= 2 + 2;
13540 fix_new (fragP
, old_fr_fix
+ 2, 2,
13542 fragP
->fr_offset
, 1,
13546 /* Fall through. */
13549 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13551 fragP
->fr_fix
+= 1;
13552 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13554 fragP
->fr_offset
, 1,
13555 BFD_RELOC_8_PCREL
);
13556 fixP
->fx_signed
= 1;
13560 /* This changes the byte-displacement jump 0x7N
13561 to the (d)word-displacement jump 0x0f,0x8N. */
13562 opcode
[1] = opcode
[0] + 0x10;
13563 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13564 /* We've added an opcode byte. */
13565 fragP
->fr_fix
+= 1 + size
;
13566 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13568 fragP
->fr_offset
, 1,
13573 BAD_CASE (fragP
->fr_subtype
);
13577 /* All jumps handled here are signed, but don't unconditionally use a
13578 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13579 around at 4G (outside of 64-bit mode) and 64k. */
13580 if (size
== 4 && flag_code
== CODE_64BIT
)
13581 fixP
->fx_signed
= 1;
13584 return fragP
->fr_fix
- old_fr_fix
;
13587 /* Guess size depending on current relax state. Initially the relax
13588 state will correspond to a short jump and we return 1, because
13589 the variable part of the frag (the branch offset) is one byte
13590 long. However, we can relax a section more than once and in that
13591 case we must either set fr_subtype back to the unrelaxed state,
13592 or return the value for the appropriate branch. */
13593 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13596 /* Called after relax() is finished.
13598 In: Address of frag.
13599 fr_type == rs_machine_dependent.
13600 fr_subtype is what the address relaxed to.
13602 Out: Any fixSs and constants are set up.
13603 Caller will turn frag into a ".space 0". */
13606 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13609 unsigned char *opcode
;
13610 unsigned char *where_to_put_displacement
= NULL
;
13611 offsetT target_address
;
13612 offsetT opcode_address
;
13613 unsigned int extension
= 0;
13614 offsetT displacement_from_opcode_start
;
13616 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13617 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13618 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13620 /* Generate nop padding. */
13621 unsigned int size
= fragP
->tc_frag_data
.length
;
13624 if (size
> fragP
->tc_frag_data
.max_bytes
)
13630 const char *branch
= "branch";
13631 const char *prefix
= "";
13632 fragS
*padding_fragP
;
13633 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13636 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13637 switch (fragP
->tc_frag_data
.default_prefix
)
13642 case CS_PREFIX_OPCODE
:
13645 case DS_PREFIX_OPCODE
:
13648 case ES_PREFIX_OPCODE
:
13651 case FS_PREFIX_OPCODE
:
13654 case GS_PREFIX_OPCODE
:
13657 case SS_PREFIX_OPCODE
:
13662 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13663 "%s within %d-byte boundary\n");
13665 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13666 "align %s within %d-byte boundary\n");
13670 padding_fragP
= fragP
;
13671 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13672 "%s within %d-byte boundary\n");
13676 switch (padding_fragP
->tc_frag_data
.branch_type
)
13678 case align_branch_jcc
:
13681 case align_branch_fused
:
13682 branch
= "fused jcc";
13684 case align_branch_jmp
:
13687 case align_branch_call
:
13690 case align_branch_indirect
:
13691 branch
= "indiret branch";
13693 case align_branch_ret
:
13700 fprintf (stdout
, msg
,
13701 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13702 (long long) fragP
->fr_address
, branch
,
13703 1 << align_branch_power
);
13705 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13706 memset (fragP
->fr_opcode
,
13707 fragP
->tc_frag_data
.default_prefix
, size
);
13709 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13711 fragP
->fr_fix
+= size
;
13716 opcode
= (unsigned char *) fragP
->fr_opcode
;
13718 /* Address we want to reach in file space. */
13719 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13721 /* Address opcode resides at in file space. */
13722 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13724 /* Displacement from opcode start to fill into instruction. */
13725 displacement_from_opcode_start
= target_address
- opcode_address
;
13727 if ((fragP
->fr_subtype
& BIG
) == 0)
13729 /* Don't have to change opcode. */
13730 extension
= 1; /* 1 opcode + 1 displacement */
13731 where_to_put_displacement
= &opcode
[1];
13735 if (no_cond_jump_promotion
13736 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13737 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13738 _("long jump required"));
13740 switch (fragP
->fr_subtype
)
13742 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13743 extension
= 4; /* 1 opcode + 4 displacement */
13745 where_to_put_displacement
= &opcode
[1];
13748 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13749 extension
= 2; /* 1 opcode + 2 displacement */
13751 where_to_put_displacement
= &opcode
[1];
13754 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13755 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13756 extension
= 5; /* 2 opcode + 4 displacement */
13757 opcode
[1] = opcode
[0] + 0x10;
13758 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13759 where_to_put_displacement
= &opcode
[2];
13762 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13763 extension
= 3; /* 2 opcode + 2 displacement */
13764 opcode
[1] = opcode
[0] + 0x10;
13765 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13766 where_to_put_displacement
= &opcode
[2];
13769 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13774 where_to_put_displacement
= &opcode
[3];
13778 BAD_CASE (fragP
->fr_subtype
);
13783 /* If size if less then four we are sure that the operand fits,
13784 but if it's 4, then it could be that the displacement is larger
13786 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13788 && ((addressT
) (displacement_from_opcode_start
- extension
13789 + ((addressT
) 1 << 31))
13790 > (((addressT
) 2 << 31) - 1)))
13792 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13793 _("jump target out of range"));
13794 /* Make us emit 0. */
13795 displacement_from_opcode_start
= extension
;
13797 /* Now put displacement after opcode. */
13798 md_number_to_chars ((char *) where_to_put_displacement
,
13799 (valueT
) (displacement_from_opcode_start
- extension
),
13800 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13801 fragP
->fr_fix
+= extension
;
13804 /* Apply a fixup (fixP) to segment data, once it has been determined
13805 by our caller that we have all the info we need to fix it up.
13807 Parameter valP is the pointer to the value of the bits.
13809 On the 386, immediates, displacements, and data pointers are all in
13810 the same (little-endian) format, so we don't need to care about which
13811 we are handling. */
13814 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13816 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13817 valueT value
= *valP
;
13819 #if !defined (TE_Mach)
13820 if (fixP
->fx_pcrel
)
13822 switch (fixP
->fx_r_type
)
13828 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13831 case BFD_RELOC_X86_64_32S
:
13832 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13835 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13838 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13843 if (fixP
->fx_addsy
!= NULL
13844 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13845 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13846 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13847 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13848 && !use_rela_relocations
)
13850 /* This is a hack. There should be a better way to handle this.
13851 This covers for the fact that bfd_install_relocation will
13852 subtract the current location (for partial_inplace, PC relative
13853 relocations); see more below. */
13857 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13860 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13862 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13865 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13867 if ((sym_seg
== seg
13868 || (symbol_section_p (fixP
->fx_addsy
)
13869 && sym_seg
!= absolute_section
))
13870 && !generic_force_reloc (fixP
))
13872 /* Yes, we add the values in twice. This is because
13873 bfd_install_relocation subtracts them out again. I think
13874 bfd_install_relocation is broken, but I don't dare change
13876 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13880 #if defined (OBJ_COFF) && defined (TE_PE)
13881 /* For some reason, the PE format does not store a
13882 section address offset for a PC relative symbol. */
13883 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13884 || S_IS_WEAK (fixP
->fx_addsy
))
13885 value
+= md_pcrel_from (fixP
);
13888 #if defined (OBJ_COFF) && defined (TE_PE)
13889 if (fixP
->fx_addsy
!= NULL
13890 && S_IS_WEAK (fixP
->fx_addsy
)
13891 /* PR 16858: Do not modify weak function references. */
13892 && ! fixP
->fx_pcrel
)
13894 #if !defined (TE_PEP)
13895 /* For x86 PE weak function symbols are neither PC-relative
13896 nor do they set S_IS_FUNCTION. So the only reliable way
13897 to detect them is to check the flags of their containing
13899 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13900 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13904 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13908 /* Fix a few things - the dynamic linker expects certain values here,
13909 and we must not disappoint it. */
13910 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13911 if (IS_ELF
&& fixP
->fx_addsy
)
13912 switch (fixP
->fx_r_type
)
13914 case BFD_RELOC_386_PLT32
:
13915 case BFD_RELOC_X86_64_PLT32
:
13916 /* Make the jump instruction point to the address of the operand.
13917 At runtime we merely add the offset to the actual PLT entry.
13918 NB: Subtract the offset size only for jump instructions. */
13919 if (fixP
->fx_pcrel
)
13923 case BFD_RELOC_386_TLS_GD
:
13924 case BFD_RELOC_386_TLS_LDM
:
13925 case BFD_RELOC_386_TLS_IE_32
:
13926 case BFD_RELOC_386_TLS_IE
:
13927 case BFD_RELOC_386_TLS_GOTIE
:
13928 case BFD_RELOC_386_TLS_GOTDESC
:
13929 case BFD_RELOC_X86_64_TLSGD
:
13930 case BFD_RELOC_X86_64_TLSLD
:
13931 case BFD_RELOC_X86_64_GOTTPOFF
:
13932 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13933 value
= 0; /* Fully resolved at runtime. No addend. */
13935 case BFD_RELOC_386_TLS_LE
:
13936 case BFD_RELOC_386_TLS_LDO_32
:
13937 case BFD_RELOC_386_TLS_LE_32
:
13938 case BFD_RELOC_X86_64_DTPOFF32
:
13939 case BFD_RELOC_X86_64_DTPOFF64
:
13940 case BFD_RELOC_X86_64_TPOFF32
:
13941 case BFD_RELOC_X86_64_TPOFF64
:
13942 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13945 case BFD_RELOC_386_TLS_DESC_CALL
:
13946 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13947 value
= 0; /* Fully resolved at runtime. No addend. */
13948 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13952 case BFD_RELOC_VTABLE_INHERIT
:
13953 case BFD_RELOC_VTABLE_ENTRY
:
13960 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13962 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13964 value
= extend_to_32bit_address (value
);
13967 #endif /* !defined (TE_Mach) */
13969 /* Are we finished with this relocation now? */
13970 if (fixP
->fx_addsy
== NULL
)
13973 switch (fixP
->fx_r_type
)
13975 case BFD_RELOC_X86_64_32S
:
13976 fixP
->fx_signed
= 1;
13983 #if defined (OBJ_COFF) && defined (TE_PE)
13984 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13987 /* Remember value for tc_gen_reloc. */
13988 fixP
->fx_addnumber
= value
;
13989 /* Clear out the frag for now. */
13993 else if (use_rela_relocations
)
13995 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13996 fixP
->fx_no_overflow
= 1;
13997 /* Remember value for tc_gen_reloc. */
13998 fixP
->fx_addnumber
= value
;
14002 md_number_to_chars (p
, value
, fixP
->fx_size
);
14006 md_atof (int type
, char *litP
, int *sizeP
)
14008 /* This outputs the LITTLENUMs in REVERSE order;
14009 in accord with the bigendian 386. */
14010 return ieee_md_atof (type
, litP
, sizeP
, false);
14013 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14016 output_invalid (int c
)
14019 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14022 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14023 "(0x%x)", (unsigned char) c
);
14024 return output_invalid_buf
;
14027 /* Verify that @r can be used in the current context. */
14029 static bool check_register (const reg_entry
*r
)
14031 if (allow_pseudo_reg
)
14034 if (operand_type_all_zero (&r
->reg_type
))
14037 if ((r
->reg_type
.bitfield
.dword
14038 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14039 || r
->reg_type
.bitfield
.class == RegCR
14040 || r
->reg_type
.bitfield
.class == RegDR
)
14041 && !cpu_arch_flags
.bitfield
.cpui386
)
14044 if (r
->reg_type
.bitfield
.class == RegTR
14045 && (flag_code
== CODE_64BIT
14046 || !cpu_arch_flags
.bitfield
.cpui386
14047 || cpu_arch_isa_flags
.bitfield
.cpui586
14048 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14051 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14054 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14056 if (r
->reg_type
.bitfield
.zmmword
14057 || r
->reg_type
.bitfield
.class == RegMask
)
14060 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14062 if (r
->reg_type
.bitfield
.ymmword
)
14065 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14070 if (r
->reg_type
.bitfield
.zmmword
)
14072 if (vector_size
< VSZ512
)
14075 if (i
.vec_encoding
== vex_encoding_default
)
14076 i
.vec_encoding
= vex_encoding_evex512
;
14077 else if (i
.vec_encoding
!= vex_encoding_evex
14078 && i
.vec_encoding
!= vex_encoding_evex512
)
14079 i
.vec_encoding
= vex_encoding_error
;
14082 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14085 if (r
->reg_type
.bitfield
.tmmword
14086 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14087 || flag_code
!= CODE_64BIT
))
14090 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14093 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14094 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14097 /* Upper 16 vector registers are only available with VREX in 64bit
14098 mode, and require EVEX encoding. */
14099 if (r
->reg_flags
& RegVRex
)
14101 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14102 || flag_code
!= CODE_64BIT
)
14105 if (i
.vec_encoding
== vex_encoding_default
14106 || i
.vec_encoding
== vex_encoding_evex512
)
14107 i
.vec_encoding
= vex_encoding_evex
;
14108 else if (i
.vec_encoding
!= vex_encoding_evex
)
14109 i
.vec_encoding
= vex_encoding_error
;
14112 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14113 && (!cpu_arch_flags
.bitfield
.cpu64
14114 || r
->reg_type
.bitfield
.class != RegCR
14116 && flag_code
!= CODE_64BIT
)
14119 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14126 /* REG_STRING starts *before* REGISTER_PREFIX. */
14128 static const reg_entry
*
14129 parse_real_register (const char *reg_string
, char **end_op
)
14131 const char *s
= reg_string
;
14133 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14134 const reg_entry
*r
;
14136 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14137 if (*s
== REGISTER_PREFIX
)
14140 if (is_space_char (*s
))
14143 p
= reg_name_given
;
14144 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14146 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14147 return (const reg_entry
*) NULL
;
14151 if (is_part_of_name (*s
))
14152 return (const reg_entry
*) NULL
;
14154 *end_op
= (char *) s
;
14156 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14158 /* Handle floating point regs, allowing spaces in the (i) part. */
14161 if (!cpu_arch_flags
.bitfield
.cpu8087
14162 && !cpu_arch_flags
.bitfield
.cpu287
14163 && !cpu_arch_flags
.bitfield
.cpu387
14164 && !allow_pseudo_reg
)
14165 return (const reg_entry
*) NULL
;
14167 if (is_space_char (*s
))
14172 if (is_space_char (*s
))
14174 if (*s
>= '0' && *s
<= '7')
14176 int fpr
= *s
- '0';
14178 if (is_space_char (*s
))
14182 *end_op
= (char *) s
+ 1;
14183 know (r
[fpr
].reg_num
== fpr
);
14187 /* We have "%st(" then garbage. */
14188 return (const reg_entry
*) NULL
;
14192 return r
&& check_register (r
) ? r
: NULL
;
14195 /* REG_STRING starts *before* REGISTER_PREFIX. */
14197 static const reg_entry
*
14198 parse_register (const char *reg_string
, char **end_op
)
14200 const reg_entry
*r
;
14202 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14203 r
= parse_real_register (reg_string
, end_op
);
14208 char *save
= input_line_pointer
;
14209 char *buf
= xstrdup (reg_string
), *name
;
14212 input_line_pointer
= buf
;
14213 get_symbol_name (&name
);
14214 symbolP
= symbol_find (name
);
14215 while (symbolP
&& symbol_equated_p (symbolP
))
14217 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14219 if (e
->X_add_number
)
14221 symbolP
= e
->X_add_symbol
;
14223 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14225 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14227 if (e
->X_op
== O_register
)
14229 know (e
->X_add_number
>= 0
14230 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14231 r
= i386_regtab
+ e
->X_add_number
;
14232 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14234 if (r
&& !check_register (r
))
14236 as_bad (_("register '%s%s' cannot be used here"),
14237 register_prefix
, r
->reg_name
);
14241 input_line_pointer
= save
;
14248 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14250 const reg_entry
*r
= NULL
;
14251 char *end
= input_line_pointer
;
14253 /* We only know the terminating character here. It being double quote could
14254 be the closing one of a quoted symbol name, or an opening one from a
14255 following string (or another quoted symbol name). Since the latter can't
14256 be valid syntax for anything, bailing in either case is good enough. */
14257 if (*nextcharP
== '"')
14261 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14262 r
= parse_real_register (name
, &input_line_pointer
);
14263 if (r
&& end
<= input_line_pointer
)
14265 *nextcharP
= *input_line_pointer
;
14266 *input_line_pointer
= 0;
14267 e
->X_op
= O_register
;
14268 e
->X_add_number
= r
- i386_regtab
;
14271 input_line_pointer
= end
;
14273 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14277 md_operand (expressionS
*e
)
14280 const reg_entry
*r
;
14282 switch (*input_line_pointer
)
14284 case REGISTER_PREFIX
:
14285 r
= parse_real_register (input_line_pointer
, &end
);
14288 e
->X_op
= O_register
;
14289 e
->X_add_number
= r
- i386_regtab
;
14290 input_line_pointer
= end
;
14295 gas_assert (intel_syntax
);
14296 end
= input_line_pointer
++;
14298 if (*input_line_pointer
== ']')
14300 ++input_line_pointer
;
14301 e
->X_op_symbol
= make_expr_symbol (e
);
14302 e
->X_add_symbol
= NULL
;
14303 e
->X_add_number
= 0;
14308 e
->X_op
= O_absent
;
14309 input_line_pointer
= end
;
14316 /* To maintain consistency with !BFD64 builds of gas record, whether any
14317 (binary) operator was involved in an expression. As expressions are
14318 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14319 truncate results. */
14320 bool i386_record_operator (operatorT op
,
14321 const expressionS
*left
,
14322 const expressionS
*right
)
14324 if (op
== O_absent
)
14329 /* Since the expression parser applies unary operators fine to bignum
14330 operands, we don't need to be concerned of respective operands not
14331 fitting in 32 bits. */
14332 if (right
->X_op
== O_constant
&& right
->X_unsigned
14333 && !fits_in_unsigned_long (right
->X_add_number
))
14336 /* This isn't entirely right: The pattern can also result when constant
14337 expressions are folded (e.g. 0xffffffff + 1). */
14338 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14339 && !fits_in_unsigned_long (left
->X_add_number
))
14340 || (right
->X_op
== O_constant
&& right
->X_unsigned
14341 && !fits_in_unsigned_long (right
->X_add_number
)))
14342 expr_mode
= expr_large_value
;
14344 if (expr_mode
!= expr_large_value
)
14345 expr_mode
= expr_operator_present
;
14351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14352 const char *md_shortopts
= "kVQ:sqnO::";
14354 const char *md_shortopts
= "qnO::";
14357 #define OPTION_32 (OPTION_MD_BASE + 0)
14358 #define OPTION_64 (OPTION_MD_BASE + 1)
14359 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14360 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14361 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14362 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14363 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14364 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14365 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14366 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14367 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14368 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14369 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14370 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14371 #define OPTION_X32 (OPTION_MD_BASE + 14)
14372 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14373 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14374 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14375 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14376 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14377 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14378 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14379 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14380 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14381 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14382 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14383 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14384 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14385 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14386 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14387 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14388 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14389 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14390 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14391 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14393 struct option md_longopts
[] =
14395 {"32", no_argument
, NULL
, OPTION_32
},
14396 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14397 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14398 {"64", no_argument
, NULL
, OPTION_64
},
14400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14401 {"x32", no_argument
, NULL
, OPTION_X32
},
14402 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14403 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14405 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14406 {"march", required_argument
, NULL
, OPTION_MARCH
},
14407 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14408 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14409 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14410 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14411 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14412 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14413 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14414 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14415 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14416 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14417 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14418 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14419 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14420 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14421 # if defined (TE_PE) || defined (TE_PEP)
14422 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14424 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14425 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14426 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14427 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14428 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14429 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14430 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14431 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14432 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14433 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14434 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14435 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14436 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14437 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14438 {NULL
, no_argument
, NULL
, 0}
14440 size_t md_longopts_size
= sizeof (md_longopts
);
14443 md_parse_option (int c
, const char *arg
)
14446 char *arch
, *next
, *saved
, *type
;
14451 optimize_align_code
= 0;
14455 quiet_warnings
= 1;
14458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14459 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14460 should be emitted or not. FIXME: Not implemented. */
14462 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14466 /* -V: SVR4 argument to print version ID. */
14468 print_version_id ();
14471 /* -k: Ignore for FreeBSD compatibility. */
14476 /* -s: On i386 Solaris, this tells the native assembler to use
14477 .stab instead of .stab.excl. We always use .stab anyhow. */
14480 case OPTION_MSHARED
:
14484 case OPTION_X86_USED_NOTE
:
14485 if (strcasecmp (arg
, "yes") == 0)
14487 else if (strcasecmp (arg
, "no") == 0)
14490 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14495 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14496 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14499 const char **list
, **l
;
14501 list
= bfd_target_list ();
14502 for (l
= list
; *l
!= NULL
; l
++)
14503 if (startswith (*l
, "elf64-x86-64")
14504 || strcmp (*l
, "coff-x86-64") == 0
14505 || strcmp (*l
, "pe-x86-64") == 0
14506 || strcmp (*l
, "pei-x86-64") == 0
14507 || strcmp (*l
, "mach-o-x86-64") == 0)
14509 default_arch
= "x86_64";
14513 as_fatal (_("no compiled in support for x86_64"));
14519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14523 const char **list
, **l
;
14525 list
= bfd_target_list ();
14526 for (l
= list
; *l
!= NULL
; l
++)
14527 if (startswith (*l
, "elf32-x86-64"))
14529 default_arch
= "x86_64:32";
14533 as_fatal (_("no compiled in support for 32bit x86_64"));
14537 as_fatal (_("32bit x86_64 is only supported for ELF"));
14543 const char **list
, **l
;
14545 list
= bfd_target_list ();
14546 for (l
= list
; *l
!= NULL
; l
++)
14547 if (strstr (*l
, "-i386")
14548 || strstr (*l
, "-go32"))
14550 default_arch
= "i386";
14554 as_fatal (_("no compiled in support for ix86"));
14559 case OPTION_DIVIDE
:
14560 #ifdef SVR4_COMMENT_CHARS
14565 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14567 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14571 i386_comment_chars
= n
;
14577 saved
= xstrdup (arg
);
14579 /* Allow -march=+nosse. */
14587 as_fatal (_("invalid -march= option: `%s'"), arg
);
14588 next
= strchr (arch
, '+');
14591 vsz
= strchr (arch
, '/');
14594 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14596 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14599 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14600 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14603 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14606 cpu_arch_name
= cpu_arch
[j
].name
;
14607 free (cpu_sub_arch_name
);
14608 cpu_sub_arch_name
= NULL
;
14609 cpu_arch_flags
= cpu_arch
[j
].enable
;
14610 cpu_arch_isa
= cpu_arch
[j
].type
;
14611 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14612 if (!cpu_arch_tune_set
)
14614 cpu_arch_tune
= cpu_arch_isa
;
14615 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14617 vector_size
= VSZ_DEFAULT
;
14620 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14621 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14622 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14624 /* ISA extension. */
14627 switch (cpu_arch
[j
].vsz
)
14636 unsigned long val
= strtoul (vsz
, &end
, 0);
14642 case 512: vector_size
= VSZ512
; break;
14643 case 256: vector_size
= VSZ256
; break;
14644 case 128: vector_size
= VSZ128
; break;
14646 as_warn (_("Unrecognized vector size specifier ignored"));
14651 /* Fall through. */
14653 vector_size
= VSZ_DEFAULT
;
14661 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14663 /* Disable an ISA extension. */
14664 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14665 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14666 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14669 if (cpu_arch
[j
].vsz
== vsz_set
)
14670 vector_size
= VSZ_DEFAULT
;
14675 if (j
>= ARRAY_SIZE (cpu_arch
))
14676 as_fatal (_("invalid -march= option: `%s'"), arg
);
14680 while (next
!= NULL
);
14686 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14687 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14689 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14690 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14692 cpu_arch_tune_set
= 1;
14693 cpu_arch_tune
= cpu_arch
[j
].type
;
14694 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14698 if (j
>= ARRAY_SIZE (cpu_arch
))
14699 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14702 case OPTION_MMNEMONIC
:
14703 if (strcasecmp (arg
, "att") == 0)
14704 intel_mnemonic
= 0;
14705 else if (strcasecmp (arg
, "intel") == 0)
14706 intel_mnemonic
= 1;
14708 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14711 case OPTION_MSYNTAX
:
14712 if (strcasecmp (arg
, "att") == 0)
14714 else if (strcasecmp (arg
, "intel") == 0)
14717 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14720 case OPTION_MINDEX_REG
:
14721 allow_index_reg
= 1;
14724 case OPTION_MNAKED_REG
:
14725 allow_naked_reg
= 1;
14728 case OPTION_MSSE2AVX
:
14732 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14733 use_unaligned_vector_move
= 1;
14736 case OPTION_MSSE_CHECK
:
14737 if (strcasecmp (arg
, "error") == 0)
14738 sse_check
= check_error
;
14739 else if (strcasecmp (arg
, "warning") == 0)
14740 sse_check
= check_warning
;
14741 else if (strcasecmp (arg
, "none") == 0)
14742 sse_check
= check_none
;
14744 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14747 case OPTION_MOPERAND_CHECK
:
14748 if (strcasecmp (arg
, "error") == 0)
14749 operand_check
= check_error
;
14750 else if (strcasecmp (arg
, "warning") == 0)
14751 operand_check
= check_warning
;
14752 else if (strcasecmp (arg
, "none") == 0)
14753 operand_check
= check_none
;
14755 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14758 case OPTION_MAVXSCALAR
:
14759 if (strcasecmp (arg
, "128") == 0)
14760 avxscalar
= vex128
;
14761 else if (strcasecmp (arg
, "256") == 0)
14762 avxscalar
= vex256
;
14764 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14767 case OPTION_MVEXWIG
:
14768 if (strcmp (arg
, "0") == 0)
14770 else if (strcmp (arg
, "1") == 0)
14773 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14776 case OPTION_MADD_BND_PREFIX
:
14777 add_bnd_prefix
= 1;
14780 case OPTION_MEVEXLIG
:
14781 if (strcmp (arg
, "128") == 0)
14782 evexlig
= evexl128
;
14783 else if (strcmp (arg
, "256") == 0)
14784 evexlig
= evexl256
;
14785 else if (strcmp (arg
, "512") == 0)
14786 evexlig
= evexl512
;
14788 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14791 case OPTION_MEVEXRCIG
:
14792 if (strcmp (arg
, "rne") == 0)
14794 else if (strcmp (arg
, "rd") == 0)
14796 else if (strcmp (arg
, "ru") == 0)
14798 else if (strcmp (arg
, "rz") == 0)
14801 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14804 case OPTION_MEVEXWIG
:
14805 if (strcmp (arg
, "0") == 0)
14807 else if (strcmp (arg
, "1") == 0)
14810 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14813 # if defined (TE_PE) || defined (TE_PEP)
14814 case OPTION_MBIG_OBJ
:
14819 case OPTION_MOMIT_LOCK_PREFIX
:
14820 if (strcasecmp (arg
, "yes") == 0)
14821 omit_lock_prefix
= 1;
14822 else if (strcasecmp (arg
, "no") == 0)
14823 omit_lock_prefix
= 0;
14825 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14828 case OPTION_MFENCE_AS_LOCK_ADD
:
14829 if (strcasecmp (arg
, "yes") == 0)
14831 else if (strcasecmp (arg
, "no") == 0)
14834 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14837 case OPTION_MLFENCE_AFTER_LOAD
:
14838 if (strcasecmp (arg
, "yes") == 0)
14839 lfence_after_load
= 1;
14840 else if (strcasecmp (arg
, "no") == 0)
14841 lfence_after_load
= 0;
14843 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14846 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14847 if (strcasecmp (arg
, "all") == 0)
14849 lfence_before_indirect_branch
= lfence_branch_all
;
14850 if (lfence_before_ret
== lfence_before_ret_none
)
14851 lfence_before_ret
= lfence_before_ret_shl
;
14853 else if (strcasecmp (arg
, "memory") == 0)
14854 lfence_before_indirect_branch
= lfence_branch_memory
;
14855 else if (strcasecmp (arg
, "register") == 0)
14856 lfence_before_indirect_branch
= lfence_branch_register
;
14857 else if (strcasecmp (arg
, "none") == 0)
14858 lfence_before_indirect_branch
= lfence_branch_none
;
14860 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14864 case OPTION_MLFENCE_BEFORE_RET
:
14865 if (strcasecmp (arg
, "or") == 0)
14866 lfence_before_ret
= lfence_before_ret_or
;
14867 else if (strcasecmp (arg
, "not") == 0)
14868 lfence_before_ret
= lfence_before_ret_not
;
14869 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14870 lfence_before_ret
= lfence_before_ret_shl
;
14871 else if (strcasecmp (arg
, "none") == 0)
14872 lfence_before_ret
= lfence_before_ret_none
;
14874 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14878 case OPTION_MRELAX_RELOCATIONS
:
14879 if (strcasecmp (arg
, "yes") == 0)
14880 generate_relax_relocations
= 1;
14881 else if (strcasecmp (arg
, "no") == 0)
14882 generate_relax_relocations
= 0;
14884 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14887 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14890 long int align
= strtoul (arg
, &end
, 0);
14895 align_branch_power
= 0;
14898 else if (align
>= 16)
14901 for (align_power
= 0;
14903 align
>>= 1, align_power
++)
14905 /* Limit alignment power to 31. */
14906 if (align
== 1 && align_power
< 32)
14908 align_branch_power
= align_power
;
14913 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14917 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14920 int align
= strtoul (arg
, &end
, 0);
14921 /* Some processors only support 5 prefixes. */
14922 if (*end
== '\0' && align
>= 0 && align
< 6)
14924 align_branch_prefix_size
= align
;
14927 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14932 case OPTION_MALIGN_BRANCH
:
14934 saved
= xstrdup (arg
);
14938 next
= strchr (type
, '+');
14941 if (strcasecmp (type
, "jcc") == 0)
14942 align_branch
|= align_branch_jcc_bit
;
14943 else if (strcasecmp (type
, "fused") == 0)
14944 align_branch
|= align_branch_fused_bit
;
14945 else if (strcasecmp (type
, "jmp") == 0)
14946 align_branch
|= align_branch_jmp_bit
;
14947 else if (strcasecmp (type
, "call") == 0)
14948 align_branch
|= align_branch_call_bit
;
14949 else if (strcasecmp (type
, "ret") == 0)
14950 align_branch
|= align_branch_ret_bit
;
14951 else if (strcasecmp (type
, "indirect") == 0)
14952 align_branch
|= align_branch_indirect_bit
;
14954 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14957 while (next
!= NULL
);
14961 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14962 align_branch_power
= 5;
14963 align_branch_prefix_size
= 5;
14964 align_branch
= (align_branch_jcc_bit
14965 | align_branch_fused_bit
14966 | align_branch_jmp_bit
);
14969 case OPTION_MAMD64
:
14973 case OPTION_MINTEL64
:
14981 /* Turn off -Os. */
14982 optimize_for_space
= 0;
14984 else if (*arg
== 's')
14986 optimize_for_space
= 1;
14987 /* Turn on all encoding optimizations. */
14988 optimize
= INT_MAX
;
14992 optimize
= atoi (arg
);
14993 /* Turn off -Os. */
14994 optimize_for_space
= 0;
15004 #define MESSAGE_TEMPLATE \
15008 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15009 int *left_p
, const char *name
, int len
)
15011 int size
= sizeof (MESSAGE_TEMPLATE
);
15012 int left
= *left_p
;
15014 /* Reserve 2 spaces for ", " or ",\0" */
15017 /* Check if there is any room. */
15025 p
= mempcpy (p
, name
, len
);
15029 /* Output the current message now and start a new one. */
15032 fprintf (stream
, "%s\n", message
);
15034 left
= size
- (start
- message
) - len
- 2;
15036 gas_assert (left
>= 0);
15038 p
= mempcpy (p
, name
, len
);
15046 show_arch (FILE *stream
, int ext
, int check
)
15048 static char message
[] = MESSAGE_TEMPLATE
;
15049 char *start
= message
+ 27;
15051 int size
= sizeof (MESSAGE_TEMPLATE
);
15058 left
= size
- (start
- message
);
15062 p
= output_message (stream
, p
, message
, start
, &left
,
15063 STRING_COMMA_LEN ("default"));
15064 p
= output_message (stream
, p
, message
, start
, &left
,
15065 STRING_COMMA_LEN ("push"));
15066 p
= output_message (stream
, p
, message
, start
, &left
,
15067 STRING_COMMA_LEN ("pop"));
15070 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15072 /* Should it be skipped? */
15073 if (cpu_arch
[j
].skip
)
15076 name
= cpu_arch
[j
].name
;
15077 len
= cpu_arch
[j
].len
;
15078 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15080 /* It is an extension. Skip if we aren't asked to show it. */
15081 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15086 /* It is an processor. Skip if we show only extension. */
15089 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15091 /* It is an impossible processor - skip. */
15095 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15098 /* Display disabled extensions. */
15100 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15104 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15105 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15107 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15108 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15114 fprintf (stream
, "%s\n", message
);
15118 md_show_usage (FILE *stream
)
15120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15121 fprintf (stream
, _("\
15122 -Qy, -Qn ignored\n\
15123 -V print assembler version number\n\
15126 fprintf (stream
, _("\
15127 -n do not optimize code alignment\n\
15128 -O{012s} attempt some code optimizations\n\
15129 -q quieten some warnings\n"));
15130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15131 fprintf (stream
, _("\
15135 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15136 fprintf (stream
, _("\
15137 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15138 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15139 fprintf (stream
, _("\
15140 --32/--64 generate 32bit/64bit object\n"));
15143 #ifdef SVR4_COMMENT_CHARS
15144 fprintf (stream
, _("\
15145 --divide do not treat `/' as a comment character\n"));
15147 fprintf (stream
, _("\
15148 --divide ignored\n"));
15150 fprintf (stream
, _("\
15151 -march=CPU[,+EXTENSION...]\n\
15152 generate code for CPU and EXTENSION, CPU is one of:\n"));
15153 show_arch (stream
, 0, 1);
15154 fprintf (stream
, _("\
15155 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15156 show_arch (stream
, 1, 0);
15157 fprintf (stream
, _("\
15158 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15159 show_arch (stream
, 0, 0);
15160 fprintf (stream
, _("\
15161 -msse2avx encode SSE instructions with VEX prefix\n"));
15162 fprintf (stream
, _("\
15163 -muse-unaligned-vector-move\n\
15164 encode aligned vector move as unaligned vector move\n"));
15165 fprintf (stream
, _("\
15166 -msse-check=[none|error|warning] (default: warning)\n\
15167 check SSE instructions\n"));
15168 fprintf (stream
, _("\
15169 -moperand-check=[none|error|warning] (default: warning)\n\
15170 check operand combinations for validity\n"));
15171 fprintf (stream
, _("\
15172 -mavxscalar=[128|256] (default: 128)\n\
15173 encode scalar AVX instructions with specific vector\n\
15175 fprintf (stream
, _("\
15176 -mvexwig=[0|1] (default: 0)\n\
15177 encode VEX instructions with specific VEX.W value\n\
15178 for VEX.W bit ignored instructions\n"));
15179 fprintf (stream
, _("\
15180 -mevexlig=[128|256|512] (default: 128)\n\
15181 encode scalar EVEX instructions with specific vector\n\
15183 fprintf (stream
, _("\
15184 -mevexwig=[0|1] (default: 0)\n\
15185 encode EVEX instructions with specific EVEX.W value\n\
15186 for EVEX.W bit ignored instructions\n"));
15187 fprintf (stream
, _("\
15188 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15189 encode EVEX instructions with specific EVEX.RC value\n\
15190 for SAE-only ignored instructions\n"));
15191 fprintf (stream
, _("\
15192 -mmnemonic=[att|intel] "));
15193 if (SYSV386_COMPAT
)
15194 fprintf (stream
, _("(default: att)\n"));
15196 fprintf (stream
, _("(default: intel)\n"));
15197 fprintf (stream
, _("\
15198 use AT&T/Intel mnemonic\n"));
15199 fprintf (stream
, _("\
15200 -msyntax=[att|intel] (default: att)\n\
15201 use AT&T/Intel syntax\n"));
15202 fprintf (stream
, _("\
15203 -mindex-reg support pseudo index registers\n"));
15204 fprintf (stream
, _("\
15205 -mnaked-reg don't require `%%' prefix for registers\n"));
15206 fprintf (stream
, _("\
15207 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15209 fprintf (stream
, _("\
15210 -mshared disable branch optimization for shared code\n"));
15211 fprintf (stream
, _("\
15212 -mx86-used-note=[no|yes] "));
15213 if (DEFAULT_X86_USED_NOTE
)
15214 fprintf (stream
, _("(default: yes)\n"));
15216 fprintf (stream
, _("(default: no)\n"));
15217 fprintf (stream
, _("\
15218 generate x86 used ISA and feature properties\n"));
15220 #if defined (TE_PE) || defined (TE_PEP)
15221 fprintf (stream
, _("\
15222 -mbig-obj generate big object files\n"));
15224 fprintf (stream
, _("\
15225 -momit-lock-prefix=[no|yes] (default: no)\n\
15226 strip all lock prefixes\n"));
15227 fprintf (stream
, _("\
15228 -mfence-as-lock-add=[no|yes] (default: no)\n\
15229 encode lfence, mfence and sfence as\n\
15230 lock addl $0x0, (%%{re}sp)\n"));
15231 fprintf (stream
, _("\
15232 -mrelax-relocations=[no|yes] "));
15233 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15234 fprintf (stream
, _("(default: yes)\n"));
15236 fprintf (stream
, _("(default: no)\n"));
15237 fprintf (stream
, _("\
15238 generate relax relocations\n"));
15239 fprintf (stream
, _("\
15240 -malign-branch-boundary=NUM (default: 0)\n\
15241 align branches within NUM byte boundary\n"));
15242 fprintf (stream
, _("\
15243 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15244 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15246 specify types of branches to align\n"));
15247 fprintf (stream
, _("\
15248 -malign-branch-prefix-size=NUM (default: 5)\n\
15249 align branches with NUM prefixes per instruction\n"));
15250 fprintf (stream
, _("\
15251 -mbranches-within-32B-boundaries\n\
15252 align branches within 32 byte boundary\n"));
15253 fprintf (stream
, _("\
15254 -mlfence-after-load=[no|yes] (default: no)\n\
15255 generate lfence after load\n"));
15256 fprintf (stream
, _("\
15257 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15258 generate lfence before indirect near branch\n"));
15259 fprintf (stream
, _("\
15260 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15261 generate lfence before ret\n"));
15262 fprintf (stream
, _("\
15263 -mamd64 accept only AMD64 ISA [default]\n"));
15264 fprintf (stream
, _("\
15265 -mintel64 accept only Intel64 ISA\n"));
15268 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15269 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15270 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15272 /* Pick the target format to use. */
15275 i386_target_format (void)
15277 if (startswith (default_arch
, "x86_64"))
15279 update_code_flag (CODE_64BIT
, 1);
15280 if (default_arch
[6] == '\0')
15281 x86_elf_abi
= X86_64_ABI
;
15283 x86_elf_abi
= X86_64_X32_ABI
;
15285 else if (!strcmp (default_arch
, "i386"))
15286 update_code_flag (CODE_32BIT
, 1);
15287 else if (!strcmp (default_arch
, "iamcu"))
15289 update_code_flag (CODE_32BIT
, 1);
15290 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15292 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15293 cpu_arch_name
= "iamcu";
15294 free (cpu_sub_arch_name
);
15295 cpu_sub_arch_name
= NULL
;
15296 cpu_arch_flags
= iamcu_flags
;
15297 cpu_arch_isa
= PROCESSOR_IAMCU
;
15298 cpu_arch_isa_flags
= iamcu_flags
;
15299 if (!cpu_arch_tune_set
)
15301 cpu_arch_tune
= cpu_arch_isa
;
15302 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
15305 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15306 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15310 as_fatal (_("unknown architecture"));
15312 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15313 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15314 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
15315 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15317 switch (OUTPUT_FLAVOR
)
15319 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15320 case bfd_target_aout_flavour
:
15321 return AOUT_TARGET_FORMAT
;
15323 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15324 # if defined (TE_PE) || defined (TE_PEP)
15325 case bfd_target_coff_flavour
:
15326 if (flag_code
== CODE_64BIT
)
15329 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15331 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15332 # elif defined (TE_GO32)
15333 case bfd_target_coff_flavour
:
15334 return "coff-go32";
15336 case bfd_target_coff_flavour
:
15337 return "coff-i386";
15340 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15341 case bfd_target_elf_flavour
:
15343 const char *format
;
15345 switch (x86_elf_abi
)
15348 format
= ELF_TARGET_FORMAT
;
15350 tls_get_addr
= "___tls_get_addr";
15354 use_rela_relocations
= 1;
15357 tls_get_addr
= "__tls_get_addr";
15359 format
= ELF_TARGET_FORMAT64
;
15361 case X86_64_X32_ABI
:
15362 use_rela_relocations
= 1;
15365 tls_get_addr
= "__tls_get_addr";
15367 disallow_64bit_reloc
= 1;
15368 format
= ELF_TARGET_FORMAT32
;
15371 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15373 if (x86_elf_abi
!= I386_ABI
)
15374 as_fatal (_("Intel MCU is 32bit only"));
15375 return ELF_TARGET_IAMCU_FORMAT
;
15381 #if defined (OBJ_MACH_O)
15382 case bfd_target_mach_o_flavour
:
15383 if (flag_code
== CODE_64BIT
)
15385 use_rela_relocations
= 1;
15387 return "mach-o-x86-64";
15390 return "mach-o-i386";
15398 #endif /* OBJ_MAYBE_ more than one */
15401 md_undefined_symbol (char *name
)
15403 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15404 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15405 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15406 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15410 if (symbol_find (name
))
15411 as_bad (_("GOT already in symbol table"));
15412 GOT_symbol
= symbol_new (name
, undefined_section
,
15413 &zero_address_frag
, 0);
15420 /* Round up a section size to the appropriate boundary. */
15423 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15425 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15426 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15428 /* For a.out, force the section size to be aligned. If we don't do
15429 this, BFD will align it for us, but it will not write out the
15430 final bytes of the section. This may be a bug in BFD, but it is
15431 easier to fix it here since that is how the other a.out targets
15435 align
= bfd_section_alignment (segment
);
15436 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15443 /* On the i386, PC-relative offsets are relative to the start of the
15444 next instruction. That is, the address of the offset, plus its
15445 size, since the offset is always the last part of the insn. */
15448 md_pcrel_from (fixS
*fixP
)
15450 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15456 s_bss (int ignore ATTRIBUTE_UNUSED
)
15460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15462 obj_elf_section_change_hook ();
15464 temp
= get_absolute_expression ();
15465 subseg_set (bss_section
, (subsegT
) temp
);
15466 demand_empty_rest_of_line ();
15471 /* Remember constant directive. */
15474 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15476 if (last_insn
.kind
!= last_insn_directive
15477 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15479 last_insn
.seg
= now_seg
;
15480 last_insn
.kind
= last_insn_directive
;
15481 last_insn
.name
= "constant directive";
15482 last_insn
.file
= as_where (&last_insn
.line
);
15483 if (lfence_before_ret
!= lfence_before_ret_none
)
15485 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15486 as_warn (_("constant directive skips -mlfence-before-ret "
15487 "and -mlfence-before-indirect-branch"));
15489 as_warn (_("constant directive skips -mlfence-before-ret"));
15491 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15492 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15497 i386_validate_fix (fixS
*fixp
)
15499 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15501 reloc_howto_type
*howto
;
15503 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15505 _("invalid %s relocation against register"),
15506 howto
? howto
->name
: "<unknown>");
15510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15511 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15512 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15513 return IS_ELF
&& fixp
->fx_addsy
15514 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15515 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15518 if (fixp
->fx_subsy
)
15520 if (fixp
->fx_subsy
== GOT_symbol
)
15522 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15527 if (fixp
->fx_tcbit2
)
15528 fixp
->fx_r_type
= (fixp
->fx_tcbit
15529 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15530 : BFD_RELOC_X86_64_GOTPCRELX
);
15533 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15538 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15540 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15542 fixp
->fx_subsy
= 0;
15545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15548 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15549 to section. Since PLT32 relocation must be against symbols,
15550 turn such PLT32 relocation into PC32 relocation. */
15552 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15553 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15554 && symbol_section_p (fixp
->fx_addsy
))
15555 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15558 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15559 && fixp
->fx_tcbit2
)
15560 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15569 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15572 bfd_reloc_code_real_type code
;
15574 switch (fixp
->fx_r_type
)
15576 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15579 case BFD_RELOC_SIZE32
:
15580 case BFD_RELOC_SIZE64
:
15582 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15583 && (!fixp
->fx_subsy
15584 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15585 sym
= fixp
->fx_addsy
;
15586 else if (fixp
->fx_subsy
15587 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15588 && (!fixp
->fx_addsy
15589 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15590 sym
= fixp
->fx_subsy
;
15593 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15595 /* Resolve size relocation against local symbol to size of
15596 the symbol plus addend. */
15597 valueT value
= S_GET_SIZE (sym
);
15599 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15600 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15601 if (sym
== fixp
->fx_subsy
)
15604 if (fixp
->fx_addsy
)
15605 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15607 else if (fixp
->fx_subsy
)
15608 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15609 value
+= fixp
->fx_offset
;
15610 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15612 && !fits_in_unsigned_long (value
))
15613 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15614 _("symbol size computation overflow"));
15615 fixp
->fx_addsy
= NULL
;
15616 fixp
->fx_subsy
= NULL
;
15617 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15620 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15622 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15623 "unsupported expression involving @size");
15627 /* Fall through. */
15629 case BFD_RELOC_X86_64_PLT32
:
15630 case BFD_RELOC_X86_64_GOT32
:
15631 case BFD_RELOC_X86_64_GOTPCREL
:
15632 case BFD_RELOC_X86_64_GOTPCRELX
:
15633 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15634 case BFD_RELOC_386_PLT32
:
15635 case BFD_RELOC_386_GOT32
:
15636 case BFD_RELOC_386_GOT32X
:
15637 case BFD_RELOC_386_GOTOFF
:
15638 case BFD_RELOC_386_GOTPC
:
15639 case BFD_RELOC_386_TLS_GD
:
15640 case BFD_RELOC_386_TLS_LDM
:
15641 case BFD_RELOC_386_TLS_LDO_32
:
15642 case BFD_RELOC_386_TLS_IE_32
:
15643 case BFD_RELOC_386_TLS_IE
:
15644 case BFD_RELOC_386_TLS_GOTIE
:
15645 case BFD_RELOC_386_TLS_LE_32
:
15646 case BFD_RELOC_386_TLS_LE
:
15647 case BFD_RELOC_386_TLS_GOTDESC
:
15648 case BFD_RELOC_386_TLS_DESC_CALL
:
15649 case BFD_RELOC_X86_64_TLSGD
:
15650 case BFD_RELOC_X86_64_TLSLD
:
15651 case BFD_RELOC_X86_64_DTPOFF32
:
15652 case BFD_RELOC_X86_64_DTPOFF64
:
15653 case BFD_RELOC_X86_64_GOTTPOFF
:
15654 case BFD_RELOC_X86_64_TPOFF32
:
15655 case BFD_RELOC_X86_64_TPOFF64
:
15656 case BFD_RELOC_X86_64_GOTOFF64
:
15657 case BFD_RELOC_X86_64_GOTPC32
:
15658 case BFD_RELOC_X86_64_GOT64
:
15659 case BFD_RELOC_X86_64_GOTPCREL64
:
15660 case BFD_RELOC_X86_64_GOTPC64
:
15661 case BFD_RELOC_X86_64_GOTPLT64
:
15662 case BFD_RELOC_X86_64_PLTOFF64
:
15663 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15664 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15665 case BFD_RELOC_RVA
:
15666 case BFD_RELOC_VTABLE_ENTRY
:
15667 case BFD_RELOC_VTABLE_INHERIT
:
15669 case BFD_RELOC_32_SECREL
:
15670 case BFD_RELOC_16_SECIDX
:
15672 code
= fixp
->fx_r_type
;
15674 case BFD_RELOC_X86_64_32S
:
15675 if (!fixp
->fx_pcrel
)
15677 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15678 code
= fixp
->fx_r_type
;
15681 /* Fall through. */
15683 if (fixp
->fx_pcrel
)
15685 switch (fixp
->fx_size
)
15688 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15689 _("can not do %d byte pc-relative relocation"),
15691 code
= BFD_RELOC_32_PCREL
;
15693 case 1: code
= BFD_RELOC_8_PCREL
; break;
15694 case 2: code
= BFD_RELOC_16_PCREL
; break;
15695 case 4: code
= BFD_RELOC_32_PCREL
; break;
15697 case 8: code
= BFD_RELOC_64_PCREL
; break;
15703 switch (fixp
->fx_size
)
15706 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15707 _("can not do %d byte relocation"),
15709 code
= BFD_RELOC_32
;
15711 case 1: code
= BFD_RELOC_8
; break;
15712 case 2: code
= BFD_RELOC_16
; break;
15713 case 4: code
= BFD_RELOC_32
; break;
15715 case 8: code
= BFD_RELOC_64
; break;
15722 if ((code
== BFD_RELOC_32
15723 || code
== BFD_RELOC_32_PCREL
15724 || code
== BFD_RELOC_X86_64_32S
)
15726 && fixp
->fx_addsy
== GOT_symbol
)
15729 code
= BFD_RELOC_386_GOTPC
;
15731 code
= BFD_RELOC_X86_64_GOTPC32
;
15733 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15735 && fixp
->fx_addsy
== GOT_symbol
)
15737 code
= BFD_RELOC_X86_64_GOTPC64
;
15740 rel
= XNEW (arelent
);
15741 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15742 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15744 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15746 if (!use_rela_relocations
)
15748 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15749 vtable entry to be used in the relocation's section offset. */
15750 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15751 rel
->address
= fixp
->fx_offset
;
15752 #if defined (OBJ_COFF) && defined (TE_PE)
15753 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15754 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15759 /* Use the rela in 64bit mode. */
15762 if (disallow_64bit_reloc
)
15765 case BFD_RELOC_X86_64_DTPOFF64
:
15766 case BFD_RELOC_X86_64_TPOFF64
:
15767 case BFD_RELOC_64_PCREL
:
15768 case BFD_RELOC_X86_64_GOTOFF64
:
15769 case BFD_RELOC_X86_64_GOT64
:
15770 case BFD_RELOC_X86_64_GOTPCREL64
:
15771 case BFD_RELOC_X86_64_GOTPC64
:
15772 case BFD_RELOC_X86_64_GOTPLT64
:
15773 case BFD_RELOC_X86_64_PLTOFF64
:
15774 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15775 _("cannot represent relocation type %s in x32 mode"),
15776 bfd_get_reloc_code_name (code
));
15782 if (!fixp
->fx_pcrel
)
15783 rel
->addend
= fixp
->fx_offset
;
15787 case BFD_RELOC_X86_64_PLT32
:
15788 case BFD_RELOC_X86_64_GOT32
:
15789 case BFD_RELOC_X86_64_GOTPCREL
:
15790 case BFD_RELOC_X86_64_GOTPCRELX
:
15791 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15792 case BFD_RELOC_X86_64_TLSGD
:
15793 case BFD_RELOC_X86_64_TLSLD
:
15794 case BFD_RELOC_X86_64_GOTTPOFF
:
15795 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15796 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15797 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15800 rel
->addend
= (section
->vma
15802 + fixp
->fx_addnumber
15803 + md_pcrel_from (fixp
));
15808 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15809 if (rel
->howto
== NULL
)
15811 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15812 _("cannot represent relocation type %s"),
15813 bfd_get_reloc_code_name (code
));
15814 /* Set howto to a garbage value so that we can keep going. */
15815 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15816 gas_assert (rel
->howto
!= NULL
);
15822 #include "tc-i386-intel.c"
15825 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15827 int saved_naked_reg
;
15828 char saved_register_dot
;
15830 saved_naked_reg
= allow_naked_reg
;
15831 allow_naked_reg
= 1;
15832 saved_register_dot
= register_chars
['.'];
15833 register_chars
['.'] = '.';
15834 allow_pseudo_reg
= 1;
15835 expression_and_evaluate (exp
);
15836 allow_pseudo_reg
= 0;
15837 register_chars
['.'] = saved_register_dot
;
15838 allow_naked_reg
= saved_naked_reg
;
15840 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15842 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15844 exp
->X_op
= O_constant
;
15845 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15846 .dw2_regnum
[flag_code
>> 1];
15849 exp
->X_op
= O_illegal
;
15854 tc_x86_frame_initial_instructions (void)
15856 static unsigned int sp_regno
[2];
15858 if (!sp_regno
[flag_code
>> 1])
15860 char *saved_input
= input_line_pointer
;
15861 char sp
[][4] = {"esp", "rsp"};
15864 input_line_pointer
= sp
[flag_code
>> 1];
15865 tc_x86_parse_to_dw2regnum (&exp
);
15866 gas_assert (exp
.X_op
== O_constant
);
15867 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15868 input_line_pointer
= saved_input
;
15871 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15872 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15876 x86_dwarf2_addr_size (void)
15878 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15879 if (x86_elf_abi
== X86_64_X32_ABI
)
15882 return bfd_arch_bits_per_address (stdoutput
) / 8;
15886 i386_elf_section_type (const char *str
, size_t len
)
15888 if (flag_code
== CODE_64BIT
15889 && len
== sizeof ("unwind") - 1
15890 && startswith (str
, "unwind"))
15891 return SHT_X86_64_UNWIND
;
15898 i386_solaris_fix_up_eh_frame (segT sec
)
15900 if (flag_code
== CODE_64BIT
)
15901 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15907 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15911 exp
.X_op
= O_secrel
;
15912 exp
.X_add_symbol
= symbol
;
15913 exp
.X_add_number
= 0;
15914 emit_expr (&exp
, size
);
15918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15919 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15922 x86_64_section_letter (int letter
, const char **ptr_msg
)
15924 if (flag_code
== CODE_64BIT
)
15927 return SHF_X86_64_LARGE
;
15929 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15932 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15937 handle_large_common (int small ATTRIBUTE_UNUSED
)
15939 if (flag_code
!= CODE_64BIT
)
15941 s_comm_internal (0, elf_common_parse
);
15942 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15946 static segT lbss_section
;
15947 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15948 asection
*saved_bss_section
= bss_section
;
15950 if (lbss_section
== NULL
)
15952 flagword applicable
;
15953 segT seg
= now_seg
;
15954 subsegT subseg
= now_subseg
;
15956 /* The .lbss section is for local .largecomm symbols. */
15957 lbss_section
= subseg_new (".lbss", 0);
15958 applicable
= bfd_applicable_section_flags (stdoutput
);
15959 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15960 seg_info (lbss_section
)->bss
= 1;
15962 subseg_set (seg
, subseg
);
15965 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15966 bss_section
= lbss_section
;
15968 s_comm_internal (0, elf_common_parse
);
15970 elf_com_section_ptr
= saved_com_section_ptr
;
15971 bss_section
= saved_bss_section
;
15974 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */