1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
356 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
357 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
358 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
363 i386_align_code (fragP
, count
)
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1
[] =
372 static const char f32_2
[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3
[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4
[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5
[] =
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6
[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7
[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8
[] =
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9
[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10
[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11
[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12
[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14
[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15
[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3
[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4
[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5
[] =
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6
[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7
[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8
[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt
[] = {
426 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
427 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
429 static const char *const f16_patt
[] = {
430 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
431 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code
== CODE_64BIT
)
439 if (count
> 0 && count
<= 15)
441 if (flag_code
== CODE_16BIT
)
443 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
444 f16_patt
[count
- 1], count
);
446 /* Adjust jump offset. */
447 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
450 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
451 f32_patt
[count
- 1], count
);
452 fragP
->fr_var
= count
;
456 static char *output_invalid
PARAMS ((int c
));
457 static int i386_operand
PARAMS ((char *operand_string
));
458 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
459 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
463 static void s_bss
PARAMS ((int));
466 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE
unsigned int
469 mode_from_disp_size (t
)
472 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
476 fits_in_signed_byte (num
)
479 return (num
>= -128) && (num
<= 127);
483 fits_in_unsigned_byte (num
)
486 return (num
& 0xff) == num
;
490 fits_in_unsigned_word (num
)
493 return (num
& 0xffff) == num
;
497 fits_in_signed_word (num
)
500 return (-32768 <= num
) && (num
<= 32767);
503 fits_in_signed_long (num
)
504 offsetT num ATTRIBUTE_UNUSED
;
509 return (!(((offsetT
) -1 << 31) & num
)
510 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
512 } /* fits_in_signed_long() */
514 fits_in_unsigned_long (num
)
515 offsetT num ATTRIBUTE_UNUSED
;
520 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
522 } /* fits_in_unsigned_long() */
525 smallest_imm_type (num
)
528 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
529 && !(cpu_arch_flags
& (CpuUnknown
)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
537 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
539 return (fits_in_signed_byte (num
)
540 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
541 : fits_in_unsigned_byte (num
)
542 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
543 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
544 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
545 : fits_in_signed_long (num
)
546 ? (Imm32
| Imm32S
| Imm64
)
547 : fits_in_unsigned_long (num
)
553 offset_in_range (val
, size
)
561 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
562 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
563 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
565 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations
)
572 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
573 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
575 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
577 char buf1
[40], buf2
[40];
579 sprint_value (buf1
, val
);
580 sprint_value (buf2
, val
& mask
);
581 as_warn (_("%s shortened to %s"), buf1
, buf2
);
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
596 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
604 case CS_PREFIX_OPCODE
:
605 case DS_PREFIX_OPCODE
:
606 case ES_PREFIX_OPCODE
:
607 case FS_PREFIX_OPCODE
:
608 case GS_PREFIX_OPCODE
:
609 case SS_PREFIX_OPCODE
:
613 case REPNE_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
617 case LOCK_PREFIX_OPCODE
:
625 case ADDR_PREFIX_OPCODE
:
629 case DATA_PREFIX_OPCODE
:
636 as_bad (_("same type of prefix used twice"));
641 i
.prefix
[q
] = prefix
;
646 set_code_flag (value
)
650 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
651 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
652 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
658 as_bad (_("32bit mode not supported on this CPU."));
664 set_16bit_gcc_code_flag (new_code_flag
)
667 flag_code
= new_code_flag
;
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
674 set_intel_syntax (syntax_flag
)
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg
= 0;
681 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
683 char *string
= input_line_pointer
;
684 int e
= get_symbol_end ();
686 if (strcmp (string
, "prefix") == 0)
688 else if (strcmp (string
, "noprefix") == 0)
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer
= e
;
694 demand_empty_rest_of_line ();
696 intel_syntax
= syntax_flag
;
698 if (ask_naked_reg
== 0)
701 allow_naked_reg
= (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
704 /* Conservative default. */
709 allow_naked_reg
= (ask_naked_reg
< 0);
714 int dummy ATTRIBUTE_UNUSED
;
718 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
720 char *string
= input_line_pointer
;
721 int e
= get_symbol_end ();
724 for (i
= 0; cpu_arch
[i
].name
; i
++)
726 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
728 cpu_arch_name
= cpu_arch
[i
].name
;
729 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
733 if (!cpu_arch
[i
].name
)
734 as_bad (_("no such architecture: `%s'"), string
);
736 *input_line_pointer
= e
;
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table
[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes
, 0},
749 {"align", s_align_ptwo
, 0},
751 {"arch", set_cpu_arch
, 0},
755 {"ffloat", float_cons
, 'f'},
756 {"dfloat", float_cons
, 'd'},
757 {"tfloat", float_cons
, 'x'},
759 {"noopt", s_ignore
, 0},
760 {"optim", s_ignore
, 0},
761 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
762 {"code16", set_code_flag
, CODE_16BIT
},
763 {"code32", set_code_flag
, CODE_32BIT
},
764 {"code64", set_code_flag
, CODE_64BIT
},
765 {"intel_syntax", set_intel_syntax
, 1},
766 {"att_syntax", set_intel_syntax
, 0},
767 {"file", dwarf2_directive_file
, 0},
768 {"loc", dwarf2_directive_loc
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
785 if (!strcmp (default_arch
, "x86_64"))
786 return bfd_mach_x86_64
;
787 else if (!strcmp (default_arch
, "i386"))
788 return bfd_mach_i386_i386
;
790 as_fatal (_("Unknown architecture"));
797 const char *hash_err
;
799 /* Initialize op_hash hash table. */
800 op_hash
= hash_new ();
803 register const template *optab
;
804 register templates
*core_optab
;
806 /* Setup for loop. */
808 core_optab
= (templates
*) xmalloc (sizeof (templates
));
809 core_optab
->start
= optab
;
814 if (optab
->name
== NULL
815 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
817 /* different name --> ship out current template list;
818 add to hash table; & begin anew. */
819 core_optab
->end
= optab
;
820 hash_err
= hash_insert (op_hash
,
825 as_fatal (_("Internal Error: Can't hash %s: %s"),
829 if (optab
->name
== NULL
)
831 core_optab
= (templates
*) xmalloc (sizeof (templates
));
832 core_optab
->start
= optab
;
837 /* Initialize reg_hash hash table. */
838 reg_hash
= hash_new ();
840 register const reg_entry
*regtab
;
842 for (regtab
= i386_regtab
;
843 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
846 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
848 as_fatal (_("Internal Error: Can't hash %s: %s"),
854 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
859 for (c
= 0; c
< 256; c
++)
864 mnemonic_chars
[c
] = c
;
865 register_chars
[c
] = c
;
866 operand_chars
[c
] = c
;
868 else if (islower (c
))
870 mnemonic_chars
[c
] = c
;
871 register_chars
[c
] = c
;
872 operand_chars
[c
] = c
;
874 else if (isupper (c
))
876 mnemonic_chars
[c
] = tolower (c
);
877 register_chars
[c
] = mnemonic_chars
[c
];
878 operand_chars
[c
] = c
;
881 if (isalpha (c
) || isdigit (c
))
882 identifier_chars
[c
] = c
;
885 identifier_chars
[c
] = c
;
886 operand_chars
[c
] = c
;
891 identifier_chars
['@'] = '@';
893 digit_chars
['-'] = '-';
894 identifier_chars
['_'] = '_';
895 identifier_chars
['.'] = '.';
897 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
898 operand_chars
[(unsigned char) *p
] = *p
;
901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
902 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
904 record_alignment (text_section
, 2);
905 record_alignment (data_section
, 2);
906 record_alignment (bss_section
, 2);
912 i386_print_statistics (file
)
915 hash_print_statistics (file
, "i386 opcode", op_hash
);
916 hash_print_statistics (file
, "i386 register", reg_hash
);
921 /* Debugging routines for md_assemble. */
922 static void pi
PARAMS ((char *, i386_insn
*));
923 static void pte
PARAMS ((template *));
924 static void pt
PARAMS ((unsigned int));
925 static void pe
PARAMS ((expressionS
*));
926 static void ps
PARAMS ((symbolS
*));
935 fprintf (stdout
, "%s: template ", line
);
937 fprintf (stdout
, " address: base %s index %s scale %x\n",
938 x
->base_reg
? x
->base_reg
->reg_name
: "none",
939 x
->index_reg
? x
->index_reg
->reg_name
: "none",
940 x
->log2_scale_factor
);
941 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
942 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
943 fprintf (stdout
, " sib: base %x index %x scale %x\n",
944 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
945 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
946 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
947 for (i
= 0; i
< x
->operands
; i
++)
949 fprintf (stdout
, " #%d: ", i
+ 1);
951 fprintf (stdout
, "\n");
953 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
954 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
955 if (x
->types
[i
] & Imm
)
957 if (x
->types
[i
] & Disp
)
967 fprintf (stdout
, " %d operands ", t
->operands
);
968 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
969 if (t
->extension_opcode
!= None
)
970 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
971 if (t
->opcode_modifier
& D
)
972 fprintf (stdout
, "D");
973 if (t
->opcode_modifier
& W
)
974 fprintf (stdout
, "W");
975 fprintf (stdout
, "\n");
976 for (i
= 0; i
< t
->operands
; i
++)
978 fprintf (stdout
, " #%d type ", i
+ 1);
979 pt (t
->operand_types
[i
]);
980 fprintf (stdout
, "\n");
988 fprintf (stdout
, " operation %d\n", e
->X_op
);
989 fprintf (stdout
, " add_number %ld (%lx)\n",
990 (long) e
->X_add_number
, (long) e
->X_add_number
);
993 fprintf (stdout
, " add_symbol ");
994 ps (e
->X_add_symbol
);
995 fprintf (stdout
, "\n");
999 fprintf (stdout
, " op_symbol ");
1000 ps (e
->X_op_symbol
);
1001 fprintf (stdout
, "\n");
1009 fprintf (stdout
, "%s type %s%s",
1011 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1012 segment_name (S_GET_SEGMENT (s
)));
1034 { BaseIndex
, "BaseIndex" },
1038 { Disp32S
, "d32s" },
1040 { InOutPortReg
, "InOutPortReg" },
1041 { ShiftCount
, "ShiftCount" },
1042 { Control
, "control reg" },
1043 { Test
, "test reg" },
1044 { Debug
, "debug reg" },
1045 { FloatReg
, "FReg" },
1046 { FloatAcc
, "FAcc" },
1050 { JumpAbsolute
, "Jump Absolute" },
1061 register struct type_name
*ty
;
1063 for (ty
= type_names
; ty
->mask
; ty
++)
1065 fprintf (stdout
, "%s, ", ty
->tname
);
1069 #endif /* DEBUG386 */
1072 tc_i386_force_relocation (fixp
)
1075 #ifdef BFD_ASSEMBLER
1076 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1077 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1082 return fixp
->fx_r_type
== 7;
1086 #ifdef BFD_ASSEMBLER
1088 static bfd_reloc_code_real_type
1089 reloc (size
, pcrel
, sign
, other
)
1093 bfd_reloc_code_real_type other
;
1095 if (other
!= NO_RELOC
)
1101 as_bad(_("There are no unsigned pc-relative relocations"));
1104 case 1: return BFD_RELOC_8_PCREL
;
1105 case 2: return BFD_RELOC_16_PCREL
;
1106 case 4: return BFD_RELOC_32_PCREL
;
1108 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1115 case 4: return BFD_RELOC_X86_64_32S
;
1120 case 1: return BFD_RELOC_8
;
1121 case 2: return BFD_RELOC_16
;
1122 case 4: return BFD_RELOC_32
;
1123 case 8: return BFD_RELOC_64
;
1125 as_bad (_("can not do %s %d byte relocation"),
1126 sign
? "signed" : "unsigned", size
);
1130 return BFD_RELOC_NONE
;
1133 /* Here we decide which fixups can be adjusted to make them relative to
1134 the beginning of the section instead of the symbol. Basically we need
1135 to make sure that the dynamic relocations are done correctly, so in
1136 some cases we force the original symbol to be used. */
1139 tc_i386_fix_adjustable (fixP
)
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 /* Prevent all adjustments to global symbols, or else dynamic
1144 linking will not work correctly. */
1145 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1146 || S_IS_WEAK (fixP
->fx_addsy
))
1149 /* adjust_reloc_syms doesn't know about the GOT. */
1150 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1151 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1152 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1153 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1154 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1155 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1156 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1161 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1162 #define BFD_RELOC_16 0
1163 #define BFD_RELOC_32 0
1164 #define BFD_RELOC_16_PCREL 0
1165 #define BFD_RELOC_32_PCREL 0
1166 #define BFD_RELOC_386_PLT32 0
1167 #define BFD_RELOC_386_GOT32 0
1168 #define BFD_RELOC_386_GOTOFF 0
1169 #define BFD_RELOC_X86_64_PLT32 0
1170 #define BFD_RELOC_X86_64_GOT32 0
1171 #define BFD_RELOC_X86_64_GOTPCREL 0
1174 static int intel_float_operand
PARAMS ((char *mnemonic
));
1177 intel_float_operand (mnemonic
)
1180 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1183 if (mnemonic
[0] == 'f')
1189 /* This is the guts of the machine-dependent assembler. LINE points to a
1190 machine dependent instruction. This function is supposed to emit
1191 the frags/bytes it assembles to. */
1197 /* Points to template once we've found it. */
1200 /* Count the size of the instruction generated. */
1205 char mnemonic
[MAX_MNEM_SIZE
];
1207 /* Initialize globals. */
1208 memset (&i
, '\0', sizeof (i
));
1209 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1210 i
.disp_reloc
[j
] = NO_RELOC
;
1211 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1212 memset (im_expressions
, '\0', sizeof (im_expressions
));
1213 save_stack_p
= save_stack
;
1215 /* First parse an instruction mnemonic & call i386_operand for the operands.
1216 We assume that the scrubber has arranged it so that line[0] is the valid
1217 start of a (possibly prefixed) mnemonic. */
1220 char *token_start
= l
;
1223 /* Non-zero if we found a prefix only acceptable with string insns. */
1224 const char *expecting_string_instruction
= NULL
;
1229 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1232 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1234 as_bad (_("no such instruction: `%s'"), token_start
);
1239 if (!is_space_char (*l
)
1240 && *l
!= END_OF_INSN
1241 && *l
!= PREFIX_SEPARATOR
)
1243 as_bad (_("invalid character %s in mnemonic"),
1244 output_invalid (*l
));
1247 if (token_start
== l
)
1249 if (*l
== PREFIX_SEPARATOR
)
1250 as_bad (_("expecting prefix; got nothing"));
1252 as_bad (_("expecting mnemonic; got nothing"));
1256 /* Look up instruction (or prefix) via hash table. */
1257 current_templates
= hash_find (op_hash
, mnemonic
);
1259 if (*l
!= END_OF_INSN
1260 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1261 && current_templates
1262 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1264 /* If we are in 16-bit mode, do not allow addr16 or data16.
1265 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1266 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1267 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1268 ^ (flag_code
== CODE_16BIT
)))
1270 as_bad (_("redundant %s prefix"),
1271 current_templates
->start
->name
);
1274 /* Add prefix, checking for repeated prefixes. */
1275 switch (add_prefix (current_templates
->start
->base_opcode
))
1280 expecting_string_instruction
= current_templates
->start
->name
;
1283 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1290 if (!current_templates
)
1292 /* See if we can get a match by trimming off a suffix. */
1295 case WORD_MNEM_SUFFIX
:
1296 case BYTE_MNEM_SUFFIX
:
1297 case QWORD_MNEM_SUFFIX
:
1298 i
.suffix
= mnem_p
[-1];
1300 current_templates
= hash_find (op_hash
, mnemonic
);
1302 case SHORT_MNEM_SUFFIX
:
1303 case LONG_MNEM_SUFFIX
:
1306 i
.suffix
= mnem_p
[-1];
1308 current_templates
= hash_find (op_hash
, mnemonic
);
1316 if (intel_float_operand (mnemonic
))
1317 i
.suffix
= SHORT_MNEM_SUFFIX
;
1319 i
.suffix
= LONG_MNEM_SUFFIX
;
1321 current_templates
= hash_find (op_hash
, mnemonic
);
1325 if (!current_templates
)
1327 as_bad (_("no such instruction: `%s'"), token_start
);
1332 /* Check if instruction is supported on specified architecture. */
1333 if (cpu_arch_flags
!= 0)
1335 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1336 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1338 as_warn (_("`%s' is not supported on `%s'"),
1339 current_templates
->start
->name
, cpu_arch_name
);
1341 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1343 as_warn (_("use .code16 to ensure correct addressing mode"));
1347 /* Check for rep/repne without a string instruction. */
1348 if (expecting_string_instruction
1349 && !(current_templates
->start
->opcode_modifier
& IsString
))
1351 as_bad (_("expecting string instruction after `%s'"),
1352 expecting_string_instruction
);
1356 /* There may be operands to parse. */
1357 if (*l
!= END_OF_INSN
)
1359 /* 1 if operand is pending after ','. */
1360 unsigned int expecting_operand
= 0;
1362 /* Non-zero if operand parens not balanced. */
1363 unsigned int paren_not_balanced
;
1367 /* Skip optional white space before operand. */
1368 if (is_space_char (*l
))
1370 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1372 as_bad (_("invalid character %s before operand %d"),
1373 output_invalid (*l
),
1377 token_start
= l
; /* after white space */
1378 paren_not_balanced
= 0;
1379 while (paren_not_balanced
|| *l
!= ',')
1381 if (*l
== END_OF_INSN
)
1383 if (paren_not_balanced
)
1386 as_bad (_("unbalanced parenthesis in operand %d."),
1389 as_bad (_("unbalanced brackets in operand %d."),
1394 break; /* we are done */
1396 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1398 as_bad (_("invalid character %s in operand %d"),
1399 output_invalid (*l
),
1406 ++paren_not_balanced
;
1408 --paren_not_balanced
;
1413 ++paren_not_balanced
;
1415 --paren_not_balanced
;
1419 if (l
!= token_start
)
1420 { /* Yes, we've read in another operand. */
1421 unsigned int operand_ok
;
1422 this_operand
= i
.operands
++;
1423 if (i
.operands
> MAX_OPERANDS
)
1425 as_bad (_("spurious operands; (%d operands/instruction max)"),
1429 /* Now parse operand adding info to 'i' as we go along. */
1430 END_STRING_AND_SAVE (l
);
1434 i386_intel_operand (token_start
,
1435 intel_float_operand (mnemonic
));
1437 operand_ok
= i386_operand (token_start
);
1439 RESTORE_END_STRING (l
);
1445 if (expecting_operand
)
1447 expecting_operand_after_comma
:
1448 as_bad (_("expecting operand after ','; got nothing"));
1453 as_bad (_("expecting operand before ','; got nothing"));
1458 /* Now *l must be either ',' or END_OF_INSN. */
1461 if (*++l
== END_OF_INSN
)
1463 /* Just skip it, if it's \n complain. */
1464 goto expecting_operand_after_comma
;
1466 expecting_operand
= 1;
1469 while (*l
!= END_OF_INSN
);
1473 /* Now we've parsed the mnemonic into a set of templates, and have the
1476 Next, we find a template that matches the given insn,
1477 making sure the overlap of the given operands types is consistent
1478 with the template operand types. */
1480 #define MATCH(overlap, given, template) \
1481 ((overlap & ~JumpAbsolute) \
1482 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1484 /* If given types r0 and r1 are registers they must be of the same type
1485 unless the expected operand type register overlap is null.
1486 Note that Acc in a template matches every size of reg. */
1487 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1488 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1489 ((g0) & Reg) == ((g1) & Reg) || \
1490 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1493 register unsigned int overlap0
, overlap1
;
1494 unsigned int overlap2
;
1495 unsigned int found_reverse_match
;
1498 /* All intel opcodes have reversed operands except for "bound" and
1499 "enter". We also don't reverse intersegment "jmp" and "call"
1500 instructions with 2 immediate operands so that the immediate segment
1501 precedes the offset, as it does when in AT&T mode. "enter" and the
1502 intersegment "jmp" and "call" instructions are the only ones that
1503 have two immediate operands. */
1504 if (intel_syntax
&& i
.operands
> 1
1505 && (strcmp (mnemonic
, "bound") != 0)
1506 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1508 union i386_op temp_op
;
1509 unsigned int temp_type
;
1510 #ifdef BFD_ASSEMBLER
1511 enum bfd_reloc_code_real temp_reloc
;
1518 if (i
.operands
== 2)
1523 else if (i
.operands
== 3)
1528 temp_type
= i
.types
[xchg2
];
1529 i
.types
[xchg2
] = i
.types
[xchg1
];
1530 i
.types
[xchg1
] = temp_type
;
1531 temp_op
= i
.op
[xchg2
];
1532 i
.op
[xchg2
] = i
.op
[xchg1
];
1533 i
.op
[xchg1
] = temp_op
;
1534 temp_reloc
= i
.disp_reloc
[xchg2
];
1535 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1536 i
.disp_reloc
[xchg1
] = temp_reloc
;
1538 if (i
.mem_operands
== 2)
1540 const seg_entry
*temp_seg
;
1541 temp_seg
= i
.seg
[0];
1542 i
.seg
[0] = i
.seg
[1];
1543 i
.seg
[1] = temp_seg
;
1549 /* Try to ensure constant immediates are represented in the smallest
1551 char guess_suffix
= 0;
1555 guess_suffix
= i
.suffix
;
1556 else if (i
.reg_operands
)
1558 /* Figure out a suffix from the last register operand specified.
1559 We can't do this properly yet, ie. excluding InOutPortReg,
1560 but the following works for instructions with immediates.
1561 In any case, we can't set i.suffix yet. */
1562 for (op
= i
.operands
; --op
>= 0;)
1563 if (i
.types
[op
] & Reg
)
1565 if (i
.types
[op
] & Reg8
)
1566 guess_suffix
= BYTE_MNEM_SUFFIX
;
1567 else if (i
.types
[op
] & Reg16
)
1568 guess_suffix
= WORD_MNEM_SUFFIX
;
1569 else if (i
.types
[op
] & Reg32
)
1570 guess_suffix
= LONG_MNEM_SUFFIX
;
1571 else if (i
.types
[op
] & Reg64
)
1572 guess_suffix
= QWORD_MNEM_SUFFIX
;
1576 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1577 guess_suffix
= WORD_MNEM_SUFFIX
;
1579 for (op
= i
.operands
; --op
>= 0;)
1580 if (i
.types
[op
] & Imm
)
1582 switch (i
.op
[op
].imms
->X_op
)
1585 /* If a suffix is given, this operand may be shortened. */
1586 switch (guess_suffix
)
1588 case LONG_MNEM_SUFFIX
:
1589 i
.types
[op
] |= Imm32
| Imm64
;
1591 case WORD_MNEM_SUFFIX
:
1592 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1594 case BYTE_MNEM_SUFFIX
:
1595 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1599 /* If this operand is at most 16 bits, convert it to a
1600 signed 16 bit number before trying to see whether it will
1601 fit in an even smaller size. This allows a 16-bit operand
1602 such as $0xffe0 to be recognised as within Imm8S range. */
1603 if ((i
.types
[op
] & Imm16
)
1604 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1606 i
.op
[op
].imms
->X_add_number
=
1607 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1609 if ((i
.types
[op
] & Imm32
)
1610 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1612 i
.op
[op
].imms
->X_add_number
=
1613 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1615 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1616 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1617 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1618 i
.types
[op
] &= ~Imm32
;
1623 /* Symbols and expressions. */
1625 /* Convert symbolic operand to proper sizes for matching. */
1626 switch (guess_suffix
)
1628 case QWORD_MNEM_SUFFIX
:
1629 i
.types
[op
] = Imm64
| Imm32S
;
1631 case LONG_MNEM_SUFFIX
:
1632 i
.types
[op
] = Imm32
| Imm64
;
1634 case WORD_MNEM_SUFFIX
:
1635 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1638 case BYTE_MNEM_SUFFIX
:
1639 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1648 if (i
.disp_operands
)
1650 /* Try to use the smallest displacement type too. */
1653 for (op
= i
.operands
; --op
>= 0;)
1654 if ((i
.types
[op
] & Disp
)
1655 && i
.op
[op
].imms
->X_op
== O_constant
)
1657 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1659 if (i
.types
[op
] & Disp16
)
1661 /* We know this operand is at most 16 bits, so
1662 convert to a signed 16 bit number before trying
1663 to see whether it will fit in an even smaller
1666 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1668 else if (i
.types
[op
] & Disp32
)
1670 /* We know this operand is at most 32 bits, so convert to a
1671 signed 32 bit number before trying to see whether it will
1672 fit in an even smaller size. */
1673 disp
&= (((offsetT
) 2 << 31) - 1);
1674 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1676 if (flag_code
== CODE_64BIT
)
1678 if (fits_in_signed_long (disp
))
1679 i
.types
[op
] |= Disp32S
;
1680 if (fits_in_unsigned_long (disp
))
1681 i
.types
[op
] |= Disp32
;
1683 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1684 && fits_in_signed_byte (disp
))
1685 i
.types
[op
] |= Disp8
;
1692 found_reverse_match
= 0;
1693 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1695 : (i
.suffix
== WORD_MNEM_SUFFIX
1697 : (i
.suffix
== SHORT_MNEM_SUFFIX
1699 : (i
.suffix
== LONG_MNEM_SUFFIX
1701 : (i
.suffix
== QWORD_MNEM_SUFFIX
1703 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1705 for (t
= current_templates
->start
;
1706 t
< current_templates
->end
;
1709 /* Must have right number of operands. */
1710 if (i
.operands
!= t
->operands
)
1713 /* Check the suffix, except for some instructions in intel mode. */
1714 if ((t
->opcode_modifier
& suffix_check
)
1716 && (t
->opcode_modifier
& IgnoreSize
))
1718 && t
->base_opcode
== 0xd9
1719 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1720 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1723 /* Do not verify operands when there are none. */
1724 else if (!t
->operands
)
1726 if (t
->cpu_flags
& ~cpu_arch_flags
)
1728 /* We've found a match; break out of loop. */
1732 overlap0
= i
.types
[0] & t
->operand_types
[0];
1733 switch (t
->operands
)
1736 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1741 overlap1
= i
.types
[1] & t
->operand_types
[1];
1742 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1743 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1744 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1745 t
->operand_types
[0],
1746 overlap1
, i
.types
[1],
1747 t
->operand_types
[1]))
1749 /* Check if other direction is valid ... */
1750 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1753 /* Try reversing direction of operands. */
1754 overlap0
= i
.types
[0] & t
->operand_types
[1];
1755 overlap1
= i
.types
[1] & t
->operand_types
[0];
1756 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1757 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1758 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1759 t
->operand_types
[1],
1760 overlap1
, i
.types
[1],
1761 t
->operand_types
[0]))
1763 /* Does not match either direction. */
1766 /* found_reverse_match holds which of D or FloatDR
1768 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1770 /* Found a forward 2 operand match here. */
1771 else if (t
->operands
== 3)
1773 /* Here we make use of the fact that there are no
1774 reverse match 3 operand instructions, and all 3
1775 operand instructions only need to be checked for
1776 register consistency between operands 2 and 3. */
1777 overlap2
= i
.types
[2] & t
->operand_types
[2];
1778 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1779 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1780 t
->operand_types
[1],
1781 overlap2
, i
.types
[2],
1782 t
->operand_types
[2]))
1786 /* Found either forward/reverse 2 or 3 operand match here:
1787 slip through to break. */
1789 if (t
->cpu_flags
& ~cpu_arch_flags
)
1791 found_reverse_match
= 0;
1794 /* We've found a match; break out of loop. */
1797 if (t
== current_templates
->end
)
1799 /* We found no match. */
1800 as_bad (_("suffix or operands invalid for `%s'"),
1801 current_templates
->start
->name
);
1805 if (!quiet_warnings
)
1808 && ((i
.types
[0] & JumpAbsolute
)
1809 != (t
->operand_types
[0] & JumpAbsolute
)))
1811 as_warn (_("indirect %s without `*'"), t
->name
);
1814 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1815 == (IsPrefix
|IgnoreSize
))
1817 /* Warn them that a data or address size prefix doesn't
1818 affect assembly of the next line of code. */
1819 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1823 /* Copy the template we found. */
1825 if (found_reverse_match
)
1827 /* If we found a reverse match we must alter the opcode
1828 direction bit. found_reverse_match holds bits to change
1829 (different for int & float insns). */
1831 i
.tm
.base_opcode
^= found_reverse_match
;
1833 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1834 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1837 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1840 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1841 i
.tm
.base_opcode
^= FloatR
;
1843 if (i
.tm
.opcode_modifier
& FWait
)
1844 if (! add_prefix (FWAIT_OPCODE
))
1847 /* Check string instruction segment overrides. */
1848 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1850 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1851 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1853 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1855 as_bad (_("`%s' operand %d must use `%%es' segment"),
1860 /* There's only ever one segment override allowed per instruction.
1861 This instruction possibly has a legal segment override on the
1862 second operand, so copy the segment to where non-string
1863 instructions store it, allowing common code. */
1864 i
.seg
[0] = i
.seg
[1];
1866 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1868 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1870 as_bad (_("`%s' operand %d must use `%%es' segment"),
1878 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1881 for (op
= i
.operands
; --op
>= 0; )
1882 if ((i
.types
[op
] & Reg
)
1883 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1885 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1886 i
.op
[op
].regs
->reg_name
);
1891 /* If matched instruction specifies an explicit instruction mnemonic
1893 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1895 if (i
.tm
.opcode_modifier
& Size16
)
1896 i
.suffix
= WORD_MNEM_SUFFIX
;
1897 else if (i
.tm
.opcode_modifier
& Size64
)
1898 i
.suffix
= QWORD_MNEM_SUFFIX
;
1900 i
.suffix
= LONG_MNEM_SUFFIX
;
1902 else if (i
.reg_operands
)
1904 /* If there's no instruction mnemonic suffix we try to invent one
1905 based on register operands. */
1908 /* We take i.suffix from the last register operand specified,
1909 Destination register type is more significant than source
1912 for (op
= i
.operands
; --op
>= 0;)
1913 if ((i
.types
[op
] & Reg
)
1914 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1916 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1917 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1918 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1923 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1926 for (op
= i
.operands
; --op
>= 0;)
1928 /* If this is an eight bit register, it's OK. If it's
1929 the 16 or 32 bit version of an eight bit register,
1930 we will just use the low portion, and that's OK too. */
1931 if (i
.types
[op
] & Reg8
)
1934 /* movzx and movsx should not generate this warning. */
1936 && (i
.tm
.base_opcode
== 0xfb7
1937 || i
.tm
.base_opcode
== 0xfb6
1938 || i
.tm
.base_opcode
== 0x63
1939 || i
.tm
.base_opcode
== 0xfbe
1940 || i
.tm
.base_opcode
== 0xfbf))
1943 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1945 /* Check that the template allows eight bit regs
1946 This kills insns such as `orb $1,%edx', which
1947 maybe should be allowed. */
1948 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1952 /* Prohibit these changes in the 64bit mode, since
1953 the lowering is more complicated. */
1954 if (flag_code
== CODE_64BIT
1955 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1956 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1957 i
.op
[op
].regs
->reg_name
,
1959 #if REGISTER_WARNINGS
1961 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1962 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1963 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1964 i
.op
[op
].regs
->reg_name
,
1969 /* Any other register is bad. */
1970 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1972 | Control
| Debug
| Test
1973 | FloatReg
| FloatAcc
))
1975 as_bad (_("`%%%s' not allowed with `%s%c'"),
1976 i
.op
[op
].regs
->reg_name
,
1983 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1987 for (op
= i
.operands
; --op
>= 0;)
1988 /* Reject eight bit registers, except where the template
1989 requires them. (eg. movzb) */
1990 if ((i
.types
[op
] & Reg8
) != 0
1991 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1993 as_bad (_("`%%%s' not allowed with `%s%c'"),
1994 i
.op
[op
].regs
->reg_name
,
1999 /* Warn if the e prefix on a general reg is missing. */
2000 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2001 && (i
.types
[op
] & Reg16
) != 0
2002 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2004 /* Prohibit these changes in the 64bit mode, since
2005 the lowering is more complicated. */
2006 if (flag_code
== CODE_64BIT
)
2007 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2008 i
.op
[op
].regs
->reg_name
,
2010 #if REGISTER_WARNINGS
2012 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2013 (i
.op
[op
].regs
+ 8)->reg_name
,
2014 i
.op
[op
].regs
->reg_name
,
2018 /* Warn if the r prefix on a general reg is missing. */
2019 else if ((i
.types
[op
] & Reg64
) != 0
2020 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2022 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2023 i
.op
[op
].regs
->reg_name
,
2027 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2031 for (op
= i
.operands
; --op
>= 0; )
2032 /* Reject eight bit registers, except where the template
2033 requires them. (eg. movzb) */
2034 if ((i
.types
[op
] & Reg8
) != 0
2035 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2037 as_bad (_("`%%%s' not allowed with `%s%c'"),
2038 i
.op
[op
].regs
->reg_name
,
2043 /* Warn if the e prefix on a general reg is missing. */
2044 else if (((i
.types
[op
] & Reg16
) != 0
2045 || (i
.types
[op
] & Reg32
) != 0)
2046 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2048 /* Prohibit these changes in the 64bit mode, since
2049 the lowering is more complicated. */
2050 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2051 i
.op
[op
].regs
->reg_name
,
2055 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2058 for (op
= i
.operands
; --op
>= 0;)
2059 /* Reject eight bit registers, except where the template
2060 requires them. (eg. movzb) */
2061 if ((i
.types
[op
] & Reg8
) != 0
2062 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2064 as_bad (_("`%%%s' not allowed with `%s%c'"),
2065 i
.op
[op
].regs
->reg_name
,
2070 /* Warn if the e prefix on a general reg is present. */
2071 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2072 && (i
.types
[op
] & Reg32
) != 0
2073 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2075 /* Prohibit these changes in the 64bit mode, since
2076 the lowering is more complicated. */
2077 if (flag_code
== CODE_64BIT
)
2078 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2079 i
.op
[op
].regs
->reg_name
,
2082 #if REGISTER_WARNINGS
2083 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2084 (i
.op
[op
].regs
- 8)->reg_name
,
2085 i
.op
[op
].regs
->reg_name
,
2090 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2091 /* Do nothing if the instruction is going to ignore the prefix. */
2096 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2098 i
.suffix
= stackop_size
;
2100 /* Make still unresolved immediate matches conform to size of immediate
2101 given in i.suffix. Note: overlap2 cannot be an immediate! */
2102 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2103 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2104 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2105 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2109 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2110 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2111 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2113 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2114 || overlap0
== (Imm16
| Imm32
)
2115 || overlap0
== (Imm16
| Imm32S
))
2118 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2120 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2121 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2122 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2124 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2128 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2129 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2130 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2131 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2135 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2136 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2137 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2139 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2140 || overlap1
== (Imm16
| Imm32
)
2141 || overlap1
== (Imm16
| Imm32S
))
2144 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2146 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2147 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2148 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2150 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2154 assert ((overlap2
& Imm
) == 0);
2156 i
.types
[0] = overlap0
;
2157 if (overlap0
& ImplicitRegister
)
2159 if (overlap0
& Imm1
)
2160 i
.imm_operands
= 0; /* kludge for shift insns. */
2162 i
.types
[1] = overlap1
;
2163 if (overlap1
& ImplicitRegister
)
2166 i
.types
[2] = overlap2
;
2167 if (overlap2
& ImplicitRegister
)
2170 /* Finalize opcode. First, we change the opcode based on the operand
2171 size given by i.suffix: We need not change things for byte insns. */
2173 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2175 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2179 /* For movzx and movsx, need to check the register type. */
2181 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2182 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2184 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2186 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2187 if (!add_prefix (prefix
))
2191 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2193 /* It's not a byte, select word/dword operation. */
2194 if (i
.tm
.opcode_modifier
& W
)
2196 if (i
.tm
.opcode_modifier
& ShortForm
)
2197 i
.tm
.base_opcode
|= 8;
2199 i
.tm
.base_opcode
|= 1;
2201 /* Now select between word & dword operations via the operand
2202 size prefix, except for instructions that will ignore this
2204 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2205 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2206 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2208 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2209 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2210 prefix
= ADDR_PREFIX_OPCODE
;
2212 if (! add_prefix (prefix
))
2216 /* Set mode64 for an operand. */
2217 if (i
.suffix
== QWORD_MNEM_SUFFIX
2218 && !(i
.tm
.opcode_modifier
& NoRex64
))
2221 if (flag_code
< CODE_64BIT
)
2223 as_bad (_("64bit operations available only in 64bit modes."));
2228 /* Size floating point instruction. */
2229 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2231 if (i
.tm
.opcode_modifier
& FloatMF
)
2232 i
.tm
.base_opcode
^= 4;
2236 if (i
.tm
.opcode_modifier
& ImmExt
)
2238 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2239 opcode suffix which is coded in the same place as an 8-bit
2240 immediate field would be. Here we fake an 8-bit immediate
2241 operand from the opcode suffix stored in tm.extension_opcode. */
2245 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2247 exp
= &im_expressions
[i
.imm_operands
++];
2248 i
.op
[i
.operands
].imms
= exp
;
2249 i
.types
[i
.operands
++] = Imm8
;
2250 exp
->X_op
= O_constant
;
2251 exp
->X_add_number
= i
.tm
.extension_opcode
;
2252 i
.tm
.extension_opcode
= None
;
2255 /* For insns with operands there are more diddles to do to the opcode. */
2258 /* Default segment register this instruction will use
2259 for memory accesses. 0 means unknown.
2260 This is only for optimizing out unnecessary segment overrides. */
2261 const seg_entry
*default_seg
= 0;
2263 /* The imul $imm, %reg instruction is converted into
2264 imul $imm, %reg, %reg, and the clr %reg instruction
2265 is converted into xor %reg, %reg. */
2266 if (i
.tm
.opcode_modifier
& regKludge
)
2268 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2269 /* Pretend we saw the extra register operand. */
2270 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2271 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2272 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2276 if (i
.tm
.opcode_modifier
& ShortForm
)
2278 /* The register or float register operand is in operand 0 or 1. */
2279 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2280 /* Register goes in low 3 bits of opcode. */
2281 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2282 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2284 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2286 /* Warn about some common errors, but press on regardless.
2287 The first case can be generated by gcc (<= 2.8.1). */
2288 if (i
.operands
== 2)
2290 /* Reversed arguments on faddp, fsubp, etc. */
2291 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2292 i
.op
[1].regs
->reg_name
,
2293 i
.op
[0].regs
->reg_name
);
2297 /* Extraneous `l' suffix on fp insn. */
2298 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2299 i
.op
[0].regs
->reg_name
);
2303 else if (i
.tm
.opcode_modifier
& Modrm
)
2305 /* The opcode is completed (modulo i.tm.extension_opcode which
2306 must be put into the modrm byte).
2307 Now, we make the modrm & index base bytes based on all the
2308 info we've collected. */
2310 /* i.reg_operands MUST be the number of real register operands;
2311 implicit registers do not count. */
2312 if (i
.reg_operands
== 2)
2314 unsigned int source
, dest
;
2315 source
= ((i
.types
[0]
2316 & (Reg
| RegMMX
| RegXMM
2318 | Control
| Debug
| Test
))
2323 /* One of the register operands will be encoded in the
2324 i.tm.reg field, the other in the combined i.tm.mode
2325 and i.tm.regmem fields. If no form of this
2326 instruction supports a memory destination operand,
2327 then we assume the source operand may sometimes be
2328 a memory operand and so we need to store the
2329 destination in the i.rm.reg field. */
2330 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2332 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2333 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2334 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2336 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2341 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2342 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2343 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2345 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2350 { /* If it's not 2 reg operands... */
2353 unsigned int fake_zero_displacement
= 0;
2354 unsigned int op
= ((i
.types
[0] & AnyMem
)
2356 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2363 if (! i
.disp_operands
)
2364 fake_zero_displacement
= 1;
2367 /* Operand is just <disp> */
2368 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2370 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2371 i
.types
[op
] &= ~Disp
;
2372 i
.types
[op
] |= Disp16
;
2374 else if (flag_code
!= CODE_64BIT
)
2376 i
.rm
.regmem
= NO_BASE_REGISTER
;
2377 i
.types
[op
] &= ~Disp
;
2378 i
.types
[op
] |= Disp32
;
2382 /* 64bit mode overwrites the 32bit absolute addressing
2383 by RIP relative addressing and absolute addressing
2384 is encoded by one of the redundant SIB forms. */
2386 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2387 i
.sib
.base
= NO_BASE_REGISTER
;
2388 i
.sib
.index
= NO_INDEX_REGISTER
;
2389 i
.types
[op
] &= ~Disp
;
2390 i
.types
[op
] |= Disp32S
;
2393 else /* ! i.base_reg && i.index_reg */
2395 i
.sib
.index
= i
.index_reg
->reg_num
;
2396 i
.sib
.base
= NO_BASE_REGISTER
;
2397 i
.sib
.scale
= i
.log2_scale_factor
;
2398 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2399 i
.types
[op
] &= ~Disp
;
2400 if (flag_code
!= CODE_64BIT
)
2401 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2403 i
.types
[op
] |= Disp32S
;
2404 if (i
.index_reg
->reg_flags
& RegRex
)
2408 /* RIP addressing for 64bit mode. */
2409 else if (i
.base_reg
->reg_type
== BaseIndex
)
2411 i
.rm
.regmem
= NO_BASE_REGISTER
;
2412 i
.types
[op
] &= ~Disp
;
2413 i
.types
[op
] |= Disp32S
;
2414 i
.flags
[op
] = Operand_PCrel
;
2416 else if (i
.base_reg
->reg_type
& Reg16
)
2418 switch (i
.base_reg
->reg_num
)
2423 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2424 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2431 if ((i
.types
[op
] & Disp
) == 0)
2433 /* fake (%bp) into 0(%bp) */
2434 i
.types
[op
] |= Disp8
;
2435 fake_zero_displacement
= 1;
2438 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2439 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2441 default: /* (%si) -> 4 or (%di) -> 5 */
2442 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2444 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2446 else /* i.base_reg and 32/64 bit mode */
2448 if (flag_code
== CODE_64BIT
2449 && (i
.types
[op
] & Disp
))
2451 if (i
.types
[op
] & Disp8
)
2452 i
.types
[op
] = Disp8
| Disp32S
;
2454 i
.types
[op
] = Disp32S
;
2456 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2457 if (i
.base_reg
->reg_flags
& RegRex
)
2459 i
.sib
.base
= i
.base_reg
->reg_num
;
2460 /* x86-64 ignores REX prefix bit here to avoid
2461 decoder complications. */
2462 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2465 if (i
.disp_operands
== 0)
2467 fake_zero_displacement
= 1;
2468 i
.types
[op
] |= Disp8
;
2471 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2475 i
.sib
.scale
= i
.log2_scale_factor
;
2478 /* <disp>(%esp) becomes two byte modrm
2479 with no index register. We've already
2480 stored the code for esp in i.rm.regmem
2481 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2482 base register besides %esp will not use
2483 the extra modrm byte. */
2484 i
.sib
.index
= NO_INDEX_REGISTER
;
2485 #if ! SCALE1_WHEN_NO_INDEX
2486 /* Another case where we force the second
2488 if (i
.log2_scale_factor
)
2489 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2494 i
.sib
.index
= i
.index_reg
->reg_num
;
2495 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2496 if (i
.index_reg
->reg_flags
& RegRex
)
2499 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2502 if (fake_zero_displacement
)
2504 /* Fakes a zero displacement assuming that i.types[op]
2505 holds the correct displacement size. */
2508 assert (i
.op
[op
].disps
== 0);
2509 exp
= &disp_expressions
[i
.disp_operands
++];
2510 i
.op
[op
].disps
= exp
;
2511 exp
->X_op
= O_constant
;
2512 exp
->X_add_number
= 0;
2513 exp
->X_add_symbol
= (symbolS
*) 0;
2514 exp
->X_op_symbol
= (symbolS
*) 0;
2518 /* Fill in i.rm.reg or i.rm.regmem field with register
2519 operand (if any) based on i.tm.extension_opcode.
2520 Again, we must be careful to make sure that
2521 segment/control/debug/test/MMX registers are coded
2522 into the i.rm.reg field. */
2527 & (Reg
| RegMMX
| RegXMM
2529 | Control
| Debug
| Test
))
2532 & (Reg
| RegMMX
| RegXMM
2534 | Control
| Debug
| Test
))
2537 /* If there is an extension opcode to put here, the
2538 register number must be put into the regmem field. */
2539 if (i
.tm
.extension_opcode
!= None
)
2541 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2542 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2547 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2548 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2552 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2553 we must set it to 3 to indicate this is a register
2554 operand in the regmem field. */
2555 if (!i
.mem_operands
)
2559 /* Fill in i.rm.reg field with extension opcode (if any). */
2560 if (i
.tm
.extension_opcode
!= None
)
2561 i
.rm
.reg
= i
.tm
.extension_opcode
;
2564 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2566 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2567 && i
.op
[0].regs
->reg_num
== 1)
2569 as_bad (_("you can't `pop %%cs'"));
2572 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2573 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2576 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2580 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2582 /* For the string instructions that allow a segment override
2583 on one of their operands, the default segment is ds. */
2587 /* If a segment was explicitly specified,
2588 and the specified segment is not the default,
2589 use an opcode prefix to select it.
2590 If we never figured out what the default segment is,
2591 then default_seg will be zero at this point,
2592 and the specified segment prefix will always be used. */
2593 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2595 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2599 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2601 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2602 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2606 /* Handle conversion of 'int $3' --> special int3 insn. */
2607 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2609 i
.tm
.base_opcode
= INT3_OPCODE
;
2613 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2614 && i
.op
[0].disps
->X_op
== O_constant
)
2616 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2617 the absolute address given by the constant. Since ix86 jumps and
2618 calls are pc relative, we need to generate a reloc. */
2619 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2620 i
.op
[0].disps
->X_op
= O_symbol
;
2623 if (i
.tm
.opcode_modifier
& Rex64
)
2626 /* For 8bit registers we would need an empty rex prefix.
2627 Also in the case instruction is already having prefix,
2628 we need to convert old registers to new ones. */
2630 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2631 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2632 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2633 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2637 for (x
= 0; x
< 2; x
++)
2639 /* Look for 8bit operand that does use old registers. */
2640 if (i
.types
[x
] & Reg8
2641 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2643 /* In case it is "hi" register, give up. */
2644 if (i
.op
[x
].regs
->reg_num
> 3)
2645 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2646 i
.op
[x
].regs
->reg_name
);
2648 /* Otherwise it is equivalent to the extended register.
2649 Since the encoding don't change this is merely cosmetical
2650 cleanup for debug output. */
2652 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2657 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2659 | (i
.rex
.mode64
? 8 : 0)
2660 | (i
.rex
.extX
? 4 : 0)
2661 | (i
.rex
.extY
? 2 : 0)
2662 | (i
.rex
.extZ
? 1 : 0));
2664 /* We are ready to output the insn. */
2669 if (i
.tm
.opcode_modifier
& Jump
)
2676 if (flag_code
== CODE_16BIT
)
2680 if (i
.prefix
[DATA_PREFIX
])
2686 if (i
.prefix
[REX_PREFIX
])
2696 if (i
.prefixes
!= 0 && !intel_syntax
)
2697 as_warn (_("skipping prefixes on this instruction"));
2699 /* It's always a symbol; End frag & setup for relax.
2700 Make sure there is enough room in this frag for the largest
2701 instruction we may generate in md_convert_frag. This is 2
2702 bytes for the opcode and room for the prefix and largest
2704 frag_grow (prefix
+ 2 + size
);
2705 insn_size
+= prefix
+ 1;
2706 /* Prefix and 1 opcode byte go in fr_fix. */
2707 p
= frag_more (prefix
+ 1);
2708 if (i
.prefix
[DATA_PREFIX
])
2709 *p
++ = DATA_PREFIX_OPCODE
;
2710 if (i
.prefix
[REX_PREFIX
])
2711 *p
++ = i
.prefix
[REX_PREFIX
];
2712 *p
= i
.tm
.base_opcode
;
2713 /* 1 possible extra opcode + displacement go in var part.
2714 Pass reloc in fr_var. */
2715 frag_var (rs_machine_dependent
,
2718 ((unsigned char) *p
== JUMP_PC_RELATIVE
2719 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2720 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2721 i
.op
[0].disps
->X_add_symbol
,
2722 i
.op
[0].disps
->X_add_number
,
2725 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2729 if (i
.tm
.opcode_modifier
& JumpByte
)
2731 /* This is a loop or jecxz type instruction. */
2733 if (i
.prefix
[ADDR_PREFIX
])
2736 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2745 if (flag_code
== CODE_16BIT
)
2748 if (i
.prefix
[DATA_PREFIX
])
2751 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2761 if (i
.prefix
[REX_PREFIX
])
2763 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2768 if (i
.prefixes
!= 0 && !intel_syntax
)
2769 as_warn (_("skipping prefixes on this instruction"));
2771 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2773 insn_size
+= 1 + size
;
2774 p
= frag_more (1 + size
);
2778 /* Opcode can be at most two bytes. */
2779 insn_size
+= 2 + size
;
2780 p
= frag_more (2 + size
);
2781 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2783 *p
++ = i
.tm
.base_opcode
& 0xff;
2785 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2786 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2788 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2795 if (flag_code
== CODE_16BIT
)
2799 if (i
.prefix
[DATA_PREFIX
])
2805 if (i
.prefix
[REX_PREFIX
])
2815 if (i
.prefixes
!= 0 && !intel_syntax
)
2816 as_warn (_("skipping prefixes on this instruction"));
2818 /* 1 opcode; 2 segment; offset */
2819 insn_size
+= prefix
+ 1 + 2 + size
;
2820 p
= frag_more (prefix
+ 1 + 2 + size
);
2822 if (i
.prefix
[DATA_PREFIX
])
2823 *p
++ = DATA_PREFIX_OPCODE
;
2825 if (i
.prefix
[REX_PREFIX
])
2826 *p
++ = i
.prefix
[REX_PREFIX
];
2828 *p
++ = i
.tm
.base_opcode
;
2829 if (i
.op
[1].imms
->X_op
== O_constant
)
2831 offsetT n
= i
.op
[1].imms
->X_add_number
;
2834 && !fits_in_unsigned_word (n
)
2835 && !fits_in_signed_word (n
))
2837 as_bad (_("16-bit jump out of range"));
2840 md_number_to_chars (p
, n
, size
);
2843 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2844 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2845 if (i
.op
[0].imms
->X_op
!= O_constant
)
2846 as_bad (_("can't handle non absolute segment in `%s'"),
2848 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2852 /* Output normal instructions here. */
2855 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2856 byte for the SSE instructions to specify prefix they require. */
2857 if (i
.tm
.base_opcode
& 0xff0000)
2858 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2860 /* The prefix bytes. */
2862 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2869 md_number_to_chars (p
, (valueT
) *q
, 1);
2873 /* Now the opcode; be careful about word order here! */
2874 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2877 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2883 /* Put out high byte first: can't use md_number_to_chars! */
2884 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2885 *p
= i
.tm
.base_opcode
& 0xff;
2888 /* Now the modrm byte and sib byte (if present). */
2889 if (i
.tm
.opcode_modifier
& Modrm
)
2893 md_number_to_chars (p
,
2894 (valueT
) (i
.rm
.regmem
<< 0
2898 /* If i.rm.regmem == ESP (4)
2899 && i.rm.mode != (Register mode)
2901 ==> need second modrm byte. */
2902 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2904 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2908 md_number_to_chars (p
,
2909 (valueT
) (i
.sib
.base
<< 0
2911 | i
.sib
.scale
<< 6),
2916 if (i
.disp_operands
)
2918 register unsigned int n
;
2920 for (n
= 0; n
< i
.operands
; n
++)
2922 if (i
.types
[n
] & Disp
)
2924 if (i
.op
[n
].disps
->X_op
== O_constant
)
2930 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2933 if (i
.types
[n
] & Disp8
)
2935 if (i
.types
[n
] & Disp64
)
2938 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2941 p
= frag_more (size
);
2942 md_number_to_chars (p
, val
, size
);
2948 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2950 /* The PC relative address is computed relative
2951 to the instruction boundary, so in case immediate
2952 fields follows, we need to adjust the value. */
2953 if (pcrel
&& i
.imm_operands
)
2956 register unsigned int n1
;
2958 for (n1
= 0; n1
< i
.operands
; n1
++)
2959 if (i
.types
[n1
] & Imm
)
2961 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2964 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2966 if (i
.types
[n1
] & Imm64
)
2971 /* We should find the immediate. */
2972 if (n1
== i
.operands
)
2974 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2977 if (i
.types
[n
] & Disp32S
)
2980 if (i
.types
[n
] & (Disp16
| Disp64
))
2983 if (i
.types
[n
] & Disp64
)
2988 p
= frag_more (size
);
2989 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2990 i
.op
[n
].disps
, pcrel
,
2991 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2997 /* Output immediate. */
3000 register unsigned int n
;
3002 for (n
= 0; n
< i
.operands
; n
++)
3004 if (i
.types
[n
] & Imm
)
3006 if (i
.op
[n
].imms
->X_op
== O_constant
)
3012 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3015 if (i
.types
[n
] & (Imm8
| Imm8S
))
3017 else if (i
.types
[n
] & Imm64
)
3020 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3023 p
= frag_more (size
);
3024 md_number_to_chars (p
, val
, size
);
3028 /* Not absolute_section.
3029 Need a 32-bit fixup (don't support 8bit
3030 non-absolute imms). Try to support other
3032 #ifdef BFD_ASSEMBLER
3033 enum bfd_reloc_code_real reloc_type
;
3040 if ((i
.types
[n
] & (Imm32S
))
3041 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3043 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3046 if (i
.types
[n
] & (Imm8
| Imm8S
))
3048 if (i
.types
[n
] & Imm64
)
3053 p
= frag_more (size
);
3054 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3055 #ifdef BFD_ASSEMBLER
3056 if (reloc_type
== BFD_RELOC_32
3058 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3059 && (i
.op
[n
].imms
->X_op
== O_symbol
3060 || (i
.op
[n
].imms
->X_op
== O_add
3061 && ((symbol_get_value_expression
3062 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3065 /* We don't support dynamic linking on x86-64 yet. */
3066 if (flag_code
== CODE_64BIT
)
3068 reloc_type
= BFD_RELOC_386_GOTPC
;
3069 i
.op
[n
].imms
->X_add_number
+= 3;
3072 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3073 i
.op
[n
].imms
, 0, reloc_type
);
3080 dwarf2_emit_insn (insn_size
);
3087 #endif /* DEBUG386 */
3091 static int i386_immediate
PARAMS ((char *));
3094 i386_immediate (imm_start
)
3097 char *save_input_line_pointer
;
3101 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3103 as_bad (_("only 1 or 2 immediate operands are allowed"));
3107 exp
= &im_expressions
[i
.imm_operands
++];
3108 i
.op
[this_operand
].imms
= exp
;
3110 if (is_space_char (*imm_start
))
3113 save_input_line_pointer
= input_line_pointer
;
3114 input_line_pointer
= imm_start
;
3118 /* We can have operands of the form
3119 <symbol>@GOTOFF+<nnn>
3120 Take the easy way out here and copy everything
3121 into a temporary buffer... */
3124 cp
= strchr (input_line_pointer
, '@');
3131 /* GOT relocations are not supported in 16 bit mode. */
3132 if (flag_code
== CODE_16BIT
)
3133 as_bad (_("GOT relocations not supported in 16 bit mode"));
3135 if (GOT_symbol
== NULL
)
3136 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3138 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3140 if (flag_code
== CODE_64BIT
)
3141 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3143 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3146 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3148 if (flag_code
== CODE_64BIT
)
3149 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3150 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3153 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3155 if (flag_code
== CODE_64BIT
)
3156 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3158 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3161 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3163 if (flag_code
== CODE_64BIT
)
3164 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3166 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3170 as_bad (_("bad reloc specifier in expression"));
3172 /* Replace the relocation token with ' ', so that errors like
3173 foo@GOTOFF1 will be detected. */
3174 first
= cp
- input_line_pointer
;
3175 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3176 memcpy (tmpbuf
, input_line_pointer
, first
);
3177 tmpbuf
[first
] = ' ';
3178 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3179 input_line_pointer
= tmpbuf
;
3184 exp_seg
= expression (exp
);
3187 if (*input_line_pointer
)
3188 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3190 input_line_pointer
= save_input_line_pointer
;
3192 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3194 /* Missing or bad expr becomes absolute 0. */
3195 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3197 exp
->X_op
= O_constant
;
3198 exp
->X_add_number
= 0;
3199 exp
->X_add_symbol
= (symbolS
*) 0;
3200 exp
->X_op_symbol
= (symbolS
*) 0;
3202 else if (exp
->X_op
== O_constant
)
3204 /* Size it properly later. */
3205 i
.types
[this_operand
] |= Imm64
;
3206 /* If BFD64, sign extend val. */
3207 if (!use_rela_relocations
)
3208 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3209 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3211 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3213 #ifdef BFD_ASSEMBLER
3214 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3216 && exp_seg
!= text_section
3217 && exp_seg
!= data_section
3218 && exp_seg
!= bss_section
3219 && exp_seg
!= undefined_section
3220 #ifdef BFD_ASSEMBLER
3221 && !bfd_is_com_section (exp_seg
)
3225 #ifdef BFD_ASSEMBLER
3226 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3228 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3235 /* This is an address. The size of the address will be
3236 determined later, depending on destination register,
3237 suffix, or the default for the section. */
3238 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3244 static int i386_scale
PARAMS ((char *));
3250 if (!isdigit (*scale
))
3257 i
.log2_scale_factor
= 0;
3260 i
.log2_scale_factor
= 1;
3263 i
.log2_scale_factor
= 2;
3266 i
.log2_scale_factor
= 3;
3270 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3274 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3276 as_warn (_("scale factor of %d without an index register"),
3277 1 << i
.log2_scale_factor
);
3278 #if SCALE1_WHEN_NO_INDEX
3279 i
.log2_scale_factor
= 0;
3285 static int i386_displacement
PARAMS ((char *, char *));
3288 i386_displacement (disp_start
, disp_end
)
3292 register expressionS
*exp
;
3294 char *save_input_line_pointer
;
3295 int bigdisp
= Disp32
;
3297 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3299 if (flag_code
== CODE_64BIT
)
3301 i
.types
[this_operand
] |= bigdisp
;
3303 exp
= &disp_expressions
[i
.disp_operands
];
3304 i
.op
[this_operand
].disps
= exp
;
3306 save_input_line_pointer
= input_line_pointer
;
3307 input_line_pointer
= disp_start
;
3308 END_STRING_AND_SAVE (disp_end
);
3310 #ifndef GCC_ASM_O_HACK
3311 #define GCC_ASM_O_HACK 0
3314 END_STRING_AND_SAVE (disp_end
+ 1);
3315 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3316 && displacement_string_end
[-1] == '+')
3318 /* This hack is to avoid a warning when using the "o"
3319 constraint within gcc asm statements.
3322 #define _set_tssldt_desc(n,addr,limit,type) \
3323 __asm__ __volatile__ ( \
3325 "movw %w1,2+%0\n\t" \
3327 "movb %b1,4+%0\n\t" \
3328 "movb %4,5+%0\n\t" \
3329 "movb $0,6+%0\n\t" \
3330 "movb %h1,7+%0\n\t" \
3332 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3334 This works great except that the output assembler ends
3335 up looking a bit weird if it turns out that there is
3336 no offset. You end up producing code that looks like:
3349 So here we provide the missing zero. */
3351 *displacement_string_end
= '0';
3356 /* We can have operands of the form
3357 <symbol>@GOTOFF+<nnn>
3358 Take the easy way out here and copy everything
3359 into a temporary buffer... */
3362 cp
= strchr (input_line_pointer
, '@');
3369 /* GOT relocations are not supported in 16 bit mode. */
3370 if (flag_code
== CODE_16BIT
)
3371 as_bad (_("GOT relocations not supported in 16 bit mode"));
3373 if (GOT_symbol
== NULL
)
3374 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3376 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3378 if (flag_code
== CODE_64BIT
)
3379 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3381 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3384 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3386 if (flag_code
== CODE_64BIT
)
3387 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3388 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3391 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3393 if (flag_code
!= CODE_64BIT
)
3394 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3395 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3398 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3400 if (flag_code
== CODE_64BIT
)
3401 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3403 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3407 as_bad (_("bad reloc specifier in expression"));
3409 /* Replace the relocation token with ' ', so that errors like
3410 foo@GOTOFF1 will be detected. */
3411 first
= cp
- input_line_pointer
;
3412 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3413 memcpy (tmpbuf
, input_line_pointer
, first
);
3414 tmpbuf
[first
] = ' ';
3415 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3416 input_line_pointer
= tmpbuf
;
3421 exp_seg
= expression (exp
);
3423 #ifdef BFD_ASSEMBLER
3424 /* We do this to make sure that the section symbol is in
3425 the symbol table. We will ultimately change the relocation
3426 to be relative to the beginning of the section. */
3427 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3428 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3430 if (S_IS_LOCAL(exp
->X_add_symbol
)
3431 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3432 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3433 assert (exp
->X_op
== O_symbol
);
3434 exp
->X_op
= O_subtract
;
3435 exp
->X_op_symbol
= GOT_symbol
;
3436 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3441 if (*input_line_pointer
)
3442 as_bad (_("ignoring junk `%s' after expression"),
3443 input_line_pointer
);
3445 RESTORE_END_STRING (disp_end
+ 1);
3447 RESTORE_END_STRING (disp_end
);
3448 input_line_pointer
= save_input_line_pointer
;
3450 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3452 /* Missing or bad expr becomes absolute 0. */
3453 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3455 exp
->X_op
= O_constant
;
3456 exp
->X_add_number
= 0;
3457 exp
->X_add_symbol
= (symbolS
*) 0;
3458 exp
->X_op_symbol
= (symbolS
*) 0;
3461 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3462 if (exp
->X_op
!= O_constant
3463 #ifdef BFD_ASSEMBLER
3464 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3466 && exp_seg
!= text_section
3467 && exp_seg
!= data_section
3468 && exp_seg
!= bss_section
3469 && exp_seg
!= undefined_section
)
3471 #ifdef BFD_ASSEMBLER
3472 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3474 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3479 else if (flag_code
== CODE_64BIT
)
3480 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3484 static int i386_index_check
PARAMS((const char *));
3486 /* Make sure the memory operand we've been dealt is valid.
3487 Return 1 on success, 0 on a failure. */
3490 i386_index_check (operand_string
)
3491 const char *operand_string
;
3494 #if INFER_ADDR_PREFIX
3500 if (flag_code
== CODE_64BIT
)
3504 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3505 && (i
.base_reg
->reg_type
!= BaseIndex
3508 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3509 != (Reg64
|BaseIndex
))))
3514 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3518 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3519 != (Reg16
|BaseIndex
)))
3521 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3522 != (Reg16
|BaseIndex
))
3524 && i
.base_reg
->reg_num
< 6
3525 && i
.index_reg
->reg_num
>= 6
3526 && i
.log2_scale_factor
== 0))))
3533 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3535 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3536 != (Reg32
|BaseIndex
))))
3542 #if INFER_ADDR_PREFIX
3543 if (flag_code
!= CODE_64BIT
3544 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3546 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3548 /* Change the size of any displacement too. At most one of
3549 Disp16 or Disp32 is set.
3550 FIXME. There doesn't seem to be any real need for separate
3551 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3552 Removing them would probably clean up the code quite a lot. */
3553 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3554 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3559 as_bad (_("`%s' is not a valid base/index expression"),
3563 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3565 flag_code_names
[flag_code
]);
3571 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3575 i386_operand (operand_string
)
3576 char *operand_string
;
3580 char *op_string
= operand_string
;
3582 if (is_space_char (*op_string
))
3585 /* We check for an absolute prefix (differentiating,
3586 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3587 if (*op_string
== ABSOLUTE_PREFIX
)
3590 if (is_space_char (*op_string
))
3592 i
.types
[this_operand
] |= JumpAbsolute
;
3595 /* Check if operand is a register. */
3596 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3597 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3599 /* Check for a segment override by searching for ':' after a
3600 segment register. */
3602 if (is_space_char (*op_string
))
3604 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3609 i
.seg
[i
.mem_operands
] = &es
;
3612 i
.seg
[i
.mem_operands
] = &cs
;
3615 i
.seg
[i
.mem_operands
] = &ss
;
3618 i
.seg
[i
.mem_operands
] = &ds
;
3621 i
.seg
[i
.mem_operands
] = &fs
;
3624 i
.seg
[i
.mem_operands
] = &gs
;
3628 /* Skip the ':' and whitespace. */
3630 if (is_space_char (*op_string
))
3633 if (!is_digit_char (*op_string
)
3634 && !is_identifier_char (*op_string
)
3635 && *op_string
!= '('
3636 && *op_string
!= ABSOLUTE_PREFIX
)
3638 as_bad (_("bad memory operand `%s'"), op_string
);
3641 /* Handle case of %es:*foo. */
3642 if (*op_string
== ABSOLUTE_PREFIX
)
3645 if (is_space_char (*op_string
))
3647 i
.types
[this_operand
] |= JumpAbsolute
;
3649 goto do_memory_reference
;
3653 as_bad (_("junk `%s' after register"), op_string
);
3656 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3657 i
.op
[this_operand
].regs
= r
;
3660 else if (*op_string
== REGISTER_PREFIX
)
3662 as_bad (_("bad register name `%s'"), op_string
);
3665 else if (*op_string
== IMMEDIATE_PREFIX
)
3668 if (i
.types
[this_operand
] & JumpAbsolute
)
3670 as_bad (_("immediate operand illegal with absolute jump"));
3673 if (!i386_immediate (op_string
))
3676 else if (is_digit_char (*op_string
)
3677 || is_identifier_char (*op_string
)
3678 || *op_string
== '(' )
3680 /* This is a memory reference of some sort. */
3683 /* Start and end of displacement string expression (if found). */
3684 char *displacement_string_start
;
3685 char *displacement_string_end
;
3687 do_memory_reference
:
3688 if ((i
.mem_operands
== 1
3689 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3690 || i
.mem_operands
== 2)
3692 as_bad (_("too many memory references for `%s'"),
3693 current_templates
->start
->name
);
3697 /* Check for base index form. We detect the base index form by
3698 looking for an ')' at the end of the operand, searching
3699 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3701 base_string
= op_string
+ strlen (op_string
);
3704 if (is_space_char (*base_string
))
3707 /* If we only have a displacement, set-up for it to be parsed later. */
3708 displacement_string_start
= op_string
;
3709 displacement_string_end
= base_string
+ 1;
3711 if (*base_string
== ')')
3714 unsigned int parens_balanced
= 1;
3715 /* We've already checked that the number of left & right ()'s are
3716 equal, so this loop will not be infinite. */
3720 if (*base_string
== ')')
3722 if (*base_string
== '(')
3725 while (parens_balanced
);
3727 temp_string
= base_string
;
3729 /* Skip past '(' and whitespace. */
3731 if (is_space_char (*base_string
))
3734 if (*base_string
== ','
3735 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3736 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3738 displacement_string_end
= temp_string
;
3740 i
.types
[this_operand
] |= BaseIndex
;
3744 base_string
= end_op
;
3745 if (is_space_char (*base_string
))
3749 /* There may be an index reg or scale factor here. */
3750 if (*base_string
== ',')
3753 if (is_space_char (*base_string
))
3756 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3757 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3759 base_string
= end_op
;
3760 if (is_space_char (*base_string
))
3762 if (*base_string
== ',')
3765 if (is_space_char (*base_string
))
3768 else if (*base_string
!= ')' )
3770 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3775 else if (*base_string
== REGISTER_PREFIX
)
3777 as_bad (_("bad register name `%s'"), base_string
);
3781 /* Check for scale factor. */
3782 if (isdigit ((unsigned char) *base_string
))
3784 if (!i386_scale (base_string
))
3788 if (is_space_char (*base_string
))
3790 if (*base_string
!= ')')
3792 as_bad (_("expecting `)' after scale factor in `%s'"),
3797 else if (!i
.index_reg
)
3799 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3804 else if (*base_string
!= ')')
3806 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3811 else if (*base_string
== REGISTER_PREFIX
)
3813 as_bad (_("bad register name `%s'"), base_string
);
3818 /* If there's an expression beginning the operand, parse it,
3819 assuming displacement_string_start and
3820 displacement_string_end are meaningful. */
3821 if (displacement_string_start
!= displacement_string_end
)
3823 if (!i386_displacement (displacement_string_start
,
3824 displacement_string_end
))
3828 /* Special case for (%dx) while doing input/output op. */
3830 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3832 && i
.log2_scale_factor
== 0
3833 && i
.seg
[i
.mem_operands
] == 0
3834 && (i
.types
[this_operand
] & Disp
) == 0)
3836 i
.types
[this_operand
] = InOutPortReg
;
3840 if (i386_index_check (operand_string
) == 0)
3846 /* It's not a memory operand; argh! */
3847 as_bad (_("invalid char %s beginning operand %d `%s'"),
3848 output_invalid (*op_string
),
3853 return 1; /* Normal return. */
3856 /* md_estimate_size_before_relax()
3858 Called just before relax() for rs_machine_dependent frags. The x86
3859 assembler uses these frags to handle variable size jump
3862 Any symbol that is now undefined will not become defined.
3863 Return the correct fr_subtype in the frag.
3864 Return the initial "guess for variable size of frag" to caller.
3865 The guess is actually the growth beyond the fixed part. Whatever
3866 we do to grow the fixed or variable part contributes to our
3870 md_estimate_size_before_relax (fragP
, segment
)
3871 register fragS
*fragP
;
3872 register segT segment
;
3874 /* We've already got fragP->fr_subtype right; all we have to do is
3875 check for un-relaxable symbols. On an ELF system, we can't relax
3876 an externally visible symbol, because it may be overridden by a
3878 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3879 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3880 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3881 || S_IS_WEAK (fragP
->fr_symbol
)
3885 /* Symbol is undefined in this segment, or we need to keep a
3886 reloc so that weak symbols can be overridden. */
3887 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3888 #ifdef BFD_ASSEMBLER
3889 enum bfd_reloc_code_real reloc_type
;
3893 unsigned char *opcode
;
3896 if (fragP
->fr_var
!= NO_RELOC
)
3897 reloc_type
= fragP
->fr_var
;
3899 reloc_type
= BFD_RELOC_16_PCREL
;
3901 reloc_type
= BFD_RELOC_32_PCREL
;
3903 old_fr_fix
= fragP
->fr_fix
;
3904 opcode
= (unsigned char *) fragP
->fr_opcode
;
3908 case JUMP_PC_RELATIVE
:
3909 /* Make jmp (0xeb) a dword displacement jump. */
3911 fragP
->fr_fix
+= size
;
3912 fix_new (fragP
, old_fr_fix
, size
,
3914 fragP
->fr_offset
, 1,
3919 /* This changes the byte-displacement jump 0x7N
3920 to the dword-displacement jump 0x0f,0x8N. */
3921 opcode
[1] = opcode
[0] + 0x10;
3922 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3923 /* We've added an opcode byte. */
3924 fragP
->fr_fix
+= 1 + size
;
3925 fix_new (fragP
, old_fr_fix
+ 1, size
,
3927 fragP
->fr_offset
, 1,
3932 return fragP
->fr_fix
- old_fr_fix
;
3934 /* Guess a short jump. */
3938 /* Called after relax() is finished.
3940 In: Address of frag.
3941 fr_type == rs_machine_dependent.
3942 fr_subtype is what the address relaxed to.
3944 Out: Any fixSs and constants are set up.
3945 Caller will turn frag into a ".space 0". */
3947 #ifndef BFD_ASSEMBLER
3949 md_convert_frag (headers
, sec
, fragP
)
3950 object_headers
*headers ATTRIBUTE_UNUSED
;
3951 segT sec ATTRIBUTE_UNUSED
;
3952 register fragS
*fragP
;
3955 md_convert_frag (abfd
, sec
, fragP
)
3956 bfd
*abfd ATTRIBUTE_UNUSED
;
3957 segT sec ATTRIBUTE_UNUSED
;
3958 register fragS
*fragP
;
3961 register unsigned char *opcode
;
3962 unsigned char *where_to_put_displacement
= NULL
;
3963 offsetT target_address
;
3964 offsetT opcode_address
;
3965 unsigned int extension
= 0;
3966 offsetT displacement_from_opcode_start
;
3968 opcode
= (unsigned char *) fragP
->fr_opcode
;
3970 /* Address we want to reach in file space. */
3971 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3972 #ifdef BFD_ASSEMBLER
3973 /* Not needed otherwise? */
3974 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3977 /* Address opcode resides at in file space. */
3978 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3980 /* Displacement from opcode start to fill into instruction. */
3981 displacement_from_opcode_start
= target_address
- opcode_address
;
3983 switch (fragP
->fr_subtype
)
3985 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3986 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3987 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3988 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3989 /* Don't have to change opcode. */
3990 extension
= 1; /* 1 opcode + 1 displacement */
3991 where_to_put_displacement
= &opcode
[1];
3994 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3995 extension
= 5; /* 2 opcode + 4 displacement */
3996 opcode
[1] = opcode
[0] + 0x10;
3997 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3998 where_to_put_displacement
= &opcode
[2];
4001 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4002 extension
= 4; /* 1 opcode + 4 displacement */
4004 where_to_put_displacement
= &opcode
[1];
4007 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4008 extension
= 3; /* 2 opcode + 2 displacement */
4009 opcode
[1] = opcode
[0] + 0x10;
4010 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4011 where_to_put_displacement
= &opcode
[2];
4014 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4015 extension
= 2; /* 1 opcode + 2 displacement */
4017 where_to_put_displacement
= &opcode
[1];
4021 BAD_CASE (fragP
->fr_subtype
);
4024 /* Now put displacement after opcode. */
4025 md_number_to_chars ((char *) where_to_put_displacement
,
4026 (valueT
) (displacement_from_opcode_start
- extension
),
4027 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4028 fragP
->fr_fix
+= extension
;
4031 /* Size of byte displacement jmp. */
4032 int md_short_jump_size
= 2;
4034 /* Size of dword displacement jmp. */
4035 int md_long_jump_size
= 5;
4037 /* Size of relocation record. */
4038 const int md_reloc_size
= 8;
4041 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4043 addressT from_addr
, to_addr
;
4044 fragS
*frag ATTRIBUTE_UNUSED
;
4045 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4049 offset
= to_addr
- (from_addr
+ 2);
4050 /* Opcode for byte-disp jump. */
4051 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4052 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4056 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4058 addressT from_addr
, to_addr
;
4059 fragS
*frag ATTRIBUTE_UNUSED
;
4060 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4064 offset
= to_addr
- (from_addr
+ 5);
4065 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4066 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4069 /* Apply a fixup (fixS) to segment data, once it has been determined
4070 by our caller that we have all the info we need to fix it up.
4072 On the 386, immediates, displacements, and data pointers are all in
4073 the same (little-endian) format, so we don't need to care about which
4077 md_apply_fix3 (fixP
, valp
, seg
)
4078 /* The fix we're to put in. */
4081 /* Pointer to the value of the bits. */
4084 /* Segment fix is from. */
4085 segT seg ATTRIBUTE_UNUSED
;
4087 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4088 valueT value
= *valp
;
4090 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4093 switch (fixP
->fx_r_type
)
4099 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4102 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4105 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4110 /* This is a hack. There should be a better way to handle this.
4111 This covers for the fact that bfd_install_relocation will
4112 subtract the current location (for partial_inplace, PC relative
4113 relocations); see more below. */
4114 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4115 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4116 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4120 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4122 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4125 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4128 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4130 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4133 || (symbol_section_p (fixP
->fx_addsy
)
4134 && fseg
!= absolute_section
))
4135 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4136 && ! S_IS_WEAK (fixP
->fx_addsy
)
4137 && S_IS_DEFINED (fixP
->fx_addsy
)
4138 && ! S_IS_COMMON (fixP
->fx_addsy
))
4140 /* Yes, we add the values in twice. This is because
4141 bfd_perform_relocation subtracts them out again. I think
4142 bfd_perform_relocation is broken, but I don't dare change
4144 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4148 #if defined (OBJ_COFF) && defined (TE_PE)
4149 /* For some reason, the PE format does not store a section
4150 address offset for a PC relative symbol. */
4151 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4152 value
+= md_pcrel_from (fixP
);
4156 /* Fix a few things - the dynamic linker expects certain values here,
4157 and we must not dissappoint it. */
4158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4159 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4161 switch (fixP
->fx_r_type
)
4163 case BFD_RELOC_386_PLT32
:
4164 case BFD_RELOC_X86_64_PLT32
:
4165 /* Make the jump instruction point to the address of the operand. At
4166 runtime we merely add the offset to the actual PLT entry. */
4169 case BFD_RELOC_386_GOTPC
:
4171 /* This is tough to explain. We end up with this one if we have
4172 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4173 * here is to obtain the absolute address of the GOT, and it is strongly
4174 * preferable from a performance point of view to avoid using a runtime
4175 * relocation for this. The actual sequence of instructions often look
4181 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4183 * The call and pop essentially return the absolute address of
4184 * the label .L66 and store it in %ebx. The linker itself will
4185 * ultimately change the first operand of the addl so that %ebx points to
4186 * the GOT, but to keep things simple, the .o file must have this operand
4187 * set so that it generates not the absolute address of .L66, but the
4188 * absolute address of itself. This allows the linker itself simply
4189 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4190 * added in, and the addend of the relocation is stored in the operand
4191 * field for the instruction itself.
4193 * Our job here is to fix the operand so that it would add the correct
4194 * offset so that %ebx would point to itself. The thing that is tricky is
4195 * that .-.L66 will point to the beginning of the instruction, so we need
4196 * to further modify the operand so that it will point to itself.
4197 * There are other cases where you have something like:
4199 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4201 * and here no correction would be required. Internally in the assembler
4202 * we treat operands of this form as not being pcrel since the '.' is
4203 * explicitly mentioned, and I wonder whether it would simplify matters
4204 * to do it this way. Who knows. In earlier versions of the PIC patches,
4205 * the pcrel_adjust field was used to store the correction, but since the
4206 * expression is not pcrel, I felt it would be confusing to do it this
4211 case BFD_RELOC_386_GOT32
:
4212 case BFD_RELOC_X86_64_GOT32
:
4213 value
= 0; /* Fully resolved at runtime. No addend. */
4215 case BFD_RELOC_386_GOTOFF
:
4216 case BFD_RELOC_X86_64_GOTPCREL
:
4219 case BFD_RELOC_VTABLE_INHERIT
:
4220 case BFD_RELOC_VTABLE_ENTRY
:
4227 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4229 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4231 #ifndef BFD_ASSEMBLER
4232 md_number_to_chars (p
, value
, fixP
->fx_size
);
4234 /* Are we finished with this relocation now? */
4235 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4237 else if (use_rela_relocations
)
4239 fixP
->fx_no_overflow
= 1;
4242 md_number_to_chars (p
, value
, fixP
->fx_size
);
4248 #define MAX_LITTLENUMS 6
4250 /* Turn the string pointed to by litP into a floating point constant
4251 of type TYPE, and emit the appropriate bytes. The number of
4252 LITTLENUMS emitted is stored in *SIZEP. An error message is
4253 returned, or NULL on OK. */
4256 md_atof (type
, litP
, sizeP
)
4262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4263 LITTLENUM_TYPE
*wordP
;
4285 return _("Bad call to md_atof ()");
4287 t
= atof_ieee (input_line_pointer
, type
, words
);
4289 input_line_pointer
= t
;
4291 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4292 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4293 the bigendian 386. */
4294 for (wordP
= words
+ prec
- 1; prec
--;)
4296 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4297 litP
+= sizeof (LITTLENUM_TYPE
);
4302 char output_invalid_buf
[8];
4309 sprintf (output_invalid_buf
, "'%c'", c
);
4311 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4312 return output_invalid_buf
;
4315 /* REG_STRING starts *before* REGISTER_PREFIX. */
4317 static const reg_entry
*
4318 parse_register (reg_string
, end_op
)
4322 char *s
= reg_string
;
4324 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4327 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4328 if (*s
== REGISTER_PREFIX
)
4331 if (is_space_char (*s
))
4335 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4337 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4338 return (const reg_entry
*) NULL
;
4342 /* For naked regs, make sure that we are not dealing with an identifier.
4343 This prevents confusing an identifier like `eax_var' with register
4345 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4346 return (const reg_entry
*) NULL
;
4350 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4352 /* Handle floating point regs, allowing spaces in the (i) part. */
4353 if (r
== i386_regtab
/* %st is first entry of table */)
4355 if (is_space_char (*s
))
4360 if (is_space_char (*s
))
4362 if (*s
>= '0' && *s
<= '7')
4364 r
= &i386_float_regtab
[*s
- '0'];
4366 if (is_space_char (*s
))
4374 /* We have "%st(" then garbage. */
4375 return (const reg_entry
*) NULL
;
4382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4383 const char *md_shortopts
= "kVQ:sq";
4385 const char *md_shortopts
= "q";
4388 struct option md_longopts
[] = {
4389 #define OPTION_32 (OPTION_MD_BASE + 0)
4390 {"32", no_argument
, NULL
, OPTION_32
},
4391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4392 #define OPTION_64 (OPTION_MD_BASE + 1)
4393 {"64", no_argument
, NULL
, OPTION_64
},
4395 {NULL
, no_argument
, NULL
, 0}
4397 size_t md_longopts_size
= sizeof (md_longopts
);
4400 md_parse_option (c
, arg
)
4402 char *arg ATTRIBUTE_UNUSED
;
4410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4411 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4412 should be emitted or not. FIXME: Not implemented. */
4416 /* -V: SVR4 argument to print version ID. */
4418 print_version_id ();
4421 /* -k: Ignore for FreeBSD compatibility. */
4426 /* -s: On i386 Solaris, this tells the native assembler to use
4427 .stab instead of .stab.excl. We always use .stab anyhow. */
4432 const char **list
, **l
;
4434 list
= bfd_target_list ();
4435 for (l
= list
; *l
!= NULL
; l
++)
4436 if (strcmp (*l
, "elf64-x86-64") == 0)
4438 default_arch
= "x86_64";
4442 as_fatal (_("No compiled in support for x86_64"));
4449 default_arch
= "i386";
4459 md_show_usage (stream
)
4462 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4463 fprintf (stream
, _("\
4465 -V print assembler version number\n\
4467 -q quieten some warnings\n\
4470 fprintf (stream
, _("\
4471 -q quieten some warnings\n"));
4475 #ifdef BFD_ASSEMBLER
4476 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4477 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4479 /* Pick the target format to use. */
4482 i386_target_format ()
4484 if (!strcmp (default_arch
, "x86_64"))
4485 set_code_flag (CODE_64BIT
);
4486 else if (!strcmp (default_arch
, "i386"))
4487 set_code_flag (CODE_32BIT
);
4489 as_fatal (_("Unknown architecture"));
4490 switch (OUTPUT_FLAVOR
)
4492 #ifdef OBJ_MAYBE_AOUT
4493 case bfd_target_aout_flavour
:
4494 return AOUT_TARGET_FORMAT
;
4496 #ifdef OBJ_MAYBE_COFF
4497 case bfd_target_coff_flavour
:
4500 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4501 case bfd_target_elf_flavour
:
4503 if (flag_code
== CODE_64BIT
)
4504 use_rela_relocations
= 1;
4505 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4514 #endif /* OBJ_MAYBE_ more than one */
4515 #endif /* BFD_ASSEMBLER */
4518 md_undefined_symbol (name
)
4521 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4522 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4523 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4524 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4528 if (symbol_find (name
))
4529 as_bad (_("GOT already in symbol table"));
4530 GOT_symbol
= symbol_new (name
, undefined_section
,
4531 (valueT
) 0, &zero_address_frag
);
4538 /* Round up a section size to the appropriate boundary. */
4541 md_section_align (segment
, size
)
4542 segT segment ATTRIBUTE_UNUSED
;
4545 #ifdef BFD_ASSEMBLER
4546 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4547 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4549 /* For a.out, force the section size to be aligned. If we don't do
4550 this, BFD will align it for us, but it will not write out the
4551 final bytes of the section. This may be a bug in BFD, but it is
4552 easier to fix it here since that is how the other a.out targets
4556 align
= bfd_get_section_alignment (stdoutput
, segment
);
4557 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4565 /* On the i386, PC-relative offsets are relative to the start of the
4566 next instruction. That is, the address of the offset, plus its
4567 size, since the offset is always the last part of the insn. */
4570 md_pcrel_from (fixP
)
4573 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4580 int ignore ATTRIBUTE_UNUSED
;
4584 temp
= get_absolute_expression ();
4585 subseg_set (bss_section
, (subsegT
) temp
);
4586 demand_empty_rest_of_line ();
4591 #ifdef BFD_ASSEMBLER
4594 i386_validate_fix (fixp
)
4597 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4599 /* GOTOFF relocation are nonsense in 64bit mode. */
4600 if (flag_code
== CODE_64BIT
)
4602 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4608 tc_gen_reloc (section
, fixp
)
4609 asection
*section ATTRIBUTE_UNUSED
;
4613 bfd_reloc_code_real_type code
;
4615 switch (fixp
->fx_r_type
)
4617 case BFD_RELOC_X86_64_PLT32
:
4618 case BFD_RELOC_X86_64_GOT32
:
4619 case BFD_RELOC_X86_64_GOTPCREL
:
4620 case BFD_RELOC_386_PLT32
:
4621 case BFD_RELOC_386_GOT32
:
4622 case BFD_RELOC_386_GOTOFF
:
4623 case BFD_RELOC_386_GOTPC
:
4624 case BFD_RELOC_X86_64_32S
:
4626 case BFD_RELOC_VTABLE_ENTRY
:
4627 case BFD_RELOC_VTABLE_INHERIT
:
4628 code
= fixp
->fx_r_type
;
4633 switch (fixp
->fx_size
)
4636 as_bad (_("can not do %d byte pc-relative relocation"),
4638 code
= BFD_RELOC_32_PCREL
;
4640 case 1: code
= BFD_RELOC_8_PCREL
; break;
4641 case 2: code
= BFD_RELOC_16_PCREL
; break;
4642 case 4: code
= BFD_RELOC_32_PCREL
; break;
4647 switch (fixp
->fx_size
)
4650 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4651 code
= BFD_RELOC_32
;
4653 case 1: code
= BFD_RELOC_8
; break;
4654 case 2: code
= BFD_RELOC_16
; break;
4655 case 4: code
= BFD_RELOC_32
; break;
4656 case 8: code
= BFD_RELOC_64
; break;
4662 if (code
== BFD_RELOC_32
4664 && fixp
->fx_addsy
== GOT_symbol
)
4666 /* We don't support GOTPC on 64bit targets. */
4667 if (flag_code
== CODE_64BIT
)
4669 code
= BFD_RELOC_386_GOTPC
;
4672 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4673 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4674 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4676 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4677 if (!use_rela_relocations
)
4679 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4680 vtable entry to be used in the relocation's section offset. */
4681 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4682 rel
->address
= fixp
->fx_offset
;
4685 rel
->addend
= fixp
->fx_addnumber
;
4689 /* Use the rela in 64bit mode. */
4692 rel
->addend
= fixp
->fx_offset
;
4694 /* Ohhh, this is ugly. The problem is that if this is a local global
4695 symbol, the relocation will entirely be performed at link time, not
4696 at assembly time. bfd_perform_reloc doesn't know about this sort
4697 of thing, and as a result we need to fake it out here. */
4698 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4699 && !S_IS_COMMON(fixp
->fx_addsy
))
4700 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4703 rel
->addend
-= fixp
->fx_size
;
4706 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4707 if (rel
->howto
== NULL
)
4709 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4710 _("cannot represent relocation type %s"),
4711 bfd_get_reloc_code_name (code
));
4712 /* Set howto to a garbage value so that we can keep going. */
4713 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4714 assert (rel
->howto
!= NULL
);
4720 #else /* ! BFD_ASSEMBLER */
4722 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4724 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4727 relax_addressT segment_address_in_file
;
4729 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4730 Out: GNU LD relocation length code: 0, 1, or 2. */
4732 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4735 know (fixP
->fx_addsy
!= NULL
);
4737 md_number_to_chars (where
,
4738 (valueT
) (fixP
->fx_frag
->fr_address
4739 + fixP
->fx_where
- segment_address_in_file
),
4742 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4743 ? S_GET_TYPE (fixP
->fx_addsy
)
4744 : fixP
->fx_addsy
->sy_number
);
4746 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4747 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4748 where
[4] = r_symbolnum
& 0x0ff;
4749 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4750 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4751 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4754 #endif /* OBJ_AOUT or OBJ_BOUT. */
4756 #if defined (I386COFF)
4759 tc_coff_fix2rtype (fixP
)
4762 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4765 return (fixP
->fx_pcrel
?
4766 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4767 fixP
->fx_size
== 2 ? R_PCRWORD
:
4769 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4770 fixP
->fx_size
== 2 ? R_RELWORD
:
4775 tc_coff_sizemachdep (frag
)
4779 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4784 #endif /* I386COFF */
4786 #endif /* ! BFD_ASSEMBLER */
4788 /* Parse operands using Intel syntax. This implements a recursive descent
4789 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4792 FIXME: We do not recognize the full operand grammar defined in the MASM
4793 documentation. In particular, all the structure/union and
4794 high-level macro operands are missing.
4796 Uppercase words are terminals, lower case words are non-terminals.
4797 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4798 bars '|' denote choices. Most grammar productions are implemented in
4799 functions called 'intel_<production>'.
4801 Initial production is 'expr'.
4807 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4809 constant digits [[ radixOverride ]]
4811 dataType BYTE | WORD | DWORD | QWORD | XWORD
4844 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4845 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4847 hexdigit a | b | c | d | e | f
4848 | A | B | C | D | E | F
4858 register specialRegister
4862 segmentRegister CS | DS | ES | FS | GS | SS
4864 specialRegister CR0 | CR2 | CR3
4865 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4866 | TR3 | TR4 | TR5 | TR6 | TR7
4868 We simplify the grammar in obvious places (e.g., register parsing is
4869 done by calling parse_register) and eliminate immediate left recursion
4870 to implement a recursive-descent parser.
4910 /* Parsing structure for the intel syntax parser. Used to implement the
4911 semantic actions for the operand grammar. */
4912 struct intel_parser_s
4914 char *op_string
; /* The string being parsed. */
4915 int got_a_float
; /* Whether the operand is a float. */
4916 int op_modifier
; /* Operand modifier. */
4917 int is_mem
; /* 1 if operand is memory reference. */
4918 const reg_entry
*reg
; /* Last register reference found. */
4919 char *disp
; /* Displacement string being built. */
4922 static struct intel_parser_s intel_parser
;
4924 /* Token structure for parsing intel syntax. */
4927 int code
; /* Token code. */
4928 const reg_entry
*reg
; /* Register entry for register tokens. */
4929 char *str
; /* String representation. */
4932 static struct intel_token cur_token
, prev_token
;
4934 /* Token codes for the intel parser. Since T_SHORT is already used
4935 by COFF, undefine it first to prevent a warning. */
4950 /* Prototypes for intel parser functions. */
4951 static int intel_match_token
PARAMS ((int code
));
4952 static void intel_get_token
PARAMS ((void));
4953 static void intel_putback_token
PARAMS ((void));
4954 static int intel_expr
PARAMS ((void));
4955 static int intel_e05
PARAMS ((void));
4956 static int intel_e05_1
PARAMS ((void));
4957 static int intel_e06
PARAMS ((void));
4958 static int intel_e06_1
PARAMS ((void));
4959 static int intel_e09
PARAMS ((void));
4960 static int intel_e09_1
PARAMS ((void));
4961 static int intel_e10
PARAMS ((void));
4962 static int intel_e10_1
PARAMS ((void));
4963 static int intel_e11
PARAMS ((void));
4966 i386_intel_operand (operand_string
, got_a_float
)
4967 char *operand_string
;
4973 /* Initialize token holders. */
4974 cur_token
.code
= prev_token
.code
= T_NIL
;
4975 cur_token
.reg
= prev_token
.reg
= NULL
;
4976 cur_token
.str
= prev_token
.str
= NULL
;
4978 /* Initialize parser structure. */
4979 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4982 strcpy (intel_parser
.op_string
, operand_string
);
4983 intel_parser
.got_a_float
= got_a_float
;
4984 intel_parser
.op_modifier
= -1;
4985 intel_parser
.is_mem
= 0;
4986 intel_parser
.reg
= NULL
;
4987 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4988 if (intel_parser
.disp
== NULL
)
4990 intel_parser
.disp
[0] = '\0';
4992 /* Read the first token and start the parser. */
4994 ret
= intel_expr ();
4998 /* If we found a memory reference, hand it over to i386_displacement
4999 to fill in the rest of the operand fields. */
5000 if (intel_parser
.is_mem
)
5002 if ((i
.mem_operands
== 1
5003 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5004 || i
.mem_operands
== 2)
5006 as_bad (_("too many memory references for '%s'"),
5007 current_templates
->start
->name
);
5012 char *s
= intel_parser
.disp
;
5015 /* Add the displacement expression. */
5017 ret
= i386_displacement (s
, s
+ strlen (s
))
5018 && i386_index_check (s
);
5022 /* Constant and OFFSET expressions are handled by i386_immediate. */
5023 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5024 || intel_parser
.reg
== NULL
)
5025 ret
= i386_immediate (intel_parser
.disp
);
5029 free (intel_parser
.disp
);
5039 /* expr SHORT e05 */
5040 if (cur_token
.code
== T_SHORT
)
5042 intel_parser
.op_modifier
= SHORT
;
5043 intel_match_token (T_SHORT
);
5045 return (intel_e05 ());
5050 return intel_e05 ();
5060 return (intel_e06 () && intel_e05_1 ());
5066 /* e05' addOp e06 e05' */
5067 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5069 strcat (intel_parser
.disp
, cur_token
.str
);
5070 intel_match_token (cur_token
.code
);
5072 return (intel_e06 () && intel_e05_1 ());
5087 return (intel_e09 () && intel_e06_1 ());
5093 /* e06' mulOp e09 e06' */
5094 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5096 strcat (intel_parser
.disp
, cur_token
.str
);
5097 intel_match_token (cur_token
.code
);
5099 return (intel_e09 () && intel_e06_1 ());
5107 /* e09 OFFSET e10 e09'
5116 /* e09 OFFSET e10 e09' */
5117 if (cur_token
.code
== T_OFFSET
)
5119 intel_parser
.is_mem
= 0;
5120 intel_parser
.op_modifier
= OFFSET_FLAT
;
5121 intel_match_token (T_OFFSET
);
5123 return (intel_e10 () && intel_e09_1 ());
5128 return (intel_e10 () && intel_e09_1 ());
5134 /* e09' PTR e10 e09' */
5135 if (cur_token
.code
== T_PTR
)
5137 if (prev_token
.code
== T_BYTE
)
5138 i
.suffix
= BYTE_MNEM_SUFFIX
;
5140 else if (prev_token
.code
== T_WORD
)
5142 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5143 i
.suffix
= SHORT_MNEM_SUFFIX
;
5145 i
.suffix
= WORD_MNEM_SUFFIX
;
5148 else if (prev_token
.code
== T_DWORD
)
5150 if (intel_parser
.got_a_float
== 1) /* "f..." */
5151 i
.suffix
= SHORT_MNEM_SUFFIX
;
5153 i
.suffix
= LONG_MNEM_SUFFIX
;
5156 else if (prev_token
.code
== T_QWORD
)
5158 if (intel_parser
.got_a_float
== 1) /* "f..." */
5159 i
.suffix
= LONG_MNEM_SUFFIX
;
5161 i
.suffix
= QWORD_MNEM_SUFFIX
;
5164 else if (prev_token
.code
== T_XWORD
)
5165 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5169 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5173 intel_match_token (T_PTR
);
5175 return (intel_e10 () && intel_e09_1 ());
5178 /* e09 : e10 e09' */
5179 else if (cur_token
.code
== ':')
5181 /* Mark as a memory operand only if it's not already known to be an
5182 offset expression. */
5183 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5184 intel_parser
.is_mem
= 1;
5186 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5201 return (intel_e11 () && intel_e10_1 ());
5207 /* e10' [ expr ] e10' */
5208 if (cur_token
.code
== '[')
5210 intel_match_token ('[');
5212 /* Mark as a memory operand only if it's not already known to be an
5213 offset expression. If it's an offset expression, we need to keep
5215 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5216 intel_parser
.is_mem
= 1;
5218 strcat (intel_parser
.disp
, "[");
5220 /* Add a '+' to the displacement string if necessary. */
5221 if (*intel_parser
.disp
!= '\0'
5222 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5223 strcat (intel_parser
.disp
, "+");
5225 if (intel_expr () && intel_match_token (']'))
5227 /* Preserve brackets when the operand is an offset expression. */
5228 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5229 strcat (intel_parser
.disp
, "]");
5231 return intel_e10_1 ();
5258 if (cur_token
.code
== '(')
5260 intel_match_token ('(');
5261 strcat (intel_parser
.disp
, "(");
5263 if (intel_expr () && intel_match_token (')'))
5265 strcat (intel_parser
.disp
, ")");
5273 else if (cur_token
.code
== '[')
5275 intel_match_token ('[');
5277 /* Mark as a memory operand only if it's not already known to be an
5278 offset expression. If it's an offset expression, we need to keep
5280 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5281 intel_parser
.is_mem
= 1;
5283 strcat (intel_parser
.disp
, "[");
5285 /* Operands for jump/call inside brackets denote absolute addresses. */
5286 if (current_templates
->start
->opcode_modifier
& Jump
5287 || current_templates
->start
->opcode_modifier
& JumpDword
5288 || current_templates
->start
->opcode_modifier
& JumpByte
5289 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5290 i
.types
[this_operand
] |= JumpAbsolute
;
5292 /* Add a '+' to the displacement string if necessary. */
5293 if (*intel_parser
.disp
!= '\0'
5294 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5295 strcat (intel_parser
.disp
, "+");
5297 if (intel_expr () && intel_match_token (']'))
5299 /* Preserve brackets when the operand is an offset expression. */
5300 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5301 strcat (intel_parser
.disp
, "]");
5314 else if (cur_token
.code
== T_BYTE
5315 || cur_token
.code
== T_WORD
5316 || cur_token
.code
== T_DWORD
5317 || cur_token
.code
== T_QWORD
5318 || cur_token
.code
== T_XWORD
)
5320 intel_match_token (cur_token
.code
);
5327 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5329 strcat (intel_parser
.disp
, cur_token
.str
);
5330 intel_match_token (cur_token
.code
);
5332 /* Mark as a memory operand only if it's not already known to be an
5333 offset expression. */
5334 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5335 intel_parser
.is_mem
= 1;
5341 else if (cur_token
.code
== T_REG
)
5343 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5345 intel_match_token (T_REG
);
5347 /* Check for segment change. */
5348 if (cur_token
.code
== ':')
5350 if (reg
->reg_type
& (SReg2
| SReg3
))
5352 switch (reg
->reg_num
)
5355 i
.seg
[i
.mem_operands
] = &es
;
5358 i
.seg
[i
.mem_operands
] = &cs
;
5361 i
.seg
[i
.mem_operands
] = &ss
;
5364 i
.seg
[i
.mem_operands
] = &ds
;
5367 i
.seg
[i
.mem_operands
] = &fs
;
5370 i
.seg
[i
.mem_operands
] = &gs
;
5376 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5381 /* Not a segment register. Check for register scaling. */
5382 else if (cur_token
.code
== '*')
5384 if (!intel_parser
.is_mem
)
5386 as_bad (_("Register scaling only allowed in memory operands."));
5390 /* What follows must be a valid scale. */
5391 if (intel_match_token ('*')
5392 && strchr ("01248", *cur_token
.str
))
5395 i
.types
[this_operand
] |= BaseIndex
;
5397 /* Set the scale after setting the register (otherwise,
5398 i386_scale will complain) */
5399 i386_scale (cur_token
.str
);
5400 intel_match_token (T_CONST
);
5404 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5410 /* No scaling. If this is a memory operand, the register is either a
5411 base register (first occurrence) or an index register (second
5413 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5415 if (i
.base_reg
&& i
.index_reg
)
5417 as_bad (_("Too many register references in memory operand.\n"));
5421 if (i
.base_reg
== NULL
)
5426 i
.types
[this_operand
] |= BaseIndex
;
5429 /* Offset modifier. Add the register to the displacement string to be
5430 parsed as an immediate expression after we're done. */
5431 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5432 strcat (intel_parser
.disp
, reg
->reg_name
);
5434 /* It's neither base nor index nor offset. */
5437 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5438 i
.op
[this_operand
].regs
= reg
;
5442 /* Since registers are not part of the displacement string (except
5443 when we're parsing offset operands), we may need to remove any
5444 preceding '+' from the displacement string. */
5445 if (*intel_parser
.disp
!= '\0'
5446 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5448 char *s
= intel_parser
.disp
;
5449 s
+= strlen (s
) - 1;
5458 else if (cur_token
.code
== T_ID
)
5460 /* Add the identifier to the displacement string. */
5461 strcat (intel_parser
.disp
, cur_token
.str
);
5462 intel_match_token (T_ID
);
5464 /* The identifier represents a memory reference only if it's not
5465 preceded by an offset modifier. */
5466 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5467 intel_parser
.is_mem
= 1;
5473 else if (cur_token
.code
== T_CONST
5474 || cur_token
.code
== '-'
5475 || cur_token
.code
== '+')
5479 /* Allow constants that start with `+' or `-'. */
5480 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5482 strcat (intel_parser
.disp
, cur_token
.str
);
5483 intel_match_token (cur_token
.code
);
5484 if (cur_token
.code
!= T_CONST
)
5486 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5492 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5493 if (save_str
== NULL
)
5495 strcpy (save_str
, cur_token
.str
);
5497 /* Get the next token to check for register scaling. */
5498 intel_match_token (cur_token
.code
);
5500 /* Check if this constant is a scaling factor for an index register. */
5501 if (cur_token
.code
== '*')
5503 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5505 if (!intel_parser
.is_mem
)
5507 as_bad (_("Register scaling only allowed in memory operands."));
5511 /* The constant is followed by `* reg', so it must be
5513 if (strchr ("01248", *save_str
))
5515 i
.index_reg
= cur_token
.reg
;
5516 i
.types
[this_operand
] |= BaseIndex
;
5518 /* Set the scale after setting the register (otherwise,
5519 i386_scale will complain) */
5520 i386_scale (save_str
);
5521 intel_match_token (T_REG
);
5523 /* Since registers are not part of the displacement
5524 string, we may need to remove any preceding '+' from
5525 the displacement string. */
5526 if (*intel_parser
.disp
!= '\0')
5528 char *s
= intel_parser
.disp
;
5529 s
+= strlen (s
) - 1;
5542 /* The constant was not used for register scaling. Since we have
5543 already consumed the token following `*' we now need to put it
5544 back in the stream. */
5546 intel_putback_token ();
5549 /* Add the constant to the displacement string. */
5550 strcat (intel_parser
.disp
, save_str
);
5556 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5560 /* Match the given token against cur_token. If they match, read the next
5561 token from the operand string. */
5563 intel_match_token (code
)
5566 if (cur_token
.code
== code
)
5573 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5578 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5583 const reg_entry
*reg
;
5584 struct intel_token new_token
;
5586 new_token
.code
= T_NIL
;
5587 new_token
.reg
= NULL
;
5588 new_token
.str
= NULL
;
5590 /* Free the memory allocated to the previous token and move
5591 cur_token to prev_token. */
5593 free (prev_token
.str
);
5595 prev_token
= cur_token
;
5597 /* Skip whitespace. */
5598 while (is_space_char (*intel_parser
.op_string
))
5599 intel_parser
.op_string
++;
5601 /* Return an empty token if we find nothing else on the line. */
5602 if (*intel_parser
.op_string
== '\0')
5604 cur_token
= new_token
;
5608 /* The new token cannot be larger than the remainder of the operand
5610 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5611 if (new_token
.str
== NULL
)
5613 new_token
.str
[0] = '\0';
5615 if (strchr ("0123456789", *intel_parser
.op_string
))
5617 char *p
= new_token
.str
;
5618 char *q
= intel_parser
.op_string
;
5619 new_token
.code
= T_CONST
;
5621 /* Allow any kind of identifier char to encompass floating point and
5622 hexadecimal numbers. */
5623 while (is_identifier_char (*q
))
5627 /* Recognize special symbol names [0-9][bf]. */
5628 if (strlen (intel_parser
.op_string
) == 2
5629 && (intel_parser
.op_string
[1] == 'b'
5630 || intel_parser
.op_string
[1] == 'f'))
5631 new_token
.code
= T_ID
;
5634 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5636 new_token
.code
= *intel_parser
.op_string
;
5637 new_token
.str
[0] = *intel_parser
.op_string
;
5638 new_token
.str
[1] = '\0';
5641 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5642 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5644 new_token
.code
= T_REG
;
5645 new_token
.reg
= reg
;
5647 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5649 new_token
.str
[0] = REGISTER_PREFIX
;
5650 new_token
.str
[1] = '\0';
5653 strcat (new_token
.str
, reg
->reg_name
);
5656 else if (is_identifier_char (*intel_parser
.op_string
))
5658 char *p
= new_token
.str
;
5659 char *q
= intel_parser
.op_string
;
5661 /* A '.' or '$' followed by an identifier char is an identifier.
5662 Otherwise, it's operator '.' followed by an expression. */
5663 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5665 new_token
.code
= *q
;
5666 new_token
.str
[0] = *q
;
5667 new_token
.str
[1] = '\0';
5671 while (is_identifier_char (*q
) || *q
== '@')
5675 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5676 new_token
.code
= T_BYTE
;
5678 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5679 new_token
.code
= T_WORD
;
5681 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5682 new_token
.code
= T_DWORD
;
5684 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5685 new_token
.code
= T_QWORD
;
5687 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5688 new_token
.code
= T_XWORD
;
5690 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5691 new_token
.code
= T_PTR
;
5693 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5694 new_token
.code
= T_SHORT
;
5696 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5698 new_token
.code
= T_OFFSET
;
5700 /* ??? This is not mentioned in the MASM grammar but gcc
5701 makes use of it with -mintel-syntax. OFFSET may be
5702 followed by FLAT: */
5703 if (strncasecmp (q
, " FLAT:", 6) == 0)
5704 strcat (new_token
.str
, " FLAT:");
5707 /* ??? This is not mentioned in the MASM grammar. */
5708 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5709 new_token
.code
= T_OFFSET
;
5712 new_token
.code
= T_ID
;
5717 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5719 intel_parser
.op_string
+= strlen (new_token
.str
);
5720 cur_token
= new_token
;
5723 /* Put cur_token back into the token stream and make cur_token point to
5726 intel_putback_token ()
5728 intel_parser
.op_string
-= strlen (cur_token
.str
);
5729 free (cur_token
.str
);
5730 cur_token
= prev_token
;
5732 /* Forget prev_token. */
5733 prev_token
.code
= T_NIL
;
5734 prev_token
.reg
= NULL
;
5735 prev_token
.str
= NULL
;