1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags enable
; /* cpu feature enable flags */
135 i386_cpu_flags disable
; /* cpu feature disable flags */
139 static void update_code_flag (int, int);
140 static void s_insn (int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
150 static void pe_directive_secidx (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static const char *parse_insn (const char *, char *, bool);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (unsigned int, unsigned int);
167 static enum flag_code
i386_addressing_mode (void);
168 static void optimize_imm (void);
169 static bool optimize_disp (const insn_template
*t
);
170 static const insn_template
*match_template (char);
171 static int check_string (void);
172 static int process_suffix (void);
173 static int check_byte_reg (void);
174 static int check_long_reg (void);
175 static int check_qword_reg (void);
176 static int check_word_reg (void);
177 static int finalize_imm (void);
178 static int process_operands (void);
179 static const reg_entry
*build_modrm_byte (void);
180 static void output_insn (void);
181 static void output_imm (fragS
*, offsetT
);
182 static void output_disp (fragS
*, offsetT
);
184 static void s_bss (int);
186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
187 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 /* GNU_PROPERTY_X86_ISA_1_USED. */
190 static unsigned int x86_isa_1_used
;
191 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
192 static unsigned int x86_feature_2_used
;
193 /* Generate x86 used ISA and feature properties. */
194 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
197 static const char *default_arch
= DEFAULT_ARCH
;
199 /* parse_register() returns this when a register alias cannot be used. */
200 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
201 { Dw2Inval
, Dw2Inval
} };
203 static const reg_entry
*reg_eax
;
204 static const reg_entry
*reg_ds
;
205 static const reg_entry
*reg_es
;
206 static const reg_entry
*reg_ss
;
207 static const reg_entry
*reg_st0
;
208 static const reg_entry
*reg_k0
;
213 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
214 unsigned char bytes
[4];
216 /* Destination or source register specifier. */
217 const reg_entry
*register_specifier
;
220 /* 'md_assemble ()' gathers together information and puts it into a
227 const reg_entry
*regs
;
232 no_error
, /* Must be first. */
233 operand_size_mismatch
,
234 operand_type_mismatch
,
235 register_type_mismatch
,
236 number_of_operands_mismatch
,
237 invalid_instruction_suffix
,
239 unsupported_with_intel_mnemonic
,
245 invalid_vsib_address
,
246 invalid_vector_register_set
,
247 invalid_tmm_register_set
,
248 invalid_dest_and_src_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 invalid_register_operand
,
261 /* TM holds the template for the insn were currently assembling. */
264 /* SUFFIX holds the instruction size suffix for byte, word, dword
265 or qword, if given. */
268 /* OPCODE_LENGTH holds the number of base opcode bytes. */
269 unsigned char opcode_length
;
271 /* OPERANDS gives the number of given operands. */
272 unsigned int operands
;
274 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
275 of given register, displacement, memory operands and immediate
277 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
279 /* TYPES [i] is the type (see above #defines) which tells us how to
280 use OP[i] for the corresponding operand. */
281 i386_operand_type types
[MAX_OPERANDS
];
283 /* Displacement expression, immediate expression, or register for each
285 union i386_op op
[MAX_OPERANDS
];
287 /* Flags for operands. */
288 unsigned int flags
[MAX_OPERANDS
];
289 #define Operand_PCrel 1
290 #define Operand_Mem 2
292 /* Relocation type for operand */
293 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
295 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
296 the base index byte below. */
297 const reg_entry
*base_reg
;
298 const reg_entry
*index_reg
;
299 unsigned int log2_scale_factor
;
301 /* SEG gives the seg_entries of this insn. They are zero unless
302 explicit segment overrides are given. */
303 const reg_entry
*seg
[2];
305 /* PREFIX holds all the given prefix opcodes (usually null).
306 PREFIXES is the number of prefix opcodes. */
307 unsigned int prefixes
;
308 unsigned char prefix
[MAX_PREFIXES
];
310 /* .insn allows for reserved opcode spaces. */
311 unsigned char insn_opcode_space
;
313 /* Register is in low 3 bits of opcode. */
316 /* The operand to a branch insn indicates an absolute branch. */
319 /* The operand to a branch insn indicates a far branch. */
322 /* There is a memory operand of (%dx) which should be only used
323 with input/output instructions. */
324 bool input_output_operand
;
326 /* Extended states. */
334 xstate_ymm
= 1 << 2 | xstate_xmm
,
336 xstate_zmm
= 1 << 3 | xstate_ymm
,
339 /* Use MASK state. */
343 /* Has GOTPC or TLS relocation. */
344 bool has_gotpc_tls_reloc
;
346 /* RM and SIB are the modrm byte and the sib byte where the
347 addressing modes of this insn are encoded. */
354 /* Masking attributes.
356 The struct describes masking, applied to OPERAND in the instruction.
357 REG is a pointer to the corresponding mask register. ZEROING tells
358 whether merging or zeroing mask is used. */
359 struct Mask_Operation
361 const reg_entry
*reg
;
362 unsigned int zeroing
;
363 /* The operand where this operation is associated. */
364 unsigned int operand
;
367 /* Rounding control and SAE attributes. */
379 /* In Intel syntax the operand modifier form is supposed to be used, but
380 we continue to accept the immediate forms as well. */
384 /* Broadcasting attributes.
386 The struct describes broadcasting, applied to OPERAND. TYPE is
387 expresses the broadcast factor. */
388 struct Broadcast_Operation
390 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
393 /* Index of broadcasted operand. */
394 unsigned int operand
;
396 /* Number of bytes to broadcast. */
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift
;
403 /* Prefer load or store in encoding. */
406 dir_encoding_default
= 0,
412 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
415 disp_encoding_default
= 0,
421 /* Prefer the REX byte in encoding. */
424 /* Disable instruction size optimization. */
427 /* How to encode vector instructions. */
430 vex_encoding_default
= 0,
438 const char *rep_prefix
;
441 const char *hle_prefix
;
443 /* Have BND prefix. */
444 const char *bnd_prefix
;
446 /* Have NOTRACK prefix. */
447 const char *notrack_prefix
;
450 enum i386_error error
;
453 typedef struct _i386_insn i386_insn
;
455 /* Link RC type with corresponding string, that'll be looked for in
464 static const struct RC_name RC_NamesTable
[] =
466 { rne
, STRING_COMMA_LEN ("rn-sae") },
467 { rd
, STRING_COMMA_LEN ("rd-sae") },
468 { ru
, STRING_COMMA_LEN ("ru-sae") },
469 { rz
, STRING_COMMA_LEN ("rz-sae") },
470 { saeonly
, STRING_COMMA_LEN ("sae") },
473 /* To be indexed by segment register number. */
474 static const unsigned char i386_seg_prefixes
[] = {
483 /* List of chars besides those in app.c:symbol_chars that can start an
484 operand. Used to prevent the scrubber eating vital white-space. */
485 const char extra_symbol_chars
[] = "*%-([{}"
494 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
495 && !defined (TE_GNU) \
496 && !defined (TE_LINUX) \
497 && !defined (TE_Haiku) \
498 && !defined (TE_FreeBSD) \
499 && !defined (TE_DragonFly) \
500 && !defined (TE_NetBSD))
501 /* This array holds the chars that always start a comment. If the
502 pre-processor is disabled, these aren't very useful. The option
503 --divide will remove '/' from this list. */
504 const char *i386_comment_chars
= "#/";
505 #define SVR4_COMMENT_CHARS 1
506 #define PREFIX_SEPARATOR '\\'
509 const char *i386_comment_chars
= "#";
510 #define PREFIX_SEPARATOR '/'
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output.
516 Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output.
519 Also note that comments started like this one will always work if
520 '/' isn't otherwise defined. */
521 const char line_comment_chars
[] = "#/";
523 const char line_separator_chars
[] = ";";
525 /* Chars that can be used to separate mant from exp in floating point
527 const char EXP_CHARS
[] = "eE";
529 /* Chars that mean this number is a floating point constant
532 const char FLT_CHARS
[] = "fFdDxXhHbB";
534 /* Tables for lexical analysis. */
535 static char mnemonic_chars
[256];
536 static char register_chars
[256];
537 static char operand_chars
[256];
539 /* Lexical macros. */
540 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
541 #define is_operand_char(x) (operand_chars[(unsigned char) x])
542 #define is_register_char(x) (register_chars[(unsigned char) x])
543 #define is_space_char(x) ((x) == ' ')
545 /* All non-digit non-letter characters that may occur in an operand. */
546 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
548 /* md_assemble() always leaves the strings it's passed unaltered. To
549 effect this we maintain a stack of saved characters that we've smashed
550 with '\0's (indicating end of strings for various sub-fields of the
551 assembler instruction). */
552 static char save_stack
[32];
553 static char *save_stack_p
;
554 #define END_STRING_AND_SAVE(s) \
555 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
556 #define RESTORE_END_STRING(s) \
557 do { *(s) = *--save_stack_p; } while (0)
559 /* The instruction we're assembling. */
562 /* Possible templates for current insn. */
563 static const templates
*current_templates
;
565 /* Per instruction expressionS buffers: max displacements & immediates. */
566 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
567 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
569 /* Current operand we are working on. */
570 static int this_operand
= -1;
572 /* Are we processing a .insn directive? */
573 #define dot_insn() (i.tm.mnem_off == MN__insn)
575 /* We support four different modes. FLAG_CODE variable is used to distinguish
583 static enum flag_code flag_code
;
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* If we have selected a cpu we are generating instructions for. */
808 static int cpu_arch_tune_set
= 0;
810 /* Cpu we are generating instructions for. */
811 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
813 /* CPU feature flags of cpu we are generating instructions for. */
814 static i386_cpu_flags cpu_arch_tune_flags
;
816 /* CPU instruction set architecture used. */
817 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of instruction set architecture used. */
820 i386_cpu_flags cpu_arch_isa_flags
;
822 /* If set, conditional jumps are not automatically promoted to handle
823 larger than a byte offset. */
824 static bool no_cond_jump_promotion
= false;
826 /* Encode SSE instructions with VEX prefix. */
827 static unsigned int sse2avx
;
829 /* Encode aligned vector move as unaligned vector move. */
830 static unsigned int use_unaligned_vector_move
;
832 /* Encode scalar AVX instructions with specific vector length. */
839 /* Encode VEX WIG instructions with specific vex.w. */
846 /* Encode scalar EVEX LIG instructions with specific vector length. */
854 /* Encode EVEX WIG instructions with specific evex.w. */
861 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
862 static enum rc_type evexrcig
= rne
;
864 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
865 static symbolS
*GOT_symbol
;
867 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
868 unsigned int x86_dwarf2_return_column
;
870 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
871 int x86_cie_data_alignment
;
873 /* Interface to relax_segment.
874 There are 3 major relax states for 386 jump insns because the
875 different types of jumps add different sizes to frags when we're
876 figuring out what sort of jump to choose to reach a given label.
878 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
879 branches which are handled by md_estimate_size_before_relax() and
880 i386_generic_table_relax_frag(). */
883 #define UNCOND_JUMP 0
885 #define COND_JUMP86 2
886 #define BRANCH_PADDING 3
887 #define BRANCH_PREFIX 4
888 #define FUSED_JCC_PADDING 5
893 #define SMALL16 (SMALL | CODE16)
895 #define BIG16 (BIG | CODE16)
899 #define INLINE __inline__
905 #define ENCODE_RELAX_STATE(type, size) \
906 ((relax_substateT) (((type) << 2) | (size)))
907 #define TYPE_FROM_RELAX_STATE(s) \
909 #define DISP_SIZE_FROM_RELAX_STATE(s) \
910 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
912 /* This table is used by relax_frag to promote short jumps to long
913 ones where necessary. SMALL (short) jumps may be promoted to BIG
914 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
915 don't allow a short jump in a 32 bit code segment to be promoted to
916 a 16 bit offset jump because it's slower (requires data size
917 prefix), and doesn't work, unless the destination is in the bottom
918 64k of the code segment (The top 16 bits of eip are zeroed). */
920 const relax_typeS md_relax_table
[] =
923 1) most positive reach of this state,
924 2) most negative reach of this state,
925 3) how many bytes this mode will have in the variable part of the frag
926 4) which index into the table to try if we can't fit into this one. */
928 /* UNCOND_JUMP states. */
929 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
930 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
931 /* dword jmp adds 4 bytes to frag:
932 0 extra opcode bytes, 4 displacement bytes. */
934 /* word jmp adds 2 byte2 to frag:
935 0 extra opcode bytes, 2 displacement bytes. */
938 /* COND_JUMP states. */
939 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
940 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
941 /* dword conditionals adds 5 bytes to frag:
942 1 extra opcode byte, 4 displacement bytes. */
944 /* word conditionals add 3 bytes to frag:
945 1 extra opcode byte, 2 displacement bytes. */
948 /* COND_JUMP86 states. */
949 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
950 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
951 /* dword conditionals adds 5 bytes to frag:
952 1 extra opcode byte, 4 displacement bytes. */
954 /* word conditionals add 4 bytes to frag:
955 1 displacement byte and a 3 byte long branch insn. */
959 #define ARCH(n, t, f, s) \
960 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \
962 #define SUBARCH(n, e, d, s) \
963 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \
964 CPU_ ## d ## _FLAGS }
966 static const arch_entry cpu_arch
[] =
968 /* Do not replace the first two entries - i386_target_format() and
969 set_cpu_arch() rely on them being there in this order. */
970 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
971 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
972 ARCH (i8086
, UNKNOWN
, NONE
, false),
973 ARCH (i186
, UNKNOWN
, 186, false),
974 ARCH (i286
, UNKNOWN
, 286, false),
975 ARCH (i386
, I386
, 386, false),
976 ARCH (i486
, I486
, 486, false),
977 ARCH (i586
, PENTIUM
, 586, false),
978 ARCH (i686
, PENTIUMPRO
, 686, false),
979 ARCH (pentium
, PENTIUM
, 586, false),
980 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
981 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
982 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
983 ARCH (pentium4
, PENTIUM4
, P4
, false),
984 ARCH (prescott
, NOCONA
, CORE
, false),
985 ARCH (nocona
, NOCONA
, NOCONA
, false),
986 ARCH (yonah
, CORE
, CORE
, true),
987 ARCH (core
, CORE
, CORE
, false),
988 ARCH (merom
, CORE2
, CORE2
, true),
989 ARCH (core2
, CORE2
, CORE2
, false),
990 ARCH (corei7
, COREI7
, COREI7
, false),
991 ARCH (iamcu
, IAMCU
, IAMCU
, false),
992 ARCH (k6
, K6
, K6
, false),
993 ARCH (k6_2
, K6
, K6_2
, false),
994 ARCH (athlon
, ATHLON
, ATHLON
, false),
995 ARCH (sledgehammer
, K8
, K8
, true),
996 ARCH (opteron
, K8
, K8
, false),
997 ARCH (k8
, K8
, K8
, false),
998 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
999 ARCH (bdver1
, BD
, BDVER1
, false),
1000 ARCH (bdver2
, BD
, BDVER2
, false),
1001 ARCH (bdver3
, BD
, BDVER3
, false),
1002 ARCH (bdver4
, BD
, BDVER4
, false),
1003 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1004 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1005 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1006 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1007 ARCH (btver1
, BT
, BTVER1
, false),
1008 ARCH (btver2
, BT
, BTVER2
, false),
1010 SUBARCH (8087, 8087, ANY_8087
, false),
1011 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1012 SUBARCH (287, 287, ANY_287
, false),
1013 SUBARCH (387, 387, ANY_387
, false),
1014 SUBARCH (687, 687, ANY_687
, false),
1015 SUBARCH (cmov
, CMOV
, CMOV
, false),
1016 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1017 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1018 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1019 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1020 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1021 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1022 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1023 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1024 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1025 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1026 SUBARCH (avx
, AVX
, ANY_AVX
, false),
1027 SUBARCH (avx2
, AVX2
, ANY_AVX2
, false),
1028 SUBARCH (avx512f
, AVX512F
, ANY_AVX512F
, false),
1029 SUBARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, false),
1030 SUBARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, false),
1031 SUBARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, false),
1032 SUBARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, false),
1033 SUBARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, false),
1034 SUBARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, false),
1035 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1036 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1037 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1038 SUBARCH (smx
, SMX
, SMX
, false),
1039 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1040 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1041 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1042 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1043 SUBARCH (aes
, AES
, ANY_AES
, false),
1044 SUBARCH (pclmul
, PCLMUL
, ANY_PCLMUL
, false),
1045 SUBARCH (clmul
, PCLMUL
, ANY_PCLMUL
, true),
1046 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1047 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1048 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1049 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1050 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1051 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1052 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1053 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1054 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1055 SUBARCH (cx16
, CX16
, CX16
, false),
1056 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1057 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1058 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1059 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1060 SUBARCH (hle
, HLE
, HLE
, false),
1061 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1062 SUBARCH (tsx
, TSX
, TSX
, false),
1063 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1064 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1065 SUBARCH (nop
, NOP
, NOP
, false),
1066 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1067 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1068 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1069 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1070 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1071 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1072 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1073 SUBARCH (abm
, ABM
, ABM
, false),
1074 SUBARCH (bmi
, BMI
, BMI
, false),
1075 SUBARCH (tbm
, TBM
, TBM
, false),
1076 SUBARCH (adx
, ADX
, ADX
, false),
1077 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1078 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1079 SUBARCH (smap
, SMAP
, SMAP
, false),
1080 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1081 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1082 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1083 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1084 SUBARCH (se1
, SE1
, SE1
, false),
1085 SUBARCH (clwb
, CLWB
, CLWB
, false),
1086 SUBARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, false),
1087 SUBARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, false),
1088 SUBARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, false),
1089 SUBARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, false),
1090 SUBARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, false),
1091 SUBARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, false),
1092 SUBARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, false),
1093 SUBARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, false),
1094 SUBARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, false),
1095 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1096 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1097 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1098 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1099 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1100 SUBARCH (ibt
, IBT
, IBT
, false),
1101 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1102 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1103 SUBARCH (vaes
, VAES
, ANY_VAES
, false),
1104 SUBARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, false),
1105 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1106 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1107 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1108 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1109 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1110 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1111 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1112 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1113 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1114 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1115 SUBARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, false),
1116 SUBARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1117 ANY_AVX512_VP2INTERSECT
, false),
1118 SUBARCH (tdx
, TDX
, TDX
, false),
1119 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1120 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1121 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1122 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1123 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1124 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1125 SUBARCH (kl
, KL
, ANY_KL
, false),
1126 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1127 SUBARCH (uintr
, UINTR
, UINTR
, false),
1128 SUBARCH (hreset
, HRESET
, HRESET
, false),
1129 SUBARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, false),
1130 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1131 SUBARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, false),
1132 SUBARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, false),
1133 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1134 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1135 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1136 SUBARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, false),
1137 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1138 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1145 /* Like s_lcomm_internal in gas/read.c but the alignment string
1146 is allowed to be optional. */
1149 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1156 && *input_line_pointer
== ',')
1158 align
= parse_align (needs_align
- 1);
1160 if (align
== (addressT
) -1)
1175 bss_alloc (symbolP
, size
, align
);
1180 pe_lcomm (int needs_align
)
1182 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1186 const pseudo_typeS md_pseudo_table
[] =
1188 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1189 {"align", s_align_bytes
, 0},
1191 {"align", s_align_ptwo
, 0},
1193 {"arch", set_cpu_arch
, 0},
1197 {"lcomm", pe_lcomm
, 1},
1199 {"ffloat", float_cons
, 'f'},
1200 {"dfloat", float_cons
, 'd'},
1201 {"tfloat", float_cons
, 'x'},
1202 {"hfloat", float_cons
, 'h'},
1203 {"bfloat16", float_cons
, 'b'},
1205 {"slong", signed_cons
, 4},
1206 {"insn", s_insn
, 0},
1207 {"noopt", s_ignore
, 0},
1208 {"optim", s_ignore
, 0},
1209 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1210 {"code16", set_code_flag
, CODE_16BIT
},
1211 {"code32", set_code_flag
, CODE_32BIT
},
1213 {"code64", set_code_flag
, CODE_64BIT
},
1215 {"intel_syntax", set_intel_syntax
, 1},
1216 {"att_syntax", set_intel_syntax
, 0},
1217 {"intel_mnemonic", set_intel_mnemonic
, 1},
1218 {"att_mnemonic", set_intel_mnemonic
, 0},
1219 {"allow_index_reg", set_allow_index_reg
, 1},
1220 {"disallow_index_reg", set_allow_index_reg
, 0},
1221 {"sse_check", set_check
, 0},
1222 {"operand_check", set_check
, 1},
1223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1224 {"largecomm", handle_large_common
, 0},
1226 {"file", dwarf2_directive_file
, 0},
1227 {"loc", dwarf2_directive_loc
, 0},
1228 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1231 {"secrel32", pe_directive_secrel
, 0},
1232 {"secidx", pe_directive_secidx
, 0},
1237 /* For interface with expression (). */
1238 extern char *input_line_pointer
;
1240 /* Hash table for instruction mnemonic lookup. */
1241 static htab_t op_hash
;
1243 /* Hash table for register lookup. */
1244 static htab_t reg_hash
;
1246 /* Various efficient no-op patterns for aligning code labels.
1247 Note: Don't try to assemble the instructions in the comments.
1248 0L and 0w are not legal. */
1249 static const unsigned char f32_1
[] =
1251 static const unsigned char f32_2
[] =
1252 {0x66,0x90}; /* xchg %ax,%ax */
1253 static const unsigned char f32_3
[] =
1254 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1255 static const unsigned char f32_4
[] =
1256 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1257 static const unsigned char f32_6
[] =
1258 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1259 static const unsigned char f32_7
[] =
1260 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1261 static const unsigned char f16_3
[] =
1262 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1263 static const unsigned char f16_4
[] =
1264 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1265 static const unsigned char jump_disp8
[] =
1266 {0xeb}; /* jmp disp8 */
1267 static const unsigned char jump32_disp32
[] =
1268 {0xe9}; /* jmp disp32 */
1269 static const unsigned char jump16_disp32
[] =
1270 {0x66,0xe9}; /* jmp disp32 */
1271 /* 32-bit NOPs patterns. */
1272 static const unsigned char *const f32_patt
[] = {
1273 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1275 /* 16-bit NOPs patterns. */
1276 static const unsigned char *const f16_patt
[] = {
1277 f32_1
, f32_2
, f16_3
, f16_4
1279 /* nopl (%[re]ax) */
1280 static const unsigned char alt_3
[] =
1282 /* nopl 0(%[re]ax) */
1283 static const unsigned char alt_4
[] =
1284 {0x0f,0x1f,0x40,0x00};
1285 /* nopl 0(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_5
[] =
1287 {0x0f,0x1f,0x44,0x00,0x00};
1288 /* nopw 0(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_6
[] =
1290 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1291 /* nopl 0L(%[re]ax) */
1292 static const unsigned char alt_7
[] =
1293 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1294 /* nopl 0L(%[re]ax,%[re]ax,1) */
1295 static const unsigned char alt_8
[] =
1296 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1297 /* nopw 0L(%[re]ax,%[re]ax,1) */
1298 static const unsigned char alt_9
[] =
1299 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1300 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1301 static const unsigned char alt_10
[] =
1302 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1303 /* data16 nopw %cs:0L(%eax,%eax,1) */
1304 static const unsigned char alt_11
[] =
1305 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1306 /* 32-bit and 64-bit NOPs patterns. */
1307 static const unsigned char *const alt_patt
[] = {
1308 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1309 alt_9
, alt_10
, alt_11
1312 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1313 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1316 i386_output_nops (char *where
, const unsigned char *const *patt
,
1317 int count
, int max_single_nop_size
)
1320 /* Place the longer NOP first. */
1323 const unsigned char *nops
;
1325 if (max_single_nop_size
< 1)
1327 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1328 max_single_nop_size
);
1332 nops
= patt
[max_single_nop_size
- 1];
1334 /* Use the smaller one if the requsted one isn't available. */
1337 max_single_nop_size
--;
1338 nops
= patt
[max_single_nop_size
- 1];
1341 last
= count
% max_single_nop_size
;
1344 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1345 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1349 nops
= patt
[last
- 1];
1352 /* Use the smaller one plus one-byte NOP if the needed one
1355 nops
= patt
[last
- 1];
1356 memcpy (where
+ offset
, nops
, last
);
1357 where
[offset
+ last
] = *patt
[0];
1360 memcpy (where
+ offset
, nops
, last
);
1365 fits_in_imm7 (offsetT num
)
1367 return (num
& 0x7f) == num
;
1371 fits_in_imm31 (offsetT num
)
1373 return (num
& 0x7fffffff) == num
;
1376 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1377 single NOP instruction LIMIT. */
1380 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1382 const unsigned char *const *patt
= NULL
;
1383 int max_single_nop_size
;
1384 /* Maximum number of NOPs before switching to jump over NOPs. */
1385 int max_number_of_nops
;
1387 switch (fragP
->fr_type
)
1392 case rs_machine_dependent
:
1393 /* Allow NOP padding for jumps and calls. */
1394 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1395 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1402 /* We need to decide which NOP sequence to use for 32bit and
1403 64bit. When -mtune= is used:
1405 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1406 PROCESSOR_GENERIC32, f32_patt will be used.
1407 2. For the rest, alt_patt will be used.
1409 When -mtune= isn't used, alt_patt will be used if
1410 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1413 When -march= or .arch is used, we can't use anything beyond
1414 cpu_arch_isa_flags. */
1416 if (flag_code
== CODE_16BIT
)
1419 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1420 /* Limit number of NOPs to 2 in 16-bit mode. */
1421 max_number_of_nops
= 2;
1425 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1427 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1428 switch (cpu_arch_tune
)
1430 case PROCESSOR_UNKNOWN
:
1431 /* We use cpu_arch_isa_flags to check if we SHOULD
1432 optimize with nops. */
1433 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1438 case PROCESSOR_PENTIUM4
:
1439 case PROCESSOR_NOCONA
:
1440 case PROCESSOR_CORE
:
1441 case PROCESSOR_CORE2
:
1442 case PROCESSOR_COREI7
:
1443 case PROCESSOR_GENERIC64
:
1445 case PROCESSOR_ATHLON
:
1447 case PROCESSOR_AMDFAM10
:
1449 case PROCESSOR_ZNVER
:
1453 case PROCESSOR_I386
:
1454 case PROCESSOR_I486
:
1455 case PROCESSOR_PENTIUM
:
1456 case PROCESSOR_PENTIUMPRO
:
1457 case PROCESSOR_IAMCU
:
1458 case PROCESSOR_GENERIC32
:
1461 case PROCESSOR_NONE
:
1467 switch (fragP
->tc_frag_data
.tune
)
1469 case PROCESSOR_UNKNOWN
:
1470 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1471 PROCESSOR_UNKNOWN. */
1475 case PROCESSOR_I386
:
1476 case PROCESSOR_I486
:
1477 case PROCESSOR_PENTIUM
:
1478 case PROCESSOR_IAMCU
:
1480 case PROCESSOR_ATHLON
:
1482 case PROCESSOR_AMDFAM10
:
1484 case PROCESSOR_ZNVER
:
1486 case PROCESSOR_GENERIC32
:
1487 /* We use cpu_arch_isa_flags to check if we CAN optimize
1489 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1494 case PROCESSOR_PENTIUMPRO
:
1495 case PROCESSOR_PENTIUM4
:
1496 case PROCESSOR_NOCONA
:
1497 case PROCESSOR_CORE
:
1498 case PROCESSOR_CORE2
:
1499 case PROCESSOR_COREI7
:
1500 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1505 case PROCESSOR_GENERIC64
:
1508 case PROCESSOR_NONE
:
1513 if (patt
== f32_patt
)
1515 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1516 /* Limit number of NOPs to 2 for older processors. */
1517 max_number_of_nops
= 2;
1521 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1522 /* Limit number of NOPs to 7 for newer processors. */
1523 max_number_of_nops
= 7;
1528 limit
= max_single_nop_size
;
1530 if (fragP
->fr_type
== rs_fill_nop
)
1532 /* Output NOPs for .nop directive. */
1533 if (limit
> max_single_nop_size
)
1535 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1536 _("invalid single nop size: %d "
1537 "(expect within [0, %d])"),
1538 limit
, max_single_nop_size
);
1542 else if (fragP
->fr_type
!= rs_machine_dependent
)
1543 fragP
->fr_var
= count
;
1545 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1547 /* Generate jump over NOPs. */
1548 offsetT disp
= count
- 2;
1549 if (fits_in_imm7 (disp
))
1551 /* Use "jmp disp8" if possible. */
1553 where
[0] = jump_disp8
[0];
1559 unsigned int size_of_jump
;
1561 if (flag_code
== CODE_16BIT
)
1563 where
[0] = jump16_disp32
[0];
1564 where
[1] = jump16_disp32
[1];
1569 where
[0] = jump32_disp32
[0];
1573 count
-= size_of_jump
+ 4;
1574 if (!fits_in_imm31 (count
))
1576 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1577 _("jump over nop padding out of range"));
1581 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1582 where
+= size_of_jump
+ 4;
1586 /* Generate multiple NOPs. */
1587 i386_output_nops (where
, patt
, count
, limit
);
1591 operand_type_all_zero (const union i386_operand_type
*x
)
1593 switch (ARRAY_SIZE(x
->array
))
1604 return !x
->array
[0];
1611 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1613 switch (ARRAY_SIZE(x
->array
))
1629 x
->bitfield
.class = ClassNone
;
1630 x
->bitfield
.instance
= InstanceNone
;
1634 operand_type_equal (const union i386_operand_type
*x
,
1635 const union i386_operand_type
*y
)
1637 switch (ARRAY_SIZE(x
->array
))
1640 if (x
->array
[2] != y
->array
[2])
1644 if (x
->array
[1] != y
->array
[1])
1648 return x
->array
[0] == y
->array
[0];
1656 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1658 switch (ARRAY_SIZE(x
->array
))
1677 return !x
->array
[0];
1684 cpu_flags_equal (const union i386_cpu_flags
*x
,
1685 const union i386_cpu_flags
*y
)
1687 switch (ARRAY_SIZE(x
->array
))
1690 if (x
->array
[4] != y
->array
[4])
1694 if (x
->array
[3] != y
->array
[3])
1698 if (x
->array
[2] != y
->array
[2])
1702 if (x
->array
[1] != y
->array
[1])
1706 return x
->array
[0] == y
->array
[0];
1714 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1716 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1717 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1720 static INLINE i386_cpu_flags
1721 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1723 switch (ARRAY_SIZE (x
.array
))
1726 x
.array
[4] &= y
.array
[4];
1729 x
.array
[3] &= y
.array
[3];
1732 x
.array
[2] &= y
.array
[2];
1735 x
.array
[1] &= y
.array
[1];
1738 x
.array
[0] &= y
.array
[0];
1746 static INLINE i386_cpu_flags
1747 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1749 switch (ARRAY_SIZE (x
.array
))
1752 x
.array
[4] |= y
.array
[4];
1755 x
.array
[3] |= y
.array
[3];
1758 x
.array
[2] |= y
.array
[2];
1761 x
.array
[1] |= y
.array
[1];
1764 x
.array
[0] |= y
.array
[0];
1772 static INLINE i386_cpu_flags
1773 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1775 switch (ARRAY_SIZE (x
.array
))
1778 x
.array
[4] &= ~y
.array
[4];
1781 x
.array
[3] &= ~y
.array
[3];
1784 x
.array
[2] &= ~y
.array
[2];
1787 x
.array
[1] &= ~y
.array
[1];
1790 x
.array
[0] &= ~y
.array
[0];
1798 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1800 #define CPU_FLAGS_ARCH_MATCH 0x1
1801 #define CPU_FLAGS_64BIT_MATCH 0x2
1803 #define CPU_FLAGS_PERFECT_MATCH \
1804 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1806 /* Return CPU flags match bits. */
1809 cpu_flags_match (const insn_template
*t
)
1811 i386_cpu_flags x
= t
->cpu_flags
;
1812 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1814 x
.bitfield
.cpu64
= 0;
1815 x
.bitfield
.cpuno64
= 0;
1817 if (cpu_flags_all_zero (&x
))
1819 /* This instruction is available on all archs. */
1820 match
|= CPU_FLAGS_ARCH_MATCH
;
1824 /* This instruction is available only on some archs. */
1825 i386_cpu_flags cpu
= cpu_arch_flags
;
1827 /* AVX512VL is no standalone feature - match it and then strip it. */
1828 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1830 x
.bitfield
.cpuavx512vl
= 0;
1832 /* AVX and AVX2 present at the same time express an operand size
1833 dependency - strip AVX2 for the purposes here. The operand size
1834 dependent check occurs in check_vecOperands(). */
1835 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1836 x
.bitfield
.cpuavx2
= 0;
1838 cpu
= cpu_flags_and (x
, cpu
);
1839 if (!cpu_flags_all_zero (&cpu
))
1841 if (x
.bitfield
.cpuavx
)
1843 /* We need to check a few extra flags with AVX. */
1844 if (cpu
.bitfield
.cpuavx
1845 && (!t
->opcode_modifier
.sse2avx
1846 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1847 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1848 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1849 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1850 match
|= CPU_FLAGS_ARCH_MATCH
;
1852 else if (x
.bitfield
.cpuavx512f
)
1854 /* We need to check a few extra flags with AVX512F. */
1855 if (cpu
.bitfield
.cpuavx512f
1856 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1857 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1858 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1859 match
|= CPU_FLAGS_ARCH_MATCH
;
1862 match
|= CPU_FLAGS_ARCH_MATCH
;
1868 static INLINE i386_operand_type
1869 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1871 if (x
.bitfield
.class != y
.bitfield
.class)
1872 x
.bitfield
.class = ClassNone
;
1873 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1874 x
.bitfield
.instance
= InstanceNone
;
1876 switch (ARRAY_SIZE (x
.array
))
1879 x
.array
[2] &= y
.array
[2];
1882 x
.array
[1] &= y
.array
[1];
1885 x
.array
[0] &= y
.array
[0];
1893 static INLINE i386_operand_type
1894 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1896 gas_assert (y
.bitfield
.class == ClassNone
);
1897 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1899 switch (ARRAY_SIZE (x
.array
))
1902 x
.array
[2] &= ~y
.array
[2];
1905 x
.array
[1] &= ~y
.array
[1];
1908 x
.array
[0] &= ~y
.array
[0];
1916 static INLINE i386_operand_type
1917 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1919 gas_assert (x
.bitfield
.class == ClassNone
||
1920 y
.bitfield
.class == ClassNone
||
1921 x
.bitfield
.class == y
.bitfield
.class);
1922 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1923 y
.bitfield
.instance
== InstanceNone
||
1924 x
.bitfield
.instance
== y
.bitfield
.instance
);
1926 switch (ARRAY_SIZE (x
.array
))
1929 x
.array
[2] |= y
.array
[2];
1932 x
.array
[1] |= y
.array
[1];
1935 x
.array
[0] |= y
.array
[0];
1943 static INLINE i386_operand_type
1944 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1946 gas_assert (y
.bitfield
.class == ClassNone
);
1947 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1949 switch (ARRAY_SIZE (x
.array
))
1952 x
.array
[2] ^= y
.array
[2];
1955 x
.array
[1] ^= y
.array
[1];
1958 x
.array
[0] ^= y
.array
[0];
1966 static const i386_operand_type anydisp
= {
1967 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
1979 operand_type_check (i386_operand_type t
, enum operand_type c
)
1984 return t
.bitfield
.class == Reg
;
1987 return (t
.bitfield
.imm8
1991 || t
.bitfield
.imm32s
1992 || t
.bitfield
.imm64
);
1995 return (t
.bitfield
.disp8
1996 || t
.bitfield
.disp16
1997 || t
.bitfield
.disp32
1998 || t
.bitfield
.disp64
);
2001 return (t
.bitfield
.disp8
2002 || t
.bitfield
.disp16
2003 || t
.bitfield
.disp32
2004 || t
.bitfield
.disp64
2005 || t
.bitfield
.baseindex
);
2014 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2015 between operand GIVEN and opeand WANTED for instruction template T. */
2018 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2021 return !((i
.types
[given
].bitfield
.byte
2022 && !t
->operand_types
[wanted
].bitfield
.byte
)
2023 || (i
.types
[given
].bitfield
.word
2024 && !t
->operand_types
[wanted
].bitfield
.word
)
2025 || (i
.types
[given
].bitfield
.dword
2026 && !t
->operand_types
[wanted
].bitfield
.dword
)
2027 || (i
.types
[given
].bitfield
.qword
2028 && (!t
->operand_types
[wanted
].bitfield
.qword
2029 /* Don't allow 64-bit (memory) operands outside of 64-bit
2030 mode, when they're used where a 64-bit GPR could also
2031 be used. Checking is needed for Intel Syntax only. */
2033 && flag_code
!= CODE_64BIT
2034 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2035 || t
->operand_types
[wanted
].bitfield
.class == Accum
2036 || t
->opcode_modifier
.isstring
))))
2037 || (i
.types
[given
].bitfield
.tbyte
2038 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2041 /* Return 1 if there is no conflict in SIMD register between operand
2042 GIVEN and opeand WANTED for instruction template T. */
2045 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2048 return !((i
.types
[given
].bitfield
.xmmword
2049 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2050 || (i
.types
[given
].bitfield
.ymmword
2051 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2052 || (i
.types
[given
].bitfield
.zmmword
2053 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2054 || (i
.types
[given
].bitfield
.tmmword
2055 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2058 /* Return 1 if there is no conflict in any size between operand GIVEN
2059 and opeand WANTED for instruction template T. */
2062 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2065 return (match_operand_size (t
, wanted
, given
)
2066 && !((i
.types
[given
].bitfield
.unspecified
2067 && !i
.broadcast
.type
2068 && !i
.broadcast
.bytes
2069 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2070 || (i
.types
[given
].bitfield
.fword
2071 && !t
->operand_types
[wanted
].bitfield
.fword
)
2072 /* For scalar opcode templates to allow register and memory
2073 operands at the same time, some special casing is needed
2074 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2075 down-conversion vpmov*. */
2076 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2077 && t
->operand_types
[wanted
].bitfield
.byte
2078 + t
->operand_types
[wanted
].bitfield
.word
2079 + t
->operand_types
[wanted
].bitfield
.dword
2080 + t
->operand_types
[wanted
].bitfield
.qword
2081 > !!t
->opcode_modifier
.broadcast
)
2082 ? (i
.types
[given
].bitfield
.xmmword
2083 || i
.types
[given
].bitfield
.ymmword
2084 || i
.types
[given
].bitfield
.zmmword
)
2085 : !match_simd_size(t
, wanted
, given
))));
2088 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2089 operands for instruction template T, and it has MATCH_REVERSE set if there
2090 is no size conflict on any operands for the template with operands reversed
2091 (and the template allows for reversing in the first place). */
2093 #define MATCH_STRAIGHT 1
2094 #define MATCH_REVERSE 2
2096 static INLINE
unsigned int
2097 operand_size_match (const insn_template
*t
)
2099 unsigned int j
, match
= MATCH_STRAIGHT
;
2101 /* Don't check non-absolute jump instructions. */
2102 if (t
->opcode_modifier
.jump
2103 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2106 /* Check memory and accumulator operand size. */
2107 for (j
= 0; j
< i
.operands
; j
++)
2109 if (i
.types
[j
].bitfield
.class != Reg
2110 && i
.types
[j
].bitfield
.class != RegSIMD
2111 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2114 if (t
->operand_types
[j
].bitfield
.class == Reg
2115 && !match_operand_size (t
, j
, j
))
2121 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2122 && !match_simd_size (t
, j
, j
))
2128 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2129 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2135 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2142 if (!t
->opcode_modifier
.d
)
2145 /* Check reverse. */
2146 gas_assert (i
.operands
>= 2);
2148 for (j
= 0; j
< i
.operands
; j
++)
2150 unsigned int given
= i
.operands
- j
- 1;
2152 /* For FMA4 and XOP insns VEX.W controls just the first two
2153 register operands. */
2154 if (t
->cpu_flags
.bitfield
.cpufma4
|| t
->cpu_flags
.bitfield
.cpuxop
)
2155 given
= j
< 2 ? 1 - j
: j
;
2157 if (t
->operand_types
[j
].bitfield
.class == Reg
2158 && !match_operand_size (t
, j
, given
))
2161 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2162 && !match_simd_size (t
, j
, given
))
2165 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2166 && (!match_operand_size (t
, j
, given
)
2167 || !match_simd_size (t
, j
, given
)))
2170 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2174 return match
| MATCH_REVERSE
;
2178 operand_type_match (i386_operand_type overlap
,
2179 i386_operand_type given
)
2181 i386_operand_type temp
= overlap
;
2183 temp
.bitfield
.unspecified
= 0;
2184 temp
.bitfield
.byte
= 0;
2185 temp
.bitfield
.word
= 0;
2186 temp
.bitfield
.dword
= 0;
2187 temp
.bitfield
.fword
= 0;
2188 temp
.bitfield
.qword
= 0;
2189 temp
.bitfield
.tbyte
= 0;
2190 temp
.bitfield
.xmmword
= 0;
2191 temp
.bitfield
.ymmword
= 0;
2192 temp
.bitfield
.zmmword
= 0;
2193 temp
.bitfield
.tmmword
= 0;
2194 if (operand_type_all_zero (&temp
))
2197 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2201 i
.error
= operand_type_mismatch
;
2205 /* If given types g0 and g1 are registers they must be of the same type
2206 unless the expected operand type register overlap is null.
2207 Intel syntax sized memory operands are also checked here. */
2210 operand_type_register_match (i386_operand_type g0
,
2211 i386_operand_type t0
,
2212 i386_operand_type g1
,
2213 i386_operand_type t1
)
2215 if (g0
.bitfield
.class != Reg
2216 && g0
.bitfield
.class != RegSIMD
2217 && (g0
.bitfield
.unspecified
2218 || !operand_type_check (g0
, anymem
)))
2221 if (g1
.bitfield
.class != Reg
2222 && g1
.bitfield
.class != RegSIMD
2223 && (g1
.bitfield
.unspecified
2224 || !operand_type_check (g1
, anymem
)))
2227 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2228 && g0
.bitfield
.word
== g1
.bitfield
.word
2229 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2230 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2231 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2232 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2233 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2236 /* If expectations overlap in no more than a single size, all is fine. */
2237 g0
= operand_type_and (t0
, t1
);
2238 if (g0
.bitfield
.byte
2242 + g0
.bitfield
.xmmword
2243 + g0
.bitfield
.ymmword
2244 + g0
.bitfield
.zmmword
<= 1)
2247 i
.error
= register_type_mismatch
;
2252 static INLINE
unsigned int
2253 register_number (const reg_entry
*r
)
2255 unsigned int nr
= r
->reg_num
;
2257 if (r
->reg_flags
& RegRex
)
2260 if (r
->reg_flags
& RegVRex
)
2266 static INLINE
unsigned int
2267 mode_from_disp_size (i386_operand_type t
)
2269 if (t
.bitfield
.disp8
)
2271 else if (t
.bitfield
.disp16
2272 || t
.bitfield
.disp32
)
2279 fits_in_signed_byte (addressT num
)
2281 return num
+ 0x80 <= 0xff;
2285 fits_in_unsigned_byte (addressT num
)
2291 fits_in_unsigned_word (addressT num
)
2293 return num
<= 0xffff;
2297 fits_in_signed_word (addressT num
)
2299 return num
+ 0x8000 <= 0xffff;
2303 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2308 return num
+ 0x80000000 <= 0xffffffff;
2310 } /* fits_in_signed_long() */
2313 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2318 return num
<= 0xffffffff;
2320 } /* fits_in_unsigned_long() */
2322 static INLINE valueT
extend_to_32bit_address (addressT num
)
2325 if (fits_in_unsigned_long(num
))
2326 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2328 if (!fits_in_signed_long (num
))
2329 return num
& 0xffffffff;
2336 fits_in_disp8 (offsetT num
)
2338 int shift
= i
.memshift
;
2344 mask
= (1 << shift
) - 1;
2346 /* Return 0 if NUM isn't properly aligned. */
2350 /* Check if NUM will fit in 8bit after shift. */
2351 return fits_in_signed_byte (num
>> shift
);
2355 fits_in_imm4 (offsetT num
)
2357 return (num
& 0xf) == num
;
2360 static i386_operand_type
2361 smallest_imm_type (offsetT num
)
2363 i386_operand_type t
;
2365 operand_type_set (&t
, 0);
2366 t
.bitfield
.imm64
= 1;
2368 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2370 /* This code is disabled on the 486 because all the Imm1 forms
2371 in the opcode table are slower on the i486. They're the
2372 versions with the implicitly specified single-position
2373 displacement, which has another syntax if you really want to
2375 t
.bitfield
.imm1
= 1;
2376 t
.bitfield
.imm8
= 1;
2377 t
.bitfield
.imm8s
= 1;
2378 t
.bitfield
.imm16
= 1;
2379 t
.bitfield
.imm32
= 1;
2380 t
.bitfield
.imm32s
= 1;
2382 else if (fits_in_signed_byte (num
))
2384 if (fits_in_unsigned_byte (num
))
2385 t
.bitfield
.imm8
= 1;
2386 t
.bitfield
.imm8s
= 1;
2387 t
.bitfield
.imm16
= 1;
2388 t
.bitfield
.imm32
= 1;
2389 t
.bitfield
.imm32s
= 1;
2391 else if (fits_in_unsigned_byte (num
))
2393 t
.bitfield
.imm8
= 1;
2394 t
.bitfield
.imm16
= 1;
2395 t
.bitfield
.imm32
= 1;
2396 t
.bitfield
.imm32s
= 1;
2398 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2400 t
.bitfield
.imm16
= 1;
2401 t
.bitfield
.imm32
= 1;
2402 t
.bitfield
.imm32s
= 1;
2404 else if (fits_in_signed_long (num
))
2406 t
.bitfield
.imm32
= 1;
2407 t
.bitfield
.imm32s
= 1;
2409 else if (fits_in_unsigned_long (num
))
2410 t
.bitfield
.imm32
= 1;
2416 offset_in_range (offsetT val
, int size
)
2422 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2423 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2425 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2427 case sizeof (val
): return val
;
2431 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2432 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2433 (uint64_t) val
, (uint64_t) (val
& mask
));
2438 static INLINE
const char *insn_name (const insn_template
*t
)
2440 return &i386_mnemonics
[t
->mnem_off
];
2453 a. PREFIX_EXIST if attempting to add a prefix where one from the
2454 same class already exists.
2455 b. PREFIX_LOCK if lock prefix is added.
2456 c. PREFIX_REP if rep/repne prefix is added.
2457 d. PREFIX_DS if ds prefix is added.
2458 e. PREFIX_OTHER if other prefix is added.
2461 static enum PREFIX_GROUP
2462 add_prefix (unsigned int prefix
)
2464 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2467 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2468 && flag_code
== CODE_64BIT
)
2470 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2471 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2472 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2473 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2484 case DS_PREFIX_OPCODE
:
2487 case CS_PREFIX_OPCODE
:
2488 case ES_PREFIX_OPCODE
:
2489 case FS_PREFIX_OPCODE
:
2490 case GS_PREFIX_OPCODE
:
2491 case SS_PREFIX_OPCODE
:
2495 case REPNE_PREFIX_OPCODE
:
2496 case REPE_PREFIX_OPCODE
:
2501 case LOCK_PREFIX_OPCODE
:
2510 case ADDR_PREFIX_OPCODE
:
2514 case DATA_PREFIX_OPCODE
:
2518 if (i
.prefix
[q
] != 0)
2526 i
.prefix
[q
] |= prefix
;
2529 as_bad (_("same type of prefix used twice"));
2535 update_code_flag (int value
, int check
)
2537 PRINTF_LIKE ((*as_error
));
2539 flag_code
= (enum flag_code
) value
;
2540 if (flag_code
== CODE_64BIT
)
2542 cpu_arch_flags
.bitfield
.cpu64
= 1;
2543 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2547 cpu_arch_flags
.bitfield
.cpu64
= 0;
2548 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2550 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2553 as_error
= as_fatal
;
2556 (*as_error
) (_("64bit mode not supported on `%s'."),
2557 cpu_arch_name
? cpu_arch_name
: default_arch
);
2559 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2562 as_error
= as_fatal
;
2565 (*as_error
) (_("32bit mode not supported on `%s'."),
2566 cpu_arch_name
? cpu_arch_name
: default_arch
);
2568 stackop_size
= '\0';
2572 set_code_flag (int value
)
2574 update_code_flag (value
, 0);
2578 set_16bit_gcc_code_flag (int new_code_flag
)
2580 flag_code
= (enum flag_code
) new_code_flag
;
2581 if (flag_code
!= CODE_16BIT
)
2583 cpu_arch_flags
.bitfield
.cpu64
= 0;
2584 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2585 stackop_size
= LONG_MNEM_SUFFIX
;
2589 set_intel_syntax (int syntax_flag
)
2591 /* Find out if register prefixing is specified. */
2592 int ask_naked_reg
= 0;
2595 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2598 int e
= get_symbol_name (&string
);
2600 if (strcmp (string
, "prefix") == 0)
2602 else if (strcmp (string
, "noprefix") == 0)
2605 as_bad (_("bad argument to syntax directive."));
2606 (void) restore_line_pointer (e
);
2608 demand_empty_rest_of_line ();
2610 intel_syntax
= syntax_flag
;
2612 if (ask_naked_reg
== 0)
2613 allow_naked_reg
= (intel_syntax
2614 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2616 allow_naked_reg
= (ask_naked_reg
< 0);
2618 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2620 register_prefix
= allow_naked_reg
? "" : "%";
2624 set_intel_mnemonic (int mnemonic_flag
)
2626 intel_mnemonic
= mnemonic_flag
;
2630 set_allow_index_reg (int flag
)
2632 allow_index_reg
= flag
;
2636 set_check (int what
)
2638 enum check_kind
*kind
;
2643 kind
= &operand_check
;
2654 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2657 int e
= get_symbol_name (&string
);
2659 if (strcmp (string
, "none") == 0)
2661 else if (strcmp (string
, "warning") == 0)
2662 *kind
= check_warning
;
2663 else if (strcmp (string
, "error") == 0)
2664 *kind
= check_error
;
2666 as_bad (_("bad argument to %s_check directive."), str
);
2667 (void) restore_line_pointer (e
);
2670 as_bad (_("missing argument for %s_check directive"), str
);
2672 demand_empty_rest_of_line ();
2676 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2677 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2680 static const char *arch
;
2682 /* Intel MCU is only supported on ELF. */
2688 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2689 use default_arch. */
2690 arch
= cpu_arch_name
;
2692 arch
= default_arch
;
2695 /* If we are targeting Intel MCU, we must enable it. */
2696 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2697 == new_flag
.bitfield
.cpuiamcu
)
2700 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2705 extend_cpu_sub_arch_name (const char *name
)
2707 if (cpu_sub_arch_name
)
2708 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2709 ".", name
, (const char *) NULL
);
2711 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2715 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2717 typedef struct arch_stack_entry
2719 const struct arch_stack_entry
*prev
;
2722 i386_cpu_flags flags
;
2723 i386_cpu_flags isa_flags
;
2724 enum processor_type isa
;
2725 enum flag_code flag_code
;
2727 bool no_cond_jump_promotion
;
2729 static const arch_stack_entry
*arch_stack_top
;
2733 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2736 int e
= get_symbol_name (&s
);
2737 const char *string
= s
;
2739 i386_cpu_flags flags
;
2741 if (strcmp (string
, "default") == 0)
2743 if (strcmp (default_arch
, "iamcu") == 0)
2744 string
= default_arch
;
2747 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2749 cpu_arch_name
= NULL
;
2750 free (cpu_sub_arch_name
);
2751 cpu_sub_arch_name
= NULL
;
2752 cpu_arch_flags
= cpu_unknown_flags
;
2753 if (flag_code
== CODE_64BIT
)
2755 cpu_arch_flags
.bitfield
.cpu64
= 1;
2756 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2760 cpu_arch_flags
.bitfield
.cpu64
= 0;
2761 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2763 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2764 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2765 if (!cpu_arch_tune_set
)
2767 cpu_arch_tune
= cpu_arch_isa
;
2768 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2771 j
= ARRAY_SIZE (cpu_arch
) + 1;
2774 else if (strcmp (string
, "push") == 0)
2776 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2778 top
->name
= cpu_arch_name
;
2779 if (cpu_sub_arch_name
)
2780 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2782 top
->sub_name
= NULL
;
2783 top
->flags
= cpu_arch_flags
;
2784 top
->isa
= cpu_arch_isa
;
2785 top
->isa_flags
= cpu_arch_isa_flags
;
2786 top
->flag_code
= flag_code
;
2787 top
->stackop_size
= stackop_size
;
2788 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2790 top
->prev
= arch_stack_top
;
2791 arch_stack_top
= top
;
2793 (void) restore_line_pointer (e
);
2794 demand_empty_rest_of_line ();
2797 else if (strcmp (string
, "pop") == 0)
2799 const arch_stack_entry
*top
= arch_stack_top
;
2802 as_bad (_(".arch stack is empty"));
2803 else if (top
->flag_code
!= flag_code
2804 || top
->stackop_size
!= stackop_size
)
2806 static const unsigned int bits
[] = {
2812 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2813 bits
[top
->flag_code
],
2814 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2818 arch_stack_top
= top
->prev
;
2820 cpu_arch_name
= top
->name
;
2821 free (cpu_sub_arch_name
);
2822 cpu_sub_arch_name
= top
->sub_name
;
2823 cpu_arch_flags
= top
->flags
;
2824 cpu_arch_isa
= top
->isa
;
2825 cpu_arch_isa_flags
= top
->isa_flags
;
2826 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2831 (void) restore_line_pointer (e
);
2832 demand_empty_rest_of_line ();
2836 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2838 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2839 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2843 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2845 cpu_arch_name
= cpu_arch
[j
].name
;
2846 free (cpu_sub_arch_name
);
2847 cpu_sub_arch_name
= NULL
;
2848 cpu_arch_flags
= cpu_arch
[j
].enable
;
2849 if (flag_code
== CODE_64BIT
)
2851 cpu_arch_flags
.bitfield
.cpu64
= 1;
2852 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2856 cpu_arch_flags
.bitfield
.cpu64
= 0;
2857 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2859 cpu_arch_isa
= cpu_arch
[j
].type
;
2860 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2861 if (!cpu_arch_tune_set
)
2863 cpu_arch_tune
= cpu_arch_isa
;
2864 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2866 pre_386_16bit_warned
= false;
2870 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2873 flags
= cpu_flags_or (cpu_arch_flags
,
2874 cpu_arch
[j
].enable
);
2876 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2878 extend_cpu_sub_arch_name (string
+ 1);
2879 cpu_arch_flags
= flags
;
2880 cpu_arch_isa_flags
= flags
;
2884 = cpu_flags_or (cpu_arch_isa_flags
,
2885 cpu_arch
[j
].enable
);
2886 (void) restore_line_pointer (e
);
2887 demand_empty_rest_of_line ();
2892 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
2894 /* Disable an ISA extension. */
2895 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2896 if (cpu_arch
[j
].type
== PROCESSOR_NONE
2897 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
2899 flags
= cpu_flags_and_not (cpu_arch_flags
,
2900 cpu_arch
[j
].disable
);
2901 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2903 extend_cpu_sub_arch_name (string
+ 1);
2904 cpu_arch_flags
= flags
;
2905 cpu_arch_isa_flags
= flags
;
2907 (void) restore_line_pointer (e
);
2908 demand_empty_rest_of_line ();
2913 if (j
== ARRAY_SIZE (cpu_arch
))
2914 as_bad (_("no such architecture: `%s'"), string
);
2916 *input_line_pointer
= e
;
2919 as_bad (_("missing cpu architecture"));
2921 no_cond_jump_promotion
= 0;
2922 if (*input_line_pointer
== ','
2923 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2928 ++input_line_pointer
;
2929 e
= get_symbol_name (&string
);
2931 if (strcmp (string
, "nojumps") == 0)
2932 no_cond_jump_promotion
= 1;
2933 else if (strcmp (string
, "jumps") == 0)
2936 as_bad (_("no such architecture modifier: `%s'"), string
);
2938 (void) restore_line_pointer (e
);
2941 demand_empty_rest_of_line ();
2944 enum bfd_architecture
2947 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2949 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2950 || flag_code
== CODE_64BIT
)
2951 as_fatal (_("Intel MCU is 32bit ELF only"));
2952 return bfd_arch_iamcu
;
2955 return bfd_arch_i386
;
2961 if (startswith (default_arch
, "x86_64"))
2963 if (default_arch
[6] == '\0')
2964 return bfd_mach_x86_64
;
2966 return bfd_mach_x64_32
;
2968 else if (!strcmp (default_arch
, "i386")
2969 || !strcmp (default_arch
, "iamcu"))
2971 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2973 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2974 as_fatal (_("Intel MCU is 32bit ELF only"));
2975 return bfd_mach_i386_iamcu
;
2978 return bfd_mach_i386_i386
;
2981 as_fatal (_("unknown architecture"));
2984 #include "opcodes/i386-tbl.h"
2989 /* Support pseudo prefixes like {disp32}. */
2990 lex_type
['{'] = LEX_BEGIN_NAME
;
2992 /* Initialize op_hash hash table. */
2993 op_hash
= str_htab_create ();
2996 const insn_template
*const *sets
= i386_op_sets
;
2997 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
2999 /* Type checks to compensate for the conversion through void * which
3000 occurs during hash table insertion / lookup. */
3001 (void) sizeof (sets
== ¤t_templates
->start
);
3002 (void) sizeof (end
== ¤t_templates
->end
);
3003 for (; sets
< end
; ++sets
)
3004 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3005 as_fatal (_("duplicate %s"), insn_name (*sets
));
3008 /* Initialize reg_hash hash table. */
3009 reg_hash
= str_htab_create ();
3011 const reg_entry
*regtab
;
3012 unsigned int regtab_size
= i386_regtab_size
;
3014 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3016 switch (regtab
->reg_type
.bitfield
.class)
3019 if (regtab
->reg_type
.bitfield
.dword
)
3021 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3024 else if (regtab
->reg_type
.bitfield
.tbyte
)
3026 /* There's no point inserting st(<N>) in the hash table, as
3027 parentheses aren't included in register_chars[] anyway. */
3028 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3035 switch (regtab
->reg_num
)
3037 case 0: reg_es
= regtab
; break;
3038 case 2: reg_ss
= regtab
; break;
3039 case 3: reg_ds
= regtab
; break;
3044 if (!regtab
->reg_num
)
3049 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3050 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3054 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3059 for (c
= 0; c
< 256; c
++)
3061 if (ISDIGIT (c
) || ISLOWER (c
))
3063 mnemonic_chars
[c
] = c
;
3064 register_chars
[c
] = c
;
3065 operand_chars
[c
] = c
;
3067 else if (ISUPPER (c
))
3069 mnemonic_chars
[c
] = TOLOWER (c
);
3070 register_chars
[c
] = mnemonic_chars
[c
];
3071 operand_chars
[c
] = c
;
3073 else if (c
== '{' || c
== '}')
3075 mnemonic_chars
[c
] = c
;
3076 operand_chars
[c
] = c
;
3078 #ifdef SVR4_COMMENT_CHARS
3079 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3080 operand_chars
[c
] = c
;
3084 operand_chars
[c
] = c
;
3088 operand_chars
['?'] = '?';
3090 mnemonic_chars
['_'] = '_';
3091 mnemonic_chars
['-'] = '-';
3092 mnemonic_chars
['.'] = '.';
3094 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3095 operand_chars
[(unsigned char) *p
] = *p
;
3098 if (flag_code
== CODE_64BIT
)
3100 #if defined (OBJ_COFF) && defined (TE_PE)
3101 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3104 x86_dwarf2_return_column
= 16;
3106 x86_cie_data_alignment
= -8;
3107 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3108 x86_sframe_cfa_sp_reg
= 7;
3109 x86_sframe_cfa_fp_reg
= 6;
3114 x86_dwarf2_return_column
= 8;
3115 x86_cie_data_alignment
= -4;
3118 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3119 can be turned into BRANCH_PREFIX frag. */
3120 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3125 i386_print_statistics (FILE *file
)
3127 htab_print_statistics (file
, "i386 opcode", op_hash
);
3128 htab_print_statistics (file
, "i386 register", reg_hash
);
3134 htab_delete (op_hash
);
3135 htab_delete (reg_hash
);
3140 /* Debugging routines for md_assemble. */
3141 static void pte (insn_template
*);
3142 static void pt (i386_operand_type
);
3143 static void pe (expressionS
*);
3144 static void ps (symbolS
*);
3147 pi (const char *line
, i386_insn
*x
)
3151 fprintf (stdout
, "%s: template ", line
);
3153 fprintf (stdout
, " address: base %s index %s scale %x\n",
3154 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3155 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3156 x
->log2_scale_factor
);
3157 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3158 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3159 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3160 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3161 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3162 (x
->rex
& REX_W
) != 0,
3163 (x
->rex
& REX_R
) != 0,
3164 (x
->rex
& REX_X
) != 0,
3165 (x
->rex
& REX_B
) != 0);
3166 for (j
= 0; j
< x
->operands
; j
++)
3168 fprintf (stdout
, " #%d: ", j
+ 1);
3170 fprintf (stdout
, "\n");
3171 if (x
->types
[j
].bitfield
.class == Reg
3172 || x
->types
[j
].bitfield
.class == RegMMX
3173 || x
->types
[j
].bitfield
.class == RegSIMD
3174 || x
->types
[j
].bitfield
.class == RegMask
3175 || x
->types
[j
].bitfield
.class == SReg
3176 || x
->types
[j
].bitfield
.class == RegCR
3177 || x
->types
[j
].bitfield
.class == RegDR
3178 || x
->types
[j
].bitfield
.class == RegTR
3179 || x
->types
[j
].bitfield
.class == RegBND
)
3180 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3181 if (operand_type_check (x
->types
[j
], imm
))
3183 if (operand_type_check (x
->types
[j
], disp
))
3184 pe (x
->op
[j
].disps
);
3189 pte (insn_template
*t
)
3191 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3192 static const char *const opc_spc
[] = {
3193 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3194 "XOP08", "XOP09", "XOP0A",
3198 fprintf (stdout
, " %d operands ", t
->operands
);
3199 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3200 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3201 if (opc_spc
[t
->opcode_space
])
3202 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3203 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3204 if (t
->extension_opcode
!= None
)
3205 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3206 if (t
->opcode_modifier
.d
)
3207 fprintf (stdout
, "D");
3208 if (t
->opcode_modifier
.w
)
3209 fprintf (stdout
, "W");
3210 fprintf (stdout
, "\n");
3211 for (j
= 0; j
< t
->operands
; j
++)
3213 fprintf (stdout
, " #%d type ", j
+ 1);
3214 pt (t
->operand_types
[j
]);
3215 fprintf (stdout
, "\n");
3222 fprintf (stdout
, " operation %d\n", e
->X_op
);
3223 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3224 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3225 if (e
->X_add_symbol
)
3227 fprintf (stdout
, " add_symbol ");
3228 ps (e
->X_add_symbol
);
3229 fprintf (stdout
, "\n");
3233 fprintf (stdout
, " op_symbol ");
3234 ps (e
->X_op_symbol
);
3235 fprintf (stdout
, "\n");
3242 fprintf (stdout
, "%s type %s%s",
3244 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3245 segment_name (S_GET_SEGMENT (s
)));
3248 static struct type_name
3250 i386_operand_type mask
;
3253 const type_names
[] =
3255 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3256 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3257 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3258 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3259 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3260 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3261 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3262 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3263 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3264 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3265 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3266 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3267 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3268 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3269 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3270 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3271 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3272 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3273 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3274 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3275 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3276 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3277 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3278 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3279 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3280 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3281 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3282 { { .bitfield
= { .class = SReg
} }, "SReg" },
3283 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3284 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3285 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3286 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3287 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3288 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3292 pt (i386_operand_type t
)
3295 i386_operand_type a
;
3297 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3299 a
= operand_type_and (t
, type_names
[j
].mask
);
3300 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3301 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3306 #endif /* DEBUG386 */
3308 static bfd_reloc_code_real_type
3309 reloc (unsigned int size
,
3312 bfd_reloc_code_real_type other
)
3314 if (other
!= NO_RELOC
)
3316 reloc_howto_type
*rel
;
3321 case BFD_RELOC_X86_64_GOT32
:
3322 return BFD_RELOC_X86_64_GOT64
;
3324 case BFD_RELOC_X86_64_GOTPLT64
:
3325 return BFD_RELOC_X86_64_GOTPLT64
;
3327 case BFD_RELOC_X86_64_PLTOFF64
:
3328 return BFD_RELOC_X86_64_PLTOFF64
;
3330 case BFD_RELOC_X86_64_GOTPC32
:
3331 other
= BFD_RELOC_X86_64_GOTPC64
;
3333 case BFD_RELOC_X86_64_GOTPCREL
:
3334 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3336 case BFD_RELOC_X86_64_TPOFF32
:
3337 other
= BFD_RELOC_X86_64_TPOFF64
;
3339 case BFD_RELOC_X86_64_DTPOFF32
:
3340 other
= BFD_RELOC_X86_64_DTPOFF64
;
3346 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3347 if (other
== BFD_RELOC_SIZE32
)
3350 other
= BFD_RELOC_SIZE64
;
3353 as_bad (_("there are no pc-relative size relocations"));
3359 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3360 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3363 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3365 as_bad (_("unknown relocation (%u)"), other
);
3366 else if (size
!= bfd_get_reloc_size (rel
))
3367 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3368 bfd_get_reloc_size (rel
),
3370 else if (pcrel
&& !rel
->pc_relative
)
3371 as_bad (_("non-pc-relative relocation for pc-relative field"));
3372 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3374 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3376 as_bad (_("relocated field and relocation type differ in signedness"));
3385 as_bad (_("there are no unsigned pc-relative relocations"));
3388 case 1: return BFD_RELOC_8_PCREL
;
3389 case 2: return BFD_RELOC_16_PCREL
;
3390 case 4: return BFD_RELOC_32_PCREL
;
3391 case 8: return BFD_RELOC_64_PCREL
;
3393 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3400 case 4: return BFD_RELOC_X86_64_32S
;
3405 case 1: return BFD_RELOC_8
;
3406 case 2: return BFD_RELOC_16
;
3407 case 4: return BFD_RELOC_32
;
3408 case 8: return BFD_RELOC_64
;
3410 as_bad (_("cannot do %s %u byte relocation"),
3411 sign
> 0 ? "signed" : "unsigned", size
);
3417 /* Here we decide which fixups can be adjusted to make them relative to
3418 the beginning of the section instead of the symbol. Basically we need
3419 to make sure that the dynamic relocations are done correctly, so in
3420 some cases we force the original symbol to be used. */
3423 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3425 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3429 /* Don't adjust pc-relative references to merge sections in 64-bit
3431 if (use_rela_relocations
3432 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3436 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3437 and changed later by validate_fix. */
3438 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3439 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3442 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3443 for size relocations. */
3444 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3445 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3446 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3447 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3448 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3449 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3450 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3451 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3452 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3453 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3454 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3455 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3456 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3457 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3458 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3459 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3460 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3461 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3462 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3463 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3464 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3465 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3466 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3467 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3468 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3469 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3473 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3474 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3481 want_disp32 (const insn_template
*t
)
3483 return flag_code
!= CODE_64BIT
3484 || i
.prefix
[ADDR_PREFIX
]
3485 || (t
->mnem_off
== MN_lea
3486 && (!i
.types
[1].bitfield
.qword
3487 || t
->opcode_modifier
.size
== SIZE32
));
3491 intel_float_operand (const char *mnemonic
)
3493 /* Note that the value returned is meaningful only for opcodes with (memory)
3494 operands, hence the code here is free to improperly handle opcodes that
3495 have no operands (for better performance and smaller code). */
3497 if (mnemonic
[0] != 'f')
3498 return 0; /* non-math */
3500 switch (mnemonic
[1])
3502 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3503 the fs segment override prefix not currently handled because no
3504 call path can make opcodes without operands get here */
3506 return 2 /* integer op */;
3508 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3509 return 3; /* fldcw/fldenv */
3512 if (mnemonic
[2] != 'o' /* fnop */)
3513 return 3; /* non-waiting control op */
3516 if (mnemonic
[2] == 's')
3517 return 3; /* frstor/frstpm */
3520 if (mnemonic
[2] == 'a')
3521 return 3; /* fsave */
3522 if (mnemonic
[2] == 't')
3524 switch (mnemonic
[3])
3526 case 'c': /* fstcw */
3527 case 'd': /* fstdw */
3528 case 'e': /* fstenv */
3529 case 's': /* fsts[gw] */
3535 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3536 return 0; /* fxsave/fxrstor are not really math ops */
3544 install_template (const insn_template
*t
)
3550 /* Note that for pseudo prefixes this produces a length of 1. But for them
3551 the length isn't interesting at all. */
3552 for (l
= 1; l
< 4; ++l
)
3553 if (!(t
->base_opcode
>> (8 * l
)))
3556 i
.opcode_length
= l
;
3559 /* Build the VEX prefix. */
3562 build_vex_prefix (const insn_template
*t
)
3564 unsigned int register_specifier
;
3565 unsigned int vector_length
;
3568 /* Check register specifier. */
3569 if (i
.vex
.register_specifier
)
3571 register_specifier
=
3572 ~register_number (i
.vex
.register_specifier
) & 0xf;
3573 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3576 register_specifier
= 0xf;
3578 /* Use 2-byte VEX prefix by swapping destination and source operand
3579 if there are more than 1 register operand. */
3580 if (i
.reg_operands
> 1
3581 && i
.vec_encoding
!= vex_encoding_vex3
3582 && i
.dir_encoding
== dir_encoding_default
3583 && i
.operands
== i
.reg_operands
3584 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3585 && i
.tm
.opcode_space
== SPACE_0F
3586 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3591 swap_2_operands (0, i
.operands
- 1);
3593 gas_assert (i
.rm
.mode
== 3);
3597 i
.rm
.regmem
= i
.rm
.reg
;
3600 if (i
.tm
.opcode_modifier
.d
)
3601 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3602 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3603 else /* Use the next insn. */
3604 install_template (&t
[1]);
3607 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3608 are no memory operands and at least 3 register ones. */
3609 if (i
.reg_operands
>= 3
3610 && i
.vec_encoding
!= vex_encoding_vex3
3611 && i
.reg_operands
== i
.operands
- i
.imm_operands
3612 && i
.tm
.opcode_modifier
.vex
3613 && i
.tm
.opcode_modifier
.commutative
3614 && (i
.tm
.opcode_modifier
.sse2avx
3615 || (optimize
> 1 && !i
.no_optimize
))
3617 && i
.vex
.register_specifier
3618 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3620 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3622 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3623 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3624 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3625 &i
.types
[i
.operands
- 3]));
3626 gas_assert (i
.rm
.mode
== 3);
3628 swap_2_operands (xchg
, xchg
+ 1);
3631 xchg
= i
.rm
.regmem
| 8;
3632 i
.rm
.regmem
= ~register_specifier
& 0xf;
3633 gas_assert (!(i
.rm
.regmem
& 8));
3634 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3635 register_specifier
= ~xchg
& 0xf;
3638 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3639 vector_length
= avxscalar
;
3640 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3642 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3648 /* Determine vector length from the last multi-length vector
3651 for (op
= t
->operands
; op
--;)
3652 if (t
->operand_types
[op
].bitfield
.xmmword
3653 && t
->operand_types
[op
].bitfield
.ymmword
3654 && i
.types
[op
].bitfield
.ymmword
)
3661 /* Check the REX.W bit and VEXW. */
3662 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3663 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3664 else if (i
.tm
.opcode_modifier
.vexw
)
3665 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3667 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3669 /* Use 2-byte VEX prefix if possible. */
3671 && i
.vec_encoding
!= vex_encoding_vex3
3672 && i
.tm
.opcode_space
== SPACE_0F
3673 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3675 /* 2-byte VEX prefix. */
3679 i
.vex
.bytes
[0] = 0xc5;
3681 /* Check the REX.R bit. */
3682 r
= (i
.rex
& REX_R
) ? 0 : 1;
3683 i
.vex
.bytes
[1] = (r
<< 7
3684 | register_specifier
<< 3
3685 | vector_length
<< 2
3686 | i
.tm
.opcode_modifier
.opcodeprefix
);
3690 /* 3-byte VEX prefix. */
3693 switch (i
.tm
.opcode_space
)
3698 i
.vex
.bytes
[0] = 0xc4;
3703 i
.vex
.bytes
[0] = 0x8f;
3709 /* The high 3 bits of the second VEX byte are 1's compliment
3710 of RXB bits from REX. */
3711 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3712 | (!dot_insn () ? i
.tm
.opcode_space
3713 : i
.insn_opcode_space
);
3715 i
.vex
.bytes
[2] = (w
<< 7
3716 | register_specifier
<< 3
3717 | vector_length
<< 2
3718 | i
.tm
.opcode_modifier
.opcodeprefix
);
3723 is_evex_encoding (const insn_template
*t
)
3725 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3726 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3727 || t
->opcode_modifier
.sae
;
3731 is_any_vex_encoding (const insn_template
*t
)
3733 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3737 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3739 unsigned int op
, bytes
;
3740 const i386_operand_type
*types
;
3742 if (i
.broadcast
.type
)
3743 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3745 gas_assert (intel_syntax
);
3747 for (op
= 0; op
< t
->operands
; ++op
)
3748 if (t
->operand_types
[op
].bitfield
.baseindex
)
3751 gas_assert (op
< t
->operands
);
3753 if (t
->opcode_modifier
.evex
3754 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3755 switch (i
.broadcast
.bytes
)
3758 if (t
->operand_types
[op
].bitfield
.word
)
3762 if (t
->operand_types
[op
].bitfield
.dword
)
3766 if (t
->operand_types
[op
].bitfield
.qword
)
3770 if (t
->operand_types
[op
].bitfield
.xmmword
)
3772 if (t
->operand_types
[op
].bitfield
.ymmword
)
3774 if (t
->operand_types
[op
].bitfield
.zmmword
)
3781 gas_assert (op
+ 1 < t
->operands
);
3783 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3784 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3785 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3787 types
= &i
.types
[op
+ 1];
3790 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3791 types
= &t
->operand_types
[op
];
3793 if (types
->bitfield
.zmmword
)
3795 else if (types
->bitfield
.ymmword
)
3801 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3802 insn_name (t
), bytes
* 8);
3807 /* Build the EVEX prefix. */
3810 build_evex_prefix (void)
3812 unsigned int register_specifier
, w
;
3813 rex_byte vrex_used
= 0;
3815 /* Check register specifier. */
3816 if (i
.vex
.register_specifier
)
3818 gas_assert ((i
.vrex
& REX_X
) == 0);
3820 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3821 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3822 register_specifier
+= 8;
3823 /* The upper 16 registers are encoded in the fourth byte of the
3825 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3826 i
.vex
.bytes
[3] = 0x8;
3827 register_specifier
= ~register_specifier
& 0xf;
3831 register_specifier
= 0xf;
3833 /* Encode upper 16 vector index register in the fourth byte of
3835 if (!(i
.vrex
& REX_X
))
3836 i
.vex
.bytes
[3] = 0x8;
3841 /* 4 byte EVEX prefix. */
3843 i
.vex
.bytes
[0] = 0x62;
3845 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3847 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3848 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3849 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3850 | (!dot_insn () ? i
.tm
.opcode_space
3851 : i
.insn_opcode_space
);
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* The third byte of the EVEX prefix. */
3886 i
.vex
.bytes
[2] = ((w
<< 7)
3887 | (register_specifier
<< 3)
3888 | 4 /* Encode the U bit. */
3889 | i
.tm
.opcode_modifier
.opcodeprefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3897 if (i
.rounding
.type
== rc_none
)
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3909 for (op
= i
.operands
; op
--;)
3910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3914 if (i
.types
[op
].bitfield
.zmmword
)
3916 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3919 else if (i
.types
[op
].bitfield
.ymmword
)
3921 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3924 else if (i
.types
[op
].bitfield
.xmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3929 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
3930 && op
== i
.broadcast
.operand
)
3932 switch (get_broadcast_bytes (&i
.tm
, true))
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3971 vec_length
= 3 << 5;
3979 i
.vex
.bytes
[3] |= vec_length
;
3980 /* Encode the broadcast bit. */
3981 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
3982 i
.vex
.bytes
[3] |= 0x10;
3984 else if (i
.rounding
.type
!= saeonly
)
3985 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3987 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3990 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
3994 process_immext (void)
3998 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3999 which is coded in the same place as an 8-bit immediate field
4000 would be. Here we fake an 8-bit immediate operand from the
4001 opcode suffix stored in tm.extension_opcode.
4003 AVX instructions also use this encoding, for some of
4004 3 argument instructions. */
4006 gas_assert (i
.imm_operands
<= 1
4008 || (is_any_vex_encoding (&i
.tm
)
4009 && i
.operands
<= 4)));
4011 exp
= &im_expressions
[i
.imm_operands
++];
4012 i
.op
[i
.operands
].imms
= exp
;
4013 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4015 exp
->X_op
= O_constant
;
4016 exp
->X_add_number
= i
.tm
.extension_opcode
;
4017 i
.tm
.extension_opcode
= None
;
4024 switch (i
.tm
.opcode_modifier
.prefixok
)
4032 as_bad (_("invalid instruction `%s' after `%s'"),
4033 insn_name (&i
.tm
), i
.hle_prefix
);
4036 if (i
.prefix
[LOCK_PREFIX
])
4038 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4042 case PrefixHLERelease
:
4043 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4045 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4049 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4051 as_bad (_("memory destination needed for instruction `%s'"
4052 " after `xrelease'"), insn_name (&i
.tm
));
4059 /* Encode aligned vector move as unaligned vector move. */
4062 encode_with_unaligned_vector_move (void)
4064 switch (i
.tm
.base_opcode
)
4066 case 0x28: /* Load instructions. */
4067 case 0x29: /* Store instructions. */
4068 /* movaps/movapd/vmovaps/vmovapd. */
4069 if (i
.tm
.opcode_space
== SPACE_0F
4070 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4071 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4073 case 0x6f: /* Load instructions. */
4074 case 0x7f: /* Store instructions. */
4075 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4076 if (i
.tm
.opcode_space
== SPACE_0F
4077 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4078 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4085 /* Try the shortest encoding by shortening operand size. */
4088 optimize_encoding (void)
4092 if (i
.tm
.mnem_off
== MN_lea
)
4095 lea symbol, %rN -> mov $symbol, %rN
4096 lea (%rM), %rN -> mov %rM, %rN
4097 lea (,%rM,1), %rN -> mov %rM, %rN
4099 and in 32-bit mode for 16-bit addressing
4101 lea (%rM), %rN -> movzx %rM, %rN
4103 and in 64-bit mode zap 32-bit addressing in favor of using a
4104 32-bit (or less) destination.
4106 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4108 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4109 i
.tm
.opcode_modifier
.size
= SIZE32
;
4110 i
.prefix
[ADDR_PREFIX
] = 0;
4113 if (!i
.index_reg
&& !i
.base_reg
)
4116 lea symbol, %rN -> mov $symbol, %rN
4118 if (flag_code
== CODE_64BIT
)
4120 /* Don't transform a relocation to a 16-bit one. */
4122 && i
.op
[0].disps
->X_op
!= O_constant
4123 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4126 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4127 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4129 i
.tm
.base_opcode
= 0xb8;
4130 i
.tm
.opcode_modifier
.modrm
= 0;
4131 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4132 i
.types
[0].bitfield
.imm32
= 1;
4135 i
.tm
.opcode_modifier
.size
= SIZE16
;
4136 i
.types
[0].bitfield
.imm16
= 1;
4141 /* Subject to further optimization below. */
4142 i
.tm
.base_opcode
= 0xc7;
4143 i
.tm
.extension_opcode
= 0;
4144 i
.types
[0].bitfield
.imm32s
= 1;
4145 i
.types
[0].bitfield
.baseindex
= 0;
4148 /* Outside of 64-bit mode address and operand sizes have to match if
4149 a relocation is involved, as otherwise we wouldn't (currently) or
4150 even couldn't express the relocation correctly. */
4151 else if (i
.op
[0].disps
4152 && i
.op
[0].disps
->X_op
!= O_constant
4153 && ((!i
.prefix
[ADDR_PREFIX
])
4154 != (flag_code
== CODE_32BIT
4155 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4156 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4158 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4159 destination is going to grow encoding size. */
4160 else if (flag_code
== CODE_16BIT
4161 && (optimize
<= 1 || optimize_for_space
)
4162 && !i
.prefix
[ADDR_PREFIX
]
4163 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4167 i
.tm
.base_opcode
= 0xb8;
4168 i
.tm
.opcode_modifier
.modrm
= 0;
4169 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4170 i
.types
[0].bitfield
.imm32
= 1;
4172 i
.types
[0].bitfield
.imm16
= 1;
4175 && i
.op
[0].disps
->X_op
== O_constant
4176 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4177 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4179 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4180 i
.op
[0].disps
->X_add_number
&= 0xffff;
4183 i
.tm
.operand_types
[0] = i
.types
[0];
4187 i
.op
[0].imms
= &im_expressions
[0];
4188 i
.op
[0].imms
->X_op
= O_absent
;
4191 else if (i
.op
[0].disps
4192 && (i
.op
[0].disps
->X_op
!= O_constant
4193 || i
.op
[0].disps
->X_add_number
))
4198 lea (%rM), %rN -> mov %rM, %rN
4199 lea (,%rM,1), %rN -> mov %rM, %rN
4200 lea (%rM), %rN -> movzx %rM, %rN
4202 const reg_entry
*addr_reg
;
4204 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4205 addr_reg
= i
.base_reg
;
4206 else if (!i
.base_reg
4207 && i
.index_reg
->reg_num
!= RegIZ
4208 && !i
.log2_scale_factor
)
4209 addr_reg
= i
.index_reg
;
4213 if (addr_reg
->reg_type
.bitfield
.word
4214 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4216 if (flag_code
!= CODE_32BIT
)
4218 i
.tm
.opcode_space
= SPACE_0F
;
4219 i
.tm
.base_opcode
= 0xb7;
4222 i
.tm
.base_opcode
= 0x8b;
4224 if (addr_reg
->reg_type
.bitfield
.dword
4225 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4226 i
.tm
.opcode_modifier
.size
= SIZE32
;
4228 i
.op
[0].regs
= addr_reg
;
4233 i
.disp_operands
= 0;
4234 i
.prefix
[ADDR_PREFIX
] = 0;
4235 i
.prefix
[SEG_PREFIX
] = 0;
4239 if (optimize_for_space
4240 && i
.tm
.mnem_off
== MN_test
4241 && i
.reg_operands
== 1
4242 && i
.imm_operands
== 1
4243 && !i
.types
[1].bitfield
.byte
4244 && i
.op
[0].imms
->X_op
== O_constant
4245 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4248 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4250 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4251 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4253 i
.types
[1].bitfield
.byte
= 1;
4254 /* Ignore the suffix. */
4256 /* Convert to byte registers. */
4257 if (i
.types
[1].bitfield
.word
)
4259 else if (i
.types
[1].bitfield
.dword
)
4263 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4268 else if (flag_code
== CODE_64BIT
4269 && i
.tm
.opcode_space
== SPACE_BASE
4270 && ((i
.types
[1].bitfield
.qword
4271 && i
.reg_operands
== 1
4272 && i
.imm_operands
== 1
4273 && i
.op
[0].imms
->X_op
== O_constant
4274 && ((i
.tm
.base_opcode
== 0xb8
4275 && i
.tm
.extension_opcode
== None
4276 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4277 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4278 && (i
.tm
.base_opcode
== 0x24
4279 || (i
.tm
.base_opcode
== 0x80
4280 && i
.tm
.extension_opcode
== 0x4)
4281 || i
.tm
.mnem_off
== MN_test
4282 || ((i
.tm
.base_opcode
| 1) == 0xc7
4283 && i
.tm
.extension_opcode
== 0x0)))
4284 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4285 && i
.tm
.base_opcode
== 0x83
4286 && i
.tm
.extension_opcode
== 0x4)))
4287 || (i
.types
[0].bitfield
.qword
4288 && ((i
.reg_operands
== 2
4289 && i
.op
[0].regs
== i
.op
[1].regs
4290 && (i
.tm
.mnem_off
== MN_xor
4291 || i
.tm
.mnem_off
== MN_sub
))
4292 || i
.tm
.mnem_off
== MN_clr
))))
4295 andq $imm31, %r64 -> andl $imm31, %r32
4296 andq $imm7, %r64 -> andl $imm7, %r32
4297 testq $imm31, %r64 -> testl $imm31, %r32
4298 xorq %r64, %r64 -> xorl %r32, %r32
4299 subq %r64, %r64 -> subl %r32, %r32
4300 movq $imm31, %r64 -> movl $imm31, %r32
4301 movq $imm32, %r64 -> movl $imm32, %r32
4303 i
.tm
.opcode_modifier
.size
= SIZE32
;
4306 i
.types
[0].bitfield
.imm32
= 1;
4307 i
.types
[0].bitfield
.imm32s
= 0;
4308 i
.types
[0].bitfield
.imm64
= 0;
4312 i
.types
[0].bitfield
.dword
= 1;
4313 i
.types
[0].bitfield
.qword
= 0;
4315 i
.types
[1].bitfield
.dword
= 1;
4316 i
.types
[1].bitfield
.qword
= 0;
4317 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4320 movq $imm31, %r64 -> movl $imm31, %r32
4321 movq $imm32, %r64 -> movl $imm32, %r32
4323 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4324 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4325 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4326 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4329 movq $imm31, %r64 -> movl $imm31, %r32
4331 i
.tm
.base_opcode
= 0xb8;
4332 i
.tm
.extension_opcode
= None
;
4333 i
.tm
.opcode_modifier
.w
= 0;
4334 i
.tm
.opcode_modifier
.modrm
= 0;
4338 else if (optimize
> 1
4339 && !optimize_for_space
4340 && i
.reg_operands
== 2
4341 && i
.op
[0].regs
== i
.op
[1].regs
4342 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4343 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4346 andb %rN, %rN -> testb %rN, %rN
4347 andw %rN, %rN -> testw %rN, %rN
4348 andq %rN, %rN -> testq %rN, %rN
4349 orb %rN, %rN -> testb %rN, %rN
4350 orw %rN, %rN -> testw %rN, %rN
4351 orq %rN, %rN -> testq %rN, %rN
4353 and outside of 64-bit mode
4355 andl %rN, %rN -> testl %rN, %rN
4356 orl %rN, %rN -> testl %rN, %rN
4358 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4360 else if (i
.tm
.base_opcode
== 0xba
4361 && i
.tm
.opcode_space
== SPACE_0F
4362 && i
.reg_operands
== 1
4363 && i
.op
[0].imms
->X_op
== O_constant
4364 && i
.op
[0].imms
->X_add_number
>= 0)
4367 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4368 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4369 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4371 With <BT> one of bts, btr, and bts also:
4372 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4373 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4378 if (i
.tm
.extension_opcode
!= 4)
4380 if (i
.types
[1].bitfield
.qword
4381 && i
.op
[0].imms
->X_add_number
< 32
4382 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4383 i
.tm
.opcode_modifier
.size
= SIZE32
;
4386 if (i
.types
[1].bitfield
.word
4387 && i
.op
[0].imms
->X_add_number
< 16)
4388 i
.tm
.opcode_modifier
.size
= SIZE32
;
4391 if (i
.op
[0].imms
->X_add_number
< 16)
4392 i
.tm
.opcode_modifier
.size
= SIZE16
;
4396 else if (i
.reg_operands
== 3
4397 && i
.op
[0].regs
== i
.op
[1].regs
4398 && !i
.types
[2].bitfield
.xmmword
4399 && (i
.tm
.opcode_modifier
.vex
4400 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4401 && is_evex_encoding (&i
.tm
)
4402 && (i
.vec_encoding
!= vex_encoding_evex
4403 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4404 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4405 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4406 && i
.types
[2].bitfield
.ymmword
))))
4407 && i
.tm
.opcode_space
== SPACE_0F
4408 && ((i
.tm
.base_opcode
| 2) == 0x57
4409 || i
.tm
.base_opcode
== 0xdf
4410 || i
.tm
.base_opcode
== 0xef
4411 || (i
.tm
.base_opcode
| 3) == 0xfb
4412 || i
.tm
.base_opcode
== 0x42
4413 || i
.tm
.base_opcode
== 0x47))
4416 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4418 EVEX VOP %zmmM, %zmmM, %zmmN
4419 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4420 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4421 EVEX VOP %ymmM, %ymmM, %ymmN
4422 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4423 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4424 VEX VOP %ymmM, %ymmM, %ymmN
4425 -> VEX VOP %xmmM, %xmmM, %xmmN
4426 VOP, one of vpandn and vpxor:
4427 VEX VOP %ymmM, %ymmM, %ymmN
4428 -> VEX VOP %xmmM, %xmmM, %xmmN
4429 VOP, one of vpandnd and vpandnq:
4430 EVEX VOP %zmmM, %zmmM, %zmmN
4431 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4432 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4433 EVEX VOP %ymmM, %ymmM, %ymmN
4434 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4435 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4436 VOP, one of vpxord and vpxorq:
4437 EVEX VOP %zmmM, %zmmM, %zmmN
4438 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4439 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4440 EVEX VOP %ymmM, %ymmM, %ymmN
4441 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4442 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4443 VOP, one of kxord and kxorq:
4444 VEX VOP %kM, %kM, %kN
4445 -> VEX kxorw %kM, %kM, %kN
4446 VOP, one of kandnd and kandnq:
4447 VEX VOP %kM, %kM, %kN
4448 -> VEX kandnw %kM, %kM, %kN
4450 if (is_evex_encoding (&i
.tm
))
4452 if (i
.vec_encoding
!= vex_encoding_evex
)
4454 i
.tm
.opcode_modifier
.vex
= VEX128
;
4455 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4456 i
.tm
.opcode_modifier
.evex
= 0;
4458 else if (optimize
> 1)
4459 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4463 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4465 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4466 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4469 i
.tm
.opcode_modifier
.vex
= VEX128
;
4471 if (i
.tm
.opcode_modifier
.vex
)
4472 for (j
= 0; j
< 3; j
++)
4474 i
.types
[j
].bitfield
.xmmword
= 1;
4475 i
.types
[j
].bitfield
.ymmword
= 0;
4478 else if (i
.vec_encoding
!= vex_encoding_evex
4479 && !i
.types
[0].bitfield
.zmmword
4480 && !i
.types
[1].bitfield
.zmmword
4482 && !i
.broadcast
.type
4483 && !i
.broadcast
.bytes
4484 && is_evex_encoding (&i
.tm
)
4485 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4486 || (i
.tm
.base_opcode
& ~4) == 0xdb
4487 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4488 && i
.tm
.extension_opcode
== None
)
4491 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4492 vmovdqu32 and vmovdqu64:
4493 EVEX VOP %xmmM, %xmmN
4494 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4495 EVEX VOP %ymmM, %ymmN
4496 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4498 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4500 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4502 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4504 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4505 VOP, one of vpand, vpandn, vpor, vpxor:
4506 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4507 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4508 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4509 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4510 EVEX VOP{d,q} mem, %xmmM, %xmmN
4511 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4512 EVEX VOP{d,q} mem, %ymmM, %ymmN
4513 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4515 for (j
= 0; j
< i
.operands
; j
++)
4516 if (operand_type_check (i
.types
[j
], disp
)
4517 && i
.op
[j
].disps
->X_op
== O_constant
)
4519 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4520 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4521 bytes, we choose EVEX Disp8 over VEX Disp32. */
4522 int evex_disp8
, vex_disp8
;
4523 unsigned int memshift
= i
.memshift
;
4524 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4526 evex_disp8
= fits_in_disp8 (n
);
4528 vex_disp8
= fits_in_disp8 (n
);
4529 if (evex_disp8
!= vex_disp8
)
4531 i
.memshift
= memshift
;
4535 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4538 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4539 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4540 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4541 i
.tm
.opcode_modifier
.vex
4542 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4543 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4544 /* VPAND, VPOR, and VPXOR are commutative. */
4545 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4546 i
.tm
.opcode_modifier
.commutative
= 1;
4547 i
.tm
.opcode_modifier
.evex
= 0;
4548 i
.tm
.opcode_modifier
.masking
= 0;
4549 i
.tm
.opcode_modifier
.broadcast
= 0;
4550 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4553 i
.types
[j
].bitfield
.disp8
4554 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4558 /* Return non-zero for load instruction. */
4564 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4565 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4569 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4570 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4571 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4575 if (i
.tm
.mnem_off
== MN_pop
)
4579 if (i
.tm
.opcode_space
== SPACE_BASE
)
4582 if (i
.tm
.base_opcode
== 0x9d
4583 || i
.tm
.base_opcode
== 0x61)
4586 /* movs, cmps, lods, scas. */
4587 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4591 if (base_opcode
== 0x6f
4592 || i
.tm
.base_opcode
== 0xd7)
4594 /* NB: For AMD-specific insns with implicit memory operands,
4595 they're intentionally not covered. */
4598 /* No memory operand. */
4599 if (!i
.mem_operands
)
4604 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4607 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4609 /* test, not, neg, mul, imul, div, idiv. */
4610 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4614 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4617 /* add, or, adc, sbb, and, sub, xor, cmp. */
4618 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4621 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4622 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4623 && i
.tm
.extension_opcode
!= 6)
4626 /* Check for x87 instructions. */
4627 if ((base_opcode
| 6) == 0xdf)
4629 /* Skip fst, fstp, fstenv, fstcw. */
4630 if (i
.tm
.base_opcode
== 0xd9
4631 && (i
.tm
.extension_opcode
== 2
4632 || i
.tm
.extension_opcode
== 3
4633 || i
.tm
.extension_opcode
== 6
4634 || i
.tm
.extension_opcode
== 7))
4637 /* Skip fisttp, fist, fistp, fstp. */
4638 if (i
.tm
.base_opcode
== 0xdb
4639 && (i
.tm
.extension_opcode
== 1
4640 || i
.tm
.extension_opcode
== 2
4641 || i
.tm
.extension_opcode
== 3
4642 || i
.tm
.extension_opcode
== 7))
4645 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4646 if (i
.tm
.base_opcode
== 0xdd
4647 && (i
.tm
.extension_opcode
== 1
4648 || i
.tm
.extension_opcode
== 2
4649 || i
.tm
.extension_opcode
== 3
4650 || i
.tm
.extension_opcode
== 6
4651 || i
.tm
.extension_opcode
== 7))
4654 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4655 if (i
.tm
.base_opcode
== 0xdf
4656 && (i
.tm
.extension_opcode
== 1
4657 || i
.tm
.extension_opcode
== 2
4658 || i
.tm
.extension_opcode
== 3
4659 || i
.tm
.extension_opcode
== 6
4660 || i
.tm
.extension_opcode
== 7))
4666 else if (i
.tm
.opcode_space
== SPACE_0F
)
4668 /* bt, bts, btr, btc. */
4669 if (i
.tm
.base_opcode
== 0xba
4670 && (i
.tm
.extension_opcode
| 3) == 7)
4673 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4674 if (i
.tm
.base_opcode
== 0xc7
4675 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4676 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4677 || i
.tm
.extension_opcode
== 6))
4680 /* fxrstor, ldmxcsr, xrstor. */
4681 if (i
.tm
.base_opcode
== 0xae
4682 && (i
.tm
.extension_opcode
== 1
4683 || i
.tm
.extension_opcode
== 2
4684 || i
.tm
.extension_opcode
== 5))
4687 /* lgdt, lidt, lmsw. */
4688 if (i
.tm
.base_opcode
== 0x01
4689 && (i
.tm
.extension_opcode
== 2
4690 || i
.tm
.extension_opcode
== 3
4691 || i
.tm
.extension_opcode
== 6))
4695 dest
= i
.operands
- 1;
4697 /* Check fake imm8 operand and 3 source operands. */
4698 if ((i
.tm
.opcode_modifier
.immext
4699 || i
.reg_operands
+ i
.mem_operands
== 4)
4700 && i
.types
[dest
].bitfield
.imm8
)
4703 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4704 if (i
.tm
.opcode_space
== SPACE_BASE
4705 && ((base_opcode
| 0x38) == 0x39
4706 || (base_opcode
| 2) == 0x87))
4709 if (i
.tm
.mnem_off
== MN_xadd
)
4712 /* Check for load instruction. */
4713 return (i
.types
[dest
].bitfield
.class != ClassNone
4714 || i
.types
[dest
].bitfield
.instance
== Accum
);
4717 /* Output lfence, 0xfaee8, after instruction. */
4720 insert_lfence_after (void)
4722 if (lfence_after_load
&& load_insn_p ())
4724 /* There are also two REP string instructions that require
4725 special treatment. Specifically, the compare string (CMPS)
4726 and scan string (SCAS) instructions set EFLAGS in a manner
4727 that depends on the data being compared/scanned. When used
4728 with a REP prefix, the number of iterations may therefore
4729 vary depending on this data. If the data is a program secret
4730 chosen by the adversary using an LVI method,
4731 then this data-dependent behavior may leak some aspect
4733 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4734 && i
.prefix
[REP_PREFIX
])
4736 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4739 char *p
= frag_more (3);
4746 /* Output lfence, 0xfaee8, before instruction. */
4749 insert_lfence_before (void)
4753 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4756 if (i
.tm
.base_opcode
== 0xff
4757 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4759 /* Insert lfence before indirect branch if needed. */
4761 if (lfence_before_indirect_branch
== lfence_branch_none
)
4764 if (i
.operands
!= 1)
4767 if (i
.reg_operands
== 1)
4769 /* Indirect branch via register. Don't insert lfence with
4770 -mlfence-after-load=yes. */
4771 if (lfence_after_load
4772 || lfence_before_indirect_branch
== lfence_branch_memory
)
4775 else if (i
.mem_operands
== 1
4776 && lfence_before_indirect_branch
!= lfence_branch_register
)
4778 as_warn (_("indirect `%s` with memory operand should be avoided"),
4785 if (last_insn
.kind
!= last_insn_other
4786 && last_insn
.seg
== now_seg
)
4788 as_warn_where (last_insn
.file
, last_insn
.line
,
4789 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4790 last_insn
.name
, insn_name (&i
.tm
));
4801 /* Output or/not/shl and lfence before near ret. */
4802 if (lfence_before_ret
!= lfence_before_ret_none
4803 && (i
.tm
.base_opcode
| 1) == 0xc3)
4805 if (last_insn
.kind
!= last_insn_other
4806 && last_insn
.seg
== now_seg
)
4808 as_warn_where (last_insn
.file
, last_insn
.line
,
4809 _("`%s` skips -mlfence-before-ret on `%s`"),
4810 last_insn
.name
, insn_name (&i
.tm
));
4814 /* Near ret ingore operand size override under CPU64. */
4815 char prefix
= flag_code
== CODE_64BIT
4817 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4819 if (lfence_before_ret
== lfence_before_ret_not
)
4821 /* not: 0xf71424, may add prefix
4822 for operand size override or 64-bit code. */
4823 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4837 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4840 if (lfence_before_ret
== lfence_before_ret_or
)
4842 /* or: 0x830c2400, may add prefix
4843 for operand size override or 64-bit code. */
4849 /* shl: 0xc1242400, may add prefix
4850 for operand size override or 64-bit code. */
4865 /* Shared helper for md_assemble() and s_insn(). */
4866 static void init_globals (void)
4870 memset (&i
, '\0', sizeof (i
));
4871 i
.rounding
.type
= rc_none
;
4872 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4873 i
.reloc
[j
] = NO_RELOC
;
4874 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4875 memset (im_expressions
, '\0', sizeof (im_expressions
));
4876 save_stack_p
= save_stack
;
4879 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
4880 parsing pass. Instead of introducing a rarely use new insn attribute this
4881 utilizes a common pattern between affected templates. It is deemed
4882 acceptable that this will lead to unnecessary pass 2 preparations in a
4883 limited set of cases. */
4884 static INLINE
bool may_need_pass2 (const insn_template
*t
)
4886 return t
->opcode_modifier
.sse2avx
4887 /* Note that all SSE2AVX templates have at least one operand. */
4888 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
4889 : (t
->opcode_space
== SPACE_0F
4890 && (t
->base_opcode
| 1) == 0xbf)
4891 || (t
->opcode_space
== SPACE_BASE
4892 && t
->base_opcode
== 0x63);
4895 /* This is the guts of the machine-dependent assembler. LINE points to a
4896 machine dependent instruction. This function is supposed to emit
4897 the frags/bytes it assembles to. */
4900 md_assemble (char *line
)
4903 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
4904 const char *end
, *pass1_mnem
= NULL
;
4905 enum i386_error pass1_err
= 0;
4906 const insn_template
*t
;
4908 /* Initialize globals. */
4909 current_templates
= NULL
;
4913 /* First parse an instruction mnemonic & call i386_operand for the operands.
4914 We assume that the scrubber has arranged it so that line[0] is the valid
4915 start of a (possibly prefixed) mnemonic. */
4917 end
= parse_insn (line
, mnemonic
, false);
4920 if (pass1_mnem
!= NULL
)
4922 if (i
.error
!= no_error
)
4924 gas_assert (current_templates
!= NULL
);
4925 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
4927 /* No point in trying a 2nd pass - it'll only find the same suffix
4929 mnem_suffix
= i
.suffix
;
4934 t
= current_templates
->start
;
4935 if (may_need_pass2 (t
))
4937 /* Make a copy of the full line in case we need to retry. */
4938 copy
= xstrdup (line
);
4941 mnem_suffix
= i
.suffix
;
4943 line
= parse_operands (line
, mnemonic
);
4951 /* Now we've parsed the mnemonic into a set of templates, and have the
4952 operands at hand. */
4954 /* All Intel opcodes have reversed operands except for "bound", "enter",
4955 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4956 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
4957 intersegment "jmp" and "call" instructions with 2 immediate operands so
4958 that the immediate segment precedes the offset consistently in Intel and
4962 && (t
->mnem_off
!= MN_bound
)
4963 && !startswith (mnemonic
, "invlpg")
4964 && !startswith (mnemonic
, "monitor")
4965 && !startswith (mnemonic
, "mwait")
4966 && (t
->mnem_off
!= MN_pvalidate
)
4967 && !startswith (mnemonic
, "rmp")
4968 && (t
->mnem_off
!= MN_tpause
)
4969 && (t
->mnem_off
!= MN_umwait
)
4970 && !(i
.operands
== 2
4971 && operand_type_check (i
.types
[0], imm
)
4972 && operand_type_check (i
.types
[1], imm
)))
4975 /* The order of the immediates should be reversed
4976 for 2 immediates extrq and insertq instructions */
4977 if (i
.imm_operands
== 2
4978 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
4979 swap_2_operands (0, 1);
4984 if (i
.disp_operands
&& !optimize_disp (t
))
4987 /* Next, we find a template that matches the given insn,
4988 making sure the overlap of the given operands types is consistent
4989 with the template operand types. */
4991 if (!(t
= match_template (mnem_suffix
)))
4993 const char *err_msg
;
4995 if (copy
&& !mnem_suffix
)
5000 pass1_err
= i
.error
;
5001 pass1_mnem
= insn_name (current_templates
->start
);
5005 /* If a non-/only-64bit template (group) was found in pass 1, and if
5006 _some_ template (group) was found in pass 2, squash pass 1's
5008 if (pass1_err
== unsupported_64bit
)
5014 switch (pass1_mnem
? pass1_err
: i
.error
)
5018 case operand_size_mismatch
:
5019 err_msg
= _("operand size mismatch");
5021 case operand_type_mismatch
:
5022 err_msg
= _("operand type mismatch");
5024 case register_type_mismatch
:
5025 err_msg
= _("register type mismatch");
5027 case number_of_operands_mismatch
:
5028 err_msg
= _("number of operands mismatch");
5030 case invalid_instruction_suffix
:
5031 err_msg
= _("invalid instruction suffix");
5034 err_msg
= _("constant doesn't fit in 4 bits");
5036 case unsupported_with_intel_mnemonic
:
5037 err_msg
= _("unsupported with Intel mnemonic");
5039 case unsupported_syntax
:
5040 err_msg
= _("unsupported syntax");
5043 as_bad (_("unsupported instruction `%s'"),
5044 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5046 case unsupported_on_arch
:
5047 as_bad (_("`%s' is not supported on `%s%s'"),
5048 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5049 cpu_arch_name
? cpu_arch_name
: default_arch
,
5050 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5052 case unsupported_64bit
:
5053 if (ISLOWER (mnem_suffix
))
5055 if (flag_code
== CODE_64BIT
)
5056 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5057 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5060 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5061 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5066 if (flag_code
== CODE_64BIT
)
5067 as_bad (_("`%s' is not supported in 64-bit mode"),
5068 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5070 as_bad (_("`%s' is only supported in 64-bit mode"),
5071 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5074 case invalid_sib_address
:
5075 err_msg
= _("invalid SIB address");
5077 case invalid_vsib_address
:
5078 err_msg
= _("invalid VSIB address");
5080 case invalid_vector_register_set
:
5081 err_msg
= _("mask, index, and destination registers must be distinct");
5083 case invalid_tmm_register_set
:
5084 err_msg
= _("all tmm registers must be distinct");
5086 case invalid_dest_and_src_register_set
:
5087 err_msg
= _("destination and source registers must be distinct");
5089 case unsupported_vector_index_register
:
5090 err_msg
= _("unsupported vector index register");
5092 case unsupported_broadcast
:
5093 err_msg
= _("unsupported broadcast");
5095 case broadcast_needed
:
5096 err_msg
= _("broadcast is needed for operand of such type");
5098 case unsupported_masking
:
5099 err_msg
= _("unsupported masking");
5101 case mask_not_on_destination
:
5102 err_msg
= _("mask not on destination operand");
5104 case no_default_mask
:
5105 err_msg
= _("default mask isn't allowed");
5107 case unsupported_rc_sae
:
5108 err_msg
= _("unsupported static rounding/sae");
5110 case invalid_register_operand
:
5111 err_msg
= _("invalid register operand");
5114 as_bad (_("%s for `%s'"), err_msg
,
5115 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5121 if (sse_check
!= check_none
5122 /* The opcode space check isn't strictly needed; it's there only to
5123 bypass the logic below when easily possible. */
5124 && t
->opcode_space
>= SPACE_0F
5125 && t
->opcode_space
<= SPACE_0F3A
5126 && !i
.tm
.cpu_flags
.bitfield
.cpusse4a
5127 && !is_any_vex_encoding (t
))
5131 for (j
= 0; j
< t
->operands
; ++j
)
5133 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5135 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5139 if (j
>= t
->operands
&& simd
)
5140 (sse_check
== check_warning
5142 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5145 if (i
.tm
.opcode_modifier
.fwait
)
5146 if (!add_prefix (FWAIT_OPCODE
))
5149 /* Check if REP prefix is OK. */
5150 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5152 as_bad (_("invalid instruction `%s' after `%s'"),
5153 insn_name (&i
.tm
), i
.rep_prefix
);
5157 /* Check for lock without a lockable instruction. Destination operand
5158 must be memory unless it is xchg (0x86). */
5159 if (i
.prefix
[LOCK_PREFIX
])
5161 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5162 || i
.mem_operands
== 0
5163 || (i
.tm
.base_opcode
!= 0x86
5164 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5166 as_bad (_("expecting lockable instruction after `lock'"));
5170 /* Zap the redundant prefix from XCHG when optimizing. */
5171 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5172 i
.prefix
[LOCK_PREFIX
] = 0;
5175 if (is_any_vex_encoding (&i
.tm
)
5176 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5177 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5179 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5180 if (i
.prefix
[DATA_PREFIX
])
5182 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5186 /* Don't allow e.g. KMOV in TLS code sequences. */
5187 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5190 case BFD_RELOC_386_TLS_GOTIE
:
5191 case BFD_RELOC_386_TLS_LE_32
:
5192 case BFD_RELOC_X86_64_GOTTPOFF
:
5193 case BFD_RELOC_X86_64_TLSLD
:
5194 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5201 /* Check if HLE prefix is OK. */
5202 if (i
.hle_prefix
&& !check_hle ())
5205 /* Check BND prefix. */
5206 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5207 as_bad (_("expecting valid branch instruction after `bnd'"));
5209 /* Check NOTRACK prefix. */
5210 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5211 as_bad (_("expecting indirect branch instruction after `notrack'"));
5213 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5215 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5216 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5217 else if (flag_code
!= CODE_16BIT
5218 ? i
.prefix
[ADDR_PREFIX
]
5219 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5220 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5223 /* Insert BND prefix. */
5224 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5226 if (!i
.prefix
[BND_PREFIX
])
5227 add_prefix (BND_PREFIX_OPCODE
);
5228 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5230 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5231 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5235 /* Check string instruction segment overrides. */
5236 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5238 gas_assert (i
.mem_operands
);
5239 if (!check_string ())
5241 i
.disp_operands
= 0;
5244 /* The memory operand of (%dx) should be only used with input/output
5245 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5246 if (i
.input_output_operand
5247 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5248 || i
.tm
.opcode_space
!= SPACE_BASE
))
5250 as_bad (_("input/output port address isn't allowed with `%s'"),
5255 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5256 optimize_encoding ();
5258 if (use_unaligned_vector_move
)
5259 encode_with_unaligned_vector_move ();
5261 if (!process_suffix ())
5264 /* Check if IP-relative addressing requirements can be satisfied. */
5265 if (i
.tm
.cpu_flags
.bitfield
.cpuprefetchi
5266 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5267 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5269 /* Update operand types and check extended states. */
5270 for (j
= 0; j
< i
.operands
; j
++)
5272 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5273 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5278 i
.xstate
|= xstate_mmx
;
5281 i
.xstate
|= xstate_mask
;
5284 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5285 i
.xstate
|= xstate_tmm
;
5286 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5287 i
.xstate
|= xstate_zmm
;
5288 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5289 i
.xstate
|= xstate_ymm
;
5290 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5291 i
.xstate
|= xstate_xmm
;
5296 /* Make still unresolved immediate matches conform to size of immediate
5297 given in i.suffix. */
5298 if (!finalize_imm ())
5301 if (i
.types
[0].bitfield
.imm1
)
5302 i
.imm_operands
= 0; /* kludge for shift insns. */
5304 /* For insns with operands there are more diddles to do to the opcode. */
5307 if (!process_operands ())
5310 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5312 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5313 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5316 if (is_any_vex_encoding (&i
.tm
))
5318 if (!cpu_arch_flags
.bitfield
.cpui286
)
5320 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5325 /* Check for explicit REX prefix. */
5326 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5328 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5332 if (i
.tm
.opcode_modifier
.vex
)
5333 build_vex_prefix (t
);
5335 build_evex_prefix ();
5337 /* The individual REX.RXBW bits got consumed. */
5338 i
.rex
&= REX_OPCODE
;
5341 /* Handle conversion of 'int $3' --> special int3 insn. */
5342 if (i
.tm
.mnem_off
== MN_int
5343 && i
.op
[0].imms
->X_add_number
== 3)
5345 i
.tm
.base_opcode
= INT3_OPCODE
;
5349 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5350 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5351 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5352 && i
.op
[0].disps
->X_op
== O_constant
)
5354 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5355 the absolute address given by the constant. Since ix86 jumps and
5356 calls are pc relative, we need to generate a reloc. */
5357 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5358 i
.op
[0].disps
->X_op
= O_symbol
;
5361 /* For 8 bit registers we need an empty rex prefix. Also if the
5362 instruction already has a prefix, we need to convert old
5363 registers to new ones. */
5365 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5366 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5367 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5368 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5369 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5370 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5375 i
.rex
|= REX_OPCODE
;
5376 for (x
= 0; x
< 2; x
++)
5378 /* Look for 8 bit operand that uses old registers. */
5379 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5380 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5382 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5383 /* In case it is "hi" register, give up. */
5384 if (i
.op
[x
].regs
->reg_num
> 3)
5385 as_bad (_("can't encode register '%s%s' in an "
5386 "instruction requiring REX prefix."),
5387 register_prefix
, i
.op
[x
].regs
->reg_name
);
5389 /* Otherwise it is equivalent to the extended register.
5390 Since the encoding doesn't change this is merely
5391 cosmetic cleanup for debug output. */
5393 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5398 if (i
.rex
== 0 && i
.rex_encoding
)
5400 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5401 that uses legacy register. If it is "hi" register, don't add
5402 the REX_OPCODE byte. */
5404 for (x
= 0; x
< 2; x
++)
5405 if (i
.types
[x
].bitfield
.class == Reg
5406 && i
.types
[x
].bitfield
.byte
5407 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5408 && i
.op
[x
].regs
->reg_num
> 3)
5410 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5411 i
.rex_encoding
= false;
5420 add_prefix (REX_OPCODE
| i
.rex
);
5422 insert_lfence_before ();
5424 /* We are ready to output the insn. */
5427 insert_lfence_after ();
5429 last_insn
.seg
= now_seg
;
5431 if (i
.tm
.opcode_modifier
.isprefix
)
5433 last_insn
.kind
= last_insn_prefix
;
5434 last_insn
.name
= insn_name (&i
.tm
);
5435 last_insn
.file
= as_where (&last_insn
.line
);
5438 last_insn
.kind
= last_insn_other
;
5441 /* The Q suffix is generally valid only in 64-bit mode, with very few
5442 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5443 and fisttp only one of their two templates is matched below: That's
5444 sufficient since other relevant attributes are the same between both
5445 respective templates. */
5446 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5448 return flag_code
== CODE_64BIT
5449 || (t
->opcode_space
== SPACE_BASE
5450 && t
->base_opcode
== 0xdf
5451 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5452 || t
->mnem_off
== MN_cmpxchg8b
;
5456 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5458 const char *l
= line
, *token_start
= l
;
5460 bool pass1
= !current_templates
;
5462 const insn_template
*t
;
5468 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5473 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5475 as_bad (_("no such instruction: `%s'"), token_start
);
5480 if (!is_space_char (*l
)
5481 && *l
!= END_OF_INSN
5483 || (*l
!= PREFIX_SEPARATOR
5488 as_bad (_("invalid character %s in mnemonic"),
5489 output_invalid (*l
));
5492 if (token_start
== l
)
5494 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5495 as_bad (_("expecting prefix; got nothing"));
5497 as_bad (_("expecting mnemonic; got nothing"));
5501 /* Look up instruction (or prefix) via hash table. */
5502 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5504 if (*l
!= END_OF_INSN
5505 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5506 && current_templates
5507 && current_templates
->start
->opcode_modifier
.isprefix
)
5509 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5511 as_bad ((flag_code
!= CODE_64BIT
5512 ? _("`%s' is only supported in 64-bit mode")
5513 : _("`%s' is not supported in 64-bit mode")),
5514 insn_name (current_templates
->start
));
5517 /* If we are in 16-bit mode, do not allow addr16 or data16.
5518 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5519 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5520 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5521 && flag_code
!= CODE_64BIT
5522 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5523 ^ (flag_code
== CODE_16BIT
)))
5525 as_bad (_("redundant %s prefix"),
5526 insn_name (current_templates
->start
));
5530 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5532 /* Handle pseudo prefixes. */
5533 switch (current_templates
->start
->extension_opcode
)
5537 i
.disp_encoding
= disp_encoding_8bit
;
5541 i
.disp_encoding
= disp_encoding_16bit
;
5545 i
.disp_encoding
= disp_encoding_32bit
;
5549 i
.dir_encoding
= dir_encoding_load
;
5553 i
.dir_encoding
= dir_encoding_store
;
5557 i
.vec_encoding
= vex_encoding_vex
;
5561 i
.vec_encoding
= vex_encoding_vex3
;
5565 i
.vec_encoding
= vex_encoding_evex
;
5569 i
.rex_encoding
= true;
5571 case Prefix_NoOptimize
:
5573 i
.no_optimize
= true;
5581 /* Add prefix, checking for repeated prefixes. */
5582 switch (add_prefix (current_templates
->start
->base_opcode
))
5587 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5588 i
.notrack_prefix
= insn_name (current_templates
->start
);
5591 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5592 i
.hle_prefix
= insn_name (current_templates
->start
);
5593 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5594 i
.bnd_prefix
= insn_name (current_templates
->start
);
5596 i
.rep_prefix
= insn_name (current_templates
->start
);
5602 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5612 if (!current_templates
)
5614 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5615 Check if we should swap operand or force 32bit displacement in
5617 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5618 i
.dir_encoding
= dir_encoding_swap
;
5619 else if (mnem_p
- 3 == dot_p
5622 i
.disp_encoding
= disp_encoding_8bit
;
5623 else if (mnem_p
- 4 == dot_p
5627 i
.disp_encoding
= disp_encoding_32bit
;
5632 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5635 if (!current_templates
|| !pass1
)
5637 current_templates
= NULL
;
5640 if (mnem_p
> mnemonic
)
5642 /* See if we can get a match by trimming off a suffix. */
5645 case WORD_MNEM_SUFFIX
:
5646 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5647 i
.suffix
= SHORT_MNEM_SUFFIX
;
5650 case BYTE_MNEM_SUFFIX
:
5651 case QWORD_MNEM_SUFFIX
:
5652 i
.suffix
= mnem_p
[-1];
5655 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5657 case SHORT_MNEM_SUFFIX
:
5658 case LONG_MNEM_SUFFIX
:
5661 i
.suffix
= mnem_p
[-1];
5664 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5672 if (intel_float_operand (mnemonic
) == 1)
5673 i
.suffix
= SHORT_MNEM_SUFFIX
;
5675 i
.suffix
= LONG_MNEM_SUFFIX
;
5678 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5680 /* For compatibility reasons accept MOVSD and CMPSD without
5681 operands even in AT&T mode. */
5682 else if (*l
== END_OF_INSN
5683 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5687 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5688 if (current_templates
!= NULL
5690 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5691 && current_templates
->start
->opcode_space
5693 && mnem_p
[-2] == 's')
5695 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5696 mnemonic
, mnemonic
);
5697 i
.suffix
= LONG_MNEM_SUFFIX
;
5701 current_templates
= NULL
;
5709 if (!current_templates
)
5712 as_bad (_("no such instruction: `%s'"), token_start
);
5717 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5718 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5720 /* Check for a branch hint. We allow ",pt" and ",pn" for
5721 predict taken and predict not taken respectively.
5722 I'm not sure that branch hints actually do anything on loop
5723 and jcxz insns (JumpByte) for current Pentium4 chips. They
5724 may work in the future and it doesn't hurt to accept them
5726 if (l
[0] == ',' && l
[1] == 'p')
5730 if (!add_prefix (DS_PREFIX_OPCODE
))
5734 else if (l
[2] == 'n')
5736 if (!add_prefix (CS_PREFIX_OPCODE
))
5742 /* Any other comma loses. */
5745 as_bad (_("invalid character %s in mnemonic"),
5746 output_invalid (*l
));
5750 /* Check if instruction is supported on specified architecture. */
5752 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5754 supported
|= cpu_flags_match (t
);
5756 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5757 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5759 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5765 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5766 i
.error
= unsupported_on_arch
;
5768 i
.error
= unsupported_64bit
;
5775 parse_operands (char *l
, const char *mnemonic
)
5779 /* 1 if operand is pending after ','. */
5780 unsigned int expecting_operand
= 0;
5782 while (*l
!= END_OF_INSN
)
5784 /* Non-zero if operand parens not balanced. */
5785 unsigned int paren_not_balanced
= 0;
5786 /* True if inside double quotes. */
5787 bool in_quotes
= false;
5789 /* Skip optional white space before operand. */
5790 if (is_space_char (*l
))
5792 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5794 as_bad (_("invalid character %s before operand %d"),
5795 output_invalid (*l
),
5799 token_start
= l
; /* After white space. */
5800 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5802 if (*l
== END_OF_INSN
)
5806 as_bad (_("unbalanced double quotes in operand %d."),
5810 if (paren_not_balanced
)
5812 know (!intel_syntax
);
5813 as_bad (_("unbalanced parenthesis in operand %d."),
5818 break; /* we are done */
5820 else if (*l
== '\\' && l
[1] == '"')
5823 in_quotes
= !in_quotes
;
5824 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5826 as_bad (_("invalid character %s in operand %d"),
5827 output_invalid (*l
),
5831 if (!intel_syntax
&& !in_quotes
)
5834 ++paren_not_balanced
;
5836 --paren_not_balanced
;
5840 if (l
!= token_start
)
5841 { /* Yes, we've read in another operand. */
5842 unsigned int operand_ok
;
5843 this_operand
= i
.operands
++;
5844 if (i
.operands
> MAX_OPERANDS
)
5846 as_bad (_("spurious operands; (%d operands/instruction max)"),
5850 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5851 /* Now parse operand adding info to 'i' as we go along. */
5852 END_STRING_AND_SAVE (l
);
5854 if (i
.mem_operands
> 1)
5856 as_bad (_("too many memory references for `%s'"),
5863 i386_intel_operand (token_start
,
5864 intel_float_operand (mnemonic
));
5866 operand_ok
= i386_att_operand (token_start
);
5868 RESTORE_END_STRING (l
);
5874 if (expecting_operand
)
5876 expecting_operand_after_comma
:
5877 as_bad (_("expecting operand after ','; got nothing"));
5882 as_bad (_("expecting operand before ','; got nothing"));
5887 /* Now *l must be either ',' or END_OF_INSN. */
5890 if (*++l
== END_OF_INSN
)
5892 /* Just skip it, if it's \n complain. */
5893 goto expecting_operand_after_comma
;
5895 expecting_operand
= 1;
5902 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5904 union i386_op temp_op
;
5905 i386_operand_type temp_type
;
5906 unsigned int temp_flags
;
5907 enum bfd_reloc_code_real temp_reloc
;
5909 temp_type
= i
.types
[xchg2
];
5910 i
.types
[xchg2
] = i
.types
[xchg1
];
5911 i
.types
[xchg1
] = temp_type
;
5913 temp_flags
= i
.flags
[xchg2
];
5914 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5915 i
.flags
[xchg1
] = temp_flags
;
5917 temp_op
= i
.op
[xchg2
];
5918 i
.op
[xchg2
] = i
.op
[xchg1
];
5919 i
.op
[xchg1
] = temp_op
;
5921 temp_reloc
= i
.reloc
[xchg2
];
5922 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5923 i
.reloc
[xchg1
] = temp_reloc
;
5927 if (i
.mask
.operand
== xchg1
)
5928 i
.mask
.operand
= xchg2
;
5929 else if (i
.mask
.operand
== xchg2
)
5930 i
.mask
.operand
= xchg1
;
5932 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
5934 if (i
.broadcast
.operand
== xchg1
)
5935 i
.broadcast
.operand
= xchg2
;
5936 else if (i
.broadcast
.operand
== xchg2
)
5937 i
.broadcast
.operand
= xchg1
;
5942 swap_operands (void)
5948 swap_2_operands (1, i
.operands
- 2);
5952 swap_2_operands (0, i
.operands
- 1);
5958 if (i
.mem_operands
== 2)
5960 const reg_entry
*temp_seg
;
5961 temp_seg
= i
.seg
[0];
5962 i
.seg
[0] = i
.seg
[1];
5963 i
.seg
[1] = temp_seg
;
5967 /* Try to ensure constant immediates are represented in the smallest
5972 char guess_suffix
= 0;
5976 guess_suffix
= i
.suffix
;
5977 else if (i
.reg_operands
)
5979 /* Figure out a suffix from the last register operand specified.
5980 We can't do this properly yet, i.e. excluding special register
5981 instances, but the following works for instructions with
5982 immediates. In any case, we can't set i.suffix yet. */
5983 for (op
= i
.operands
; --op
>= 0;)
5984 if (i
.types
[op
].bitfield
.class != Reg
)
5986 else if (i
.types
[op
].bitfield
.byte
)
5988 guess_suffix
= BYTE_MNEM_SUFFIX
;
5991 else if (i
.types
[op
].bitfield
.word
)
5993 guess_suffix
= WORD_MNEM_SUFFIX
;
5996 else if (i
.types
[op
].bitfield
.dword
)
5998 guess_suffix
= LONG_MNEM_SUFFIX
;
6001 else if (i
.types
[op
].bitfield
.qword
)
6003 guess_suffix
= QWORD_MNEM_SUFFIX
;
6007 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6008 guess_suffix
= WORD_MNEM_SUFFIX
;
6010 for (op
= i
.operands
; --op
>= 0;)
6011 if (operand_type_check (i
.types
[op
], imm
))
6013 switch (i
.op
[op
].imms
->X_op
)
6016 /* If a suffix is given, this operand may be shortened. */
6017 switch (guess_suffix
)
6019 case LONG_MNEM_SUFFIX
:
6020 i
.types
[op
].bitfield
.imm32
= 1;
6021 i
.types
[op
].bitfield
.imm64
= 1;
6023 case WORD_MNEM_SUFFIX
:
6024 i
.types
[op
].bitfield
.imm16
= 1;
6025 i
.types
[op
].bitfield
.imm32
= 1;
6026 i
.types
[op
].bitfield
.imm32s
= 1;
6027 i
.types
[op
].bitfield
.imm64
= 1;
6029 case BYTE_MNEM_SUFFIX
:
6030 i
.types
[op
].bitfield
.imm8
= 1;
6031 i
.types
[op
].bitfield
.imm8s
= 1;
6032 i
.types
[op
].bitfield
.imm16
= 1;
6033 i
.types
[op
].bitfield
.imm32
= 1;
6034 i
.types
[op
].bitfield
.imm32s
= 1;
6035 i
.types
[op
].bitfield
.imm64
= 1;
6039 /* If this operand is at most 16 bits, convert it
6040 to a signed 16 bit number before trying to see
6041 whether it will fit in an even smaller size.
6042 This allows a 16-bit operand such as $0xffe0 to
6043 be recognised as within Imm8S range. */
6044 if ((i
.types
[op
].bitfield
.imm16
)
6045 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6047 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6048 ^ 0x8000) - 0x8000);
6051 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6052 if ((i
.types
[op
].bitfield
.imm32
)
6053 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6055 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6056 ^ ((offsetT
) 1 << 31))
6057 - ((offsetT
) 1 << 31));
6061 = operand_type_or (i
.types
[op
],
6062 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6064 /* We must avoid matching of Imm32 templates when 64bit
6065 only immediate is available. */
6066 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6067 i
.types
[op
].bitfield
.imm32
= 0;
6074 /* Symbols and expressions. */
6076 /* Convert symbolic operand to proper sizes for matching, but don't
6077 prevent matching a set of insns that only supports sizes other
6078 than those matching the insn suffix. */
6080 i386_operand_type mask
, allowed
;
6081 const insn_template
*t
= current_templates
->start
;
6083 operand_type_set (&mask
, 0);
6084 switch (guess_suffix
)
6086 case QWORD_MNEM_SUFFIX
:
6087 mask
.bitfield
.imm64
= 1;
6088 mask
.bitfield
.imm32s
= 1;
6090 case LONG_MNEM_SUFFIX
:
6091 mask
.bitfield
.imm32
= 1;
6093 case WORD_MNEM_SUFFIX
:
6094 mask
.bitfield
.imm16
= 1;
6096 case BYTE_MNEM_SUFFIX
:
6097 mask
.bitfield
.imm8
= 1;
6103 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6104 while (++t
< current_templates
->end
)
6106 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6107 allowed
= operand_type_and (allowed
, mask
);
6110 if (!operand_type_all_zero (&allowed
))
6111 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6118 /* Try to use the smallest displacement type too. */
6120 optimize_disp (const insn_template
*t
)
6124 if (!want_disp32 (t
)
6125 && (!t
->opcode_modifier
.jump
6126 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6128 for (op
= 0; op
< i
.operands
; ++op
)
6130 const expressionS
*exp
= i
.op
[op
].disps
;
6132 if (!operand_type_check (i
.types
[op
], disp
))
6135 if (exp
->X_op
!= O_constant
)
6138 /* Since displacement is signed extended to 64bit, don't allow
6139 disp32 if it is out of range. */
6140 if (fits_in_signed_long (exp
->X_add_number
))
6143 i
.types
[op
].bitfield
.disp32
= 0;
6144 if (i
.types
[op
].bitfield
.baseindex
)
6146 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6147 (uint64_t) exp
->X_add_number
);
6153 /* Don't optimize displacement for movabs since it only takes 64bit
6155 if (i
.disp_encoding
> disp_encoding_8bit
6156 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6159 for (op
= i
.operands
; op
-- > 0;)
6160 if (operand_type_check (i
.types
[op
], disp
))
6162 if (i
.op
[op
].disps
->X_op
== O_constant
)
6164 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6166 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6168 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6169 i
.op
[op
].disps
= NULL
;
6174 if (i
.types
[op
].bitfield
.disp16
6175 && fits_in_unsigned_word (op_disp
))
6177 /* If this operand is at most 16 bits, convert
6178 to a signed 16 bit number and don't use 64bit
6180 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6181 i
.types
[op
].bitfield
.disp64
= 0;
6185 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6186 if ((flag_code
!= CODE_64BIT
6187 ? i
.types
[op
].bitfield
.disp32
6189 && (!t
->opcode_modifier
.jump
6190 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6191 && fits_in_unsigned_long (op_disp
))
6193 /* If this operand is at most 32 bits, convert
6194 to a signed 32 bit number and don't use 64bit
6196 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6197 i
.types
[op
].bitfield
.disp64
= 0;
6198 i
.types
[op
].bitfield
.disp32
= 1;
6201 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6203 i
.types
[op
].bitfield
.disp64
= 0;
6204 i
.types
[op
].bitfield
.disp32
= 1;
6207 if ((i
.types
[op
].bitfield
.disp32
6208 || i
.types
[op
].bitfield
.disp16
)
6209 && fits_in_disp8 (op_disp
))
6210 i
.types
[op
].bitfield
.disp8
= 1;
6212 i
.op
[op
].disps
->X_add_number
= op_disp
;
6214 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6215 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6217 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6218 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6219 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6222 /* We only support 64bit displacement on constants. */
6223 i
.types
[op
].bitfield
.disp64
= 0;
6229 /* Return 1 if there is a match in broadcast bytes between operand
6230 GIVEN and instruction template T. */
6233 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6235 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6236 && i
.types
[given
].bitfield
.byte
)
6237 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6238 && i
.types
[given
].bitfield
.word
)
6239 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6240 && i
.types
[given
].bitfield
.dword
)
6241 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6242 && i
.types
[given
].bitfield
.qword
));
6245 /* Check if operands are valid for the instruction. */
6248 check_VecOperands (const insn_template
*t
)
6253 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6254 any one operand are implicity requiring AVX512VL support if the actual
6255 operand size is YMMword or XMMword. Since this function runs after
6256 template matching, there's no need to check for YMMword/XMMword in
6258 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
6259 if (!cpu_flags_all_zero (&cpu
)
6260 && !t
->cpu_flags
.bitfield
.cpuavx512vl
6261 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6263 for (op
= 0; op
< t
->operands
; ++op
)
6265 if (t
->operand_types
[op
].bitfield
.zmmword
6266 && (i
.types
[op
].bitfield
.ymmword
6267 || i
.types
[op
].bitfield
.xmmword
))
6269 i
.error
= unsupported
;
6275 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6276 requiring AVX2 support if the actual operand size is YMMword. */
6277 if (t
->cpu_flags
.bitfield
.cpuavx
6278 && t
->cpu_flags
.bitfield
.cpuavx2
6279 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6281 for (op
= 0; op
< t
->operands
; ++op
)
6283 if (t
->operand_types
[op
].bitfield
.xmmword
6284 && i
.types
[op
].bitfield
.ymmword
)
6286 i
.error
= unsupported
;
6292 /* Without VSIB byte, we can't have a vector register for index. */
6293 if (!t
->opcode_modifier
.sib
6295 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6296 || i
.index_reg
->reg_type
.bitfield
.ymmword
6297 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6299 i
.error
= unsupported_vector_index_register
;
6303 /* Check if default mask is allowed. */
6304 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6305 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6307 i
.error
= no_default_mask
;
6311 /* For VSIB byte, we need a vector register for index, and all vector
6312 registers must be distinct. */
6313 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6316 || !((t
->opcode_modifier
.sib
== VECSIB128
6317 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6318 || (t
->opcode_modifier
.sib
== VECSIB256
6319 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6320 || (t
->opcode_modifier
.sib
== VECSIB512
6321 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6323 i
.error
= invalid_vsib_address
;
6327 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6328 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6330 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6331 gas_assert (i
.types
[0].bitfield
.xmmword
6332 || i
.types
[0].bitfield
.ymmword
);
6333 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6334 gas_assert (i
.types
[2].bitfield
.xmmword
6335 || i
.types
[2].bitfield
.ymmword
);
6336 if (operand_check
== check_none
)
6338 if (register_number (i
.op
[0].regs
)
6339 != register_number (i
.index_reg
)
6340 && register_number (i
.op
[2].regs
)
6341 != register_number (i
.index_reg
)
6342 && register_number (i
.op
[0].regs
)
6343 != register_number (i
.op
[2].regs
))
6345 if (operand_check
== check_error
)
6347 i
.error
= invalid_vector_register_set
;
6350 as_warn (_("mask, index, and destination registers should be distinct"));
6352 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6354 if (i
.types
[1].bitfield
.class == RegSIMD
6355 && (i
.types
[1].bitfield
.xmmword
6356 || i
.types
[1].bitfield
.ymmword
6357 || i
.types
[1].bitfield
.zmmword
)
6358 && (register_number (i
.op
[1].regs
)
6359 == register_number (i
.index_reg
)))
6361 if (operand_check
== check_error
)
6363 i
.error
= invalid_vector_register_set
;
6366 if (operand_check
!= check_none
)
6367 as_warn (_("index and destination registers should be distinct"));
6372 /* For AMX instructions with 3 TMM register operands, all operands
6373 must be distinct. */
6374 if (i
.reg_operands
== 3
6375 && t
->operand_types
[0].bitfield
.tmmword
6376 && (i
.op
[0].regs
== i
.op
[1].regs
6377 || i
.op
[0].regs
== i
.op
[2].regs
6378 || i
.op
[1].regs
== i
.op
[2].regs
))
6380 i
.error
= invalid_tmm_register_set
;
6384 /* For some special instructions require that destination must be distinct
6385 from source registers. */
6386 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6388 unsigned int dest_reg
= i
.operands
- 1;
6390 know (i
.operands
>= 3);
6392 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6393 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6394 || (i
.reg_operands
> 2
6395 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6397 i
.error
= invalid_dest_and_src_register_set
;
6402 /* Check if broadcast is supported by the instruction and is applied
6403 to the memory operand. */
6404 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6406 i386_operand_type type
, overlap
;
6408 /* Check if specified broadcast is supported in this instruction,
6409 and its broadcast bytes match the memory operand. */
6410 op
= i
.broadcast
.operand
;
6411 if (!t
->opcode_modifier
.broadcast
6412 || !(i
.flags
[op
] & Operand_Mem
)
6413 || (!i
.types
[op
].bitfield
.unspecified
6414 && !match_broadcast_size (t
, op
)))
6417 i
.error
= unsupported_broadcast
;
6421 operand_type_set (&type
, 0);
6422 switch (get_broadcast_bytes (t
, false))
6425 type
.bitfield
.word
= 1;
6428 type
.bitfield
.dword
= 1;
6431 type
.bitfield
.qword
= 1;
6434 type
.bitfield
.xmmword
= 1;
6437 type
.bitfield
.ymmword
= 1;
6440 type
.bitfield
.zmmword
= 1;
6446 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6447 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6448 && t
->operand_types
[op
].bitfield
.byte
6449 + t
->operand_types
[op
].bitfield
.word
6450 + t
->operand_types
[op
].bitfield
.dword
6451 + t
->operand_types
[op
].bitfield
.qword
> 1)
6453 overlap
.bitfield
.xmmword
= 0;
6454 overlap
.bitfield
.ymmword
= 0;
6455 overlap
.bitfield
.zmmword
= 0;
6457 if (operand_type_all_zero (&overlap
))
6460 if (t
->opcode_modifier
.checkoperandsize
)
6464 type
.bitfield
.baseindex
= 1;
6465 for (j
= 0; j
< i
.operands
; ++j
)
6468 && !operand_type_register_match(i
.types
[j
],
6469 t
->operand_types
[j
],
6471 t
->operand_types
[op
]))
6476 /* If broadcast is supported in this instruction, we need to check if
6477 operand of one-element size isn't specified without broadcast. */
6478 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6480 /* Find memory operand. */
6481 for (op
= 0; op
< i
.operands
; op
++)
6482 if (i
.flags
[op
] & Operand_Mem
)
6484 gas_assert (op
< i
.operands
);
6485 /* Check size of the memory operand. */
6486 if (match_broadcast_size (t
, op
))
6488 i
.error
= broadcast_needed
;
6493 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6495 /* Check if requested masking is supported. */
6498 switch (t
->opcode_modifier
.masking
)
6502 case MERGING_MASKING
:
6506 i
.error
= unsupported_masking
;
6510 case DYNAMIC_MASKING
:
6511 /* Memory destinations allow only merging masking. */
6512 if (i
.mask
.zeroing
&& i
.mem_operands
)
6514 /* Find memory operand. */
6515 for (op
= 0; op
< i
.operands
; op
++)
6516 if (i
.flags
[op
] & Operand_Mem
)
6518 gas_assert (op
< i
.operands
);
6519 if (op
== i
.operands
- 1)
6521 i
.error
= unsupported_masking
;
6531 /* Check if masking is applied to dest operand. */
6532 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6534 i
.error
= mask_not_on_destination
;
6539 if (i
.rounding
.type
!= rc_none
)
6541 if (!t
->opcode_modifier
.sae
6542 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6545 i
.error
= unsupported_rc_sae
;
6549 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6551 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6553 for (op
= 0; op
< t
->operands
; ++op
)
6554 if (i
.types
[op
].bitfield
.zmmword
)
6556 if (op
>= t
->operands
)
6558 i
.error
= operand_size_mismatch
;
6564 /* Check the special Imm4 cases; must be the first operand. */
6565 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6567 if (i
.op
[0].imms
->X_op
!= O_constant
6568 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6574 /* Turn off Imm<N> so that update_imm won't complain. */
6575 operand_type_set (&i
.types
[0], 0);
6578 /* Check vector Disp8 operand. */
6579 if (t
->opcode_modifier
.disp8memshift
6580 && i
.disp_encoding
<= disp_encoding_8bit
)
6582 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6583 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6584 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6585 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6588 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6591 for (op
= 0; op
< i
.operands
; op
++)
6592 if (i
.flags
[op
] & Operand_Mem
)
6594 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6595 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6596 else if (t
->operand_types
[op
].bitfield
.xmmword
6597 + t
->operand_types
[op
].bitfield
.ymmword
6598 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6599 type
= &t
->operand_types
[op
];
6600 else if (!i
.types
[op
].bitfield
.unspecified
)
6601 type
= &i
.types
[op
];
6602 else /* Ambiguities get resolved elsewhere. */
6603 fallback
= &t
->operand_types
[op
];
6605 else if (i
.types
[op
].bitfield
.class == RegSIMD
6606 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6608 if (i
.types
[op
].bitfield
.zmmword
)
6610 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6612 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6616 if (!type
&& !i
.memshift
)
6620 if (type
->bitfield
.zmmword
)
6622 else if (type
->bitfield
.ymmword
)
6624 else if (type
->bitfield
.xmmword
)
6628 /* For the check in fits_in_disp8(). */
6629 if (i
.memshift
== 0)
6633 for (op
= 0; op
< i
.operands
; op
++)
6634 if (operand_type_check (i
.types
[op
], disp
)
6635 && i
.op
[op
].disps
->X_op
== O_constant
)
6637 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6639 i
.types
[op
].bitfield
.disp8
= 1;
6642 i
.types
[op
].bitfield
.disp8
= 0;
6651 /* Check if encoding requirements are met by the instruction. */
6654 VEX_check_encoding (const insn_template
*t
)
6656 if (i
.vec_encoding
== vex_encoding_error
)
6658 i
.error
= unsupported
;
6662 if (i
.vec_encoding
== vex_encoding_evex
)
6664 /* This instruction must be encoded with EVEX prefix. */
6665 if (!is_evex_encoding (t
))
6667 i
.error
= unsupported
;
6673 if (!t
->opcode_modifier
.vex
)
6675 /* This instruction template doesn't have VEX prefix. */
6676 if (i
.vec_encoding
!= vex_encoding_default
)
6678 i
.error
= unsupported
;
6687 /* Helper function for the progress() macro in match_template(). */
6688 static INLINE
enum i386_error
progress (enum i386_error
new,
6689 enum i386_error last
,
6690 unsigned int line
, unsigned int *line_p
)
6692 if (line
<= *line_p
)
6698 static const insn_template
*
6699 match_template (char mnem_suffix
)
6701 /* Points to template once we've found it. */
6702 const insn_template
*t
;
6703 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6704 i386_operand_type overlap4
;
6705 unsigned int found_reverse_match
;
6706 i386_operand_type operand_types
[MAX_OPERANDS
];
6707 int addr_prefix_disp
;
6708 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6709 enum i386_error specific_error
= number_of_operands_mismatch
;
6710 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6712 #if MAX_OPERANDS != 5
6713 # error "MAX_OPERANDS must be 5."
6716 found_reverse_match
= 0;
6717 addr_prefix_disp
= -1;
6719 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6721 addr_prefix_disp
= -1;
6722 found_reverse_match
= 0;
6724 /* Must have right number of operands. */
6725 if (i
.operands
!= t
->operands
)
6728 /* Check processor support. */
6729 specific_error
= progress (unsupported
);
6730 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6733 /* Check AT&T mnemonic. */
6734 specific_error
= progress (unsupported_with_intel_mnemonic
);
6735 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6738 /* Check AT&T/Intel syntax. */
6739 specific_error
= progress (unsupported_syntax
);
6740 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6741 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6744 /* Check Intel64/AMD64 ISA. */
6748 /* Default: Don't accept Intel64. */
6749 if (t
->opcode_modifier
.isa64
== INTEL64
)
6753 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6754 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6758 /* -mintel64: Don't accept AMD64. */
6759 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6764 /* Check the suffix. */
6765 specific_error
= progress (invalid_instruction_suffix
);
6766 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6767 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6768 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6769 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6770 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6773 specific_error
= progress (operand_size_mismatch
);
6774 size_match
= operand_size_match (t
);
6778 /* This is intentionally not
6780 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6782 as the case of a missing * on the operand is accepted (perhaps with
6783 a warning, issued further down). */
6784 specific_error
= progress (operand_type_mismatch
);
6785 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6788 /* In Intel syntax, normally we can check for memory operand size when
6789 there is no mnemonic suffix. But jmp and call have 2 different
6790 encodings with Dword memory operand size. Skip the "near" one
6791 (permitting a register operand) when "far" was requested. */
6793 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
6794 && t
->operand_types
[0].bitfield
.class == Reg
)
6797 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6798 operand_types
[j
] = t
->operand_types
[j
];
6800 /* In general, don't allow 32-bit operands on pre-386. */
6801 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
6802 : operand_size_mismatch
);
6803 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6804 if (i
.suffix
== LONG_MNEM_SUFFIX
6805 && !cpu_arch_flags
.bitfield
.cpui386
6807 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6808 && !intel_float_operand (insn_name (t
)))
6809 : intel_float_operand (insn_name (t
)) != 2)
6810 && (t
->operands
== i
.imm_operands
6811 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6812 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6813 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6814 || (operand_types
[j
].bitfield
.class != RegMMX
6815 && operand_types
[j
].bitfield
.class != RegSIMD
6816 && operand_types
[j
].bitfield
.class != RegMask
))
6817 && !t
->opcode_modifier
.sib
)
6820 /* Do not verify operands when there are none. */
6823 if (VEX_check_encoding (t
))
6825 specific_error
= progress (i
.error
);
6829 /* We've found a match; break out of loop. */
6833 if (!t
->opcode_modifier
.jump
6834 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6836 /* There should be only one Disp operand. */
6837 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6838 if (operand_type_check (operand_types
[j
], disp
))
6840 if (j
< MAX_OPERANDS
)
6842 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6844 addr_prefix_disp
= j
;
6846 /* Address size prefix will turn Disp64 operand into Disp32 and
6847 Disp32/Disp16 one into Disp16/Disp32 respectively. */
6851 override
= !override
;
6854 if (operand_types
[j
].bitfield
.disp32
6855 && operand_types
[j
].bitfield
.disp16
)
6857 operand_types
[j
].bitfield
.disp16
= override
;
6858 operand_types
[j
].bitfield
.disp32
= !override
;
6860 gas_assert (!operand_types
[j
].bitfield
.disp64
);
6864 if (operand_types
[j
].bitfield
.disp64
)
6866 gas_assert (!operand_types
[j
].bitfield
.disp32
);
6867 operand_types
[j
].bitfield
.disp32
= override
;
6868 operand_types
[j
].bitfield
.disp64
= !override
;
6870 operand_types
[j
].bitfield
.disp16
= 0;
6876 /* We check register size if needed. */
6877 if (t
->opcode_modifier
.checkoperandsize
)
6879 check_register
= (1 << t
->operands
) - 1;
6880 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6881 check_register
&= ~(1 << i
.broadcast
.operand
);
6886 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6887 switch (t
->operands
)
6890 if (!operand_type_match (overlap0
, i
.types
[0]))
6893 /* Allow the ModR/M encoding to be requested by using the {load} or
6894 {store} pseudo prefix on an applicable insn. */
6895 if (!t
->opcode_modifier
.modrm
6896 && i
.reg_operands
== 1
6897 && ((i
.dir_encoding
== dir_encoding_load
6898 && t
->mnem_off
!= MN_pop
)
6899 || (i
.dir_encoding
== dir_encoding_store
6900 && t
->mnem_off
!= MN_push
))
6902 && t
->mnem_off
!= MN_bswap
)
6907 /* xchg %eax, %eax is a special case. It is an alias for nop
6908 only in 32bit mode and we can use opcode 0x90. In 64bit
6909 mode, we can't use 0x90 for xchg %eax, %eax since it should
6910 zero-extend %eax to %rax. */
6911 if (t
->base_opcode
== 0x90
6912 && t
->opcode_space
== SPACE_BASE
)
6914 if (flag_code
== CODE_64BIT
6915 && i
.types
[0].bitfield
.instance
== Accum
6916 && i
.types
[0].bitfield
.dword
6917 && i
.types
[1].bitfield
.instance
== Accum
)
6920 /* Allow the ModR/M encoding to be requested by using the
6921 {load} or {store} pseudo prefix. */
6922 if (i
.dir_encoding
== dir_encoding_load
6923 || i
.dir_encoding
== dir_encoding_store
)
6927 if (t
->base_opcode
== MOV_AX_DISP32
6928 && t
->opcode_space
== SPACE_BASE
6929 && t
->mnem_off
!= MN_movabs
)
6931 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6932 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
6935 /* xrelease mov %eax, <disp> is another special case. It must not
6936 match the accumulator-only encoding of mov. */
6940 /* Allow the ModR/M encoding to be requested by using a suitable
6941 {load} or {store} pseudo prefix. */
6942 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
6943 ? dir_encoding_store
6944 : dir_encoding_load
)
6945 && !i
.types
[0].bitfield
.disp64
6946 && !i
.types
[1].bitfield
.disp64
)
6950 /* Allow the ModR/M encoding to be requested by using the {load} or
6951 {store} pseudo prefix on an applicable insn. */
6952 if (!t
->opcode_modifier
.modrm
6953 && i
.reg_operands
== 1
6954 && i
.imm_operands
== 1
6955 && (i
.dir_encoding
== dir_encoding_load
6956 || i
.dir_encoding
== dir_encoding_store
)
6957 && t
->opcode_space
== SPACE_BASE
)
6959 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
6960 && i
.dir_encoding
== dir_encoding_store
)
6963 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
6964 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
6965 || i
.dir_encoding
== dir_encoding_load
))
6968 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
6969 && i
.dir_encoding
== dir_encoding_load
)
6975 if (!(size_match
& MATCH_STRAIGHT
))
6977 /* Reverse direction of operands if swapping is possible in the first
6978 place (operands need to be symmetric) and
6979 - the load form is requested, and the template is a store form,
6980 - the store form is requested, and the template is a load form,
6981 - the non-default (swapped) form is requested. */
6982 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6983 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6984 && !operand_type_all_zero (&overlap1
))
6985 switch (i
.dir_encoding
)
6987 case dir_encoding_load
:
6988 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6989 || t
->opcode_modifier
.regmem
)
6993 case dir_encoding_store
:
6994 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6995 && !t
->opcode_modifier
.regmem
)
6999 case dir_encoding_swap
:
7002 case dir_encoding_default
:
7005 /* If we want store form, we skip the current load. */
7006 if ((i
.dir_encoding
== dir_encoding_store
7007 || i
.dir_encoding
== dir_encoding_swap
)
7008 && i
.mem_operands
== 0
7009 && t
->opcode_modifier
.load
)
7014 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7015 if (!operand_type_match (overlap0
, i
.types
[0])
7016 || !operand_type_match (overlap1
, i
.types
[1])
7017 || ((check_register
& 3) == 3
7018 && !operand_type_register_match (i
.types
[0],
7023 specific_error
= progress (i
.error
);
7025 /* Check if other direction is valid ... */
7026 if (!t
->opcode_modifier
.d
)
7030 if (!(size_match
& MATCH_REVERSE
))
7032 /* Try reversing direction of operands. */
7033 j
= t
->cpu_flags
.bitfield
.cpufma4
7034 || t
->cpu_flags
.bitfield
.cpuxop
? 1 : i
.operands
- 1;
7035 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7036 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7037 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7038 gas_assert (t
->operands
!= 3 || !check_register
);
7039 if (!operand_type_match (overlap0
, i
.types
[0])
7040 || !operand_type_match (overlap1
, i
.types
[j
])
7041 || (t
->operands
== 3
7042 && !operand_type_match (overlap2
, i
.types
[1]))
7044 && !operand_type_register_match (i
.types
[0],
7049 /* Does not match either direction. */
7050 specific_error
= progress (i
.error
);
7053 /* found_reverse_match holds which variant of D
7055 if (!t
->opcode_modifier
.d
)
7056 found_reverse_match
= 0;
7057 else if (operand_types
[0].bitfield
.tbyte
)
7059 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7060 found_reverse_match
= Opcode_FloatD
;
7062 found_reverse_match
= ~0;
7063 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7064 if ((t
->extension_opcode
& 4)
7065 && (intel_syntax
|| intel_mnemonic
))
7066 found_reverse_match
|= Opcode_FloatR
;
7068 else if (t
->cpu_flags
.bitfield
.cpufma4
7069 || t
->cpu_flags
.bitfield
.cpuxop
)
7071 found_reverse_match
= Opcode_VexW
;
7072 goto check_operands_345
;
7074 else if (t
->opcode_space
!= SPACE_BASE
7075 && (t
->opcode_space
!= SPACE_0F
7076 /* MOV to/from CR/DR/TR, as an exception, follow
7077 the base opcode space encoding model. */
7078 || (t
->base_opcode
| 7) != 0x27))
7079 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7080 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7081 else if (!t
->opcode_modifier
.commutative
)
7082 found_reverse_match
= Opcode_D
;
7084 found_reverse_match
= ~0;
7088 /* Found a forward 2 operand match here. */
7090 switch (t
->operands
)
7093 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7094 if (!operand_type_match (overlap4
, i
.types
[4])
7095 || !operand_type_register_match (i
.types
[3],
7100 specific_error
= progress (i
.error
);
7105 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7106 if (!operand_type_match (overlap3
, i
.types
[3])
7107 || ((check_register
& 0xa) == 0xa
7108 && !operand_type_register_match (i
.types
[1],
7112 || ((check_register
& 0xc) == 0xc
7113 && !operand_type_register_match (i
.types
[2],
7118 specific_error
= progress (i
.error
);
7123 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7124 if (!operand_type_match (overlap2
, i
.types
[2])
7125 || ((check_register
& 5) == 5
7126 && !operand_type_register_match (i
.types
[0],
7130 || ((check_register
& 6) == 6
7131 && !operand_type_register_match (i
.types
[1],
7136 specific_error
= progress (i
.error
);
7142 /* Found either forward/reverse 2, 3 or 4 operand match here:
7143 slip through to break. */
7146 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7147 if (VEX_check_encoding (t
))
7149 specific_error
= progress (i
.error
);
7153 /* Check if vector operands are valid. */
7154 if (check_VecOperands (t
))
7156 specific_error
= progress (i
.error
);
7160 /* We've found a match; break out of loop. */
7166 if (t
== current_templates
->end
)
7168 /* We found no match. */
7169 i
.error
= specific_error
;
7173 if (!quiet_warnings
)
7176 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7177 as_warn (_("indirect %s without `*'"), insn_name (t
));
7179 if (t
->opcode_modifier
.isprefix
7180 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7182 /* Warn them that a data or address size prefix doesn't
7183 affect assembly of the next line of code. */
7184 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7188 /* Copy the template we found. */
7189 install_template (t
);
7191 if (addr_prefix_disp
!= -1)
7192 i
.tm
.operand_types
[addr_prefix_disp
]
7193 = operand_types
[addr_prefix_disp
];
7195 switch (found_reverse_match
)
7201 case Opcode_FloatR
| Opcode_FloatD
:
7202 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7203 found_reverse_match
&= Opcode_FloatD
;
7207 /* If we found a reverse match we must alter the opcode direction
7208 bit and clear/flip the regmem modifier one. found_reverse_match
7209 holds bits to change (different for int & float insns). */
7211 i
.tm
.base_opcode
^= found_reverse_match
;
7213 /* Certain SIMD insns have their load forms specified in the opcode
7214 table, and hence we need to _set_ RegMem instead of clearing it.
7215 We need to avoid setting the bit though on insns like KMOVW. */
7216 i
.tm
.opcode_modifier
.regmem
7217 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7218 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7219 && !i
.tm
.opcode_modifier
.regmem
;
7223 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7224 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7228 /* Only the first two register operands need reversing, alongside
7230 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7232 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7233 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7234 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7244 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7245 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7247 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7249 as_bad (_("`%s' operand %u must use `%ses' segment"),
7251 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7256 /* There's only ever one segment override allowed per instruction.
7257 This instruction possibly has a legal segment override on the
7258 second operand, so copy the segment to where non-string
7259 instructions store it, allowing common code. */
7260 i
.seg
[op
] = i
.seg
[1];
7266 process_suffix (void)
7268 bool is_movx
= false;
7270 /* If matched instruction specifies an explicit instruction mnemonic
7272 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7273 i
.suffix
= WORD_MNEM_SUFFIX
;
7274 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7275 i
.suffix
= LONG_MNEM_SUFFIX
;
7276 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7277 i
.suffix
= QWORD_MNEM_SUFFIX
;
7278 else if (i
.reg_operands
7279 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7280 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7282 unsigned int numop
= i
.operands
;
7285 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7286 && (i
.tm
.base_opcode
| 8) == 0xbe)
7287 || (i
.tm
.opcode_space
== SPACE_BASE
7288 && i
.tm
.base_opcode
== 0x63
7289 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
7291 /* movsx/movzx want only their source operand considered here, for the
7292 ambiguity checking below. The suffix will be replaced afterwards
7293 to represent the destination (register). */
7294 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7297 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7298 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7301 /* If there's no instruction mnemonic suffix we try to invent one
7302 based on GPR operands. */
7305 /* We take i.suffix from the last register operand specified,
7306 Destination register type is more significant than source
7307 register type. crc32 in SSE4.2 prefers source register
7309 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7312 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7313 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7315 if (i
.types
[op
].bitfield
.class != Reg
)
7317 if (i
.types
[op
].bitfield
.byte
)
7318 i
.suffix
= BYTE_MNEM_SUFFIX
;
7319 else if (i
.types
[op
].bitfield
.word
)
7320 i
.suffix
= WORD_MNEM_SUFFIX
;
7321 else if (i
.types
[op
].bitfield
.dword
)
7322 i
.suffix
= LONG_MNEM_SUFFIX
;
7323 else if (i
.types
[op
].bitfield
.qword
)
7324 i
.suffix
= QWORD_MNEM_SUFFIX
;
7330 /* As an exception, movsx/movzx silently default to a byte source
7332 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7333 i
.suffix
= BYTE_MNEM_SUFFIX
;
7335 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7337 if (!check_byte_reg ())
7340 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7342 if (!check_long_reg ())
7345 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7347 if (!check_qword_reg ())
7350 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7352 if (!check_word_reg ())
7355 else if (intel_syntax
7356 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7357 /* Do nothing if the instruction is going to ignore the prefix. */
7362 /* Undo the movsx/movzx change done above. */
7365 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7368 i
.suffix
= stackop_size
;
7369 if (stackop_size
== LONG_MNEM_SUFFIX
)
7371 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7372 .code16gcc directive to support 16-bit mode with
7373 32-bit address. For IRET without a suffix, generate
7374 16-bit IRET (opcode 0xcf) to return from an interrupt
7376 if (i
.tm
.base_opcode
== 0xcf)
7378 i
.suffix
= WORD_MNEM_SUFFIX
;
7379 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7381 /* Warn about changed behavior for segment register push/pop. */
7382 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7383 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7388 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7389 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7390 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7391 || (i
.tm
.opcode_space
== SPACE_0F
7392 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7393 && i
.tm
.extension_opcode
<= 3)))
7398 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7400 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7401 || i
.tm
.opcode_modifier
.no_lsuf
)
7402 i
.suffix
= QWORD_MNEM_SUFFIX
;
7407 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7408 i
.suffix
= LONG_MNEM_SUFFIX
;
7411 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7412 i
.suffix
= WORD_MNEM_SUFFIX
;
7418 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7419 /* Also cover lret/retf/iret in 64-bit mode. */
7420 || (flag_code
== CODE_64BIT
7421 && !i
.tm
.opcode_modifier
.no_lsuf
7422 && !i
.tm
.opcode_modifier
.no_qsuf
))
7423 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7424 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7425 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7426 /* Accept FLDENV et al without suffix. */
7427 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7429 unsigned int suffixes
, evex
= 0;
7431 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7432 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7434 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7436 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7438 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7441 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7442 also suitable for AT&T syntax mode, it was requested that this be
7443 restricted to just Intel syntax. */
7444 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7445 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7449 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7451 if (is_evex_encoding (&i
.tm
)
7452 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7454 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7455 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7456 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7457 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7458 if (!i
.tm
.opcode_modifier
.evex
7459 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7460 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7463 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7464 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7465 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7468 /* Any properly sized operand disambiguates the insn. */
7469 if (i
.types
[op
].bitfield
.xmmword
7470 || i
.types
[op
].bitfield
.ymmword
7471 || i
.types
[op
].bitfield
.zmmword
)
7473 suffixes
&= ~(7 << 6);
7478 if ((i
.flags
[op
] & Operand_Mem
)
7479 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7481 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7483 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7485 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7487 if (is_evex_encoding (&i
.tm
))
7493 /* Are multiple suffixes / operand sizes allowed? */
7494 if (suffixes
& (suffixes
- 1))
7497 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7498 || operand_check
== check_error
))
7500 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7503 if (operand_check
== check_error
)
7505 as_bad (_("no instruction mnemonic suffix given and "
7506 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7509 if (operand_check
== check_warning
)
7510 as_warn (_("%s; using default for `%s'"),
7512 ? _("ambiguous operand size")
7513 : _("no instruction mnemonic suffix given and "
7514 "no register operands"),
7517 if (i
.tm
.opcode_modifier
.floatmf
)
7518 i
.suffix
= SHORT_MNEM_SUFFIX
;
7520 /* handled below */;
7522 i
.tm
.opcode_modifier
.evex
= evex
;
7523 else if (flag_code
== CODE_16BIT
)
7524 i
.suffix
= WORD_MNEM_SUFFIX
;
7525 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7526 i
.suffix
= LONG_MNEM_SUFFIX
;
7528 i
.suffix
= QWORD_MNEM_SUFFIX
;
7534 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7535 In AT&T syntax, if there is no suffix (warned about above), the default
7536 will be byte extension. */
7537 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7538 i
.tm
.base_opcode
|= 1;
7540 /* For further processing, the suffix should represent the destination
7541 (register). This is already the case when one was used with
7542 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7543 no suffix to begin with. */
7544 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7546 if (i
.types
[1].bitfield
.word
)
7547 i
.suffix
= WORD_MNEM_SUFFIX
;
7548 else if (i
.types
[1].bitfield
.qword
)
7549 i
.suffix
= QWORD_MNEM_SUFFIX
;
7551 i
.suffix
= LONG_MNEM_SUFFIX
;
7553 i
.tm
.opcode_modifier
.w
= 0;
7557 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7558 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7559 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7561 /* Change the opcode based on the operand size given by i.suffix. */
7564 /* Size floating point instruction. */
7565 case LONG_MNEM_SUFFIX
:
7566 if (i
.tm
.opcode_modifier
.floatmf
)
7568 i
.tm
.base_opcode
^= 4;
7572 case WORD_MNEM_SUFFIX
:
7573 case QWORD_MNEM_SUFFIX
:
7574 /* It's not a byte, select word/dword operation. */
7575 if (i
.tm
.opcode_modifier
.w
)
7578 i
.tm
.base_opcode
|= 8;
7580 i
.tm
.base_opcode
|= 1;
7583 case SHORT_MNEM_SUFFIX
:
7584 /* Now select between word & dword operations via the operand
7585 size prefix, except for instructions that will ignore this
7587 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7588 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7589 && !i
.tm
.opcode_modifier
.floatmf
7590 && !is_any_vex_encoding (&i
.tm
)
7591 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7592 || (flag_code
== CODE_64BIT
7593 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7595 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7597 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7598 prefix
= ADDR_PREFIX_OPCODE
;
7600 if (!add_prefix (prefix
))
7604 /* Set mode64 for an operand. */
7605 if (i
.suffix
== QWORD_MNEM_SUFFIX
7606 && flag_code
== CODE_64BIT
7607 && !i
.tm
.opcode_modifier
.norex64
7608 && !i
.tm
.opcode_modifier
.vexw
7609 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7611 && ! (i
.operands
== 2
7612 && i
.tm
.base_opcode
== 0x90
7613 && i
.tm
.opcode_space
== SPACE_BASE
7614 && i
.types
[0].bitfield
.instance
== Accum
7615 && i
.types
[0].bitfield
.qword
7616 && i
.types
[1].bitfield
.instance
== Accum
))
7622 /* Select word/dword/qword operation with explicit data sizing prefix
7623 when there are no suitable register operands. */
7624 if (i
.tm
.opcode_modifier
.w
7625 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7627 || (i
.reg_operands
== 1
7629 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7631 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7632 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7633 || i
.tm
.mnem_off
== MN_crc32
))))
7634 i
.tm
.base_opcode
|= 1;
7638 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7640 gas_assert (!i
.suffix
);
7641 gas_assert (i
.reg_operands
);
7643 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7646 /* The address size override prefix changes the size of the
7648 if (flag_code
== CODE_64BIT
7649 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7651 as_bad (_("16-bit addressing unavailable for `%s'"),
7656 if ((flag_code
== CODE_32BIT
7657 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7658 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7659 && !add_prefix (ADDR_PREFIX_OPCODE
))
7664 /* Check invalid register operand when the address size override
7665 prefix changes the size of register operands. */
7667 enum { need_word
, need_dword
, need_qword
} need
;
7669 /* Check the register operand for the address size prefix if
7670 the memory operand has no real registers, like symbol, DISP
7671 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7672 if (i
.mem_operands
== 1
7673 && i
.reg_operands
== 1
7675 && i
.types
[1].bitfield
.class == Reg
7676 && (flag_code
== CODE_32BIT
7677 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7678 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7679 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7680 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7681 || (x86_elf_abi
== X86_64_X32_ABI
7683 && i
.base_reg
->reg_num
== RegIP
7684 && i
.base_reg
->reg_type
.bitfield
.qword
))
7688 && !add_prefix (ADDR_PREFIX_OPCODE
))
7691 if (flag_code
== CODE_32BIT
)
7692 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7693 else if (i
.prefix
[ADDR_PREFIX
])
7696 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7698 for (op
= 0; op
< i
.operands
; op
++)
7700 if (i
.types
[op
].bitfield
.class != Reg
)
7706 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7710 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7714 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7719 as_bad (_("invalid register operand size for `%s'"),
7730 check_byte_reg (void)
7734 for (op
= i
.operands
; --op
>= 0;)
7736 /* Skip non-register operands. */
7737 if (i
.types
[op
].bitfield
.class != Reg
)
7740 /* If this is an eight bit register, it's OK. If it's the 16 or
7741 32 bit version of an eight bit register, we will just use the
7742 low portion, and that's OK too. */
7743 if (i
.types
[op
].bitfield
.byte
)
7746 /* I/O port address operands are OK too. */
7747 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7748 && i
.tm
.operand_types
[op
].bitfield
.word
)
7751 /* crc32 only wants its source operand checked here. */
7752 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
7755 /* Any other register is bad. */
7756 as_bad (_("`%s%s' not allowed with `%s%c'"),
7757 register_prefix
, i
.op
[op
].regs
->reg_name
,
7758 insn_name (&i
.tm
), i
.suffix
);
7765 check_long_reg (void)
7769 for (op
= i
.operands
; --op
>= 0;)
7770 /* Skip non-register operands. */
7771 if (i
.types
[op
].bitfield
.class != Reg
)
7773 /* Reject eight bit registers, except where the template requires
7774 them. (eg. movzb) */
7775 else if (i
.types
[op
].bitfield
.byte
7776 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7777 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7778 && (i
.tm
.operand_types
[op
].bitfield
.word
7779 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7781 as_bad (_("`%s%s' not allowed with `%s%c'"),
7783 i
.op
[op
].regs
->reg_name
,
7788 /* Error if the e prefix on a general reg is missing. */
7789 else if (i
.types
[op
].bitfield
.word
7790 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7791 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7792 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7794 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7795 register_prefix
, i
.op
[op
].regs
->reg_name
,
7799 /* Warn if the r prefix on a general reg is present. */
7800 else if (i
.types
[op
].bitfield
.qword
7801 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7802 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7803 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7805 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7806 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7813 check_qword_reg (void)
7817 for (op
= i
.operands
; --op
>= 0; )
7818 /* Skip non-register operands. */
7819 if (i
.types
[op
].bitfield
.class != Reg
)
7821 /* Reject eight bit registers, except where the template requires
7822 them. (eg. movzb) */
7823 else if (i
.types
[op
].bitfield
.byte
7824 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7825 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7826 && (i
.tm
.operand_types
[op
].bitfield
.word
7827 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7829 as_bad (_("`%s%s' not allowed with `%s%c'"),
7831 i
.op
[op
].regs
->reg_name
,
7836 /* Warn if the r prefix on a general reg is missing. */
7837 else if ((i
.types
[op
].bitfield
.word
7838 || i
.types
[op
].bitfield
.dword
)
7839 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7840 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7841 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7843 /* Prohibit these changes in the 64bit mode, since the
7844 lowering is more complicated. */
7845 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7846 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7853 check_word_reg (void)
7856 for (op
= i
.operands
; --op
>= 0;)
7857 /* Skip non-register operands. */
7858 if (i
.types
[op
].bitfield
.class != Reg
)
7860 /* Reject eight bit registers, except where the template requires
7861 them. (eg. movzb) */
7862 else if (i
.types
[op
].bitfield
.byte
7863 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7864 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7865 && (i
.tm
.operand_types
[op
].bitfield
.word
7866 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7868 as_bad (_("`%s%s' not allowed with `%s%c'"),
7870 i
.op
[op
].regs
->reg_name
,
7875 /* Error if the e or r prefix on a general reg is present. */
7876 else if ((i
.types
[op
].bitfield
.dword
7877 || i
.types
[op
].bitfield
.qword
)
7878 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7879 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7880 && i
.tm
.operand_types
[op
].bitfield
.word
)
7882 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7883 register_prefix
, i
.op
[op
].regs
->reg_name
,
7891 update_imm (unsigned int j
)
7893 i386_operand_type overlap
= i
.types
[j
];
7895 if (i
.tm
.operand_types
[j
].bitfield
.imm8
7896 && i
.tm
.operand_types
[j
].bitfield
.imm8s
7897 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
7899 /* This combination is used on 8-bit immediates where e.g. $~0 is
7900 desirable to permit. We're past operand type matching, so simply
7901 put things back in the shape they were before introducing the
7902 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
7903 overlap
.bitfield
.imm8s
= 0;
7906 if (overlap
.bitfield
.imm8
7907 + overlap
.bitfield
.imm8s
7908 + overlap
.bitfield
.imm16
7909 + overlap
.bitfield
.imm32
7910 + overlap
.bitfield
.imm32s
7911 + overlap
.bitfield
.imm64
> 1)
7913 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
7914 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
7915 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
7916 static const i386_operand_type imm16_32
= { .bitfield
=
7917 { .imm16
= 1, .imm32
= 1 }
7919 static const i386_operand_type imm16_32s
= { .bitfield
=
7920 { .imm16
= 1, .imm32s
= 1 }
7922 static const i386_operand_type imm16_32_32s
= { .bitfield
=
7923 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
7928 i386_operand_type temp
;
7930 operand_type_set (&temp
, 0);
7931 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7933 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7934 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7936 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7937 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7938 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7940 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7941 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7944 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7947 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7948 || operand_type_equal (&overlap
, &imm16_32
)
7949 || operand_type_equal (&overlap
, &imm16_32s
))
7951 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7956 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7957 overlap
= operand_type_and (overlap
, imm32s
);
7958 else if (i
.prefix
[DATA_PREFIX
])
7959 overlap
= operand_type_and (overlap
,
7960 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7961 if (overlap
.bitfield
.imm8
7962 + overlap
.bitfield
.imm8s
7963 + overlap
.bitfield
.imm16
7964 + overlap
.bitfield
.imm32
7965 + overlap
.bitfield
.imm32s
7966 + overlap
.bitfield
.imm64
!= 1)
7968 as_bad (_("no instruction mnemonic suffix given; "
7969 "can't determine immediate size"));
7973 i
.types
[j
] = overlap
;
7983 /* Update the first 2 immediate operands. */
7984 n
= i
.operands
> 2 ? 2 : i
.operands
;
7987 for (j
= 0; j
< n
; j
++)
7988 if (update_imm (j
) == 0)
7991 /* The 3rd operand can't be immediate operand. */
7992 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7998 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8001 if (r
->reg_flags
& RegRex
)
8003 if (i
.rex
& rex_bit
)
8004 as_bad (_("same type of prefix used twice"));
8007 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8009 gas_assert (i
.vex
.register_specifier
== r
);
8010 i
.vex
.register_specifier
+= 8;
8013 if (r
->reg_flags
& RegVRex
)
8018 process_operands (void)
8020 /* Default segment register this instruction will use for memory
8021 accesses. 0 means unknown. This is only for optimizing out
8022 unnecessary segment overrides. */
8023 const reg_entry
*default_seg
= NULL
;
8025 /* We only need to check those implicit registers for instructions
8026 with 3 operands or less. */
8027 if (i
.operands
<= 3)
8028 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8029 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8032 if (i
.tm
.opcode_modifier
.sse2avx
)
8034 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8036 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8037 i
.prefix
[REX_PREFIX
] = 0;
8040 /* ImmExt should be processed after SSE2AVX. */
8041 else if (i
.tm
.opcode_modifier
.immext
)
8044 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8045 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8046 new destination operand here, while converting the source one to register
8048 if (i
.tm
.mnem_off
== MN_tilezero
)
8050 i
.op
[1].regs
= i
.op
[0].regs
;
8051 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8052 i
.types
[1] = i
.types
[0];
8053 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8054 i
.flags
[1] = i
.flags
[0];
8060 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8062 static const i386_operand_type regxmm
= {
8063 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8065 unsigned int dupl
= i
.operands
;
8066 unsigned int dest
= dupl
- 1;
8069 /* The destination must be an xmm register. */
8070 gas_assert (i
.reg_operands
8071 && MAX_OPERANDS
> dupl
8072 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8074 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8075 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8077 /* Keep xmm0 for instructions with VEX prefix and 3
8079 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8080 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8085 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8087 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8089 /* Add the implicit xmm0 for instructions with VEX prefix
8091 for (j
= i
.operands
; j
> 0; j
--)
8093 i
.op
[j
] = i
.op
[j
- 1];
8094 i
.types
[j
] = i
.types
[j
- 1];
8095 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8096 i
.flags
[j
] = i
.flags
[j
- 1];
8099 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8100 i
.types
[0] = regxmm
;
8101 i
.tm
.operand_types
[0] = regxmm
;
8104 i
.reg_operands
+= 2;
8109 i
.op
[dupl
] = i
.op
[dest
];
8110 i
.types
[dupl
] = i
.types
[dest
];
8111 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8112 i
.flags
[dupl
] = i
.flags
[dest
];
8121 i
.op
[dupl
] = i
.op
[dest
];
8122 i
.types
[dupl
] = i
.types
[dest
];
8123 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8124 i
.flags
[dupl
] = i
.flags
[dest
];
8127 if (i
.tm
.opcode_modifier
.immext
)
8130 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8131 && i
.tm
.opcode_modifier
.modrm
)
8135 for (j
= 1; j
< i
.operands
; j
++)
8137 i
.op
[j
- 1] = i
.op
[j
];
8138 i
.types
[j
- 1] = i
.types
[j
];
8140 /* We need to adjust fields in i.tm since they are used by
8141 build_modrm_byte. */
8142 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8144 i
.flags
[j
- 1] = i
.flags
[j
];
8147 /* No adjustment to i.reg_operands: This was already done at the top
8152 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8154 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8156 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8157 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8158 regnum
= register_number (i
.op
[1].regs
);
8159 first_reg_in_group
= regnum
& ~3;
8160 last_reg_in_group
= first_reg_in_group
+ 3;
8161 if (regnum
!= first_reg_in_group
)
8162 as_warn (_("source register `%s%s' implicitly denotes"
8163 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8164 register_prefix
, i
.op
[1].regs
->reg_name
,
8165 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8166 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8169 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8171 /* The imul $imm, %reg instruction is converted into
8172 imul $imm, %reg, %reg, and the clr %reg instruction
8173 is converted into xor %reg, %reg. */
8175 unsigned int first_reg_op
;
8177 if (operand_type_check (i
.types
[0], reg
))
8181 /* Pretend we saw the extra register operand. */
8182 gas_assert (i
.reg_operands
== 1
8183 && i
.op
[first_reg_op
+ 1].regs
== 0);
8184 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8185 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8190 if (i
.tm
.opcode_modifier
.modrm
)
8192 /* The opcode is completed (modulo i.tm.extension_opcode which
8193 must be put into the modrm byte). Now, we make the modrm and
8194 index base bytes based on all the info we've collected. */
8196 default_seg
= build_modrm_byte ();
8198 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8200 /* Warn about some common errors, but press on regardless. */
8201 if (i
.operands
== 2)
8203 /* Reversed arguments on faddp or fmulp. */
8204 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8205 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8206 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8208 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8210 /* Extraneous `l' suffix on fp insn. */
8211 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8212 register_prefix
, i
.op
[0].regs
->reg_name
);
8216 else if (i
.types
[0].bitfield
.class == SReg
)
8218 if (flag_code
!= CODE_64BIT
8219 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8220 && i
.op
[0].regs
->reg_num
== 1
8221 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8222 && i
.op
[0].regs
->reg_num
< 4)
8224 as_bad (_("you can't `%s %s%s'"),
8225 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8228 if (i
.op
[0].regs
->reg_num
> 3
8229 && i
.tm
.opcode_space
== SPACE_BASE
)
8231 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8232 i
.tm
.opcode_space
= SPACE_0F
;
8234 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8236 else if (i
.tm
.opcode_space
== SPACE_BASE
8237 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8239 default_seg
= reg_ds
;
8241 else if (i
.tm
.opcode_modifier
.isstring
)
8243 /* For the string instructions that allow a segment override
8244 on one of their operands, the default segment is ds. */
8245 default_seg
= reg_ds
;
8247 else if (i
.short_form
)
8249 /* The register operand is in operand 0 or 1. */
8250 const reg_entry
*r
= i
.op
[0].regs
;
8253 || (r
->reg_type
.bitfield
.instance
== Accum
&& i
.op
[1].regs
))
8255 /* Register goes in low 3 bits of opcode. */
8256 i
.tm
.base_opcode
|= r
->reg_num
;
8257 set_rex_vrex (r
, REX_B
, false);
8260 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8261 && i
.tm
.mnem_off
== MN_lea
)
8263 if (!quiet_warnings
)
8264 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8265 if (optimize
&& !i
.no_optimize
)
8268 i
.prefix
[SEG_PREFIX
] = 0;
8272 /* If a segment was explicitly specified, and the specified segment
8273 is neither the default nor the one already recorded from a prefix,
8274 use an opcode prefix to select it. If we never figured out what
8275 the default segment is, then default_seg will be zero at this
8276 point, and the specified segment prefix will always be used. */
8278 && i
.seg
[0] != default_seg
8279 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8281 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8287 static const reg_entry
*
8288 build_modrm_byte (void)
8290 const reg_entry
*default_seg
= NULL
;
8291 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8292 /* Compensate for kludge in md_assemble(). */
8293 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8294 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8295 unsigned int v
, op
, reg_slot
= ~0;
8297 /* Accumulator (in particular %st), shift count (%cl), and alike need
8298 to be skipped just like immediate operands do. */
8299 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8301 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8304 for (op
= source
; op
< i
.operands
; ++op
)
8305 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8308 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8312 /* There are 2 kinds of instructions:
8313 1. 5 operands: 4 register operands or 3 register operands
8314 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8315 VexW0 or VexW1. The destination must be either XMM, YMM or
8317 2. 4 operands: 4 register operands or 3 register operands
8318 plus 1 memory operand, with VexXDS. */
8319 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8320 && i
.tm
.opcode_modifier
.vexw
8321 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8323 /* Of the first two non-immediate operands the one with the template
8324 not allowing for a memory one is encoded in the immediate operand. */
8326 reg_slot
= source
+ 1;
8328 reg_slot
= source
++;
8330 if (i
.imm_operands
== 0)
8332 /* When there is no immediate operand, generate an 8bit
8333 immediate operand to encode the first operand. */
8334 exp
= &im_expressions
[i
.imm_operands
++];
8335 i
.op
[i
.operands
].imms
= exp
;
8336 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8339 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8340 exp
->X_op
= O_constant
;
8341 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8342 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8346 gas_assert (i
.imm_operands
== 1);
8347 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8348 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8350 /* Turn on Imm8 again so that output_imm will generate it. */
8351 i
.types
[0].bitfield
.imm8
= 1;
8353 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8354 i
.op
[0].imms
->X_add_number
8355 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8356 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8360 for (v
= source
+ 1; v
< dest
; ++v
)
8365 if (i
.tm
.extension_opcode
!= None
)
8371 gas_assert (source
< dest
);
8372 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8375 unsigned int tmp
= source
;
8381 if (v
< MAX_OPERANDS
)
8383 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8384 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8387 if (op
< i
.operands
)
8391 unsigned int fake_zero_displacement
= 0;
8393 gas_assert (i
.flags
[op
] & Operand_Mem
);
8395 if (i
.tm
.opcode_modifier
.sib
)
8397 /* The index register of VSIB shouldn't be RegIZ. */
8398 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8399 && i
.index_reg
->reg_num
== RegIZ
)
8402 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8405 i
.sib
.base
= NO_BASE_REGISTER
;
8406 i
.sib
.scale
= i
.log2_scale_factor
;
8407 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8408 i
.types
[op
].bitfield
.disp32
= 1;
8411 /* Since the mandatory SIB always has index register, so
8412 the code logic remains unchanged. The non-mandatory SIB
8413 without index register is allowed and will be handled
8417 if (i
.index_reg
->reg_num
== RegIZ
)
8418 i
.sib
.index
= NO_INDEX_REGISTER
;
8420 i
.sib
.index
= i
.index_reg
->reg_num
;
8421 set_rex_vrex (i
.index_reg
, REX_X
, false);
8425 default_seg
= reg_ds
;
8427 if (i
.base_reg
== 0)
8430 if (!i
.disp_operands
)
8431 fake_zero_displacement
= 1;
8432 if (i
.index_reg
== 0)
8434 /* Both check for VSIB and mandatory non-vector SIB. */
8435 gas_assert (!i
.tm
.opcode_modifier
.sib
8436 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8437 /* Operand is just <disp> */
8438 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8439 if (flag_code
== CODE_64BIT
)
8441 /* 64bit mode overwrites the 32bit absolute
8442 addressing by RIP relative addressing and
8443 absolute addressing is encoded by one of the
8444 redundant SIB forms. */
8445 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8446 i
.sib
.base
= NO_BASE_REGISTER
;
8447 i
.sib
.index
= NO_INDEX_REGISTER
;
8448 i
.types
[op
].bitfield
.disp32
= 1;
8450 else if ((flag_code
== CODE_16BIT
)
8451 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8453 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8454 i
.types
[op
].bitfield
.disp16
= 1;
8458 i
.rm
.regmem
= NO_BASE_REGISTER
;
8459 i
.types
[op
].bitfield
.disp32
= 1;
8462 else if (!i
.tm
.opcode_modifier
.sib
)
8464 /* !i.base_reg && i.index_reg */
8465 if (i
.index_reg
->reg_num
== RegIZ
)
8466 i
.sib
.index
= NO_INDEX_REGISTER
;
8468 i
.sib
.index
= i
.index_reg
->reg_num
;
8469 i
.sib
.base
= NO_BASE_REGISTER
;
8470 i
.sib
.scale
= i
.log2_scale_factor
;
8471 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8472 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8473 i
.types
[op
].bitfield
.disp32
= 1;
8474 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8478 /* RIP addressing for 64bit mode. */
8479 else if (i
.base_reg
->reg_num
== RegIP
)
8481 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8482 i
.rm
.regmem
= NO_BASE_REGISTER
;
8483 i
.types
[op
].bitfield
.disp8
= 0;
8484 i
.types
[op
].bitfield
.disp16
= 0;
8485 i
.types
[op
].bitfield
.disp32
= 1;
8486 i
.types
[op
].bitfield
.disp64
= 0;
8487 i
.flags
[op
] |= Operand_PCrel
;
8488 if (! i
.disp_operands
)
8489 fake_zero_displacement
= 1;
8491 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8493 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8494 switch (i
.base_reg
->reg_num
)
8497 if (i
.index_reg
== 0)
8499 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8500 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8503 default_seg
= reg_ss
;
8504 if (i
.index_reg
== 0)
8507 if (operand_type_check (i
.types
[op
], disp
) == 0)
8509 /* fake (%bp) into 0(%bp) */
8510 if (i
.disp_encoding
== disp_encoding_16bit
)
8511 i
.types
[op
].bitfield
.disp16
= 1;
8513 i
.types
[op
].bitfield
.disp8
= 1;
8514 fake_zero_displacement
= 1;
8517 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8518 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8520 default: /* (%si) -> 4 or (%di) -> 5 */
8521 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8523 if (!fake_zero_displacement
8527 fake_zero_displacement
= 1;
8528 if (i
.disp_encoding
== disp_encoding_8bit
)
8529 i
.types
[op
].bitfield
.disp8
= 1;
8531 i
.types
[op
].bitfield
.disp16
= 1;
8533 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8535 else /* i.base_reg and 32/64 bit mode */
8537 if (operand_type_check (i
.types
[op
], disp
))
8539 i
.types
[op
].bitfield
.disp16
= 0;
8540 i
.types
[op
].bitfield
.disp64
= 0;
8541 i
.types
[op
].bitfield
.disp32
= 1;
8544 if (!i
.tm
.opcode_modifier
.sib
)
8545 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8546 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8548 i
.sib
.base
= i
.base_reg
->reg_num
;
8549 /* x86-64 ignores REX prefix bit here to avoid decoder
8551 if (!(i
.base_reg
->reg_flags
& RegRex
)
8552 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8553 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8554 default_seg
= reg_ss
;
8555 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8557 fake_zero_displacement
= 1;
8558 if (i
.disp_encoding
== disp_encoding_32bit
)
8559 i
.types
[op
].bitfield
.disp32
= 1;
8561 i
.types
[op
].bitfield
.disp8
= 1;
8563 i
.sib
.scale
= i
.log2_scale_factor
;
8564 if (i
.index_reg
== 0)
8566 /* Only check for VSIB. */
8567 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8568 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8569 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8571 /* <disp>(%esp) becomes two byte modrm with no index
8572 register. We've already stored the code for esp
8573 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8574 Any base register besides %esp will not use the
8575 extra modrm byte. */
8576 i
.sib
.index
= NO_INDEX_REGISTER
;
8578 else if (!i
.tm
.opcode_modifier
.sib
)
8580 if (i
.index_reg
->reg_num
== RegIZ
)
8581 i
.sib
.index
= NO_INDEX_REGISTER
;
8583 i
.sib
.index
= i
.index_reg
->reg_num
;
8584 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8585 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8590 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8591 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8595 if (!fake_zero_displacement
8599 fake_zero_displacement
= 1;
8600 if (i
.disp_encoding
== disp_encoding_8bit
)
8601 i
.types
[op
].bitfield
.disp8
= 1;
8603 i
.types
[op
].bitfield
.disp32
= 1;
8605 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8609 if (fake_zero_displacement
)
8611 /* Fakes a zero displacement assuming that i.types[op]
8612 holds the correct displacement size. */
8615 gas_assert (i
.op
[op
].disps
== 0);
8616 exp
= &disp_expressions
[i
.disp_operands
++];
8617 i
.op
[op
].disps
= exp
;
8618 exp
->X_op
= O_constant
;
8619 exp
->X_add_number
= 0;
8620 exp
->X_add_symbol
= (symbolS
*) 0;
8621 exp
->X_op_symbol
= (symbolS
*) 0;
8627 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8628 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8639 if (!i
.tm
.opcode_modifier
.regmem
)
8641 gas_assert (source
< MAX_OPERANDS
);
8642 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8643 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8644 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8649 gas_assert (dest
< MAX_OPERANDS
);
8650 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8651 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8656 /* Fill in i.rm.reg field with extension opcode (if any) or the
8657 appropriate register. */
8658 if (i
.tm
.extension_opcode
!= None
)
8659 i
.rm
.reg
= i
.tm
.extension_opcode
;
8660 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
8662 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8663 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8667 gas_assert (source
< MAX_OPERANDS
);
8668 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8669 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8672 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8674 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
8676 add_prefix (LOCK_PREFIX_OPCODE
);
8683 frag_opcode_byte (unsigned char byte
)
8685 if (now_seg
!= absolute_section
)
8686 FRAG_APPEND_1_CHAR (byte
);
8688 ++abs_section_offset
;
8692 flip_code16 (unsigned int code16
)
8694 gas_assert (i
.tm
.operands
== 1);
8696 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8697 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8698 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8703 output_branch (void)
8709 relax_substateT subtype
;
8713 if (now_seg
== absolute_section
)
8715 as_bad (_("relaxable branches not supported in absolute section"));
8719 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8720 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8723 if (i
.prefix
[DATA_PREFIX
] != 0)
8727 code16
^= flip_code16(code16
);
8729 /* Pentium4 branch hints. */
8730 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8731 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8736 if (i
.prefix
[REX_PREFIX
] != 0)
8742 /* BND prefixed jump. */
8743 if (i
.prefix
[BND_PREFIX
] != 0)
8749 if (i
.prefixes
!= 0)
8750 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8752 /* It's always a symbol; End frag & setup for relax.
8753 Make sure there is enough room in this frag for the largest
8754 instruction we may generate in md_convert_frag. This is 2
8755 bytes for the opcode and room for the prefix and largest
8757 frag_grow (prefix
+ 2 + 4);
8758 /* Prefix and 1 opcode byte go in fr_fix. */
8759 p
= frag_more (prefix
+ 1);
8760 if (i
.prefix
[DATA_PREFIX
] != 0)
8761 *p
++ = DATA_PREFIX_OPCODE
;
8762 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8763 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8764 *p
++ = i
.prefix
[SEG_PREFIX
];
8765 if (i
.prefix
[BND_PREFIX
] != 0)
8766 *p
++ = BND_PREFIX_OPCODE
;
8767 if (i
.prefix
[REX_PREFIX
] != 0)
8768 *p
++ = i
.prefix
[REX_PREFIX
];
8769 *p
= i
.tm
.base_opcode
;
8771 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8772 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8773 else if (cpu_arch_flags
.bitfield
.cpui386
)
8774 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8776 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8779 sym
= i
.op
[0].disps
->X_add_symbol
;
8780 off
= i
.op
[0].disps
->X_add_number
;
8782 if (i
.op
[0].disps
->X_op
!= O_constant
8783 && i
.op
[0].disps
->X_op
!= O_symbol
)
8785 /* Handle complex expressions. */
8786 sym
= make_expr_symbol (i
.op
[0].disps
);
8790 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
8792 /* 1 possible extra opcode + 4 byte displacement go in var part.
8793 Pass reloc in fr_var. */
8794 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8798 /* Return TRUE iff PLT32 relocation should be used for branching to
8802 need_plt32_p (symbolS
*s
)
8804 /* PLT32 relocation is ELF only. */
8809 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8810 krtld support it. */
8814 /* Since there is no need to prepare for PLT branch on x86-64, we
8815 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8816 be used as a marker for 32-bit PC-relative branches. */
8823 /* Weak or undefined symbol need PLT32 relocation. */
8824 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8827 /* Non-global symbol doesn't need PLT32 relocation. */
8828 if (! S_IS_EXTERNAL (s
))
8831 /* Other global symbols need PLT32 relocation. NB: Symbol with
8832 non-default visibilities are treated as normal global symbol
8833 so that PLT32 relocation can be used as a marker for 32-bit
8834 PC-relative branches. It is useful for linker relaxation. */
8845 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8847 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8849 /* This is a loop or jecxz type instruction. */
8851 if (i
.prefix
[ADDR_PREFIX
] != 0)
8853 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8856 /* Pentium4 branch hints. */
8857 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8858 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8860 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8869 if (flag_code
== CODE_16BIT
)
8872 if (i
.prefix
[DATA_PREFIX
] != 0)
8874 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8876 code16
^= flip_code16(code16
);
8884 /* BND prefixed jump. */
8885 if (i
.prefix
[BND_PREFIX
] != 0)
8887 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8891 if (i
.prefix
[REX_PREFIX
] != 0)
8893 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8897 if (i
.prefixes
!= 0)
8898 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8900 if (now_seg
== absolute_section
)
8902 abs_section_offset
+= i
.opcode_length
+ size
;
8906 p
= frag_more (i
.opcode_length
+ size
);
8907 switch (i
.opcode_length
)
8910 *p
++ = i
.tm
.base_opcode
>> 8;
8913 *p
++ = i
.tm
.base_opcode
;
8919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8920 if (flag_code
== CODE_64BIT
&& size
== 4
8921 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
8922 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8923 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8926 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8928 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8929 i
.op
[0].disps
, 1, jump_reloc
);
8931 /* All jumps handled here are signed, but don't unconditionally use a
8932 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8933 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8938 fixP
->fx_signed
= 1;
8942 if (i
.tm
.mnem_off
== MN_xbegin
)
8943 fixP
->fx_signed
= 1;
8947 if (flag_code
== CODE_64BIT
)
8948 fixP
->fx_signed
= 1;
8954 output_interseg_jump (void)
8962 if (flag_code
== CODE_16BIT
)
8966 if (i
.prefix
[DATA_PREFIX
] != 0)
8973 gas_assert (!i
.prefix
[REX_PREFIX
]);
8979 if (i
.prefixes
!= 0)
8980 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
8982 if (now_seg
== absolute_section
)
8984 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8988 /* 1 opcode; 2 segment; offset */
8989 p
= frag_more (prefix
+ 1 + 2 + size
);
8991 if (i
.prefix
[DATA_PREFIX
] != 0)
8992 *p
++ = DATA_PREFIX_OPCODE
;
8994 if (i
.prefix
[REX_PREFIX
] != 0)
8995 *p
++ = i
.prefix
[REX_PREFIX
];
8997 *p
++ = i
.tm
.base_opcode
;
8998 if (i
.op
[1].imms
->X_op
== O_constant
)
9000 offsetT n
= i
.op
[1].imms
->X_add_number
;
9003 && !fits_in_unsigned_word (n
)
9004 && !fits_in_signed_word (n
))
9006 as_bad (_("16-bit jump out of range"));
9009 md_number_to_chars (p
, n
, size
);
9012 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9013 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9016 if (i
.op
[0].imms
->X_op
== O_constant
)
9017 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9019 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9020 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9028 asection
*seg
= now_seg
;
9029 subsegT subseg
= now_subseg
;
9031 unsigned int alignment
, align_size_1
;
9032 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9033 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9034 unsigned int padding
;
9036 if (!IS_ELF
|| !x86_used_note
)
9039 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9041 /* The .note.gnu.property section layout:
9043 Field Length Contents
9046 n_descsz 4 The note descriptor size
9047 n_type 4 NT_GNU_PROPERTY_TYPE_0
9049 n_desc n_descsz The program property array
9053 /* Create the .note.gnu.property section. */
9054 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9055 bfd_set_section_flags (sec
,
9062 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9073 bfd_set_section_alignment (sec
, alignment
);
9074 elf_section_type (sec
) = SHT_NOTE
;
9076 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9078 isa_1_descsz_raw
= 4 + 4 + 4;
9079 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9080 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9082 feature_2_descsz_raw
= isa_1_descsz
;
9083 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9085 feature_2_descsz_raw
+= 4 + 4 + 4;
9086 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9087 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9090 descsz
= feature_2_descsz
;
9091 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9092 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9094 /* Write n_namsz. */
9095 md_number_to_chars (p
, (valueT
) 4, 4);
9097 /* Write n_descsz. */
9098 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9101 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9104 memcpy (p
+ 4 * 3, "GNU", 4);
9106 /* Write 4-byte type. */
9107 md_number_to_chars (p
+ 4 * 4,
9108 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9110 /* Write 4-byte data size. */
9111 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9113 /* Write 4-byte data. */
9114 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9116 /* Zero out paddings. */
9117 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9119 memset (p
+ 4 * 7, 0, padding
);
9121 /* Write 4-byte type. */
9122 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9123 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9125 /* Write 4-byte data size. */
9126 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9128 /* Write 4-byte data. */
9129 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9130 (valueT
) x86_feature_2_used
, 4);
9132 /* Zero out paddings. */
9133 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9135 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9137 /* We probably can't restore the current segment, for there likely
9140 subseg_set (seg
, subseg
);
9144 x86_support_sframe_p (void)
9146 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9147 return (x86_elf_abi
== X86_64_ABI
);
9151 x86_sframe_ra_tracking_p (void)
9153 /* In AMD64, return address is always stored on the stack at a fixed offset
9154 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9155 Do not track explicitly via an SFrame Frame Row Entry. */
9160 x86_sframe_cfa_ra_offset (void)
9162 gas_assert (x86_elf_abi
== X86_64_ABI
);
9163 return (offsetT
) -8;
9167 x86_sframe_get_abi_arch (void)
9169 unsigned char sframe_abi_arch
= 0;
9171 if (x86_support_sframe_p ())
9173 gas_assert (!target_big_endian
);
9174 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9177 return sframe_abi_arch
;
9183 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9184 const char *frag_now_ptr
)
9186 unsigned int len
= 0;
9188 if (start_frag
!= frag_now
)
9190 const fragS
*fr
= start_frag
;
9195 } while (fr
&& fr
!= frag_now
);
9198 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9201 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9202 be macro-fused with conditional jumps.
9203 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9204 or is one of the following format:
9217 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9219 /* No RIP address. */
9220 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9223 /* No opcodes outside of base encoding space. */
9224 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9227 /* add, sub without add/sub m, imm. */
9228 if (i
.tm
.base_opcode
<= 5
9229 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9230 || ((i
.tm
.base_opcode
| 3) == 0x83
9231 && (i
.tm
.extension_opcode
== 0x5
9232 || i
.tm
.extension_opcode
== 0x0)))
9234 *mf_cmp_p
= mf_cmp_alu_cmp
;
9235 return !(i
.mem_operands
&& i
.imm_operands
);
9238 /* and without and m, imm. */
9239 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9240 || ((i
.tm
.base_opcode
| 3) == 0x83
9241 && i
.tm
.extension_opcode
== 0x4))
9243 *mf_cmp_p
= mf_cmp_test_and
;
9244 return !(i
.mem_operands
&& i
.imm_operands
);
9247 /* test without test m imm. */
9248 if ((i
.tm
.base_opcode
| 1) == 0x85
9249 || (i
.tm
.base_opcode
| 1) == 0xa9
9250 || ((i
.tm
.base_opcode
| 1) == 0xf7
9251 && i
.tm
.extension_opcode
== 0))
9253 *mf_cmp_p
= mf_cmp_test_and
;
9254 return !(i
.mem_operands
&& i
.imm_operands
);
9257 /* cmp without cmp m, imm. */
9258 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9259 || ((i
.tm
.base_opcode
| 3) == 0x83
9260 && (i
.tm
.extension_opcode
== 0x7)))
9262 *mf_cmp_p
= mf_cmp_alu_cmp
;
9263 return !(i
.mem_operands
&& i
.imm_operands
);
9266 /* inc, dec without inc/dec m. */
9267 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9268 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9269 || ((i
.tm
.base_opcode
| 1) == 0xff
9270 && i
.tm
.extension_opcode
<= 0x1))
9272 *mf_cmp_p
= mf_cmp_incdec
;
9273 return !i
.mem_operands
;
9279 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9282 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9284 /* NB: Don't work with COND_JUMP86 without i386. */
9285 if (!align_branch_power
9286 || now_seg
== absolute_section
9287 || !cpu_arch_flags
.bitfield
.cpui386
9288 || !(align_branch
& align_branch_fused_bit
))
9291 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9293 if (last_insn
.kind
== last_insn_other
9294 || last_insn
.seg
!= now_seg
)
9297 as_warn_where (last_insn
.file
, last_insn
.line
,
9298 _("`%s` skips -malign-branch-boundary on `%s`"),
9299 last_insn
.name
, insn_name (&i
.tm
));
9305 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9308 add_branch_prefix_frag_p (void)
9310 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9311 to PadLock instructions since they include prefixes in opcode. */
9312 if (!align_branch_power
9313 || !align_branch_prefix_size
9314 || now_seg
== absolute_section
9315 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9316 || !cpu_arch_flags
.bitfield
.cpui386
)
9319 /* Don't add prefix if it is a prefix or there is no operand in case
9320 that segment prefix is special. */
9321 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9324 if (last_insn
.kind
== last_insn_other
9325 || last_insn
.seg
!= now_seg
)
9329 as_warn_where (last_insn
.file
, last_insn
.line
,
9330 _("`%s` skips -malign-branch-boundary on `%s`"),
9331 last_insn
.name
, insn_name (&i
.tm
));
9336 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9339 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9340 enum mf_jcc_kind
*mf_jcc_p
)
9344 /* NB: Don't work with COND_JUMP86 without i386. */
9345 if (!align_branch_power
9346 || now_seg
== absolute_section
9347 || !cpu_arch_flags
.bitfield
.cpui386
9348 || i
.tm
.opcode_space
!= SPACE_BASE
)
9353 /* Check for jcc and direct jmp. */
9354 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9356 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9358 *branch_p
= align_branch_jmp
;
9359 add_padding
= align_branch
& align_branch_jmp_bit
;
9363 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9364 igore the lowest bit. */
9365 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9366 *branch_p
= align_branch_jcc
;
9367 if ((align_branch
& align_branch_jcc_bit
))
9371 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9374 *branch_p
= align_branch_ret
;
9375 if ((align_branch
& align_branch_ret_bit
))
9380 /* Check for indirect jmp, direct and indirect calls. */
9381 if (i
.tm
.base_opcode
== 0xe8)
9384 *branch_p
= align_branch_call
;
9385 if ((align_branch
& align_branch_call_bit
))
9388 else if (i
.tm
.base_opcode
== 0xff
9389 && (i
.tm
.extension_opcode
== 2
9390 || i
.tm
.extension_opcode
== 4))
9392 /* Indirect call and jmp. */
9393 *branch_p
= align_branch_indirect
;
9394 if ((align_branch
& align_branch_indirect_bit
))
9401 && (i
.op
[0].disps
->X_op
== O_symbol
9402 || (i
.op
[0].disps
->X_op
== O_subtract
9403 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9405 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9406 /* No padding to call to global or undefined tls_get_addr. */
9407 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9408 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9414 && last_insn
.kind
!= last_insn_other
9415 && last_insn
.seg
== now_seg
)
9418 as_warn_where (last_insn
.file
, last_insn
.line
,
9419 _("`%s` skips -malign-branch-boundary on `%s`"),
9420 last_insn
.name
, insn_name (&i
.tm
));
9430 fragS
*insn_start_frag
;
9431 offsetT insn_start_off
;
9432 fragS
*fragP
= NULL
;
9433 enum align_branch_kind branch
= align_branch_none
;
9434 /* The initializer is arbitrary just to avoid uninitialized error.
9435 it's actually either assigned in add_branch_padding_frag_p
9436 or never be used. */
9437 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9440 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9442 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9443 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9444 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9446 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9447 || i
.tm
.cpu_flags
.bitfield
.cpu287
9448 || i
.tm
.cpu_flags
.bitfield
.cpu387
9449 || i
.tm
.cpu_flags
.bitfield
.cpu687
9450 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9451 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9453 if ((i
.xstate
& xstate_mmx
)
9454 || i
.tm
.mnem_off
== MN_emms
9455 || i
.tm
.mnem_off
== MN_femms
)
9456 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9460 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9461 i
.xstate
|= xstate_zmm
;
9462 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9463 i
.xstate
|= xstate_ymm
;
9464 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9465 i
.xstate
|= xstate_xmm
;
9468 /* vzeroall / vzeroupper */
9469 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9470 i
.xstate
|= xstate_ymm
;
9472 if ((i
.xstate
& xstate_xmm
)
9473 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9474 || (i
.tm
.base_opcode
== 0xae
9475 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9476 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9477 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9478 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9479 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9481 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9482 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9483 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9484 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9485 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9486 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9487 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9488 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9489 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9490 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9491 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9492 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9493 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9494 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9496 if (x86_feature_2_used
9497 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9498 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9499 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9500 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9501 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9502 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9503 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9504 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9505 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9506 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9507 /* LAHF-SAHF insns in 64-bit mode. */
9508 || (flag_code
== CODE_64BIT
9509 && (i
.tm
.base_opcode
| 1) == 0x9f
9510 && i
.tm
.opcode_space
== SPACE_BASE
))
9511 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9512 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9513 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9514 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9515 XOP, FMA4, LPW, TBM, and AMX. */
9516 || (i
.tm
.opcode_modifier
.vex
9517 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9518 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9519 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9520 && !i
.tm
.cpu_flags
.bitfield
.cpuxop
9521 && !i
.tm
.cpu_flags
.bitfield
.cpufma4
9522 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9523 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9524 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9525 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9526 || i
.tm
.cpu_flags
.bitfield
.cpufma
9527 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9528 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9529 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9530 || (x86_feature_2_used
9531 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9532 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9533 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9534 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9535 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9536 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9537 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9538 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9539 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9540 AVX512-4FMAPS, and AVX512-4VNNIW. */
9541 || (i
.tm
.opcode_modifier
.evex
9542 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9543 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9544 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
9545 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9546 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9550 /* Tie dwarf2 debug info to the address at the start of the insn.
9551 We can't do this after the insn has been output as the current
9552 frag may have been closed off. eg. by frag_var. */
9553 dwarf2_emit_insn (0);
9555 insn_start_frag
= frag_now
;
9556 insn_start_off
= frag_now_fix ();
9558 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9561 /* Branch can be 8 bytes. Leave some room for prefixes. */
9562 unsigned int max_branch_padding_size
= 14;
9564 /* Align section to boundary. */
9565 record_alignment (now_seg
, align_branch_power
);
9567 /* Make room for padding. */
9568 frag_grow (max_branch_padding_size
);
9570 /* Start of the padding. */
9575 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9576 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9579 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9580 fragP
->tc_frag_data
.branch_type
= branch
;
9581 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9584 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9585 && !pre_386_16bit_warned
)
9587 as_warn (_("use .code16 to ensure correct addressing mode"));
9588 pre_386_16bit_warned
= true;
9592 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9594 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9595 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9597 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9598 output_interseg_jump ();
9601 /* Output normal instructions here. */
9605 enum mf_cmp_kind mf_cmp
;
9608 && (i
.tm
.base_opcode
== 0xaee8
9609 || i
.tm
.base_opcode
== 0xaef0
9610 || i
.tm
.base_opcode
== 0xaef8))
9612 /* Encode lfence, mfence, and sfence as
9613 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9614 if (flag_code
== CODE_16BIT
)
9615 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9616 else if (omit_lock_prefix
)
9617 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9619 else if (now_seg
!= absolute_section
)
9621 offsetT val
= 0x240483f0ULL
;
9624 md_number_to_chars (p
, val
, 5);
9627 abs_section_offset
+= 5;
9631 /* Some processors fail on LOCK prefix. This options makes
9632 assembler ignore LOCK prefix and serves as a workaround. */
9633 if (omit_lock_prefix
)
9635 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9636 && i
.tm
.opcode_modifier
.isprefix
)
9638 i
.prefix
[LOCK_PREFIX
] = 0;
9642 /* Skip if this is a branch. */
9644 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9646 /* Make room for padding. */
9647 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9652 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9653 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9656 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9657 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9658 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9660 else if (add_branch_prefix_frag_p ())
9662 unsigned int max_prefix_size
= align_branch_prefix_size
;
9664 /* Make room for padding. */
9665 frag_grow (max_prefix_size
);
9670 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9671 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9674 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9677 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9678 don't need the explicit prefix. */
9679 if (!is_any_vex_encoding (&i
.tm
))
9681 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9690 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9691 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9695 switch (i
.opcode_length
)
9700 /* Check for pseudo prefixes. */
9701 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9703 as_bad_where (insn_start_frag
->fr_file
,
9704 insn_start_frag
->fr_line
,
9705 _("pseudo prefix without instruction"));
9715 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9716 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9717 R_X86_64_GOTTPOFF relocation so that linker can safely
9718 perform IE->LE optimization. A dummy REX_OPCODE prefix
9719 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9720 relocation for GDesc -> IE/LE optimization. */
9721 if (x86_elf_abi
== X86_64_X32_ABI
9723 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9724 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9725 && i
.prefix
[REX_PREFIX
] == 0)
9726 add_prefix (REX_OPCODE
);
9729 /* The prefix bytes. */
9730 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9732 frag_opcode_byte (*q
);
9736 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9742 frag_opcode_byte (*q
);
9745 /* There should be no other prefixes for instructions
9750 /* For EVEX instructions i.vrex should become 0 after
9751 build_evex_prefix. For VEX instructions upper 16 registers
9752 aren't available, so VREX should be 0. */
9755 /* Now the VEX prefix. */
9756 if (now_seg
!= absolute_section
)
9758 p
= frag_more (i
.vex
.length
);
9759 for (j
= 0; j
< i
.vex
.length
; j
++)
9760 p
[j
] = i
.vex
.bytes
[j
];
9763 abs_section_offset
+= i
.vex
.length
;
9766 /* Now the opcode; be careful about word order here! */
9767 j
= i
.opcode_length
;
9769 switch (i
.tm
.opcode_space
)
9784 if (now_seg
== absolute_section
)
9785 abs_section_offset
+= j
;
9788 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9794 && i
.tm
.opcode_space
!= SPACE_BASE
)
9797 if (i
.tm
.opcode_space
!= SPACE_0F
)
9798 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
9802 switch (i
.opcode_length
)
9805 /* Put out high byte first: can't use md_number_to_chars! */
9806 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9809 *p
= i
.tm
.base_opcode
& 0xff;
9818 /* Now the modrm byte and sib byte (if present). */
9819 if (i
.tm
.opcode_modifier
.modrm
)
9821 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9823 | (i
.rm
.mode
<< 6));
9824 /* If i.rm.regmem == ESP (4)
9825 && i.rm.mode != (Register mode)
9827 ==> need second modrm byte. */
9828 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9830 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9831 frag_opcode_byte ((i
.sib
.base
<< 0)
9832 | (i
.sib
.index
<< 3)
9833 | (i
.sib
.scale
<< 6));
9836 if (i
.disp_operands
)
9837 output_disp (insn_start_frag
, insn_start_off
);
9840 output_imm (insn_start_frag
, insn_start_off
);
9843 * frag_now_fix () returning plain abs_section_offset when we're in the
9844 * absolute section, and abs_section_offset not getting updated as data
9845 * gets added to the frag breaks the logic below.
9847 if (now_seg
!= absolute_section
)
9849 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9851 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9855 /* NB: Don't add prefix with GOTPC relocation since
9856 output_disp() above depends on the fixed encoding
9857 length. Can't add prefix with TLS relocation since
9858 it breaks TLS linker optimization. */
9859 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9860 /* Prefix count on the current instruction. */
9861 unsigned int count
= i
.vex
.length
;
9863 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9864 /* REX byte is encoded in VEX/EVEX prefix. */
9865 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9868 /* Count prefixes for extended opcode maps. */
9870 switch (i
.tm
.opcode_space
)
9885 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9888 /* Set the maximum prefix size in BRANCH_PREFIX
9890 if (fragP
->tc_frag_data
.max_bytes
> max
)
9891 fragP
->tc_frag_data
.max_bytes
= max
;
9892 if (fragP
->tc_frag_data
.max_bytes
> count
)
9893 fragP
->tc_frag_data
.max_bytes
-= count
;
9895 fragP
->tc_frag_data
.max_bytes
= 0;
9899 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9901 unsigned int max_prefix_size
;
9902 if (align_branch_prefix_size
> max
)
9903 max_prefix_size
= max
;
9905 max_prefix_size
= align_branch_prefix_size
;
9906 if (max_prefix_size
> count
)
9907 fragP
->tc_frag_data
.max_prefix_length
9908 = max_prefix_size
- count
;
9911 /* Use existing segment prefix if possible. Use CS
9912 segment prefix in 64-bit mode. In 32-bit mode, use SS
9913 segment prefix with ESP/EBP base register and use DS
9914 segment prefix without ESP/EBP base register. */
9915 if (i
.prefix
[SEG_PREFIX
])
9916 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9917 else if (flag_code
== CODE_64BIT
)
9918 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9920 && (i
.base_reg
->reg_num
== 4
9921 || i
.base_reg
->reg_num
== 5))
9922 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9924 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9929 /* NB: Don't work with COND_JUMP86 without i386. */
9930 if (align_branch_power
9931 && now_seg
!= absolute_section
9932 && cpu_arch_flags
.bitfield
.cpui386
)
9934 /* Terminate each frag so that we can add prefix and check for
9936 frag_wane (frag_now
);
9943 pi ("" /*line*/, &i
);
9945 #endif /* DEBUG386 */
9948 /* Return the size of the displacement operand N. */
9951 disp_size (unsigned int n
)
9955 if (i
.types
[n
].bitfield
.disp64
)
9957 else if (i
.types
[n
].bitfield
.disp8
)
9959 else if (i
.types
[n
].bitfield
.disp16
)
9964 /* Return the size of the immediate operand N. */
9967 imm_size (unsigned int n
)
9970 if (i
.types
[n
].bitfield
.imm64
)
9972 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9974 else if (i
.types
[n
].bitfield
.imm16
)
9980 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9985 for (n
= 0; n
< i
.operands
; n
++)
9987 if (operand_type_check (i
.types
[n
], disp
))
9989 int size
= disp_size (n
);
9991 if (now_seg
== absolute_section
)
9992 abs_section_offset
+= size
;
9993 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9995 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9997 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9999 p
= frag_more (size
);
10000 md_number_to_chars (p
, val
, size
);
10004 enum bfd_reloc_code_real reloc_type
;
10005 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10006 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10007 && (!want_disp32 (&i
.tm
)
10008 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10009 && !i
.types
[n
].bitfield
.baseindex
)))
10013 /* We can't have 8 bit displacement here. */
10014 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10016 /* The PC relative address is computed relative
10017 to the instruction boundary, so in case immediate
10018 fields follows, we need to adjust the value. */
10019 if (pcrel
&& i
.imm_operands
)
10024 for (n1
= 0; n1
< i
.operands
; n1
++)
10025 if (operand_type_check (i
.types
[n1
], imm
))
10027 /* Only one immediate is allowed for PC
10028 relative address. */
10029 gas_assert (sz
== 0);
10030 sz
= imm_size (n1
);
10031 i
.op
[n
].disps
->X_add_number
-= sz
;
10033 /* We should find the immediate. */
10034 gas_assert (sz
!= 0);
10037 p
= frag_more (size
);
10038 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10040 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10041 && (((reloc_type
== BFD_RELOC_32
10042 || reloc_type
== BFD_RELOC_X86_64_32S
10043 || (reloc_type
== BFD_RELOC_64
10045 && (i
.op
[n
].disps
->X_op
== O_symbol
10046 || (i
.op
[n
].disps
->X_op
== O_add
10047 && ((symbol_get_value_expression
10048 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10050 || reloc_type
== BFD_RELOC_32_PCREL
))
10054 reloc_type
= BFD_RELOC_386_GOTPC
;
10055 i
.has_gotpc_tls_reloc
= true;
10056 i
.op
[n
].disps
->X_add_number
+=
10057 encoding_length (insn_start_frag
, insn_start_off
, p
);
10059 else if (reloc_type
== BFD_RELOC_64
)
10060 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10062 /* Don't do the adjustment for x86-64, as there
10063 the pcrel addressing is relative to the _next_
10064 insn, and that is taken care of in other code. */
10065 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10067 else if (align_branch_power
)
10069 switch (reloc_type
)
10071 case BFD_RELOC_386_TLS_GD
:
10072 case BFD_RELOC_386_TLS_LDM
:
10073 case BFD_RELOC_386_TLS_IE
:
10074 case BFD_RELOC_386_TLS_IE_32
:
10075 case BFD_RELOC_386_TLS_GOTIE
:
10076 case BFD_RELOC_386_TLS_GOTDESC
:
10077 case BFD_RELOC_386_TLS_DESC_CALL
:
10078 case BFD_RELOC_X86_64_TLSGD
:
10079 case BFD_RELOC_X86_64_TLSLD
:
10080 case BFD_RELOC_X86_64_GOTTPOFF
:
10081 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10082 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10083 i
.has_gotpc_tls_reloc
= true;
10088 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10089 size
, i
.op
[n
].disps
, pcrel
,
10092 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10093 && !i
.prefix
[ADDR_PREFIX
])
10094 fixP
->fx_signed
= 1;
10096 /* Check for "call/jmp *mem", "mov mem, %reg",
10097 "test %reg, mem" and "binop mem, %reg" where binop
10098 is one of adc, add, and, cmp, or, sbb, sub, xor
10099 instructions without data prefix. Always generate
10100 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10101 if (i
.prefix
[DATA_PREFIX
] == 0
10102 && (generate_relax_relocations
10105 && i
.rm
.regmem
== 5))
10107 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10108 && i
.tm
.opcode_space
== SPACE_BASE
10109 && ((i
.operands
== 1
10110 && i
.tm
.base_opcode
== 0xff
10111 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10112 || (i
.operands
== 2
10113 && (i
.tm
.base_opcode
== 0x8b
10114 || i
.tm
.base_opcode
== 0x85
10115 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10119 fixP
->fx_tcbit
= i
.rex
!= 0;
10121 && (i
.base_reg
->reg_num
== RegIP
))
10122 fixP
->fx_tcbit2
= 1;
10125 fixP
->fx_tcbit2
= 1;
10133 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10138 for (n
= 0; n
< i
.operands
; n
++)
10140 if (operand_type_check (i
.types
[n
], imm
))
10142 int size
= imm_size (n
);
10144 if (now_seg
== absolute_section
)
10145 abs_section_offset
+= size
;
10146 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10150 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10152 p
= frag_more (size
);
10153 md_number_to_chars (p
, val
, size
);
10157 /* Not absolute_section.
10158 Need a 32-bit fixup (don't support 8bit
10159 non-absolute imms). Try to support other
10161 enum bfd_reloc_code_real reloc_type
;
10164 if (i
.types
[n
].bitfield
.imm32s
10165 && (i
.suffix
== QWORD_MNEM_SUFFIX
10166 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10171 p
= frag_more (size
);
10172 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10174 /* This is tough to explain. We end up with this one if we
10175 * have operands that look like
10176 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10177 * obtain the absolute address of the GOT, and it is strongly
10178 * preferable from a performance point of view to avoid using
10179 * a runtime relocation for this. The actual sequence of
10180 * instructions often look something like:
10185 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10187 * The call and pop essentially return the absolute address
10188 * of the label .L66 and store it in %ebx. The linker itself
10189 * will ultimately change the first operand of the addl so
10190 * that %ebx points to the GOT, but to keep things simple, the
10191 * .o file must have this operand set so that it generates not
10192 * the absolute address of .L66, but the absolute address of
10193 * itself. This allows the linker itself simply treat a GOTPC
10194 * relocation as asking for a pcrel offset to the GOT to be
10195 * added in, and the addend of the relocation is stored in the
10196 * operand field for the instruction itself.
10198 * Our job here is to fix the operand so that it would add
10199 * the correct offset so that %ebx would point to itself. The
10200 * thing that is tricky is that .-.L66 will point to the
10201 * beginning of the instruction, so we need to further modify
10202 * the operand so that it will point to itself. There are
10203 * other cases where you have something like:
10205 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10207 * and here no correction would be required. Internally in
10208 * the assembler we treat operands of this form as not being
10209 * pcrel since the '.' is explicitly mentioned, and I wonder
10210 * whether it would simplify matters to do it this way. Who
10211 * knows. In earlier versions of the PIC patches, the
10212 * pcrel_adjust field was used to store the correction, but
10213 * since the expression is not pcrel, I felt it would be
10214 * confusing to do it this way. */
10216 if ((reloc_type
== BFD_RELOC_32
10217 || reloc_type
== BFD_RELOC_X86_64_32S
10218 || reloc_type
== BFD_RELOC_64
)
10220 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10221 && (i
.op
[n
].imms
->X_op
== O_symbol
10222 || (i
.op
[n
].imms
->X_op
== O_add
10223 && ((symbol_get_value_expression
10224 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10228 reloc_type
= BFD_RELOC_386_GOTPC
;
10229 else if (size
== 4)
10230 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10231 else if (size
== 8)
10232 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10233 i
.has_gotpc_tls_reloc
= true;
10234 i
.op
[n
].imms
->X_add_number
+=
10235 encoding_length (insn_start_frag
, insn_start_off
, p
);
10237 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10238 i
.op
[n
].imms
, 0, reloc_type
);
10244 /* x86_cons_fix_new is called via the expression parsing code when a
10245 reloc is needed. We use this hook to get the correct .got reloc. */
10246 static int cons_sign
= -1;
10249 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10250 expressionS
*exp
, bfd_reloc_code_real_type r
)
10252 r
= reloc (len
, 0, cons_sign
, r
);
10255 if (exp
->X_op
== O_secrel
)
10257 exp
->X_op
= O_symbol
;
10258 r
= BFD_RELOC_32_SECREL
;
10260 else if (exp
->X_op
== O_secidx
)
10261 r
= BFD_RELOC_16_SECIDX
;
10264 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10267 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10268 purpose of the `.dc.a' internal pseudo-op. */
10271 x86_address_bytes (void)
10273 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10275 return stdoutput
->arch_info
->bits_per_address
/ 8;
10278 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10279 || defined (LEX_AT)) && !defined (TE_PE)
10280 # define lex_got(reloc, adjust, types) NULL
10282 /* Parse operands of the form
10283 <symbol>@GOTOFF+<nnn>
10284 and similar .plt or .got references.
10286 If we find one, set up the correct relocation in RELOC and copy the
10287 input string, minus the `@GOTOFF' into a malloc'd buffer for
10288 parsing by the calling routine. Return this buffer, and if ADJUST
10289 is non-null set it to the length of the string we removed from the
10290 input line. Otherwise return NULL. */
10292 lex_got (enum bfd_reloc_code_real
*rel
,
10294 i386_operand_type
*types
)
10296 /* Some of the relocations depend on the size of what field is to
10297 be relocated. But in our callers i386_immediate and i386_displacement
10298 we don't yet know the operand size (this will be set by insn
10299 matching). Hence we record the word32 relocation here,
10300 and adjust the reloc according to the real size in reloc(). */
10301 static const struct
10305 const enum bfd_reloc_code_real rel
[2];
10306 const i386_operand_type types64
;
10307 bool need_GOT_symbol
;
10312 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10313 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10314 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10315 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10316 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10317 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10318 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10319 { .imm64 = 1, .disp64 = 1 } }
10322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10323 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10324 BFD_RELOC_SIZE32
},
10325 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10327 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10328 BFD_RELOC_X86_64_PLTOFF64
},
10329 { .bitfield
= { .imm64
= 1 } }, true },
10330 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10331 BFD_RELOC_X86_64_PLT32
},
10332 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10333 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10334 BFD_RELOC_X86_64_GOTPLT64
},
10335 OPERAND_TYPE_IMM64_DISP64
, true },
10336 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10337 BFD_RELOC_X86_64_GOTOFF64
},
10338 OPERAND_TYPE_IMM64_DISP64
, true },
10339 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10340 BFD_RELOC_X86_64_GOTPCREL
},
10341 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10342 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10343 BFD_RELOC_X86_64_TLSGD
},
10344 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10345 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10346 _dummy_first_bfd_reloc_code_real
},
10347 OPERAND_TYPE_NONE
, true },
10348 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10349 BFD_RELOC_X86_64_TLSLD
},
10350 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10351 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10352 BFD_RELOC_X86_64_GOTTPOFF
},
10353 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10354 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10355 BFD_RELOC_X86_64_TPOFF32
},
10356 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10357 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10358 _dummy_first_bfd_reloc_code_real
},
10359 OPERAND_TYPE_NONE
, true },
10360 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10361 BFD_RELOC_X86_64_DTPOFF32
},
10362 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10363 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10364 _dummy_first_bfd_reloc_code_real
},
10365 OPERAND_TYPE_NONE
, true },
10366 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10367 _dummy_first_bfd_reloc_code_real
},
10368 OPERAND_TYPE_NONE
, true },
10369 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10370 BFD_RELOC_X86_64_GOT32
},
10371 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10372 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10373 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10374 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10375 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10376 BFD_RELOC_X86_64_TLSDESC_CALL
},
10377 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10379 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10380 BFD_RELOC_32_SECREL
},
10381 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10384 #undef OPERAND_TYPE_IMM32_32S_DISP32
10385 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10386 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10387 #undef OPERAND_TYPE_IMM64_DISP64
10393 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10398 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10399 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10402 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10404 int len
= gotrel
[j
].len
;
10405 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10407 if (gotrel
[j
].rel
[object_64bit
] != 0)
10410 char *tmpbuf
, *past_reloc
;
10412 *rel
= gotrel
[j
].rel
[object_64bit
];
10416 if (flag_code
!= CODE_64BIT
)
10418 types
->bitfield
.imm32
= 1;
10419 types
->bitfield
.disp32
= 1;
10422 *types
= gotrel
[j
].types64
;
10425 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10426 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10428 /* The length of the first part of our input line. */
10429 first
= cp
- input_line_pointer
;
10431 /* The second part goes from after the reloc token until
10432 (and including) an end_of_line char or comma. */
10433 past_reloc
= cp
+ 1 + len
;
10435 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10437 second
= cp
+ 1 - past_reloc
;
10439 /* Allocate and copy string. The trailing NUL shouldn't
10440 be necessary, but be safe. */
10441 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10442 memcpy (tmpbuf
, input_line_pointer
, first
);
10443 if (second
!= 0 && *past_reloc
!= ' ')
10444 /* Replace the relocation token with ' ', so that
10445 errors like foo@GOTOFF1 will be detected. */
10446 tmpbuf
[first
++] = ' ';
10448 /* Increment length by 1 if the relocation token is
10453 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10454 tmpbuf
[first
+ second
] = '\0';
10458 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10459 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10464 /* Might be a symbol version string. Don't as_bad here. */
10469 bfd_reloc_code_real_type
10470 x86_cons (expressionS
*exp
, int size
)
10472 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10474 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10475 && !defined (LEX_AT)) \
10477 intel_syntax
= -intel_syntax
;
10480 if (size
== 4 || (object_64bit
&& size
== 8))
10482 /* Handle @GOTOFF and the like in an expression. */
10484 char *gotfree_input_line
;
10487 save
= input_line_pointer
;
10488 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10489 if (gotfree_input_line
)
10490 input_line_pointer
= gotfree_input_line
;
10494 if (gotfree_input_line
)
10496 /* expression () has merrily parsed up to the end of line,
10497 or a comma - in the wrong buffer. Transfer how far
10498 input_line_pointer has moved to the right buffer. */
10499 input_line_pointer
= (save
10500 + (input_line_pointer
- gotfree_input_line
)
10502 free (gotfree_input_line
);
10503 if (exp
->X_op
== O_constant
10504 || exp
->X_op
== O_absent
10505 || exp
->X_op
== O_illegal
10506 || exp
->X_op
== O_register
10507 || exp
->X_op
== O_big
)
10509 char c
= *input_line_pointer
;
10510 *input_line_pointer
= 0;
10511 as_bad (_("missing or invalid expression `%s'"), save
);
10512 *input_line_pointer
= c
;
10514 else if ((got_reloc
== BFD_RELOC_386_PLT32
10515 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10516 && exp
->X_op
!= O_symbol
)
10518 char c
= *input_line_pointer
;
10519 *input_line_pointer
= 0;
10520 as_bad (_("invalid PLT expression `%s'"), save
);
10521 *input_line_pointer
= c
;
10528 intel_syntax
= -intel_syntax
;
10531 i386_intel_simplify (exp
);
10536 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10537 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10538 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10544 signed_cons (int size
)
10553 s_insn (int dummy ATTRIBUTE_UNUSED
)
10555 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
;
10556 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10560 bool vex
= false, xop
= false, evex
= false;
10561 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10565 saved_char
= *saved_ilp
;
10568 end
= parse_insn (line
, mnemonic
, true);
10572 *saved_ilp
= saved_char
;
10573 ignore_rest_of_line ();
10577 line
+= end
- line
;
10579 current_templates
= &tt
;
10580 i
.tm
.mnem_off
= MN__insn
;
10582 if (startswith (line
, "VEX")
10583 && (line
[3] == '.' || is_space_char (line
[3])))
10588 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10591 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10593 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10594 && (*e
== '.' || is_space_char (*e
)))
10597 /* Arrange for build_vex_prefix() to emit 0x8f. */
10598 i
.tm
.opcode_space
= SPACE_XOP08
;
10599 i
.insn_opcode_space
= n
;
10603 else if (startswith (line
, "EVEX")
10604 && (line
[4] == '.' || is_space_char (line
[4])))
10611 ? i
.vec_encoding
== vex_encoding_evex
10613 ? i
.vec_encoding
== vex_encoding_vex
10614 || i
.vec_encoding
== vex_encoding_vex3
10615 : i
.vec_encoding
!= vex_encoding_default
)
10617 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10621 if (line
> end
&& *line
== '.')
10623 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
10631 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10633 i
.tm
.opcode_modifier
.vex
= VEX128
;
10638 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10640 i
.tm
.opcode_modifier
.vex
= VEX256
;
10645 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10650 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
10654 if (line
[3] == 'G')
10657 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10659 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10665 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
10670 if (line
[2] == '2' && line
[3] == '8')
10673 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10675 i
.tm
.opcode_modifier
.vex
= VEX128
;
10681 if (line
[2] == '5' && line
[3] == '6')
10684 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10686 i
.tm
.opcode_modifier
.vex
= VEX256
;
10692 if (evex
&& line
[2] == '1' && line
[3] == '2')
10694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10701 if (line
> end
&& *line
== '.')
10703 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
10707 if (line
[2] == 'P')
10712 if (line
[2] == '6')
10714 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
10719 case 'F': case 'f':
10720 if (line
[2] == '3')
10722 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
10725 else if (line
[2] == '2')
10727 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
10734 if (line
> end
&& !xop
&& *line
== '.')
10736 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
10740 if (TOUPPER (line
[2]) != 'F')
10742 if (line
[3] == '.' || is_space_char (line
[3]))
10744 i
.insn_opcode_space
= SPACE_0F
;
10747 else if (line
[3] == '3'
10748 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
10749 && (line
[5] == '.' || is_space_char (line
[5])))
10751 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
10757 if (ISDIGIT (line
[2]) && line
[2] != '0')
10760 unsigned long n
= strtoul (line
+ 2, &e
, 10);
10762 if (n
<= (evex
? 15 : 31)
10763 && (*e
== '.' || is_space_char (*e
)))
10765 i
.insn_opcode_space
= n
;
10773 if (line
> end
&& *line
== '.' && line
[1] == 'W')
10775 /* VEX.W, XOP.W, EVEX.W */
10779 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
10783 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
10787 if (line
[3] == 'G')
10789 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
10795 if (i
.tm
.opcode_modifier
.vexw
)
10799 if (line
> end
&& *line
&& !is_space_char (*line
))
10801 /* Improve diagnostic a little. */
10802 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
10807 input_line_pointer
= line
;
10808 val
= get_absolute_expression ();
10809 line
= input_line_pointer
;
10811 for (j
= 1; j
< sizeof(val
); ++j
)
10812 if (!(val
>> (j
* 8)))
10815 /* Trim off a prefix if present. */
10816 if (j
> 1 && !vex
&& !xop
&& !evex
)
10818 uint8_t byte
= val
>> ((j
- 1) * 8);
10822 case DATA_PREFIX_OPCODE
:
10823 case REPE_PREFIX_OPCODE
:
10824 case REPNE_PREFIX_OPCODE
:
10825 if (!add_prefix (byte
))
10827 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
10832 /* Trim off encoding space. */
10833 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
10835 uint8_t byte
= val
>> ((--j
- 1) * 8);
10837 i
.insn_opcode_space
= SPACE_0F
;
10838 switch (byte
& -(j
> 1))
10841 i
.insn_opcode_space
= SPACE_0F38
;
10845 i
.insn_opcode_space
= SPACE_0F3A
;
10849 i
.tm
.opcode_space
= i
.insn_opcode_space
;
10850 val
&= ((uint64_t)1 << (j
* 8)) - 1;
10852 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
10853 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
10854 Also avoid hitting abort() there or in build_evex_prefix(). */
10855 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
10860 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
10863 i
.opcode_length
= j
;
10864 i
.tm
.base_opcode
= val
;
10868 if (!i
.tm
.opcode_modifier
.vex
)
10869 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10871 build_vex_prefix (NULL
);
10872 i
.rex
&= REX_OPCODE
;
10876 if (!i
.tm
.opcode_modifier
.evex
)
10877 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10879 build_evex_prefix ();
10880 i
.rex
&= REX_OPCODE
;
10886 *saved_ilp
= saved_char
;
10887 input_line_pointer
= line
;
10889 demand_empty_rest_of_line ();
10891 /* Make sure dot_insn() won't yield "true" anymore. */
10897 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10904 if (exp
.X_op
== O_symbol
)
10905 exp
.X_op
= O_secrel
;
10907 emit_expr (&exp
, 4);
10909 while (*input_line_pointer
++ == ',');
10911 input_line_pointer
--;
10912 demand_empty_rest_of_line ();
10916 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
10923 if (exp
.X_op
== O_symbol
)
10924 exp
.X_op
= O_secidx
;
10926 emit_expr (&exp
, 2);
10928 while (*input_line_pointer
++ == ',');
10930 input_line_pointer
--;
10931 demand_empty_rest_of_line ();
10935 /* Handle Rounding Control / SAE specifiers. */
10938 RC_SAE_specifier (const char *pstr
)
10942 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10944 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10946 if (i
.rounding
.type
!= rc_none
)
10948 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
10952 i
.rounding
.type
= RC_NamesTable
[j
].type
;
10954 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
10961 /* Handle Vector operations. */
10964 check_VecOperations (char *op_string
)
10966 const reg_entry
*mask
;
10973 if (*op_string
== '{')
10977 /* Check broadcasts. */
10978 if (startswith (op_string
, "1to"))
10980 unsigned int bcst_type
;
10982 if (i
.broadcast
.type
)
10983 goto duplicated_vec_op
;
10986 if (*op_string
== '8')
10988 else if (*op_string
== '4')
10990 else if (*op_string
== '2')
10992 else if (*op_string
== '1'
10993 && *(op_string
+1) == '6')
10998 else if (*op_string
== '3'
10999 && *(op_string
+1) == '2')
11006 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11011 i
.broadcast
.type
= bcst_type
;
11012 i
.broadcast
.operand
= this_operand
;
11014 /* Check masking operation. */
11015 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11017 if (mask
== &bad_reg
)
11020 /* k0 can't be used for write mask. */
11021 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11023 as_bad (_("`%s%s' can't be used for write mask"),
11024 register_prefix
, mask
->reg_name
);
11031 i
.mask
.operand
= this_operand
;
11033 else if (i
.mask
.reg
->reg_num
)
11034 goto duplicated_vec_op
;
11039 /* Only "{z}" is allowed here. No need to check
11040 zeroing mask explicitly. */
11041 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11043 as_bad (_("invalid write mask `%s'"), saved
);
11048 op_string
= end_op
;
11050 /* Check zeroing-flag for masking operation. */
11051 else if (*op_string
== 'z')
11055 i
.mask
.reg
= reg_k0
;
11056 i
.mask
.zeroing
= 1;
11057 i
.mask
.operand
= this_operand
;
11061 if (i
.mask
.zeroing
)
11064 as_bad (_("duplicated `%s'"), saved
);
11068 i
.mask
.zeroing
= 1;
11070 /* Only "{%k}" is allowed here. No need to check mask
11071 register explicitly. */
11072 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11074 as_bad (_("invalid zeroing-masking `%s'"),
11082 else if (intel_syntax
11083 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11084 i
.rounding
.modifier
= true;
11086 goto unknown_vec_op
;
11088 if (*op_string
!= '}')
11090 as_bad (_("missing `}' in `%s'"), saved
);
11095 /* Strip whitespace since the addition of pseudo prefixes
11096 changed how the scrubber treats '{'. */
11097 if (is_space_char (*op_string
))
11103 /* We don't know this one. */
11104 as_bad (_("unknown vector operation: `%s'"), saved
);
11108 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11110 as_bad (_("zeroing-masking only allowed with write mask"));
11118 i386_immediate (char *imm_start
)
11120 char *save_input_line_pointer
;
11121 char *gotfree_input_line
;
11124 i386_operand_type types
;
11126 operand_type_set (&types
, ~0);
11128 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11130 as_bad (_("at most %d immediate operands are allowed"),
11131 MAX_IMMEDIATE_OPERANDS
);
11135 exp
= &im_expressions
[i
.imm_operands
++];
11136 i
.op
[this_operand
].imms
= exp
;
11138 if (is_space_char (*imm_start
))
11141 save_input_line_pointer
= input_line_pointer
;
11142 input_line_pointer
= imm_start
;
11144 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11145 if (gotfree_input_line
)
11146 input_line_pointer
= gotfree_input_line
;
11148 exp_seg
= expression (exp
);
11150 SKIP_WHITESPACE ();
11151 if (*input_line_pointer
)
11152 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11154 input_line_pointer
= save_input_line_pointer
;
11155 if (gotfree_input_line
)
11157 free (gotfree_input_line
);
11159 if (exp
->X_op
== O_constant
)
11160 exp
->X_op
= O_illegal
;
11163 if (exp_seg
== reg_section
)
11165 as_bad (_("illegal immediate register operand %s"), imm_start
);
11169 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
11173 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11174 i386_operand_type types
, const char *imm_start
)
11176 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
11179 as_bad (_("missing or invalid immediate expression `%s'"),
11183 else if (exp
->X_op
== O_constant
)
11185 /* Size it properly later. */
11186 i
.types
[this_operand
].bitfield
.imm64
= 1;
11188 /* If not 64bit, sign/zero extend val, to account for wraparound
11190 if (flag_code
!= CODE_64BIT
)
11191 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11193 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11194 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11195 && exp_seg
!= absolute_section
11196 && exp_seg
!= text_section
11197 && exp_seg
!= data_section
11198 && exp_seg
!= bss_section
11199 && exp_seg
!= undefined_section
11200 && !bfd_is_com_section (exp_seg
))
11202 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11208 /* This is an address. The size of the address will be
11209 determined later, depending on destination register,
11210 suffix, or the default for the section. */
11211 i
.types
[this_operand
].bitfield
.imm8
= 1;
11212 i
.types
[this_operand
].bitfield
.imm16
= 1;
11213 i
.types
[this_operand
].bitfield
.imm32
= 1;
11214 i
.types
[this_operand
].bitfield
.imm32s
= 1;
11215 i
.types
[this_operand
].bitfield
.imm64
= 1;
11216 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11224 i386_scale (char *scale
)
11227 char *save
= input_line_pointer
;
11229 input_line_pointer
= scale
;
11230 val
= get_absolute_expression ();
11235 i
.log2_scale_factor
= 0;
11238 i
.log2_scale_factor
= 1;
11241 i
.log2_scale_factor
= 2;
11244 i
.log2_scale_factor
= 3;
11248 char sep
= *input_line_pointer
;
11250 *input_line_pointer
= '\0';
11251 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
11253 *input_line_pointer
= sep
;
11254 input_line_pointer
= save
;
11258 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
11260 as_warn (_("scale factor of %d without an index register"),
11261 1 << i
.log2_scale_factor
);
11262 i
.log2_scale_factor
= 0;
11264 scale
= input_line_pointer
;
11265 input_line_pointer
= save
;
11270 i386_displacement (char *disp_start
, char *disp_end
)
11274 char *save_input_line_pointer
;
11275 char *gotfree_input_line
;
11277 i386_operand_type bigdisp
, types
= anydisp
;
11280 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
11282 as_bad (_("at most %d displacement operands are allowed"),
11283 MAX_MEMORY_OPERANDS
);
11287 operand_type_set (&bigdisp
, 0);
11289 || i
.types
[this_operand
].bitfield
.baseindex
11290 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
11291 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
11293 i386_addressing_mode ();
11294 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
11295 if (flag_code
== CODE_64BIT
)
11297 bigdisp
.bitfield
.disp32
= 1;
11299 bigdisp
.bitfield
.disp64
= 1;
11301 else if ((flag_code
== CODE_16BIT
) ^ override
)
11302 bigdisp
.bitfield
.disp16
= 1;
11304 bigdisp
.bitfield
.disp32
= 1;
11308 /* For PC-relative branches, the width of the displacement may be
11309 dependent upon data size, but is never dependent upon address size.
11310 Also make sure to not unintentionally match against a non-PC-relative
11311 branch template. */
11312 static templates aux_templates
;
11313 const insn_template
*t
= current_templates
->start
;
11314 bool has_intel64
= false;
11316 aux_templates
.start
= t
;
11317 while (++t
< current_templates
->end
)
11319 if (t
->opcode_modifier
.jump
11320 != current_templates
->start
->opcode_modifier
.jump
)
11322 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
11323 has_intel64
= true;
11325 if (t
< current_templates
->end
)
11327 aux_templates
.end
= t
;
11328 current_templates
= &aux_templates
;
11331 override
= (i
.prefix
[DATA_PREFIX
] != 0);
11332 if (flag_code
== CODE_64BIT
)
11334 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
11335 && (!intel64
|| !has_intel64
))
11336 bigdisp
.bitfield
.disp16
= 1;
11338 bigdisp
.bitfield
.disp32
= 1;
11343 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
11345 : LONG_MNEM_SUFFIX
));
11346 bigdisp
.bitfield
.disp32
= 1;
11347 if ((flag_code
== CODE_16BIT
) ^ override
)
11349 bigdisp
.bitfield
.disp32
= 0;
11350 bigdisp
.bitfield
.disp16
= 1;
11354 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11357 exp
= &disp_expressions
[i
.disp_operands
];
11358 i
.op
[this_operand
].disps
= exp
;
11360 save_input_line_pointer
= input_line_pointer
;
11361 input_line_pointer
= disp_start
;
11362 END_STRING_AND_SAVE (disp_end
);
11364 #ifndef GCC_ASM_O_HACK
11365 #define GCC_ASM_O_HACK 0
11368 END_STRING_AND_SAVE (disp_end
+ 1);
11369 if (i
.types
[this_operand
].bitfield
.baseIndex
11370 && displacement_string_end
[-1] == '+')
11372 /* This hack is to avoid a warning when using the "o"
11373 constraint within gcc asm statements.
11376 #define _set_tssldt_desc(n,addr,limit,type) \
11377 __asm__ __volatile__ ( \
11378 "movw %w2,%0\n\t" \
11379 "movw %w1,2+%0\n\t" \
11380 "rorl $16,%1\n\t" \
11381 "movb %b1,4+%0\n\t" \
11382 "movb %4,5+%0\n\t" \
11383 "movb $0,6+%0\n\t" \
11384 "movb %h1,7+%0\n\t" \
11386 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
11388 This works great except that the output assembler ends
11389 up looking a bit weird if it turns out that there is
11390 no offset. You end up producing code that looks like:
11403 So here we provide the missing zero. */
11405 *displacement_string_end
= '0';
11408 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11409 if (gotfree_input_line
)
11410 input_line_pointer
= gotfree_input_line
;
11412 exp_seg
= expression (exp
);
11414 SKIP_WHITESPACE ();
11415 if (*input_line_pointer
)
11416 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11418 RESTORE_END_STRING (disp_end
+ 1);
11420 input_line_pointer
= save_input_line_pointer
;
11421 if (gotfree_input_line
)
11423 free (gotfree_input_line
);
11425 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
11426 exp
->X_op
= O_illegal
;
11429 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
11431 RESTORE_END_STRING (disp_end
);
11437 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11438 i386_operand_type types
, const char *disp_start
)
11442 /* We do this to make sure that the section symbol is in
11443 the symbol table. We will ultimately change the relocation
11444 to be relative to the beginning of the section. */
11445 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
11446 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
11447 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11449 if (exp
->X_op
!= O_symbol
)
11452 if (S_IS_LOCAL (exp
->X_add_symbol
)
11453 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
11454 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
11455 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
11456 exp
->X_op
= O_subtract
;
11457 exp
->X_op_symbol
= GOT_symbol
;
11458 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
11459 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
11460 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11461 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11463 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11466 else if (exp
->X_op
== O_absent
11467 || exp
->X_op
== O_illegal
11468 || exp
->X_op
== O_big
)
11471 as_bad (_("missing or invalid displacement expression `%s'"),
11476 else if (exp
->X_op
== O_constant
)
11478 /* Sizing gets taken care of by optimize_disp().
11480 If not 64bit, sign/zero extend val, to account for wraparound
11482 if (flag_code
!= CODE_64BIT
)
11483 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11486 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11487 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11488 && exp_seg
!= absolute_section
11489 && exp_seg
!= text_section
11490 && exp_seg
!= data_section
11491 && exp_seg
!= bss_section
11492 && exp_seg
!= undefined_section
11493 && !bfd_is_com_section (exp_seg
))
11495 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11500 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
11501 i
.types
[this_operand
].bitfield
.disp8
= 1;
11503 /* Check if this is a displacement only operand. */
11504 if (!i
.types
[this_operand
].bitfield
.baseindex
)
11505 i
.types
[this_operand
] =
11506 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
11507 operand_type_and (i
.types
[this_operand
], types
));
11512 /* Return the active addressing mode, taking address override and
11513 registers forming the address into consideration. Update the
11514 address override prefix if necessary. */
11516 static enum flag_code
11517 i386_addressing_mode (void)
11519 enum flag_code addr_mode
;
11521 if (i
.prefix
[ADDR_PREFIX
])
11522 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11523 else if (flag_code
== CODE_16BIT
11524 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11525 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11526 from md_assemble() by "is not a valid base/index expression"
11527 when there is a base and/or index. */
11528 && !i
.types
[this_operand
].bitfield
.baseindex
)
11530 /* MPX insn memory operands with neither base nor index must be forced
11531 to use 32-bit addressing in 16-bit mode. */
11532 addr_mode
= CODE_32BIT
;
11533 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11535 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11536 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11540 addr_mode
= flag_code
;
11542 #if INFER_ADDR_PREFIX
11543 if (i
.mem_operands
== 0)
11545 /* Infer address prefix from the first memory operand. */
11546 const reg_entry
*addr_reg
= i
.base_reg
;
11548 if (addr_reg
== NULL
)
11549 addr_reg
= i
.index_reg
;
11553 if (addr_reg
->reg_type
.bitfield
.dword
)
11554 addr_mode
= CODE_32BIT
;
11555 else if (flag_code
!= CODE_64BIT
11556 && addr_reg
->reg_type
.bitfield
.word
)
11557 addr_mode
= CODE_16BIT
;
11559 if (addr_mode
!= flag_code
)
11561 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11563 /* Change the size of any displacement too. At most one
11564 of Disp16 or Disp32 is set.
11565 FIXME. There doesn't seem to be any real need for
11566 separate Disp16 and Disp32 flags. The same goes for
11567 Imm16 and Imm32. Removing them would probably clean
11568 up the code quite a lot. */
11569 if (flag_code
!= CODE_64BIT
11570 && (i
.types
[this_operand
].bitfield
.disp16
11571 || i
.types
[this_operand
].bitfield
.disp32
))
11573 static const i386_operand_type disp16_32
= {
11574 .bitfield
= { .disp16
= 1, .disp32
= 1 }
11577 i
.types
[this_operand
]
11578 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11589 /* Make sure the memory operand we've been dealt is valid.
11590 Return 1 on success, 0 on a failure. */
11593 i386_index_check (const char *operand_string
)
11595 const char *kind
= "base/index";
11596 enum flag_code addr_mode
= i386_addressing_mode ();
11597 const insn_template
*t
= current_templates
->end
- 1;
11599 if (t
->opcode_modifier
.isstring
)
11601 /* Memory operands of string insns are special in that they only allow
11602 a single register (rDI, rSI, or rBX) as their memory address. */
11603 const reg_entry
*expected_reg
;
11604 static const char *di_si
[][2] =
11610 static const char *bx
[] = { "ebx", "bx", "rbx" };
11612 kind
= "string address";
11614 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11616 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
11619 if (!t
->operand_types
[0].bitfield
.baseindex
11620 || ((!i
.mem_operands
!= !intel_syntax
)
11621 && t
->operand_types
[1].bitfield
.baseindex
))
11624 = (const reg_entry
*) str_hash_find (reg_hash
,
11625 di_si
[addr_mode
][op
== es_op
]);
11629 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11631 if (i
.base_reg
!= expected_reg
11633 || operand_type_check (i
.types
[this_operand
], disp
))
11635 /* The second memory operand must have the same size as
11639 && !((addr_mode
== CODE_64BIT
11640 && i
.base_reg
->reg_type
.bitfield
.qword
)
11641 || (addr_mode
== CODE_32BIT
11642 ? i
.base_reg
->reg_type
.bitfield
.dword
11643 : i
.base_reg
->reg_type
.bitfield
.word
)))
11646 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11648 intel_syntax
? '[' : '(',
11650 expected_reg
->reg_name
,
11651 intel_syntax
? ']' : ')');
11658 as_bad (_("`%s' is not a valid %s expression"),
11659 operand_string
, kind
);
11664 t
= current_templates
->start
;
11666 if (addr_mode
!= CODE_16BIT
)
11668 /* 32-bit/64-bit checks. */
11669 if (i
.disp_encoding
== disp_encoding_16bit
)
11672 as_bad (_("invalid `%s' prefix"),
11673 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11678 && ((addr_mode
== CODE_64BIT
11679 ? !i
.base_reg
->reg_type
.bitfield
.qword
11680 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11681 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11682 || i
.base_reg
->reg_num
== RegIZ
))
11684 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11685 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11686 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11687 && ((addr_mode
== CODE_64BIT
11688 ? !i
.index_reg
->reg_type
.bitfield
.qword
11689 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11690 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11693 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11694 if (t
->mnem_off
== MN_bndmk
11695 || t
->mnem_off
== MN_bndldx
11696 || t
->mnem_off
== MN_bndstx
11697 || t
->opcode_modifier
.sib
== SIBMEM
)
11699 /* They cannot use RIP-relative addressing. */
11700 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11702 as_bad (_("`%s' cannot be used here"), operand_string
);
11706 /* bndldx and bndstx ignore their scale factor. */
11707 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
11708 && i
.log2_scale_factor
)
11709 as_warn (_("register scaling is being ignored here"));
11714 /* 16-bit checks. */
11715 if (i
.disp_encoding
== disp_encoding_32bit
)
11719 && (!i
.base_reg
->reg_type
.bitfield
.word
11720 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11722 && (!i
.index_reg
->reg_type
.bitfield
.word
11723 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11725 && i
.base_reg
->reg_num
< 6
11726 && i
.index_reg
->reg_num
>= 6
11727 && i
.log2_scale_factor
== 0))))
11734 /* Handle vector immediates. */
11737 RC_SAE_immediate (const char *imm_start
)
11739 const char *pstr
= imm_start
;
11744 pstr
= RC_SAE_specifier (pstr
+ 1);
11748 if (*pstr
++ != '}')
11750 as_bad (_("Missing '}': '%s'"), imm_start
);
11753 /* RC/SAE immediate string should contain nothing more. */;
11756 as_bad (_("Junk after '}': '%s'"), imm_start
);
11760 /* Internally this doesn't count as an operand. */
11766 static INLINE
bool starts_memory_operand (char c
)
11769 || is_name_beginner (c
)
11770 || strchr ("([\"+-!~", c
);
11773 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11777 i386_att_operand (char *operand_string
)
11779 const reg_entry
*r
;
11781 char *op_string
= operand_string
;
11783 if (is_space_char (*op_string
))
11786 /* We check for an absolute prefix (differentiating,
11787 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11788 if (*op_string
== ABSOLUTE_PREFIX
11789 && current_templates
->start
->opcode_modifier
.jump
)
11792 if (is_space_char (*op_string
))
11794 i
.jumpabsolute
= true;
11797 /* Check if operand is a register. */
11798 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11800 i386_operand_type temp
;
11805 /* Check for a segment override by searching for ':' after a
11806 segment register. */
11807 op_string
= end_op
;
11808 if (is_space_char (*op_string
))
11810 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11812 i
.seg
[i
.mem_operands
] = r
;
11814 /* Skip the ':' and whitespace. */
11816 if (is_space_char (*op_string
))
11819 /* Handle case of %es:*foo. */
11820 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
11821 && current_templates
->start
->opcode_modifier
.jump
)
11824 if (is_space_char (*op_string
))
11826 i
.jumpabsolute
= true;
11829 if (!starts_memory_operand (*op_string
))
11831 as_bad (_("bad memory operand `%s'"), op_string
);
11834 goto do_memory_reference
;
11837 /* Handle vector operations. */
11838 if (*op_string
== '{')
11840 op_string
= check_VecOperations (op_string
);
11841 if (op_string
== NULL
)
11847 as_bad (_("junk `%s' after register"), op_string
);
11850 temp
= r
->reg_type
;
11851 temp
.bitfield
.baseindex
= 0;
11852 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11854 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11855 i
.op
[this_operand
].regs
= r
;
11858 /* A GPR may follow an RC or SAE immediate only if a (vector) register
11859 operand was also present earlier on. */
11860 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
11861 && i
.reg_operands
== 1)
11865 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
11866 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
11868 as_bad (_("`%s': misplaced `{%s}'"),
11869 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
11873 else if (*op_string
== REGISTER_PREFIX
)
11875 as_bad (_("bad register name `%s'"), op_string
);
11878 else if (*op_string
== IMMEDIATE_PREFIX
)
11881 if (i
.jumpabsolute
)
11883 as_bad (_("immediate operand illegal with absolute jump"));
11886 if (!i386_immediate (op_string
))
11888 if (i
.rounding
.type
!= rc_none
)
11890 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
11891 insn_name (current_templates
->start
));
11895 else if (RC_SAE_immediate (operand_string
))
11897 /* If it is a RC or SAE immediate, do the necessary placement check:
11898 Only another immediate or a GPR may precede it. */
11899 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
11900 || (i
.reg_operands
== 1
11901 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
11903 as_bad (_("`%s': misplaced `%s'"),
11904 insn_name (current_templates
->start
), operand_string
);
11908 else if (starts_memory_operand (*op_string
))
11910 /* This is a memory reference of some sort. */
11913 /* Start and end of displacement string expression (if found). */
11914 char *displacement_string_start
;
11915 char *displacement_string_end
;
11917 do_memory_reference
:
11918 /* Check for base index form. We detect the base index form by
11919 looking for an ')' at the end of the operand, searching
11920 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11922 base_string
= op_string
+ strlen (op_string
);
11924 /* Handle vector operations. */
11926 if (is_space_char (*base_string
))
11929 if (*base_string
== '}')
11931 char *vop_start
= NULL
;
11933 while (base_string
-- > op_string
)
11935 if (*base_string
== '"')
11937 if (*base_string
!= '{')
11940 vop_start
= base_string
;
11943 if (is_space_char (*base_string
))
11946 if (*base_string
!= '}')
11954 as_bad (_("unbalanced figure braces"));
11958 if (check_VecOperations (vop_start
) == NULL
)
11962 /* If we only have a displacement, set-up for it to be parsed later. */
11963 displacement_string_start
= op_string
;
11964 displacement_string_end
= base_string
+ 1;
11966 if (*base_string
== ')')
11969 unsigned int parens_not_balanced
= 0;
11970 bool in_quotes
= false;
11972 /* We've already checked that the number of left & right ()'s are
11973 equal, and that there's a matching set of double quotes. */
11974 end_op
= base_string
;
11975 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
11977 if (*temp_string
== '\\' && temp_string
[1] == '"')
11979 else if (*temp_string
== '"')
11980 in_quotes
= !in_quotes
;
11981 else if (!in_quotes
)
11983 if (*temp_string
== '(' && !parens_not_balanced
++)
11984 base_string
= temp_string
;
11985 if (*temp_string
== ')')
11986 --parens_not_balanced
;
11990 temp_string
= base_string
;
11992 /* Skip past '(' and whitespace. */
11993 if (*base_string
!= '(')
11995 as_bad (_("unbalanced braces"));
11999 if (is_space_char (*base_string
))
12002 if (*base_string
== ','
12003 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12006 displacement_string_end
= temp_string
;
12008 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12012 if (i
.base_reg
== &bad_reg
)
12014 base_string
= end_op
;
12015 if (is_space_char (*base_string
))
12019 /* There may be an index reg or scale factor here. */
12020 if (*base_string
== ',')
12023 if (is_space_char (*base_string
))
12026 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12029 if (i
.index_reg
== &bad_reg
)
12031 base_string
= end_op
;
12032 if (is_space_char (*base_string
))
12034 if (*base_string
== ',')
12037 if (is_space_char (*base_string
))
12040 else if (*base_string
!= ')')
12042 as_bad (_("expecting `,' or `)' "
12043 "after index register in `%s'"),
12048 else if (*base_string
== REGISTER_PREFIX
)
12050 end_op
= strchr (base_string
, ',');
12053 as_bad (_("bad register name `%s'"), base_string
);
12057 /* Check for scale factor. */
12058 if (*base_string
!= ')')
12060 char *end_scale
= i386_scale (base_string
);
12065 base_string
= end_scale
;
12066 if (is_space_char (*base_string
))
12068 if (*base_string
!= ')')
12070 as_bad (_("expecting `)' "
12071 "after scale factor in `%s'"),
12076 else if (!i
.index_reg
)
12078 as_bad (_("expecting index register or scale factor "
12079 "after `,'; got '%c'"),
12084 else if (*base_string
!= ')')
12086 as_bad (_("expecting `,' or `)' "
12087 "after base register in `%s'"),
12092 else if (*base_string
== REGISTER_PREFIX
)
12094 end_op
= strchr (base_string
, ',');
12097 as_bad (_("bad register name `%s'"), base_string
);
12102 /* If there's an expression beginning the operand, parse it,
12103 assuming displacement_string_start and
12104 displacement_string_end are meaningful. */
12105 if (displacement_string_start
!= displacement_string_end
)
12107 if (!i386_displacement (displacement_string_start
,
12108 displacement_string_end
))
12112 /* Special case for (%dx) while doing input/output op. */
12114 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12115 && i
.base_reg
->reg_type
.bitfield
.word
12116 && i
.index_reg
== 0
12117 && i
.log2_scale_factor
== 0
12118 && i
.seg
[i
.mem_operands
] == 0
12119 && !operand_type_check (i
.types
[this_operand
], disp
))
12121 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12122 i
.input_output_operand
= true;
12126 if (i386_index_check (operand_string
) == 0)
12128 i
.flags
[this_operand
] |= Operand_Mem
;
12133 /* It's not a memory operand; argh! */
12134 as_bad (_("invalid char %s beginning operand %d `%s'"),
12135 output_invalid (*op_string
),
12140 return 1; /* Normal return. */
12143 /* Calculate the maximum variable size (i.e., excluding fr_fix)
12144 that an rs_machine_dependent frag may reach. */
12147 i386_frag_max_var (fragS
*frag
)
12149 /* The only relaxable frags are for jumps.
12150 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
12151 gas_assert (frag
->fr_type
== rs_machine_dependent
);
12152 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
12155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12157 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
12159 /* STT_GNU_IFUNC symbol must go through PLT. */
12160 if ((symbol_get_bfdsym (fr_symbol
)->flags
12161 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
12164 if (!S_IS_EXTERNAL (fr_symbol
))
12165 /* Symbol may be weak or local. */
12166 return !S_IS_WEAK (fr_symbol
);
12168 /* Global symbols with non-default visibility can't be preempted. */
12169 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
12172 if (fr_var
!= NO_RELOC
)
12173 switch ((enum bfd_reloc_code_real
) fr_var
)
12175 case BFD_RELOC_386_PLT32
:
12176 case BFD_RELOC_X86_64_PLT32
:
12177 /* Symbol with PLT relocation may be preempted. */
12183 /* Global symbols with default visibility in a shared library may be
12184 preempted by another definition. */
12189 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
12190 Note also work for Skylake and Cascadelake.
12191 ---------------------------------------------------------------------
12192 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
12193 | ------ | ----------- | ------- | -------- |
12195 | Jno | N | N | Y |
12196 | Jc/Jb | Y | N | Y |
12197 | Jae/Jnb | Y | N | Y |
12198 | Je/Jz | Y | Y | Y |
12199 | Jne/Jnz | Y | Y | Y |
12200 | Jna/Jbe | Y | N | Y |
12201 | Ja/Jnbe | Y | N | Y |
12203 | Jns | N | N | Y |
12204 | Jp/Jpe | N | N | Y |
12205 | Jnp/Jpo | N | N | Y |
12206 | Jl/Jnge | Y | Y | Y |
12207 | Jge/Jnl | Y | Y | Y |
12208 | Jle/Jng | Y | Y | Y |
12209 | Jg/Jnle | Y | Y | Y |
12210 --------------------------------------------------------------------- */
12212 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
12214 if (mf_cmp
== mf_cmp_alu_cmp
)
12215 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
12216 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
12217 if (mf_cmp
== mf_cmp_incdec
)
12218 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
12219 || mf_jcc
== mf_jcc_jle
);
12220 if (mf_cmp
== mf_cmp_test_and
)
12225 /* Return the next non-empty frag. */
12228 i386_next_non_empty_frag (fragS
*fragP
)
12230 /* There may be a frag with a ".fill 0" when there is no room in
12231 the current frag for frag_grow in output_insn. */
12232 for (fragP
= fragP
->fr_next
;
12234 && fragP
->fr_type
== rs_fill
12235 && fragP
->fr_fix
== 0);
12236 fragP
= fragP
->fr_next
)
12241 /* Return the next jcc frag after BRANCH_PADDING. */
12244 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
12246 fragS
*branch_fragP
;
12250 if (pad_fragP
->fr_type
== rs_machine_dependent
12251 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
12252 == BRANCH_PADDING
))
12254 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
12255 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
12257 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
12258 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
12259 pad_fragP
->tc_frag_data
.mf_type
))
12260 return branch_fragP
;
12266 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
12269 i386_classify_machine_dependent_frag (fragS
*fragP
)
12273 fragS
*branch_fragP
;
12275 unsigned int max_prefix_length
;
12277 if (fragP
->tc_frag_data
.classified
)
12280 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
12281 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
12282 for (next_fragP
= fragP
;
12283 next_fragP
!= NULL
;
12284 next_fragP
= next_fragP
->fr_next
)
12286 next_fragP
->tc_frag_data
.classified
= 1;
12287 if (next_fragP
->fr_type
== rs_machine_dependent
)
12288 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
12290 case BRANCH_PADDING
:
12291 /* The BRANCH_PADDING frag must be followed by a branch
12293 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
12294 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12296 case FUSED_JCC_PADDING
:
12297 /* Check if this is a fused jcc:
12299 CMP like instruction
12303 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
12304 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
12305 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
12308 /* The BRANCH_PADDING frag is merged with the
12309 FUSED_JCC_PADDING frag. */
12310 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12311 /* CMP like instruction size. */
12312 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
12313 frag_wane (pad_fragP
);
12314 /* Skip to branch_fragP. */
12315 next_fragP
= branch_fragP
;
12317 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
12319 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
12321 next_fragP
->fr_subtype
12322 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
12323 next_fragP
->tc_frag_data
.max_bytes
12324 = next_fragP
->tc_frag_data
.max_prefix_length
;
12325 /* This will be updated in the BRANCH_PREFIX scan. */
12326 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
12329 frag_wane (next_fragP
);
12334 /* Stop if there is no BRANCH_PREFIX. */
12335 if (!align_branch_prefix_size
)
12338 /* Scan for BRANCH_PREFIX. */
12339 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
12341 if (fragP
->fr_type
!= rs_machine_dependent
12342 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12346 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
12347 COND_JUMP_PREFIX. */
12348 max_prefix_length
= 0;
12349 for (next_fragP
= fragP
;
12350 next_fragP
!= NULL
;
12351 next_fragP
= next_fragP
->fr_next
)
12353 if (next_fragP
->fr_type
== rs_fill
)
12354 /* Skip rs_fill frags. */
12356 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
12357 /* Stop for all other frags. */
12360 /* rs_machine_dependent frags. */
12361 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12364 /* Count BRANCH_PREFIX frags. */
12365 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
12367 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
12368 frag_wane (next_fragP
);
12372 += next_fragP
->tc_frag_data
.max_bytes
;
12374 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12376 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12377 == FUSED_JCC_PADDING
))
12379 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
12380 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
12384 /* Stop for other rs_machine_dependent frags. */
12388 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
12390 /* Skip to the next frag. */
12391 fragP
= next_fragP
;
12395 /* Compute padding size for
12398 CMP like instruction
12400 COND_JUMP/UNCOND_JUMP
12405 COND_JUMP/UNCOND_JUMP
12409 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
12411 unsigned int offset
, size
, padding_size
;
12412 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
12414 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
12416 address
= fragP
->fr_address
;
12417 address
+= fragP
->fr_fix
;
12419 /* CMP like instrunction size. */
12420 size
= fragP
->tc_frag_data
.cmp_size
;
12422 /* The base size of the branch frag. */
12423 size
+= branch_fragP
->fr_fix
;
12425 /* Add opcode and displacement bytes for the rs_machine_dependent
12427 if (branch_fragP
->fr_type
== rs_machine_dependent
)
12428 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
12430 /* Check if branch is within boundary and doesn't end at the last
12432 offset
= address
& ((1U << align_branch_power
) - 1);
12433 if ((offset
+ size
) >= (1U << align_branch_power
))
12434 /* Padding needed to avoid crossing boundary. */
12435 padding_size
= (1U << align_branch_power
) - offset
;
12437 /* No padding needed. */
12440 /* The return value may be saved in tc_frag_data.length which is
12442 if (!fits_in_unsigned_byte (padding_size
))
12445 return padding_size
;
12448 /* i386_generic_table_relax_frag()
12450 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12451 grow/shrink padding to align branch frags. Hand others to
12455 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12457 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12458 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12460 long padding_size
= i386_branch_padding_size (fragP
, 0);
12461 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12463 /* When the BRANCH_PREFIX frag is used, the computed address
12464 must match the actual address and there should be no padding. */
12465 if (fragP
->tc_frag_data
.padding_address
12466 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12470 /* Update the padding size. */
12472 fragP
->tc_frag_data
.length
= padding_size
;
12476 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12478 fragS
*padding_fragP
, *next_fragP
;
12479 long padding_size
, left_size
, last_size
;
12481 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12482 if (!padding_fragP
)
12483 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12484 return (fragP
->tc_frag_data
.length
12485 - fragP
->tc_frag_data
.last_length
);
12487 /* Compute the relative address of the padding frag in the very
12488 first time where the BRANCH_PREFIX frag sizes are zero. */
12489 if (!fragP
->tc_frag_data
.padding_address
)
12490 fragP
->tc_frag_data
.padding_address
12491 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12493 /* First update the last length from the previous interation. */
12494 left_size
= fragP
->tc_frag_data
.prefix_length
;
12495 for (next_fragP
= fragP
;
12496 next_fragP
!= padding_fragP
;
12497 next_fragP
= next_fragP
->fr_next
)
12498 if (next_fragP
->fr_type
== rs_machine_dependent
12499 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12504 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12508 if (max
> left_size
)
12513 next_fragP
->tc_frag_data
.last_length
= size
;
12517 next_fragP
->tc_frag_data
.last_length
= 0;
12520 /* Check the padding size for the padding frag. */
12521 padding_size
= i386_branch_padding_size
12522 (padding_fragP
, (fragP
->fr_address
12523 + fragP
->tc_frag_data
.padding_address
));
12525 last_size
= fragP
->tc_frag_data
.prefix_length
;
12526 /* Check if there is change from the last interation. */
12527 if (padding_size
== last_size
)
12529 /* Update the expected address of the padding frag. */
12530 padding_fragP
->tc_frag_data
.padding_address
12531 = (fragP
->fr_address
+ padding_size
12532 + fragP
->tc_frag_data
.padding_address
);
12536 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12538 /* No padding if there is no sufficient room. Clear the
12539 expected address of the padding frag. */
12540 padding_fragP
->tc_frag_data
.padding_address
= 0;
12544 /* Store the expected address of the padding frag. */
12545 padding_fragP
->tc_frag_data
.padding_address
12546 = (fragP
->fr_address
+ padding_size
12547 + fragP
->tc_frag_data
.padding_address
);
12549 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12551 /* Update the length for the current interation. */
12552 left_size
= padding_size
;
12553 for (next_fragP
= fragP
;
12554 next_fragP
!= padding_fragP
;
12555 next_fragP
= next_fragP
->fr_next
)
12556 if (next_fragP
->fr_type
== rs_machine_dependent
12557 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12562 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12566 if (max
> left_size
)
12571 next_fragP
->tc_frag_data
.length
= size
;
12575 next_fragP
->tc_frag_data
.length
= 0;
12578 return (fragP
->tc_frag_data
.length
12579 - fragP
->tc_frag_data
.last_length
);
12581 return relax_frag (segment
, fragP
, stretch
);
12584 /* md_estimate_size_before_relax()
12586 Called just before relax() for rs_machine_dependent frags. The x86
12587 assembler uses these frags to handle variable size jump
12590 Any symbol that is now undefined will not become defined.
12591 Return the correct fr_subtype in the frag.
12592 Return the initial "guess for variable size of frag" to caller.
12593 The guess is actually the growth beyond the fixed part. Whatever
12594 we do to grow the fixed or variable part contributes to our
12598 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12600 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12601 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12602 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12604 i386_classify_machine_dependent_frag (fragP
);
12605 return fragP
->tc_frag_data
.length
;
12608 /* We've already got fragP->fr_subtype right; all we have to do is
12609 check for un-relaxable symbols. On an ELF system, we can't relax
12610 an externally visible symbol, because it may be overridden by a
12612 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12615 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12618 #if defined (OBJ_COFF) && defined (TE_PE)
12619 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12620 && S_IS_WEAK (fragP
->fr_symbol
))
12624 /* Symbol is undefined in this segment, or we need to keep a
12625 reloc so that weak symbols can be overridden. */
12626 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12627 enum bfd_reloc_code_real reloc_type
;
12628 unsigned char *opcode
;
12632 if (fragP
->fr_var
!= NO_RELOC
)
12633 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12634 else if (size
== 2)
12635 reloc_type
= BFD_RELOC_16_PCREL
;
12636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12637 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
12638 && need_plt32_p (fragP
->fr_symbol
))
12639 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12642 reloc_type
= BFD_RELOC_32_PCREL
;
12644 old_fr_fix
= fragP
->fr_fix
;
12645 opcode
= (unsigned char *) fragP
->fr_opcode
;
12647 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12650 /* Make jmp (0xeb) a (d)word displacement jump. */
12652 fragP
->fr_fix
+= size
;
12653 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12655 fragP
->fr_offset
, 1,
12661 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12663 /* Negate the condition, and branch past an
12664 unconditional jump. */
12667 /* Insert an unconditional jump. */
12669 /* We added two extra opcode bytes, and have a two byte
12671 fragP
->fr_fix
+= 2 + 2;
12672 fix_new (fragP
, old_fr_fix
+ 2, 2,
12674 fragP
->fr_offset
, 1,
12678 /* Fall through. */
12681 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12683 fragP
->fr_fix
+= 1;
12684 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12686 fragP
->fr_offset
, 1,
12687 BFD_RELOC_8_PCREL
);
12688 fixP
->fx_signed
= 1;
12692 /* This changes the byte-displacement jump 0x7N
12693 to the (d)word-displacement jump 0x0f,0x8N. */
12694 opcode
[1] = opcode
[0] + 0x10;
12695 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12696 /* We've added an opcode byte. */
12697 fragP
->fr_fix
+= 1 + size
;
12698 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12700 fragP
->fr_offset
, 1,
12705 BAD_CASE (fragP
->fr_subtype
);
12709 /* All jumps handled here are signed, but don't unconditionally use a
12710 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12711 around at 4G (outside of 64-bit mode) and 64k. */
12712 if (size
== 4 && flag_code
== CODE_64BIT
)
12713 fixP
->fx_signed
= 1;
12716 return fragP
->fr_fix
- old_fr_fix
;
12719 /* Guess size depending on current relax state. Initially the relax
12720 state will correspond to a short jump and we return 1, because
12721 the variable part of the frag (the branch offset) is one byte
12722 long. However, we can relax a section more than once and in that
12723 case we must either set fr_subtype back to the unrelaxed state,
12724 or return the value for the appropriate branch. */
12725 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12728 /* Called after relax() is finished.
12730 In: Address of frag.
12731 fr_type == rs_machine_dependent.
12732 fr_subtype is what the address relaxed to.
12734 Out: Any fixSs and constants are set up.
12735 Caller will turn frag into a ".space 0". */
12738 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12741 unsigned char *opcode
;
12742 unsigned char *where_to_put_displacement
= NULL
;
12743 offsetT target_address
;
12744 offsetT opcode_address
;
12745 unsigned int extension
= 0;
12746 offsetT displacement_from_opcode_start
;
12748 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12749 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12750 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12752 /* Generate nop padding. */
12753 unsigned int size
= fragP
->tc_frag_data
.length
;
12756 if (size
> fragP
->tc_frag_data
.max_bytes
)
12762 const char *branch
= "branch";
12763 const char *prefix
= "";
12764 fragS
*padding_fragP
;
12765 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12768 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12769 switch (fragP
->tc_frag_data
.default_prefix
)
12774 case CS_PREFIX_OPCODE
:
12777 case DS_PREFIX_OPCODE
:
12780 case ES_PREFIX_OPCODE
:
12783 case FS_PREFIX_OPCODE
:
12786 case GS_PREFIX_OPCODE
:
12789 case SS_PREFIX_OPCODE
:
12794 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12795 "%s within %d-byte boundary\n");
12797 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12798 "align %s within %d-byte boundary\n");
12802 padding_fragP
= fragP
;
12803 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12804 "%s within %d-byte boundary\n");
12808 switch (padding_fragP
->tc_frag_data
.branch_type
)
12810 case align_branch_jcc
:
12813 case align_branch_fused
:
12814 branch
= "fused jcc";
12816 case align_branch_jmp
:
12819 case align_branch_call
:
12822 case align_branch_indirect
:
12823 branch
= "indiret branch";
12825 case align_branch_ret
:
12832 fprintf (stdout
, msg
,
12833 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12834 (long long) fragP
->fr_address
, branch
,
12835 1 << align_branch_power
);
12837 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12838 memset (fragP
->fr_opcode
,
12839 fragP
->tc_frag_data
.default_prefix
, size
);
12841 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12843 fragP
->fr_fix
+= size
;
12848 opcode
= (unsigned char *) fragP
->fr_opcode
;
12850 /* Address we want to reach in file space. */
12851 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12853 /* Address opcode resides at in file space. */
12854 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12856 /* Displacement from opcode start to fill into instruction. */
12857 displacement_from_opcode_start
= target_address
- opcode_address
;
12859 if ((fragP
->fr_subtype
& BIG
) == 0)
12861 /* Don't have to change opcode. */
12862 extension
= 1; /* 1 opcode + 1 displacement */
12863 where_to_put_displacement
= &opcode
[1];
12867 if (no_cond_jump_promotion
12868 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12869 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12870 _("long jump required"));
12872 switch (fragP
->fr_subtype
)
12874 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12875 extension
= 4; /* 1 opcode + 4 displacement */
12877 where_to_put_displacement
= &opcode
[1];
12880 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12881 extension
= 2; /* 1 opcode + 2 displacement */
12883 where_to_put_displacement
= &opcode
[1];
12886 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12887 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12888 extension
= 5; /* 2 opcode + 4 displacement */
12889 opcode
[1] = opcode
[0] + 0x10;
12890 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12891 where_to_put_displacement
= &opcode
[2];
12894 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12895 extension
= 3; /* 2 opcode + 2 displacement */
12896 opcode
[1] = opcode
[0] + 0x10;
12897 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12898 where_to_put_displacement
= &opcode
[2];
12901 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12906 where_to_put_displacement
= &opcode
[3];
12910 BAD_CASE (fragP
->fr_subtype
);
12915 /* If size if less then four we are sure that the operand fits,
12916 but if it's 4, then it could be that the displacement is larger
12918 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12920 && ((addressT
) (displacement_from_opcode_start
- extension
12921 + ((addressT
) 1 << 31))
12922 > (((addressT
) 2 << 31) - 1)))
12924 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12925 _("jump target out of range"));
12926 /* Make us emit 0. */
12927 displacement_from_opcode_start
= extension
;
12929 /* Now put displacement after opcode. */
12930 md_number_to_chars ((char *) where_to_put_displacement
,
12931 (valueT
) (displacement_from_opcode_start
- extension
),
12932 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12933 fragP
->fr_fix
+= extension
;
12936 /* Apply a fixup (fixP) to segment data, once it has been determined
12937 by our caller that we have all the info we need to fix it up.
12939 Parameter valP is the pointer to the value of the bits.
12941 On the 386, immediates, displacements, and data pointers are all in
12942 the same (little-endian) format, so we don't need to care about which
12943 we are handling. */
12946 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12948 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12949 valueT value
= *valP
;
12951 #if !defined (TE_Mach)
12952 if (fixP
->fx_pcrel
)
12954 switch (fixP
->fx_r_type
)
12960 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12963 case BFD_RELOC_X86_64_32S
:
12964 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12967 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12970 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12975 if (fixP
->fx_addsy
!= NULL
12976 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12977 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12978 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12979 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12980 && !use_rela_relocations
)
12982 /* This is a hack. There should be a better way to handle this.
12983 This covers for the fact that bfd_install_relocation will
12984 subtract the current location (for partial_inplace, PC relative
12985 relocations); see more below. */
12989 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12992 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12997 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12999 if ((sym_seg
== seg
13000 || (symbol_section_p (fixP
->fx_addsy
)
13001 && sym_seg
!= absolute_section
))
13002 && !generic_force_reloc (fixP
))
13004 /* Yes, we add the values in twice. This is because
13005 bfd_install_relocation subtracts them out again. I think
13006 bfd_install_relocation is broken, but I don't dare change
13008 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13012 #if defined (OBJ_COFF) && defined (TE_PE)
13013 /* For some reason, the PE format does not store a
13014 section address offset for a PC relative symbol. */
13015 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13016 || S_IS_WEAK (fixP
->fx_addsy
))
13017 value
+= md_pcrel_from (fixP
);
13020 #if defined (OBJ_COFF) && defined (TE_PE)
13021 if (fixP
->fx_addsy
!= NULL
13022 && S_IS_WEAK (fixP
->fx_addsy
)
13023 /* PR 16858: Do not modify weak function references. */
13024 && ! fixP
->fx_pcrel
)
13026 #if !defined (TE_PEP)
13027 /* For x86 PE weak function symbols are neither PC-relative
13028 nor do they set S_IS_FUNCTION. So the only reliable way
13029 to detect them is to check the flags of their containing
13031 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13032 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13036 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13040 /* Fix a few things - the dynamic linker expects certain values here,
13041 and we must not disappoint it. */
13042 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13043 if (IS_ELF
&& fixP
->fx_addsy
)
13044 switch (fixP
->fx_r_type
)
13046 case BFD_RELOC_386_PLT32
:
13047 case BFD_RELOC_X86_64_PLT32
:
13048 /* Make the jump instruction point to the address of the operand.
13049 At runtime we merely add the offset to the actual PLT entry.
13050 NB: Subtract the offset size only for jump instructions. */
13051 if (fixP
->fx_pcrel
)
13055 case BFD_RELOC_386_TLS_GD
:
13056 case BFD_RELOC_386_TLS_LDM
:
13057 case BFD_RELOC_386_TLS_IE_32
:
13058 case BFD_RELOC_386_TLS_IE
:
13059 case BFD_RELOC_386_TLS_GOTIE
:
13060 case BFD_RELOC_386_TLS_GOTDESC
:
13061 case BFD_RELOC_X86_64_TLSGD
:
13062 case BFD_RELOC_X86_64_TLSLD
:
13063 case BFD_RELOC_X86_64_GOTTPOFF
:
13064 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13065 value
= 0; /* Fully resolved at runtime. No addend. */
13067 case BFD_RELOC_386_TLS_LE
:
13068 case BFD_RELOC_386_TLS_LDO_32
:
13069 case BFD_RELOC_386_TLS_LE_32
:
13070 case BFD_RELOC_X86_64_DTPOFF32
:
13071 case BFD_RELOC_X86_64_DTPOFF64
:
13072 case BFD_RELOC_X86_64_TPOFF32
:
13073 case BFD_RELOC_X86_64_TPOFF64
:
13074 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13077 case BFD_RELOC_386_TLS_DESC_CALL
:
13078 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13079 value
= 0; /* Fully resolved at runtime. No addend. */
13080 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13084 case BFD_RELOC_VTABLE_INHERIT
:
13085 case BFD_RELOC_VTABLE_ENTRY
:
13092 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13094 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13096 value
= extend_to_32bit_address (value
);
13099 #endif /* !defined (TE_Mach) */
13101 /* Are we finished with this relocation now? */
13102 if (fixP
->fx_addsy
== NULL
)
13105 switch (fixP
->fx_r_type
)
13107 case BFD_RELOC_X86_64_32S
:
13108 fixP
->fx_signed
= 1;
13115 #if defined (OBJ_COFF) && defined (TE_PE)
13116 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13119 /* Remember value for tc_gen_reloc. */
13120 fixP
->fx_addnumber
= value
;
13121 /* Clear out the frag for now. */
13125 else if (use_rela_relocations
)
13127 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13128 fixP
->fx_no_overflow
= 1;
13129 /* Remember value for tc_gen_reloc. */
13130 fixP
->fx_addnumber
= value
;
13134 md_number_to_chars (p
, value
, fixP
->fx_size
);
13138 md_atof (int type
, char *litP
, int *sizeP
)
13140 /* This outputs the LITTLENUMs in REVERSE order;
13141 in accord with the bigendian 386. */
13142 return ieee_md_atof (type
, litP
, sizeP
, false);
13145 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
13148 output_invalid (int c
)
13151 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13154 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13155 "(0x%x)", (unsigned char) c
);
13156 return output_invalid_buf
;
13159 /* Verify that @r can be used in the current context. */
13161 static bool check_register (const reg_entry
*r
)
13163 if (allow_pseudo_reg
)
13166 if (operand_type_all_zero (&r
->reg_type
))
13169 if ((r
->reg_type
.bitfield
.dword
13170 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
13171 || r
->reg_type
.bitfield
.class == RegCR
13172 || r
->reg_type
.bitfield
.class == RegDR
)
13173 && !cpu_arch_flags
.bitfield
.cpui386
)
13176 if (r
->reg_type
.bitfield
.class == RegTR
13177 && (flag_code
== CODE_64BIT
13178 || !cpu_arch_flags
.bitfield
.cpui386
13179 || cpu_arch_isa_flags
.bitfield
.cpui586
13180 || cpu_arch_isa_flags
.bitfield
.cpui686
))
13183 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
13186 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
13188 if (r
->reg_type
.bitfield
.zmmword
13189 || r
->reg_type
.bitfield
.class == RegMask
)
13192 if (!cpu_arch_flags
.bitfield
.cpuavx
)
13194 if (r
->reg_type
.bitfield
.ymmword
)
13197 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
13202 if (r
->reg_type
.bitfield
.tmmword
13203 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
13204 || flag_code
!= CODE_64BIT
))
13207 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
13210 /* Don't allow fake index register unless allow_index_reg isn't 0. */
13211 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
13214 /* Upper 16 vector registers are only available with VREX in 64bit
13215 mode, and require EVEX encoding. */
13216 if (r
->reg_flags
& RegVRex
)
13218 if (!cpu_arch_flags
.bitfield
.cpuavx512f
13219 || flag_code
!= CODE_64BIT
)
13222 if (i
.vec_encoding
== vex_encoding_default
)
13223 i
.vec_encoding
= vex_encoding_evex
;
13224 else if (i
.vec_encoding
!= vex_encoding_evex
)
13225 i
.vec_encoding
= vex_encoding_error
;
13228 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
13229 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
13230 && flag_code
!= CODE_64BIT
)
13233 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
13240 /* REG_STRING starts *before* REGISTER_PREFIX. */
13242 static const reg_entry
*
13243 parse_real_register (char *reg_string
, char **end_op
)
13245 char *s
= reg_string
;
13247 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
13248 const reg_entry
*r
;
13250 /* Skip possible REGISTER_PREFIX and possible whitespace. */
13251 if (*s
== REGISTER_PREFIX
)
13254 if (is_space_char (*s
))
13257 p
= reg_name_given
;
13258 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
13260 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
13261 return (const reg_entry
*) NULL
;
13265 if (is_part_of_name (*s
))
13266 return (const reg_entry
*) NULL
;
13270 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
13272 /* Handle floating point regs, allowing spaces in the (i) part. */
13275 if (!cpu_arch_flags
.bitfield
.cpu8087
13276 && !cpu_arch_flags
.bitfield
.cpu287
13277 && !cpu_arch_flags
.bitfield
.cpu387
13278 && !allow_pseudo_reg
)
13279 return (const reg_entry
*) NULL
;
13281 if (is_space_char (*s
))
13286 if (is_space_char (*s
))
13288 if (*s
>= '0' && *s
<= '7')
13290 int fpr
= *s
- '0';
13292 if (is_space_char (*s
))
13297 know (r
[fpr
].reg_num
== fpr
);
13301 /* We have "%st(" then garbage. */
13302 return (const reg_entry
*) NULL
;
13306 return r
&& check_register (r
) ? r
: NULL
;
13309 /* REG_STRING starts *before* REGISTER_PREFIX. */
13311 static const reg_entry
*
13312 parse_register (char *reg_string
, char **end_op
)
13314 const reg_entry
*r
;
13316 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
13317 r
= parse_real_register (reg_string
, end_op
);
13322 char *save
= input_line_pointer
;
13326 input_line_pointer
= reg_string
;
13327 c
= get_symbol_name (®_string
);
13328 symbolP
= symbol_find (reg_string
);
13329 while (symbolP
&& S_GET_SEGMENT (symbolP
) != reg_section
)
13331 const expressionS
*e
= symbol_get_value_expression(symbolP
);
13333 if (e
->X_op
!= O_symbol
|| e
->X_add_number
)
13335 symbolP
= e
->X_add_symbol
;
13337 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
13339 const expressionS
*e
= symbol_get_value_expression (symbolP
);
13341 if (e
->X_op
== O_register
)
13343 know (e
->X_add_number
>= 0
13344 && (valueT
) e
->X_add_number
< i386_regtab_size
);
13345 r
= i386_regtab
+ e
->X_add_number
;
13346 *end_op
= input_line_pointer
;
13348 if (r
&& !check_register (r
))
13350 as_bad (_("register '%s%s' cannot be used here"),
13351 register_prefix
, r
->reg_name
);
13355 *input_line_pointer
= c
;
13356 input_line_pointer
= save
;
13362 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
13364 const reg_entry
*r
= NULL
;
13365 char *end
= input_line_pointer
;
13368 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
13369 r
= parse_real_register (name
, &input_line_pointer
);
13370 if (r
&& end
<= input_line_pointer
)
13372 *nextcharP
= *input_line_pointer
;
13373 *input_line_pointer
= 0;
13376 e
->X_op
= O_register
;
13377 e
->X_add_number
= r
- i386_regtab
;
13380 e
->X_op
= O_illegal
;
13383 input_line_pointer
= end
;
13385 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
13389 md_operand (expressionS
*e
)
13392 const reg_entry
*r
;
13394 switch (*input_line_pointer
)
13396 case REGISTER_PREFIX
:
13397 r
= parse_real_register (input_line_pointer
, &end
);
13400 e
->X_op
= O_register
;
13401 e
->X_add_number
= r
- i386_regtab
;
13402 input_line_pointer
= end
;
13407 gas_assert (intel_syntax
);
13408 end
= input_line_pointer
++;
13410 if (*input_line_pointer
== ']')
13412 ++input_line_pointer
;
13413 e
->X_op_symbol
= make_expr_symbol (e
);
13414 e
->X_add_symbol
= NULL
;
13415 e
->X_add_number
= 0;
13420 e
->X_op
= O_absent
;
13421 input_line_pointer
= end
;
13428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13429 const char *md_shortopts
= "kVQ:sqnO::";
13431 const char *md_shortopts
= "qnO::";
13434 #define OPTION_32 (OPTION_MD_BASE + 0)
13435 #define OPTION_64 (OPTION_MD_BASE + 1)
13436 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
13437 #define OPTION_MARCH (OPTION_MD_BASE + 3)
13438 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
13439 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
13440 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
13441 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13442 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13443 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13444 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13445 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13446 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13447 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13448 #define OPTION_X32 (OPTION_MD_BASE + 14)
13449 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
13450 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
13451 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
13452 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13453 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13454 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13455 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13456 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13457 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13458 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13459 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13460 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13461 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13462 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13463 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13464 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13465 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13466 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13467 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13468 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
13470 struct option md_longopts
[] =
13472 {"32", no_argument
, NULL
, OPTION_32
},
13473 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13474 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13475 {"64", no_argument
, NULL
, OPTION_64
},
13477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13478 {"x32", no_argument
, NULL
, OPTION_X32
},
13479 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13480 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13482 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13483 {"march", required_argument
, NULL
, OPTION_MARCH
},
13484 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13485 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13486 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13487 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13488 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13489 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13490 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
13491 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13492 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13493 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13494 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13495 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13496 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13497 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13498 # if defined (TE_PE) || defined (TE_PEP)
13499 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13501 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13502 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13503 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13504 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13505 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13506 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13507 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13508 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13509 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13510 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13511 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13512 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13513 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13514 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13515 {NULL
, no_argument
, NULL
, 0}
13517 size_t md_longopts_size
= sizeof (md_longopts
);
13520 md_parse_option (int c
, const char *arg
)
13523 char *arch
, *next
, *saved
, *type
;
13528 optimize_align_code
= 0;
13532 quiet_warnings
= 1;
13535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13536 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13537 should be emitted or not. FIXME: Not implemented. */
13539 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13543 /* -V: SVR4 argument to print version ID. */
13545 print_version_id ();
13548 /* -k: Ignore for FreeBSD compatibility. */
13553 /* -s: On i386 Solaris, this tells the native assembler to use
13554 .stab instead of .stab.excl. We always use .stab anyhow. */
13557 case OPTION_MSHARED
:
13561 case OPTION_X86_USED_NOTE
:
13562 if (strcasecmp (arg
, "yes") == 0)
13564 else if (strcasecmp (arg
, "no") == 0)
13567 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13572 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13576 const char **list
, **l
;
13578 list
= bfd_target_list ();
13579 for (l
= list
; *l
!= NULL
; l
++)
13580 if (startswith (*l
, "elf64-x86-64")
13581 || strcmp (*l
, "coff-x86-64") == 0
13582 || strcmp (*l
, "pe-x86-64") == 0
13583 || strcmp (*l
, "pei-x86-64") == 0
13584 || strcmp (*l
, "mach-o-x86-64") == 0)
13586 default_arch
= "x86_64";
13590 as_fatal (_("no compiled in support for x86_64"));
13596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13600 const char **list
, **l
;
13602 list
= bfd_target_list ();
13603 for (l
= list
; *l
!= NULL
; l
++)
13604 if (startswith (*l
, "elf32-x86-64"))
13606 default_arch
= "x86_64:32";
13610 as_fatal (_("no compiled in support for 32bit x86_64"));
13614 as_fatal (_("32bit x86_64 is only supported for ELF"));
13619 default_arch
= "i386";
13622 case OPTION_DIVIDE
:
13623 #ifdef SVR4_COMMENT_CHARS
13628 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13630 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13634 i386_comment_chars
= n
;
13640 saved
= xstrdup (arg
);
13642 /* Allow -march=+nosse. */
13648 as_fatal (_("invalid -march= option: `%s'"), arg
);
13649 next
= strchr (arch
, '+');
13652 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13654 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
13655 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
13658 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
13661 cpu_arch_name
= cpu_arch
[j
].name
;
13662 free (cpu_sub_arch_name
);
13663 cpu_sub_arch_name
= NULL
;
13664 cpu_arch_flags
= cpu_arch
[j
].enable
;
13665 cpu_arch_isa
= cpu_arch
[j
].type
;
13666 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
13667 if (!cpu_arch_tune_set
)
13669 cpu_arch_tune
= cpu_arch_isa
;
13670 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13674 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
13675 && strcmp (arch
, cpu_arch
[j
].name
) == 0
13676 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13678 /* ISA extension. */
13679 i386_cpu_flags flags
;
13681 flags
= cpu_flags_or (cpu_arch_flags
,
13682 cpu_arch
[j
].enable
);
13684 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13686 extend_cpu_sub_arch_name (arch
);
13687 cpu_arch_flags
= flags
;
13688 cpu_arch_isa_flags
= flags
;
13692 = cpu_flags_or (cpu_arch_isa_flags
,
13693 cpu_arch
[j
].enable
);
13698 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
13700 /* Disable an ISA extension. */
13701 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13702 if (cpu_arch
[j
].type
== PROCESSOR_NONE
13703 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
13705 i386_cpu_flags flags
;
13707 flags
= cpu_flags_and_not (cpu_arch_flags
,
13708 cpu_arch
[j
].disable
);
13709 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13711 extend_cpu_sub_arch_name (arch
);
13712 cpu_arch_flags
= flags
;
13713 cpu_arch_isa_flags
= flags
;
13719 if (j
>= ARRAY_SIZE (cpu_arch
))
13720 as_fatal (_("invalid -march= option: `%s'"), arg
);
13724 while (next
!= NULL
);
13730 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13731 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13733 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
13734 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
13736 cpu_arch_tune_set
= 1;
13737 cpu_arch_tune
= cpu_arch
[j
].type
;
13738 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
13742 if (j
>= ARRAY_SIZE (cpu_arch
))
13743 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13746 case OPTION_MMNEMONIC
:
13747 if (strcasecmp (arg
, "att") == 0)
13748 intel_mnemonic
= 0;
13749 else if (strcasecmp (arg
, "intel") == 0)
13750 intel_mnemonic
= 1;
13752 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13755 case OPTION_MSYNTAX
:
13756 if (strcasecmp (arg
, "att") == 0)
13758 else if (strcasecmp (arg
, "intel") == 0)
13761 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13764 case OPTION_MINDEX_REG
:
13765 allow_index_reg
= 1;
13768 case OPTION_MNAKED_REG
:
13769 allow_naked_reg
= 1;
13772 case OPTION_MSSE2AVX
:
13776 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
13777 use_unaligned_vector_move
= 1;
13780 case OPTION_MSSE_CHECK
:
13781 if (strcasecmp (arg
, "error") == 0)
13782 sse_check
= check_error
;
13783 else if (strcasecmp (arg
, "warning") == 0)
13784 sse_check
= check_warning
;
13785 else if (strcasecmp (arg
, "none") == 0)
13786 sse_check
= check_none
;
13788 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13791 case OPTION_MOPERAND_CHECK
:
13792 if (strcasecmp (arg
, "error") == 0)
13793 operand_check
= check_error
;
13794 else if (strcasecmp (arg
, "warning") == 0)
13795 operand_check
= check_warning
;
13796 else if (strcasecmp (arg
, "none") == 0)
13797 operand_check
= check_none
;
13799 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13802 case OPTION_MAVXSCALAR
:
13803 if (strcasecmp (arg
, "128") == 0)
13804 avxscalar
= vex128
;
13805 else if (strcasecmp (arg
, "256") == 0)
13806 avxscalar
= vex256
;
13808 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13811 case OPTION_MVEXWIG
:
13812 if (strcmp (arg
, "0") == 0)
13814 else if (strcmp (arg
, "1") == 0)
13817 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13820 case OPTION_MADD_BND_PREFIX
:
13821 add_bnd_prefix
= 1;
13824 case OPTION_MEVEXLIG
:
13825 if (strcmp (arg
, "128") == 0)
13826 evexlig
= evexl128
;
13827 else if (strcmp (arg
, "256") == 0)
13828 evexlig
= evexl256
;
13829 else if (strcmp (arg
, "512") == 0)
13830 evexlig
= evexl512
;
13832 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13835 case OPTION_MEVEXRCIG
:
13836 if (strcmp (arg
, "rne") == 0)
13838 else if (strcmp (arg
, "rd") == 0)
13840 else if (strcmp (arg
, "ru") == 0)
13842 else if (strcmp (arg
, "rz") == 0)
13845 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13848 case OPTION_MEVEXWIG
:
13849 if (strcmp (arg
, "0") == 0)
13851 else if (strcmp (arg
, "1") == 0)
13854 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13857 # if defined (TE_PE) || defined (TE_PEP)
13858 case OPTION_MBIG_OBJ
:
13863 case OPTION_MOMIT_LOCK_PREFIX
:
13864 if (strcasecmp (arg
, "yes") == 0)
13865 omit_lock_prefix
= 1;
13866 else if (strcasecmp (arg
, "no") == 0)
13867 omit_lock_prefix
= 0;
13869 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13872 case OPTION_MFENCE_AS_LOCK_ADD
:
13873 if (strcasecmp (arg
, "yes") == 0)
13875 else if (strcasecmp (arg
, "no") == 0)
13878 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13881 case OPTION_MLFENCE_AFTER_LOAD
:
13882 if (strcasecmp (arg
, "yes") == 0)
13883 lfence_after_load
= 1;
13884 else if (strcasecmp (arg
, "no") == 0)
13885 lfence_after_load
= 0;
13887 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13890 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13891 if (strcasecmp (arg
, "all") == 0)
13893 lfence_before_indirect_branch
= lfence_branch_all
;
13894 if (lfence_before_ret
== lfence_before_ret_none
)
13895 lfence_before_ret
= lfence_before_ret_shl
;
13897 else if (strcasecmp (arg
, "memory") == 0)
13898 lfence_before_indirect_branch
= lfence_branch_memory
;
13899 else if (strcasecmp (arg
, "register") == 0)
13900 lfence_before_indirect_branch
= lfence_branch_register
;
13901 else if (strcasecmp (arg
, "none") == 0)
13902 lfence_before_indirect_branch
= lfence_branch_none
;
13904 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13908 case OPTION_MLFENCE_BEFORE_RET
:
13909 if (strcasecmp (arg
, "or") == 0)
13910 lfence_before_ret
= lfence_before_ret_or
;
13911 else if (strcasecmp (arg
, "not") == 0)
13912 lfence_before_ret
= lfence_before_ret_not
;
13913 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13914 lfence_before_ret
= lfence_before_ret_shl
;
13915 else if (strcasecmp (arg
, "none") == 0)
13916 lfence_before_ret
= lfence_before_ret_none
;
13918 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13922 case OPTION_MRELAX_RELOCATIONS
:
13923 if (strcasecmp (arg
, "yes") == 0)
13924 generate_relax_relocations
= 1;
13925 else if (strcasecmp (arg
, "no") == 0)
13926 generate_relax_relocations
= 0;
13928 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13931 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13934 long int align
= strtoul (arg
, &end
, 0);
13939 align_branch_power
= 0;
13942 else if (align
>= 16)
13945 for (align_power
= 0;
13947 align
>>= 1, align_power
++)
13949 /* Limit alignment power to 31. */
13950 if (align
== 1 && align_power
< 32)
13952 align_branch_power
= align_power
;
13957 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13961 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13964 int align
= strtoul (arg
, &end
, 0);
13965 /* Some processors only support 5 prefixes. */
13966 if (*end
== '\0' && align
>= 0 && align
< 6)
13968 align_branch_prefix_size
= align
;
13971 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13976 case OPTION_MALIGN_BRANCH
:
13978 saved
= xstrdup (arg
);
13982 next
= strchr (type
, '+');
13985 if (strcasecmp (type
, "jcc") == 0)
13986 align_branch
|= align_branch_jcc_bit
;
13987 else if (strcasecmp (type
, "fused") == 0)
13988 align_branch
|= align_branch_fused_bit
;
13989 else if (strcasecmp (type
, "jmp") == 0)
13990 align_branch
|= align_branch_jmp_bit
;
13991 else if (strcasecmp (type
, "call") == 0)
13992 align_branch
|= align_branch_call_bit
;
13993 else if (strcasecmp (type
, "ret") == 0)
13994 align_branch
|= align_branch_ret_bit
;
13995 else if (strcasecmp (type
, "indirect") == 0)
13996 align_branch
|= align_branch_indirect_bit
;
13998 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14001 while (next
!= NULL
);
14005 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14006 align_branch_power
= 5;
14007 align_branch_prefix_size
= 5;
14008 align_branch
= (align_branch_jcc_bit
14009 | align_branch_fused_bit
14010 | align_branch_jmp_bit
);
14013 case OPTION_MAMD64
:
14017 case OPTION_MINTEL64
:
14025 /* Turn off -Os. */
14026 optimize_for_space
= 0;
14028 else if (*arg
== 's')
14030 optimize_for_space
= 1;
14031 /* Turn on all encoding optimizations. */
14032 optimize
= INT_MAX
;
14036 optimize
= atoi (arg
);
14037 /* Turn off -Os. */
14038 optimize_for_space
= 0;
14048 #define MESSAGE_TEMPLATE \
14052 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14053 int *left_p
, const char *name
, int len
)
14055 int size
= sizeof (MESSAGE_TEMPLATE
);
14056 int left
= *left_p
;
14058 /* Reserve 2 spaces for ", " or ",\0" */
14061 /* Check if there is any room. */
14069 p
= mempcpy (p
, name
, len
);
14073 /* Output the current message now and start a new one. */
14076 fprintf (stream
, "%s\n", message
);
14078 left
= size
- (start
- message
) - len
- 2;
14080 gas_assert (left
>= 0);
14082 p
= mempcpy (p
, name
, len
);
14090 show_arch (FILE *stream
, int ext
, int check
)
14092 static char message
[] = MESSAGE_TEMPLATE
;
14093 char *start
= message
+ 27;
14095 int size
= sizeof (MESSAGE_TEMPLATE
);
14102 left
= size
- (start
- message
);
14106 p
= output_message (stream
, p
, message
, start
, &left
,
14107 STRING_COMMA_LEN ("default"));
14108 p
= output_message (stream
, p
, message
, start
, &left
,
14109 STRING_COMMA_LEN ("push"));
14110 p
= output_message (stream
, p
, message
, start
, &left
,
14111 STRING_COMMA_LEN ("pop"));
14114 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14116 /* Should it be skipped? */
14117 if (cpu_arch
[j
].skip
)
14120 name
= cpu_arch
[j
].name
;
14121 len
= cpu_arch
[j
].len
;
14122 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
14124 /* It is an extension. Skip if we aren't asked to show it. */
14125 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14130 /* It is an processor. Skip if we show only extension. */
14133 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14135 /* It is an impossible processor - skip. */
14139 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
14142 /* Display disabled extensions. */
14144 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14148 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14149 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14151 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
14152 p
= output_message (stream
, p
, message
, start
, &left
, str
,
14158 fprintf (stream
, "%s\n", message
);
14162 md_show_usage (FILE *stream
)
14164 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14165 fprintf (stream
, _("\
14166 -Qy, -Qn ignored\n\
14167 -V print assembler version number\n\
14170 fprintf (stream
, _("\
14171 -n do not optimize code alignment\n\
14172 -O{012s} attempt some code optimizations\n\
14173 -q quieten some warnings\n"));
14174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14175 fprintf (stream
, _("\
14179 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14180 fprintf (stream
, _("\
14181 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
14182 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
14183 fprintf (stream
, _("\
14184 --32/--64 generate 32bit/64bit object\n"));
14187 #ifdef SVR4_COMMENT_CHARS
14188 fprintf (stream
, _("\
14189 --divide do not treat `/' as a comment character\n"));
14191 fprintf (stream
, _("\
14192 --divide ignored\n"));
14194 fprintf (stream
, _("\
14195 -march=CPU[,+EXTENSION...]\n\
14196 generate code for CPU and EXTENSION, CPU is one of:\n"));
14197 show_arch (stream
, 0, 1);
14198 fprintf (stream
, _("\
14199 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
14200 show_arch (stream
, 1, 0);
14201 fprintf (stream
, _("\
14202 -mtune=CPU optimize for CPU, CPU is one of:\n"));
14203 show_arch (stream
, 0, 0);
14204 fprintf (stream
, _("\
14205 -msse2avx encode SSE instructions with VEX prefix\n"));
14206 fprintf (stream
, _("\
14207 -muse-unaligned-vector-move\n\
14208 encode aligned vector move as unaligned vector move\n"));
14209 fprintf (stream
, _("\
14210 -msse-check=[none|error|warning] (default: warning)\n\
14211 check SSE instructions\n"));
14212 fprintf (stream
, _("\
14213 -moperand-check=[none|error|warning] (default: warning)\n\
14214 check operand combinations for validity\n"));
14215 fprintf (stream
, _("\
14216 -mavxscalar=[128|256] (default: 128)\n\
14217 encode scalar AVX instructions with specific vector\n\
14219 fprintf (stream
, _("\
14220 -mvexwig=[0|1] (default: 0)\n\
14221 encode VEX instructions with specific VEX.W value\n\
14222 for VEX.W bit ignored instructions\n"));
14223 fprintf (stream
, _("\
14224 -mevexlig=[128|256|512] (default: 128)\n\
14225 encode scalar EVEX instructions with specific vector\n\
14227 fprintf (stream
, _("\
14228 -mevexwig=[0|1] (default: 0)\n\
14229 encode EVEX instructions with specific EVEX.W value\n\
14230 for EVEX.W bit ignored instructions\n"));
14231 fprintf (stream
, _("\
14232 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
14233 encode EVEX instructions with specific EVEX.RC value\n\
14234 for SAE-only ignored instructions\n"));
14235 fprintf (stream
, _("\
14236 -mmnemonic=[att|intel] "));
14237 if (SYSV386_COMPAT
)
14238 fprintf (stream
, _("(default: att)\n"));
14240 fprintf (stream
, _("(default: intel)\n"));
14241 fprintf (stream
, _("\
14242 use AT&T/Intel mnemonic\n"));
14243 fprintf (stream
, _("\
14244 -msyntax=[att|intel] (default: att)\n\
14245 use AT&T/Intel syntax\n"));
14246 fprintf (stream
, _("\
14247 -mindex-reg support pseudo index registers\n"));
14248 fprintf (stream
, _("\
14249 -mnaked-reg don't require `%%' prefix for registers\n"));
14250 fprintf (stream
, _("\
14251 -madd-bnd-prefix add BND prefix for all valid branches\n"));
14252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14253 fprintf (stream
, _("\
14254 -mshared disable branch optimization for shared code\n"));
14255 fprintf (stream
, _("\
14256 -mx86-used-note=[no|yes] "));
14257 if (DEFAULT_X86_USED_NOTE
)
14258 fprintf (stream
, _("(default: yes)\n"));
14260 fprintf (stream
, _("(default: no)\n"));
14261 fprintf (stream
, _("\
14262 generate x86 used ISA and feature properties\n"));
14264 #if defined (TE_PE) || defined (TE_PEP)
14265 fprintf (stream
, _("\
14266 -mbig-obj generate big object files\n"));
14268 fprintf (stream
, _("\
14269 -momit-lock-prefix=[no|yes] (default: no)\n\
14270 strip all lock prefixes\n"));
14271 fprintf (stream
, _("\
14272 -mfence-as-lock-add=[no|yes] (default: no)\n\
14273 encode lfence, mfence and sfence as\n\
14274 lock addl $0x0, (%%{re}sp)\n"));
14275 fprintf (stream
, _("\
14276 -mrelax-relocations=[no|yes] "));
14277 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
14278 fprintf (stream
, _("(default: yes)\n"));
14280 fprintf (stream
, _("(default: no)\n"));
14281 fprintf (stream
, _("\
14282 generate relax relocations\n"));
14283 fprintf (stream
, _("\
14284 -malign-branch-boundary=NUM (default: 0)\n\
14285 align branches within NUM byte boundary\n"));
14286 fprintf (stream
, _("\
14287 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
14288 TYPE is combination of jcc, fused, jmp, call, ret,\n\
14290 specify types of branches to align\n"));
14291 fprintf (stream
, _("\
14292 -malign-branch-prefix-size=NUM (default: 5)\n\
14293 align branches with NUM prefixes per instruction\n"));
14294 fprintf (stream
, _("\
14295 -mbranches-within-32B-boundaries\n\
14296 align branches within 32 byte boundary\n"));
14297 fprintf (stream
, _("\
14298 -mlfence-after-load=[no|yes] (default: no)\n\
14299 generate lfence after load\n"));
14300 fprintf (stream
, _("\
14301 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
14302 generate lfence before indirect near branch\n"));
14303 fprintf (stream
, _("\
14304 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
14305 generate lfence before ret\n"));
14306 fprintf (stream
, _("\
14307 -mamd64 accept only AMD64 ISA [default]\n"));
14308 fprintf (stream
, _("\
14309 -mintel64 accept only Intel64 ISA\n"));
14312 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
14313 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14314 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14316 /* Pick the target format to use. */
14319 i386_target_format (void)
14321 if (startswith (default_arch
, "x86_64"))
14323 update_code_flag (CODE_64BIT
, 1);
14324 if (default_arch
[6] == '\0')
14325 x86_elf_abi
= X86_64_ABI
;
14327 x86_elf_abi
= X86_64_X32_ABI
;
14329 else if (!strcmp (default_arch
, "i386"))
14330 update_code_flag (CODE_32BIT
, 1);
14331 else if (!strcmp (default_arch
, "iamcu"))
14333 update_code_flag (CODE_32BIT
, 1);
14334 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
14336 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
14337 cpu_arch_name
= "iamcu";
14338 free (cpu_sub_arch_name
);
14339 cpu_sub_arch_name
= NULL
;
14340 cpu_arch_flags
= iamcu_flags
;
14341 cpu_arch_isa
= PROCESSOR_IAMCU
;
14342 cpu_arch_isa_flags
= iamcu_flags
;
14343 if (!cpu_arch_tune_set
)
14345 cpu_arch_tune
= cpu_arch_isa
;
14346 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14349 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
14350 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
14354 as_fatal (_("unknown architecture"));
14356 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
14357 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14358 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
14359 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14361 switch (OUTPUT_FLAVOR
)
14363 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
14364 case bfd_target_aout_flavour
:
14365 return AOUT_TARGET_FORMAT
;
14367 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
14368 # if defined (TE_PE) || defined (TE_PEP)
14369 case bfd_target_coff_flavour
:
14370 if (flag_code
== CODE_64BIT
)
14373 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
14375 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
14376 # elif defined (TE_GO32)
14377 case bfd_target_coff_flavour
:
14378 return "coff-go32";
14380 case bfd_target_coff_flavour
:
14381 return "coff-i386";
14384 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14385 case bfd_target_elf_flavour
:
14387 const char *format
;
14389 switch (x86_elf_abi
)
14392 format
= ELF_TARGET_FORMAT
;
14394 tls_get_addr
= "___tls_get_addr";
14398 use_rela_relocations
= 1;
14401 tls_get_addr
= "__tls_get_addr";
14403 format
= ELF_TARGET_FORMAT64
;
14405 case X86_64_X32_ABI
:
14406 use_rela_relocations
= 1;
14409 tls_get_addr
= "__tls_get_addr";
14411 disallow_64bit_reloc
= 1;
14412 format
= ELF_TARGET_FORMAT32
;
14415 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
14417 if (x86_elf_abi
!= I386_ABI
)
14418 as_fatal (_("Intel MCU is 32bit only"));
14419 return ELF_TARGET_IAMCU_FORMAT
;
14425 #if defined (OBJ_MACH_O)
14426 case bfd_target_mach_o_flavour
:
14427 if (flag_code
== CODE_64BIT
)
14429 use_rela_relocations
= 1;
14431 return "mach-o-x86-64";
14434 return "mach-o-i386";
14442 #endif /* OBJ_MAYBE_ more than one */
14445 md_undefined_symbol (char *name
)
14447 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14448 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14449 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
14450 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14454 if (symbol_find (name
))
14455 as_bad (_("GOT already in symbol table"));
14456 GOT_symbol
= symbol_new (name
, undefined_section
,
14457 &zero_address_frag
, 0);
14464 /* Round up a section size to the appropriate boundary. */
14467 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14469 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14470 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14472 /* For a.out, force the section size to be aligned. If we don't do
14473 this, BFD will align it for us, but it will not write out the
14474 final bytes of the section. This may be a bug in BFD, but it is
14475 easier to fix it here since that is how the other a.out targets
14479 align
= bfd_section_alignment (segment
);
14480 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14487 /* On the i386, PC-relative offsets are relative to the start of the
14488 next instruction. That is, the address of the offset, plus its
14489 size, since the offset is always the last part of the insn. */
14492 md_pcrel_from (fixS
*fixP
)
14494 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14500 s_bss (int ignore ATTRIBUTE_UNUSED
)
14504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14506 obj_elf_section_change_hook ();
14508 temp
= get_absolute_expression ();
14509 subseg_set (bss_section
, (subsegT
) temp
);
14510 demand_empty_rest_of_line ();
14515 /* Remember constant directive. */
14518 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14520 if (last_insn
.kind
!= last_insn_directive
14521 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14523 last_insn
.seg
= now_seg
;
14524 last_insn
.kind
= last_insn_directive
;
14525 last_insn
.name
= "constant directive";
14526 last_insn
.file
= as_where (&last_insn
.line
);
14527 if (lfence_before_ret
!= lfence_before_ret_none
)
14529 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14530 as_warn (_("constant directive skips -mlfence-before-ret "
14531 "and -mlfence-before-indirect-branch"));
14533 as_warn (_("constant directive skips -mlfence-before-ret"));
14535 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14536 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14541 i386_validate_fix (fixS
*fixp
)
14543 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
14545 reloc_howto_type
*howto
;
14547 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
14548 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14549 _("invalid %s relocation against register"),
14550 howto
? howto
->name
: "<unknown>");
14554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14555 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14556 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14557 return IS_ELF
&& fixp
->fx_addsy
14558 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14559 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14562 if (fixp
->fx_subsy
)
14564 if (fixp
->fx_subsy
== GOT_symbol
)
14566 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14570 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14571 if (fixp
->fx_tcbit2
)
14572 fixp
->fx_r_type
= (fixp
->fx_tcbit
14573 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14574 : BFD_RELOC_X86_64_GOTPCRELX
);
14577 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14582 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14584 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14586 fixp
->fx_subsy
= 0;
14589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14592 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14593 to section. Since PLT32 relocation must be against symbols,
14594 turn such PLT32 relocation into PC32 relocation. */
14596 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14597 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14598 && symbol_section_p (fixp
->fx_addsy
))
14599 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14602 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14603 && fixp
->fx_tcbit2
)
14604 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14613 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14616 bfd_reloc_code_real_type code
;
14618 switch (fixp
->fx_r_type
)
14620 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14623 case BFD_RELOC_SIZE32
:
14624 case BFD_RELOC_SIZE64
:
14626 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14627 && (!fixp
->fx_subsy
14628 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14629 sym
= fixp
->fx_addsy
;
14630 else if (fixp
->fx_subsy
14631 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14632 && (!fixp
->fx_addsy
14633 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14634 sym
= fixp
->fx_subsy
;
14637 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14639 /* Resolve size relocation against local symbol to size of
14640 the symbol plus addend. */
14641 valueT value
= S_GET_SIZE (sym
);
14643 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14644 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14645 if (sym
== fixp
->fx_subsy
)
14648 if (fixp
->fx_addsy
)
14649 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14651 else if (fixp
->fx_subsy
)
14652 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14653 value
+= fixp
->fx_offset
;
14654 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14656 && !fits_in_unsigned_long (value
))
14657 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14658 _("symbol size computation overflow"));
14659 fixp
->fx_addsy
= NULL
;
14660 fixp
->fx_subsy
= NULL
;
14661 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14664 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14666 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14667 "unsupported expression involving @size");
14671 /* Fall through. */
14673 case BFD_RELOC_X86_64_PLT32
:
14674 case BFD_RELOC_X86_64_GOT32
:
14675 case BFD_RELOC_X86_64_GOTPCREL
:
14676 case BFD_RELOC_X86_64_GOTPCRELX
:
14677 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14678 case BFD_RELOC_386_PLT32
:
14679 case BFD_RELOC_386_GOT32
:
14680 case BFD_RELOC_386_GOT32X
:
14681 case BFD_RELOC_386_GOTOFF
:
14682 case BFD_RELOC_386_GOTPC
:
14683 case BFD_RELOC_386_TLS_GD
:
14684 case BFD_RELOC_386_TLS_LDM
:
14685 case BFD_RELOC_386_TLS_LDO_32
:
14686 case BFD_RELOC_386_TLS_IE_32
:
14687 case BFD_RELOC_386_TLS_IE
:
14688 case BFD_RELOC_386_TLS_GOTIE
:
14689 case BFD_RELOC_386_TLS_LE_32
:
14690 case BFD_RELOC_386_TLS_LE
:
14691 case BFD_RELOC_386_TLS_GOTDESC
:
14692 case BFD_RELOC_386_TLS_DESC_CALL
:
14693 case BFD_RELOC_X86_64_TLSGD
:
14694 case BFD_RELOC_X86_64_TLSLD
:
14695 case BFD_RELOC_X86_64_DTPOFF32
:
14696 case BFD_RELOC_X86_64_DTPOFF64
:
14697 case BFD_RELOC_X86_64_GOTTPOFF
:
14698 case BFD_RELOC_X86_64_TPOFF32
:
14699 case BFD_RELOC_X86_64_TPOFF64
:
14700 case BFD_RELOC_X86_64_GOTOFF64
:
14701 case BFD_RELOC_X86_64_GOTPC32
:
14702 case BFD_RELOC_X86_64_GOT64
:
14703 case BFD_RELOC_X86_64_GOTPCREL64
:
14704 case BFD_RELOC_X86_64_GOTPC64
:
14705 case BFD_RELOC_X86_64_GOTPLT64
:
14706 case BFD_RELOC_X86_64_PLTOFF64
:
14707 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14708 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14709 case BFD_RELOC_RVA
:
14710 case BFD_RELOC_VTABLE_ENTRY
:
14711 case BFD_RELOC_VTABLE_INHERIT
:
14713 case BFD_RELOC_32_SECREL
:
14714 case BFD_RELOC_16_SECIDX
:
14716 code
= fixp
->fx_r_type
;
14718 case BFD_RELOC_X86_64_32S
:
14719 if (!fixp
->fx_pcrel
)
14721 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14722 code
= fixp
->fx_r_type
;
14725 /* Fall through. */
14727 if (fixp
->fx_pcrel
)
14729 switch (fixp
->fx_size
)
14732 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14733 _("can not do %d byte pc-relative relocation"),
14735 code
= BFD_RELOC_32_PCREL
;
14737 case 1: code
= BFD_RELOC_8_PCREL
; break;
14738 case 2: code
= BFD_RELOC_16_PCREL
; break;
14739 case 4: code
= BFD_RELOC_32_PCREL
; break;
14741 case 8: code
= BFD_RELOC_64_PCREL
; break;
14747 switch (fixp
->fx_size
)
14750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14751 _("can not do %d byte relocation"),
14753 code
= BFD_RELOC_32
;
14755 case 1: code
= BFD_RELOC_8
; break;
14756 case 2: code
= BFD_RELOC_16
; break;
14757 case 4: code
= BFD_RELOC_32
; break;
14759 case 8: code
= BFD_RELOC_64
; break;
14766 if ((code
== BFD_RELOC_32
14767 || code
== BFD_RELOC_32_PCREL
14768 || code
== BFD_RELOC_X86_64_32S
)
14770 && fixp
->fx_addsy
== GOT_symbol
)
14773 code
= BFD_RELOC_386_GOTPC
;
14775 code
= BFD_RELOC_X86_64_GOTPC32
;
14777 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14779 && fixp
->fx_addsy
== GOT_symbol
)
14781 code
= BFD_RELOC_X86_64_GOTPC64
;
14784 rel
= XNEW (arelent
);
14785 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14786 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14788 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14790 if (!use_rela_relocations
)
14792 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14793 vtable entry to be used in the relocation's section offset. */
14794 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14795 rel
->address
= fixp
->fx_offset
;
14796 #if defined (OBJ_COFF) && defined (TE_PE)
14797 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14798 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14803 /* Use the rela in 64bit mode. */
14806 if (disallow_64bit_reloc
)
14809 case BFD_RELOC_X86_64_DTPOFF64
:
14810 case BFD_RELOC_X86_64_TPOFF64
:
14811 case BFD_RELOC_64_PCREL
:
14812 case BFD_RELOC_X86_64_GOTOFF64
:
14813 case BFD_RELOC_X86_64_GOT64
:
14814 case BFD_RELOC_X86_64_GOTPCREL64
:
14815 case BFD_RELOC_X86_64_GOTPC64
:
14816 case BFD_RELOC_X86_64_GOTPLT64
:
14817 case BFD_RELOC_X86_64_PLTOFF64
:
14818 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14819 _("cannot represent relocation type %s in x32 mode"),
14820 bfd_get_reloc_code_name (code
));
14826 if (!fixp
->fx_pcrel
)
14827 rel
->addend
= fixp
->fx_offset
;
14831 case BFD_RELOC_X86_64_PLT32
:
14832 case BFD_RELOC_X86_64_GOT32
:
14833 case BFD_RELOC_X86_64_GOTPCREL
:
14834 case BFD_RELOC_X86_64_GOTPCRELX
:
14835 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14836 case BFD_RELOC_X86_64_TLSGD
:
14837 case BFD_RELOC_X86_64_TLSLD
:
14838 case BFD_RELOC_X86_64_GOTTPOFF
:
14839 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14840 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14841 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14844 rel
->addend
= (section
->vma
14846 + fixp
->fx_addnumber
14847 + md_pcrel_from (fixp
));
14852 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14853 if (rel
->howto
== NULL
)
14855 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14856 _("cannot represent relocation type %s"),
14857 bfd_get_reloc_code_name (code
));
14858 /* Set howto to a garbage value so that we can keep going. */
14859 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14860 gas_assert (rel
->howto
!= NULL
);
14866 #include "tc-i386-intel.c"
14869 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14871 int saved_naked_reg
;
14872 char saved_register_dot
;
14874 saved_naked_reg
= allow_naked_reg
;
14875 allow_naked_reg
= 1;
14876 saved_register_dot
= register_chars
['.'];
14877 register_chars
['.'] = '.';
14878 allow_pseudo_reg
= 1;
14879 expression_and_evaluate (exp
);
14880 allow_pseudo_reg
= 0;
14881 register_chars
['.'] = saved_register_dot
;
14882 allow_naked_reg
= saved_naked_reg
;
14884 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14886 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14888 exp
->X_op
= O_constant
;
14889 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14890 .dw2_regnum
[flag_code
>> 1];
14893 exp
->X_op
= O_illegal
;
14898 tc_x86_frame_initial_instructions (void)
14900 static unsigned int sp_regno
[2];
14902 if (!sp_regno
[flag_code
>> 1])
14904 char *saved_input
= input_line_pointer
;
14905 char sp
[][4] = {"esp", "rsp"};
14908 input_line_pointer
= sp
[flag_code
>> 1];
14909 tc_x86_parse_to_dw2regnum (&exp
);
14910 gas_assert (exp
.X_op
== O_constant
);
14911 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14912 input_line_pointer
= saved_input
;
14915 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14916 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14920 x86_dwarf2_addr_size (void)
14922 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14923 if (x86_elf_abi
== X86_64_X32_ABI
)
14926 return bfd_arch_bits_per_address (stdoutput
) / 8;
14930 i386_elf_section_type (const char *str
, size_t len
)
14932 if (flag_code
== CODE_64BIT
14933 && len
== sizeof ("unwind") - 1
14934 && startswith (str
, "unwind"))
14935 return SHT_X86_64_UNWIND
;
14942 i386_solaris_fix_up_eh_frame (segT sec
)
14944 if (flag_code
== CODE_64BIT
)
14945 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14951 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14955 exp
.X_op
= O_secrel
;
14956 exp
.X_add_symbol
= symbol
;
14957 exp
.X_add_number
= 0;
14958 emit_expr (&exp
, size
);
14962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14963 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14966 x86_64_section_letter (int letter
, const char **ptr_msg
)
14968 if (flag_code
== CODE_64BIT
)
14971 return SHF_X86_64_LARGE
;
14973 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14976 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14981 x86_64_section_word (char *str
, size_t len
)
14983 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14984 return SHF_X86_64_LARGE
;
14990 handle_large_common (int small ATTRIBUTE_UNUSED
)
14992 if (flag_code
!= CODE_64BIT
)
14994 s_comm_internal (0, elf_common_parse
);
14995 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14999 static segT lbss_section
;
15000 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15001 asection
*saved_bss_section
= bss_section
;
15003 if (lbss_section
== NULL
)
15005 flagword applicable
;
15006 segT seg
= now_seg
;
15007 subsegT subseg
= now_subseg
;
15009 /* The .lbss section is for local .largecomm symbols. */
15010 lbss_section
= subseg_new (".lbss", 0);
15011 applicable
= bfd_applicable_section_flags (stdoutput
);
15012 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15013 seg_info (lbss_section
)->bss
= 1;
15015 subseg_set (seg
, subseg
);
15018 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15019 bss_section
= lbss_section
;
15021 s_comm_internal (0, elf_common_parse
);
15023 elf_com_section_ptr
= saved_com_section_ptr
;
15024 bss_section
= saved_bss_section
;
15027 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */